[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/pps: Add PPS power domain
== Series Details == Series: drm/i915/pps: Add PPS power domain URL : https://patchwork.freedesktop.org/series/85470/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9544 -> Patchwork_19256 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19256 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19256, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19256: ### CI changes ### Possible regressions * boot: - fi-bsw-n3050: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/fi-bsw-n3050/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-bsw-n3050/boot.html ### IGT changes ### Possible regressions * igt@runner@aborted: - fi-ilk-650: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-ilk-650/igt@run...@aborted.html - fi-bsw-kefka: NOTRUN -> [FAIL][4] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-bsw-kefka/igt@run...@aborted.html - fi-tgl-y: NOTRUN -> [FAIL][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-tgl-y/igt@run...@aborted.html - fi-elk-e7500: NOTRUN -> [FAIL][6] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-elk-e7500/igt@run...@aborted.html - fi-tgl-u2: NOTRUN -> [FAIL][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-tgl-u2/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_19256 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s0: - fi-bsw-nick:[PASS][8] -> [INCOMPLETE][9] ([i915#1250] / [i915#1436] / [i915#2539]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/fi-bsw-nick/igt@gem_exec_susp...@basic-s0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-bsw-nick/igt@gem_exec_susp...@basic-s0.html * igt@runner@aborted: - fi-kbl-x1275: NOTRUN -> [FAIL][10] ([i915#1569] / [i915#192] / [i915#193] / [i915#194] / [i915#2295]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-kbl-x1275/igt@run...@aborted.html - fi-skl-6600u: NOTRUN -> [FAIL][11] ([i915#2295]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-skl-6600u/igt@run...@aborted.html - fi-cfl-8109u: NOTRUN -> [FAIL][12] ([i915#2295] / [i915#483] / [k.org#202107] / [k.org#202109]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-cfl-8109u/igt@run...@aborted.html - fi-bsw-nick:NOTRUN -> [FAIL][13] ([i915#1602] / [i915#483]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-bsw-nick/igt@run...@aborted.html - fi-kbl-r: NOTRUN -> [FAIL][14] ([i915#1569] / [i915#192] / [i915#193] / [i915#194] / [i915#2295]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-kbl-r/igt@run...@aborted.html - fi-bdw-5557u: NOTRUN -> [FAIL][15] ([i915#483]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-bdw-5557u/igt@run...@aborted.html - fi-kbl-soraka: NOTRUN -> [FAIL][16] ([i915#1569] / [i915#192] / [i915#193] / [i915#194] / [i915#2295]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-kbl-soraka/igt@run...@aborted.html - fi-kbl-7500u: NOTRUN -> [FAIL][17] ([i915#1569] / [i915#192] / [i915#193] / [i915#194] / [i915#2295] / [i915#483]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-kbl-7500u/igt@run...@aborted.html - fi-snb-2600:NOTRUN -> [FAIL][18] ([i915#698]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-snb-2600/igt@run...@aborted.html - fi-cml-u2: NOTRUN -> [FAIL][19] ([i915#2295]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-cml-u2/igt@run...@aborted.html - fi-bxt-dsi: NOTRUN -> [FAIL][20] ([i915#2295]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-bxt-dsi/igt@run...@aborted.html - fi-byt-j1900: NOTRUN -> [FAIL][21] ([i915#2505] / [i915#483]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-byt-j1900/igt@run...@aborted.html - fi-icl-y: NOTRUN -> [FAIL][22] ([i915#1569] / [i915#2295] / [i915#2724] / [i915#483]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19256/fi-icl-y/igt@run...@aborted.html Warnings * igt@runner@aborted: -
Re: [Intel-gfx] Missing DPPLL case on i7-1165G7
On Tue, Dec 29, 2020 at 04:41:31PM +0200, Imre Deak wrote: > Hi, > > On Mon, Dec 21, 2020 at 04:07:58AM +, Matthew Wilcox wrote: > > > > At boot, > > > > [2.787995] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon > > [2.788001] i915 :00:02.0: [drm] *ERROR* LSPCON init failed on port E > > [2.790752] [ cut here ] > > [2.790753] Missing case (clock == 539440) > > [2.790790] WARNING: CPU: 0 PID: 159 at > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2967 > > icl_get_dplls+0x53a/0xa50 [i915] > > the above warn looks to be due to a missing workaround fixed by > > commit 0e2497e334de42dbaaee8e325241b5b5b34ede7e > Author: Imre Deak > Date: Sat Oct 3 03:18:46 2020 +0300 > > drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock > > in drm-tip. Could you give it a try? I tried -rc2, which contains that commit, and the problem is gone. Thank you! There is a different problem, which is that the brightness buttons (on F2 and F3 on this laptop) do not actually increase/decrease the brightness. GNOME pops up a graphic that illustrates it is changing the brightness, but nothing actually changes. xbacklight says "No outputs have backlight property" and using xrandr --output XWAYLAND0 --brightness 0.0001 doesn't change anything (for various different values, not just 0.0001). Using xrandr --prop --verbose shows the reported value of "Brightness" changing, but nothing has changed on the screen. I found /sys/devices/pci:00/:00:02.0/drm/card0/card0-eDP-1/intel_backlight and tried setting 'brightness' in there to a few different values (100, 2000, 19200, 7000) and also nothing changed. Any thoughts? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC] drm/i915/pps: Add PPS power domain
It abstracts getting the AUX power domain in pps_lock under
PPS power domain. This makes sure that the platforms which really
requires AUX power in order to access PPS registers will get the
reference to necessary power wells.
PPS power domain requires only to track the AUX_A associated
power wells as the platforms need AUX power in order to access PPS
registers supports eDP only on PORT_A.
Cc: Imre Deak
Cc: Jani Nikula
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++
drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c| 3 +--
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index d52374f01316..1dc4ca9e5d1a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -107,6 +107,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "VGA";
case POWER_DOMAIN_AUDIO:
return "AUDIO";
+ case POWER_DOMAIN_PPS:
+ return "PPS";
case POWER_DOMAIN_AUX_A:
return "AUX_A";
case POWER_DOMAIN_AUX_B:
@@ -2651,11 +2653,13 @@ intel_display_power_put_mask_in_set(struct
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_PPS) | \
BIT_ULL(POWER_DOMAIN_GMBUS) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) |\
BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_PPS) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define BXT_DPIO_CMN_BC_POWER_DOMAINS (\
BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |\
@@ -2688,6 +2692,7 @@ intel_display_power_put_mask_in_set(struct
drm_i915_private *i915,
#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) |\
BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_PPS) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |\
@@ -2700,6 +2705,7 @@ intel_display_power_put_mask_in_set(struct
drm_i915_private *i915,
#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_AUX_IO_A) |\
+ BIT_ULL(POWER_DOMAIN_PPS) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
@@ -2712,6 +2718,7 @@ intel_display_power_put_mask_in_set(struct
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_PPS) | \
BIT_ULL(POWER_DOMAIN_GMBUS) | \
BIT_ULL(POWER_DOMAIN_INIT))
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index bc30c479be53..7642be3c8e2e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -55,6 +55,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_OTHER,
POWER_DOMAIN_VGA,
POWER_DOMAIN_AUDIO,
+ POWER_DOMAIN_PPS,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 8a00e609085f..0e6e5e2d873e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -895,8 +895,7 @@ pps_lock(struct intel_dp *intel_dp)
* See intel_power_sequencer_reset() why we need
* a power domain reference here.
*/
- wakeref = intel_display_power_get(dev_priv,
-
intel_aux_power_domain(dp_to_dig_port(intel_dp)));
+ wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PPS);
mutex_lock(_priv->pps_mutex);
--
2.26.2
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Re: [Intel-gfx] [PATCH v2] drm/i915/debugfs : PM_REQ and PM_RES registers
> -Original Message-
> From: S, Saichandana
> Sent: Monday, January 4, 2021 4:01 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: S, Saichandana ; Nikula, Jani
> ; Gupta, Anshuman
> Subject: [PATCH v2] drm/i915/debugfs : PM_REQ and PM_RES registers
>
> From: Saichandana
>
> PM_REQ register provides the value of the last PM request from PCU to
> Display Engine.PM_RES register provides the value of the last PM response
> from Display Engine to PCU.This debugfs will be used by
> DC9 IGT test to know about "DC9 Ready" status.
>
> B.Spec : 49501, 49502
Please mention here the review comment u had fixed.
So it will be easy for review.
V2:
Added a functional print to debugs. [Keep name of Reviewer]
>
> Signed-off-by: Saichandana
> ---
> .../drm/i915/display/intel_display_debugfs.c | 30
> +++
> drivers/gpu/drm/i915/i915_reg.h | 8 +
> 2 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index cd7e5519ee7d..551fb1a90bb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -559,6 +559,36 @@ static int i915_dmc_info(struct seq_file *m, void
> *unused)
> return 0;
> }
>
> +static int i915_pm_req_res_info(struct seq_file *m, void *unused) {
> + struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_csr *csr = _priv->csr;
> + const char *status;
> +
> + if (!HAS_CSR(dev_priv))
> + return -ENODEV;
> + if (!csr->dmc_payload)
> + return 0;
> + seq_printf(m, "PM debug request 0 (0x45284): 0x%08x\n",
> +intel_de_read(dev_priv, PM_REQ_DBG_0));
> + seq_printf(m, "PM debug request 1 (0x45288): 0x%08x\n",
> +intel_de_read(dev_priv, PM_REQ_DBG_1));
> + seq_printf(m, "PM debug response 0 (0x4528C): 0x%08x\n",
> +intel_de_read(dev_priv, PM_RSP_DBG_0));
> + seq_printf(m, "PM debug response 1 (0x45290): 0x%08x\n",
> +intel_de_read(dev_priv, PM_RSP_DBG_1));
> + status = (intel_de_read(dev_priv, PM_RSP_DBG_1) &
> MASK_DC9_BIT) ?
> +"yes" : "no";
You don't need to read the value of register again , please store in a variable
And use that value.
Thanks,
Anshuman Gupta.
> +
> + seq_printf(m, "Time to Next Fill = 0x%0x\n",
> +(intel_de_read(dev_priv, PM_RSP_DBG_0) &
> ~MASK_RSP_0));
> + seq_printf(m, "Time to Next VBI = 0x%0x\n",
> +((intel_de_read(dev_priv, PM_RSP_DBG_0) &
> MASK_RSP_0)) >> 16);
> + seq_printf(m, "Selective Exit Latency = 0x%0x\n",
> +(intel_de_read(dev_priv, PM_RSP_DBG_1) &
> MASK_RSP_1));
> + seq_printf(m, "DC9 Ready = %s\n", status);
> + return 0;
> +}
> +
> static void intel_seq_print_mode(struct seq_file *m, int tabs,
>const struct drm_display_mode *mode) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 0023c023f472..3e9ed555f928
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -371,6 +371,14 @@ static inline bool
> i915_mmio_reg_valid(i915_reg_t reg)
> #define VLV_G3DCTL _MMIO(0x9024)
> #define VLV_GSCKGCTL _MMIO(0x9028)
>
> +#define PM_REQ_DBG_0 _MMIO(0x45284)
> +#define PM_REQ_DBG_1 _MMIO(0x45288)
> +#define PM_RSP_DBG_0 _MMIO(0x4528C)
> +#define PM_RSP_DBG_1 _MMIO(0x45290)
> +#define MASK_RSP_0 (0x << 16)
> +#define MASK_RSP_1 (7 << 0)
> +#define MASK_DC9_BIT (1 << 17)
> +
> #define GEN6_MBCTL _MMIO(0x0907c)
> #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
> #define GEN6_MBCTL_CTX_FETCH_NEEDED(1 << 3)
> --
> 2.17.1
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Re: [Intel-gfx] [PATCH 5/6] drm/i915/gt: Restore ce->signal flush before releasing virtual engine
Hi Chris,
> Before we mark the virtual engine as no longer inflight, flush any
> ongoing signaling that may be using the ce->signal_link along the
> previous breadcrumbs. On switch to a new physical engine, that link will
> be inserted into the new set of breadcrumbs, causing confusion to an
> ongoing iterator.
>
> This patch undoes a last minute mistake introduced into commit
> bab0557c8dca ("drm/i915/gt: Remove virtual breadcrumb before transfer"),
> whereby instead of unconditionally applying the flush, it was only
> applied if the request itself was going to be reused.
>
> Fixes: bab0557c8dca ("drm/i915/gt: Remove virtual breadcrumb before transfer")
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index a5b442683c18..6414dbb124a7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -592,8 +592,6 @@ resubmit_virtual_request(struct i915_request *rq, struct
> virtual_engine *ve)
>* ce->signal_link.
>*/
> i915_request_cancel_breadcrumb(rq);
> - while (atomic_read(>breadcrumbs->signaler_active))
> - cpu_relax();
> }
As you are at it, you can also remove the braces, with that:
Reviewed-by: Andi Shyti
Thanks,
Andi
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Re: [Intel-gfx] [PATCH 4/6] drm/i915/gt: Check the virtual still matches upon locking
Hi Chris, On Mon, Jan 04, 2021 at 11:51:43AM +, Chris Wilson wrote: > If another sibling is able to claim the virtual request, by the time we > inspect the request under the lock if may no longer match the local > engine. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2877 > Signed-off-by: Chris Wilson Reviewed-by: Andi Shyti Thanks, Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/6] drm/i915/gt: Allow failed resets without assertion
Hi Chris,
On Mon, Jan 04, 2021 at 11:51:42AM +, Chris Wilson wrote:
> If the engine reset fails, we will attempt to resume with the current
> inflight submissions. When that happens, we cannot assert that the
> engine reset cleared the pending submission, so do not.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2878
> Fixes: 16f2941ad307 ("drm/i915/gt: Replace direct submit with direct call to
> tasklet")
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +
> .../drm/i915/gt/intel_execlists_submission.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_reset.c | 3 +
> drivers/gpu/drm/i915/gt/selftest_execlists.c | 75 +++
> 4 files changed, 85 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index c28f4e190fe6..430066e5884c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -561,6 +561,8 @@ struct intel_engine_cs {
> unsigned long stop_timeout_ms;
> unsigned long timeslice_duration_ms;
> } props, defaults;
> +
> + I915_SELFTEST_DECLARE(struct fault_attr reset_timeout);
> };
>
> static inline bool
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 2afbc0a4ca03..f02e3ae10d28 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -3047,9 +3047,13 @@ static void execlists_reset_finish(struct
> intel_engine_cs *engine)
>* After a GPU reset, we may have requests to replay. Do so now while
>* we still have the forcewake to be sure that the GPU is not allowed
>* to sleep before we restart and reload a context.
> + *
> + * If the GPU reset fails, the engine may still be alive with requests
> + * inflight. We expect those to complete, or for the device to be
> + * reset as the next level of recovery, and as a final resort we
> + * will declare the device wedged.
>*/
> GEM_BUG_ON(!reset_in_progress(execlists));
> - GEM_BUG_ON(engine->execlists.pending[0]);
I would have split this in two patches, but it looks good anyway.
Reviewed-by: Andi Shyti
Thanks,
Andi
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/8] drm/i915/gt: Rearrange vlv workarounds
== Series Details == Series: series starting with [1/8] drm/i915/gt: Rearrange vlv workarounds URL : https://patchwork.freedesktop.org/series/85467/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9544 -> Patchwork_19255 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19255 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19255, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19255/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19255: ### IGT changes ### Possible regressions * igt@i915_selftest@live@hangcheck: - fi-snb-2520m: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19255/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html Known issues Here are the changes found in Patchwork_19255 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap_gtt@basic: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/fi-tgl-y/igt@gem_mmap_...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19255/fi-tgl-y/igt@gem_mmap_...@basic.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7500u: [PASS][5] -> [DMESG-FAIL][6] ([i915#165]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19255/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/fi-tgl-y/igt@debugfs_test@read_all_entries.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19255/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@i915_selftest@live@blt: - fi-snb-2600:[DMESG-FAIL][9] ([i915#1409]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/fi-snb-2600/igt@i915_selftest@l...@blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19255/fi-snb-2600/igt@i915_selftest@l...@blt.html [i915#1409]: https://gitlab.freedesktop.org/drm/intel/issues/1409 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (42 -> 37) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9544 -> Patchwork_19255 CI-20190529: 20190529 CI_DRM_9544: b950eb2b863a3e5de7b9647aa037ed50d7dd687c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5942: e14e76a87c44c684ec958b391b030bb549254f88 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19255: 381a338aeab7493a9665f41d2fb1678a62aea154 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 381a338aeab7 drm/i915: Mark per-engine-reset as supported on gen7 bfd290fb0ba5 drm/i915/selftests: Prepare the selftests for engine resets with ring submission eb1b3bbacb90 drm/i915/gt: Pull ring submission resume under its caller forcewake 8ca9b97fa1d9 drm/i915/gt: Lift stop_ring() to reset_prepare d84c80e2b669 drm/i915/gt: Reapply ppgtt enabling after engine resets 2c087f529dc8 drm/i915/gt: Replace open-coded intel_engine_stop_cs() fa52d2e1af5f drm/i915/gt: Rearrange ivb workarounds 1d7a62d3a826 drm/i915/gt: Rearrange vlv workarounds == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19255/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/6] drm/i915: Set rawclk earlier during mmio probe
Hi Chris,
On Mon, Jan 04, 2021 at 11:51:41AM +, Chris Wilson wrote:
> Fixes: f170523a7b8e ("drm/i915/gt: Consolidate the CS timestamp clocks")
> Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
Thanks,
Andi
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Re: [Intel-gfx] [PATCH 1/6] drm/i915/selftests: Set error returns
Hi Chris, On Mon, Jan 04, 2021 at 11:51:40AM +, Chris Wilson wrote: > A few missed PTR_ERR() upon create_gang() errors. > > Signed-off-by: Chris Wilson Reviewed-by: Andi Shyti Thanks, Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/8] drm/i915/gt: Rearrange vlv workarounds
== Series Details == Series: series starting with [1/8] drm/i915/gt: Rearrange vlv workarounds URL : https://patchwork.freedesktop.org/series/85467/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1326:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34: warning: incorrect type in argument 1 (different address spaces) +./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:869:16: warning: trying to copy expression type 31 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/4] drm: Add function to convert rect in 16.16 fixed format to regular format
== Series Details == Series: series starting with [CI,1/4] drm: Add function to convert rect in 16.16 fixed format to regular format URL : https://patchwork.freedesktop.org/series/85458/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9544_full -> Patchwork_19254_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19254_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19254_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19254_full: ### IGT changes ### Possible regressions * igt@gem_exec_nop@basic-sequential: - shard-hsw: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/shard-hsw6/igt@gem_exec_...@basic-sequential.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19254/shard-hsw6/igt@gem_exec_...@basic-sequential.html New tests - New tests have been introduced between CI_DRM_9544_full and Patchwork_19254_full: ### New IGT tests (1) ### * igt@gem_spin_batch@resubmit-new-all: - Statuses : - Exec time: [None] s Known issues Here are the changes found in Patchwork_19254_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-hostile: - shard-hsw: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19254/shard-hsw4/igt@gem_ctx_persiste...@engines-hostile.html * igt@gem_exec_whisper@basic-queues-forked-all: - shard-glk: [PASS][4] -> [DMESG-WARN][5] ([i915#118] / [i915#95]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/shard-glk1/igt@gem_exec_whis...@basic-queues-forked-all.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19254/shard-glk7/igt@gem_exec_whis...@basic-queues-forked-all.html * igt@gem_userptr_blits@mmap-offset-invalidate-active@wb: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271]) +50 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19254/shard-snb6/igt@gem_userptr_blits@mmap-offset-invalidate-act...@wb.html * igt@gem_userptr_blits@vma-merge: - shard-hsw: NOTRUN -> [FAIL][7] ([i915#2724]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19254/shard-hsw6/igt@gem_userptr_bl...@vma-merge.html * igt@i915_selftest@live@hangcheck: - shard-iclb: [PASS][8] -> [INCOMPLETE][9] ([i915#926]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/shard-iclb7/igt@i915_selftest@l...@hangcheck.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19254/shard-iclb6/igt@i915_selftest@l...@hangcheck.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2574]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/shard-tglb5/igt@kms_async_fl...@test-time-stamp.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19254/shard-tglb8/igt@kms_async_fl...@test-time-stamp.html * igt@kms_chamelium@hdmi-hpd-with-enabled-mode: - shard-kbl: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19254/shard-kbl7/igt@kms_chamel...@hdmi-hpd-with-enabled-mode.html * igt@kms_color@pipe-b-ctm-0-25: - shard-tglb: NOTRUN -> [FAIL][13] ([i915#1149] / [i915#315]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19254/shard-tglb6/igt@kms_co...@pipe-b-ctm-0-25.html * igt@kms_color_chamelium@pipe-b-ctm-green-to-red: - shard-hsw: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +9 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19254/shard-hsw4/igt@kms_color_chamel...@pipe-b-ctm-green-to-red.html * igt@kms_color_chamelium@pipe-d-gamma: - shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19254/shard-snb6/igt@kms_color_chamel...@pipe-d-gamma.html * igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen: - shard-skl: [PASS][16] -> [FAIL][17] ([i915#54]) +8 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/shard-skl4/igt@kms_cursor_...@pipe-a-cursor-256x85-offscreen.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19254/shard-skl5/igt@kms_cursor_...@pipe-a-cursor-256x85-offscreen.html * igt@kms_cursor_crc@pipe-c-cursor-64x21-random: - shard-skl: NOTRUN -> [FAIL][18] ([i915#54]) +1 similar issue [18]:
[Intel-gfx] [PATCH 5/8] drm/i915/gt: Lift stop_ring() to reset_prepare
Push the sleeping stop_ring() out of the reset resume function to reset
prepare; we are not allowed to sleep in the former.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 97 +++
1 file changed, 36 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index d794e13610b2..7c31126a1b6d 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -156,21 +156,6 @@ static void ring_setup_status_page(struct intel_engine_cs
*engine)
flush_cs_tlb(engine);
}
-static bool stop_ring(struct intel_engine_cs *engine)
-{
- intel_engine_stop_cs(engine);
-
- ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL));
-
- ENGINE_WRITE(engine, RING_HEAD, 0);
- ENGINE_WRITE(engine, RING_TAIL, 0);
-
- /* The ring must be empty before it is disabled */
- ENGINE_WRITE(engine, RING_CTL, 0);
-
- return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0;
-}
-
static struct i915_address_space *vm_alias(struct i915_address_space *vm)
{
if (i915_is_ggtt(vm))
@@ -212,31 +197,6 @@ static int xcs_resume(struct intel_engine_cs *engine)
intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
- /* WaClearRingBufHeadRegAtInit:ctg,elk */
- if (!stop_ring(engine)) {
- /* G45 ring initialization often fails to reset head to zero */
- drm_dbg(_priv->drm, "%s head not reset to zero "
- "ctl %08x head %08x tail %08x start %08x\n",
- engine->name,
- ENGINE_READ(engine, RING_CTL),
- ENGINE_READ(engine, RING_HEAD),
- ENGINE_READ(engine, RING_TAIL),
- ENGINE_READ(engine, RING_START));
-
- if (!stop_ring(engine)) {
- drm_err(_priv->drm,
- "failed to set %s head to zero "
- "ctl %08x head %08x tail %08x start %08x\n",
- engine->name,
- ENGINE_READ(engine, RING_CTL),
- ENGINE_READ(engine, RING_HEAD),
- ENGINE_READ(engine, RING_TAIL),
- ENGINE_READ(engine, RING_START));
- ret = -EIO;
- goto out;
- }
- }
-
if (HWS_NEEDS_PHYSICAL(dev_priv))
ring_setup_phys_status_page(engine);
else
@@ -338,11 +298,21 @@ static void xcs_sanitize(struct intel_engine_cs *engine)
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
}
-static void reset_prepare(struct intel_engine_cs *engine)
+static bool stop_ring(struct intel_engine_cs *engine)
{
- struct intel_uncore *uncore = engine->uncore;
- const u32 base = engine->mmio_base;
+ ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL));
+
+ ENGINE_WRITE_FW(engine, RING_HEAD, 0);
+ ENGINE_WRITE_FW(engine, RING_TAIL, 0);
+ /* The ring must be empty before it is disabled */
+ ENGINE_WRITE_FW(engine, RING_CTL, 0);
+
+ return (ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) == 0;
+}
+
+static void reset_prepare(struct intel_engine_cs *engine)
+{
/*
* We stop engines, otherwise we might get failed reset and a
* dead gpu (on elk). Also as modern gpu as kbl can suffer
@@ -354,30 +324,35 @@ static void reset_prepare(struct intel_engine_cs *engine)
* WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
*
* WaMediaResetMainRingCleanup:ctg,elk (presumably)
+* WaClearRingBufHeadRegAtInit:ctg,elk
*
* FIXME: Wa for more modern gens needs to be validated
*/
ENGINE_TRACE(engine, "\n");
+ intel_engine_stop_cs(engine);
- if (intel_engine_stop_cs(engine))
- ENGINE_TRACE(engine, "timed out on STOP_RING\n");
-
- intel_uncore_write_fw(uncore,
- RING_HEAD(base),
- intel_uncore_read_fw(uncore, RING_TAIL(base)));
- intel_uncore_posting_read_fw(uncore, RING_HEAD(base)); /* paranoia */
-
- intel_uncore_write_fw(uncore, RING_HEAD(base), 0);
- intel_uncore_write_fw(uncore, RING_TAIL(base), 0);
- intel_uncore_posting_read_fw(uncore, RING_TAIL(base));
-
- /* The ring must be empty before it is disabled */
- intel_uncore_write_fw(uncore, RING_CTL(base), 0);
+ if (!stop_ring(engine)) {
+ /* G45 ring initialization often fails to reset head to zero */
+ drm_dbg(>i915->drm,
+ "%s head not reset to zero "
+ "ctl %08x head %08x tail %08x start %08x\n",
+ engine->name,
+
[Intel-gfx] [PATCH 4/8] drm/i915/gt: Reapply ppgtt enabling after engine resets
The GFX_MODE is reset along with the engine, turning off ppGTT. We need
to re-enable it upon resume.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c| 9 -
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 13 ++---
2 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 680bd9442eb0..0f02afe7f43a 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -27,8 +27,6 @@ void gen7_ppgtt_enable(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore = gt->uncore;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
u32 ecochk;
intel_uncore_rmw(uncore, GAC_ECO_BITS, 0, ECOBITS_PPGTT_CACHE64B);
@@ -41,13 +39,6 @@ void gen7_ppgtt_enable(struct intel_gt *gt)
ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
}
intel_uncore_write(uncore, GAM_ECOCHK, ecochk);
-
- for_each_engine(engine, gt, id) {
- /* GFX_MODE is per-ring on gen7+ */
- ENGINE_WRITE(engine,
-RING_MODE_GEN7,
-_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
- }
}
void gen6_ppgtt_enable(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 90b483b4ae5d..d794e13610b2 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -188,9 +188,16 @@ static void set_pp_dir(struct intel_engine_cs *engine)
{
struct i915_address_space *vm = vm_alias(engine->gt->vm);
- if (vm) {
- ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
- ENGINE_WRITE(engine, RING_PP_DIR_BASE, pp_dir(vm));
+ if (!vm)
+ return;
+
+ ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
+ ENGINE_WRITE(engine, RING_PP_DIR_BASE, pp_dir(vm));
+
+ if (INTEL_GEN(engine->i915) >= 7) {
+ ENGINE_WRITE(engine,
+RING_MODE_GEN7,
+_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
}
}
--
2.20.1
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[Intel-gfx] [PATCH 6/8] drm/i915/gt: Pull ring submission resume under its caller forcewake
Take advantage of calling xcs_resume under a forcewake by using direct
mmio access. In particular, we can avoid the sleeping variants to allow
resume to be called from softirq context, required for engine resets.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 98 ---
1 file changed, 43 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 7c31126a1b6d..77aec0a94541 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -121,31 +121,27 @@ static void set_hwsp(struct intel_engine_cs *engine, u32
offset)
hwsp = RING_HWS_PGA(engine->mmio_base);
}
- intel_uncore_write(engine->uncore, hwsp, offset);
- intel_uncore_posting_read(engine->uncore, hwsp);
+ intel_uncore_write_fw(engine->uncore, hwsp, offset);
+ intel_uncore_posting_read_fw(engine->uncore, hwsp);
}
static void flush_cs_tlb(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
-
- if (!IS_GEN_RANGE(dev_priv, 6, 7))
+ if (!IS_GEN_RANGE(engine->i915, 6, 7))
return;
/* ring should be idle before issuing a sync flush*/
- drm_WARN_ON(_priv->drm,
- (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
-
- ENGINE_WRITE(engine, RING_INSTPM,
-_MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
- INSTPM_SYNC_FLUSH));
- if (intel_wait_for_register(engine->uncore,
- RING_INSTPM(engine->mmio_base),
- INSTPM_SYNC_FLUSH, 0,
- 1000))
- drm_err(_priv->drm,
- "%s: wait for SyncFlush to complete for TLB
invalidation timed out\n",
- engine->name);
+ GEM_DEBUG_WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
+
+ ENGINE_WRITE_FW(engine, RING_INSTPM,
+ _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
+ INSTPM_SYNC_FLUSH));
+ if (__intel_wait_for_register_fw(engine->uncore,
+RING_INSTPM(engine->mmio_base),
+INSTPM_SYNC_FLUSH, 0,
+2000, 0, NULL))
+ ENGINE_TRACE(engine,
+"wait for SyncFlush to complete for TLB
invalidation timed out\n");
}
static void ring_setup_status_page(struct intel_engine_cs *engine)
@@ -176,13 +172,13 @@ static void set_pp_dir(struct intel_engine_cs *engine)
if (!vm)
return;
- ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
- ENGINE_WRITE(engine, RING_PP_DIR_BASE, pp_dir(vm));
+ ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
+ ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm));
if (INTEL_GEN(engine->i915) >= 7) {
- ENGINE_WRITE(engine,
-RING_MODE_GEN7,
-_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+ ENGINE_WRITE_FW(engine,
+ RING_MODE_GEN7,
+ _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
}
}
@@ -190,13 +186,10 @@ static int xcs_resume(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
struct intel_ring *ring = engine->legacy.ring;
- int ret = 0;
ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n",
ring->head, ring->tail);
- intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
-
if (HWS_NEEDS_PHYSICAL(dev_priv))
ring_setup_phys_status_page(engine);
else
@@ -204,16 +197,13 @@ static int xcs_resume(struct intel_engine_cs *engine)
intel_breadcrumbs_reset(engine->breadcrumbs);
- /* Enforce ordering by reading HEAD register back */
- ENGINE_POSTING_READ(engine, RING_HEAD);
-
/*
* Initialize the ring. This must happen _after_ we've cleared the ring
* registers with the above sequence (the readback of the HEAD registers
* also enforces ordering), otherwise the hw might lose the new ring
* register values.
*/
- ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma));
+ ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma));
/* Check that the ring offsets point within the ring! */
GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
@@ -223,46 +213,44 @@ static int xcs_resume(struct intel_engine_cs *engine)
set_pp_dir(engine);
/* First wake the ring up to an empty/idle ring */
- ENGINE_WRITE(engine, RING_HEAD, ring->head);
-
[Intel-gfx] [PATCH 8/8] drm/i915: Mark per-engine-reset as supported on gen7
The benefit of only resetting a single engine is that we leave other
streams of userspace work intact across a hang; vital for process
isolation. We had wired up individual engine resets for gen6, but only
enabled it from gen8; now let's turn it on for the forgotten gen7. gen6
is still a mystery as how to unravel some global state that appears to
be reset along with an engine (in particular the ppgtt enabling in
GFX_MODE).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pci.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 11fe790b1969..91e0092d081e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -455,6 +455,7 @@ static const struct intel_device_info snb_m_gt2_info = {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
+ .has_reset_engine = true, \
.has_rps = true, \
.dma_mask_size = 40, \
.ppgtt_type = INTEL_PPGTT_ALIASING, \
@@ -513,6 +514,7 @@ static const struct intel_device_info vlv_info = {
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
.has_runtime_pm = 1,
.has_rc6 = 1,
+ .has_reset_engine = true,
.has_rps = true,
.display.has_gmch = 1,
.display.has_hotplug = 1,
@@ -571,8 +573,7 @@ static const struct intel_device_info hsw_gt3_info = {
.dma_mask_size = 39, \
.ppgtt_type = INTEL_PPGTT_FULL, \
.ppgtt_size = 48, \
- .has_64bit_reloc = 1, \
- .has_reset_engine = 1
+ .has_64bit_reloc = 1
#define BDW_PLATFORM \
GEN8_FEATURES, \
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/8] drm/i915/selftests: Prepare the selftests for engine resets with ring submission
The engine resets selftests kick the tasklets, safe up until now as only
execlists supported engine resets.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 18 ++
drivers/gpu/drm/i915/gt/selftest_reset.c | 11 ---
2 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index c28d1fcad673..28f71cc2004d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -560,6 +560,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool
active)
for_each_engine(engine, gt, id) {
unsigned int reset_count, reset_engine_count;
+ unsigned long count;
IGT_TIMEOUT(end_time);
if (active && !intel_engine_can_store_dword(engine))
@@ -577,6 +578,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool
active)
st_engine_heartbeat_disable(engine);
set_bit(I915_RESET_ENGINE + id, >reset.flags);
+ count = 0;
do {
if (active) {
struct i915_request *rq;
@@ -625,9 +627,13 @@ static int __igt_reset_engine(struct intel_gt *gt, bool
active)
err = -EINVAL;
break;
}
+
+ count++;
} while (time_before(jiffies, end_time));
clear_bit(I915_RESET_ENGINE + id, >reset.flags);
st_engine_heartbeat_enable(engine);
+ pr_info("%s: Completed %lu %s resets\n",
+ engine->name, count, active ? "active" : "idle");
if (err)
break;
@@ -1478,7 +1484,8 @@ static int igt_reset_queue(void *arg)
prev = rq;
count++;
} while (time_before(jiffies, end_time));
- pr_info("%s: Completed %d resets\n", engine->name, count);
+ pr_info("%s: Completed %d queued resets\n",
+ engine->name, count);
*h.batch = MI_BATCH_BUFFER_END;
intel_gt_chipset_flush(engine->gt);
@@ -1575,7 +1582,8 @@ static int __igt_atomic_reset_engine(struct
intel_engine_cs *engine,
GEM_TRACE("i915_reset_engine(%s:%s) under %s\n",
engine->name, mode, p->name);
- tasklet_disable(t);
+ if (t->func)
+ tasklet_disable(t);
if (strcmp(p->name, "softirq"))
local_bh_disable();
p->critical_section_begin();
@@ -1585,8 +1593,10 @@ static int __igt_atomic_reset_engine(struct
intel_engine_cs *engine,
p->critical_section_end();
if (strcmp(p->name, "softirq"))
local_bh_enable();
- tasklet_enable(t);
- tasklet_hi_schedule(t);
+ if (t->func) {
+ tasklet_enable(t);
+ tasklet_hi_schedule(t);
+ }
if (err)
pr_err("i915_reset_engine(%s:%s) failed under %s\n",
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c
b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 5ec8d4e9983f..07946c33044a 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -321,7 +321,10 @@ static int igt_atomic_engine_reset(void *arg)
goto out_unlock;
for_each_engine(engine, gt, id) {
- tasklet_disable(>execlists.tasklet);
+ struct tasklet_struct *t = >execlists.tasklet;
+
+ if (t->func)
+ tasklet_disable(t);
intel_engine_pm_get(engine);
for (p = igt_atomic_phases; p->name; p++) {
@@ -345,8 +348,10 @@ static int igt_atomic_engine_reset(void *arg)
}
intel_engine_pm_put(engine);
- tasklet_enable(>execlists.tasklet);
- tasklet_hi_schedule(>execlists.tasklet);
+ if (t->func) {
+ tasklet_enable(t);
+ tasklet_hi_schedule(t);
+ }
if (err)
break;
}
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/8] drm/i915/gt: Replace open-coded intel_engine_stop_cs()
In the legacy ringbuffer submission, we still had an open-coded version
of intel_engine_stop_cs() with one addition verification step. Transfer
that verification to intel_engine_stop_cs() itself, and call it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 15 +--
.../gpu/drm/i915/gt/intel_ring_submission.c | 25 +--
2 files changed, 14 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1847d3c2ea99..58c900a12c13 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1048,8 +1048,19 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
ENGINE_TRACE(engine, "\n");
if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
- ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n");
- err = -ETIMEDOUT;
+ ENGINE_TRACE(engine,
+"timed out on STOP_RING -> IDLE; HEAD:%04x,
TAIL:%04x\n",
+ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR,
+ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR);
+
+ /*
+* Sometimes we observe that the idle flag is not
+* set even though the ring is empty. So double
+* check before giving up.
+*/
+ if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) !=
+ (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR))
+ err = -ETIMEDOUT;
}
return err;
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 4ea741f488a8..90b483b4ae5d 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -158,30 +158,7 @@ static void ring_setup_status_page(struct intel_engine_cs
*engine)
static bool stop_ring(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
-
- if (INTEL_GEN(dev_priv) > 2) {
- ENGINE_WRITE(engine,
-RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING));
- if (intel_wait_for_register(engine->uncore,
- RING_MI_MODE(engine->mmio_base),
- MODE_IDLE,
- MODE_IDLE,
- 1000)) {
- drm_err(_priv->drm,
- "%s : timed out trying to stop ring\n",
- engine->name);
-
- /*
-* Sometimes we observe that the idle flag is not
-* set even though the ring is empty. So double
-* check before giving up.
-*/
- if (ENGINE_READ(engine, RING_HEAD) !=
- ENGINE_READ(engine, RING_TAIL))
- return false;
- }
- }
+ intel_engine_stop_cs(engine);
ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL));
--
2.20.1
___
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[Intel-gfx] [PATCH 2/8] drm/i915/gt: Rearrange ivb workarounds
Some rcs0 workarounds were being incorrectly applied to the GT, and so
we failed to restore the expected register settings after a reset.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 118
1 file changed, 47 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3d5122301f64..7c18893f5164 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -829,18 +829,6 @@ snb_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
static void
ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
{
- /* WaDisableEarlyCull:ivb */
- wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
-
- /* WaDisablePSDDualDispatchEnable:ivb */
- if (IS_IVB_GT1(i915))
- wa_masked_en(wal,
-GEN7_HALF_SLICE_CHICKEN1,
-GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
-
- /* WaDisable_RenderCache_OperationalFlush:ivb */
- wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
-
/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
wa_masked_dis(wal,
GEN7_COMMON_SLICE_CHICKEN1,
@@ -852,38 +840,6 @@ ivb_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
/* WaForceL3Serialization:ivb */
wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
-
- /*
-* WaVSThreadDispatchOverride:ivb,vlv
-*
-* This actually overrides the dispatch
-* mode for all thread types.
-*/
- wa_write_clr_set(wal, GEN7_FF_THREAD_MODE,
-GEN7_FF_SCHED_MASK,
-GEN7_FF_TS_SCHED_HW |
-GEN7_FF_VS_SCHED_HW |
-GEN7_FF_DS_SCHED_HW);
-
- if (0) { /* causes HiZ corruption on ivb:gt1 */
- /* enable HiZ Raw Stall Optimization */
- wa_masked_dis(wal, CACHE_MODE_0_GEN7,
HIZ_RAW_STALL_OPT_DISABLE);
- }
-
- /* WaDisable4x2SubspanOptimization:ivb */
- wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
-
- /*
-* BSpec recommends 8x4 when MSAA is used,
-* however in practice 16x4 seems fastest.
-*
-* Note that PS/WM thread counts depend on the WIZ hashing
-* disable bit, which we don't touch here, but it's good
-* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
-*/
- wa_add(wal, GEN7_GT_MODE, 0,
- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
- GEN6_WIZ_HASHING_16x4);
}
static void
@@ -1886,34 +1842,53 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
wa_masked_dis(wal,
CACHE_MODE_0_GEN7,
- /* WaDisable_RenderCache_OperationalFlush:hsw */
- RC_OP_FLUSH_ENABLE |
/* enable HiZ Raw Stall Optimization */
HIZ_RAW_STALL_OPT_DISABLE);
/* WaDisable4x2SubspanOptimization:hsw */
wa_masked_en(wal, CACHE_MODE_1,
PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
+ }
+
+ if (IS_VALLEYVIEW(i915)) {
+ /* WaDisableEarlyCull:vlv */
+ wa_masked_en(wal,
+_3D_CHICKEN3,
+_3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
/*
-* BSpec recommends 8x4 when MSAA is used,
-* however in practice 16x4 seems fastest.
+* WaVSThreadDispatchOverride:ivb,vlv
*
-* Note that PS/WM thread counts depend on the WIZ hashing
-* disable bit, which we don't touch here, but it's good
-* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
+* This actually overrides the dispatch
+* mode for all thread types.
*/
- wa_add(wal, GEN7_GT_MODE, 0,
- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK,
-GEN6_WIZ_HASHING_16x4),
- GEN6_WIZ_HASHING_16x4);
+ wa_write_clr_set(wal,
+GEN7_FF_THREAD_MODE,
+GEN7_FF_SCHED_MASK,
+GEN7_FF_TS_SCHED_HW |
+GEN7_FF_VS_SCHED_HW |
+GEN7_FF_DS_SCHED_HW);
+
+ /* WaPsdDispatchEnable:vlv */
+ /* WaDisablePSDDualDispatchEnable:vlv */
+ wa_masked_en(wal,
+GEN7_HALF_SLICE_CHICKEN1,
+GEN7_MAX_PS_THREAD_DEP |
+
[Intel-gfx] [PATCH 1/8] drm/i915/gt: Rearrange vlv workarounds
Some rcs0 workarounds were being incorrectly applied to the GT, and so
we failed to restore the expected register settings after a reset.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 95 +++--
1 file changed, 51 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index c21a9726326a..3d5122301f64 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -889,53 +889,9 @@ ivb_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
static void
vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
{
- /* WaDisableEarlyCull:vlv */
- wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
-
- /* WaPsdDispatchEnable:vlv */
- /* WaDisablePSDDualDispatchEnable:vlv */
- wa_masked_en(wal,
-GEN7_HALF_SLICE_CHICKEN1,
-GEN7_MAX_PS_THREAD_DEP |
-GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
-
- /* WaDisable_RenderCache_OperationalFlush:vlv */
- wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
-
/* WaForceL3Serialization:vlv */
wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
- /*
-* WaVSThreadDispatchOverride:ivb,vlv
-*
-* This actually overrides the dispatch
-* mode for all thread types.
-*/
- wa_write_clr_set(wal,
-GEN7_FF_THREAD_MODE,
-GEN7_FF_SCHED_MASK,
-GEN7_FF_TS_SCHED_HW |
-GEN7_FF_VS_SCHED_HW |
-GEN7_FF_DS_SCHED_HW);
-
- /*
-* BSpec says this must be set, even though
-* WaDisable4x2SubspanOptimization isn't listed for VLV.
-*/
- wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
-
- /*
-* BSpec recommends 8x4 when MSAA is used,
-* however in practice 16x4 seems fastest.
-*
-* Note that PS/WM thread counts depend on the WIZ hashing
-* disable bit, which we don't touch here, but it's good
-* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
-*/
- wa_add(wal, GEN7_GT_MODE, 0,
- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
- GEN6_WIZ_HASHING_16x4);
-
/*
* WaIncreaseL3CreditsForVLVB0:vlv
* This is the hardware default actually.
@@ -1952,6 +1908,57 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
GEN6_WIZ_HASHING_16x4);
}
+ if (IS_VALLEYVIEW(i915)) {
+ /* WaDisableEarlyCull:vlv */
+ wa_masked_en(wal,
+_3D_CHICKEN3,
+_3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
+
+ /*
+* WaVSThreadDispatchOverride:ivb,vlv
+*
+* This actually overrides the dispatch
+* mode for all thread types.
+*/
+ wa_write_clr_set(wal,
+GEN7_FF_THREAD_MODE,
+GEN7_FF_SCHED_MASK,
+GEN7_FF_TS_SCHED_HW |
+GEN7_FF_VS_SCHED_HW |
+GEN7_FF_DS_SCHED_HW);
+
+ /* WaDisable_RenderCache_OperationalFlush:vlv */
+ wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
+
+ /*
+* BSpec says this must be set, even though
+* WaDisable4x2SubspanOptimization isn't listed for VLV.
+*/
+ wa_masked_en(wal,
+CACHE_MODE_1,
+PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
+
+ /*
+* BSpec recommends 8x4 when MSAA is used,
+* however in practice 16x4 seems fastest.
+*
+* Note that PS/WM thread counts depend on the WIZ hashing
+* disable bit, which we don't touch here, but it's good
+* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
+*/
+ wa_add(wal, GEN7_GT_MODE, 0,
+ _MASKED_FIELD(GEN6_WIZ_HASHING_MASK,
+GEN6_WIZ_HASHING_16x4),
+ GEN6_WIZ_HASHING_16x4);
+
+ /* WaPsdDispatchEnable:vlv */
+ /* WaDisablePSDDualDispatchEnable:vlv */
+ wa_masked_en(wal,
+GEN7_HALF_SLICE_CHICKEN1,
+GEN7_MAX_PS_THREAD_DEP |
+GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
+ }
+
if (IS_GEN(i915, 7))
/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Disable RPM wakeref assertions during driver shutdown
== Series Details == Series: drm/i915: Disable RPM wakeref assertions during driver shutdown URL : https://patchwork.freedesktop.org/series/85456/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9544_full -> Patchwork_19253_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19253_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19253_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19253_full: ### Piglit changes ### Possible regressions * spec@!opengl 3.2@layered-rendering@gl-layer-render-storage (NEW): - pig-glk-j5005: NOTRUN -> [INCOMPLETE][1] +4 similar issues [1]: None New tests - New tests have been introduced between CI_DRM_9544_full and Patchwork_19253_full: ### New IGT tests (2) ### * igt@gem_spin_batch@legacy: - Statuses : - Exec time: [None] s * igt@gem_spin_batch@resubmit-new-all: - Statuses : - Exec time: [None] s ### New Piglit tests (5) ### * spec@!opengl 2.0@tex3d-npot: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@!opengl 3.2@layered-rendering@clear-color-all-types 3d single_level: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@!opengl 3.2@layered-rendering@gl-layer-render: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@!opengl 3.2@layered-rendering@gl-layer-render-storage: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_texture_multisample@large-float-texture: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19253_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-cleanup: - shard-hsw: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +5 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/shard-hsw5/igt@gem_ctx_persiste...@legacy-engines-cleanup.html * igt@gem_exec_reloc@basic-many-active@vcs0: - shard-hsw: NOTRUN -> [FAIL][3] ([i915#2389]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/shard-hsw5/igt@gem_exec_reloc@basic-many-act...@vcs0.html * igt@gem_exec_whisper@basic-queues-forked-all: - shard-glk: [PASS][4] -> [DMESG-WARN][5] ([i915#118] / [i915#95]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/shard-glk1/igt@gem_exec_whis...@basic-queues-forked-all.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/shard-glk9/igt@gem_exec_whis...@basic-queues-forked-all.html * igt@gem_userptr_blits@mmap-offset-invalidate-active@wb: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271]) +50 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/shard-snb6/igt@gem_userptr_blits@mmap-offset-invalidate-act...@wb.html * igt@gem_userptr_blits@process-exit-mmap@wc: - shard-hsw: NOTRUN -> [SKIP][7] ([fdo#109271]) +267 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/shard-hsw5/igt@gem_userptr_blits@process-exit-m...@wc.html * igt@gem_userptr_blits@vma-merge: - shard-hsw: NOTRUN -> [FAIL][8] ([i915#2724]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/shard-hsw5/igt@gem_userptr_bl...@vma-merge.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][9] -> [INCOMPLETE][10] ([i915#2295]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/shard-apl7/igt@gem_workarou...@suspend-resume-context.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/shard-apl8/igt@gem_workarou...@suspend-resume-context.html * igt@gen9_exec_parse@allowed-all: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1436] / [i915#716]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/shard-skl1/igt@gen9_exec_pa...@allowed-all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/shard-skl4/igt@gen9_exec_pa...@allowed-all.html * igt@i915_selftest@live@gt_heartbeat: - shard-skl: [PASS][13] -> [DMESG-FAIL][14] ([i915#2291] / [i915#541]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/shard-skl3/igt@i915_selftest@live@gt_heartbeat.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/shard-skl9/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2597]) [15]:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm: Add function to convert rect in 16.16 fixed format to regular format
== Series Details == Series: series starting with [CI,1/4] drm: Add function to convert rect in 16.16 fixed format to regular format URL : https://patchwork.freedesktop.org/series/85458/ State : success == Summary == CI Bug Log - changes from CI_DRM_9544 -> Patchwork_19254 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19254/index.html Known issues Here are the changes found in Patchwork_19254 that come from known issues: ### IGT changes ### Possible fixes * igt@i915_selftest@live@blt: - fi-snb-2600:[DMESG-FAIL][1] ([i915#1409]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/fi-snb-2600/igt@i915_selftest@l...@blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19254/fi-snb-2600/igt@i915_selftest@l...@blt.html [i915#1409]: https://gitlab.freedesktop.org/drm/intel/issues/1409 Participating hosts (42 -> 36) -- Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-tgl-y fi-bdw-samus Build changes - * Linux: CI_DRM_9544 -> Patchwork_19254 CI-20190529: 20190529 CI_DRM_9544: b950eb2b863a3e5de7b9647aa037ed50d7dd687c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5942: e14e76a87c44c684ec958b391b030bb549254f88 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19254: 7b34b5cee6ec5e996c12b1013f3f587b8e4e6d5c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7b34b5cee6ec drm/i915/display/psr: Program plane's calculated offset to plane SF register 8d547e349776 drm/i915/display: Split and export main surface calculation from skl_check_main_surface() f2f94c7d10be drm/i915/display/psr: Use plane damage clips to calculate damaged area 1d5b3487eab7 drm: Add function to convert rect in 16.16 fixed format to regular format == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19254/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/4] drm: Add function to convert rect in 16.16 fixed format to regular format
== Series Details == Series: series starting with [CI,1/4] drm: Add function to convert rect in 16.16 fixed format to regular format URL : https://patchwork.freedesktop.org/series/85458/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable RPM wakeref assertions during driver shutdown
== Series Details ==
Series: drm/i915: Disable RPM wakeref assertions during driver shutdown
URL : https://patchwork.freedesktop.org/series/85456/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9544 -> Patchwork_19253
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19253:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_parallel@engines@userptr:
- {fi-tgl-dsi}: [PASS][1] -> [FAIL][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/fi-tgl-dsi/igt@gem_exec_parallel@engi...@userptr.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/fi-tgl-dsi/igt@gem_exec_parallel@engi...@userptr.html
Known issues
Here are the changes found in Patchwork_19253 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-kbl-soraka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/fi-kbl-soraka/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/fi-kbl-soraka/igt@i915_module_l...@reload.html
* igt@prime_vgem@basic-fence-flip:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +2 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/fi-tgl-y/igt@prime_v...@basic-fence-flip.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/fi-tgl-y/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@i915_selftest@live@blt:
- fi-snb-2600:[DMESG-FAIL][9] ([i915#1409]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9544/fi-snb-2600/igt@i915_selftest@l...@blt.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/fi-snb-2600/igt@i915_selftest@l...@blt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1409]: https://gitlab.freedesktop.org/drm/intel/issues/1409
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (42 -> 37)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9544 -> Patchwork_19253
CI-20190529: 20190529
CI_DRM_9544: b950eb2b863a3e5de7b9647aa037ed50d7dd687c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5942: e14e76a87c44c684ec958b391b030bb549254f88 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19253: 43ac52d56a96ad98dd75a27eedfec02057465412 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
43ac52d56a96 drm/i915: Disable RPM wakeref assertions during driver shutdown
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19253/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v10 1/2] drm/i915/display: Support PSR Multiple Instances
On Mon, 2021-01-04 at 15:07 +0200, Gwan-gyeong Mun wrote:
> It is a preliminary work for supporting multiple EDP PSR and
> DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
> supportable PSR.
> And this moves and renames the i915_psr structure of drm_i915_private's to
> intel_dp's intel_psr structure.
> It also causes changes in PSR interrupt handling routine for supporting
> multiple transcoders. But it does not change the scenario and timing of
> enabling and disabling PSR. And it not support multiple pipes with
> a single transcoder PSR case yet.
>
> v2: Fix indentation and add comments
> v3: Remove Blank line
> v4: Rebased
> v5: Rebased and Addressed Anshuman's review comment.
> - Move calling of intel_psr_init() to intel_dp_init_connector()
> v6: Address Anshuman's review comments
> - Remove wrong comments and add comments for a limit of supporting of
> a single pipe PSR
> v7: Update intel_psr_compute_config() for supporting multiple transcoder
> PSR on BDW+
> v8: Address Anshuman's review comments
> - Replace DRM_DEBUG_KMS with drm_dbg_kms() / DRM_WARN with drm_warn()
> v9: Fix commit message
> v10: Rebased
>
> Signed-off-by: Gwan-gyeong Mun
> Cc: José Roberto de Souza
> Cc: Juha-Pekka Heikkila
> Cc: Anshuman Gupta
> Reviewed-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
> drivers/gpu/drm/i915/display/intel_display.c | 4 -
> .../drm/i915/display/intel_display_debugfs.c | 111 ++--
> .../drm/i915/display/intel_display_types.h| 38 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 23 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 576 ++
> drivers/gpu/drm/i915/display/intel_psr.h | 14 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
> drivers/gpu/drm/i915/i915_drv.h | 38 --
> drivers/gpu/drm/i915/i915_irq.c | 49 +-
> 10 files changed, 485 insertions(+), 377 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 17eaa56c5a99..ae78167013d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4324,7 +4324,10 @@ static void intel_ddi_update_pipe_dp(struct
> intel_atomic_state *state,
>
>
>
>
> intel_ddi_set_dp_msa(crtc_state, conn_state);
>
>
>
>
> + //TODO: move PSR related functions into intel_psr_update()
> + intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
Call intel_psr2_program_trans_man_trk_ctl() before intel_psr_update() that is
wrong, PSR could be disable or with PSR1 enabled and
intel_psr2_program_trans_man_trk_ctl() would be executed before the PSR switch
also this change don't look related to this patch.
> intel_psr_update(intel_dp, crtc_state, conn_state);
> +
> intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> intel_edp_drrs_update(intel_dp, crtc_state);
>
>
>
>
>
>
>
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f2c48e5cdb43..c857489f2ccd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14821,8 +14821,6 @@ static void commit_pipe_config(struct
> intel_atomic_state *state,
>
>
>
>
>
>
>
>
> if (new_crtc_state->update_pipe)
> intel_pipe_fastset(old_crtc_state, new_crtc_state);
> -
> - intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
> }
>
>
>
>
>
>
>
>
> if (dev_priv->display.atomic_update_watermarks)
> @@ -16348,8 +16346,6 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> intel_dvo_init(dev_priv);
> }
>
>
>
>
>
>
>
>
> - intel_psr_init(dev_priv);
> -
> for_each_intel_encoder(_priv->drm, encoder) {
> encoder->base.possible_crtcs =
> intel_encoder_possible_crtcs(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index cd7e5519ee7d..041053167d7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -249,18 +249,17 @@ static int i915_psr_sink_status_show(struct seq_file
> *m, void *data)
> "sink internal error",
> };
> struct drm_connector *connector = m->private;
> - struct drm_i915_private *dev_priv = to_i915(connector->dev);
> struct intel_dp *intel_dp =
> intel_attached_dp(to_intel_connector(connector));
> int ret;
>
>
>
>
>
>
>
>
> - if (!CAN_PSR(dev_priv)) {
> - seq_puts(m, "PSR Unsupported\n");
> + if (connector->status != connector_status_connected)
> return -ENODEV;
> - }
>
>
>
>
>
>
>
>
> - if (connector->status
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Use kzalloc for allocating only one thing
== Series Details ==
Series: drm/i915: Use kzalloc for allocating only one thing
URL : https://patchwork.freedesktop.org/series/85447/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9542_full -> Patchwork_19250_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19250_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_spin_batch@user-each}:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-skl6/igt@gem_spin_ba...@user-each.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/shard-skl2/igt@gem_spin_ba...@user-each.html
Known issues
Here are the changes found in Patchwork_19250_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@engines-cleanup:
- shard-hsw: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +2
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/shard-hsw4/igt@gem_ctx_persiste...@engines-cleanup.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2389])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-glk2/igt@gem_exec_reloc@basic-many-act...@rcs0.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/shard-glk2/igt@gem_exec_reloc@basic-many-act...@rcs0.html
* igt@gem_exec_whisper@basic-queues-all:
- shard-glk: [PASS][6] -> [DMESG-WARN][7] ([i915#118] / [i915#95])
+1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-glk5/igt@gem_exec_whis...@basic-queues-all.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/shard-glk3/igt@gem_exec_whis...@basic-queues-all.html
* igt@gen3_render_tiledx_blits:
- shard-tglb: NOTRUN -> [SKIP][8] ([fdo#109289])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/shard-tglb6/igt@gen3_render_tiledx_blits.html
* igt@gen9_exec_parse@unaligned-jump:
- shard-tglb: NOTRUN -> [SKIP][9] ([fdo#112306])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/shard-tglb6/igt@gen9_exec_pa...@unaligned-jump.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][10] ([fdo#111615]) +1 similar issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/shard-tglb6/igt@kms_big...@yf-tiled-32bpp-rotate-0.html
* igt@kms_chamelium@dp-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/shard-skl7/igt@kms_chamel...@dp-crc-multiple.html
* igt@kms_chamelium@hdmi-crc-multiple:
- shard-tglb: NOTRUN -> [SKIP][12] ([fdo#109284] / [fdo#111827])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/shard-tglb6/igt@kms_chamel...@hdmi-crc-multiple.html
* igt@kms_color@pipe-a-ctm-0-25:
- shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-skl2/igt@kms_co...@pipe-a-ctm-0-25.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/shard-skl4/igt@kms_co...@pipe-a-ctm-0-25.html
* igt@kms_color@pipe-a-ctm-0-75:
- shard-tglb: NOTRUN -> [FAIL][15] ([i915#1149] / [i915#315])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/shard-tglb6/igt@kms_co...@pipe-a-ctm-0-75.html
* igt@kms_color_chamelium@pipe-d-ctm-max:
- shard-hsw: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827])
+11 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/shard-hsw4/igt@kms_color_chamel...@pipe-d-ctm-max.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#54]) +5 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-skl2/igt@kms_cursor_...@pipe-b-cursor-128x42-onscreen.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/shard-skl4/igt@kms_cursor_...@pipe-b-cursor-128x42-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen:
- shard-skl: NOTRUN -> [FAIL][19] ([i915#54]) +1 similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/shard-skl1/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-random:
- shard-tglb: NOTRUN -> [SKIP][20] ([fdo#109279])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/shard-tglb6/igt@kms_cursor_...@pipe-d-cursor-512x512-random.html
*
[Intel-gfx] [PULL] drm-intel-next
Hi Dave and Daniel, Happy New Year. Here goes the first pull request targeting 5.12. drm-intel-next-2021-01-04: - Display hotplug fix for gen2/gen3 (Chris) - Remove trailing semicolon (Tom) - Suppress display warnings for old ifwi presend on our CI (Chris) - OA/Perf related workaround (Lionel) - Replace I915_READ/WRITE per new uncore and display read/write functions (Jani)\ . - PSR improvements (Jose) - HDR and other color changes on LSPCON (Uma, Ville) - FBC fixes for TGL (Uma) - Record plane update times for debugging (Chris) - Refactor panel backlight control functions (Dave) - Display power improvements (Imre) - Add VRR register definition (Manasi) - Atomic modeset improvements for bigjoiner pipes (Ville) - Switch off the scanout during driver unregister (Chris) - Clean-up DP's FEW enable (Manasi) - Fix VDSCP slice count (Manasi) - Fix and clean up around rc_model_size for DSC (Jani) - Remove Type-C noisy debug warn message (Sean) - Display HPD code clean-up (Ville) - Refactor Intel Display (Dave) - Start adding support for Intel's eDP backlight controls (Lyude) Thanks, Rodrigo. The following changes since commit b3bf99daaee96a141536ce5c60a0d6dba6ec1d23: drm/i915/display: Defer initial modeset until after GGTT is initialised (2020-11-26 11:01:52 +) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2021-01-04 for you to fetch changes up to b3304591f14b437b6bccd8dbff06006c11837031: drm/i915/dp: Track pm_qos per connector (2020-12-30 21:22:55 +) - Display hotplug fix for gen2/gen3 (Chris) - Remove trailing semicolon (Tom) - Suppress display warnings for old ifwi presend on our CI (Chris) - OA/Perf related workaround (Lionel) - Replace I915_READ/WRITE per new uncore and display read/write functions (Jani)\ . - PSR improvements (Jose) - HDR and other color changes on LSPCON (Uma, Ville) - FBC fixes for TGL (Uma) - Record plane update times for debugging (Chris) - Refactor panel backlight control functions (Dave) - Display power improvements (Imre) - Add VRR register definition (Manasi) - Atomic modeset improvements for bigjoiner pipes (Ville) - Switch off the scanout during driver unregister (Chris) - Clean-up DP's FEW enable (Manasi) - Fix VDSCP slice count (Manasi) - Fix and clean up around rc_model_size for DSC (Jani) - Remove Type-C noisy debug warn message (Sean) - Display HPD code clean-up (Ville) - Refactor Intel Display (Dave) - Start adding support for Intel's eDP backlight controls (Lyude) Chris Wilson (6): Revert "drm/i915: re-order if/else ladder for hpd_irq_setup" drm/i915/display: Suppress "Combo PHY A HW state changed unexpectedly" drm/i915/display: Record the plane update times for debugging drm/i915/gem: Spring clean debugfs drm/i915: Disable outputs during unregister drm/i915/dp: Track pm_qos per connector Dave Airlie (6): drm/i915: refactor panel backlight control functions. (v2) drm/i915/display: move needs_modeset to an inline in header drm/i915/display: move to_intel_frontbuffer to header drm/i915/display: fix misused comma drm/i915: refactor cursor code out of i915_display.c drm/i915: refactor i915 plane code into separate file. Imre Deak (10): drm/i915: Use CRTC index consistently during getting/putting CRTC power domains drm/i915: Factor out helpers to get/put a set of tracked power domains drm/i915: Track power references taken for enabled CRTCs drm/i915/ddi: Track power reference taken for encoder DDI IO use drm/i915/ddi: Track power reference taken for encoder main lane AUX use drm/i915: Track power reference taken for eDP VDD drm/i915: Rename power_domains.wakeref to init_wakeref drm/i915: Track power reference taken to disable power well functionality drm/i915: Make intel_display_power_put_unchecked() an internal-only function drm/i915/icl: Fix initing the DSI DSC power refcount during HW readout Jani Nikula (15): drm/i915/debugfs: remove RPS autotuning details from i915_rps_boost_info drm/i915: remove last traces of I915_READ_FW() and I915_WRITE_FW() drm/i915/cdclk: prefer intel_de_write() over I915_WRITE() drm/i915/debugfs: remove the i915_cache_sharing debugfs file drm/i915/debugfs: replace I915_READ() with intel_uncore_read() drm/i915/suspend: replace I915_READ()/WRITE() with intel_de_read()/write() drm/i915/pm: replace I915_READ()/WRITE() with intel_uncore_read()/write() drm/i915/irq: replace I915_READ()/WRITE() with intel_uncore_read()/write() drm/i915/gvt: replace I915_WRITE with intel_uncore_write drm/i915: remove last traces of I915_READ(), I915_WRITE() and POSTING_READ() drm/dsc: use rc_model_size from DSC config for PPS drm/i915/dsc: configure
[Intel-gfx] [PATCH CI 4/4] drm/i915/display/psr: Program plane's calculated offset to plane SF register
It programs Plane's calculated x, y, offset to Plane SF register. It does the calculation of x and y offsets using skl_calc_main_surface_offset(). v3: Update commit message Cc: Gwan-gyeong Mun Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun Tested-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_psr.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f5b9519b3756..c24ae69426cf 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1186,7 +1186,8 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum pipe pipe = plane->pipe; const struct drm_rect *clip; - u32 val; + u32 val, offset; + int ret, x, y; if (!crtc_state->enable_psr2_sel_fetch) return; @@ -1203,9 +1204,14 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, val |= plane_state->uapi.dst.x1; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); - /* TODO: consider tiling and auxiliary surfaces */ - val = (clip->y1 + plane_state->color_plane[color_plane].y) << 16; - val |= plane_state->color_plane[color_plane].x; + /* TODO: consider auxiliary surfaces */ + x = plane_state->uapi.src.x1 >> 16; + y = (plane_state->uapi.src.y1 >> 16) + clip->y1; + ret = skl_calc_main_surface_offset(plane_state, , , ); + if (ret) + drm_warn_once(_priv->drm, "skl_calc_main_surface_offset() returned %i\n", + ret); + val = y << 16 | x; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), val); -- 2.30.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH CI 2/4] drm/i915/display/psr: Use plane damage clips to calculate damaged area
Now using plane damage clips property to calcualte the damaged area.
Selective fetch only supports one region to be fetched so software
needs to calculate a bounding box around all damage clips.
Now that we are not complete fetching each plane, there is another
loop needed as all the plane areas that intersect with the pipe
damaged area needs to be fetched from memory so the complete blending
of all planes can happen.
v2:
- do not shifting new_plane_state->uapi.dst only src is in 16.16 format
v4:
- setting plane selective fetch area using the whole pipe damage area
- mark the whole plane area damaged if plane visibility or alpha
changed
v5:
- taking in consideration src.y1 in the damage coordinates
- adding to the pipe damaged area planes that were visible but are
invisible in the new state
v6:
- consider old state plane coordinates when visibility changes or it
moved to calculate damaged area
- remove from damaged area the portion not in src clip
v7:
- intersec every damage clip with src to minimize damaged area
v8:
- adjust pipe_damaged area to 4 lines grouping
- adjust calculation now that is understood that uapi.src is the
framebuffer coordinates that plane will start to fetch from
v9:
- Only add plane dst or src to damaged_area if visible
- Early skip plane damage calculation if it was not visible in old and
new state
Cc: Ville Syrjälä
Cc: Gwan-gyeong Mun
Reviewed-by: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 113 ---
1 file changed, 99 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index d9a395c486d3..f5b9519b3756 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1242,9 +1242,11 @@ static void psr2_man_trk_ctl_calc(struct
intel_crtc_state *crtc_state,
if (clip->y1 == -1)
goto exit;
+ drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
+
val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
- val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(DIV_ROUND_UP(clip->y2, 4) +
1);
+ val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
exit:
crtc_state->psr2_man_track_ctl = val;
}
@@ -1269,8 +1271,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state
*state,
struct intel_crtc *crtc)
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 =
-1 };
struct intel_plane_state *new_plane_state, *old_plane_state;
- struct drm_rect pipe_clip = { .y1 = -1 };
struct intel_plane *plane;
bool full_update = false;
int i, ret;
@@ -1282,13 +1284,25 @@ int intel_psr2_sel_fetch_update(struct
intel_atomic_state *state,
if (ret)
return ret;
+ /*
+* Calculate minimal selective fetch area of each plane and calculate
+* the pipe damaged area.
+* In the next loop the plane selective fetch area will actually be set
+* using whole pipe damaged area.
+*/
for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
new_plane_state, i) {
- struct drm_rect *sel_fetch_area, temp;
+ struct drm_rect src, damaged_area = { .y1 = -1 };
+ struct drm_mode_rect *damaged_clips;
+ u32 num_clips, j;
if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
continue;
+ if (!new_plane_state->uapi.visible &&
+ !old_plane_state->uapi.visible)
+ continue;
+
/*
* TODO: Not clear how to handle planes with negative position,
* also planes are not updated if they have a negative X
@@ -1300,23 +1314,94 @@ int intel_psr2_sel_fetch_update(struct
intel_atomic_state *state,
break;
}
- if (!new_plane_state->uapi.visible)
- continue;
+ num_clips =
drm_plane_get_damage_clips_count(_plane_state->uapi);
/*
-* For now doing a selective fetch in the whole plane area,
-* optimizations will come in the future.
+* If visibility or plane moved, mark the whole plane area as
+* damaged as it needs to be complete redraw in the new and old
+* position.
*/
- sel_fetch_area = _plane_state->psr2_sel_fetch_area;
- sel_fetch_area->y1 = new_plane_state->uapi.src.y1 >> 16;
- sel_fetch_area->y2 = new_plane_state->uapi.src.y2 >> 16;
+
[Intel-gfx] [PATCH CI 3/4] drm/i915/display: Split and export main surface calculation from skl_check_main_surface()
The calculation the offsets of the main surface will be needed by PSR2
selective fetch code so here splitting and exporting it.
No functional changes were done here.
v3: Rebased
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Reviewed-by: Gwan-gyeong Mun
Tested-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_display.c | 78
drivers/gpu/drm/i915/display/intel_display.h | 2 +
2 files changed, 51 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f2c48e5cdb43..0189d379a55e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3752,33 +3752,19 @@ static int intel_plane_max_height(struct intel_plane
*plane,
return INT_MAX;
}
-static int skl_check_main_surface(struct intel_plane_state *plane_state)
+int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
+int *x, int *y, u32 *offset)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
- unsigned int rotation = plane_state->hw.rotation;
- int x = plane_state->uapi.src.x1 >> 16;
- int y = plane_state->uapi.src.y1 >> 16;
- int w = drm_rect_width(_state->uapi.src) >> 16;
- int h = drm_rect_height(_state->uapi.src) >> 16;
- int min_width = intel_plane_min_width(plane, fb, 0, rotation);
- int max_width = intel_plane_max_width(plane, fb, 0, rotation);
- int max_height = intel_plane_max_height(plane, fb, 0, rotation);
- int aux_plane = intel_main_to_aux_plane(fb, 0);
- u32 aux_offset = plane_state->color_plane[aux_plane].offset;
- u32 alignment, offset;
+ const int aux_plane = intel_main_to_aux_plane(fb, 0);
+ const u32 aux_offset = plane_state->color_plane[aux_plane].offset;
+ const u32 alignment = intel_surf_alignment(fb, 0);
+ const int w = drm_rect_width(_state->uapi.src) >> 16;
- if (w > max_width || w < min_width || h > max_height) {
- drm_dbg_kms(_priv->drm,
- "requested Y/RGB source size %dx%d outside limits
(min: %dx1 max: %dx%d)\n",
- w, h, min_width, max_width, max_height);
- return -EINVAL;
- }
-
- intel_add_fb_offsets(, , plane_state, 0);
- offset = intel_plane_compute_aligned_offset(, , plane_state, 0);
- alignment = intel_surf_alignment(fb, 0);
+ intel_add_fb_offsets(x, y, plane_state, 0);
+ *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);
if (drm_WARN_ON(_priv->drm, alignment && !is_power_of_2(alignment)))
return -EINVAL;
@@ -3787,9 +3773,10 @@ static int skl_check_main_surface(struct
intel_plane_state *plane_state)
* main surface offset, and it must be non-negative. Make
* sure that is what we will get.
*/
- if (aux_plane && offset > aux_offset)
- offset = intel_plane_adjust_aligned_offset(, , plane_state,
0,
- offset, aux_offset &
~(alignment - 1));
+ if (aux_plane && *offset > aux_offset)
+ *offset = intel_plane_adjust_aligned_offset(x, y, plane_state,
0,
+ *offset,
+ aux_offset &
~(alignment - 1));
/*
* When using an X-tiled surface, the plane blows up
@@ -3800,18 +3787,51 @@ static int skl_check_main_surface(struct
intel_plane_state *plane_state)
if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
int cpp = fb->format->cpp[0];
- while ((x + w) * cpp > plane_state->color_plane[0].stride) {
- if (offset == 0) {
+ while ((*x + w) * cpp > plane_state->color_plane[0].stride) {
+ if (*offset == 0) {
drm_dbg_kms(_priv->drm,
"Unable to find suitable display
surface offset due to X-tiling\n");
return -EINVAL;
}
- offset = intel_plane_adjust_aligned_offset(, ,
plane_state, 0,
- offset,
offset - alignment);
+ *offset = intel_plane_adjust_aligned_offset(x, y,
plane_state, 0,
+ *offset,
+ *offset -
alignment);
}
}
+ return 0;
+}
+
+static int skl_check_main_surface(struct intel_plane_state *plane_state)
[Intel-gfx] [PATCH CI 1/4] drm: Add function to convert rect in 16.16 fixed format to regular format
Much more clear to read one function call than four lines doing this
conversion.
v7:
- function renamed
- calculating width and height before truncate
- inlined
v10:
- renamed parameters from source and destination to src and dst
to match sister functions
Cc: Ville Syrjälä
Cc: dri-de...@lists.freedesktop.org
Cc: Gwan-gyeong Mun
Reviewed-by: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
include/drm/drm_rect.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/drm/drm_rect.h b/include/drm/drm_rect.h
index e7f4d24cdd00..39f2deee709c 100644
--- a/include/drm/drm_rect.h
+++ b/include/drm/drm_rect.h
@@ -206,6 +206,19 @@ static inline bool drm_rect_equals(const struct drm_rect
*r1,
r1->y1 == r2->y1 && r1->y2 == r2->y2;
}
+/**
+ * drm_rect_fp_to_int - Convert a rect in 16.16 fixed point form to int form.
+ * @dst: rect to be stored the converted value
+ * @src: rect in 16.16 fixed point form
+ */
+static inline void drm_rect_fp_to_int(struct drm_rect *dst,
+ const struct drm_rect *src)
+{
+ drm_rect_init(dst, src->x1 >> 16, src->y1 >> 16,
+ drm_rect_width(src) >> 16,
+ drm_rect_height(src) >> 16);
+}
+
bool drm_rect_intersect(struct drm_rect *r, const struct drm_rect *clip);
bool drm_rect_clip_scaled(struct drm_rect *src, struct drm_rect *dst,
const struct drm_rect *clip);
--
2.30.0
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[Intel-gfx] [PATCH] drm/i915: Disable RPM wakeref assertions during driver shutdown
As with the regular suspend paths, also disable the wakeref assertions
as we disable the driver during shutdown.
Reported-by: Hans de Goede
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2899
Fixes: fe0f1e3bfdfe ("drm/i915: Shut down displays gracefully on reboot")
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Hans de Goede
---
drivers/gpu/drm/i915/i915_drv.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 249f765993f7..643a899b3b44 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1046,6 +1046,8 @@ static void intel_shutdown_encoders(struct
drm_i915_private *dev_priv)
void i915_driver_shutdown(struct drm_i915_private *i915)
{
+ disable_rpm_wakeref_asserts(>runtime_pm);
+
i915_gem_suspend(i915);
drm_kms_helper_poll_disable(>drm);
@@ -1059,6 +1061,8 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
intel_suspend_encoders(i915);
intel_shutdown_encoders(i915);
+
+ enable_rpm_wakeref_asserts(>runtime_pm);
}
static bool suspend_to_idle(struct drm_i915_private *dev_priv)
--
2.20.1
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/gem: Almagamate clflushes on freeze
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip v5.11-rc2 next-20210104]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-gem-Almagamate-clflushes-on-suspend/20210104-220329
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a004-20210105 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
98cd1c33e3c2c3cfee36fb0fea3285fda06224d3)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
#
https://github.com/0day-ci/linux/commit/54314b2c3991bf37b7a6bf3b35eee4179a5e908a
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Chris-Wilson/drm-i915-gem-Almagamate-clflushes-on-suspend/20210104-220329
git checkout 54314b2c3991bf37b7a6bf3b35eee4179a5e908a
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/i915_gem.c:1286:2: error: implicit declaration of
>> function 'wbinvd_on_all_cpus' [-Werror,-Wimplicit-function-declaration]
wbinvd_on_all_cpus();
^
1 error generated.
vim +/wbinvd_on_all_cpus +1286 drivers/gpu/drm/i915/i915_gem.c
1261
1262 int i915_gem_freeze_late(struct drm_i915_private *i915)
1263 {
1264 struct drm_i915_gem_object *obj;
1265 intel_wakeref_t wakeref;
1266
1267 /*
1268 * Called just before we write the hibernation image.
1269 *
1270 * We need to update the domain tracking to reflect that the CPU
1271 * will be accessing all the pages to create and restore from
the
1272 * hibernation, and so upon restoration those pages will be in
the
1273 * CPU domain.
1274 *
1275 * To make sure the hibernation image contains the latest state,
1276 * we update that state just before writing out the image.
1277 *
1278 * To try and reduce the hibernation image, we manually shrink
1279 * the objects as well, see i915_gem_freeze()
1280 */
1281
1282 with_intel_runtime_pm(>runtime_pm, wakeref)
1283 i915_gem_shrink(i915, -1UL, NULL, ~0);
1284 i915_gem_drain_freed_objects(i915);
1285
> 1286 wbinvd_on_all_cpus();
1287 list_for_each_entry(obj, >mm.shrink_list, mm.link)
1288 __start_cpu_write(obj);
1289
1290 return 0;
1291 }
1292
---
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Guard against redifinition of SZ_8G
Quoting Souza, Jose (2021-01-04 19:59:42) > On Mon, 2021-01-04 at 17:13 +, Chris Wilson wrote: > > In the near future, upstream will introduce a SZ_8G macro that is > > slightly different to our own. Employ a temporary ifndef to avoid > > compilation failure until we have backmerged. > > Already here! > > Reviewed-by: José Roberto de Souza > > Will push this to fix build but from now on we probably want to remove this > macro right? I'd wait to remove our local SZ_8G until after we backmerge into drm-intel-gt-next. Got to keep both sides of the merge building. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/gem: Almagamate clflushes on suspend
== Series Details == Series: series starting with [1/2] drm/i915/gem: Almagamate clflushes on suspend URL : https://patchwork.freedesktop.org/series/85445/ State : success == Summary == CI Bug Log - changes from CI_DRM_9542_full -> Patchwork_19249_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19249_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@file: - shard-hsw: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/shard-hsw5/igt@gem_ctx_persiste...@file.html * igt@gem_exec_reloc@basic-many-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][2] ([i915#2389]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/shard-iclb1/igt@gem_exec_reloc@basic-many-act...@vcs1.html * igt@gem_exec_whisper@basic-contexts-forked: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-glk6/igt@gem_exec_whis...@basic-contexts-forked.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/shard-glk3/igt@gem_exec_whis...@basic-contexts-forked.html * igt@gen3_render_tiledx_blits: - shard-tglb: NOTRUN -> [SKIP][5] ([fdo#109289]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/shard-tglb7/igt@gen3_render_tiledx_blits.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][6] -> [DMESG-WARN][7] ([i915#1436] / [i915#716]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-skl10/igt@gen9_exec_pa...@allowed-single.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/shard-skl6/igt@gen9_exec_pa...@allowed-single.html * igt@gen9_exec_parse@unaligned-jump: - shard-tglb: NOTRUN -> [SKIP][8] ([fdo#112306]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/shard-tglb7/igt@gen9_exec_pa...@unaligned-jump.html * igt@i915_pm_rpm@system-suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#151]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-skl3/igt@i915_pm_...@system-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/shard-skl8/igt@i915_pm_...@system-suspend.html * igt@i915_selftest@mock@requests: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#198]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-skl1/igt@i915_selftest@m...@requests.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/shard-skl5/igt@i915_selftest@m...@requests.html * igt@kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-tglb: NOTRUN -> [SKIP][13] ([fdo#111615]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/shard-tglb7/igt@kms_big...@yf-tiled-32bpp-rotate-0.html * igt@kms_chamelium@dp-crc-multiple: - shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/shard-skl4/igt@kms_chamel...@dp-crc-multiple.html * igt@kms_chamelium@hdmi-crc-multiple: - shard-tglb: NOTRUN -> [SKIP][15] ([fdo#109284] / [fdo#111827]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/shard-tglb7/igt@kms_chamel...@hdmi-crc-multiple.html * igt@kms_color@pipe-a-ctm-0-75: - shard-tglb: NOTRUN -> [FAIL][16] ([i915#1149] / [i915#315]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/shard-tglb7/igt@kms_co...@pipe-a-ctm-0-75.html * igt@kms_color@pipe-b-ctm-green-to-red: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-skl7/igt@kms_co...@pipe-b-ctm-green-to-red.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/shard-skl6/igt@kms_co...@pipe-b-ctm-green-to-red.html * igt@kms_color_chamelium@pipe-d-ctm-max: - shard-hsw: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +6 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/shard-hsw5/igt@kms_color_chamel...@pipe-d-ctm-max.html * igt@kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-skl: NOTRUN -> [FAIL][20] ([i915#54]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/shard-skl4/igt@kms_cursor_...@pipe-a-cursor-64x21-random.html * igt@kms_cursor_crc@pipe-b-cursor-128x128-random: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#54]) +8 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-skl7/igt@kms_cursor_...@pipe-b-cursor-128x128-random.html [22]:
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Guard against redifinition of SZ_8G
On Mon, 2021-01-04 at 17:13 +, Chris Wilson wrote:
> In the near future, upstream will introduce a SZ_8G macro that is
> slightly different to our own. Employ a temporary ifndef to avoid
> compilation failure until we have backmerged.
Already here!
Reviewed-by: José Roberto de Souza
Will push this to fix build but from now on we probably want to remove this
macro right?
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/selftests/intel_memory_region.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> index a55079a061dd..75839db63bea 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> @@ -352,7 +352,9 @@ static int igt_mock_splintered_region(void *arg)
> return err;
> }
>
>
>
>
> +#ifndef SZ_8G
> #define SZ_8G BIT_ULL(33)
> +#endif
>
>
>
>
> static int igt_mock_max_segment(void *arg)
> {
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/gem: Almagamate clflushes on suspend
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip v5.11-rc2 next-20210104]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-gem-Almagamate-clflushes-on-suspend/20210104-220329
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a004-20210105 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
98cd1c33e3c2c3cfee36fb0fea3285fda06224d3)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
#
https://github.com/0day-ci/linux/commit/e17680e4b8352355fb03d0aeab4b0f16994fa2bd
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Chris-Wilson/drm-i915-gem-Almagamate-clflushes-on-suspend/20210104-220329
git checkout e17680e4b8352355fb03d0aeab4b0f16994fa2bd
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gem/i915_gem_pm.c:78:3: error: implicit declaration of
>> function 'wbinvd_on_all_cpus' [-Werror,-Wimplicit-function-declaration]
wbinvd_on_all_cpus();
^
1 error generated.
vim +/wbinvd_on_all_cpus +78 drivers/gpu/drm/i915/gem/i915_gem_pm.c
34
35 void i915_gem_suspend_late(struct drm_i915_private *i915)
36 {
37 struct drm_i915_gem_object *obj;
38 struct list_head *phases[] = {
39 >mm.shrink_list,
40 >mm.purge_list,
41 NULL
42 }, **phase;
43 unsigned long flags;
44 bool flush = false;
45
46 /*
47 * Neither the BIOS, ourselves or any other kernel
48 * expects the system to be in execlists mode on startup,
49 * so we need to reset the GPU back to legacy mode. And the only
50 * known way to disable logical contexts is through a GPU reset.
51 *
52 * So in order to leave the system in a known default
configuration,
53 * always reset the GPU upon unload and suspend. Afterwards we
then
54 * clean up the GEM state tracking, flushing off the requests
and
55 * leaving the system in a known idle state.
56 *
57 * Note that is of the upmost importance that the GPU is idle
and
58 * all stray writes are flushed *before* we dismantle the
backing
59 * storage for the pinned objects.
60 *
61 * However, since we are uncertain that resetting the GPU on
older
62 * machines is a good idea, we don't - just in case it leaves
the
63 * machine in an unusable condition.
64 */
65
66 intel_gt_suspend_late(>gt);
67
68 spin_lock_irqsave(>mm.obj_lock, flags);
69 for (phase = phases; *phase; phase++) {
70 list_for_each_entry(obj, *phase, mm.link) {
71 if (!(obj->cache_coherent &
I915_BO_CACHE_COHERENT_FOR_READ))
72 flush |= (obj->read_domains &
I915_GEM_DOMAIN_CPU) == 0;
73 __start_cpu_write(obj); /* presume
auto-hibernate */
74 }
75 }
76 spin_unlock_irqrestore(>mm.obj_lock, flags);
77 if (flush)
> 78 wbinvd_on_all_cpus();
79 }
80
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v10,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details == Series: series starting with [v10,1/2] drm/i915/display: Support PSR Multiple Instances URL : https://patchwork.freedesktop.org/series/85444/ State : success == Summary == CI Bug Log - changes from CI_DRM_9542_full -> Patchwork_19248_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19248_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-cleanup: - shard-hsw: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/shard-hsw8/igt@gem_ctx_persiste...@engines-cleanup.html * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][2] -> [INCOMPLETE][3] ([i915#2369] / [i915#2502]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-skl4/igt@gem_exec_capture@p...@rcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/shard-skl5/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-glk: [PASS][4] -> [FAIL][5] ([i915#2389]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-glk2/igt@gem_exec_reloc@basic-many-act...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/shard-glk8/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gen3_render_tiledx_blits: - shard-tglb: NOTRUN -> [SKIP][6] ([fdo#109289]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/shard-tglb6/igt@gen3_render_tiledx_blits.html * igt@gen9_exec_parse@unaligned-jump: - shard-tglb: NOTRUN -> [SKIP][7] ([fdo#112306]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/shard-tglb6/igt@gen9_exec_pa...@unaligned-jump.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2574]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-tglb7/igt@kms_async_fl...@test-time-stamp.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/shard-tglb8/igt@kms_async_fl...@test-time-stamp.html * igt@kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-tglb: NOTRUN -> [SKIP][10] ([fdo#111615]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/shard-tglb6/igt@kms_big...@yf-tiled-32bpp-rotate-0.html * igt@kms_ccs@pipe-c-bad-rotation-90: - shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111304]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/shard-skl5/igt@kms_...@pipe-c-bad-rotation-90.html * igt@kms_chamelium@dp-crc-multiple: - shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/shard-skl4/igt@kms_chamel...@dp-crc-multiple.html * igt@kms_chamelium@hdmi-crc-multiple: - shard-tglb: NOTRUN -> [SKIP][13] ([fdo#109284] / [fdo#111827]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/shard-tglb6/igt@kms_chamel...@hdmi-crc-multiple.html * igt@kms_color@pipe-a-ctm-0-75: - shard-tglb: NOTRUN -> [FAIL][14] ([i915#1149] / [i915#315]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/shard-tglb6/igt@kms_co...@pipe-a-ctm-0-75.html * igt@kms_color_chamelium@pipe-d-ctm-max: - shard-hsw: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +11 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/shard-hsw2/igt@kms_color_chamel...@pipe-d-ctm-max.html * igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen: - shard-skl: [PASS][16] -> [FAIL][17] ([i915#54]) +6 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-skl8/igt@kms_cursor_...@pipe-b-cursor-64x64-offscreen.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/shard-skl3/igt@kms_cursor_...@pipe-b-cursor-64x64-offscreen.html * igt@kms_cursor_crc@pipe-c-cursor-64x21-random: - shard-skl: NOTRUN -> [FAIL][18] ([i915#54]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/shard-skl5/igt@kms_cursor_...@pipe-c-cursor-64x21-random.html * igt@kms_cursor_crc@pipe-d-cursor-512x512-random: - shard-tglb: NOTRUN -> [SKIP][19] ([fdo#109279]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/shard-tglb6/igt@kms_cursor_...@pipe-d-cursor-512x512-random.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][20] -> [FAIL][21] ([i915#96]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-hsw5/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [21]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Guard against redifinition of SZ_8G (rev2)
== Series Details == Series: drm/i915/selftests: Guard against redifinition of SZ_8G (rev2) URL : https://patchwork.freedesktop.org/series/85451/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9542 -> Patchwork_19252 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19252 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19252, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19252/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19252: ### IGT changes ### Possible regressions * igt@i915_selftest@live@active: - fi-bwr-2160:[PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-bwr-2160/igt@i915_selftest@l...@active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19252/fi-bwr-2160/igt@i915_selftest@l...@active.html Warnings * igt@i915_hangman@error-state-basic: - fi-apl-guc: [DMESG-WARN][3] ([i915#1610]) -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-apl-guc/igt@i915_hang...@error-state-basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19252/fi-apl-guc/igt@i915_hang...@error-state-basic.html Known issues Here are the changes found in Patchwork_19252 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-tgl-y: NOTRUN -> [SKIP][5] ([fdo#109315] / [i915#2575]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19252/fi-tgl-y/igt@amdgpu/amd_ba...@cs-compute.html * igt@gem_close_race@basic-threads: - fi-tgl-y: [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-y/igt@gem_close_r...@basic-threads.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19252/fi-tgl-y/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live@requests: - fi-kbl-soraka: [PASS][8] -> [INCOMPLETE][9] ([i915#2782]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-kbl-soraka/igt@i915_selftest@l...@requests.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19252/fi-kbl-soraka/igt@i915_selftest@l...@requests.html * igt@runner@aborted: - fi-kbl-soraka: NOTRUN -> [FAIL][10] ([i915#1436] / [i915#2295]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19252/fi-kbl-soraka/igt@run...@aborted.html Possible fixes * igt@gem_tiled_blits@basic: - fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-y/igt@gem_tiled_bl...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19252/fi-tgl-y/igt@gem_tiled_bl...@basic.html [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (40 -> 37) -- Missing(3): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9542 -> Patchwork_19252 CI-20190529: 20190529 CI_DRM_9542: 64db0a08e9841f4cbe0fa5a37feba8606802fe13 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5941: 58b135e66be4fa4db8f668fa5d125b31537cb9a6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19252: a1bfe2c002d1620b888ba869bbb70db998fa816e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a1bfe2c002d1 drm/i915/selftests: Guard against redifinition of SZ_8G == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19252/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Guard against redifinition of SZ_8G (rev2)
== Series Details ==
Series: drm/i915/selftests: Guard against redifinition of SZ_8G (rev2)
URL : https://patchwork.freedesktop.org/series/85451/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a1bfe2c002d1 drm/i915/selftests: Guard against redifinition of SZ_8G
-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 8b0fac44bd1f ("sizes.h: add
SZ_8G/SZ_16G/SZ_32G macros")'
#10:
References: 8b0fac44bd1f ("sizes.h: add SZ_8G/SZ_16G/SZ_32G macros")
total: 1 errors, 0 warnings, 0 checks, 9 lines checked
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use kzalloc for allocating only one thing
== Series Details == Series: drm/i915: Use kzalloc for allocating only one thing URL : https://patchwork.freedesktop.org/series/85447/ State : success == Summary == CI Bug Log - changes from CI_DRM_9542 -> Patchwork_19250 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/index.html Known issues Here are the changes found in Patchwork_19250 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-tgl-y: NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/fi-tgl-y/igt@amdgpu/amd_ba...@query-info.html * igt@gem_exec_create@basic: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-y/igt@gem_exec_cre...@basic.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/fi-tgl-y/igt@gem_exec_cre...@basic.html Possible fixes * igt@gem_tiled_blits@basic: - fi-tgl-y: [DMESG-WARN][4] ([i915#402]) -> [PASS][5] +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-y/igt@gem_tiled_bl...@basic.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/fi-tgl-y/igt@gem_tiled_bl...@basic.html [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (40 -> 37) -- Missing(3): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9542 -> Patchwork_19250 CI-20190529: 20190529 CI_DRM_9542: 64db0a08e9841f4cbe0fa5a37feba8606802fe13 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5941: 58b135e66be4fa4db8f668fa5d125b31537cb9a6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19250: a84513135f5ac921d207d7b0c740806ee3519f5b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a84513135f5a drm/i915: Use kzalloc for allocating only one thing == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19250/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for i915: fix shift warning (rev2)
== Series Details == Series: i915: fix shift warning (rev2) URL : https://patchwork.freedesktop.org/series/85448/ State : failure == Summary == Applying: i915: fix shift warning Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Guard against redifinition of SZ_8G
In the near future, upstream will introduce a SZ_8G macro that is
slightly different to our own. Employ a temporary ifndef to avoid
compilation failure until we have backmerged.
References: 8b0fac44bd1f ("sizes.h: add SZ_8G/SZ_16G/SZ_32G macros")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_memory_region.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index a55079a061dd..75839db63bea 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -352,7 +352,9 @@ static int igt_mock_splintered_region(void *arg)
return err;
}
+#ifndef SZ_8G
#define SZ_8G BIT_ULL(33)
+#endif
static int igt_mock_max_segment(void *arg)
{
--
2.20.1
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[Intel-gfx] [PATCH] drm/i915/selftests: Guard against redifinition of SZ_8G
In the near future, upstream will introduce a SZ_8G macro that is
slightly different to our own. Employ a temporary ifndef to avoid
compilation failure until we have backmerged.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_memory_region.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index a55079a061dd..75839db63bea 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -352,7 +352,9 @@ static int igt_mock_splintered_region(void *arg)
return err;
}
+#ifndef SZ_8G
#define SZ_8G BIT_ULL(33)
+#endif
static int igt_mock_max_segment(void *arg)
{
--
2.20.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gem: Almagamate clflushes on suspend
== Series Details == Series: series starting with [1/2] drm/i915/gem: Almagamate clflushes on suspend URL : https://patchwork.freedesktop.org/series/85445/ State : success == Summary == CI Bug Log - changes from CI_DRM_9542 -> Patchwork_19249 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/index.html Known issues Here are the changes found in Patchwork_19249 that come from known issues: ### IGT changes ### Issues hit * igt@gem_linear_blits@basic: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-y/igt@gem_linear_bl...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/fi-tgl-y/igt@gem_linear_bl...@basic.html * igt@i915_selftest@live@gt_heartbeat: - fi-tgl-y: [PASS][3] -> [DMESG-FAIL][4] ([i915#2601]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html - fi-bsw-nick:[PASS][5] -> [DMESG-FAIL][6] ([i915#2675] / [i915#541]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-bsw-nick/igt@i915_selftest@live@gt_heartbeat.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/fi-bsw-nick/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@requests: - fi-ivb-3770:[PASS][7] -> [INCOMPLETE][8] ([i915#2782]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-ivb-3770/igt@i915_selftest@l...@requests.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/fi-ivb-3770/igt@i915_selftest@l...@requests.html Possible fixes * igt@gem_tiled_blits@basic: - fi-tgl-y: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-y/igt@gem_tiled_bl...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/fi-tgl-y/igt@gem_tiled_bl...@basic.html [i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601 [i915#2675]: https://gitlab.freedesktop.org/drm/intel/issues/2675 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 Participating hosts (40 -> 36) -- Missing(4): fi-cml-u2 fi-ilk-m540 fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9542 -> Patchwork_19249 CI-20190529: 20190529 CI_DRM_9542: 64db0a08e9841f4cbe0fa5a37feba8606802fe13 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5941: 58b135e66be4fa4db8f668fa5d125b31537cb9a6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19249: 644d89d97dcfd3ee52e9406c4cfc9f11bf0ed44d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 644d89d97dcf drm/i915/gem: Almagamate clflushes on freeze 6aa49b77f911 drm/i915/gem: Almagamate clflushes on suspend == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19249/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Replace open-coded intel_engine_stop_cs() (rev2)
== Series Details == Series: drm/i915/gt: Replace open-coded intel_engine_stop_cs() (rev2) URL : https://patchwork.freedesktop.org/series/84726/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9542_full -> Patchwork_19247_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19247_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19247_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19247_full: ### IGT changes ### Possible regressions * igt@sysfs_timeslice_duration@timeout@vcs0: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-skl10/igt@sysfs_timeslice_duration@time...@vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/shard-skl5/igt@sysfs_timeslice_duration@time...@vcs0.html Known issues Here are the changes found in Patchwork_19247_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-cleanup: - shard-hsw: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/shard-hsw2/igt@gem_ctx_persiste...@engines-cleanup.html * igt@gem_ctx_persistence@smoketest: - shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2896]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-tglb5/igt@gem_ctx_persiste...@smoketest.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/shard-tglb1/igt@gem_ctx_persiste...@smoketest.html * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-glk: [PASS][6] -> [FAIL][7] ([i915#2389]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-glk2/igt@gem_exec_reloc@basic-many-act...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/shard-glk9/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_exec_whisper@basic-contexts-forked: - shard-glk: [PASS][8] -> [DMESG-WARN][9] ([i915#118] / [i915#95]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-glk6/igt@gem_exec_whis...@basic-contexts-forked.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/shard-glk8/igt@gem_exec_whis...@basic-contexts-forked.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][10] -> [SKIP][11] ([i915#2190]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-tglb7/igt@gem_huc_c...@huc-copy.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@gen3_render_tiledx_blits: - shard-tglb: NOTRUN -> [SKIP][12] ([fdo#109289]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/shard-tglb2/igt@gen3_render_tiledx_blits.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1436] / [i915#716]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-skl10/igt@gen9_exec_pa...@allowed-single.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/shard-skl3/igt@gen9_exec_pa...@allowed-single.html * igt@gen9_exec_parse@unaligned-jump: - shard-tglb: NOTRUN -> [SKIP][15] ([fdo#112306]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/shard-tglb2/igt@gen9_exec_pa...@unaligned-jump.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-hsw: [PASS][16] -> [WARN][17] ([i915#1519]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-hsw4/igt@i915_pm_rc6_reside...@rc6-fence.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/shard-hsw4/igt@i915_pm_rc6_reside...@rc6-fence.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][18] -> [FAIL][19] ([i915#2574]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/shard-tglb7/igt@kms_async_fl...@test-time-stamp.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/shard-tglb6/igt@kms_async_fl...@test-time-stamp.html * igt@kms_big_fb@y-tiled-addfb-size-overflow: - shard-hsw: NOTRUN -> [SKIP][20] ([fdo#109271]) +183 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/shard-hsw2/igt@kms_big...@y-tiled-addfb-size-overflow.html * igt@kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-tglb: NOTRUN -> [SKIP][21] ([fdo#111615]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/shard-tglb2/igt@kms_big...@yf-tiled-32bpp-rotate-0.html *
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v10,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details ==
Series: series starting with [v10,1/2] drm/i915/display: Support PSR Multiple
Instances
URL : https://patchwork.freedesktop.org/series/85444/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9542 -> Patchwork_19248
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19248:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_psr@primary_mmap_gtt:
- {fi-tgl-dsi}: [SKIP][1] ([fdo#110189]) -> [SKIP][2] +3 similar
issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
Known issues
Here are the changes found in Patchwork_19248 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@memory-alloc:
- fi-tgl-y: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/fi-tgl-y/igt@amdgpu/amd_ba...@memory-alloc.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [PASS][4] -> [DMESG-FAIL][5] ([i915#2291] /
[i915#541])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][6] -> [FAIL][7] ([i915#1161] / [i915#262])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [PASS][8] -> [DMESG-WARN][9] ([i915#402]) +1 similar
issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
Possible fixes
* igt@gem_tiled_blits@basic:
- fi-tgl-y: [DMESG-WARN][10] ([i915#402]) -> [PASS][11] +1
similar issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-y/igt@gem_tiled_bl...@basic.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/fi-tgl-y/igt@gem_tiled_bl...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (40 -> 36)
--
Missing(4): fi-byt-j1900 fi-ilk-m540 fi-bsw-cyan fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9542 -> Patchwork_19248
CI-20190529: 20190529
CI_DRM_9542: 64db0a08e9841f4cbe0fa5a37feba8606802fe13 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5941: 58b135e66be4fa4db8f668fa5d125b31537cb9a6 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19248: 4d440cc839146c9b76da2b3578121395053ce9ff @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4d440cc83914 drm/i915/display: Support Multiple Transcoders' PSR status on
debugfs
5338f9b30dac drm/i915/display: Support PSR Multiple Instances
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19248/index.html
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v10,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details == Series: series starting with [v10,1/2] drm/i915/display: Support PSR Multiple Instances URL : https://patchwork.freedesktop.org/series/85444/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1326:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:869:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v10,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details == Series: series starting with [v10,1/2] drm/i915/display: Support PSR Multiple Instances URL : https://patchwork.freedesktop.org/series/85444/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5338f9b30dac drm/i915/display: Support PSR Multiple Instances -:1715: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible side-effects? #1715: FILE: drivers/gpu/drm/i915/display/intel_psr.h:21: +#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && intel_dp->psr.sink_support) total: 0 errors, 0 warnings, 1 checks, 1737 lines checked 4d440cc83914 drm/i915/display: Support Multiple Transcoders' PSR status on debugfs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] [v2] i915: fix shift warning
From: Arnd Bergmann
Randconfig builds on 32-bit machines show lots of warnings for
the i915 driver for passing a 32-bit value into __const_hweight64():
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2584:9: error: shift count >=
width of type [-Werror,-Wshift-count-overflow]
return hweight64(VDBOX_MASK(>gt));
^~~~
include/asm-generic/bitops/const_hweight.h:29:49: note: expanded from macro
'hweight64'
#define hweight64(w) (__builtin_constant_p(w) ? __const_hweight64(w) :
__arch_hweight64(w))
Change it to hweight_long() to avoid the warning.
Signed-off-by: Arnd Bergmann
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index bcc80f428172..43164a0b0023 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2581,7 +2581,7 @@ static int eb_submit(struct i915_execbuffer *eb, struct
i915_vma *batch)
static int num_vcs_engines(const struct drm_i915_private *i915)
{
- return hweight64(VDBOX_MASK(>gt));
+ return hweight_long(VDBOX_MASK(>gt));
}
/*
--
2.29.2
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[Intel-gfx] [PATCH -next] drm/i915: Use kzalloc for allocating only one thing
Use kzalloc rather than kcalloc(1,...)
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
//
@@
@@
- kcalloc(1,
+ kzalloc(
...)
//
Signed-off-by: Zheng Yongjun
---
drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index f88473d396f4..6994b167d0c8 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -415,7 +415,7 @@ static int igt_evict_contexts(void *arg)
struct reserved *r;
mutex_unlock(>vm.mutex);
- r = kcalloc(1, sizeof(*r), GFP_KERNEL);
+ r = kzalloc(sizeof(*r), GFP_KERNEL);
mutex_lock(>vm.mutex);
if (!r) {
err = -ENOMEM;
--
2.22.0
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[Intel-gfx] [PATCH] i915: fix shift warning
From: Arnd Bergmann Randconfig builds on 32-bit machines show lots of warnings for the i915 driver for incorrect bit masks like: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2584:9: error: shift count >= width of type [-Werror,-Wshift-count-overflow] return hweight64(VDBOX_MASK(>gt)); ^~~~ include/asm-generic/bitops/const_hweight.h:29:49: note: expanded from macro 'hweight64' #define hweight64(w) (__builtin_constant_p(w) ? __const_hweight64(w) : __arch_hweight64(w)) Since this is a 64-bit mask, use GENMASK_ULL instead of GENMASK. Signed-off-by: Arnd Bergmann --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0a3ee4f9dc0a..ca32fa0d6a57 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1624,7 +1624,7 @@ tgl_revids_get(struct drm_i915_private *dev_priv) unsigned int first__ = (first); \ unsigned int count__ = (count); \ ((gt)->info.engine_mask & \ -GENMASK(first__ + count__ - 1, first__)) >> first__; \ +GENMASK_ULL(first__ + count__ - 1, first__)) >> first__; \ }) #define VDBOX_MASK(gt) \ ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) -- 2.29.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] i915: fix shift warning
On Wed, Dec 30, 2020 at 4:56 PM Chris Wilson wrote:
>
> Quoting Arnd Bergmann (2020-12-30 15:39:14)
> > From: Arnd Bergmann
> >
> > Randconfig builds on 32-bit machines show lots of warnings for
> > the i915 driver for incorrect bit masks like:
>
> mask is a u8.
>
> VCS0 is 2, I915_MAX_VCS 4
>
> (u8 & GENMASK(5, 2)) >> 2
Ah right, I misread the warning then.
> > drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2584:9: error: shift count
> > >= width of type [-Werror,-Wshift-count-overflow]
> > return hweight64(VDBOX_MASK(>gt));
> >^~~~
> > include/asm-generic/bitops/const_hweight.h:29:49: note: expanded from macro
> > 'hweight64'
> > #define hweight64(w) (__builtin_constant_p(w) ? __const_hweight64(w) :
> > __arch_hweight64(w))
>
> So it's upset by hweight64() on the unsigned long?
I suspect what is going on is that clang once again warns because it performs
more code checks before dead-code elimination than gcc does. The warning is
for the __const_hweight64() case, which is not actually used here because the
input is not a compile-time constant.
> So hweight_long?
That seems to work, I'll send a new version with that.
> Or use a cast, hweight8((intel_engine_mask_t)VDMASK())?
>
> static __always_inline int engine_count(intel_engine_mask_t mask)
> {
> return sizeof(mask) == 1 ? hweight8(mask) :
> sizeof(mask) == 2 ? hweight16(mask) :
> sizeof(mask) == 4 ? hweight32(mask) :
> hweight64(mask);
> }
Fine with me as well. If you prefer that way, I'll let you handle that.
Arnd
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/6] drm/i915/selftests: Set error returns
== Series Details ==
Series: series starting with [1/6] drm/i915/selftests: Set error returns
URL : https://patchwork.freedesktop.org/series/85440/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9541_full -> Patchwork_19245_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19245_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19245_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19245_full:
### IGT changes ###
Possible regressions
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/shard-tglb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-indfb-plflip-blt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/shard-tglb3/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-indfb-plflip-blt.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_spin_batch@user-each}:
- shard-apl: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/shard-apl1/igt@gem_spin_ba...@user-each.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/shard-apl2/igt@gem_spin_ba...@user-each.html
Known issues
Here are the changes found in Patchwork_19245_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@legacy-engines-cleanup:
- shard-hsw: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +6
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/shard-hsw2/igt@gem_ctx_persiste...@legacy-engines-cleanup.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [PASS][6] -> [INCOMPLETE][7] ([i915#2369])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/shard-skl9/igt@gem_exec_capture@p...@rcs0.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/shard-skl8/igt@gem_exec_capture@p...@rcs0.html
* igt@gem_exec_reloc@basic-many-active@vcs0:
- shard-hsw: NOTRUN -> [FAIL][8] ([i915#2389]) +3 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/shard-hsw2/igt@gem_exec_reloc@basic-many-act...@vcs0.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#454])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/shard-iclb3/igt@i915_pm...@dc6-psr.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/shard-iclb8/igt@i915_pm...@dc6-psr.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271]) +23 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/shard-snb2/igt@i915_pm_...@system-suspend-execbuf.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [PASS][12] -> [FAIL][13] ([i915#2521])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/shard-skl4/igt@kms_async_fl...@alternate-sync-async-flip.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/shard-skl5/igt@kms_async_fl...@alternate-sync-async-flip.html
* igt@kms_chamelium@dp-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/shard-skl3/igt@kms_chamel...@dp-crc-multiple.html
- shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/shard-snb2/igt@kms_chamel...@dp-crc-multiple.html
* igt@kms_chamelium@vga-hpd-with-enabled-mode:
- shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +1
similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/shard-kbl4/igt@kms_chamel...@vga-hpd-with-enabled-mode.html
* igt@kms_color@pipe-a-ctm-red-to-blue:
- shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/shard-skl1/igt@kms_co...@pipe-a-ctm-red-to-blue.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/shard-skl6/igt@kms_co...@pipe-a-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-b-ctm-green-to-red:
- shard-hsw: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827])
+19 similar issues
[19]:
Re: [Intel-gfx] [PATCH] drm/i915/dp: Remove aux xfer timeout debug message
Quoting Souza, Jose (2021-01-04 14:50:59)
> On Thu, 2020-12-31 at 09:17 +, Chris Wilson wrote:
> > Quoting Almahallawy, Khaled (2020-12-31 01:24:34)
> > > On Wed, 2020-12-30 at 16:02 -0800, Matt Roper wrote:
> > > > On Wed, Dec 30, 2020 at 10:37:42AM +, Chris Wilson wrote:
> > > > > The timeouts are frequent and expected. We will complain if we
> > > > > retry so
> > > > > often as to lose patience and give up, so the cacophony from
> > > > > individual
> > > > > complaints is redundant.
> > > > >
> > > > > Signed-off-by: Chris Wilson
> > > >
> > > > Reviewed-by: Matt Roper
> > > >
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_dp.c | 2 --
> > > > > 1 file changed, 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > index 8ae769b18879..704e4cebf7f3 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > @@ -1613,8 +1613,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> > > > > /* Timeouts occur when the device isn't connected, so they're
> > > > > * "normal" -- don't fill the kernel log with these */
> > > > > if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
> > > > > - drm_dbg_kms(>drm, "%s: timeout (status
> > > > > 0x%08x)\n",
> > > > > - intel_dp->aux.name, status);
> > >
> > > AUX timeout logs are very important for TGL TCSS Display debugging. We
> > > actually can get AUX timeout when the display is connected for the
> > > following reasons:
> > > * If AUX orientation is not configured correctly in BIOS
> > > * If USB3 dock is downgraded to USB2 and SBU/AUX lines are disabled
> > > * When LTTPR/Retimer started to act funny and not configured correctly
> > > by EC
> > > * When we have a bug in the PMC mux configuration because of bug in the
> > > following files: drivers/usb/typec/mux/intel_pmc_mux.c and
> > > drivers/platform/x86/intel_scu_ipc.c
> > > * When user space is not cleanly disconnected all MST connectors for
> > > disconnected MST hub with 2+ display. We will be left with enabled
> > > pipes although the cable is disconnected and next connect of type-c
> > > display will give aux timeout:
> > > ** User space fix in Chrome:
> > > https://chromium-review.googlesource.com/c/chromium/src/+/2512550/
> > > ** WA in driver: https://patchwork.freedesktop.org/patch/395901/
> > >
> > > These logs are especially important for Chrome based platforms with
> > > type-C. Seeing these logs we can know who is screwing up (TCSS driver,
> > > CB, or EC).
> >
> > Then capture the information you require to analyse your failures.
> > Flooding the debug log makes debugging everything else much, much harder.
> > -Chris
>
> I agree with Khaled this message is helpful to debug why display is not
> coming up.
Isn't that the case where it falls through to the later timeout warning?
If there's some information in there to explain a display failure, can
it be extracted automatically? Or to turn the table around, if it is so
useful to debug failures, why do we still see it in CI?
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Replace open-coded intel_engine_stop_cs() (rev2)
== Series Details == Series: drm/i915/gt: Replace open-coded intel_engine_stop_cs() (rev2) URL : https://patchwork.freedesktop.org/series/84726/ State : success == Summary == CI Bug Log - changes from CI_DRM_9542 -> Patchwork_19247 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/index.html Known issues Here are the changes found in Patchwork_19247 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@memory-alloc: - fi-tgl-y: NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/fi-tgl-y/igt@amdgpu/amd_ba...@memory-alloc.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html Possible fixes * igt@gem_tiled_blits@basic: - fi-tgl-y: [DMESG-WARN][4] ([i915#402]) -> [PASS][5] +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-y/igt@gem_tiled_bl...@basic.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/fi-tgl-y/igt@gem_tiled_bl...@basic.html [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (40 -> 37) -- Missing(3): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9542 -> Patchwork_19247 CI-20190529: 20190529 CI_DRM_9542: 64db0a08e9841f4cbe0fa5a37feba8606802fe13 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5941: 58b135e66be4fa4db8f668fa5d125b31537cb9a6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19247: 7254e1abeb33c17538e0852b502ced81f74995db @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7254e1abeb33 drm/i915/gt: Replace open-coded intel_engine_stop_cs() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19247/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/dp: Remove aux xfer timeout debug message
On Thu, 2020-12-31 at 09:17 +, Chris Wilson wrote:
> Quoting Almahallawy, Khaled (2020-12-31 01:24:34)
> > On Wed, 2020-12-30 at 16:02 -0800, Matt Roper wrote:
> > > On Wed, Dec 30, 2020 at 10:37:42AM +, Chris Wilson wrote:
> > > > The timeouts are frequent and expected. We will complain if we
> > > > retry so
> > > > often as to lose patience and give up, so the cacophony from
> > > > individual
> > > > complaints is redundant.
> > > >
> > > > Signed-off-by: Chris Wilson
> > >
> > > Reviewed-by: Matt Roper
> > >
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 2 --
> > > > 1 file changed, 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 8ae769b18879..704e4cebf7f3 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -1613,8 +1613,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> > > > /* Timeouts occur when the device isn't connected, so they're
> > > > * "normal" -- don't fill the kernel log with these */
> > > > if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
> > > > - drm_dbg_kms(>drm, "%s: timeout (status
> > > > 0x%08x)\n",
> > > > - intel_dp->aux.name, status);
> >
> > AUX timeout logs are very important for TGL TCSS Display debugging. We
> > actually can get AUX timeout when the display is connected for the
> > following reasons:
> > * If AUX orientation is not configured correctly in BIOS
> > * If USB3 dock is downgraded to USB2 and SBU/AUX lines are disabled
> > * When LTTPR/Retimer started to act funny and not configured correctly
> > by EC
> > * When we have a bug in the PMC mux configuration because of bug in the
> > following files: drivers/usb/typec/mux/intel_pmc_mux.c and
> > drivers/platform/x86/intel_scu_ipc.c
> > * When user space is not cleanly disconnected all MST connectors for
> > disconnected MST hub with 2+ display. We will be left with enabled
> > pipes although the cable is disconnected and next connect of type-c
> > display will give aux timeout:
> > ** User space fix in Chrome:
> > https://chromium-review.googlesource.com/c/chromium/src/+/2512550/
> > ** WA in driver: https://patchwork.freedesktop.org/patch/395901/
> >
> > These logs are especially important for Chrome based platforms with
> > type-C. Seeing these logs we can know who is screwing up (TCSS driver,
> > CB, or EC).
>
> Then capture the information you require to analyse your failures.
> Flooding the debug log makes debugging everything else much, much harder.
> -Chris
I agree with Khaled this message is helpful to debug why display is not coming
up.
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Re: [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power sequencer from intel_dp.c
On Mon, 28 Dec 2020, "Gupta, Anshuman" wrote: >> -Original Message- >> From: Intel-gfx On Behalf Of Jani >> Nikula >> Sent: Tuesday, December 22, 2020 8:20 PM >> To: intel-gfx@lists.freedesktop.org >> Cc: Nikula, Jani >> Subject: [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power >> sequencer from intel_dp.c >> >> In a long overdue refactoring, split out all panel sequencer code from >> intel_dp.c to new intel_pps.[ch]. >> >> The first part is mostly just code movement as-is, without cleanups. >> >> We need to add a vlv_get_dpll() helper to get at the vlv/chv dpll from >> pps code. > IMHO functions intel_dp_init_panel_power_sequencer, > intel_dp_init_panel_power_sequencer_registers, > intel_dp_pps_init suits a intel_edp_* prefix. This patch just moves code. The rename would be a separate change on top. Possibly with intel_pps prefix instead because they're not so much about dp or edp as about pps. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915/gt: Rearrange snb workarounds
== Series Details == Series: series starting with [CI,1/2] drm/i915/gt: Rearrange snb workarounds URL : https://patchwork.freedesktop.org/series/85439/ State : success == Summary == CI Bug Log - changes from CI_DRM_9541_full -> Patchwork_19244_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19244_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#2369] / [i915#2502]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/shard-skl9/igt@gem_exec_capture@p...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/shard-skl6/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_endless@dispatch@bcs0: - shard-tglb: [PASS][3] -> [INCOMPLETE][4] ([i915#2270]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/shard-tglb2/igt@gem_exec_endless@dispa...@bcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/shard-tglb2/igt@gem_exec_endless@dispa...@bcs0.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][5] -> [SKIP][6] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/shard-tglb3/igt@gem_huc_c...@huc-copy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271]) +23 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/shard-snb2/igt@i915_pm_...@system-suspend-execbuf.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][8] -> [FAIL][9] ([i915#2521]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/shard-skl4/igt@kms_async_fl...@alternate-sync-async-flip.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/shard-skl2/igt@kms_async_fl...@alternate-sync-async-flip.html * igt@kms_ccs@pipe-c-bad-rotation-90: - shard-skl: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111304]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/shard-skl6/igt@kms_...@pipe-c-bad-rotation-90.html * igt@kms_chamelium@dp-crc-multiple: - shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/shard-skl4/igt@kms_chamel...@dp-crc-multiple.html - shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/shard-snb2/igt@kms_chamel...@dp-crc-multiple.html * igt@kms_chamelium@vga-hpd-with-enabled-mode: - shard-kbl: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/shard-kbl4/igt@kms_chamel...@vga-hpd-with-enabled-mode.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding: - shard-skl: [PASS][14] -> [FAIL][15] ([i915#54]) +6 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/shard-skl3/igt@kms_cursor_...@pipe-a-cursor-128x42-sliding.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/shard-skl3/igt@kms_cursor_...@pipe-a-cursor-128x42-sliding.html * igt@kms_cursor_crc@pipe-c-cursor-64x21-random: - shard-skl: NOTRUN -> [FAIL][16] ([i915#54]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-64x21-random.html * igt@kms_cursor_crc@pipe-d-cursor-suspend: - shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271]) +31 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/shard-kbl4/igt@kms_cursor_...@pipe-d-cursor-suspend.html * igt@kms_cursor_edge_walk@pipe-a-64x64-right-edge: - shard-skl: [PASS][18] -> [DMESG-WARN][19] ([i915#1982]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/shard-skl8/igt@kms_cursor_edge_w...@pipe-a-64x64-right-edge.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/shard-skl1/igt@kms_cursor_edge_w...@pipe-a-64x64-right-edge.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: [PASS][20] -> [FAIL][21] ([i915#2346] / [i915#533]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/shard-skl7/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/shard-skl8/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy: - shard-skl: [PASS][22] -> [FAIL][23] ([i915#2346]) [22]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Replace open-coded intel_engine_stop_cs() (rev2)
== Series Details == Series: drm/i915/gt: Replace open-coded intel_engine_stop_cs() (rev2) URL : https://patchwork.freedesktop.org/series/84726/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7254e1abeb33 drm/i915/gt: Replace open-coded intel_engine_stop_cs() -:32: ERROR:SPACING: spaces required around that '!=' (ctx:VxE) #32: FILE: drivers/gpu/drm/i915/gt/intel_engine_cs.c:1061: + if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR)!= ^ total: 1 errors, 0 warnings, 0 checks, 52 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v10,1/5] drm: Add function to convert rect in 16.16 fixed format to regular format
== Series Details == Series: series starting with [v10,1/5] drm: Add function to convert rect in 16.16 fixed format to regular format URL : https://patchwork.freedesktop.org/series/85441/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9542 -> Patchwork_19246 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19246 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19246, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19246/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19246: ### IGT changes ### Possible regressions * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-y: [PASS][1] -> [FAIL][2] +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-y/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19246/fi-tgl-y/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-tgl-u2: [PASS][3] -> [FAIL][4] +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19246/fi-tgl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html Warnings * igt@i915_hangman@error-state-basic: - fi-apl-guc: [DMESG-WARN][5] ([i915#1610]) -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-apl-guc/igt@i915_hang...@error-state-basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19246/fi-apl-guc/igt@i915_hang...@error-state-basic.html Known issues Here are the changes found in Patchwork_19246 that come from known issues: ### IGT changes ### Issues hit * igt@gem_sync@basic-all: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-y/igt@gem_s...@basic-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19246/fi-tgl-y/igt@gem_s...@basic-all.html * igt@i915_selftest@live@gt_heartbeat: - fi-bwr-2160:[PASS][9] -> [DMESG-FAIL][10] ([i915#541]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-bwr-2160/igt@i915_selftest@live@gt_heartbeat.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19246/fi-bwr-2160/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@sanitycheck: - fi-kbl-7500u: [PASS][11] -> [DMESG-WARN][12] ([i915#2605]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19246/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html Possible fixes * igt@gem_tiled_blits@basic: - fi-tgl-y: [DMESG-WARN][13] ([i915#402]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9542/fi-tgl-y/igt@gem_tiled_bl...@basic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19246/fi-tgl-y/igt@gem_tiled_bl...@basic.html [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 Participating hosts (40 -> 37) -- Missing(3): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9542 -> Patchwork_19246 CI-20190529: 20190529 CI_DRM_9542: 64db0a08e9841f4cbe0fa5a37feba8606802fe13 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5941: 58b135e66be4fa4db8f668fa5d125b31537cb9a6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19246: 3a68f5ff2ea35a9f0eea45f43397317d86619a6e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3a68f5ff2ea3 HAX/DO_NOT_MERGE_IT: drm/i915/display: Enable PSR2 selective fetch for testing d6a27d3fbaa4 drm/i915/display/psr: Program plane's calculated offset to plane SF register c27edb13e307 drm/i915/display: Split and export main surface calculation from skl_check_main_surface() 0529801de161 drm/i915/display/psr: Use plane damage clips to calculate damaged area 7bbcec5fd7ea drm: Add function to convert rect in 16.16 fixed format to regular format == Logs == For more details see:
[Intel-gfx] [PATCH 1/2] drm/i915/gem: Almagamate clflushes on suspend
When flushing objects larger than the CPU cache it is preferrable to use
a single wbinvd() rather than overlapping clflush(). At runtime, we
avoid wbinvd() due to its system-wide latencies, but during
singlethreaded suspend, no one will observe the imposed latency and we
can opt for the faster wbinvd to clear all objects in a single hit.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 34 ++
1 file changed, 7 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 40d3e40500fa..6f9bba1ba20e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -32,13 +32,6 @@ void i915_gem_suspend(struct drm_i915_private *i915)
i915_gem_drain_freed_objects(i915);
}
-static struct drm_i915_gem_object *first_mm_object(struct list_head *list)
-{
- return list_first_entry_or_null(list,
- struct drm_i915_gem_object,
- mm.link);
-}
-
void i915_gem_suspend_late(struct drm_i915_private *i915)
{
struct drm_i915_gem_object *obj;
@@ -48,6 +41,7 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
NULL
}, **phase;
unsigned long flags;
+ bool flush = false;
/*
* Neither the BIOS, ourselves or any other kernel
@@ -73,29 +67,15 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
spin_lock_irqsave(>mm.obj_lock, flags);
for (phase = phases; *phase; phase++) {
- LIST_HEAD(keep);
-
- while ((obj = first_mm_object(*phase))) {
- list_move_tail(>mm.link, );
-
- /* Beware the background _i915_gem_free_objects */
- if (!kref_get_unless_zero(>base.refcount))
- continue;
-
- spin_unlock_irqrestore(>mm.obj_lock, flags);
-
- i915_gem_object_lock(obj, NULL);
- drm_WARN_ON(>drm,
- i915_gem_object_set_to_gtt_domain(obj, false));
- i915_gem_object_unlock(obj);
- i915_gem_object_put(obj);
-
- spin_lock_irqsave(>mm.obj_lock, flags);
+ list_for_each_entry(obj, *phase, mm.link) {
+ if (!(obj->cache_coherent &
I915_BO_CACHE_COHERENT_FOR_READ))
+ flush |= (obj->read_domains &
I915_GEM_DOMAIN_CPU) == 0;
+ __start_cpu_write(obj); /* presume auto-hibernate */
}
-
- list_splice_tail(, *phase);
}
spin_unlock_irqrestore(>mm.obj_lock, flags);
+ if (flush)
+ wbinvd_on_all_cpus();
}
void i915_gem_resume(struct drm_i915_private *i915)
--
2.20.1
___
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[Intel-gfx] [PATCH 2/2] drm/i915/gem: Almagamate clflushes on freeze
When flushing objects larger than the CPU cache it is preferrable to use
a single wbinvd() rather than overlapping clflush(). At runtime, we
avoid wbinvd() due to its system-wide latencies, but during
singlethreaded suspend, no one will observe the imposed latency and we
can opt for the faster wbinvd to clear all objects in a single hit.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 16 +---
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 17a4636ee542..21194ebfc31e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1277,19 +1277,13 @@ int i915_gem_freeze_late(struct drm_i915_private *i915)
* the objects as well, see i915_gem_freeze()
*/
- wakeref = intel_runtime_pm_get(>runtime_pm);
-
- i915_gem_shrink(i915, -1UL, NULL, ~0);
+ with_intel_runtime_pm(>runtime_pm, wakeref)
+ i915_gem_shrink(i915, -1UL, NULL, ~0);
i915_gem_drain_freed_objects(i915);
- list_for_each_entry(obj, >mm.shrink_list, mm.link) {
- i915_gem_object_lock(obj, NULL);
- drm_WARN_ON(>drm,
- i915_gem_object_set_to_cpu_domain(obj, true));
- i915_gem_object_unlock(obj);
- }
-
- intel_runtime_pm_put(>runtime_pm, wakeref);
+ wbinvd_on_all_cpus();
+ list_for_each_entry(obj, >mm.shrink_list, mm.link)
+ __start_cpu_write(obj);
return 0;
}
--
2.20.1
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v10,1/5] drm: Add function to convert rect in 16.16 fixed format to regular format
== Series Details == Series: series starting with [v10,1/5] drm: Add function to convert rect in 16.16 fixed format to regular format URL : https://patchwork.freedesktop.org/series/85441/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed:
[Intel-gfx] [PATCH v10 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.
v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
permissions '0444'
v5: Addressed JJani Nikula's review comments
- Remove checking of Gen12 for i915_psr_status.
- Add check of HAS_PSR()
- Remove meaningless check routine.
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
Cc: Jani Nikula
Cc: Anshuman Gupta
Reviewed-by: Anshuman Gupta
---
.../gpu/drm/i915/display/intel_display_debugfs.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 041053167d7f..d2dd61c4ee0b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2224,6 +2224,16 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
+static int i915_psr_status_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct intel_dp *intel_dp =
+ intel_attached_dp(to_intel_connector(connector));
+
+ return intel_psr_status(m, intel_dp);
+}
+DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
+
#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
seq_puts(m, "LPSP: incapable\n"))
@@ -2399,6 +2409,12 @@ int intel_connector_debugfs_add(struct drm_connector
*connector)
connector, _psr_sink_status_fops);
}
+ if (HAS_PSR(dev_priv) &&
+ connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ debugfs_create_file("i915_psr_status", 0444, root,
+ connector, _psr_status_fops);
+ }
+
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
--
2.25.0
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[Intel-gfx] [PATCH v10 1/2] drm/i915/display: Support PSR Multiple Instances
It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt handling routine for supporting
multiple transcoders. But it does not change the scenario and timing of
enabling and disabling PSR. And it not support multiple pipes with
a single transcoder PSR case yet.
v2: Fix indentation and add comments
v3: Remove Blank line
v4: Rebased
v5: Rebased and Addressed Anshuman's review comment.
- Move calling of intel_psr_init() to intel_dp_init_connector()
v6: Address Anshuman's review comments
- Remove wrong comments and add comments for a limit of supporting of
a single pipe PSR
v7: Update intel_psr_compute_config() for supporting multiple transcoder
PSR on BDW+
v8: Address Anshuman's review comments
- Replace DRM_DEBUG_KMS with drm_dbg_kms() / DRM_WARN with drm_warn()
v9: Fix commit message
v10: Rebased
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
Cc: Juha-Pekka Heikkila
Cc: Anshuman Gupta
Reviewed-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
drivers/gpu/drm/i915/display/intel_display.c | 4 -
.../drm/i915/display/intel_display_debugfs.c | 111 ++--
.../drm/i915/display/intel_display_types.h| 38 ++
drivers/gpu/drm/i915/display/intel_dp.c | 23 +-
drivers/gpu/drm/i915/display/intel_psr.c | 576 ++
drivers/gpu/drm/i915/display/intel_psr.h | 14 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 38 --
drivers/gpu/drm/i915/i915_irq.c | 49 +-
10 files changed, 485 insertions(+), 377 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 17eaa56c5a99..ae78167013d1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4324,7 +4324,10 @@ static void intel_ddi_update_pipe_dp(struct
intel_atomic_state *state,
intel_ddi_set_dp_msa(crtc_state, conn_state);
+ //TODO: move PSR related functions into intel_psr_update()
+ intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
intel_psr_update(intel_dp, crtc_state, conn_state);
+
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_update(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f2c48e5cdb43..c857489f2ccd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14821,8 +14821,6 @@ static void commit_pipe_config(struct
intel_atomic_state *state,
if (new_crtc_state->update_pipe)
intel_pipe_fastset(old_crtc_state, new_crtc_state);
-
- intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
}
if (dev_priv->display.atomic_update_watermarks)
@@ -16348,8 +16346,6 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_dvo_init(dev_priv);
}
- intel_psr_init(dev_priv);
-
for_each_intel_encoder(_priv->drm, encoder) {
encoder->base.possible_crtcs =
intel_encoder_possible_crtcs(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cd7e5519ee7d..041053167d7f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -249,18 +249,17 @@ static int i915_psr_sink_status_show(struct seq_file *m,
void *data)
"sink internal error",
};
struct drm_connector *connector = m->private;
- struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
int ret;
- if (!CAN_PSR(dev_priv)) {
- seq_puts(m, "PSR Unsupported\n");
+ if (connector->status != connector_status_connected)
return -ENODEV;
- }
- if (connector->status != connector_status_connected)
+ if (!CAN_PSR(intel_dp)) {
+ seq_puts(m, "PSR Unsupported\n");
return -ENODEV;
+ }
ret = drm_dp_dpcd_readb(_dp->aux, DP_PSR_STATUS, );
@@ -280,12 +279,13 @@ static int i915_psr_sink_status_show(struct seq_file *m,
void *data)
DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
static void
-psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
+psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
{
u32 val, status_val;
const char *status = "unknown";
+ struct drm_i915_private
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/selftests: Set error returns
== Series Details == Series: series starting with [1/6] drm/i915/selftests: Set error returns URL : https://patchwork.freedesktop.org/series/85440/ State : success == Summary == CI Bug Log - changes from CI_DRM_9541 -> Patchwork_19245 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/index.html Known issues Here are the changes found in Patchwork_19245 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-tgl-y: NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/fi-tgl-y/igt@amdgpu/amd_ba...@query-info.html * igt@gem_render_tiled_blits@basic: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html * igt@i915_selftest@live@execlists: - fi-tgl-u2: [PASS][4] -> [INCOMPLETE][5] ([i915#2268]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/fi-tgl-u2/igt@i915_selftest@l...@execlists.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/fi-tgl-u2/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gem_contexts: - fi-bsw-kefka: [PASS][6] -> [INCOMPLETE][7] ([i915#2369]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html * igt@i915_selftest@live@hugepages: - fi-bsw-kefka: [PASS][8] -> [DMESG-WARN][9] ([i915#2826]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/fi-bsw-kefka/igt@i915_selftest@l...@hugepages.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/fi-bsw-kefka/igt@i915_selftest@l...@hugepages.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7500u: [PASS][10] -> [DMESG-FAIL][11] ([i915#165]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html * igt@runner@aborted: - fi-bsw-kefka: NOTRUN -> [FAIL][12] ([i915#1436]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/fi-bsw-kefka/igt@run...@aborted.html Possible fixes * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [DMESG-WARN][13] ([i915#402]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#2268]: https://gitlab.freedesktop.org/drm/intel/issues/2268 [i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2826]: https://gitlab.freedesktop.org/drm/intel/issues/2826 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (39 -> 36) -- Missing(3): fi-cml-u2 fi-ilk-m540 fi-bsw-cyan Build changes - * Linux: CI_DRM_9541 -> Patchwork_19245 CI-20190529: 20190529 CI_DRM_9541: e8f34fa9c86e87ec32f92ec9b615e468928233f4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5941: 58b135e66be4fa4db8f668fa5d125b31537cb9a6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19245: c04ace8141415d169345b2ef447d70246c95f6e3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c04ace814141 drm/i915/gt: Remove timeslice suppression f4334c245caa drm/i915/gt: Restore ce->signal flush before releasing virtual engine a09becee5f16 drm/i915/gt: Check the virtual still matches upon locking 64dc3f4f54bb drm/i915/gt: Allow failed resets without assertion ad716358ae5b drm/i915: Set rawclk earlier during mmio probe a79946cc2df2 drm/i915/selftests: Set error returns == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19245/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915/selftests: Set error returns
== Series Details ==
Series: series starting with [1/6] drm/i915/selftests: Set error returns
URL : https://patchwork.freedesktop.org/series/85440/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a79946cc2df2 drm/i915/selftests: Set error returns
ad716358ae5b drm/i915: Set rawclk earlier during mmio probe
64dc3f4f54bb drm/i915/gt: Allow failed resets without assertion
a09becee5f16 drm/i915/gt: Check the virtual still matches upon locking
f4334c245caa drm/i915/gt: Restore ce->signal flush before releasing virtual
engine
-:14: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit bab0557c8dca ("drm/i915/gt:
Remove virtual breadcrumb before transfer")'
#14:
bab0557c8dca ("drm/i915/gt: Remove virtual breadcrumb before transfer"),
total: 1 errors, 0 warnings, 0 checks, 25 lines checked
c04ace814141 drm/i915/gt: Remove timeslice suppression
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/gt: Rearrange snb workarounds
== Series Details == Series: series starting with [CI,1/2] drm/i915/gt: Rearrange snb workarounds URL : https://patchwork.freedesktop.org/series/85439/ State : success == Summary == CI Bug Log - changes from CI_DRM_9541 -> Patchwork_19244 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/index.html Known issues Here are the changes found in Patchwork_19244 that come from known issues: ### IGT changes ### Issues hit * igt@gem_linear_blits@basic: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/fi-tgl-y/igt@gem_linear_bl...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/fi-tgl-y/igt@gem_linear_bl...@basic.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#2203]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_frontbuffer_tracking@basic: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/fi-tgl-y/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/fi-tgl-y/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@gem_flink_basic@bad-flink: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9541/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (39 -> 36) -- Missing(3): fi-byt-j1900 fi-ilk-m540 fi-bsw-cyan Build changes - * Linux: CI_DRM_9541 -> Patchwork_19244 CI-20190529: 20190529 CI_DRM_9541: e8f34fa9c86e87ec32f92ec9b615e468928233f4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5941: 58b135e66be4fa4db8f668fa5d125b31537cb9a6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19244: a0c0727d1918876ae5a6f8fa4cd882f5e5b5bf92 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a0c0727d1918 drm/i915/gt: Rearrange hsw workarounds 40fb092ba005 drm/i915/gt: Rearrange snb workarounds == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19244/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gt: Replace open-coded intel_engine_stop_cs()
In the legacy ringbuffer submission, we still had an open-coded version
of intel_engine_stop_cs() with one addition verification step. Transfer
that verification to intel_engine_stop_cs() itself, and call it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 15 +--
.../gpu/drm/i915/gt/intel_ring_submission.c | 25 +--
2 files changed, 14 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index b1b44afc94ba..dcba59b53fde 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1023,8 +1023,19 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
ENGINE_TRACE(engine, "\n");
if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
- ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n");
- err = -ETIMEDOUT;
+ ENGINE_TRACE(engine,
+"timed out on STOP_RING -> IDLE; HEAD:%04x,
TAIL:%04x\n",
+ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR,
+ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR);
+
+ /*
+* Sometimes we observe that the idle flag is not
+* set even though the ring is empty. So double
+* check before giving up.
+*/
+ if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR)!=
+ (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR))
+ err = -ETIMEDOUT;
}
return err;
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 32b7d74c24e8..ac67d1b61b5e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -159,30 +159,7 @@ static void ring_setup_status_page(struct intel_engine_cs
*engine)
static bool stop_ring(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
-
- if (INTEL_GEN(dev_priv) > 2) {
- ENGINE_WRITE(engine,
-RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING));
- if (intel_wait_for_register(engine->uncore,
- RING_MI_MODE(engine->mmio_base),
- MODE_IDLE,
- MODE_IDLE,
- 1000)) {
- drm_err(_priv->drm,
- "%s : timed out trying to stop ring\n",
- engine->name);
-
- /*
-* Sometimes we observe that the idle flag is not
-* set even though the ring is empty. So double
-* check before giving up.
-*/
- if (ENGINE_READ(engine, RING_HEAD) !=
- ENGINE_READ(engine, RING_TAIL))
- return false;
- }
- }
+ intel_engine_stop_cs(engine);
ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL));
--
2.20.1
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[Intel-gfx] [PATCH v10 2/5] drm/i915/display/psr: Use plane damage clips to calculate damaged area
From: José Roberto de Souza
Now using plane damage clips property to calcualte the damaged area.
Selective fetch only supports one region to be fetched so software
needs to calculate a bounding box around all damage clips.
Now that we are not complete fetching each plane, there is another
loop needed as all the plane areas that intersect with the pipe
damaged area needs to be fetched from memory so the complete blending
of all planes can happen.
v2:
- do not shifting new_plane_state->uapi.dst only src is in 16.16 format
v4:
- setting plane selective fetch area using the whole pipe damage area
- mark the whole plane area damaged if plane visibility or alpha
changed
v5:
- taking in consideration src.y1 in the damage coordinates
- adding to the pipe damaged area planes that were visible but are
invisible in the new state
v6:
- consider old state plane coordinates when visibility changes or it
moved to calculate damaged area
- remove from damaged area the portion not in src clip
v7:
- intersec every damage clip with src to minimize damaged area
v8:
- adjust pipe_damaged area to 4 lines grouping
- adjust calculation now that is understood that uapi.src is the
framebuffer coordinates that plane will start to fetch from
v9:
- Only add plane dst or src to damaged_area if visible
- Early skip plane damage calculation if it was not visible in old and
new state
Cc: Ville Syrjälä
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
Reviewed-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_psr.c | 113 ---
1 file changed, 99 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index d9a395c486d3..f5b9519b3756 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1242,9 +1242,11 @@ static void psr2_man_trk_ctl_calc(struct
intel_crtc_state *crtc_state,
if (clip->y1 == -1)
goto exit;
+ drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
+
val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
- val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(DIV_ROUND_UP(clip->y2, 4) +
1);
+ val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
exit:
crtc_state->psr2_man_track_ctl = val;
}
@@ -1269,8 +1271,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state
*state,
struct intel_crtc *crtc)
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 =
-1 };
struct intel_plane_state *new_plane_state, *old_plane_state;
- struct drm_rect pipe_clip = { .y1 = -1 };
struct intel_plane *plane;
bool full_update = false;
int i, ret;
@@ -1282,13 +1284,25 @@ int intel_psr2_sel_fetch_update(struct
intel_atomic_state *state,
if (ret)
return ret;
+ /*
+* Calculate minimal selective fetch area of each plane and calculate
+* the pipe damaged area.
+* In the next loop the plane selective fetch area will actually be set
+* using whole pipe damaged area.
+*/
for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
new_plane_state, i) {
- struct drm_rect *sel_fetch_area, temp;
+ struct drm_rect src, damaged_area = { .y1 = -1 };
+ struct drm_mode_rect *damaged_clips;
+ u32 num_clips, j;
if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
continue;
+ if (!new_plane_state->uapi.visible &&
+ !old_plane_state->uapi.visible)
+ continue;
+
/*
* TODO: Not clear how to handle planes with negative position,
* also planes are not updated if they have a negative X
@@ -1300,23 +1314,94 @@ int intel_psr2_sel_fetch_update(struct
intel_atomic_state *state,
break;
}
- if (!new_plane_state->uapi.visible)
- continue;
+ num_clips =
drm_plane_get_damage_clips_count(_plane_state->uapi);
/*
-* For now doing a selective fetch in the whole plane area,
-* optimizations will come in the future.
+* If visibility or plane moved, mark the whole plane area as
+* damaged as it needs to be complete redraw in the new and old
+* position.
*/
- sel_fetch_area = _plane_state->psr2_sel_fetch_area;
- sel_fetch_area->y1 = new_plane_state->uapi.src.y1 >> 16;
- sel_fetch_area->y2 =
[Intel-gfx] [PATCH v10 4/5] drm/i915/display/psr: Program plane's calculated offset to plane SF register
From: José Roberto de Souza It programs Plane's calculated x, y, offset to Plane SF register. It does the calculation of x and y offsets using skl_calc_main_surface_offset(). v3: Update commit message Cc: Gwan-gyeong Mun Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun Tested-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_psr.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f5b9519b3756..c24ae69426cf 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1186,7 +1186,8 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum pipe pipe = plane->pipe; const struct drm_rect *clip; - u32 val; + u32 val, offset; + int ret, x, y; if (!crtc_state->enable_psr2_sel_fetch) return; @@ -1203,9 +1204,14 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, val |= plane_state->uapi.dst.x1; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); - /* TODO: consider tiling and auxiliary surfaces */ - val = (clip->y1 + plane_state->color_plane[color_plane].y) << 16; - val |= plane_state->color_plane[color_plane].x; + /* TODO: consider auxiliary surfaces */ + x = plane_state->uapi.src.x1 >> 16; + y = (plane_state->uapi.src.y1 >> 16) + clip->y1; + ret = skl_calc_main_surface_offset(plane_state, , , ); + if (ret) + drm_warn_once(_priv->drm, "skl_calc_main_surface_offset() returned %i\n", + ret); + val = y << 16 | x; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), val); -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v10 5/5] HAX/DO_NOT_MERGE_IT: drm/i915/display: Enable PSR2 selective fetch for testing
From: José Roberto de Souza Enabling it to check if it causes regressions in CI but the feature is still not ready to be enabled by default. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 330c03e2b4f7..b8b19270c339 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -54,7 +54,7 @@ struct drm_printer; param(int, enable_fbc, -1, 0600) \ param(int, enable_psr, -1, 0600) \ param(bool, psr_safest_params, false, 0600) \ - param(bool, enable_psr2_sel_fetch, false, 0600) \ + param(bool, enable_psr2_sel_fetch, true, 0600) \ param(int, disable_power_well, -1, 0400) \ param(int, enable_ips, 1, 0600) \ param(int, invert_brightness, 0, 0600) \ -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v10 3/5] drm/i915/display: Split and export main surface calculation from skl_check_main_surface()
From: José Roberto de Souza
The calculation the offsets of the main surface will be needed by PSR2
selective fetch code so here splitting and exporting it.
No functional changes were done here.
v3: Rebased
v10: Rebased
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Reviewed-by: Gwan-gyeong Mun
Tested-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_display.c | 78
drivers/gpu/drm/i915/display/intel_display.h | 2 +
2 files changed, 51 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f2c48e5cdb43..0189d379a55e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3752,33 +3752,19 @@ static int intel_plane_max_height(struct intel_plane
*plane,
return INT_MAX;
}
-static int skl_check_main_surface(struct intel_plane_state *plane_state)
+int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
+int *x, int *y, u32 *offset)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
- unsigned int rotation = plane_state->hw.rotation;
- int x = plane_state->uapi.src.x1 >> 16;
- int y = plane_state->uapi.src.y1 >> 16;
- int w = drm_rect_width(_state->uapi.src) >> 16;
- int h = drm_rect_height(_state->uapi.src) >> 16;
- int min_width = intel_plane_min_width(plane, fb, 0, rotation);
- int max_width = intel_plane_max_width(plane, fb, 0, rotation);
- int max_height = intel_plane_max_height(plane, fb, 0, rotation);
- int aux_plane = intel_main_to_aux_plane(fb, 0);
- u32 aux_offset = plane_state->color_plane[aux_plane].offset;
- u32 alignment, offset;
+ const int aux_plane = intel_main_to_aux_plane(fb, 0);
+ const u32 aux_offset = plane_state->color_plane[aux_plane].offset;
+ const u32 alignment = intel_surf_alignment(fb, 0);
+ const int w = drm_rect_width(_state->uapi.src) >> 16;
- if (w > max_width || w < min_width || h > max_height) {
- drm_dbg_kms(_priv->drm,
- "requested Y/RGB source size %dx%d outside limits
(min: %dx1 max: %dx%d)\n",
- w, h, min_width, max_width, max_height);
- return -EINVAL;
- }
-
- intel_add_fb_offsets(, , plane_state, 0);
- offset = intel_plane_compute_aligned_offset(, , plane_state, 0);
- alignment = intel_surf_alignment(fb, 0);
+ intel_add_fb_offsets(x, y, plane_state, 0);
+ *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);
if (drm_WARN_ON(_priv->drm, alignment && !is_power_of_2(alignment)))
return -EINVAL;
@@ -3787,9 +3773,10 @@ static int skl_check_main_surface(struct
intel_plane_state *plane_state)
* main surface offset, and it must be non-negative. Make
* sure that is what we will get.
*/
- if (aux_plane && offset > aux_offset)
- offset = intel_plane_adjust_aligned_offset(, , plane_state,
0,
- offset, aux_offset &
~(alignment - 1));
+ if (aux_plane && *offset > aux_offset)
+ *offset = intel_plane_adjust_aligned_offset(x, y, plane_state,
0,
+ *offset,
+ aux_offset &
~(alignment - 1));
/*
* When using an X-tiled surface, the plane blows up
@@ -3800,18 +3787,51 @@ static int skl_check_main_surface(struct
intel_plane_state *plane_state)
if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
int cpp = fb->format->cpp[0];
- while ((x + w) * cpp > plane_state->color_plane[0].stride) {
- if (offset == 0) {
+ while ((*x + w) * cpp > plane_state->color_plane[0].stride) {
+ if (*offset == 0) {
drm_dbg_kms(_priv->drm,
"Unable to find suitable display
surface offset due to X-tiling\n");
return -EINVAL;
}
- offset = intel_plane_adjust_aligned_offset(, ,
plane_state, 0,
- offset,
offset - alignment);
+ *offset = intel_plane_adjust_aligned_offset(x, y,
plane_state, 0,
+ *offset,
+ *offset -
alignment);
}
}
+ return 0;
+}
+
+static int
[Intel-gfx] [PATCH v10 1/5] drm: Add function to convert rect in 16.16 fixed format to regular format
From: José Roberto de Souza
Much more clear to read one function call than four lines doing this
conversion.
v7:
- function renamed
- calculating width and height before truncate
- inlined
Cc: Ville Syrjälä
Cc: dri-de...@lists.freedesktop.org
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
Reviewed-by: Gwan-gyeong Mun
---
include/drm/drm_rect.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/drm/drm_rect.h b/include/drm/drm_rect.h
index e7f4d24cdd00..7eb84af4a818 100644
--- a/include/drm/drm_rect.h
+++ b/include/drm/drm_rect.h
@@ -206,6 +206,19 @@ static inline bool drm_rect_equals(const struct drm_rect
*r1,
r1->y1 == r2->y1 && r1->y2 == r2->y2;
}
+/**
+ * drm_rect_fp_to_int - Convert a rect in 16.16 fixed point form to int form.
+ * @destination: rect to be stored the converted value
+ * @source: rect in 16.16 fixed point form
+ */
+static inline void drm_rect_fp_to_int(struct drm_rect *destination,
+ const struct drm_rect *source)
+{
+ drm_rect_init(destination, source->x1 >> 16, source->y1 >> 16,
+ drm_rect_width(source) >> 16,
+ drm_rect_height(source) >> 16);
+}
+
bool drm_rect_intersect(struct drm_rect *r, const struct drm_rect *clip);
bool drm_rect_clip_scaled(struct drm_rect *src, struct drm_rect *dst,
const struct drm_rect *clip);
--
2.25.0
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/debugfs : PM_REQ and PM_RES registers
== Series Details == Series: drm/i915/debugfs : PM_REQ and PM_RES registers URL : https://patchwork.freedesktop.org/series/85437/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/display/intel_display_debugfs.o drivers/gpu/drm/i915/display/intel_display_debugfs.c:562:12: error: ‘i915_pm_req_res_info’ defined but not used [-Werror=unused-function] static int i915_pm_req_res_info(struct seq_file *m, void *unused) ^~~~ cc1: all warnings being treated as errors scripts/Makefile.build:279: recipe for target 'drivers/gpu/drm/i915/display/intel_display_debugfs.o' failed make[4]: *** [drivers/gpu/drm/i915/display/intel_display_debugfs.o] Error 1 scripts/Makefile.build:496: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:496: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:496: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1805: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/6] drm/i915/gt: Restore ce->signal flush before releasing virtual engine
Before we mark the virtual engine as no longer inflight, flush any
ongoing signaling that may be using the ce->signal_link along the
previous breadcrumbs. On switch to a new physical engine, that link will
be inserted into the new set of breadcrumbs, causing confusion to an
ongoing iterator.
This patch undoes a last minute mistake introduced into commit
bab0557c8dca ("drm/i915/gt: Remove virtual breadcrumb before transfer"),
whereby instead of unconditionally applying the flush, it was only
applied if the request itself was going to be reused.
Fixes: bab0557c8dca ("drm/i915/gt: Remove virtual breadcrumb before transfer")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index a5b442683c18..6414dbb124a7 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -592,8 +592,6 @@ resubmit_virtual_request(struct i915_request *rq, struct
virtual_engine *ve)
* ce->signal_link.
*/
i915_request_cancel_breadcrumb(rq);
- while (atomic_read(>breadcrumbs->signaler_active))
- cpu_relax();
}
spin_lock_irq(>active.lock);
@@ -609,6 +607,7 @@ static void kick_siblings(struct i915_request *rq, struct
intel_context *ce)
{
struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
struct intel_engine_cs *engine = rq->engine;
+ bool signals = !list_empty(>signals);
/*
* This engine is now too busy to run this virtual request, so
@@ -622,6 +621,10 @@ static void kick_siblings(struct i915_request *rq, struct
intel_context *ce)
if (READ_ONCE(ve->request))
tasklet_hi_schedule(>base.execlists.tasklet);
+
+ /* Flush concurrent signal_irq_work before we reuse the link */
+ while (signals && atomic_read(>breadcrumbs->signaler_active))
+ cpu_relax();
}
static inline void __execlists_schedule_out(struct i915_request *rq)
--
2.20.1
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/6] drm/i915/gt: Remove timeslice suppression
In the next patch, we remove the strict priority system and continuously
re-evaluate the relative priority of tasks. As such we need to enable
the timeslice whenever there is more than one context in the pipeline.
This simplifies the decision and removes some of the tweaks to suppress
timeslicing, allowing us to lift the timeslice enabling to a common spot
at the end of running the submission tasklet.
Testcase: igt/gem_exec_balancer/fairslice
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 10 --
.../drm/i915/gt/intel_execlists_submission.c | 159 +++---
2 files changed, 61 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 430066e5884c..df62e793e747 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -238,16 +238,6 @@ struct intel_engine_execlists {
*/
unsigned int port_mask;
- /**
-* @switch_priority_hint: Second context priority.
-*
-* We submit multiple contexts to the HW simultaneously and would
-* like to occasionally switch between them to emulate timeslicing.
-* To know when timeslicing is suitable, we track the priority of
-* the context submitted second.
-*/
- int switch_priority_hint;
-
/**
* @queue_priority_hint: Highest pending priority.
*
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 6414dbb124a7..fda83fe2e451 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1151,25 +1151,6 @@ static void defer_active(struct intel_engine_cs *engine)
defer_request(rq, i915_sched_lookup_priolist(engine, rq_prio(rq)));
}
-static bool
-need_timeslice(const struct intel_engine_cs *engine,
- const struct i915_request *rq)
-{
- int hint;
-
- if (!intel_engine_has_timeslices(engine))
- return false;
-
- hint = max(engine->execlists.queue_priority_hint,
- virtual_prio(>execlists));
-
- if (!list_is_last(>sched.link, >active.requests))
- hint = max(hint, rq_prio(list_next_entry(rq, sched.link)));
-
- GEM_BUG_ON(hint >= I915_PRIORITY_UNPREEMPTABLE);
- return hint >= effective_prio(rq);
-}
-
static bool
timeslice_yield(const struct intel_engine_execlists *el,
const struct i915_request *rq)
@@ -1189,76 +1170,68 @@ timeslice_yield(const struct intel_engine_execlists *el,
return rq->context->lrc.ccid == READ_ONCE(el->yield);
}
-static bool
-timeslice_expired(const struct intel_engine_execlists *el,
- const struct i915_request *rq)
+static bool needs_timeslice(const struct intel_engine_cs *engine,
+ const struct i915_request *rq)
{
- return timer_expired(>timer) || timeslice_yield(el, rq);
-}
+ if (!intel_engine_has_timeslices(engine))
+ return false;
-static int
-switch_prio(struct intel_engine_cs *engine, const struct i915_request *rq)
-{
- if (list_is_last(>sched.link, >active.requests))
- return engine->execlists.queue_priority_hint;
+ /* If not currently active, or about to switch, wait for next event */
+ if (!rq || __i915_request_is_complete(rq))
+ return false;
- return rq_prio(list_next_entry(rq, sched.link));
-}
+ /* We do not need to start the timeslice until after the ACK */
+ if (READ_ONCE(engine->execlists.pending[0]))
+ return false;
-static inline unsigned long
-timeslice(const struct intel_engine_cs *engine)
-{
- return READ_ONCE(engine->props.timeslice_duration_ms);
+ /* If ELSP[1] is occupied, always check to see if worth slicing */
+ if (!list_is_last_rcu(>sched.link, >active.requests))
+ return true;
+
+ /* Otherwise, ELSP[0] is by itself, but may be waiting in the queue */
+ if (!RB_EMPTY_ROOT(>execlists.queue.rb_root))
+ return true;
+
+ return !RB_EMPTY_ROOT(>execlists.virtual.rb_root);
}
-static unsigned long active_timeslice(const struct intel_engine_cs *engine)
+static bool
+timeslice_expired(struct intel_engine_cs *engine, const struct i915_request
*rq)
{
- const struct intel_engine_execlists *execlists = >execlists;
- const struct i915_request *rq = *execlists->active;
+ const struct intel_engine_execlists *el = >execlists;
- if (!rq || __i915_request_is_complete(rq))
- return 0;
+ if (i915_request_has_nopreempt(rq) && __i915_request_has_started(rq))
+ return false;
- if (READ_ONCE(execlists->switch_priority_hint) < effective_prio(rq))
- return 0;
+ if (!needs_timeslice(engine, rq))
+
[Intel-gfx] [PATCH 3/6] drm/i915/gt: Allow failed resets without assertion
If the engine reset fails, we will attempt to resume with the current
inflight submissions. When that happens, we cannot assert that the
engine reset cleared the pending submission, so do not.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2878
Fixes: 16f2941ad307 ("drm/i915/gt: Replace direct submit with direct call to
tasklet")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +
.../drm/i915/gt/intel_execlists_submission.c | 6 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 3 +
drivers/gpu/drm/i915/gt/selftest_execlists.c | 75 +++
4 files changed, 85 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index c28f4e190fe6..430066e5884c 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -561,6 +561,8 @@ struct intel_engine_cs {
unsigned long stop_timeout_ms;
unsigned long timeslice_duration_ms;
} props, defaults;
+
+ I915_SELFTEST_DECLARE(struct fault_attr reset_timeout);
};
static inline bool
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 2afbc0a4ca03..f02e3ae10d28 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3047,9 +3047,13 @@ static void execlists_reset_finish(struct
intel_engine_cs *engine)
* After a GPU reset, we may have requests to replay. Do so now while
* we still have the forcewake to be sure that the GPU is not allowed
* to sleep before we restart and reload a context.
+*
+* If the GPU reset fails, the engine may still be alive with requests
+* inflight. We expect those to complete, or for the device to be
+* reset as the next level of recovery, and as a final resort we
+* will declare the device wedged.
*/
GEM_BUG_ON(!reset_in_progress(execlists));
- GEM_BUG_ON(engine->execlists.pending[0]);
/* And kick in case we missed a new request submission. */
if (__tasklet_enable(>tasklet))
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 761b50eca33b..9d177297db79 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -497,6 +497,9 @@ static int gen8_engine_reset_prepare(struct intel_engine_cs
*engine)
u32 request, mask, ack;
int ret;
+ if (I915_SELFTEST_ONLY(should_fail(>reset_timeout, 1)))
+ return -ETIMEDOUT;
+
ack = intel_uncore_read_fw(uncore, reg);
if (ack & RESET_CTL_CAT_ERROR) {
/*
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 3854da5a4e65..bfa7fd5c2c91 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -2299,6 +2299,77 @@ static int __cancel_hostile(struct live_preempt_cancel
*arg)
return err;
}
+static void force_reset_timeout(struct intel_engine_cs *engine)
+{
+ engine->reset_timeout.probability = 999;
+ atomic_set(>reset_timeout.times, -1);
+}
+
+static void cancel_reset_timeout(struct intel_engine_cs *engine)
+{
+ memset(>reset_timeout, 0, sizeof(engine->reset_timeout));
+}
+
+static int __cancel_fail(struct live_preempt_cancel *arg)
+{
+ struct intel_engine_cs *engine = arg->engine;
+ struct i915_request *rq;
+ int err;
+
+ if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT))
+ return 0;
+
+ if (!intel_has_reset_engine(engine->gt))
+ return 0;
+
+ GEM_TRACE("%s(%s)\n", __func__, engine->name);
+ rq = spinner_create_request(>a.spin,
+ arg->a.ctx, engine,
+ MI_NOOP); /* preemption disabled */
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ clear_bit(CONTEXT_BANNED, >context->flags);
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (!igt_wait_for_spinner(>a.spin, rq)) {
+ err = -EIO;
+ goto out;
+ }
+
+ intel_context_set_banned(rq->context);
+
+ err = intel_engine_pulse(engine);
+ if (err)
+ goto out;
+
+ force_reset_timeout(engine);
+
+ /* force preempt reset [failure] */
+ while (!engine->execlists.pending[0])
+ intel_engine_flush_submission(engine);
+ del_timer_sync(>execlists.preempt);
+ intel_engine_flush_submission(engine);
+
+ cancel_reset_timeout(engine);
+
+ /* after failure, require heartbeats to reset device */
+ intel_engine_set_heartbeat(engine, 1);
+ err = wait_for_reset(engine, rq, HZ / 2);
+
[Intel-gfx] [PATCH 1/6] drm/i915/selftests: Set error returns
A few missed PTR_ERR() upon create_gang() errors.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 080b63000a4e..3854da5a4e65 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -2658,8 +2658,10 @@ static int create_gang(struct intel_engine_cs *engine,
goto err_obj;
cs = i915_gem_object_pin_map(obj, I915_MAP_WC);
- if (IS_ERR(cs))
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
goto err_obj;
+ }
/* Semaphore target: spin until zero */
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
@@ -2686,8 +2688,10 @@ static int create_gang(struct intel_engine_cs *engine,
i915_gem_object_unpin_map(obj);
rq = intel_context_create_request(ce);
- if (IS_ERR(rq))
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
goto err_obj;
+ }
rq->batch = i915_vma_get(vma);
i915_request_get(rq);
--
2.20.1
___
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[Intel-gfx] [PATCH 4/6] drm/i915/gt: Check the virtual still matches upon locking
If another sibling is able to claim the virtual request, by the time we
inspect the request under the lock if may no longer match the local
engine.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2877
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index f02e3ae10d28..a5b442683c18 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1016,6 +1016,9 @@ static bool virtual_matches(const struct virtual_engine
*ve,
{
const struct intel_engine_cs *inflight;
+ if (!rq)
+ return false;
+
if (!(rq->execution_mask & engine->mask)) /* We peeked too soon! */
return false;
@@ -1423,8 +1426,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
spin_lock(>base.active.lock);
rq = ve->request;
- if (unlikely(!rq)) /* lost the race to a sibling */
- goto unlock;
+ if (unlikely(!virtual_matches(ve, rq, engine)))
+ goto unlock; /* lost the race to a sibling */
GEM_BUG_ON(rq->engine != >base);
GEM_BUG_ON(rq->context != >context);
@@ -1434,8 +1437,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
break;
}
- GEM_BUG_ON(!virtual_matches(ve, rq, engine));
-
if (last && !can_merge_rq(last, rq)) {
spin_unlock(>base.active.lock);
spin_unlock(>active.lock);
--
2.20.1
___
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[Intel-gfx] [PATCH 2/6] drm/i915: Set rawclk earlier during mmio probe
Fixes: f170523a7b8e ("drm/i915/gt: Consolidate the CS timestamp clocks")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 249f765993f7..3e504247f2da 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -410,6 +410,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
/* Try to make sure MCHBAR is enabled before poking at it */
intel_setup_mchbar(dev_priv);
+ intel_device_info_runtime_init(dev_priv);
ret = intel_gt_init_mmio(_priv->gt);
if (ret)
@@ -516,8 +517,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
- intel_device_info_runtime_init(dev_priv);
-
if (HAS_PPGTT(dev_priv)) {
if (intel_vgpu_active(dev_priv) &&
!intel_vgpu_has_full_ppgtt(dev_priv)) {
--
2.20.1
___
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[Intel-gfx] [CI 2/2] drm/i915/gt: Rearrange hsw workarounds
Some rcs0 workarounds were being incorrectly applied to the GT, and so
we failed to restore the expected register settings after a reset.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 54 +++--
1 file changed, 29 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 741ed6e9f5cb..c21a9726326a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -956,31 +956,6 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
/* WaVSRefCountFullforceMissDisable:hsw */
wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
-
- wa_masked_dis(wal,
- CACHE_MODE_0_GEN7,
- /* WaDisable_RenderCache_OperationalFlush:hsw */
- RC_OP_FLUSH_ENABLE |
- /* enable HiZ Raw Stall Optimization */
- HIZ_RAW_STALL_OPT_DISABLE);
-
- /* WaDisable4x2SubspanOptimization:hsw */
- wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
-
- /*
-* BSpec recommends 8x4 when MSAA is used,
-* however in practice 16x4 seems fastest.
-*
-* Note that PS/WM thread counts depend on the WIZ hashing
-* disable bit, which we don't touch here, but it's good
-* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
-*/
- wa_add(wal, GEN7_GT_MODE, 0,
- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
- GEN6_WIZ_HASHING_16x4);
-
- /* WaSampleCChickenBitEnable:hsw */
- wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
}
static void
@@ -1948,6 +1923,35 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
GEN8_LQSC_FLUSH_COHERENT_LINES);
}
+ if (IS_HASWELL(i915)) {
+ /* WaSampleCChickenBitEnable:hsw */
+ wa_masked_en(wal,
+HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
+
+ wa_masked_dis(wal,
+ CACHE_MODE_0_GEN7,
+ /* WaDisable_RenderCache_OperationalFlush:hsw */
+ RC_OP_FLUSH_ENABLE |
+ /* enable HiZ Raw Stall Optimization */
+ HIZ_RAW_STALL_OPT_DISABLE);
+
+ /* WaDisable4x2SubspanOptimization:hsw */
+ wa_masked_en(wal, CACHE_MODE_1,
PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
+
+ /*
+* BSpec recommends 8x4 when MSAA is used,
+* however in practice 16x4 seems fastest.
+*
+* Note that PS/WM thread counts depend on the WIZ hashing
+* disable bit, which we don't touch here, but it's good
+* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
+*/
+ wa_add(wal, GEN7_GT_MODE, 0,
+ _MASKED_FIELD(GEN6_WIZ_HASHING_MASK,
+GEN6_WIZ_HASHING_16x4),
+ GEN6_WIZ_HASHING_16x4);
+ }
+
if (IS_GEN(i915, 7))
/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
wa_masked_en(wal,
--
2.20.1
___
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[Intel-gfx] [CI 1/2] drm/i915/gt: Rearrange snb workarounds
Some rcs0 workarounds were being incorrectly applied to the GT, and so
we failed to restore the expected register settings after a reset.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 67 ++---
1 file changed, 33 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b0e3a5ba0320..741ed6e9f5cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -824,40 +824,6 @@ ilk_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
static void
snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
{
- /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
- wa_masked_en(wal,
-_3D_CHICKEN,
-_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB);
-
- /* WaDisable_RenderCache_OperationalFlush:snb */
- wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
-
- /*
-* BSpec recommends 8x4 when MSAA is used,
-* however in practice 16x4 seems fastest.
-*
-* Note that PS/WM thread counts depend on the WIZ hashing
-* disable bit, which we don't touch here, but it's good
-* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
-*/
- wa_add(wal,
- GEN6_GT_MODE, 0,
- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
- GEN6_WIZ_HASHING_16x4);
-
- wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB);
-
- wa_masked_en(wal,
-_3D_CHICKEN3,
-/* WaStripsFansDisableFastClipPerformanceFix:snb */
-_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL |
-/*
- * Bspec says:
- * "This bit must be set if 3DSTATE_CLIP clip mode is set
- * to normal and 3DSTATE_SF number of SF output attributes
- * is more than 16."
- */
- _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH);
}
static void
@@ -2010,6 +1976,39 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
GFX_MODE,
GFX_TLB_INVALIDATE_EXPLICIT);
+ /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
+ wa_masked_en(wal,
+_3D_CHICKEN,
+_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB);
+
+ wa_masked_en(wal,
+_3D_CHICKEN3,
+/* WaStripsFansDisableFastClipPerformanceFix:snb */
+_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL |
+/*
+ * Bspec says:
+ * "This bit must be set if 3DSTATE_CLIP clip mode
is set
+ * to normal and 3DSTATE_SF number of SF output
attributes
+ * is more than 16."
+ */
+_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH);
+
+ /*
+* BSpec recommends 8x4 when MSAA is used,
+* however in practice 16x4 seems fastest.
+*
+* Note that PS/WM thread counts depend on the WIZ hashing
+* disable bit, which we don't touch here, but it's good
+* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
+*/
+ wa_add(wal,
+ GEN6_GT_MODE, 0,
+ _MASKED_FIELD(GEN6_WIZ_HASHING_MASK,
GEN6_WIZ_HASHING_16x4),
+ GEN6_WIZ_HASHING_16x4);
+
+ /* WaDisable_RenderCache_OperationalFlush:snb */
+ wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
+
/*
* From the Sandybridge PRM, volume 1 part 3, page 24:
* "If this bit is set, STCunit will have LRA as replacement
--
2.20.1
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[Intel-gfx] [PATCH i-g-t] i915/gem_spin_batch: Convert to dynamic engine discovery
Only run the tests on the available engines using igt_dynamic. This
prevents flip-flops with SKIP on shards that have a mixture of machine
types (e.g. shard-icl that has some machines with vcs1 and some
without).
Signed-off-by: Chris Wilson
---
tests/i915/gem_spin_batch.c | 82 ++---
1 file changed, 39 insertions(+), 43 deletions(-)
diff --git a/tests/i915/gem_spin_batch.c b/tests/i915/gem_spin_batch.c
index 0a5cfdf36..c2ce2373b 100644
--- a/tests/i915/gem_spin_batch.c
+++ b/tests/i915/gem_spin_batch.c
@@ -35,7 +35,7 @@
#x, #ref, (long long)x, tolerance, (long long)ref)
static void spin(int fd,
-const struct intel_execution_engine2 *e2,
+unsigned int engine,
unsigned int flags,
unsigned int timeout_sec)
{
@@ -46,10 +46,10 @@ static void spin(int fd,
struct timespec itv = { };
uint64_t elapsed;
- spin = __igt_spin_new(fd, .engine = e2->flags, .flags = flags);
+ spin = __igt_spin_new(fd, .engine = engine, .flags = flags);
while ((elapsed = igt_nsec_elapsed()) >> 30 < timeout_sec) {
igt_spin_t *next =
- __igt_spin_new(fd, .engine = e2->flags, .flags = flags);
+ __igt_spin_new(fd, .engine = engine, .flags = flags);
igt_spin_set_timeout(spin,
timeout_100ms - igt_nsec_elapsed());
@@ -75,14 +75,13 @@ static void spin(int fd,
#define RESUBMIT_NEW_CTX (1 << 0)
#define RESUBMIT_ALL_ENGINES (1 << 1)
-static void spin_resubmit(int fd, const struct intel_execution_engine2 *e2,
- unsigned int flags)
+static void spin_resubmit(int fd, unsigned int engine, unsigned int flags)
{
const uint32_t ctx0 = gem_context_clone_with_engines(fd, 0);
const uint32_t ctx1 =
(flags & RESUBMIT_NEW_CTX) ?
gem_context_clone_with_engines(fd, 0) : ctx0;
- igt_spin_t *spin = __igt_spin_new(fd, .ctx = ctx0, .engine = e2->flags);
+ igt_spin_t *spin = __igt_spin_new(fd, .ctx = ctx0, .engine = engine);
const struct intel_execution_engine2 *other;
struct drm_i915_gem_execbuffer2 eb = {
@@ -96,14 +95,14 @@ static void spin_resubmit(int fd, const struct
intel_execution_engine2 *e2,
if (flags & RESUBMIT_ALL_ENGINES) {
for_each_context_engine(fd, ctx1, other) {
- if (gem_engine_is_equal(other, e2))
+ if (other->flags == engine)
continue;
eb.flags = other->flags;
gem_execbuf(fd, );
}
} else {
- eb.flags = e2->flags;
+ eb.flags = engine;
gem_execbuf(fd, );
}
@@ -132,7 +131,7 @@ spin_on_all_engines(int fd, unsigned long flags, unsigned
int timeout_sec)
__for_each_physical_engine(fd, e2) {
igt_fork(child, 1) {
igt_install_exit_handler(spin_exit_handler);
- spin(fd, e2, flags, timeout_sec);
+ spin(fd, e2->flags, flags, timeout_sec);
}
}
@@ -181,7 +180,6 @@ igt_main
{
const struct intel_execution_engine2 *e2;
const struct intel_execution_ring *e;
- struct intel_execution_engine2 e2__;
int fd = -1;
igt_fixture {
@@ -190,51 +188,49 @@ igt_main
igt_fork_hang_detector(fd);
}
- for (e = intel_execution_rings; e->name; e++) {
- e2__ = gem_eb_flags_to_engine(eb_ring(e));
- if (e2__.flags == -1)
- continue;
- e2 = __;
+#define test_each_legacy_ring(test) \
+ igt_subtest_with_dynamic(test) \
+ for (e = intel_execution_rings; e->name; e++) \
+ if (gem_has_ring(fd, eb_ring(e))) \
+ igt_dynamic_f("%s", e->name)
- igt_subtest_f("legacy-%s", e->name) {
- igt_require(gem_has_ring(fd, eb_ring(e)));
- spin(fd, e2, 0, 3);
- }
+ test_each_legacy_ring("legacy")
+ spin(fd, eb_ring(e), 0, 3);
+ test_each_legacy_ring("legacy-resubmit")
+ spin_resubmit(fd, eb_ring(e), 0);
+ test_each_legacy_ring("legacy-resubmit-new")
+ spin_resubmit(fd, eb_ring(e), RESUBMIT_NEW_CTX);
- igt_subtest_f("legacy-resubmit-%s", e->name) {
- igt_require(gem_has_ring(fd, eb_ring(e)));
- spin_resubmit(fd, e2, 0);
- }
-
- igt_subtest_f("legacy-resubmit-new-%s", e->name) {
- igt_require(gem_has_ring(fd, eb_ring(e)));
- spin_resubmit(fd, e2, RESUBMIT_NEW_CTX);
- }
- }
+#undef test_each_legcy_ring
[Intel-gfx] [PATCH v2] drm/i915/debugfs : PM_REQ and PM_RES registers
From: Saichandana
PM_REQ register provides the value of the last PM request from PCU to
Display Engine.PM_RES register provides the value of the last PM
response from Display Engine to PCU.This debugfs will be used by
DC9 IGT test to know about "DC9 Ready" status.
B.Spec : 49501, 49502
Signed-off-by: Saichandana
---
.../drm/i915/display/intel_display_debugfs.c | 30 +++
drivers/gpu/drm/i915/i915_reg.h | 8 +
2 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cd7e5519ee7d..551fb1a90bb3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -559,6 +559,36 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
return 0;
}
+static int i915_pm_req_res_info(struct seq_file *m, void *unused)
+{
+ struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_csr *csr = _priv->csr;
+ const char *status;
+
+ if (!HAS_CSR(dev_priv))
+ return -ENODEV;
+ if (!csr->dmc_payload)
+ return 0;
+ seq_printf(m, "PM debug request 0 (0x45284): 0x%08x\n",
+ intel_de_read(dev_priv, PM_REQ_DBG_0));
+ seq_printf(m, "PM debug request 1 (0x45288): 0x%08x\n",
+ intel_de_read(dev_priv, PM_REQ_DBG_1));
+ seq_printf(m, "PM debug response 0 (0x4528C): 0x%08x\n",
+ intel_de_read(dev_priv, PM_RSP_DBG_0));
+ seq_printf(m, "PM debug response 1 (0x45290): 0x%08x\n",
+ intel_de_read(dev_priv, PM_RSP_DBG_1));
+ status = (intel_de_read(dev_priv, PM_RSP_DBG_1) & MASK_DC9_BIT) ? "yes"
: "no";
+
+ seq_printf(m, "Time to Next Fill = 0x%0x\n",
+ (intel_de_read(dev_priv, PM_RSP_DBG_0) & ~MASK_RSP_0));
+ seq_printf(m, "Time to Next VBI = 0x%0x\n",
+ ((intel_de_read(dev_priv, PM_RSP_DBG_0) & MASK_RSP_0)) >>
16);
+ seq_printf(m, "Selective Exit Latency = 0x%0x\n",
+ (intel_de_read(dev_priv, PM_RSP_DBG_1) & MASK_RSP_1));
+ seq_printf(m, "DC9 Ready = %s\n", status);
+ return 0;
+}
+
static void intel_seq_print_mode(struct seq_file *m, int tabs,
const struct drm_display_mode *mode)
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0023c023f472..3e9ed555f928 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -371,6 +371,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define VLV_G3DCTL _MMIO(0x9024)
#define VLV_GSCKGCTL _MMIO(0x9028)
+#define PM_REQ_DBG_0 _MMIO(0x45284)
+#define PM_REQ_DBG_1 _MMIO(0x45288)
+#define PM_RSP_DBG_0 _MMIO(0x4528C)
+#define PM_RSP_DBG_1 _MMIO(0x45290)
+#define MASK_RSP_0 (0x << 16)
+#define MASK_RSP_1 (7 << 0)
+#define MASK_DC9_BIT (1 << 17)
+
#define GEN6_MBCTL _MMIO(0x0907c)
#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
--
2.17.1
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Re: [Intel-gfx] [PULL] drm-misc-next-fixes
Hi, it looks like this PR has not been merged yet. Best regard Thomas Am 22.12.20 um 20:13 schrieb Thomas Zimmermann: Hi Dave and Daniel, here's this week's PR for drm-misc-next-fixes. Best regards Thomas drm-misc-next-fixes-2020-12-22: Short summary of fixes pull: * dma-buf: Include for building on MIPS * komeda: Fix order of operation in commit tail; Fix NULL-pointer and out-of-bounds access; Cleanups * ttm: Fix an unused-function warning The following changes since commit ee46d16d2e40bebc2aa790fd7b6a056466ff895c: drm: mxsfb: Silence -EPROBE_DEFER while waiting for bridge (2020-12-15 11:01:10 +0100) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-fixes-2020-12-22 for you to fetch changes up to be3e477effba636ad25dcd244db264c6cd5c1f36: drm/komeda: Fix bit check to import to value of proper type (2020-12-18 16:36:00 +) Short summary of fixes pull: * dma-buf: Include for building on MIPS * komeda: Fix order of operation in commit tail; Fix NULL-pointer and out-of-bounds access; Cleanups * ttm: Fix an unused-function warning Arnd Bergmann (1): drm/ttm: fix unused function warning Carsten Haitzler (3): drm/komeda: Remove useless variable assignment drm/komeda: Handle NULL pointer access code path in error case drm/komeda: Fix bit check to import to value of proper type Christian König (1): drm/qxl: don't allocate a dma_address array James Qian Wang (1): drm/komeda: Correct the sequence of hw_done() and flip_done() John Stultz (1): dma-buf: cma_heap: Include linux/vmalloc.h to fix build failures on MIPS drivers/dma-buf/heaps/cma_heap.c | 1 + drivers/gpu/drm/arm/display/komeda/komeda_dev.c| 1 - drivers/gpu/drm/arm/display/komeda/komeda_kms.c| 4 +-- .../gpu/drm/arm/display/komeda/komeda_pipeline.c | 3 ++- .../drm/arm/display/komeda/komeda_pipeline_state.c | 4 +-- drivers/gpu/drm/qxl/qxl_ttm.c | 2 +- drivers/gpu/drm/ttm/ttm_pool.c | 29 +++--- 7 files changed, 22 insertions(+), 22 deletions(-) -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer ___ dri-devel mailing list dri-de...@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer OpenPGP_signature Description: OpenPGP digital signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
