[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Remove unused function 'dword_in_page'
== Series Details == Series: drm/i915/gt: Remove unused function 'dword_in_page' URL : https://patchwork.freedesktop.org/series/85634/ State : success == Summary == CI Bug Log - changes from CI_DRM_9569_full -> Patchwork_19300_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19300_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_endless@dispatch@bcs0: - shard-kbl: NOTRUN -> [SKIP][1] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/shard-kbl6/igt@gem_exec_endless@dispa...@bcs0.html * igt@gem_exec_reloc@basic-many-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][2] ([i915#2389]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/shard-iclb2/igt@gem_exec_reloc@basic-many-act...@vcs1.html * igt@gen3_render_mixed_blits: - shard-skl: NOTRUN -> [SKIP][3] ([fdo#109271]) +15 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/shard-skl6/igt@gen3_render_mixed_blits.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2597]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/shard-tglb7/igt@kms_async_fl...@test-time-stamp.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/shard-tglb6/igt@kms_async_fl...@test-time-stamp.html * igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes: - shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/shard-skl6/igt@kms_color_chamel...@pipe-invalid-ctm-matrix-sizes.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-random: - shard-skl: NOTRUN -> [FAIL][7] ([i915#54]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/shard-skl6/igt@kms_cursor_...@pipe-a-cursor-128x42-random.html * igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding: - shard-skl: [PASS][8] -> [FAIL][9] ([i915#54]) +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/shard-skl10/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/shard-skl7/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [PASS][10] -> [INCOMPLETE][11] ([i915#2405] / [i915#300]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/shard-skl2/igt@kms_cursor_...@pipe-b-cursor-suspend.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/shard-skl5/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions-varying-size: - shard-skl: [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/shard-skl7/igt@kms_cursor_leg...@short-flip-before-cursor-atomic-transitions-varying-size.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/shard-skl2/igt@kms_cursor_leg...@short-flip-before-cursor-atomic-transitions-varying-size.html * igt@kms_flip@2x-plain-flip-fb-recreate@ac-hdmi-a1-hdmi-a2: - shard-glk: [PASS][14] -> [FAIL][15] ([i915#2122]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/shard-glk6/igt@kms_flip@2x-plain-flip-fb-recre...@ac-hdmi-a1-hdmi-a2.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/shard-glk8/igt@kms_flip@2x-plain-flip-fb-recre...@ac-hdmi-a1-hdmi-a2.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-kbl: [PASS][16] -> [DMESG-WARN][17] ([i915#180]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/shard-kbl3/igt@kms_flip@flip-vs-suspend-interrupti...@a-dp1.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/shard-kbl4/igt@kms_flip@flip-vs-suspend-interrupti...@a-dp1.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt: - shard-skl: NOTRUN -> [FAIL][18] ([i915#49]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/shard-skl6/igt@kms_frontbuffer_track...@psr-1p-primscrn-indfb-plflip-blt.html * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: NOTRUN -> [FAIL][19] ([fdo#108145] / [i915#265]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/shard-skl6/igt@kms_plane_alpha_bl...@pipe-a-alpha-7efc.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-skl: [PASS][20] -> [INCOMPLETE][21] ([i915#146] / [i915#198] / [i915#2295]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/shard-skl5/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [21]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/7] drm/i915/gt: Prevent use of engine->wa_ctx after error
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/gt: Prevent use of
engine->wa_ctx after error
URL : https://patchwork.freedesktop.org/series/85631/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9567_full -> Patchwork_19298_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19298_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19298_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19298_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_balancer@waits:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-tglb8/igt@gem_exec_balan...@waits.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/shard-tglb1/igt@gem_exec_balan...@waits.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2}:
- shard-iclb: [SKIP][3] ([i915#2920]) -> [SKIP][4] +2 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-iclb2/igt@kms_psr2...@primary-plane-update-sf-dmg-area-2.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/shard-iclb6/igt@kms_psr2...@primary-plane-update-sf-dmg-area-2.html
Known issues
Here are the changes found in Patchwork_19298_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@engines-mixed:
- shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/shard-snb7/igt@gem_ctx_persiste...@engines-mixed.html
* igt@gem_exec_reloc@basic-wide-active@bcs0:
- shard-skl: NOTRUN -> [FAIL][6] ([i915#2389]) +3 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/shard-skl8/igt@gem_exec_reloc@basic-wide-act...@bcs0.html
* igt@gem_media_vme:
- shard-skl: NOTRUN -> [SKIP][7] ([fdo#109271]) +145 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/shard-skl7/igt@gem_media_vme.html
* igt@gem_userptr_blits@process-exit-mmap-busy@uc:
- shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1699]) +3
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/shard-skl7/igt@gem_userptr_blits@process-exit-mmap-b...@uc.html
* igt@gen7_exec_parse@basic-allocation:
- shard-glk: NOTRUN -> [SKIP][9] ([fdo#109271]) +4 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/shard-glk4/igt@gen7_exec_pa...@basic-allocation.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][10] -> [DMESG-WARN][11] ([i915#1436] /
[i915#716])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-skl8/igt@gen9_exec_pa...@allowed-single.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/shard-skl2/igt@gen9_exec_pa...@allowed-single.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-kbl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#658])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/shard-kbl6/igt@i915_pm...@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][13] ([i915#454])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/shard-skl7/igt@i915_pm...@dc6-dpms.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-skl: [PASS][14] -> [DMESG-FAIL][15] ([i915#2291] /
[i915#541])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-skl5/igt@i915_selftest@live@gt_heartbeat.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/shard-skl5/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2597])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-tglb5/igt@kms_async_fl...@test-time-stamp.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/shard-tglb5/igt@kms_async_fl...@test-time-stamp.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827])
+15 similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/shard-skl7/igt@kms_chamel...@hdmi-aspect-ratio.html
* igt@kms_color@pipe-a-ctm-0-25:
- shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982])
[19]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Mark up a debug-only function
== Series Details == Series: drm/i915/gt: Mark up a debug-only function URL : https://patchwork.freedesktop.org/series/85640/ State : success == Summary == CI Bug Log - changes from CI_DRM_9570 -> Patchwork_19304 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19304/index.html Known issues Here are the changes found in Patchwork_19304 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-byt-j1900: NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19304/fi-byt-j1900/igt@gem_huc_c...@huc-copy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/fi-tgl-y/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19304/fi-tgl-y/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][4] -> [FAIL][5] ([i915#1161] / [i915#262]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19304/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@hdmi-crc-fast: - fi-byt-j1900: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19304/fi-byt-j1900/igt@kms_chamel...@hdmi-crc-fast.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/fi-tgl-y/igt@debugfs_test@read_all_entries.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19304/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][9] ([i915#1888]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19304/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [DMESG-WARN][11] ([i915#2868]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19304/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (42 -> 38) -- Additional (1): fi-byt-j1900 Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9570 -> Patchwork_19304 CI-20190529: 20190529 CI_DRM_9570: 0c67d33cc01c40bc40213adb42e6420db337bb84 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5952: c946985af198e8f859c3c08fd562b09686fa387b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19304: 22a532e6903cfa34c80a0c3314daded88041e4a0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 22a532e6903c drm/i915/gt: Mark up a debug-only function == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19304/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Mark up a debug-only function
== Series Details == Series: drm/i915/gt: Mark up a debug-only function URL : https://patchwork.freedesktop.org/series/85640/ State : warning == Summary == $ dim checkpatch origin/drm-tip 22a532e6903c drm/i915/gt: Mark up a debug-only function -:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #6: drivers/gpu/drm/i915//gt/intel_workarounds.c:1394:20: error: function 'is_nonpriv_flags_valid' is not needed and will not be emitted [-Werror,-Wunneeded-internal-declaration] total: 0 errors, 1 warnings, 0 checks, 7 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Use TGL stepping info and add ADLS platform changes
== Series Details == Series: Use TGL stepping info and add ADLS platform changes URL : https://patchwork.freedesktop.org/series/85639/ State : success == Summary == CI Bug Log - changes from CI_DRM_9570 -> Patchwork_19303 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/index.html Known issues Here are the changes found in Patchwork_19303 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@memory-alloc: - fi-tgl-y: NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/fi-tgl-y/igt@amdgpu/amd_ba...@memory-alloc.html * igt@gem_huc_copy@huc-copy: - fi-byt-j1900: NOTRUN -> [SKIP][2] ([fdo#109271]) +27 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/fi-byt-j1900/igt@gem_huc_c...@huc-copy.html * igt@gem_render_tiled_blits@basic: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html * igt@kms_chamelium@hdmi-crc-fast: - fi-byt-j1900: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/fi-byt-j1900/igt@kms_chamel...@hdmi-crc-fast.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][6] ([i915#402]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/fi-tgl-y/igt@debugfs_test@read_all_entries.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][8] ([i915#1888]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [DMESG-WARN][10] ([i915#2868]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (42 -> 38) -- Additional (1): fi-byt-j1900 Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9570 -> Patchwork_19303 CI-20190529: 20190529 CI_DRM_9570: 0c67d33cc01c40bc40213adb42e6420db337bb84 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5952: c946985af198e8f859c3c08fd562b09686fa387b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19303: 6e0b18efc188ea6ba3d95227f5422c87974ecb81 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6e0b18efc188 drm/i915/adl_s: Add ADL-S platform info and PCI ids 8370ee3ba04f drm/i915/tgl: Use TGL stepping info for applying WAs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use TGL stepping info and add ADLS platform changes
== Series Details == Series: Use TGL stepping info and add ADLS platform changes URL : https://patchwork.freedesktop.org/series/85639/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8370ee3ba04f drm/i915/tgl: Use TGL stepping info for applying WAs -:198: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #198: FILE: drivers/gpu/drm/i915/i915_drv.h:1595: +#define IS_TGL_DISP_STEPPING(p, since, until) \ (IS_TIGERLAKE(p) && \ +tgl_stepping_get(p)->disp_stepping >= (since) && \ +tgl_stepping_get(p)->disp_stepping <= (until)) -:206: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #206: FILE: drivers/gpu/drm/i915/i915_drv.h:1600: +#define IS_TGL_UY_GT_STEPPING(p, since, until) \ ((IS_TGL_U(p) || IS_TGL_Y(p)) && \ +tgl_stepping_get(p)->gt_stepping >= (since) && \ +tgl_stepping_get(p)->gt_stepping <= (until)) -:214: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #214: FILE: drivers/gpu/drm/i915/i915_drv.h:1605: +#define IS_TGL_GT_STEPPING(p, since, until) \ (IS_TIGERLAKE(p) && \ !(IS_TGL_U(p) || IS_TGL_Y(p)) && \ +tgl_stepping_get(p)->gt_stepping >= (since) && \ +tgl_stepping_get(p)->gt_stepping <= (until)) total: 0 errors, 0 warnings, 3 checks, 182 lines checked 6e0b18efc188 drm/i915/adl_s: Add ADL-S platform info and PCI ids -:123: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #123: FILE: drivers/gpu/drm/i915/i915_drv.h:1639: +#define IS_ADLS_DISP_STEPPING(p, since, until) \ + (IS_ALDERLAKE_S(p) && \ +tgl_stepping_get(p)->disp_stepping >= (since) && \ +tgl_stepping_get(p)->disp_stepping <= (until)) -:128: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #128: FILE: drivers/gpu/drm/i915/i915_drv.h:1644: +#define IS_ADLS_GT_STEPPING(p, since, until) \ + (IS_ALDERLAKE_S(p) && \ +tgl_stepping_get(p)->gt_stepping >= (since) && \ +tgl_stepping_get(p)->gt_stepping <= (until)) -:200: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #200: FILE: include/drm/i915_pciids.h:638: +#define INTEL_ADLS_IDS(info) \ + INTEL_VGA_DEVICE(0x4680, info), \ + INTEL_VGA_DEVICE(0x4681, info), \ + INTEL_VGA_DEVICE(0x4682, info), \ + INTEL_VGA_DEVICE(0x4683, info), \ + INTEL_VGA_DEVICE(0x4690, info), \ + INTEL_VGA_DEVICE(0x4691, info), \ + INTEL_VGA_DEVICE(0x4692, info), \ + INTEL_VGA_DEVICE(0x4693, info) -:200: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #200: FILE: include/drm/i915_pciids.h:638: +#define INTEL_ADLS_IDS(info) \ + INTEL_VGA_DEVICE(0x4680, info), \ + INTEL_VGA_DEVICE(0x4681, info), \ + INTEL_VGA_DEVICE(0x4682, info), \ + INTEL_VGA_DEVICE(0x4683, info), \ + INTEL_VGA_DEVICE(0x4690, info), \ + INTEL_VGA_DEVICE(0x4691, info), \ + INTEL_VGA_DEVICE(0x4692, info), \ + INTEL_VGA_DEVICE(0x4693, info) total: 1 errors, 0 warnings, 3 checks, 128 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Async flips for all ilk+ platforms
== Series Details ==
Series: drm/i915: Async flips for all ilk+ platforms
URL : https://patchwork.freedesktop.org/series/85627/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9567_full -> Patchwork_19297_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19297_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19297_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19297_full:
### IGT changes ###
Possible regressions
* igt@kms_big_fb@x-tiled-16bpp-rotate-0:
- shard-hsw: [PASS][1] -> [FAIL][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-hsw2/igt@kms_big...@x-tiled-16bpp-rotate-0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/shard-hsw6/igt@kms_big...@x-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-180:
- shard-snb: [PASS][3] -> [FAIL][4] +5 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-snb5/igt@kms_big...@x-tiled-16bpp-rotate-180.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/shard-snb6/igt@kms_big...@x-tiled-16bpp-rotate-180.html
- shard-hsw: NOTRUN -> [FAIL][5] +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/shard-hsw2/igt@kms_big...@x-tiled-16bpp-rotate-180.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-onscreen:
- shard-hsw: NOTRUN -> [INCOMPLETE][6]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/shard-hsw4/igt@kms_cursor_...@pipe-c-cursor-256x85-onscreen.html
Warnings
* igt@kms_async_flips@invalid-async-flip:
- shard-hsw: [SKIP][7] ([fdo#109271]) -> [FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-hsw4/igt@kms_async_fl...@invalid-async-flip.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/shard-hsw2/igt@kms_async_fl...@invalid-async-flip.html
- shard-snb: [SKIP][9] ([fdo#109271]) -> [FAIL][10] +1 similar
issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-snb6/igt@kms_async_fl...@invalid-async-flip.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/shard-snb5/igt@kms_async_fl...@invalid-async-flip.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2}:
- shard-iclb: [SKIP][11] ([i915#2920]) -> [SKIP][12] +1 similar
issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-iclb2/igt@kms_psr2...@primary-plane-update-sf-dmg-area-2.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/shard-iclb5/igt@kms_psr2...@primary-plane-update-sf-dmg-area-2.html
Known issues
Here are the changes found in Patchwork_19297_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@engines-mixed:
- shard-hsw: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099]) +4
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/shard-hsw2/igt@gem_ctx_persiste...@engines-mixed.html
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1099]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/shard-snb6/igt@gem_ctx_persiste...@engines-mixed.html
* igt@gem_exec_reloc@basic-wide-active@bcs0:
- shard-skl: NOTRUN -> [FAIL][15] ([i915#2389]) +3 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/shard-skl10/igt@gem_exec_reloc@basic-wide-act...@bcs0.html
- shard-hsw: NOTRUN -> [FAIL][16] ([i915#2389]) +3 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/shard-hsw4/igt@gem_exec_reloc@basic-wide-act...@bcs0.html
* igt@gem_media_vme:
- shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271]) +151 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/shard-skl9/igt@gem_media_vme.html
* igt@gem_pread@exhaustion:
- shard-hsw: NOTRUN -> [WARN][18] ([i915#2658])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/shard-hsw2/igt@gem_pr...@exhaustion.html
* igt@gem_userptr_blits@process-exit-mmap-busy@uc:
- shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#1699]) +3
similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/shard-skl9/igt@gem_userptr_blits@process-exit-mmap-b...@uc.html
*
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Exercise lrc_wa_ctx initialisation failure (rev2)
== Series Details == Series: drm/i915/gt: Exercise lrc_wa_ctx initialisation failure (rev2) URL : https://patchwork.freedesktop.org/series/85632/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9569 -> Patchwork_19302 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19302 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19302, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19302/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19302: ### IGT changes ### Possible regressions * igt@i915_selftest@live@hugepages: - fi-bsw-kefka: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/fi-bsw-kefka/igt@i915_selftest@l...@hugepages.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19302/fi-bsw-kefka/igt@i915_selftest@l...@hugepages.html Known issues Here are the changes found in Patchwork_19302 that come from known issues: ### IGT changes ### Issues hit * igt@i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19302/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html * igt@i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][5] -> [INCOMPLETE][6] ([i915#142] / [i915#2405]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/fi-byt-j1900/igt@i915_pm_...@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19302/fi-byt-j1900/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@gem_contexts: - fi-bsw-kefka: [PASS][7] -> [SKIP][8] ([fdo#109271]) +10 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19302/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7500u: [PASS][9] -> [DMESG-FAIL][10] ([i915#165]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19302/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html * igt@runner@aborted: - fi-bsw-kefka: NOTRUN -> [FAIL][11] ([i915#1436]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19302/fi-bsw-kefka/igt@run...@aborted.html - fi-bdw-5557u: NOTRUN -> [FAIL][12] ([i915#2029]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19302/fi-bdw-5557u/igt@run...@aborted.html - fi-byt-j1900: NOTRUN -> [FAIL][13] ([i915#1814] / [i915#2505]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19302/fi-byt-j1900/igt@run...@aborted.html Possible fixes * igt@gem_tiled_blits@basic: - fi-tgl-y: [DMESG-WARN][14] ([i915#402]) -> [PASS][15] +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/fi-tgl-y/igt@gem_tiled_bl...@basic.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19302/fi-tgl-y/igt@gem_tiled_bl...@basic.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405 [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 38) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9569 -> Patchwork_19302 CI-20190529: 20190529 CI_DRM_9569: 15909dfd09f8c62cd3df8645239a7a8c3f056c81 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5951: fec3b9c7d88357144f0d7a1447b9316a1c81da1a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19302: 808e0e01d133df5e37136f1c702c6a81eb9e6d80 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 808e0e01d133 drm/i915/gt: Exercise lrc_wa_ctx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg1: Update voltage swing tables for DP (rev3)
== Series Details == Series: drm/i915/dg1: Update voltage swing tables for DP (rev3) URL : https://patchwork.freedesktop.org/series/84611/ State : success == Summary == CI Bug Log - changes from CI_DRM_9569 -> Patchwork_19301 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19301/index.html Known issues Here are the changes found in Patchwork_19301 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s0: - fi-snb-2600:[PASS][1] -> [DMESG-WARN][2] ([i915#2772]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/fi-snb-2600/igt@gem_exec_susp...@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19301/fi-snb-2600/igt@gem_exec_susp...@basic-s0.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#2411] / [i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19301/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live@gtt: - fi-kbl-soraka: [PASS][5] -> [INCOMPLETE][6] ([i915#2826]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/fi-kbl-soraka/igt@i915_selftest@l...@gtt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19301/fi-kbl-soraka/igt@i915_selftest@l...@gtt.html * igt@prime_vgem@basic-userptr: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/fi-tgl-y/igt@prime_v...@basic-userptr.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19301/fi-tgl-y/igt@prime_v...@basic-userptr.html * igt@runner@aborted: - fi-kbl-soraka: NOTRUN -> [FAIL][9] ([i915#1436] / [i915#2295]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19301/fi-kbl-soraka/igt@run...@aborted.html - fi-snb-2600:NOTRUN -> [FAIL][10] ([i915#698]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19301/fi-snb-2600/igt@run...@aborted.html Possible fixes * igt@gem_tiled_blits@basic: - fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/fi-tgl-y/igt@gem_tiled_bl...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19301/fi-tgl-y/igt@gem_tiled_bl...@basic.html [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772 [i915#2826]: https://gitlab.freedesktop.org/drm/intel/issues/2826 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#698]: https://gitlab.freedesktop.org/drm/intel/issues/698 Participating hosts (43 -> 37) -- Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9569 -> Patchwork_19301 CI-20190529: 20190529 CI_DRM_9569: 15909dfd09f8c62cd3df8645239a7a8c3f056c81 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5951: fec3b9c7d88357144f0d7a1447b9316a1c81da1a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19301: b7572f7a88deac3a4b83cea4800ad46d69fffb77 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b7572f7a88de drm/i915/dg1: Update voltage swing tables for DP == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19301/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: split out pps and aux (rev2)
== Series Details ==
Series: drm/i915/dp: split out pps and aux (rev2)
URL : https://patchwork.freedesktop.org/series/85167/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9567_full -> Patchwork_19296_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19296_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19296_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19296_full:
### IGT changes ###
Possible regressions
* igt@gem_eio@in-flight-immediate:
- shard-skl: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/shard-skl8/igt@gem_...@in-flight-immediate.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_schedule@u-fairslice@rcs0}:
- shard-apl: [DMESG-WARN][2] ([i915#1610]) -> [DMESG-WARN][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-apl4/igt@gem_exec_schedule@u-fairsl...@rcs0.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/shard-apl3/igt@gem_exec_schedule@u-fairsl...@rcs0.html
* {igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2}:
- shard-iclb: [SKIP][4] ([i915#2920]) -> [SKIP][5] +2 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-iclb2/igt@kms_psr2...@primary-plane-update-sf-dmg-area-2.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/shard-iclb7/igt@kms_psr2...@primary-plane-update-sf-dmg-area-2.html
Known issues
Here are the changes found in Patchwork_19296_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@engines-mixed:
- shard-hsw: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +3
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/shard-hsw6/igt@gem_ctx_persiste...@engines-mixed.html
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/shard-snb7/igt@gem_ctx_persiste...@engines-mixed.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-apl: [PASS][8] -> [FAIL][9] ([i915#2389])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-apl7/igt@gem_exec_reloc@basic-many-act...@rcs0.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/shard-apl4/igt@gem_exec_reloc@basic-many-act...@rcs0.html
* igt@gem_exec_reloc@basic-wide-active@bcs0:
- shard-skl: NOTRUN -> [FAIL][10] ([i915#2389]) +3 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/shard-skl7/igt@gem_exec_reloc@basic-wide-act...@bcs0.html
* igt@gem_media_vme:
- shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271]) +151 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/shard-skl8/igt@gem_media_vme.html
* igt@gem_pread@exhaustion:
- shard-hsw: NOTRUN -> [WARN][12] ([i915#2658])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/shard-hsw7/igt@gem_pr...@exhaustion.html
* igt@gem_userptr_blits@process-exit-mmap-busy@uc:
- shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1699]) +3
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/shard-skl8/igt@gem_userptr_blits@process-exit-mmap-b...@uc.html
* igt@gem_userptr_blits@process-exit-mmap@wc:
- shard-hsw: NOTRUN -> [SKIP][14] ([fdo#109271]) +203 similar
issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/shard-hsw7/igt@gem_userptr_blits@process-exit-m...@wc.html
* igt@gen7_exec_parse@basic-allocation:
- shard-glk: NOTRUN -> [SKIP][15] ([fdo#109271]) +4 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/shard-glk4/igt@gen7_exec_pa...@basic-allocation.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#658])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/shard-kbl1/igt@i915_pm...@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][17] ([i915#454])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/shard-skl8/igt@i915_pm...@dc6-dpms.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827])
+15 similar issues
[18]:
Re: [Intel-gfx] [PATCH 2/2] drm/i915/adl_s: Add ADL-S platform info and PCI ids
On Fri, Jan 08, 2021 at 03:18:53PM -0800, Aditya Swarup wrote:
> From: Caz Yokoyama
>
> - Add the initial platform information for Alderlake-S.
> - Specify ppgtt_size value
> - Add dma_mask_size
> - Add ADLS REVIDs
> - HW tracking(Selective Update Tracking Enable) has been
> removed from ADLS. Disable PSR2 till we enable software/
> manual tracking.
>
> v2:
> - Add support for different ADLS SOC steppings to select
> correct GT/DISP stepping based on Bspec 53655 based on
> feedback from Matt Roper.(aswarup)
>
> v3:
> - Make display/gt steppings info generic for reuse with TGL and ADLS.
> - Modify the macros to reuse tgl_revids_get()
> - Add HTI support to adls device info.(mdroper)
>
> v4:
> - Rebase on TGL patch for applying WAs based on stepping info from
> Matt Roper's feedback.(aswarup)
>
> Bspec: 53597
> Bspec: 53648
> Bspec: 53655
> Bspec: 48028
> Bspec: 53650
> BSpec: 50422
>
> Cc: José Roberto de Souza
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Cc: Anusha Srivatsa
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Signed-off-by: Caz Yokoyama
> Signed-off-by: Aditya Swarup
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++
> drivers/gpu/drm/i915/i915_drv.h | 27 -
> drivers/gpu/drm/i915/i915_pci.c | 13 ++
> drivers/gpu/drm/i915/intel_device_info.c| 1 +
> drivers/gpu/drm/i915/intel_device_info.h| 1 +
> include/drm/i915_pciids.h | 11 +
> 6 files changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 111d01e2f81e..c89bd653af17 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -84,6 +84,14 @@ const struct i915_rev_steppings tgl_revid_step_tbl[] = {
> [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
> };
>
> +const struct i915_rev_steppings adls_revid_step_tbl[] = {
> + [ADLS_REVID_A0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
> + [ADLS_REVID_A2] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 },
> + [ADLS_REVID_B0] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
> + [ADLS_REVID_G0] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
> + [ADLS_REVID_C0] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 },
> +};
Now that we've disassociated IP steppings from revision ID, I don't
think we should use stepping terminology for the constant inputs to the
array anymore. The terms you're using seem to roughly correspond to
what the bspec refers to as "SOC stepping" but even that's not terribly
accurate since, for example, PCI revision ID 0xC is used for SoC
steppings C0, C1, D0, and H0. I'd just use the exact numeric PCI ID as
documented in the bspec to remove any ambiguity:
const struct i915_rev_steppings adls_revid_step_tbl[] = {
[0x0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
[0x1] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 },
[0x4] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
[0x8] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
[0xC] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 },
};
That also matches how we're indexing into the TGL arrays.
Matt
> +
> static void wa_init_start(struct i915_wa_list *wal, const char *name, const
> char *engine_name)
> {
> wal->name = name;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 11d6e8abde46..8d8a046a7b0c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1417,6 +1417,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
> #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
> #define IS_DG1(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG1)
> +#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
> @@ -1560,6 +1561,7 @@ extern const struct i915_rev_steppings kbl_revids[];
>
> enum {
> STEP_A0,
> + STEP_A2,
> STEP_B0,
> STEP_B1,
> STEP_C0,
> @@ -1568,9 +1570,11 @@ enum {
>
> #define TGL_UY_REVID_STEP_TBL_SIZE 4
> #define TGL_REVID_STEP_TBL_SIZE 2
> +#define ADLS_REVID_STEP_TBL_SIZE 13
>
> extern const struct i915_rev_steppings
> tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
> extern const struct i915_rev_steppings
> tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
> +extern const struct i915_rev_steppings
> adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE];
>
> static inline const struct
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/backlight: fix CPU mode backlight takeover on LPT
== Series Details == Series: drm/i915/backlight: fix CPU mode backlight takeover on LPT URL : https://patchwork.freedesktop.org/series/85619/ State : success == Summary == CI Bug Log - changes from CI_DRM_9567_full -> Patchwork_19295_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19295_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-mixed: - shard-hsw: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-hsw4/igt@gem_ctx_persiste...@engines-mixed.html - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-snb6/igt@gem_ctx_persiste...@engines-mixed.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-skl: NOTRUN -> [FAIL][3] ([i915#2389]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-skl2/igt@gem_exec_reloc@basic-wide-act...@bcs0.html - shard-hsw: NOTRUN -> [FAIL][4] ([i915#2389]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-hsw7/igt@gem_exec_reloc@basic-wide-act...@bcs0.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][5] ([i915#2389]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-iclb2/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@gem_exec_whisper@basic-normal-all: - shard-skl: NOTRUN -> [DMESG-WARN][6] ([i915#1982]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-skl5/igt@gem_exec_whis...@basic-normal-all.html * igt@gem_media_vme: - shard-skl: NOTRUN -> [SKIP][7] ([fdo#109271]) +152 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-skl7/igt@gem_media_vme.html * igt@gem_pread@exhaustion: - shard-hsw: NOTRUN -> [WARN][8] ([i915#2658]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-hsw7/igt@gem_pr...@exhaustion.html * igt@gem_userptr_blits@process-exit-mmap-busy@uc: - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1699]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-skl7/igt@gem_userptr_blits@process-exit-mmap-b...@uc.html * igt@gem_userptr_blits@process-exit-mmap@wc: - shard-hsw: NOTRUN -> [SKIP][10] ([fdo#109271]) +259 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-hsw7/igt@gem_userptr_blits@process-exit-m...@wc.html * igt@gen7_exec_parse@basic-allocation: - shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-glk7/igt@gen7_exec_pa...@basic-allocation.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-kbl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#658]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-kbl4/igt@i915_pm...@dc3co-vpb-simulation.html * igt@i915_pm_dc@dc6-dpms: - shard-skl: NOTRUN -> [FAIL][13] ([i915#454]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-skl7/igt@i915_pm...@dc6-dpms.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-hsw: [PASS][14] -> [WARN][15] ([i915#1519]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-hsw7/igt@i915_pm_rc6_reside...@rc6-fence.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-hsw6/igt@i915_pm_rc6_reside...@rc6-fence.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2597]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-tglb5/igt@kms_async_fl...@test-time-stamp.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-tglb3/igt@kms_async_fl...@test-time-stamp.html * igt@kms_chamelium@hdmi-aspect-ratio: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +15 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-skl7/igt@kms_chamel...@hdmi-aspect-ratio.html * igt@kms_color@pipe-b-ctm-0-25: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-skl9/igt@kms_co...@pipe-b-ctm-0-25.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/shard-skl9/igt@kms_co...@pipe-b-ctm-0-25.html * igt@kms_color_chamelium@pipe-d-gamma: - shard-hsw: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +19 similar issues [21]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Remove unused function 'dword_in_page'
== Series Details == Series: drm/i915/gt: Remove unused function 'dword_in_page' URL : https://patchwork.freedesktop.org/series/85634/ State : success == Summary == CI Bug Log - changes from CI_DRM_9569 -> Patchwork_19300 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/index.html Known issues Here are the changes found in Patchwork_19300 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ringfill@basic-all: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/fi-tgl-y/igt@gem_ringf...@basic-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/fi-tgl-y/igt@gem_ringf...@basic-all.html * igt@i915_pm_rpm@module-reload: - fi-kbl-7500u: [PASS][3] -> [DMESG-WARN][4] ([i915#2605]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/fi-kbl-7500u/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/fi-kbl-7500u/igt@i915_pm_...@module-reload.html Possible fixes * igt@gem_tiled_blits@basic: - fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9569/fi-tgl-y/igt@gem_tiled_bl...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/fi-tgl-y/igt@gem_tiled_bl...@basic.html [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 38) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9569 -> Patchwork_19300 CI-20190529: 20190529 CI_DRM_9569: 15909dfd09f8c62cd3df8645239a7a8c3f056c81 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5951: fec3b9c7d88357144f0d7a1447b9316a1c81da1a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19300: c0032a656fa581df713b31ba0efcd34a353574ac @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c0032a656fa5 drm/i915/gt: Remove unused function 'dword_in_page' == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19300/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
On Fri, Jan 08, 2021 at 03:18:52PM -0800, Aditya Swarup wrote:
> TGL adds another level of indirection for applying WA based on stepping
> information rather than PCI REVID. So change TGL_REVID enum into
> stepping enum and use PCI REVID as index into revid to stepping table to
> fetch correct display and GT stepping for application of WAs as
> suggested by Matt Roper.
So to clarify the goal is to rename "revid" -> "stepping" because the
values like "A1," "C0," etc. are't the actual PCI revision ID, but
rather descriptions of the stepping of a given IP block; the enum values
we use to represent those are arbitrary and don't matter as long as
they're monotonically increasing for comparisons. The PCI revision ID
is just the input we use today to deduce what the IP steppings are, and
there's talk that we could determine the IP steppings in a different way
at some point in the future.
Furthermore, since the same scheme will be used at least for ADL-S, we
should drop the "TGL" prefix since there's no need to name these general
enum values in a platform-specific manner.
Reviewed-by: Matt Roper
We should probably make the same kind of change to KBL (and use the same
stepping enum) too since it has the same kind of extra indirection as
TGL/ADL-S, but we can do that as a followup patch.
Matt
>
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Cc: José Roberto de Souza
> Signed-off-by: Aditya Swarup
> ---
> .../drm/i915/display/intel_display_power.c| 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 4 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 +-
> drivers/gpu/drm/i915/i915_drv.h | 50 +--
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 6 files changed, 43 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index d52374f01316..bb04b502a442 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private
> *dev_priv)
> int config, i;
>
> if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> + IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
> /* Wa_1409767108:tgl,dg1 */
> table = wa_1409767108_buddy_page_masks;
> else
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index c24ae69426cf..a93717178957 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>
> if (dev_priv->psr.psr2_sel_fetch_enabled) {
> /* WA 1408330847 */
> - if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> + if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
> IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
>
> /* WA 1408330847 */
> if (dev_priv->psr.psr2_sel_fetch_enabled &&
> - (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> + (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index cf3589fd0ddb..4ce32df3855f 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -3033,7 +3033,7 @@ static bool gen12_plane_supports_mc_ccs(struct
> drm_i915_private *dev_priv,
> {
> /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
> - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
> + IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
> return false;
>
> return plane_id < PLANE_SPRITE4;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index c21a9726326a..111d01e2f81e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -71,17 +71,17 @@ const struct i915_rev_steppings kbl_revids[] = {
> [7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
> };
>
> -const struct i915_rev_steppings tgl_uy_revids[] = {
> - [0] = {
[Intel-gfx] [PATCH] drm/i915/gt: Mark up a debug-only function
drivers/gpu/drm/i915//gt/intel_workarounds.c:1394:20: error: function
'is_nonpriv_flags_valid' is not needed and will not be emitted
[-Werror,-Wunneeded-internal-declaration]
static inline bool is_nonpriv_flags_valid(u32 flags)
This is only used by debug build, so mark it as maybe-unused to keep the
compiler from complaining.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index c21a9726326a..c52433914d52 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1391,6 +1391,7 @@ bool intel_gt_verify_workarounds(struct intel_gt *gt,
const char *from)
return wa_list_verify(gt->uncore, >i915->gt_wa_list, from);
}
+__maybe_unused
static inline bool is_nonpriv_flags_valid(u32 flags)
{
/* Check only valid flag bits are set */
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Remove unused function 'dword_in_page'
== Series Details == Series: drm/i915/gt: Remove unused function 'dword_in_page' URL : https://patchwork.freedesktop.org/series/85634/ State : warning == Summary == $ dim checkpatch origin/drm-tip c0032a656fa5 drm/i915/gt: Remove unused function 'dword_in_page' -:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #6: >> drivers/gpu/drm/i915/gt/intel_lrc.c:17:28: error: unused function >> 'dword_in_page' [-Werror,-Wunused-function] total: 0 errors, 1 warnings, 0 checks, 11 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/adl_s: Add ADL-S platform info and PCI ids
From: Caz Yokoyama
- Add the initial platform information for Alderlake-S.
- Specify ppgtt_size value
- Add dma_mask_size
- Add ADLS REVIDs
- HW tracking(Selective Update Tracking Enable) has been
removed from ADLS. Disable PSR2 till we enable software/
manual tracking.
v2:
- Add support for different ADLS SOC steppings to select
correct GT/DISP stepping based on Bspec 53655 based on
feedback from Matt Roper.(aswarup)
v3:
- Make display/gt steppings info generic for reuse with TGL and ADLS.
- Modify the macros to reuse tgl_revids_get()
- Add HTI support to adls device info.(mdroper)
v4:
- Rebase on TGL patch for applying WAs based on stepping info from
Matt Roper's feedback.(aswarup)
Bspec: 53597
Bspec: 53648
Bspec: 53655
Bspec: 48028
Bspec: 53650
BSpec: 50422
Cc: José Roberto de Souza
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Signed-off-by: Caz Yokoyama
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++
drivers/gpu/drm/i915/i915_drv.h | 27 -
drivers/gpu/drm/i915/i915_pci.c | 13 ++
drivers/gpu/drm/i915/intel_device_info.c| 1 +
drivers/gpu/drm/i915/intel_device_info.h| 1 +
include/drm/i915_pciids.h | 11 +
6 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 111d01e2f81e..c89bd653af17 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -84,6 +84,14 @@ const struct i915_rev_steppings tgl_revid_step_tbl[] = {
[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
};
+const struct i915_rev_steppings adls_revid_step_tbl[] = {
+ [ADLS_REVID_A0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
+ [ADLS_REVID_A2] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 },
+ [ADLS_REVID_B0] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
+ [ADLS_REVID_G0] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
+ [ADLS_REVID_C0] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 },
+};
+
static void wa_init_start(struct i915_wa_list *wal, const char *name, const
char *engine_name)
{
wal->name = name;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 11d6e8abde46..8d8a046a7b0c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1417,6 +1417,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
#define IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
#define IS_DG1(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG1)
+#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
@@ -1560,6 +1561,7 @@ extern const struct i915_rev_steppings kbl_revids[];
enum {
STEP_A0,
+ STEP_A2,
STEP_B0,
STEP_B1,
STEP_C0,
@@ -1568,9 +1570,11 @@ enum {
#define TGL_UY_REVID_STEP_TBL_SIZE 4
#define TGL_REVID_STEP_TBL_SIZE2
+#define ADLS_REVID_STEP_TBL_SIZE 13
extern const struct i915_rev_steppings
tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
extern const struct i915_rev_steppings
tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
+extern const struct i915_rev_steppings
adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE];
static inline const struct i915_rev_steppings *
tgl_stepping_get(struct drm_i915_private *dev_priv)
@@ -1579,7 +1583,10 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
u8 size;
const struct i915_rev_steppings *revid_step_tbl;
- if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ revid_step_tbl = adls_revid_step_tbl;
+ size = ARRAY_SIZE(adls_revid_step_tbl);
+ } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
revid_step_tbl = tgl_uy_revid_step_tbl;
size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
} else {
@@ -1621,6 +1628,24 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
#define IS_DG1_REVID(p, since, until) \
(IS_DG1(p) && IS_REVID(p, since, until))
+#define ADLS_REVID_A0 0x0
+#define ADLS_REVID_A2 0x1
+#define ADLS_REVID_B0 0x4
+#define ADLS_REVID_G0 0x8
+#define ADLS_REVID_C0 0xC /*Same as H0 ADLS SOC stepping*/
+
+extern const struct i915_rev_steppings adls_revids[];
+
+#define IS_ADLS_DISP_STEPPING(p, since, until) \
+ (IS_ALDERLAKE_S(p) && \
+tgl_stepping_get(p)->disp_stepping >= (since) && \
+tgl_stepping_get(p)->disp_stepping
[Intel-gfx] [PATCH 0/2] Use TGL stepping info and add ADLS platform changes
1. Change TGL REVID enums/macros to TGL stepping info to apply TGL WAs. 2. Add ADL-S platform info and PCI IDs and add TGL style stepping macros for applying WAs. Aditya Swarup (1): drm/i915/tgl: Use TGL stepping info for applying WAs Caz Yokoyama (1): drm/i915/adl_s: Add ADL-S platform info and PCI ids .../drm/i915/display/intel_display_power.c| 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 4 +- drivers/gpu/drm/i915/display/intel_sprite.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 +--- drivers/gpu/drm/i915/i915_drv.h | 79 --- drivers/gpu/drm/i915/i915_pci.c | 13 +++ drivers/gpu/drm/i915/intel_device_info.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 2 +- include/drm/i915_pciids.h | 11 +++ 10 files changed, 104 insertions(+), 45 deletions(-) -- 2.27.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
TGL adds another level of indirection for applying WA based on stepping
information rather than PCI REVID. So change TGL_REVID enum into
stepping enum and use PCI REVID as index into revid to stepping table to
fetch correct display and GT stepping for application of WAs as
suggested by Matt Roper.
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: José Roberto de Souza
Signed-off-by: Aditya Swarup
---
.../drm/i915/display/intel_display_power.c| 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 4 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 +-
drivers/gpu/drm/i915/i915_drv.h | 50 +--
drivers/gpu/drm/i915/intel_pm.c | 2 +-
6 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index d52374f01316..bb04b502a442 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private
*dev_priv)
int config, i;
if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
- IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
+ IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
/* Wa_1409767108:tgl,dg1 */
table = wa_1409767108_buddy_page_masks;
else
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index c24ae69426cf..a93717178957 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
if (dev_priv->psr.psr2_sel_fetch_enabled) {
/* WA 1408330847 */
- if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+ if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK,
@@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
/* WA 1408330847 */
if (dev_priv->psr.psr2_sel_fetch_enabled &&
- (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+ (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index cf3589fd0ddb..4ce32df3855f 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -3033,7 +3033,7 @@ static bool gen12_plane_supports_mc_ccs(struct
drm_i915_private *dev_priv,
{
/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
- IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
+ IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
return false;
return plane_id < PLANE_SPRITE4;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index c21a9726326a..111d01e2f81e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -71,17 +71,17 @@ const struct i915_rev_steppings kbl_revids[] = {
[7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
};
-const struct i915_rev_steppings tgl_uy_revids[] = {
- [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
- [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
- [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
- [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
+const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
+ [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
+ [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
+ [2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
+ [3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
};
/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same
HW */
-const struct i915_rev_steppings tgl_revids[] = {
- [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
- [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
+const struct i915_rev_steppings tgl_revid_step_tbl[] = {
+ [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
+ [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Prevent use of engine->wa_ctx after error
== Series Details == Series: drm/i915/gt: Prevent use of engine->wa_ctx after error URL : https://patchwork.freedesktop.org/series/85618/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9567_full -> Patchwork_19293_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19293_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19293_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19293_full: ### IGT changes ### Possible regressions * igt@gem_partial_pwrite_pread@write-uncached: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-skl6/igt@gem_partial_pwrite_pr...@write-uncached.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/shard-skl7/igt@gem_partial_pwrite_pr...@write-uncached.html Known issues Here are the changes found in Patchwork_19293_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-mixed: - shard-hsw: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/shard-hsw2/igt@gem_ctx_persiste...@engines-mixed.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-skl: NOTRUN -> [FAIL][4] ([i915#2389]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/shard-skl5/igt@gem_exec_reloc@basic-wide-act...@bcs0.html * igt@gem_media_vme: - shard-skl: NOTRUN -> [SKIP][5] ([fdo#109271]) +145 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/shard-skl4/igt@gem_media_vme.html * igt@gem_userptr_blits@process-exit-mmap-busy@uc: - shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1699]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/shard-skl4/igt@gem_userptr_blits@process-exit-mmap-b...@uc.html * igt@gen7_exec_parse@basic-allocation: - shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/shard-glk6/igt@gen7_exec_pa...@basic-allocation.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][8] -> [DMESG-WARN][9] ([i915#1436] / [i915#716]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-skl8/igt@gen9_exec_pa...@allowed-single.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/shard-skl8/igt@gen9_exec_pa...@allowed-single.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-kbl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#658]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/shard-kbl4/igt@i915_pm...@dc3co-vpb-simulation.html * igt@i915_pm_dc@dc6-dpms: - shard-skl: NOTRUN -> [FAIL][11] ([i915#454]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/shard-skl4/igt@i915_pm...@dc6-dpms.html * igt@i915_selftest@live@gt_heartbeat: - shard-skl: [PASS][12] -> [DMESG-FAIL][13] ([i915#2291] / [i915#541]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-skl5/igt@i915_selftest@live@gt_heartbeat.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/shard-skl1/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][14] -> [FAIL][15] ([i915#2521]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-skl1/igt@kms_async_fl...@alternate-sync-async-flip.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/shard-skl4/igt@kms_async_fl...@alternate-sync-async-flip.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2597]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/shard-tglb5/igt@kms_async_fl...@test-time-stamp.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/shard-tglb3/igt@kms_async_fl...@test-time-stamp.html * igt@kms_chamelium@hdmi-aspect-ratio: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +15 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/shard-skl4/igt@kms_chamel...@hdmi-aspect-ratio.html * igt@kms_chamelium@hdmi-hpd-after-suspend: - shard-hsw: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +10 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/shard-hsw2/igt@kms_chamel...@hdmi-hpd-after-suspend.html *
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Exercise lrc_wa_ctx initialisation failure
== Series Details == Series: drm/i915/gt: Exercise lrc_wa_ctx initialisation failure URL : https://patchwork.freedesktop.org/series/85632/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9568 -> Patchwork_19299 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19299 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19299, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19299/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19299: ### IGT changes ### Possible regressions * igt@i915_selftest@live@late_gt_pm: - fi-bsw-n3050: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9568/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19299/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html Known issues Here are the changes found in Patchwork_19299 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#1888]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9568/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19299/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#2411] / [i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9568/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19299/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live@hangcheck: - fi-icl-y: [PASS][7] -> [INCOMPLETE][8] ([i915#926]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9568/fi-icl-y/igt@i915_selftest@l...@hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19299/fi-icl-y/igt@i915_selftest@l...@hangcheck.html * igt@prime_vgem@basic-fence-flip: - fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9568/fi-tgl-y/igt@prime_v...@basic-fence-flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19299/fi-tgl-y/igt@prime_v...@basic-fence-flip.html * igt@runner@aborted: - fi-icl-y: NOTRUN -> [FAIL][11] ([i915#1580] / [i915#2295] / [i915#2724]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19299/fi-icl-y/igt@run...@aborted.html - fi-bsw-n3050: NOTRUN -> [FAIL][12] ([i915#1436]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19299/fi-bsw-n3050/igt@run...@aborted.html Possible fixes * igt@i915_pm_rpm@module-reload: - fi-kbl-guc: [FAIL][13] -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9568/fi-kbl-guc/igt@i915_pm_...@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19299/fi-kbl-guc/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@sanitycheck: - fi-kbl-7500u: [DMESG-WARN][15] ([i915#2605]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9568/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19299/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [DMESG-WARN][17] ([i915#402]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9568/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19299/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1580]: https://gitlab.freedesktop.org/drm/intel/issues/1580 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605 [i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#926]: https://gitlab.freedesktop.org/drm/intel/issues/926 Participating hosts (43 -> 38) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9568 -> Patchwork_19299 CI-20190529: 20190529 CI_DRM_9568:
Re: [Intel-gfx] [PATCH] drm/i915/gt: Exercise lrc_wa_ctx initialisation failure
On Fri, Jan 08, 2021 at 08:51:14PM +, Chris Wilson wrote: > Inject a fault into lrc_init_wa_ctx() to ensure that we can tolerate a > failure to construct the workarounds. > > Signed-off-by: Chris Wilson > Cc: Matt Roper Reviewed-by: Matt Roper > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c > b/drivers/gpu/drm/i915/gt/intel_lrc.c > index 703d9ecc3f7e..f0de3f661042 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -1525,6 +1525,9 @@ int lrc_init_wa_ctx(struct intel_engine_cs *engine) > > __i915_gem_object_flush_map(wa_ctx->vma->obj, 0, batch_ptr - batch); > __i915_gem_object_release_map(wa_ctx->vma->obj); > + > + if (i915_inject_probe_error(engine->i915, -ENODEV)) > + ret = -ENODEV; > if (ret) > lrc_fini_wa_ctx(engine); > > -- > 2.20.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/dg1: Update voltage swing tables for DP
DG1's vswing tables are the same for eDP and HDMI but have slight
differences from ICL/TGL for DP.
v2:
- Use a "_hbr2_hbr3" suffix on the table name to make it more clear
that the same table is used for both HBR2 and HBR3 link rates.
(Swathi)
Bspec: 49291
Cc: Clinton Taylor
Cc: José Roberto de Souza
Cc: Radhakrishna Sripada
Cc: Swathi Dhanavanthri
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 34
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3df6913369bc..a047fd81e433 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -611,6 +611,34 @@ static const struct cnl_ddi_buf_trans
jsl_combo_phy_ddi_translations_edp_hbr2[]
{ 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
};
+static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr[]
= {
+ /* NT mV Trans mV db*/
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+ { 0xA, 0x48, 0x35, 0x00, 0x0A },/* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 },/* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2C, 0x00, 0x13 },/* 350 900 8.2 */
+ { 0xA, 0x43, 0x3F, 0x00, 0x00 },/* 500 500 0.0 */
+ { 0xC, 0x60, 0x36, 0x00, 0x09 },/* 500 700 2.9 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F },/* 500 900 5.1 */
+ { 0xC, 0x60, 0x3F, 0x00, 0x00 },/* 650 700 0.6 */
+ { 0x6, 0x7F, 0x37, 0x00, 0x08 },/* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
+};
+
+static const struct cnl_ddi_buf_trans
dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
+ /* NT mV Trans mV db*/
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+ { 0xA, 0x48, 0x35, 0x00, 0x0A },/* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 },/* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2C, 0x00, 0x13 },/* 350 900 8.2 */
+ { 0xA, 0x43, 0x3F, 0x00, 0x00 },/* 500 500 0.0 */
+ { 0xC, 0x60, 0x36, 0x00, 0x09 },/* 500 700 2.9 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F },/* 500 900 5.1 */
+ { 0xC, 0x58, 0x3F, 0x00, 0x00 },/* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A },/* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
+};
+
struct icl_mg_phy_ddi_buf_trans {
u32 cri_txdeemph_override_11_6;
u32 cri_txdeemph_override_5_0;
@@ -1121,6 +1149,12 @@ icl_get_combo_buf_trans_edp(struct intel_encoder
*encoder,
} else if (dev_priv->vbt.edp.low_vswing) {
*n_entries =
ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
return icl_combo_phy_ddi_translations_edp_hbr2;
+ } else if (IS_DG1(dev_priv) && crtc_state->port_clock > 27) {
+ *n_entries =
ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2_hbr3);
+ return dg1_combo_phy_ddi_translations_dp_hbr2_hbr3;
+ } else if (IS_DG1(dev_priv)) {
+ *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr);
+ return dg1_combo_phy_ddi_translations_dp_hbr;
}
return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
--
2.24.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915/gt: Only disable preemption on gen8 render engines
Hi Chris, On Thu, Jan 07, 2021 at 10:17:23PM +, Chris Wilson wrote: > The reason why we did not enable preemption on Broadwater was due to > missing GPGPU workarounds. Since this only applies to rcs0, only > restrict rcs0 (and our global capabilities). > > While this does not affect exposing a preemption capability to > userspace, it does affect our internal decisions on whether to use > timeslicing and semaphores between individual engines. > > Signed-off-by: Chris Wilson Reviewed-by: Andi Shyti Thanks, Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/7] drm/i915/gt: Prevent use of engine->wa_ctx after error
== Series Details == Series: series starting with [CI,1/7] drm/i915/gt: Prevent use of engine->wa_ctx after error URL : https://patchwork.freedesktop.org/series/85631/ State : success == Summary == CI Bug Log - changes from CI_DRM_9567 -> Patchwork_19298 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/index.html Known issues Here are the changes found in Patchwork_19298 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html * igt@i915_selftest@live@execlists: - fi-icl-y: [PASS][2] -> [INCOMPLETE][3] ([i915#1037] / [i915#2276]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-icl-y/igt@i915_selftest@l...@execlists.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/fi-icl-y/igt@i915_selftest@l...@execlists.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [PASS][4] -> [DMESG-WARN][5] ([i915#402]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html * igt@runner@aborted: - fi-icl-y: NOTRUN -> [FAIL][6] ([i915#1580] / [i915#2295] / [i915#2724]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/fi-icl-y/igt@run...@aborted.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-tgl-y/igt@debugfs_test@read_all_entries.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@i915_selftest@live@gem: - fi-kbl-soraka: [DMESG-FAIL][9] -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-kbl-soraka/igt@i915_selftest@l...@gem.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/fi-kbl-soraka/igt@i915_selftest@l...@gem.html * igt@i915_selftest@live@reset: - fi-kbl-soraka: [SKIP][11] ([fdo#109271]) -> [PASS][12] +12 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-kbl-soraka/igt@i915_selftest@l...@reset.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/fi-kbl-soraka/igt@i915_selftest@l...@reset.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037 [i915#1580]: https://gitlab.freedesktop.org/drm/intel/issues/1580 [i915#2276]: https://gitlab.freedesktop.org/drm/intel/issues/2276 [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295 [i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 38) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9567 -> Patchwork_19298 CI-20190529: 20190529 CI_DRM_9567: 9fc1f6dac2ec9339e390931322768a0286f01f71 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5951: fec3b9c7d88357144f0d7a1447b9316a1c81da1a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19298: 29bd98e3a6a3659519404350abf0508042fde167 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 29bd98e3a6a3 drm/i915/gt: Disable arbitration on no-preempt requests bd79ef49bf52 drm/i915/gt: Only disable preemption on gen8 render engines b9b17d26acb3 drm/i915/gt: Only retire on the last breadcrumb if the last request d84e74909312 drm/i915/gt: Restore ce->signal flush before releasing virtual engine 0e9b79e3d075 drm/i915/selftests: Rearrange ktime_get to reduce latency against CS d55691482444 drm/i915/selftests: Skip unstable timing measurements fe89d2253481 drm/i915/gt: Prevent use of engine->wa_ctx after error == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19298/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Disable RPM wakeref assertions during driver shutdown
Quoting Hans de Goede (2021-01-05 15:25:56)
> Hi,
>
> On 1/4/21 9:39 PM, Chris Wilson wrote:
> > As with the regular suspend paths, also disable the wakeref assertions
> > as we disable the driver during shutdown.
> >
> > Reported-by: Hans de Goede
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2899
> > Fixes: fe0f1e3bfdfe ("drm/i915: Shut down displays gracefully on reboot")
> > Signed-off-by: Chris Wilson
> > Cc: Ville Syrjälä
> > Cc: Hans de Goede
>
> Thanks, I can confirm that this patch fixes the warn/backtrace on
> shutdown/reboot:
>
> Tested-by: Hans de Goede
Thanks for the report, and thanks Ville for double checking.
Pushed,
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915/selftests: Skip unstable timing measurements
Hi Chris, > > > diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c > > > b/drivers/gpu/drm/i915/selftests/intel_memory_region.c > > > index 75839db63bea..59c58a276677 100644 > > > --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c > > > +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c > > > @@ -852,6 +852,9 @@ static int _perf_memcpy(struct intel_memory_region > > > *src_mr, > > > } > > > > > > sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, > > > NULL); > > > + if (!t[0]) > > > + continue; > > > + > > > > are you assuming here that if t[0] is '0', also the rest of 't' > > is '0'? > > It's sorted into ascending order with ktime_t... Hmm, s64 not u64 as I > presumed. So better to check <= 0. by division by 0 I guess you mean here: div64_u64(mul_u32_u32(4 * size, 1000 * 1000 * 1000), t[1] + 2 * t[2] + t[3]) >> 20); why are you testing t[0]? Did I miss anything else? Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix HTI port checking
== Series Details == Series: drm/i915: Fix HTI port checking URL : https://patchwork.freedesktop.org/series/85615/ State : success == Summary == CI Bug Log - changes from CI_DRM_9566_full -> Patchwork_19292_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19292_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-2x: - shard-tglb: NOTRUN -> [SKIP][1] ([i915#1839]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-tglb6/igt@feature_discov...@display-2x.html * igt@gem_ctx_persistence@processes: - shard-hsw: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-hsw7/igt@gem_ctx_persiste...@processes.html * igt@gem_exec_whisper@basic-queues-all: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-glk5/igt@gem_exec_whis...@basic-queues-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-glk1/igt@gem_exec_whis...@basic-queues-all.html * igt@gem_pread@exhaustion: - shard-hsw: NOTRUN -> [WARN][5] ([i915#2658]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-hsw7/igt@gem_pr...@exhaustion.html * igt@gem_userptr_blits@process-exit-mmap@wc: - shard-hsw: NOTRUN -> [SKIP][6] ([fdo#109271]) +145 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-hsw7/igt@gem_userptr_blits@process-exit-m...@wc.html * igt@gen3_render_mixed_blits: - shard-skl: NOTRUN -> [SKIP][7] ([fdo#109271]) +15 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-skl6/igt@gen3_render_mixed_blits.html * igt@gen9_exec_parse@bb-start-cmd: - shard-tglb: NOTRUN -> [SKIP][8] ([fdo#112306]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-tglb6/igt@gen9_exec_pa...@bb-start-cmd.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#658]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-skl2/igt@i915_pm...@dc3co-vpb-simulation.html * igt@i915_selftest@live@gt_lrc: - shard-tglb: NOTRUN -> [DMESG-FAIL][10] ([i915#2373]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-tglb6/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@gt_pm: - shard-tglb: NOTRUN -> [DMESG-FAIL][11] ([i915#1759] / [i915#2291]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-tglb6/igt@i915_selftest@live@gt_pm.html * igt@kms_ccs@pipe-c-missing-ccs-buffer: - shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111304]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-skl2/igt@kms_...@pipe-c-missing-ccs-buffer.html * igt@kms_color@pipe-a-ctm-0-75: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl2/igt@kms_co...@pipe-a-ctm-0-75.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-skl10/igt@kms_co...@pipe-a-ctm-0-75.html * igt@kms_color_chamelium@pipe-b-ctm-0-75: - shard-tglb: NOTRUN -> [SKIP][15] ([fdo#109284] / [fdo#111827]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-tglb6/igt@kms_color_chamel...@pipe-b-ctm-0-75.html * igt@kms_color_chamelium@pipe-d-gamma: - shard-hsw: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +11 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-hsw7/igt@kms_color_chamel...@pipe-d-gamma.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen: - shard-skl: NOTRUN -> [FAIL][17] ([i915#54]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-skl2/igt@kms_cursor_...@pipe-a-cursor-128x42-onscreen.html * igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding: - shard-skl: [PASS][18] -> [FAIL][19] ([i915#54]) +5 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl6/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-skl4/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html * igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#109279]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/shard-tglb6/igt@kms_cursor_...@pipe-d-cursor-512x512-sliding.html * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic: - shard-tglb:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/7] drm/i915/gt: Prevent use of engine->wa_ctx after error
== Series Details == Series: series starting with [CI,1/7] drm/i915/gt: Prevent use of engine->wa_ctx after error URL : https://patchwork.freedesktop.org/series/85631/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:869:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block ___ Intel-gfx mailing list
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/7] drm/i915/gt: Prevent use of engine->wa_ctx after error
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/gt: Prevent use of
engine->wa_ctx after error
URL : https://patchwork.freedesktop.org/series/85631/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fe89d2253481 drm/i915/gt: Prevent use of engine->wa_ctx after error
d55691482444 drm/i915/selftests: Skip unstable timing measurements
0e9b79e3d075 drm/i915/selftests: Rearrange ktime_get to reduce latency against
CS
d84e74909312 drm/i915/gt: Restore ce->signal flush before releasing virtual
engine
-:14: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit bab0557c8dca ("drm/i915/gt:
Remove virtual breadcrumb before transfer")'
#14:
bab0557c8dca ("drm/i915/gt: Remove virtual breadcrumb before transfer"),
total: 1 errors, 0 warnings, 0 checks, 90 lines checked
b9b17d26acb3 drm/i915/gt: Only retire on the last breadcrumb if the last request
bd79ef49bf52 drm/i915/gt: Only disable preemption on gen8 render engines
29bd98e3a6a3 drm/i915/gt: Disable arbitration on no-preempt requests
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gt: Remove unused function 'dword_in_page'
>> drivers/gpu/drm/i915/gt/intel_lrc.c:17:28: error: unused function
>> 'dword_in_page' [-Werror,-Wunused-function]
static inline unsigned int dword_in_page(void *addr)
Reported-by: kernel test robot
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index f0de3f661042..855bd6e70dd7 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -14,11 +14,6 @@
#include "intel_ring.h"
#include "shmem_utils.h"
-static inline unsigned int dword_in_page(void *addr)
-{
- return offset_in_page(addr) / sizeof(u32);
-}
-
static void set_offsets(u32 *regs,
const u8 *data,
const struct intel_engine_cs *engine,
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [drm-intel:drm-intel-gt-next 3/48] drivers/gpu/drm/i915/gt/intel_lrc.c:17:28: error: unused function 'dword_in_page'
tree: git://anongit.freedesktop.org/drm-intel drm-intel-gt-next
head: 4386b8e5ad71c0fc0b6b6088d7c70dc5d903863a
commit: a0d3fdb628b83e3a24acbf6915ede9359a1ecc2b [3/48] drm/i915/gt: Split
logical ring contexts from execlist submission
config: x86_64-randconfig-r011-20210108 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
5c951623bc8965fa1e89660f2f5f4a2944e4981a)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
git remote add drm-intel git://anongit.freedesktop.org/drm-intel
git fetch --no-tags drm-intel drm-intel-gt-next
git checkout a0d3fdb628b83e3a24acbf6915ede9359a1ecc2b
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gt/intel_lrc.c:17:28: error: unused function
>> 'dword_in_page' [-Werror,-Wunused-function]
static inline unsigned int dword_in_page(void *addr)
^
1 error generated.
vim +/dword_in_page +17 drivers/gpu/drm/i915/gt/intel_lrc.c
16
> 17 static inline unsigned int dword_in_page(void *addr)
18 {
19 return offset_in_page(addr) / sizeof(u32);
20 }
21
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gt: Exercise lrc_wa_ctx initialisation failure
Inject a fault into lrc_init_wa_ctx() to ensure that we can tolerate a failure to construct the workarounds. Signed-off-by: Chris Wilson Cc: Matt Roper --- drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 703d9ecc3f7e..f0de3f661042 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1525,6 +1525,9 @@ int lrc_init_wa_ctx(struct intel_engine_cs *engine) __i915_gem_object_flush_map(wa_ctx->vma->obj, 0, batch_ptr - batch); __i915_gem_object_release_map(wa_ctx->vma->obj); + + if (i915_inject_probe_error(engine->i915, -ENODEV)) + ret = -ENODEV; if (ret) lrc_fini_wa_ctx(engine); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 4/7] drm/i915/gt: Restore ce->signal flush before releasing virtual engine
Before we mark the virtual engine as no longer inflight, flush any
ongoing signaling that may be using the ce->signal_link along the
previous breadcrumbs. On switch to a new physical engine, that link will
be inserted into the new set of breadcrumbs, causing confusion to an
ongoing iterator.
This patch undoes a last minute mistake introduced into commit
bab0557c8dca ("drm/i915/gt: Remove virtual breadcrumb before transfer"),
whereby instead of unconditionally applying the flush, it was only
applied if the request itself was going to be reused.
v2: Generalise and cancel all remaining ce->signals
Fixes: bab0557c8dca ("drm/i915/gt: Remove virtual breadcrumb before transfer")
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 33 +++
drivers/gpu/drm/i915/gt/intel_breadcrumbs.h | 4 +++
.../drm/i915/gt/intel_execlists_submission.c | 25 ++
3 files changed, 47 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index 2eabb9ab5d47..7137b6f24f55 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -472,6 +472,39 @@ void i915_request_cancel_breadcrumb(struct i915_request
*rq)
i915_request_put(rq);
}
+void intel_context_remove_breadcrumbs(struct intel_context *ce,
+ struct intel_breadcrumbs *b)
+{
+ struct i915_request *rq, *rn;
+ bool release = false;
+ unsigned long flags;
+
+ spin_lock_irqsave(>signal_lock, flags);
+
+ if (list_empty(>signals))
+ goto unlock;
+
+ list_for_each_entry_safe(rq, rn, >signals, signal_link) {
+ GEM_BUG_ON(!__i915_request_is_complete(rq));
+ if (!test_and_clear_bit(I915_FENCE_FLAG_SIGNAL,
+ >fence.flags))
+ continue;
+
+ list_del_rcu(>signal_link);
+ irq_signal_request(rq, b);
+ i915_request_put(rq);
+ }
+ release = remove_signaling_context(b, ce);
+
+unlock:
+ spin_unlock_irqrestore(>signal_lock, flags);
+ if (release)
+ intel_context_put(ce);
+
+ while (atomic_read(>signaler_active))
+ cpu_relax();
+}
+
static void print_signals(struct intel_breadcrumbs *b, struct drm_printer *p)
{
struct intel_context *ce;
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
index 75cc9cff3ae3..3ce5ce270b04 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
@@ -6,6 +6,7 @@
#ifndef __INTEL_BREADCRUMBS__
#define __INTEL_BREADCRUMBS__
+#include
#include
#include "intel_engine_types.h"
@@ -44,4 +45,7 @@ void intel_engine_print_breadcrumbs(struct intel_engine_cs
*engine,
bool i915_request_enable_breadcrumb(struct i915_request *request);
void i915_request_cancel_breadcrumb(struct i915_request *request);
+void intel_context_remove_breadcrumbs(struct intel_context *ce,
+ struct intel_breadcrumbs *b);
+
#endif /* __INTEL_BREADCRUMBS__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 2f8e10450f7e..eb69eef9d7db 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -581,21 +581,6 @@ resubmit_virtual_request(struct i915_request *rq, struct
virtual_engine *ve)
{
struct intel_engine_cs *engine = rq->engine;
- /* Flush concurrent rcu iterators in signal_irq_work */
- if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >fence.flags)) {
- /*
-* After this point, the rq may be transferred to a new
-* sibling, so before we clear ce->inflight make sure that
-* the context has been removed from the b->signalers and
-* furthermore we need to make sure that the concurrent
-* iterator in signal_irq_work is no longer following
-* ce->signal_link.
-*/
- i915_request_cancel_breadcrumb(rq);
- while (atomic_read(>breadcrumbs->signaler_active))
- cpu_relax();
- }
-
spin_lock_irq(>active.lock);
clear_bit(I915_FENCE_FLAG_PQUEUE, >fence.flags);
@@ -610,6 +595,16 @@ static void kick_siblings(struct i915_request *rq, struct
intel_context *ce)
struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
struct intel_engine_cs *engine = rq->engine;
+ /*
+* After this point, the rq may be transferred to a new sibling, so
+* before we clear ce->inflight make sure that the context has been
+* removed from the b->signalers and furthermore we
[Intel-gfx] [CI 2/7] drm/i915/selftests: Skip unstable timing measurements
If any of the perf tests run into 0 time, not only are we liable to
divide by zero, but the result would be highly questionable.
Nevertheless, let's not have a div-by-zero error.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
Reviewed-by: Andi Shyti
---
.../drm/i915/selftests/intel_memory_region.c | 20 +--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 75839db63bea..ce7adfa3bca0 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -852,14 +852,22 @@ static int _perf_memcpy(struct intel_memory_region
*src_mr,
}
sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
+ if (t[0] <= 0) {
+ /* ignore the impossible to protect our sanity */
+ pr_debug("Skipping %s src(%s, %s) -> dst(%s, %s) %14s
%4lluKiB copy, unstable measurement [%lld, %lld]\n",
+__func__,
+src_mr->name, repr_type(src_type),
+dst_mr->name, repr_type(dst_type),
+tests[i].name, size >> 10,
+t[0], t[4]);
+ continue;
+ }
+
pr_info("%s src(%s, %s) -> dst(%s, %s) %14s %4llu KiB copy:
%5lld MiB/s\n",
__func__,
- src_mr->name,
- repr_type(src_type),
- dst_mr->name,
- repr_type(dst_type),
- tests[i].name,
- size >> 10,
+ src_mr->name, repr_type(src_type),
+ dst_mr->name, repr_type(dst_type),
+ tests[i].name, size >> 10,
div64_u64(mul_u32_u32(4 * size,
1000 * 1000 * 1000),
t[1] + 2 * t[2] + t[3]) >> 20);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 7/7] drm/i915/gt: Disable arbitration on no-preempt requests
If a request is submitted and known to require no preemption, disable
arbitration around the batch which prevents the HW from handling a
preemption request during the payload.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Matthew Brost
Cc: Lionel Landwerlin
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 6 +++---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 +++
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index cf9a6b4eb913..b91b32195dcf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2534,6 +2534,9 @@ static int eb_submit(struct i915_execbuffer *eb, struct
i915_vma *batch)
{
int err;
+ if (intel_context_nopreempt(eb->context))
+ __set_bit(I915_FENCE_FLAG_NOPREEMPT, >request->fence.flags);
+
err = eb_move_to_gpu(eb);
if (err)
return err;
@@ -2574,9 +2577,6 @@ static int eb_submit(struct i915_execbuffer *eb, struct
i915_vma *batch)
return err;
}
- if (intel_context_nopreempt(eb->context))
- __set_bit(I915_FENCE_FLAG_NOPREEMPT, >request->fence.flags);
-
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 1972dd5dca00..2e36e0a9d8a6 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -427,6 +427,9 @@ int gen8_emit_bb_start(struct i915_request *rq,
{
u32 *cs;
+ if (unlikely(i915_request_has_nopreempt(rq)))
+ return gen8_emit_bb_start_noarb(rq, offset, len, flags);
+
cs = intel_ring_begin(rq, 6);
if (IS_ERR(cs))
return PTR_ERR(cs);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 6/7] drm/i915/gt: Only disable preemption on gen8 render engines
The reason why we did not enable preemption on Broadwater was due to
missing GPGPU workarounds. Since this only applies to rcs0, only
restrict rcs0 (and our global capabilities).
While this does not affect exposing a preemption capability to
userspace, it does affect our internal decisions on whether to use
timeslicing and semaphores between individual engines.
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
.../drm/i915/gt/intel_execlists_submission.c | 11 -
drivers/gpu/drm/i915/gt/selftest_execlists.c | 40 +++
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/i915_pci.c | 2 -
drivers/gpu/drm/i915/intel_device_info.h | 1 -
5 files changed, 15 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index aadd04f8dc9e..d857d168adcc 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3093,6 +3093,15 @@ static void execlists_park(struct intel_engine_cs
*engine)
cancel_timer(>execlists.preempt);
}
+static bool can_preempt(struct intel_engine_cs *engine)
+{
+ if (INTEL_GEN(engine->i915) > 8)
+ return true;
+
+ /* GPGPU on bdw requires extra w/a; not implemented */
+ return engine->class != RENDER_CLASS;
+}
+
void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = execlists_submit_request;
@@ -3110,7 +3119,7 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->flags |= I915_ENGINE_SUPPORTS_STATS;
if (!intel_vgpu_active(engine->i915)) {
engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
- if (HAS_LOGICAL_RING_PREEMPTION(engine->i915)) {
+ if (can_preempt(engine)) {
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
engine->flags |= I915_ENGINE_HAS_TIMESLICES;
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index bfa7fd5c2c91..e9070f51ff15 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -924,6 +924,9 @@ slice_semaphore_queue(struct intel_engine_cs *outer,
return PTR_ERR(head);
for_each_engine(engine, outer->gt, id) {
+ if (!intel_engine_has_preemption(engine))
+ continue;
+
for (i = 0; i < count; i++) {
struct i915_request *rq;
@@ -943,8 +946,8 @@ slice_semaphore_queue(struct intel_engine_cs *outer,
if (i915_request_wait(head, 0,
2 * outer->gt->info.num_engines * (count + 2) *
(count + 3)) < 0) {
- pr_err("Failed to slice along semaphore chain of length (%d,
%d)!\n",
- count, n);
+ pr_err("%s: Failed to slice along semaphore chain of length
(%d, %d)!\n",
+ outer->name, count, n);
GEM_TRACE_DUMP();
intel_gt_set_wedged(outer->gt);
err = -EIO;
@@ -1721,12 +1724,6 @@ static int live_preempt(void *arg)
enum intel_engine_id id;
int err = -ENOMEM;
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
- if (!(gt->i915->caps.scheduler & I915_SCHEDULER_CAP_PREEMPTION))
- pr_err("Logical preemption supported, but not exposed\n");
-
if (igt_spinner_init(_hi, gt))
return -ENOMEM;
@@ -1821,9 +1818,6 @@ static int live_late_preempt(void *arg)
enum intel_engine_id id;
int err = -ENOMEM;
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
if (igt_spinner_init(_hi, gt))
return -ENOMEM;
@@ -1957,9 +1951,6 @@ static int live_nopreempt(void *arg)
* that may be being observed and not want to be interrupted.
*/
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
if (preempt_client_init(gt, ))
return -ENOMEM;
if (preempt_client_init(gt, ))
@@ -2382,9 +2373,6 @@ static int live_preempt_cancel(void *arg)
* GPU. That sounds like preemption! Plus a little bit of bookkeeping.
*/
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
if (preempt_client_init(gt, ))
return -ENOMEM;
if (preempt_client_init(gt, ))
@@ -2448,9 +2436,6 @@ static int live_suppress_self_preempt(void *arg)
* completion event.
*/
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
if (intel_uc_uses_guc_submission(>uc))
return 0; /* presume
[Intel-gfx] [CI 3/7] drm/i915/selftests: Rearrange ktime_get to reduce latency against CS
In our tests where we measure the elapsed time on both the CPU and CS
using a udelay, our CS results match the udelay much more accurately
than the ktime (even when using ktime_get_fast_ns). With preemption
disabled, we can go one step lower than ktime and use local_clock.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2919
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
index ca080445695e..c3d965279fc3 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
@@ -112,11 +112,11 @@ static int __measure_timestamps(struct intel_context *ce,
/* Run the request for a 100us, sampling timestamps before/after */
preempt_disable();
- *dt = ktime_get_raw_fast_ns();
+ *dt = local_clock();
write_semaphore([2], 0);
udelay(100);
+ *dt = local_clock() - *dt;
write_semaphore([2], 1);
- *dt = ktime_get_raw_fast_ns() - *dt;
preempt_enable();
if (i915_request_wait(rq, 0, HZ / 2) < 0) {
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 5/7] drm/i915/gt: Only retire on the last breadcrumb if the last request
We use the completion of the last active breadcrumb to retire the
requests along a timeline. This is purely opportunistic as nothing
guarantees that any particular timeline is terminated by a breadcrumb;
except for parking the engine where we explicitly add a breadcrumb so
that we park quickly and do an explicit retire upon signaling to reduce
the latency dramatically (avoiding a retire worker roundtrip).
With scheduling, we anticipate retiring completed timelines as a matter
of course. Performing the same action from inside the breadcrumbs is
intended to provide similar functionality for legacy ringbuffer
submission.
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 10 +-
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_timeline.h | 7 +++
3 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index 7137b6f24f55..be2c285a0ac7 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -257,17 +257,17 @@ static void signal_irq_work(struct irq_work *work)
list_del_rcu(>signal_link);
release = remove_signaling_context(b, ce);
spin_unlock(>signal_lock);
+ if (release) {
+ if (intel_timeline_is_last(ce->timeline, rq))
+ add_retire(b, ce->timeline);
+ intel_context_put(ce);
+ }
if (__dma_fence_signal(>fence))
/* We own signal_node now, xfer to local list */
signal = slist_add(>signal_node, signal);
else
i915_request_put(rq);
-
- if (release) {
- add_retire(b, ce->timeline);
- intel_context_put(ce);
- }
}
}
atomic_dec(>signaler_active);
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index eb69eef9d7db..aadd04f8dc9e 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -640,7 +640,7 @@ static inline void __execlists_schedule_out(struct
i915_request *rq)
* If we have just completed this context, the engine may now be
* idle and we want to re-enter powersaving.
*/
- if (list_is_last_rcu(>link, >timeline->requests) &&
+ if (intel_timeline_is_last(ce->timeline, rq) &&
__i915_request_is_complete(rq))
intel_engine_add_retire(engine, ce->timeline);
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h
b/drivers/gpu/drm/i915/gt/intel_timeline.h
index f502a619843f..dcdee692a80e 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
@@ -110,4 +110,11 @@ void intel_gt_show_timelines(struct intel_gt *gt,
const char *prefix,
int indent));
+static inline bool
+intel_timeline_is_last(const struct intel_timeline *tl,
+ const struct i915_request *rq)
+{
+ return list_is_last_rcu(>link, >requests);
+}
+
#endif
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/7] drm/i915/gt: Prevent use of engine->wa_ctx after error
On error we unpin and free the wa_ctx.vma, but do not clear any of the
derived flags. During lrc_init, we look at the flags and attempt to
dereference the wa_ctx.vma if they are set. To protect the error path
where we try to limp along without the wa_ctx, make sure we clear those
flags!
Reported-by: Matt Roper
Fixes: 604a8f6f1e33 ("drm/i915/lrc: Only enable per-context and per-bb buffers
if set")
Signed-off-by: Chris Wilson
Cc: Matt Roper
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: # v4.15+
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 4e856947fb13..703d9ecc3f7e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1453,6 +1453,9 @@ static int lrc_setup_wa_ctx(struct intel_engine_cs
*engine)
void lrc_fini_wa_ctx(struct intel_engine_cs *engine)
{
i915_vma_unpin_and_release(>wa_ctx.vma, 0);
+
+ /* Called on error unwind, clear all flags to prevent further use */
+ memset(>wa_ctx, 0, sizeof(engine->wa_ctx));
}
typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Async flips for all ilk+ platforms
== Series Details == Series: drm/i915: Async flips for all ilk+ platforms URL : https://patchwork.freedesktop.org/series/85627/ State : success == Summary == CI Bug Log - changes from CI_DRM_9567 -> Patchwork_19297 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/index.html Known issues Here are the changes found in Patchwork_19297 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#2411] / [i915#402]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [PASS][4] -> [DMESG-FAIL][5] ([i915#2291] / [i915#541]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_chamelium@dp-crc-fast: - fi-icl-u2: [PASS][6] -> [FAIL][7] ([i915#1161] / [i915#262]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [PASS][8] -> [FAIL][9] ([i915#1372]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][10] -> [DMESG-FAIL][11] ([i915#165]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@prime_vgem@basic-fence-flip: - fi-tgl-y: [PASS][12] -> [DMESG-WARN][13] ([i915#402]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-tgl-y/igt@prime_v...@basic-fence-flip.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/fi-tgl-y/igt@prime_v...@basic-fence-flip.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][14] ([i915#402]) -> [PASS][15] +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-tgl-y/igt@debugfs_test@read_all_entries.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@i915_selftest@live@gem: - fi-kbl-soraka: [DMESG-FAIL][16] -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-kbl-soraka/igt@i915_selftest@l...@gem.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/fi-kbl-soraka/igt@i915_selftest@l...@gem.html * igt@i915_selftest@live@reset: - fi-kbl-soraka: [SKIP][18] ([fdo#109271]) -> [PASS][19] +12 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-kbl-soraka/igt@i915_selftest@l...@reset.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19297/fi-kbl-soraka/igt@i915_selftest@l...@reset.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161 [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 Participating hosts (43 -> 38) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9567 -> Patchwork_19297 CI-20190529: 20190529 CI_DRM_9567: 9fc1f6dac2ec9339e390931322768a0286f01f71 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5951: fec3b9c7d88357144f0d7a1447b9316a1c81da1a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19297:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gen9_bc : Add TGP PCH support (rev2)
== Series Details == Series: drm/i915/gen9_bc : Add TGP PCH support (rev2) URL : https://patchwork.freedesktop.org/series/85502/ State : success == Summary == CI Bug Log - changes from CI_DRM_9566_full -> Patchwork_19291_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19291_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-2x: - shard-tglb: NOTRUN -> [SKIP][1] ([i915#1839]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb5/igt@feature_discov...@display-2x.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-skl: [PASS][2] -> [INCOMPLETE][3] ([i915#198]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl4/igt@gem_ctx_isolation@preservation...@vcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl6/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_ctx_persistence@engines-hang: - shard-hsw: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-hsw4/igt@gem_ctx_persiste...@engines-hang.html * igt@gem_eio@in-flight-contexts-immediate: - shard-hsw: [PASS][5] -> [INCOMPLETE][6] ([i915#2870]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-hsw7/igt@gem_...@in-flight-contexts-immediate.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-hsw7/igt@gem_...@in-flight-contexts-immediate.html * igt@gem_pread@exhaustion: - shard-hsw: NOTRUN -> [WARN][7] ([i915#2658]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-hsw4/igt@gem_pr...@exhaustion.html * igt@gem_userptr_blits@process-exit-mmap@wc: - shard-hsw: NOTRUN -> [SKIP][8] ([fdo#109271]) +195 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-hsw4/igt@gem_userptr_blits@process-exit-m...@wc.html * igt@gem_workarounds@suspend-resume: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#146] / [i915#198]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl6/igt@gem_workarou...@suspend-resume.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl1/igt@gem_workarou...@suspend-resume.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1436] / [i915#716]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl9/igt@gen9_exec_pa...@allowed-single.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl10/igt@gen9_exec_pa...@allowed-single.html * igt@gen9_exec_parse@bb-start-cmd: - shard-tglb: NOTRUN -> [SKIP][13] ([fdo#112306]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb5/igt@gen9_exec_pa...@bb-start-cmd.html * igt@i915_module_load@reload-with-fault-injection: - shard-snb: [PASS][14] -> [INCOMPLETE][15] ([i915#2880]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-snb7/igt@i915_module_l...@reload-with-fault-injection.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-snb4/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#658]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl10/igt@i915_pm...@dc3co-vpb-simulation.html * igt@i915_selftest@live@gt_lrc: - shard-tglb: NOTRUN -> [DMESG-FAIL][17] ([i915#2373]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb5/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@gt_pm: - shard-tglb: NOTRUN -> [DMESG-FAIL][18] ([i915#1759] / [i915#2291]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb5/igt@i915_selftest@live@gt_pm.html * igt@kms_ccs@pipe-c-missing-ccs-buffer: - shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111304]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl10/igt@kms_...@pipe-c-missing-ccs-buffer.html * igt@kms_color_chamelium@pipe-b-ctm-0-75: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#109284] / [fdo#111827]) +2 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb5/igt@kms_color_chamel...@pipe-b-ctm-0-75.html * igt@kms_color_chamelium@pipe-d-gamma: - shard-hsw: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +15 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-hsw4/igt@kms_color_chamel...@pipe-d-gamma.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen: - shard-skl:
Re: [Intel-gfx] [PATCH 3/5] drm/i915/gt: Only retire on the last breadcrumb if the last request
Hi Chris, On Thu, Jan 07, 2021 at 10:17:22PM +, Chris Wilson wrote: > We use the completion of the last active breadcrumb to retire the > requests along a timeline. This is purely opportunistic as nothing > guarantees that any particular timeline is terminated by a breadcrumb; > except for the parking the engine. We explicitly add a breadcrumb to > parking the engine so that we park quickly and do an explicit retire > upon signaling to reduce the latency dramatically. > > With scheduling, we anticipate retiring completed timelines as a matter > of course. Performing the same action from inside the breadcrumbs is > intended to provide similar functionality for legacy ringbuffer > submission. > > Signed-off-by: Chris Wilson Reviewed-by: Andi Shyti Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/5] drm/i915/gt: Restore ce->signal flush before releasing virtual engine
> > > +void intel_context_remove_breadcrumbs(struct intel_context *ce,
> > > + struct intel_breadcrumbs *b)
> > > +{
> > > + struct i915_request *rq, *rn;
> > > + bool release = false;
> > > + unsigned long flags;
> > > +
> > > + spin_lock_irqsave(>signal_lock, flags);
> > > +
> > > + if (list_empty(>signals))
> > > + goto unlock;
> >
> > does "list_empty" need to be under lock or you've been lazy?
>
> This check is required to be under the lock, we have to be careful about
> not calling remove_signaling_context() from here and signal_irq_work.
> I put the unlocked check in the caller to avoid the function call as well.
OK...
Reviewed-by: Andi Shyti
Andi
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: split out pps and aux (rev2)
== Series Details ==
Series: drm/i915/dp: split out pps and aux (rev2)
URL : https://patchwork.freedesktop.org/series/85167/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9567 -> Patchwork_19296
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/index.html
Known issues
Here are the changes found in Patchwork_19296 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@amdgpu/amd_cs_nop@nop-compute0:
- fi-tgl-y: NOTRUN -> [SKIP][2] ([fdo#109315] / [i915#2575]) +8
similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/fi-tgl-y/igt@amdgpu/amd_cs_...@nop-compute0.html
* igt@prime_vgem@basic-fence-flip:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar
issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-tgl-y/igt@prime_v...@basic-fence-flip.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/fi-tgl-y/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +2 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@i915_selftest@live@gem:
- fi-kbl-soraka: [DMESG-FAIL][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-kbl-soraka/igt@i915_selftest@l...@gem.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/fi-kbl-soraka/igt@i915_selftest@l...@gem.html
* igt@i915_selftest@live@reset:
- fi-kbl-soraka: [SKIP][9] ([fdo#109271]) -> [PASS][10] +12 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-kbl-soraka/igt@i915_selftest@l...@reset.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/fi-kbl-soraka/igt@i915_selftest@l...@reset.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9567 -> Patchwork_19296
CI-20190529: 20190529
CI_DRM_9567: 9fc1f6dac2ec9339e390931322768a0286f01f71 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5951: fec3b9c7d88357144f0d7a1447b9316a1c81da1a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19296: d6be48f109873e9857af7afab7f34224b92f57b0 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d6be48f10987 drm/i915/dp: split out aux functionality to intel_dp_aux.c
d7a14085a159 drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
d50dad330043 drm/i915/pps: move pps code over from intel_display.c and refactor
f57fa5d3bb5d drm/i915/pps: refactor init abstractions
ca6b78cc5788 drm/i915/pps: rename intel_dp_init_panel_power_sequencer* functions
eaad3ef82888 drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init
cb6cf18c5623 drm/i915/pps: add locked intel_pps_wait_power_cycle
4c5d95f01d72 drm/i915/pps: rename intel_power_sequencer_reset to
intel_pps_reset_all
46024084caf5 drm/i915/pps: rename intel_dp_check_edp to
intel_pps_check_power_unlocked
fcd60022bd6d drm/i915/pps: abstract intel_pps_encoder_reset()
b0c7e08de7bc drm/i915/pps: add higher level intel_pps_init() call
13979e877fa3 drm/i915/pps: abstract intel_pps_vdd_off_sync
4c39d047e6a5 drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked
67bedb793872 drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
9de69e6f8cbd drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_*
84bd85deaf0b drm/i915/pps: rename pps_{, un}lock -> intel_pps_{, un}lock
1d7a1bfde18c drm/i915/pps: abstract panel power sequencer from intel_dp.c
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19296/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/5] drm/i915/gt: Disable arbitration on no-preempt requests
Hi Chris,
On Thu, Jan 07, 2021 at 10:17:24PM +, Chris Wilson wrote:
> If a request is submitted and known to require no preemption, disable
> arbitration around the batch which prevents the HW from handling a
> preemption request during the payload.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Matthew Brost
> Cc: Lionel Landwerlin
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 6 +++---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 +++
> 2 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index cf9a6b4eb913..b91b32195dcf 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -2534,6 +2534,9 @@ static int eb_submit(struct i915_execbuffer *eb, struct
> i915_vma *batch)
> {
> int err;
>
> + if (intel_context_nopreempt(eb->context))
> + __set_bit(I915_FENCE_FLAG_NOPREEMPT, >request->fence.flags);
> +
> err = eb_move_to_gpu(eb);
> if (err)
> return err;
> @@ -2574,9 +2577,6 @@ static int eb_submit(struct i915_execbuffer *eb, struct
> i915_vma *batch)
> return err;
> }
>
> - if (intel_context_nopreempt(eb->context))
> - __set_bit(I915_FENCE_FLAG_NOPREEMPT, >request->fence.flags);
> -
makes sense to me...
Reviewed-by: Andi Shyti
Thanks,
Andi
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915/selftests: Skip unstable timing measurements
Hi Chris, > > > > > diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c > > > > > b/drivers/gpu/drm/i915/selftests/intel_memory_region.c > > > > > index 75839db63bea..59c58a276677 100644 > > > > > --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c > > > > > +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c > > > > > @@ -852,6 +852,9 @@ static int _perf_memcpy(struct > > > > > intel_memory_region *src_mr, > > > > > } > > > > > > > > > > sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, > > > > > NULL); > > > > > + if (!t[0]) > > > > > + continue; > > > > > + > > > > > > > > are you assuming here that if t[0] is '0', also the rest of 't' > > > > is '0'? > > > > > > It's sorted into ascending order with ktime_t... Hmm, s64 not u64 as I > > > presumed. So better to check <= 0. > > > > by division by 0 I guess you mean here: > > > > div64_u64(mul_u32_u32(4 * size, > > 1000 * 1000 * 1000), > > t[1] + 2 * t[2] + t[3]) >> 20); > > > > why are you testing t[0]? Did I miss anything else? > > Since t[0] is the most negative value, if it is <= 0 that implies at > least one of the measurements was bad. If any are bad, all are bad by > association. I considered checking t[4] to make sure that at least the > best was good enough, but paranoia won. yes, that's what I actually meant with the first question. Thanks, Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/5] drm/i915/gt: Restore ce->signal flush before releasing virtual engine
Hi Chris,
> +void intel_context_remove_breadcrumbs(struct intel_context *ce,
> + struct intel_breadcrumbs *b)
> +{
> + struct i915_request *rq, *rn;
> + bool release = false;
> + unsigned long flags;
> +
> + spin_lock_irqsave(>signal_lock, flags);
> +
> + if (list_empty(>signals))
> + goto unlock;
does "list_empty" need to be under lock or you've been lazy?
The rest looks fine,
Andi
> + list_for_each_entry_safe(rq, rn, >signals, signal_link) {
> + GEM_BUG_ON(!__i915_request_is_complete(rq));
> + if (!test_and_clear_bit(I915_FENCE_FLAG_SIGNAL,
> + >fence.flags))
> + continue;
> +
> + list_del_rcu(>signal_link);
> + irq_signal_request(rq, b);
> + i915_request_put(rq);
> + }
> + release = remove_signaling_context(b, ce);
> +
> +unlock:
> + spin_unlock_irqrestore(>signal_lock, flags);
> + if (release)
> + intel_context_put(ce);
> +
> + while (atomic_read(>signaler_active))
> + cpu_relax();
> +}
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Skip unstable timing measurements
Hi Chris, On Fri, Jan 08, 2021 at 03:14:49PM +, Chris Wilson wrote: > If any of the perf tests run into 0 time, not only are we liable to > divide by zero, but the result would be highly questionable. > Nevertheless, let's not have a div-by-zero error. > > Signed-off-by: Chris Wilson > Cc: Andi Shyti Reviewed-by: Andi Shyti Thanks, Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dp: split out pps and aux (rev2)
== Series Details == Series: drm/i915/dp: split out pps and aux (rev2) URL : https://patchwork.freedesktop.org/series/85167/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:869:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: split out pps and aux (rev2)
== Series Details == Series: drm/i915/dp: split out pps and aux (rev2) URL : https://patchwork.freedesktop.org/series/85167/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1d7a1bfde18c drm/i915/pps: abstract panel power sequencer from intel_dp.c -:1082: CHECK:LINE_SPACING: Please don't use multiple blank lines #1082: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2552: + -:1623: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #1623: new file mode 100644 -:2073: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #2073: FILE: drivers/gpu/drm/i915/display/intel_pps.c:446: +#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) -:2074: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #2074: FILE: drivers/gpu/drm/i915/display/intel_pps.c:447: +#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) -:2074: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #2074: FILE: drivers/gpu/drm/i915/display/intel_pps.c:447: +#define IDLE_ON_VALUE ^I(PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)$ -:2079: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #2079: FILE: drivers/gpu/drm/i915/display/intel_pps.c:452: +#define IDLE_CYCLE_MASK(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) -:2080: WARNING:LONG_LINE: line length of 111 exceeds 100 columns #2080: FILE: drivers/gpu/drm/i915/display/intel_pps.c:453: +#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) -:2085: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #2085: FILE: drivers/gpu/drm/i915/display/intel_pps.c:458: +static void wait_panel_status(struct intel_dp *intel_dp, + u32 mask, -:2139: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #2139: FILE: drivers/gpu/drm/i915/display/intel_pps.c:512: +* and then make panel wait for t11_t12 if needed. */ -:2141: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #2141: FILE: drivers/gpu/drm/i915/display/intel_pps.c:514: + panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); -:2144: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #2144: FILE: drivers/gpu/drm/i915/display/intel_pps.c:517: +* wait. */ -:2147: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #2147: FILE: drivers/gpu/drm/i915/display/intel_pps.c:520: + intel_dp->panel_power_cycle_delay - panel_power_off_duration); -:2147: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #2147: FILE: drivers/gpu/drm/i915/display/intel_pps.c:520: + wait_remaining_ms_from_jiffies(jiffies, + intel_dp->panel_power_cycle_delay - panel_power_off_duration); -:2441: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #2441: FILE: drivers/gpu/drm/i915/display/intel_pps.c:814: +* panels get very unhappy and cease to work. */ -:2790: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #2790: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1163: +* too. */ -:2794: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #2794: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1167: +* our hw here, which are all in 100usec. */ -:2802: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #2802: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1175: +* too. */ -:2808: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #2808: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1181: +* unset, fall back to the spec limits. */ -:2809: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #2809: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1182: +#define assign_final(field)final->field = (max(cur.field, vbt.field) == 0 ? \ + spec.field : \ + max(cur.field, vbt.field)) -:2809: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'field' - possible side-effects? #2809: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1182: +#define assign_final(field)final->field = (max(cur.field, vbt.field) == 0 ? \ + spec.field : \ + max(cur.field, vbt.field)) -:2809: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'field' may be better as '(field)' to avoid precedence issues #2809: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1182: +#define assign_final(field)final->field = (max(cur.field,
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/backlight: fix CPU mode backlight takeover on LPT
== Series Details == Series: drm/i915/backlight: fix CPU mode backlight takeover on LPT URL : https://patchwork.freedesktop.org/series/85619/ State : success == Summary == CI Bug Log - changes from CI_DRM_9567 -> Patchwork_19295 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/index.html Known issues Here are the changes found in Patchwork_19295 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html * igt@fbdev@read: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-tgl-y/igt@fb...@read.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/fi-tgl-y/igt@fb...@read.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][4] ([i915#402]) -> [PASS][5] +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-tgl-y/igt@debugfs_test@read_all_entries.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@i915_selftest@live@gem: - fi-kbl-soraka: [DMESG-FAIL][6] -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-kbl-soraka/igt@i915_selftest@l...@gem.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/fi-kbl-soraka/igt@i915_selftest@l...@gem.html * igt@i915_selftest@live@reset: - fi-kbl-soraka: [SKIP][8] ([fdo#109271]) -> [PASS][9] +12 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-kbl-soraka/igt@i915_selftest@l...@reset.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/fi-kbl-soraka/igt@i915_selftest@l...@reset.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 38) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9567 -> Patchwork_19295 CI-20190529: 20190529 CI_DRM_9567: 9fc1f6dac2ec9339e390931322768a0286f01f71 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5951: fec3b9c7d88357144f0d7a1447b9316a1c81da1a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19295: 26bee7ddae51ded6388b8cb1d913596eb52bf795 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 26bee7ddae51 drm/i915/backlight: fix CPU mode backlight takeover on LPT == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19295/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/backlight: fix CPU mode backlight takeover on LPT
Reviewed-by: Lyude Paul
Let me know when you've pushed this upstream and I'll go ahead and send out a
rebased version of my backlight series.
On Fri, 2021-01-08 at 17:28 +0200, Jani Nikula wrote:
> The pch_get_backlight(), lpt_get_backlight(), and lpt_set_backlight()
> functions operate directly on the hardware registers. If inverting the
> value is needed, using intel_panel_compute_brightness(), it should only
> be done in the interface between hardware registers and
> panel->backlight.level.
>
> The CPU mode takeover code added in commit 5b1ec9ac7ab5
> ("drm/i915/backlight: Fix backlight takeover on LPT, v3.") reads the
> hardware register and converts to panel->backlight.level correctly,
> however the value written back should remain in the hardware register
> "domain".
>
> This hasn't been an issue, because GM45 machines are the only known
> users of i915.invert_brightness and the brightness invert quirk, and
> without one of them no conversion is made. It's likely nobody's ever hit
> the problem.
>
> Fixes: 5b1ec9ac7ab5 ("drm/i915/backlight: Fix backlight takeover on LPT, v3.")
> Cc: Maarten Lankhorst
> Cc: Ville Syrjälä
> Cc: Lyude Paul
> Cc: # v5.1+
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_panel.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
> b/drivers/gpu/drm/i915/display/intel_panel.c
> index 67f81ae995c4..7a4239d1c241 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -1649,16 +1649,13 @@ static int lpt_setup_backlight(struct intel_connector
> *connector, enum pipe unus
> val = pch_get_backlight(connector);
> else
> val = lpt_get_backlight(connector);
> - val = intel_panel_compute_brightness(connector, val);
> - panel->backlight.level = clamp(val, panel->backlight.min,
> - panel->backlight.max);
>
> if (cpu_mode) {
> drm_dbg_kms(_priv->drm,
> "CPU backlight register was enabled, switching to
> PCH override\n");
>
> /* Write converted CPU PWM value to PCH override register */
> - lpt_set_backlight(connector->base.state, panel-
> >backlight.level);
> + lpt_set_backlight(connector->base.state, val);
> intel_de_write(dev_priv, BLC_PWM_PCH_CTL1,
> pch_ctl1 | BLM_PCH_OVERRIDE_ENABLE);
>
> @@ -1666,6 +1663,10 @@ static int lpt_setup_backlight(struct intel_connector
> *connector, enum pipe unus
> cpu_ctl2 & ~BLM_PWM_ENABLE);
> }
>
> + val = intel_panel_compute_brightness(connector, val);
> + panel->backlight.level = clamp(val, panel->backlight.min,
> + panel->backlight.max);
> +
> return 0;
> }
>
--
Sincerely,
Lyude Paul (she/her)
Software Engineer at Red Hat
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
asked me a question, are waiting for a review/merge on a patch, etc. and I
haven't responded in a while, please feel free to send me another email to check
on my status. I don't bite!
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [drm-intel:topic/dp-hdmi-2.1-pcon 15/15] drivers/gpu/drm/i915/display/intel_dp.c:6909:42: error: use of logical '||' with constant operand
tree: git://anongit.freedesktop.org/drm-intel topic/dp-hdmi-2.1-pcon
head: 522508b665df3bbfdf40381d4e61777844b1703f
commit: 522508b665df3bbfdf40381d4e61777844b1703f [15/15] drm/i915/display: Let
PCON convert from RGB to YCbCr if it can
config: x86_64-randconfig-r011-20210108 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
5c951623bc8965fa1e89660f2f5f4a2944e4981a)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
git remote add drm-intel git://anongit.freedesktop.org/drm-intel
git fetch --no-tags drm-intel topic/dp-hdmi-2.1-pcon
git checkout 522508b665df3bbfdf40381d4e61777844b1703f
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_dp.c:6909:42: error: use of logical '||'
>> with constant operand [-Werror,-Wconstant-logical-operand]
DP_DS_HDMI_BT601_RGB_YCBCR_CONV ||
^
drivers/gpu/drm/i915/display/intel_dp.c:6909:42: note: use '|' for a bitwise
operation
DP_DS_HDMI_BT601_RGB_YCBCR_CONV ||
^~
|
drivers/gpu/drm/i915/display/intel_dp.c:6910:42: error: use of logical '||'
with constant operand [-Werror,-Wconstant-logical-operand]
DP_DS_HDMI_BT709_RGB_YCBCR_CONV ||
^
drivers/gpu/drm/i915/display/intel_dp.c:6910:42: note: use '|' for a bitwise
operation
DP_DS_HDMI_BT709_RGB_YCBCR_CONV ||
^~
|
>> drivers/gpu/drm/i915/display/intel_dp.c:6911:10: error: converting the
>> result of '<<' to a boolean always evaluates to true
>> [-Werror,-Wtautological-constant-compare]
DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
^
include/drm/drm_dp_helper.h:444:48: note: expanded from macro
'DP_DS_HDMI_BT2020_RGB_YCBCR_CONV'
# define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV (1 << 7)
^
drivers/gpu/drm/i915/display/intel_dp.c:6909:10: error: converting the
result of '<<' to a boolean always evaluates to true
[-Werror,-Wtautological-constant-compare]
DP_DS_HDMI_BT601_RGB_YCBCR_CONV ||
^
include/drm/drm_dp_helper.h:442:48: note: expanded from macro
'DP_DS_HDMI_BT601_RGB_YCBCR_CONV'
# define DP_DS_HDMI_BT601_RGB_YCBCR_CONV(1 << 5)
^
drivers/gpu/drm/i915/display/intel_dp.c:6910:10: error: converting the
result of '<<' to a boolean always evaluates to true
[-Werror,-Wtautological-constant-compare]
DP_DS_HDMI_BT709_RGB_YCBCR_CONV ||
^
include/drm/drm_dp_helper.h:443:48: note: expanded from macro
'DP_DS_HDMI_BT709_RGB_YCBCR_CONV'
# define DP_DS_HDMI_BT709_RGB_YCBCR_CONV(1 << 6)
^
5 errors generated.
vim +6909 drivers/gpu/drm/i915/display/intel_dp.c
6879
6880 static void
6881 intel_dp_update_420(struct intel_dp *intel_dp)
6882 {
6883 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6884 struct intel_connector *connector =
intel_dp->attached_connector;
6885 bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420,
rgb_to_ycbcr;
6886
6887 /* No YCbCr output support on gmch platforms */
6888 if (HAS_GMCH(i915))
6889 return;
6890
6891 /*
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with drm/i915/selftests: Skip unstable timing measurements (rev4)
== Series Details == Series: series starting with drm/i915/selftests: Skip unstable timing measurements (rev4) URL : https://patchwork.freedesktop.org/series/85596/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9567 -> Patchwork_19294 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19294 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19294, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19294/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19294: ### IGT changes ### Possible regressions * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19294/fi-bsw-nick/igt@i915_selftest@l...@execlists.html Known issues Here are the changes found in Patchwork_19294 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-tgl-y: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19294/fi-tgl-y/igt@amdgpu/amd_ba...@cs-compute.html * igt@amdgpu/amd_basic@cs-gfx: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19294/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html * igt@fbdev@read: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-tgl-y/igt@fb...@read.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19294/fi-tgl-y/igt@fb...@read.html * igt@runner@aborted: - fi-bsw-nick:NOTRUN -> [FAIL][7] ([i915#1436]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19294/fi-bsw-nick/igt@run...@aborted.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-tgl-y/igt@debugfs_test@read_all_entries.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19294/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@i915_selftest@live@gem: - fi-kbl-soraka: [DMESG-FAIL][10] -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-kbl-soraka/igt@i915_selftest@l...@gem.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19294/fi-kbl-soraka/igt@i915_selftest@l...@gem.html * igt@i915_selftest@live@reset: - fi-kbl-soraka: [SKIP][12] ([fdo#109271]) -> [PASS][13] +12 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-kbl-soraka/igt@i915_selftest@l...@reset.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19294/fi-kbl-soraka/igt@i915_selftest@l...@reset.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 38) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9567 -> Patchwork_19294 CI-20190529: 20190529 CI_DRM_9567: 9fc1f6dac2ec9339e390931322768a0286f01f71 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5951: fec3b9c7d88357144f0d7a1447b9316a1c81da1a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19294: 41cf60168fed8cf3d97ac34bb4a109556d14b9e4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 41cf60168fed drm/i915/gt: Disable arbitration on no-preempt requests 72c97acf0662 drm/i915/gt: Only disable preemption on gen8 render engines f1eef8304063 drm/i915/gt: Only retire on the last breadcrumb if the last request ee160682ce23 drm/i915/gt: Restore ce->signal flush before releasing virtual engine 32998db1cdb6 drm/i915/selftests: Skip unstable timing measurements == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19294/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/9] drm/i915: Implement async flips for ivb/hsw
From: Ville Syrjälä
Add support for async flips on ivb/hsw. Unlike bdw+ we don't need
any workarounds to disable async flips. Apart from that the only
real difference from the bdw implementation is the location of the
flip_done interrupt bits.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c| 24
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
drivers/gpu/drm/i915/i915_irq.c | 6 +
3 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 336a5df32f2f..aa2f6c4ed9ba 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -532,6 +532,26 @@ bdw_primary_disable_flip_done(struct intel_plane *plane)
spin_unlock_irq(>irq_lock);
}
+static void
+ivb_primary_enable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ spin_lock_irq(>irq_lock);
+ ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
+ spin_unlock_irq(>irq_lock);
+}
+
+static void
+ivb_primary_disable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ spin_lock_irq(>irq_lock);
+ ilk_disable_display_irq(i915,
DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
+ spin_unlock_irq(>irq_lock);
+}
+
static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
enum pipe *pipe)
{
@@ -704,6 +724,10 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
plane->async_flip = g4x_primary_async_flip;
plane->enable_flip_done = bdw_primary_enable_flip_done;
plane->disable_flip_done = bdw_primary_disable_flip_done;
+ } else if (IS_HASWELL(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
+ plane->async_flip = g4x_primary_async_flip;
+ plane->enable_flip_done = ivb_primary_enable_flip_done;
+ plane->disable_flip_done = ivb_primary_disable_flip_done;
}
if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 794b32d21a11..3d6ce3ced92c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2122,7 +2122,8 @@ static unsigned int intel_linear_alignment(const struct
drm_i915_private *dev_pr
static bool has_async_flips(struct drm_i915_private *i915)
{
- return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915);
+ return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915) ||
+ IS_HASWELL(i915) || IS_IVYBRIDGE(i915);
}
static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 407a9dd0a21e..3518f6f23896 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2081,6 +2081,9 @@ static void ivb_display_irq_handler(struct
drm_i915_private *dev_priv,
for_each_pipe(dev_priv, pipe) {
if (de_iir & DE_PIPE_VBLANK_IVB(pipe))
intel_handle_vblank(dev_priv, pipe);
+
+ if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
+ flip_done_handler(dev_priv, pipe);
}
/* check event from PCH */
@@ -3564,6 +3567,9 @@ static void ilk_irq_postinstall(struct drm_i915_private
*dev_priv)
DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
+ DE_PLANE_FLIP_DONE_IVB(PLANE_C) |
+ DE_PLANE_FLIP_DONE_IVB(PLANE_B) |
+ DE_PLANE_FLIP_DONE_IVB(PLANE_A) |
DE_DP_A_HOTPLUG_IVB);
} else {
display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/9] drm/i915: Add plane vfuncs to enable/disable flip_done interrupt
From: Ville Syrjälä
Prepare for more platforms with async flip support by turning
the flip_done interrupt enable/disable into plane vfuncs.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 42 +--
.../drm/i915/display/intel_display_types.h| 2 +
drivers/gpu/drm/i915/display/intel_sprite.c | 27 +++-
drivers/gpu/drm/i915/i915_irq.c | 26
drivers/gpu/drm/i915/i915_irq.h | 3 --
5 files changed, 67 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index aec403712c63..12d556b0d7e4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6129,6 +6129,42 @@ static void intel_post_plane_update(struct
intel_atomic_state *state,
icl_wa_scalerclkgating(dev_priv, pipe, false);
}
+static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ u8 update_planes = crtc_state->update_planes;
+ const struct intel_plane_state *plane_state;
+ struct intel_plane *plane;
+ int i;
+
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ if (plane->enable_flip_done &&
+ plane->pipe == crtc->pipe &&
+ update_planes & BIT(plane->id))
+ plane->enable_flip_done(plane);
+ }
+}
+
+static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
+{
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ u8 update_planes = crtc_state->update_planes;
+ const struct intel_plane_state *plane_state;
+ struct intel_plane *plane;
+ int i;
+
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ if (plane->disable_flip_done &&
+ plane->pipe == crtc->pipe &&
+ update_planes & BIT(plane->id))
+ plane->disable_flip_done(plane);
+ }
+}
+
static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
struct intel_crtc *crtc,
const struct intel_crtc_state
*new_crtc_state)
@@ -14329,7 +14365,7 @@ static void kill_bigjoiner_slave(struct
intel_atomic_state *state,
* Async flip can only change the plane surface address, so anything else
* changing is rejected from the intel_atomic_check_async() function.
* Once this check is cleared, flip done interrupt is enabled using
- * the skl_enable_flip_done() function.
+ * the intel_crtc_enable_flip_done() function.
*
* As soon as the surface address register is written, flip done interrupt is
* generated and the requested events are sent to the usersapce in the
interrupt
@@ -15285,7 +15321,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (new_crtc_state->uapi.async_flip)
- skl_enable_flip_done(crtc);
+ intel_crtc_enable_flip_done(state, crtc);
}
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
@@ -15310,7 +15346,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (new_crtc_state->uapi.async_flip)
- skl_disable_flip_done(crtc);
+ intel_crtc_disable_flip_done(state, crtc);
if (new_crtc_state->hw.active &&
!intel_crtc_needs_modeset(new_crtc_state) &&
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1067bd073c95..255648ab0fa7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1258,6 +1258,8 @@ struct intel_plane {
void (*async_flip)(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
+ void (*enable_flip_done)(struct intel_plane *plane);
+ void (*disable_flip_done)(struct intel_plane *plane);
};
struct intel_watermark_params {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index e839a7748068..affd8cffa306 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++
[Intel-gfx] [PATCH 9/9] drm/i915: Implement async flips for vlv/chv
From: Ville Syrjälä
Add support for async flips on vlv/chv. Unlike all the other
platforms vlv/chv do not use the async flip bit in DSPCNTR and
instead we select between async vs. sync flips based on the
surface address register. The normal DSPSURF generates sync
flips DSPADDR_VLV generates async flips. And as usual the
interrupt bits are different from the other platforms.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c| 49 ++--
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
drivers/gpu/drm/i915/i915_irq.c | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 2 +
4 files changed, 52 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 3a1922931a3f..c24a8e85ce91 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -510,6 +510,23 @@ g4x_primary_async_flip(struct intel_plane *plane,
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
+static void
+vlv_primary_async_flip(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
+ bool async_flip)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ u32 dspaddr_offset = plane_state->color_plane[0].offset;
+ enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(_priv->uncore.lock, irqflags);
+ intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane),
+ intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
+ spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
+}
+
static void
bdw_primary_enable_flip_done(struct intel_plane *plane)
{
@@ -572,6 +589,28 @@ ilk_primary_disable_flip_done(struct intel_plane *plane)
spin_unlock_irq(>irq_lock);
}
+static void
+vlv_primary_enable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+
+ spin_lock_irq(>irq_lock);
+ i915_enable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
+ spin_unlock_irq(>irq_lock);
+}
+
+static void
+vlv_primary_disable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+
+ spin_lock_irq(>irq_lock);
+ i915_disable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
+ spin_unlock_irq(>irq_lock);
+}
+
static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
enum pipe *pipe)
{
@@ -739,16 +778,20 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
plane->get_hw_state = i9xx_plane_get_hw_state;
plane->check_plane = i9xx_plane_check;
- if (IS_BROADWELL(dev_priv)) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ plane->async_flip = vlv_primary_async_flip;
+ plane->enable_flip_done = vlv_primary_enable_flip_done;
+ plane->disable_flip_done = vlv_primary_disable_flip_done;
+ } else if (IS_BROADWELL(dev_priv)) {
plane->need_async_flip_disable_wa = true;
plane->async_flip = g4x_primary_async_flip;
plane->enable_flip_done = bdw_primary_enable_flip_done;
plane->disable_flip_done = bdw_primary_disable_flip_done;
- } else if (IS_HASWELL(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
+ } else if (INTEL_GEN(dev_priv) >= 7) {
plane->async_flip = g4x_primary_async_flip;
plane->enable_flip_done = ivb_primary_enable_flip_done;
plane->disable_flip_done = ivb_primary_disable_flip_done;
- } else if (IS_GEN_RANGE(dev_priv, 5, 6)) {
+ } else if (INTEL_GEN(dev_priv) >= 5) {
plane->async_flip = g4x_primary_async_flip;
plane->enable_flip_done = ilk_primary_enable_flip_done;
plane->disable_flip_done = ilk_primary_disable_flip_done;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c9ad4e935b6b..4597100c0186 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2122,9 +2122,7 @@ static unsigned int intel_linear_alignment(const struct
drm_i915_private *dev_pr
static bool has_async_flips(struct drm_i915_private *i915)
{
- return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915) ||
- IS_HASWELL(i915) || IS_IVYBRIDGE(i915) ||
- IS_GEN_RANGE(i915, 5, 6);
+ return INTEL_GEN(i915) >= 5;
}
static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
diff --git
[Intel-gfx] [PATCH 8/9] drm/i915: Implement async flips for ilk/snb
From: Ville Syrjälä
Add support for async flips on ivb/hsw. Again no need for any
workarounds and just have to deal with the interrupt bits being
shuffled around a bit.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c| 24
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
drivers/gpu/drm/i915/i915_irq.c | 5
3 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index aa2f6c4ed9ba..3a1922931a3f 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -552,6 +552,26 @@ ivb_primary_disable_flip_done(struct intel_plane *plane)
spin_unlock_irq(>irq_lock);
}
+static void
+ilk_primary_enable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ spin_lock_irq(>irq_lock);
+ ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
+ spin_unlock_irq(>irq_lock);
+}
+
+static void
+ilk_primary_disable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ spin_lock_irq(>irq_lock);
+ ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
+ spin_unlock_irq(>irq_lock);
+}
+
static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
enum pipe *pipe)
{
@@ -728,6 +748,10 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
plane->async_flip = g4x_primary_async_flip;
plane->enable_flip_done = ivb_primary_enable_flip_done;
plane->disable_flip_done = ivb_primary_disable_flip_done;
+ } else if (IS_GEN_RANGE(dev_priv, 5, 6)) {
+ plane->async_flip = g4x_primary_async_flip;
+ plane->enable_flip_done = ilk_primary_enable_flip_done;
+ plane->disable_flip_done = ilk_primary_disable_flip_done;
}
if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 3d6ce3ced92c..c9ad4e935b6b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2123,7 +2123,8 @@ static unsigned int intel_linear_alignment(const struct
drm_i915_private *dev_pr
static bool has_async_flips(struct drm_i915_private *i915)
{
return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915) ||
- IS_HASWELL(i915) || IS_IVYBRIDGE(i915);
+ IS_HASWELL(i915) || IS_IVYBRIDGE(i915) ||
+ IS_GEN_RANGE(i915, 5, 6);
}
static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3518f6f23896..9e04c6b28c12 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2029,6 +2029,9 @@ static void ilk_display_irq_handler(struct
drm_i915_private *dev_priv,
if (de_iir & DE_PIPE_VBLANK(pipe))
intel_handle_vblank(dev_priv, pipe);
+ if (de_iir & DE_PLANE_FLIP_DONE(pipe))
+ flip_done_handler(dev_priv, pipe);
+
if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
@@ -3577,6 +3580,8 @@ static void ilk_irq_postinstall(struct drm_i915_private
*dev_priv)
DE_PIPEA_CRC_DONE | DE_POISON);
extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK |
DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
+ DE_PLANE_FLIP_DONE(PLANE_A) |
+ DE_PLANE_FLIP_DONE(PLANE_B) |
DE_DP_A_HOTPLUG);
}
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/9] drm/i915: Implement async flips for bdw
From: Ville Syrjälä
Implement async flip support for BDW. The implementation is
similar to the skl+ code. And just like skl/bxt/glk bdw also
needs the disable w/a, thus we need to plumb the desired state
of the async flip all the way down to i9xx_plane_ctl_crtc().
According to the spec we do need to bump the surface alignment
to 256KiB for this. Async flips require an X-tiled buffer so
we don't have to worry about linear.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c| 51
drivers/gpu/drm/i915/display/intel_display.c | 10 ++--
drivers/gpu/drm/i915/i915_irq.c | 25 +-
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 73 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b78985c855a5..336a5df32f2f 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -488,6 +488,50 @@ static void i9xx_disable_plane(struct intel_plane *plane,
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
+static void
+g4x_primary_async_flip(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
+ bool async_flip)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
+ u32 dspaddr_offset = plane_state->color_plane[0].offset;
+ enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
+ unsigned long irqflags;
+
+ if (async_flip)
+ dspcntr |= DISPPLANE_ASYNC_FLIP;
+
+ spin_lock_irqsave(_priv->uncore.lock, irqflags);
+ intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
+ intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
+ intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
+ spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
+}
+
+static void
+bdw_primary_enable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+
+ spin_lock_irq(>irq_lock);
+ bdw_enable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
+ spin_unlock_irq(>irq_lock);
+}
+
+static void
+bdw_primary_disable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+
+ spin_lock_irq(>irq_lock);
+ bdw_disable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
+ spin_unlock_irq(>irq_lock);
+}
+
static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
enum pipe *pipe)
{
@@ -655,6 +699,13 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
plane->get_hw_state = i9xx_plane_get_hw_state;
plane->check_plane = i9xx_plane_check;
+ if (IS_BROADWELL(dev_priv)) {
+ plane->need_async_flip_disable_wa = true;
+ plane->async_flip = g4x_primary_async_flip;
+ plane->enable_flip_done = bdw_primary_enable_flip_done;
+ plane->disable_flip_done = bdw_primary_disable_flip_done;
+ }
+
if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
ret = drm_universal_plane_init(_priv->drm, >base,
0, plane_funcs,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 24cf77458dec..794b32d21a11 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2120,6 +2120,11 @@ static unsigned int intel_linear_alignment(const struct
drm_i915_private *dev_pr
return 0;
}
+static bool has_async_flips(struct drm_i915_private *i915)
+{
+ return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915);
+}
+
static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
int color_plane)
{
@@ -2134,7 +2139,7 @@ static unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
case DRM_FORMAT_MOD_LINEAR:
return intel_linear_alignment(dev_priv);
case I915_FORMAT_MOD_X_TILED:
- if (INTEL_GEN(dev_priv) >= 9)
+ if (has_async_flips(dev_priv))
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
@@ -17093,8 +17098,7 @@ static void intel_mode_config_init(struct
drm_i915_private *i915)
mode_config->funcs = _mode_funcs;
- if (INTEL_GEN(i915) >= 9)
- mode_config->async_page_flip = true;
+ mode_config->async_page_flip = has_async_flips(i915);
/*
[Intel-gfx] [PATCH 5/9] drm/i915: Reuse the async_flip() hook for the async flip disable w/a
From: Ville Syrjälä
On some platforms we need to trigger an extra async flip with
the async flip bit disabled, and then wait for the next vblank
until the async flip bit off state will actually latch.
Currently the w/a is just open coded for skl+ universal planes.
Instead of doing that lets reuse the .async_flip() hook for this
purpose since it needs to write the exact same set of registers.
In order to do this we'll just have the caller pass in the state
of the async flip bit explicitly.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 59 ---
.../drm/i915/display/intel_display_types.h| 4 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 7 ++-
4 files changed, 35 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index b5e1ee99535c..4683f98f7e54 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -452,7 +452,7 @@ void intel_update_plane(struct intel_plane *plane,
trace_intel_update_plane(>base, crtc);
if (crtc_state->uapi.async_flip && plane->async_flip)
- plane->async_flip(plane, crtc_state, plane_state);
+ plane->async_flip(plane, crtc_state, plane_state, true);
else
plane->update_plane(plane, crtc_state, plane_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c1e98868eb2e..24cf77458dec 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6162,41 +6162,36 @@ static void intel_crtc_disable_flip_done(struct
intel_atomic_state *state,
}
}
-static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- const struct intel_crtc_state
*new_crtc_state)
+static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ u8 update_planes = new_crtc_state->update_planes;
+ const struct intel_plane_state *old_plane_state;
struct intel_plane *plane;
- struct intel_plane_state *new_plane_state;
+ bool need_vbl_wait = false;
int i;
- for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
- u32 update_mask = new_crtc_state->update_planes;
- u32 plane_ctl, surf_addr;
- enum plane_id plane_id;
- unsigned long irqflags;
- enum pipe pipe;
-
- if (crtc->pipe != plane->pipe ||
- !(update_mask & BIT(plane->id)))
- continue;
-
- plane_id = plane->id;
- pipe = plane->pipe;
-
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
- plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe,
plane_id));
- surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe,
plane_id));
-
- plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
-
- intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id),
plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
surf_addr);
- spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
+ for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
+ if (plane->need_async_flip_disable_wa &&
+ plane->pipe == crtc->pipe &&
+ update_planes & BIT(plane->id)) {
+ /*
+* Apart from the async flip bit we want to
+* preserve the old state for the plane.
+*/
+ plane->async_flip(plane, old_crtc_state,
+ old_plane_state, false);
+ need_vbl_wait = true;
+ }
}
- intel_wait_for_vblank(dev_priv, crtc->pipe);
+ if (need_vbl_wait)
+ intel_wait_for_vblank(i915, crtc->pipe);
}
static void intel_pre_plane_update(struct intel_atomic_state *state,
@@ -6289,10 +6284,8 @@ static void intel_pre_plane_update(struct
intel_atomic_state *state,
* WA for platforms where async address update enable bit
* is double buffered and only latched at
[Intel-gfx] [PATCH 4/9] drm/i915: Move the async_flip bit setup into the .async_flip() hook
From: Ville Syrjälä Set up the async flip PLANE_CTL bit directly in the .async_flip() hook. Neither .update_plane() nor .disable_plane() ever need to set this so having it done by skl_plane_ctl_crtc() is rather pointless. Cc: Karthik B S Cc: Vandita Kulkarni Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 3 --- drivers/gpu/drm/i915/display/intel_sprite.c | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 12d556b0d7e4..c1e98868eb2e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4246,9 +4246,6 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); u32 plane_ctl = 0; - if (crtc_state->uapi.async_flip) - plane_ctl |= PLANE_CTL_ASYNC_FLIP; - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) return plane_ctl; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index affd8cffa306..2798ee005ca0 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -782,6 +782,8 @@ skl_plane_async_flip(struct intel_plane *plane, plane_ctl |= skl_plane_ctl_crtc(crtc_state); + plane_ctl |= PLANE_CTL_ASYNC_FLIP; + spin_lock_irqsave(_priv->uncore.lock, irqflags); intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/9] drm/i915: Generalize the async flip capability check
From: Ville Syrjälä Only assign the plane->async_flip() vfunc when the plane supports async flips. For now we keep this artificially limited to the primary plane since thats the only thing the legacy page flip uapi can target and there is no async flip support in the atomic uapi yet. Cc: Karthik B S Cc: Vandita Kulkarni Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_sprite.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0189d379a55e..aec403712c63 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14373,7 +14373,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state) * this(vlv/chv and icl+) should be added when async flip is * enabled in the atomic IOCTL path. */ - if (plane->id != PLANE_PRIMARY) + if (!plane->async_flip) return -EINVAL; /* diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index cf3589fd0ddb..e839a7748068 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -3290,7 +3290,9 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->get_hw_state = skl_plane_get_hw_state; plane->check_plane = skl_plane_check; plane->min_cdclk = skl_plane_min_cdclk; - plane->async_flip = skl_plane_async_flip; + + if (plane_id == PLANE_PRIMARY) + plane->async_flip = skl_plane_async_flip; if (INTEL_GEN(dev_priv) >= 11) formats = icl_get_plane_formats(dev_priv, pipe, -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/9] drm/i915: Drop redundant parens
From: Ville Syrjälä
Drop the pointless extra parens.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dd1971040bbc..4484609d870d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2079,7 +2079,7 @@ static void ivb_display_irq_handler(struct
drm_i915_private *dev_priv,
intel_opregion_asle_intr(dev_priv);
for_each_pipe(dev_priv, pipe) {
- if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
+ if (de_iir & DE_PIPE_VBLANK_IVB(pipe))
intel_handle_vblank(dev_priv, pipe);
}
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/9] drm/i915: Async flips for all ilk+ platforms
From: Ville Syrjälä MMIO async flips have been suported since g4x. We can easily enable them for all ilk+ platforms. So let's do that. g4x is more problematic since it doesn't have a flip done interrupt (which the current solution depends on), and the flip pending blit that it does have only works with CS flips. Some potential ideas would involve just polling the live surface register etc. but not sure it's worth the hassle. So at least for the time being we leave g4x out in the cold. Ville Syrjälä (9): drm/i915: Drop redundant parens drm/i915: Generalize the async flip capability check drm/i915: Add plane vfuncs to enable/disable flip_done interrupt drm/i915: Move the async_flip bit setup into the .async_flip() hook drm/i915: Reuse the async_flip() hook for the async flip disable w/a drm/i915: Implement async flips for bdw drm/i915: Implement async flips for ivb/hsw drm/i915: Implement async flips for ilk/snb drm/i915: Implement async flips for vlv/chv drivers/gpu/drm/i915/display/i9xx_plane.c | 142 ++ .../gpu/drm/i915/display/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 108 - .../drm/i915/display/intel_display_types.h| 6 +- drivers/gpu/drm/i915/display/intel_sprite.c | 36 - drivers/gpu/drm/i915/i915_irq.c | 67 - drivers/gpu/drm/i915/i915_irq.h | 3 - drivers/gpu/drm/i915/i915_reg.h | 3 + 8 files changed, 283 insertions(+), 84 deletions(-) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gt: Prevent use of engine->wa_ctx after error
On Fri, Jan 08, 2021 at 03:09:24PM +, Chris Wilson wrote:
> On error we unpin and free the wa_ctx.vma, but do not clear any of the
> derived flags. During lrc_init, we look at the flags and attempt to
> dereference the wa_ctx.vma if they are set. To protect the error path
> where we try to limp along without the wa_ctx, make sure we clear those
> flags!
>
> Reported-by: Matt Roper
> Fixes: 604a8f6f1e33 ("drm/i915/lrc: Only enable per-context and per-bb
> buffers if set")
> Signed-off-by: Chris Wilson
> Cc: Matt Roper
> Cc: Tvrtko Ursulin
> Cc: Mika Kuoppala
> Cc: # v4.15+
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 4e856947fb13..703d9ecc3f7e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1453,6 +1453,9 @@ static int lrc_setup_wa_ctx(struct intel_engine_cs
> *engine)
> void lrc_fini_wa_ctx(struct intel_engine_cs *engine)
> {
> i915_vma_unpin_and_release(>wa_ctx.vma, 0);
> +
> + /* Called on error unwind, clear all flags to prevent further use */
> + memset(>wa_ctx, 0, sizeof(engine->wa_ctx));
> }
>
> typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
> --
> 2.20.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with drm/i915/selftests: Skip unstable timing measurements (rev4)
== Series Details == Series: series starting with drm/i915/selftests: Skip unstable timing measurements (rev4) URL : https://patchwork.freedesktop.org/series/85596/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:869:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with drm/i915/selftests: Skip unstable timing measurements (rev4)
== Series Details ==
Series: series starting with drm/i915/selftests: Skip unstable timing
measurements (rev4)
URL : https://patchwork.freedesktop.org/series/85596/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
32998db1cdb6 drm/i915/selftests: Skip unstable timing measurements
ee160682ce23 drm/i915/gt: Restore ce->signal flush before releasing virtual
engine
-:14: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit bab0557c8dca ("drm/i915/gt:
Remove virtual breadcrumb before transfer")'
#14:
bab0557c8dca ("drm/i915/gt: Remove virtual breadcrumb before transfer"),
total: 1 errors, 0 warnings, 0 checks, 90 lines checked
f1eef8304063 drm/i915/gt: Only retire on the last breadcrumb if the last request
72c97acf0662 drm/i915/gt: Only disable preemption on gen8 render engines
41cf60168fed drm/i915/gt: Disable arbitration on no-preempt requests
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Prevent use of engine->wa_ctx after error
== Series Details == Series: drm/i915/gt: Prevent use of engine->wa_ctx after error URL : https://patchwork.freedesktop.org/series/85618/ State : success == Summary == CI Bug Log - changes from CI_DRM_9567 -> Patchwork_19293 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/index.html Known issues Here are the changes found in Patchwork_19293 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html * igt@i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][4] ([i915#2029]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/fi-bdw-5557u/igt@run...@aborted.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-tgl-y/igt@debugfs_test@read_all_entries.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@i915_selftest@live@gem: - fi-kbl-soraka: [DMESG-FAIL][7] -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-kbl-soraka/igt@i915_selftest@l...@gem.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/fi-kbl-soraka/igt@i915_selftest@l...@gem.html * igt@i915_selftest@live@reset: - fi-kbl-soraka: [SKIP][9] ([fdo#109271]) -> [PASS][10] +12 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9567/fi-kbl-soraka/igt@i915_selftest@l...@reset.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/fi-kbl-soraka/igt@i915_selftest@l...@reset.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 37) -- Missing(6): fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9567 -> Patchwork_19293 CI-20190529: 20190529 CI_DRM_9567: 9fc1f6dac2ec9339e390931322768a0286f01f71 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5951: fec3b9c7d88357144f0d7a1447b9316a1c81da1a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19293: dcd5cec48b31afb4ecebf7073238dfdbce8107b2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == dcd5cec48b31 drm/i915/gt: Prevent use of engine->wa_ctx after error == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19293/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Disable RPM wakeref assertions during driver shutdown
On Mon, Jan 04, 2021 at 08:39:05PM +, Chris Wilson wrote:
> As with the regular suspend paths, also disable the wakeref assertions
> as we disable the driver during shutdown.
>
> Reported-by: Hans de Goede
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2899
> Fixes: fe0f1e3bfdfe ("drm/i915: Shut down displays gracefully on reboot")
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> Cc: Hans de Goede
lgtm
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 249f765993f7..643a899b3b44 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1046,6 +1046,8 @@ static void intel_shutdown_encoders(struct
> drm_i915_private *dev_priv)
>
> void i915_driver_shutdown(struct drm_i915_private *i915)
> {
> + disable_rpm_wakeref_asserts(>runtime_pm);
> +
> i915_gem_suspend(i915);
>
> drm_kms_helper_poll_disable(>drm);
> @@ -1059,6 +1061,8 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
>
> intel_suspend_encoders(i915);
> intel_shutdown_encoders(i915);
> +
> + enable_rpm_wakeref_asserts(>runtime_pm);
> }
>
> static bool suspend_to_idle(struct drm_i915_private *dev_priv)
> --
> 2.20.1
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix HTI port checking
On Fri, Jan 08, 2021 at 05:48:02AM -0800, José Roberto de Souza wrote:
> There was some misinterpretation of specification, when DDIX_USED is
> set, the next bit means 0 for DP and 1 for HDMI.
>
> Anyways this misinterpretation is not causing any issues, this change
> is just to comply with specification.
> Also as for us it do not matters if it is HDMI or DP, not checking the
> port type that HTI is using.
>
> Cc: Anusha Srivatsa
> Cc: Matt Roper
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +--
> drivers/gpu/drm/i915/i915_reg.h | 3 +--
> 2 files changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3df6913369bc..e90d1af1a54d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5321,8 +5321,7 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port)
> static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
> {
> return i915->hti_state & HDPORT_ENABLED &&
> - (i915->hti_state & HDPORT_PHY_USED_DP(phy) ||
> - i915->hti_state & HDPORT_PHY_USED_HDMI(phy));
> +i915->hti_state & HDPORT_DDI_USED(phy);
> }
>
> static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0023c023f472..1d8ba10847ca 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2928,8 +2928,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>
> #define HDPORT_STATE _MMIO(0x45050)
> #define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12)
> -#define HDPORT_PHY_USED_DP(phy)REG_BIT(2 * (phy) + 2)
> -#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1)
> +#define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1)
> #define HDPORT_ENABLED REG_BIT(0)
>
> /* Make render/texture TLB fetches lower priorty than associated data
> --
> 2.30.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Missing DPPLL case on i7-1165G7
On Wed, 06 Jan 2021, Imre Deak wrote: > On Tue, Jan 05, 2021 at 05:50:41AM +, Matthew Wilcox wrote: >> On Tue, Dec 29, 2020 at 04:41:31PM +0200, Imre Deak wrote: >> > Hi, >> > >> > On Mon, Dec 21, 2020 at 04:07:58AM +, Matthew Wilcox wrote: >> > > >> > > At boot, >> > > >> > > [2.787995] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon >> > > [2.788001] i915 :00:02.0: [drm] *ERROR* LSPCON init failed on >> > > port E >> > > [2.790752] [ cut here ] >> > > [2.790753] Missing case (clock == 539440) >> > > [2.790790] WARNING: CPU: 0 PID: 159 at >> > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2967 >> > > icl_get_dplls+0x53a/0xa50 [i915] >> > >> > the above warn looks to be due to a missing workaround fixed by >> > >> > commit 0e2497e334de42dbaaee8e325241b5b5b34ede7e >> > Author: Imre Deak >> > Date: Sat Oct 3 03:18:46 2020 +0300 >> > >> > drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref >> > clock >> > >> > in drm-tip. Could you give it a try? >> >> I tried -rc2, which contains that commit, and the problem is gone. Thank >> you! > > Thanks for testing it, I'll send a patch for the 5.10 stable tree as > well. > >> There is a different problem, which is that the brightness buttons >> (on F2 and F3 on this laptop) do not actually increase/decrease the >> brightness. GNOME pops up a graphic that illustrates it is changing >> the brightness, but nothing actually changes. >> >> xbacklight says "No outputs have backlight property" and using >> xrandr --output XWAYLAND0 --brightness 0.0001 doesn't change anything >> (for various different values, not just 0.0001). Using xrandr --prop >> --verbose shows the reported value of "Brightness" changing, but nothing >> has changed on the screen. >> >> I found >> /sys/devices/pci:00/:00:02.0/drm/card0/card0-eDP-1/intel_backlight >> and tried setting 'brightness' in there to a few different values (100, >> 2000, 19200, 7000) and also nothing changed. >> >> Any thoughts? > > One possibility is that from the different backlight methods (DPCD, > direct PWM on a CPU pin) the driver selects the incorrect one. Could you > provide a log booting with drm.debug=0x1e adding it to a new ticket at > > https://gitlab.freedesktop.org/drm/intel/-/issues/new?issue > > or at least in a reply to this thread? > > Adding Jani for further ideas. Please try: 1) i915.enable_dpcd_backlight=1 module param 2) https://cgit.freedesktop.org/drm/drm-tip drm-tip branch with patches from Lyude on top https://patchwork.freedesktop.org/series/81702/ BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/13] drm/i915/pps: abstract intel_pps_vdd_off_sync
On Tue, 29 Dec 2020, Anshuman Gupta wrote:
> On 2020-12-22 at 20:19:46 +0530, Jani Nikula wrote:
>> Add a locked version of intel_pps_vdd_off_sync_unlocked() that does
>> everything the callers expect it to.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 31 +++-
>> drivers/gpu/drm/i915/display/intel_pps.c | 17 -
>> drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
>> 3 files changed, 20 insertions(+), 30 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index f2794cc4292a..1a34c9351c30 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -5809,17 +5809,8 @@ void intel_dp_encoder_flush_work(struct drm_encoder
>> *encoder)
>> struct intel_dp *intel_dp = _port->dp;
>>
>> intel_dp_mst_encoder_cleanup(dig_port);
>> -if (intel_dp_is_edp(intel_dp)) {
>> -intel_wakeref_t wakeref;
>>
>> -cancel_delayed_work_sync(_dp->panel_vdd_work);
>> -/*
>> - * vdd might still be enabled do to the delayed vdd off.
>> - * Make sure vdd is actually turned off here.
>> - */
>> -with_intel_pps_lock(intel_dp, wakeref)
>> -intel_pps_vdd_off_sync_unlocked(intel_dp);
>> -}
>> +intel_pps_vdd_off_sync(intel_dp);
>>
>> intel_dp_aux_fini(intel_dp);
>> }
>> @@ -5835,18 +5826,8 @@ static void intel_dp_encoder_destroy(struct
>> drm_encoder *encoder)
>> void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
>> {
>> struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
>> -intel_wakeref_t wakeref;
>> -
>> -if (!intel_dp_is_edp(intel_dp))
>> -return;
>>
>> -/*
>> - * vdd might still be enabled do to the delayed vdd off.
>> - * Make sure vdd is actually turned off here.
>> - */
>> -cancel_delayed_work_sync(_dp->panel_vdd_work);
>> -with_intel_pps_lock(intel_dp, wakeref)
>> -intel_pps_vdd_off_sync_unlocked(intel_dp);
>> +intel_pps_vdd_off_sync(intel_dp);
>> }
>>
>> void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
>> @@ -6700,13 +6681,7 @@ static bool intel_edp_init_connector(struct intel_dp
>> *intel_dp,
>> return true;
>>
>> out_vdd_off:
>> -cancel_delayed_work_sync(_dp->panel_vdd_work);
>> -/*
>> - * vdd might still be enabled do to the delayed vdd off.
>> - * Make sure vdd is actually turned off here.
>> - */
>> -with_intel_pps_lock(intel_dp, wakeref)
>> -intel_pps_vdd_off_sync_unlocked(intel_dp);
>> +intel_pps_vdd_off_sync(intel_dp);
>>
>> return false;
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
>> b/drivers/gpu/drm/i915/display/intel_pps.c
>> index 01c9e69f4e3a..acd6d0092bc6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> @@ -641,7 +641,7 @@ void intel_pps_vdd_on(struct intel_dp *intel_dp)
>> dp_to_dig_port(intel_dp)->base.base.name);
>> }
>>
>> -void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
>> +static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
>> {
>> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> struct intel_digital_port *dig_port =
>> @@ -682,6 +682,21 @@ void intel_pps_vdd_off_sync_unlocked(struct intel_dp
>> *intel_dp)
>> fetch_and_zero(_dp->vdd_wakeref));
>> }
>>
>> +void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
>> +{
>> +intel_wakeref_t wakeref;
>> +if (!intel_dp_is_edp(intel_dp))
>> +return;
>> +
>> +cancel_delayed_work_sync(_dp->panel_vdd_work);
>> +/*
>> + * vdd might still be enabled do to the delayed vdd off.
> I belive there is a typo here "do -> due"
I just copy-pasted this over, but fixed in v2.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 16/17] drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
Add some namespacing to highlight what belongs where. No functional
changes.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_debugfs.c | 8 +-
.../drm/i915/display/intel_display_types.h| 61 +++---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
drivers/gpu/drm/i915/display/intel_pps.c | 192 +-
4 files changed, 140 insertions(+), 135 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cd7e5519ee7d..885d2d3c91a3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2155,13 +2155,13 @@ static int i915_panel_show(struct seq_file *m, void
*data)
return -ENODEV;
seq_printf(m, "Panel power up delay: %d\n",
- intel_dp->panel_power_up_delay);
+ intel_dp->pps.panel_power_up_delay);
seq_printf(m, "Panel power down delay: %d\n",
- intel_dp->panel_power_down_delay);
+ intel_dp->pps.panel_power_down_delay);
seq_printf(m, "Backlight on delay: %d\n",
- intel_dp->backlight_on_delay);
+ intel_dp->pps.backlight_on_delay);
seq_printf(m, "Backlight off delay: %d\n",
- intel_dp->backlight_off_delay);
+ intel_dp->pps.backlight_off_delay);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1067bd073c95..69b34378cc6e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1344,6 +1344,38 @@ struct intel_dp_pcon_frl {
int trained_rate_gbps;
};
+struct intel_pps {
+ int panel_power_up_delay;
+ int panel_power_down_delay;
+ int panel_power_cycle_delay;
+ int backlight_on_delay;
+ int backlight_off_delay;
+ struct delayed_work panel_vdd_work;
+ bool want_panel_vdd;
+ unsigned long last_power_on;
+ unsigned long last_backlight_off;
+ ktime_t panel_power_off_time;
+ intel_wakeref_t vdd_wakeref;
+
+ /*
+* Pipe whose power sequencer is currently locked into
+* this port. Only relevant on VLV/CHV.
+*/
+ enum pipe pps_pipe;
+ /*
+* Pipe currently driving the port. Used for preventing
+* the use of the PPS for any pipe currentrly driving
+* external DP as that will mess things up on VLV.
+*/
+ enum pipe active_pipe;
+ /*
+* Set if the sequencer may be reset due to a power transition,
+* requiring a reinitialization. Only relevant on BXT.
+*/
+ bool pps_reset;
+ struct edp_power_seq pps_delays;
+};
+
struct intel_dp {
i915_reg_t output_reg;
u32 DP;
@@ -1383,35 +1415,8 @@ struct intel_dp {
struct drm_dp_aux aux;
u32 aux_busy_last_status;
u8 train_set[4];
- int panel_power_up_delay;
- int panel_power_down_delay;
- int panel_power_cycle_delay;
- int backlight_on_delay;
- int backlight_off_delay;
- struct delayed_work panel_vdd_work;
- bool want_panel_vdd;
- unsigned long last_power_on;
- unsigned long last_backlight_off;
- ktime_t panel_power_off_time;
- intel_wakeref_t vdd_wakeref;
- /*
-* Pipe whose power sequencer is currently locked into
-* this port. Only relevant on VLV/CHV.
-*/
- enum pipe pps_pipe;
- /*
-* Pipe currently driving the port. Used for preventing
-* the use of the PPS for any pipe currentrly driving
-* external DP as that will mess things up on VLV.
-*/
- enum pipe active_pipe;
- /*
-* Set if the sequencer may be reset due to a power transition,
-* requiring a reinitialization. Only relevant on BXT.
-*/
- bool pps_reset;
- struct edp_power_seq pps_delays;
+ struct intel_pps pps;
bool can_mst; /* this port supports mst */
bool is_mst;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a8835e3b1ac1..e6859b9925b9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4075,7 +4075,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
}
- msleep(intel_dp->panel_power_down_delay);
+ msleep(intel_dp->pps.panel_power_down_delay);
intel_dp->DP = DP;
@@ -4083,7 +4083,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
intel_wakeref_t wakeref;
with_intel_pps_lock(intel_dp, wakeref)
- intel_dp->active_pipe = INVALID_PIPE;
+
[Intel-gfx] [PATCH v2 17/17] drm/i915/dp: split out aux functionality to intel_dp_aux.c
Split out the DP aux functionality to a new intel_dp_aux.[ch]. This is a
surprisingly clean cut.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 680 +--
drivers/gpu/drm/i915/display/intel_dp_aux.c | 687
drivers/gpu/drm/i915/display/intel_dp_aux.h | 18 +
4 files changed, 707 insertions(+), 679 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8a04403a11bb..71df8cbd63bc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -238,6 +238,7 @@ i915-y += \
display/intel_crt.o \
display/intel_ddi.o \
display/intel_dp.o \
+ display/intel_dp_aux.o \
display/intel_dp_aux_backlight.o \
display/intel_dp_hdcp.o \
display/intel_dp_link_training.o \
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index e6859b9925b9..1705d58bf64c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -41,13 +41,13 @@
#include "i915_debugfs.h"
#include "i915_drv.h"
-#include "i915_trace.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_connector.h"
#include "intel_ddi.h"
#include "intel_display_types.h"
#include "intel_dp.h"
+#include "intel_dp_aux.h"
#include "intel_dp_link_training.h"
#include "intel_dp_mst.h"
#include "intel_dpio_phy.h"
@@ -856,684 +856,6 @@ intel_dp_mode_valid(struct drm_connector *connector,
return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
}
-u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
-{
- int i;
- u32 v = 0;
-
- if (src_bytes > 4)
- src_bytes = 4;
- for (i = 0; i < src_bytes; i++)
- v |= ((u32)src[i]) << ((3 - i) * 8);
- return v;
-}
-
-static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
-{
- int i;
- if (dst_bytes > 4)
- dst_bytes = 4;
- for (i = 0; i < dst_bytes; i++)
- dst[i] = src >> ((3-i) * 8);
-}
-
-static u32
-intel_dp_aux_wait_done(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
- const unsigned int timeout_ms = 10;
- u32 status;
- bool done;
-
-#define C (((status = intel_uncore_read_notrace(>uncore, ch_ctl)) &
DP_AUX_CH_CTL_SEND_BUSY) == 0)
- done = wait_event_timeout(i915->gmbus_wait_queue, C,
- msecs_to_jiffies_timeout(timeout_ms));
-
- /* just trace the final value */
- trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
-
- if (!done)
- drm_err(>drm,
- "%s: did not complete or timeout within %ums (status
0x%08x)\n",
- intel_dp->aux.name, timeout_ms, status);
-#undef C
-
- return status;
-}
-
-static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- if (index)
- return 0;
-
- /*
-* The clock divider is based off the hrawclk, and would like to run at
-* 2MHz. So, take the hrawclk value and divide by 2000 and use that
-*/
- return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
-}
-
-static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- u32 freq;
-
- if (index)
- return 0;
-
- /*
-* The clock divider is based off the cdclk or PCH rawclk, and would
-* like to run at 2MHz. So, take the cdclk or PCH rawclk value and
-* divide by 2000 and use that
-*/
- if (dig_port->aux_ch == AUX_CH_A)
- freq = dev_priv->cdclk.hw.cdclk;
- else
- freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
- return DIV_ROUND_CLOSEST(freq, 2000);
-}
-
-static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-
- if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
- /* Workaround for non-ULT HSW */
- switch (index) {
- case 0: return 63;
- case 1: return 72;
- default: return 0;
- }
- }
-
- return ilk_get_aux_clock_divider(intel_dp, index);
-}
-
-static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- /*
-
[Intel-gfx] [PATCH v2 14/17] drm/i915/pps: refactor init abstractions
Once you realize there is no need to hold the pps mutex when calling
pps_init_timestamps() in intel_pps_init(), we can reuse
intel_pps_encoder_reset() which has the same code.
Since intel_dp_pps_init() is only called from one place now, move it
inline to remove one "init" function altogether.
Finally, remove some initialization from
vlv_initial_power_sequencer_setup() and do it in the caller to highlight
the similarity, not the difference, in the platforms.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_pps.c | 33 +++-
1 file changed, 10 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 58eff6289d12..b4d026ca3313 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -305,9 +305,6 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
dig_port->base.base.base.id,
dig_port->base.base.name,
pipe_name(intel_dp->pps_pipe));
-
- pps_init_delays(intel_dp);
- pps_init_registers(intel_dp, false);
}
void intel_pps_reset_all(struct drm_i915_private *dev_priv)
@@ -1342,20 +1339,9 @@ static void pps_init_registers(struct intel_dp
*intel_dp, bool force_disable_vdd
(intel_de_read(dev_priv, regs.pp_ctrl) &
BXT_POWER_CYCLE_DELAY_MASK));
}
-static void intel_dp_pps_init(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- vlv_initial_power_sequencer_setup(intel_dp);
- } else {
- pps_init_delays(intel_dp);
- pps_init_registers(intel_dp, false);
- }
-}
-
void intel_pps_encoder_reset(struct intel_dp *intel_dp)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
intel_wakeref_t wakeref;
if (!intel_dp_is_edp(intel_dp))
@@ -1366,20 +1352,21 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp)
* Reinit the power sequencer, in case BIOS did something nasty
* with it.
*/
- intel_dp_pps_init(intel_dp);
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ vlv_initial_power_sequencer_setup(intel_dp);
+
+ pps_init_delays(intel_dp);
+ pps_init_registers(intel_dp, false);
+
intel_pps_vdd_sanitize(intel_dp);
}
}
void intel_pps_init(struct intel_dp *intel_dp)
{
- intel_wakeref_t wakeref;
-
INIT_DELAYED_WORK(_dp->panel_vdd_work, edp_panel_vdd_work);
- with_intel_pps_lock(intel_dp, wakeref) {
- pps_init_timestamps(intel_dp);
- intel_dp_pps_init(intel_dp);
- intel_pps_vdd_sanitize(intel_dp);
- }
+ pps_init_timestamps(intel_dp);
+
+ intel_pps_encoder_reset(intel_dp);
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 15/17] drm/i915/pps: move pps code over from intel_display.c and refactor
intel_display.c has some pps functions that belong to intel_pps.c. Move
them over.
While at it, refactor the duplicate intel_pps_init() in intel_display.c
into an orthogonal intel_pps_setup() in intel_pps.c, and call it earlier
in intel_modeset_init_nogem().
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 41 ++--
drivers/gpu/drm/i915/display/intel_display.h | 1 -
drivers/gpu/drm/i915/display/intel_pps.c | 34
drivers/gpu/drm/i915/display/intel_pps.h | 3 ++
drivers/gpu/drm/i915/i915_drv.c | 1 +
5 files changed, 42 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0189d379a55e..f8806c4ecb21 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -81,6 +81,7 @@
#include "intel_overlay.h"
#include "intel_pipe_crc.h"
#include "intel_pm.h"
+#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_quirks.h"
#include "intel_sideband.h"
@@ -16100,48 +16101,12 @@ static bool intel_ddi_crt_present(struct
drm_i915_private *dev_priv)
return true;
}
-void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
-{
- int pps_num;
- int pps_idx;
-
- if (HAS_DDI(dev_priv))
- return;
- /*
-* This w/a is needed at least on CPT/PPT, but to be sure apply it
-* everywhere where registers can be write protected.
-*/
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- pps_num = 2;
- else
- pps_num = 1;
-
- for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
- u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
-
- val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
- intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
- }
-}
-
-static void intel_pps_init(struct drm_i915_private *dev_priv)
-{
- if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
- dev_priv->pps_mmio_base = PCH_PPS_BASE;
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->pps_mmio_base = VLV_PPS_BASE;
- else
- dev_priv->pps_mmio_base = PPS_BASE;
-
- intel_pps_unlock_regs_wa(dev_priv);
-}
-
static void intel_setup_outputs(struct drm_i915_private *dev_priv)
{
struct intel_encoder *encoder;
bool dpd_is_edp = false;
- intel_pps_init(dev_priv);
+ intel_pps_unlock_regs_wa(dev_priv);
if (!HAS_DISPLAY(dev_priv))
return;
@@ -17199,6 +17164,8 @@ int intel_modeset_init_nogem(struct drm_i915_private
*i915)
intel_panel_sanitize_ssc(i915);
+ intel_pps_setup(i915);
+
intel_gmbus_setup(i915);
drm_dbg_kms(>drm, "%d display pipe%s available.\n",
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 7ddbc00a0f41..bbd5dbc61ce9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -546,7 +546,6 @@ unsigned int intel_rotation_info_size(const struct
intel_rotation_info *rot_info
unsigned int intel_remapped_info_size(const struct intel_remapped_info
*rem_info);
bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
int intel_display_suspend(struct drm_device *dev);
-void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
void intel_encoder_destroy(struct drm_encoder *encoder);
struct drm_display_mode *
intel_encoder_current_mode(struct intel_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index b4d026ca3313..c3a0fc933500 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1370,3 +1370,37 @@ void intel_pps_init(struct intel_dp *intel_dp)
intel_pps_encoder_reset(intel_dp);
}
+
+void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
+{
+ int pps_num;
+ int pps_idx;
+
+ if (HAS_DDI(dev_priv))
+ return;
+ /*
+* This w/a is needed at least on CPT/PPT, but to be sure apply it
+* everywhere where registers can be write protected.
+*/
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ pps_num = 2;
+ else
+ pps_num = 1;
+
+ for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
+ u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
+
+ val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
+ intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
+ }
+}
+
+void intel_pps_setup(struct drm_i915_private *i915)
+{
+ if (HAS_PCH_SPLIT(i915) || IS_GEN9_LP(i915))
+ i915->pps_mmio_base = PCH_PPS_BASE;
+ else if
[Intel-gfx] [PATCH v2 13/17] drm/i915/pps: rename intel_dp_init_panel_power_sequencer* functions
There are a number of functions that "init" pps in various ways. Try to
find some more consistency in the naming.
Rename:
- intel_dp_init_panel_power_sequencer -> pps_init_delays
- intel_dp_init_panel_power_sequencer_registers -> pps_init_registers
- intel_dp_init_panel_power_timestamps -> pps_init_timestamps
as this is what the functions do. Skip the intel_ prefix here to
emphasize these are static and not exported.
No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_pps.c | 37 ++--
1 file changed, 16 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 8925df55e22e..58eff6289d12 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -10,11 +10,9 @@
static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
enum pipe pipe);
-static void
-intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
-static void
-intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
- bool force_disable_vdd);
+
+static void pps_init_delays(struct intel_dp *intel_dp);
+static void pps_init_registers(struct intel_dp *intel_dp, bool
force_disable_vdd);
intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
{
@@ -190,8 +188,8 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
dig_port->base.base.name);
/* init power sequencer on this pipe and port */
- intel_dp_init_panel_power_sequencer(intel_dp);
- intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
+ pps_init_delays(intel_dp);
+ pps_init_registers(intel_dp, true);
/*
* Even vdd force doesn't work until we've made
@@ -222,7 +220,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
* Only the HW needs to be reprogrammed, the SW state is fixed and
* has been setup during connector init.
*/
- intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
+ pps_init_registers(intel_dp, false);
return backlight_controller;
}
@@ -308,8 +306,8 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
dig_port->base.base.name,
pipe_name(intel_dp->pps_pipe));
- intel_dp_init_panel_power_sequencer(intel_dp);
- intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
+ pps_init_delays(intel_dp);
+ pps_init_registers(intel_dp, false);
}
void intel_pps_reset_all(struct drm_i915_private *dev_priv)
@@ -1046,8 +1044,8 @@ void vlv_pps_init(struct intel_encoder *encoder,
encoder->base.name);
/* init power sequencer on this pipe and port */
- intel_dp_init_panel_power_sequencer(intel_dp);
- intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
+ pps_init_delays(intel_dp);
+ pps_init_registers(intel_dp, true);
}
static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
@@ -1088,7 +1086,7 @@ bool intel_pps_have_power(struct intel_dp *intel_dp)
return have_power;
}
-static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
+static void pps_init_timestamps(struct intel_dp *intel_dp)
{
intel_dp->panel_power_off_time = ktime_get_boottime();
intel_dp->last_power_on = jiffies;
@@ -1154,8 +1152,7 @@ intel_pps_verify_state(struct intel_dp *intel_dp)
}
}
-static void
-intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
+static void pps_init_delays(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct edp_power_seq cur, vbt, spec,
@@ -1250,9 +1247,7 @@ intel_dp_init_panel_power_sequencer(struct intel_dp
*intel_dp)
final->t11_t12 = roundup(final->t11_t12, 100 * 10);
}
-static void
-intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
- bool force_disable_vdd)
+static void pps_init_registers(struct intel_dp *intel_dp, bool
force_disable_vdd)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 pp_on, pp_off, port_sel = 0;
@@ -1354,8 +1349,8 @@ static void intel_dp_pps_init(struct intel_dp *intel_dp)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
vlv_initial_power_sequencer_setup(intel_dp);
} else {
- intel_dp_init_panel_power_sequencer(intel_dp);
- intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
+ pps_init_delays(intel_dp);
+ pps_init_registers(intel_dp, false);
}
}
@@ -1383,7 +1378,7 @@ void intel_pps_init(struct intel_dp *intel_dp)
INIT_DELAYED_WORK(_dp->panel_vdd_work, edp_panel_vdd_work);
with_intel_pps_lock(intel_dp,
Re: [Intel-gfx] [PATCH 04/13] drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
On Tue, 29 Dec 2020, Anshuman Gupta wrote: >> /* >> - * Must be paired with intel_edp_panel_vdd_off() or >> - * intel_edp_panel_off(). >> + * Must be paired with intel_pps_vdd_off() or > IMHO can we change the comment, there is no function with name > intel_pps_vdd_off() Fixed in v2. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 12/17] drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init
This function is a bit of an outlier, but try to change to a name that
is more in line with the rest of the intel_pps functions. No functional
changes.
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps.c | 4 ++--
drivers/gpu/drm/i915/display/intel_pps.h | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ffb6f6c9b858..a8835e3b1ac1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3516,7 +3516,7 @@ static void intel_enable_dp(struct intel_atomic_state
*state,
with_intel_pps_lock(intel_dp, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- vlv_init_panel_power_sequencer(encoder, pipe_config);
+ vlv_pps_init(encoder, pipe_config);
intel_dp_enable_port(intel_dp, pipe_config);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 79276ab20c75..8925df55e22e 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1005,8 +1005,8 @@ static void vlv_steal_power_sequencer(struct
drm_i915_private *dev_priv,
}
}
-void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+void vlv_pps_init(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index fdf7a17e2dfa..22045c5cdc86 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -43,7 +43,7 @@ void intel_pps_init(struct intel_dp *intel_dp);
void intel_pps_encoder_reset(struct intel_dp *intel_dp);
void intel_pps_reset_all(struct drm_i915_private *i915);
-void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state);
+void vlv_pps_init(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_PPS_H__ */
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 11/17] drm/i915/pps: add locked intel_pps_wait_power_cycle
Prefer keeping the unlocked variants hidden if possible. No functional
changes.
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 +--
drivers/gpu/drm/i915/display/intel_pps.c | 13 -
drivers/gpu/drm/i915/display/intel_pps.h | 3 +--
3 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1685e48b17cd..ffb6f6c9b858 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6273,13 +6273,8 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
- intel_wakeref_t wakeref;
-
- if (!intel_dp_is_edp(intel_dp))
- return;
- with_intel_pps_lock(intel_dp, wakeref)
- wait_panel_power_cycle(intel_dp);
+ intel_pps_wait_power_cycle(intel_dp);
}
static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index d396ee5f6f69..79276ab20c75 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -500,7 +500,7 @@ static void wait_panel_off(struct intel_dp *intel_dp)
wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
}
-void wait_panel_power_cycle(struct intel_dp *intel_dp)
+static void wait_panel_power_cycle(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
ktime_t panel_power_on_time;
@@ -522,6 +522,17 @@ void wait_panel_power_cycle(struct intel_dp *intel_dp)
wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
}
+void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ with_intel_pps_lock(intel_dp, wakeref)
+ wait_panel_power_cycle(intel_dp);
+}
+
static void wait_backlight_on(struct intel_dp *intel_dp)
{
wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index ecd9ea2a095c..fdf7a17e2dfa 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -37,8 +37,7 @@ void intel_pps_on(struct intel_dp *intel_dp);
void intel_pps_off(struct intel_dp *intel_dp);
void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
bool intel_pps_have_power(struct intel_dp *intel_dp);
-
-void wait_panel_power_cycle(struct intel_dp *intel_dp);
+void intel_pps_wait_power_cycle(struct intel_dp *intel_dp);
void intel_pps_init(struct intel_dp *intel_dp);
void intel_pps_encoder_reset(struct intel_dp *intel_dp);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 10/17] drm/i915/pps: rename intel_power_sequencer_reset to intel_pps_reset_all
Follow the usual naming pattern for functions. "reset all" because it
iterates over all DP encoders. No functional changes.
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++--
drivers/gpu/drm/i915/display/intel_pps.c | 5 ++---
drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index a11bd8213df4..c11c37c65d86 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -936,7 +936,7 @@ static void bxt_enable_dc9(struct drm_i915_private
*dev_priv)
* because PPS registers are always on.
*/
if (!HAS_PCH_SPLIT(dev_priv))
- intel_power_sequencer_reset(dev_priv);
+ intel_pps_reset_all(dev_priv);
gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
}
@@ -1446,7 +1446,7 @@ static void vlv_display_power_well_deinit(struct
drm_i915_private *dev_priv)
/* make sure we're done processing display irqs */
intel_synchronize_irq(dev_priv);
- intel_power_sequencer_reset(dev_priv);
+ intel_pps_reset_all(dev_priv);
/* Prevent us from re-enabling polling on accident in late suspend */
if (!dev_priv->drm.dev->power.is_suspended)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 9e5744578b26..d396ee5f6f69 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -22,8 +22,7 @@ intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
intel_wakeref_t wakeref;
/*
-* See intel_power_sequencer_reset() why we need
-* a power domain reference here.
+* See intel_pps_reset_all() why we need a power domain reference here.
*/
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
mutex_lock(_priv->pps_mutex);
@@ -313,7 +312,7 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
}
-void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
+void intel_pps_reset_all(struct drm_i915_private *dev_priv)
{
struct intel_encoder *encoder;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index e0391c9c8383..ecd9ea2a095c 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -42,7 +42,7 @@ void wait_panel_power_cycle(struct intel_dp *intel_dp);
void intel_pps_init(struct intel_dp *intel_dp);
void intel_pps_encoder_reset(struct intel_dp *intel_dp);
-void intel_power_sequencer_reset(struct drm_i915_private *i915);
+void intel_pps_reset_all(struct drm_i915_private *i915);
void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 09/17] drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked
Follow the usual naming pattern for functions. No functional changes.
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index cfaadeaf9f00..1685e48b17cd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1069,7 +1069,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
*/
cpu_latency_qos_update_request(_dp->pm_qos, 0);
- intel_dp_check_edp(intel_dp);
+ intel_pps_check_power_unlocked(intel_dp);
/* Try to wait for any previous AUX channel activity */
for (try = 0; try < 3; try++) {
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 3b962be4f4c0..9e5744578b26 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -428,7 +428,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
}
-void intel_dp_check_edp(struct intel_dp *intel_dp)
+void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index 7c3b5ea4f47b..e0391c9c8383 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -22,7 +22,6 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
intel_wakeref_t wake
#define with_intel_pps_lock(dp, wf)
\
for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp),
(wf)))
-void intel_dp_check_edp(struct intel_dp *intel_dp);
void intel_pps_backlight_on(struct intel_dp *intel_dp);
void intel_pps_backlight_off(struct intel_dp *intel_dp);
void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
@@ -31,6 +30,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
+void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
void intel_pps_on(struct intel_dp *intel_dp);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 08/17] drm/i915/pps: abstract intel_pps_encoder_reset()
Add an "encoder reset" call to hide some more pps functions, and clean
up the callers. A minor functional change is not holding the pps lock
across the whole operation in intel_dp_encoder_reset, but instead doing
it in two steps.
v2: rename intel_pps_reinit to intel_pps_encoder_reset for clarity
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 +---
drivers/gpu/drm/i915/display/intel_pps.c | 21 +++--
drivers/gpu/drm/i915/display/intel_pps.h | 3 +--
3 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 31c5474f85d6..cfaadeaf9f00 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6299,30 +6299,20 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->dev);
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
- intel_wakeref_t wakeref;
if (!HAS_DDI(dev_priv))
intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
intel_dp->reset_link_params = true;
- if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
- !intel_dp_is_edp(intel_dp))
- return;
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ intel_wakeref_t wakeref;
- with_intel_pps_lock(intel_dp, wakeref) {
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ with_intel_pps_lock(intel_dp, wakeref)
intel_dp->active_pipe = vlv_active_pipe(intel_dp);
-
- if (intel_dp_is_edp(intel_dp)) {
- /*
-* Reinit the power sequencer, in case BIOS did
-* something nasty with it.
-*/
- intel_dp_pps_init(intel_dp);
- intel_pps_vdd_sanitize(intel_dp);
- }
}
+
+ intel_pps_encoder_reset(intel_dp);
}
static int intel_modeset_tile_group(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 799190fafa4f..3b962be4f4c0 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1040,7 +1040,7 @@ void vlv_init_panel_power_sequencer(struct intel_encoder
*encoder,
intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
}
-void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
+static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -1337,7 +1337,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
intel_dp *intel_dp,
(intel_de_read(dev_priv, regs.pp_ctrl) &
BXT_POWER_CYCLE_DELAY_MASK));
}
-void intel_dp_pps_init(struct intel_dp *intel_dp)
+static void intel_dp_pps_init(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1349,6 +1349,23 @@ void intel_dp_pps_init(struct intel_dp *intel_dp)
}
}
+void intel_pps_encoder_reset(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ with_intel_pps_lock(intel_dp, wakeref) {
+ /*
+* Reinit the power sequencer, in case BIOS did something nasty
+* with it.
+*/
+ intel_dp_pps_init(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
+ }
+}
+
void intel_pps_init(struct intel_dp *intel_dp)
{
intel_wakeref_t wakeref;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index 53c0fafd1440..7c3b5ea4f47b 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -32,7 +32,6 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp,
bool sync);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
-void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
void intel_pps_on(struct intel_dp *intel_dp);
void intel_pps_off(struct intel_dp *intel_dp);
@@ -42,7 +41,7 @@ bool intel_pps_have_power(struct intel_dp *intel_dp);
void wait_panel_power_cycle(struct intel_dp *intel_dp);
void intel_pps_init(struct intel_dp *intel_dp);
-void intel_dp_pps_init(struct intel_dp *intel_dp);
+void intel_pps_encoder_reset(struct intel_dp *intel_dp);
void intel_power_sequencer_reset(struct drm_i915_private *i915);
void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
--
2.20.1
[Intel-gfx] [PATCH v2 07/17] drm/i915/pps: add higher level intel_pps_init() call
Add a new init call to be called only once, unlike some of the other
various init calls. This lets us hide more functions within
intel_pps.c. No functional changes.
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 +
drivers/gpu/drm/i915/display/intel_pps.c | 17 +++--
drivers/gpu/drm/i915/display/intel_pps.h | 3 +--
3 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index bff5e735a92e..31c5474f85d6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7026,14 +7026,11 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
enum pipe pipe = INVALID_PIPE;
- intel_wakeref_t wakeref;
struct edid *edid;
if (!intel_dp_is_edp(intel_dp))
return true;
- INIT_DELAYED_WORK(_dp->panel_vdd_work, edp_panel_vdd_work);
-
/*
* On IBX/CPT we may get here with LVDS already registered. Since the
* driver uses the only internal power sequencer available for both
@@ -7049,11 +7046,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
return false;
}
- with_intel_pps_lock(intel_dp, wakeref) {
- intel_dp_init_panel_power_timestamps(intel_dp);
- intel_dp_pps_init(intel_dp);
- intel_pps_vdd_sanitize(intel_dp);
- }
+ intel_pps_init(intel_dp);
/* Cache DPCD and EDID for edp. */
has_dpcd = intel_edp_init_dpcd(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index b6c07694ae9d..799190fafa4f 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -694,7 +694,7 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
intel_pps_vdd_off_sync_unlocked(intel_dp);
}
-void edp_panel_vdd_work(struct work_struct *__work)
+static void edp_panel_vdd_work(struct work_struct *__work)
{
struct intel_dp *intel_dp =
container_of(to_delayed_work(__work),
@@ -1078,7 +1078,7 @@ bool intel_pps_have_power(struct intel_dp *intel_dp)
return have_power;
}
-void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
+static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
{
intel_dp->panel_power_off_time = ktime_get_boottime();
intel_dp->last_power_on = jiffies;
@@ -1348,3 +1348,16 @@ void intel_dp_pps_init(struct intel_dp *intel_dp)
intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
}
}
+
+void intel_pps_init(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ INIT_DELAYED_WORK(_dp->panel_vdd_work, edp_panel_vdd_work);
+
+ with_intel_pps_lock(intel_dp, wakeref) {
+ intel_dp_init_panel_power_timestamps(intel_dp);
+ intel_dp_pps_init(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index 3cab183658c6..53c0fafd1440 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -31,7 +31,6 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
-void edp_panel_vdd_work(struct work_struct *__work);
void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
@@ -42,9 +41,9 @@ bool intel_pps_have_power(struct intel_dp *intel_dp);
void wait_panel_power_cycle(struct intel_dp *intel_dp);
+void intel_pps_init(struct intel_dp *intel_dp);
void intel_dp_pps_init(struct intel_dp *intel_dp);
void intel_power_sequencer_reset(struct drm_i915_private *i915);
-void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp);
void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 06/17] drm/i915/pps: abstract intel_pps_vdd_off_sync
Add a locked version of intel_pps_vdd_off_sync_unlocked() that does
everything the callers expect it to. No functional changes.
v2: Fix typo (Anshuman)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 31 +++-
drivers/gpu/drm/i915/display/intel_pps.c | 18 +-
drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
3 files changed, 21 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1384f1d3a9cf..bff5e735a92e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6249,17 +6249,8 @@ void intel_dp_encoder_flush_work(struct drm_encoder
*encoder)
struct intel_dp *intel_dp = _port->dp;
intel_dp_mst_encoder_cleanup(dig_port);
- if (intel_dp_is_edp(intel_dp)) {
- intel_wakeref_t wakeref;
- cancel_delayed_work_sync(_dp->panel_vdd_work);
- /*
-* vdd might still be enabled do to the delayed vdd off.
-* Make sure vdd is actually turned off here.
-*/
- with_intel_pps_lock(intel_dp, wakeref)
- intel_pps_vdd_off_sync_unlocked(intel_dp);
- }
+ intel_pps_vdd_off_sync(intel_dp);
intel_dp_aux_fini(intel_dp);
}
@@ -6275,18 +6266,8 @@ static void intel_dp_encoder_destroy(struct drm_encoder
*encoder)
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
- intel_wakeref_t wakeref;
-
- if (!intel_dp_is_edp(intel_dp))
- return;
- /*
-* vdd might still be enabled do to the delayed vdd off.
-* Make sure vdd is actually turned off here.
-*/
- cancel_delayed_work_sync(_dp->panel_vdd_work);
- with_intel_pps_lock(intel_dp, wakeref)
- intel_pps_vdd_off_sync_unlocked(intel_dp);
+ intel_pps_vdd_off_sync(intel_dp);
}
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
@@ -7140,13 +7121,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
return true;
out_vdd_off:
- cancel_delayed_work_sync(_dp->panel_vdd_work);
- /*
-* vdd might still be enabled do to the delayed vdd off.
-* Make sure vdd is actually turned off here.
-*/
- with_intel_pps_lock(intel_dp, wakeref)
- intel_pps_vdd_off_sync_unlocked(intel_dp);
+ intel_pps_vdd_off_sync(intel_dp);
return false;
}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index fd3677948800..b6c07694ae9d 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -637,7 +637,7 @@ void intel_pps_vdd_on(struct intel_dp *intel_dp)
dp_to_dig_port(intel_dp)->base.base.name);
}
-void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
+static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port =
@@ -678,6 +678,22 @@ void intel_pps_vdd_off_sync_unlocked(struct intel_dp
*intel_dp)
fetch_and_zero(_dp->vdd_wakeref));
}
+void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ cancel_delayed_work_sync(_dp->panel_vdd_work);
+ /*
+* vdd might still be enabled due to the delayed vdd off.
+* Make sure vdd is actually turned off here.
+*/
+ with_intel_pps_lock(intel_dp, wakeref)
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
+}
+
void edp_panel_vdd_work(struct work_struct *__work)
{
struct intel_dp *intel_dp =
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index e7f0473be9a7..3cab183658c6 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -29,7 +29,6 @@ void intel_pps_backlight_power(struct intel_connector
*connector, bool enable);
bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
-void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
void edp_panel_vdd_work(struct work_struct *__work);
@@ -38,6 +37,7 @@ void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
void intel_pps_on(struct intel_dp *intel_dp);
void intel_pps_off(struct intel_dp *intel_dp);
+void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
bool intel_pps_have_power(struct intel_dp *intel_dp);
void
[Intel-gfx] [PATCH v2 05/17] drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked
Follow the usual naming pattern for functions, both for the prefix and
the _unlocked suffix for functions that expect the lock to be held when
calling. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 +++
drivers/gpu/drm/i915/display/intel_pps.c | 26
drivers/gpu/drm/i915/display/intel_pps.h | 10 -
3 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index eac674ad91c8..1384f1d3a9cf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1061,7 +1061,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* to turn it off. But for eg. i2c-dev access we need to turn it on/off
* ourselves.
*/
- vdd = edp_panel_vdd_on(intel_dp);
+ vdd = intel_pps_vdd_on_unlocked(intel_dp);
/* dp aux is extremely sensitive to irq latency, hence request the
* lowest possible wakeup latency and so prevent the cpu from going into
@@ -1203,7 +1203,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
cpu_latency_qos_update_request(_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
if (vdd)
- edp_panel_vdd_off(intel_dp, false);
+ intel_pps_vdd_off_unlocked(intel_dp, false);
intel_pps_unlock(intel_dp, pps_wakeref);
intel_display_power_put_async(i915, aux_domain, aux_wakeref);
@@ -3520,9 +3520,9 @@ static void intel_enable_dp(struct intel_atomic_state
*state,
intel_dp_enable_port(intel_dp, pipe_config);
- edp_panel_vdd_on(intel_dp);
- edp_panel_on(intel_dp);
- edp_panel_vdd_off(intel_dp, true);
+ intel_pps_vdd_on_unlocked(intel_dp);
+ intel_pps_on_unlocked(intel_dp);
+ intel_pps_vdd_off_unlocked(intel_dp, true);
}
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
@@ -6258,7 +6258,7 @@ void intel_dp_encoder_flush_work(struct drm_encoder
*encoder)
* Make sure vdd is actually turned off here.
*/
with_intel_pps_lock(intel_dp, wakeref)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
}
intel_dp_aux_fini(intel_dp);
@@ -6286,7 +6286,7 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
*/
cancel_delayed_work_sync(_dp->panel_vdd_work);
with_intel_pps_lock(intel_dp, wakeref)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
}
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
@@ -7146,7 +7146,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
* Make sure vdd is actually turned off here.
*/
with_intel_pps_lock(intel_dp, wakeref)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
return false;
}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 59215cfd7d97..fd3677948800 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -556,11 +556,11 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
}
/*
- * Must be paired with edp_panel_vdd_off().
+ * Must be paired with intel_pps_vdd_off_unlocked().
* Must hold pps_mutex around the whole on/off sequence.
* Can be nested with intel_pps_vdd_{on,off}() calls.
*/
-bool edp_panel_vdd_on(struct intel_dp *intel_dp)
+bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -631,13 +631,13 @@ void intel_pps_vdd_on(struct intel_dp *intel_dp)
vdd = false;
with_intel_pps_lock(intel_dp, wakeref)
- vdd = edp_panel_vdd_on(intel_dp);
+ vdd = intel_pps_vdd_on_unlocked(intel_dp);
I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
dp_to_dig_port(intel_dp)->base.base.base.id,
dp_to_dig_port(intel_dp)->base.base.name);
}
-void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
+void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port =
@@ -687,7 +687,7 @@ void edp_panel_vdd_work(struct work_struct *__work)
with_intel_pps_lock(intel_dp, wakeref) {
if (!intel_dp->want_panel_vdd)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
}
}
@@ -709,7 +709,7 @@ static void
[Intel-gfx] [PATCH v2 04/17] drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
Follow the usual naming pattern for functions. We don't need to repeat
"panel" here. No functional changes.
v2: Fix comment (Anshuman)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8
drivers/gpu/drm/i915/display/intel_dp.c | 10 +-
drivers/gpu/drm/i915/display/intel_pps.c | 17 -
drivers/gpu/drm/i915/display/intel_pps.h | 11 +--
4 files changed, 22 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index f09a597bf730..243ab635aa34 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3592,7 +3592,7 @@ static void tgl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
*/
/* 2. Enable Panel Power if PPS is required */
- intel_edp_panel_on(intel_dp);
+ intel_pps_on(intel_dp);
/*
* 3. For non-TBT Type-C ports, set FIA lane count
@@ -3735,7 +3735,7 @@ static void hsw_ddi_pre_enable_dp(struct
intel_atomic_state *state,
crtc_state->port_clock,
crtc_state->lane_count);
- intel_edp_panel_on(intel_dp);
+ intel_pps_on(intel_dp);
intel_ddi_clk_select(encoder, crtc_state);
@@ -3977,8 +3977,8 @@ static void intel_ddi_post_disable_dp(struct
intel_atomic_state *state,
if (INTEL_GEN(dev_priv) >= 12)
intel_ddi_disable_pipe_clock(old_crtc_state);
- intel_edp_panel_vdd_on(intel_dp);
- intel_edp_panel_off(intel_dp);
+ intel_pps_vdd_on(intel_dp);
+ intel_pps_off(intel_dp);
if (!intel_phy_is_tc(dev_priv, phy) ||
dig_port->tc_mode != TC_PORT_TBT_ALT)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 421e68bb436f..eac674ad91c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3001,10 +3001,10 @@ static void intel_disable_dp(struct intel_atomic_state
*state,
/* Make sure the panel is off before trying to change the mode. But also
* ensure that we have vdd while we switch off the panel. */
- intel_edp_panel_vdd_on(intel_dp);
+ intel_pps_vdd_on(intel_dp);
intel_edp_backlight_off(old_conn_state);
intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
- intel_edp_panel_off(intel_dp);
+ intel_pps_off(intel_dp);
intel_dp->frl.is_trained = false;
intel_dp->frl.trained_rate_gbps = 0;
}
@@ -6339,7 +6339,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
* something nasty with it.
*/
intel_dp_pps_init(intel_dp);
- intel_edp_panel_vdd_sanitize(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
}
}
}
@@ -6513,7 +6513,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
bool long_hpd)
struct intel_dp *intel_dp = _port->dp;
if (dig_port->base.type == INTEL_OUTPUT_EDP &&
- (long_hpd || !intel_edp_have_power(intel_dp))) {
+ (long_hpd || !intel_pps_have_power(intel_dp))) {
/*
* vdd off can generate a long/short pulse on eDP which
* would require vdd on to handle it, and thus we
@@ -7071,7 +7071,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
with_intel_pps_lock(intel_dp, wakeref) {
intel_dp_init_panel_power_timestamps(intel_dp);
intel_dp_pps_init(intel_dp);
- intel_edp_panel_vdd_sanitize(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
}
/* Cache DPCD and EDID for edp. */
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 36d8782d8df1..59215cfd7d97 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -558,7 +558,7 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
/*
* Must be paired with edp_panel_vdd_off().
* Must hold pps_mutex around the whole on/off sequence.
- * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
+ * Can be nested with intel_pps_vdd_{on,off}() calls.
*/
bool edp_panel_vdd_on(struct intel_dp *intel_dp)
{
@@ -616,13 +616,12 @@ bool edp_panel_vdd_on(struct intel_dp *intel_dp)
}
/*
- * Must be paired with intel_edp_panel_vdd_off() or
- * intel_edp_panel_off().
+ * Must be paired with intel_pps_off().
* Nested calls to these functions are not allowed since
* we drop the lock. Caller must use some higher level
* locking to prevent nested calls from other threads.
*/
-void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
+void intel_pps_vdd_on(struct intel_dp *intel_dp)
{
intel_wakeref_t wakeref;
bool vdd;
@@ -708,7 +707,7 @@ static void
Re: [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power sequencer from intel_dp.c
On Mon, 04 Jan 2021, Jani Nikula wrote: > On Mon, 28 Dec 2020, "Gupta, Anshuman" wrote: >>> -Original Message- >>> From: Intel-gfx On Behalf Of Jani >>> Nikula >>> Sent: Tuesday, December 22, 2020 8:20 PM >>> To: intel-gfx@lists.freedesktop.org >>> Cc: Nikula, Jani >>> Subject: [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power >>> sequencer from intel_dp.c >>> >>> In a long overdue refactoring, split out all panel sequencer code from >>> intel_dp.c to new intel_pps.[ch]. >>> >>> The first part is mostly just code movement as-is, without cleanups. >>> >>> We need to add a vlv_get_dpll() helper to get at the vlv/chv dpll from >>> pps code. >> IMHO functions intel_dp_init_panel_power_sequencer, >> intel_dp_init_panel_power_sequencer_registers, >> intel_dp_pps_init suits a intel_edp_* prefix. > > This patch just moves code. The rename would be a separate change on > top. Possibly with intel_pps prefix instead because they're not so much > about dp or edp as about pps. I've added some additional renames in v2. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 03/17] drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_*
Follow the usual naming pattern for functions. No functional changes.
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
drivers/gpu/drm/i915/display/intel_pps.c | 10 +-
drivers/gpu/drm/i915/display/intel_pps.h | 6 +++---
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6e9b114171be..421e68bb436f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2563,7 +2563,7 @@ void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state,
drm_dbg_kms(>drm, "\n");
intel_panel_enable_backlight(crtc_state, conn_state);
- _intel_edp_backlight_on(intel_dp);
+ intel_pps_backlight_on(intel_dp);
}
/* Disable backlight PP control and backlight PWM. */
@@ -2577,7 +2577,7 @@ void intel_edp_backlight_off(const struct
drm_connector_state *old_conn_state)
drm_dbg_kms(>drm, "\n");
- _intel_edp_backlight_off(intel_dp);
+ intel_pps_backlight_off(intel_dp);
intel_panel_disable_backlight(old_conn_state);
}
@@ -7128,7 +7128,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
}
intel_panel_init(_connector->panel, fixed_mode, downclock_mode);
- intel_connector->panel.backlight.power = intel_edp_backlight_power;
+ intel_connector->panel.backlight.power = intel_pps_backlight_power;
intel_panel_setup_backlight(connector, pipe);
if (fixed_mode) {
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 1a05f2c7f690..36d8782d8df1 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -844,7 +844,7 @@ void intel_edp_panel_off(struct intel_dp *intel_dp)
}
/* Enable backlight in the panel power control. */
-void _intel_edp_backlight_on(struct intel_dp *intel_dp)
+void intel_pps_backlight_on(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_wakeref_t wakeref;
@@ -870,7 +870,7 @@ void _intel_edp_backlight_on(struct intel_dp *intel_dp)
}
/* Disable backlight in the panel power control. */
-void _intel_edp_backlight_off(struct intel_dp *intel_dp)
+void intel_pps_backlight_off(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_wakeref_t wakeref;
@@ -897,7 +897,7 @@ void _intel_edp_backlight_off(struct intel_dp *intel_dp)
* Hook for controlling the panel power control backlight through the bl_power
* sysfs attribute. Take care to handle multiple calls.
*/
-void intel_edp_backlight_power(struct intel_connector *connector, bool enable)
+void intel_pps_backlight_power(struct intel_connector *connector, bool enable)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -914,9 +914,9 @@ void intel_edp_backlight_power(struct intel_connector
*connector, bool enable)
enable ? "enable" : "disable");
if (enable)
- _intel_edp_backlight_on(intel_dp);
+ intel_pps_backlight_on(intel_dp);
else
- _intel_edp_backlight_off(intel_dp);
+ intel_pps_backlight_off(intel_dp);
}
static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index f44e6ce9e8c1..81e4e9fc3cf5 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -23,9 +23,9 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
intel_wakeref_t wake
for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp),
(wf)))
void intel_dp_check_edp(struct intel_dp *intel_dp);
-void _intel_edp_backlight_on(struct intel_dp *intel_dp);
-void _intel_edp_backlight_off(struct intel_dp *intel_dp);
-void intel_edp_backlight_power(struct intel_connector *connector, bool enable);
+void intel_pps_backlight_on(struct intel_dp *intel_dp);
+void intel_pps_backlight_off(struct intel_dp *intel_dp);
+void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
bool edp_panel_vdd_on(struct intel_dp *intel_dp);
void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 02/17] drm/i915/pps: rename pps_{, un}lock -> intel_pps_{, un}lock
Start following the usual naming pattern for functions. No functional
changes.
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++--
drivers/gpu/drm/i915/display/intel_pps.c | 21 +++--
drivers/gpu/drm/i915/display/intel_pps.h | 8
3 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 07279b10812e..6e9b114171be 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1053,7 +1053,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
aux_domain = intel_aux_power_domain(dig_port);
aux_wakeref = intel_display_power_get(i915, aux_domain);
- pps_wakeref = pps_lock(intel_dp);
+ pps_wakeref = intel_pps_lock(intel_dp);
/*
* We will be called with VDD already enabled for dpcd/edid/oui reads.
@@ -1205,7 +1205,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
if (vdd)
edp_panel_vdd_off(intel_dp, false);
- pps_unlock(intel_dp, pps_wakeref);
+ intel_pps_unlock(intel_dp, pps_wakeref);
intel_display_power_put_async(i915, aux_domain, aux_wakeref);
if (is_tc_port)
@@ -3514,7 +3514,7 @@ static void intel_enable_dp(struct intel_atomic_state
*state,
if (drm_WARN_ON(_priv->drm, dp_reg & DP_PORT_EN))
return;
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_init_panel_power_sequencer(encoder, pipe_config);
@@ -4082,7 +4082,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
intel_wakeref_t wakeref;
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
intel_dp->active_pipe = INVALID_PIPE;
}
}
@@ -6257,7 +6257,7 @@ void intel_dp_encoder_flush_work(struct drm_encoder
*encoder)
* vdd might still be enabled do to the delayed vdd off.
* Make sure vdd is actually turned off here.
*/
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
edp_panel_vdd_off_sync(intel_dp);
}
@@ -6285,7 +6285,7 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
* Make sure vdd is actually turned off here.
*/
cancel_delayed_work_sync(_dp->panel_vdd_work);
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
edp_panel_vdd_off_sync(intel_dp);
}
@@ -6297,7 +6297,7 @@ void intel_dp_encoder_shutdown(struct intel_encoder
*intel_encoder)
if (!intel_dp_is_edp(intel_dp))
return;
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
wait_panel_power_cycle(intel_dp);
}
@@ -6329,7 +6329,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
!intel_dp_is_edp(intel_dp))
return;
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
intel_dp->active_pipe = vlv_active_pipe(intel_dp);
@@ -7068,7 +7068,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
return false;
}
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
intel_dp_init_panel_power_timestamps(intel_dp);
intel_dp_pps_init(intel_dp);
intel_edp_panel_vdd_sanitize(intel_dp);
@@ -7145,7 +7145,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
* vdd might still be enabled do to the delayed vdd off.
* Make sure vdd is actually turned off here.
*/
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
edp_panel_vdd_off_sync(intel_dp);
return false;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 83bd83b3e3c4..1a05f2c7f690 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -16,7 +16,7 @@ static void
intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
bool force_disable_vdd);
-intel_wakeref_t pps_lock(struct intel_dp *intel_dp)
+intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_wakeref_t wakeref;
@@ -31,7 +31,8 @@ intel_wakeref_t pps_lock(struct intel_dp *intel_dp)
[Intel-gfx] [PATCH v2 01/17] drm/i915/pps: abstract panel power sequencer from intel_dp.c
In a long overdue refactoring, split out all panel sequencer code from
intel_dp.c to new intel_pps.[ch].
The first part is mostly just code movement as-is, without cleanups or
functional changes.
We need to add a vlv_get_dpll() helper to get at the vlv/chv dpll from
pps code.
v2: Rebase.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display/intel_ddi.c |1 +
.../drm/i915/display/intel_display_power.c|2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 1436 +
drivers/gpu/drm/i915/display/intel_dp.h |5 +-
drivers/gpu/drm/i915/display/intel_pps.c | 1334 +++
drivers/gpu/drm/i915/display/intel_pps.h | 53 +
7 files changed, 1443 insertions(+), 1389 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.c
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4074d8cb0d6e..8a04403a11bb 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -251,6 +251,7 @@ i915-y += \
display/intel_lspcon.o \
display/intel_lvds.o \
display/intel_panel.o \
+ display/intel_pps.o \
display/intel_sdvo.o \
display/intel_tv.o \
display/intel_vdsc.o \
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3df6913369bc..f09a597bf730 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -46,6 +46,7 @@
#include "intel_hotplug.h"
#include "intel_lspcon.h"
#include "intel_panel.h"
+#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_sprite.h"
#include "intel_tc.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index d52374f01316..a11bd8213df4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4,7 +4,6 @@
*/
#include "display/intel_crt.h"
-#include "display/intel_dp.h"
#include "i915_drv.h"
#include "i915_irq.h"
@@ -16,6 +15,7 @@
#include "intel_dpio_phy.h"
#include "intel_hotplug.h"
#include "intel_pm.h"
+#include "intel_pps.h"
#include "intel_sideband.h"
#include "intel_tc.h"
#include "intel_vga.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4f190a82d4ad..07279b10812e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -58,6 +58,7 @@
#include "intel_lspcon.h"
#include "intel_lvds.h"
#include "intel_panel.h"
+#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_sideband.h"
#include "intel_tc.h"
@@ -121,6 +122,11 @@ static const struct dp_link_dpll chv_dpll[] = {
{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c0 } },
};
+const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
+{
+ return IS_CHERRYVIEW(i915) ? _dpll[0].dpll : _dpll[0].dpll;
+}
+
/* Constants for DP DSC configurations */
static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
@@ -145,12 +151,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_link_down(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state);
-static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
-static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
-static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
- const struct intel_crtc_state
*crtc_state);
-static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
- enum pipe pipe);
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
/* update sink rates from dpcd */
@@ -877,447 +877,6 @@ static void intel_dp_unpack_aux(u32 src, u8 *dst, int
dst_bytes)
dst[i] = src >> ((3-i) * 8);
}
-static void
-intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
-static void
-intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
- bool force_disable_vdd);
-static void
-intel_dp_pps_init(struct intel_dp *intel_dp);
-
-static intel_wakeref_t
-pps_lock(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- intel_wakeref_t wakeref;
-
- /*
-* See intel_power_sequencer_reset() why we need
-* a power domain reference here.
-*/
- wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
- mutex_lock(_priv->pps_mutex);
-
- return wakeref;
-}
-
-static intel_wakeref_t
-pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
-
[Intel-gfx] [PATCH v2 00/17] drm/i915/dp: split out pps and aux
This is v2 of [1], with comments from Anshuman addressed, and a few additional
patches at the end.
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/85167/
Jani Nikula (17):
drm/i915/pps: abstract panel power sequencer from intel_dp.c
drm/i915/pps: rename pps_{,un}lock -> intel_pps_{,un}lock
drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_*
drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked
drm/i915/pps: abstract intel_pps_vdd_off_sync
drm/i915/pps: add higher level intel_pps_init() call
drm/i915/pps: abstract intel_pps_encoder_reset()
drm/i915/pps: rename intel_dp_check_edp to
intel_pps_check_power_unlocked
drm/i915/pps: rename intel_power_sequencer_reset to
intel_pps_reset_all
drm/i915/pps: add locked intel_pps_wait_power_cycle
drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init
drm/i915/pps: rename intel_dp_init_panel_power_sequencer* functions
drm/i915/pps: refactor init abstractions
drm/i915/pps: move pps code over from intel_display.c and refactor
drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
drm/i915/dp: split out aux functionality to intel_dp_aux.c
drivers/gpu/drm/i915/Makefile |2 +
drivers/gpu/drm/i915/display/intel_ddi.c |9 +-
drivers/gpu/drm/i915/display/intel_display.c | 41 +-
drivers/gpu/drm/i915/display/intel_display.h |1 -
.../drm/i915/display/intel_display_debugfs.c |8 +-
.../drm/i915/display/intel_display_power.c|6 +-
.../drm/i915/display/intel_display_types.h| 61 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2249 +
drivers/gpu/drm/i915/display/intel_dp.h |5 +-
drivers/gpu/drm/i915/display/intel_dp_aux.c | 687 +
drivers/gpu/drm/i915/display/intel_dp_aux.h | 18 +
drivers/gpu/drm/i915/display/intel_pps.c | 1406 +++
drivers/gpu/drm/i915/display/intel_pps.h | 52 +
drivers/gpu/drm/i915/i915_drv.c |1 +
14 files changed, 2312 insertions(+), 2234 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.h
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.c
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.h
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix HTI port checking
== Series Details == Series: drm/i915: Fix HTI port checking URL : https://patchwork.freedesktop.org/series/85615/ State : success == Summary == CI Bug Log - changes from CI_DRM_9566 -> Patchwork_19292 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/index.html Known issues Here are the changes found in Patchwork_19292 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap_gtt@basic: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/fi-tgl-y/igt@gem_mmap_...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/fi-tgl-y/igt@gem_mmap_...@basic.html Possible fixes * igt@gem_flink_basic@bad-flink: - fi-tgl-y: [DMESG-WARN][3] ([i915#402]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 38) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9566 -> Patchwork_19292 CI-20190529: 20190529 CI_DRM_9566: 43ca049026a4c8808645c7f21cb0fc34a337c612 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5951: fec3b9c7d88357144f0d7a1447b9316a1c81da1a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19292: d7e254bf929b82d237306e002cd63494946218e9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d7e254bf929b drm/i915: Fix HTI port checking == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19292/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915/selftests: Skip unstable timing measurements
Hi Chris,
> diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> index 75839db63bea..59c58a276677 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> @@ -852,6 +852,9 @@ static int _perf_memcpy(struct intel_memory_region
> *src_mr,
> }
>
> sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
> + if (!t[0])
> + continue;
> +
are you assuming here that if t[0] is '0', also the rest of 't'
is '0'?
Andi
> pr_info("%s src(%s, %s) -> dst(%s, %s) %14s %4llu KiB copy:
> %5lld MiB/s\n",
> __func__,
> src_mr->name,
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/pps: Reuse POWER_DOMAIN_DISPLAY_CORE in pps_{lock, unlock}
On Fri, 08 Jan 2021, Imre Deak wrote:
> On Fri, Jan 08, 2021 at 11:38:04AM +0200, Jani Nikula wrote:
>> On Thu, 07 Jan 2021, Anshuman Gupta wrote:
>> > We need a power_domain wakeref in pps_{lock,unlock} to prevent
>> > a race while resetting pps state in intel_power_sequencer_reset().
>> >
>> > intel_power_sequencer_reset() need a pps_mutex to access pps_pipe
>> > but it can't grab pps_mutex due to deadlock with power_well
>> > functions are called while holding pps_mutex.
>> > intel_power_sequencer_reset() is called by power_well function
>> > associated with legacy platforms like vlv and chv therefore re-use
>> > the POWER_DOMAIN_DISPLAY_CORE power domain, which only used
>> > by vlv and chv display power domain.
>> >
>> > This will avoids the unnecessary noise of unrelated power wells
>> > in pps_{lock,unlock}.
>> >
>> > Cc: Jani Nikula
>> > Cc: Imre Deak
>> > Signed-off-by: Anshuman Gupta
>>
>> Imre convinced me yesterday on irc that this should work.
>>
>> Reviewed-by: Jani Nikula
>>
>> On the surface, this reduces the need to enable/disable the aux power so
>> much. It's unnecessary, so it stands to reason to optimize it. We should
>> only grab the domain references we actually need.
>>
>> However, this *also* papers over an issue we've been seeing [1]. We need
>> to be aware the root cause for that remains unknown, and needs to be
>> figured out.
>>
>> I presume simply doing aux transfers won't reproduce the problem,
>> because that disables the power asynchronously since commit f39194a7a8b9
>> ("drm/i915: Disable power asynchronously during DP AUX
>> transfers"). Perhaps we wouldn't have seen this at all if pps_unlock()
>> also did that as suggested in the commit message.
>>
>> Anyway, I'd like to get acks or rb's from Imre and Ville before merging
>> this.
>
> Looks ok to me:
> Acked-by: Imre Deak
Thanks, pushed to din.
BR,
Jani.
>
>>
>>
>> BR,
>> Jani.
>>
>>
>> [1] http://lore.kernel.org/r/20201204081845.26528-1-anshuman.gu...@intel.com
>>
>>
>> > ---
>> > drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
>> > 1 file changed, 2 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> > b/drivers/gpu/drm/i915/display/intel_dp.c
>> > index 8a00e609085f..4f190a82d4ad 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> > @@ -895,9 +895,7 @@ pps_lock(struct intel_dp *intel_dp)
>> > * See intel_power_sequencer_reset() why we need
>> > * a power domain reference here.
>> > */
>> > - wakeref = intel_display_power_get(dev_priv,
>> > -
>> > intel_aux_power_domain(dp_to_dig_port(intel_dp)));
>> > -
>> > + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
>> >mutex_lock(_priv->pps_mutex);
>> >
>> >return wakeref;
>> > @@ -909,9 +907,7 @@ pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t
>> > wakeref)
>> >struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> >
>> >mutex_unlock(_priv->pps_mutex);
>> > - intel_display_power_put(dev_priv,
>> > -
>> > intel_aux_power_domain(dp_to_dig_port(intel_dp)),
>> > - wakeref);
>> > + intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
>> >return 0;
>> > }
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9_bc : Add TGP PCH support (rev2)
== Series Details ==
Series: drm/i915/gen9_bc : Add TGP PCH support (rev2)
URL : https://patchwork.freedesktop.org/series/85502/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9566 -> Patchwork_19291
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/index.html
Known issues
Here are the changes found in Patchwork_19291 that come from known issues:
### IGT changes ###
Issues hit
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar
issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
Possible fixes
* igt@gem_flink_basic@bad-flink:
- fi-tgl-y: [DMESG-WARN][3] ([i915#402]) -> [PASS][4] +1 similar
issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 37)
--
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan
fi-ctg-p8600 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9566 -> Patchwork_19291
CI-20190529: 20190529
CI_DRM_9566: 43ca049026a4c8808645c7f21cb0fc34a337c612 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5951: fec3b9c7d88357144f0d7a1447b9316a1c81da1a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19291: 4167cb3a91fe63a8b79e9ad0b5b7adb9f33a0e26 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4167cb3a91fe drm/i915/gen9_bc : Add TGP PCH support
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Rearrange ktime_get to reduce latency against CS
== Series Details ==
Series: drm/i915/selftests: Rearrange ktime_get to reduce latency against CS
URL : https://patchwork.freedesktop.org/series/85611/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9565_full -> Patchwork_19290_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19290_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19290_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19290_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_whisper@basic-contexts-priority-all:
- shard-iclb: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9565/shard-iclb7/igt@gem_exec_whis...@basic-contexts-priority-all.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19290/shard-iclb6/igt@gem_exec_whis...@basic-contexts-priority-all.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_fair@basic-pace-solo@rcs0}:
- shard-tglb: [FAIL][3] ([i915#2842]) -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9565/shard-tglb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19290/shard-tglb1/igt@gem_exec_fair@basic-pace-s...@rcs0.html
Known issues
Here are the changes found in Patchwork_19290_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@legacy-engines-hang:
- shard-hsw: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19290/shard-hsw8/igt@gem_ctx_persiste...@legacy-engines-hang.html
* igt@gem_userptr_blits@process-exit-mmap@wb:
- shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1699]) +3
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19290/shard-skl9/igt@gem_userptr_blits@process-exit-m...@wb.html
* igt@gem_userptr_blits@readonly-mmap-unsync@wb:
- shard-tglb: NOTRUN -> [SKIP][7] ([i915#1704]) +3 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19290/shard-tglb2/igt@gem_userptr_blits@readonly-mmap-uns...@wb.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][8] -> [DMESG-WARN][9] ([i915#1436] /
[i915#1982] / [i915#716])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9565/shard-skl7/igt@gen9_exec_pa...@allowed-single.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19290/shard-skl8/igt@gen9_exec_pa...@allowed-single.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-skl: [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +1
similar issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9565/shard-skl7/igt@i915_module_l...@reload-with-fault-injection.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19290/shard-skl8/igt@i915_module_l...@reload-with-fault-injection.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][12] ([i915#454])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19290/shard-skl9/igt@i915_pm...@dc6-dpms.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-hsw: NOTRUN -> [SKIP][13] ([fdo#109271]) +155 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19290/shard-hsw8/igt@i915_pm_...@gem-execbuf-stress-pc8.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-tglb: NOTRUN -> [SKIP][14] ([fdo#111644] / [i915#1397] /
[i915#2411])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19290/shard-tglb2/igt@i915_pm_...@modeset-non-lpsp-stress.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][15] ([fdo#111614])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19290/shard-tglb2/igt@kms_big...@x-tiled-16bpp-rotate-270.html
* igt@kms_chamelium@dp-crc-fast:
- shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +3
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19290/shard-apl2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@hdmi-crc-nonplanar-formats:
- shard-hsw: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827])
+10 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19290/shard-hsw5/igt@kms_chamel...@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium@vga-hpd-with-enabled-mode:
- shard-tglb: NOTRUN -> [SKIP][18]
[Intel-gfx] [PATCH] drm/i915/backlight: fix CPU mode backlight takeover on LPT
The pch_get_backlight(), lpt_get_backlight(), and lpt_set_backlight()
functions operate directly on the hardware registers. If inverting the
value is needed, using intel_panel_compute_brightness(), it should only
be done in the interface between hardware registers and
panel->backlight.level.
The CPU mode takeover code added in commit 5b1ec9ac7ab5
("drm/i915/backlight: Fix backlight takeover on LPT, v3.") reads the
hardware register and converts to panel->backlight.level correctly,
however the value written back should remain in the hardware register
"domain".
This hasn't been an issue, because GM45 machines are the only known
users of i915.invert_brightness and the brightness invert quirk, and
without one of them no conversion is made. It's likely nobody's ever hit
the problem.
Fixes: 5b1ec9ac7ab5 ("drm/i915/backlight: Fix backlight takeover on LPT, v3.")
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Lyude Paul
Cc: # v5.1+
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_panel.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gpu/drm/i915/display/intel_panel.c
index 67f81ae995c4..7a4239d1c241 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -1649,16 +1649,13 @@ static int lpt_setup_backlight(struct intel_connector
*connector, enum pipe unus
val = pch_get_backlight(connector);
else
val = lpt_get_backlight(connector);
- val = intel_panel_compute_brightness(connector, val);
- panel->backlight.level = clamp(val, panel->backlight.min,
- panel->backlight.max);
if (cpu_mode) {
drm_dbg_kms(_priv->drm,
"CPU backlight register was enabled, switching to
PCH override\n");
/* Write converted CPU PWM value to PCH override register */
- lpt_set_backlight(connector->base.state,
panel->backlight.level);
+ lpt_set_backlight(connector->base.state, val);
intel_de_write(dev_priv, BLC_PWM_PCH_CTL1,
pch_ctl1 | BLM_PCH_OVERRIDE_ENABLE);
@@ -1666,6 +1663,10 @@ static int lpt_setup_backlight(struct intel_connector
*connector, enum pipe unus
cpu_ctl2 & ~BLM_PWM_ENABLE);
}
+ val = intel_panel_compute_brightness(connector, val);
+ panel->backlight.level = clamp(val, panel->backlight.min,
+ panel->backlight.max);
+
return 0;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/5] drm/i915/gt: Restore ce->signal flush before releasing virtual engine
Quoting Andi Shyti (2021-01-08 15:18:22)
> Hi Chris,
>
> > +void intel_context_remove_breadcrumbs(struct intel_context *ce,
> > + struct intel_breadcrumbs *b)
> > +{
> > + struct i915_request *rq, *rn;
> > + bool release = false;
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(>signal_lock, flags);
> > +
> > + if (list_empty(>signals))
> > + goto unlock;
>
> does "list_empty" need to be under lock or you've been lazy?
This check is required to be under the lock, we have to be careful about
not calling remove_signaling_context() from here and signal_irq_work.
I put the unlocked check in the caller to avoid the function call as well.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
