date:20210114

Re: [Intel-gfx] [BUG] on reboot: bisected to: drm/i915: Shut down displays gracefully on reboot

2021-01-14 Thread Jani Nikula

On Thu, 14 Jan 2021, Steven Rostedt  wrote:
> [ Forgot to add those on the commit itself ]
>
> -- Steve
>
>
> On Thu, 14 Jan 2021 16:32:06 -0500
> Steven Rostedt  wrote:
>
>> On reboot, one of my test boxes now triggers the following warning:
>> 
>>  [ cut here ]
>>  RPM raw-wakeref not held
>>  WARNING: CPU: 4 PID: 1 at drivers/gpu/drm/i915/intel_runtime_pm.h:106 
>> gen6_write32+0x1bc/0x2a0 [i915]
>>  Modules linked in: ebtable_filter ebtables bridge stp llc ip6t_REJECT 
>> nf_reject_ipv6 vsock vmw_vmci xt_state xt_conntrack nf_conntrack 
>> nf_defrag_ipv6 nf_defrag_ipv4 ip6table_filter ip6_tables snd_hda_codec_hdmi 
>> snd_hda_codec_realtek snd_hda_codec_generic le
>> 15 snd_hda_intel snd_intel_dspcfg snd_hda_codec snd_hwdep i2c_algo_bit 
>> snd_hda_core snd_seq intel_rapl_msr snd_seq_device intel_rapl_common snd_pcm 
>> x86_pkg_temp_thermal intel_powerclamp snd_timer snd coretemp kvm_intel 
>> soundcore kvm mei_wdt irqbypass joydev 
>> _pmc_bxt hp_wmi wmi_bmof sparse_keymap rfkill iTCO_vendor_support 
>> crct10dif_pclmul crc32_pclmul crc32c_intel ghash_clmulni_intel 
>> drm_kms_helper i2c_i801 cec drm rapl intel_cstate intel_uncore mei_me 
>> i2c_smbus e1000e tpm_infineon wmi serio_raw mei video lpc_i
>> 
>>  CPU: 4 PID: 1 Comm: systemd-shutdow Not tainted 5.9.0-rc4-test+ #861
>>  Hardware name: Hewlett-Packard HP Compaq Pro 6300 SFF/339A, BIOS K01 v03.03 
>> 07/14/2016
>>  RIP: 0010:gen6_write32+0x1bc/0x2a0 [i915]
>>  Code: 5d 82 e0 0f 0b e9 b5 fe ff ff 80 3d 95 6b 22 00 00 0f 85 b2 fe ff ff 
>> 48 c7 c7 04 d2 a4 c0 c6 05 81 6b 22 00 01 e8 f6 5c 82 e0 <0f> 0b e9 98 fe ff 
>> ff 80 3d 6d 6b 22 00 00 0f 85 95 fe ff ff 48 c7
>>  RSP: 0018:b9c1c002fd08 EFLAGS: 00010296
>>  RAX: 0018 RBX: 99aec8881010 RCX: 99aeda40
>>  RDX:  RSI: a115d9ef RDI: a115d9ef
>>  RBP: 00044004 R08: 0001 R09: 
>>  R10: 0001 R11: 0001 R12: 
>>  R13: 0001 R14:  R15: 
>>  FS:  7f91257a9940() GS:99aeda40() knlGS:
>>  CS:  0010 DS:  ES:  CR0: 80050033
>>  CR2: 7f9126829400 CR3: 0001088f0006 CR4: 001706e0
>>  Call Trace:
>>   gen3_irq_reset+0x2e/0xd0 [i915]
>>   intel_irq_reset+0x59/0x6a0 [i915]
>>   intel_runtime_pm_disable_interrupts+0xe/0x30 [i915]
>>   i915_driver_shutdown+0x2e/0x40 [i915]
>>   pci_device_shutdown+0x34/0x60
>>   device_shutdown+0x15d/0x1b3
>>   kernel_restart+0xe/0x30
>>   __do_sys_reboot+0x1d7/0x210
>>   ? vfs_writev+0x9d/0xe0
>>   ? syscall_enter_from_user_mode+0x1d/0x70
>>   ? trace_hardirqs_on+0x2c/0xe0
>>   do_syscall_64+0x33/0x40
>>   entry_SYSCALL_64_after_hwframe+0x44/0xa9
>>  RIP: 0033:0x7f912675f2d7
>>  Code: 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 
>> 89 fa be 69 19 12 28 bf ad de e1 fe b8 a9 00 00 00 0f 05 <48> 3d 00 f0 ff ff 
>> 77 01 c3 48 8b 15 81 8b 0c 00 f7 d8 64 89 02 b8
>>  RSP: 002b:7ffeca28e148 EFLAGS: 0206 ORIG_RAX: 00a9
>>  RAX: ffda RBX:  RCX: 7f912675f2d7
>>  RDX: 01234567 RSI: 28121969 RDI: fee1dead
>>  RBP: 7ffeca28e3d0 R08: 000a R09: 
>>  R10: 0232 R11: 0206 R12: 0001
>>  R13:  R14:  R15: 7ffeca28e4b8
>>  ---[ end trace 2ed17eabd3ab6938 ]---
>>  [ cut here ]
>> 
>> The bisect came to this commit:
>> 
>>   fe0f1e3bfdfeb53e18f1206aea4f40b9bd1f291c
>>   ("drm/i915: Shut down displays gracefully on reboot")
>> 
>> Which makes sense, as it happens on shutdown.

Please try this pull, heading to -rc4, which cointains "drm/i915:
Disable RPM wakeref assertions during driver shutdown":

http://lore.kernel.org/r/87sg73pz42@intel.com


BR,
Jani.

>> 
>> -- Steve
>

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH] drm/i915/display: Bitwise or the conversion colour specifier together

2021-01-14 Thread Nautiyal, Ankit K




On 1/13/2021 5:22 PM, Jani Nikula wrote:

On Fri, 08 Jan 2021, Jani Nikula  wrote:

On Thu, 24 Dec 2020, "Nautiyal, Ankit K"  wrote:

Thanks Chris to catch this.

This definitely should be bitwise Operator, as mentioned by Jani is
right thing to do.

The PCON which I had access to, had the F/W which was using 303Ch
(previously proposed) for color conversion capability, instead of what
is latest mentioned in the spec ie. 83h.

While testing, I had to skip this line of code, and hardcoded to older
register ie. 303Ch.

I Will get this patch tested and update.

In the mean time, the topic/dp-hdmi-2.1-pcon branch has been merged to
drm-next and backmerged to drm-intel-next. So drm-intel-next is where
the fixes should now land.

Ankit, where are we with this? I'm anxious to merge this.


Jani, I checked the lastest F/W we had got for source control mode, but 
its still having support in older DPCD 303Ch and has not updated to use 
DPCD 83h.


So this patch cannot be directly tested.

Since this patch is correctly fixing to use bitwise operator, can we go 
ahead with the merge?




BR,
Jani.




BR,
Jani.




Thanks & Regards,

Ankit


On 12/23/2020 4:21 PM, Jani Nikula wrote:

On Wed, 23 Dec 2020, Chris Wilson  wrote:

drivers/gpu/drm/i915/display/intel_dp.c:6922 intel_dp_update_420() warn: should 
this be a bitwise op?
drivers/gpu/drm/i915/display/intel_dp.c:6922 intel_dp_update_420() warn: should 
this be a bitwise op?
drivers/gpu/drm/i915/display/intel_dp.c:6923 intel_dp_update_420() warn: should 
this be a bitwise op?

Inside drm_dp_downstream_rgb_to_ycbcr_conversion(), that paramter
'color_spc' is used as return port_cap[3] & color_spc, implying that it
is indeed a mask and not a boolean value.

So this one belongs in topic/dp-hdmi-2.1-pcon branch.

Purely based on the context this is the right thing to do, so:

Reviewed-by: Jani Nikula 

Ankit, please test the patch in case it uncovers some other
issues. It'll impact the RGB to YCbCr conversion.

BR,
Jani.



Fixes: 522508b665df ("drm/i915/display: Let PCON convert from RGB to YCbCr if it 
can")
Signed-off-by: Chris Wilson 
Cc: Uma Shankar 
Cc: Ankit Nautiyal 
Cc: Jani Nikula 
---
   drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
   1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 8b4b2ea52859..157a850a83a7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6918,8 +6918,8 @@ intel_dp_update_420(struct intel_dp *intel_dp)

intel_dp->downstream_ports);
rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
 
intel_dp->downstream_ports,
-
DP_DS_HDMI_BT601_RGB_YCBCR_CONV ||
-
DP_DS_HDMI_BT709_RGB_YCBCR_CONV ||
+
DP_DS_HDMI_BT601_RGB_YCBCR_CONV |
+
DP_DS_HDMI_BT709_RGB_YCBCR_CONV |
 
DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
   
   	if (INTEL_GEN(i915) >= 11) {

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: support two CSC module on gen11 and later (rev2)

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm/i915: support two CSC module on gen11 and later (rev2)
URL   : https://patchwork.freedesktop.org/series/85847/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9617 -> Patchwork_19364


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19364/index.html

Known issues


  Here are the changes found in Patchwork_19364 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@query-info:
- fi-tgl-y:   NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19364/fi-tgl-y/igt@amdgpu/amd_ba...@query-info.html

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +1 similar 
issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9617/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19364/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@i915_pm_rpm@module-reload:
- fi-byt-j1900:   [PASS][4] -> [INCOMPLETE][5] ([i915#142] / 
[i915#2405])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9617/fi-byt-j1900/igt@i915_pm_...@module-reload.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19364/fi-byt-j1900/igt@i915_pm_...@module-reload.html

  * igt@runner@aborted:
- fi-byt-j1900:   NOTRUN -> [FAIL][6] ([i915#1814] / [i915#2505])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19364/fi-byt-j1900/igt@run...@aborted.html

  
 Possible fixes 

  * igt@debugfs_test@read_all_entries:
- fi-cfl-8109u:   [DMESG-WARN][7] ([i915#203] / [i915#262]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9617/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19364/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html

  * igt@gem_exec_suspend@basic-s0:
- fi-cfl-8109u:   [DMESG-WARN][9] ([i915#262]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9617/fi-cfl-8109u/igt@gem_exec_susp...@basic-s0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19364/fi-cfl-8109u/igt@gem_exec_susp...@basic-s0.html

  * igt@gem_linear_blits@basic:
- fi-tgl-y:   [DMESG-WARN][11] ([i915#402]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9617/fi-tgl-y/igt@gem_linear_bl...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19364/fi-tgl-y/igt@gem_linear_bl...@basic.html

  
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
  [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
  [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (41 -> 37)
--

  Missing(4): fi-ctg-p8600 fi-bdw-samus fi-bsw-cyan fi-apl-guc 


Build changes
-

  * Linux: CI_DRM_9617 -> Patchwork_19364

  CI-20190529: 20190529
  CI_DRM_9617: 7a59b49a5bc6b8fe65ca6b9d5ff69abb43081f95 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5959: c5cf0734c4f6c1fa17a6a15b5aa721c3a0b8c494 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19364: 3c8df051f8f6d07642b86d7247f691f27571d824 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3c8df051f8f6 drm/i915: support two CSC module on gen11 and later

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19364/index.html
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Re: [Intel-gfx] [PATCH] drm/i915: support two CSC module on gen11 and later

2021-01-14 Thread Lee, Shawn C

On Thursday, January 14, 2021 11:32 PM, Ville Syrjälä wrote:
>On Thu, Jan 14, 2021 at 05:22:36PM +0800, Lee Shawn C wrote:
>> There are two CSC on pipeline on gen11 and later platform.
>> User space application is allowed to enable CTM and RGB to YCbCr 
>> coversion at the same time now.
>> 
>> Cc: Ville Syrjala 
>> Cc: Imre Deak 
>> Cc: Jani Nikula 
>> Cc: Cooper Chiou 
>> Cc: Shankar Uma 
>> 
>> Signed-off-by: Lee Shawn C 
>> ---
>>  drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index 1a0f00f37ca9..721d5ce1ed2b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -8303,7 +8303,8 @@ static int intel_crtc_compute_config(struct intel_crtc 
>> *crtc,
>>  return -EINVAL;
>>  }
>>  
>> -if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>> +if ((INTEL_GEN(dev_priv) < 11) &&
>> +(pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>>   pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
>>   pipe_config->hw.ctm) {
>
>Didn't realize we had this check here. It should really be moved into 
>{ivb,glk}_color_check().

Thanks for comments! I will move it to {ivb,glk}_color_check() and submit patch 
v2.

Best regards,
Shawn

>
>--
>Ville Syrjälä
>Intel
>
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[Intel-gfx] [PATCH v2] drm/i915: support two CSC module on gen11 and later

2021-01-14 Thread Lee Shawn C

There are two CSC on pipeline on gen11 and later platform.
User space application is allowed to enable CTM and RGB
to YCbCr coversion at the same time now.

v2: check csc capability in {}_color_check function.

Cc: Ville Syrjala 
Cc: Imre Deak 
Cc: Jani Nikula 
Cc: Cooper Chiou 
Cc: Shankar Uma 

Signed-off-by: Lee Shawn C 
---
 drivers/gpu/drm/i915/display/intel_color.c   | 45 
 drivers/gpu/drm/i915/display/intel_display.c | 13 --
 2 files changed, 45 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c 
b/drivers/gpu/drm/i915/display/intel_color.c
index 172d398081ee..22edcd0c9ad5 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1322,10 +1322,35 @@ static u32 i9xx_gamma_mode(struct intel_crtc_state 
*crtc_state)
return GAMMA_MODE_MODE_10BIT; /* i965+ only */
 }
 
+static int check_csc(const struct intel_crtc_state *pipe_config)
+{
+   struct drm_i915_private *dev_priv = 
to_i915(pipe_config->uapi.crtc->dev);
+
+   if ((INTEL_GEN(dev_priv) < 11) &&
+   (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
+pipe_config->hw.ctm) {
+   /*
+* There is only one pipe CSC unit per pipe, and we need that
+* for output conversion from RGB->YCBCR. So if CTM is already
+* applied we can't support YCBCR420 output.
+*/
+   drm_dbg_kms(&dev_priv->drm,
+   "YCBCR420 and CTM together are not possible\n");
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
 static int i9xx_color_check(struct intel_crtc_state *crtc_state)
 {
int ret;
 
+   ret = check_csc(crtc_state);
+   if (ret)
+   return ret;
+
ret = check_luts(crtc_state);
if (ret)
return ret;
@@ -1374,6 +1399,10 @@ static int chv_color_check(struct intel_crtc_state 
*crtc_state)
 {
int ret;
 
+   ret = check_csc(crtc_state);
+   if (ret)
+   return ret;
+
ret = check_luts(crtc_state);
if (ret)
return ret;
@@ -1427,6 +1456,10 @@ static int ilk_color_check(struct intel_crtc_state 
*crtc_state)
 {
int ret;
 
+   ret = check_csc(crtc_state);
+   if (ret)
+   return ret;
+
ret = check_luts(crtc_state);
if (ret)
return ret;
@@ -1488,6 +1521,10 @@ static int ivb_color_check(struct intel_crtc_state 
*crtc_state)
bool limited_color_range = ilk_csc_limited_range(crtc_state);
int ret;
 
+   ret = check_csc(crtc_state);
+   if (ret)
+   return ret;
+
ret = check_luts(crtc_state);
if (ret)
return ret;
@@ -1527,6 +1564,10 @@ static int glk_color_check(struct intel_crtc_state 
*crtc_state)
 {
int ret;
 
+   ret = check_csc(crtc_state);
+   if (ret)
+   return ret;
+
ret = check_luts(crtc_state);
if (ret)
return ret;
@@ -1592,6 +1633,10 @@ static int icl_color_check(struct intel_crtc_state 
*crtc_state)
 {
int ret;
 
+   ret = check_csc(crtc_state);
+   if (ret)
+   return ret;
+
ret = check_luts(crtc_state);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 66990e48c0d4..e60cbe8b0203 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7835,19 +7835,6 @@ static int intel_crtc_compute_config(struct intel_crtc 
*crtc,
return -EINVAL;
}
 
-   if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
-pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
-pipe_config->hw.ctm) {
-   /*
-* There is only one pipe CSC unit per pipe, and we need that
-* for output conversion from RGB->YCBCR. So if CTM is already
-* applied we can't support YCBCR420 output.
-*/
-   drm_dbg_kms(&dev_priv->drm,
-   "YCBCR420 and CTM together are not possible\n");
-   return -EINVAL;
-   }
-
/*
 * Pipe horizontal size must be even in:
 * - DVO ganged mode
-- 
2.17.1

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Re: [Intel-gfx] [BUG] on reboot: bisected to: drm/i915: Shut down displays gracefully on reboot

2021-01-14 Thread Linus Torvalds

On Thu, Jan 14, 2021 at 2:01 PM Steven Rostedt  wrote:
>
> Thanks, I take it, it will be going into mainline soon.

Just got merged - it might be a good idea to verify that your problem is solved.

Linus
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[Intel-gfx] linux-next: build warnings after merge of the drm-misc tree

2021-01-14 Thread Stephen Rothwell

Hi all,

After merging the drm-misc tree, today's linux-next build (x86_64
allmodconfig) produced this warning:

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c: In function 
'amdgpu_display_user_framebuffer_create':
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:929:24: warning: unused variable 
'adev' [-Wunused-variable]
  929 |  struct amdgpu_device *adev = drm_to_adev(dev);
  |^~~~

Introduced by commit

  8f66090b7bb7 ("drm/amdgpu: Remove references to struct drm_device.pdev")

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c: In function 
'amdgpu_device_resize_fb_bar':
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1109:6: warning: unused variable 
'space_needed' [-Wunused-variable]
 1109 |  u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
  |  ^~~~

Introduced by commit

  453f617a30aa ("drm/amdgpu: Resize BAR0 to the maximum available size, even if 
it doesn't cover VRAM")

-- 
Cheers,
Stephen Rothwell


pgpzTTzZvqwKN.pgp
Description: OpenPGP digital signature
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add support for Intel's eDP backlight controls (rev10)

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm/i915: Add support for Intel's eDP backlight controls (rev10)
URL   : https://patchwork.freedesktop.org/series/81702/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9612 -> Patchwork_19363


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19363/index.html

Known issues


  Here are the changes found in Patchwork_19363 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rpm@module-reload:
- fi-byt-j1900:   [PASS][1] -> [INCOMPLETE][2] ([i915#142] / 
[i915#2405])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-byt-j1900/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19363/fi-byt-j1900/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@blt:
- fi-snb-2520m:   [PASS][3] -> [DMESG-FAIL][4] ([i915#1409])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-snb-2520m/igt@i915_selftest@l...@blt.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19363/fi-snb-2520m/igt@i915_selftest@l...@blt.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u:   [PASS][5] -> [FAIL][6] ([i915#1161] / [i915#262])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19363/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar 
issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19363/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  * igt@runner@aborted:
- fi-byt-j1900:   NOTRUN -> [FAIL][9] ([i915#1814] / [i915#2505])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19363/fi-byt-j1900/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_render_tiled_blits@basic:
- fi-tgl-y:   [DMESG-WARN][10] ([i915#402]) -> [PASS][11] +1 
similar issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19363/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html

  
  [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
  [i915#1409]: https://gitlab.freedesktop.org/drm/intel/issues/1409
  [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
  [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (41 -> 38)
--

  Missing(3): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9612 -> Patchwork_19363

  CI-20190529: 20190529
  CI_DRM_9612: 3d921d1ad818c1aabb5b2bd3f0861df99e49be9b @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5959: c5cf0734c4f6c1fa17a6a15b5aa721c3a0b8c494 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19363: 6910bd0cd8fc9ff9a037db66558da7c727e3c8e4 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

6910bd0cd8fc drm/dp: Revert "drm/dp: Introduce EDID-based quirks"
eafcab165713 drm/i915/dp: Allow forcing specific interfaces through 
enable_dpcd_backlight
b2c2f834248b drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for 
now)
e8d05076842e drm/i915: Keep track of pwm-related backlight hooks separately
a14218296b37 drm/i915: Pass port to intel_panel_bl_funcs.get()

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19363/index.html
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add DEBUG_GEM to the recommended CI config

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm/i915: Add DEBUG_GEM to the recommended CI config
URL   : https://patchwork.freedesktop.org/series/85868/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9608_full -> Patchwork_19356_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19356_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19356_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19356_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_softpin@softpin:
- shard-glk:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9608/shard-glk4/igt@gem_soft...@softpin.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/shard-glk1/igt@gem_soft...@softpin.html

  
Known issues


  Here are the changes found in Patchwork_19356_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@api_intel_bb@render-ccs:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([i915#2405])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9608/shard-iclb4/igt@api_intel...@render-ccs.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/shard-iclb6/igt@api_intel...@render-ccs.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-skl:  NOTRUN -> [WARN][5] ([i915#2658])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/shard-skl1/igt@gem_pwr...@basic-exhaustion.html

  * igt@gen9_exec_parse@allowed-all:
- shard-apl:  [PASS][6] -> [DMESG-WARN][7] ([i915#1436] / 
[i915#716])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9608/shard-apl3/igt@gen9_exec_pa...@allowed-all.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/shard-apl6/igt@gen9_exec_pa...@allowed-all.html

  * igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl:  [PASS][8] -> [FAIL][9] ([i915#2521])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9608/shard-skl7/igt@kms_async_fl...@alternate-sync-async-flip.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/shard-skl5/igt@kms_async_fl...@alternate-sync-async-flip.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- shard-skl:  NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/shard-skl9/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_color_chamelium@pipe-c-ctm-max:
- shard-kbl:  NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +1 
similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/shard-kbl3/igt@kms_color_chamel...@pipe-c-ctm-max.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen:
- shard-skl:  [PASS][12] -> [FAIL][13] ([i915#54]) +6 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9608/shard-skl6/igt@kms_cursor_...@pipe-a-cursor-256x85-offscreen.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/shard-skl2/igt@kms_cursor_...@pipe-a-cursor-256x85-offscreen.html

  * igt@kms_cursor_edge_walk@pipe-d-64x64-left-edge:
- shard-kbl:  NOTRUN -> [SKIP][14] ([fdo#109271]) +33 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/shard-kbl3/igt@kms_cursor_edge_w...@pipe-d-64x64-left-edge.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl:  [PASS][15] -> [FAIL][16] ([i915#79])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9608/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl:  NOTRUN -> [FAIL][17] ([i915#2122]) +2 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/shard-skl1/igt@kms_flip@plain-flip-fb-recre...@b-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt:
- shard-apl:  NOTRUN -> [SKIP][18] ([fdo#109271]) +10 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/shard-apl4/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-skl:  NOTRUN -> [SKIP][19] ([fdo#109271]) +20 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/shard-skl9/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_plane_alpha_blend@pipe-c-

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add support for Intel's eDP backlight controls (rev10)

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm/i915: Add support for Intel's eDP backlight controls (rev10)
URL   : https://patchwork.freedesktop.org/series/81702/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a14218296b37 drm/i915: Pass port to intel_panel_bl_funcs.get()
e8d05076842e drm/i915: Keep track of pwm-related backlight hooks separately
-:87: WARNING:BAD_SIGN_OFF: Duplicate signature
#87: 
Signed-off-by: Lyude Paul 

total: 0 errors, 1 warnings, 0 checks, 740 lines checked
b2c2f834248b drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for 
now)
eafcab165713 drm/i915/dp: Allow forcing specific interfaces through 
enable_dpcd_backlight
6910bd0cd8fc drm/dp: Revert "drm/dp: Introduce EDID-based quirks"


___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Shuffle DP code around

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm/i915: Shuffle DP code around
URL   : https://patchwork.freedesktop.org/series/85878/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9612 -> Patchwork_19362


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19362/index.html

Known issues


  Here are the changes found in Patchwork_19362 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y:   [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar 
issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19362/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html

  * igt@runner@aborted:
- fi-kbl-r:   NOTRUN -> [FAIL][3] ([i915#1569] / [i915#192] / 
[i915#193] / [i915#194] / [i915#2295])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19362/fi-kbl-r/igt@run...@aborted.html

  
 Possible fixes 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [DMESG-WARN][4] ([i915#402]) -> [PASS][5] +2 similar 
issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19362/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  
  [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569
  [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192
  [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193
  [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194
  [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (41 -> 37)
--

  Missing(4): fi-byt-j1900 fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9612 -> Patchwork_19362

  CI-20190529: 20190529
  CI_DRM_9612: 3d921d1ad818c1aabb5b2bd3f0861df99e49be9b @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5959: c5cf0734c4f6c1fa17a6a15b5aa721c3a0b8c494 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19362: 303d614cbb64c6495251dea9f9b28fdb8045d96c @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

303d614cbb64 drm/i915: Introduce g4x_dp.c
90067b76465c drm/i915: Fix the PHY compliance test vs. hotplug mishap
88f2b4fea349 drm/i915: Split intel_ddi_encoder_reset() from 
intel_dp_encoder_reset()
2d486f60d7dd drm/i915: Relocate intel_dp_program_link_training_pattern()
77a30579d793 drm/i915: Remove dead signal level debugs
e5f62898fdee drm/i915: Remove dead TPS3->TPS2 fallback code
4c22a0db410f drm/i915: Fix the training pattern debug print

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19362/index.html
___
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[Intel-gfx] [PATCH v7 5/5] drm/dp: Revert "drm/dp: Introduce EDID-based quirks"

2021-01-14 Thread Lyude Paul

This reverts commit 0883ce8146ed6074c76399f4e70dbed788582e12. Originally
these quirks were added because of the issues with using the eDP
backlight interfaces on certain laptop panels, which made it impossible
to properly probe for DPCD backlight support without having a whitelist
for panels that we know have working VESA backlight control interfaces
over DPCD. As well, it should be noted it was impossible to use the
normal sink OUI for recognizing these panels as none of them actually
filled out their OUIs, hence needing to resort to checking EDIDs.

At the time we weren't really sure why certain panels had issues with
DPCD backlight controls, but we eventually figured out that there was a
second interface that these problematic laptop panels actually did work
with and advertise properly: Intel's proprietary backlight interface for
HDR panels. So far the testing we've done hasn't brought any panels to
light that advertise this interface and don't support it properly, which
means we finally have a real solution to this problem.

As a result, we now have no need for the force DPCD backlight quirk, and
furthermore this also removes the need for any kind of EDID quirk
checking in DRM. So, let's just revert it for now since we were the only
driver using this.

v3:
* Rebase
v2:
* Fix indenting error picked up by checkpatch in
  intel_edp_init_connector()

Signed-off-by: Lyude Paul 
Acked-by: Jani Nikula 
Cc: thay...@noraisin.net
Cc: Vasily Khoruzhick 
---
 drivers/gpu/drm/drm_dp_helper.c   | 83 +--
 drivers/gpu/drm/drm_dp_mst_topology.c |  3 +-
 .../drm/i915/display/intel_display_types.h|  1 -
 drivers/gpu/drm/i915/display/intel_dp.c   |  9 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  3 +-
 drivers/gpu/drm/i915/display/intel_psr.c  |  2 +-
 include/drm/drm_dp_helper.h   | 21 +
 7 files changed, 9 insertions(+), 113 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 3ecde451f523..19dbdeb581cb 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1236,7 +1236,7 @@ bool drm_dp_read_sink_count_cap(struct drm_connector 
*connector,
return connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
-   !drm_dp_has_quirk(desc, 0, DP_DPCD_QUIRK_NO_SINK_COUNT);
+   !drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT);
 }
 EXPORT_SYMBOL(drm_dp_read_sink_count_cap);
 
@@ -1957,87 +1957,6 @@ drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, 
bool is_branch)
 #undef DEVICE_ID_ANY
 #undef DEVICE_ID
 
-struct edid_quirk {
-   u8 mfg_id[2];
-   u8 prod_id[2];
-   u32 quirks;
-};
-
-#define MFG(first, second) { (first), (second) }
-#define PROD_ID(first, second) { (first), (second) }
-
-/*
- * Some devices have unreliable OUIDs where they don't set the device ID
- * correctly, and as a result we need to use the EDID for finding additional
- * DP quirks in such cases.
- */
-static const struct edid_quirk edid_quirk_list[] = {
-   /* Optional 4K AMOLED panel in the ThinkPad X1 Extreme 2nd Generation
-* only supports DPCD backlight controls
-*/
-   { MFG(0x4c, 0x83), PROD_ID(0x41, 0x41), 
BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
-   /*
-* Some Dell CML 2020 systems have panels support both AUX and PWM
-* backlight control, and some only support AUX backlight control. All
-* said panels start up in AUX mode by default, and we don't have any
-* support for disabling HDR mode on these panels which would be
-* required to switch to PWM backlight control mode (plus, I'm not
-* even sure we want PWM backlight controls over DPCD backlight
-* controls anyway...). Until we have a better way of detecting these,
-* force DPCD backlight mode on all of them.
-*/
-   { MFG(0x06, 0xaf), PROD_ID(0x9b, 0x32), 
BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
-   { MFG(0x06, 0xaf), PROD_ID(0xeb, 0x41), 
BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
-   { MFG(0x4d, 0x10), PROD_ID(0xc7, 0x14), 
BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
-   { MFG(0x4d, 0x10), PROD_ID(0xe6, 0x14), 
BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
-   { MFG(0x4c, 0x83), PROD_ID(0x47, 0x41), 
BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
-   { MFG(0x09, 0xe5), PROD_ID(0xde, 0x08), 
BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
-};
-
-#undef MFG
-#undef PROD_ID
-
-/**
- * drm_dp_get_edid_quirks() - Check the EDID of a DP device to find additional
- * DP-specific quirks
- * @edid: The EDID to check
- *
- * While OUIDs are meant to be used to recognize a DisplayPort device, a lot
- * of manufacturers don't seem to like following standards and neglect to fill
- * the dev-ID in, making it impossible to only use OUIDs for determining
- * quirks in some cases. This function can

[Intel-gfx] [PATCH v7 4/5] drm/i915/dp: Allow forcing specific interfaces through enable_dpcd_backlight

2021-01-14 Thread Lyude Paul

Since we now support controlling panel backlights through DPCD using
both the standard VESA interface, and Intel's proprietary HDR backlight
interface, we should allow the user to be able to explicitly choose
between one or the other in the event that we're wrong about panels
reliably reporting support for the Intel HDR interface.

So, this commit adds support for this by introducing two new
enable_dpcd_backlight options: 2 which forces i915 to only probe for the
VESA interface, and 3 which forces i915 to only probe for the Intel
backlight interface (might be useful if we find panels in the wild that
report the VESA interface in their VBT, but actually only support the
Intel backlight interface).

v3:
* Rebase

Signed-off-by: Lyude Paul 
Reviewed-by: Jani Nikula 
Cc: thay...@noraisin.net
Cc: Vasily Khoruzhick 
---
 .../drm/i915/display/intel_dp_aux_backlight.c | 45 +--
 drivers/gpu/drm/i915/i915_params.c|  2 +-
 2 files changed, 43 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 9b0589cf8d17..31a478f63d52 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -612,15 +612,54 @@ static const struct intel_panel_bl_funcs 
intel_dp_vesa_bl_funcs = {
.get = intel_dp_aux_vesa_get_backlight,
 };
 
+enum intel_dp_aux_backlight_modparam {
+   INTEL_DP_AUX_BACKLIGHT_AUTO = -1,
+   INTEL_DP_AUX_BACKLIGHT_OFF = 0,
+   INTEL_DP_AUX_BACKLIGHT_ON = 1,
+   INTEL_DP_AUX_BACKLIGHT_FORCE_VESA = 2,
+   INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL = 3,
+};
+
 int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector)
 {
struct drm_device *dev = connector->base.dev;
struct intel_panel *panel = &connector->panel;
struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+   bool try_intel_interface = false, try_vesa_interface = false;
 
-   if (i915->params.enable_dpcd_backlight == 0)
+   /* Check the VBT and user's module parameters to figure out which
+* interfaces to probe
+*/
+   switch (i915->params.enable_dpcd_backlight) {
+   case INTEL_DP_AUX_BACKLIGHT_OFF:
return -ENODEV;
+   case INTEL_DP_AUX_BACKLIGHT_AUTO:
+   switch (i915->vbt.backlight.type) {
+   case INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE:
+   try_vesa_interface = true;
+   break;
+   case INTEL_BACKLIGHT_DISPLAY_DDI:
+   try_intel_interface = true;
+   try_vesa_interface = true;
+   break;
+   default:
+   return -ENODEV;
+   }
+   break;
+   case INTEL_DP_AUX_BACKLIGHT_ON:
+   if (i915->vbt.backlight.type != 
INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE)
+   try_intel_interface = true;
+
+   try_vesa_interface = true;
+   break;
+   case INTEL_DP_AUX_BACKLIGHT_FORCE_VESA:
+   try_vesa_interface = true;
+   break;
+   case INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL:
+   try_intel_interface = true;
+   break;
+   }
 
/*
 * A lot of eDP panels in the wild will report supporting both the
@@ -629,13 +668,13 @@ int intel_dp_aux_init_backlight_funcs(struct 
intel_connector *connector)
 * and will only work with the Intel interface. So, always probe for
 * that first.
 */
-   if (intel_dp_aux_supports_hdr_backlight(connector)) {
+   if (try_intel_interface && 
intel_dp_aux_supports_hdr_backlight(connector)) {
drm_dbg_kms(dev, "Using Intel proprietary eDP backlight 
controls\n");
panel->backlight.funcs = &intel_dp_hdr_bl_funcs;
return 0;
}
 
-   if (intel_dp_aux_supports_vesa_backlight(connector)) {
+   if (try_vesa_interface && 
intel_dp_aux_supports_vesa_backlight(connector)) {
drm_dbg_kms(dev, "Using VESA eDP backlight controls\n");
panel->backlight.funcs = &intel_dp_vesa_bl_funcs;
return 0;
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 7f139ea4a90b..6939634e56ed 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -185,7 +185,7 @@ i915_param_named_unsafe(inject_probe_failure, uint, 0400,
 
 i915_param_named(enable_dpcd_backlight, int, 0400,
"Enable support for DPCD backlight control"
-   "(-1=use per-VBT LFP backlight type setting [default], 0=disabled, 
1=enabled)");
+   "(-1=use per-VBT LFP backlight type setting [default], 0=disabled, 
1=enable, 2=force VESA interface, 3=force Intel interface)");
 
 #if IS_ENABLED(CONFIG_DRM_

[Intel-gfx] [PATCH v7 3/5] drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now)

2021-01-14 Thread Lyude Paul

So-recently a bunch of laptops on the market have started using DPCD
backlight controls instead of the traditional DDI backlight controls.
Originally we thought we had this handled by adding VESA backlight
control support to i915, but the story ended up being a lot more
complicated then that.

Simply put-there's two main backlight interfaces Intel can see in the
wild. Intel's proprietary HDR backlight interface, and the standard VESA
backlight interface. Note that many panels have been observed to report
support for both backlight interfaces, but testing has shown far more
panels work with the Intel HDR backlight interface at the moment.
Additionally, the VBT appears to be capable of reporting support for the
VESA backlight interface but not the Intel HDR interface which needs to
be probed by setting the right magic OUI.

On top of that however, there's also actually two different variants of
the Intel HDR backlight interface. The first uses the AUX channel for
controlling the brightness of the screen in both SDR and HDR mode, and
the second only uses the AUX channel for setting the brightness level in
HDR mode - relying on PWM for setting the brightness level in SDR mode.

For the time being we've been using EDIDs to maintain a list of quirks
for panels that safely do support the VESA backlight interface. Adding
support for Intel's HDR backlight interface in addition however, should
finally allow us to auto-detect eDP backlight controls properly so long
as we probe like so:

* If the panel's VBT reports VESA backlight support, assume it really
  does support it
* If the panel's VBT reports DDI backlight controls:
  * First probe for Intel's HDR backlight interface
  * If that fails, probe for VESA's backlight interface
  * If that fails, assume no DPCD backlight control
* If the panel's VBT reports any other backlight type: just assume it
  doesn't have DPCD backlight controls

Changes since v4:
* Fix checkpatch issues
Changes since v3:
* Stop using drm_device and use drm_i915_private instead
* Don't forget to return from intel_dp_aux_hdr_get_backlight() if we fail
  to read the current backlight mode from the DPCD
* s/uint8_t/u8/
* Remove unneeded parenthesis in intel_dp_aux_hdr_enable_backlight()
* Use drm_dbg_kms() in intel_dp_aux_init_backlight_funcs()

Signed-off-by: Lyude Paul 
Reviewed-by: Jani Nikula 
Cc: thay...@noraisin.net
Cc: Vasily Khoruzhick 
---
 .../drm/i915/display/intel_display_types.h|   9 +-
 .../drm/i915/display/intel_dp_aux_backlight.c | 247 --
 drivers/gpu/drm/i915/display/intel_panel.c|  40 ++-
 drivers/gpu/drm/i915/display/intel_panel.h|   4 +
 4 files changed, 269 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index ee23cc1518df..a2ea651ece79 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -261,7 +261,14 @@ struct intel_panel {
struct pwm_state pwm_state;
 
/* DPCD backlight */
-   u8 pwmgen_bit_count;
+   union {
+   struct {
+   u8 pwmgen_bit_count;
+   } vesa;
+   struct {
+   bool sdr_uses_aux;
+   } intel;
+   } edp;
 
struct backlight_device *device;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index de764dae1e66..9b0589cf8d17 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -22,8 +22,26 @@
  *
  */
 
+/*
+ * Laptops with Intel GPUs which have panels that support controlling the
+ * backlight through DP AUX can actually use two different interfaces: Intel's
+ * proprietary DP AUX backlight interface, and the standard VESA backlight
+ * interface. Unfortunately, at the time of writing this a lot of laptops will
+ * advertise support for the standard VESA backlight interface when they
+ * don't properly support it. However, on these systems the Intel backlight
+ * interface generally does work properly. Additionally, these systems will
+ * usually just indicate that they use PWM backlight controls in their VBIOS
+ * for some reason.
+ */
+
 #include "intel_display_types.h"
 #include "intel_dp_aux_backlight.h"
+#include "intel_panel.h"
+
+/* TODO:
+ * Implement HDR, right now we just implement the bare minimum to bring us 
back into SDR mode so we
+ * can make people's backlights work in the mean time
+ */
 
 /*
  * DP AUX registers for Intel's proprietary HDR backlight interface. We define
@@ -77,6 +95,178 @@
 
 #define INTEL_EDP_BRIGHTNESS_OPTIMIZATION_10x359
 
+/* Intel EDP backlight callbacks */
+static bool
+intel_dp_aux_supports_hdr_backlight(struct intel_connector

[Intel-gfx] [PATCH v7 2/5] drm/i915: Keep track of pwm-related backlight hooks separately

2021-01-14 Thread Lyude Paul

Currently, every different type of backlight hook that i915 supports is
pretty straight forward - you have a backlight, probably through PWM
(but maybe DPCD), with a single set of platform-specific hooks that are
used for controlling it.

HDR backlights, in particular VESA and Intel's HDR backlight
implementations, can end up being more complicated. With Intel's
proprietary interface, HDR backlight controls always run through the
DPCD. When the backlight is in SDR backlight mode however, the driver
may need to bypass the TCON and control the backlight directly through
PWM.

So, in order to support this we'll need to split our backlight callbacks
into two groups: a set of high-level backlight control callbacks in
intel_panel, and an additional set of pwm-specific backlight control
callbacks. This also implies a functional changes for how these
callbacks are used:

* We now keep track of two separate backlight level ranges, one for the
  high-level backlight, and one for the pwm backlight range
* We also keep track of backlight enablement and PWM backlight
  enablement separately
* Since the currently set backlight level might not be the same as the
  currently programmed PWM backlight level, we stop setting
  panel->backlight.level with the currently programmed PWM backlight
  level in panel->backlight.pwm_funcs->setup(). Instead, we rely
  on the higher level backlight control functions to retrieve the
  current PWM backlight level (in this case, intel_pwm_get_backlight()).
  Note that there are still a few PWM backlight setup callbacks that
  do actually need to retrieve the current PWM backlight level, although
  we no longer save this value in panel->backlight.level like before.

Additionally, we drop the call to lpt_get_backlight() in
lpt_setup_backlight(), and avoid unconditionally writing the PWM value that
we get from it and only write it back if we're in CPU mode, and switching
to PCH mode. The reason for this is because in the original codepath for
this, it was expected that the intel_panel_bl_funcs->setup() hook would be
responsible for fetching the initial backlight level. On lpt systems, the
only time we could ever be in PCH backlight mode is during the initial
driver load - meaning that outside of the setup() hook, lpt_get_backlight()
will always be the callback used for retrieving the current backlight
level. After this patch we still need to fetch and write-back the PCH
backlight value if we're switching from CPU mode to PCH, but because
intel_pwm_setup_backlight() will retrieve the backlight level after setup()
using the get() hook, which always ends up being lpt_get_backlight(). Thus
- an additional call to lpt_get_backlight() in lpt_setup_backlight() is
made redundant.

v8:
* Go back to getting initial brightness level with
  intel_pwm_get_backlight(), the other fix we had was definitely wrong.
v7:
* Use panel->backlight.pwm_funcs->get() to get the backlight level in
  intel_pwm_setup_backlight(), lest we upset lockdep
* Rebase
* Rename intel_panel_sanitize_pwm_level() to intel_panel_invert_pwm_level()
v6:
* Make sure to grab connection_mutex before calling
  intel_pwm_get_backlight() in intel_pwm_setup_backlight()
v5:
* Fix indenting warnings from checkpatch
v4:
* Fix commit message
* Remove outdated comment in intel_panel.c
* Rename pwm_(min|max) to pwm_level_(min|max)
* Use intel_pwm_get_backlight() in intel_pwm_setup_backlight() instead of
  indirection
* Don't move intel_dp_aux_init_bcklight_funcs() call to bottom of
  intel_panel_init_backlight_funcs() quite yet
v3:
* Reuse intel_panel_bl_funcs() for pwm_funcs
* Explain why we drop lpt_get_backlight()

Signed-off-by: Lyude Paul 
Reviewed-by: Jani Nikula 
Cc: thay...@noraisin.net
Cc: Vasily Khoruzhick 

squash! drm/i915: Keep track of pwm-related backlight hooks separately

Signed-off-by: Lyude Paul 
---
 .../drm/i915/display/intel_display_types.h|   4 +
 drivers/gpu/drm/i915/display/intel_panel.c| 331 ++
 2 files changed, 188 insertions(+), 147 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index b1f4ec144207..ee23cc1518df 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -252,6 +252,9 @@ struct intel_panel {
bool alternate_pwm_increment;   /* lpt+ */
 
/* PWM chip */
+   u32 pwm_level_min;
+   u32 pwm_level_max;
+   bool pwm_enabled;
bool util_pin_active_low;   /* bxt+ */
u8 controller;  /* bxt+ only */
struct pwm_device *pwm;
@@ -263,6 +266,7 @@ struct intel_panel {
struct backlight_device *device;
 
const struct intel_panel_bl_funcs *funcs;
+   const struct intel_panel_bl_funcs *pwm_funcs;
void (*power)(struct intel_connector *, bool enable);
} backlight;
 }

[Intel-gfx] [PATCH v7 1/5] drm/i915: Pass port to intel_panel_bl_funcs.get()

2021-01-14 Thread Lyude Paul

In the next commit where we split PWM related backlight functions from
higher-level backlight functions, we'll want to be able to retrieve the
backlight level for the current display panel from the
intel_panel_bl_funcs->setup() function using pwm_funcs->get(). Since
intel_panel_bl_funcs->setup() is called before we've fully read in the
current hardware state into our atomic state, we can't grab atomic
modesetting locks safely anyway in intel_panel_bl_funcs->setup(), and some
PWM backlight functions (vlv_get_backlight() in particular) require knowing
the currently used pipe we need to be able to discern the current display
pipe through other means. Luckily, we're already passing the current
display pipe to intel_panel_bl_funcs->setup() so all we have to do in order
to achieve this is pass down that parameter to intel_panel_bl_funcs->get().

So, fix this by accepting an additional pipe parameter in
intel_panel_bl_funcs->get(), and leave figuring out the current display
pipe up to the caller.

Signed-off-by: Lyude Paul 
---
 .../drm/i915/display/intel_display_types.h|  2 +-
 .../drm/i915/display/intel_dp_aux_backlight.c |  4 +-
 .../i915/display/intel_dsi_dcs_backlight.c|  2 +-
 drivers/gpu/drm/i915/display/intel_panel.c| 40 ---
 4 files changed, 21 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 585bb1edea04..b1f4ec144207 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -228,7 +228,7 @@ struct intel_encoder {
 struct intel_panel_bl_funcs {
/* Connector and platform specific backlight functions */
int (*setup)(struct intel_connector *connector, enum pipe pipe);
-   u32 (*get)(struct intel_connector *connector);
+   u32 (*get)(struct intel_connector *connector, enum pipe pipe);
void (*set)(const struct drm_connector_state *conn_state, u32 level);
void (*disable)(const struct drm_connector_state *conn_state, u32 
level);
void (*enable)(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 9775f33d1aac..de764dae1e66 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -128,7 +128,7 @@ static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct 
intel_connector *connec
  * Read the current backlight value from DPCD register(s) based
  * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
  */
-static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector)
+static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, 
enum pipe unused)
 {
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -381,7 +381,7 @@ static int intel_dp_aux_vesa_setup_backlight(struct 
intel_connector *connector,
return -ENODEV;
 
panel->backlight.min = 0;
-   panel->backlight.level = intel_dp_aux_vesa_get_backlight(connector);
+   panel->backlight.level = intel_dp_aux_vesa_get_backlight(connector, 
pipe);
panel->backlight.enabled = 
intel_dp_aux_vesa_backlight_dpcd_mode(connector) &&
   panel->backlight.level != 0;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
index 88628764956d..584c14c4cbd0 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
@@ -43,7 +43,7 @@
 
 #define PANEL_PWM_MAX_VALUE0xFF
 
-static u32 dcs_get_backlight(struct intel_connector *connector)
+static u32 dcs_get_backlight(struct intel_connector *connector, enum pipe 
unused)
 {
struct intel_encoder *encoder = intel_attached_encoder(connector);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c 
b/drivers/gpu/drm/i915/display/intel_panel.c
index 7a4239d1c241..7587aaefc7a0 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -530,21 +530,21 @@ static u32 intel_panel_compute_brightness(struct 
intel_connector *connector,
return val;
 }
 
-static u32 lpt_get_backlight(struct intel_connector *connector)
+static u32 lpt_get_backlight(struct intel_connector *connector, enum pipe 
unused)
 {
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 
return intel_de_read(dev_priv, BLC_PWM_PCH_CTL2) & 
BACKLIGHT_DUTY_CYCLE_MASK;
 }
 
-static u32 pch_get_backlight(struct intel_connector *connector)
+static u32 pch_get_backlight(struct intel_connector *connector, enum pipe 
unused)
 {
struct drm_i915_private *dev_

[Intel-gfx] [PATCH v7 0/5] drm/i915: Add support for Intel's eDP backlight controls

2021-01-14 Thread Lyude Paul

A while ago we ran into issues while trying to enable the eDP backlight
control interface as defined by VESA, in order to make the DPCD
backlight controls on newer laptop panels work. The issue ended up being
much more complicated however, as we also apparently needed to add
support for an Intel-specific DPCD backlight control interface as the
VESA interface is broken on many laptop panels. For lack of a better
name, we just call this the Intel HDR backlight interface.

While this only adds support for the SDR backlight mode (I think), this
will fix a lot of user's laptop panels that we weren't able to properly
automatically detect DPCD backlight controls on previously.

Series-wide changes in v7:
* Add another patch that allows passing the current display pipe to
  intel_panel_bl_funcs.get(), which should fix the lockdep issues we
  were seeing with Intel's CI

Lyude Paul (5):
  drm/i915: Pass port to intel_panel_bl_funcs.get()
  drm/i915: Keep track of pwm-related backlight hooks separately
  drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now)
  drm/i915/dp: Allow forcing specific interfaces through
enable_dpcd_backlight
  drm/dp: Revert "drm/dp: Introduce EDID-based quirks"

 drivers/gpu/drm/drm_dp_helper.c   |  83 +---
 drivers/gpu/drm/drm_dp_mst_topology.c |   3 +-
 .../drm/i915/display/intel_display_types.h|  16 +-
 drivers/gpu/drm/i915/display/intel_dp.c   |   9 +-
 .../drm/i915/display/intel_dp_aux_backlight.c | 290 +++--
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   3 +-
 .../i915/display/intel_dsi_dcs_backlight.c|   2 +-
 drivers/gpu/drm/i915/display/intel_panel.c| 395 ++
 drivers/gpu/drm/i915/display/intel_panel.h|   4 +
 drivers/gpu/drm/i915/display/intel_psr.c  |   2 +-
 drivers/gpu/drm/i915/i915_params.c|   2 +-
 include/drm/drm_dp_helper.h   |  21 +-
 12 files changed, 519 insertions(+), 311 deletions(-)

-- 
2.29.2

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Shuffle DP code around

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm/i915: Shuffle DP code around
URL   : https://patchwork.freedesktop.org/series/85878/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
4c22a0db410f drm/i915: Fix the training pattern debug print
e5f62898fdee drm/i915: Remove dead TPS3->TPS2 fallback code
77a30579d793 drm/i915: Remove dead signal level debugs
2d486f60d7dd drm/i915: Relocate intel_dp_program_link_training_pattern()
88f2b4fea349 drm/i915: Split intel_ddi_encoder_reset() from 
intel_dp_encoder_reset()
90067b76465c drm/i915: Fix the PHY compliance test vs. hotplug mishap
303d614cbb64 drm/i915: Introduce g4x_dp.c
-:29: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#29: 
new file mode 100644

-:225: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#225: FILE: drivers/gpu/drm/i915/display/g4x_dp.c:192:
+}
+#define assert_dp_port_disabled(d) assert_dp_port((d), false)

-:235: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#235: FILE: drivers/gpu/drm/i915/display/g4x_dp.c:202:
+}
+#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)

-:260: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see 
Documentation/timers/timers-howto.rst
#260: FILE: drivers/gpu/drm/i915/display/g4x_dp.c:227:
+   udelay(500);

-:275: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see 
Documentation/timers/timers-howto.rst
#275: FILE: drivers/gpu/drm/i915/display/g4x_dp.c:242:
+   udelay(200);

-:294: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see 
Documentation/timers/timers-howto.rst
#294: FILE: drivers/gpu/drm/i915/display/g4x_dp.c:261:
+   udelay(200);

-:538: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a 
separate line
#538: FILE: drivers/gpu/drm/i915/display/g4x_dp.c:505:
+* ensure that we have vdd while we switch off the panel. */

-:2899: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#2899: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2961:
+  
DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);

-:2931: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2931: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2983:
+   drm_dbg_kms(&i915->drm,
+  "Failed to set protocol converter RGB->YCbCr 
conversion mode to %s\n",

total: 0 errors, 3 warnings, 6 checks, 3261 lines checked


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen12: Add display render clear color decompression support

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm/i915/gen12: Add display render clear color decompression support
URL   : https://patchwork.freedesktop.org/series/85877/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9612 -> Patchwork_19361


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19361/index.html

Known issues


  Here are the changes found in Patchwork_19361 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@fbdev@read:
- fi-tgl-y:   [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +2 similar 
issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-tgl-y/igt@fb...@read.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19361/fi-tgl-y/igt@fb...@read.html

  * igt@i915_pm_rpm@module-reload:
- fi-byt-j1900:   [PASS][3] -> [INCOMPLETE][4] ([i915#142] / 
[i915#2405])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-byt-j1900/igt@i915_pm_...@module-reload.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19361/fi-byt-j1900/igt@i915_pm_...@module-reload.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u:   [PASS][5] -> [DMESG-FAIL][6] ([i915#165])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19361/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u:   [PASS][7] -> [DMESG-WARN][8] ([i915#2868])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19361/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@runner@aborted:
- fi-byt-j1900:   NOTRUN -> [FAIL][9] ([i915#1814] / [i915#2505])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19361/fi-byt-j1900/igt@run...@aborted.html

  
 Possible fixes 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [DMESG-WARN][10] ([i915#402]) -> [PASS][11] +2 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19361/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  
  [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
  [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
  [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (41 -> 38)
--

  Missing(3): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9612 -> Patchwork_19361

  CI-20190529: 20190529
  CI_DRM_9612: 3d921d1ad818c1aabb5b2bd3f0861df99e49be9b @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5959: c5cf0734c4f6c1fa17a6a15b5aa721c3a0b8c494 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19361: 89044f4fa5e2a4bb6c3ef9be481196e64a68565b @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

89044f4fa5e2 drm/i915/tgl: Add Clear Color support for TGL Render Decompression
45aadd34aaa8 drm/i915/gem: Add a helper to read data from a GEM object page
89e07f063541 drm/framebuffer: Format modifier for Intel Gen 12 render 
compression with Clear Color

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19361/index.html
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Re: [Intel-gfx] [BUG] on reboot: bisected to: drm/i915: Shut down displays gracefully on reboot

2021-01-14 Thread Steven Rostedt

On Thu, 14 Jan 2021 21:35:53 +
Chris Wilson  wrote:

> Quoting Steven Rostedt (2021-01-14 21:32:06)
> > On reboot, one of my test boxes now triggers the following warning:  
> 
> 057fe3535eb3 ("drm/i915: Disable RPM wakeref assertions during driver 
> shutdown")
> is included with the drm-intel-fixes PR.

Thanks, I take it, it will be going into mainline soon.

-- Steve
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gen12: Add display render clear color decompression support

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm/i915/gen12: Add display render clear color decompression support
URL   : https://patchwork.freedesktop.org/series/85877/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+  ^~~~
+^~~~
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static 
assertion fai

Re: [Intel-gfx] [PATCH] drm/i915/uc: Add function to define defaults for GuC/HuC enable

2021-01-14 Thread John Harrison


On 1/13/2021 14:07, john.c.harri...@intel.com wrote:

From: John Harrison 

There is a module parameter for controlling what GuC/HuC features are
enabled. Setting to -1 means 'use the default'. However, the default
was not well defined, out of date and needs to be different across
platforms.

The default is now to disable both GuC and HuC on legacy platforms
where legacy means TGL/RKL and anything prior to Gen12. For new
platforms, the default is to load HuC but not GuC as GuC submission
has not yet landed.
Daniele pointed out that the above wording is somewhat inaccurate. GuC 
is still loaded (in order to do HuC authentication). Better wording 
would be:


   The default is now to disable both GuC and HuC on legacy platforms
   where legacy means TGL/RKL and anything prior to Gen12. For new
   platforms, the default is to load HuC but not enable GuC submission
   as that has not landed yet.


John.



Signed-off-by: John Harrison 
Reviewed-by: Daniele Ceraolo Spurio 
---
  drivers/gpu/drm/i915/gt/uc/intel_uc.c| 31 
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c |  7 +-
  drivers/gpu/drm/i915/i915_params.h   |  1 +
  3 files changed, 28 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 6a0452815c41..6abb8f2dc33d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -15,6 +15,29 @@
  static const struct intel_uc_ops uc_ops_off;
  static const struct intel_uc_ops uc_ops_on;
  
+static void uc_expand_default_options(struct intel_uc *uc)

+{
+   struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
+
+   if (i915->params.enable_guc != -1)
+   return;
+
+   /* Don't enable GuC/HuC on pre-Gen12 */
+   if (INTEL_GEN(i915) < 12) {
+   i915->params.enable_guc = 0;
+   return;
+   }
+
+   /* Don't enable GuC/HuC on older Gen12 platforms */
+   if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) {
+   i915->params.enable_guc = 0;
+   return;
+   }
+
+   /* Default: enable HuC authentication only */
+   i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
+}
+
  /* Reset GuC providing us with fresh state for both GuC and HuC.
   */
  static int __intel_uc_reset_hw(struct intel_uc *uc)
@@ -52,9 +75,6 @@ static void __confirm_options(struct intel_uc *uc)
yesno(intel_uc_wants_guc_submission(uc)),
yesno(intel_uc_wants_huc(uc)));
  
-	if (i915->params.enable_guc == -1)

-   return;
-
if (i915->params.enable_guc == 0) {
GEM_BUG_ON(intel_uc_wants_guc(uc));
GEM_BUG_ON(intel_uc_wants_guc_submission(uc));
@@ -79,8 +99,7 @@ static void __confirm_options(struct intel_uc *uc)
 "Incompatible option enable_guc=%d - %s\n",
 i915->params.enable_guc, "GuC submission is N/A");
  
-	if (i915->params.enable_guc & ~(ENABLE_GUC_SUBMISSION |

- ENABLE_GUC_LOAD_HUC))
+   if (i915->params.enable_guc & ~ENABLE_GUC_MASK)
drm_info(&i915->drm,
 "Incompatible option enable_guc=%d - %s\n",
 i915->params.enable_guc, "undocumented flag");
@@ -88,6 +107,8 @@ static void __confirm_options(struct intel_uc *uc)
  
  void intel_uc_init_early(struct intel_uc *uc)

  {
+   uc_expand_default_options(uc);
+
intel_guc_init_early(&uc->guc);
intel_huc_init_early(&uc->huc);
  
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c

index 602f1a0bc587..67b06fde1225 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -152,16 +152,11 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct 
intel_uc_fw *uc_fw)
uc_fw->path = NULL;
}
}
-
-   /* We don't want to enable GuC/HuC on pre-Gen11 by default */
-   if (i915->params.enable_guc == -1 && p < INTEL_ICELAKE)
-   uc_fw->path = NULL;
  }
  
  static const char *__override_guc_firmware_path(struct drm_i915_private *i915)

  {
-   if (i915->params.enable_guc & (ENABLE_GUC_SUBMISSION |
-  ENABLE_GUC_LOAD_HUC))
+   if (i915->params.enable_guc & ENABLE_GUC_MASK)
return i915->params.guc_firmware_path;
return "";
  }
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 330c03e2b4f7..f031966af5b7 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -32,6 +32,7 @@ struct drm_printer;
  
  #define ENABLE_GUC_SUBMISSION		BIT(0)

  #define ENABLE_GUC_LOAD_HUC   BIT(1)
+#define ENABLE_GUC_MASKGENMASK(1, 0)
  
  /*

   * Invoke param, a function-like macro, for each i915 param, with arguments:

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gen12: Add display render clear color decompression support

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm/i915/gen12: Add display render clear color decompression support
URL   : https://patchwork.freedesktop.org/series/85877/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
89e07f063541 drm/framebuffer: Format modifier for Intel Gen 12 render 
compression with Clear Color
45aadd34aaa8 drm/i915/gem: Add a helper to read data from a GEM object page
-:34: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#34: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.c:388:
+i915_gem_object_read_from_page_kmap(struct drm_i915_gem_object *obj, unsigned 
long offset, int size, void *dst)

-:50: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#50: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.c:404:
+i915_gem_object_read_from_page_iomap(struct drm_i915_gem_object *obj, unsigned 
long offset, int size, void *dst)

-:76: WARNING:TYPO_SPELLING: 'sucess' may be misspelled - perhaps 'success'?
#76: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.c:430:
+ * Returns 0 on sucess, negative error code on failre.
 ^^

-:78: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#78: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.c:432:
+int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, unsigned 
long offset, size_t size, void *dst)

-:118: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#118: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:543:
+int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, unsigned 
long offset, size_t size, void *dst);

total: 0 errors, 5 warnings, 0 checks, 93 lines checked
89044f4fa5e2 drm/i915/tgl: Add Clear Color support for TGL Render Decompression
-:235: WARNING:SIZEOF_ADDRESS: sizeof(& should be avoided
#235: FILE: drivers/gpu/drm/i915/display/intel_display.c:15299:
+
sizeof(&plane_state->ccval),

-:360: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible 
side-effects?
#360: FILE: drivers/gpu/drm/i915/i915_reg.h:7120:
+#define PLANE_CC_VAL(pipe, plane)  \
+   _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))

total: 0 errors, 1 warnings, 1 checks, 280 lines checked


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Re: [Intel-gfx] [BUG] on reboot: bisected to: drm/i915: Shut down displays gracefully on reboot

2021-01-14 Thread Chris Wilson

Quoting Steven Rostedt (2021-01-14 21:32:06)
> On reboot, one of my test boxes now triggers the following warning:

057fe3535eb3 ("drm/i915: Disable RPM wakeref assertions during driver shutdown")
is included with the drm-intel-fixes PR.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gem: split gem_create into own file

2021-01-14 Thread Patchwork

== Series Details ==

Series: series starting with [1/3] drm/i915/gem: split gem_create into own file
URL   : https://patchwork.freedesktop.org/series/85875/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9612 -> Patchwork_19360


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19360/index.html

Known issues


  Here are the changes found in Patchwork_19360 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@query-info:
- fi-tgl-y:   NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19360/fi-tgl-y/igt@amdgpu/amd_ba...@query-info.html

  * igt@vgem_basic@create:
- fi-tgl-y:   [PASS][2] -> [DMESG-WARN][3] ([i915#402])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-tgl-y/igt@vgem_ba...@create.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19360/fi-tgl-y/igt@vgem_ba...@create.html

  
 Possible fixes 

  * igt@vgem_basic@debugfs:
- fi-tgl-y:   [DMESG-WARN][4] ([i915#402]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-tgl-y/igt@vgem_ba...@debugfs.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19360/fi-tgl-y/igt@vgem_ba...@debugfs.html

  
 Warnings 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [DMESG-WARN][6] ([i915#402]) -> [DMESG-WARN][7] 
([i915#1982] / [i915#402])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19360/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (41 -> 38)
--

  Missing(3): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9612 -> Patchwork_19360

  CI-20190529: 20190529
  CI_DRM_9612: 3d921d1ad818c1aabb5b2bd3f0861df99e49be9b @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5959: c5cf0734c4f6c1fa17a6a15b5aa721c3a0b8c494 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19360: d2f1450391581a982d427056f62b5c22199a7e6f @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

d2f145039158 drm/i915/region: convert object_create into object_init
177fa885172b drm/i915/gem: sanity check object size in gem_create
b246ef5eb0cb drm/i915/gem: split gem_create into own file

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19360/index.html
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Re: [Intel-gfx] [BUG] on reboot: bisected to: drm/i915: Shut down displays gracefully on reboot

2021-01-14 Thread Steven Rostedt



[ Forgot to add those on the commit itself ]

-- Steve


On Thu, 14 Jan 2021 16:32:06 -0500
Steven Rostedt  wrote:

> On reboot, one of my test boxes now triggers the following warning:
> 
>  [ cut here ]
>  RPM raw-wakeref not held
>  WARNING: CPU: 4 PID: 1 at drivers/gpu/drm/i915/intel_runtime_pm.h:106 
> gen6_write32+0x1bc/0x2a0 [i915]
>  Modules linked in: ebtable_filter ebtables bridge stp llc ip6t_REJECT 
> nf_reject_ipv6 vsock vmw_vmci xt_state xt_conntrack nf_conntrack 
> nf_defrag_ipv6 nf_defrag_ipv4 ip6table_filter ip6_tables snd_hda_codec_hdmi 
> snd_hda_codec_realtek snd_hda_codec_generic le
> 15 snd_hda_intel snd_intel_dspcfg snd_hda_codec snd_hwdep i2c_algo_bit 
> snd_hda_core snd_seq intel_rapl_msr snd_seq_device intel_rapl_common snd_pcm 
> x86_pkg_temp_thermal intel_powerclamp snd_timer snd coretemp kvm_intel 
> soundcore kvm mei_wdt irqbypass joydev 
> _pmc_bxt hp_wmi wmi_bmof sparse_keymap rfkill iTCO_vendor_support 
> crct10dif_pclmul crc32_pclmul crc32c_intel ghash_clmulni_intel drm_kms_helper 
> i2c_i801 cec drm rapl intel_cstate intel_uncore mei_me i2c_smbus e1000e 
> tpm_infineon wmi serio_raw mei video lpc_i
> 
>  CPU: 4 PID: 1 Comm: systemd-shutdow Not tainted 5.9.0-rc4-test+ #861
>  Hardware name: Hewlett-Packard HP Compaq Pro 6300 SFF/339A, BIOS K01 v03.03 
> 07/14/2016
>  RIP: 0010:gen6_write32+0x1bc/0x2a0 [i915]
>  Code: 5d 82 e0 0f 0b e9 b5 fe ff ff 80 3d 95 6b 22 00 00 0f 85 b2 fe ff ff 
> 48 c7 c7 04 d2 a4 c0 c6 05 81 6b 22 00 01 e8 f6 5c 82 e0 <0f> 0b e9 98 fe ff 
> ff 80 3d 6d 6b 22 00 00 0f 85 95 fe ff ff 48 c7
>  RSP: 0018:b9c1c002fd08 EFLAGS: 00010296
>  RAX: 0018 RBX: 99aec8881010 RCX: 99aeda40
>  RDX:  RSI: a115d9ef RDI: a115d9ef
>  RBP: 00044004 R08: 0001 R09: 
>  R10: 0001 R11: 0001 R12: 
>  R13: 0001 R14:  R15: 
>  FS:  7f91257a9940() GS:99aeda40() knlGS:
>  CS:  0010 DS:  ES:  CR0: 80050033
>  CR2: 7f9126829400 CR3: 0001088f0006 CR4: 001706e0
>  Call Trace:
>   gen3_irq_reset+0x2e/0xd0 [i915]
>   intel_irq_reset+0x59/0x6a0 [i915]
>   intel_runtime_pm_disable_interrupts+0xe/0x30 [i915]
>   i915_driver_shutdown+0x2e/0x40 [i915]
>   pci_device_shutdown+0x34/0x60
>   device_shutdown+0x15d/0x1b3
>   kernel_restart+0xe/0x30
>   __do_sys_reboot+0x1d7/0x210
>   ? vfs_writev+0x9d/0xe0
>   ? syscall_enter_from_user_mode+0x1d/0x70
>   ? trace_hardirqs_on+0x2c/0xe0
>   do_syscall_64+0x33/0x40
>   entry_SYSCALL_64_after_hwframe+0x44/0xa9
>  RIP: 0033:0x7f912675f2d7
>  Code: 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 
> 89 fa be 69 19 12 28 bf ad de e1 fe b8 a9 00 00 00 0f 05 <48> 3d 00 f0 ff ff 
> 77 01 c3 48 8b 15 81 8b 0c 00 f7 d8 64 89 02 b8
>  RSP: 002b:7ffeca28e148 EFLAGS: 0206 ORIG_RAX: 00a9
>  RAX: ffda RBX:  RCX: 7f912675f2d7
>  RDX: 01234567 RSI: 28121969 RDI: fee1dead
>  RBP: 7ffeca28e3d0 R08: 000a R09: 
>  R10: 0232 R11: 0206 R12: 0001
>  R13:  R14:  R15: 7ffeca28e4b8
>  ---[ end trace 2ed17eabd3ab6938 ]---
>  [ cut here ]
> 
> The bisect came to this commit:
> 
>   fe0f1e3bfdfeb53e18f1206aea4f40b9bd1f291c
>   ("drm/i915: Shut down displays gracefully on reboot")
> 
> Which makes sense, as it happens on shutdown.
> 
> -- Steve

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[Intel-gfx] [BUG] on reboot: bisected to: drm/i915: Shut down displays gracefully on reboot

2021-01-14 Thread Steven Rostedt

On reboot, one of my test boxes now triggers the following warning:

 [ cut here ]
 RPM raw-wakeref not held
 WARNING: CPU: 4 PID: 1 at drivers/gpu/drm/i915/intel_runtime_pm.h:106 
gen6_write32+0x1bc/0x2a0 [i915]
 Modules linked in: ebtable_filter ebtables bridge stp llc ip6t_REJECT 
nf_reject_ipv6 vsock vmw_vmci xt_state xt_conntrack nf_conntrack nf_defrag_ipv6 
nf_defrag_ipv4 ip6table_filter ip6_tables snd_hda_codec_hdmi 
snd_hda_codec_realtek snd_hda_codec_generic le
15 snd_hda_intel snd_intel_dspcfg snd_hda_codec snd_hwdep i2c_algo_bit 
snd_hda_core snd_seq intel_rapl_msr snd_seq_device intel_rapl_common snd_pcm 
x86_pkg_temp_thermal intel_powerclamp snd_timer snd coretemp kvm_intel 
soundcore kvm mei_wdt irqbypass joydev 
_pmc_bxt hp_wmi wmi_bmof sparse_keymap rfkill iTCO_vendor_support 
crct10dif_pclmul crc32_pclmul crc32c_intel ghash_clmulni_intel drm_kms_helper 
i2c_i801 cec drm rapl intel_cstate intel_uncore mei_me i2c_smbus e1000e 
tpm_infineon wmi serio_raw mei video lpc_i

 CPU: 4 PID: 1 Comm: systemd-shutdow Not tainted 5.9.0-rc4-test+ #861
 Hardware name: Hewlett-Packard HP Compaq Pro 6300 SFF/339A, BIOS K01 v03.03 
07/14/2016
 RIP: 0010:gen6_write32+0x1bc/0x2a0 [i915]
 Code: 5d 82 e0 0f 0b e9 b5 fe ff ff 80 3d 95 6b 22 00 00 0f 85 b2 fe ff ff 48 
c7 c7 04 d2 a4 c0 c6 05 81 6b 22 00 01 e8 f6 5c 82 e0 <0f> 0b e9 98 fe ff ff 80 
3d 6d 6b 22 00 00 0f 85 95 fe ff ff 48 c7
 RSP: 0018:b9c1c002fd08 EFLAGS: 00010296
 RAX: 0018 RBX: 99aec8881010 RCX: 99aeda40
 RDX:  RSI: a115d9ef RDI: a115d9ef
 RBP: 00044004 R08: 0001 R09: 
 R10: 0001 R11: 0001 R12: 
 R13: 0001 R14:  R15: 
 FS:  7f91257a9940() GS:99aeda40() knlGS:
 CS:  0010 DS:  ES:  CR0: 80050033
 CR2: 7f9126829400 CR3: 0001088f0006 CR4: 001706e0
 Call Trace:
  gen3_irq_reset+0x2e/0xd0 [i915]
  intel_irq_reset+0x59/0x6a0 [i915]
  intel_runtime_pm_disable_interrupts+0xe/0x30 [i915]
  i915_driver_shutdown+0x2e/0x40 [i915]
  pci_device_shutdown+0x34/0x60
  device_shutdown+0x15d/0x1b3
  kernel_restart+0xe/0x30
  __do_sys_reboot+0x1d7/0x210
  ? vfs_writev+0x9d/0xe0
  ? syscall_enter_from_user_mode+0x1d/0x70
  ? trace_hardirqs_on+0x2c/0xe0
  do_syscall_64+0x33/0x40
  entry_SYSCALL_64_after_hwframe+0x44/0xa9
 RIP: 0033:0x7f912675f2d7
 Code: 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 89 
fa be 69 19 12 28 bf ad de e1 fe b8 a9 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 01 
c3 48 8b 15 81 8b 0c 00 f7 d8 64 89 02 b8
 RSP: 002b:7ffeca28e148 EFLAGS: 0206 ORIG_RAX: 00a9
 RAX: ffda RBX:  RCX: 7f912675f2d7
 RDX: 01234567 RSI: 28121969 RDI: fee1dead
 RBP: 7ffeca28e3d0 R08: 000a R09: 
 R10: 0232 R11: 0206 R12: 0001
 R13:  R14:  R15: 7ffeca28e4b8
 ---[ end trace 2ed17eabd3ab6938 ]---
 [ cut here ]

The bisect came to this commit:

  fe0f1e3bfdfeb53e18f1206aea4f40b9bd1f291c
  ("drm/i915: Shut down displays gracefully on reboot")

Which makes sense, as it happens on shutdown.

-- Steve
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Re: [Intel-gfx] [PATCH v7 2/3] drm/i915/gem: Add a helper to read data from a GEM object page

2021-01-14 Thread Chris Wilson

Quoting Imre Deak (2021-01-14 20:13:13)
> Add a simple helper to read data with the CPU from the page of a GEM
> object. Do the read either via a kmap if the object has struct pages
> or an iomap otherwise. This is needed by the next patch, reading a u64
> value from the object (w/o requiring the obj to be mapped to the GPU).
> 
> Suggested by Chris.
> 
> Cc: Chris Wilson 
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_object.c | 75 ++
>  drivers/gpu/drm/i915/gem/i915_gem_object.h |  2 +
>  2 files changed, 77 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> index 00d24000b5e8..010f8d735e40 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> @@ -32,6 +32,7 @@
>  #include "i915_gem_mman.h"
>  #include "i915_gem_object.h"
>  #include "i915_globals.h"
> +#include "i915_memcpy.h"
>  #include "i915_trace.h"
>  
>  static struct i915_global_object {
> @@ -383,6 +384,80 @@ void __i915_gem_object_invalidate_frontbuffer(struct 
> drm_i915_gem_object *obj,
> }
>  }
>  
> +static void
> +i915_gem_object_read_from_page_kmap(struct drm_i915_gem_object *obj, 
> unsigned long offset, int size, void *dst)
[noted later about parameter order + types]

> +{
> +   const void *src_map;
> +   const void *src_ptr;
> +
> +   src_map = kmap_atomic(i915_gem_object_get_page(obj, offset >> 
> PAGE_SHIFT));
> +
> +   src_ptr = src_map + offset_in_page(offset);
> +   if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))
> +   drm_clflush_virt_range((void *)src_ptr, size);
> +   memcpy(dst, src_ptr, size);
> +
> +   kunmap_atomic((void *)src_map);

Live without marking the src pointers as const*.

> +}
> +
> +static void
> +i915_gem_object_read_from_page_iomap(struct drm_i915_gem_object *obj, 
> unsigned long offset, int size, void *dst)
> +{
> +   const void __iomem *src_map;
> +   const void __iomem *src_ptr;
> +
> +   src_map = io_mapping_map_wc(&obj->mm.region->iomap,
> +   i915_gem_object_get_dma_address(obj, 
> offset >> PAGE_SHIFT),
> +   PAGE_SIZE);
> +
> +   src_ptr = src_map + offset_in_page(offset);
> +   if (!i915_memcpy_from_wc(dst, src_ptr, size))
> +   memcpy(dst, src_ptr, size);

Sparse will complain about the mixed __iomem/regular pointers. So you
might as well use memcpy_from_io() here. Unfortunately memcpy_from_wc
needs explicit casting. A task for rainy day is massaging
i915_memcpy_from_wc() to be sparse clean for iomem.

> +
> +   io_mapping_unmap((void __iomem *)src_map);
> +}
> +
> +/**
> + * i915_gem_object_read_from_page - read data from the page of a GEM object
> + * @obj: GEM object to read from
> + * @offset: offset within the object
> + * @size: size to read
> + * @dst: buffer to store the read data
> + *
> + * Reads data from @obj after syncing against any pending GPU writes on it.
> + * The requested region to read from can't cross a page boundary.
> + *
> + * Returns 0 on sucess, negative error code on failre.
> + */
> +int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, unsigned 
> long offset, size_t size, void *dst)

offset -> u64
size_t size? meh, it must only be an int

We use the convention of 
read_from_page(obj, offset_into_obj,
   dst, length_of_read_into_dst)
for parameter ordering.

> +{
> +   int ret;
> +
> +   WARN_ON(offset + size > obj->base.size ||
> +   offset_in_page(offset) + size > PAGE_SIZE);

This is only from internal users, so GEM_BUG_ON() (or you would use
if(GEM_WARN_ON) return -EINVAL).

GEM_BUG_ON(offset > obj->base.size);
GEM_BUG_ON(offset_in_page(offset) > PAGE_SIZE - size);
(since size is a multiple of pages)

> +
> +   i915_gem_object_lock(obj, NULL);
> +
> +   ret = i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT);
> +   if (ret)
> +   goto unlock;

Is there an absolute requirement for this read to be serialised against
everything? If not, let the caller decide if they need some sort of
flush/wait before reading, and the lock can be removed.

In any case, always prefer interruptible waits and if there's a callpath
that absolutely must not be interruptible, pass that information along
the arguments.

> +   ret = i915_gem_object_pin_pages(obj);

So at present one would not need to lock the object for the pages.
And then we would not need to hold the lock across the read as we hold
the pages.

> +   if (ret)
> +   goto unlock;
> +
> +   if (i915_gem_object_has_struct_page(obj))
> +   i915_gem_object_read_from_page_kmap(obj, offset, size, dst);
> +   else
else if (i915_gem_object_is_iomem(obj))
> +   i915_gem_object_read_from_page_iomap(obj, offset, size, dst);
else
ret = -ENODEV;

But on the whole, this works and is

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/gem: split gem_create into own file

2021-01-14 Thread Patchwork

== Series Details ==

Series: series starting with [1/3] drm/i915/gem: split gem_create into own file
URL   : https://patchwork.freedesktop.org/series/85875/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/gem/i915_gem_stolen.c:624:5: warning: symbol 
'__i915_gem_object_create_stolen' was not declared. Should it be static?
+drivers/gpu/drm/i915/gem/i915_gem_stolen.c:649:5: warning: symbol 
'_i915_gem_object_stolen_init' was not declared. Should it be static?


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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gem: split gem_create into own file

2021-01-14 Thread Patchwork

== Series Details ==

Series: series starting with [1/3] drm/i915/gem: split gem_create into own file
URL   : https://patchwork.freedesktop.org/series/85875/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b246ef5eb0cb drm/i915/gem: split gem_create into own file
-:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#25: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 226 lines checked
177fa885172b drm/i915/gem: sanity check object size in gem_create
d2f145039158 drm/i915/region: convert object_create into object_init


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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/5] drm/i915: Mark up protected uses of 'i915_request_completed'

2021-01-14 Thread Patchwork

== Series Details ==

Series: series starting with [CI,1/5] drm/i915: Mark up protected uses of 
'i915_request_completed'
URL   : https://patchwork.freedesktop.org/series/85871/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9612 -> Patchwork_19359


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19359/index.html

Known issues


  Here are the changes found in Patchwork_19359 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@query-info:
- fi-tgl-y:   NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19359/fi-tgl-y/igt@amdgpu/amd_ba...@query-info.html

  * igt@fbdev@read:
- fi-tgl-y:   [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +2 similar 
issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-tgl-y/igt@fb...@read.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19359/fi-tgl-y/igt@fb...@read.html

  * igt@gem_exec_suspend@basic-s0:
- fi-snb-2600:[PASS][4] -> [DMESG-WARN][5] ([i915#2772])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-snb-2600/igt@gem_exec_susp...@basic-s0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19359/fi-snb-2600/igt@gem_exec_susp...@basic-s0.html

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-7500u:   [PASS][6] -> [DMESG-WARN][7] ([i915#2605])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-kbl-7500u/igt@i915_pm_...@module-reload.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19359/fi-kbl-7500u/igt@i915_pm_...@module-reload.html

  * igt@runner@aborted:
- fi-snb-2600:NOTRUN -> [FAIL][8] ([i915#698])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19359/fi-snb-2600/igt@run...@aborted.html

  
 Possible fixes 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +2 similar 
issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19359/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
  [i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#698]: https://gitlab.freedesktop.org/drm/intel/issues/698


Participating hosts (41 -> 37)
--

  Missing(4): fi-byt-j1900 fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9612 -> Patchwork_19359

  CI-20190529: 20190529
  CI_DRM_9612: 3d921d1ad818c1aabb5b2bd3f0861df99e49be9b @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5959: c5cf0734c4f6c1fa17a6a15b5aa721c3a0b8c494 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19359: 9c8dc1c949fc7275c07e0e66d941626d552cd192 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

9c8dc1c949fc drm/i915: Reduce test_and_set_bit to set_bit in 
i915_request_submit()
c86145af0baa drm/i915/gem: Reduce ctx->engines_mutex for get_engines()
f2037c8f347c drm/i915/gem: Reduce ctx->engine_mutex for reading the clone source
abefdc5fe6d9 drm/i915: Drop i915_request.lock serialisation around await_start
543d06eaf73f drm/i915: Mark up protected uses of 'i915_request_completed'

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19359/index.html
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/region: convert object_create into object_init

2021-01-14 Thread Chris Wilson

Quoting Matthew Auld (2021-01-14 18:24:02)
> Give more flexibility to the caller, if they already have an allocated
> object, in case they wish to apply some transformation to the object
> prior to handing it over to the region specific initialisation step,
> like in gem_create_ext where we would like to first apply the extensions
> to the object.

I notice that we need to include userptr and the mock objects in
INTEL_MEMORY_SYSTEM for better bookkeeping.
 
> Signed-off-by: Matthew Auld 
Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH 2/3] drm/i915/gem: sanity check object size in gem_create

2021-01-14 Thread Chris Wilson

Quoting Matthew Auld (2021-01-14 18:24:01)
> Depending on the regions min_page_size we might need to adjust the
> object size, ensure this matches our expectations.
> 
> Suggested-by: Chris Wilson 
> Signed-off-by: Matthew Auld 
Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH 1/3] drm/i915/gem: split gem_create into own file

2021-01-14 Thread Chris Wilson

Quoting Matthew Auld (2021-01-14 18:24:00)
> In preparation for gem_create_ext break out the gem_create uAPI, so that
> we don't clutter i915_gem.c once we start adding various extensions
> 
> Signed-off-by: Matthew Auld 
Reviewed-by: Chris Wilson 
-Chris
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[Intel-gfx] [PATCH 7/7] drm/i915: Introduce g4x_dp.c

2021-01-14 Thread Ville Syrjala

From: Ville Syrjälä 

Move the g4x+ DP code into a new file. This will leave mostly
platform agnostic code in intel_dp.c. Well, the misplaced phy
test stuff pretty much ruins that, but let's squint real hard
for now.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/Makefile |1 +
 drivers/gpu/drm/i915/display/g4x_dp.c | 1431 +
 drivers/gpu/drm/i915/display/g4x_dp.h |   36 +
 drivers/gpu/drm/i915/display/intel_display.c  |1 +
 drivers/gpu/drm/i915/display/intel_dp.c   | 1418 +---
 drivers/gpu/drm/i915/display/intel_dp.h   |   11 -
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |2 +-
 drivers/gpu/drm/i915/display/intel_pps.c  |1 +
 8 files changed, 1472 insertions(+), 1429 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/g4x_dp.c
 create mode 100644 drivers/gpu/drm/i915/display/g4x_dp.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 00d4dd5ecdb7..34916fac4643 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -235,6 +235,7 @@ i915-y += \
display/dvo_ns2501.o \
display/dvo_sil164.o \
display/dvo_tfp410.o \
+   display/g4x_dp.o \
display/icl_dsi.o \
display/intel_crt.o \
display/intel_ddi.o \
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c 
b/drivers/gpu/drm/i915/display/g4x_dp.c
new file mode 100644
index ..2ca1d0482374
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -0,0 +1,1431 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "g4x_dp.h"
+#include "intel_audio.h"
+#include "intel_connector.h"
+#include "intel_display_types.h"
+#include "intel_dp.h"
+#include "intel_dp_link_training.h"
+#include "intel_dpio_phy.h"
+#include "intel_fifo_underrun.h"
+#include "intel_hdmi.h"
+#include "intel_hotplug.h"
+#include "intel_panel.h"
+#include "intel_pps.h"
+#include "intel_sideband.h"
+
+struct dp_link_dpll {
+   int clock;
+   struct dpll dpll;
+};
+
+static const struct dp_link_dpll g4x_dpll[] = {
+   { 162000,
+   { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
+   { 27,
+   { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
+};
+
+static const struct dp_link_dpll pch_dpll[] = {
+   { 162000,
+   { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
+   { 27,
+   { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
+};
+
+static const struct dp_link_dpll vlv_dpll[] = {
+   { 162000,
+   { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
+   { 27,
+   { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
+};
+
+/*
+ * CHV supports eDP 1.4 that have  more link rates.
+ * Below only provides the fixed rate but exclude variable rate.
+ */
+static const struct dp_link_dpll chv_dpll[] = {
+   /*
+* CHV requires to program fractional division for m2.
+* m2 is stored in fixed point format using formula below
+* (m2_int << 22) | m2_fraction
+*/
+   { 162000,   /* m2_int = 32, m2_fraction = 1677722 */
+   { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x81a } },
+   { 27,   /* m2_int = 27, m2_fraction = 0 */
+   { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c0 } },
+};
+
+const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
+{
+   return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll;
+}
+
+void intel_dp_set_clock(struct intel_encoder *encoder,
+   struct intel_crtc_state *pipe_config)
+{
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   const struct dp_link_dpll *divisor = NULL;
+   int i, count = 0;
+
+   if (IS_G4X(dev_priv)) {
+   divisor = g4x_dpll;
+   count = ARRAY_SIZE(g4x_dpll);
+   } else if (HAS_PCH_SPLIT(dev_priv)) {
+   divisor = pch_dpll;
+   count = ARRAY_SIZE(pch_dpll);
+   } else if (IS_CHERRYVIEW(dev_priv)) {
+   divisor = chv_dpll;
+   count = ARRAY_SIZE(chv_dpll);
+   } else if (IS_VALLEYVIEW(dev_priv)) {
+   divisor = vlv_dpll;
+   count = ARRAY_SIZE(vlv_dpll);
+   }
+
+   if (divisor && count) {
+   for (i = 0; i < count; i++) {
+   if (pipe_config->port_clock == divisor[i].clock) {
+   pipe_config->dpll = divisor[i].dpll;
+   pipe_config->clock_set = true;
+   break;
+   }
+   }
+   }
+}
+
+static void intel_dp_prepare(struct intel_encoder *encoder,
+const struct intel_crtc_state *pipe_config)
+{
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+   enum

[Intel-gfx] [PATCH 6/7] drm/i915: Fix the PHY compliance test vs. hotplug mishap

2021-01-14 Thread Ville Syrjala

From: Ville Syrjälä 

I accidentally added the compliance test hacks only to
intel_dp_hotplug() which doesn't even get used on any DDI
platform. Put the same crap into intel_ddi_hotplug().

Cc: Imre Deak 
Fixes: 193af12cd681 ("drm/i915: Shove the PHY test into the hotplug work")
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 8 
 drivers/gpu/drm/i915/display/intel_dp.c  | 2 +-
 drivers/gpu/drm/i915/display/intel_dp.h  | 1 +
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4443a4ab722f..d7df1828a740 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5204,12 +5204,20 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+   struct intel_dp *intel_dp = &dig_port->dp;
enum phy phy = intel_port_to_phy(i915, encoder->port);
bool is_tc = intel_phy_is_tc(i915, phy);
struct drm_modeset_acquire_ctx ctx;
enum intel_hotplug_state state;
int ret;
 
+   if (intel_dp->compliance.test_active &&
+   intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
+   intel_dp_phy_test(encoder);
+   /* just do the PHY test and nothing else */
+   return INTEL_HOTPLUG_UNCHANGED;
+   }
+
state = intel_encoder_hotplug(encoder, connector);
 
drm_modeset_acquire_init(&ctx, 0);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 30713816bf9d..349647f6bbb9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5522,7 +5522,7 @@ static int intel_dp_do_phy_test(struct intel_encoder 
*encoder,
return 0;
 }
 
-static void intel_dp_phy_test(struct intel_encoder *encoder)
+void intel_dp_phy_test(struct intel_encoder *encoder)
 {
struct drm_modeset_acquire_ctx ctx;
int ret;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h 
b/drivers/gpu/drm/i915/display/intel_dp.h
index 6a2c759ad46f..d42860ef4521 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -137,5 +137,6 @@ const struct dpll *vlv_get_dpll(struct drm_i915_private 
*i915);
 void intel_dp_check_frl_training(struct intel_dp *intel_dp);
 void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
 const struct intel_crtc_state *crtc_state);
+void intel_dp_phy_test(struct intel_encoder *encoder);
 
 #endif /* __INTEL_DP_H__ */
-- 
2.26.2

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[Intel-gfx] [PATCH 5/7] drm/i915: Split intel_ddi_encoder_reset() from intel_dp_encoder_reset()

2021-01-14 Thread Ville Syrjala

From: Ville Syrjälä 

Most of intel_dp_encoder_reset() is for pre-ddi platforms.
Make a clean split.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 11 ++-
 drivers/gpu/drm/i915/display/intel_dp.c  |  5 ++---
 drivers/gpu/drm/i915/display/intel_dp.h  |  1 -
 3 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index d714e8b34d52..4443a4ab722f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5045,8 +5045,17 @@ static void intel_ddi_encoder_destroy(struct drm_encoder 
*encoder)
kfree(dig_port);
 }
 
+static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
+{
+   struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
+
+   intel_dp->reset_link_params = true;
+
+   intel_pps_encoder_reset(intel_dp);
+}
+
 static const struct drm_encoder_funcs intel_ddi_funcs = {
-   .reset = intel_dp_encoder_reset,
+   .reset = intel_ddi_encoder_reset,
.destroy = intel_ddi_encoder_destroy,
 };
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1df00c4980bf..30713816bf9d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6319,13 +6319,12 @@ static enum pipe vlv_active_pipe(struct intel_dp 
*intel_dp)
return INVALID_PIPE;
 }
 
-void intel_dp_encoder_reset(struct drm_encoder *encoder)
+static void intel_dp_encoder_reset(struct drm_encoder *encoder)
 {
struct drm_i915_private *dev_priv = to_i915(encoder->dev);
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
 
-   if (!HAS_DDI(dev_priv))
-   intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
+   intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
 
intel_dp->reset_link_params = true;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h 
b/drivers/gpu/drm/i915/display/intel_dp.h
index 9508fa79d9be..6a2c759ad46f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -56,7 +56,6 @@ void intel_dp_configure_protocol_converter(struct intel_dp 
*intel_dp,
 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
   const struct intel_crtc_state 
*crtc_state,
   bool enable);
-void intel_dp_encoder_reset(struct drm_encoder *encoder);
 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder);
 void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
-- 
2.26.2

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[Intel-gfx] [PATCH 4/7] drm/i915: Relocate intel_dp_program_link_training_pattern()

2021-01-14 Thread Ville Syrjala

From: Ville Syrjälä 

intel_dp_program_link_training_pattern() clearly belongs in
intel_dp_link_training.c. Make it so.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dp.c   | 33 ---
 drivers/gpu/drm/i915/display/intel_dp.h   |  4 ---
 .../drm/i915/display/intel_dp_link_training.c | 33 +++
 .../drm/i915/display/intel_dp_link_training.h |  3 ++
 4 files changed, 36 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2b276549cecd..1df00c4980bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4031,39 +4031,6 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
intel_de_posting_read(dev_priv, intel_dp->output_reg);
 }
 
-static char dp_training_pattern_name(u8 train_pat)
-{
-   switch (train_pat) {
-   case DP_TRAINING_PATTERN_1:
-   case DP_TRAINING_PATTERN_2:
-   case DP_TRAINING_PATTERN_3:
-   return '0' + train_pat;
-   case DP_TRAINING_PATTERN_4:
-   return '4';
-   default:
-   MISSING_CASE(train_pat);
-   return '?';
-   }
-}
-
-void
-intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
-  const struct intel_crtc_state 
*crtc_state,
-  u8 dp_train_pat)
-{
-   struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
-   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-   u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
-
-   if (train_pat != DP_TRAINING_PATTERN_DISABLE)
-   drm_dbg_kms(&dev_priv->drm,
-   "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
-   encoder->base.base.id, encoder->base.name,
-   dp_training_pattern_name(train_pat));
-
-   intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
-}
-
 static void
 intel_dp_link_down(struct intel_encoder *encoder,
   const struct intel_crtc_state *old_crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h 
b/drivers/gpu/drm/i915/display/intel_dp.h
index abf834729309..9508fa79d9be 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -88,10 +88,6 @@ void intel_edp_drrs_invalidate(struct drm_i915_private 
*dev_priv,
 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
  unsigned int frontbuffer_bits);
 
-void
-intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
-  const struct intel_crtc_state 
*crtc_state,
-  u8 dp_train_pat);
 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
   u8 *link_bw, u8 *rate_select);
 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index d8c6d7054d11..f6474b45f8ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -334,6 +334,39 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
 }
 
+static char dp_training_pattern_name(u8 train_pat)
+{
+   switch (train_pat) {
+   case DP_TRAINING_PATTERN_1:
+   case DP_TRAINING_PATTERN_2:
+   case DP_TRAINING_PATTERN_3:
+   return '0' + train_pat;
+   case DP_TRAINING_PATTERN_4:
+   return '4';
+   default:
+   MISSING_CASE(train_pat);
+   return '?';
+   }
+}
+
+void
+intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
+  const struct intel_crtc_state 
*crtc_state,
+  u8 dp_train_pat)
+{
+   struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
+
+   if (train_pat != DP_TRAINING_PATTERN_DISABLE)
+   drm_dbg_kms(&dev_priv->drm,
+   "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
+   encoder->base.base.id, encoder->base.name,
+   dp_training_pattern_name(train_pat));
+
+   intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
+}
+
 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
enum drm_dp_phy dp_phy)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h 
b/drivers/gpu/drm/i915/display/intel_dp_link_train

[Intel-gfx] [PATCH 3/7] drm/i915: Remove dead signal level debugs

2021-01-14 Thread Ville Syrjala

From: Ville Syrjälä 

If we ever get here with bogus signal levels we've messed
up somewhere earlier. Just use MISSIN_CASE().

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 10930884ce42..2b276549cecd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3955,8 +3955,7 @@ static u32 snb_cpu_edp_signal_levels(u8 train_set)
case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
default:
-   DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
- "0x%x\n", signal_levels);
+   MISSING_CASE(signal_levels);
return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
}
 }
@@ -4007,8 +4006,7 @@ static u32 ivb_cpu_edp_signal_levels(u8 train_set)
return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
 
default:
-   DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
- "0x%x\n", signal_levels);
+   MISSING_CASE(signal_levels);
return EDP_LINK_TRAIN_500MV_0DB_IVB;
}
 }
-- 
2.26.2

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[Intel-gfx] [PATCH 2/7] drm/i915: Remove dead TPS3->TPS2 fallback code

2021-01-14 Thread Ville Syrjala

From: Ville Syrjälä 

If we ever get here with TPS3 then intel_dp_training_pattern()
is just broken. Replace the creful fallback with just
MISSING_CASE().

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 16 ++--
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6ed93cbef828..10930884ce42 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3148,11 +3148,9 @@ cpt_set_link_train(struct intel_dp *intel_dp,
case DP_TRAINING_PATTERN_2:
*DP |= DP_LINK_TRAIN_PAT_2_CPT;
break;
-   case DP_TRAINING_PATTERN_3:
-   drm_dbg_kms(&dev_priv->drm,
-   "TPS3 not supported, using TPS2 instead\n");
-   *DP |= DP_LINK_TRAIN_PAT_2_CPT;
-   break;
+   default:
+   MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
+   return;
}
 
intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
@@ -3453,11 +3451,9 @@ g4x_set_link_train(struct intel_dp *intel_dp,
case DP_TRAINING_PATTERN_2:
*DP |= DP_LINK_TRAIN_PAT_2;
break;
-   case DP_TRAINING_PATTERN_3:
-   drm_dbg_kms(&dev_priv->drm,
-   "TPS3 not supported, using TPS2 instead\n");
-   *DP |= DP_LINK_TRAIN_PAT_2;
-   break;
+   default:
+   MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
+   return;
}
 
intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
-- 
2.26.2

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[Intel-gfx] [PATCH 1/7] drm/i915: Fix the training pattern debug print

2021-01-14 Thread Ville Syrjala

From: Ville Syrjälä 

Currently we claim to use TPS7 when using TPS4. That is just
confusing, so let's fix the debug print.

And while we're touching this let's add the customary
encoder id/name as well.

v2: Add MISSING_CASE() (Manasi)

Reviewed-by: Manasi Navare 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 27 -
 1 file changed, 22 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index ec94ebdaf7b8..6ed93cbef828 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4037,18 +4037,35 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
intel_de_posting_read(dev_priv, intel_dp->output_reg);
 }
 
+static char dp_training_pattern_name(u8 train_pat)
+{
+   switch (train_pat) {
+   case DP_TRAINING_PATTERN_1:
+   case DP_TRAINING_PATTERN_2:
+   case DP_TRAINING_PATTERN_3:
+   return '0' + train_pat;
+   case DP_TRAINING_PATTERN_4:
+   return '4';
+   default:
+   MISSING_CASE(train_pat);
+   return '?';
+   }
+}
+
 void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
   const struct intel_crtc_state 
*crtc_state,
   u8 dp_train_pat)
 {
-   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+   struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
 
-   if ((intel_dp_training_pattern_symbol(dp_train_pat)) !=
-   DP_TRAINING_PATTERN_DISABLE)
+   if (train_pat != DP_TRAINING_PATTERN_DISABLE)
drm_dbg_kms(&dev_priv->drm,
-   "Using DP training pattern TPS%d\n",
-   intel_dp_training_pattern_symbol(dp_train_pat));
+   "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
+   encoder->base.base.id, encoder->base.name,
+   dp_training_pattern_name(train_pat));
 
intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
 }
-- 
2.26.2

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[Intel-gfx] [PATCH 0/7] drm/i915: Shuffle DP code around

2021-01-14 Thread Ville Syrjala

From: Ville Syrjälä 

In keeping with current trends, let's try to clean up
intel_dp.c a bit.

Ville Syrjälä (7):
  drm/i915: Fix the training pattern debug print
  drm/i915: Remove dead TPS3->TPS2 fallback code
  drm/i915: Remove dead signal level debugs
  drm/i915: Relocate intel_dp_program_link_training_pattern()
  drm/i915: Split intel_ddi_encoder_reset() from
intel_dp_encoder_reset()
  drm/i915: Fix the PHY compliance test vs. hotplug mishap
  drm/i915: Introduce g4x_dp.c

 drivers/gpu/drm/i915/Makefile |1 +
 drivers/gpu/drm/i915/display/g4x_dp.c | 1431 
 drivers/gpu/drm/i915/display/g4x_dp.h |   36 +
 drivers/gpu/drm/i915/display/intel_ddi.c  |   19 +-
 drivers/gpu/drm/i915/display/intel_display.c  |1 +
 drivers/gpu/drm/i915/display/intel_dp.c   | 1443 +
 drivers/gpu/drm/i915/display/intel_dp.h   |   17 +-
 .../drm/i915/display/intel_dp_link_training.c |   33 +
 .../drm/i915/display/intel_dp_link_training.h |3 +
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |2 +-
 drivers/gpu/drm/i915/display/intel_pps.c  |1 +
 11 files changed, 1528 insertions(+), 1459 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/g4x_dp.c
 create mode 100644 drivers/gpu/drm/i915/display/g4x_dp.h

-- 
2.26.2

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/5] drm/i915: Mark up protected uses of 'i915_request_completed'

2021-01-14 Thread Patchwork

== Series Details ==

Series: series starting with [CI,1/5] drm/i915: Mark up protected uses of 
'i915_request_completed'
URL   : https://patchwork.freedesktop.org/series/85871/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1328:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:869:16: warning: trying to copy expression type 31


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm-buf: Add debug option (rev2)

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm-buf: Add debug option (rev2)
URL   : https://patchwork.freedesktop.org/series/85813/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9612 -> Patchwork_19358


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19358/index.html

Known issues


  Here are the changes found in Patchwork_19358 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-compute:
- fi-tgl-y:   NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575]) +4 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19358/fi-tgl-y/igt@amdgpu/amd_ba...@cs-compute.html

  * igt@fbdev@read:
- fi-tgl-y:   [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +2 similar 
issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-tgl-y/igt@fb...@read.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19358/fi-tgl-y/igt@fb...@read.html

  * igt@i915_pm_rpm@module-reload:
- fi-byt-j1900:   [PASS][4] -> [INCOMPLETE][5] ([i915#142] / 
[i915#2405])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-byt-j1900/igt@i915_pm_...@module-reload.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19358/fi-byt-j1900/igt@i915_pm_...@module-reload.html

  * igt@runner@aborted:
- fi-byt-j1900:   NOTRUN -> [FAIL][6] ([i915#1814] / [i915#2505])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19358/fi-byt-j1900/igt@run...@aborted.html

  
 Possible fixes 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9612/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19358/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
  [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (41 -> 38)
--

  Missing(3): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9612 -> Patchwork_19358

  CI-20190529: 20190529
  CI_DRM_9612: 3d921d1ad818c1aabb5b2bd3f0861df99e49be9b @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5959: c5cf0734c4f6c1fa17a6a15b5aa721c3a0b8c494 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19358: 9406d53d49b1616e1059ab7edac199cc11ffe79f @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

9406d53d49b1 drm-buf: Add debug option

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19358/index.html
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[Intel-gfx] [PATCH v7 3/3] drm/i915/tgl: Add Clear Color support for TGL Render Decompression

2021-01-14 Thread Imre Deak

From: Radhakrishna Sripada 

Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.

v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
plane config(Matt). Fix Lookup error.
v3: Fix the panic while running kms_cube
v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
v5: Fix typos and wrap comments(Matt)
v6:
- Use format block descriptors to get the subsampling calculations for
  the CCS surface right.
- Use helpers to convert between main and CCS surfaces.
- Prevent coordinate checks for the CC surface.
- Simplify reading CC value from surface map, add description of CC val
  layout.
- Remove redundant ccval variable from skl_program_plane().
v7:
- Move the CC value readout after syncing against any GPU write on the
  FB obj (Nanley, Chris)
- Make sure the CC value readout works on platforms w/o struct pages
  (dGFX) and other non-coherent platforms wrt. CPU reads (none atm).
  (Chris)

Cc: Dhinakaran Pandiyan 
Cc: Ville Syrjala 
Cc: Shashank Sharma 
Cc: Rafael Antognolli 
Cc: Nanley G Chery 
Cc: Chris Wilson 
Reviewed-by: Matt Roper  (v5)
Signed-off-by: Radhakrishna Sripada 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_display.c  | 101 +-
 .../drm/i915/display/intel_display_types.h|   3 +
 drivers/gpu/drm/i915/display/intel_sprite.c   |  10 +-
 drivers/gpu/drm/i915/i915_reg.h   |   9 ++
 4 files changed, 117 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 66990e48c0d4..f1b4ae451fa9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -58,6 +58,8 @@
 #include "display/intel_tv.h"
 #include "display/intel_vdsc.h"
 
+#include "gem/i915_gem_object.h"
+
 #include "gt/intel_rps.h"
 
 #include "i915_drv.h"
@@ -1906,8 +1908,8 @@ static bool is_ccs_plane(const struct drm_framebuffer 
*fb, int plane)
 static bool is_gen12_ccs_modifier(u64 modifier)
 {
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+  modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
   modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
-
 }
 
 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
@@ -1915,6 +1917,12 @@ static bool is_gen12_ccs_plane(const struct 
drm_framebuffer *fb, int plane)
return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
 }
 
+static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
+{
+   return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
+  plane == 2;
+}
+
 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
 {
if (is_ccs_modifier(fb->modifier))
@@ -1936,6 +1944,9 @@ static int ccs_to_main_plane(const struct drm_framebuffer 
*fb, int ccs_plane)
drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
ccs_plane < fb->format->num_planes / 2);
 
+   if (is_gen12_ccs_cc_plane(fb, ccs_plane))
+   return 0;
+
return ccs_plane - fb->format->num_planes / 2;
 }
 
@@ -1986,6 +1997,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, 
int color_plane)
return 128;
fallthrough;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+   case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
if (is_ccs_plane(fb, color_plane))
return 64;
@@ -2142,6 +2154,7 @@ static unsigned int intel_surf_alignment(const struct 
drm_framebuffer *fb,
return intel_tile_row_size(fb, color_plane);
fallthrough;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+   case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2546,6 +2559,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 
fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+   case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return I915_TILING_Y;
default:
@@ -2624,6 +2638,25 @@ static const struct drm_format_info gen12_ccs_formats[] 
= {
  .hsub = 2, .vsub = 2, .is_yuv = true },
 };
 
+/*
+ * Same as gen12_ccs_formats[] above, but with additional surface used
+ * to pass Clear Color information in plane 2 with 64 bits of

[Intel-gfx] [PATCH v7 1/3] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color

2021-01-14 Thread Imre Deak

From: Radhakrishna Sripada 

Gen12 display can decompress surfaces compressed by render engine with
Clear Color, add a new modifier as the driver needs to know the surface
was compressed by render engine.

V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
v4: Fix trailing whitespaces
v5: Explain Clear Color in the documentation.
v6: Documentation Nitpicks(Nanley)

Cc: Ville Syrjala 
Cc: Dhinakaran Pandiyan 
Cc: Kalyan Kondapally 
Cc: Rafael Antognolli 
Cc: Nanley Chery 
Signed-off-by: Radhakrishna Sripada 
Signed-off-by: Imre Deak 
Acked-by: Daniel Vetter 
Acked-by: Jani Nikula 
---
 include/uapi/drm/drm_fourcc.h | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 5f42a14481bd..f76de49c768f 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -527,6 +527,25 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
 
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
+ * compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates
+ * the converted clear color of size 64 bits. The first 32 bits store the Lower
+ * Converted Clear Color value and the next 32 bits store the Higher Converted
+ * Clear Color value when applicable. The Converted Clear Color values are
+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable
+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.25.1

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[Intel-gfx] [PATCH v7 0/3] drm/i915/gen12: Add display render clear color decompression support

2021-01-14 Thread Imre Deak

This is v7 of [1] addressing the review comments from Chris and Nanley.
Tested on TGL and DG1.

[1] https://patchwork.freedesktop.org/series/84183/

Cc: Nanley G Chery 
Cc: Chris Wilson https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v7 2/3] drm/i915/gem: Add a helper to read data from a GEM object page

2021-01-14 Thread Imre Deak

Add a simple helper to read data with the CPU from the page of a GEM
object. Do the read either via a kmap if the object has struct pages
or an iomap otherwise. This is needed by the next patch, reading a u64
value from the object (w/o requiring the obj to be mapped to the GPU).

Suggested by Chris.

Cc: Chris Wilson 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/gem/i915_gem_object.c | 75 ++
 drivers/gpu/drm/i915/gem/i915_gem_object.h |  2 +
 2 files changed, 77 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 00d24000b5e8..010f8d735e40 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -32,6 +32,7 @@
 #include "i915_gem_mman.h"
 #include "i915_gem_object.h"
 #include "i915_globals.h"
+#include "i915_memcpy.h"
 #include "i915_trace.h"
 
 static struct i915_global_object {
@@ -383,6 +384,80 @@ void __i915_gem_object_invalidate_frontbuffer(struct 
drm_i915_gem_object *obj,
}
 }
 
+static void
+i915_gem_object_read_from_page_kmap(struct drm_i915_gem_object *obj, unsigned 
long offset, int size, void *dst)
+{
+   const void *src_map;
+   const void *src_ptr;
+
+   src_map = kmap_atomic(i915_gem_object_get_page(obj, offset >> 
PAGE_SHIFT));
+
+   src_ptr = src_map + offset_in_page(offset);
+   if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))
+   drm_clflush_virt_range((void *)src_ptr, size);
+   memcpy(dst, src_ptr, size);
+
+   kunmap_atomic((void *)src_map);
+}
+
+static void
+i915_gem_object_read_from_page_iomap(struct drm_i915_gem_object *obj, unsigned 
long offset, int size, void *dst)
+{
+   const void __iomem *src_map;
+   const void __iomem *src_ptr;
+
+   src_map = io_mapping_map_wc(&obj->mm.region->iomap,
+   i915_gem_object_get_dma_address(obj, offset 
>> PAGE_SHIFT),
+   PAGE_SIZE);
+
+   src_ptr = src_map + offset_in_page(offset);
+   if (!i915_memcpy_from_wc(dst, src_ptr, size))
+   memcpy(dst, src_ptr, size);
+
+   io_mapping_unmap((void __iomem *)src_map);
+}
+
+/**
+ * i915_gem_object_read_from_page - read data from the page of a GEM object
+ * @obj: GEM object to read from
+ * @offset: offset within the object
+ * @size: size to read
+ * @dst: buffer to store the read data
+ *
+ * Reads data from @obj after syncing against any pending GPU writes on it.
+ * The requested region to read from can't cross a page boundary.
+ *
+ * Returns 0 on sucess, negative error code on failre.
+ */
+int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, unsigned 
long offset, size_t size, void *dst)
+{
+   int ret;
+
+   WARN_ON(offset + size > obj->base.size ||
+   offset_in_page(offset) + size > PAGE_SIZE);
+
+   i915_gem_object_lock(obj, NULL);
+
+   ret = i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT);
+   if (ret)
+   goto unlock;
+
+   ret = i915_gem_object_pin_pages(obj);
+   if (ret)
+   goto unlock;
+
+   if (i915_gem_object_has_struct_page(obj))
+   i915_gem_object_read_from_page_kmap(obj, offset, size, dst);
+   else
+   i915_gem_object_read_from_page_iomap(obj, offset, size, dst);
+
+   i915_gem_object_unpin_pages(obj);
+unlock:
+   i915_gem_object_unlock(obj);
+
+   return ret;
+}
+
 void i915_gem_init__objects(struct drm_i915_private *i915)
 {
INIT_WORK(&i915->mm.free_work, __i915_gem_free_work);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index be14486f63a7..75223f472a2b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -540,4 +540,6 @@ i915_gem_object_invalidate_frontbuffer(struct 
drm_i915_gem_object *obj,
__i915_gem_object_invalidate_frontbuffer(obj, origin);
 }
 
+int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, unsigned 
long offset, size_t size, void *dst);
+
 #endif
-- 
2.25.1

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm-buf: Add debug option (rev2)

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm-buf: Add debug option (rev2)
URL   : https://patchwork.freedesktop.org/series/85813/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
9406d53d49b1 drm-buf: Add debug option
-:64: ERROR:POINTER_LOCATION: "foo * bar" should be "foo *bar"
#64: FILE: drivers/dma-buf/dma-buf.c:669:
+static struct sg_table * __map_dma_buf(struct dma_buf_attachment *attach,

-:79: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a 
separate line
#79: FILE: drivers/dma-buf/dma-buf.c:684:
+* before passing the sgt back to the exporter. */

-:108: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#108: FILE: drivers/dma-buf/dma-buf.c:815:
+{
+

-:150: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address 
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: 
Daniel Vetter '

total: 1 errors, 2 warnings, 1 checks, 99 lines checked


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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Add DEBUG_GEM to the recommended CI config

2021-01-14 Thread Patchwork

== Series Details ==

Series: series starting with [1/2] drm/i915: Add DEBUG_GEM to the recommended 
CI config
URL   : https://patchwork.freedesktop.org/series/85869/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9611 -> Patchwork_19357


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19357/index.html

Known issues


  Here are the changes found in Patchwork_19357 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y:   [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +2 similar 
issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9611/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19357/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html

  
 Possible fixes 

  * igt@gem_sync@basic-all:
- fi-tgl-y:   [DMESG-WARN][3] ([i915#402]) -> [PASS][4] +1 similar 
issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9611/fi-tgl-y/igt@gem_s...@basic-all.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19357/fi-tgl-y/igt@gem_s...@basic-all.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u:   [DMESG-WARN][5] ([i915#2868]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9611/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19357/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html

  
  [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (41 -> 38)
--

  Missing(3): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9611 -> Patchwork_19357

  CI-20190529: 20190529
  CI_DRM_9611: b8541c1dee4c710073a77b3a1ce4d261c420105e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5959: c5cf0734c4f6c1fa17a6a15b5aa721c3a0b8c494 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19357: 011954fe6a8a3590a167c834cee93b6da0b98b15 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

011954fe6a8a drm/i915: Make GEM errors non-fatal by default
2ab1c85e3427 drm/i915: Add DEBUG_GEM to the recommended CI config

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19357/index.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Add DEBUG_GEM to the recommended CI config

2021-01-14 Thread Patchwork

== Series Details ==

Series: series starting with [1/2] drm/i915: Add DEBUG_GEM to the recommended 
CI config
URL   : https://patchwork.freedesktop.org/series/85869/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
2ab1c85e3427 drm/i915: Add DEBUG_GEM to the recommended CI config
011954fe6a8a drm/i915: Make GEM errors non-fatal by default
-:59: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & 
recovery code rather than BUG() or BUG_ON()
#59: FILE: drivers/gpu/drm/i915/i915_gem.h:42:
+#define __GEM_BUG(cond) BUG()

total: 0 errors, 1 warnings, 0 checks, 47 lines checked


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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers

2021-01-14 Thread Patchwork

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/selftests: Exercise relative 
mmio paths to non-privileged registers
URL   : https://patchwork.freedesktop.org/series/85865/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9607_full -> Patchwork_19354_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19354_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_import_export@flink:
- shard-glk:  [PASS][1] -> [INCOMPLETE][2] ([i915#2369])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-glk5/igt@drm_import_exp...@flink.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-glk8/igt@drm_import_exp...@flink.html

  * igt@gem_ctx_persistence@smoketest:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2896])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-tglb3/igt@gem_ctx_persiste...@smoketest.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-tglb8/igt@gem_ctx_persiste...@smoketest.html

  * igt@gem_exec_reloc@basic-many-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][5] ([i915#2389])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb1/igt@gem_exec_reloc@basic-many-act...@vcs1.html

  * igt@gem_mmap_gtt@coherency:
- shard-iclb: NOTRUN -> [SKIP][6] ([fdo#109292])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb5/igt@gem_mmap_...@coherency.html

  * igt@i915_suspend@sysfs-reader:
- shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([i915#1185])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-iclb3/igt@i915_susp...@sysfs-reader.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb3/igt@i915_susp...@sysfs-reader.html

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic:
- shard-skl:  NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111304]) +2 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl4/igt@kms_...@pipe-c-crc-sprite-planes-basic.html

  * igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-iclb: NOTRUN -> [SKIP][10] ([fdo#109284] / [fdo#111827])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb5/igt@kms_chamel...@hdmi-hpd-storm-disable.html

  * igt@kms_chamelium@vga-hpd:
- shard-skl:  NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +9 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl8/igt@kms_chamel...@vga-hpd.html

  * igt@kms_color_chamelium@pipe-d-ctm-max:
- shard-iclb: NOTRUN -> [SKIP][12] ([fdo#109278] / [fdo#109284] / 
[fdo#111827])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb5/igt@kms_color_chamel...@pipe-d-ctm-max.html

  * igt@kms_concurrent@pipe-c:
- shard-skl:  [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-skl8/igt@kms_concurr...@pipe-c.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl3/igt@kms_concurr...@pipe-c.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen:
- shard-iclb: [PASS][15] -> [DMESG-WARN][16] ([i915#1226])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-iclb2/igt@kms_cursor_...@pipe-a-cursor-64x21-offscreen.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb2/igt@kms_cursor_...@pipe-a-cursor-64x21-offscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen:
- shard-skl:  [PASS][17] -> [FAIL][18] ([i915#54]) +12 similar 
issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-64x21-offscreen.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl9/igt@kms_cursor_...@pipe-c-cursor-64x21-offscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109278])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb5/igt@kms_cursor_...@pipe-d-cursor-512x512-offscreen.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-tglb: [PASS][20] -> [FAIL][21] ([i915#2346])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-tglb2/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-tglb6/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-kbl:  [PASS][22] -> [DMESG-WARN][23] ([i915#180])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-kbl4/igt@kms_flip@flip-vs-suspend-interrupti...@b-dp1.html
   [23]: 
https://intel-gfx-c

[Intel-gfx] [PATCH 2/3] drm/i915/gem: sanity check object size in gem_create

2021-01-14 Thread Matthew Auld

Depending on the regions min_page_size we might need to adjust the
object size, ensure this matches our expectations.

Suggested-by: Chris Wilson 
Signed-off-by: Matthew Auld 
---
 drivers/gpu/drm/i915/gem/i915_gem_create.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c 
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index ce923ed49eee..45d60e3d98e3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -32,6 +32,8 @@ i915_gem_create(struct drm_file *file,
if (IS_ERR(obj))
return PTR_ERR(obj);
 
+   GEM_BUG_ON(size != obj->base.size);
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
-- 
2.26.2

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[Intel-gfx] [PATCH 3/3] drm/i915/region: convert object_create into object_init

2021-01-14 Thread Matthew Auld

Give more flexibility to the caller, if they already have an allocated
object, in case they wish to apply some transformation to the object
prior to handing it over to the region specific initialisation step,
like in gem_create_ext where we would like to first apply the extensions
to the object.

Signed-off-by: Matthew Auld 
---
 drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 15 ++---
 drivers/gpu/drm/i915/gem/i915_gem_lmem.h |  8 +--
 drivers/gpu/drm/i915/gem/i915_gem_region.c   | 16 -
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c| 23 +++
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c   | 65 ++--
 drivers/gpu/drm/i915/gt/intel_region_lmem.c  |  2 +-
 drivers/gpu/drm/i915/intel_memory_region.h   |  8 +--
 drivers/gpu/drm/i915/selftests/mock_region.c | 19 +++---
 8 files changed, 72 insertions(+), 84 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c 
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 932ee21e6609..194f35342710 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -31,18 +31,13 @@ i915_gem_object_create_lmem(struct drm_i915_private *i915,
 size, flags);
 }
 
-struct drm_i915_gem_object *
-__i915_gem_lmem_object_create(struct intel_memory_region *mem,
- resource_size_t size,
- unsigned int flags)
+int __i915_gem_lmem_object_init(struct intel_memory_region *mem,
+   struct drm_i915_gem_object *obj,
+   resource_size_t size,
+   unsigned int flags)
 {
static struct lock_class_key lock_class;
struct drm_i915_private *i915 = mem->i915;
-   struct drm_i915_gem_object *obj;
-
-   obj = i915_gem_object_alloc();
-   if (!obj)
-   return ERR_PTR(-ENOMEM);
 
drm_gem_private_object_init(&i915->drm, &obj->base, size);
i915_gem_object_init(obj, &i915_gem_lmem_obj_ops, &lock_class);
@@ -53,5 +48,5 @@ __i915_gem_lmem_object_create(struct intel_memory_region *mem,
 
i915_gem_object_init_memory_region(obj, mem, flags);
 
-   return obj;
+   return 0;
 }
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h 
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index fc3f15580fe3..036d53c01de9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -21,9 +21,9 @@ i915_gem_object_create_lmem(struct drm_i915_private *i915,
resource_size_t size,
unsigned int flags);
 
-struct drm_i915_gem_object *
-__i915_gem_lmem_object_create(struct intel_memory_region *mem,
- resource_size_t size,
- unsigned int flags);
+int __i915_gem_lmem_object_init(struct intel_memory_region *mem,
+   struct drm_i915_gem_object *obj,
+   resource_size_t size,
+   unsigned int flags);
 
 #endif /* !__I915_GEM_LMEM_H */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c 
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 835bd01f2e5d..4834a0b272f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -143,6 +143,7 @@ i915_gem_object_create_region(struct intel_memory_region 
*mem,
  unsigned int flags)
 {
struct drm_i915_gem_object *obj;
+   int err;
 
/*
 * NB: Our use of resource_size_t for the size stems from using struct
@@ -160,6 +161,10 @@ i915_gem_object_create_region(struct intel_memory_region 
*mem,
GEM_BUG_ON(!size);
GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_MIN_ALIGNMENT));
 
+   obj = i915_gem_object_alloc();
+   if (!obj)
+   return ERR_PTR(-ENOMEM);
+
/*
 * XXX: There is a prevalence of the assumption that we fit the
 * object's page count inside a 32bit _signed_ variable. Let's document
@@ -173,9 +178,14 @@ i915_gem_object_create_region(struct intel_memory_region 
*mem,
if (overflows_type(size, obj->base.size))
return ERR_PTR(-E2BIG);
 
-   obj = mem->ops->create_object(mem, size, flags);
-   if (!IS_ERR(obj))
-   trace_i915_gem_object_create(obj);
+   err = mem->ops->init_object(mem, obj, size, flags);
+   if (err)
+   goto err_object_free;
 
+   trace_i915_gem_object_create(obj);
return obj;
+
+err_object_free:
+   i915_gem_object_free(obj);
+   return ERR_PTR(err);
 }
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c 
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 75e8b71c18b9..722e02164c3e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -464,26 +464,21 @@ static int __create_shmem(struct drm_i915_private *i915,
return 0;
 }
 
-stat

[Intel-gfx] [PATCH 1/3] drm/i915/gem: split gem_create into own file

2021-01-14 Thread Matthew Auld

In preparation for gem_create_ext break out the gem_create uAPI, so that
we don't clutter i915_gem.c once we start adding various extensions

Signed-off-by: Matthew Auld 
---
 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/gem/i915_gem_create.c | 111 +
 drivers/gpu/drm/i915/i915_gem.c| 102 ---
 3 files changed, 112 insertions(+), 102 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_create.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 00d4dd5ecdb7..cf163d08269e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -136,6 +136,7 @@ gem-y += \
gem/i915_gem_clflush.o \
gem/i915_gem_client_blt.o \
gem/i915_gem_context.o \
+   gem/i915_gem_create.o \
gem/i915_gem_dmabuf.o \
gem/i915_gem_domain.o \
gem/i915_gem_execbuffer.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c 
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
new file mode 100644
index ..ce923ed49eee
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "gem/i915_gem_ioctls.h"
+#include "gem/i915_gem_region.h"
+
+#include "i915_drv.h"
+
+static int
+i915_gem_create(struct drm_file *file,
+   struct intel_memory_region *mr,
+   u64 *size_p,
+   u32 *handle_p)
+{
+   struct drm_i915_gem_object *obj;
+   u32 handle;
+   u64 size;
+   int ret;
+
+   GEM_BUG_ON(!is_power_of_2(mr->min_page_size));
+   size = round_up(*size_p, mr->min_page_size);
+   if (size == 0)
+   return -EINVAL;
+
+   /* For most of the ABI (e.g. mmap) we think in system pages */
+   GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE));
+
+   /* Allocate the new object */
+   obj = i915_gem_object_create_region(mr, size, 0);
+   if (IS_ERR(obj))
+   return PTR_ERR(obj);
+
+   ret = drm_gem_handle_create(file, &obj->base, &handle);
+   /* drop reference from allocate - handle holds it now */
+   i915_gem_object_put(obj);
+   if (ret)
+   return ret;
+
+   *handle_p = handle;
+   *size_p = size;
+   return 0;
+}
+
+int
+i915_gem_dumb_create(struct drm_file *file,
+struct drm_device *dev,
+struct drm_mode_create_dumb *args)
+{
+   enum intel_memory_type mem_type;
+   int cpp = DIV_ROUND_UP(args->bpp, 8);
+   u32 format;
+
+   switch (cpp) {
+   case 1:
+   format = DRM_FORMAT_C8;
+   break;
+   case 2:
+   format = DRM_FORMAT_RGB565;
+   break;
+   case 4:
+   format = DRM_FORMAT_XRGB;
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   /* have to work out size/pitch and return them */
+   args->pitch = ALIGN(args->width * cpp, 64);
+
+   /* align stride to page size so that we can remap */
+   if (args->pitch > intel_plane_fb_max_stride(to_i915(dev), format,
+   DRM_FORMAT_MOD_LINEAR))
+   args->pitch = ALIGN(args->pitch, 4096);
+
+   if (args->pitch < args->width)
+   return -EINVAL;
+
+   args->size = mul_u32_u32(args->pitch, args->height);
+
+   mem_type = INTEL_MEMORY_SYSTEM;
+   if (HAS_LMEM(to_i915(dev)))
+   mem_type = INTEL_MEMORY_LOCAL;
+
+   return i915_gem_create(file,
+  intel_memory_region_by_type(to_i915(dev),
+  mem_type),
+  &args->size, &args->handle);
+}
+
+/**
+ * Creates a new mm object and returns a handle to it.
+ * @dev: drm device pointer
+ * @data: ioctl data blob
+ * @file: drm file pointer
+ */
+int
+i915_gem_create_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+   struct drm_i915_private *i915 = to_i915(dev);
+   struct drm_i915_gem_create *args = data;
+
+   i915_gem_flush_free_objects(i915);
+
+   return i915_gem_create(file,
+  intel_memory_region_by_type(i915,
+  INTEL_MEMORY_SYSTEM),
+  &args->size, &args->handle);
+}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 17a4636ee542..c013148835e6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -179,108 +179,6 @@ int i915_gem_object_unbind(struct drm_i915_gem_object 
*obj,
return ret;
 }
 
-static int
-i915_gem_create(struct drm_file *file,
-   struct intel_memory_region *mr,
-   u64 *size_p,
-   u32 *handle_p)
-{
-   struct drm_i915_gem_object *obj;
-

Re: [Intel-gfx] [PATCH 01/10] drm/i915: Mark up protected uses of 'i915_request_completed'

2021-01-14 Thread Andi Shyti

Hi Chris,

> > > diff --git a/drivers/gpu/drm/i915/i915_request.c 
> > > b/drivers/gpu/drm/i915/i915_request.c
> > > index 0b1a46a0d866..784c05ac5cca 100644
> > > --- a/drivers/gpu/drm/i915/i915_request.c
> > > +++ b/drivers/gpu/drm/i915/i915_request.c
> > > @@ -276,7 +276,7 @@ static void remove_from_engine(struct i915_request 
> > > *rq)
> > >  
> > >  bool i915_request_retire(struct i915_request *rq)
> > >  {
> > > - if (!i915_request_completed(rq))
> > > + if (!__i915_request_is_complete(rq))
> > 
> > 
> > >   return false;
> > >  
> > >   RQ_TRACE(rq, "\n");
> > > @@ -342,8 +342,7 @@ void i915_request_retire_upto(struct i915_request *rq)
> > >   struct i915_request *tmp;
> > >  
> > >   RQ_TRACE(rq, "\n");
> > > -
> > > - GEM_BUG_ON(!i915_request_completed(rq));
> > > + GEM_BUG_ON(!__i915_request_is_complete(rq));
> > 
> > I might be a bit shallow, but where is the lock here?
> 
> This holds the request->context->timeline->mutex.
> 
> The locking is basically split between frontend/backend:
> 
>   construction/destruction - under the timeline->mutex
> 
>   execution - under the engine->active.lock (coordinates with
>   timeline->mutex)
> 
> At all other times, RCU protected access (using the SLAB_TYPESAFE_BY_RCU
> so approach with caution).

Right! Thanks!

Reviewed-by: Andi Shyti 

Andi
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Re: [Intel-gfx] [PATCH v6 1/4] drm/i915: Keep track of pwm-related backlight hooks separately

2021-01-14 Thread Lyude Paul

On Thu, 2021-01-14 at 09:12 +0200, Jani Nikula wrote:
> On Wed, 13 Jan 2021, Lyude Paul  wrote:
> > Currently, every different type of backlight hook that i915 supports is
> > pretty straight forward - you have a backlight, probably through PWM
> > (but maybe DPCD), with a single set of platform-specific hooks that are
> > used for controlling it.
> > 
> > HDR backlights, in particular VESA and Intel's HDR backlight
> > implementations, can end up being more complicated. With Intel's
> > proprietary interface, HDR backlight controls always run through the
> > DPCD. When the backlight is in SDR backlight mode however, the driver
> > may need to bypass the TCON and control the backlight directly through
> > PWM.
> > 
> > So, in order to support this we'll need to split our backlight callbacks
> > into two groups: a set of high-level backlight control callbacks in
> > intel_panel, and an additional set of pwm-specific backlight control
> > callbacks. This also implies a functional changes for how these
> > callbacks are used:
> > 
> > * We now keep track of two separate backlight level ranges, one for the
> >   high-level backlight, and one for the pwm backlight range
> > * We also keep track of backlight enablement and PWM backlight
> >   enablement separately
> > * Since the currently set backlight level might not be the same as the
> >   currently programmed PWM backlight level, we stop setting
> >   panel->backlight.level with the currently programmed PWM backlight
> >   level in panel->backlight.pwm_funcs->setup(). Instead, we rely
> >   on the higher level backlight control functions to retrieve the
> >   current PWM backlight level (in this case, intel_pwm_get_backlight()).
> >   Note that there are still a few PWM backlight setup callbacks that
> >   do actually need to retrieve the current PWM backlight level, although
> >   we no longer save this value in panel->backlight.level like before.
> > 
> > Additionally, we drop the call to lpt_get_backlight() in
> > lpt_setup_backlight(), and avoid unconditionally writing the PWM value that
> > we get from it and only write it back if we're in CPU mode, and switching
> > to PCH mode. The reason for this is because in the original codepath for
> > this, it was expected that the intel_panel_bl_funcs->setup() hook would be
> > responsible for fetching the initial backlight level. On lpt systems, the
> > only time we could ever be in PCH backlight mode is during the initial
> > driver load - meaning that outside of the setup() hook, lpt_get_backlight()
> > will always be the callback used for retrieving the current backlight
> > level. After this patch we still need to fetch and write-back the PCH
> > backlight value if we're switching from CPU mode to PCH, but because
> > intel_pwm_setup_backlight() will retrieve the backlight level after setup()
> > using the get() hook, which always ends up being lpt_get_backlight(). Thus
> > - an additional call to lpt_get_backlight() in lpt_setup_backlight() is
> > made redundant.
> > 
> > v7:
> > * Use panel->backlight.pwm_funcs->get() to get the backlight level in
> >   intel_pwm_setup_backlight(), lest we upset lockdep
> 
> I think this change is wrong, as it now bypasses
> intel_panel_invert_pwm_level(). Please explain. I don't see anything in
> there that could trigger a lockdep warning.

yeah-this was definitely me misunderstanding what the issue we were hitting here
was.

> 
> Perhaps it's the below you're referring to, but I think the root cause
> is different?
> 
> > @@ -1788,22 +1780,17 @@ static int vlv_setup_backlight(struct
> > intel_connector *connector, enum pipe pipe
> > panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965;
> >  
> > ctl = intel_de_read(dev_priv, VLV_BLC_PWM_CTL(pipe));
> > -   panel->backlight.max = ctl >> 16;
> > +   panel->backlight.pwm_level_max = ctl >> 16;
> >  
> > -   if (!panel->backlight.max)
> > -   panel->backlight.max = get_backlight_max_vbt(connector);
> > +   if (!panel->backlight.pwm_level_max)
> > +   panel->backlight.pwm_level_max =
> > get_backlight_max_vbt(connector);
> >  
> > -   if (!panel->backlight.max)
> > +   if (!panel->backlight.pwm_level_max)
> > return -ENODEV;
> >  
> > -   panel->backlight.min = get_backlight_min_vbt(connector);
> > +   panel->backlight.pwm_level_min = get_backlight_min_vbt(connector);
> >  
> > -   val = _vlv_get_backlight(dev_priv, pipe);
> 
> Turns out this is a meaningful change, as the higher level
> vlv_get_backlight() function that will be called instead hits:
> 
> <4>[   12.870202] i915 :00:02.0: drm_WARN_ON(!drm_modeset_is_locked(&dev-
> >mode_config.connection_mutex))
> 
> in intel_connector_get_pipe(connector).
> 
> It's a real problem. See this, it's obvious (in retrospect):
> 
>  
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19348/fi-bsw-kefka/igt@run...@aborted.html
>  
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchw

Re: [Intel-gfx] [PATCH v4 08/18] drm/i915/display: VRR + DRRS cannot be enabled together

2021-01-14 Thread Ville Syrjälä

On Wed, Jan 13, 2021 at 02:09:25PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä 
> 
> If VRR is enabled, DRRS cannot be enabled, so make this check
> in atomic check.

Signed-off-by: Ville Syrjälä 

if we want to keep this as a separete patch.

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index a275303c0c5c..869a9d291e1b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2845,6 +2845,9 @@ intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
>   struct intel_connector *intel_connector = intel_dp->attached_connector;
>   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> + if (pipe_config->vrr.enable)
> + return;
> +
>   /*
>* DRRS and PSR can't be enable together, so giving preference to PSR
>* as it allows more power-savings by complete shutting down display,
> -- 
> 2.19.1

-- 
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Reapply ppgtt enabling after engine resets

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm/i915/gt: Reapply ppgtt enabling after engine resets
URL   : https://patchwork.freedesktop.org/series/85864/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9606_full -> Patchwork_19353_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19353_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_balancer@waits:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2] ([i915#2931])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9606/shard-tglb3/igt@gem_exec_balan...@waits.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-tglb7/igt@gem_exec_balan...@waits.html

  * igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][3] ([fdo#112283])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-iclb7/igt@gem_exec_par...@secure-non-root.html

  * igt@gem_exec_suspend@basic-s3:
- shard-skl:  [PASS][4] -> [INCOMPLETE][5] ([i915#198]) +1 similar 
issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9606/shard-skl2/igt@gem_exec_susp...@basic-s3.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-skl8/igt@gem_exec_susp...@basic-s3.html

  * igt@gem_userptr_blits@readonly-unsync:
- shard-tglb: NOTRUN -> [SKIP][6] ([fdo#110426] / [i915#1704])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-tglb8/igt@gem_userptr_bl...@readonly-unsync.html

  * igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglb: NOTRUN -> [WARN][7] ([i915#2681])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-tglb8/igt@i915_pm_rc6_reside...@rc6-fence.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][8] ([fdo#110892])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-iclb7/igt@i915_pm_...@dpms-mode-unset-non-lpsp.html

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-tglb: NOTRUN -> [SKIP][9] ([fdo#109506] / [i915#2411])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-tglb8/igt@i915_pm_...@gem-execbuf-stress-pc8.html

  * igt@i915_pm_sseu@full-enable:
- shard-tglb: NOTRUN -> [SKIP][10] ([fdo#109288])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-tglb8/igt@i915_pm_s...@full-enable.html

  * igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2597])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9606/shard-tglb6/igt@kms_async_fl...@test-time-stamp.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-tglb6/igt@kms_async_fl...@test-time-stamp.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing@dp-1-pipe-a:
- shard-kbl:  [PASS][13] -> [DMESG-WARN][14] ([i915#62])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9606/shard-kbl6/igt@kms_atomic_transition@plane-all-modeset-transition-fenc...@dp-1-pipe-a.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-kbl2/igt@kms_atomic_transition@plane-all-modeset-transition-fenc...@dp-1-pipe-a.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing@dp-1-pipe-b:
- shard-kbl:  [PASS][15] -> [DMESG-WARN][16] ([i915#165] / 
[i915#180])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9606/shard-kbl6/igt@kms_atomic_transition@plane-all-modeset-transition-fenc...@dp-1-pipe-b.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-kbl2/igt@kms_atomic_transition@plane-all-modeset-transition-fenc...@dp-1-pipe-b.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][17] ([fdo#111615])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-tglb8/igt@kms_big...@yf-tiled-64bpp-rotate-0.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo:
- shard-glk:  NOTRUN -> [SKIP][18] ([fdo#109271]) +12 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-glk5/igt@kms_...@pipe-c-ccs-on-another-bo.html

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic:
- shard-skl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111304])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-skl9/igt@kms_...@pipe-c-crc-sprite-planes-basic.html

  * igt@kms_chamelium@dp-edid-read:
- shard-iclb: NOTRUN -> [SKIP][20] ([fdo#109284] / [fdo#111827]) +1 
similar issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-iclb7/igt@kms_chamel...@dp-edid-read.html

  * igt@kms_color@pipe-b-degamma:
- shard-iclb: NOTRUN -> [FAIL][21] ([i915#1149])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/shard-iclb7/igt@kms_co...@pipe-b-degamma.h

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg1: Apply WA 1409120013 and 14011059788

2021-01-14 Thread Souza, Jose

On Wed, 2021-01-13 at 20:03 +, Patchwork wrote:
Patch Details
Series: drm/i915/dg1: Apply WA 1409120013 and 14011059788
URL:https://patchwork.freedesktop.org/series/85807/
State:  success
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19333/index.html
CI Bug Log - changes from CI_DRM_9602_full -> Patchwork_19333_full
Summary

SUCCESS

No regressions found.

Pushed, thanks for the review Matt Roper.

Known issues

Here are the changes found in Patchwork_19333_full that come from known issues:

IGT changes
Issues hit

  *   igt@gem_exec_whisper@basic-queues-forked-all:

 *   shard-glk: 
PASS
 -> 
DMESG-WARN
 (i915#118 / 
i915#95) +1 similar issue
  *   igt@kms_ccs@pipe-c-crc-sprite-planes-basic:

 *   shard-skl: NOTRUN -> 
SKIP
 (fdo#109271 / 
fdo#111304)
  *   igt@kms_color@pipe-c-degamma:

 *   shard-skl: 
PASS
 -> 
FAIL
 (i915#71)
  *   igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes:

 *   shard-skl: NOTRUN -> 
SKIP
 (fdo#109271 / 
fdo#111827) +4 similar 
issues
  *   igt@kms_cursor_crc@pipe-c-cursor-64x21-random:

 *   shard-skl: 
PASS
 -> 
FAIL
 (i915#54) +7 similar issues
  *   igt@kms_cursor_legacy@flip-vs-cursor-varying-size:

 *   shard-tglb: 
PASS
 -> 
FAIL
 (i915#2346)
  *   igt@kms_flip@flip-vs-expired-vblank@a-edp1:

 *   shard-skl: 
PASS
 -> 
FAIL
 (i915#79) +1 similar issue

 *   shard-tglb: 
PASS
 -> 
FAIL
 (i915#2598)

  *   igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:

 *   shard-skl: 
PASS
 -> 
INCOMPLETE
 (i915#2295)
  *   igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:

 *   shard-skl: NOTRUN -> 
SKIP
 (fdo#109271) +34 similar 
issues
  *   igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt:

 *   shard-skl: 
PASS
 -> 
FAIL
 (i915#49)
  *   igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:

 *   shard-skl: NOTRUN -> 
FAIL

Re: [Intel-gfx] [PATCH 11/11] drm/i915: migrate i9xx plane get config

2021-01-14 Thread Ville Syrjälä

On Thu, Jan 14, 2021 at 01:13:55PM +0200, Jani Nikula wrote:
> From: Dave Airlie 
> 
> Migrate this code out like the skylake code.
> 
> !!! FIXME: Dave's s-o-b !!!
> 
> Signed-off-by: Jani Nikula 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/display/i9xx_plane.c| 119 +++
>  drivers/gpu/drm/i915/display/i9xx_plane.h|   4 +
>  drivers/gpu/drm/i915/display/intel_display.c | 119 ---
>  3 files changed, 123 insertions(+), 119 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c 
> b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 6c568079f492..a063a92f04dc 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -698,3 +698,122 @@ intel_primary_plane_create(struct drm_i915_private 
> *dev_priv, enum pipe pipe)
>   return ERR_PTR(ret);
>  }
>  
> +static int i9xx_format_to_fourcc(int format)
> +{
> + switch (format) {
> + case DISPPLANE_8BPP:
> + return DRM_FORMAT_C8;
> + case DISPPLANE_BGRA555:
> + return DRM_FORMAT_ARGB1555;
> + case DISPPLANE_BGRX555:
> + return DRM_FORMAT_XRGB1555;
> + case DISPPLANE_BGRX565:
> + return DRM_FORMAT_RGB565;
> + default:
> + case DISPPLANE_BGRX888:
> + return DRM_FORMAT_XRGB;
> + case DISPPLANE_RGBX888:
> + return DRM_FORMAT_XBGR;
> + case DISPPLANE_BGRA888:
> + return DRM_FORMAT_ARGB;
> + case DISPPLANE_RGBA888:
> + return DRM_FORMAT_ABGR;
> + case DISPPLANE_BGRX101010:
> + return DRM_FORMAT_XRGB2101010;
> + case DISPPLANE_RGBX101010:
> + return DRM_FORMAT_XBGR2101010;
> + case DISPPLANE_BGRA101010:
> + return DRM_FORMAT_ARGB2101010;
> + case DISPPLANE_RGBA101010:
> + return DRM_FORMAT_ABGR2101010;
> + case DISPPLANE_RGBX161616:
> + return DRM_FORMAT_XBGR16161616F;
> + }
> +}
> +
> +void
> +i9xx_get_initial_plane_config(struct intel_crtc *crtc,
> +   struct intel_initial_plane_config *plane_config)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> + enum pipe pipe;
> + u32 val, base, offset;
> + int fourcc, pixel_format;
> + unsigned int aligned_height;
> + struct drm_framebuffer *fb;
> + struct intel_framebuffer *intel_fb;
> +
> + if (!plane->get_hw_state(plane, &pipe))
> + return;
> +
> + drm_WARN_ON(dev, pipe != crtc->pipe);
> +
> + intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
> + if (!intel_fb) {
> + drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
> + return;
> + }
> +
> + fb = &intel_fb->base;
> +
> + fb->dev = dev;
> +
> + val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
> +
> + if (INTEL_GEN(dev_priv) >= 4) {
> + if (val & DISPPLANE_TILED) {
> + plane_config->tiling = I915_TILING_X;
> + fb->modifier = I915_FORMAT_MOD_X_TILED;
> + }
> +
> + if (val & DISPPLANE_ROTATE_180)
> + plane_config->rotation = DRM_MODE_ROTATE_180;
> + }
> +
> + if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
> + val & DISPPLANE_MIRROR)
> + plane_config->rotation |= DRM_MODE_REFLECT_X;
> +
> + pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
> + fourcc = i9xx_format_to_fourcc(pixel_format);
> + fb->format = drm_format_info(fourcc);
> +
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> + offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
> + base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 
> 0xf000;
> + } else if (INTEL_GEN(dev_priv) >= 4) {
> + if (plane_config->tiling)
> + offset = intel_de_read(dev_priv,
> +DSPTILEOFF(i9xx_plane));
> + else
> + offset = intel_de_read(dev_priv,
> +DSPLINOFF(i9xx_plane));
> + base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 
> 0xf000;
> + } else {
> + base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
> + }
> + plane_config->base = base;
> +
> + val = intel_de_read(dev_priv, PIPESRC(pipe));
> + fb->width = ((val >> 16) & 0xfff) + 1;
> + fb->height = ((val >> 0) & 0xfff) + 1;
> +
> + val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
> + fb->pitches[0] = val & 0xffc0;
> +
> + aligned_height = intel_fb_align_height(fb, 0, fb->height);
> +
> + plane_config->size = fb->pitches[0] * aligned_height;
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "%s/%

Re: [Intel-gfx] [PATCH 10/11] drm/i915: migrate pll enable/disable code to intel_dpll.[ch]

2021-01-14 Thread Ville Syrjälä

On Thu, Jan 14, 2021 at 01:13:54PM +0200, Jani Nikula wrote:
> From: Dave Airlie 
> 
> This moves the older i9xx/vlv/chv enable/disable to dpll file.
> 
> !!! FIXME: Dave's s-o-b !!!
> 
> Signed-off-by: Jani Nikula 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 512 ---
>  drivers/gpu/drm/i915/display/intel_display.h |   3 -
>  drivers/gpu/drm/i915/display/intel_dp.c  |   1 +
>  drivers/gpu/drm/i915/display/intel_dpll.c| 509 ++
>  drivers/gpu/drm/i915/display/intel_dpll.h|  18 +
>  drivers/gpu/drm/i915/display/intel_pps.c |   1 +
>  6 files changed, 529 insertions(+), 515 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 7398927e1627..8abd49cf9c2b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -109,10 +109,6 @@ static void i9xx_set_pipeconf(const struct 
> intel_crtc_state *crtc_state);
>  static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
>  static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
>  static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
> -static void vlv_prepare_pll(struct intel_crtc *crtc,
> - const struct intel_crtc_state *pipe_config);
> -static void chv_prepare_pll(struct intel_crtc *crtc,
> - const struct intel_crtc_state *pipe_config);
>  static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
>  static void intel_modeset_setup_hw_state(struct drm_device *dev,
>struct drm_modeset_acquire_ctx *ctx);
> @@ -565,224 +561,6 @@ static void assert_pch_ports_disabled(struct 
> drm_i915_private *dev_priv,
>   assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
>  }
>  
> -static void _vlv_enable_pll(struct intel_crtc *crtc,
> - const struct intel_crtc_state *pipe_config)
> -{
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum pipe pipe = crtc->pipe;
> -
> - intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
> - intel_de_posting_read(dev_priv, DPLL(pipe));
> - udelay(150);
> -
> - if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
> - drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
> -}
> -
> -static void vlv_enable_pll(struct intel_crtc *crtc,
> -const struct intel_crtc_state *pipe_config)
> -{
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum pipe pipe = crtc->pipe;
> -
> - assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
> -
> - /* PLL is protected by panel, make sure we can write it */
> - assert_panel_unlocked(dev_priv, pipe);
> -
> - if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
> - _vlv_enable_pll(crtc, pipe_config);
> -
> - intel_de_write(dev_priv, DPLL_MD(pipe),
> -pipe_config->dpll_hw_state.dpll_md);
> - intel_de_posting_read(dev_priv, DPLL_MD(pipe));
> -}
> -
> -
> -static void _chv_enable_pll(struct intel_crtc *crtc,
> - const struct intel_crtc_state *pipe_config)
> -{
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum pipe pipe = crtc->pipe;
> - enum dpio_channel port = vlv_pipe_to_channel(pipe);
> - u32 tmp;
> -
> - vlv_dpio_get(dev_priv);
> -
> - /* Enable back the 10bit clock to display controller */
> - tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
> - tmp |= DPIO_DCLKP_EN;
> - vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
> -
> - vlv_dpio_put(dev_priv);
> -
> - /*
> -  * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
> -  */
> - udelay(1);
> -
> - /* Enable PLL */
> - intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
> -
> - /* Check PLL is locked */
> - if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
> - drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
> -}
> -
> -static void chv_enable_pll(struct intel_crtc *crtc,
> -const struct intel_crtc_state *pipe_config)
> -{
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum pipe pipe = crtc->pipe;
> -
> - assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
> -
> - /* PLL is protected by panel, make sure we can write it */
> - assert_panel_unlocked(dev_priv, pipe);
> -
> - if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
> - _chv_enable_pll(crtc, pipe_config);
> -
> - if (pipe != PIPE_A) {
> - /*
> -  * WaPixelRepeatModeFixForC0:chv
> -  *
> -  * DPLLCMD is AWOL. Use chicken bits to propagate
> -

Re: [Intel-gfx] [PATCH 09/11] drm/i915: move is_ccs_modifier to an inline

2021-01-14 Thread Ville Syrjälä

On Thu, Jan 14, 2021 at 01:13:53PM +0200, Jani Nikula wrote:
> From: Dave Airlie 
> 
> There is no need for this to be out of line.
> 
> Signed-off-by: Dave Airlie 
> Signed-off-by: Jani Nikula 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/display/intel_display.c   | 8 
>  drivers/gpu/drm/i915/display/intel_display.h   | 1 -
>  drivers/gpu/drm/i915/display/intel_display_types.h | 8 
>  3 files changed, 8 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index ab9d164345e5..7398927e1627 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1791,14 +1791,6 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 
> *cmd)
>   }
>  }
>  
> -bool is_ccs_modifier(u64 modifier)
> -{
> - return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> -modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> -modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> -modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> -}
> -
>  static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
>  {
>   return DIV_ROUND_UP(fb->pitches[skl_ccs_to_main_plane(fb, ccs_plane)],
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h 
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 0b2fed58badf..f4214e161a9d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -508,7 +508,6 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
>   int pixel_clock, int link_clock,
>   struct intel_link_m_n *m_n,
>   bool constant_n, bool fec_enable);
> -bool is_ccs_modifier(u64 modifier);
>  void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
>  u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> u32 pixel_format, u64 modifier);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 179c277e5cf7..a2cd4bf9e246 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1862,6 +1862,14 @@ static inline u32 intel_fdi_link_freq(struct 
> drm_i915_private *dev_priv,
>   return dev_priv->fdi_pll_freq;
>  }
>  
> +static inline bool is_ccs_modifier(u64 modifier)
> +{
> + return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> +modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> +modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> +}
> +
>  static inline bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
>  {
>   if (!is_ccs_modifier(fb->modifier))
> -- 
> 2.20.1
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [Intel-gfx] [PATCH 06/11] drm/i915: migrate skl planes code new file (v3)

2021-01-14 Thread Ville Syrjälä

On Thu, Jan 14, 2021 at 01:13:50PM +0200, Jani Nikula wrote:
> From: Dave Airlie 
> 
> Rework the plane init calls to do the gen test one level higher.
> 
> Rework some of the plane helpers so they can live in new file,
> there is still some scope to clean up the plane/fb interactions
> later.
> 
> v2: drop atomic code back, rename file to Ville suggestions,
> add header file.
> v3: move scaler bits back
> 
> Signed-off-by: Dave Airlie 
> [Jani: fixed up sparse warnings.]
> Signed-off-by: Jani Nikula 
> Reported-by: kernel test robot 
> Reported-by: Dan Carpenter 
> ---

> -unsigned int
> -intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
> -{
> - int x = 0, y = 0;
> -
> - intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
> -   plane_state->color_plane[0].offset, 
> 0);
> -
> - return y;
> -}

This getting moved around is messing up the diff.


> @@ -4386,15 +3633,6 @@ static int skl_update_scaler_plane(struct 
> intel_crtc_state *crtc_state,
>   return 0;
>  }
>  
> -void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
> -{
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> - int i;
> -
> - for (i = 0; i < crtc->num_scalers; i++)
> - skl_detach_scaler(crtc, i);
> -}

Same here.


> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index f76e2c2a83b8..8e4b6647752f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -39,6 +39,7 @@
>  #include "intel_dp_mst.h"
>  #include "intel_dpio_phy.h"
>  #include "intel_hdcp.h"
> +#include "skl_universal_plane.h"

Why is this here?

>  
>  static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
>   struct intel_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index c24ae69426cf..0d0b0d3c52a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -31,6 +31,7 @@
>  #include "intel_psr.h"
>  #include "intel_sprite.h"
>  #include "intel_hdmi.h"
> +#include "skl_universal_plane.h"

Is this due to the psr damage stuff?


> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c 
> b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index f94025ec603a..ebf266457518 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -38,6 +38,7 @@
>  #include "intel_fifo_underrun.h"
>  #include "intel_panel.h"
>  #include "intel_sideband.h"
> +#include "skl_universal_plane.h"

Why do we need this here?

>  
>  /* return pixels in terms of txbyteclkhs */
>  static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bbc73df7f753..bc40ecc17a52 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -38,6 +38,7 @@
>  #include "display/intel_display_types.h"
>  #include "display/intel_fbc.h"
>  #include "display/intel_sprite.h"
> +#include "display/skl_universal_plane.h"
>  
>  #include "gt/intel_llc.h"
>  
> -- 
> 2.20.1
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add DEBUG_GEM to the recommended CI config

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm/i915: Add DEBUG_GEM to the recommended CI config
URL   : https://patchwork.freedesktop.org/series/85868/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9608 -> Patchwork_19356


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/index.html

Known issues


  Here are the changes found in Patchwork_19356 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u:   NOTRUN -> [SKIP][1] ([fdo#109271]) +22 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html

  * igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-bsw-n3050:   NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/fi-bsw-n3050/igt@amdgpu/amd_cs_...@sync-gfx0.html

  * igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u:   NOTRUN -> [WARN][3] ([i915#2283])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_flink_basic@double-flink:
- fi-tgl-y:   [PASS][4] -> [DMESG-WARN][5] ([i915#402]) +1 similar 
issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9608/fi-tgl-y/igt@gem_flink_ba...@double-flink.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/fi-tgl-y/igt@gem_flink_ba...@double-flink.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u:   [PASS][6] -> [FAIL][7] ([i915#2128])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9608/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- fi-tgl-u2:  [FAIL][8] ([i915#1888]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9608/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-n3050:   [INCOMPLETE][10] -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9608/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html

  * igt@prime_vgem@basic-fence-flip:
- fi-tgl-y:   [DMESG-WARN][12] ([i915#402]) -> [PASS][13] +2 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9608/fi-tgl-y/igt@prime_v...@basic-fence-flip.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/fi-tgl-y/igt@prime_v...@basic-fence-flip.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2128]: https://gitlab.freedesktop.org/drm/intel/issues/2128
  [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (41 -> 37)
--

  Missing(4): fi-ctg-p8600 fi-cml-u2 fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9608 -> Patchwork_19356

  CI-20190529: 20190529
  CI_DRM_9608: 006125b38858f9be67f924e1834a1bb25ad20dec @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5958: cb5bc26db33ed77cfabfc6a9e4777b9167596a67 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19356: 01d6d815be1ed2ebda7e786b0dff4538e915c083 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

01d6d815be1e drm/i915: Add DEBUG_GEM to the recommended CI config

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19356/index.html
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Re: [Intel-gfx] [PATCH 05/11] drm/i915: migrate hsw fdi code to new file.

2021-01-14 Thread Ville Syrjälä

On Thu, Jan 14, 2021 at 01:13:49PM +0200, Jani Nikula wrote:
> From: Dave Airlie 
> 
> Daniel asked for this, but it's a bit messy and I'm not sure
> how best to clean it up yet.
> 
> Signed-off-by: Dave Airlie 
> [Jani: also moved fdi buf trans to intel_fdi.c.]
> Signed-off-by: Jani Nikula 

I guess this is ok. Although the code is pretty ddi'ish.

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/display/intel_crt.c |   1 +
>  drivers/gpu/drm/i915/display/intel_ddi.c | 151 ++-
>  drivers/gpu/drm/i915/display/intel_ddi.h |   8 +-
>  drivers/gpu/drm/i915/display/intel_fdi.c | 139 +
>  drivers/gpu/drm/i915/display/intel_fdi.h |   3 +
>  5 files changed, 156 insertions(+), 146 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c 
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index 4934edd51cb0..077ebc7e6396 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -38,6 +38,7 @@
>  #include "intel_crt.h"
>  #include "intel_ddi.h"
>  #include "intel_display_types.h"
> +#include "intel_fdi.h"
>  #include "intel_fifo_underrun.h"
>  #include "intel_gmbus.h"
>  #include "intel_hotplug.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 1caf643e6400..61ac1e1b7b55 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -36,10 +36,11 @@
>  #include "intel_ddi_buf_trans.h"
>  #include "intel_display_types.h"
>  #include "intel_dp.h"
> -#include "intel_dp_mst.h"
>  #include "intel_dp_link_training.h"
> +#include "intel_dp_mst.h"
>  #include "intel_dpio_phy.h"
>  #include "intel_dsi.h"
> +#include "intel_fdi.h"
>  #include "intel_fifo_underrun.h"
>  #include "intel_gmbus.h"
>  #include "intel_hdcp.h"
> @@ -90,8 +91,8 @@ static int intel_ddi_hdmi_level(struct intel_encoder 
> *encoder,
>   * values in advance. This function programs the correct values for
>   * DP/eDP/FDI use cases.
>   */
> -static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
> -  const struct intel_crtc_state 
> *crtc_state)
> +void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
> +   const struct intel_crtc_state *crtc_state)
>  {
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   u32 iboost_bit = 0;
> @@ -153,8 +154,8 @@ static void intel_prepare_hdmi_ddi_buffers(struct 
> intel_encoder *encoder,
>  ddi_translations[level].trans2);
>  }
>  
> -static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> - enum port port)
> +void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> +  enum port port)
>  {
>   if (IS_BROXTON(dev_priv)) {
>   udelay(16);
> @@ -182,7 +183,7 @@ static void intel_wait_ddi_buf_active(struct 
> drm_i915_private *dev_priv,
>   port_name(port));
>  }
>  
> -static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> +u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
>  {
>   switch (pll->info->id) {
>   case DPLL_ID_WRPLL1:
> @@ -242,144 +243,6 @@ static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder 
> *encoder,
>   }
>  }
>  
> -/* Starting with Haswell, different DDI ports can work in FDI mode for
> - * connection to the PCH-located connectors. For this, it is necessary to 
> train
> - * both the DDI port and PCH receiver for the desired DDI buffer settings.
> - *
> - * The recommended port to work in FDI mode is DDI E, which we use here. 
> Also,
> - * please note that when FDI mode is active on DDI E, it shares 2 lines with
> - * DDI A (which is used for eDP)
> - */
> -
> -void hsw_fdi_link_train(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state)
> -{
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - u32 temp, i, rx_ctl_val, ddi_pll_sel;
> - int n_entries;
> -
> - intel_ddi_get_buf_trans_fdi(dev_priv, &n_entries);
> -
> - intel_prepare_dp_ddi_buffers(encoder, crtc_state);
> -
> - /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
> -  * mode set "sequence for CRT port" document:
> -  * - TP1 to TP2 time with the default value
> -  * - FDI delay to 90h
> -  *
> -  * WaFDIAutoLinkSetTimingOverrride:hsw
> -  */
> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
> -FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | 
> FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
> -
> - /* Enable the PCH Receiver FDI PLL */
> - rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
> -  FDI_RX_PLL_ENABLE |
> -  FDI_DP_PORT_WIDTH(crtc_s

Re: [Intel-gfx] [PATCH 04/11] drm/i915: refactor ddi translations into a separate file

2021-01-14 Thread Ville Syrjälä

On Thu, Jan 14, 2021 at 01:13:48PM +0200, Jani Nikula wrote:
> From: Dave Airlie 
> 
> Ville suggested this, these tables are probably better being
> standalone.
> 
> This fixes up the cnl/bxt interfaces to be like the others,
> the intel one I left alone since it has a few extra entrypoints.
> 
> v2 by Jani: fix intel_ddi_buf_trans.h header test
> 
> Signed-off-by: Dave Airlie 
> Signed-off-by: Jani Nikula 

Cool. Some pending patches will need a rebase but so be it.

Did a cursory scan and didn't spot any warts so
Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/Makefile |1 +
>  drivers/gpu/drm/i915/display/intel_ddi.c  | 1417 +
>  .../drm/i915/display/intel_ddi_buf_trans.c| 1358 
>  .../drm/i915/display/intel_ddi_buf_trans.h|  100 ++
>  4 files changed, 1471 insertions(+), 1405 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index e245a036613e..9e19395c8c8e 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -241,6 +241,7 @@ i915-y += \
>   display/icl_dsi.o \
>   display/intel_crt.o \
>   display/intel_ddi.o \
> + display/intel_ddi_buf_trans.o \
>   display/intel_dp.o \
>   display/intel_dp_aux_backlight.o \
>   display/intel_dp_hdcp.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index d714e8b34d52..1caf643e6400 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -33,6 +33,7 @@
>  #include "intel_combo_phy.h"
>  #include "intel_connector.h"
>  #include "intel_ddi.h"
> +#include "intel_ddi_buf_trans.h"
>  #include "intel_display_types.h"
>  #include "intel_dp.h"
>  #include "intel_dp_mst.h"
> @@ -52,12 +53,6 @@
>  #include "intel_tc.h"
>  #include "intel_vdsc.h"
>  
> -struct ddi_buf_trans {
> - u32 trans1; /* balance leg enable, de-emph level */
> - u32 trans2; /* vref sel, vswing */
> - u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
> -};
> -
>  static const u8 index_to_dp_signal_levels[] = {
>   [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
>   [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
> @@ -71,1389 +66,15 @@ static const u8 index_to_dp_signal_levels[] = {
>   [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
>  };
>  
> -/* HDMI/DVI modes ignore everything but the last 2 items. So we share
> - * them for both DP and FDI transports, allowing those ports to
> - * automatically adapt to HDMI connections as well
> - */
> -static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
> - { 0x00FF, 0x0006000E, 0x0 },
> - { 0x00D75FFF, 0x0005000A, 0x0 },
> - { 0x00C30FFF, 0x00040006, 0x0 },
> - { 0x80AAAFFF, 0x000B, 0x0 },
> - { 0x00FF, 0x0005000A, 0x0 },
> - { 0x00D75FFF, 0x000C0004, 0x0 },
> - { 0x80C30FFF, 0x000B, 0x0 },
> - { 0x00FF, 0x00040006, 0x0 },
> - { 0x80D75FFF, 0x000B, 0x0 },
> -};
> -
> -static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
> - { 0x00FF, 0x0007000E, 0x0 },
> - { 0x00D75FFF, 0x000F000A, 0x0 },
> - { 0x00C30FFF, 0x00060006, 0x0 },
> - { 0x00AAAFFF, 0x001E, 0x0 },
> - { 0x00FF, 0x000F000A, 0x0 },
> - { 0x00D75FFF, 0x00160004, 0x0 },
> - { 0x00C30FFF, 0x001E, 0x0 },
> - { 0x00FF, 0x00060006, 0x0 },
> - { 0x00D75FFF, 0x001E, 0x0 },
> -};
> -
> -static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
> - /* Idx  NT mV d T mV d  db  */
> - { 0x00FF, 0x0006000E, 0x0 },/* 0:   400 400 0   */
> - { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400 500 2   */
> - { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400 600 3.5 */
> - { 0x00FF, 0x0005000A, 0x0 },/* 3:   600 600 0   */
> - { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600 750 2   */
> - { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600 900 3.5 */
> - { 0x00FF, 0x00040006, 0x0 },/* 6:   800 800 0   */
> - { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800 10002   */
> - { 0x00FF, 0x00140005, 0x0 },/* 8:   850 850 0   */
> - { 0x00FF, 0x000C0004, 0x0 },/* 9:   900 900 0   */
> - { 0x00FF, 0x001C0003, 0x0 },/* 10:  950 950 0   */
> - { 0x80FF, 0x00030002, 0x0 },/* 11:  100010000   */
> -};
> -
> -static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
> - { 0x00FF, 0x0012, 0x0 },
> - { 0x00EBAFFF, 0x00020011, 0x0 },
> - { 0x00C71FFF, 0x0006000F, 0x0 },
> - { 0x00AAAFFF, 0x000E000A, 0x0 },
>

Re: [Intel-gfx] [PATCH] drm/i915: support two CSC module on gen11 and later

2021-01-14 Thread Ville Syrjälä

On Thu, Jan 14, 2021 at 05:22:36PM +0800, Lee Shawn C wrote:
> There are two CSC on pipeline on gen11 and later platform.
> User space application is allowed to enable CTM and RGB
> to YCbCr coversion at the same time now.
> 
> Cc: Ville Syrjala 
> Cc: Imre Deak 
> Cc: Jani Nikula 
> Cc: Cooper Chiou 
> Cc: Shankar Uma 
> 
> Signed-off-by: Lee Shawn C 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 1a0f00f37ca9..721d5ce1ed2b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8303,7 +8303,8 @@ static int intel_crtc_compute_config(struct intel_crtc 
> *crtc,
>   return -EINVAL;
>   }
>  
> - if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> + if ((INTEL_GEN(dev_priv) < 11) &&
> + (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
>pipe_config->hw.ctm) {

Didn't realize we had this check here. It should really be moved
into {ivb,glk}_color_check().

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 08/10] drm/i915/gt: Convert stats.active to plain unsigned int

2021-01-14 Thread Andi Shyti

Hi Chris,

On Wed, Jan 13, 2021 at 12:45:58PM +, Chris Wilson wrote:
> As context-in/out is now always serialised, we do not have to worry
> about concurrent enabling/disable of the busy-stats and can reduce the
> atomic_t active to a plain unsigned int, and the seqlock to a seqcount.
> 
> Signed-off-by: Chris Wilson 

looks correct...

Reviewed-by: Andi Shyti 

Thanks,
Andi
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[Intel-gfx] [PULL] drm-intel-gt-next

2021-01-14 Thread Joonas Lahtinen

Hi Dave & Daniel,

Here is the first PR for v5.12. There are quite a few patches
accumulated after the holidays as usual:

Most importantly there are fixes to the clear residual security
mitigations to avoid GPU hangs caused by them. Further there is
option to allow the user to decide to disable such mitigations
similar to CPU side (i915.mitigations=auto,!residuals), if they
are an expert user and wish to do so. Of course, usual caveats
apply to disabling any security mitigations!

For Tigerlake, a fix to reduce the likelihood of DMAR errors when
IOMMU is enabled (MTBF bump from 10 secs to hours) and correction
to detecting the device stepping. Addition of W/As for DG1 and TGL.

Tuning the RPS algorithm further to limit to RPe on parking an
engine. Plenty of refactoring, cleanups and optimizing code in
preparation of upcoming series. The usual amount of selftest and
documentation fixes.

Then there are 3 other fixes for user reported/visible bugs;
GPU hang due to wrong MOCS caching for index used by HW, false
error message for case where GuC firmware doesn't load on first
instance of the retry-loop and supplementing the GuC firmware
table for Cometlake SKUs.

Fixes for pre-emption on Gen8-era devices. Build and runtime
fixes for 32-bit machines.

Regards, Joonas

PS. After you merge this, I will proceed to backmerge drm-next so
that we can have a common topic branches for din and dign as
requested by Jani and Rodrigo.

***

drm-intel-gt-next-2021-01-14:

UAPI Changes:
- Deprecate I915_PMU_LAST and optimize state tracking (Tvrtko)

  Avoid relying on last item ABI marker in i915_drm.h, add a
  comment to mark as deprecated.

Driver Changes:

- Restore clear residuals security mitigations for Ivybridge and
  Baytrail (Chris)
- Close #1858: Allow sysadmin to choose applied GPU security mitigations
  through i915.mitigations=... similar to CPU (Chris)
- Fix for #2024: GPU hangs on HSW GT1 (Chris)
- Fix for #2707: Driver hang when editing UVs in Blender (Chris, Ville)
- Fix for #2797: False positive GuC loading error message (Chris)
- Fix for #2859: Missing GuC firmware for older Cometlakes (Chris)
- Lessen probability of GPU hang due to DMAR faults [reason 7,
  next page table ptr is invalid] on Tigerlake (Chris)
- Fix REVID macros for TGL to fetch correct stepping (Aditya)
- Limit frequency drop to RPe on parking (Chris, Edward)
- Limit W/A 1406941453 to TGL, RKL and DG1 (Swathi)
- Make W/A 22010271021 permanent on DG1 (Lucas)
- Implement W/A 16011163337 to prevent a HS/DS hang on DG1 (Swathi)
- Only disable preemption on gen8 render engines (Chris)
- Disable arbitration around Braswell's PDP updates (Chris)
- Disable arbitration on no-preempt requests (Chris)
- Check for arbitration after writing start seqno before busywaiting (Chris)
- Retain default context state across shrinking (Venkata, CQ)
- Fix mismatch between misplaced vma check and vma insert for 32-bit
  addressing userspaces (Chris, CQ)
- Propagate error for vmap() failure instead kernel NULL deref (Chris)
- Propagate error from cancelled submit due to context closure
  immediately (Chris)
- Fix RCU race on HWSP tracking per request (Chris)
- Clear CMD parser shadow and GPU reloc batches (Matt A)

- Populate logical context during first pin (Maarten)
- Optimistically prune dma-resv from the shrinker (Chris)
- Fix for virtual engine ownership race (Chris)
- Remove timeslice suppression to restore fairness for virtual engines (Chris)
- Rearrange IVB/HSW workarounds properly between GT and engine (Chris)
- Taint the reset mutex with the shrinker (Chris)
- Replace direct submit with direct call to tasklet (Chris)
- Multiple corrections to virtual engine dequeue and breadcrumbs code (Chris)
- Avoid wakeref from potentially hard IRQ context in PMU (Tvrtko)
- Use raw clock for RC6 time estimation in PMU (Tvrtko)
- Differentiate OOM failures from invalid map types (Chris)
- Fix Gen9 to have 64 MOCS entries similar to Gen11 (Chris)
- Ignore repeated attempts to suspend request flow across reset (Chris)
- Remove livelock from "do_idle_maps" VT-d W/A (Chris)
- Cancel the preemption timeout early in case engine reset fails (Chris)
- Code flow optimization in the scheduling code (Chris)
- Clear the execlists timers upon reset (Chris)
- Drain the breadcrumbs just once (Chris, Matt A)
- Track the overall GT awake/busy time (Chris)
- Tweak submission tasklet flushing to avoid starvation (Chris)
- Track timelines created using the HWSP to restore on resume (Chris)
- Use cmpxchg64 for 32b compatilibity for active tracking (Chris)
- Prefer recycling an idle GGTT fence to avoid GPU wait (Chris)

- Restructure GT code organization for clearer split between GuC
  and execlists (Chris, Daniele, John, Matt A)
- Remove GuC code that will remain unused by new interfaces (Matt B)
- Restructure the CS timestamp clocks code to local to GT (Chris)
- Fix error return paths in perf code (Zhang)
- Replace idr_init() by idr_init_base() in perf (Deepak)
- Fix shmem_pin_map error p

Re: [Intel-gfx] [PATCH] drm/i915/gt: Prune 'inline' from execlists

2021-01-14 Thread Mika Kuoppala

Chris Wilson  writes:

> Remove the extraneous inlines. The only split by the compiler that
> looked dubious was execlists_schedule_out, so push the code around
> slightly to move all the work into the out-of-line function.
>
> In a normal build, bloat-o-meter shows that only the
> execlists_schedule_out is contentious:
>
> add/remove: 1/0 grow/shrink: 0/2 up/down: 803/-1532 (-729)
> Function old new   delta
> __execlists_schedule_out   - 803+803
> execlists_submission_tasklet64885766-722
> execlists_reset_csb.constprop   1587 777-810
> Total: Before=1605815, After=1605086, chg -0.05%
>
> Signed-off-by: Chris Wilson 
> Cc: Jani Nikula 

Reviewed-by: Mika Kuoppala 

> ---
>  .../drm/i915/gt/intel_execlists_submission.c  | 63 +--
>  1 file changed, 29 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index d7d5a58990bb..33c7495b12b1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -230,8 +230,7 @@ active_request(const struct intel_timeline * const tl, 
> struct i915_request *rq)
>   return __active_request(tl, rq, 0);
>  }
>  
> -static inline void
> -ring_set_paused(const struct intel_engine_cs *engine, int state)
> +static void ring_set_paused(const struct intel_engine_cs *engine, int state)
>  {
>   /*
>* We inspect HWS_PREEMPT with a semaphore inside
> @@ -244,12 +243,12 @@ ring_set_paused(const struct intel_engine_cs *engine, 
> int state)
>   wmb();
>  }
>  
> -static inline struct i915_priolist *to_priolist(struct rb_node *rb)
> +static struct i915_priolist *to_priolist(struct rb_node *rb)
>  {
>   return rb_entry(rb, struct i915_priolist, node);
>  }
>  
> -static inline int rq_prio(const struct i915_request *rq)
> +static int rq_prio(const struct i915_request *rq)
>  {
>   return READ_ONCE(rq->sched.attr.priority);
>  }
> @@ -299,8 +298,8 @@ static int virtual_prio(const struct 
> intel_engine_execlists *el)
>   return rb ? rb_entry(rb, struct ve_node, rb)->prio : INT_MIN;
>  }
>  
> -static inline bool need_preempt(const struct intel_engine_cs *engine,
> - const struct i915_request *rq)
> +static bool need_preempt(const struct intel_engine_cs *engine,
> +  const struct i915_request *rq)
>  {
>   int last_prio;
>  
> @@ -351,7 +350,7 @@ static inline bool need_preempt(const struct 
> intel_engine_cs *engine,
>  queue_prio(&engine->execlists)) > last_prio;
>  }
>  
> -__maybe_unused static inline bool
> +__maybe_unused static bool
>  assert_priority_queue(const struct i915_request *prev,
> const struct i915_request *next)
>  {
> @@ -418,7 +417,7 @@ execlists_unwind_incomplete_requests(struct 
> intel_engine_execlists *execlists)
>   return __unwind_incomplete_requests(engine);
>  }
>  
> -static inline void
> +static void
>  execlists_context_status_change(struct i915_request *rq, unsigned long 
> status)
>  {
>   /*
> @@ -503,7 +502,7 @@ static void reset_active(struct i915_request *rq,
>   ce->lrc.lrca = lrc_update_regs(ce, engine, head);
>  }
>  
> -static inline struct intel_engine_cs *
> +static struct intel_engine_cs *
>  __execlists_schedule_in(struct i915_request *rq)
>  {
>   struct intel_engine_cs * const engine = rq->engine;
> @@ -549,7 +548,7 @@ __execlists_schedule_in(struct i915_request *rq)
>   return engine;
>  }
>  
> -static inline void execlists_schedule_in(struct i915_request *rq, int idx)
> +static void execlists_schedule_in(struct i915_request *rq, int idx)
>  {
>   struct intel_context * const ce = rq->context;
>   struct intel_engine_cs *old;
> @@ -608,9 +607,9 @@ static void kick_siblings(struct i915_request *rq, struct 
> intel_context *ce)
>   tasklet_hi_schedule(&ve->base.execlists.tasklet);
>  }
>  
> -static inline void __execlists_schedule_out(struct i915_request *rq)
> +static void __execlists_schedule_out(struct i915_request * const rq,
> +  struct intel_context * const ce)
>  {
> - struct intel_context * const ce = rq->context;
>   struct intel_engine_cs * const engine = rq->engine;
>   unsigned int ccid;
>  
> @@ -621,6 +620,7 @@ static inline void __execlists_schedule_out(struct 
> i915_request *rq)
>*/
>  
>   CE_TRACE(ce, "schedule-out, ccid:%x\n", ce->lrc.ccid);
> + GEM_BUG_ON(ce->inflight != engine);
>  
>   if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
>   lrc_check_regs(ce, engine, "after");
> @@ -660,10 +660,12 @@ static inline void __execlists_schedule_out(struct 
> i915_request *rq)
>*/
>   if (ce->engine != engine)
>   kick_siblings(rq, ce);
> +
> + WRITE_ONCE(ce->inflight,

Re: [Intel-gfx] [PATCH] drm/i915: Only enable DFP 4:4:4->4:2:0 conversion when outputting YCbCr 4:4:4

2021-01-14 Thread Ville Syrjälä

On Thu, Jan 14, 2021 at 09:27:35AM +0200, Jani Nikula wrote:
> On Mon, 11 Jan 2021, Ville Syrjala  wrote:
> > From: Ville Syrjälä 
> >
> > Let's not enable the 4:4:4->4:2:0 conversion bit in the DFP unless we're
> > actually outputting YCbCr 4:4:4. It would appear some protocol
> > converters blindy consult this bit even when the source is outputting
> > RGB, resulting in a visual mess.
> >
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2914
> > Signed-off-by: Ville Syrjälä 
> 
> Fixes: 181567aa9f0d ("drm/i915: Do YCbCr 444->420 conversion via DP protocol 
> converters")
> Cc:  # v5.10+
> 
> Right?

Not sure I should to add the stable tag directly since it apparently
applies cleanly but does not build. So needs a custom backport.

> 
> Reviewed-by: Jani Nikula 

Ta.

> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 4f190a82d4ad..aa30ef9f6906 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4368,8 +4368,8 @@ void intel_dp_configure_protocol_converter(struct 
> > intel_dp *intel_dp,
> > drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI 
> > mode to %s\n",
> > enableddisabled(intel_dp->has_hdmi_sink));
> >  
> > -   tmp = intel_dp->dfp.ycbcr_444_to_420 ?
> > -   DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
> > +   tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
> > +   intel_dp->dfp.ycbcr_444_to_420 ? 
> > DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
> >  
> > if (drm_dp_dpcd_writeb(&intel_dp->aux,
> >DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.BAT: failure for rebased refactor of intel_display

2021-01-14 Thread Patchwork

== Series Details ==

Series: rebased refactor of intel_display
URL   : https://patchwork.freedesktop.org/series/85867/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9607 -> Patchwork_19355


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19355 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19355, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19355/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_19355:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/fi-kbl-guc/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19355/fi-kbl-guc/igt@i915_pm_...@module-reload.html

  
Known issues


  Here are the changes found in Patchwork_19355 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rpm@module-reload:
- fi-byt-j1900:   [PASS][3] -> [INCOMPLETE][4] ([i915#142] / 
[i915#2405])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/fi-byt-j1900/igt@i915_pm_...@module-reload.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19355/fi-byt-j1900/igt@i915_pm_...@module-reload.html

  * igt@prime_vgem@basic-gtt:
- fi-tgl-y:   [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar 
issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/fi-tgl-y/igt@prime_v...@basic-gtt.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19355/fi-tgl-y/igt@prime_v...@basic-gtt.html

  * igt@runner@aborted:
- fi-byt-j1900:   NOTRUN -> [FAIL][7] ([i915#1814] / [i915#2505])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19355/fi-byt-j1900/igt@run...@aborted.html

  
 Possible fixes 

  * igt@prime_vgem@basic-fence-flip:
- fi-tgl-y:   [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +2 similar 
issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/fi-tgl-y/igt@prime_v...@basic-fence-flip.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19355/fi-tgl-y/igt@prime_v...@basic-fence-flip.html

  
  [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
  [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (41 -> 38)
--

  Missing(3): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9607 -> Patchwork_19355

  CI-20190529: 20190529
  CI_DRM_9607: 1cd1433e50924f963a31d50a0bfcccb1f872544f @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5957: 2a2b3418f7458dfa1fac255cc5c71603f617690a @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19355: 6a2d5102588a78b3ecc507cb351ecb1b74368cfe @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

6a2d5102588a drm/i915: migrate i9xx plane get config
c6eed4d66621 drm/i915: migrate pll enable/disable code to intel_dpll.[ch]
0d5e20703b44 drm/i915: move is_ccs_modifier to an inline
0845353b71f8 drm/i915: split fb scalable checks into g4x and skl versions
a4bbb4337935 drm/i915: move pipe update code into crtc.
e0e478e60136 drm/i915: migrate skl planes code new file (v3)
e44a3e487e50 drm/i915: migrate hsw fdi code to new file.
03c751a642be drm/i915: refactor ddi translations into a separate file
adc635930a19 drm/i915: split fdi code out from intel_display.c
c5a10aa1a6ad drm/i915: refactor pll code out into intel_dpll.c
604e87846b3b drm/i915: refactor some crtc code out of intel display. (v2)

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19355/index.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: support two CSC module on gen11 and later

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm/i915: support two CSC module on gen11 and later
URL   : https://patchwork.freedesktop.org/series/85847/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9605_full -> Patchwork_19352_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19352_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][1] ([i915#146] / [i915#198])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-skl4/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][2] -> [SKIP][3] ([i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9605/shard-tglb8/igt@gem_huc_c...@huc-copy.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-tglb6/igt@gem_huc_c...@huc-copy.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo:
- shard-glk:  NOTRUN -> [SKIP][4] ([fdo#109271]) +12 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-glk2/igt@kms_...@pipe-c-ccs-on-another-bo.html

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic:
- shard-skl:  NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111304]) +1 
similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-skl5/igt@kms_...@pipe-c-crc-sprite-planes-basic.html

  * igt@kms_chamelium@vga-hpd-after-suspend:
- shard-skl:  NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +12 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-skl4/igt@kms_chamel...@vga-hpd-after-suspend.html

  * igt@kms_color@pipe-a-ctm-0-75:
- shard-skl:  [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9605/shard-skl3/igt@kms_co...@pipe-a-ctm-0-75.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-skl5/igt@kms_co...@pipe-a-ctm-0-75.html

  * igt@kms_color@pipe-d-ctm-blue-to-red:
- shard-kbl:  NOTRUN -> [SKIP][9] ([fdo#109271]) +27 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-kbl6/igt@kms_co...@pipe-d-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-kbl:  NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +2 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-kbl6/igt@kms_color_chamel...@pipe-a-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-glk:  NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +4 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-glk2/igt@kms_color_chamel...@pipe-a-ctm-green-to-red.html

  * igt@kms_color_chamelium@pipe-a-gamma:
- shard-iclb: NOTRUN -> [SKIP][12] ([fdo#109284] / [fdo#111827])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-iclb7/igt@kms_color_chamel...@pipe-a-gamma.html

  * igt@kms_content_protection@lic:
- shard-kbl:  NOTRUN -> [TIMEOUT][13] ([i915#1319])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-kbl6/igt@kms_content_protect...@lic.html

  * igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque:
- shard-skl:  NOTRUN -> [FAIL][14] ([i915#54]) +2 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-skl5/igt@kms_cursor_...@pipe-a-cursor-alpha-opaque.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-skl:  [PASS][15] -> [INCOMPLETE][16] ([i915#2295] / 
[i915#300])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9605/shard-skl9/igt@kms_cursor_...@pipe-a-cursor-suspend.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-skl3/igt@kms_cursor_...@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-random:
- shard-skl:  [PASS][17] -> [FAIL][18] ([i915#54]) +4 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9605/shard-skl9/igt@kms_cursor_...@pipe-c-cursor-64x21-random.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-skl10/igt@kms_cursor_...@pipe-c-cursor-64x21-random.html

  * igt@kms_cursor_crc@pipe-d-cursor-256x85-onscreen:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109278]) +1 similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-iclb7/igt@kms_cursor_...@pipe-d-cursor-256x85-onscreen.html

  * igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
- shard-skl:  NOTRUN -> [SKIP][20] ([fdo#109271]) +94 similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19352/shard-skl4/igt@kms_cursor_edge_w...@pipe-d-128x128-right-edge.html

  * igt@kms_cu

[Intel-gfx] [CI 2/5] drm/i915: Drop i915_request.lock serialisation around await_start

2021-01-14 Thread Chris Wilson

Originally, we used the signal->lock as a means of following the
previous link in its timeline and peeking at the previous fence.
However, we have replaced the explicit serialisation with a series of
very careful probes that anticipate the links being deleted and the
fences recycled before we are able to acquire a strong reference to it.
We do not need the signal->lock crutch anymore, nor want the contention.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Reviewed-by: Andi Shyti 
---
 drivers/gpu/drm/i915/i915_request.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index 784c05ac5cca..973eceabbcca 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -969,9 +969,16 @@ i915_request_await_start(struct i915_request *rq, struct 
i915_request *signal)
if (i915_request_started(signal))
return 0;
 
+   /*
+* The caller holds a reference on @signal, but we do not serialise
+* against it being retired and removed from the lists.
+*
+* We do not hold a reference to the request before @signal, and
+* so must be very careful to ensure that it is not _recycled_ as
+* we follow the link backwards.
+*/
fence = NULL;
rcu_read_lock();
-   spin_lock_irq(&signal->lock);
do {
struct list_head *pos = READ_ONCE(signal->link.prev);
struct i915_request *prev;
@@ -1002,7 +1009,6 @@ i915_request_await_start(struct i915_request *rq, struct 
i915_request *signal)
 
fence = &prev->fence;
} while (0);
-   spin_unlock_irq(&signal->lock);
rcu_read_unlock();
if (!fence)
return 0;
-- 
2.20.1

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[Intel-gfx] [CI 3/5] drm/i915/gem: Reduce ctx->engine_mutex for reading the clone source

2021-01-14 Thread Chris Wilson

When cloning the engines from the source context, we need to ensure that
the engines are not freed as we copy them, and that the flags we clone
from the source correspond with the engines we copy across. To do this
we need only take a reference to the src->engines, rather than hold the
src->engine_mutex, so long as we verify that nothing changed under the
read.

Signed-off-by: Chris Wilson 
Reviewed-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 24 +
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index cac0c52fc681..4a709c625ccb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -717,7 +717,8 @@ __create_context(struct drm_i915_private *i915)
 }
 
 static inline struct i915_gem_engines *
-__context_engines_await(const struct i915_gem_context *ctx)
+__context_engines_await(const struct i915_gem_context *ctx,
+   bool *user_engines)
 {
struct i915_gem_engines *engines;
 
@@ -726,6 +727,10 @@ __context_engines_await(const struct i915_gem_context *ctx)
engines = rcu_dereference(ctx->engines);
GEM_BUG_ON(!engines);
 
+   if (user_engines)
+   *user_engines = i915_gem_context_user_engines(ctx);
+
+   /* successful await => strong mb */
if (unlikely(!i915_sw_fence_await(&engines->fence)))
continue;
 
@@ -749,7 +754,7 @@ context_apply_all(struct i915_gem_context *ctx,
struct intel_context *ce;
int err = 0;
 
-   e = __context_engines_await(ctx);
+   e = __context_engines_await(ctx, NULL);
for_each_gem_engine(ce, e, it) {
err = fn(ce, data);
if (err)
@@ -1075,7 +1080,7 @@ static int context_barrier_task(struct i915_gem_context 
*ctx,
return err;
}
 
-   e = __context_engines_await(ctx);
+   e = __context_engines_await(ctx, NULL);
if (!e) {
i915_active_release(&cb->base);
return -ENOENT;
@@ -2095,11 +2100,14 @@ static int copy_ring_size(struct intel_context *dst,
 static int clone_engines(struct i915_gem_context *dst,
 struct i915_gem_context *src)
 {
-   struct i915_gem_engines *e = i915_gem_context_lock_engines(src);
-   struct i915_gem_engines *clone;
+   struct i915_gem_engines *clone, *e;
bool user_engines;
unsigned long n;
 
+   e = __context_engines_await(src, &user_engines);
+   if (!e)
+   return -ENOENT;
+
clone = alloc_engines(e->num_engines);
if (!clone)
goto err_unlock;
@@ -2141,9 +2149,7 @@ static int clone_engines(struct i915_gem_context *dst,
}
}
clone->num_engines = n;
-
-   user_engines = i915_gem_context_user_engines(src);
-   i915_gem_context_unlock_engines(src);
+   i915_sw_fence_complete(&e->fence);
 
/* Serialised by constructor */
engines_idle_release(dst, rcu_replace_pointer(dst->engines, clone, 1));
@@ -2154,7 +2160,7 @@ static int clone_engines(struct i915_gem_context *dst,
return 0;
 
 err_unlock:
-   i915_gem_context_unlock_engines(src);
+   i915_sw_fence_complete(&e->fence);
return -ENOMEM;
 }
 
-- 
2.20.1

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[Intel-gfx] [CI 4/5] drm/i915/gem: Reduce ctx->engines_mutex for get_engines()

2021-01-14 Thread Chris Wilson

Take a snapshot of the ctx->engines, so we can avoid taking the
ctx->engines_mutex for a mere read in get_engines().

Signed-off-by: Chris Wilson 
Reviewed-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 39 +
 1 file changed, 8 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 4a709c625ccb..4d2f40cf237b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1843,27 +1843,6 @@ set_engines(struct i915_gem_context *ctx,
return 0;
 }
 
-static struct i915_gem_engines *
-__copy_engines(struct i915_gem_engines *e)
-{
-   struct i915_gem_engines *copy;
-   unsigned int n;
-
-   copy = alloc_engines(e->num_engines);
-   if (!copy)
-   return ERR_PTR(-ENOMEM);
-
-   for (n = 0; n < e->num_engines; n++) {
-   if (e->engines[n])
-   copy->engines[n] = intel_context_get(e->engines[n]);
-   else
-   copy->engines[n] = NULL;
-   }
-   copy->num_engines = n;
-
-   return copy;
-}
-
 static int
 get_engines(struct i915_gem_context *ctx,
struct drm_i915_gem_context_param *args)
@@ -1871,19 +1850,17 @@ get_engines(struct i915_gem_context *ctx,
struct i915_context_param_engines __user *user;
struct i915_gem_engines *e;
size_t n, count, size;
+   bool user_engines;
int err = 0;
 
-   err = mutex_lock_interruptible(&ctx->engines_mutex);
-   if (err)
-   return err;
+   e = __context_engines_await(ctx, &user_engines);
+   if (!e)
+   return -ENOENT;
 
-   e = NULL;
-   if (i915_gem_context_user_engines(ctx))
-   e = __copy_engines(i915_gem_context_engines(ctx));
-   mutex_unlock(&ctx->engines_mutex);
-   if (IS_ERR_OR_NULL(e)) {
+   if (!user_engines) {
+   i915_sw_fence_complete(&e->fence);
args->size = 0;
-   return PTR_ERR_OR_ZERO(e);
+   return 0;
}
 
count = e->num_engines;
@@ -1934,7 +1911,7 @@ get_engines(struct i915_gem_context *ctx,
args->size = size;
 
 err_free:
-   free_engines(e);
+   i915_sw_fence_complete(&e->fence);
return err;
 }
 
-- 
2.20.1

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[Intel-gfx] [CI 5/5] drm/i915: Reduce test_and_set_bit to set_bit in i915_request_submit()

2021-01-14 Thread Chris Wilson

Avoid the full blown memory barrier of test_and_set_bit() by noting the
completed request and removing it from the lists.

Signed-off-by: Chris Wilson 
Reviewed-by: Andi Shyti 
---
 drivers/gpu/drm/i915/i915_request.c | 16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index 973eceabbcca..22e39d938f17 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -551,8 +551,10 @@ bool __i915_request_submit(struct i915_request *request)
 * dropped upon retiring. (Otherwise if resubmit a *retired*
 * request, this would be a horrible use-after-free.)
 */
-   if (__i915_request_is_complete(request))
-   goto xfer;
+   if (__i915_request_is_complete(request)) {
+   list_del_init(&request->sched.link);
+   goto active;
+   }
 
if (unlikely(intel_context_is_banned(request->context)))
i915_request_set_error_once(request, -EIO);
@@ -587,11 +589,11 @@ bool __i915_request_submit(struct i915_request *request)
engine->serial++;
result = true;
 
-xfer:
-   if (!test_and_set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)) {
-   list_move_tail(&request->sched.link, &engine->active.requests);
-   clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags);
-   }
+   GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
+   list_move_tail(&request->sched.link, &engine->active.requests);
+active:
+   clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags);
+   set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
 
/*
 * XXX Rollback bonded-execution on __i915_request_unsubmit()?
-- 
2.20.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [CI 1/5] drm/i915: Mark up protected uses of 'i915_request_completed'

2021-01-14 Thread Chris Wilson

When we know that we are inside the timeline mutex, or inside the
submission flow (under active.lock or the holder's rcu lock), we know
that the rq->hwsp is stable and we can use the simpler direct version.

Signed-off-by: Chris Wilson 
Reviewed-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c   |  4 ++--
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  6 +++---
 .../drm/i915/gt/intel_execlists_submission.c  |  4 ++--
 drivers/gpu/drm/i915/gt/intel_reset.c |  3 +--
 .../gpu/drm/i915/gt/intel_ring_submission.c   |  4 +++-
 drivers/gpu/drm/i915/gt/intel_timeline.c  |  4 ++--
 drivers/gpu/drm/i915/i915_request.c   | 19 +--
 drivers/gpu/drm/i915/i915_scheduler.c |  2 +-
 9 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 68f58762d5e3..cac0c52fc681 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -408,7 +408,7 @@ __active_engine(struct i915_request *rq, struct 
intel_engine_cs **active)
}
 
if (i915_request_is_active(rq)) {
-   if (!i915_request_completed(rq))
+   if (!__i915_request_is_complete(rq))
*active = locked;
ret = true;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index be2c285a0ac7..d098fc0c14ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -517,8 +517,8 @@ static void print_signals(struct intel_breadcrumbs *b, 
struct drm_printer *p)
list_for_each_entry_rcu(rq, &ce->signals, signal_link)
drm_printf(p, "\t[%llx:%llx%s] @ %dms\n",
   rq->fence.context, rq->fence.seqno,
-  i915_request_completed(rq) ? "!" :
-  i915_request_started(rq) ? "*" :
+  __i915_request_is_complete(rq) ? "!" :
+  __i915_request_has_started(rq) ? "*" :
   "",
   jiffies_to_msecs(jiffies - 
rq->emitted_jiffies));
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index fa76602f9852..3fe44cdfe20a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1811,7 +1811,7 @@ intel_engine_find_active_request(struct intel_engine_cs 
*engine)
struct intel_timeline *tl = request->context->timeline;
 
list_for_each_entry_from_reverse(request, &tl->requests, link) {
-   if (i915_request_completed(request))
+   if (__i915_request_is_complete(request))
break;
 
active = request;
@@ -1822,10 +1822,10 @@ intel_engine_find_active_request(struct intel_engine_cs 
*engine)
return active;
 
list_for_each_entry(request, &engine->active.requests, sched.link) {
-   if (i915_request_completed(request))
+   if (__i915_request_is_complete(request))
continue;
 
-   if (!i915_request_started(request))
+   if (!__i915_request_has_started(request))
continue;
 
/* More than one preemptible request may match! */
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index d7d5a58990bb..e28f32661df4 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3296,7 +3296,7 @@ static void rcu_virtual_context_destroy(struct 
work_struct *wrk)
 
old = fetch_and_zero(&ve->request);
if (old) {
-   GEM_BUG_ON(!i915_request_completed(old));
+   GEM_BUG_ON(!__i915_request_is_complete(old));
__i915_request_submit(old);
i915_request_put(old);
}
@@ -3573,7 +3573,7 @@ static void virtual_submit_request(struct i915_request 
*rq)
}
 
if (ve->request) { /* background completion from preempt-to-busy */
-   GEM_BUG_ON(!i915_request_completed(ve->request));
+   GEM_BUG_ON(!__i915_request_is_complete(ve->request));
__i915_request_submit(ve->request);
i915_request_put(ve->request);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 9d177297db79..bba385497d7b 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -151,8 +151,7 @@ sta

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Exercise relative mmio paths to non-privileged registers

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm/i915/selftests: Exercise relative mmio paths to non-privileged 
registers
URL   : https://patchwork.freedesktop.org/series/85841/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9605_full -> Patchwork_19350_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19350_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@core_hotunplug@unbind-rebind:
- shard-hsw:  NOTRUN -> [WARN][1] ([i915#2283])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-hsw6/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_ctx_persistence@legacy-engines-cleanup:
- shard-hsw:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +2 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-hsw4/igt@gem_ctx_persiste...@legacy-engines-cleanup.html

  * igt@gem_exec_params@secure-non-root:
- shard-tglb: NOTRUN -> [SKIP][3] ([fdo#112283])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-tglb3/igt@gem_exec_par...@secure-non-root.html

  * igt@gem_exec_reloc@basic-many-active@vcs0:
- shard-hsw:  NOTRUN -> [FAIL][4] ([i915#2389]) +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-hsw4/igt@gem_exec_reloc@basic-many-act...@vcs0.html

  * igt@gem_exec_whisper@basic-queues-forked:
- shard-glk:  [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9605/shard-glk6/igt@gem_exec_whis...@basic-queues-forked.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-glk8/igt@gem_exec_whis...@basic-queues-forked.html

  * igt@i915_module_load@reload-with-fault-injection:
- shard-skl:  [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar 
issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9605/shard-skl1/igt@i915_module_l...@reload-with-fault-injection.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-skl5/igt@i915_module_l...@reload-with-fault-injection.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-tglb: NOTRUN -> [SKIP][9] ([fdo#111644] / [i915#1397] / 
[i915#2411])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-tglb3/igt@i915_pm_...@dpms-mode-unset-non-lpsp.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo:
- shard-glk:  NOTRUN -> [SKIP][10] ([fdo#109271]) +12 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-glk3/igt@kms_...@pipe-c-ccs-on-another-bo.html

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic:
- shard-skl:  NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111304]) +1 
similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-skl10/igt@kms_...@pipe-c-crc-sprite-planes-basic.html

  * igt@kms_chamelium@hdmi-hpd-with-enabled-mode:
- shard-hsw:  NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) 
+14 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-hsw6/igt@kms_chamel...@hdmi-hpd-with-enabled-mode.html

  * igt@kms_chamelium@vga-hpd-after-suspend:
- shard-skl:  NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) 
+10 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-skl9/igt@kms_chamel...@vga-hpd-after-suspend.html

  * igt@kms_color@pipe-b-degamma:
- shard-tglb: NOTRUN -> [FAIL][14] ([i915#1149])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-tglb3/igt@kms_co...@pipe-b-degamma.html

  * igt@kms_color@pipe-d-ctm-blue-to-red:
- shard-kbl:  NOTRUN -> [SKIP][15] ([fdo#109271]) +27 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-kbl4/igt@kms_co...@pipe-d-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +2 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-kbl4/igt@kms_color_chamel...@pipe-a-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-glk:  NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +4 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-glk3/igt@kms_color_chamel...@pipe-a-ctm-green-to-red.html

  * igt@kms_color_chamelium@pipe-a-gamma:
- shard-iclb: NOTRUN -> [SKIP][18] ([fdo#109284] / [fdo#111827])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19350/shard-iclb2/igt@kms_color_chamel...@pipe-a-gamma.html

  * igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes:
- shard-tglb: NOTRUN -> [SKIP][19] ([fdo#109284] / [fdo#111827]) +1 
similar issue
   [19]:

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for rebased refactor of intel_display

2021-01-14 Thread Patchwork

== Series Details ==

Series: rebased refactor of intel_display
URL   : https://patchwork.freedesktop.org/series/85867/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:714:28: warning: symbol 
'bdw_get_buf_trans_edp' was not declared. Should it be static?
+drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:728:28: warning: symbol 
'skl_get_buf_trans_dp' was not declared. Should it be static?
+drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:745:28: warning: symbol 
'kbl_get_buf_trans_dp' was not declared. Should it be static?
+drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:766:28: warning: symbol 
'skl_get_buf_trans_edp' was not declared. Should it be static?
+drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:798:28: warning: symbol 
'skl_get_buf_trans_hdmi' was not declared. Should it be static?
+drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:813:5: warning: symbol 
'skl_buf_trans_num_entries' was not declared. Should it be static?
+drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 
279040
+drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 
'wakeref_auto_timeout' - unexpected unlock
+./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:869:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for rebased refactor of intel_display

2021-01-14 Thread Patchwork

== Series Details ==

Series: rebased refactor of intel_display
URL   : https://patchwork.freedesktop.org/series/85867/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
604e87846b3b drm/i915: refactor some crtc code out of intel display. (v2)
-:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#32: 
new file mode 100644

-:332: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & 
recovery code rather than BUG() or BUG_ON()
#332: FILE: drivers/gpu/drm/i915/display/intel_crtc.c:296:
+   BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||

-:333: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written 
"dev_priv->pipe_to_crtc_mapping[pipe]"
#333: FILE: drivers/gpu/drm/i915/display/intel_crtc.c:297:
+  dev_priv->pipe_to_crtc_mapping[pipe] != NULL);

-:339: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & 
recovery code rather than BUG() or BUG_ON()
#339: FILE: drivers/gpu/drm/i915/display/intel_crtc.c:303:
+   BUG_ON(i9xx_plane >= 
ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||

-:340: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written 
"dev_priv->plane_to_crtc_mapping[i9xx_plane]"
#340: FILE: drivers/gpu/drm/i915/display/intel_crtc.c:304:
+  dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);

-:346: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#346: FILE: drivers/gpu/drm/i915/display/intel_crtc.c:310:
+   drm_crtc_create_scaling_filter_property(&crtc->base,
+   BIT(DRM_SCALING_FILTER_DEFAULT) 
|

total: 0 errors, 3 warnings, 3 checks, 714 lines checked
c5a10aa1a6ad drm/i915: refactor pll code out into intel_dpll.c
-:1577: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the 
previous line
#1577: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1847:
+   return dev_priv->vbt.lvds_use_ssc
+   && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);

-:1587: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#1587: 
new file mode 100644

-:1613: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#1613: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:22:
+};
+static const struct intel_limit intel_limits_i8xx_dac = {

-:1678: CHECK:LINE_SPACING: Please don't use multiple blank lines
#1678: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:87:
+
+

-:2250: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#2250: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:659:
+   for (clock.m1 = limit->m1.min; clock.m1 <= 
limit->m1.max; clock.m1++) {

-:2321: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#2321: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:730:
+   if (m2 > INT_MAX/clock.m1)
^

-:2418: CHECK:BRACES: braces {} should be used on all arms of this statement
#2418: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:827:
+   if (IS_PINEVIEW(dev_priv))
[...]
+   else {
[...]

-:2420: CHECK:BRACES: Unbalanced braces around else statement
#2420: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:829:
+   else {

-:2538: CHECK:LINE_SPACING: Please don't use multiple blank lines
#2538: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:947:
+
+

total: 0 errors, 2 warnings, 7 checks, 2919 lines checked
adc635930a19 drm/i915: split fdi code out from intel_display.c
-:778: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#778: 
new file mode 100644

-:874: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & 
recovery code rather than BUG() or BUG_ON()
#874: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:92:
+   BUG();

-:879: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#879: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:97:
+int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *pipe_config)

-:911: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#911: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:129:
+   if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
   ^

-:912: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#912: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:130:
+   pipe_config->pipe_bpp -= 2*3;
  ^

-:961: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see 
Documentation/timers/timers-howto.rst
#961: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:179:
+   udelay(1000);

-:966: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#966: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:184:
+  intel_de_read(dev_priv

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers

2021-01-14 Thread Patchwork

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/selftests: Exercise relative 
mmio paths to non-privileged registers
URL   : https://patchwork.freedesktop.org/series/85865/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9607 -> Patchwork_19354


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/index.html

Known issues


  Here are the changes found in Patchwork_19354 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_hangman@error-state-basic:
- fi-tgl-y:   [PASS][1] -> [DMESG-WARN][2] ([i915#402])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/fi-tgl-y/igt@i915_hang...@error-state-basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/fi-tgl-y/igt@i915_hang...@error-state-basic.html

  * igt@i915_selftest@live@active:
- fi-kbl-soraka:  [PASS][3] -> [DMESG-FAIL][4] ([i915#2291] / 
[i915#666])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/fi-kbl-soraka/igt@i915_selftest@l...@active.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/fi-kbl-soraka/igt@i915_selftest@l...@active.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u:   [PASS][5] -> [FAIL][6] ([i915#2128])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Possible fixes 

  * igt@gem_render_tiled_blits@basic:
- fi-tgl-y:   [DMESG-WARN][7] ([i915#402]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html

  
  [i915#2128]: https://gitlab.freedesktop.org/drm/intel/issues/2128
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666


Participating hosts (41 -> 38)
--

  Missing(3): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9607 -> Patchwork_19354

  CI-20190529: 20190529
  CI_DRM_9607: 1cd1433e50924f963a31d50a0bfcccb1f872544f @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5957: 2a2b3418f7458dfa1fac255cc5c71603f617690a @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19354: 633f3050f2b666de909387521bc86f0df7e11f81 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

633f3050f2b6 drm/i915/selftests: Exercise cross-process context isolation
e31030c86d7e drm/i915/selftests: Exercise relative mmio paths to non-privileged 
registers

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/index.html
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Re: [Intel-gfx] [PATCH v6 01/64] drm/i915: Do not share hwsp across contexts any more, v6

2021-01-14 Thread Tvrtko Ursulin



On 05/01/2021 15:34, Maarten Lankhorst wrote:

Instead of sharing pages with breadcrumbs, give each timeline a
single page. This allows unrelated timelines not to share locks
any more during command submission.

As an additional benefit, seqno wraparound no longer requires
i915_vma_pin, which means we no longer need to worry about a
potential -EDEADLK at a point where we are ready to submit.

Changes since v1:
- Fix erroneous i915_vma_acquire that should be a i915_vma_release (ickle).
- Extra check for completion in intel_read_hwsp().
Changes since v2:
- Fix inconsistent indent in hwsp_alloc() (kbuild)
- memset entire cacheline to 0.
Changes since v3:
- Do same in intel_timeline_reset_seqno(), and clflush for good measure.
Changes since v4:
- Use refcounting on timeline, instead of relying on i915_active.
- Fix waiting on kernel requests.
Changes since v5:
- Bump amount of slots to maximum (256), for best wraparounds.
- Add hwsp_offset to i915_request to fix potential wraparound hang.
- Ensure timeline wrap test works with the changes.
- Assign hwsp in intel_timeline_read_hwsp() within the rcu lock to
   fix a hang.

Signed-off-by: Maarten Lankhorst 
Reviewed-by: Thomas Hellström  #v1
Reported-by: kernel test robot 
---
  drivers/gpu/drm/i915/gt/gen2_engine_cs.c  |   2 +-
  drivers/gpu/drm/i915/gt/gen6_engine_cs.c  |   8 +-
  drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |  12 +-
  drivers/gpu/drm/i915/gt/intel_engine_cs.c |   1 +
  drivers/gpu/drm/i915/gt/intel_gt_types.h  |   4 -
  drivers/gpu/drm/i915/gt/intel_timeline.c  | 422 --
  .../gpu/drm/i915/gt/intel_timeline_types.h|  17 +-
  drivers/gpu/drm/i915/gt/selftest_engine_cs.c  |   5 +-
  drivers/gpu/drm/i915/gt/selftest_timeline.c   |  83 ++--
  drivers/gpu/drm/i915/i915_request.c   |   4 -
  drivers/gpu/drm/i915/i915_request.h   |  17 +-
  11 files changed, 160 insertions(+), 415 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
index b491a64919c8..9646200d2792 100644
--- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
@@ -143,7 +143,7 @@ static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, 
u32 *cs,
   int flush, int post)
  {
GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != 
rq->engine->status_page.vma);
-   
GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != 
I915_GEM_HWS_SEQNO_ADDR);
+   GEM_BUG_ON(offset_in_page(rq->hwsp_seqno) != I915_GEM_HWS_SEQNO_ADDR);
  
  	*cs++ = MI_FLUSH;
  
diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c

index ce38d1bcaba3..dd094e21bb51 100644
--- a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
@@ -161,7 +161,7 @@ u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 
*cs)
 PIPE_CONTROL_DC_FLUSH_ENABLE |
 PIPE_CONTROL_QW_WRITE |
 PIPE_CONTROL_CS_STALL);
-   *cs++ = i915_request_active_timeline(rq)->hwsp_offset |
+   *cs++ = i915_request_active_offset(rq) |


"Active offset" is maybe a bit non-descriptive. How about 
i915_request_hwsp_seqno()?



PIPE_CONTROL_GLOBAL_GTT;
*cs++ = rq->fence.seqno;
  
@@ -359,7 +359,7 @@ u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)

 PIPE_CONTROL_QW_WRITE |
 PIPE_CONTROL_GLOBAL_GTT_IVB |
 PIPE_CONTROL_CS_STALL);
-   *cs++ = i915_request_active_timeline(rq)->hwsp_offset;
+   *cs++ = i915_request_active_offset(rq);
*cs++ = rq->fence.seqno;
  
  	*cs++ = MI_USER_INTERRUPT;

@@ -374,7 +374,7 @@ u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 
*cs)
  u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
  {
GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != 
rq->engine->status_page.vma);
-   
GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != 
I915_GEM_HWS_SEQNO_ADDR);
+   GEM_BUG_ON(offset_in_page(rq->hwsp_seqno) != I915_GEM_HWS_SEQNO_ADDR);
  
  	*cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;

*cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
@@ -394,7 +394,7 @@ u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 
*cs)
int i;
  
  	GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);

-   
GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != 
I915_GEM_HWS_SEQNO_ADDR);
+   GEM_BUG_ON(offset_in_page(rq->hwsp_seqno) != I915_GEM_HWS_SEQNO_ADDR);
  
  	*cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |

MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 1972dd5dca00..33eaa0203b1d 100644
--- a/drivers/gpu

Re: [Intel-gfx] [PATCH 01/10] drm/i915: Mark up protected uses of 'i915_request_completed'

2021-01-14 Thread Chris Wilson

Quoting Andi Shyti (2021-01-14 03:01:15)
> Hi Chris,
> 
> > diff --git a/drivers/gpu/drm/i915/i915_request.c 
> > b/drivers/gpu/drm/i915/i915_request.c
> > index 0b1a46a0d866..784c05ac5cca 100644
> > --- a/drivers/gpu/drm/i915/i915_request.c
> > +++ b/drivers/gpu/drm/i915/i915_request.c
> > @@ -276,7 +276,7 @@ static void remove_from_engine(struct i915_request *rq)
> >  
> >  bool i915_request_retire(struct i915_request *rq)
> >  {
> > - if (!i915_request_completed(rq))
> > + if (!__i915_request_is_complete(rq))
> 
> 
> >   return false;
> >  
> >   RQ_TRACE(rq, "\n");
> > @@ -342,8 +342,7 @@ void i915_request_retire_upto(struct i915_request *rq)
> >   struct i915_request *tmp;
> >  
> >   RQ_TRACE(rq, "\n");
> > -
> > - GEM_BUG_ON(!i915_request_completed(rq));
> > + GEM_BUG_ON(!__i915_request_is_complete(rq));
> 
> I might be a bit shallow, but where is the lock here?

This holds the request->context->timeline->mutex.

The locking is basically split between frontend/backend:

  construction/destruction - under the timeline->mutex

  execution - under the engine->active.lock (coordinates with
  timeline->mutex)

At all other times, RCU protected access (using the SLAB_TYPESAFE_BY_RCU
so approach with caution).
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Reapply ppgtt enabling after engine resets

2021-01-14 Thread Patchwork

== Series Details ==

Series: drm/i915/gt: Reapply ppgtt enabling after engine resets
URL   : https://patchwork.freedesktop.org/series/85864/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9606 -> Patchwork_19353


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/index.html

Known issues


  Here are the changes found in Patchwork_19353 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u:   NOTRUN -> [SKIP][1] ([fdo#109271]) +22 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html

  * igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u:   NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html

  * igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u:   NOTRUN -> [WARN][3] ([i915#2283])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271]) +30 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +1 similar 
issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9606/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- fi-snb-2600:[DMESG-WARN][8] ([i915#2772]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9606/fi-snb-2600/igt@gem_exec_susp...@basic-s0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/fi-snb-2600/igt@gem_exec_susp...@basic-s0.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6600u:   [INCOMPLETE][10] ([i915#198]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9606/fi-skl-6600u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/fi-skl-6600u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  * igt@prime_vgem@basic-userptr:
- fi-tgl-y:   [DMESG-WARN][12] ([i915#402]) -> [PASS][13] +2 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9606/fi-tgl-y/igt@prime_v...@basic-userptr.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/fi-tgl-y/igt@prime_v...@basic-userptr.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
  [i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (41 -> 38)
--

  Missing(3): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9606 -> Patchwork_19353

  CI-20190529: 20190529
  CI_DRM_9606: 64adac0d663a51c3e1faa8c97c9cd03dacddecdd @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5957: 2a2b3418f7458dfa1fac255cc5c71603f617690a @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19353: bdf293fc51d50e24235cdc3617f6ea33fe9f4962 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

bdf293fc51d5 drm/i915/gt: Reapply ppgtt enabling after engine resets

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19353/index.html
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Re: [Intel-gfx] [PATCH 07/10] drm/i915/gt: Extract busy-stats for ring-scheduler

2021-01-14 Thread Chris Wilson

Quoting Andi Shyti (2021-01-14 03:02:25)
> Hi Chris,
> 
> On Wed, Jan 13, 2021 at 12:45:57PM +, Chris Wilson wrote:
> > Lift the busy-stats context-in/out implementation out of intel_lrc, so
> > that we can reuse it for other scheduler implementations.
> > 
> > Signed-off-by: Chris Wilson 
> > ---
> >  drivers/gpu/drm/i915/gt/intel_engine_stats.h  | 49 +++
> >  .../drm/i915/gt/intel_execlists_submission.c  | 34 +
> >  2 files changed, 50 insertions(+), 33 deletions(-)
> >  create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_stats.h
> 
> this looks like just a copy paste...

It's closer now indeed. It's not quite identical yet, as in one case we
have boolean, the other an uint counter. (There's a third case for class
runtime stats where it would be an atomic_t.) So not quite hitting the
rule of 3 for adequate generalisation, though maybe with some magic
macro constructors...
-Chris
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[Intel-gfx] [PATCH 2/2] drm/i915: Make GEM errors non-fatal by default

2021-01-14 Thread Chris Wilson

While immensely convenient for developing to only tackle the first
error, and not be flooded by repeated or secondiary issues, many more
casual testers are not setup to remotely capture debug traces. For those
testers, it is more beneficial to keep the system running in the remote
chance that they are able to extract the original debug logs.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/Kconfig.debug | 16 
 drivers/gpu/drm/i915/i915_gem.h|  9 -
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.debug 
b/drivers/gpu/drm/i915/Kconfig.debug
index 3701bae5b855..4005f6619bec 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -41,6 +41,7 @@ config DRM_I915_DEBUG
select SW_SYNC # signaling validation framework (igt/syncobj*)
select DRM_I915_WERROR
select DRM_I915_DEBUG_GEM
+   select DRM_I915_DEBUG_GEM_ONCE
select DRM_I915_DEBUG_MMIO
select DRM_I915_DEBUG_RUNTIME_PM
select DRM_I915_SW_FENCE_DEBUG_OBJECTS
@@ -80,6 +81,21 @@ config DRM_I915_DEBUG_GEM
 
  If in doubt, say "N".
 
+config DRM_I915_DEBUG_GEM_ONCE
+   bool "Make a GEM debug failure fatal"
+   default n
+   depends on DRM_I915_DEBUG_GEM
+   help
+ During development, we often only want the very first failure
+ as that would otherwise be lost in the deluge of subsequent
+ failures. However, more causal testers may not want to trigger
+ a hard BUG_ON and hope that the system remains sufficiently usable
+ to capture a bug report in situ.
+
+ Recommended for driver developers only.
+
+ If in doubt, say "N".
+
 config DRM_I915_ERRLOG_GEM
bool "Insert extra logging (very verbose) for common GEM errors"
default n
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index a4cad3f154ca..e622aee6e4be 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -38,11 +38,18 @@ struct drm_i915_private;
 
 #define GEM_SHOW_DEBUG() drm_debug_enabled(DRM_UT_DRIVER)
 
+#ifdef CONFIG_DRM_I915_DEBUG_GEM_ONCE
+#define __GEM_BUG(cond) BUG()
+#else
+#define __GEM_BUG(cond) \
+   WARN(1, "%s:%d GEM_BUG_ON(%s)\n", __func__, __LINE__, __stringify(cond))
+#endif
+
 #define GEM_BUG_ON(condition) do { if (unlikely((condition))) {\
GEM_TRACE_ERR("%s:%d GEM_BUG_ON(%s)\n", \
  __func__, __LINE__, __stringify(condition)); \
GEM_TRACE_DUMP(); \
-   BUG(); \
+   __GEM_BUG(condition); \
} \
} while(0)
 #define GEM_WARN_ON(expr) WARN_ON(expr)
-- 
2.20.1

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[Intel-gfx] [PATCH 1/2] drm/i915: Add DEBUG_GEM to the recommended CI config

2021-01-14 Thread Chris Wilson

Now that i915 compiles cleanly with Werror, we can enforce enabling
DEBUG_GEM when selecting the default debug config.

Signed-off-by: Chris Wilson 
Cc: Jani Nikula 
---
 drivers/gpu/drm/i915/Kconfig.debug | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.debug 
b/drivers/gpu/drm/i915/Kconfig.debug
index 0fb7fd0ef717..3701bae5b855 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -39,10 +39,12 @@ config DRM_I915_DEBUG
select DRM_DEBUG_SELFTEST
select DMABUF_SELFTESTS
select SW_SYNC # signaling validation framework (igt/syncobj*)
+   select DRM_I915_WERROR
+   select DRM_I915_DEBUG_GEM
+   select DRM_I915_DEBUG_MMIO
+   select DRM_I915_DEBUG_RUNTIME_PM
select DRM_I915_SW_FENCE_DEBUG_OBJECTS
select DRM_I915_SELFTEST
-   select DRM_I915_DEBUG_RUNTIME_PM
-   select DRM_I915_DEBUG_MMIO
select BROKEN # for prototype uAPI
default n
help
-- 
2.20.1

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[Intel-gfx] [PATCH] drm/i915: Add DEBUG_GEM to the recommended CI config

2021-01-14 Thread Chris Wilson

Now that i915 compiles cleanly with Werror, we can enforce enabling
DEBUG_GEM when selecting the default debug config.

Signed-off-by: Chris Wilson 
Cc: Jani Nikula 
---
 drivers/gpu/drm/i915/Kconfig.debug | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.debug 
b/drivers/gpu/drm/i915/Kconfig.debug
index 0fb7fd0ef717..3701bae5b855 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -39,10 +39,12 @@ config DRM_I915_DEBUG
select DRM_DEBUG_SELFTEST
select DMABUF_SELFTESTS
select SW_SYNC # signaling validation framework (igt/syncobj*)
+   select DRM_I915_WERROR
+   select DRM_I915_DEBUG_GEM
+   select DRM_I915_DEBUG_MMIO
+   select DRM_I915_DEBUG_RUNTIME_PM
select DRM_I915_SW_FENCE_DEBUG_OBJECTS
select DRM_I915_SELFTEST
-   select DRM_I915_DEBUG_RUNTIME_PM
-   select DRM_I915_DEBUG_MMIO
select BROKEN # for prototype uAPI
default n
help
-- 
2.20.1

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Re: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree

2021-01-14 Thread Thomas Zimmermann


Hi

Am 14.01.21 um 01:31 schrieb Stephen Rothwell:

Hi all,

After merging the drm-misc tree, today's linux-next build (arm
multi_v7_defconfig) failed like this:

drivers/gpu/drm/drm_cache.c: In function 'drm_need_swiotlb':
drivers/gpu/drm/drm_cache.c:202:6: error: implicit declaration of function 
'mem_encrypt_active' [-Werror=implicit-function-declaration]
   202 |  if (mem_encrypt_active())
   |  ^~


Caused by commit

   3abc66706385 ("drm: Implement drm_need_swiotlb() in drm_cache.c")

I have used the drm-misc tree from next-20210107 again for today.


Sorry for the breakage. Fixed in drm-misc-next.

Best regards
Thomas





--
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Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer



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[Intel-gfx] [PATCH 11/11] drm/i915: migrate i9xx plane get config

2021-01-14 Thread Jani Nikula

From: Dave Airlie 

Migrate this code out like the skylake code.

!!! FIXME: Dave's s-o-b !!!

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/i9xx_plane.c| 119 +++
 drivers/gpu/drm/i915/display/i9xx_plane.h|   4 +
 drivers/gpu/drm/i915/display/intel_display.c | 119 ---
 3 files changed, 123 insertions(+), 119 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c 
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 6c568079f492..a063a92f04dc 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -698,3 +698,122 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
return ERR_PTR(ret);
 }
 
+static int i9xx_format_to_fourcc(int format)
+{
+   switch (format) {
+   case DISPPLANE_8BPP:
+   return DRM_FORMAT_C8;
+   case DISPPLANE_BGRA555:
+   return DRM_FORMAT_ARGB1555;
+   case DISPPLANE_BGRX555:
+   return DRM_FORMAT_XRGB1555;
+   case DISPPLANE_BGRX565:
+   return DRM_FORMAT_RGB565;
+   default:
+   case DISPPLANE_BGRX888:
+   return DRM_FORMAT_XRGB;
+   case DISPPLANE_RGBX888:
+   return DRM_FORMAT_XBGR;
+   case DISPPLANE_BGRA888:
+   return DRM_FORMAT_ARGB;
+   case DISPPLANE_RGBA888:
+   return DRM_FORMAT_ABGR;
+   case DISPPLANE_BGRX101010:
+   return DRM_FORMAT_XRGB2101010;
+   case DISPPLANE_RGBX101010:
+   return DRM_FORMAT_XBGR2101010;
+   case DISPPLANE_BGRA101010:
+   return DRM_FORMAT_ARGB2101010;
+   case DISPPLANE_RGBA101010:
+   return DRM_FORMAT_ABGR2101010;
+   case DISPPLANE_RGBX161616:
+   return DRM_FORMAT_XBGR16161616F;
+   }
+}
+
+void
+i9xx_get_initial_plane_config(struct intel_crtc *crtc,
+ struct intel_initial_plane_config *plane_config)
+{
+   struct drm_device *dev = crtc->base.dev;
+   struct drm_i915_private *dev_priv = to_i915(dev);
+   struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+   enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
+   enum pipe pipe;
+   u32 val, base, offset;
+   int fourcc, pixel_format;
+   unsigned int aligned_height;
+   struct drm_framebuffer *fb;
+   struct intel_framebuffer *intel_fb;
+
+   if (!plane->get_hw_state(plane, &pipe))
+   return;
+
+   drm_WARN_ON(dev, pipe != crtc->pipe);
+
+   intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
+   if (!intel_fb) {
+   drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
+   return;
+   }
+
+   fb = &intel_fb->base;
+
+   fb->dev = dev;
+
+   val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
+
+   if (INTEL_GEN(dev_priv) >= 4) {
+   if (val & DISPPLANE_TILED) {
+   plane_config->tiling = I915_TILING_X;
+   fb->modifier = I915_FORMAT_MOD_X_TILED;
+   }
+
+   if (val & DISPPLANE_ROTATE_180)
+   plane_config->rotation = DRM_MODE_ROTATE_180;
+   }
+
+   if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
+   val & DISPPLANE_MIRROR)
+   plane_config->rotation |= DRM_MODE_REFLECT_X;
+
+   pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
+   fourcc = i9xx_format_to_fourcc(pixel_format);
+   fb->format = drm_format_info(fourcc);
+
+   if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+   offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
+   base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 
0xf000;
+   } else if (INTEL_GEN(dev_priv) >= 4) {
+   if (plane_config->tiling)
+   offset = intel_de_read(dev_priv,
+  DSPTILEOFF(i9xx_plane));
+   else
+   offset = intel_de_read(dev_priv,
+  DSPLINOFF(i9xx_plane));
+   base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 
0xf000;
+   } else {
+   base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
+   }
+   plane_config->base = base;
+
+   val = intel_de_read(dev_priv, PIPESRC(pipe));
+   fb->width = ((val >> 16) & 0xfff) + 1;
+   fb->height = ((val >> 0) & 0xfff) + 1;
+
+   val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
+   fb->pitches[0] = val & 0xffc0;
+
+   aligned_height = intel_fb_align_height(fb, 0, fb->height);
+
+   plane_config->size = fb->pitches[0] * aligned_height;
+
+   drm_dbg_kms(&dev_priv->drm,
+   "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 
0x%x\n",
+   crtc->base.name, plane->base.name, fb->width, fb->height,
+   fb->format->cpp[0] * 8, b

[Intel-gfx] [PATCH 10/11] drm/i915: migrate pll enable/disable code to intel_dpll.[ch]

2021-01-14 Thread Jani Nikula

From: Dave Airlie 

This moves the older i9xx/vlv/chv enable/disable to dpll file.

!!! FIXME: Dave's s-o-b !!!

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_display.c | 512 ---
 drivers/gpu/drm/i915/display/intel_display.h |   3 -
 drivers/gpu/drm/i915/display/intel_dp.c  |   1 +
 drivers/gpu/drm/i915/display/intel_dpll.c| 509 ++
 drivers/gpu/drm/i915/display/intel_dpll.h|  18 +
 drivers/gpu/drm/i915/display/intel_pps.c |   1 +
 6 files changed, 529 insertions(+), 515 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 7398927e1627..8abd49cf9c2b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -109,10 +109,6 @@ static void i9xx_set_pipeconf(const struct 
intel_crtc_state *crtc_state);
 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
-static void vlv_prepare_pll(struct intel_crtc *crtc,
-   const struct intel_crtc_state *pipe_config);
-static void chv_prepare_pll(struct intel_crtc *crtc,
-   const struct intel_crtc_state *pipe_config);
 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 struct drm_modeset_acquire_ctx *ctx);
@@ -565,224 +561,6 @@ static void assert_pch_ports_disabled(struct 
drm_i915_private *dev_priv,
assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
 }
 
-static void _vlv_enable_pll(struct intel_crtc *crtc,
-   const struct intel_crtc_state *pipe_config)
-{
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   enum pipe pipe = crtc->pipe;
-
-   intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
-   intel_de_posting_read(dev_priv, DPLL(pipe));
-   udelay(150);
-
-   if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
-   drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
-}
-
-static void vlv_enable_pll(struct intel_crtc *crtc,
-  const struct intel_crtc_state *pipe_config)
-{
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   enum pipe pipe = crtc->pipe;
-
-   assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
-
-   /* PLL is protected by panel, make sure we can write it */
-   assert_panel_unlocked(dev_priv, pipe);
-
-   if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
-   _vlv_enable_pll(crtc, pipe_config);
-
-   intel_de_write(dev_priv, DPLL_MD(pipe),
-  pipe_config->dpll_hw_state.dpll_md);
-   intel_de_posting_read(dev_priv, DPLL_MD(pipe));
-}
-
-
-static void _chv_enable_pll(struct intel_crtc *crtc,
-   const struct intel_crtc_state *pipe_config)
-{
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   enum pipe pipe = crtc->pipe;
-   enum dpio_channel port = vlv_pipe_to_channel(pipe);
-   u32 tmp;
-
-   vlv_dpio_get(dev_priv);
-
-   /* Enable back the 10bit clock to display controller */
-   tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
-   tmp |= DPIO_DCLKP_EN;
-   vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
-
-   vlv_dpio_put(dev_priv);
-
-   /*
-* Need to wait > 100ns between dclkp clock enable bit and PLL enable.
-*/
-   udelay(1);
-
-   /* Enable PLL */
-   intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
-
-   /* Check PLL is locked */
-   if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
-   drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
-}
-
-static void chv_enable_pll(struct intel_crtc *crtc,
-  const struct intel_crtc_state *pipe_config)
-{
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   enum pipe pipe = crtc->pipe;
-
-   assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
-
-   /* PLL is protected by panel, make sure we can write it */
-   assert_panel_unlocked(dev_priv, pipe);
-
-   if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
-   _chv_enable_pll(crtc, pipe_config);
-
-   if (pipe != PIPE_A) {
-   /*
-* WaPixelRepeatModeFixForC0:chv
-*
-* DPLLCMD is AWOL. Use chicken bits to propagate
-* the value from DPLLBMD to either pipe B or C.
-*/
-   intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
-   intel_de_write(dev_priv, DPLL_MD(PIPE_B),
-

Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [01/11] drm/i915: refactor some crtc code out of intel display. (v2)

2021-01-14 Thread Jani Nikula

On Thu, 14 Jan 2021, Patchwork  wrote:
> == Series Details ==
>
> Series: series starting with [01/11] drm/i915: refactor some crtc code out of 
> intel display. (v2)
> URL   : https://patchwork.freedesktop.org/series/85846/
> State : failure
>
> == Summary ==
>
> Applying: drm/i915: refactor some crtc code out of intel display. (v2)
> Applying: drm/i915: refactor pll code out into intel_dpll.c
> Applying: drm/i915: split fdi code out from intel_display.c
> Applying: drm/i915: refactor ddi translations into a separate file
> Applying: drm/i915: migrate hsw fdi code to new file.
> Applying: drm/i915: migrate skl planes code new file (v3)
> error: sha1 information is lacking or useless (drivers/gpu/drm/i915/Makefile).
> error: could not build fake ancestor
> hint: Use 'git am --show-current-patch=diff' to see the failed patch
> Patch failed at 0006 drm/i915: migrate skl planes code new file (v3)
> When you have resolved this problem, run "git am --continue".
> If you prefer to skip this patch, run "git am --skip" instead.
> To restore the original branch and stop patching, run "git am --abort".

My bad, just pushed some stuff that conflicted, I rebased and resent the
series: https://patchwork.freedesktop.org/series/85867/

BR,
Jani.


>
>
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[Intel-gfx] [PATCH 07/11] drm/i915: move pipe update code into crtc.

2021-01-14 Thread Jani Nikula

From: Dave Airlie 

Daniel suggested this should move here.

Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_crtc.c   | 230 
 drivers/gpu/drm/i915/display/intel_sprite.c | 228 ---
 2 files changed, 230 insertions(+), 228 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c 
b/drivers/gpu/drm/i915/display/intel_crtc.c
index eb478712c381..8825f960a121 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -10,6 +10,9 @@
 #include 
 #include 
 
+#include "i915_trace.h"
+#include "i915_vgpu.h"
+
 #include "intel_atomic.h"
 #include "intel_atomic_plane.h"
 #include "intel_color.h"
@@ -17,7 +20,9 @@
 #include "intel_cursor.h"
 #include "intel_display_debugfs.h"
 #include "intel_display_types.h"
+#include "intel_dsi.h"
 #include "intel_pipe_crc.h"
+#include "intel_psr.h"
 #include "intel_sprite.h"
 #include "i9xx_plane.h"
 #include "skl_universal_plane.h"
@@ -332,3 +337,228 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, 
enum pipe pipe)
 
return ret;
 }
+
+int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
+int usecs)
+{
+   /* paranoia */
+   if (!adjusted_mode->crtc_htotal)
+   return 1;
+
+   return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
+   1000 * adjusted_mode->crtc_htotal);
+}
+
+/**
+ * intel_pipe_update_start() - start update of a set of display registers
+ * @new_crtc_state: the new crtc state
+ *
+ * Mark the start of an update to pipe registers that should be updated
+ * atomically regarding vblank. If the next vblank will happens within
+ * the next 100 us, this function waits until the vblank passes.
+ *
+ * After a successful call to this function, interrupts will be disabled
+ * until a subsequent call to intel_pipe_update_end(). That is done to
+ * avoid random delays.
+ */
+void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
+{
+   struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   const struct drm_display_mode *adjusted_mode = 
&new_crtc_state->hw.adjusted_mode;
+   long timeout = msecs_to_jiffies_timeout(1);
+   int scanline, min, max, vblank_start;
+   wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
+   bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || 
IS_CHERRYVIEW(dev_priv)) &&
+   intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
+   DEFINE_WAIT(wait);
+   u32 psr_status;
+
+   if (new_crtc_state->uapi.async_flip)
+   return;
+
+   vblank_start = adjusted_mode->crtc_vblank_start;
+   if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
+   vblank_start = DIV_ROUND_UP(vblank_start, 2);
+
+   /* FIXME needs to be calibrated sensibly */
+   min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
+ VBLANK_EVASION_TIME_US);
+   max = vblank_start - 1;
+
+   if (min <= 0 || max <= 0)
+   goto irq_disable;
+
+   if (drm_WARN_ON(&dev_priv->drm, drm_crtc_vblank_get(&crtc->base)))
+   goto irq_disable;
+
+   /*
+* Wait for psr to idle out after enabling the VBL interrupts
+* VBL interrupts will start the PSR exit and prevent a PSR
+* re-entry as well.
+*/
+   if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
+   drm_err(&dev_priv->drm,
+   "PSR idle timed out 0x%x, atomic update may fail\n",
+   psr_status);
+
+   local_irq_disable();
+
+   crtc->debug.min_vbl = min;
+   crtc->debug.max_vbl = max;
+   trace_intel_pipe_update_start(crtc);
+
+   for (;;) {
+   /*
+* prepare_to_wait() has a memory barrier, which guarantees
+* other CPUs can see the task state update by the time we
+* read the scanline.
+*/
+   prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
+
+   scanline = intel_get_crtc_scanline(crtc);
+   if (scanline < min || scanline > max)
+   break;
+
+   if (!timeout) {
+   drm_err(&dev_priv->drm,
+   "Potential atomic update failure on pipe %c\n",
+   pipe_name(crtc->pipe));
+   break;
+   }
+
+   local_irq_enable();
+
+   timeout = schedule_timeout(timeout);
+
+   local_irq_disable();
+   }
+
+   finish_wait(wq, &wait);
+
+   drm_crtc_vblank_put(&crtc->base);
+
+   /*
+* On VLV/CHV DSI the scanline counter would appear to
+* increment approx. 1/3 o

[Intel-gfx] [PATCH 09/11] drm/i915: move is_ccs_modifier to an inline

2021-01-14 Thread Jani Nikula

From: Dave Airlie 

There is no need for this to be out of line.

Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_display.c   | 8 
 drivers/gpu/drm/i915/display/intel_display.h   | 1 -
 drivers/gpu/drm/i915/display/intel_display_types.h | 8 
 3 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index ab9d164345e5..7398927e1627 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1791,14 +1791,6 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
}
 }
 
-bool is_ccs_modifier(u64 modifier)
-{
-   return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
-  modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
-  modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-  modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
-}
-
 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
 {
return DIV_ROUND_UP(fb->pitches[skl_ccs_to_main_plane(fb, ccs_plane)],
diff --git a/drivers/gpu/drm/i915/display/intel_display.h 
b/drivers/gpu/drm/i915/display/intel_display.h
index 0b2fed58badf..f4214e161a9d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -508,7 +508,6 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n, bool fec_enable);
-bool is_ccs_modifier(u64 modifier);
 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
  u32 pixel_format, u64 modifier);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 179c277e5cf7..a2cd4bf9e246 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1862,6 +1862,14 @@ static inline u32 intel_fdi_link_freq(struct 
drm_i915_private *dev_priv,
return dev_priv->fdi_pll_freq;
 }
 
+static inline bool is_ccs_modifier(u64 modifier)
+{
+   return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+  modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+  modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+  modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+}
+
 static inline bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
 {
if (!is_ccs_modifier(fb->modifier))
-- 
2.20.1

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[Intel-gfx] [PATCH 08/11] drm/i915: split fb scalable checks into g4x and skl versions

2021-01-14 Thread Jani Nikula

From: Dave Airlie 

This just cleans these up a bit.

Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_sprite.c| 7 +++
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c 
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 7d779402cef7..9995bf6c39b9 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1345,19 +1345,18 @@ g4x_plane_get_hw_state(struct intel_plane *plane,
return ret;
 }
 
-static bool intel_fb_scalable(const struct drm_framebuffer *fb)
+static bool g4x_fb_scalable(const struct drm_framebuffer *fb)
 {
if (!fb)
return false;
 
switch (fb->format->format) {
case DRM_FORMAT_C8:
-   return false;
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
case DRM_FORMAT_XBGR16161616F:
case DRM_FORMAT_ABGR16161616F:
-   return INTEL_GEN(to_i915(fb->dev)) >= 11;
+   return false;
default:
return true;
}
@@ -1434,7 +1433,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
int max_scale = DRM_PLANE_HELPER_NO_SCALING;
int ret;
 
-   if (intel_fb_scalable(plane_state->hw.fb)) {
+   if (g4x_fb_scalable(plane_state->hw.fb)) {
if (INTEL_GEN(dev_priv) < 7) {
min_scale = 1;
max_scale = 16 << 16;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index f9659079ac18..fb590580223e 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1645,7 +1645,7 @@ static int skl_check_plane_surface(struct 
intel_plane_state *plane_state)
return 0;
 }
 
-static bool intel_fb_scalable(const struct drm_framebuffer *fb)
+static bool skl_fb_scalable(const struct drm_framebuffer *fb)
 {
if (!fb)
return false;
@@ -1678,7 +1678,7 @@ static int skl_plane_check(struct intel_crtc_state 
*crtc_state,
return ret;
 
/* use scaler when colorkey is not required */
-   if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
+   if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
min_scale = 1;
max_scale = skl_plane_max_scale(dev_priv, fb);
}
-- 
2.20.1

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[Intel-gfx] [PATCH 05/11] drm/i915: migrate hsw fdi code to new file.

2021-01-14 Thread Jani Nikula

From: Dave Airlie 

Daniel asked for this, but it's a bit messy and I'm not sure
how best to clean it up yet.

Signed-off-by: Dave Airlie 
[Jani: also moved fdi buf trans to intel_fdi.c.]
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_crt.c |   1 +
 drivers/gpu/drm/i915/display/intel_ddi.c | 151 ++-
 drivers/gpu/drm/i915/display/intel_ddi.h |   8 +-
 drivers/gpu/drm/i915/display/intel_fdi.c | 139 +
 drivers/gpu/drm/i915/display/intel_fdi.h |   3 +
 5 files changed, 156 insertions(+), 146 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c 
b/drivers/gpu/drm/i915/display/intel_crt.c
index 4934edd51cb0..077ebc7e6396 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -38,6 +38,7 @@
 #include "intel_crt.h"
 #include "intel_ddi.h"
 #include "intel_display_types.h"
+#include "intel_fdi.h"
 #include "intel_fifo_underrun.h"
 #include "intel_gmbus.h"
 #include "intel_hotplug.h"
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1caf643e6400..61ac1e1b7b55 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -36,10 +36,11 @@
 #include "intel_ddi_buf_trans.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
-#include "intel_dp_mst.h"
 #include "intel_dp_link_training.h"
+#include "intel_dp_mst.h"
 #include "intel_dpio_phy.h"
 #include "intel_dsi.h"
+#include "intel_fdi.h"
 #include "intel_fifo_underrun.h"
 #include "intel_gmbus.h"
 #include "intel_hdcp.h"
@@ -90,8 +91,8 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
  * values in advance. This function programs the correct values for
  * DP/eDP/FDI use cases.
  */
-static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
-const struct intel_crtc_state 
*crtc_state)
+void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 iboost_bit = 0;
@@ -153,8 +154,8 @@ static void intel_prepare_hdmi_ddi_buffers(struct 
intel_encoder *encoder,
   ddi_translations[level].trans2);
 }
 
-static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
-   enum port port)
+void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
+enum port port)
 {
if (IS_BROXTON(dev_priv)) {
udelay(16);
@@ -182,7 +183,7 @@ static void intel_wait_ddi_buf_active(struct 
drm_i915_private *dev_priv,
port_name(port));
 }
 
-static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
+u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 {
switch (pll->info->id) {
case DPLL_ID_WRPLL1:
@@ -242,144 +243,6 @@ static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder 
*encoder,
}
 }
 
-/* Starting with Haswell, different DDI ports can work in FDI mode for
- * connection to the PCH-located connectors. For this, it is necessary to train
- * both the DDI port and PCH receiver for the desired DDI buffer settings.
- *
- * The recommended port to work in FDI mode is DDI E, which we use here. Also,
- * please note that when FDI mode is active on DDI E, it shares 2 lines with
- * DDI A (which is used for eDP)
- */
-
-void hsw_fdi_link_train(struct intel_encoder *encoder,
-   const struct intel_crtc_state *crtc_state)
-{
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   u32 temp, i, rx_ctl_val, ddi_pll_sel;
-   int n_entries;
-
-   intel_ddi_get_buf_trans_fdi(dev_priv, &n_entries);
-
-   intel_prepare_dp_ddi_buffers(encoder, crtc_state);
-
-   /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
-* mode set "sequence for CRT port" document:
-* - TP1 to TP2 time with the default value
-* - FDI delay to 90h
-*
-* WaFDIAutoLinkSetTimingOverrride:hsw
-*/
-   intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
-  FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | 
FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
-
-   /* Enable the PCH Receiver FDI PLL */
-   rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
-FDI_RX_PLL_ENABLE |
-FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
-   intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
-   intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
-   udelay(220);
-
-   /* Switch from Rawclk to PCDclk */
-   rx_ctl_val |= FDI_PCDCLK;
-   intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
-
-   /* Configure Po

[Intel-gfx] [PATCH 03/11] drm/i915: split fdi code out from intel_display.c

2021-01-14 Thread Jani Nikula

From: Dave Airlie 

This just refactors out the fdi code to a separate file.

Signed-off-by: Dave Airlie 
[Jani: cleaned up intel_fdi.h a bit.]
Signed-off-by: Jani Nikula 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/display/intel_display.c  | 685 +-
 .../drm/i915/display/intel_display_types.h|   9 +
 drivers/gpu/drm/i915/display/intel_fdi.c  | 683 +
 drivers/gpu/drm/i915/display/intel_fdi.h  |  22 +
 5 files changed, 718 insertions(+), 682 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_fdi.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_fdi.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2479ab2ffb09..e245a036613e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -210,6 +210,7 @@ i915-y += \
display/intel_dpll_mgr.o \
display/intel_dsb.o \
display/intel_fbc.o \
+   display/intel_fdi.o \
display/intel_fifo_underrun.o \
display/intel_frontbuffer.o \
display/intel_global_state.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index f4d9ccaafcb3..a2fa7a219c4a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -74,6 +74,7 @@
 #include "intel_display_types.h"
 #include "intel_dp_link_training.h"
 #include "intel_fbc.h"
+#include "intel_fdi.h"
 #include "intel_fbdev.h"
 #include "intel_fifo_underrun.h"
 #include "intel_frontbuffer.h"
@@ -173,16 +174,6 @@ static void intel_update_czclk(struct drm_i915_private 
*dev_priv)
dev_priv->czclk_freq);
 }
 
-/* units of 100MHz */
-static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
-  const struct intel_crtc_state *pipe_config)
-{
-   if (HAS_DDI(dev_priv))
-   return pipe_config->port_clock; /* SPLL */
-   else
-   return dev_priv->fdi_pll_freq;
-}
-
 /* WA Display #0827: Gen9:all */
 static void
 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
@@ -3727,532 +3718,6 @@ static void icl_set_pipe_chicken(struct intel_crtc 
*crtc)
intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
 }
 
-static void intel_fdi_normal_train(struct intel_crtc *crtc)
-{
-   struct drm_device *dev = crtc->base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
-   enum pipe pipe = crtc->pipe;
-   i915_reg_t reg;
-   u32 temp;
-
-   /* enable normal train */
-   reg = FDI_TX_CTL(pipe);
-   temp = intel_de_read(dev_priv, reg);
-   if (IS_IVYBRIDGE(dev_priv)) {
-   temp &= ~FDI_LINK_TRAIN_NONE_IVB;
-   temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
-   } else {
-   temp &= ~FDI_LINK_TRAIN_NONE;
-   temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
-   }
-   intel_de_write(dev_priv, reg, temp);
-
-   reg = FDI_RX_CTL(pipe);
-   temp = intel_de_read(dev_priv, reg);
-   if (HAS_PCH_CPT(dev_priv)) {
-   temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
-   temp |= FDI_LINK_TRAIN_NORMAL_CPT;
-   } else {
-   temp &= ~FDI_LINK_TRAIN_NONE;
-   temp |= FDI_LINK_TRAIN_NONE;
-   }
-   intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
-
-   /* wait one idle pattern time */
-   intel_de_posting_read(dev_priv, reg);
-   udelay(1000);
-
-   /* IVB wants error correction enabled */
-   if (IS_IVYBRIDGE(dev_priv))
-   intel_de_write(dev_priv, reg,
-  intel_de_read(dev_priv, reg) | 
FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
-}
-
-/* The FDI link training functions for ILK/Ibexpeak. */
-static void ilk_fdi_link_train(struct intel_crtc *crtc,
-  const struct intel_crtc_state *crtc_state)
-{
-   struct drm_device *dev = crtc->base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
-   enum pipe pipe = crtc->pipe;
-   i915_reg_t reg;
-   u32 temp, tries;
-
-   /* FDI needs bits from pipe first */
-   assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
-
-   /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
-  for train result */
-   reg = FDI_RX_IMR(pipe);
-   temp = intel_de_read(dev_priv, reg);
-   temp &= ~FDI_RX_SYMBOL_LOCK;
-   temp &= ~FDI_RX_BIT_LOCK;
-   intel_de_write(dev_priv, reg, temp);
-   intel_de_read(dev_priv, reg);
-   udelay(150);
-
-   /* enable CPU FDI TX and PCH FDI RX */
-   reg = FDI_TX_CTL(pipe);
-   temp = intel_de_read(dev_priv, reg);
-   temp &= ~FDI_DP_PORT_WIDTH_MASK;
-   temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
-   temp &= ~FDI_LINK_TRAIN_NONE;
-   temp |= FDI_LINK_TRAIN_PAT

[Intel-gfx] [PATCH 02/11] drm/i915: refactor pll code out into intel_dpll.c

2021-01-14 Thread Jani Nikula

From: Dave Airlie 

This pulls a large chunk of the pll calculation code out of
intel_display.c to a new file.

One function makes sense to be an inline, otherwise this
is pretty much a straight copy cover. Also all the
remaining hooks for g45 and older end up the same now.

Signed-off-by: Dave Airlie 
[Jani: cleaned up intel_dpll.h a bit, de-duped intel_panel_use_ssc().]
Signed-off-by: Jani Nikula 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/Makefile |1 +
 drivers/gpu/drm/i915/display/intel_display.c  | 1402 +
 drivers/gpu/drm/i915/display/intel_display.h  |3 +
 .../drm/i915/display/intel_display_types.h|   13 +
 drivers/gpu/drm/i915/display/intel_dpll.c | 1363 
 drivers/gpu/drm/i915/display/intel_dpll.h |   23 +
 6 files changed, 1414 insertions(+), 1391 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dpll.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_dpll.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 44b4f052dc0b..2479ab2ffb09 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -206,6 +206,7 @@ i915-y += \
display/intel_display.o \
display/intel_display_power.o \
display/intel_dpio_phy.o \
+   display/intel_dpll.o \
display/intel_dpll_mgr.o \
display/intel_dsb.o \
display/intel_fbc.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index dfec9170d69d..f4d9ccaafcb3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -48,6 +48,7 @@
 #include "display/intel_display_debugfs.h"
 #include "display/intel_dp.h"
 #include "display/intel_dp_mst.h"
+#include "display/intel_dpll.h"
 #include "display/intel_dpll_mgr.h"
 #include "display/intel_dsi.h"
 #include "display/intel_dvo.h"
@@ -115,17 +116,6 @@ static void ilk_pfit_enable(const struct intel_crtc_state 
*crtc_state);
 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 struct drm_modeset_acquire_ctx *ctx);
 
-struct intel_limit {
-   struct {
-   int min, max;
-   } dot, vco, n, m, m1, m2, p, p1;
-
-   struct {
-   int dot_limit;
-   int p2_slow, p2_fast;
-   } p2;
-};
-
 /* returns HPLL frequency in kHz */
 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 {
@@ -193,271 +183,6 @@ static u32 intel_fdi_link_freq(struct drm_i915_private 
*dev_priv,
return dev_priv->fdi_pll_freq;
 }
 
-static const struct intel_limit intel_limits_i8xx_dac = {
-   .dot = { .min = 25000, .max = 35 },
-   .vco = { .min = 908000, .max = 1512000 },
-   .n = { .min = 2, .max = 16 },
-   .m = { .min = 96, .max = 140 },
-   .m1 = { .min = 18, .max = 26 },
-   .m2 = { .min = 6, .max = 16 },
-   .p = { .min = 4, .max = 128 },
-   .p1 = { .min = 2, .max = 33 },
-   .p2 = { .dot_limit = 165000,
-   .p2_slow = 4, .p2_fast = 2 },
-};
-
-static const struct intel_limit intel_limits_i8xx_dvo = {
-   .dot = { .min = 25000, .max = 35 },
-   .vco = { .min = 908000, .max = 1512000 },
-   .n = { .min = 2, .max = 16 },
-   .m = { .min = 96, .max = 140 },
-   .m1 = { .min = 18, .max = 26 },
-   .m2 = { .min = 6, .max = 16 },
-   .p = { .min = 4, .max = 128 },
-   .p1 = { .min = 2, .max = 33 },
-   .p2 = { .dot_limit = 165000,
-   .p2_slow = 4, .p2_fast = 4 },
-};
-
-static const struct intel_limit intel_limits_i8xx_lvds = {
-   .dot = { .min = 25000, .max = 35 },
-   .vco = { .min = 908000, .max = 1512000 },
-   .n = { .min = 2, .max = 16 },
-   .m = { .min = 96, .max = 140 },
-   .m1 = { .min = 18, .max = 26 },
-   .m2 = { .min = 6, .max = 16 },
-   .p = { .min = 4, .max = 128 },
-   .p1 = { .min = 1, .max = 6 },
-   .p2 = { .dot_limit = 165000,
-   .p2_slow = 14, .p2_fast = 7 },
-};
-
-static const struct intel_limit intel_limits_i9xx_sdvo = {
-   .dot = { .min = 2, .max = 40 },
-   .vco = { .min = 140, .max = 280 },
-   .n = { .min = 1, .max = 6 },
-   .m = { .min = 70, .max = 120 },
-   .m1 = { .min = 8, .max = 18 },
-   .m2 = { .min = 3, .max = 7 },
-   .p = { .min = 5, .max = 80 },
-   .p1 = { .min = 1, .max = 8 },
-   .p2 = { .dot_limit = 20,
-   .p2_slow = 10, .p2_fast = 5 },
-};
-
-static const struct intel_limit intel_limits_i9xx_lvds = {
-   .dot = { .min = 2, .max = 40 },
-   .vco = { .min = 140, .max = 280 },
-   .n = { .min = 1, .max = 6 },
-   .m = { .min = 70, .max = 120 },
-   .m1 = { .min = 8, .max = 18 },
-   .m2 = { .min = 3, .max = 7 },
-   .p = { .min = 7, .max = 98 },
-   .p1 = { .min = 1, .max = 8 },
-   .p2 = { .dot_limit = 112000,
-

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