[Intel-gfx] [PATCH 1/1] drm/i915/hdcp: disable the QSES check for HDCP2.2 over MST

[Anshuman Gupta]

From: Juston Li 

Like the patch to disable QSES for HDCP 1.4 over MST
https://patchwork.freedesktop.org/patch/415297/ the HDCP2.2 spec
doesn't require QSES as well and we've seen QSES not supported on a
couple HDCP2.2 docks so far (Dell WD19 and Lenovo LDC-G2)

Remove it for now until we get a better idea of how widely supported
QSES is and how to support it optionally.

Signed-off-by: Juston Li 
Reviewed-by: Anshuman Gupta 
Signed-off-by: Anshuman Gupta 
Link: 
https://patchwork.freedesktop.org/patch/msgid/20210127065034.2501119-4-juston...@intel.com
---
 drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 31 +---
 1 file changed, 1 insertion(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c 
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 4dba5bb15af5..40c516e90193 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -698,30 +698,6 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_connector 
*connector,
return 0;
 }
 
-static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
-struct intel_connector *connector)
-{
-   struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
-   struct drm_dp_query_stream_enc_status_ack_reply reply;
-   struct intel_dp *intel_dp = _port->dp;
-   int ret;
-
-   ret = drm_dp_send_query_stream_enc_status(_dp->mst_mgr,
- connector->port, );
-   if (ret) {
-   drm_dbg_kms(>drm,
-   "[%s:%d] failed QSES ret=%d\n",
-   connector->base.name, connector->base.base.id, ret);
-   return false;
-   }
-
-   drm_dbg_kms(>drm, "[%s:%d] QSES stream auth: %d stream enc: %d\n",
-   connector->base.name, connector->base.base.id,
-   reply.auth_completed, reply.encryption_enabled);
-
-   return reply.auth_completed && reply.encryption_enabled;
-}
-
 static int
 intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
 bool enable)
@@ -757,11 +733,6 @@ intel_dp_mst_hdcp2_stream_encryption(struct 
intel_connector *connector,
return 0;
 }
 
-/*
- * DP v2.0 I.3.3 ignore the stream signature L' in QSES reply msg reply.
- * I.3.5 MST source device may use a QSES msg to query downstream status
- * for a particular stream.
- */
 static
 int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
  struct intel_connector *connector)
@@ -781,7 +752,7 @@ int intel_dp_mst_hdcp2_check_link(struct intel_digital_port 
*dig_port,
return ret;
}
 
-   return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 : -EINVAL;
+   return 0;
 }
 
 static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
-- 
2.26.2

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[Intel-gfx] [PATCH 0/1] disable the QSES check for HDCP2.2 over MST

[Anshuman Gupta]

Floating a stand-alone patch form the below series in order to 
merge it.
https://patchwork.freedesktop.org/series/86325/

Juston Li (1):
  drm/i915/hdcp: disable the QSES check for HDCP2.2 over MST

 drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 31 +---
 1 file changed, 1 insertion(+), 30 deletions(-)

-- 
2.26.2

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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST (rev2)

[Gupta, Anshuman]

Pushed to drm-intel-next.

From: Intel-gfx  On Behalf Of Patchwork
Sent: Thursday, January 28, 2021 12:36 PM
To: Sean Paul 
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hdcp: Disable the QSES 
check for HDCP 1.4 over MST (rev2)

Patch Details
Series:

drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST (rev2)

URL:

https://patchwork.freedesktop.org/series/8/

State:

success

Details:

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19447/index.html

CI Bug Log - changes from CI_DRM_9666_full -> Patchwork_19447_full
Summary

SUCCESS

No regressions found.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19447/index.html

Changes

No changes found

Participating hosts (10 -> 8)

Missing (2): pig-skl-6260u pig-glk-j5005

Build changes

  *   CI: CI-20190529 -> None
  *   Linux: CI_DRM_9666 -> Patchwork_19447
  *   Piglit: piglit_4509 -> None

CI-20190529: 20190529
CI_DRM_9666: 9ccbc653bf2948d1f7e9ff300dd7679b888ffa25 @ 
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5962: 22e3daaed82ab7890018a2f2aabf5082cd536023 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19447: 69d7db003fa406df7851ab08239dd409a78f4421 @ 
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST (rev2)

[Petri Latvala]

On Wed, Jan 27, 2021 at 09:13:36PM +0200, Vudum, Lakshminarayana wrote:
> I am not totally sure why shard run is not triggered here 
> https://patchwork.freedesktop.org/series/8/#rev2
> @Latvala, Petri any help here?

The results were there but reporting it failed. Re-reported it and
it's now on patchwork.


-- 
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST (rev2)
URL   : https://patchwork.freedesktop.org/series/8/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9666_full -> Patchwork_19447_full


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19447/index.html


Changes
---

  No changes found


Participating hosts (10 -> 8)
--

  Missing(2): pig-skl-6260u pig-glk-j5005 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_9666 -> Patchwork_19447
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_9666: 9ccbc653bf2948d1f7e9ff300dd7679b888ffa25 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5962: 22e3daaed82ab7890018a2f2aabf5082cd536023 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19447: 69d7db003fa406df7851ab08239dd409a78f4421 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19447/index.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for Final set of patches for ADLS enabling (rev2)

[Patchwork]

== Series Details ==

Series: Final set of patches for ADLS enabling (rev2)
URL   : https://patchwork.freedesktop.org/series/86322/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9690 -> Patchwork_19525


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19525/index.html

Known issues


  Here are the changes found in Patchwork_19525 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_mmap_gtt@basic:
- fi-tgl-y:   [PASS][1] -> [DMESG-WARN][2] ([i915#402])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9690/fi-tgl-y/igt@gem_mmap_...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19525/fi-tgl-y/igt@gem_mmap_...@basic.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-bdw-5557u:   NOTRUN -> [SKIP][3] ([fdo#109271]) +3 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19525/fi-bdw-5557u/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u:   NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19525/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2:  [PASS][5] -> [DMESG-WARN][6] ([i915#2868])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9690/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19525/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-y:   [DMESG-WARN][7] ([i915#2411] / [i915#402]) -> 
[PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9690/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19525/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html

  * igt@gem_flink_basic@bad-open:
- fi-tgl-y:   [DMESG-WARN][9] ([i915#402]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9690/fi-tgl-y/igt@gem_flink_ba...@bad-open.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19525/fi-tgl-y/igt@gem_flink_ba...@bad-open.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (44 -> 39)
--

  Missing(5): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9690 -> Patchwork_19525

  CI-20190529: 20190529
  CI_DRM_9690: 9aaca070110254fe08a15ec909f8793c47ada2bc @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5975: e2a754840c4d413b7b7a642caca47f7d174d6304 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19525: 234b877a1668b4773b50b8407a610cb21b340d79 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

234b877a1668 drm/i915/adl_s: Add GT and CTX WAs for ADL-S
28a8fca6f022 drm/i915/adl_s: Add display WAs for ADL-S
9d4007d2b51b drm/i915/adl_s: Update memory bandwidth parameters
804019e4857d drm/i915/adl_s: Load DMC
cd49856755a6 drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
2344dadc51da drm/i915/adl_s: Re-use TGL GuC/HuC firmware
83ca04828dec drm/i915/adl_s: Add power wells
8cede37510f4 drm/i915/adl_s: MCHBAR memory info registers are moved
36f14b084aab drm/i915/adl_s: Update PHY_MISC programming

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19525/index.html
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Final set of patches for ADLS enabling (rev2)

[Patchwork]

== Series Details ==

Series: Final set of patches for ADLS enabling (rev2)
URL   : https://patchwork.freedesktop.org/series/86322/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1327:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 
279040
+drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 
16777216
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - 
different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' 
- different lock contexts for basic block

Re: [Intel-gfx] [PATCH 2/9] drm/i915/adl_s: MCHBAR memory info registers are moved

[Aditya Swarup]

On 1/27/21 8:48 AM, Souza, Jose wrote:
> On Wed, 2021-01-27 at 07:07 -0800, Lucas De Marchi wrote:
>> On Tue, Jan 26, 2021 at 08:11:52PM -0800, Aditya Swarup wrote:
>>> From: Caz Yokoyama 
>>>
>>> The crwebview indicates on ADL-S that some of our MCHBAR
>>> registers have moved from their traditional 0x50XX offsets to
>>> new locations. The meaning and bit layout of the registers
>>> remain same.
>>>
>>> v2: Simplify logic to a single if else chain and fix indents.(Lucas)
>>>
>>> Cc: Lucas De Marchi 
>>> Cc: Jani Nikula 
>>> Cc: Ville Syrjälä 
>>> Cc: Imre Deak 
>>> Cc: Matt Roper 
>>> Signed-off-by: Caz Yokoyama 
>>> Signed-off-by: Aditya Swarup 
>>> ---
>>> drivers/gpu/drm/i915/i915_reg.h   |  5 +
>>> drivers/gpu/drm/i915/intel_dram.c | 24 ++--
>>> 2 files changed, 23 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>>> b/drivers/gpu/drm/i915/i915_reg.h
>>> index aa872446337b..3031897239a0 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -10916,6 +10916,8 @@ enum skl_power_gate {
>>> #define  SKL_DRAM_DDR_TYPE_LPDDR3   (2 << 0)
>>> #define  SKL_DRAM_DDR_TYPE_LPDDR4   (3 << 0)
>>>
>>> +#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 
>>> 0x6048)
>>> +
>>> #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN
>>> _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
>>> #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN
>>> _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
>>> #define  SKL_DRAM_S_SHIFT   16
>>> @@ -10943,6 +10945,9 @@ enum skl_power_gate {
>>> #define  CNL_DRAM_RANK_3(0x2 << 9)
>>> #define  CNL_DRAM_RANK_4(0x3 << 9)
>>>
>>> +#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR 
>>> _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054)
>>> +#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR 
>>> _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058)
>>> +
>>> /*
>>>  * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this 
>>> register,
>>>  * since on HSW we can't write to it using intel_uncore_write.
>>> diff --git a/drivers/gpu/drm/i915/intel_dram.c 
>>> b/drivers/gpu/drm/i915/intel_dram.c
>>> index 4754296a250e..84f84e118531 100644
>>> --- a/drivers/gpu/drm/i915/intel_dram.c
>>> +++ b/drivers/gpu/drm/i915/intel_dram.c
>>> @@ -181,17 +181,24 @@ skl_dram_get_channels_info(struct drm_i915_private 
>>> *i915)
>>> {
>>> struct dram_info *dram_info = >dram_info;
>>> struct dram_channel_info ch0 = {}, ch1 = {};
>>> +   i915_reg_t ch0_reg, ch1_reg;
>>> u32 val;
>>> int ret;
>>>
>>> -   val = intel_uncore_read(>uncore,
>>> -   SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
>>> +   if (IS_ALDERLAKE_S(i915)) {
>>> +   ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
>>> +   ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;
>>> +   } else {
>>> +   ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
>>> +   ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;
>>
>> I commented on the wrong version of the patch, but the bug is still
>> here. And this patch conflict with Jose's patch.
> 
> Yep, for GEN12+ we should use PCODE to read DRAM information.
> Lucas left some comments, working in the fixes and soon another version will 
> be send.
> It already takes care of all GEN12 platforms.
> 
> https://patchwork.freedesktop.org/series/86092/

Since I didn't see the removal of code 
skl_dram_get_channels_info/get_dram_type, I have corrected this patch and 
submitted as part of rev2
just in case to please CI not to report errors with the next revision. Please 
ignore/drop the MCHBAR patch
if your patch series has been merged.

Aditya 

> 
>>
>> Lucas De Marchi
>> ___
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>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Final set of patches for ADLS enabling (rev2)

[Patchwork]

== Series Details ==

Series: Final set of patches for ADLS enabling (rev2)
URL   : https://patchwork.freedesktop.org/series/86322/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
36f14b084aab drm/i915/adl_s: Update PHY_MISC programming
8cede37510f4 drm/i915/adl_s: MCHBAR memory info registers are moved
83ca04828dec drm/i915/adl_s: Add power wells
2344dadc51da drm/i915/adl_s: Re-use TGL GuC/HuC firmware
cd49856755a6 drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
-:45: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible 
side-effects?
#45: FILE: drivers/gpu/drm/i915/i915_drv.h:1788:
+#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
+ IS_ALDERLAKE_S(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 33 lines checked
804019e4857d drm/i915/adl_s: Load DMC
9d4007d2b51b drm/i915/adl_s: Update memory bandwidth parameters
-:48: CHECK:LINE_SPACING: Please don't use multiple blank lines
#48: FILE: drivers/gpu/drm/i915/display/intel_bw.c:324:
 
+

total: 0 errors, 0 warnings, 1 checks, 23 lines checked
28a8fca6f022 drm/i915/adl_s: Add display WAs for ADL-S
234b877a1668 drm/i915/adl_s: Add GT and CTX WAs for ADL-S


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Re: [Intel-gfx] [PATCH 8/9] drm/i915/adl_s: Add display WAs for ADL-S

[Aditya Swarup]

On 1/26/21 9:22 PM, Matt Roper wrote:
> On Tue, Jan 26, 2021 at 08:11:58PM -0800, Aditya Swarup wrote:
>> - Extend permanent driver WA Wa_1409767108, Wa_14010685332
>>   and Wa_14011294188 to adl-s.
>> - Extend permanent driver WA Wa_1606054188 to adl-s.
>> - Add Wa_14011765242 for adl-s A0 stepping.
>>
>> Cc: Jani Nikula 
>> Cc: Ville Syrjälä 
>> Cc: Imre Deak 
>> Cc: Matt Roper 
>> Cc: Lucas De Marchi 
>> Signed-off-by: Aditya Swarup 
>> ---
>>  drivers/gpu/drm/i915/display/intel_display_power.c | 7 ---
>>  drivers/gpu/drm/i915/display/intel_sprite.c| 4 ++--
>>  drivers/gpu/drm/i915/intel_device_info.c   | 6 +-
>>  3 files changed, 11 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
>> b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index cccfd45a67cf..e17b1ca356c3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -5339,9 +5339,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private 
>> *dev_priv)
>>  unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
>>  int config, i;
>>  
>> -if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>> +if (IS_ALDERLAKE_S(dev_priv) ||
>> +IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>>  IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
>> -/* Wa_1409767108:tgl,dg1 */
>> +/* Wa_1409767108:tgl,dg1,adl-s */
>>  table = wa_1409767108_buddy_page_masks;
>>  else
>>  table = tgl_buddy_page_masks;
>> @@ -5379,7 +5380,7 @@ static void icl_display_core_init(struct 
>> drm_i915_private *dev_priv,
>>  
>>  gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>>  
>> -/* Wa_14011294188:ehl,jsl,tgl,rkl */
>> +/* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
>>  if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
>>  INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
>>  intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c 
>> b/drivers/gpu/drm/i915/display/intel_sprite.c
>> index 68cea5ca251c..a7077babd31c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> @@ -2418,8 +2418,8 @@ static int skl_plane_check_fb(const struct 
>> intel_crtc_state *crtc_state,
>>  return -EINVAL;
>>  }
>>  
>> -/* Wa_1606054188:tgl */
>> -if (IS_TIGERLAKE(dev_priv) &&
>> +/* Wa_1606054188:tgl,adl-s */
>> +if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
>>  plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
>>  intel_format_is_p01x(fb->format->format)) {
>>  drm_dbg_kms(_priv->drm,
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
>> b/drivers/gpu/drm/i915/intel_device_info.c
>> index 85d6883745d8..92ad3e7d1f6f 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -250,7 +250,11 @@ void intel_device_info_runtime_init(struct 
>> drm_i915_private *dev_priv)
>>  struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
>>  enum pipe pipe;
>>  
>> -if (INTEL_GEN(dev_priv) >= 10) {
>> +/* Wa_14011765242: adl-s A0 */
>> +if (IS_ADLS_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0))
> 
> I think this workaround is also needed on A1 stepping now and should
> only be removed on A2.

There is no A1 stepping for ADLS. We directly have stepping A2 after A0. But I 
have made the change
that you have suggested in rev2.

Aditya

> 
> 
> Matt
> 
>> +for_each_pipe(dev_priv, pipe)
>> +runtime->num_scalers[pipe] = 0;
>> +else if (INTEL_GEN(dev_priv) >= 10) {
>>  for_each_pipe(dev_priv, pipe)
>>  runtime->num_scalers[pipe] = 2;
>>  } else if (IS_GEN(dev_priv, 9)) {
>> -- 
>> 2.27.0
>>
> 

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[Intel-gfx] [PATCH 8/9] drm/i915/adl_s: Add display WAs for ADL-S

[Aditya Swarup]

- Extend permanent driver WA Wa_1409767108, Wa_14010685332
  and Wa_14011294188 to adl-s.
- Extend permanent driver WA Wa_1606054188 to adl-s.
- Add Wa_14011765242 for adl-s A0 stepping.

v2:
- Extend Wa_14011765242 to STEP A1.(mdroper)

Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Matt Roper 
Cc: Lucas De Marchi 
Signed-off-by: Aditya Swarup 
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 7 ---
 drivers/gpu/drm/i915/display/intel_sprite.c| 4 ++--
 drivers/gpu/drm/i915/i915_drv.h| 1 +
 drivers/gpu/drm/i915/intel_device_info.c   | 6 +-
 4 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index cccfd45a67cf..e17b1ca356c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5339,9 +5339,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private 
*dev_priv)
unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
int config, i;
 
-   if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+   if (IS_ALDERLAKE_S(dev_priv) ||
+   IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
-   /* Wa_1409767108:tgl,dg1 */
+   /* Wa_1409767108:tgl,dg1,adl-s */
table = wa_1409767108_buddy_page_masks;
else
table = tgl_buddy_page_masks;
@@ -5379,7 +5380,7 @@ static void icl_display_core_init(struct drm_i915_private 
*dev_priv,
 
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
-   /* Wa_14011294188:ehl,jsl,tgl,rkl */
+   /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c 
b/drivers/gpu/drm/i915/display/intel_sprite.c
index d216a863d818..ec931a08ff28 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2373,8 +2373,8 @@ static int skl_plane_check_fb(const struct 
intel_crtc_state *crtc_state,
return -EINVAL;
}
 
-   /* Wa_1606054188:tgl */
-   if (IS_TIGERLAKE(dev_priv) &&
+   /* Wa_1606054188:tgl,adl-s */
+   if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
intel_format_is_p01x(fb->format->format)) {
drm_dbg_kms(_priv->drm,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9713ab963122..a1fef2176ae0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1559,6 +1559,7 @@ extern const struct i915_rev_steppings kbl_revids[];
 
 enum {
STEP_A0,
+   STEP_A1,
STEP_A2,
STEP_B0,
STEP_B1,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 85d6883745d8..06df1911cc7d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -250,7 +250,11 @@ void intel_device_info_runtime_init(struct 
drm_i915_private *dev_priv)
struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
enum pipe pipe;
 
-   if (INTEL_GEN(dev_priv) >= 10) {
+   /* Wa_14011765242: adl-s A0 */
+   if (IS_ADLS_DISP_STEPPING(dev_priv, STEP_A0, STEP_A1))
+   for_each_pipe(dev_priv, pipe)
+   runtime->num_scalers[pipe] = 0;
+   else if (INTEL_GEN(dev_priv) >= 10) {
for_each_pipe(dev_priv, pipe)
runtime->num_scalers[pipe] = 2;
} else if (IS_GEN(dev_priv, 9)) {
-- 
2.27.0

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[Intel-gfx] [PATCH 6/9] drm/i915/adl_s: Load DMC

[Aditya Swarup]

From: Anusha Srivatsa 

Load DMC on ADL_S v2.01. This is the first offcial
release of DMC for ADL_S.

Cc: Jani Nikula 
Cc: Imre Deak 
Cc: Matt Roper 
Cc: Lucas De Marchi 
Cc: Aditya Swarup 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Aditya Swarup 
Reviewed-by: Aditya Swarup 
---
 drivers/gpu/drm/i915/display/intel_csr.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_csr.c 
b/drivers/gpu/drm/i915/display/intel_csr.c
index 67dc64df78a5..db9f219c4b5a 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -40,6 +40,10 @@
 
 #define GEN12_CSR_MAX_FW_SIZE  ICL_CSR_MAX_FW_SIZE
 
+#define ADLS_CSR_PATH  "i915/adls_dmc_ver2_01.bin"
+#define ADLS_CSR_VERSION_REQUIRED  CSR_VERSION(2, 1)
+MODULE_FIRMWARE(ADLS_CSR_PATH);
+
 #define DG1_CSR_PATH   "i915/dg1_dmc_ver2_02.bin"
 #define DG1_CSR_VERSION_REQUIRED   CSR_VERSION(2, 2)
 MODULE_FIRMWARE(DG1_CSR_PATH);
@@ -689,7 +693,11 @@ void intel_csr_ucode_init(struct drm_i915_private 
*dev_priv)
 */
intel_csr_runtime_pm_get(dev_priv);
 
-   if (IS_DG1(dev_priv)) {
+   if (IS_ALDERLAKE_S(dev_priv)) {
+   csr->fw_path = ADLS_CSR_PATH;
+   csr->required_version = ADLS_CSR_VERSION_REQUIRED;
+   csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+   } else if (IS_DG1(dev_priv)) {
csr->fw_path = DG1_CSR_PATH;
csr->required_version = DG1_CSR_VERSION_REQUIRED;
csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
-- 
2.27.0

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[Intel-gfx] [PATCH 7/9] drm/i915/adl_s: Update memory bandwidth parameters

[Aditya Swarup]

From: Tejas Upadhyay 

Just like RKL, the ADL_S platform also has different memory
characteristics from past platforms.  Update the values used
by our memory bandwidth calculations accordingly.

v2: Fix minor nitpick for shifting ADLS case above RKL(based on platform
order).(mdroper)

Bspec: 64631
Cc: Matt Roper 
Cc: Lucas De Marchi 
Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Imre Deak 
Signed-off-by: Tejas Upadhyay 
Signed-off-by: Aditya Swarup 
Reviewed-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/display/intel_bw.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index bd060404d249..4e7a30d44fc1 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -205,6 +205,12 @@ static const struct intel_sa_info rkl_sa_info = {
.displayrtids = 128,
 };
 
+static const struct intel_sa_info adls_sa_info = {
+   .deburst = 16,
+   .deprogbwlimit = 38, /* GB/s */
+   .displayrtids = 256,
+};
+
 static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct 
intel_sa_info *sa)
 {
struct intel_qgv_info qi = {};
@@ -315,7 +321,10 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
 
-   if (IS_ROCKETLAKE(dev_priv))
+
+   if (IS_ALDERLAKE_S(dev_priv))
+   icl_get_bw_info(dev_priv, _sa_info);
+   else if (IS_ROCKETLAKE(dev_priv))
icl_get_bw_info(dev_priv, _sa_info);
else if (IS_GEN(dev_priv, 12))
icl_get_bw_info(dev_priv, _sa_info);
-- 
2.27.0

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[Intel-gfx] [PATCH 9/9] drm/i915/adl_s: Add GT and CTX WAs for ADL-S

[Aditya Swarup]

- Extend Wa_1606931601 and Wa_1409804808 to ADL-S.
- Extend Wa_14010919138 and Wa_14010229206 to ADL-S (Madhumitha)
- Extend Wa_22010271021 to ADLS (cyokoyam)

v2:
- Extend Wa_1409804808 and remove unnecessary branching/redundant
  adls workaround placeholder functions.
- Split WAs properly based on previous platforms and applicable ADLS
  WA.

Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Matt Roper 
Cc: Lucas De Marchi 
Signed-off-by: Madhumitha Tolakanahalli Pradeep 

Signed-off-by: Aditya Swarup 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 +
 1 file changed, 21 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 71d1c19c868b..3b4a7da60f0b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -729,7 +729,8 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 
if (IS_DG1(i915))
dg1_ctx_workarounds_init(engine, wal);
-   else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
+   else if (IS_ALDERLAKE_S(i915) || IS_ROCKETLAKE(i915) ||
+IS_TIGERLAKE(i915))
tgl_ctx_workarounds_init(engine, wal);
else if (IS_GEN(i915, 12))
gen12_ctx_workarounds_init(engine, wal);
@@ -1639,45 +1640,45 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
GEN7_DISABLE_SAMPLER_PREFETCH);
}
 
-   if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
-   /* Wa_1606931601:tgl,rkl,dg1 */
+   if (IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
+   IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+   /* Wa_1606931601:tgl,rkl,dg1,adl-s */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
 
/*
 * Wa_1407928979:tgl A*
 * Wa_18011464164:tgl[B0+],dg1[B0+]
 * Wa_22010931296:tgl[B0+],dg1[B0+]
-* Wa_14010919138:rkl, dg1
+* Wa_14010919138:rkl,dg1,adl-s
 */
wa_write_or(wal, GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
 
/*
 * Wa_1606700617:tgl,dg1
-* Wa_22010271021:tgl,rkl,dg1
+* Wa_22010271021:tgl,rkl,dg1, adl-s
 */
wa_masked_en(wal,
 GEN9_CS_DEBUG_MODE1,
 FF_DOP_CLOCK_GATE_DISABLE);
-
-   /* Wa_1406941453:tgl,rkl,dg1 */
-   wa_masked_en(wal,
-GEN10_SAMPLER_MODE,
-ENABLE_SMALLPL);
}
 
-   if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+   if (IS_ALDERLAKE_S(i915) || IS_DG1_REVID(i915, DG1_REVID_A0, 
DG1_REVID_A0) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
-   /* Wa_1409804808:tgl,rkl,dg1[a0] */
+   /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s */
wa_masked_en(wal, GEN7_ROW_CHICKEN2,
 GEN12_PUSH_CONST_DEREF_HOLD_DIS);
 
/*
 * Wa_1409085225:tgl
-* Wa_14010229206:tgl,rkl,dg1[a0]
+* Wa_14010229206:tgl,rkl,dg1[a0],adl-s
 */
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
+   }
+
 
+   if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+   IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/*
 * Wa_1607030317:tgl
 * Wa_1607186500:tgl
@@ -1694,6 +1695,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
 GEN8_RC_SEMA_IDLE_MSG_DISABLE);
}
 
+   if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+   /* Wa_1406941453:tgl,rkl,dg1 */
+   wa_masked_en(wal,
+GEN10_SAMPLER_MODE,
+ENABLE_SMALLPL);
+   }
+
if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
-- 
2.27.0

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[Intel-gfx] [PATCH 5/9] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION

[Aditya Swarup]

From: José Roberto de Souza 

- As RKL and ADL-S only have 5 planes, primary and 4 sprites and
  the cursor plane, let's group the handling together under
  HAS_D12_PLANE_MINIMIZATION.
- Also use macro to select pipe irq fault error mask.

BSpec: 49251
Cc: Lucas De Marchi 
Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Matt Roper 
Signed-off-by: José Roberto de Souza 
Signed-off-by: Aditya Swarup 
Reviewed-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h | 3 +++
 drivers/gpu/drm/i915/i915_irq.c | 2 +-
 drivers/gpu/drm/i915/intel_device_info.c| 2 +-
 4 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c 
b/drivers/gpu/drm/i915/display/intel_sprite.c
index e83c878ac7b0..d216a863d818 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -382,7 +382,7 @@ int intel_plane_check_src_coordinates(struct 
intel_plane_state *plane_state)
 
 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
 {
-   if (IS_ROCKETLAKE(i915))
+   if (HAS_D12_PLANE_MINIMIZATION(i915))
return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
else
return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3edc9c4f2d21..9713ab963122 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1785,6 +1785,9 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
 #define INTEL_DISPLAY_ENABLED(dev_priv) \
(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), 
!(dev_priv)->params.disable_display)
 
+#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
+ IS_ALDERLAKE_S(dev_priv))
+
 static inline bool run_as_guest(void)
 {
return !hypervisor_is_type(X86_HYPER_NATIVE);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a31980f69120..06937a2d2714 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2280,7 +2280,7 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private 
*dev_priv)
 
 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
 {
-   if (IS_ROCKETLAKE(dev_priv))
+   if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
else if (INTEL_GEN(dev_priv) >= 11)
return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 7d98a718a051..85d6883745d8 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -261,7 +261,7 @@ void intel_device_info_runtime_init(struct drm_i915_private 
*dev_priv)
 
BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 
-   if (IS_ROCKETLAKE(dev_priv))
+   if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 4;
else if (INTEL_GEN(dev_priv) >= 11)
-- 
2.27.0

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[Intel-gfx] [PATCH 3/9] drm/i915/adl_s: Add power wells

[Aditya Swarup]

From: Lucas De Marchi 

TGL power wells can be re-used for ADL-S with the exception of the fake
power well for TC_COLD, just like DG-1.

BSpec: 53597
Bspec: 49231

Cc: Imre Deak 
Cc: Matt Roper 
Cc: Aditya Swarup 
Signed-off-by: Lucas De Marchi 
Signed-off-by: Aditya Swarup 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 708f0b7e0990..cccfd45a67cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4689,7 +4689,7 @@ int intel_power_domains_init(struct drm_i915_private 
*dev_priv)
 * The enabling order will be from lower to higher indexed wells,
 * the disabling order is reversed.
 */
-   if (IS_DG1(dev_priv)) {
+   if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
err = set_power_wells_mask(power_domains, tgl_power_wells,
   BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
} else if (IS_ROCKETLAKE(dev_priv)) {
-- 
2.27.0

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[Intel-gfx] [PATCH 4/9] drm/i915/adl_s: Re-use TGL GuC/HuC firmware

[Aditya Swarup]

From: Matt Roper 

ADL-S, like RKL, uses the same internal device ID for the GuC and HuC as
TGL did, making them all firmware-compatible.  Let's re-use TGL's
firmware for ADL-S.

Bspec: 50668
Cc: John Harrison 
Cc: Lucas De Marchi 
Signed-off-by: Matt Roper 
Signed-off-by: Aditya Swarup 
Reviewed-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 67b06fde1225..984fa79e0fa7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -44,9 +44,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  * List of required GuC and HuC binaries per-platform.
  * Must be ordered based on platform + revid, from newer to older.
  *
- * Note that RKL uses the same firmware as TGL.
+ * Note that RKL and ADL-S have the same GuC/HuC device ID's and use the same
+ * firmware as TGL.
  */
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
+   fw_def(ALDERLAKE_S, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
fw_def(ROCKETLAKE,  0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
fw_def(TIGERLAKE,   0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
fw_def(JASPERLAKE,  0, guc_def(ehl, 49, 0, 1), huc_def(ehl,  9, 0, 0)) \
-- 
2.27.0

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[Intel-gfx] [PATCH 2/9] drm/i915/adl_s: MCHBAR memory info registers are moved

[Aditya Swarup]

From: Caz Yokoyama 

The crwebview indicates on ADL-S that some of our MCHBAR
registers have moved from their traditional 0x50XX offsets to
new locations. The meaning and bit layout of the registers
remain same.

v2: Simplify logic to a single if else chain and fix indents.(Lucas)

v3: Fix bug due to assignment of ADLS offsets in both if/else
branches in function skl_dram_get_channels_info().(Lucas)

Cc: Lucas De Marchi 
Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Matt Roper 
Signed-off-by: Caz Yokoyama 
Signed-off-by: Aditya Swarup 
---
 drivers/gpu/drm/i915/i915_reg.h   |  5 +
 drivers/gpu/drm/i915/intel_dram.c | 24 ++--
 2 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aa872446337b..3031897239a0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10916,6 +10916,8 @@ enum skl_power_gate {
 #define  SKL_DRAM_DDR_TYPE_LPDDR3  (2 << 0)
 #define  SKL_DRAM_DDR_TYPE_LPDDR4  (3 << 0)
 
+#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x6048)
+
 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN   _MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x500C)
 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN   _MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x5010)
 #define  SKL_DRAM_S_SHIFT  16
@@ -10943,6 +10945,9 @@ enum skl_power_gate {
 #define  CNL_DRAM_RANK_3   (0x2 << 9)
 #define  CNL_DRAM_RANK_4   (0x3 << 9)
 
+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x6054)
+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x6058)
+
 /*
  * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this 
register,
  * since on HSW we can't write to it using intel_uncore_write.
diff --git a/drivers/gpu/drm/i915/intel_dram.c 
b/drivers/gpu/drm/i915/intel_dram.c
index 4754296a250e..c61ae4b6dc86 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -181,17 +181,24 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
 {
struct dram_info *dram_info = >dram_info;
struct dram_channel_info ch0 = {}, ch1 = {};
+   i915_reg_t ch0_reg, ch1_reg;
u32 val;
int ret;
 
-   val = intel_uncore_read(>uncore,
-   SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
+   if (IS_ALDERLAKE_S(i915)) {
+   ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
+   ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;
+   } else {
+   ch0_reg = SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN;
+   ch1_reg = SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN;
+   }
+
+   val = intel_uncore_read(>uncore, ch0_reg);
ret = skl_dram_get_channel_info(i915, , 0, val);
if (ret == 0)
dram_info->num_channels++;
 
-   val = intel_uncore_read(>uncore,
-   SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
+   val = intel_uncore_read(>uncore, ch1_reg);
ret = skl_dram_get_channel_info(i915, , 1, val);
if (ret == 0)
dram_info->num_channels++;
@@ -229,10 +236,15 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
 static enum intel_dram_type
 skl_get_dram_type(struct drm_i915_private *i915)
 {
+   i915_reg_t reg;
u32 val;
 
-   val = intel_uncore_read(>uncore,
-   SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
+   if (IS_ALDERLAKE_S(i915))
+   reg = ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR;
+   else
+   reg = SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN;
+
+   val = intel_uncore_read(>uncore, reg);
 
switch (val & SKL_DRAM_DDR_TYPE_MASK) {
case SKL_DRAM_DDR_TYPE_DDR3:
-- 
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[Intel-gfx] [PATCH 0/9] Final set of patches for ADLS enabling

[Aditya Swarup]

These are the final set of patches required for enabling ADL-S. The
patches have been tested on platform and all display outputs are
working.

v2: Address minor nitpicks provided by mdroper.

Patch "drm/i915/adl_s: MCHBAR memory info registers are moved"
can be ignored as Jose's submission 
https://patchwork.freedesktop.org/series/86092/
allows us to fetch dram info from pcode.

Currently in his series, I didn't see removal of
skl_dram_get_channels_info(). So just to get clear results from CI, I
have included the MCHBAR patch in series.

Aditya Swarup (2):
  drm/i915/adl_s: Add display WAs for ADL-S
  drm/i915/adl_s: Add GT and CTX WAs for ADL-S

Anusha Srivatsa (1):
  drm/i915/adl_s: Load DMC

Caz Yokoyama (1):
  drm/i915/adl_s: MCHBAR memory info registers are moved

José Roberto de Souza (1):
  drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION

Lucas De Marchi (1):
  drm/i915/adl_s: Add power wells

Matt Roper (2):
  drm/i915/adl_s: Update PHY_MISC programming
  drm/i915/adl_s: Re-use TGL GuC/HuC firmware

Tejas Upadhyay (1):
  drm/i915/adl_s: Update memory bandwidth parameters

 drivers/gpu/drm/i915/display/intel_bw.c   | 11 +-
 .../gpu/drm/i915/display/intel_combo_phy.c| 12 +--
 drivers/gpu/drm/i915/display/intel_csr.c  | 10 +-
 .../drm/i915/display/intel_display_power.c|  9 ++---
 drivers/gpu/drm/i915/display/intel_sprite.c   |  6 ++--
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 34 ---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  |  4 ++-
 drivers/gpu/drm/i915/i915_drv.h   |  4 +++
 drivers/gpu/drm/i915/i915_irq.c   |  2 +-
 drivers/gpu/drm/i915/i915_reg.h   |  5 +++
 drivers/gpu/drm/i915/intel_device_info.c  |  8 +++--
 drivers/gpu/drm/i915/intel_dram.c | 24 +
 12 files changed, 94 insertions(+), 35 deletions(-)

-- 
2.27.0

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[Intel-gfx] [PATCH 1/9] drm/i915/adl_s: Update PHY_MISC programming

[Aditya Swarup]

From: Matt Roper 

ADL-S switches up which PHYs are considered a master to other PHYs;
PHY-C is no longer a master, but PHY-D is now.

Bspec: 49291
Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Lucas De Marchi 
Signed-off-by: Matt Roper 
Signed-off-by: Aditya Swarup 
Reviewed-by: Aditya Swarup 
---
 drivers/gpu/drm/i915/display/intel_combo_phy.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c 
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index dd45cbafcf42..c55813c6194a 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -187,10 +187,16 @@ static bool has_phy_misc(struct drm_i915_private *i915, 
enum phy phy)
 * Some platforms only expect PHY_MISC to be programmed for PHY-A and
 * PHY-B and may not even have instances of the register for the
 * other combo PHY's.
+*
+* ADL-S technically has three instances of PHY_MISC, but only requires
+* that we program it for PHY A.
 */
-   if (IS_JSL_EHL(i915) ||
-   IS_ROCKETLAKE(i915) ||
-   IS_DG1(i915))
+
+   if (IS_ALDERLAKE_S(i915))
+   return phy == PHY_A;
+   else if (IS_JSL_EHL(i915) ||
+IS_ROCKETLAKE(i915) ||
+IS_DG1(i915))
return phy < PHY_C;
 
return true;
-- 
2.27.0

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Re: [Intel-gfx] [PATCH v2 3/4] drm/i915: Fail driver probe when unable to load DRAM information

[Lucas De Marchi]

On Wed, Jan 27, 2021 at 08:54:01AM -0800, Jose Souza wrote:

DRAM information is required to properly program display.
Before "drm/i915/gen11+: Only load DRAM information from pcode" we
were failing driver load if unable to fetch DRAM information from
pcode form GEN11+ but we should also extend it to GEN9 plaforms.

Signed-off-by: José Roberto de Souza 


makes sense and seems correct. But this needs to be tested on DG1 that
is not on CI and AFAIR misbehaved when trying to get this info from
pcode.  If that is passing now,


Reviewed-by: Lucas De Marchi 

Lucas De Marchi


---
drivers/gpu/drm/i915/i915_drv.c   |  6 +-
drivers/gpu/drm/i915/intel_dram.c | 13 +
drivers/gpu/drm/i915/intel_dram.h |  2 +-
3 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aec0e870dc25..7ff58ea30c7c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -622,12 +622,16 @@ static int i915_driver_hw_probe(struct drm_i915_private 
*dev_priv)
 * Fill the dram structure to get the system dram info. This will be
 * used for memory latency calculation.
 */
-   intel_dram_detect(dev_priv);
+   ret = intel_dram_detect(dev_priv);
+   if (ret)
+   goto err_dram;

intel_bw_init_hw(dev_priv);

return 0;

+err_dram:
+   intel_gvt_driver_remove(dev_priv);
err_msi:
if (pdev->msi_enabled)
pci_disable_msi(pdev);
diff --git a/drivers/gpu/drm/i915/intel_dram.c 
b/drivers/gpu/drm/i915/intel_dram.c
index 4d5ab206eacb..6ce56eedaf12 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -484,7 +484,7 @@ static int gen12_get_dram_info(struct drm_i915_private 
*i915)
return icl_pcode_read_mem_global_info(i915);
}

-void intel_dram_detect(struct drm_i915_private *i915)
+int intel_dram_detect(struct drm_i915_private *i915)
{
struct dram_info *dram_info = >dram_info;
int ret;
@@ -497,7 +497,7 @@ void intel_dram_detect(struct drm_i915_private *i915)
dram_info->is_16gb_dimm = !IS_GEN9_LP(i915);

if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
-   return;
+   return 0;

if (INTEL_GEN(i915) >= 12)
ret = gen12_get_dram_info(i915);
@@ -507,13 +507,18 @@ void intel_dram_detect(struct drm_i915_private *i915)
ret = bxt_get_dram_info(i915);
else
ret = skl_get_dram_info(i915);
-   if (ret)
-   return;
+
+   if (ret) {
+   drm_warn(>drm, "Unable to load dram information\n");
+   return ret;
+   }

drm_dbg_kms(>drm, "DRAM channels: %u\n", dram_info->num_channels);

drm_dbg_kms(>drm, "DRAM 16Gb DIMMs: %s\n",
yesno(dram_info->is_16gb_dimm));
+
+   return 0;
}

static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
diff --git a/drivers/gpu/drm/i915/intel_dram.h 
b/drivers/gpu/drm/i915/intel_dram.h
index 4ba13c13162c..2a0f283b1a1d 100644
--- a/drivers/gpu/drm/i915/intel_dram.h
+++ b/drivers/gpu/drm/i915/intel_dram.h
@@ -9,6 +9,6 @@
struct drm_i915_private;

void intel_dram_edram_detect(struct drm_i915_private *i915);
-void intel_dram_detect(struct drm_i915_private *i915);
+int intel_dram_detect(struct drm_i915_private *i915);

#endif /* __INTEL_DRAM_H__ */
--
2.30.0

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Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/gen11+: Only load DRAM information from pcode

[Lucas De Marchi]

On Wed, Jan 27, 2021 at 08:54:00AM -0800, Jose Souza wrote:

Up to now we were reading some DRAM information from MCHBAR register
and from pcode what is already not good but some GEN12(TGL-H and ADL-S)
platforms have MCHBAR DRAM information in different offsets.

This was notified to HW team that decided that the best alternative is
always apply the 16gb_dimm watermark adjustment for GEN12+ platforms
and read the remaning DRAM information needed to other display
programming from pcode.

So here moving the DRAM pcode function to intel_dram.c, removing
the duplicated fields from intel_qgv_info, setting and using
information from dram_info.

v2:
- bring back num_points to intel_qgv_info as num_qgv_point can be
overwritten in icl_get_qgv_points()
- add gen12_get_dram_info() and simplify gen11_get_dram_info()

Signed-off-by: José Roberto de Souza 



Reviewed-by: Lucas De Marchi 

Lucas De Marchi


---
drivers/gpu/drm/i915/display/intel_bw.c | 80 +++-
drivers/gpu/drm/i915/i915_drv.c |  5 +-
drivers/gpu/drm/i915/i915_drv.h |  1 +
drivers/gpu/drm/i915/intel_dram.c   | 82 -
4 files changed, 93 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index bd060404d249..4b5a30ac84bc 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -20,76 +20,9 @@ struct intel_qgv_point {
struct intel_qgv_info {
struct intel_qgv_point points[I915_NUM_QGV_POINTS];
u8 num_points;
-   u8 num_channels;
u8 t_bl;
-   enum intel_dram_type dram_type;
};

-static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
- struct intel_qgv_info *qi)
-{
-   u32 val = 0;
-   int ret;
-
-   ret = sandybridge_pcode_read(dev_priv,
-ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
-ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
-, NULL);
-   if (ret)
-   return ret;
-
-   if (IS_GEN(dev_priv, 12)) {
-   switch (val & 0xf) {
-   case 0:
-   qi->dram_type = INTEL_DRAM_DDR4;
-   break;
-   case 3:
-   qi->dram_type = INTEL_DRAM_LPDDR4;
-   break;
-   case 4:
-   qi->dram_type = INTEL_DRAM_DDR3;
-   break;
-   case 5:
-   qi->dram_type = INTEL_DRAM_LPDDR3;
-   break;
-   default:
-   MISSING_CASE(val & 0xf);
-   break;
-   }
-   } else if (IS_GEN(dev_priv, 11)) {
-   switch (val & 0xf) {
-   case 0:
-   qi->dram_type = INTEL_DRAM_DDR4;
-   break;
-   case 1:
-   qi->dram_type = INTEL_DRAM_DDR3;
-   break;
-   case 2:
-   qi->dram_type = INTEL_DRAM_LPDDR3;
-   break;
-   case 3:
-   qi->dram_type = INTEL_DRAM_LPDDR4;
-   break;
-   default:
-   MISSING_CASE(val & 0xf);
-   break;
-   }
-   } else {
-   MISSING_CASE(INTEL_GEN(dev_priv));
-   qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */
-   }
-
-   qi->num_channels = (val & 0xf0) >> 4;
-   qi->num_points = (val & 0xf00) >> 8;
-
-   if (IS_GEN(dev_priv, 12))
-   qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16;
-   else if (IS_GEN(dev_priv, 11))
-   qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
-
-   return 0;
-}
-
static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
 struct intel_qgv_point *sp,
 int point)
@@ -139,11 +72,15 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private 
*dev_priv,
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
  struct intel_qgv_info *qi)
{
+   const struct dram_info *dram_info = _priv->dram_info;
int i, ret;

-   ret = icl_pcode_read_mem_global_info(dev_priv, qi);
-   if (ret)
-   return ret;
+   qi->num_points = dram_info->num_qgv_points;
+
+   if (IS_GEN(dev_priv, 12))
+   qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 16;
+   else if (IS_GEN(dev_priv, 11))
+   qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;

if (drm_WARN_ON(_priv->drm,
qi->num_points > ARRAY_SIZE(qi->points)))
@@ -209,7 +146,7 @@ static int icl_get_bw_info(struct drm_i915_private 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Disable runtime power management during shutdown

[Patchwork]

== Series Details ==

Series: drm/i915: Disable runtime power management during shutdown
URL   : https://patchwork.freedesktop.org/series/86362/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9688_full -> Patchwork_19524_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19524_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@close-replace-race:
- shard-glk:  [PASS][1] -> [TIMEOUT][2] ([i915#2918])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk6/igt@gem_ctx_persiste...@close-replace-race.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-glk7/igt@gem_ctx_persiste...@close-replace-race.html

  * igt@gem_exec_fair@basic-deadline:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2846])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb5/igt@gem_exec_f...@basic-deadline.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-tglb6/igt@gem_exec_f...@basic-deadline.html
- shard-glk:  [PASS][5] -> [FAIL][6] ([i915#2846])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk7/igt@gem_exec_f...@basic-deadline.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-glk1/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html
- shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2849])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-iclb2/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][15] ([fdo#109283])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-iclb7/igt@gem_exec_par...@no-vebox.html

  * igt@gen7_exec_parse@basic-allowed:
- shard-skl:  NOTRUN -> [SKIP][16] ([fdo#109271]) +9 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-skl8/igt@gen7_exec_pa...@basic-allowed.html

  * igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#454])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb5/igt@i915_pm...@dc6-psr.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-iclb2/igt@i915_pm...@dc6-psr.html

  * igt@i915_pm_rpm@system-suspend-modeset:
- shard-kbl:  [PASS][19] -> [INCOMPLETE][20] ([i915#151])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl7/igt@i915_pm_...@system-suspend-modeset.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-kbl3/igt@i915_pm_...@system-suspend-modeset.html

  * igt@kms_chamelium@hdmi-cmp-planar-formats:
- shard-glk:  NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +1 
similar issue
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-glk1/igt@kms_chamel...@hdmi-cmp-planar-formats.html

  * igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
- shard-skl:  NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827]) +2 
similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-skl8/igt@kms_color_chamel...@pipe-invalid-ctm-matrix-sizes.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen:
- shard-skl:  [PASS][23] -> [FAIL][24] ([i915#54]) +9 similar issues
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-skl9/igt@kms_cursor_...@pipe-a-cursor-256x85-onscreen.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-skl2/igt@kms_cursor_...@pipe-a-cursor-256x85-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl:  

Re: [Intel-gfx] [PATCH 3/3] drm/i915/hdcp: disable the QSES check for HDCP2.2 over MST

[kernel test robot]

Hi Juston,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip next-20210125]
[cannot apply to v5.11-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Juston-Li/drm-i915-hdcp-update-cp_irq_count_cached-in-intel_dp_hdcp2_read_msg/20210127-082615
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-rhel (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce (this is a W=1 build):
# 
https://github.com/0day-ci/linux/commit/46e1277aaec81a0c1a754855cc0f077f4ef866e0
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review 
Juston-Li/drm-i915-hdcp-update-cp_irq_count_cached-in-intel_dp_hdcp2_read_msg/20210127-082615
git checkout 46e1277aaec81a0c1a754855cc0f077f4ef866e0
# save the attached .config to linux build tree
make W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/display/intel_dp_hdcp.c: In function 
'intel_dp_mst_hdcp_check_link':
>> drivers/gpu/drm/i915/display/intel_dp_hdcp.c:709:9: error: implicit 
>> declaration of function 'intel_dp_mst_get_qses_status'; did you mean 
>> 'intel_dpll_get_hw_state'? [-Werror=implicit-function-declaration]
 709 |  return intel_dp_mst_get_qses_status(dig_port, connector);
 | ^~~~
 | intel_dpll_get_hw_state
   cc1: some warnings being treated as errors


vim +709 drivers/gpu/drm/i915/display/intel_dp_hdcp.c

1a67a168f57b68 Anshuman Gupta 2021-01-11  701  
e9fd05c3e4f21a Anshuman Gupta 2021-01-11  702  static
e9fd05c3e4f21a Anshuman Gupta 2021-01-11  703  bool 
intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
e9fd05c3e4f21a Anshuman Gupta 2021-01-11  704 
struct intel_connector *connector)
e9fd05c3e4f21a Anshuman Gupta 2021-01-11  705  {
e9fd05c3e4f21a Anshuman Gupta 2021-01-11  706   if 
(!intel_dp_hdcp_check_link(dig_port, connector))
e9fd05c3e4f21a Anshuman Gupta 2021-01-11  707   return false;
e9fd05c3e4f21a Anshuman Gupta 2021-01-11  708  
e9fd05c3e4f21a Anshuman Gupta 2021-01-11 @709   return 
intel_dp_mst_get_qses_status(dig_port, connector);
e9fd05c3e4f21a Anshuman Gupta 2021-01-11  710  }
e9fd05c3e4f21a Anshuman Gupta 2021-01-11  711  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org


.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v13,1/2] drm/i915/display: Support PSR Multiple Instances

[Patchwork]

== Series Details ==

Series: series starting with [v13,1/2] drm/i915/display: Support PSR Multiple 
Instances
URL   : https://patchwork.freedesktop.org/series/86361/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9688_full -> Patchwork_19523_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19523_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][1] -> [FAIL][2] ([i915#2846])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk7/igt@gem_exec_f...@basic-deadline.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/shard-glk2/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2842]) +2 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][5] ([i915#2842])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace:
- shard-hsw:  NOTRUN -> [SKIP][6] ([fdo#109271]) +27 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/shard-hsw1/igt@gem_exec_f...@basic-pace.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl:  [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl2/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/shard-kbl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/shard-glk1/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][11] ([fdo#109283])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/shard-iclb1/igt@gem_exec_par...@no-vebox.html

  * igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][12] ([i915#2389]) +1 similar issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/shard-iclb1/igt@gem_exec_reloc@basic-wide-act...@vcs1.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk:  [PASS][13] -> [FAIL][14] ([i915#644])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk1/igt@gem_pp...@flink-and-close-vma-leak.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/shard-glk2/igt@gem_pp...@flink-and-close-vma-leak.html

  * igt@gen7_exec_parse@basic-allowed:
- shard-skl:  NOTRUN -> [SKIP][15] ([fdo#109271]) +9 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/shard-skl8/igt@gen7_exec_pa...@basic-allowed.html

  * igt@i915_pm_rpm@system-suspend-modeset:
- shard-kbl:  [PASS][16] -> [INCOMPLETE][17] ([i915#151])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl7/igt@i915_pm_...@system-suspend-modeset.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/shard-kbl4/igt@i915_pm_...@system-suspend-modeset.html

  * igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl:  [PASS][18] -> [FAIL][19] ([i915#2521])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-skl6/igt@kms_async_fl...@alternate-sync-async-flip.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/shard-skl9/igt@kms_async_fl...@alternate-sync-async-flip.html

  * igt@kms_chamelium@hdmi-cmp-planar-formats:
- shard-glk:  NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +1 
similar issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/shard-glk2/igt@kms_chamel...@hdmi-cmp-planar-formats.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- shard-hsw:  NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +1 
similar issue
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/shard-hsw1/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
- shard-skl:  NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827]) +2 
similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/shard-skl8/igt@kms_color_chamel...@pipe-invalid-ctm-matrix-sizes.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl:  

Re: [Intel-gfx] [PATCH v2] drm/i915/display: Prevent double YUV range correction on HDR planes

[Ville Syrjälä]

On Tue, Dec 15, 2020 at 10:42:19PM +, Andres Calderon Jaramillo wrote:
> From: Andres Calderon Jaramillo 
> 
> Prevent the ICL HDR plane pipeline from performing YUV color range
> correction twice when the input is in limited range. This is done by
> removing the limited-range code from icl_program_input_csc().
> 
> Before this patch the following could happen: user space gives us a YUV
> buffer in limited range; per the pipeline in [1], the plane would first
> go through a "YUV Range correct" stage that expands the range; the plane
> would then go through the "Input CSC" stage which would also expand the
> range because icl_program_input_csc() would use a matrix and an offset
> that assume limited-range input; this would ultimately cause dark and
> light colors to appear darker and lighter than they should respectively.
> 
> This is an issue because if a buffer switches between being scanned out
> and being composited with the GPU, the user will see a color difference.
> If this switching happens quickly and frequently, the user will perceive
> this as a flickering.
> 
> [1] 
> https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-icllp-vol12-displayengine_0.pdf#page=281
> 
> Signed-off-by: Andres Calderon Jaramillo 

Thanks. Slapped a cc:stable on this and pushed.

> ---
> Changelog since v1:
> - Don't skip the YUV range correction stage. Instead, use that stage and
>   modify icl_program_input_csc() to always assume full-range input.
> 
>  drivers/gpu/drm/i915/display/intel_display.c |  2 +
>  drivers/gpu/drm/i915/display/intel_sprite.c  | 65 +++-
>  2 files changed, 12 insertions(+), 55 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 761be8deaa9b..8fb9b4f8c1df 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4811,6 +4811,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state 
> *crtc_state,
>   plane_color_ctl |= 
> PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
>   } else if (fb->format->is_yuv) {
>   plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
> + if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> + plane_color_ctl |= 
> PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
>   }
>  
>   return plane_color_ctl;
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c 
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index b7e208816074..121e1b5120fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -633,13 +633,19 @@ skl_program_scaler(struct intel_plane *plane,
>  
>  /* Preoffset values for YUV to RGB Conversion */
>  #define PREOFF_YUV_TO_RGB_HI 0x1800
> -#define PREOFF_YUV_TO_RGB_ME 0x1F00
> +#define PREOFF_YUV_TO_RGB_ME 0x
>  #define PREOFF_YUV_TO_RGB_LO 0x1800
>  
>  #define  ROFF(x)  (((x) & 0x) << 16)
>  #define  GOFF(x)  (((x) & 0x) << 0)
>  #define  BOFF(x)  (((x) & 0x) << 16)
>  
> +/*
> + * Programs the input color space conversion stage for ICL HDR planes.
> + * Note that it is assumed that this stage always happens after YUV
> + * range correction. Thus, the input to this stage is assumed to be
> + * in full-range YCbCr.
> + */
>  static void
>  icl_program_input_csc(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> @@ -687,52 +693,7 @@ icl_program_input_csc(struct intel_plane *plane,
>   0x0, 0x7800, 0x7F10,
>   },
>   };
> -
> - /* Matrix for Limited Range to Full Range Conversion */
> - static const u16 input_csc_matrix_lr[][9] = {
> - /*
> -  * BT.601 Limted range YCbCr -> full range RGB
> -  * The matrix required is :
> -  * [1.164384, 0.000, 1.596027,
> -  *  1.164384, -0.39175, -0.812813,
> -  *  1.164384, 2.017232, 0.]
> -  */
> - [DRM_COLOR_YCBCR_BT601] = {
> - 0x7CC8, 0x7950, 0x0,
> - 0x8D00, 0x7950, 0x9C88,
> - 0x0, 0x7950, 0x6810,
> - },
> - /*
> -  * BT.709 Limited range YCbCr -> full range RGB
> -  * The matrix required is :
> -  * [1.164384, 0.000, 1.792741,
> -  *  1.164384, -0.213249, -0.532909,
> -  *  1.164384, 2.112402, 0.]
> -  */
> - [DRM_COLOR_YCBCR_BT709] = {
> - 0x7E58, 0x7950, 0x0,
> - 0x, 0x7950, 0xADA8,
> - 0x0, 0x7950,  0x6870,
> - },
> - /*
> -  * BT.2020 Limited range YCbCr -> full range RGB
> -  * The matrix required is :
> -  * [1.164, 0.000, 1.678,
> -  *  

Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Ville Syrjälä]

On Wed, Jan 27, 2021 at 03:38:30PM +0530, Tejas Upadhyay wrote:
> For Legacy S3 suspend/resume GEN9 BC needs to enable and
> setup TGP PCH.
> 
> Cc: Matt Roper 
> Signed-off-by: Tejas Upadhyay 
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 36 -
>  1 file changed, 27 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index a31980f69120..6dcefc3e24ac 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3026,8 +3026,20 @@ static void gen8_irq_reset(struct drm_i915_private 
> *dev_priv)
>   GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
>   GEN3_IRQ_RESET(uncore, GEN8_PCU_);
>  
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + GEN3_IRQ_RESET(uncore, SDE);
> + else if (HAS_PCH_SPLIT(dev_priv))
>   ibx_irq_reset(dev_priv);
> +
> + /* Wa_14010685332:cnp/cmp,tgp,adp */
> + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> + INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> +  SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> +  SBCLK_RUN_REFCLK_DIS, 0);
> + }

Time to refactor instead of copypasta.

>  }
>  
>  static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3442,6 +3454,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private 
> *dev_priv)
>   ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
>  
>   spt_hpd_detection_setup(dev_priv);
> +
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + icp_hpd_irq_setup(dev_priv);
>  }
>  
>  static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
> @@ -3729,9 +3744,19 @@ static void gen8_de_irq_postinstall(struct 
> drm_i915_private *dev_priv)
>   }
>  }
>  
> +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = _priv->uncore;
> + u32 mask = SDE_GMBUS_ICP;
> +
> + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0x);
> +}
> +
>  static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
>  {
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + icp_irq_postinstall(dev_priv);
> + else if (HAS_PCH_SPLIT(dev_priv))
>   ibx_irq_postinstall(dev_priv);
>  
>   gen8_gt_irq_postinstall(_priv->gt);
> @@ -3740,13 +3765,6 @@ static void gen8_irq_postinstall(struct 
> drm_i915_private *dev_priv)
>   gen8_master_intr_enable(dev_priv->uncore.regs);
>  }
>  
> -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> -{
> - struct intel_uncore *uncore = _priv->uncore;
> - u32 mask = SDE_GMBUS_ICP;
> -
> - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0x);
> -}
>  
>  static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
>  {
> -- 
> 2.30.0
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Drop active.lock around active request read inside execlists

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Drop active.lock around active request read inside 
execlists
URL   : https://patchwork.freedesktop.org/series/86356/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9688_full -> Patchwork_19521_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19521_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19521_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19521_full:

### IGT changes ###

 Possible regressions 

  * igt@debugfs_test@sysfs:
- shard-tglb: [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb5/igt@debugfs_t...@sysfs.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/shard-tglb7/igt@debugfs_t...@sysfs.html

  * igt@gem_exec_parallel@fds@rcs0:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb4/igt@gem_exec_parallel@f...@rcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/shard-iclb1/igt@gem_exec_parallel@f...@rcs0.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@sysfs_clients@busy@vecs0}:
- shard-kbl:  [PASS][5] -> [FAIL][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl1/igt@sysfs_clients@b...@vecs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/shard-kbl4/igt@sysfs_clients@b...@vecs0.html

  
Known issues


  Here are the changes found in Patchwork_19521_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][7] -> [FAIL][8] ([i915#2846])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk7/igt@gem_exec_f...@basic-deadline.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/shard-glk1/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) +2 similar 
issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/shard-tglb2/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-apl:  [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-apl6/igt@gem_exec_fair@basic-n...@vcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/shard-apl4/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl:  [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl3/igt@gem_exec_fair@basic-p...@vcs1.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/shard-kbl2/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][17] ([fdo#109283])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/shard-iclb4/igt@gem_exec_par...@no-vebox.html

  * igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-iclb: [PASS][18] -> [DMESG-WARN][19] ([i915#2803])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb3/igt@gem_exec_schedule@u-fairsl...@rcs0.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/shard-iclb6/igt@gem_exec_schedule@u-fairsl...@rcs0.html

  * igt@gem_exec_whisper@basic-queues-priority-all:
- shard-glk:  [PASS][20] -> [DMESG-WARN][21] ([i915#118] / 
[i915#95])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk6/igt@gem_exec_whis...@basic-queues-priority-all.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/shard-glk7/igt@gem_exec_whis...@basic-queues-priority-all.html

  * igt@gen7_exec_parse@basic-allowed:
- shard-skl:  NOTRUN -> [SKIP][22] ([fdo#109271]) +9 similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/shard-skl9/igt@gen7_exec_pa...@basic-allowed.html

  * 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Move struct drm_device.pdev to legacy (rev5)

[Patchwork]

== Series Details ==

Series: drm: Move struct drm_device.pdev to legacy (rev5)
URL   : https://patchwork.freedesktop.org/series/84205/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9688_full -> Patchwork_19519_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19519_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_ctx_persistence@many-contexts}:
- shard-tglb: [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/shard-tglb7/igt@gem_ctx_persiste...@many-contexts.html

  
Known issues


  Here are the changes found in Patchwork_19519_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-apl:  [PASS][3] -> [FAIL][4] ([i915#2842]) +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-apl6/igt@gem_exec_fair@basic-n...@vcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/shard-apl8/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][5] ([i915#2842])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl:  [PASS][6] -> [SKIP][7] ([fdo#109271])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl3/igt@gem_exec_fair@basic-p...@vcs1.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb1/igt@gem_exec_fair@basic-p...@vecs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/shard-tglb7/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][14] ([fdo#109283])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/shard-iclb2/igt@gem_exec_par...@no-vebox.html

  * igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-iclb: [PASS][15] -> [DMESG-WARN][16] ([i915#2803])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb3/igt@gem_exec_schedule@u-fairsl...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/shard-iclb3/igt@gem_exec_schedule@u-fairsl...@rcs0.html

  * igt@gem_exec_schedule@u-fairslice@vcs0:
- shard-skl:  [PASS][17] -> [DMESG-WARN][18] ([i915#1610] / 
[i915#2803])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-skl2/igt@gem_exec_schedule@u-fairsl...@vcs0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/shard-skl4/igt@gem_exec_schedule@u-fairsl...@vcs0.html

  * igt@gen7_exec_parse@basic-allowed:
- shard-skl:  NOTRUN -> [SKIP][19] ([fdo#109271]) +9 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/shard-skl5/igt@gen7_exec_pa...@basic-allowed.html

  * igt@i915_module_load@reload-with-fault-injection:
- shard-skl:  [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) +1 
similar issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-skl2/igt@i915_module_l...@reload-with-fault-injection.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/shard-skl5/igt@i915_module_l...@reload-with-fault-injection.html

  * igt@i915_pm_rpm@system-suspend-modeset:
- shard-kbl:  [PASS][22] -> [INCOMPLETE][23] ([i915#151])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl7/igt@i915_pm_...@system-suspend-modeset.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/shard-kbl4/igt@i915_pm_...@system-suspend-modeset.html

  * igt@kms_chamelium@hdmi-cmp-planar-formats:

Re: [Intel-gfx] [PULL] drm-intel-next

[Ville Syrjälä]

On Wed, Jan 27, 2021 at 09:08:22AM -0500, Rodrigo Vivi wrote:
> Hi Dave and Daniel,
> 
> Hopefully this is the last pull request towards 5.12.
> 
> Please notice this contains a drm/framebuffer change needed for
> supporting clear color support for TGL Render Decompression.
> 
> Here goes drm-intel-next-2021-01-27:
> 
...
> - Async flips for all ilk+ platforms (Ville)

Not quite yet. Still missing one rb so couldn't push the full thing.
So still limited to skl+ I'm afraid.

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] drm/i915: Disable runtime power management during shutdown

[Almahallawy, Khaled]

On Wed, 2021-01-27 at 20:19 +0200, Imre Deak wrote:
> At least on some TGL platforms PUNIT wants to access some display HW
> registers, but it doesn't handle display power managment (disabling
> DC
> states as required) and so this register access will lead to a hang.
> To
> prevent this disable runtime power management for poweroff and
> reboot.
> 
> Reported-and-tested-by: Khaled Almahallawy <
> khaled.almahall...@intel.com>
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 0037b81d991e..6f83cca8e27b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1054,6 +1054,8 @@ static void intel_shutdown_encoders(struct
> drm_i915_private *dev_priv)
>  void i915_driver_shutdown(struct drm_i915_private *i915)
>  {
>   disable_rpm_wakeref_asserts(>runtime_pm);
> + intel_runtime_pm_disable(>runtime_pm);
> + intel_power_domains_disable(i915);
>  
>   i915_gem_suspend(i915);
>  
> @@ -1069,7 +1071,10 @@ void i915_driver_shutdown(struct
> drm_i915_private *i915)
>   intel_suspend_encoders(i915);
>   intel_shutdown_encoders(i915);
>  
> + intel_power_domains_driver_remove(i915);
>   enable_rpm_wakeref_asserts(>runtime_pm);
> +
> + intel_runtime_pm_driver_release(>runtime_pm);
>  }
>  
>  static bool suspend_to_idle(struct drm_i915_private *dev_priv)

Reviewed-by: Khaled Almahallawy 
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/4] drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/4] drm/i915/hdcp: Disable the QSES check for 
HDCP 1.4 over MST
URL   : https://patchwork.freedesktop.org/series/86325/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9686_full -> Patchwork_19513_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19513_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_ctx_persistence@many-contexts}:
- shard-tglb: [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9686/shard-tglb6/igt@gem_ctx_persiste...@many-contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/shard-tglb6/igt@gem_ctx_persiste...@many-contexts.html

  
Known issues


  Here are the changes found in Patchwork_19513_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  [PASS][3] -> [FAIL][4] ([i915#2842]) +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9686/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/shard-kbl2/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk:  [PASS][5] -> [FAIL][6] ([i915#2842]) +2 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9686/shard-glk7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/shard-glk3/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9686/shard-iclb8/igt@gem_exec_fair@basic-p...@vcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/shard-iclb6/igt@gem_exec_fair@basic-p...@vcs0.html
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9686/shard-tglb2/igt@gem_exec_fair@basic-p...@vcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/shard-tglb2/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][11] ([i915#2389])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/shard-iclb2/igt@gem_exec_reloc@basic-wide-act...@vcs1.html

  * igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-skl:  [PASS][12] -> [DMESG-WARN][13] ([i915#2803])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9686/shard-skl1/igt@gem_exec_schedule@u-fairsl...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/shard-skl8/igt@gem_exec_schedule@u-fairsl...@rcs0.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][14] -> [SKIP][15] ([i915#2190])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9686/shard-tglb5/igt@gem_huc_c...@huc-copy.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/shard-tglb6/igt@gem_huc_c...@huc-copy.html

  * igt@gem_render_copy@y-tiled-to-vebox-x-tiled:
- shard-glk:  NOTRUN -> [SKIP][16] ([fdo#109271]) +12 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/shard-glk3/igt@gem_render_c...@y-tiled-to-vebox-x-tiled.html

  * igt@i915_selftest@live@evict:
- shard-skl:  NOTRUN -> [INCOMPLETE][17] ([i915#198] / [i915#2782])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/shard-skl8/igt@i915_selftest@l...@evict.html

  * igt@i915_selftest@live@gt_pm:
- shard-skl:  NOTRUN -> [DMESG-FAIL][18] ([i915#1886] / [i915#2291])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/shard-skl8/igt@i915_selftest@live@gt_pm.html

  * igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][19] -> [FAIL][20] ([i915#2597])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9686/shard-tglb5/igt@kms_async_fl...@test-time-stamp.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/shard-tglb6/igt@kms_async_fl...@test-time-stamp.html

  * igt@kms_chamelium@hdmi-cmp-planar-formats:
- shard-iclb: NOTRUN -> [SKIP][21] ([fdo#109284] / [fdo#111827])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/shard-iclb3/igt@kms_chamel...@hdmi-cmp-planar-formats.html

  * igt@kms_chamelium@vga-hpd-after-suspend:
- shard-glk:  NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/shard-glk9/igt@kms_chamel...@vga-hpd-after-suspend.html

  * 

Re: [Intel-gfx] linux-next: Tree for Jan 27 (drm/i915)

[Chris Wilson]

Quoting Randy Dunlap (2021-01-27 20:28:05)
> On 1/27/21 11:30 AM, Randy Dunlap wrote:
> > On 1/27/21 11:08 AM, Randy Dunlap wrote:
> >> On 1/27/21 6:44 AM, Stephen Rothwell wrote:
> >>> Hi all,
> >>>
> >>> Note: the patch file has failed to upload :-(
> >>>
> >>> Changes since 20210125:
> >>>
> >>
> >> on x86_64:
> >>
> >> ../drivers/gpu/drm/i915/i915_gem.c: In function ‘i915_gem_freeze_late’:
> >> ../drivers/gpu/drm/i915/i915_gem.c:1182:2: error: implicit declaration of 
> >> function ‘wbinvd_on_all_cpus’; did you mean ‘wrmsr_on_cpus’? 
> >> [-Werror=implicit-function-declaration]
> >>   wbinvd_on_all_cpus();
> >>
> > 
> > My apologies: this was in Andrew's mmotm 2021-01-25.
> > Sorry about that.
> 
> 
> and now I see that it also happens in today's linux-next.

The fix is in the tree that should be feeding into linux-next, so I
trust it will resolve itself shortly. Along with the WERROR depends
snafu.
-Chris
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Re: [Intel-gfx] [PATCH v13 1/2] drm/i915/display: Support PSR Multiple Instances

[Souza, Jose]

On Wed, 2021-01-27 at 19:23 +0200, Gwan-gyeong Mun wrote:
> It is a preliminary work for supporting multiple EDP PSR and
> DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
> supportable PSR.
> And this moves and renames the i915_psr structure of drm_i915_private's to
> intel_dp's intel_psr structure.
> It also causes changes in PSR interrupt handling routine for supporting
> multiple transcoders. But it does not change the scenario and timing of
> enabling and disabling PSR. And it not support multiple pipes with
> a single transcoder PSR case yet.
> 
> v2: Fix indentation and add comments
> v3: Remove Blank line
> v4: Rebased
> v5: Rebased and Addressed Anshuman's review comment.
> - Move calling of intel_psr_init() to intel_dp_init_connector()
> v6: Address Anshuman's review comments
>- Remove wrong comments and add comments for a limit of supporting of
>  a single pipe PSR
> v7: Update intel_psr_compute_config() for supporting multiple transcoder
> PSR on BDW+
> v8: Address Anshuman's review comments
>- Replace DRM_DEBUG_KMS with drm_dbg_kms() / DRM_WARN with drm_warn()
> v9: Fix commit message
> v10: Rebased
> v11: Address Jose's review comment.
>   - Reorder calling order of intel_psr2_program_trans_man_trk_ctl().
>   - In order to reduce changes keep the old name for drm_i915_private.
>   - Change restrictions of multiple instances of PSR.
> v12: Address Jose's review comment.
>   - Change the calling of intel_psr2_program_trans_man_trk_ctl() into
> commit_pipe_config().
>   - Change a checking order of CAN_PSR() and connector_status to original
> on i915_psr_sink_status_show().
>   - Drop unneeded intel_dp_update_pipe() function.
>   - In order to wait a specific encoder which belong to crtc_state on
> intel_psr_wait_for_idle(), add checking of encoder.
>   - Add an whitespace to comments.
> v13: Rebased and Address Jose's review comment.
>   - Add and use for_each_intel_psr_enabled_encoder() macro.
>   - In order to use correct frontbuffer_bit for each pipe,
> fix intel_psr_invalidate() and intel_psr_flush().
>   - Remove redundant or unneeded codes.
>   - Update comments.
> 
> Signed-off-by: Gwan-gyeong Mun 
> Cc: José Roberto de Souza 
> Cc: Juha-Pekka Heikkila 
> Cc: Anshuman Gupta 
> Reviewed-by: Anshuman Gupta 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |   2 -
>  drivers/gpu/drm/i915/display/intel_display.h  |   8 +
>  .../drm/i915/display/intel_display_debugfs.c  | 105 +++-
>  .../drm/i915/display/intel_display_types.h|  46 ++
>  drivers/gpu/drm/i915/display/intel_dp.c   |  10 +-
>  drivers/gpu/drm/i915/display/intel_psr.c  | 576 ++
>  drivers/gpu/drm/i915/display/intel_psr.h  |  11 +-
>  drivers/gpu/drm/i915/display/intel_sprite.c   |   6 +-
>  drivers/gpu/drm/i915/i915_drv.h   |  38 --
>  drivers/gpu/drm/i915/i915_irq.c   |  48 +-
>  10 files changed, 485 insertions(+), 365 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 667d941878a3..24df9dfb57fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14135,8 +14135,6 @@ static void intel_setup_outputs(struct 
> drm_i915_private *dev_priv)
>   intel_dvo_init(dev_priv);
>   }
>  
> 
> - intel_psr_init(dev_priv);
> -
>   for_each_intel_encoder(_priv->drm, encoder) {
>   encoder->base.possible_crtcs =
>   intel_encoder_possible_crtcs(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h 
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 64ffa34544a7..fc41d0d9e5a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -417,6 +417,14 @@ enum phy_fia {
>   for_each_if((encoder_mask) &\
>   drm_encoder_mask(_encoder->base))
>  
> 
> +#define for_each_intel_encoder_is_psr_enabled(dev, intel_encoder, 
> encoder_mask) \

I'm not a native speaker but "is" sounds wrong, maybe 
for_each_intel_encoder_with_psr_enabled()?


> + list_for_each_entry(intel_encoder,  \
> + &(dev)->mode_config.encoder_list,   \
> + base.head)  \
> + for_each_if(((encoder_mask) &   \
> +  drm_encoder_mask(_encoder->base)) && \
> + intel_encoder_is_psr_enabled(intel_encoder))

Looks like style is wrong here but bot will tell you if it is.

> +
>  #define for_each_intel_dp(dev, intel_encoder)\
>   for_each_intel_encoder(dev, intel_encoder)  \
>   for_each_if(intel_encoder_is_dp(intel_encoder))
> diff --git 

Re: [Intel-gfx] linux-next: Tree for Jan 27 (drm/i915)

[Randy Dunlap]

On 1/27/21 11:30 AM, Randy Dunlap wrote:
> On 1/27/21 11:08 AM, Randy Dunlap wrote:
>> On 1/27/21 6:44 AM, Stephen Rothwell wrote:
>>> Hi all,
>>>
>>> Note: the patch file has failed to upload :-(
>>>
>>> Changes since 20210125:
>>>
>>
>> on x86_64:
>>
>> ../drivers/gpu/drm/i915/i915_gem.c: In function ‘i915_gem_freeze_late’:
>> ../drivers/gpu/drm/i915/i915_gem.c:1182:2: error: implicit declaration of 
>> function ‘wbinvd_on_all_cpus’; did you mean ‘wrmsr_on_cpus’? 
>> [-Werror=implicit-function-declaration]
>>   wbinvd_on_all_cpus();
>>
> 
> My apologies: this was in Andrew's mmotm 2021-01-25.
> Sorry about that.


and now I see that it also happens in today's linux-next.

-- 
~Randy

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Patchwork]

== Series Details ==

Series: drm/i915/gen9bc: Handle TGP PCH during suspend/resume
URL   : https://patchwork.freedesktop.org/series/86346/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9688_full -> Patchwork_19518_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19518_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_ctx_persistence@many-contexts}:
- shard-tglb: [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-tglb8/igt@gem_ctx_persiste...@many-contexts.html

  
Known issues


  Here are the changes found in Patchwork_19518_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][3] ([i915#2842])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2842]) +1 similar issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-glk4/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][8] ([fdo#109283])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-iclb1/igt@gem_exec_par...@no-vebox.html

  * igt@gen7_exec_parse@basic-allowed:
- shard-skl:  NOTRUN -> [SKIP][9] ([fdo#109271]) +9 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl10/igt@gen7_exec_pa...@basic-allowed.html

  * igt@i915_pm_rpm@system-suspend-modeset:
- shard-kbl:  [PASS][10] -> [INCOMPLETE][11] ([i915#151])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl7/igt@i915_pm_...@system-suspend-modeset.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-kbl6/igt@i915_pm_...@system-suspend-modeset.html

  * igt@kms_chamelium@hdmi-cmp-planar-formats:
- shard-glk:  NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +1 
similar issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-glk7/igt@kms_chamel...@hdmi-cmp-planar-formats.html

  * igt@kms_color@pipe-a-ctm-0-5:
- shard-skl:  [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-skl10/igt@kms_co...@pipe-a-ctm-0-5.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl8/igt@kms_co...@pipe-a-ctm-0-5.html

  * igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
- shard-skl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +2 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl10/igt@kms_color_chamel...@pipe-invalid-ctm-matrix-sizes.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-skl:  [PASS][16] -> [FAIL][17] ([i915#54]) +4 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-skl9/igt@kms_cursor_...@pipe-a-cursor-128x42-onscreen.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl6/igt@kms_cursor_...@pipe-a-cursor-128x42-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen:
- shard-skl:  NOTRUN -> [FAIL][18] ([i915#54])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl7/igt@kms_cursor_...@pipe-b-cursor-128x128-onscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-128x42-random:
- shard-glk:  NOTRUN -> [SKIP][19] ([fdo#109271]) +3 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-glk7/igt@kms_cursor_...@pipe-d-cursor-128x42-random.html

  * igt@kms_cursor_crc@pipe-d-cursor-256x256-sliding:
- shard-kbl:  NOTRUN -> [SKIP][20] ([fdo#109271]) +4 similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-kbl7/igt@kms_cursor_...@pipe-d-cursor-256x256-sliding.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable runtime power management during shutdown

[Patchwork]

== Series Details ==

Series: drm/i915: Disable runtime power management during shutdown
URL   : https://patchwork.freedesktop.org/series/86362/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9688 -> Patchwork_19524


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/index.html

Known issues


  Here are the changes found in Patchwork_19524 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-byt-j1900:   NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/fi-byt-j1900/igt@gem_huc_c...@huc-copy.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-byt-j1900:   NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/fi-byt-j1900/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y:   [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar 
issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html

  
 Possible fixes 

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +2 similar 
issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
 Warnings 

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:[SKIP][7] ([fdo#109271]) -> [SKIP][8] ([fdo#109271] / 
[i915#3012])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:[SKIP][9] ([fdo#109271]) -> [SKIP][10] ([fdo#109271] 
/ [fdo#109289])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-4770:[SKIP][11] ([fdo#109271]) -> [SKIP][12] ([fdo#109271] 
/ [i915#533])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#3011]: https://gitlab.freedesktop.org/drm/intel/issues/3011
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Participating hosts (45 -> 39)
--

  Additional (1): fi-byt-j1900 
  Missing(7): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 
fi-cml-drallion fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9688 -> Patchwork_19524

  CI-20190529: 20190529
  CI_DRM_9688: 43295c2b7bc37446a480bb5d42b03675baed171a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5974: a85398dcae50930c0e27548cf8c9575ad0bf69d1 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19524: 207a500f0a86f5a8bc5ceff6b57a86f07f606cbe @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

207a500f0a86 drm/i915: Disable runtime power management during shutdown

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/index.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Disable runtime power management during shutdown

[Patchwork]

== Series Details ==

Series: drm/i915: Disable runtime power management during shutdown
URL   : https://patchwork.freedesktop.org/series/86362/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
207a500f0a86 drm/i915: Disable runtime power management during shutdown
-:7: WARNING:TYPO_SPELLING: 'managment' may be misspelled - perhaps 
'management'?
#7: 
registers, but it doesn't handle display power managment (disabling DC
   ^

total: 0 errors, 1 warnings, 0 checks, 18 lines checked


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Re: [Intel-gfx] mmotm 2021-01-25-21-18 uploaded (drm/i915/Kconfig.debug)

[Randy Dunlap]

On 1/25/21 9:19 PM, a...@linux-foundation.org wrote:
> The mm-of-the-moment snapshot 2021-01-25-21-18 has been uploaded to
> 
>https://www.ozlabs.org/~akpm/mmotm/
> 
> mmotm-readme.txt says
> 
> README for mm-of-the-moment:
> 
> https://www.ozlabs.org/~akpm/mmotm/
> 
> This is a snapshot of my -mm patch queue.  Uploaded at random hopefully
> more than once a week.
> 
> You will need quilt to apply these patches to the latest Linus release (5.x
> or 5.x-rcY).  The series file is in broken-out.tar.gz and is duplicated in
> https://ozlabs.org/~akpm/mmotm/series
> 
> The file broken-out.tar.gz contains two datestamp files: .DATE and
> .DATE--mm-dd-hh-mm-ss.  Both contain the string -mm-dd-hh-mm-ss,
> followed by the base kernel version against which this patch series is to
> be applied.

on x86_64:

when CONFIG_COMPILE_TEST=y:

WARNING: unmet direct dependencies detected for DRM_I915_WERROR
  Depends on [n]: HAS_IOMEM [=y] && DRM_I915 [=m] && EXPERT [=y] && 
!COMPILE_TEST [=y]
  Selected by [m]:
  - DRM_I915_DEBUG [=y] && HAS_IOMEM [=y] && EXPERT [=y] && DRM_I915 [=m]


-- 
~Randy
Reported-by: Randy Dunlap 

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v13,1/2] drm/i915/display: Support PSR Multiple Instances

[Patchwork]

== Series Details ==

Series: series starting with [v13,1/2] drm/i915/display: Support PSR Multiple 
Instances
URL   : https://patchwork.freedesktop.org/series/86361/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9688 -> Patchwork_19523


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_19523:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_psr@cursor_plane_move:
- {fi-rkl-11500t}:[SKIP][1] ([i915#1072]) -> [SKIP][2] +3 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-rkl-11500t/igt@kms_psr@cursor_plane_move.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/fi-rkl-11500t/igt@kms_psr@cursor_plane_move.html

  * igt@kms_psr@primary_mmap_gtt:
- {fi-tgl-dsi}:   [SKIP][3] ([fdo#110189]) -> [SKIP][4] +3 similar 
issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html

  
Known issues


  Here are the changes found in Patchwork_19523 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [PASS][5] -> [DMESG-WARN][6] ([i915#1982] / 
[i915#402])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@gem_exec_suspend@basic-s0:
- fi-tgl-u2:  [PASS][7] -> [FAIL][8] ([i915#1888])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-y:   [PASS][9] -> [DMESG-WARN][10] ([i915#2411] / 
[i915#402])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html

  * igt@gem_flink_basic@bad-flink:
- fi-tgl-y:   [PASS][11] -> [DMESG-WARN][12] ([i915#402])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html

  * igt@gem_huc_copy@huc-copy:
- fi-byt-j1900:   NOTRUN -> [SKIP][13] ([fdo#109271]) +27 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/fi-byt-j1900/igt@gem_huc_c...@huc-copy.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-n3050:   [PASS][14] -> [INCOMPLETE][15] ([i915#2940])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-byt-j1900:   NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/fi-byt-j1900/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@runner@aborted:
- fi-bsw-n3050:   NOTRUN -> [FAIL][17] ([i915#1436])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/fi-bsw-n3050/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_basic@bad-close:
- fi-tgl-y:   [DMESG-WARN][18] ([i915#402]) -> [PASS][19] +1 
similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@gem_ba...@bad-close.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/fi-tgl-y/igt@gem_ba...@bad-close.html

  
 Warnings 

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:[SKIP][20] ([fdo#109271]) -> [SKIP][21] ([fdo#109271] 
/ [i915#3012])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19523/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:[SKIP][22] ([fdo#109271]) -> [SKIP][23] ([fdo#109271] 
/ [fdo#109289])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
   [23]: 

Re: [Intel-gfx] linux-next: Tree for Jan 27 (drm/i915)

[Randy Dunlap]

On 1/27/21 11:08 AM, Randy Dunlap wrote:
> On 1/27/21 6:44 AM, Stephen Rothwell wrote:
>> Hi all,
>>
>> Note: the patch file has failed to upload :-(
>>
>> Changes since 20210125:
>>
> 
> on x86_64:
> 
> ../drivers/gpu/drm/i915/i915_gem.c: In function ‘i915_gem_freeze_late’:
> ../drivers/gpu/drm/i915/i915_gem.c:1182:2: error: implicit declaration of 
> function ‘wbinvd_on_all_cpus’; did you mean ‘wrmsr_on_cpus’? 
> [-Werror=implicit-function-declaration]
>   wbinvd_on_all_cpus();
> 

My apologies: this was in Andrew's mmotm 2021-01-25.
Sorry about that.

-- 
~Randy

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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST (rev2)

[Vudum, Lakshminarayana]

I am not totally sure why shard run is not triggered here 
https://patchwork.freedesktop.org/series/8/#rev2
@Latvala, Petri any help here?

Thanks,
Lakshmi.

-Original Message-
From: Gupta, Anshuman  
Sent: Tuesday, January 26, 2021 11:38 PM
To: Vudum, Lakshminarayana ; 
intel-gfx@lists.freedesktop.org
Cc: Sean Paul 
Subject: RE: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/hdcp: Disable the 
QSES check for HDCP 1.4 over MST (rev2)



> -Original Message-
> From: Vudum, Lakshminarayana 
> Sent: Wednesday, January 27, 2021 11:00 AM
> To: Gupta, Anshuman ; intel- 
> g...@lists.freedesktop.org
> Cc: Sean Paul 
> Subject: RE: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/hdcp: 
> Disable the QSES check for HDCP 1.4 over MST (rev2)
> 
> Re-reporting will just re-report the results once more time. 
> Re-reporting will re-check if there is an existing bug for the 
> regression failures or not. If a bug is found, series shows as success (as 
> the failure is not a regression).
> Regression failures will find a bug when a re-report as I either file 
> a new bug or I will associate the regression failure to an existing bug 
> before I re-report.
> 
> But re-reporting will not trigger re-run to see version 2 results. Let 
> me know if you have any further questions.
We don't have CI-IGT (full) results for the series 
https://patchwork.freedesktop.org/series/8/#rev2 yet.
In order to merge this patch we would require CI pre merge results.
Thanks,
Anshuman Gupta.
> 
> Thanks,
> Lakshmi.
> -Original Message-
> From: Gupta, Anshuman 
> Sent: Tuesday, January 26, 2021 9:20 PM
> To: Vudum, Lakshminarayana ; intel- 
> g...@lists.freedesktop.org
> Cc: Sean Paul 
> Subject: RE: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/hdcp: 
> Disable the QSES check for HDCP 1.4 over MST (rev2)
> 
> Thanks Lakshmi for re-reporting it.
> May I know that re-reporting will also trigger a CI-IGT run.
> I am not able to see this series in CI Queue https://intel-gfx- 
> ci.01.org/queue/index.html Currently this patch Rev2 is not showing 
> any CI-IGT results.
> 
> Br,
> Anshuman
> 
> > -Original Message-
> > From: Vudum, Lakshminarayana 
> > Sent: Monday, January 25, 2021 10:40 PM
> > To: Gupta, Anshuman ; intel- 
> > g...@lists.freedesktop.org
> > Cc: Sean Paul 
> > Subject: RE: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/hdcp:
> > Disable the QSES check for HDCP 1.4 over MST (rev2)
> >
> > Re-reported.
> >
> > -Original Message-
> > From: Gupta, Anshuman 
> > Sent: Monday, January 25, 2021 7:26 AM
> > To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 
> > 
> > Cc: Sean Paul 
> > Subject: RE: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/hdcp:
> > Disable the QSES check for HDCP 1.4 over MST (rev2)
> >
> > Hi Lakshmi ,
> > We need to merge the patch
> > https://patchwork.freedesktop.org/series/8/
> > Below are the gem failures causing the BAT to fail , those were not 
> > seen on
> > Rev1 of this patch.
> > Could you please rereport-the results to trigger CI-IGT run.
> > Thanks,
> > Anshuman Gupta.
> >
> > From: Intel-gfx  On Behalf 
> > Of Patchwork
> > Sent: Friday, January 22, 2021 8:13 AM
> > To: Sean Paul 
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/hdcp: Disable 
> > the QSES check for HDCP 1.4 over MST (rev2)
> >
> > Patch Details
> > Series:
> > drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST (rev2)
> > URL:
> > https://patchwork.freedesktop.org/series/8/
> > State:
> > failure
> > Details:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19447/index.html
> > CI Bug Log - changes from CI_DRM_9666 -> Patchwork_19447 Summary 
> > FAILURE Serious unknown changes coming with Patchwork_19447
> absolutely
> > need to be verified manually.
> > If you think the reported changes have nothing to do with the 
> > changes introduced in Patchwork_19447, please notify your bug team 
> > to allow them to document this new failure mode, which will reduce 
> > false positives
> in CI.
> > External URL: https://intel-gfx-ci.01.org/tree/drm-
> > tip/Patchwork_19447/index.html
> > Possible new issues
> > Here are the unknown changes that may have been introduced in
> > Patchwork_19447:
> > IGT changes
> > Possible regressions
> > • igt@i915_selftest@live@gt_lrc:
> > o fi-bsw-n3050:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9666/fi-
> > bsw-n3050/igt@i915_selftest@live@gt_lrc.html -> https://intel-gfx-
> > ci.01.org/tree/drm-tip/Patchwork_19447/fi-bsw-
> > n3050/igt@i915_selftest@live@gt_lrc.html
> > Known issues
> > Here are the changes found in Patchwork_19447 that come from known
> > issues:
> > IGT changes
> > Issues hit
> > • igt@gem_mmap_gtt@basic:
> > o fi-tgl-y:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9666/fi-tgl-
> > y/igt@gem_mmap_...@basic.html -> https://intel-gfx-
> ci.01.org/tree/drm-
> > tip/Patchwork_19447/fi-tgl-y/igt@gem_mmap_...@basic.html
> > 

Re: [Intel-gfx] linux-next: Tree for Jan 27 (drm/i915)

[Randy Dunlap]

On 1/27/21 6:44 AM, Stephen Rothwell wrote:
> Hi all,
> 
> Note: the patch file has failed to upload :-(
> 
> Changes since 20210125:
> 

on x86_64:

../drivers/gpu/drm/i915/i915_gem.c: In function ‘i915_gem_freeze_late’:
../drivers/gpu/drm/i915/i915_gem.c:1182:2: error: implicit declaration of 
function ‘wbinvd_on_all_cpus’; did you mean ‘wrmsr_on_cpus’? 
[-Werror=implicit-function-declaration]
  wbinvd_on_all_cpus();


-- 
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Reported-by: Randy Dunlap 

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v13,1/2] drm/i915/display: Support PSR Multiple Instances

[Patchwork]

== Series Details ==

Series: series starting with [v13,1/2] drm/i915/display: Support PSR Multiple 
Instances
URL   : https://patchwork.freedesktop.org/series/86361/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1327:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 
279040
+drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 
'wakeref_auto_timeout' - unexpected unlock
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - 
different lock contexts for basic 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v13,1/2] drm/i915/display: Support PSR Multiple Instances

[Patchwork]

== Series Details ==

Series: series starting with [v13,1/2] drm/i915/display: Support PSR Multiple 
Instances
URL   : https://patchwork.freedesktop.org/series/86361/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a69d1c74e99d drm/i915/display: Support PSR Multiple Instances
-:80: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#80: FILE: drivers/gpu/drm/i915/display/intel_display.h:420:
+#define for_each_intel_encoder_is_psr_enabled(dev, intel_encoder, 
encoder_mask) \
+   list_for_each_entry(intel_encoder,  \
+   &(dev)->mode_config.encoder_list,   \
+   base.head)  \
+   for_each_if(((encoder_mask) &   \
+drm_encoder_mask(_encoder->base)) && \
+   intel_encoder_is_psr_enabled(intel_encoder))

-:80: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_encoder' - possible 
side-effects?
#80: FILE: drivers/gpu/drm/i915/display/intel_display.h:420:
+#define for_each_intel_encoder_is_psr_enabled(dev, intel_encoder, 
encoder_mask) \
+   list_for_each_entry(intel_encoder,  \
+   &(dev)->mode_config.encoder_list,   \
+   base.head)  \
+   for_each_if(((encoder_mask) &   \
+drm_encoder_mask(_encoder->base)) && \
+   intel_encoder_is_psr_enabled(intel_encoder))

-:1464: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#1464: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1731:
+   unsigned pipe_frontbuffer_bits = frontbuffer_bits;

-:1567: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#1567: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1813:
+   unsigned pipe_frontbuffer_bits = frontbuffer_bits;

-:1716: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible 
side-effects?
#1716: FILE: drivers/gpu/drm/i915/display/intel_psr.h:21:
+#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && 
intel_dp->psr.sink_support)

total: 1 errors, 2 warnings, 2 checks, 1713 lines checked
250803287c38 drm/i915/display: Support Multiple Transcoders' PSR status on 
debugfs


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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/4] drm/i915: Nuke not needed members of dram_info

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/4] drm/i915: Nuke not needed members of 
dram_info
URL   : https://patchwork.freedesktop.org/series/86360/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9688 -> Patchwork_19522


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19522 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19522, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19522/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_19522:

### IGT changes ###

 Possible regressions 

  * igt@i915_module_load@reload:
- fi-glk-dsi: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-glk-dsi/igt@i915_module_l...@reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19522/fi-glk-dsi/igt@i915_module_l...@reload.html

  
Known issues


  Here are the changes found in Patchwork_19522 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy:
- fi-glk-dsi: NOTRUN -> [SKIP][3] ([fdo#109271]) +13 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19522/fi-glk-dsi/igt@gem_exec_fe...@basic-busy.html

  * igt@gem_huc_copy@huc-copy:
- fi-byt-j1900:   NOTRUN -> [SKIP][4] ([fdo#109271]) +27 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19522/fi-byt-j1900/igt@gem_huc_c...@huc-copy.html

  * igt@gem_mmap_gtt@basic:
- fi-tgl-y:   [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar 
issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@gem_mmap_...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19522/fi-tgl-y/igt@gem_mmap_...@basic.html

  * igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick:[PASS][7] -> [DMESG-FAIL][8] ([i915#2927])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19522/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html

  * igt@i915_selftest@live@sanitycheck:
- fi-kbl-7500u:   [PASS][9] -> [DMESG-WARN][10] ([i915#2605])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19522/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html

  * igt@kms_addfb_basic@invalid-set-prop-any:
- fi-glk-dsi: [PASS][11] -> [SKIP][12] ([fdo#109271]) +116 similar 
issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-glk-dsi/igt@kms_addfb_ba...@invalid-set-prop-any.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19522/fi-glk-dsi/igt@kms_addfb_ba...@invalid-set-prop-any.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-byt-j1900:   NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19522/fi-byt-j1900/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@runner@aborted:
- fi-glk-dsi: NOTRUN -> [FAIL][14] ([i915#2292] / [i915#2295] / 
[k.org#202321] / [k.org#204565])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19522/fi-glk-dsi/igt@run...@aborted.html
- fi-bsw-nick:NOTRUN -> [FAIL][15] ([i915#1436])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19522/fi-bsw-nick/igt@run...@aborted.html
- fi-bdw-5557u:   NOTRUN -> [FAIL][16] ([i915#1602] / [i915#2029] / 
[i915#2369])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19522/fi-bdw-5557u/igt@run...@aborted.html

  
 Possible fixes 

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [DMESG-WARN][17] ([i915#402]) -> [PASS][18] +2 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19522/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
 Warnings 

  * igt@gem_huc_copy@huc-copy:
- fi-glk-dsi: [SKIP][19] ([fdo#109271] / [i915#2190]) -> [SKIP][20] 
([fdo#109271])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-glk-dsi/igt@gem_huc_c...@huc-copy.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19522/fi-glk-dsi/igt@gem_huc_c...@huc-copy.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:[SKIP][21] ([fdo#109271]) -> [SKIP][22] ([fdo#109271] 
/ [i915#3012])
   

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Drop active.lock around active request read inside execlists

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Drop active.lock around active request read inside 
execlists
URL   : https://patchwork.freedesktop.org/series/86356/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9688 -> Patchwork_19521


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/index.html

Known issues


  Here are the changes found in Patchwork_19521 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-byt-j1900:   NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/fi-byt-j1900/igt@gem_huc_c...@huc-copy.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-byt-j1900:   NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/fi-byt-j1900/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@prime_vgem@basic-fence-flip:
- fi-tgl-y:   [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar 
issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@prime_v...@basic-fence-flip.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/fi-tgl-y/igt@prime_v...@basic-fence-flip.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- {fi-cml-drallion}:  [INCOMPLETE][5] ([i915#1614]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-cml-drallion/igt@gem_exec_susp...@basic-s0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/fi-cml-drallion/igt@gem_exec_susp...@basic-s0.html

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +1 similar 
issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
 Warnings 

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:[SKIP][9] ([fdo#109271]) -> [SKIP][10] ([fdo#109271] 
/ [fdo#109289])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1614]: https://gitlab.freedesktop.org/drm/intel/issues/1614
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2331]: https://gitlab.freedesktop.org/drm/intel/issues/2331
  [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (45 -> 40)
--

  Additional (1): fi-byt-j1900 
  Missing(6): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 
fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9688 -> Patchwork_19521

  CI-20190529: 20190529
  CI_DRM_9688: 43295c2b7bc37446a480bb5d42b03675baed171a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5974: a85398dcae50930c0e27548cf8c9575ad0bf69d1 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19521: 518067f3819fdddfc5364d8fa36c96d9c03e0e1c @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

518067f3819f drm/i915/gt: Drop active.lock around active request read inside 
execlists

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19521/index.html
___
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[Intel-gfx] [PATCH] drm/i915: Disable runtime power management during shutdown

[Imre Deak]

At least on some TGL platforms PUNIT wants to access some display HW
registers, but it doesn't handle display power managment (disabling DC
states as required) and so this register access will lead to a hang. To
prevent this disable runtime power management for poweroff and reboot.

Reported-and-tested-by: Khaled Almahallawy 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/i915_drv.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0037b81d991e..6f83cca8e27b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1054,6 +1054,8 @@ static void intel_shutdown_encoders(struct 
drm_i915_private *dev_priv)
 void i915_driver_shutdown(struct drm_i915_private *i915)
 {
disable_rpm_wakeref_asserts(>runtime_pm);
+   intel_runtime_pm_disable(>runtime_pm);
+   intel_power_domains_disable(i915);
 
i915_gem_suspend(i915);
 
@@ -1069,7 +1071,10 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
intel_suspend_encoders(i915);
intel_shutdown_encoders(i915);
 
+   intel_power_domains_driver_remove(i915);
enable_rpm_wakeref_asserts(>runtime_pm);
+
+   intel_runtime_pm_driver_release(>runtime_pm);
 }
 
 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
-- 
2.25.1

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hdcp: mst streams type1 capability check

[Patchwork]

== Series Details ==

Series: drm/i915/hdcp: mst streams type1 capability check
URL   : https://patchwork.freedesktop.org/series/86345/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9687_full -> Patchwork_19517_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19517_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@chamelium:
- shard-iclb: NOTRUN -> [SKIP][1] ([fdo#111827])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/shard-iclb8/igt@feature_discov...@chamelium.html

  * igt@gem_ctx_persistence@clone:
- shard-hsw:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/shard-hsw2/igt@gem_ctx_persiste...@clone.html

  * igt@gem_exec_fair@basic-deadline:
- shard-kbl:  [PASS][3] -> [FAIL][4] ([i915#2846])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-kbl2/igt@gem_exec_f...@basic-deadline.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/shard-kbl7/igt@gem_exec_f...@basic-deadline.html
- shard-glk:  [PASS][5] -> [FAIL][6] ([i915#2846])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-glk6/igt@gem_exec_f...@basic-deadline.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/shard-glk3/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl:  [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-kbl2/igt@gem_exec_fair@basic-n...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/shard-kbl6/igt@gem_exec_fair@basic-n...@rcs0.html

  * igt@gem_exec_fair@basic-none@vecs0:
- shard-apl:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-apl2/igt@gem_exec_fair@basic-n...@vecs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/shard-apl2/igt@gem_exec_fair@basic-n...@vecs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar 
issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-tglb5/igt@gem_exec_fair@basic-p...@bcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/shard-tglb3/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842]) +1 similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2849])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_reloc@basic-many-active@vcs0:
- shard-kbl:  NOTRUN -> [FAIL][16] ([i915#2389]) +4 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/shard-kbl7/igt@gem_exec_reloc@basic-many-act...@vcs0.html

  * igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-tglb: [PASS][17] -> [DMESG-WARN][18] ([i915#2803])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-tglb2/igt@gem_exec_schedule@u-fairsl...@rcs0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/shard-tglb7/igt@gem_exec_schedule@u-fairsl...@rcs0.html

  * igt@gem_exec_schedule@u-fairslice@vcs0:
- shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([i915#2803])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-iclb6/igt@gem_exec_schedule@u-fairsl...@vcs0.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/shard-iclb7/igt@gem_exec_schedule@u-fairsl...@vcs0.html

  * igt@gem_render_copy@yf-tiled-to-vebox-linear:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#768]) +1 similar issue
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/shard-iclb8/igt@gem_render_c...@yf-tiled-to-vebox-linear.html

  * igt@gem_softpin@evict-snoop-interruptible:
- shard-iclb: NOTRUN -> [SKIP][22] ([fdo#109312])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/shard-iclb8/igt@gem_soft...@evict-snoop-interruptible.html

  * igt@gen7_exec_parse@basic-allowed:
- shard-iclb: NOTRUN -> [SKIP][23] ([fdo#109289])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/shard-iclb8/igt@gen7_exec_pa...@basic-allowed.html

  * igt@i915_hangman@engine-error@vecs0:
- shard-kbl:  NOTRUN -> [SKIP][24] ([fdo#109271]) +32 similar issues
   [24]: 

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/4] drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST

[Vudum, Lakshminarayana]

Re-reported.

From: Gupta, Anshuman 
Sent: Wednesday, January 27, 2021 3:14 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Cc: Li, Juston 
Subject: RE: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/4] 
drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST

Hi Lakshmi ,
Below CI failure is a Core failures, which has failed BAT results.
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/fi-bxt-dsi/igt@i915_selftest@l...@hangcheck.html#dmesg-warnings426
Could you please re-report results.
Thanks ,
Anshuman Gupta.

From: Intel-gfx 
mailto:intel-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of Patchwork
Sent: Wednesday, January 27, 2021 1:16 PM
To: Li, Juston mailto:juston...@intel.com>>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/4] 
drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST

Patch Details
Series:

series starting with [v2,1/4] drm/i915/hdcp: Disable the QSES check for HDCP 
1.4 over MST

URL:

https://patchwork.freedesktop.org/series/86325/

State:

failure

Details:

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/index.html

CI Bug Log - changes from CI_DRM_9686 -> Patchwork_19513
Summary

FAILURE

Serious unknown changes coming with Patchwork_19513 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19513, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/index.html

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_19513:

IGT changes
Possible regressions

  *   igt@i915_selftest@live@hangcheck:

 *   fi-bxt-dsi: 
PASS
 -> 
INCOMPLETE

Known issues

Here are the changes found in Patchwork_19513 that come from known issues:

IGT changes
Issues hit

  *   igt@gem_mmap_gtt@basic:

 *   fi-tgl-y: 
PASS
 -> 
DMESG-WARN
 (i915#402) +1 similar 
issue

  *   igt@runner@aborted:

 *   fi-bxt-dsi: NOTRUN -> 
FAIL
 (i915#2426)

Possible fixes

  *   igt@gem_exec_create@basic:

 *   fi-tgl-y: 
DMESG-WARN
 (i915#402) -> 
PASS
 +1 similar issue

Participating hosts (44 -> 39)

Missing (5): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-jsl-2

Build changes

  *   Linux: CI_DRM_9686 -> Patchwork_19513

CI-20190529: 20190529
CI_DRM_9686: 8de0436dc0e777bbd5490d56134a838da4c19121 @ 
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5973: 7ae3d0d68e6bf4c5e404c87b570773d1b3173d47 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19513: cf90167ec8d878cf7739b728e49fd65c5203ac32 @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

cf90167ec8d8 drm/i915/hdcp: disable the QSES check for HDCP2.2 over MST
0f5367aacba6 drm/i915/hdcp: read RxInfo once when reading Send_Pairing_Info
c03a6673e642 drm/i915/hdcp: update cp_irq_count_cached in 
intel_dp_hdcp2_read_msg()
69e116124dea drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v5,1/8] drm/i915: make local-memory probing a GT operation

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/8] drm/i915: make local-memory probing a GT 
operation
URL   : https://patchwork.freedesktop.org/series/86355/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9688 -> Patchwork_19520


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19520 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19520, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19520/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_19520:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@workarounds:
- fi-tgl-y:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@i915_selftest@l...@workarounds.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19520/fi-tgl-y/igt@i915_selftest@l...@workarounds.html

  
Known issues


  Here are the changes found in Patchwork_19520 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +2 similar 
issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19520/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@gem_huc_copy@huc-copy:
- fi-byt-j1900:   NOTRUN -> [SKIP][5] ([fdo#109271]) +27 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19520/fi-byt-j1900/igt@gem_huc_c...@huc-copy.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u:   [PASS][6] -> [FAIL][7] ([i915#1161] / [i915#262])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19520/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-byt-j1900:   NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19520/fi-byt-j1900/igt@kms_chamel...@hdmi-crc-fast.html

  
 Possible fixes 

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +2 similar 
issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19520/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (45 -> 40)
--

  Additional (1): fi-byt-j1900 
  Missing(6): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 
fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9688 -> Patchwork_19520

  CI-20190529: 20190529
  CI_DRM_9688: 43295c2b7bc37446a480bb5d42b03675baed171a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5974: a85398dcae50930c0e27548cf8c9575ad0bf69d1 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19520: 7874b30f7d44c3d16ee5de4bc3519e0d93355cc3 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7874b30f7d44 drm/i915: allocate cmd ring in lmem
761ab0754313 drm/i915: move engine scratch to LMEM
5f5610a977fb drm/i915: allocate context from LMEM
8173f2b6030d drm/i915/dg1: Reserve first 1MB of local memory
cd1a9b80c3a0 drm/i915: introduce mem->reserved
fe2045f56b21 drm/i915: reserve stolen for LMEM region
93136429ec96 drm/i915: setup the LMEM region
5a1abb4304a2 drm/i915: make local-memory probing a GT operation

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19520/index.html
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/4] drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/4] drm/i915/hdcp: Disable the QSES check for 
HDCP 1.4 over MST
URL   : https://patchwork.freedesktop.org/series/86325/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9686 -> Patchwork_19513


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/index.html

Known issues


  Here are the changes found in Patchwork_19513 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_mmap_gtt@basic:
- fi-tgl-y:   [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar 
issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9686/fi-tgl-y/igt@gem_mmap_...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/fi-tgl-y/igt@gem_mmap_...@basic.html

  * igt@i915_selftest@live@hangcheck:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([i915#2895])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9686/fi-bxt-dsi/igt@i915_selftest@l...@hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/fi-bxt-dsi/igt@i915_selftest@l...@hangcheck.html

  * igt@runner@aborted:
- fi-bxt-dsi: NOTRUN -> [FAIL][5] ([i915#2426])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/fi-bxt-dsi/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_create@basic:
- fi-tgl-y:   [DMESG-WARN][6] ([i915#402]) -> [PASS][7] +1 similar 
issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9686/fi-tgl-y/igt@gem_exec_cre...@basic.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/fi-tgl-y/igt@gem_exec_cre...@basic.html

  
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2895]: https://gitlab.freedesktop.org/drm/intel/issues/2895
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (44 -> 39)
--

  Missing(5): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-jsl-2 


Build changes
-

  * Linux: CI_DRM_9686 -> Patchwork_19513

  CI-20190529: 20190529
  CI_DRM_9686: 8de0436dc0e777bbd5490d56134a838da4c19121 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5973: 7ae3d0d68e6bf4c5e404c87b570773d1b3173d47 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19513: cf90167ec8d878cf7739b728e49fd65c5203ac32 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

cf90167ec8d8 drm/i915/hdcp: disable the QSES check for HDCP2.2 over MST
0f5367aacba6 drm/i915/hdcp: read RxInfo once when reading Send_Pairing_Info
c03a6673e642 drm/i915/hdcp: update cp_irq_count_cached in 
intel_dp_hdcp2_read_msg()
69e116124dea drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/index.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v13 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs

[Gwan-gyeong Mun]

In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.

v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
permissions '0444'
v5: Addressed JJani Nikula's review comments
 - Remove checking of Gen12 for i915_psr_status.
 - Add check of HAS_PSR()
 - Remove meaningless check routine.

Signed-off-by: Gwan-gyeong Mun 
Cc: José Roberto de Souza 
Cc: Jani Nikula 
Cc: Anshuman Gupta 
Reviewed-by: Anshuman Gupta 
---
 .../gpu/drm/i915/display/intel_display_debugfs.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 9868253df61f..c3ffa50d92b1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2223,6 +2223,16 @@ static int i915_hdcp_sink_capability_show(struct 
seq_file *m, void *data)
 }
 DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
 
+static int i915_psr_status_show(struct seq_file *m, void *data)
+{
+   struct drm_connector *connector = m->private;
+   struct intel_dp *intel_dp =
+   intel_attached_dp(to_intel_connector(connector));
+
+   return intel_psr_status(m, intel_dp);
+}
+DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
+
 #define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
seq_puts(m, "LPSP: incapable\n"))
 
@@ -2398,6 +2408,12 @@ int intel_connector_debugfs_add(struct drm_connector 
*connector)
connector, _psr_sink_status_fops);
}
 
+   if (HAS_PSR(dev_priv) &&
+   connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+   debugfs_create_file("i915_psr_status", 0444, root,
+   connector, _psr_status_fops);
+   }
+
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
-- 
2.30.0

___
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[Intel-gfx] [PATCH v13 1/2] drm/i915/display: Support PSR Multiple Instances

[Gwan-gyeong Mun]

It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt handling routine for supporting
multiple transcoders. But it does not change the scenario and timing of
enabling and disabling PSR. And it not support multiple pipes with
a single transcoder PSR case yet.

v2: Fix indentation and add comments
v3: Remove Blank line
v4: Rebased
v5: Rebased and Addressed Anshuman's review comment.
- Move calling of intel_psr_init() to intel_dp_init_connector()
v6: Address Anshuman's review comments
   - Remove wrong comments and add comments for a limit of supporting of
 a single pipe PSR
v7: Update intel_psr_compute_config() for supporting multiple transcoder
PSR on BDW+
v8: Address Anshuman's review comments
   - Replace DRM_DEBUG_KMS with drm_dbg_kms() / DRM_WARN with drm_warn()
v9: Fix commit message
v10: Rebased
v11: Address Jose's review comment.
  - Reorder calling order of intel_psr2_program_trans_man_trk_ctl().
  - In order to reduce changes keep the old name for drm_i915_private.
  - Change restrictions of multiple instances of PSR.
v12: Address Jose's review comment.
  - Change the calling of intel_psr2_program_trans_man_trk_ctl() into
commit_pipe_config().
  - Change a checking order of CAN_PSR() and connector_status to original
on i915_psr_sink_status_show().
  - Drop unneeded intel_dp_update_pipe() function.
  - In order to wait a specific encoder which belong to crtc_state on
intel_psr_wait_for_idle(), add checking of encoder.
  - Add an whitespace to comments.
v13: Rebased and Address Jose's review comment.
  - Add and use for_each_intel_psr_enabled_encoder() macro.
  - In order to use correct frontbuffer_bit for each pipe,
fix intel_psr_invalidate() and intel_psr_flush().
  - Remove redundant or unneeded codes.
  - Update comments.

Signed-off-by: Gwan-gyeong Mun 
Cc: José Roberto de Souza 
Cc: Juha-Pekka Heikkila 
Cc: Anshuman Gupta 
Reviewed-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/display/intel_display.c  |   2 -
 drivers/gpu/drm/i915/display/intel_display.h  |   8 +
 .../drm/i915/display/intel_display_debugfs.c  | 105 +++-
 .../drm/i915/display/intel_display_types.h|  46 ++
 drivers/gpu/drm/i915/display/intel_dp.c   |  10 +-
 drivers/gpu/drm/i915/display/intel_psr.c  | 576 ++
 drivers/gpu/drm/i915/display/intel_psr.h  |  11 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |   6 +-
 drivers/gpu/drm/i915/i915_drv.h   |  38 --
 drivers/gpu/drm/i915/i915_irq.c   |  48 +-
 10 files changed, 485 insertions(+), 365 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 667d941878a3..24df9dfb57fb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14135,8 +14135,6 @@ static void intel_setup_outputs(struct drm_i915_private 
*dev_priv)
intel_dvo_init(dev_priv);
}
 
-   intel_psr_init(dev_priv);
-
for_each_intel_encoder(_priv->drm, encoder) {
encoder->base.possible_crtcs =
intel_encoder_possible_crtcs(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h 
b/drivers/gpu/drm/i915/display/intel_display.h
index 64ffa34544a7..fc41d0d9e5a5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -417,6 +417,14 @@ enum phy_fia {
for_each_if((encoder_mask) &\
drm_encoder_mask(_encoder->base))
 
+#define for_each_intel_encoder_is_psr_enabled(dev, intel_encoder, 
encoder_mask) \
+   list_for_each_entry(intel_encoder,  \
+   &(dev)->mode_config.encoder_list,   \
+   base.head)  \
+   for_each_if(((encoder_mask) &   \
+drm_encoder_mask(_encoder->base)) && \
+   intel_encoder_is_psr_enabled(intel_encoder))
+
 #define for_each_intel_dp(dev, intel_encoder)  \
for_each_intel_encoder(dev, intel_encoder)  \
for_each_if(intel_encoder_is_dp(intel_encoder))
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index d62b18d5ecd8..9868253df61f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -249,12 +249,11 @@ static int i915_psr_sink_status_show(struct seq_file *m, 
void *data)
"sink internal error",
};
struct drm_connector *connector = 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v5,1/8] drm/i915: make local-memory probing a GT operation

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/8] drm/i915: make local-memory probing a GT 
operation
URL   : https://patchwork.freedesktop.org/series/86355/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1327:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 
279040
+drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 
16777216
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - 
different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' 
- different lock contexts for basic 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/8] drm/i915: make local-memory probing a GT operation

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/8] drm/i915: make local-memory probing a GT 
operation
URL   : https://patchwork.freedesktop.org/series/86355/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5a1abb4304a2 drm/i915: make local-memory probing a GT operation
93136429ec96 drm/i915: setup the LMEM region
fe2045f56b21 drm/i915: reserve stolen for LMEM region
cd1a9b80c3a0 drm/i915: introduce mem->reserved
-:91: WARNING:LINE_SPACING: Missing a blank line after declarations
#91: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:155:
+   u64 allocated, cur_avail;
+   I915_RND_STATE(prng);

total: 0 errors, 1 warnings, 0 checks, 135 lines checked
8173f2b6030d drm/i915/dg1: Reserve first 1MB of local memory
5f5610a977fb drm/i915: allocate context from LMEM
761ab0754313 drm/i915: move engine scratch to LMEM
7874b30f7d44 drm/i915: allocate cmd ring in lmem


___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Move struct drm_device.pdev to legacy (rev5)

[Patchwork]

== Series Details ==

Series: drm: Move struct drm_device.pdev to legacy (rev5)
URL   : https://patchwork.freedesktop.org/series/84205/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9688 -> Patchwork_19519


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_19519:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- {fi-cml-drallion}:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/fi-cml-drallion/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  
Known issues


  Here are the changes found in Patchwork_19519 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-y:   [PASS][2] -> [DMESG-WARN][3] ([i915#2411] / 
[i915#402])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html

  * igt@gem_huc_copy@huc-copy:
- fi-byt-j1900:   NOTRUN -> [SKIP][4] ([fdo#109271]) +27 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/fi-byt-j1900/igt@gem_huc_c...@huc-copy.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-byt-j1900:   NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/fi-byt-j1900/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@vgem_basic@setversion:
- fi-tgl-y:   [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +2 similar 
issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@vgem_ba...@setversion.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/fi-tgl-y/igt@vgem_ba...@setversion.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- {fi-cml-drallion}:  [INCOMPLETE][8] ([i915#1614]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-cml-drallion/igt@gem_exec_susp...@basic-s0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/fi-cml-drallion/igt@gem_exec_susp...@basic-s0.html

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [DMESG-WARN][10] ([i915#402]) -> [PASS][11] +2 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1614]: https://gitlab.freedesktop.org/drm/intel/issues/1614
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (45 -> 40)
--

  Additional (1): fi-byt-j1900 
  Missing(6): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 
fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9688 -> Patchwork_19519

  CI-20190529: 20190529
  CI_DRM_9688: 43295c2b7bc37446a480bb5d42b03675baed171a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5974: a85398dcae50930c0e27548cf8c9575ad0bf69d1 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19519: 3b576275084e835e268af70b743b32c57d860b93 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3b576275084e drm: Move struct drm_device.pdev to legacy section
58c5e1039c99 drm/i915: Don't assign to struct drm_device.pdev
6301a0471d6d drm/i915/gvt: Remove references to struct drm_device.pdev
6830ebc5cc2f drm/i915/gt: Remove references to struct drm_device.pdev
0a8140c5a88b drm/i915: Remove references to struct drm_device.pdev

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19519/index.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Prefer local execution_mask for determing viable engines

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Prefer local execution_mask for determing viable engines
URL   : https://patchwork.freedesktop.org/series/86342/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9687_full -> Patchwork_19516_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19516_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_ctx_persistence@many-contexts}:
- shard-tglb: [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-tglb5/igt@gem_ctx_persiste...@many-contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html

  * {igt@sysfs_clients@busy@rcs0}:
- shard-skl:  [PASS][3] -> [FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-skl1/igt@sysfs_clients@b...@rcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/shard-skl9/igt@sysfs_clients@b...@rcs0.html

  
Known issues


  Here are the changes found in Patchwork_19516_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@chamelium:
- shard-iclb: NOTRUN -> [SKIP][5] ([fdo#111827])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/shard-iclb2/igt@feature_discov...@chamelium.html

  * igt@gem_ctx_persistence@clone:
- shard-hsw:  NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/shard-hsw4/igt@gem_ctx_persiste...@clone.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-kbl2/igt@gem_exec_fair@basic-n...@vcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-tglb5/igt@gem_exec_fair@basic-p...@bcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/shard-tglb1/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2849])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_reloc@basic-many-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2389])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/shard-iclb1/igt@gem_exec_reloc@basic-many-act...@vcs1.html

  * igt@gem_exec_schedule@u-fairslice@vecs0:
- shard-skl:  [PASS][14] -> [DMESG-WARN][15] ([i915#1610] / 
[i915#2803])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-skl10/igt@gem_exec_schedule@u-fairsl...@vecs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/shard-skl10/igt@gem_exec_schedule@u-fairsl...@vecs0.html

  * igt@gem_render_copy@yf-tiled-to-vebox-linear:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#768]) +1 similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/shard-iclb2/igt@gem_render_c...@yf-tiled-to-vebox-linear.html

  * igt@gem_softpin@evict-snoop-interruptible:
- shard-iclb: NOTRUN -> [SKIP][17] ([fdo#109312])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/shard-iclb2/igt@gem_soft...@evict-snoop-interruptible.html

  * igt@gen7_exec_parse@basic-allowed:
- shard-iclb: NOTRUN -> [SKIP][18] ([fdo#109289])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/shard-iclb2/igt@gen7_exec_pa...@basic-allowed.html

  * igt@gen9_exec_parse@allowed-single:
- shard-skl:  [PASS][19] -> [DMESG-WARN][20] ([i915#1436] / 
[i915#716])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-skl2/igt@gen9_exec_pa...@allowed-single.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/shard-skl8/igt@gen9_exec_pa...@allowed-single.html

  * igt@i915_selftest@live@hangcheck:
- shard-hsw:  NOTRUN -> [INCOMPLETE][21] ([i915#2782])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/shard-hsw4/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][22] -> [FAIL][23] ([i915#2597])
   [22]: 

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/4] drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/4] drm/i915/hdcp: Disable the QSES check for 
HDCP 1.4 over MST
URL   : https://patchwork.freedesktop.org/series/86325/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9686 -> Patchwork_19513


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19513 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19513, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_19513:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@hangcheck:
- fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9686/fi-bxt-dsi/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/fi-bxt-dsi/igt@i915_selftest@l...@hangcheck.html

  
Known issues


  Here are the changes found in Patchwork_19513 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_mmap_gtt@basic:
- fi-tgl-y:   [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar 
issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9686/fi-tgl-y/igt@gem_mmap_...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/fi-tgl-y/igt@gem_mmap_...@basic.html

  * igt@runner@aborted:
- fi-bxt-dsi: NOTRUN -> [FAIL][5] ([i915#2426])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/fi-bxt-dsi/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_create@basic:
- fi-tgl-y:   [DMESG-WARN][6] ([i915#402]) -> [PASS][7] +1 similar 
issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9686/fi-tgl-y/igt@gem_exec_cre...@basic.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/fi-tgl-y/igt@gem_exec_cre...@basic.html

  
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (44 -> 39)
--

  Missing(5): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-jsl-2 


Build changes
-

  * Linux: CI_DRM_9686 -> Patchwork_19513

  CI-20190529: 20190529
  CI_DRM_9686: 8de0436dc0e777bbd5490d56134a838da4c19121 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5973: 7ae3d0d68e6bf4c5e404c87b570773d1b3173d47 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19513: cf90167ec8d878cf7739b728e49fd65c5203ac32 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

cf90167ec8d8 drm/i915/hdcp: disable the QSES check for HDCP2.2 over MST
0f5367aacba6 drm/i915/hdcp: read RxInfo once when reading Send_Pairing_Info
c03a6673e642 drm/i915/hdcp: update cp_irq_count_cached in 
intel_dp_hdcp2_read_msg()
69e116124dea drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19513/index.html
___
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[Intel-gfx] [PATCH v2 4/4] drm/i915: Rename is_16gb_dimm to wm_lv_0_adjust_needed

[José Roberto de Souza]

As it now it is always required for GEN12+ the is_16gb_dimm name
do not make sense for GEN12+.

v2:
- Updated comment on top of "dram_info->wm_lv_0_adjust_needed =
!IS_GEN9_LP(i915);"

Reviewed-by: Lucas De Marchi 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.h   |  2 +-
 drivers/gpu/drm/i915/intel_dram.c | 15 +++
 drivers/gpu/drm/i915/intel_pm.c   |  2 +-
 3 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 80227d47b5cb..f684147290cb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1128,7 +1128,7 @@ struct drm_i915_private {
} wm;
 
struct dram_info {
-   bool is_16gb_dimm;
+   bool wm_lv_0_adjust_needed;
u8 num_channels;
bool symmetric_memory;
enum intel_dram_type {
diff --git a/drivers/gpu/drm/i915/intel_dram.c 
b/drivers/gpu/drm/i915/intel_dram.c
index 6ce56eedaf12..6a13cf39da99 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -207,7 +207,7 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
return -EINVAL;
}
 
-   dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
+   dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
 
dram_info->symmetric_memory = intel_is_dram_symmetric(, );
 
@@ -479,7 +479,7 @@ static int gen11_get_dram_info(struct drm_i915_private 
*i915)
 static int gen12_get_dram_info(struct drm_i915_private *i915)
 {
/* Always needed for GEN12+ */
-   i915->dram_info.is_16gb_dimm = true;
+   i915->dram_info.wm_lv_0_adjust_needed = true;
 
return icl_pcode_read_mem_global_info(i915);
 }
@@ -490,11 +490,10 @@ int intel_dram_detect(struct drm_i915_private *i915)
int ret;
 
/*
-* Assume 16Gb DIMMs are present until proven otherwise.
-* This is only used for the level 0 watermark latency
-* w/a which does not apply to bxt/glk.
+* Assume level 0 watermark latency adjustment is needed until proven
+* otherwise, this w/a is not needed by bxt/glk.
 */
-   dram_info->is_16gb_dimm = !IS_GEN9_LP(i915);
+   dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);
 
if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
return 0;
@@ -515,8 +514,8 @@ int intel_dram_detect(struct drm_i915_private *i915)
 
drm_dbg_kms(>drm, "DRAM channels: %u\n", dram_info->num_channels);
 
-   drm_dbg_kms(>drm, "DRAM 16Gb DIMMs: %s\n",
-   yesno(dram_info->is_16gb_dimm));
+   drm_dbg_kms(>drm, "Watermark level 0 adjustment needed: %s\n",
+   yesno(dram_info->wm_lv_0_adjust_needed));
 
return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6e9678bd0597..c58e5077590d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2930,7 +2930,7 @@ static void intel_read_wm_latency(struct drm_i915_private 
*dev_priv,
 * any underrun. If not able to get Dimm info assume 16GB dimm
 * to avoid any underrun.
 */
-   if (dev_priv->dram_info.is_16gb_dimm)
+   if (dev_priv->dram_info.wm_lv_0_adjust_needed)
wm[0] += 1;
 
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-- 
2.30.0

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[Intel-gfx] [PATCH v2 2/4] drm/i915/gen11+: Only load DRAM information from pcode

[José Roberto de Souza]

Up to now we were reading some DRAM information from MCHBAR register
and from pcode what is already not good but some GEN12(TGL-H and ADL-S)
platforms have MCHBAR DRAM information in different offsets.

This was notified to HW team that decided that the best alternative is
always apply the 16gb_dimm watermark adjustment for GEN12+ platforms
and read the remaning DRAM information needed to other display
programming from pcode.

So here moving the DRAM pcode function to intel_dram.c, removing
the duplicated fields from intel_qgv_info, setting and using
information from dram_info.

v2:
- bring back num_points to intel_qgv_info as num_qgv_point can be
overwritten in icl_get_qgv_points()
- add gen12_get_dram_info() and simplify gen11_get_dram_info()

Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/display/intel_bw.c | 80 +++-
 drivers/gpu/drm/i915/i915_drv.c |  5 +-
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/intel_dram.c   | 82 -
 4 files changed, 93 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index bd060404d249..4b5a30ac84bc 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -20,76 +20,9 @@ struct intel_qgv_point {
 struct intel_qgv_info {
struct intel_qgv_point points[I915_NUM_QGV_POINTS];
u8 num_points;
-   u8 num_channels;
u8 t_bl;
-   enum intel_dram_type dram_type;
 };
 
-static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
- struct intel_qgv_info *qi)
-{
-   u32 val = 0;
-   int ret;
-
-   ret = sandybridge_pcode_read(dev_priv,
-ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
-ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
-, NULL);
-   if (ret)
-   return ret;
-
-   if (IS_GEN(dev_priv, 12)) {
-   switch (val & 0xf) {
-   case 0:
-   qi->dram_type = INTEL_DRAM_DDR4;
-   break;
-   case 3:
-   qi->dram_type = INTEL_DRAM_LPDDR4;
-   break;
-   case 4:
-   qi->dram_type = INTEL_DRAM_DDR3;
-   break;
-   case 5:
-   qi->dram_type = INTEL_DRAM_LPDDR3;
-   break;
-   default:
-   MISSING_CASE(val & 0xf);
-   break;
-   }
-   } else if (IS_GEN(dev_priv, 11)) {
-   switch (val & 0xf) {
-   case 0:
-   qi->dram_type = INTEL_DRAM_DDR4;
-   break;
-   case 1:
-   qi->dram_type = INTEL_DRAM_DDR3;
-   break;
-   case 2:
-   qi->dram_type = INTEL_DRAM_LPDDR3;
-   break;
-   case 3:
-   qi->dram_type = INTEL_DRAM_LPDDR4;
-   break;
-   default:
-   MISSING_CASE(val & 0xf);
-   break;
-   }
-   } else {
-   MISSING_CASE(INTEL_GEN(dev_priv));
-   qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */
-   }
-
-   qi->num_channels = (val & 0xf0) >> 4;
-   qi->num_points = (val & 0xf00) >> 8;
-
-   if (IS_GEN(dev_priv, 12))
-   qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16;
-   else if (IS_GEN(dev_priv, 11))
-   qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
-
-   return 0;
-}
-
 static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
 struct intel_qgv_point *sp,
 int point)
@@ -139,11 +72,15 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private 
*dev_priv,
 static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
  struct intel_qgv_info *qi)
 {
+   const struct dram_info *dram_info = _priv->dram_info;
int i, ret;
 
-   ret = icl_pcode_read_mem_global_info(dev_priv, qi);
-   if (ret)
-   return ret;
+   qi->num_points = dram_info->num_qgv_points;
+
+   if (IS_GEN(dev_priv, 12))
+   qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 16;
+   else if (IS_GEN(dev_priv, 11))
+   qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
 
if (drm_WARN_ON(_priv->drm,
qi->num_points > ARRAY_SIZE(qi->points)))
@@ -209,7 +146,7 @@ static int icl_get_bw_info(struct drm_i915_private 
*dev_priv, const struct intel
 {
struct intel_qgv_info qi = {};
bool is_y_tile = true; /* 

[Intel-gfx] [PATCH v2 3/4] drm/i915: Fail driver probe when unable to load DRAM information

[José Roberto de Souza]

DRAM information is required to properly program display.
Before "drm/i915/gen11+: Only load DRAM information from pcode" we
were failing driver load if unable to fetch DRAM information from
pcode form GEN11+ but we should also extend it to GEN9 plaforms.

Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.c   |  6 +-
 drivers/gpu/drm/i915/intel_dram.c | 13 +
 drivers/gpu/drm/i915/intel_dram.h |  2 +-
 3 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aec0e870dc25..7ff58ea30c7c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -622,12 +622,16 @@ static int i915_driver_hw_probe(struct drm_i915_private 
*dev_priv)
 * Fill the dram structure to get the system dram info. This will be
 * used for memory latency calculation.
 */
-   intel_dram_detect(dev_priv);
+   ret = intel_dram_detect(dev_priv);
+   if (ret)
+   goto err_dram;
 
intel_bw_init_hw(dev_priv);
 
return 0;
 
+err_dram:
+   intel_gvt_driver_remove(dev_priv);
 err_msi:
if (pdev->msi_enabled)
pci_disable_msi(pdev);
diff --git a/drivers/gpu/drm/i915/intel_dram.c 
b/drivers/gpu/drm/i915/intel_dram.c
index 4d5ab206eacb..6ce56eedaf12 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -484,7 +484,7 @@ static int gen12_get_dram_info(struct drm_i915_private 
*i915)
return icl_pcode_read_mem_global_info(i915);
 }
 
-void intel_dram_detect(struct drm_i915_private *i915)
+int intel_dram_detect(struct drm_i915_private *i915)
 {
struct dram_info *dram_info = >dram_info;
int ret;
@@ -497,7 +497,7 @@ void intel_dram_detect(struct drm_i915_private *i915)
dram_info->is_16gb_dimm = !IS_GEN9_LP(i915);
 
if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
-   return;
+   return 0;
 
if (INTEL_GEN(i915) >= 12)
ret = gen12_get_dram_info(i915);
@@ -507,13 +507,18 @@ void intel_dram_detect(struct drm_i915_private *i915)
ret = bxt_get_dram_info(i915);
else
ret = skl_get_dram_info(i915);
-   if (ret)
-   return;
+
+   if (ret) {
+   drm_warn(>drm, "Unable to load dram information\n");
+   return ret;
+   }
 
drm_dbg_kms(>drm, "DRAM channels: %u\n", dram_info->num_channels);
 
drm_dbg_kms(>drm, "DRAM 16Gb DIMMs: %s\n",
yesno(dram_info->is_16gb_dimm));
+
+   return 0;
 }
 
 static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
diff --git a/drivers/gpu/drm/i915/intel_dram.h 
b/drivers/gpu/drm/i915/intel_dram.h
index 4ba13c13162c..2a0f283b1a1d 100644
--- a/drivers/gpu/drm/i915/intel_dram.h
+++ b/drivers/gpu/drm/i915/intel_dram.h
@@ -9,6 +9,6 @@
 struct drm_i915_private;
 
 void intel_dram_edram_detect(struct drm_i915_private *i915);
-void intel_dram_detect(struct drm_i915_private *i915);
+int intel_dram_detect(struct drm_i915_private *i915);
 
 #endif /* __INTEL_DRAM_H__ */
-- 
2.30.0

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[Intel-gfx] [PATCH v2 1/4] drm/i915: Nuke not needed members of dram_info

[José Roberto de Souza]

Valid, ranks and bandwidth_kbps are set into dram_info but are not
used anywhere else so nuking it.

Reviewed-by: Lucas De Marchi 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.c   |  4 +--
 drivers/gpu/drm/i915/i915_drv.h   |  3 --
 drivers/gpu/drm/i915/intel_dram.c | 47 +++
 3 files changed, 12 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0037b81d991e..36e073c4bc06 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -616,8 +616,8 @@ static int i915_driver_hw_probe(struct drm_i915_private 
*dev_priv)
 
intel_opregion_setup(dev_priv);
/*
-* Fill the dram structure to get the system raw bandwidth and
-* dram info. This will be used for memory latency calculation.
+* Fill the dram structure to get the system dram info. This will be
+* used for memory latency calculation.
 */
intel_dram_detect(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3edc9c4f2d21..4e8e151c7ade 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1128,11 +1128,8 @@ struct drm_i915_private {
} wm;
 
struct dram_info {
-   bool valid;
bool is_16gb_dimm;
u8 num_channels;
-   u8 ranks;
-   u32 bandwidth_kbps;
bool symmetric_memory;
enum intel_dram_type {
INTEL_DRAM_UNKNOWN,
diff --git a/drivers/gpu/drm/i915/intel_dram.c 
b/drivers/gpu/drm/i915/intel_dram.c
index 4754296a250e..694fbd8c9cd4 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -201,17 +201,7 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
return -EINVAL;
}
 
-   /*
-* If any of the channel is single rank channel, worst case output
-* will be same as if single rank memory, so consider single rank
-* memory.
-*/
-   if (ch0.ranks == 1 || ch1.ranks == 1)
-   dram_info->ranks = 1;
-   else
-   dram_info->ranks = max(ch0.ranks, ch1.ranks);
-
-   if (dram_info->ranks == 0) {
+   if (ch0.ranks == 0 && ch1.ranks == 0) {
drm_info(>drm, "couldn't get memory rank information\n");
return -EINVAL;
}
@@ -269,16 +259,12 @@ skl_get_dram_info(struct drm_i915_private *i915)
mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
 
-   dram_info->bandwidth_kbps = dram_info->num_channels *
-   mem_freq_khz * 8;
-
-   if (dram_info->bandwidth_kbps == 0) {
+   if (dram_info->num_channels * mem_freq_khz == 0) {
drm_info(>drm,
 "Couldn't get system memory bandwidth\n");
return -EINVAL;
}
 
-   dram_info->valid = true;
return 0;
 }
 
@@ -365,7 +351,7 @@ static int bxt_get_dram_info(struct drm_i915_private *i915)
struct dram_info *dram_info = >dram_info;
u32 dram_channels;
u32 mem_freq_khz, val;
-   u8 num_active_channels;
+   u8 num_active_channels, valid_ranks = 0;
int i;
 
val = intel_uncore_read(>uncore, BXT_P_CR_MC_BIOS_REQ_0_0_0);
@@ -375,10 +361,7 @@ static int bxt_get_dram_info(struct drm_i915_private *i915)
dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
num_active_channels = hweight32(dram_channels);
 
-   /* Each active bit represents 4-byte channel */
-   dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
-
-   if (dram_info->bandwidth_kbps == 0) {
+   if (mem_freq_khz * num_active_channels == 0) {
drm_info(>drm,
 "Couldn't get system memory bandwidth\n");
return -EINVAL;
@@ -410,27 +393,18 @@ static int bxt_get_dram_info(struct drm_i915_private 
*i915)
dimm.size, dimm.width, dimm.ranks,
intel_dram_type_str(type));
 
-   /*
-* If any of the channel is single rank channel,
-* worst case output will be same as if single rank
-* memory, so consider single rank memory.
-*/
-   if (dram_info->ranks == 0)
-   dram_info->ranks = dimm.ranks;
-   else if (dimm.ranks == 1)
-   dram_info->ranks = 1;
+   if (valid_ranks == 0)
+   valid_ranks = dimm.ranks;
 
if (type != INTEL_DRAM_UNKNOWN)
dram_info->type = type;
}
 
-   if (dram_info->type == INTEL_DRAM_UNKNOWN || dram_info->ranks == 0) {
+   if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) {
  

Re: [Intel-gfx] [PATCH 2/9] drm/i915/adl_s: MCHBAR memory info registers are moved

[Souza, Jose]

On Wed, 2021-01-27 at 07:07 -0800, Lucas De Marchi wrote:
> On Tue, Jan 26, 2021 at 08:11:52PM -0800, Aditya Swarup wrote:
> > From: Caz Yokoyama 
> > 
> > The crwebview indicates on ADL-S that some of our MCHBAR
> > registers have moved from their traditional 0x50XX offsets to
> > new locations. The meaning and bit layout of the registers
> > remain same.
> > 
> > v2: Simplify logic to a single if else chain and fix indents.(Lucas)
> > 
> > Cc: Lucas De Marchi 
> > Cc: Jani Nikula 
> > Cc: Ville Syrjälä 
> > Cc: Imre Deak 
> > Cc: Matt Roper 
> > Signed-off-by: Caz Yokoyama 
> > Signed-off-by: Aditya Swarup 
> > ---
> > drivers/gpu/drm/i915/i915_reg.h   |  5 +
> > drivers/gpu/drm/i915/intel_dram.c | 24 ++--
> > 2 files changed, 23 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index aa872446337b..3031897239a0 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10916,6 +10916,8 @@ enum skl_power_gate {
> > #define  SKL_DRAM_DDR_TYPE_LPDDR3   (2 << 0)
> > #define  SKL_DRAM_DDR_TYPE_LPDDR4   (3 << 0)
> > 
> > +#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 
> > 0x6048)
> > +
> > #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN
> > _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
> > #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN
> > _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
> > #define  SKL_DRAM_S_SHIFT   16
> > @@ -10943,6 +10945,9 @@ enum skl_power_gate {
> > #define  CNL_DRAM_RANK_3(0x2 << 9)
> > #define  CNL_DRAM_RANK_4(0x3 << 9)
> > 
> > +#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR 
> > _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054)
> > +#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR 
> > _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058)
> > +
> > /*
> >  * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this 
> > register,
> >  * since on HSW we can't write to it using intel_uncore_write.
> > diff --git a/drivers/gpu/drm/i915/intel_dram.c 
> > b/drivers/gpu/drm/i915/intel_dram.c
> > index 4754296a250e..84f84e118531 100644
> > --- a/drivers/gpu/drm/i915/intel_dram.c
> > +++ b/drivers/gpu/drm/i915/intel_dram.c
> > @@ -181,17 +181,24 @@ skl_dram_get_channels_info(struct drm_i915_private 
> > *i915)
> > {
> > struct dram_info *dram_info = >dram_info;
> > struct dram_channel_info ch0 = {}, ch1 = {};
> > +   i915_reg_t ch0_reg, ch1_reg;
> > u32 val;
> > int ret;
> > 
> > -   val = intel_uncore_read(>uncore,
> > -   SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
> > +   if (IS_ALDERLAKE_S(i915)) {
> > +   ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
> > +   ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;
> > +   } else {
> > +   ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
> > +   ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;
> 
> I commented on the wrong version of the patch, but the bug is still
> here. And this patch conflict with Jose's patch.

Yep, for GEN12+ we should use PCODE to read DRAM information.
Lucas left some comments, working in the fixes and soon another version will be 
send.
It already takes care of all GEN12 platforms.

https://patchwork.freedesktop.org/series/86092/

> 
> Lucas De Marchi
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Patchwork]

== Series Details ==

Series: drm/i915/gen9bc: Handle TGP PCH during suspend/resume
URL   : https://patchwork.freedesktop.org/series/86346/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9688 -> Patchwork_19518


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_19518:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_flip@basic-flip-vs-dpms@c-edp1:
- {fi-cml-drallion}:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-cml-drallion/igt@kms_flip@basic-flip-vs-d...@c-edp1.html

  
Known issues


  Here are the changes found in Patchwork_19518 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@core_hotunplug@unbind-rebind:
- fi-kbl-7500u:   [PASS][2] -> [DMESG-WARN][3] ([i915#2605])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [PASS][4] -> [DMESG-WARN][5] ([i915#402])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-y:   [PASS][6] -> [DMESG-WARN][7] ([i915#2411] / 
[i915#402])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html

  * igt@gem_huc_copy@huc-copy:
- fi-byt-j1900:   NOTRUN -> [SKIP][8] ([fdo#109271]) +27 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-byt-j1900/igt@gem_huc_c...@huc-copy.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-byt-j1900:   NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-byt-j1900/igt@kms_chamel...@hdmi-crc-fast.html

  
 Possible fixes 

  * igt@gem_basic@bad-close:
- fi-tgl-y:   [DMESG-WARN][10] ([i915#402]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@gem_ba...@bad-close.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-tgl-y/igt@gem_ba...@bad-close.html

  * igt@gem_exec_suspend@basic-s0:
- {fi-cml-drallion}:  [INCOMPLETE][12] ([i915#1614]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-cml-drallion/igt@gem_exec_susp...@basic-s0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-cml-drallion/igt@gem_exec_susp...@basic-s0.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1614]: https://gitlab.freedesktop.org/drm/intel/issues/1614
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (45 -> 40)
--

  Additional (1): fi-byt-j1900 
  Missing(6): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 
fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9688 -> Patchwork_19518

  CI-20190529: 20190529
  CI_DRM_9688: 43295c2b7bc37446a480bb5d42b03675baed171a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5974: a85398dcae50930c0e27548cf8c9575ad0bf69d1 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19518: f7ab96d28d4a9215cc9c8ede76fc27dac7f79fef @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f7ab96d28d4a drm/i915/gen9bc: Handle TGP PCH during suspend/resume

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/index.html
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Re: [Intel-gfx] [PATCH 2/4] drm/i915/gen11+: Only load DRAM information from pcode

[Souza, Jose]

On Wed, 2021-01-27 at 06:49 -0800, Lucas De Marchi wrote:
> On Wed, Jan 20, 2021 at 07:16:09AM -0800, Jose Souza wrote:
> > Up to now we were reading some DRAM information from MCHBAR register
> > and from pcode what is already not good but some GEN12(TGL-H and ADL-S)
> > platforms have MCHBAR DRAM information in different offsets.
> > 
> > This was notified to HW team that decided that the best alternative is
> > always apply the 16gb_dimm watermark adjustment for GEN12+ platforms
> > and read the remaning DRAM information needed to other display
> > programming from pcode.
> > 
> > So here moving the DRAM pcode function to intel_dram.c, removing
> > the duplicated fields from intel_qgv_info, setting and using
> > information from dram_info.
> > 
> > Signed-off-by: José Roberto de Souza 
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.c | 98 +
> > drivers/gpu/drm/i915/i915_drv.c |  5 +-
> > drivers/gpu/drm/i915/i915_drv.h |  1 +
> > drivers/gpu/drm/i915/intel_dram.c   | 77 ++-
> > 4 files changed, 97 insertions(+), 84 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index bd060404d249..1368bd96ed73 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -19,77 +19,9 @@ struct intel_qgv_point {
> > 
> > struct intel_qgv_info {
> > struct intel_qgv_point points[I915_NUM_QGV_POINTS];
> > -   u8 num_points;
> > -   u8 num_channels;
> > u8 t_bl;
> > -   enum intel_dram_type dram_type;
> 
> humn... given this struct already has padding, we could very well leave
> the num_points field. See below.
> 
> > static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
> >  struct intel_qgv_point *sp,
> >  int point)
> > @@ -139,17 +71,19 @@ int icl_pcode_restrict_qgv_points(struct 
> > drm_i915_private *dev_priv,
> > static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> >   struct intel_qgv_info *qi)
> > {
> > +   struct dram_info *dram_info = _priv->dram_info;
> > int i, ret;
> > 
> > -   ret = icl_pcode_read_mem_global_info(dev_priv, qi);
> > -   if (ret)
> > -   return ret;
> > +   if (IS_GEN(dev_priv, 12))
> > +   qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 16;
> > +   else if (IS_GEN(dev_priv, 11))
> > +   qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
> > 
> > if (drm_WARN_ON(_priv->drm,
> > -   qi->num_points > ARRAY_SIZE(qi->points)))
> > -   qi->num_points = ARRAY_SIZE(qi->points);
> > +   dram_info->qgv_points > ARRAY_SIZE(qi->points)))
> > +   dram_info->qgv_points = ARRAY_SIZE(qi->points);
> 
> previously we were overriding a member of qi. Now we are overriding a
> member of dram_info, which seems to cross the boundaries of what this
> code should be doing.
> 
> So maybe:
> 
> qi->num_points = dev_priv->dram_info->qgv_points;

Okay, reasonable enough to keep this duplicated.

> 
> and leave the check alone and also the renames in this file?
> Also, dram_info->qgv_points should be named dram_info->num_qgv_points
> for consistency with other structs.
> 
> > 
> > -   for (i = 0; i < qi->num_points; i++) {
> > +   for (i = 0; i < dram_info->qgv_points; i++) {
> > struct intel_qgv_point *sp = >points[i];
> > 
> > ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
> > @@ -171,12 +105,13 @@ static int icl_calc_bw(int dclk, int num, int den)
> > return DIV_ROUND_CLOSEST(num * dclk * 100, den * 6);
> > }
> > 
> > -static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
> > +static int icl_sagv_max_dclk(struct drm_i915_private *dev_priv,
> > +const struct intel_qgv_info *qi)
> > {
> > u16 dclk = 0;
> > int i;
> > 
> > -   for (i = 0; i < qi->num_points; i++)
> > +   for (i = 0; i < dev_priv->dram_info.qgv_points; i++)
> > dclk = max(dclk, qi->points[i].dclk);
> > 
> > return dclk;
> > @@ -207,6 +142,7 @@ static const struct intel_sa_info rkl_sa_info = {
> > 
> > static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct 
> > intel_sa_info *sa)
> > {
> > +   struct dram_info *dram_info = _priv->dram_info;
> > struct intel_qgv_info qi = {};
> > bool is_y_tile = true; /* assume y tile may be used */
> > int num_channels;
> > @@ -222,10 +158,10 @@ static int icl_get_bw_info(struct drm_i915_private 
> > *dev_priv, const struct intel
> > "Failed to get memory subsystem information, 
> > ignoring bandwidth limits");
> > return ret;
> > }
> > -   num_channels = qi.num_channels;
> > +   num_channels = dram_info->num_channels;
> > 
> > deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
> > -   dclk_max = icl_sagv_max_dclk();

Re: [Intel-gfx] [PATCH 5/8] drm/i915/selftests: Replace unbound set-domain waits with explicit timeouts

[Matthew Auld]

On Mon, 25 Jan 2021 at 14:18, Chris Wilson  wrote:
>
> Let's prefer to use explicit request tracking and bounded timeouts in
> our selftests.
>
> Signed-off-by: Chris Wilson 
Reviewed-by: Matthew Auld 
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/bios: tidy up child device debug logging

[Patchwork]

== Series Details ==

Series: drm/i915/bios: tidy up child device debug logging
URL   : https://patchwork.freedesktop.org/series/86341/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9687_full -> Patchwork_19515_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19515_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@chamelium:
- shard-iclb: NOTRUN -> [SKIP][1] ([fdo#111827])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-iclb3/igt@feature_discov...@chamelium.html

  * igt@gem_ctx_persistence@clone:
- shard-hsw:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-hsw8/igt@gem_ctx_persiste...@clone.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][3] ([i915#2842])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace:
- shard-hsw:  NOTRUN -> [SKIP][4] ([fdo#109271]) +43 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-hsw8/igt@gem_exec_f...@basic-pace.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842]) +1 similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-tglb5/igt@gem_exec_fair@basic-p...@bcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-tglb2/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_reloc@basic-many-active@vcs0:
- shard-kbl:  NOTRUN -> [FAIL][9] ([i915#2389]) +4 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-kbl3/igt@gem_exec_reloc@basic-many-act...@vcs0.html

  * igt@gem_exec_reloc@basic-many-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][10] ([i915#2389])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-iclb2/igt@gem_exec_reloc@basic-many-act...@vcs1.html

  * igt@gem_exec_whisper@basic-queues-forked-all:
- shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([i915#2295])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-iclb3/igt@gem_exec_whis...@basic-queues-forked-all.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-iclb4/igt@gem_exec_whis...@basic-queues-forked-all.html

  * igt@gem_render_copy@yf-tiled-to-vebox-linear:
- shard-iclb: NOTRUN -> [SKIP][13] ([i915#768]) +1 similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-iclb3/igt@gem_render_c...@yf-tiled-to-vebox-linear.html

  * igt@gem_softpin@evict-snoop-interruptible:
- shard-iclb: NOTRUN -> [SKIP][14] ([fdo#109312])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-iclb3/igt@gem_soft...@evict-snoop-interruptible.html

  * igt@gen7_exec_parse@basic-allowed:
- shard-iclb: NOTRUN -> [SKIP][15] ([fdo#109289])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-iclb3/igt@gen7_exec_pa...@basic-allowed.html

  * igt@i915_hangman@engine-error@vecs0:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271]) +32 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-kbl3/igt@i915_hangman@engine-er...@vecs0.html

  * igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][17] -> [FAIL][18] ([i915#2597])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-tglb8/igt@kms_async_fl...@test-time-stamp.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-tglb5/igt@kms_async_fl...@test-time-stamp.html

  * igt@kms_ccs@pipe-c-crc-primary-basic:
- shard-skl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111304])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-skl1/igt@kms_...@pipe-c-crc-primary-basic.html

  * igt@kms_chamelium@dp-mode-timings:
- shard-iclb: NOTRUN -> [SKIP][20] ([fdo#109284] / [fdo#111827]) +2 
similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-iclb3/igt@kms_chamel...@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-cmp-planar-formats:
- shard-glk:  NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +1 
similar issue
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/shard-glk5/igt@kms_chamel...@hdmi-cmp-planar-formats.html

Re: [Intel-gfx] [PATCH 7/8] drm/i915/selftests: Remove redundant set-to-gtt-domain before batch submission

[Matthew Auld]

On Mon, 25 Jan 2021 at 14:18, Chris Wilson  wrote:
>
> In construction the rpcs_query batch we know that it is device coherent
> and ready for execution, the set-to-gtt-domain here is redudant.
>
> Signed-off-by: Chris Wilson 
Reviewed-by: Matthew Auld 
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Re: [Intel-gfx] [PATCH 6/8] drm/i915/selftests: Replace an unbounded set-domain wait with a timeout

[Matthew Auld]

On Mon, 25 Jan 2021 at 14:18, Chris Wilson  wrote:
>
> After the memory-region test completes, it flushes the test by calling
> set-to-cpu-domain. Use the igt_flush_test as it includes a timeout,
> recovery and reports and error for miscreant tests.
>
> Signed-off-by: Chris Wilson 
Reviewed-by: Matthew Auld 
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Re: [Intel-gfx] [PATCH 4/8] drm/i915/selftests: Remove redundant set-to-gtt-domain

[Matthew Auld]

On Mon, 25 Jan 2021 at 14:18, Chris Wilson  wrote:
>
> Since the vma's backing store is flushed upon first creation, remove the
> manual calls to set-to-gtt-domain.
>
> Signed-off-by: Chris Wilson 
Reviewed-by: Matthew Auld 
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Re: [Intel-gfx] [PATCH 3/8] drm/i915/selftests: Replace the unbounded set-domain with an explicit wait

[Matthew Auld]

On Mon, 25 Jan 2021 at 14:18, Chris Wilson  wrote:
>
> After running client_blt, we flush the object by changing its domain.
> This causes us to wait forever instead of an bounded wait suitable for
> the selftest timeout. So do an explicit wait with a suitable timeout --
> which in turn means we have to limit the size of the object/blit to run
> within reason.
>
> Signed-off-by: Chris Wilson 
Reviewed-by: Matthew Auld 
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Re: [Intel-gfx] [PATCH 20/41] drm/i915: Replace priolist rbtree with a skiplist

[Tvrtko Ursulin]

On 27/01/2021 15:44, Chris Wilson wrote:

Quoting Chris Wilson (2021-01-27 15:33:05)

Quoting Tvrtko Ursulin (2021-01-27 15:10:43)


On 25/01/2021 14:01, Chris Wilson wrote:

Replace the priolist rbtree with a skiplist. The crucial difference is
that walking and removing the first element of a skiplist is O(1), but


I wasn't (and am not) familiar with them, but wikipedia page says
removal is O(logN) average case to O(N) worst case.

If I understand correctly O(1) could be ignoring the need to traverse
from top to bottom level and removing the element from all. But since
I915_PRIOLIST_HEIGHT is fixed maybe it is okay to call it O(1).


Correct, since we removing the first element, we do not need to do the
lgN search and can just move the next[I915_PRIOLIST_HEIGHT] forwards.
(Although, I did starting doing the lgN removal for timeslicing as
traversing the empty levels were showing up in worst case lock hold
times.) But the primary means of removing from the skiplist is as we
consume the first request during the dequeue.


I wonder though why this wouldn't mean skip list would be worse for both
lightly loaded and highly-loaded scenarios? Presumably height would need
to be balanced to compensate for that.


I think the answer is yes. skiplists uses probablistic balancing so they
are only from a bird's eye view as good as a rbtree. If you look at the
perf tests, the skiplists are generally faster, but it's close overall.

What sold me was lock_stat and that I could remove a few hacky patches
trying to hide some of the worst case behaviour of rbtree and how we had
frees within the critical submit path.
  

In summary I have no idea for what number of in-flight requests would
they be better.

How about putting this patch aside for now since it doesn't sound it is
critical for deadline scheduling per se?


Oh no, we are not going back to the hacky patches like
https://patchwork.freedesktop.org/patch/407913/?series=84900=1
https://patchwork.freedesktop.org/patch/407903/?series=84900=1


To be extra clear, the biggest drawback in using deadlines as the sort
key is that they are very, very sparse in comparison to priorities.
Where we would typically have only a single priority level for every
request, with deadlines we typically have a new deadline with every
request (and it's not until we get into priority bumping or timeslice
deferring do we start to see the deadlines coalesce). In this situation,
the lgN list traversal of rbtree during execlists_dequeue() was
abyssmal, and so as the skiplists give similar lgN insertion but O(1)
list traversal, the difference is enough to completely negate the
overhead of having more levels to process. It is a dramatic improvement.


Okay makes sense. The change in key drives the requirement so just 
please mention in the commit message and I'll tackle the skip list 
mechanics in the meantime.


Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH 2/8] drm/i915/selftests: Use a coherent map to setup scratch batch buffers

[Matthew Auld]

On Mon, 25 Jan 2021 at 14:18, Chris Wilson  wrote:
>
> Instead of manipulating the object's cache domain, just use the device
> coherent map to write the batch buffer.
>
> Signed-off-by: Chris Wilson 
Reviewed-by: Matthew Auld 
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Re: [Intel-gfx] [PATCH 1/8] drm/i915/selftests: Set cache status for huge_gem_object

[Matthew Auld]

On Mon, 25 Jan 2021 at 14:18, Chris Wilson  wrote:
>
> Set the cache coherency and status using the set-coherency helper.
> Otherwise, we forget to mark the new pages as cache dirty.
>
> Signed-off-by: Chris Wilson 
Reviewed-by: Matthew Auld 
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Re: [Intel-gfx] [PATCH 20/41] drm/i915: Replace priolist rbtree with a skiplist

[Chris Wilson]

Quoting Chris Wilson (2021-01-27 15:33:05)
> Quoting Tvrtko Ursulin (2021-01-27 15:10:43)
> > 
> > On 25/01/2021 14:01, Chris Wilson wrote:
> > > Replace the priolist rbtree with a skiplist. The crucial difference is
> > > that walking and removing the first element of a skiplist is O(1), but
> > 
> > I wasn't (and am not) familiar with them, but wikipedia page says 
> > removal is O(logN) average case to O(N) worst case.
> > 
> > If I understand correctly O(1) could be ignoring the need to traverse 
> > from top to bottom level and removing the element from all. But since 
> > I915_PRIOLIST_HEIGHT is fixed maybe it is okay to call it O(1).
> 
> Correct, since we removing the first element, we do not need to do the
> lgN search and can just move the next[I915_PRIOLIST_HEIGHT] forwards.
> (Although, I did starting doing the lgN removal for timeslicing as
> traversing the empty levels were showing up in worst case lock hold
> times.) But the primary means of removing from the skiplist is as we
> consume the first request during the dequeue.
> 
> > I wonder though why this wouldn't mean skip list would be worse for both 
> > lightly loaded and highly-loaded scenarios? Presumably height would need 
> > to be balanced to compensate for that.
> 
> I think the answer is yes. skiplists uses probablistic balancing so they
> are only from a bird's eye view as good as a rbtree. If you look at the
> perf tests, the skiplists are generally faster, but it's close overall.
> 
> What sold me was lock_stat and that I could remove a few hacky patches
> trying to hide some of the worst case behaviour of rbtree and how we had
> frees within the critical submit path.
>  
> > In summary I have no idea for what number of in-flight requests would 
> > they be better.
> > 
> > How about putting this patch aside for now since it doesn't sound it is 
> > critical for deadline scheduling per se?
> 
> Oh no, we are not going back to the hacky patches like
> https://patchwork.freedesktop.org/patch/407913/?series=84900=1
> https://patchwork.freedesktop.org/patch/407903/?series=84900=1

To be extra clear, the biggest drawback in using deadlines as the sort
key is that they are very, very sparse in comparison to priorities.
Where we would typically have only a single priority level for every
request, with deadlines we typically have a new deadline with every
request (and it's not until we get into priority bumping or timeslice
deferring do we start to see the deadlines coalesce). In this situation,
the lgN list traversal of rbtree during execlists_dequeue() was
abyssmal, and so as the skiplists give similar lgN insertion but O(1)
list traversal, the difference is enough to completely negate the
overhead of having more levels to process. It is a dramatic improvement.
-Chris
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Re: [Intel-gfx] [PATCH 20/41] drm/i915: Replace priolist rbtree with a skiplist

[Chris Wilson]

Quoting Tvrtko Ursulin (2021-01-27 15:10:43)
> 
> On 25/01/2021 14:01, Chris Wilson wrote:
> > Replace the priolist rbtree with a skiplist. The crucial difference is
> > that walking and removing the first element of a skiplist is O(1), but
> 
> I wasn't (and am not) familiar with them, but wikipedia page says 
> removal is O(logN) average case to O(N) worst case.
> 
> If I understand correctly O(1) could be ignoring the need to traverse 
> from top to bottom level and removing the element from all. But since 
> I915_PRIOLIST_HEIGHT is fixed maybe it is okay to call it O(1).

Correct, since we removing the first element, we do not need to do the
lgN search and can just move the next[I915_PRIOLIST_HEIGHT] forwards.
(Although, I did starting doing the lgN removal for timeslicing as
traversing the empty levels were showing up in worst case lock hold
times.) But the primary means of removing from the skiplist is as we
consume the first request during the dequeue.

> I wonder though why this wouldn't mean skip list would be worse for both 
> lightly loaded and highly-loaded scenarios? Presumably height would need 
> to be balanced to compensate for that.

I think the answer is yes. skiplists uses probablistic balancing so they
are only from a bird's eye view as good as a rbtree. If you look at the
perf tests, the skiplists are generally faster, but it's close overall.

What sold me was lock_stat and that I could remove a few hacky patches
trying to hide some of the worst case behaviour of rbtree and how we had
frees within the critical submit path.
 
> In summary I have no idea for what number of in-flight requests would 
> they be better.
> 
> How about putting this patch aside for now since it doesn't sound it is 
> critical for deadline scheduling per se?

Oh no, we are not going back to the hacky patches like
https://patchwork.freedesktop.org/patch/407913/?series=84900=1
https://patchwork.freedesktop.org/patch/407903/?series=84900=1
-Chris
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Re: [Intel-gfx] [PATCH 21/41] drm/i915: Wrap cmpxchg64 with try_cmpxchg64() helper

[Tvrtko Ursulin]

On 25/01/2021 14:01, Chris Wilson wrote:

Wrap cmpxchg64 with a try_cmpxchg()-esque helper. Hiding the old-value
dance in the helper allows for cleaner code.

Signed-off-by: Chris Wilson 
---
  drivers/gpu/drm/i915/i915_utils.h | 32 +++
  1 file changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_utils.h 
b/drivers/gpu/drm/i915/i915_utils.h
index abd4dcd9f79c..95ead6bb1ba6 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -461,4 +461,36 @@ static inline bool timer_expired(const struct timer_list 
*t)
   */
  #define IS_ACTIVE(config) ((config) != 0)
  
+#ifndef try_cmpxchg64

+#if IS_ENABLED(CONFIG_64BIT)
+#define try_cmpxchg64(_ptr, _pold, _new) try_cmpxchg(_ptr, _pold, _new)
+#else
+#define try_cmpxchg64(_ptr, _pold, _new)   \
+({ \
+   __typeof__(_ptr) _old = (__typeof__(_ptr))(_pold);  \
+   __typeof__(*(_ptr)) __old = *_old;  \
+   __typeof__(*(_ptr)) __cur = cmpxchg64(_ptr, __old, _new);   \
+   bool success = __cur == __old;  \
+   if (unlikely(!success)) \
+   *_old = __cur;  \
+   likely(success);\
+})
+#endif
+#endif
+
+#ifndef xchg64
+#if IS_ENABLED(CONFIG_64BIT)
+#define xchg64(_ptr, _new) xchg(_ptr, _new)
+#else
+#define xchg64(_ptr, _new) \
+({ \
+   __typeof__(_ptr) __ptr = (_ptr);\
+   __typeof__(*(_ptr)) __old = *__ptr; \
+   while (!try_cmpxchg64(__ptr, &__old, (_new)))   \
+   ;   \
+   __old;  \
+})
+#endif
+#endif
+
  #endif /* !__I915_UTILS_H */



Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH] drm/i915/gt: Drop active.lock around active request read inside execlists

[Mika Kuoppala]

Chris Wilson  writes:

> As we find the active request for capturing upon a hang, we know that the
> lists are stable as we are inside the execlists tasklet, the only path
> that can modify those lists. As such, we do not need to disable irqs and
> take the active lock for a simple read of the current request.
>
> Suggested-by: Mika Kuoppala 
> Signed-off-by: Chris Wilson 
> Cc: Mika Kuoppala 

Reviewed-by: Mika Kuoppala 

> ---
>  drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index b5f2459cac2c..e20ab2eab3a8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2262,13 +2262,11 @@ static void execlists_capture(struct intel_engine_cs 
> *engine)
>   if (!cap)
>   return;
>  
> - spin_lock_irq(>active.lock);
>   cap->rq = active_context(engine, active_ccid(engine));
>   if (cap->rq) {
>   cap->rq = active_request(cap->rq->context->timeline, cap->rq);
>   cap->rq = i915_request_get_rcu(cap->rq);
>   }
> - spin_unlock_irq(>active.lock);
>   if (!cap->rq)
>   goto err_free;
>  
> -- 
> 2.20.1
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Re: [Intel-gfx] [PATCH] drm/i915/rkl: Remove require_force_probe protection

[Chris Wilson]

Quoting Pandey, Hariom (2021-01-27 15:10:53)
> Hi Chris,
> 
> (i) To your concern on the GPU dying issue gitlab#2743 --> this issue has 
> been resolved and not observed in last 3 runs --> The gitlab had been updated 
> with the pass results and closed.
> (ii) RocketLate platform has been setup in Public CI with the name " 
> fi-rkl-11500t" --> https://intel-gfx-ci.01.org/tree/drm-tip/bat-all.html? --> 
> This link shows last few Pass runs.
> 
> With the above progress, please confirm if you are fine to merge/accept this 
> patch of RKL force probe flag removal.

Now that we have some visibility in CI, those of us without rkl (who
_just_ see the bug reports) can all build up some confidence. From the
CI, it's looking good, but you want to wait for a few idle [full] runs to
get a true feel of the overall health.

So if people are happy that the scary forcewake error was truly a one off
and doesn't need any follow up, then I see nothing stopping us from
declaring ourselves in good shape -- barring a disastrous idle run.
-Chris
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Re: [Intel-gfx] [PATCH 6/9] drm/i915/adl_s: Load DMC

[Lucas De Marchi]

On Tue, Jan 26, 2021 at 08:11:56PM -0800, Aditya Swarup wrote:

From: Anusha Srivatsa 

Load DMC on ADL_S v2.01. This is the first offcial
release of DMC for ADL_S.

Cc: Jani Nikula 
Cc: Imre Deak 
Cc: Matt Roper 
Cc: Lucas De Marchi 
Cc: Aditya Swarup 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Aditya Swarup 
---
drivers/gpu/drm/i915/display/intel_csr.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_csr.c 
b/drivers/gpu/drm/i915/display/intel_csr.c
index 67dc64df78a5..db9f219c4b5a 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -40,6 +40,10 @@

#define GEN12_CSR_MAX_FW_SIZE   ICL_CSR_MAX_FW_SIZE

+#define ADLS_CSR_PATH  "i915/adls_dmc_ver2_01.bin"


Anusha, did you send this firmware to linux-firmware repo? I don't see
it there.

https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915


Lucas De Marchi


+#define ADLS_CSR_VERSION_REQUIRED  CSR_VERSION(2, 1)
+MODULE_FIRMWARE(ADLS_CSR_PATH);
+
#define DG1_CSR_PATH"i915/dg1_dmc_ver2_02.bin"
#define DG1_CSR_VERSION_REQUIREDCSR_VERSION(2, 2)
MODULE_FIRMWARE(DG1_CSR_PATH);
@@ -689,7 +693,11 @@ void intel_csr_ucode_init(struct drm_i915_private 
*dev_priv)
 */
intel_csr_runtime_pm_get(dev_priv);

-   if (IS_DG1(dev_priv)) {
+   if (IS_ALDERLAKE_S(dev_priv)) {
+   csr->fw_path = ADLS_CSR_PATH;
+   csr->required_version = ADLS_CSR_VERSION_REQUIRED;
+   csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+   } else if (IS_DG1(dev_priv)) {
csr->fw_path = DG1_CSR_PATH;
csr->required_version = DG1_CSR_VERSION_REQUIRED;
csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
--
2.27.0

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Re: [Intel-gfx] [PATCH] drm/i915/rkl: Remove require_force_probe protection

[Pandey, Hariom]

Hi Chris,

(i) To your concern on the GPU dying issue gitlab#2743 --> this issue has been 
resolved and not observed in last 3 runs --> The gitlab had been updated with 
the pass results and closed.
(ii) RocketLate platform has been setup in Public CI with the name " 
fi-rkl-11500t" --> https://intel-gfx-ci.01.org/tree/drm-tip/bat-all.html? --> 
This link shows last few Pass runs.

With the above progress, please confirm if you are fine to merge/accept this 
patch of RKL force probe flag removal.

Thanks
Hariom Pandey

> -Original Message-
> From: Chris Wilson 
> Sent: Friday, December 4, 2020 3:23 PM
> To: Kattamanchi, JaswanthX ; Pandey,
> Hariom ; Surendrakumar Upadhyay,
> TejaskumarX ; intel-
> g...@lists.freedesktop.org
> Cc: Naramasetti, LaxminarayanaX 
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/rkl: Remove require_force_probe
> protection
> 
> Quoting Kattamanchi, JaswanthX (2020-12-04 09:41:17)
> > Hi Tejas,
> >
> > As per your request triggered resume run on RKL CI machine, the testcases
> which chris mentioned were passing with this run, Please find the below logs
> for your reference
> 
> It is not particular to a testcase. HW failure rarely is.
> -Chris
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Re: [Intel-gfx] [PATCH 20/41] drm/i915: Replace priolist rbtree with a skiplist

[Tvrtko Ursulin]

On 25/01/2021 14:01, Chris Wilson wrote:

Replace the priolist rbtree with a skiplist. The crucial difference is
that walking and removing the first element of a skiplist is O(1), but


I wasn't (and am not) familiar with them, but wikipedia page says 
removal is O(logN) average case to O(N) worst case.


If I understand correctly O(1) could be ignoring the need to traverse 
from top to bottom level and removing the element from all. But since 
I915_PRIOLIST_HEIGHT is fixed maybe it is okay to call it O(1).


I wonder though why this wouldn't mean skip list would be worse for both 
lightly loaded and highly-loaded scenarios? Presumably height would need 
to be balanced to compensate for that.


In summary I have no idea for what number of in-flight requests would 
they be better.


How about putting this patch aside for now since it doesn't sound it is 
critical for deadline scheduling per se?


Regards,

Tvrtko


O(lgN) for an rbtree, as we need to rebalance on remove. This is a
hindrance for submission latency as it occurs between picking a request
for the priolist and submitting it to hardware, as well effectively
trippling the number of O(lgN) operations required under the irqoff lock.
This is critical to reducing the latency jitter with multiple clients.

The downsides to skiplists are that lookup/insertion is only
probablistically O(lgN) and there is a significant memory penalty to
as each skip node is larger than the rbtree equivalent. Furthermore, we
don't use dynamic arrays for the skiplist, so the allocation is fixed,
and imposes an upper bound on the scalability wrt to the number of
inflight requests.

Signed-off-by: Chris Wilson 
---
  .../drm/i915/gt/intel_execlists_submission.c  |  63 +++--
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  30 +--
  drivers/gpu/drm/i915/i915_priolist_types.h|  28 +-
  drivers/gpu/drm/i915/i915_scheduler.c | 244 ++
  drivers/gpu/drm/i915/i915_scheduler.h |  11 +-
  drivers/gpu/drm/i915/i915_scheduler_types.h   |   2 +-
  .../drm/i915/selftests/i915_mock_selftests.h  |   1 +
  .../gpu/drm/i915/selftests/i915_scheduler.c   |  53 +++-
  8 files changed, 316 insertions(+), 116 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 1103c8a00af1..129144dd86b0 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -244,11 +244,6 @@ static void ring_set_paused(const struct intel_engine_cs 
*engine, int state)
wmb();
  }
  
-static struct i915_priolist *to_priolist(struct rb_node *rb)

-{
-   return rb_entry(rb, struct i915_priolist, node);
-}
-
  static int rq_prio(const struct i915_request *rq)
  {
return READ_ONCE(rq->sched.attr.priority);
@@ -272,15 +267,31 @@ static int effective_prio(const struct i915_request *rq)
return prio;
  }
  
-static int queue_prio(const struct i915_sched_engine *se)

+static struct i915_request *first_request(struct i915_sched_engine *se)
  {
-   struct rb_node *rb;
+   struct i915_priolist *pl;
  
-	rb = rb_first_cached(>queue);

-   if (!rb)
+   for_each_priolist(pl, >queue) {
+   if (likely(!list_empty(>requests)))
+   return list_first_entry(>requests,
+   struct i915_request,
+   sched.link);
+
+   i915_priolist_advance(>queue, pl);
+   }
+
+   return NULL;
+}
+
+static int queue_prio(struct i915_sched_engine *se)
+{
+   struct i915_request *rq;
+
+   rq = first_request(se);
+   if (!rq)
return INT_MIN;
  
-	return to_priolist(rb)->priority;

+   return rq_prio(rq);
  }
  
  static int virtual_prio(const struct intel_engine_execlists *el)

@@ -290,7 +301,7 @@ static int virtual_prio(const struct intel_engine_execlists 
*el)
return rb ? rb_entry(rb, struct ve_node, rb)->prio : INT_MIN;
  }
  
-static bool need_preempt(const struct intel_engine_cs *engine,

+static bool need_preempt(struct intel_engine_cs *engine,
 const struct i915_request *rq)
  {
int last_prio;
@@ -1136,6 +1147,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
struct i915_request ** const last_port = port + execlists->port_mask;
struct i915_request *last, * const *active;
struct virtual_engine *ve;
+   struct i915_priolist *pl;
struct rb_node *rb;
bool submit = false;
  
@@ -1346,11 +1358,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)

break;
}
  
-	while ((rb = rb_first_cached(>active.queue))) {

-   struct i915_priolist *p = to_priolist(rb);
+   for_each_priolist(pl, >active.queue) {
struct i915_request *rq, *rn;
  
-		priolist_for_each_request_consume(rq, rn, p) {

Re: [Intel-gfx] [PATCH 2/9] drm/i915/adl_s: MCHBAR memory info registers are moved

[Lucas De Marchi]

On Tue, Jan 26, 2021 at 08:11:52PM -0800, Aditya Swarup wrote:

From: Caz Yokoyama 

The crwebview indicates on ADL-S that some of our MCHBAR
registers have moved from their traditional 0x50XX offsets to
new locations. The meaning and bit layout of the registers
remain same.

v2: Simplify logic to a single if else chain and fix indents.(Lucas)

Cc: Lucas De Marchi 
Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Matt Roper 
Signed-off-by: Caz Yokoyama 
Signed-off-by: Aditya Swarup 
---
drivers/gpu/drm/i915/i915_reg.h   |  5 +
drivers/gpu/drm/i915/intel_dram.c | 24 ++--
2 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aa872446337b..3031897239a0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10916,6 +10916,8 @@ enum skl_power_gate {
#define  SKL_DRAM_DDR_TYPE_LPDDR3   (2 << 0)
#define  SKL_DRAM_DDR_TYPE_LPDDR4   (3 << 0)

+#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x6048)
+
#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN_MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x500C)
#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN_MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x5010)
#define  SKL_DRAM_S_SHIFT   16
@@ -10943,6 +10945,9 @@ enum skl_power_gate {
#define  CNL_DRAM_RANK_3(0x2 << 9)
#define  CNL_DRAM_RANK_4(0x3 << 9)

+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x6054)
+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x6058)
+
/*
 * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
 * since on HSW we can't write to it using intel_uncore_write.
diff --git a/drivers/gpu/drm/i915/intel_dram.c 
b/drivers/gpu/drm/i915/intel_dram.c
index 4754296a250e..84f84e118531 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -181,17 +181,24 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
{
struct dram_info *dram_info = >dram_info;
struct dram_channel_info ch0 = {}, ch1 = {};
+   i915_reg_t ch0_reg, ch1_reg;
u32 val;
int ret;

-   val = intel_uncore_read(>uncore,
-   SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
+   if (IS_ALDERLAKE_S(i915)) {
+   ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
+   ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;
+   } else {
+   ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
+   ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;


I commented on the wrong version of the patch, but the bug is still
here. And this patch conflict with Jose's patch.

Lucas De Marchi
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/hdcp: mst streams type1 capability check

[Patchwork]

== Series Details ==

Series: drm/i915/hdcp: mst streams type1 capability check
URL   : https://patchwork.freedesktop.org/series/86345/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9687 -> Patchwork_19517


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/index.html

Known issues


  Here are the changes found in Patchwork_19517 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u:   NOTRUN -> [SKIP][1] ([fdo#109271]) +26 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html

  * igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u:   NOTRUN -> [WARN][2] ([i915#2283])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_flink_basic@bad-flink:
- fi-tgl-y:   [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar 
issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-7500u:   [PASS][5] -> [DMESG-WARN][6] ([i915#2605])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-kbl-7500u/igt@i915_pm_...@module-reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/fi-kbl-7500u/igt@i915_pm_...@module-reload.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u:   NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html

  
 Possible fixes 

  * igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2:  [FAIL][8] ([i915#1161] / [i915#262]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html

  * igt@prime_vgem@basic-gtt:
- fi-tgl-y:   [DMESG-WARN][10] ([i915#402]) -> [PASS][11] +2 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-tgl-y/igt@prime_v...@basic-gtt.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/fi-tgl-y/igt@prime_v...@basic-gtt.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
  [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
  [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (45 -> 39)
--

  Missing(6): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 
fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9687 -> Patchwork_19517

  CI-20190529: 20190529
  CI_DRM_9687: 7b5229b02338bfb24c3db4e76abb328d1e9cf8f1 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5974: a85398dcae50930c0e27548cf8c9575ad0bf69d1 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19517: ea0ed47d998c3704ead35b0a755a640fe6ca4616 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ea0ed47d998c drm/i915/hdcp: mst streams type1 capability check

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19517/index.html
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rename is_16gb_dimm to wm_lv_0_adjust_needed

[Lucas De Marchi]

On Wed, Jan 20, 2021 at 07:16:11AM -0800, Jose Souza wrote:

As it now it is always required for GEN12+ the is_16gb_dimm name
do not make sense for GEN12+.

Signed-off-by: José Roberto de Souza 
---
drivers/gpu/drm/i915/i915_drv.h   |  2 +-
drivers/gpu/drm/i915/intel_dram.c | 10 +-
drivers/gpu/drm/i915/intel_pm.c   |  2 +-
3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a2ae21082b34..adc008c65b14 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1134,7 +1134,7 @@ struct drm_i915_private {
} wm;

struct dram_info {
-   bool is_16gb_dimm;
+   bool wm_lv_0_adjust_needed;
u8 num_channels;
bool symmetric_memory;
enum intel_dram_type {
diff --git a/drivers/gpu/drm/i915/intel_dram.c 
b/drivers/gpu/drm/i915/intel_dram.c
index 4871d48589f9..a5850f0f25aa 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -207,7 +207,7 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
return -EINVAL;
}

-   dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
+   dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm;

dram_info->symmetric_memory = intel_is_dram_symmetric(, );

@@ -475,7 +475,7 @@ static int gen11_get_dram_info(struct drm_i915_private 
*i915)
return ret;
} else {
/* Always needed for GEN12+ */
-   i915->dram_info.is_16gb_dimm = true;
+   i915->dram_info.wm_lv_0_adjust_needed = true;
}

return icl_pcode_read_mem_global_info(i915);
@@ -491,7 +491,7 @@ int intel_dram_detect(struct drm_i915_private *i915)
 * This is only used for the level 0 watermark latency
 * w/a which does not apply to bxt/glk.
 */
-   dram_info->is_16gb_dimm = !IS_GEN9_LP(i915);
+   dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);


comment above also needs to be updated. With that:


Reviewed-by: Lucas De Marchi 


Lucas De Marchi



if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
return 0;
@@ -510,8 +510,8 @@ int intel_dram_detect(struct drm_i915_private *i915)

drm_dbg_kms(>drm, "DRAM channels: %u\n", dram_info->num_channels);

-   drm_dbg_kms(>drm, "DRAM 16Gb DIMMs: %s\n",
-   yesno(dram_info->is_16gb_dimm));
+   drm_dbg_kms(>drm, "Watermark level 0 adjustment needed: %s\n",
+   yesno(dram_info->wm_lv_0_adjust_needed));

return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 992fce8b8d13..f778aae19f82 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2930,7 +2930,7 @@ static void intel_read_wm_latency(struct drm_i915_private 
*dev_priv,
 * any underrun. If not able to get Dimm info assume 16GB dimm
 * to avoid any underrun.
 */
-   if (dev_priv->dram_info.is_16gb_dimm)
+   if (dev_priv->dram_info.wm_lv_0_adjust_needed)
wm[0] += 1;

} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
--
2.30.0

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Re: [Intel-gfx] [PATCH 19/41] drm/i915/gt: Show scheduler queues when dumping state

[Chris Wilson]

Quoting Tvrtko Ursulin (2021-01-27 14:50:19)
> 
> On 27/01/2021 14:35, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2021-01-27 14:13:11)
> >>
> >> On 25/01/2021 14:01, Chris Wilson wrote:
> >>> Move the scheduler pretty printer from out of the execlists state to
> >>> match its more common location.
> >>>
> >>> Signed-off-by: Chris Wilson 
> >>> ---
> >>>drivers/gpu/drm/i915/gt/intel_engine_cs.c | 34 +--
> >>>1 file changed, 19 insertions(+), 15 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
> >>> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >>> index cdd07aeada05..2f9a8960144b 100644
> >>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >>> @@ -1443,20 +1443,15 @@ static void intel_engine_print_registers(struct 
> >>> intel_engine_cs *engine,
> >>>
> >>>if (intel_engine_in_guc_submission_mode(engine)) {
> >>>/* nothing to print yet */
> >>> - } else if (HAS_EXECLISTS(dev_priv)) {
> >>> - struct i915_request * const *port, *rq;
> >>>const u32 *hws =
> >>>>status_page.addr[I915_HWS_CSB_BUF0_INDEX];
> >>>const u8 num_entries = execlists->csb_size;
> >>>unsigned int idx;
> >>>u8 read, write;
> >>>
> >>> - drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? 
> >>> %s, timeslice? %s\n",
> >>> -yesno(test_bit(TASKLET_STATE_SCHED,
> >>> -   >active.tasklet.state)),
> >>> -
> >>> enableddisabled(!atomic_read(>active.tasklet.count)),
> >>> -repr_timer(>execlists.preempt),
> >>> -repr_timer(>execlists.timer));
> >>> + drm_printf(m, "\tExeclists preempt? %s, timeslice? %s\n",
> >>> +repr_timer(>preempt),
> >>> +repr_timer(>timer));
> >>>
> >>>read = execlists->csb_head;
> >>>write = READ_ONCE(*execlists->csb_write);
> >>> @@ -1477,6 +1472,22 @@ static void intel_engine_print_registers(struct 
> >>> intel_engine_cs *engine,
> >>>drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, 
> >>> context: %d\n",
> >>>   idx, hws[idx * 2], hws[idx * 2 + 1]);
> >>>}
> >>> + } else if (INTEL_GEN(dev_priv) > 6) {
> >>> + drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
> >>> +ENGINE_READ(engine, RING_PP_DIR_BASE));
> >>> + drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
> >>> +ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
> >>> + drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
> >>> +ENGINE_READ(engine, RING_PP_DIR_DCLV));
> >>> + }
> >>> +
> >>> + if (engine->active.tasklet.func) {
> >>> + struct i915_request * const *port, *rq;
> >>> +
> >>> + drm_printf(m, "\tTasklet queued? %s (%s)\n",
> >>> +yesno(test_bit(TASKLET_STATE_SCHED,
> >>> +   >active.tasklet.state)),
> >>> +
> >>> enableddisabled(!atomic_read(>active.tasklet.count)));
> >>
> >> Or have i915_sched_print_state() exported? Again it will depend on how
> >> clean split will be possible.
> > 
> > Not quite, unfortunately this is not dumping generic state but the
> > backend bookkeeping for execlists/ringscheduler. Common for that pair,
> > not so common with the guc.
> > 
> > I guess I oversold it.
> 
> Okay I see it after a less superficial look. I guess it's okay. Too hard 
> to get perfect separation so I'll focus on the scheduling changes.

Inside intel_execlists_show_requests, we have the scheduler list pretty
printer. Maybe something to salvage here after all.
-Chris
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Re: [Intel-gfx] [PATCH 19/41] drm/i915/gt: Show scheduler queues when dumping state

[Tvrtko Ursulin]

On 27/01/2021 14:35, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2021-01-27 14:13:11)


On 25/01/2021 14:01, Chris Wilson wrote:

Move the scheduler pretty printer from out of the execlists state to
match its more common location.

Signed-off-by: Chris Wilson 
---
   drivers/gpu/drm/i915/gt/intel_engine_cs.c | 34 +--
   1 file changed, 19 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index cdd07aeada05..2f9a8960144b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1443,20 +1443,15 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
   
   if (intel_engine_in_guc_submission_mode(engine)) {

   /* nothing to print yet */
- } else if (HAS_EXECLISTS(dev_priv)) {
- struct i915_request * const *port, *rq;
   const u32 *hws =
   >status_page.addr[I915_HWS_CSB_BUF0_INDEX];
   const u8 num_entries = execlists->csb_size;
   unsigned int idx;
   u8 read, write;
   
- drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",

-yesno(test_bit(TASKLET_STATE_SCHED,
-   >active.tasklet.state)),
-
enableddisabled(!atomic_read(>active.tasklet.count)),
-repr_timer(>execlists.preempt),
-repr_timer(>execlists.timer));
+ drm_printf(m, "\tExeclists preempt? %s, timeslice? %s\n",
+repr_timer(>preempt),
+repr_timer(>timer));
   
   read = execlists->csb_head;

   write = READ_ONCE(*execlists->csb_write);
@@ -1477,6 +1472,22 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
   drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: 
%d\n",
  idx, hws[idx * 2], hws[idx * 2 + 1]);
   }
+ } else if (INTEL_GEN(dev_priv) > 6) {
+ drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
+ENGINE_READ(engine, RING_PP_DIR_BASE));
+ drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
+ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
+ drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
+ENGINE_READ(engine, RING_PP_DIR_DCLV));
+ }
+
+ if (engine->active.tasklet.func) {
+ struct i915_request * const *port, *rq;
+
+ drm_printf(m, "\tTasklet queued? %s (%s)\n",
+yesno(test_bit(TASKLET_STATE_SCHED,
+   >active.tasklet.state)),
+
enableddisabled(!atomic_read(>active.tasklet.count)));


Or have i915_sched_print_state() exported? Again it will depend on how
clean split will be possible.


Not quite, unfortunately this is not dumping generic state but the
backend bookkeeping for execlists/ringscheduler. Common for that pair,
not so common with the guc.

I guess I oversold it.


Okay I see it after a less superficial look. I guess it's okay. Too hard 
to get perfect separation so I'll focus on the scheduling changes.


Regards,

Tvrtko
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[Intel-gfx] ✓ Fi.CI.IGT: success for HDCP 2.2 DP errata

[Patchwork]

== Series Details ==

Series: HDCP 2.2 DP errata
URL   : https://patchwork.freedesktop.org/series/86340/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9687_full -> Patchwork_19514_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19514_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@chamelium:
- shard-iclb: NOTRUN -> [SKIP][1] ([fdo#111827])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-iclb7/igt@feature_discov...@chamelium.html

  * igt@gem_ctx_persistence@clone:
- shard-hsw:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-hsw4/igt@gem_ctx_persiste...@clone.html

  * igt@gem_exec_fair@basic-deadline:
- shard-kbl:  [PASS][3] -> [FAIL][4] ([i915#2846])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-kbl2/igt@gem_exec_f...@basic-deadline.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-kbl6/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842]) +1 similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-tglb5/igt@gem_exec_fair@basic-p...@bcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-tglb1/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl:  [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_reloc@basic-many-active@vcs0:
- shard-kbl:  NOTRUN -> [FAIL][9] ([i915#2389]) +4 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-kbl6/igt@gem_exec_reloc@basic-many-act...@vcs0.html

  * igt@gem_exec_schedule@u-fairslice@vecs0:
- shard-skl:  [PASS][10] -> [DMESG-WARN][11] ([i915#1610] / 
[i915#2803])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-skl10/igt@gem_exec_schedule@u-fairsl...@vecs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-skl5/igt@gem_exec_schedule@u-fairsl...@vecs0.html

  * igt@gem_render_copy@yf-tiled-to-vebox-linear:
- shard-iclb: NOTRUN -> [SKIP][12] ([i915#768]) +1 similar issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-iclb7/igt@gem_render_c...@yf-tiled-to-vebox-linear.html

  * igt@gem_softpin@evict-snoop-interruptible:
- shard-iclb: NOTRUN -> [SKIP][13] ([fdo#109312])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-iclb7/igt@gem_soft...@evict-snoop-interruptible.html

  * igt@gem_vm_create@destroy-race:
- shard-tglb: [PASS][14] -> [INCOMPLETE][15] ([i915#2912])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-tglb1/igt@gem_vm_cre...@destroy-race.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-tglb2/igt@gem_vm_cre...@destroy-race.html

  * igt@gen7_exec_parse@basic-allowed:
- shard-iclb: NOTRUN -> [SKIP][16] ([fdo#109289])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-iclb7/igt@gen7_exec_pa...@basic-allowed.html

  * igt@i915_hangman@engine-error@vecs0:
- shard-kbl:  NOTRUN -> [SKIP][17] ([fdo#109271]) +45 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-kbl6/igt@i915_hangman@engine-er...@vecs0.html

  * igt@i915_selftest@live@hangcheck:
- shard-hsw:  NOTRUN -> [INCOMPLETE][18] ([i915#2782])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-hsw4/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][19] -> [FAIL][20] ([i915#2597])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/shard-tglb8/igt@kms_async_fl...@test-time-stamp.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-tglb3/igt@kms_async_fl...@test-time-stamp.html

  * igt@kms_ccs@pipe-c-crc-primary-basic:
- shard-skl:  NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111304])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-skl6/igt@kms_...@pipe-c-crc-primary-basic.html

  * igt@kms_chamelium@dp-mode-timings:
- shard-iclb: NOTRUN -> [SKIP][22] ([fdo#109284] / [fdo#111827]) +2 
similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19514/shard-iclb7/igt@kms_chamel...@dp-mode-timings.html

  * igt@kms_chamelium@vga-hpd-enable-disable-mode:
- shard-hsw:  NOTRUN -> [SKIP][23] 

Re: [Intel-gfx] [PATCH 2/4] drm/i915/gen11+: Only load DRAM information from pcode

[Lucas De Marchi]

On Wed, Jan 20, 2021 at 07:16:09AM -0800, Jose Souza wrote:

Up to now we were reading some DRAM information from MCHBAR register
and from pcode what is already not good but some GEN12(TGL-H and ADL-S)
platforms have MCHBAR DRAM information in different offsets.

This was notified to HW team that decided that the best alternative is
always apply the 16gb_dimm watermark adjustment for GEN12+ platforms
and read the remaning DRAM information needed to other display
programming from pcode.

So here moving the DRAM pcode function to intel_dram.c, removing
the duplicated fields from intel_qgv_info, setting and using
information from dram_info.

Signed-off-by: José Roberto de Souza 
---
drivers/gpu/drm/i915/display/intel_bw.c | 98 +
drivers/gpu/drm/i915/i915_drv.c |  5 +-
drivers/gpu/drm/i915/i915_drv.h |  1 +
drivers/gpu/drm/i915/intel_dram.c   | 77 ++-
4 files changed, 97 insertions(+), 84 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index bd060404d249..1368bd96ed73 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -19,77 +19,9 @@ struct intel_qgv_point {

struct intel_qgv_info {
struct intel_qgv_point points[I915_NUM_QGV_POINTS];
-   u8 num_points;
-   u8 num_channels;
u8 t_bl;
-   enum intel_dram_type dram_type;


humn... given this struct already has padding, we could very well leave
the num_points field. See below.


static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
 struct intel_qgv_point *sp,
 int point)
@@ -139,17 +71,19 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private 
*dev_priv,
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
  struct intel_qgv_info *qi)
{
+   struct dram_info *dram_info = _priv->dram_info;
int i, ret;

-   ret = icl_pcode_read_mem_global_info(dev_priv, qi);
-   if (ret)
-   return ret;
+   if (IS_GEN(dev_priv, 12))
+   qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 16;
+   else if (IS_GEN(dev_priv, 11))
+   qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;

if (drm_WARN_ON(_priv->drm,
-   qi->num_points > ARRAY_SIZE(qi->points)))
-   qi->num_points = ARRAY_SIZE(qi->points);
+   dram_info->qgv_points > ARRAY_SIZE(qi->points)))
+   dram_info->qgv_points = ARRAY_SIZE(qi->points);


previously we were overriding a member of qi. Now we are overriding a
member of dram_info, which seems to cross the boundaries of what this
code should be doing.

So maybe:

qi->num_points = dev_priv->dram_info->qgv_points;

and leave the check alone and also the renames in this file?
Also, dram_info->qgv_points should be named dram_info->num_qgv_points
for consistency with other structs.



-   for (i = 0; i < qi->num_points; i++) {
+   for (i = 0; i < dram_info->qgv_points; i++) {
struct intel_qgv_point *sp = >points[i];

ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
@@ -171,12 +105,13 @@ static int icl_calc_bw(int dclk, int num, int den)
return DIV_ROUND_CLOSEST(num * dclk * 100, den * 6);
}

-static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
+static int icl_sagv_max_dclk(struct drm_i915_private *dev_priv,
+const struct intel_qgv_info *qi)
{
u16 dclk = 0;
int i;

-   for (i = 0; i < qi->num_points; i++)
+   for (i = 0; i < dev_priv->dram_info.qgv_points; i++)
dclk = max(dclk, qi->points[i].dclk);

return dclk;
@@ -207,6 +142,7 @@ static const struct intel_sa_info rkl_sa_info = {

static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct 
intel_sa_info *sa)
{
+   struct dram_info *dram_info = _priv->dram_info;
struct intel_qgv_info qi = {};
bool is_y_tile = true; /* assume y tile may be used */
int num_channels;
@@ -222,10 +158,10 @@ static int icl_get_bw_info(struct drm_i915_private 
*dev_priv, const struct intel
"Failed to get memory subsystem information, ignoring 
bandwidth limits");
return ret;
}
-   num_channels = qi.num_channels;
+   num_channels = dram_info->num_channels;

deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
-   dclk_max = icl_sagv_max_dclk();
+   dclk_max = icl_sagv_max_dclk(dev_priv, );

ipqdepthpch = 16;

@@ -241,9 +177,9 @@ static int icl_get_bw_info(struct drm_i915_private 
*dev_priv, const struct intel
clpchgroup = (sa->deburst * deinterleave / num_channels) << i;
bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;

-   

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Nuke not needed members of dram_info

[Lucas De Marchi]

On Wed, Jan 20, 2021 at 07:29:37PM +, Jose Souza wrote:

On Wed, 2021-01-20 at 10:52 -0800, Lucas De Marchi wrote:

On Wed, Jan 20, 2021 at 10:42:46AM -0800, Jose Souza wrote:
> On Wed, 2021-01-20 at 10:31 -0800, Lucas De Marchi wrote:
> > On Wed, Jan 20, 2021 at 07:16:08AM -0800, Jose Souza wrote:
> > > Valid, ranks and bandwidth_kbps are set into dram_info but are not
> > > used anywhere else so nuking it.
> > >
> > > Signed-off-by: José Roberto de Souza 
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c   |  4 +--
> > > drivers/gpu/drm/i915/i915_drv.h   |  3 --
> > > drivers/gpu/drm/i915/intel_dram.c | 47 +++
> > > 3 files changed, 12 insertions(+), 42 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c 
b/drivers/gpu/drm/i915/i915_drv.c
> > > index f5666b44ea9d..a1cc60de99f0 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -609,8 +609,8 @@ static int i915_driver_hw_probe(struct 
drm_i915_private *dev_priv)
> > >
> > >  intel_opregion_setup(dev_priv);
> > >  /*
> > > - * Fill the dram structure to get the system raw bandwidth and
> > > - * dram info. This will be used for memory latency calculation.
> > > + * Fill the dram structure to get the system dram info. This 
will be
> > > + * used for memory latency calculation.
> > >   */
> > >  intel_dram_detect(dev_priv);
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
b/drivers/gpu/drm/i915/i915_drv.h
> > > index 8376cff5ba86..250e92910fa1 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1134,11 +1134,8 @@ struct drm_i915_private {
> > >  } wm;
> > >
> > >  struct dram_info {
> > > -bool valid;
> > >  bool is_16gb_dimm;
> > >  u8 num_channels;
> > > -u8 ranks;
> > > -u32 bandwidth_kbps;
> > >  bool symmetric_memory;
> > >  enum intel_dram_type {
> > >  INTEL_DRAM_UNKNOWN,
> > > diff --git a/drivers/gpu/drm/i915/intel_dram.c 
b/drivers/gpu/drm/i915/intel_dram.c
> > > index 4754296a250e..694fbd8c9cd4 100644
> > > --- a/drivers/gpu/drm/i915/intel_dram.c
> > > +++ b/drivers/gpu/drm/i915/intel_dram.c
> > > @@ -201,17 +201,7 @@ skl_dram_get_channels_info(struct drm_i915_private 
*i915)
> > >  return -EINVAL;
> > >  }
> > >
> > > -/*
> > > - * If any of the channel is single rank channel, worst case 
output
> > > - * will be same as if single rank memory, so consider single rank
> > > - * memory.
> > > - */
> > > -if (ch0.ranks == 1 || ch1.ranks == 1)
> > > -dram_info->ranks = 1;
> > > -else
> > > -dram_info->ranks = max(ch0.ranks, ch1.ranks);
> > > -
> > > -if (dram_info->ranks == 0) {
> > > +if (ch0.ranks == 0 && ch1.ranks == 0) {
> >
> > previously if any of them were != 0, we would not fall here.
>
> This is the same behavior.

indeed, I misread the condition

>
> >
> >
> > >  drm_info(>drm, "couldn't get memory rank information\n");
> > >  return -EINVAL;
> > >  }
> > > @@ -269,16 +259,12 @@ skl_get_dram_info(struct drm_i915_private *i915)
> > >  mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
> > >  SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
> > >
> > > -dram_info->bandwidth_kbps = dram_info->num_channels *
> > > -mem_freq_khz * 8;
> > > -
> > > -if (dram_info->bandwidth_kbps == 0) {
> > > +if (dram_info->num_channels * mem_freq_khz == 0) {
> > >  drm_info(>drm,
> > >   "Couldn't get system memory bandwidth\n");
> > >  return -EINVAL;
> > >  }
> > >
> > > -dram_info->valid = true;
> > >  return 0;
> > > }
> > >
> > > @@ -365,7 +351,7 @@ static int bxt_get_dram_info(struct drm_i915_private 
*i915)
> > >  struct dram_info *dram_info = >dram_info;
> > >  u32 dram_channels;
> > >  u32 mem_freq_khz, val;
> > > -u8 num_active_channels;
> > > +u8 num_active_channels, valid_ranks = 0;
> > >  int i;
> > >
> > >  val = intel_uncore_read(>uncore, BXT_P_CR_MC_BIOS_REQ_0_0_0);
> > > @@ -375,10 +361,7 @@ static int bxt_get_dram_info(struct drm_i915_private 
*i915)
> > >  dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
> > >  num_active_channels = hweight32(dram_channels);
> > >
> > > -/* Each active bit represents 4-byte channel */
> > > -dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels 
* 4);
> > > -
> > > -if (dram_info->bandwidth_kbps == 0) {
> > > +if (mem_freq_khz * num_active_channels == 0) {
> >
> > maybe better to replace with a local var?
> >
> >   bandwidth_kbps = mem_freq_khz * num_active_channels;
> >
> > and then check it where needed.
>
> The only place it is used is in this if to return -EINVAL, same for the SKL 
function.
> The multiplication fits under the 

Re: [Intel-gfx] [PATCH 19/41] drm/i915/gt: Show scheduler queues when dumping state

[Chris Wilson]

Quoting Tvrtko Ursulin (2021-01-27 14:13:11)
> 
> On 25/01/2021 14:01, Chris Wilson wrote:
> > Move the scheduler pretty printer from out of the execlists state to
> > match its more common location.
> > 
> > Signed-off-by: Chris Wilson 
> > ---
> >   drivers/gpu/drm/i915/gt/intel_engine_cs.c | 34 +--
> >   1 file changed, 19 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
> > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index cdd07aeada05..2f9a8960144b 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -1443,20 +1443,15 @@ static void intel_engine_print_registers(struct 
> > intel_engine_cs *engine,
> >   
> >   if (intel_engine_in_guc_submission_mode(engine)) {
> >   /* nothing to print yet */
> > - } else if (HAS_EXECLISTS(dev_priv)) {
> > - struct i915_request * const *port, *rq;
> >   const u32 *hws =
> >   >status_page.addr[I915_HWS_CSB_BUF0_INDEX];
> >   const u8 num_entries = execlists->csb_size;
> >   unsigned int idx;
> >   u8 read, write;
> >   
> > - drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? 
> > %s, timeslice? %s\n",
> > -yesno(test_bit(TASKLET_STATE_SCHED,
> > -   >active.tasklet.state)),
> > -
> > enableddisabled(!atomic_read(>active.tasklet.count)),
> > -repr_timer(>execlists.preempt),
> > -repr_timer(>execlists.timer));
> > + drm_printf(m, "\tExeclists preempt? %s, timeslice? %s\n",
> > +repr_timer(>preempt),
> > +repr_timer(>timer));
> >   
> >   read = execlists->csb_head;
> >   write = READ_ONCE(*execlists->csb_write);
> > @@ -1477,6 +1472,22 @@ static void intel_engine_print_registers(struct 
> > intel_engine_cs *engine,
> >   drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: 
> > %d\n",
> >  idx, hws[idx * 2], hws[idx * 2 + 1]);
> >   }
> > + } else if (INTEL_GEN(dev_priv) > 6) {
> > + drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
> > +ENGINE_READ(engine, RING_PP_DIR_BASE));
> > + drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
> > +ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
> > + drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
> > +ENGINE_READ(engine, RING_PP_DIR_DCLV));
> > + }
> > +
> > + if (engine->active.tasklet.func) {
> > + struct i915_request * const *port, *rq;
> > +
> > + drm_printf(m, "\tTasklet queued? %s (%s)\n",
> > +yesno(test_bit(TASKLET_STATE_SCHED,
> > +   >active.tasklet.state)),
> > +
> > enableddisabled(!atomic_read(>active.tasklet.count)));
> 
> Or have i915_sched_print_state() exported? Again it will depend on how 
> clean split will be possible.

Not quite, unfortunately this is not dumping generic state but the
backend bookkeeping for execlists/ringscheduler. Common for that pair,
not so common with the guc.

I guess I oversold it.
-Chris
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Re: [Intel-gfx] [PATCH 17/22] drm/i915/adl_s: MCHBAR memory info registers are moved

[Lucas De Marchi]

On Fri, Dec 04, 2020 at 05:08:39PM -0800, Aditya Swarup wrote:

From: Caz Yokoyama 

The crwebview indicates on ADL-S that some of our MCHBAR
registers have moved from their traditional 0x50XX offsets to
new locations. The meaning and bit layout of the registers
remain same.

v2: Simplify logic to a single if else chain and fix indents.(Lucas)

Cc: Lucas De Marchi 
Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Matt Roper 
Signed-off-by: Caz Yokoyama 
Signed-off-by: Aditya Swarup 
---
drivers/gpu/drm/i915/i915_reg.h   |  5 +
drivers/gpu/drm/i915/intel_dram.c | 23 +--
2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ce4ef7fa4000..55e186293fbb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10865,6 +10865,8 @@ enum skl_power_gate {
#define  SKL_DRAM_DDR_TYPE_LPDDR3   (2 << 0)
#define  SKL_DRAM_DDR_TYPE_LPDDR4   (3 << 0)

+#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x6048)
+
#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN_MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x500C)
#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN_MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x5010)
#define  SKL_DRAM_S_SHIFT   16
@@ -10892,6 +10894,9 @@ enum skl_power_gate {
#define  CNL_DRAM_RANK_3(0x2 << 9)
#define  CNL_DRAM_RANK_4(0x3 << 9)

+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x6054)
+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x6058)
+
/*
 * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
 * since on HSW we can't write to it using intel_uncore_write.
diff --git a/drivers/gpu/drm/i915/intel_dram.c 
b/drivers/gpu/drm/i915/intel_dram.c
index 4754296a250e..fc9942139ccc 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -181,17 +181,24 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
{
struct dram_info *dram_info = >dram_info;
struct dram_channel_info ch0 = {}, ch1 = {};
+   i915_reg_t ch0_reg, ch1_reg;
u32 val;
int ret;

-   val = intel_uncore_read(>uncore,
-   SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
+   if (IS_ALDERLAKE_S(i915)) {
+   ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
+   ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;
+   } else {
+   ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
+   ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;


this is not right and breaks all the other platforms.

Also this patch conflicts with
https://patchwork.freedesktop.org/series/86092/
and general direction that we should get these values from pcode rather
than keep changing the offset we use to avoid MCHBAR.

Lucas De Marchi
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Prefer local execution_mask for determing viable engines

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Prefer local execution_mask for determing viable engines
URL   : https://patchwork.freedesktop.org/series/86342/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9687 -> Patchwork_19516


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/index.html

Known issues


  Here are the changes found in Patchwork_19516 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-y:   [PASS][1] -> [DMESG-WARN][2] ([i915#2411] / 
[i915#402])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html

  * igt@i915_selftest@live@hangcheck:
- fi-glk-dsi: [PASS][3] -> [INCOMPLETE][4] ([i915#2895])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-glk-dsi/igt@i915_selftest@l...@hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/fi-glk-dsi/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-7500u:   [PASS][5] -> [DMESG-FAIL][6] ([i915#165])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [PASS][7] -> [DMESG-WARN][8] ([i915#402])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
 Possible fixes 

  * igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2:  [FAIL][9] ([i915#1161] / [i915#262]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html

  * igt@prime_vgem@basic-gtt:
- fi-tgl-y:   [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +1 
similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-tgl-y/igt@prime_v...@basic-gtt.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/fi-tgl-y/igt@prime_v...@basic-gtt.html

  
  [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#2895]: https://gitlab.freedesktop.org/drm/intel/issues/2895
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (45 -> 38)
--

  Missing(7): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-bsw-cyan 
fi-ctg-p8600 fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9687 -> Patchwork_19516

  CI-20190529: 20190529
  CI_DRM_9687: 7b5229b02338bfb24c3db4e76abb328d1e9cf8f1 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5974: a85398dcae50930c0e27548cf8c9575ad0bf69d1 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19516: f44073b31909dda007cf8c510eebdff04b9da8fe @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f44073b31909 drm/i915/gt: Prefer local execution_mask for determing viable 
engines

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19516/index.html
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Re: [Intel-gfx] [PATCH 18/41] drm/i915: Move tasklet from execlists to sched

[Chris Wilson]

Quoting Tvrtko Ursulin (2021-01-27 14:10:55)
> 
> + Matt to check on how this fits with GuC. This patch and a few before 
> it in this series.
> 
> The split between physical and scheduling engine (i915_sched_engine) 
> makes sense to me. Gut feeling says it should work for GuC as well, in 
> principle.
> 
> A small comment or two below:
> 
> On 25/01/2021 14:01, Chris Wilson wrote:
> > Move the scheduling tasklists out of the execlists backend into the
> > per-engine scheduling bookkeeping.
> > 
> > Signed-off-by: Chris Wilson 
> > ---
> >   drivers/gpu/drm/i915/gt/intel_engine.h| 14 
> >   drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++--
> >   drivers/gpu/drm/i915/gt/intel_engine_types.h  |  5 --
> >   .../drm/i915/gt/intel_execlists_submission.c  | 65 +--
> >   drivers/gpu/drm/i915/gt/intel_gt_irq.c|  2 +-
> >   drivers/gpu/drm/i915/gt/selftest_execlists.c  | 16 ++---
> >   drivers/gpu/drm/i915/gt/selftest_hangcheck.c  |  2 +-
> >   drivers/gpu/drm/i915/gt/selftest_lrc.c|  6 +-
> >   drivers/gpu/drm/i915/gt/selftest_reset.c  |  2 +-
> >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 ++---
> >   drivers/gpu/drm/i915/i915_scheduler.c | 14 ++--
> >   drivers/gpu/drm/i915/i915_scheduler.h | 20 ++
> >   drivers/gpu/drm/i915/i915_scheduler_types.h   |  6 ++
> >   .../gpu/drm/i915/selftests/i915_scheduler.c   | 16 ++---
> >   14 files changed, 99 insertions(+), 98 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h 
> > b/drivers/gpu/drm/i915/gt/intel_engine.h
> > index 20974415e7d8..801ae54cf60d 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> > @@ -122,20 +122,6 @@ execlists_active(const struct intel_engine_execlists 
> > *execlists)
> >   return active;
> >   }
> >   
> > -static inline void
> > -execlists_active_lock_bh(struct intel_engine_execlists *execlists)
> > -{
> > - local_bh_disable(); /* prevent local softirq and lock recursion */
> > - tasklet_lock(>tasklet);
> > -}
> > -
> > -static inline void
> > -execlists_active_unlock_bh(struct intel_engine_execlists *execlists)
> > -{
> > - tasklet_unlock(>tasklet);
> > - local_bh_enable(); /* restore softirq, and kick ksoftirqd! */
> > -}
> > -
> >   static inline u32
> >   intel_read_status_page(const struct intel_engine_cs *engine, int reg)
> >   {
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
> > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index ef225da35399..cdd07aeada05 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -902,7 +902,6 @@ int intel_engines_init(struct intel_gt *gt)
> >   void intel_engine_cleanup_common(struct intel_engine_cs *engine)
> >   {
> >   i915_sched_fini_engine(>active);
> > - tasklet_kill(>execlists.tasklet); /* flush the callback */
> >   
> >   intel_breadcrumbs_free(engine->breadcrumbs);
> >   
> > @@ -1187,7 +1186,7 @@ static bool ring_is_idle(struct intel_engine_cs 
> > *engine)
> >   
> >   void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool 
> > sync)
> >   {
> > - struct tasklet_struct *t = >execlists.tasklet;
> > + struct tasklet_struct *t = >active.tasklet;
> >   
> >   if (!t->func)
> >   return;
> > @@ -1454,8 +1453,8 @@ static void intel_engine_print_registers(struct 
> > intel_engine_cs *engine,
> >   
> >   drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? 
> > %s, timeslice? %s\n",
> >  yesno(test_bit(TASKLET_STATE_SCHED,
> > -   >execlists.tasklet.state)),
> > -
> > enableddisabled(!atomic_read(>execlists.tasklet.count)),
> > +   >active.tasklet.state)),
> > +
> > enableddisabled(!atomic_read(>active.tasklet.count)),
> >  repr_timer(>execlists.preempt),
> >  repr_timer(>execlists.timer));
> >   
> > @@ -1479,7 +1478,7 @@ static void intel_engine_print_registers(struct 
> > intel_engine_cs *engine,
> >  idx, hws[idx * 2], hws[idx * 2 + 1]);
> >   }
> >   
> > - execlists_active_lock_bh(execlists);
> > + i915_sched_lock_bh(>active);
> >   rcu_read_lock();
> >   for (port = execlists->active; (rq = *port); port++) {
> >   char hdr[160];
> > @@ -1510,7 +1509,7 @@ static void intel_engine_print_registers(struct 
> > intel_engine_cs *engine,
> >   i915_request_show(m, rq, hdr, 0);
> >   }
> >   rcu_read_unlock();
> > - execlists_active_unlock_bh(execlists);
> > + i915_sched_unlock_bh(>active);
> >   } else if (INTEL_GEN(dev_priv) > 6) {
> >   drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
> >

Re: [Intel-gfx] [PATCH 19/41] drm/i915/gt: Show scheduler queues when dumping state

[Tvrtko Ursulin]

On 25/01/2021 14:01, Chris Wilson wrote:

Move the scheduler pretty printer from out of the execlists state to
match its more common location.

Signed-off-by: Chris Wilson 
---
  drivers/gpu/drm/i915/gt/intel_engine_cs.c | 34 +--
  1 file changed, 19 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index cdd07aeada05..2f9a8960144b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1443,20 +1443,15 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
  
  	if (intel_engine_in_guc_submission_mode(engine)) {

/* nothing to print yet */
-   } else if (HAS_EXECLISTS(dev_priv)) {
-   struct i915_request * const *port, *rq;
const u32 *hws =
>status_page.addr[I915_HWS_CSB_BUF0_INDEX];
const u8 num_entries = execlists->csb_size;
unsigned int idx;
u8 read, write;
  
-		drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",

-  yesno(test_bit(TASKLET_STATE_SCHED,
- >active.tasklet.state)),
-  
enableddisabled(!atomic_read(>active.tasklet.count)),
-  repr_timer(>execlists.preempt),
-  repr_timer(>execlists.timer));
+   drm_printf(m, "\tExeclists preempt? %s, timeslice? %s\n",
+  repr_timer(>preempt),
+  repr_timer(>timer));
  
  		read = execlists->csb_head;

write = READ_ONCE(*execlists->csb_write);
@@ -1477,6 +1472,22 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: 
%d\n",
   idx, hws[idx * 2], hws[idx * 2 + 1]);
}
+   } else if (INTEL_GEN(dev_priv) > 6) {
+   drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
+  ENGINE_READ(engine, RING_PP_DIR_BASE));
+   drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
+  ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
+   drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
+  ENGINE_READ(engine, RING_PP_DIR_DCLV));
+   }
+
+   if (engine->active.tasklet.func) {
+   struct i915_request * const *port, *rq;
+
+   drm_printf(m, "\tTasklet queued? %s (%s)\n",
+  yesno(test_bit(TASKLET_STATE_SCHED,
+ >active.tasklet.state)),
+  
enableddisabled(!atomic_read(>active.tasklet.count)));


Or have i915_sched_print_state() exported? Again it will depend on how 
clean split will be possible.


Regards,

Tvrtko

  
  		i915_sched_lock_bh(>active);

rcu_read_lock();
@@ -1510,13 +1521,6 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
}
rcu_read_unlock();
i915_sched_unlock_bh(>active);
-   } else if (INTEL_GEN(dev_priv) > 6) {
-   drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
-  ENGINE_READ(engine, RING_PP_DIR_BASE));
-   drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
-  ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
-   drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
-  ENGINE_READ(engine, RING_PP_DIR_DCLV));
}
  }
  


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Re: [Intel-gfx] [PATCH 18/41] drm/i915: Move tasklet from execlists to sched

[Tvrtko Ursulin]

+ Matt to check on how this fits with GuC. This patch and a few before 
it in this series.


The split between physical and scheduling engine (i915_sched_engine) 
makes sense to me. Gut feeling says it should work for GuC as well, in 
principle.


A small comment or two below:

On 25/01/2021 14:01, Chris Wilson wrote:

Move the scheduling tasklists out of the execlists backend into the
per-engine scheduling bookkeeping.

Signed-off-by: Chris Wilson 
---
  drivers/gpu/drm/i915/gt/intel_engine.h| 14 
  drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++--
  drivers/gpu/drm/i915/gt/intel_engine_types.h  |  5 --
  .../drm/i915/gt/intel_execlists_submission.c  | 65 +--
  drivers/gpu/drm/i915/gt/intel_gt_irq.c|  2 +-
  drivers/gpu/drm/i915/gt/selftest_execlists.c  | 16 ++---
  drivers/gpu/drm/i915/gt/selftest_hangcheck.c  |  2 +-
  drivers/gpu/drm/i915/gt/selftest_lrc.c|  6 +-
  drivers/gpu/drm/i915/gt/selftest_reset.c  |  2 +-
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 ++---
  drivers/gpu/drm/i915/i915_scheduler.c | 14 ++--
  drivers/gpu/drm/i915/i915_scheduler.h | 20 ++
  drivers/gpu/drm/i915/i915_scheduler_types.h   |  6 ++
  .../gpu/drm/i915/selftests/i915_scheduler.c   | 16 ++---
  14 files changed, 99 insertions(+), 98 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h 
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 20974415e7d8..801ae54cf60d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -122,20 +122,6 @@ execlists_active(const struct intel_engine_execlists 
*execlists)
return active;
  }
  
-static inline void

-execlists_active_lock_bh(struct intel_engine_execlists *execlists)
-{
-   local_bh_disable(); /* prevent local softirq and lock recursion */
-   tasklet_lock(>tasklet);
-}
-
-static inline void
-execlists_active_unlock_bh(struct intel_engine_execlists *execlists)
-{
-   tasklet_unlock(>tasklet);
-   local_bh_enable(); /* restore softirq, and kick ksoftirqd! */
-}
-
  static inline u32
  intel_read_status_page(const struct intel_engine_cs *engine, int reg)
  {
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index ef225da35399..cdd07aeada05 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -902,7 +902,6 @@ int intel_engines_init(struct intel_gt *gt)
  void intel_engine_cleanup_common(struct intel_engine_cs *engine)
  {
i915_sched_fini_engine(>active);
-   tasklet_kill(>execlists.tasklet); /* flush the callback */
  
  	intel_breadcrumbs_free(engine->breadcrumbs);
  
@@ -1187,7 +1186,7 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
  
  void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync)

  {
-   struct tasklet_struct *t = >execlists.tasklet;
+   struct tasklet_struct *t = >active.tasklet;
  
  	if (!t->func)

return;
@@ -1454,8 +1453,8 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
  
  		drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",

   yesno(test_bit(TASKLET_STATE_SCHED,
- >execlists.tasklet.state)),
-  
enableddisabled(!atomic_read(>execlists.tasklet.count)),
+ >active.tasklet.state)),
+  
enableddisabled(!atomic_read(>active.tasklet.count)),
   repr_timer(>execlists.preempt),
   repr_timer(>execlists.timer));
  
@@ -1479,7 +1478,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,

   idx, hws[idx * 2], hws[idx * 2 + 1]);
}
  
-		execlists_active_lock_bh(execlists);

+   i915_sched_lock_bh(>active);
rcu_read_lock();
for (port = execlists->active; (rq = *port); port++) {
char hdr[160];
@@ -1510,7 +1509,7 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
i915_request_show(m, rq, hdr, 0);
}
rcu_read_unlock();
-   execlists_active_unlock_bh(execlists);
+   i915_sched_unlock_bh(>active);
} else if (INTEL_GEN(dev_priv) > 6) {
drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
   ENGINE_READ(engine, RING_PP_DIR_BASE));
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h 
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index c46d70b7e484..76d561c2c6aa 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -138,11 +138,6 @@ struct st_preempt_hang {
   * driver and the hardware state for execlist mode of submission.
   */
  struct 

[Intel-gfx] [PULL] drm-intel-next

[Rodrigo Vivi]

Hi Dave and Daniel,

Hopefully this is the last pull request towards 5.12.

Please notice this contains a drm/framebuffer change needed for
supporting clear color support for TGL Render Decompression.

Here goes drm-intel-next-2021-01-27:

- HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (Anshuman)
- Fix DP vswing settings and handling (Imre, Ville)
- Various display code clean-up (Jani, Ville)
- Various display refactoring, including split out of pps, aux, and fdi (Ja\
ni, Dave)
- Add DG1 missing workarounds (Jose)
- Fix display color conversion (Chris, Ville)
- Try to guess PCH type even without ISA bridge (Zhenyu)
- More backlight refactor (Lyude)
- Support two CSC module on gen11 and later (Lee)
- Async flips for all ilk+ platforms (Ville)
- Clear color support for TGL (RK)
- Add a helper to read data from a GEM object page (Imre)
- VRR/Adaptive Sync Enabling on DP/eDP for TGL+ (Manasi, Ville Aditya)

Thanks,
Rodrigo.

The following changes since commit fb5cfcaa2efbb4c71abb1dfbc8f4da727e0bfd89:

  Merge tag 'drm-intel-gt-next-2021-01-14' of 
git://anongit.freedesktop.org/drm/drm-intel into drm-next (2021-01-15 15:03:36 
+1000)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2021-01-27

for you to fetch changes up to 784953a46589276b38d7e6dcb5ebf7e29db72ff1:

  drm/i915/display/vrr: Skip the VRR HW state readout on DSI transcoder 
(2021-01-26 16:34:53 -0800)


- HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (Anshuman)
- Fix DP vswing settings and handling (Imre, Ville)
- Various display code clean-up (Jani, Ville)
- Various display refactoring, including split out of pps, aux, and fdi (Ja\
ni, Dave)
- Add DG1 missing workarounds (Jose)
- Fix display color conversion (Chris, Ville)
- Try to guess PCH type even without ISA bridge (Zhenyu)
- More backlight refactor (Lyude)
- Support two CSC module on gen11 and later (Lee)
- Async flips for all ilk+ platforms (Ville)
- Clear color support for TGL (RK)
- Add a helper to read data from a GEM object page (Imre)
- VRR/Adaptive Sync Enabling on DP/eDP for TGL+ (Manasi, Ville Aditya)


Aditya Swarup (1):
  drm/i915/display/dp: Attach and set drm connector VRR property

Anshuman Gupta (21):
  drm/i915/hdcp: Update CP property in update_pipe
  drm/i915/hdcp: Get conn while content_type changed
  drm/i915/hotplug: Handle CP_IRQ for DP-MST
  drm/i915/hdcp: No HDCP when encoder is't initialized
  drm/i915/hdcp: DP MST transcoder for link and stream
  drm/i915/hdcp: Move HDCP enc status timeout to header
  drm/i915/hdcp: HDCP stream encryption support
  drm/i915/hdcp: Configure HDCP1.4 MST steram encryption status
  drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
  drm/i915/hdcp: Pass dig_port to intel_hdcp_init
  drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
  misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
  drm/hdcp: Max MST content streams
  drm/i915/hdcp: MST streams support in hdcp port_data
  drm/i915/hdcp: Pass connector to check_2_2_link
  drm/i915/hdcp: Add HDCP 2.2 stream register
  drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
  drm/i915/hdcp: Configure HDCP2.2 MST steram encryption status
  drm/i915/hdcp: Enable HDCP 2.2 MST support
  drm/i915/hdcp: Fix WARN_ON(data->k > INTEL_NUM_PIPES)
  drm/i915/hdcp: Fix uninitialized symbol

Chris Wilson (1):
  drm/i915/display: Bitwise or the conversion colour specifier together

Dave Airlie (3):
  drm/i915: refactor some crtc code out of intel display. (v2)
  drm/i915: refactor pll code out into intel_dpll.c
  drm/i915: split fdi code out from intel_display.c

Imre Deak (3):
  drm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.c
  drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode
  drm/i915/gem: Add a helper to read data from a GEM object page

Jani Nikula (20):
  drm/i915/display: remove useless use of inline
  drm/i915/display: fix the uint*_t types that have crept in
  drm/i915/pps: abstract panel power sequencer from intel_dp.c
  drm/i915/pps: rename pps_{,un}lock -> intel_pps_{,un}lock
  drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_*
  drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
  drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked
  drm/i915/pps: abstract intel_pps_vdd_off_sync
  drm/i915/pps: add higher level intel_pps_init() call
  drm/i915/pps: abstract intel_pps_encoder_reset()
  drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked
  drm/i915/pps: rename intel_power_sequencer_reset to intel_pps_reset_all
  drm/i915/pps: add locked intel_pps_wait_power_cycle
  drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init
  

[Intel-gfx] [PATCH] drm/i915/gt: Drop active.lock around active request read inside execlists

[Chris Wilson]

As we find the active request for capturing upon a hang, we know that the
lists are stable as we are inside the execlists tasklet, the only path
that can modify those lists. As such, we do not need to disable irqs and
take the active lock for a simple read of the current request.

Suggested-by: Mika Kuoppala 
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index b5f2459cac2c..e20ab2eab3a8 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2262,13 +2262,11 @@ static void execlists_capture(struct intel_engine_cs 
*engine)
if (!cap)
return;
 
-   spin_lock_irq(>active.lock);
cap->rq = active_context(engine, active_ccid(engine));
if (cap->rq) {
cap->rq = active_request(cap->rq->context->timeline, cap->rq);
cap->rq = i915_request_get_rcu(cap->rq);
}
-   spin_unlock_irq(>active.lock);
if (!cap->rq)
goto err_free;
 
-- 
2.20.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/bios: tidy up child device debug logging

[Patchwork]

== Series Details ==

Series: drm/i915/bios: tidy up child device debug logging
URL   : https://patchwork.freedesktop.org/series/86341/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9687 -> Patchwork_19515


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/index.html

Known issues


  Here are the changes found in Patchwork_19515 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u:   NOTRUN -> [SKIP][1] ([fdo#109271]) +26 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html

  * igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u:   NOTRUN -> [WARN][2] ([i915#2283])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html

  * igt@fbdev@write:
- fi-tgl-y:   [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar 
issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-tgl-y/igt@fb...@write.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/fi-tgl-y/igt@fb...@write.html

  * igt@i915_pm_rpm@module-reload:
- fi-byt-j1900:   [PASS][5] -> [INCOMPLETE][6] ([i915#142] / 
[i915#2405])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-byt-j1900/igt@i915_pm_...@module-reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/fi-byt-j1900/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050:   [PASS][7] -> [DMESG-FAIL][8] ([i915#2675])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@hangcheck:
- fi-ivb-3770:[PASS][9] -> [INCOMPLETE][10] ([i915#2782])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u:   NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html

  * igt@prime_vgem@basic-userptr:
- fi-bxt-dsi: [PASS][12] -> [DMESG-WARN][13] ([i915#1610])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-bxt-dsi/igt@prime_v...@basic-userptr.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/fi-bxt-dsi/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- fi-bxt-dsi: NOTRUN -> [FAIL][14] ([i915#2426] / [i915#409])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/fi-bxt-dsi/igt@run...@aborted.html
- fi-byt-j1900:   NOTRUN -> [FAIL][15] ([i915#1814] / [i915#2505])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/fi-byt-j1900/igt@run...@aborted.html

  
 Possible fixes 

  * igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2:  [FAIL][16] ([i915#1161] / [i915#262]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html

  * igt@prime_vgem@basic-gtt:
- fi-tgl-y:   [DMESG-WARN][18] ([i915#402]) -> [PASS][19] +1 
similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9687/fi-tgl-y/igt@prime_v...@basic-gtt.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19515/fi-tgl-y/igt@prime_v...@basic-gtt.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
  [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
  [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#2268]: https://gitlab.freedesktop.org/drm/intel/issues/2268
  [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
  [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#2675]: