[Intel-gfx] [CI 2/3] drm/i915/gt: Move submission_method into intel_gt
Since we setup the submission method for the engines once, it is easy to
assign an enum and use that instead of probing into the backends.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h | 8 +++-
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 12
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 8
drivers/gpu/drm/i915/gt/intel_execlists_submission.h | 3 ---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +++
drivers/gpu/drm/i915/gt/intel_reset.c| 7 +++
drivers/gpu/drm/i915/gt/selftest_execlists.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c| 5 -
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h| 1 -
drivers/gpu/drm/i915/i915_perf.c | 10 +-
11 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 47ee8578e511..8d9184920c51 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -13,8 +13,9 @@
#include "i915_reg.h"
#include "i915_request.h"
#include "i915_selftest.h"
-#include "gt/intel_timeline.h"
#include "intel_engine_types.h"
+#include "intel_gt_types.h"
+#include "intel_timeline.h"
#include "intel_workarounds.h"
struct drm_printer;
@@ -262,6 +263,11 @@ void intel_engine_init_active(struct intel_engine_cs
*engine,
#define ENGINE_MOCK1
#define ENGINE_VIRTUAL 2
+static inline bool intel_engine_uses_guc(const struct intel_engine_cs *engine)
+{
+ return engine->gt->submission_method >= INTEL_SUBMISSION_GUC;
+}
+
static inline bool
intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 56fb9cece71b..dab8d734e272 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -891,12 +891,16 @@ int intel_engines_init(struct intel_gt *gt)
enum intel_engine_id id;
int err;
- if (intel_uc_uses_guc_submission(>->uc))
+ if (intel_uc_uses_guc_submission(>->uc)) {
+ gt->submission_method = INTEL_SUBMISSION_GUC;
setup = intel_guc_submission_setup;
- else if (HAS_EXECLISTS(gt->i915))
+ } else if (HAS_EXECLISTS(gt->i915)) {
+ gt->submission_method = INTEL_SUBMISSION_ELSP;
setup = intel_execlists_submission_setup;
- else
+ } else {
+ gt->submission_method = INTEL_SUBMISSION_RING;
setup = intel_ring_submission_setup;
+ }
for_each_engine(engine, gt, id) {
err = engine_setup_common(engine);
@@ -1467,7 +1471,7 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
}
- if (intel_engine_in_guc_submission_mode(engine)) {
+ if (intel_engine_uses_guc(engine)) {
/* nothing to print yet */
} else if (HAS_EXECLISTS(dev_priv)) {
struct i915_request * const *port, *rq;
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index c98fdeb94dba..8dc52cc43f27 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1757,7 +1757,6 @@ process_csb(struct intel_engine_cs *engine, struct
i915_request **inactive)
*/
GEM_BUG_ON(!tasklet_is_locked(&execlists->tasklet) &&
!reset_in_progress(execlists));
- GEM_BUG_ON(!intel_engine_in_execlists_submission_mode(engine));
/*
* Note that csb_write, csb_status may be either in HWSP or mmio.
@@ -3877,13 +3876,6 @@ void intel_execlists_show_requests(struct
intel_engine_cs *engine,
spin_unlock_irqrestore(&engine->active.lock, flags);
}
-bool
-intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine)
-{
- return engine->set_default_submission ==
- execlists_set_default_submission;
-}
-
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_execlists.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
index a8fd7adefd82..f7bd3fccfee8 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
@@ -41,7 +41,4 @@ int intel_virtual_engine_attach_bond(struct intel_engine_cs
*engine,
const struct intel_engine_cs *master,
const struct intel_engine_cs *sibling);
-bool
-intel_engine_in_execlists_submission_mode
[Intel-gfx] [CI 3/3] drm/i915/gt: Move CS interrupt handler to the backend
The different submission backends each have their own preferred
behaviour and interrupt setup. Let each handle their own interrupts.
This becomes more useful later as we to extract the use of auxiliary
state in the interrupt handler that is backend specific.
v2: An overabundance of caution is always justified; put a barrier on
updating the irq handler so that we know that the next interrupt will
be redirected towards ourselves.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +---
.../drm/i915/gt/intel_execlists_submission.c | 41 ++
drivers/gpu/drm/i915/gt/intel_gt_irq.c| 82 ++-
drivers/gpu/drm/i915/gt/intel_gt_irq.h| 23 ++
.../gpu/drm/i915/gt/intel_ring_submission.c | 8 ++
drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 ++-
drivers/gpu/drm/i915/i915_irq.c | 8 +-
9 files changed, 122 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index dab8d734e272..13ef5725ef51 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -255,6 +255,11 @@ static void intel_engine_sanitize_mmio(struct
intel_engine_cs *engine)
intel_engine_set_hwsp_writemask(engine, ~0u);
}
+static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir)
+{
+ GEM_DEBUG_WARN_ON(iir);
+}
+
static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
{
const struct engine_info *info = &intel_engines[id];
@@ -292,6 +297,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
engine->hw_id = info->hw_id;
engine->guc_id = MAKE_GUC_ID(info->class, info->instance);
+ engine->irq_handler = nop_irq_handler;
+
engine->class = info->class;
engine->instance = info->instance;
__sprint_engine_name(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 9d59de5c559a..c9974de2dd00 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -402,6 +402,7 @@ struct intel_engine_cs {
u32 irq_enable_mask; /* bitmask to enable ring interrupt */
void(*irq_enable)(struct intel_engine_cs *engine);
void(*irq_disable)(struct intel_engine_cs *engine);
+ void(*irq_handler)(struct intel_engine_cs *engine, u16 iir);
void(*sanitize)(struct intel_engine_cs *engine);
int (*resume)(struct intel_engine_cs *engine);
@@ -481,10 +482,9 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_PREEMPTION BIT(2)
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
#define I915_ENGINE_HAS_TIMESLICES BIT(4)
-#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5)
-#define I915_ENGINE_IS_VIRTUAL BIT(6)
-#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)
-#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)
+#define I915_ENGINE_IS_VIRTUAL BIT(5)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
+#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
unsigned int flags;
/*
@@ -588,12 +588,6 @@ intel_engine_has_timeslices(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_HAS_TIMESLICES;
}
-static inline bool
-intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
-{
- return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
-}
-
static inline bool
intel_engine_is_virtual(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 8dc52cc43f27..554eaaa268a7 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -118,6 +118,7 @@
#include "intel_engine_stats.h"
#include "intel_execlists_submission.h"
#include "intel_gt.h"
+#include "intel_gt_irq.h"
#include "intel_gt_pm.h"
#include "intel_gt_requests.h"
#include "intel_lrc.h"
@@ -2394,6 +2395,45 @@ static void execlists_submission_tasklet(struct
tasklet_struct *t)
rcu_read_unlock();
}
+static void execlists_irq_handler(struct intel_engine_cs *engine, u16 iir)
+{
+ bool tasklet = false;
+
+ if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
+ u32 eir;
+
+ /* Upper 16b are the enabling mask, rsvd for internal errors */
+ eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0);
+ ENGINE_TRACE(engine, "CS error: %x\n", eir);
+
+ /* Disable the error interrupt until after the reset */
+ if (likely(eir)) {
+ ENGINE_WRITE(engine,
[Intel-gfx] [CI 1/3] drm/i915/gt: Move engine setup out of set_default_submission
Now that we no longer switch back and forth between guc and execlists,
we no longer need to restore the backend's vfunc and can leave them set
after initialisation. The only catch is that we lose the submission on
wedging and still need to reset the submit_request vfunc on unwedging.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 46 -
.../gpu/drm/i915/gt/intel_ring_submission.c | 4 --
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 50 ---
3 files changed, 44 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index b8bd3d48b345..c98fdeb94dba 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3069,29 +3069,6 @@ static void execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->submit_request = execlists_submit_request;
engine->schedule = i915_schedule;
engine->execlists.tasklet.callback = execlists_submission_tasklet;
-
- engine->reset.prepare = execlists_reset_prepare;
- engine->reset.rewind = execlists_reset_rewind;
- engine->reset.cancel = execlists_reset_cancel;
- engine->reset.finish = execlists_reset_finish;
-
- engine->park = execlists_park;
- engine->unpark = NULL;
-
- engine->flags |= I915_ENGINE_SUPPORTS_STATS;
- if (!intel_vgpu_active(engine->i915)) {
- engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
- if (can_preempt(engine)) {
- engine->flags |= I915_ENGINE_HAS_PREEMPTION;
- if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
- engine->flags |= I915_ENGINE_HAS_TIMESLICES;
- }
- }
-
- if (intel_engine_has_preemption(engine))
- engine->emit_bb_start = gen8_emit_bb_start;
- else
- engine->emit_bb_start = gen8_emit_bb_start_noarb;
}
static void execlists_shutdown(struct intel_engine_cs *engine)
@@ -3122,6 +3099,14 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
engine->cops = &execlists_context_ops;
engine->request_alloc = execlists_request_alloc;
+ engine->reset.prepare = execlists_reset_prepare;
+ engine->reset.rewind = execlists_reset_rewind;
+ engine->reset.cancel = execlists_reset_cancel;
+ engine->reset.finish = execlists_reset_finish;
+
+ engine->park = execlists_park;
+ engine->unpark = NULL;
+
engine->emit_flush = gen8_emit_flush_xcs;
engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
@@ -3142,6 +3127,21 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
* until a more refined solution exists.
*/
}
+
+ engine->flags |= I915_ENGINE_SUPPORTS_STATS;
+ if (!intel_vgpu_active(engine->i915)) {
+ engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
+ if (can_preempt(engine)) {
+ engine->flags |= I915_ENGINE_HAS_PREEMPTION;
+ if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
+ engine->flags |= I915_ENGINE_HAS_TIMESLICES;
+ }
+ }
+
+ if (intel_engine_has_preemption(engine))
+ engine->emit_bb_start = gen8_emit_bb_start;
+ else
+ engine->emit_bb_start = gen8_emit_bb_start_noarb;
}
static void logical_ring_default_irqs(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 9c2c605d7a92..3cb2ce503544 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -969,14 +969,10 @@ static void gen6_bsd_submit_request(struct i915_request
*request)
static void i9xx_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = i9xx_submit_request;
-
- engine->park = NULL;
- engine->unpark = NULL;
}
static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
{
- i9xx_set_default_submission(engine);
engine->submit_request = gen6_bsd_submit_request;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 92688a9b6717..f72faa0b8339 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -608,35 +608,6 @@ static int guc_resume(struct intel_engine_cs *engine)
static void guc_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = guc_submit_request;
- engine->schedule = i915_schedule;
- engine->execl
[Intel-gfx] ✓ Fi.CI.IGT: success for Oops with "ALSA: jack: implement software jack injection via debugfs"
== Series Details ==
Series: Oops with "ALSA: jack: implement software jack injection via debugfs"
URL : https://patchwork.freedesktop.org/series/86597/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9719_full -> Patchwork_19565_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19565_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@sysfs_clients@fair-1@vcs}:
- shard-kbl: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/shard-kbl1/igt@sysfs_clients@fai...@vcs.html
* {igt@sysfs_clients@recycle-many}:
- shard-tglb: [PASS][2] -> [FAIL][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9719/shard-tglb6/igt@sysfs_clie...@recycle-many.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/shard-tglb5/igt@sysfs_clie...@recycle-many.html
Known issues
Here are the changes found in Patchwork_19565_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +5 similar
issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9719/shard-kbl6/igt@gem_ctx_isolation@preservation...@vcs0.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/shard-kbl7/igt@gem_ctx_isolation@preservation...@vcs0.html
* igt@gem_ctx_param@set-priority-not-supported:
- shard-tglb: NOTRUN -> [SKIP][6] ([fdo#109314])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/shard-tglb8/igt@gem_ctx_pa...@set-priority-not-supported.html
- shard-iclb: NOTRUN -> [SKIP][7] ([fdo#109314])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/shard-iclb3/igt@gem_ctx_pa...@set-priority-not-supported.html
* igt@gem_ctx_persistence@close-replace-race:
- shard-glk: [PASS][8] -> [TIMEOUT][9] ([i915#2918])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9719/shard-glk9/igt@gem_ctx_persiste...@close-replace-race.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/shard-glk1/igt@gem_ctx_persiste...@close-replace-race.html
* igt@gem_exec_capture@pi@vcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][10] ([i915#2295])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/shard-skl2/igt@gem_exec_capture@p...@vcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-apl: [PASS][11] -> [SKIP][12] ([fdo#109271])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9719/shard-apl1/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/shard-apl2/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][13] ([i915#2842])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842]) +1 similar
issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9719/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842]) +1 similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-apl: [PASS][17] -> [FAIL][18] ([i915#2389])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9719/shard-apl1/igt@gem_exec_reloc@basic-many-act...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/shard-apl2/igt@gem_exec_reloc@basic-many-act...@rcs0.html
* igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][19] ([i915#2389])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/shard-iclb1/igt@gem_exec_reloc@basic-wide-act...@vcs1.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-tglb: [PASS][20] -> [DMESG-WARN][21] ([i915#2803])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9719/shard-tglb8/igt@gem_exec_schedule@u-fairsl...@rcs0.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/shard-tglb3/igt@gem_exec_schedule@u-fairsl...@rcs0.html
- shard-skl: NOTRUN -> [DMESG-WARN][22] ([i915#2803])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/shard-skl9/igt@g
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Remove notion of GEM from i915_gem_shrinker_taints_mutex
== Series Details ==
Series: drm/i915: Remove notion of GEM from i915_gem_shrinker_taints_mutex
URL : https://patchwork.freedesktop.org/series/86586/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9718_full -> Patchwork_19560_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19560_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@sysfs_clients@recycle-many}:
- shard-iclb: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9718/shard-iclb5/igt@sysfs_clie...@recycle-many.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/shard-iclb4/igt@sysfs_clie...@recycle-many.html
- shard-glk: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9718/shard-glk6/igt@sysfs_clie...@recycle-many.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/shard-glk2/igt@sysfs_clie...@recycle-many.html
Known issues
Here are the changes found in Patchwork_19560_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@psr2:
- shard-iclb: NOTRUN -> [SKIP][5] ([i915#658])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/shard-iclb7/igt@feature_discov...@psr2.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [PASS][6] -> [DMESG-WARN][7] ([i915#180]) +6 similar
issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9718/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/shard-kbl2/igt@gem_ctx_isolation@preservation...@vcs0.html
* igt@gem_exec_create@madvise:
- shard-glk: [PASS][8] -> [DMESG-WARN][9] ([i915#118] / [i915#95])
+2 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9718/shard-glk6/igt@gem_exec_cre...@madvise.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/shard-glk2/igt@gem_exec_cre...@madvise.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9718/shard-kbl2/igt@gem_exec_fair@basic-n...@vecs0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/shard-kbl1/igt@gem_exec_fair@basic-n...@vecs0.html
- shard-apl: [PASS][12] -> [FAIL][13] ([i915#2842])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9718/shard-apl7/igt@gem_exec_fair@basic-n...@vecs0.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/shard-apl2/igt@gem_exec_fair@basic-n...@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842]) +1 similar
issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9718/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
- shard-glk: [PASS][16] -> [FAIL][17] ([i915#2842]) +1 similar
issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9718/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [PASS][18] -> [FAIL][19] ([i915#2842])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9718/shard-iclb2/igt@gem_exec_fair@basic-p...@vecs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/shard-iclb8/igt@gem_exec_fair@basic-p...@vecs0.html
* igt@gem_exec_reloc@basic-many-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][20] ([i915#2389])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/shard-iclb2/igt@gem_exec_reloc@basic-many-act...@vcs1.html
* igt@gem_exec_schedule@u-fairslice@vecs0:
- shard-skl: NOTRUN -> [DMESG-WARN][21] ([i915#1610] / [i915#2803])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/shard-skl3/igt@gem_exec_schedule@u-fairsl...@vecs0.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#2190])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/shard-kbl2/igt@gem_huc_c...@huc-copy.html
* igt@gem_softpin@noreloc-s3:
- shard-kbl: NOTRUN -> [DMESG-WARN][23] ([i915#180])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/shard-kbl2/igt@gem_soft...@noreloc-s3.html
* igt@gem_userptr_blits@process-exit-mmap-busy@uc:
- shard-skl: NOTRUN -
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,01/13] Oops with "ALSA: jack: implement software jack injection via debugfs"
== Series Details == Series: series starting with [CI,01/13] Oops with "ALSA: jack: implement software jack injection via debugfs" URL : https://patchwork.freedesktop.org/series/86599/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9719 -> Patchwork_19566 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19566 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19566, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/index.html New tests - New tests have been introduced between CI_DRM_9719 and Patchwork_19566: ### New IGT tests (1) ### * igt@i915_selftest@live@scheduler: - Statuses : 18 pass(s) - Exec time: [0.52, 7.17] s Known issues Here are the changes found in Patchwork_19566 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-elk-e7500: NOTRUN -> [SKIP][1] ([fdo#109271]) +18 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-elk-e7500/igt@amdgpu/amd_ba...@cs-compute.html * igt@amdgpu/amd_basic@cs-gfx: - fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#109315]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_basic@cs-sdma: - fi-cfl-8109u: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-cfl-8109u/igt@amdgpu/amd_ba...@cs-sdma.html * igt@amdgpu/amd_basic@semaphore: - fi-icl-y: NOTRUN -> [SKIP][4] ([fdo#109315]) +17 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-icl-y/igt@amdgpu/amd_ba...@semaphore.html - fi-bdw-5557u: NOTRUN -> [SKIP][5] ([fdo#109271]) +17 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@amdgpu/amd_basic@userptr: - fi-byt-j1900: NOTRUN -> [SKIP][6] ([fdo#109271]) +17 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-byt-j1900/igt@amdgpu/amd_ba...@userptr.html * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-tgl-u2: NOTRUN -> [SKIP][7] ([fdo#109315] / [i915#2575]) +17 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-tgl-u2/igt@amdgpu/amd_cs_...@fork-compute0.html - fi-ivb-3770:NOTRUN -> [SKIP][8] ([fdo#109271]) +18 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-ivb-3770/igt@amdgpu/amd_cs_...@fork-compute0.html * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][9] ([fdo#109315]) +17 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@amdgpu/amd_cs_nop@nop-compute0: - fi-ilk-650: NOTRUN -> [SKIP][10] ([fdo#109271]) +18 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-ilk-650/igt@amdgpu/amd_cs_...@nop-compute0.html * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600:NOTRUN -> [SKIP][11] ([fdo#109271]) +18 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html * igt@amdgpu/amd_prime@amd-to-i915: - fi-pnv-d510:NOTRUN -> [SKIP][12] ([fdo#109271]) +18 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-pnv-d510/igt@amdgpu/amd_pr...@amd-to-i915.html * igt@amdgpu/amd_prime@i915-to-amd: - fi-snb-2520m: NOTRUN -> [SKIP][13] ([fdo#109271]) +18 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html * igt@debugfs_test@read_all_entries: - fi-tgl-y: [PASS][14] -> [DMESG-WARN][15] ([i915#402]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9719/fi-tgl-y/igt@debugfs_test@read_all_entries.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@i915_selftest@live@gt_lrc: - fi-tgl-y: NOTRUN -> [DMESG-FAIL][16] ([i915#2373]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-tgl-y/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@gt_pm: - fi-tgl-y: NOTRUN -> [DMESG-FAIL][17] ([i915#1759]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19566/fi-tgl-y/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,01/13] Oops with "ALSA: jack: implement software jack injection via debugfs"
== Series Details == Series: series starting with [CI,01/13] Oops with "ALSA: jack: implement software jack injection via debugfs" URL : https://patchwork.freedesktop.org/series/86599/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/13] Oops with "ALSA: jack: implement software jack injection via debugfs"
== Series Details ==
Series: series starting with [CI,01/13] Oops with "ALSA: jack: implement
software jack injection via debugfs"
URL : https://patchwork.freedesktop.org/series/86599/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
27bd3e4245a9 Oops with "ALSA: jack: implement software jack injection via
debugfs"
-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 2d670ea2bd53 ("ALSA: jack:
implement software jack injection via debugfs")'
#10:
> commit 2d670ea2bd53 ("ALSA: jack: implement software jack injection via
-:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#14:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9715/fi-skl-6700k2/pstore0-1612277467_Oops_1.txt
total: 1 errors, 1 warnings, 0 checks, 21 lines checked
bd2be6353af9 drm/i915/gt: Move engine setup out of set_default_submission
922e205e6eec drm/i915/gt: Move submission_method into intel_gt
0e2a6bc1a95a drm/i915/gt: Move CS interrupt handler to the backend
31b32cb0f63b drm/i915: Replace engine->schedule() with a known request operation
043b1f700b88 drm/i915: Restructure priority inheritance
be807a2e516f drm/i915/selftests: Measure set-priority duration
-:53: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#53:
new file mode 100644
-:429: WARNING:LINE_SPACING: Missing a blank line after declarations
#429: FILE: drivers/gpu/drm/i915/selftests/i915_scheduler.c:372:
+ struct igt_spinner spin;
+ I915_RND_STATE(prng);
total: 0 errors, 2 warnings, 0 checks, 695 lines checked
fc01456ae916 drm/i915/selftests: Exercise priority inheritance around an engine
loop
fc7cad69ff29 drm/i915: Improve DFS for priority inheritance
688a50d52142 drm/i915: Extract request submission from execlists
dcccee656424 drm/i915: Extract request rewinding from execlists
21ffbbe398b2 drm/i915: Extract request suspension from the execlists
2d43a2f45c8c drm/i915: Extract the ability to defer and rerun a request later
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[Intel-gfx] ✓ Fi.CI.BAT: success for Oops with "ALSA: jack: implement software jack injection via debugfs"
== Series Details == Series: Oops with "ALSA: jack: implement software jack injection via debugfs" URL : https://patchwork.freedesktop.org/series/86597/ State : success == Summary == CI Bug Log - changes from CI_DRM_9719 -> Patchwork_19565 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/index.html Known issues Here are the changes found in Patchwork_19565 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-cfl-guc: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-cfl-guc/igt@amdgpu/amd_ba...@cs-compute.html - fi-skl-guc: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-skl-guc/igt@amdgpu/amd_ba...@cs-compute.html - fi-elk-e7500: NOTRUN -> [SKIP][3] ([fdo#109271]) +18 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-elk-e7500/igt@amdgpu/amd_ba...@cs-compute.html * igt@amdgpu/amd_basic@cs-gfx: - fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#109315]) +17 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html - fi-skl-6700k2: NOTRUN -> [SKIP][5] ([fdo#109271]) +17 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-skl-6700k2/igt@amdgpu/amd_ba...@cs-gfx.html - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271]) +17 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_basic@cs-sdma: - fi-kbl-guc: NOTRUN -> [SKIP][7] ([fdo#109271]) +17 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-kbl-guc/igt@amdgpu/amd_ba...@cs-sdma.html - fi-cfl-8109u: NOTRUN -> [SKIP][8] ([fdo#109271]) +17 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-cfl-8109u/igt@amdgpu/amd_ba...@cs-sdma.html - fi-kbl-7500u: NOTRUN -> [SKIP][9] ([fdo#109271]) +17 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-kbl-7500u/igt@amdgpu/amd_ba...@cs-sdma.html * igt@amdgpu/amd_basic@memory-alloc: - fi-cml-u2: NOTRUN -> [SKIP][10] ([fdo#109315]) +17 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> [SKIP][11] ([fdo#109271]) +17 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html - fi-glk-dsi: NOTRUN -> [SKIP][12] ([fdo#109271]) +17 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-glk-dsi/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_basic@semaphore: - fi-icl-y: NOTRUN -> [SKIP][13] ([fdo#109315]) +17 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-icl-y/igt@amdgpu/amd_ba...@semaphore.html - fi-bsw-nick:NOTRUN -> [SKIP][14] ([fdo#109271]) +17 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html - fi-bdw-5557u: NOTRUN -> [SKIP][15] ([fdo#109271]) +17 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@amdgpu/amd_basic@userptr: - fi-bxt-dsi: NOTRUN -> [SKIP][16] ([fdo#109271]) +17 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-bxt-dsi/igt@amdgpu/amd_ba...@userptr.html - fi-byt-j1900: NOTRUN -> [SKIP][17] ([fdo#109271]) +17 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-byt-j1900/igt@amdgpu/amd_ba...@userptr.html * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-tgl-u2: NOTRUN -> [SKIP][18] ([fdo#109315] / [i915#2575]) +17 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-tgl-u2/igt@amdgpu/amd_cs_...@fork-compute0.html - fi-ivb-3770:NOTRUN -> [SKIP][19] ([fdo#109271]) +18 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-ivb-3770/igt@amdgpu/amd_cs_...@fork-compute0.html * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][20] ([fdo#109315]) +17 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19565/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@amdgpu/amd_cs_nop@nop-compute0: - fi-ilk-650: NOTRUN -> [SKIP][21] ([fdo#109271]) +18 similar issues [21]: https://inte
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Oops with "ALSA: jack: implement software jack injection via debugfs"
== Series Details ==
Series: Oops with "ALSA: jack: implement software jack injection via debugfs"
URL : https://patchwork.freedesktop.org/series/86597/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
05f71ab54209 Oops with "ALSA: jack: implement software jack injection via
debugfs"
-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 2d670ea2bd53 ("ALSA: jack:
implement software jack injection via debugfs")'
#10:
> commit 2d670ea2bd53 ("ALSA: jack: implement software jack injection via
-:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#14:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9715/fi-skl-6700k2/pstore0-1612277467_Oops_1.txt
total: 1 errors, 1 warnings, 0 checks, 21 lines checked
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[Intel-gfx] [CI 01/13] Oops with "ALSA: jack: implement software jack injection via debugfs"
From: Takashi Iwai
On Tue, 02 Feb 2021 17:30:36 +0100,
Chris Wilson wrote:
>
> commit 2d670ea2bd53 ("ALSA: jack: implement software jack injection via
> debugfs") is causing issues for our CI as we see a use-after-free on
> module unload (on all machines):
>
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9715/fi-skl-6700k2/pstore0-1612277467_Oops_1.txt
Could you try the patch below? The unload test was completely
forgotten.
thanks,
Takashi
-- 8< --
From: Takashi Iwai
Subject: [PATCH] ALSA: core: Fix the debugfs removal at snd_card_free()
The debugfs_remove() call should have been done at the right place
before the card object gets freed.
Fixes: 2d670ea2bd53 ("ALSA: jack: implement software jack injection via
debugfs")
Signed-off-by: Takashi Iwai
---
sound/core/init.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/sound/core/init.c b/sound/core/init.c
index d4e78b176793..84b573e9c1f9 100644
--- a/sound/core/init.c
+++ b/sound/core/init.c
@@ -487,6 +487,10 @@ static int snd_card_do_free(struct snd_card *card)
dev_warn(card->dev, "unable to free card info\n");
/* Not fatal error */
}
+#ifdef CONFIG_SND_DEBUG
+ debugfs_remove(card->debugfs_root);
+ card->debugfs_root = NULL;
+#endif
if (card->release_completion)
complete(card->release_completion);
kfree(card);
@@ -537,11 +541,6 @@ int snd_card_free(struct snd_card *card)
/* wait, until all devices are ready for the free operation */
wait_for_completion(&released);
-#ifdef CONFIG_SND_DEBUG
- debugfs_remove(card->debugfs_root);
- card->debugfs_root = NULL;
-#endif
-
return 0;
}
EXPORT_SYMBOL(snd_card_free);
--
2.20.1
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[Intel-gfx] [CI 04/13] drm/i915/gt: Move CS interrupt handler to the backend
The different submission backends each have their own preferred
behaviour and interrupt setup. Let each handle their own interrupts.
This becomes more useful later as we to extract the use of auxiliary
state in the interrupt handler that is backend specific.
v2: An overabundance of caution is always justified; put a barrier on
updating the irq handler so that we know that the next interrupt will
be redirected towards ourselves.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +---
.../drm/i915/gt/intel_execlists_submission.c | 41 ++
drivers/gpu/drm/i915/gt/intel_gt_irq.c| 82 ++-
drivers/gpu/drm/i915/gt/intel_gt_irq.h| 22 +
.../gpu/drm/i915/gt/intel_ring_submission.c | 8 ++
drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 ++-
drivers/gpu/drm/i915/i915_irq.c | 8 +-
9 files changed, 121 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index dab8d734e272..2a453ba5f25a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -255,6 +255,11 @@ static void intel_engine_sanitize_mmio(struct
intel_engine_cs *engine)
intel_engine_set_hwsp_writemask(engine, ~0u);
}
+static void nop_irq_handler(struct intel_engine_cs *engine, u32 iir)
+{
+ GEM_DEBUG_WARN_ON(iir);
+}
+
static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
{
const struct engine_info *info = &intel_engines[id];
@@ -292,6 +297,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
engine->hw_id = info->hw_id;
engine->guc_id = MAKE_GUC_ID(info->class, info->instance);
+ engine->irq_handler = nop_irq_handler;
+
engine->class = info->class;
engine->instance = info->instance;
__sprint_engine_name(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 9d59de5c559a..7fd035d45263 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -402,6 +402,7 @@ struct intel_engine_cs {
u32 irq_enable_mask; /* bitmask to enable ring interrupt */
void(*irq_enable)(struct intel_engine_cs *engine);
void(*irq_disable)(struct intel_engine_cs *engine);
+ void(*irq_handler)(struct intel_engine_cs *engine, u32 iir);
void(*sanitize)(struct intel_engine_cs *engine);
int (*resume)(struct intel_engine_cs *engine);
@@ -481,10 +482,9 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_PREEMPTION BIT(2)
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
#define I915_ENGINE_HAS_TIMESLICES BIT(4)
-#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5)
-#define I915_ENGINE_IS_VIRTUAL BIT(6)
-#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)
-#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)
+#define I915_ENGINE_IS_VIRTUAL BIT(5)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
+#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
unsigned int flags;
/*
@@ -588,12 +588,6 @@ intel_engine_has_timeslices(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_HAS_TIMESLICES;
}
-static inline bool
-intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
-{
- return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
-}
-
static inline bool
intel_engine_is_virtual(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 8dc52cc43f27..d69108b45377 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -118,6 +118,7 @@
#include "intel_engine_stats.h"
#include "intel_execlists_submission.h"
#include "intel_gt.h"
+#include "intel_gt_irq.h"
#include "intel_gt_pm.h"
#include "intel_gt_requests.h"
#include "intel_lrc.h"
@@ -2394,6 +2395,45 @@ static void execlists_submission_tasklet(struct
tasklet_struct *t)
rcu_read_unlock();
}
+static void execlists_irq_handler(struct intel_engine_cs *engine, u32 iir)
+{
+ bool tasklet = false;
+
+ if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
+ u32 eir;
+
+ /* Upper 16b are the enabling mask, rsvd for internal errors */
+ eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0);
+ ENGINE_TRACE(engine, "CS error: %x\n", eir);
+
+ /* Disable the error interrupt until after the reset */
+ if (likely(eir)) {
+ ENGINE_WRITE(engine, R
[Intel-gfx] [CI 10/13] drm/i915: Extract request submission from execlists
In the process of preparing to reuse the request submission logic for
other backends, lift it out of the execlists backend. It already
operates on the common structs, so just a matter of moving and renaming.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 55 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 30 +--
drivers/gpu/drm/i915/i915_scheduler.c | 82 +++
drivers/gpu/drm/i915/i915_scheduler.h | 2 +
4 files changed, 86 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index b4317ba20e77..787a029f5975 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2453,59 +2453,6 @@ static void execlists_preempt(struct timer_list *timer)
execlists_kick(timer, preempt);
}
-static void queue_request(struct intel_engine_cs *engine,
- struct i915_request *rq)
-{
- GEM_BUG_ON(!list_empty(&rq->sched.link));
- list_add_tail(&rq->sched.link,
- i915_sched_lookup_priolist(engine, rq_prio(rq)));
- set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
-}
-
-static bool submit_queue(struct intel_engine_cs *engine,
-const struct i915_request *rq)
-{
- struct intel_engine_execlists *execlists = &engine->execlists;
-
- if (rq_prio(rq) <= execlists->queue_priority_hint)
- return false;
-
- execlists->queue_priority_hint = rq_prio(rq);
- return true;
-}
-
-static bool ancestor_on_hold(const struct intel_engine_cs *engine,
-const struct i915_request *rq)
-{
- GEM_BUG_ON(i915_request_on_hold(rq));
- return !list_empty(&engine->active.hold) && hold_request(rq);
-}
-
-static void execlists_submit_request(struct i915_request *request)
-{
- struct intel_engine_cs *engine = request->engine;
- unsigned long flags;
-
- /* Will be called from irq-context when using foreign fences. */
- spin_lock_irqsave(&engine->active.lock, flags);
-
- if (unlikely(ancestor_on_hold(engine, request))) {
- RQ_TRACE(request, "ancestor on hold\n");
- list_add_tail(&request->sched.link, &engine->active.hold);
- i915_request_set_hold(request);
- } else {
- queue_request(engine, request);
-
- GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
- GEM_BUG_ON(list_empty(&request->sched.link));
-
- if (submit_queue(engine, request))
- __execlists_kick(&engine->execlists);
- }
-
- spin_unlock_irqrestore(&engine->active.lock, flags);
-}
-
static int execlists_context_pre_pin(struct intel_context *ce,
struct i915_gem_ww_ctx *ww,
void **vaddr)
@@ -3105,7 +3052,7 @@ static bool can_preempt(struct intel_engine_cs *engine)
static void execlists_set_default_submission(struct intel_engine_cs *engine)
{
- engine->submit_request = execlists_submit_request;
+ engine->submit_request = i915_request_enqueue;
engine->execlists.tasklet.callback = execlists_submission_tasklet;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 029e1719ca29..b549e87d05cf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -520,34 +520,6 @@ static int guc_request_alloc(struct i915_request *request)
return 0;
}
-static inline void queue_request(struct intel_engine_cs *engine,
-struct i915_request *rq,
-int prio)
-{
- GEM_BUG_ON(!list_empty(&rq->sched.link));
- list_add_tail(&rq->sched.link,
- i915_sched_lookup_priolist(engine, prio));
- set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
-}
-
-static void guc_submit_request(struct i915_request *rq)
-{
- struct intel_engine_cs *engine = rq->engine;
- unsigned long flags;
-
- /* Will be called from irq-context when using foreign fences. */
- spin_lock_irqsave(&engine->active.lock, flags);
-
- queue_request(engine, rq, rq_prio(rq));
-
- GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
- GEM_BUG_ON(list_empty(&rq->sched.link));
-
- tasklet_hi_schedule(&engine->execlists.tasklet);
-
- spin_unlock_irqrestore(&engine->active.lock, flags);
-}
-
static void sanitize_hwsp(struct intel_engine_cs *engine)
{
struct intel_timeline *tl;
@@ -616,7 +588,7 @@ static int guc_resume(struct intel_engine_cs *engine)
static void guc_set_default_submission(struct intel_engine_cs *engine)
{
- engine->submit_requ
[Intel-gfx] [CI 02/13] drm/i915/gt: Move engine setup out of set_default_submission
Now that we no longer switch back and forth between guc and execlists,
we no longer need to restore the backend's vfunc and can leave them set
after initialisation. The only catch is that we lose the submission on
wedging and still need to reset the submit_request vfunc on unwedging.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 46 -
.../gpu/drm/i915/gt/intel_ring_submission.c | 4 --
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 50 ---
3 files changed, 44 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index b8bd3d48b345..c98fdeb94dba 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3069,29 +3069,6 @@ static void execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->submit_request = execlists_submit_request;
engine->schedule = i915_schedule;
engine->execlists.tasklet.callback = execlists_submission_tasklet;
-
- engine->reset.prepare = execlists_reset_prepare;
- engine->reset.rewind = execlists_reset_rewind;
- engine->reset.cancel = execlists_reset_cancel;
- engine->reset.finish = execlists_reset_finish;
-
- engine->park = execlists_park;
- engine->unpark = NULL;
-
- engine->flags |= I915_ENGINE_SUPPORTS_STATS;
- if (!intel_vgpu_active(engine->i915)) {
- engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
- if (can_preempt(engine)) {
- engine->flags |= I915_ENGINE_HAS_PREEMPTION;
- if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
- engine->flags |= I915_ENGINE_HAS_TIMESLICES;
- }
- }
-
- if (intel_engine_has_preemption(engine))
- engine->emit_bb_start = gen8_emit_bb_start;
- else
- engine->emit_bb_start = gen8_emit_bb_start_noarb;
}
static void execlists_shutdown(struct intel_engine_cs *engine)
@@ -3122,6 +3099,14 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
engine->cops = &execlists_context_ops;
engine->request_alloc = execlists_request_alloc;
+ engine->reset.prepare = execlists_reset_prepare;
+ engine->reset.rewind = execlists_reset_rewind;
+ engine->reset.cancel = execlists_reset_cancel;
+ engine->reset.finish = execlists_reset_finish;
+
+ engine->park = execlists_park;
+ engine->unpark = NULL;
+
engine->emit_flush = gen8_emit_flush_xcs;
engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
@@ -3142,6 +3127,21 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
* until a more refined solution exists.
*/
}
+
+ engine->flags |= I915_ENGINE_SUPPORTS_STATS;
+ if (!intel_vgpu_active(engine->i915)) {
+ engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
+ if (can_preempt(engine)) {
+ engine->flags |= I915_ENGINE_HAS_PREEMPTION;
+ if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
+ engine->flags |= I915_ENGINE_HAS_TIMESLICES;
+ }
+ }
+
+ if (intel_engine_has_preemption(engine))
+ engine->emit_bb_start = gen8_emit_bb_start;
+ else
+ engine->emit_bb_start = gen8_emit_bb_start_noarb;
}
static void logical_ring_default_irqs(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 9c2c605d7a92..3cb2ce503544 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -969,14 +969,10 @@ static void gen6_bsd_submit_request(struct i915_request
*request)
static void i9xx_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = i9xx_submit_request;
-
- engine->park = NULL;
- engine->unpark = NULL;
}
static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
{
- i9xx_set_default_submission(engine);
engine->submit_request = gen6_bsd_submit_request;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 92688a9b6717..f72faa0b8339 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -608,35 +608,6 @@ static int guc_resume(struct intel_engine_cs *engine)
static void guc_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = guc_submit_request;
- engine->schedule = i915_schedule;
- engine->execl
[Intel-gfx] [CI 03/13] drm/i915/gt: Move submission_method into intel_gt
Since we setup the submission method for the engines once, it is easy to
assign an enum and use that instead of probing into the backends.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h | 8 +++-
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 12
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 8
drivers/gpu/drm/i915/gt/intel_execlists_submission.h | 3 ---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +++
drivers/gpu/drm/i915/gt/intel_reset.c| 7 +++
drivers/gpu/drm/i915/gt/selftest_execlists.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c| 5 -
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h| 1 -
drivers/gpu/drm/i915/i915_perf.c | 10 +-
11 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 47ee8578e511..8d9184920c51 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -13,8 +13,9 @@
#include "i915_reg.h"
#include "i915_request.h"
#include "i915_selftest.h"
-#include "gt/intel_timeline.h"
#include "intel_engine_types.h"
+#include "intel_gt_types.h"
+#include "intel_timeline.h"
#include "intel_workarounds.h"
struct drm_printer;
@@ -262,6 +263,11 @@ void intel_engine_init_active(struct intel_engine_cs
*engine,
#define ENGINE_MOCK1
#define ENGINE_VIRTUAL 2
+static inline bool intel_engine_uses_guc(const struct intel_engine_cs *engine)
+{
+ return engine->gt->submission_method >= INTEL_SUBMISSION_GUC;
+}
+
static inline bool
intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 56fb9cece71b..dab8d734e272 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -891,12 +891,16 @@ int intel_engines_init(struct intel_gt *gt)
enum intel_engine_id id;
int err;
- if (intel_uc_uses_guc_submission(>->uc))
+ if (intel_uc_uses_guc_submission(>->uc)) {
+ gt->submission_method = INTEL_SUBMISSION_GUC;
setup = intel_guc_submission_setup;
- else if (HAS_EXECLISTS(gt->i915))
+ } else if (HAS_EXECLISTS(gt->i915)) {
+ gt->submission_method = INTEL_SUBMISSION_ELSP;
setup = intel_execlists_submission_setup;
- else
+ } else {
+ gt->submission_method = INTEL_SUBMISSION_RING;
setup = intel_ring_submission_setup;
+ }
for_each_engine(engine, gt, id) {
err = engine_setup_common(engine);
@@ -1467,7 +1471,7 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
}
- if (intel_engine_in_guc_submission_mode(engine)) {
+ if (intel_engine_uses_guc(engine)) {
/* nothing to print yet */
} else if (HAS_EXECLISTS(dev_priv)) {
struct i915_request * const *port, *rq;
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index c98fdeb94dba..8dc52cc43f27 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1757,7 +1757,6 @@ process_csb(struct intel_engine_cs *engine, struct
i915_request **inactive)
*/
GEM_BUG_ON(!tasklet_is_locked(&execlists->tasklet) &&
!reset_in_progress(execlists));
- GEM_BUG_ON(!intel_engine_in_execlists_submission_mode(engine));
/*
* Note that csb_write, csb_status may be either in HWSP or mmio.
@@ -3877,13 +3876,6 @@ void intel_execlists_show_requests(struct
intel_engine_cs *engine,
spin_unlock_irqrestore(&engine->active.lock, flags);
}
-bool
-intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine)
-{
- return engine->set_default_submission ==
- execlists_set_default_submission;
-}
-
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_execlists.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
index a8fd7adefd82..f7bd3fccfee8 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
@@ -41,7 +41,4 @@ int intel_virtual_engine_attach_bond(struct intel_engine_cs
*engine,
const struct intel_engine_cs *master,
const struct intel_engine_cs *sibling);
-bool
-intel_engine_in_execlists_submission_mode
[Intel-gfx] [CI 11/13] drm/i915: Extract request rewinding from execlists
In the process of preparing to reuse the request submission logic for
other backends, lift it out of the execlists backend.
While this operates on the common structs, we do have a bit of backend
knowledge, which is harmless for !lrc but still unsightly.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h| 3 -
.../drm/i915/gt/intel_execlists_submission.c | 58 ++-
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 3 +
drivers/gpu/drm/i915/gt/selftest_execlists.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 +-
drivers/gpu/drm/i915/i915_scheduler.c | 44 ++
drivers/gpu/drm/i915/i915_scheduler.h | 3 +
7 files changed, 56 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 8d9184920c51..cc2df80eb449 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -137,9 +137,6 @@ execlists_active_unlock_bh(struct intel_engine_execlists
*execlists)
local_bh_enable(); /* restore softirq, and kick ksoftirqd! */
}
-struct i915_request *
-execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
-
static inline u32
intel_read_status_page(const struct intel_engine_cs *engine, int reg)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 787a029f5975..172144a96bb1 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -360,56 +360,6 @@ assert_priority_queue(const struct i915_request *prev,
return rq_prio(prev) >= rq_prio(next);
}
-static struct i915_request *
-__unwind_incomplete_requests(struct intel_engine_cs *engine)
-{
- struct i915_request *rq, *rn, *active = NULL;
- struct list_head *pl;
- int prio = I915_PRIORITY_INVALID;
-
- lockdep_assert_held(&engine->active.lock);
-
- list_for_each_entry_safe_reverse(rq, rn,
-&engine->active.requests,
-sched.link) {
- if (__i915_request_is_complete(rq)) {
- list_del_init(&rq->sched.link);
- continue;
- }
-
- __i915_request_unsubmit(rq);
-
- GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
- if (rq_prio(rq) != prio) {
- prio = rq_prio(rq);
- pl = i915_sched_lookup_priolist(engine, prio);
- }
- GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
-
- list_move(&rq->sched.link, pl);
- set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
-
- /* Check in case we rollback so far we wrap [size/2] */
- if (intel_ring_direction(rq->ring,
-rq->tail,
-rq->ring->tail + 8) > 0)
- rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE;
-
- active = rq;
- }
-
- return active;
-}
-
-struct i915_request *
-execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
-{
- struct intel_engine_cs *engine =
- container_of(execlists, typeof(*engine), execlists);
-
- return __unwind_incomplete_requests(engine);
-}
-
static void
execlists_context_status_change(struct i915_request *rq, unsigned long status)
{
@@ -1081,7 +1031,7 @@ static void defer_active(struct intel_engine_cs *engine)
{
struct i915_request *rq;
- rq = __unwind_incomplete_requests(engine);
+ rq = __i915_sched_rewind_requests(engine);
if (!rq)
return;
@@ -1293,7 +1243,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* the preemption, some of the unwound requests may
* complete!
*/
- __unwind_incomplete_requests(engine);
+ __i915_sched_rewind_requests(engine);
last = NULL;
} else if (timeslice_expired(engine, last)) {
@@ -2288,7 +2238,7 @@ static void execlists_capture(struct intel_engine_cs
*engine)
* which we return it to the queue for signaling.
*
* By removing them from the execlists queue, we also remove the
-* requests from being processed by __unwind_incomplete_requests()
+* requests from being processed by __intel_engine_rewind_requests()
* during the intel_engine_reset(), and so they will *not* be replayed
* afterwards.
*
@@ -2898,7 +2848,7 @@ static void execlists_reset_rewind(struct intel_engine_cs
*engine, bool stalled)
/* Push back any incomplete requests for replay afte
[Intel-gfx] [CI 08/13] drm/i915/selftests: Exercise priority inheritance around an engine loop
Exercise rescheduling priority inheritance around a sequence of requests
that wrap around all the engines.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/selftests/i915_scheduler.c | 225 ++
1 file changed, 225 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
index d095fab2ccec..acc666f755d7 100644
--- a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
@@ -7,6 +7,7 @@
#include "gt/intel_context.h"
#include "gt/intel_gpu_commands.h"
+#include "gt/intel_ring.h"
#include "gt/selftest_engine_heartbeat.h"
#include "selftests/igt_spinner.h"
#include "selftests/i915_random.h"
@@ -504,10 +505,234 @@ static int igt_priority_chains(void *arg)
return igt_schedule_chains(arg, igt_priority);
}
+static struct i915_request *
+__write_timestamp(struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *obj,
+ int slot,
+ struct i915_request *prev)
+{
+ struct i915_request *rq = ERR_PTR(-EINVAL);
+ bool use_64b = INTEL_GEN(engine->i915) >= 8;
+ struct intel_context *ce;
+ struct i915_vma *vma;
+ int err = 0;
+ u32 *cs;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return ERR_CAST(ce);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_ce;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto out_ce;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unpin;
+ }
+
+ i915_vma_lock(vma);
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+ if (err)
+ goto out_request;
+
+ if (prev) {
+ err = i915_request_await_dma_fence(rq, &prev->fence);
+ if (err)
+ goto out_request;
+ }
+
+ if (engine->emit_init_breadcrumb) {
+ err = engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_request;
+ }
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto out_request;
+ }
+
+ *cs++ = MI_STORE_REGISTER_MEM + use_64b;
+ *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base));
+ *cs++ = lower_32_bits(vma->node.start) + sizeof(u32) * slot;
+ *cs++ = upper_32_bits(vma->node.start);
+ intel_ring_advance(rq, cs);
+
+ i915_request_get(rq);
+out_request:
+ i915_request_add(rq);
+out_unpin:
+ i915_vma_unpin(vma);
+out_ce:
+ intel_context_put(ce);
+ i915_request_put(prev);
+ return err ? ERR_PTR(err) : rq;
+}
+
+static struct i915_request *create_spinner(struct drm_i915_private *i915,
+ struct igt_spinner *spin)
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ struct intel_context *ce;
+ struct i915_request *rq;
+
+ if (igt_spinner_init(spin, engine->gt))
+ return ERR_PTR(-ENOMEM);
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return ERR_CAST(ce);
+
+ rq = igt_spinner_create_request(spin, ce, MI_NOOP);
+ intel_context_put(ce);
+ if (rq == ERR_PTR(-ENODEV))
+ continue;
+ if (IS_ERR(rq))
+ return rq;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ return rq;
+ }
+
+ return ERR_PTR(-ENODEV);
+}
+
+static bool has_timestamp(const struct drm_i915_private *i915)
+{
+ return INTEL_GEN(i915) >= 7;
+}
+
+static int __igt_schedule_cycle(struct drm_i915_private *i915,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_engine_cs *engine;
+ struct drm_i915_gem_object *obj;
+ struct igt_spinner spin;
+ struct i915_request *rq;
+ unsigned long count, n;
+ u32 *time, last;
+ int err;
+
+ /*
+* Queue a bunch of ordered requests (each waiting on the previous)
+* around the engines a couple of times. Each request will write
+* the timestamp it executes at into the scratch, with the expectation
+* that the timestamp will be in our desired execution order.
+*/
+
+ if (!i915->caps.scheduler || !has_timestamp(i915))
+ return 0;
+
+ obj = i915_gem_object_create_internal(i915, SZ_64K);
+ if (IS_ERR(ob
[Intel-gfx] [CI 05/13] drm/i915: Replace engine->schedule() with a known request operation
Looking to the future, we want to set the scheduling attributes
explicitly and so replace the generic engine->schedule() with the more
direct i915_request_set_priority()
What it loses in removing the 'schedule' name from the function, it
gains in having an explicit entry point with a stated goal.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++-
drivers/gpu/drm/i915/gem/i915_gem_object.h| 5 ++-
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 29 +---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 --
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 +--
drivers/gpu/drm/i915/gt/intel_engine_types.h | 27 ---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 3 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 33 +--
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 11 +++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 +-
drivers/gpu/drm/i915/i915_request.c | 10 +++---
drivers/gpu/drm/i915/i915_request.h | 5 +++
drivers/gpu/drm/i915/i915_scheduler.c | 15 +
drivers/gpu/drm/i915/i915_scheduler.h | 3 +-
15 files changed, 64 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d8f10589e09e..aca964f7ba72 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13662,7 +13662,6 @@ int
intel_prepare_plane_fb(struct drm_plane *_plane,
struct drm_plane_state *_new_plane_state)
{
- struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
struct intel_plane *plane = to_intel_plane(_plane);
struct intel_plane_state *new_plane_state =
to_intel_plane_state(_new_plane_state);
@@ -13703,7 +13702,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
if (new_plane_state->uapi.fence) { /* explicit fencing */
i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
-&attr);
+I915_PRIORITY_DISPLAY);
ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
new_plane_state->uapi.fence,
i915_fence_timeout(dev_priv),
@@ -13725,7 +13724,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
if (ret)
return ret;
- i915_gem_object_wait_priority(obj, 0, &attr);
+ i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
if (!new_plane_state->uapi.fence) { /* implicit fencing */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 3411ad197fa6..325766abca21 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -549,15 +549,14 @@ static inline void __start_cpu_write(struct
drm_i915_gem_object *obj)
obj->cache_dirty = true;
}
-void i915_gem_fence_wait_priority(struct dma_fence *fence,
- const struct i915_sched_attr *attr);
+void i915_gem_fence_wait_priority(struct dma_fence *fence, int prio);
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
unsigned int flags,
long timeout);
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
unsigned int flags,
- const struct i915_sched_attr *attr);
+ int prio);
void __i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
enum fb_op_origin origin);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
index 4b9856d5ba14..d79bf16083bd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
@@ -91,22 +91,12 @@ i915_gem_object_wait_reservation(struct dma_resv *resv,
return timeout;
}
-static void fence_set_priority(struct dma_fence *fence,
- const struct i915_sched_attr *attr)
+static void fence_set_priority(struct dma_fence *fence, int prio)
{
- struct i915_request *rq;
- struct intel_engine_cs *engine;
-
if (dma_fence_is_signaled(fence) || !dma_fence_is_i915(fence))
return;
- rq = to_request(fence);
- engine = rq->engine;
-
- rcu_read_lock(); /* RCU serialisation for set-wedged protection */
- if (engine->schedule)
- engine->schedule(rq, attr);
- rcu_read_unlock();
+ i915_request_set_priority(to_request(fence)
[Intel-gfx] [CI 07/13] drm/i915/selftests: Measure set-priority duration
As a topological sort, we expect it to run in linear graph time,
O(V+E). In removing the recursion, it is no longer a DFS but rather a
BFS, and performs as O(VE). Let's demonstrate how bad this is with a few
examples, and build a few test cases to verify a potential fix.
Signed-off-by: Chris Wilson
Acked-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_scheduler.c | 4 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/i915_perf_selftests.h | 1 +
.../gpu/drm/i915/selftests/i915_scheduler.c | 672 ++
4 files changed, 678 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_scheduler.c
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 035e4be5d573..27bda7617b29 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -609,6 +609,10 @@ void i915_request_show_with_schedule(struct drm_printer *m,
rcu_read_unlock();
}
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/i915_scheduler.c"
+#endif
+
static void i915_global_scheduler_shrink(void)
{
kmem_cache_shrink(global.slab_dependencies);
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index a92c0e9b7e6b..2200a5baa68e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -26,6 +26,7 @@ selftest(gt_mocs, intel_mocs_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
selftest(gt_heartbeat, intel_heartbeat_live_selftests)
selftest(requests, i915_request_live_selftests)
+selftest(scheduler, i915_scheduler_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
selftest(mman, i915_gem_mman_live_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
index c2389f8a257d..137e35283fee 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
@@ -17,5 +17,6 @@
*/
selftest(engine_cs, intel_engine_cs_perf_selftests)
selftest(request, i915_request_perf_selftests)
+selftest(scheduler, i915_scheduler_perf_selftests)
selftest(blt, i915_gem_object_blt_perf_selftests)
selftest(region, intel_memory_region_perf_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
new file mode 100644
index ..d095fab2ccec
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
@@ -0,0 +1,672 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_selftest.h"
+
+#include "gt/intel_context.h"
+#include "gt/intel_gpu_commands.h"
+#include "gt/selftest_engine_heartbeat.h"
+#include "selftests/igt_spinner.h"
+#include "selftests/i915_random.h"
+
+static void scheduling_disable(struct intel_engine_cs *engine)
+{
+ engine->props.preempt_timeout_ms = 0;
+ engine->props.timeslice_duration_ms = 0;
+
+ st_engine_heartbeat_disable(engine);
+}
+
+static void scheduling_enable(struct intel_engine_cs *engine)
+{
+ st_engine_heartbeat_enable(engine);
+
+ engine->props.preempt_timeout_ms =
+ engine->defaults.preempt_timeout_ms;
+ engine->props.timeslice_duration_ms =
+ engine->defaults.timeslice_duration_ms;
+}
+
+static int first_engine(struct drm_i915_private *i915,
+ int (*chain)(struct intel_engine_cs *engine,
+unsigned long param,
+bool (*fn)(struct i915_request *rq,
+ unsigned long v,
+ unsigned long e)),
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ if (!intel_engine_has_scheduler(engine))
+ continue;
+
+ return chain(engine, param, fn);
+ }
+
+ return 0;
+}
+
+static int all_engines(struct drm_i915_private *i915,
+ int (*chain)(struct intel_engine_cs *engine,
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v,
+ unsigned long e)),
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_engine_cs *engine;
+ int err;
+
+ for_each_uabi_en
[Intel-gfx] [CI 12/13] drm/i915: Extract request suspension from the execlists
Make the ability to suspend and resume a request and its dependents
generic.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 167 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 8 +-
drivers/gpu/drm/i915/i915_scheduler.c | 153
drivers/gpu/drm/i915/i915_scheduler.h | 10 ++
4 files changed, 169 insertions(+), 169 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 172144a96bb1..0a0df40823b9 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1922,169 +1922,6 @@ static void post_process_csb(struct i915_request **port,
execlists_schedule_out(*port++);
}
-static void __execlists_hold(struct i915_request *rq)
-{
- LIST_HEAD(list);
-
- do {
- struct i915_dependency *p;
-
- if (i915_request_is_active(rq))
- __i915_request_unsubmit(rq);
-
- clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
- list_move_tail(&rq->sched.link, &rq->engine->active.hold);
- i915_request_set_hold(rq);
- RQ_TRACE(rq, "on hold\n");
-
- for_each_waiter(p, rq) {
- struct i915_request *w =
- container_of(p->waiter, typeof(*w), sched);
-
- if (p->flags & I915_DEPENDENCY_WEAK)
- continue;
-
- /* Leave semaphores spinning on the other engines */
- if (w->engine != rq->engine)
- continue;
-
- if (!i915_request_is_ready(w))
- continue;
-
- if (__i915_request_is_complete(w))
- continue;
-
- if (i915_request_on_hold(w))
- continue;
-
- list_move_tail(&w->sched.link, &list);
- }
-
- rq = list_first_entry_or_null(&list, typeof(*rq), sched.link);
- } while (rq);
-}
-
-static bool execlists_hold(struct intel_engine_cs *engine,
- struct i915_request *rq)
-{
- if (i915_request_on_hold(rq))
- return false;
-
- spin_lock_irq(&engine->active.lock);
-
- if (__i915_request_is_complete(rq)) { /* too late! */
- rq = NULL;
- goto unlock;
- }
-
- /*
-* Transfer this request onto the hold queue to prevent it
-* being resumbitted to HW (and potentially completed) before we have
-* released it. Since we may have already submitted following
-* requests, we need to remove those as well.
-*/
- GEM_BUG_ON(i915_request_on_hold(rq));
- GEM_BUG_ON(rq->engine != engine);
- __execlists_hold(rq);
- GEM_BUG_ON(list_empty(&engine->active.hold));
-
-unlock:
- spin_unlock_irq(&engine->active.lock);
- return rq;
-}
-
-static bool hold_request(const struct i915_request *rq)
-{
- struct i915_dependency *p;
- bool result = false;
-
- /*
-* If one of our ancestors is on hold, we must also be on hold,
-* otherwise we will bypass it and execute before it.
-*/
- rcu_read_lock();
- for_each_signaler(p, rq) {
- const struct i915_request *s =
- container_of(p->signaler, typeof(*s), sched);
-
- if (s->engine != rq->engine)
- continue;
-
- result = i915_request_on_hold(s);
- if (result)
- break;
- }
- rcu_read_unlock();
-
- return result;
-}
-
-static void __execlists_unhold(struct i915_request *rq)
-{
- LIST_HEAD(list);
-
- do {
- struct i915_dependency *p;
-
- RQ_TRACE(rq, "hold release\n");
-
- GEM_BUG_ON(!i915_request_on_hold(rq));
- GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
-
- i915_request_clear_hold(rq);
- list_move_tail(&rq->sched.link,
- i915_sched_lookup_priolist(rq->engine,
- rq_prio(rq)));
- set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
-
- /* Also release any children on this engine that are ready */
- for_each_waiter(p, rq) {
- struct i915_request *w =
- container_of(p->waiter, typeof(*w), sched);
-
- if (p->flags & I915_DEPENDENCY_WEAK)
- continue;
-
- /* Propagate any change in error status */
- if (rq->fence.error)
-
[Intel-gfx] [CI 06/13] drm/i915: Restructure priority inheritance
In anticipation of wanting to be able to call pi from underneath an
engine's active.lock, rework the priority inheritance to primarily work
along an engine's priority queue, delegating any other engine that the
chain may traverse to a worker. This reduces the global spinlock from
governing the entire multi-engine priority inheritance depth-first search,
to a smaller lock on each engine around a single list on that engine.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 3 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +
drivers/gpu/drm/i915/i915_scheduler.c | 356 +++---
drivers/gpu/drm/i915/i915_scheduler.h | 3 +
drivers/gpu/drm/i915/i915_scheduler_types.h | 23 +-
6 files changed, 249 insertions(+), 141 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 92a3c8a43e14..36c6b8d7287d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -582,6 +582,8 @@ void intel_engine_init_execlists(struct intel_engine_cs
*engine)
execlists->queue_priority_hint = INT_MIN;
execlists->queue = RB_ROOT_CACHED;
+
+ i915_sched_init_ipi(&execlists->ipi);
}
static void cleanup_status_page(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index 0b026cde9f09..48a91c0dbad6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -114,8 +114,7 @@ static void heartbeat(struct work_struct *wrk)
* but all other contexts, including the kernel
* context are stuck waiting for the signal.
*/
- } else if (intel_engine_has_scheduler(engine) &&
- rq->sched.attr.priority < I915_PRIORITY_BARRIER) {
+ } else if (rq->sched.attr.priority < I915_PRIORITY_BARRIER) {
/*
* Gradually raise the priority of the heartbeat to
* give high priority work [which presumably desires
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index cb81f0d93189..1b404fef40a6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -20,6 +20,7 @@
#include "i915_gem.h"
#include "i915_pmu.h"
#include "i915_priolist_types.h"
+#include "i915_scheduler_types.h"
#include "i915_selftest.h"
#include "intel_breadcrumbs_types.h"
#include "intel_sseu.h"
@@ -257,6 +258,8 @@ struct intel_engine_execlists {
struct rb_root_cached queue;
struct rb_root_cached virtual;
+ struct i915_sched_ipi ipi;
+
/**
* @csb_write: control register for Context Switch buffer
*
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 84a55df88687..035e4be5d573 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -17,7 +17,25 @@ static struct i915_global_scheduler {
struct kmem_cache *slab_priorities;
} global;
-static DEFINE_SPINLOCK(schedule_lock);
+/*
+ * Virtual engines complicate acquiring the engine timeline lock,
+ * as their rq->engine pointer is not stable until under that
+ * engine lock. The simple ploy we use is to take the lock then
+ * check that the rq still belongs to the newly locked engine.
+ */
+#define lock_engine_irqsave(rq, flags) ({ \
+ struct i915_request * const rq__ = (rq); \
+ struct intel_engine_cs *engine__ = READ_ONCE(rq__->engine); \
+\
+ spin_lock_irqsave(&engine__->active.lock, (flags)); \
+ while (engine__ != READ_ONCE((rq__)->engine)) { \
+ spin_unlock(&engine__->active.lock); \
+ engine__ = READ_ONCE(rq__->engine); \
+ spin_lock(&engine__->active.lock); \
+ } \
+\
+ engine__; \
+})
static struct i915_sched_node *node_get(struct i915_sched_node *node)
{
@@ -30,17 +48,104 @@ static void node_put(struct i915_sched_node *node)
i915_request_put(container_of(node, struct i915_request, sched));
}
+static inline int rq_prio(const struct i915_request *rq)
+{
+ return READ_ONCE(rq->sched.attr.priority);
+}
+
+static int ipi_get_prio(struct i915_request *rq)
+{
+ if (READ_ONCE(rq->sched.ipi_priority) == I915_PRIORITY_INVALID)
+ return I915_PRIORITY_INVALID;
+
+ return xchg(&rq->sched.ipi_priority, I915_PRIORITY_INVALID);
+}
+
+static void ipi_schedule(struct work_struct *wrk)
+{
+ struct i915_sched_ipi *ipi = container_of(wrk, typeof(*ipi), work);
+ struct i915_request *rq = xchg(&ipi->list, NULL);
+
+ do {
+
[Intel-gfx] [CI 09/13] drm/i915: Improve DFS for priority inheritance
The core of the scheduling algorithm is that we compute the topological
order of the fence DAG. Knowing that we have a DAG, we should be able to
use a DFS to compute the topological sort in linear time. However,
during the conversion of the recursive algorithm into an iterative one,
the memoization of how far we had progressed down a branch was
forgotten. The result was that instead of running in linear time, it was
running in geometric time and could easily run for a few hundred
milliseconds given a wide enough graph, not the microseconds as required.
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_scheduler.c | 58 -
drivers/gpu/drm/i915/i915_scheduler_types.h | 6 ++-
2 files changed, 39 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 27bda7617b29..9e88417bf451 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -242,6 +242,26 @@ void __i915_priolist_free(struct i915_priolist *p)
kmem_cache_free(global.slab_priorities, p);
}
+static struct i915_request *
+stack_push(struct i915_request *rq,
+ struct i915_request *prev,
+ struct list_head *pos)
+{
+ prev->sched.dfs.pos = pos;
+ rq->sched.dfs.prev = prev;
+ return rq;
+}
+
+static struct i915_request *
+stack_pop(struct i915_request *rq,
+ struct list_head **pos)
+{
+ rq = rq->sched.dfs.prev;
+ if (rq)
+ *pos = rq->sched.dfs.pos;
+ return rq;
+}
+
static inline bool need_preempt(int prio, int active)
{
/*
@@ -306,11 +326,10 @@ static void ipi_priority(struct i915_request *rq, int
prio)
static void __i915_request_set_priority(struct i915_request *rq, int prio)
{
struct intel_engine_cs *engine = rq->engine;
- struct i915_request *rn;
+ struct list_head *pos = &rq->sched.signalers_list;
struct list_head *plist;
- LIST_HEAD(dfs);
- list_add(&rq->sched.dfs, &dfs);
+ plist = i915_sched_lookup_priolist(engine, prio);
/*
* Recursively bump all dependent priorities to match the new request.
@@ -330,40 +349,31 @@ static void __i915_request_set_priority(struct
i915_request *rq, int prio)
* end result is a topological list of requests in reverse order, the
* last element in the list is the request we must execute first.
*/
- list_for_each_entry(rq, &dfs, sched.dfs) {
- struct i915_dependency *p;
-
- /* Also release any children on this engine that are ready */
- GEM_BUG_ON(rq->engine != engine);
-
- for_each_signaler(p, rq) {
+ rq->sched.dfs.prev = NULL;
+ do {
+ list_for_each_continue(pos, &rq->sched.signalers_list) {
+ struct i915_dependency *p =
+ list_entry(pos, typeof(*p), signal_link);
struct i915_request *s =
container_of(p->signaler, typeof(*s), sched);
- GEM_BUG_ON(s == rq);
-
if (rq_prio(s) >= prio)
continue;
if (__i915_request_is_complete(s))
continue;
- if (s->engine != rq->engine) {
+ if (s->engine != engine) {
ipi_priority(s, prio);
continue;
}
- list_move_tail(&s->sched.dfs, &dfs);
+ /* Remember our position along this branch */
+ rq = stack_push(s, rq, pos);
+ pos = &rq->sched.signalers_list;
}
- }
- plist = i915_sched_lookup_priolist(engine, prio);
-
- /* Fifo and depth-first replacement ensure our deps execute first */
- list_for_each_entry_safe_reverse(rq, rn, &dfs, sched.dfs) {
- GEM_BUG_ON(rq->engine != engine);
-
- INIT_LIST_HEAD(&rq->sched.dfs);
+ RQ_TRACE(rq, "set-priority:%d\n", prio);
WRITE_ONCE(rq->sched.attr.priority, prio);
/*
@@ -377,12 +387,13 @@ static void __i915_request_set_priority(struct
i915_request *rq, int prio)
if (!i915_request_is_ready(rq))
continue;
+ GEM_BUG_ON(rq->engine != engine);
if (i915_request_in_priority_queue(rq))
list_move_tail(&rq->sched.link, plist);
/* Defer (tasklet) submission until after all updates. */
kick_submission(engine, rq, prio);
- }
+ } while ((rq = stack_pop(rq, &pos)));
}
#define all_signalers_checked(p, rq) \
@@ -456,7 +467,6 @@ void i915_sched_node_init(struct i915_sched_node *no
[Intel-gfx] [CI 13/13] drm/i915: Extract the ability to defer and rerun a request later
Lift the ability to defer a request until later from execlists into the
common layer.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 57 +++--
drivers/gpu/drm/i915/i915_scheduler.c | 63 +--
drivers/gpu/drm/i915/i915_scheduler.h | 5 +-
3 files changed, 67 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 0a0df40823b9..8b6eb1a9b29a 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -979,54 +979,6 @@ static void virtual_xfer_context(struct virtual_engine *ve,
}
}
-static void defer_request(struct i915_request *rq, struct list_head * const pl)
-{
- LIST_HEAD(list);
-
- /*
-* We want to move the interrupted request to the back of
-* the round-robin list (i.e. its priority level), but
-* in doing so, we must then move all requests that were in
-* flight and were waiting for the interrupted request to
-* be run after it again.
-*/
- do {
- struct i915_dependency *p;
-
- GEM_BUG_ON(i915_request_is_active(rq));
- list_move_tail(&rq->sched.link, pl);
-
- for_each_waiter(p, rq) {
- struct i915_request *w =
- container_of(p->waiter, typeof(*w), sched);
-
- if (p->flags & I915_DEPENDENCY_WEAK)
- continue;
-
- /* Leave semaphores spinning on the other engines */
- if (w->engine != rq->engine)
- continue;
-
- /* No waiter should start before its signaler */
- GEM_BUG_ON(i915_request_has_initial_breadcrumb(w) &&
- __i915_request_has_started(w) &&
- !__i915_request_is_complete(rq));
-
- if (!i915_request_is_ready(w))
- continue;
-
- if (rq_prio(w) < rq_prio(rq))
- continue;
-
- GEM_BUG_ON(rq_prio(w) > rq_prio(rq));
- GEM_BUG_ON(i915_request_is_active(w));
- list_move_tail(&w->sched.link, &list);
- }
-
- rq = list_first_entry_or_null(&list, typeof(*rq), sched.link);
- } while (rq);
-}
-
static void defer_active(struct intel_engine_cs *engine)
{
struct i915_request *rq;
@@ -1035,7 +987,14 @@ static void defer_active(struct intel_engine_cs *engine)
if (!rq)
return;
- defer_request(rq, i915_sched_lookup_priolist(engine, rq_prio(rq)));
+ /*
+* We want to move the interrupted request to the back of
+* the round-robin list (i.e. its priority level), but
+* in doing so, we must then move all requests that were in
+* flight and were waiting for the interrupted request to
+* be run after it again.
+*/
+ __i915_sched_defer_request(engine, rq);
}
static bool
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index a5df27061c3c..641141f3ce10 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -179,8 +179,8 @@ static void assert_priolists(struct intel_engine_execlists
* const execlists)
}
}
-struct list_head *
-i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio)
+static struct list_head *
+lookup_priolist(struct intel_engine_cs *engine, int prio)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
struct i915_priolist *p;
@@ -332,7 +332,7 @@ static void __i915_request_set_priority(struct i915_request
*rq, int prio)
struct list_head *pos = &rq->sched.signalers_list;
struct list_head *plist;
- plist = i915_sched_lookup_priolist(engine, prio);
+ plist = lookup_priolist(engine, prio);
/*
* Recursively bump all dependent priorities to match the new request.
@@ -463,12 +463,63 @@ void i915_request_set_priority(struct i915_request *rq,
int prio)
spin_unlock_irqrestore(&engine->active.lock, flags);
}
+void __i915_sched_defer_request(struct intel_engine_cs *engine,
+ struct i915_request *rq)
+{
+ struct list_head *pl;
+ LIST_HEAD(list);
+
+ lockdep_assert_held(&engine->active.lock);
+ GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags));
+
+ /*
+* When we defer a request, we must maintain its order with respect
+* to those that are waiting upon it. So we traverse its chain of
+* waiters and move any that are earlier than the reques
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [CI,1/3] *** HAX FOR CI *** Revert "rtc: mc146818: Detect and handle broken RTCs"
== Series Details == Series: series starting with [CI,1/3] *** HAX FOR CI *** Revert "rtc: mc146818: Detect and handle broken RTCs" URL : https://patchwork.freedesktop.org/series/86596/ State : failure == Summary == Applying: *** HAX FOR CI *** Revert "rtc: mc146818: Detect and handle broken RTCs" Using index info to reconstruct a base tree... M drivers/rtc/rtc-cmos.c M drivers/rtc/rtc-mc146818-lib.c Falling back to patching base and 3-way merge... No changes -- Patch already applied. Applying: drm-tip: 2021y-02m-02d-12h-50m-06s UTC integration manifest Using index info to reconstruct a base tree... Falling back to patching base and 3-way merge... CONFLICT (add/add): Merge conflict in integration-manifest Auto-merging integration-manifest error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0002 drm-tip: 2021y-02m-02d-12h-50m-06s UTC integration manifest When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gt: Retire unexpected starting state error dumping
Hi Chris, On Mon, Feb 01, 2021 at 04:42:22PM +, Chris Wilson wrote: > We have not seen an occurrence of the false restart state recenty, and if > we did such an event from inside engine-reset, it would deadlock on > trying to suspend the tasklet to read the register state. Instead, we > inspect the context state before submission which will alert us to any > issues prior to execution. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > Cc: Tvrtko Ursulin > Cc: Andi Shyti Reviewed-by: Andi Shyti Thanks, Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI 08/14] drm/i915/selftests: Force a rewind if at first we don't succeed
Quoting Chris Wilson (2021-02-02 21:24:16) > Quoting Chris Wilson (2021-02-02 21:14:35) > > Quoting Chris Wilson (2021-02-02 17:43:53) > > > Let's see how horrible it is to cycle elements on defer. (Curse the > > > irqlock pollution.) > > > > While that did work. I do not have a good idea on how to do list > > rotation on an RCU list. I can see that it must require a pair of > > synchronize_rcu, and that spells disaster (at least for handling it > > inline). > > > > Another way might be to randomize the deadlines along each branch to the > > tree... Except we don't have deadlines at this point and we can't so > > freely change the priorities. > > Speaking of which, this is 'fixed' by the deadlines as there we will > reorder ELSP as the test expects. (Which is why I didn't notice this for > so long.) And I thinks that's how I am going to handle this, by deferring the dfs fix for defer_request until we are ready with deadlines. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI 08/14] drm/i915/selftests: Force a rewind if at first we don't succeed
Quoting Chris Wilson (2021-02-02 21:14:35) > Quoting Chris Wilson (2021-02-02 17:43:53) > > Let's see how horrible it is to cycle elements on defer. (Curse the > > irqlock pollution.) > > While that did work. I do not have a good idea on how to do list > rotation on an RCU list. I can see that it must require a pair of > synchronize_rcu, and that spells disaster (at least for handling it > inline). > > Another way might be to randomize the deadlines along each branch to the > tree... Except we don't have deadlines at this point and we can't so > freely change the priorities. Speaking of which, this is 'fixed' by the deadlines as there we will reorder ELSP as the test expects. (Which is why I didn't notice this for so long.) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] Oops with "ALSA: jack: implement software jack injection via debugfs"
From: Takashi Iwai
On Tue, 02 Feb 2021 17:30:36 +0100,
Chris Wilson wrote:
>
> commit 2d670ea2bd53 ("ALSA: jack: implement software jack injection via
> debugfs") is causing issues for our CI as we see a use-after-free on
> module unload (on all machines):
>
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9715/fi-skl-6700k2/pstore0-1612277467_Oops_1.txt
Could you try the patch below? The unload test was completely
forgotten.
thanks,
Takashi
-- 8< --
From: Takashi Iwai
Subject: [PATCH] ALSA: core: Fix the debugfs removal at snd_card_free()
The debugfs_remove() call should have been done at the right place
before the card object gets freed.
Fixes: 2d670ea2bd53 ("ALSA: jack: implement software jack injection via
debugfs")
Signed-off-by: Takashi Iwai
---
sound/core/init.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/sound/core/init.c b/sound/core/init.c
index d4e78b176793..84b573e9c1f9 100644
--- a/sound/core/init.c
+++ b/sound/core/init.c
@@ -487,6 +487,10 @@ static int snd_card_do_free(struct snd_card *card)
dev_warn(card->dev, "unable to free card info\n");
/* Not fatal error */
}
+#ifdef CONFIG_SND_DEBUG
+ debugfs_remove(card->debugfs_root);
+ card->debugfs_root = NULL;
+#endif
if (card->release_completion)
complete(card->release_completion);
kfree(card);
@@ -537,11 +541,6 @@ int snd_card_free(struct snd_card *card)
/* wait, until all devices are ready for the free operation */
wait_for_completion(&released);
-#ifdef CONFIG_SND_DEBUG
- debugfs_remove(card->debugfs_root);
- card->debugfs_root = NULL;
-#endif
-
return 0;
}
EXPORT_SYMBOL(snd_card_free);
--
2.20.1
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[Intel-gfx] [CI 3/3] Oops with "ALSA: jack: implement software jack injection via debugfs"
From: Takashi Iwai
On Tue, 02 Feb 2021 17:30:36 +0100,
Chris Wilson wrote:
>
> commit 2d670ea2bd53 ("ALSA: jack: implement software jack injection via
> debugfs") is causing issues for our CI as we see a use-after-free on
> module unload (on all machines):
>
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9715/fi-skl-6700k2/pstore0-1612277467_Oops_1.txt
Could you try the patch below? The unload test was completely
forgotten.
thanks,
Takashi
-- 8< --
From: Takashi Iwai
Subject: [PATCH] ALSA: core: Fix the debugfs removal at snd_card_free()
The debugfs_remove() call should have been done at the right place
before the card object gets freed.
Fixes: 2d670ea2bd53 ("ALSA: jack: implement software jack injection via
debugfs")
Signed-off-by: Takashi Iwai
---
sound/core/init.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/sound/core/init.c b/sound/core/init.c
index d4e78b176793..84b573e9c1f9 100644
--- a/sound/core/init.c
+++ b/sound/core/init.c
@@ -487,6 +487,10 @@ static int snd_card_do_free(struct snd_card *card)
dev_warn(card->dev, "unable to free card info\n");
/* Not fatal error */
}
+#ifdef CONFIG_SND_DEBUG
+ debugfs_remove(card->debugfs_root);
+ card->debugfs_root = NULL;
+#endif
if (card->release_completion)
complete(card->release_completion);
kfree(card);
@@ -537,11 +541,6 @@ int snd_card_free(struct snd_card *card)
/* wait, until all devices are ready for the free operation */
wait_for_completion(&released);
-#ifdef CONFIG_SND_DEBUG
- debugfs_remove(card->debugfs_root);
- card->debugfs_root = NULL;
-#endif
-
return 0;
}
EXPORT_SYMBOL(snd_card_free);
--
2.20.1
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[Intel-gfx] [CI 2/3] drm-tip: 2021y-02m-02d-12h-50m-06s UTC integration manifest
From: Joonas Lahtinen --- integration-manifest | 40 1 file changed, 40 insertions(+) create mode 100644 integration-manifest diff --git a/integration-manifest b/integration-manifest new file mode 100644 index ..d80099bceaa5 --- /dev/null +++ b/integration-manifest @@ -0,0 +1,40 @@ +drm drm-fixes e0ecafede87eb1a3d1e708f0365fad0d59489285 + Merge tag 'amd-drm-fixes-5.11-2021-01-28' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes +drm-misc drm-misc-fixes 2b1b3e544f65f40df5eef99753e460a127910479 + drm/ttm: Use __GFP_NOWARN for huge pages in ttm_pool_alloc_page +drm-intel drm-intel-fixes 71a480f455c59041af65b31fa919fc19ce9f9bac + *** HAX FOR CI *** Revert "rtc: mc146818: Detect and handle broken RTCs" +drm-amd drm-amd-fixes 2b702e72e33bbdec0764cfb6e1dd00fe1142ae55 + Merge tag 'drm-misc-fixes-2017-09-28-1' of git://anongit.freedesktop.org/git/drm-misc into drm-fixes +drm drm-next af2922fa158eccf0b1534bad5375cee62a622a4a + Merge branch 'linux-5.12' of git://github.com/skeggsb/linux into drm-next +drm-misc drm-misc-next-fixes be3e477effba636ad25dcd244db264c6cd5c1f36 + drm/komeda: Fix bit check to import to value of proper type +drm-intel drm-intel-next-fixes 046f70d31ddb2069941aec54966fec5b7fbc7b7b + drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping +drm-amd drm-amd-next-fixes 2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e + Linux 4.14-rc1 +drm-misc drm-misc-next 576a08e008e2e3ed7c7ff3d96b3e813f5fdb2b5e + drm/v3d/v3d_sched: fix scheduler callbacks return status +drm-intel drm-intel-next eaf9a3465d9b1fd1dc5a9a151380d84ac3789964 + Merge tag 'topic/drm-device-pdev-2021-02-02' of git://anongit.freedesktop.org/drm/drm-intel into drm-intel-next +drm-intel drm-intel-next-queued 9d8fddf8579a2a20d0e8a8b631547069a62b953e + drm/i915: Disable outputs during unregister +drm-amd drm-amd-next 754270c7c56292e97d0eff924a5d5d83f92add07 + Merge branch 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux into drm-next +sound-upstream for-linus 4841b8e6318a7f0ae57c4e5ec09032ea057c97a8 + ALSA: hda/realtek: modify EAPD in the ALC886 +sound-upstream for-next 2d670ea2bd53a9792f453bb5b97cb8ef695988ff + ALSA: jack: implement software jack injection via debugfs +drm-intel topic/core-for-CI be9bde5a8b7b5cff58bd01c8ca094d571295c40b + Revert "rtc: mc146818: Detect and handle broken RTCs" +drm-intel drm-intel-gt-next 3f33625866cb8fe0a2f08dfac9e339ccb12c6682 + Merge tag 'topic/drm-device-pdev-2021-02-02' of git://anongit.freedesktop.org/drm/drm-intel into drm-intel-gt-next +drm topic/iomem-mmap-vs-gup 74b30195395c406c787280a77ae55aed82dbbfc7 + sysfs: Support zapping of binary attr mmaps +drm topic/nouveau-ampere-modeset 584265dfec70e78ce2085b82ed389f27e06fbca0 + Merge branch '04.01-ampere-lite' of git://github.com/skeggsb/linux into topic/nouveau-ampere-modeset +drm-intel topic/adl-s-enabling 4043277ad18fc7cb9a79d0d043063fb5f42a6f06 + drm/i915/adl_s: Add GT and CTX WAs for ADL-S +drm-intel topic/drm-device-pdev 9ff06c38530099b197b6389193e8cc34ab60288f + drm/i915/gvt: Remove references to struct drm_device.pdev -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/3] *** HAX FOR CI *** Revert "rtc: mc146818: Detect and handle broken RTCs"
From: Jani Nikula
This reverts commit 211e5db19d15a721b2953ea54b8f26c2963720eb.
---
drivers/rtc/rtc-cmos.c | 8
drivers/rtc/rtc-mc146818-lib.c | 7 ---
2 files changed, 15 deletions(-)
diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c
index 68a9ac6f2fe1..51e80bc70d42 100644
--- a/drivers/rtc/rtc-cmos.c
+++ b/drivers/rtc/rtc-cmos.c
@@ -805,14 +805,6 @@ cmos_do_probe(struct device *dev, struct resource *ports,
int rtc_irq)
spin_lock_irq(&rtc_lock);
- /* Ensure that the RTC is accessible. Bit 0-6 must be 0! */
- if ((CMOS_READ(RTC_VALID) & 0x7f) != 0) {
- spin_unlock_irq(&rtc_lock);
- dev_warn(dev, "not accessible\n");
- retval = -ENXIO;
- goto cleanup1;
- }
-
if (!(flags & CMOS_RTC_FLAGS_NOFREQ)) {
/* force periodic irq to CMOS reset default of 1024Hz;
*
diff --git a/drivers/rtc/rtc-mc146818-lib.c b/drivers/rtc/rtc-mc146818-lib.c
index f83c13818af3..972a5b9a629d 100644
--- a/drivers/rtc/rtc-mc146818-lib.c
+++ b/drivers/rtc/rtc-mc146818-lib.c
@@ -21,13 +21,6 @@ unsigned int mc146818_get_time(struct rtc_time *time)
again:
spin_lock_irqsave(&rtc_lock, flags);
- /* Ensure that the RTC is accessible. Bit 0-6 must be 0! */
- if (WARN_ON_ONCE((CMOS_READ(RTC_VALID) & 0x7f) != 0)) {
- spin_unlock_irqrestore(&rtc_lock, flags);
- memset(time, 0xff, sizeof(*time));
- return 0;
- }
-
/*
* Check whether there is an update in progress during which the
* readout is unspecified. The maximum update time is ~2ms. Poll
--
2.20.1
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Re: [Intel-gfx] [CI 08/14] drm/i915/selftests: Force a rewind if at first we don't succeed
Quoting Chris Wilson (2021-02-02 17:43:53) > Let's see how horrible it is to cycle elements on defer. (Curse the > irqlock pollution.) While that did work. I do not have a good idea on how to do list rotation on an RCU list. I can see that it must require a pair of synchronize_rcu, and that spells disaster (at least for handling it inline). Another way might be to randomize the deadlines along each branch to the tree... Except we don't have deadlines at this point and we can't so freely change the priorities. Hmm. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] i915/perf: Store a mask of valid OA formats for a platform
Quoting Umesh Nerlige Ramappa (2021-02-02 20:10:44)
> On Tue, Feb 02, 2021 at 08:24:15AM +, Chris Wilson wrote:
> >Ok, this looks as compact and readable as writing it as a bunch of
> >tables. I presume there's a reason you didn't just use generation rather
> >than platform.
> >
> >switch (gen) {
> >case 7:
> > haswell();
> > break;
> >case 8 .. 11:
> > broadwell();
> > break;
> >case 12:
> > tigerlake();
> > break;
> >}
> >if you wanted to stick with a switch rather than an if-else tree for the
> >ranges.
>
> only haswell is supported on gen7 and gen12 may define new formats that
> are platform specific.
>
> How about a mix? -
>
> if (gen == 7 && haswell)
> haswell();
> else if (gen >= 8 && gen <= 11)
> broadwell;
> else
> gen12_formats();
>
> gen12_formats can choose to use the switch if formats vary between
> platforms.
I didn't mind the platform switch too much, so no need to change at the
moment. I just worry that it's more typing to maintain :)
What I thought you were going to do (from the subject) were tables with
a platform_mask for applicability, but that I feell would be just as
much typing, now and in the future.
I thought support started at Haswell, so the other gen7 were not a
concern? But yes, if we look at how we end up doing it else where it's a
mix of gen and platform
if (gen >= 12)
gen12_formats;
else if (gen >= 8)
gen8_formats;
else if (IS_HSW)
hsw_formats;
else
MISSING_CASE(gen)
At the end of the day, you're the person who is typing this, so it's up
to you how much effort you want to spend now to save later. :)
-Chris
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Re: [Intel-gfx] [PATCH 1/3] i915/perf: Store a mask of valid OA formats for a platform
On Tue, Feb 02, 2021 at 08:24:15AM +, Chris Wilson wrote:
Quoting Umesh Nerlige Ramappa (2021-02-02 07:54:15)
Validity of an OA format is checked by using a sparse array of formats
per gen. Instead maintain a mask of supported formats for a platform in
the perf object.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 64 +-
drivers/gpu/drm/i915/i915_perf_types.h | 16 +++
2 files changed, 79 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 112ba5f2ce90..973577fcad58 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3524,6 +3524,19 @@ static u64 oa_exponent_to_ns(struct i915_perf *perf, int
exponent)
2ULL << exponent);
}
+static __always_inline bool
+oa_format_valid(struct i915_perf *perf, enum drm_i915_oa_format format)
+{
+ return !!(perf->format_mask[__format_index(format)] &
+ __format_bit(format));
!! is already provided by the implicit cast to (bool)
+}
+
+static __always_inline void
+oa_format_add(struct i915_perf *perf, enum drm_i915_oa_format format)
+{
+ perf->format_mask[__format_index(format)] |= __format_bit(format);
+}
+
/**
* read_properties_unlocked - validate + copy userspace stream open properties
* @perf: i915 perf instance
@@ -3615,7 +3628,7 @@ static int read_properties_unlocked(struct i915_perf
*perf,
value);
return -EINVAL;
}
- if (!perf->oa_formats[value].size) {
+ if (!oa_format_valid(perf, value)) {
DRM_DEBUG("Unsupported OA report format %llu\n",
value);
return -EINVAL;
@@ -4259,6 +4272,53 @@ static struct ctl_table dev_root[] = {
{}
};
+static void oa_init_supported_formats(struct i915_perf *perf)
+{
+ struct drm_i915_private *i915 = perf->i915;
+ enum intel_platform platform = INTEL_INFO(i915)->platform;
+
+ switch (platform) {
+ case INTEL_HASWELL:
+ oa_format_add(perf, I915_OA_FORMAT_A13);
+ oa_format_add(perf, I915_OA_FORMAT_A13);
+ oa_format_add(perf, I915_OA_FORMAT_A29);
+ oa_format_add(perf, I915_OA_FORMAT_A13_B8_C8);
+ oa_format_add(perf, I915_OA_FORMAT_B4_C8);
+ oa_format_add(perf, I915_OA_FORMAT_A45_B8_C8);
+ oa_format_add(perf, I915_OA_FORMAT_B4_C8_A16);
+ oa_format_add(perf, I915_OA_FORMAT_C4_B8);
+ break;
+
+ case INTEL_BROADWELL:
+ case INTEL_CHERRYVIEW:
+ case INTEL_SKYLAKE:
+ case INTEL_BROXTON:
+ case INTEL_KABYLAKE:
+ case INTEL_GEMINILAKE:
+ case INTEL_COFFEELAKE:
+ case INTEL_COMETLAKE:
+ case INTEL_CANNONLAKE:
+ case INTEL_ICELAKE:
+ case INTEL_ELKHARTLAKE:
+ case INTEL_JASPERLAKE:
+ oa_format_add(perf, I915_OA_FORMAT_A12);
+ oa_format_add(perf, I915_OA_FORMAT_A12_B8_C8);
+ oa_format_add(perf, I915_OA_FORMAT_A32u40_A4u32_B8_C8);
+ oa_format_add(perf, I915_OA_FORMAT_C4_B8);
+ break;
Ok, this looks as compact and readable as writing it as a bunch of
tables. I presume there's a reason you didn't just use generation rather
than platform.
switch (gen) {
case 7:
haswell();
break;
case 8 .. 11:
broadwell();
break;
case 12:
tigerlake();
break;
}
if you wanted to stick with a switch rather than an if-else tree for the
ranges.
only haswell is supported on gen7 and gen12 may define new formats that
are platform specific.
How about a mix? -
if (gen == 7 && haswell)
haswell();
else if (gen >= 8 && gen <= 11)
broadwell;
else
gen12_formats();
gen12_formats can choose to use the switch if formats vary between
platforms.
Thanks,
Umesh
Note you could equally do
case INTEL_BROADWELL .. INTEL_JASPERLAKE:
but I expect that to cause confusion for the reader.
+ /**
+* Use a format mask to store the supported formats
+* for a platform.
+*/
+#define __fbits (BITS_PER_TYPE(u32))
+#define __format_bit(__f) \
+ BIT((__f) & (__fbits - 1))
+
+#define __format_index_shift (5)
+#define __format_index(__f) \
+ (((__f) & ~(__fbits - 1)) >> __format_index_shift)
+
+#define FORMAT_MASK_SIZE (((I915_OA_FORMAT_MAX - 1) / __fbits) + 1)
+ u32 format_mask[FORMAT_MASK_SIZE];
This is just open-coding set_bit/test_bit
#define FORMAT_MASK_SIZE DIV_ROUND_UP(I915_OA_FORMAT_MAX - 1, BITS_PER_LONG)
unsigned long format_mask[FORMAT_MASK_SIZE];
static __always_inline bool
oa_format_valid(struct i915_perf *perf, enum drm_i915_oa_format format)
{
return test_
[Intel-gfx] linux-next: Signed-off-by missing for commit in the drm-intel-fixes tree
Hi all,
Commit
44c5bd08518c ("*** HAX FOR CI *** Revert "rtc: mc146818: Detect and handle
broken RTCs"")
is missing a Signed-off-by from its author and committer.
Reverts are commits as well.
--
Cheers,
Stephen Rothwell
pgpKZp048c5Hl.pgp
Description: OpenPGP digital signature
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "ALSA: jack: implement software jack injection via debugfs"
== Series Details == Series: Revert "ALSA: jack: implement software jack injection via debugfs" URL : https://patchwork.freedesktop.org/series/86590/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9718 -> Patchwork_19563 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19563 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19563, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19563: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_lrc: - fi-bsw-n3050: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html Known issues Here are the changes found in Patchwork_19563 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-cfl-guc: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-cfl-guc/igt@amdgpu/amd_ba...@cs-compute.html - fi-skl-guc: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-skl-guc/igt@amdgpu/amd_ba...@cs-compute.html - fi-elk-e7500: NOTRUN -> [SKIP][4] ([fdo#109271]) +18 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-elk-e7500/igt@amdgpu/amd_ba...@cs-compute.html * igt@amdgpu/amd_basic@cs-gfx: - fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#109315]) +17 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html - fi-skl-6700k2: NOTRUN -> [SKIP][6] ([fdo#109271]) +17 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-skl-6700k2/igt@amdgpu/amd_ba...@cs-gfx.html - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271]) +17 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_basic@cs-sdma: - fi-kbl-guc: NOTRUN -> [SKIP][8] ([fdo#109271]) +17 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-kbl-guc/igt@amdgpu/amd_ba...@cs-sdma.html - fi-cfl-8109u: NOTRUN -> [SKIP][9] ([fdo#109271]) +17 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-cfl-8109u/igt@amdgpu/amd_ba...@cs-sdma.html - fi-kbl-7500u: NOTRUN -> [SKIP][10] ([fdo#109271]) +17 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-kbl-7500u/igt@amdgpu/amd_ba...@cs-sdma.html * igt@amdgpu/amd_basic@memory-alloc: - fi-cml-u2: NOTRUN -> [SKIP][11] ([fdo#109315]) +17 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> [SKIP][12] ([fdo#109271]) +17 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html - fi-glk-dsi: NOTRUN -> [SKIP][13] ([fdo#109271]) +17 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-glk-dsi/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_basic@semaphore: - fi-icl-y: NOTRUN -> [SKIP][14] ([fdo#109315]) +17 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-icl-y/igt@amdgpu/amd_ba...@semaphore.html - fi-bsw-nick:NOTRUN -> [SKIP][15] ([fdo#109271]) +17 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html - fi-bdw-5557u: NOTRUN -> [SKIP][16] ([fdo#109271]) +17 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@amdgpu/amd_basic@userptr: - fi-bxt-dsi: NOTRUN -> [SKIP][17] ([fdo#109271]) +17 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-bxt-dsi/igt@amdgpu/amd_ba...@userptr.html * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-tgl-u2: NOTRUN -> [SKIP][18] ([fdo#109315] / [i915#2575]) +17 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19563/fi-tgl-u2/igt@amdgpu/amd_cs_...@fork-compute0.html - fi-ivb-3770:NOTRUN -> [SKIP][19] ([fdo#109271]) +18 similar issues [19]: h
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Use a single copy of the mocs table
Chris Wilson writes:
> Instead of copying the whole table to each category (mocs, l3cc), use a
> single table with a pointer to it if the category is enabled.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/selftest_mocs.c | 32 +
> 1 file changed, 22 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> index e6f6807487d4..44609d1c7780 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> @@ -12,8 +12,9 @@
> #include "selftests/igt_spinner.h"
>
> struct live_mocs {
> - struct drm_i915_mocs_table mocs;
> - struct drm_i915_mocs_table l3cc;
> + struct drm_i915_mocs_table table;
> + struct drm_i915_mocs_table *mocs;
> + struct drm_i915_mocs_table *l3cc;
> struct i915_vma *scratch;
> void *vaddr;
> };
> @@ -58,21 +59,20 @@ static int request_add_spin(struct i915_request *rq,
> struct igt_spinner *spin)
>
> static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
> {
> - struct drm_i915_mocs_table table;
> unsigned int flags;
> int err;
>
> memset(arg, 0, sizeof(*arg));
>
> - flags = get_mocs_settings(gt->i915, &table);
> + flags = get_mocs_settings(gt->i915, &arg->table);
> if (!flags)
> return -EINVAL;
>
> if (flags & HAS_RENDER_L3CC)
> - arg->l3cc = table;
> + arg->l3cc = &arg->table;
>
> if (flags & (HAS_GLOBAL_MOCS | HAS_ENGINE_MOCS))
> - arg->mocs = table;
> + arg->mocs = &arg->table;
>
> arg->scratch = __vm_create_scratch_for_read(>->ggtt->vm, PAGE_SIZE);
> if (IS_ERR(arg->scratch))
> @@ -130,6 +130,9 @@ static int read_mocs_table(struct i915_request *rq,
> {
> u32 addr;
>
> + if (!table)
> + return 0;
> +
> if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
> addr = global_mocs_offset();
> else
> @@ -144,6 +147,9 @@ static int read_l3cc_table(struct i915_request *rq,
> {
> u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
>
> + if (!table)
> + return 0;
> +
> return read_regs(rq, addr, (table->n_entries + 1) / 2, offset);
> }
>
> @@ -154,6 +160,9 @@ static int check_mocs_table(struct intel_engine_cs
> *engine,
> unsigned int i;
> u32 expect;
>
> + if (!table)
> + return 0;
> +
> for_each_mocs(expect, table, i) {
> if (**vaddr != expect) {
> pr_err("%s: Invalid MOCS[%d] entry, found %08x,
> expected %08x\n",
> @@ -185,6 +194,9 @@ static int check_l3cc_table(struct intel_engine_cs
> *engine,
> unsigned int i;
> u32 expect;
>
> + if (!table)
> + return 0;
> +
> for_each_l3cc(expect, table, i) {
> if (!mcr_range(engine->i915, reg) && **vaddr != expect) {
> pr_err("%s: Invalid L3CC[%d] entry, found %08x,
> expected %08x\n",
> @@ -222,9 +234,9 @@ static int check_mocs_engine(struct live_mocs *arg,
> /* Read the mocs tables back using SRM */
> offset = i915_ggtt_offset(vma);
> if (!err)
> - err = read_mocs_table(rq, &arg->mocs, &offset);
> + err = read_mocs_table(rq, arg->mocs, &offset);
> if (!err && ce->engine->class == RENDER_CLASS)
> - err = read_l3cc_table(rq, &arg->l3cc, &offset);
> + err = read_l3cc_table(rq, arg->l3cc, &offset);
> offset -= i915_ggtt_offset(vma);
> GEM_BUG_ON(offset > PAGE_SIZE);
>
> @@ -235,9 +247,9 @@ static int check_mocs_engine(struct live_mocs *arg,
> /* Compare the results against the expected tables */
> vaddr = arg->vaddr;
> if (!err)
> - err = check_mocs_table(ce->engine, &arg->mocs, &vaddr);
> + err = check_mocs_table(ce->engine, arg->mocs, &vaddr);
> if (!err && ce->engine->class == RENDER_CLASS)
> - err = check_l3cc_table(ce->engine, &arg->l3cc, &vaddr);
> + err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr);
> if (err)
> return err;
>
> --
> 2.20.1
>
> ___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Revert "ALSA: jack: implement software jack injection via debugfs"
== Series Details == Series: Revert "ALSA: jack: implement software jack injection via debugfs" URL : https://patchwork.freedesktop.org/series/86590/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6adf76b93ea8 Revert "ALSA: jack: implement software jack injection via debugfs" -:10: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one -:19: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #19: deleted file mode 100644 -:643: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #643: FILE: sound/core/jack.c:352: + snd_kctl_jack_report(jack->card, jack_kctl->kctl, + status & jack_kctl->mask_bits); -:709: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) total: 1 errors, 2 warnings, 1 checks, 480 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Remove notion of GEM from i915_gem_shrinker_taints_mutex
== Series Details == Series: series starting with [1/2] drm/i915: Remove notion of GEM from i915_gem_shrinker_taints_mutex URL : https://patchwork.freedesktop.org/series/86587/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9718 -> Patchwork_19561 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19561 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19561, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19561/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19561: ### IGT changes ### Possible regressions * igt@i915_module_load@reload: - fi-kbl-r: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19561/fi-kbl-r/igt@i915_module_l...@reload.html Known issues Here are the changes found in Patchwork_19561 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-r: NOTRUN -> [SKIP][2] ([fdo#109271]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19561/fi-kbl-r/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-r: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19561/fi-kbl-r/igt@gem_huc_c...@huc-copy.html * igt@kms_chamelium@hdmi-edid-read: - fi-kbl-r: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19561/fi-kbl-r/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-r: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#533]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19561/fi-kbl-r/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@prime_vgem@basic-read: - fi-tgl-y: [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9718/fi-tgl-y/igt@prime_v...@basic-read.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19561/fi-tgl-y/igt@prime_v...@basic-read.html Possible fixes * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9718/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19561/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html Warnings * igt@runner@aborted: - fi-kbl-r: [FAIL][10] ([i915#1569] / [i915#192] / [i915#193] / [i915#194] / [i915#2295]) -> [FAIL][11] ([i915#2292] / [i915#2426] / [k.org#204565]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9718/fi-kbl-r/igt@run...@aborted.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19561/fi-kbl-r/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2292]: https://gitlab.freedesktop.org/drm/intel/issues/2292 [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [k.org#204565]: https://bugzilla.kernel.org/show_bug.cgi?id=204565 Participating hosts (42 -> 38) -- Missing(4): fi-jsl-1 fi-bsw-cyan fi-bsw-nick fi-bdw-samus Build changes - * Linux: CI_DRM_9718 -> Patchwork_19561 CI-20190529: 20190529 CI_DRM_9718: e123813e002aaa9a6a9d81b0294c93dd1edf9b4f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5988: 4581082c706498cc3afe20e89fc4836a3fc69105 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19561: 249a5647a02ecc41e5e605b6fe63658a12a72b87 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 249a5647a02e drm/i915: Lift marking a lock as used to utils ae8fd4977377 drm/i915: Remove notion of GEM from i915_gem_shrinker_taints_mutex == Logs == For more de
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [CI,01/14] drm/i915/gt: Move engine setup out of set_default_submission (rev2)
== Series Details == Series: series starting with [CI,01/14] drm/i915/gt: Move engine setup out of set_default_submission (rev2) URL : https://patchwork.freedesktop.org/series/86585/ State : failure == Summary == Applying: drm/i915/gt: Move engine setup out of set_default_submission Applying: drm/i915/gt: Move submission_method into intel_gt Applying: drm/i915/gt: Move CS interrupt handler to the backend Applying: drm/i915: Replace engine->schedule() with a known request operation error: sha1 information is lacking or useless (drivers/gpu/drm/i915/gt/intel_execlists_submission.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0004 drm/i915: Replace engine->schedule() with a known request operation When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/57] drm/i915: Take rcu_read_lock for querying fence's driver/timeline names
Chris Wilson writes:
> The name very often may be freed independently of the fence, with the
> only protection being RCU. To be safe as we read the names, hold RCU.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_sw_fence.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c
> b/drivers/gpu/drm/i915/i915_sw_fence.c
> index 2744558f3050..dfabf291e5cd 100644
> --- a/drivers/gpu/drm/i915/i915_sw_fence.c
> +++ b/drivers/gpu/drm/i915/i915_sw_fence.c
> @@ -430,11 +430,13 @@ static void timer_i915_sw_fence_wake(struct timer_list
> *t)
> if (!fence)
> return;
>
> + rcu_read_lock();
> pr_notice("Asynchronous wait on fence %s:%s:%llx timed out
> (hint:%ps)\n",
> cb->dma->ops->get_driver_name(cb->dma),
> cb->dma->ops->get_timeline_name(cb->dma),
> cb->dma->seqno,
> i915_sw_fence_debug_hint(fence));
> + rcu_read_unlock();
>
> i915_sw_fence_set_error_once(fence, -ETIMEDOUT);
> i915_sw_fence_complete(fence);
> --
> 2.20.1
>
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove notion of GEM from i915_gem_shrinker_taints_mutex
== Series Details == Series: drm/i915: Remove notion of GEM from i915_gem_shrinker_taints_mutex URL : https://patchwork.freedesktop.org/series/86586/ State : success == Summary == CI Bug Log - changes from CI_DRM_9718 -> Patchwork_19560 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/index.html Known issues Here are the changes found in Patchwork_19560 that come from known issues: ### IGT changes ### Issues hit * igt@gem_render_tiled_blits@basic: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9718/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html Possible fixes * igt@gem_linear_blits@basic: - fi-tgl-y: [DMESG-WARN][3] ([i915#402]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9718/fi-tgl-y/igt@gem_linear_bl...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/fi-tgl-y/igt@gem_linear_bl...@basic.html [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (42 -> 39) -- Missing(3): fi-jsl-1 fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9718 -> Patchwork_19560 CI-20190529: 20190529 CI_DRM_9718: e123813e002aaa9a6a9d81b0294c93dd1edf9b4f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5988: 4581082c706498cc3afe20e89fc4836a3fc69105 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19560: 140989719221be8e72305c0020f8c3c18c8fc8cb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 140989719221 drm/i915: Remove notion of GEM from i915_gem_shrinker_taints_mutex == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19560/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI 08/14] drm/i915/selftests: Force a rewind if at first we don't succeed
Quoting Tvrtko Ursulin (2021-02-02 16:52:18)
>
> On 02/02/2021 15:14, Chris Wilson wrote:
> > live_timeslice_rewind assumes a particular traversal and reordering
> > after the first timeslice yield. However, the outcome can be either
> > (A1, A2, B1) or (A1, B2, A2) depending on the path taken through the
> > dependency graph. So if we do not get the outcome we need at first, give
> > it a priority kick to force a rewind.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/gt/selftest_execlists.c | 21 +++-
> > 1 file changed, 20 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
> > b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> > index 951e2bf867e1..68e1398704a4 100644
> > --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
> > +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> > @@ -1107,6 +1107,7 @@ static int live_timeslice_rewind(void *arg)
> > struct i915_request *rq[3] = {};
> > struct intel_context *ce;
> > unsigned long timeslice;
> > + unsigned long timeout;
> > int i, err = 0;
> > u32 *slot;
> >
> > @@ -1173,11 +1174,29 @@ static int live_timeslice_rewind(void *arg)
> >
> > /* ELSP[] = { { A:rq1, A:rq2 }, { B:rq1 } } */
> > ENGINE_TRACE(engine, "forcing tasklet for rewind\n");
> > - while (i915_request_is_active(rq[A2])) { /* semaphore yield!
> > */
> > + i = 0;
> > + timeout = jiffies + HZ;
> > + while (i915_request_is_active(rq[A2]) &&
> > +time_before(jiffies, timeout)) { /* semaphore yield! */
> > /* Wait for the timeslice to kick in */
> > del_timer(&engine->execlists.timer);
> > tasklet_hi_schedule(&engine->execlists.tasklet);
> > intel_engine_flush_submission(engine);
> > +
> > + /*
> > + * Unfortunately this assumes that during the
> > + * search of the wait tree it sees the requests
> > + * in a particular order. That order is not
> > + * strictly determined and it may pick either
> > + * A2 or B1 to immediately follow A1.
> > + *
> > + * Break the tie with a set-priority. This defeats
> > + * the goal of trying to cause a rewind with a
> > + * timeslice, but alas, a rewind is better than
> > + * none.
> > + */
> > + if (i++)
> > + i915_request_set_priority(rq[B1], 1);
> > }
> > /* -> ELSP[] = { { A:rq1 }, { B:rq1 } } */
> > GEM_BUG_ON(!i915_request_is_active(rq[A1]));
> >
>
> Didn't fully get the intricacies of the test, but, how about not messing
> with priorities but just kicking it for longer until it eventually
> re-orders to the desired sequence? Surely if it keeps insisting of the
> same order which is making no progress there is a flaw in timeslicing
> anyway? Or if it fails skip the test.
Ah. The test is trying to prove internals of the ELSP[] behave in a
certain manner without forcing it to. However, there's no requirement
for it to do anything of the sort.
[What is the test trying to prove? That on timeslice we are capable of
removing a request from an earlier context to allow early switching to a
second context. This requires us to force the context switch to prevent
the currently executing context from keeping its RING_TAIL (which points
at the A2) but resample it so that it ends at A1. We attempt to prove
that with independent spinners, if we don't reset A2 then it will remain
executing instead of switching to B2 as we expect.]
So what happens is that we queue
[{A1, A2}, {B1}]
trigger a timeslice [by forcing the timer expiry]
and expect us to rearrange ELSP
as [{A1}, {B2}]
because B2 depends on A1, on every timeslice that pair must be in that
order.
And we are looking for A2 to be back in the queue.
Since A2 has no dependency on B2, and vice versa that is a free
variable. Everytime we walk the graph, we start with deferring
A1, then A2, then B2. Looking at the graph in the same order everytime,
and end up packing {A1, A2} together into the same context submission.
You are right that if we allowed A1 to finish, then the timeslicing would
reverse A2, B2. However, we don't let spinner A1 finish so everything
stays in the same order.
Hmm. The problem is the graph order is determined by order of
construction. Now, we are free to randomise the order of that graph,
though we need to take different locks. Even if we just cycle the graph
one element (that would be enough to break the repetition here, we still
need that lock). Hmm.
The other option is to change the order of
Re: [Intel-gfx] [CI 07/14] drm/i915/selftests: Exercise priority inheritance around an engine loop
Quoting Tvrtko Ursulin (2021-02-02 16:44:26)
>
> On 02/02/2021 15:14, Chris Wilson wrote:
> > + err = 0;
> > + count = 0;
> > + for_each_uabi_engine(engine, i915) {
> > + if (!intel_engine_has_scheduler(engine))
> > + continue;
> > +
> > + rq = __write_timestamp(engine, obj, count, rq);
> > + if (IS_ERR(rq)) {
> > + err = PTR_ERR(rq);
> > + break;
> > + }
> > +
> > + count++;
> > + }
>
> - two of the same by copy&paste error or couldn't be bothered
> with outer loop?
It was just my thought process at the time, I wanted the
A->Z; A->Z pair so that it clear that it was cyclic and just didn't
think of putting it inside another loop.
-Chris
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Re: [Intel-gfx] [CI 08/14] drm/i915/selftests: Force a rewind if at first we don't succeed
On 02/02/2021 15:14, Chris Wilson wrote:
live_timeslice_rewind assumes a particular traversal and reordering
after the first timeslice yield. However, the outcome can be either
(A1, A2, B1) or (A1, B2, A2) depending on the path taken through the
dependency graph. So if we do not get the outcome we need at first, give
it a priority kick to force a rewind.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 21 +++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 951e2bf867e1..68e1398704a4 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -1107,6 +1107,7 @@ static int live_timeslice_rewind(void *arg)
struct i915_request *rq[3] = {};
struct intel_context *ce;
unsigned long timeslice;
+ unsigned long timeout;
int i, err = 0;
u32 *slot;
@@ -1173,11 +1174,29 @@ static int live_timeslice_rewind(void *arg)
/* ELSP[] = { { A:rq1, A:rq2 }, { B:rq1 } } */
ENGINE_TRACE(engine, "forcing tasklet for rewind\n");
- while (i915_request_is_active(rq[A2])) { /* semaphore yield! */
+ i = 0;
+ timeout = jiffies + HZ;
+ while (i915_request_is_active(rq[A2]) &&
+ time_before(jiffies, timeout)) { /* semaphore yield! */
/* Wait for the timeslice to kick in */
del_timer(&engine->execlists.timer);
tasklet_hi_schedule(&engine->execlists.tasklet);
intel_engine_flush_submission(engine);
+
+ /*
+* Unfortunately this assumes that during the
+* search of the wait tree it sees the requests
+* in a particular order. That order is not
+* strictly determined and it may pick either
+* A2 or B1 to immediately follow A1.
+*
+* Break the tie with a set-priority. This defeats
+* the goal of trying to cause a rewind with a
+* timeslice, but alas, a rewind is better than
+* none.
+*/
+ if (i++)
+ i915_request_set_priority(rq[B1], 1);
}
/* -> ELSP[] = { { A:rq1 }, { B:rq1 } } */
GEM_BUG_ON(!i915_request_is_active(rq[A1]));
Didn't fully get the intricacies of the test, but, how about not messing
with priorities but just kicking it for longer until it eventually
re-orders to the desired sequence? Surely if it keeps insisting of the
same order which is making no progress there is a flaw in timeslicing
anyway? Or if it fails skip the test.
Regards,
Tvrtko
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Re: [Intel-gfx] [CI 06/14] drm/i915/selftests: Measure set-priority duration
On 02/02/2021 15:14, Chris Wilson wrote:
As a topological sort, we expect it to run in linear graph time,
O(V+E). In removing the recursion, it is no longer a DFS but rather a
BFS, and performs as O(VE). Let's demonstrate how bad this is with a few
examples, and build a few test cases to verify a potential fix.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_scheduler.c | 4 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/i915_perf_selftests.h | 1 +
.../gpu/drm/i915/selftests/i915_scheduler.c | 672 ++
4 files changed, 678 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_scheduler.c
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 035e4be5d573..27bda7617b29 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -609,6 +609,10 @@ void i915_request_show_with_schedule(struct drm_printer *m,
rcu_read_unlock();
}
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/i915_scheduler.c"
+#endif
+
static void i915_global_scheduler_shrink(void)
{
kmem_cache_shrink(global.slab_dependencies);
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index a92c0e9b7e6b..2200a5baa68e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -26,6 +26,7 @@ selftest(gt_mocs, intel_mocs_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
selftest(gt_heartbeat, intel_heartbeat_live_selftests)
selftest(requests, i915_request_live_selftests)
+selftest(scheduler, i915_scheduler_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
selftest(mman, i915_gem_mman_live_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
index c2389f8a257d..137e35283fee 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
@@ -17,5 +17,6 @@
*/
selftest(engine_cs, intel_engine_cs_perf_selftests)
selftest(request, i915_request_perf_selftests)
+selftest(scheduler, i915_scheduler_perf_selftests)
selftest(blt, i915_gem_object_blt_perf_selftests)
selftest(region, intel_memory_region_perf_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
new file mode 100644
index ..d095fab2ccec
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
@@ -0,0 +1,672 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_selftest.h"
+
+#include "gt/intel_context.h"
+#include "gt/intel_gpu_commands.h"
+#include "gt/selftest_engine_heartbeat.h"
+#include "selftests/igt_spinner.h"
+#include "selftests/i915_random.h"
+
+static void scheduling_disable(struct intel_engine_cs *engine)
+{
+ engine->props.preempt_timeout_ms = 0;
+ engine->props.timeslice_duration_ms = 0;
+
+ st_engine_heartbeat_disable(engine);
+}
+
+static void scheduling_enable(struct intel_engine_cs *engine)
+{
+ st_engine_heartbeat_enable(engine);
+
+ engine->props.preempt_timeout_ms =
+ engine->defaults.preempt_timeout_ms;
+ engine->props.timeslice_duration_ms =
+ engine->defaults.timeslice_duration_ms;
+}
+
+static int first_engine(struct drm_i915_private *i915,
+ int (*chain)(struct intel_engine_cs *engine,
+unsigned long param,
+bool (*fn)(struct i915_request *rq,
+ unsigned long v,
+ unsigned long e)),
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ if (!intel_engine_has_scheduler(engine))
+ continue;
+
+ return chain(engine, param, fn);
+ }
+
+ return 0;
+}
+
+static int all_engines(struct drm_i915_private *i915,
+ int (*chain)(struct intel_engine_cs *engine,
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v,
+ unsigned long e)),
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_engine_cs *engine;
+
Re: [Intel-gfx] [CI 07/14] drm/i915/selftests: Exercise priority inheritance around an engine loop
On 02/02/2021 15:14, Chris Wilson wrote:
Exercise rescheduling priority inheritance around a sequence of requests
that wrap around all the engines.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/selftests/i915_scheduler.c | 225 ++
1 file changed, 225 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
index d095fab2ccec..acc666f755d7 100644
--- a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
@@ -7,6 +7,7 @@
#include "gt/intel_context.h"
#include "gt/intel_gpu_commands.h"
+#include "gt/intel_ring.h"
#include "gt/selftest_engine_heartbeat.h"
#include "selftests/igt_spinner.h"
#include "selftests/i915_random.h"
@@ -504,10 +505,234 @@ static int igt_priority_chains(void *arg)
return igt_schedule_chains(arg, igt_priority);
}
+static struct i915_request *
+__write_timestamp(struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *obj,
+ int slot,
+ struct i915_request *prev)
+{
+ struct i915_request *rq = ERR_PTR(-EINVAL);
+ bool use_64b = INTEL_GEN(engine->i915) >= 8;
+ struct intel_context *ce;
+ struct i915_vma *vma;
+ int err = 0;
+ u32 *cs;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return ERR_CAST(ce);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_ce;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto out_ce;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unpin;
+ }
+
+ i915_vma_lock(vma);
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+ if (err)
+ goto out_request;
+
+ if (prev) {
+ err = i915_request_await_dma_fence(rq, &prev->fence);
+ if (err)
+ goto out_request;
+ }
+
+ if (engine->emit_init_breadcrumb) {
+ err = engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_request;
+ }
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto out_request;
+ }
+
+ *cs++ = MI_STORE_REGISTER_MEM + use_64b;
+ *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base));
+ *cs++ = lower_32_bits(vma->node.start) + sizeof(u32) * slot;
+ *cs++ = upper_32_bits(vma->node.start);
+ intel_ring_advance(rq, cs);
+
+ i915_request_get(rq);
+out_request:
+ i915_request_add(rq);
+out_unpin:
+ i915_vma_unpin(vma);
+out_ce:
+ intel_context_put(ce);
+ i915_request_put(prev);
+ return err ? ERR_PTR(err) : rq;
+}
+
+static struct i915_request *create_spinner(struct drm_i915_private *i915,
+ struct igt_spinner *spin)
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ struct intel_context *ce;
+ struct i915_request *rq;
+
+ if (igt_spinner_init(spin, engine->gt))
+ return ERR_PTR(-ENOMEM);
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return ERR_CAST(ce);
+
+ rq = igt_spinner_create_request(spin, ce, MI_NOOP);
+ intel_context_put(ce);
+ if (rq == ERR_PTR(-ENODEV))
+ continue;
+ if (IS_ERR(rq))
+ return rq;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ return rq;
+ }
+
+ return ERR_PTR(-ENODEV);
+}
+
+static bool has_timestamp(const struct drm_i915_private *i915)
+{
+ return INTEL_GEN(i915) >= 7;
+}
+
+static int __igt_schedule_cycle(struct drm_i915_private *i915,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_engine_cs *engine;
+ struct drm_i915_gem_object *obj;
+ struct igt_spinner spin;
+ struct i915_request *rq;
+ unsigned long count, n;
+ u32 *time, last;
+ int err;
+
+ /*
+* Queue a bunch of ordered requests (each waiting on the previous)
+* around the engines a couple of times. Each request will write
+* the timestamp it executes at into the scratch, with the expectation
+* that the timestamp will be in our desired execution order.
+*/
+
+ if (!i915->caps.scheduler || !has_timestamp(i915))
+ return 0;
+
+ obj = i915_gem_object_create_internal(i915, SZ
Re: [Intel-gfx] [PATCH v2] drm/i915/gt: Move CS interrupt handler to the backend
On 02/02/2021 16:15, Chris Wilson wrote:
The different submission backends each have their own preferred
behaviour and interrupt setup. Let each handle their own interrupts.
This becomes more useful later as we to extract the use of auxiliary
state in the interrupt handler that is backend specific.
v2: An overabundance of caution is always justified; put a barrier on
updating the irq handler so that we know that the next interrupt will
be redirected towards ourselves.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +---
.../drm/i915/gt/intel_execlists_submission.c | 40 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c| 82 ++-
drivers/gpu/drm/i915/gt/intel_gt_irq.h| 22 +
.../gpu/drm/i915/gt/intel_ring_submission.c | 7 ++
drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 ++-
drivers/gpu/drm/i915/i915_irq.c | 8 +-
9 files changed, 118 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c7d17f8767a1..e06ae4ae1710 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -255,6 +255,11 @@ static void intel_engine_sanitize_mmio(struct
intel_engine_cs *engine)
intel_engine_set_hwsp_writemask(engine, ~0u);
}
+static void nop_irq_handler(struct intel_engine_cs *engine, u32 iir)
+{
+ GEM_DEBUG_WARN_ON(iir);
+}
+
static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
{
const struct engine_info *info = &intel_engines[id];
@@ -292,6 +297,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
engine->hw_id = info->hw_id;
engine->guc_id = MAKE_GUC_ID(info->class, info->instance);
+ engine->irq_handler = nop_irq_handler;
+
engine->class = info->class;
engine->instance = info->instance;
__sprint_engine_name(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 9d59de5c559a..7fd035d45263 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -402,6 +402,7 @@ struct intel_engine_cs {
u32 irq_enable_mask; /* bitmask to enable ring interrupt */
void(*irq_enable)(struct intel_engine_cs *engine);
void(*irq_disable)(struct intel_engine_cs *engine);
+ void(*irq_handler)(struct intel_engine_cs *engine, u32 iir);
void (*sanitize)(struct intel_engine_cs *engine);
int (*resume)(struct intel_engine_cs *engine);
@@ -481,10 +482,9 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_PREEMPTION BIT(2)
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
#define I915_ENGINE_HAS_TIMESLICES BIT(4)
-#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5)
-#define I915_ENGINE_IS_VIRTUAL BIT(6)
-#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)
-#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)
+#define I915_ENGINE_IS_VIRTUAL BIT(5)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
+#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
unsigned int flags;
/*
@@ -588,12 +588,6 @@ intel_engine_has_timeslices(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_HAS_TIMESLICES;
}
-static inline bool
-intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
-{
- return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
-}
-
static inline bool
intel_engine_is_virtual(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 4ddd2099a931..05846f97f1af 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2394,6 +2394,45 @@ static void execlists_submission_tasklet(struct
tasklet_struct *t)
rcu_read_unlock();
}
+static void execlists_irq_handler(struct intel_engine_cs *engine, u32 iir)
+{
+ bool tasklet = false;
+
+ if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
+ u32 eir;
+
+ /* Upper 16b are the enabling mask, rsvd for internal errors */
+ eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0);
+ ENGINE_TRACE(engine, "CS error: %x\n", eir);
+
+ /* Disable the error interrupt until after the reset */
+ if (likely(eir)) {
+ ENGINE_WRITE(engine, RING_EMR, ~0u);
+ ENGINE_WRITE(engine, RING_EIR, eir);
+ WRITE_ONCE(engine->execlists.error_interrupt, eir);
+ tasklet = true;
+
[Intel-gfx] [CI] Revert "ALSA: jack: implement software jack injection via debugfs"
This reverts commit 2d670ea2bd53a9792f453bb5b97cb8ef695988ff. --- Documentation/sound/designs/index.rst | 1 - .../sound/designs/jack-injection.rst | 166 -- include/sound/core.h | 6 - include/sound/jack.h | 1 - sound/core/Kconfig| 9 - sound/core/init.c | 16 - sound/core/jack.c | 304 +- sound/core/sound.c| 13 - 8 files changed, 4 insertions(+), 512 deletions(-) delete mode 100644 Documentation/sound/designs/jack-injection.rst diff --git a/Documentation/sound/designs/index.rst b/Documentation/sound/designs/index.rst index 1eb08e7bae52..f0749943ccb2 100644 --- a/Documentation/sound/designs/index.rst +++ b/Documentation/sound/designs/index.rst @@ -14,4 +14,3 @@ Designs and Implementations powersave oss-emulation seq-oss - jack-injection diff --git a/Documentation/sound/designs/jack-injection.rst b/Documentation/sound/designs/jack-injection.rst deleted file mode 100644 index f9790521523e.. --- a/Documentation/sound/designs/jack-injection.rst +++ /dev/null @@ -1,166 +0,0 @@ - -ALSA Jack Software Injection - - -Simple Introduction On Jack Injection -= - -Here jack injection means users could inject plugin or plugout events -to the audio jacks through debugfs interface, it is helpful to -validate ALSA userspace changes. For example, we change the audio -profile switching code in the pulseaudio, and we want to verify if the -change works as expected and if the change introduce the regression, -in this case, we could inject plugin or plugout events to an audio -jack or to some audio jacks, we don't need to physically access the -machine and plug/unplug physical devices to the audio jack. - -In this design, an audio jack doesn't equal to a physical audio jack. -Sometimes a physical audio jack contains multi functions, and the -ALSA driver creates multi ``jack_kctl`` for a ``snd_jack``, here the -``snd_jack`` represents a physical audio jack and the ``jack_kctl`` -represents a function, for example a physical jack has two functions: -headphone and mic_in, the ALSA ASoC driver will build 2 ``jack_kctl`` -for this jack. The jack injection is implemented based on the -``jack_kctl`` instead of ``snd_jack``. - -To inject events to audio jacks, we need to enable the jack injection -via ``sw_inject_enable`` first, once it is enabled, this jack will not -change the state by hardware events anymore, we could inject plugin or -plugout events via ``jackin_inject`` and check the jack state via -``status``, after we finish our test, we need to disable the jack -injection via ``sw_inject_enable`` too, once it is disabled, the jack -state will be restored according to the last reported hardware events -and will change by future hardware events. - -The Layout of Jack Injection Interface -== - -If users enable the SND_JACK_INJECTION_DEBUG in the kernel, the audio -jack injection interface will be created as below: -:: - - $debugfs_mount_dir/sound - |-- card0 - |-- |-- HDMI_DP_pcm_10_Jack - |-- |-- |-- jackin_inject - |-- |-- |-- kctl_id - |-- |-- |-- mask_bits - |-- |-- |-- status - |-- |-- |-- sw_inject_enable - |-- |-- |-- type - ... - |-- |-- HDMI_DP_pcm_9_Jack - |-- |-- jackin_inject - |-- |-- kctl_id - |-- |-- mask_bits - |-- |-- status - |-- |-- sw_inject_enable - |-- |-- type - |-- card1 - |-- HDMI_DP_pcm_5_Jack - |-- |-- jackin_inject - |-- |-- kctl_id - |-- |-- mask_bits - |-- |-- status - |-- |-- sw_inject_enable - |-- |-- type - ... - |-- Headphone_Jack - |-- |-- jackin_inject - |-- |-- kctl_id - |-- |-- mask_bits - |-- |-- status - |-- |-- sw_inject_enable - |-- |-- type - |-- Headset_Mic_Jack - |-- jackin_inject - |-- kctl_id - |-- mask_bits - |-- status - |-- sw_inject_enable - |-- type - -The Explanation Of The Nodes -== - -kctl_id - read-only, get jack_kctl->kctl's id - :: - - sound/card1/Headphone_Jack# cat kctl_id - Headphone Jack - -mask_bits - read-only, get jack_kctl's supported events mask_bits - :: - - sound/card1/Headphone_Jack# cat mask_bits - 0x0001 HEADPHONE(0x0001) - -status - read-only, get jack_kctl's current status - -- headphone unplugged: - - :: - - sound/card1/Headphone_Jack# cat status - Unplugged - -- headphone plugged: - - :: - - sound/card1/Headphone_Jack# cat status - Plugged - -type - read-only, get snd_jack's supported events from type (all supported events on the physical audio jack) - :: - - sound/card1/Headphone_Jack# cat type
[Intel-gfx] [PATCH v2] drm/i915/gt: Move CS interrupt handler to the backend
The different submission backends each have their own preferred
behaviour and interrupt setup. Let each handle their own interrupts.
This becomes more useful later as we to extract the use of auxiliary
state in the interrupt handler that is backend specific.
v2: An overabundance of caution is always justified; put a barrier on
updating the irq handler so that we know that the next interrupt will
be redirected towards ourselves.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +---
.../drm/i915/gt/intel_execlists_submission.c | 40 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c| 82 ++-
drivers/gpu/drm/i915/gt/intel_gt_irq.h| 22 +
.../gpu/drm/i915/gt/intel_ring_submission.c | 7 ++
drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 ++-
drivers/gpu/drm/i915/i915_irq.c | 8 +-
9 files changed, 118 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c7d17f8767a1..e06ae4ae1710 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -255,6 +255,11 @@ static void intel_engine_sanitize_mmio(struct
intel_engine_cs *engine)
intel_engine_set_hwsp_writemask(engine, ~0u);
}
+static void nop_irq_handler(struct intel_engine_cs *engine, u32 iir)
+{
+ GEM_DEBUG_WARN_ON(iir);
+}
+
static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
{
const struct engine_info *info = &intel_engines[id];
@@ -292,6 +297,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
engine->hw_id = info->hw_id;
engine->guc_id = MAKE_GUC_ID(info->class, info->instance);
+ engine->irq_handler = nop_irq_handler;
+
engine->class = info->class;
engine->instance = info->instance;
__sprint_engine_name(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 9d59de5c559a..7fd035d45263 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -402,6 +402,7 @@ struct intel_engine_cs {
u32 irq_enable_mask; /* bitmask to enable ring interrupt */
void(*irq_enable)(struct intel_engine_cs *engine);
void(*irq_disable)(struct intel_engine_cs *engine);
+ void(*irq_handler)(struct intel_engine_cs *engine, u32 iir);
void(*sanitize)(struct intel_engine_cs *engine);
int (*resume)(struct intel_engine_cs *engine);
@@ -481,10 +482,9 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_PREEMPTION BIT(2)
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
#define I915_ENGINE_HAS_TIMESLICES BIT(4)
-#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5)
-#define I915_ENGINE_IS_VIRTUAL BIT(6)
-#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)
-#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)
+#define I915_ENGINE_IS_VIRTUAL BIT(5)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
+#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
unsigned int flags;
/*
@@ -588,12 +588,6 @@ intel_engine_has_timeslices(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_HAS_TIMESLICES;
}
-static inline bool
-intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
-{
- return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
-}
-
static inline bool
intel_engine_is_virtual(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 4ddd2099a931..05846f97f1af 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2394,6 +2394,45 @@ static void execlists_submission_tasklet(struct
tasklet_struct *t)
rcu_read_unlock();
}
+static void execlists_irq_handler(struct intel_engine_cs *engine, u32 iir)
+{
+ bool tasklet = false;
+
+ if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
+ u32 eir;
+
+ /* Upper 16b are the enabling mask, rsvd for internal errors */
+ eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0);
+ ENGINE_TRACE(engine, "CS error: %x\n", eir);
+
+ /* Disable the error interrupt until after the reset */
+ if (likely(eir)) {
+ ENGINE_WRITE(engine, RING_EMR, ~0u);
+ ENGINE_WRITE(engine, RING_EIR, eir);
+ WRITE_ONCE(engine->execlists.error_interrupt, eir);
+ tasklet = true;
+ }
+ }
+
+ if (iir & GT_WAIT_SEMAPHOR
Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
On Tue, Feb 02, 2021 at 08:59:20AM +, Surendrakumar Upadhyay, TejaskumarX
wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: 02 February 2021 12:42
> > To: Surendrakumar Upadhyay, TejaskumarX
> >
> > Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> >
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during
> > suspend/resume
> >
> > On Tue, Feb 02, 2021 at 08:31:48AM +0200, Ville Syrjälä wrote:
> > > On Tue, Feb 02, 2021 at 05:52:28AM +, Surendrakumar Upadhyay,
> > TejaskumarX wrote:
> > > >
> > > >
> > > > > -Original Message-
> > > > > From: Ville Syrjälä
> > > > > Sent: 28 January 2021 04:46
> > > > > To: Surendrakumar Upadhyay, TejaskumarX
> > > > >
> > > > > Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> > > > > ; Roper, Matthew D
> > > > >
> > > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH
> > > > > during suspend/resume
> > > > >
> > > > > On Wed, Jan 27, 2021 at 03:38:30PM +0530, Tejas Upadhyay wrote:
> > > > > > For Legacy S3 suspend/resume GEN9 BC needs to enable and setup
> > > > > > TGP PCH.
> > > > > >
> > > > > > Cc: Matt Roper
> > > > > > Signed-off-by: Tejas Upadhyay
> > > > > >
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/i915_irq.c | 36
> > > > > > -
> > > > > > 1 file changed, 27 insertions(+), 9 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > b/drivers/gpu/drm/i915/i915_irq.c index
> > > > > > a31980f69120..6dcefc3e24ac
> > > > > > 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > @@ -3026,8 +3026,20 @@ static void gen8_irq_reset(struct
> > > > > > drm_i915_private *dev_priv)
> > > > > > GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > > > > > GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> > > > > >
> > > > > > - if (HAS_PCH_SPLIT(dev_priv))
> > > > > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > > > > + GEN3_IRQ_RESET(uncore, SDE);
> > > > > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > > > > ibx_irq_reset(dev_priv);
> > > > > > +
> > > > > > + /* Wa_14010685332:cnp/cmp,tgp,adp */
> > > > > > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > > > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > > > > + INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > > > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > > > > +SBCLK_RUN_REFCLK_DIS,
> > > > > > SBCLK_RUN_REFCLK_DIS);
> > > > > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > > > > +SBCLK_RUN_REFCLK_DIS, 0);
> > > > > > + }
> > > > >
> > > > > Time to refactor instead of copypasta.
> > > > Do you expect below? :
> > > >
> > > > If ((INTEL_PCH_TYPE(dev_priv) == PCH_TGP) {
> > > > intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > > SBCLK_RUN_REFCLK_DIS,
> > > > SBCLK_RUN_REFCLK_DIS);
> > > > intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > > SBCLK_RUN_REFCLK_DIS, 0);
> > > > }
> > >
> > > I expect a new function instead of copy pasting this whole thing into
> > > multiple places.
> > >
> > > That said even the current code doesn't make any sense to me.
> > > Take for instance this part:
> > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > GEN3_IRQ_RESET(uncore, SDE); What is that PCH type
> > > check doing there? What weird PCH type are we supposed to have that
> > > doesn't need this?
> > >
> > > Also the Wa_14010685332 part looks a bit odd. Is it correct that icp
> > > doesn't need that, but cnp and tgp both do somehow? Can we even have
> > > cnp on icl+?
> >
> > Hmm. Looking at it a bit more, that w/a seems to have something to do with
> > suspend/resume, so seems rather misplaced in irq_reset(). Should probably
> > just move the whole thing into a more appropriate place.
> >
> GEN11+ needs these checks in irq_reset(). Please check irq_reset for
> GEN11. Now that customer like dell are expecting TGP PCH with gen9bc
> platforms, I have done similar PCH checking in irq_reset() for gen9bc.
> You mean these checks are at wrong place for GEN11 irq_reset() as
> well? Or you want one function doing these checks and calling it
> everywhere!
BSpec says about this WA for both ICL and TGL:
"""
Display driver should set and clear register offset 0xC2000 bit #7 as
last step in programming south display registers in preparation for
entering S0ix state, or set 0xC2000 bit #7 on S0ix entry and clear it on
S0ix exit.
"""
This means to me the WA is only relevant for S0ix and we can implement
it by setting/clearing 0xC2000 bit #7 right before entering/right after
exiting S0ix. This is done atm on PCH_ICP..PCH_MCC in
intel_display_power_suspend_late()/intel_display_power_resume_early(),
so I'd move the WA for all platforms there.
I assume the current code in irq_reset(
Re: [Intel-gfx] [CI 03/14] drm/i915/gt: Move CS interrupt handler to the backend
Quoting Chris Wilson (2021-02-02 15:53:41)
> Quoting Tvrtko Ursulin (2021-02-02 15:49:59)
> >
> > On 02/02/2021 15:14, Chris Wilson wrote:
> > > The different submission backends each have their own preferred
> > > behaviour and interrupt setup. Let each handle their own interrupts.
> > >
> > > This becomes more useful later as we to extract the use of auxiliary
> > > state in the interrupt handler that is backend specific.
> > >
> > > Signed-off-by: Chris Wilson
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++
> > > drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +---
> > > .../drm/i915/gt/intel_execlists_submission.c | 40 +
> > > drivers/gpu/drm/i915/gt/intel_gt_irq.c| 82 ++-
> > > drivers/gpu/drm/i915/gt/intel_gt_irq.h| 7 ++
> > > .../gpu/drm/i915/gt/intel_ring_submission.c | 7 ++
> > > drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
> > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 ++-
> > > drivers/gpu/drm/i915/i915_irq.c | 8 +-
> > > 9 files changed, 103 insertions(+), 74 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > index dab8d734e272..2a453ba5f25a 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > @@ -255,6 +255,11 @@ static void intel_engine_sanitize_mmio(struct
> > > intel_engine_cs *engine)
> > > intel_engine_set_hwsp_writemask(engine, ~0u);
> > > }
> > >
> > > +static void nop_irq_handler(struct intel_engine_cs *engine, u32 iir)
> > > +{
> > > + GEM_DEBUG_WARN_ON(iir);
> > > +}
> > > +
> > > static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id
> > > id)
> > > {
> > > const struct engine_info *info = &intel_engines[id];
> > > @@ -292,6 +297,8 @@ static int intel_engine_setup(struct intel_gt *gt,
> > > enum intel_engine_id id)
> > > engine->hw_id = info->hw_id;
> > > engine->guc_id = MAKE_GUC_ID(info->class, info->instance);
> > >
> > > + engine->irq_handler = nop_irq_handler;
> > > +
> > > engine->class = info->class;
> > > engine->instance = info->instance;
> > > __sprint_engine_name(engine);
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > index 9d59de5c559a..7fd035d45263 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > @@ -402,6 +402,7 @@ struct intel_engine_cs {
> > > u32 irq_enable_mask; /* bitmask to enable ring
> > > interrupt */
> > > void(*irq_enable)(struct intel_engine_cs *engine);
> > > void(*irq_disable)(struct intel_engine_cs *engine);
> > > + void(*irq_handler)(struct intel_engine_cs *engine, u32
> > > iir);
> > >
> > > void(*sanitize)(struct intel_engine_cs *engine);
> > > int (*resume)(struct intel_engine_cs *engine);
> > > @@ -481,10 +482,9 @@ struct intel_engine_cs {
> > > #define I915_ENGINE_HAS_PREEMPTION BIT(2)
> > > #define I915_ENGINE_HAS_SEMAPHORES BIT(3)
> > > #define I915_ENGINE_HAS_TIMESLICES BIT(4)
> > > -#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5)
> > > -#define I915_ENGINE_IS_VIRTUAL BIT(6)
> > > -#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)
> > > -#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)
> > > +#define I915_ENGINE_IS_VIRTUAL BIT(5)
> > > +#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
> > > +#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
> > > unsigned int flags;
> > >
> > > /*
> > > @@ -588,12 +588,6 @@ intel_engine_has_timeslices(const struct
> > > intel_engine_cs *engine)
> > > return engine->flags & I915_ENGINE_HAS_TIMESLICES;
> > > }
> > >
> > > -static inline bool
> > > -intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs
> > > *engine)
> > > -{
> > > - return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
> > > -}
> > > -
> > > static inline bool
> > > intel_engine_is_virtual(const struct intel_engine_cs *engine)
> > > {
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > index 4ddd2099a931..ed62e4b549d2 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > @@ -2394,6 +2394,45 @@ static void execlists_submission_tasklet(struct
> > > tasklet_struct *t)
> > > rcu_read_unlock();
> > > }
> > >
> > > +static void execlists_irq_handler(struct intel_engine_cs *engine, u32
> > > iir)
> > > +{
> > > + bool tasklet = false;
> > > +
> > > + if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
> > > + u32 eir;
> > > +
> > > + /* Upper 16b
Re: [Intel-gfx] [CI 03/14] drm/i915/gt: Move CS interrupt handler to the backend
Quoting Tvrtko Ursulin (2021-02-02 15:49:59)
>
> On 02/02/2021 15:14, Chris Wilson wrote:
> > The different submission backends each have their own preferred
> > behaviour and interrupt setup. Let each handle their own interrupts.
> >
> > This becomes more useful later as we to extract the use of auxiliary
> > state in the interrupt handler that is backend specific.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++
> > drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +---
> > .../drm/i915/gt/intel_execlists_submission.c | 40 +
> > drivers/gpu/drm/i915/gt/intel_gt_irq.c| 82 ++-
> > drivers/gpu/drm/i915/gt/intel_gt_irq.h| 7 ++
> > .../gpu/drm/i915/gt/intel_ring_submission.c | 7 ++
> > drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 ++-
> > drivers/gpu/drm/i915/i915_irq.c | 8 +-
> > 9 files changed, 103 insertions(+), 74 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index dab8d734e272..2a453ba5f25a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -255,6 +255,11 @@ static void intel_engine_sanitize_mmio(struct
> > intel_engine_cs *engine)
> > intel_engine_set_hwsp_writemask(engine, ~0u);
> > }
> >
> > +static void nop_irq_handler(struct intel_engine_cs *engine, u32 iir)
> > +{
> > + GEM_DEBUG_WARN_ON(iir);
> > +}
> > +
> > static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id
> > id)
> > {
> > const struct engine_info *info = &intel_engines[id];
> > @@ -292,6 +297,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum
> > intel_engine_id id)
> > engine->hw_id = info->hw_id;
> > engine->guc_id = MAKE_GUC_ID(info->class, info->instance);
> >
> > + engine->irq_handler = nop_irq_handler;
> > +
> > engine->class = info->class;
> > engine->instance = info->instance;
> > __sprint_engine_name(engine);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > index 9d59de5c559a..7fd035d45263 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > @@ -402,6 +402,7 @@ struct intel_engine_cs {
> > u32 irq_enable_mask; /* bitmask to enable ring interrupt
> > */
> > void(*irq_enable)(struct intel_engine_cs *engine);
> > void(*irq_disable)(struct intel_engine_cs *engine);
> > + void(*irq_handler)(struct intel_engine_cs *engine, u32
> > iir);
> >
> > void(*sanitize)(struct intel_engine_cs *engine);
> > int (*resume)(struct intel_engine_cs *engine);
> > @@ -481,10 +482,9 @@ struct intel_engine_cs {
> > #define I915_ENGINE_HAS_PREEMPTION BIT(2)
> > #define I915_ENGINE_HAS_SEMAPHORES BIT(3)
> > #define I915_ENGINE_HAS_TIMESLICES BIT(4)
> > -#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5)
> > -#define I915_ENGINE_IS_VIRTUAL BIT(6)
> > -#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)
> > -#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)
> > +#define I915_ENGINE_IS_VIRTUAL BIT(5)
> > +#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
> > +#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
> > unsigned int flags;
> >
> > /*
> > @@ -588,12 +588,6 @@ intel_engine_has_timeslices(const struct
> > intel_engine_cs *engine)
> > return engine->flags & I915_ENGINE_HAS_TIMESLICES;
> > }
> >
> > -static inline bool
> > -intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
> > -{
> > - return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
> > -}
> > -
> > static inline bool
> > intel_engine_is_virtual(const struct intel_engine_cs *engine)
> > {
> > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > index 4ddd2099a931..ed62e4b549d2 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > @@ -2394,6 +2394,45 @@ static void execlists_submission_tasklet(struct
> > tasklet_struct *t)
> > rcu_read_unlock();
> > }
> >
> > +static void execlists_irq_handler(struct intel_engine_cs *engine, u32 iir)
> > +{
> > + bool tasklet = false;
> > +
> > + if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
> > + u32 eir;
> > +
> > + /* Upper 16b are the enabling mask, rsvd for internal errors
> > */
> > + eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0);
> > + ENGINE_TRACE(engine, "CS error: %x\n", eir);
> > +
> > + /* Disable the error interrupt until after the reset */
> > +
Re: [Intel-gfx] [CI 03/14] drm/i915/gt: Move CS interrupt handler to the backend
On 02/02/2021 15:14, Chris Wilson wrote:
The different submission backends each have their own preferred
behaviour and interrupt setup. Let each handle their own interrupts.
This becomes more useful later as we to extract the use of auxiliary
state in the interrupt handler that is backend specific.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +---
.../drm/i915/gt/intel_execlists_submission.c | 40 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c| 82 ++-
drivers/gpu/drm/i915/gt/intel_gt_irq.h| 7 ++
.../gpu/drm/i915/gt/intel_ring_submission.c | 7 ++
drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 ++-
drivers/gpu/drm/i915/i915_irq.c | 8 +-
9 files changed, 103 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index dab8d734e272..2a453ba5f25a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -255,6 +255,11 @@ static void intel_engine_sanitize_mmio(struct
intel_engine_cs *engine)
intel_engine_set_hwsp_writemask(engine, ~0u);
}
+static void nop_irq_handler(struct intel_engine_cs *engine, u32 iir)
+{
+ GEM_DEBUG_WARN_ON(iir);
+}
+
static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
{
const struct engine_info *info = &intel_engines[id];
@@ -292,6 +297,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
engine->hw_id = info->hw_id;
engine->guc_id = MAKE_GUC_ID(info->class, info->instance);
+ engine->irq_handler = nop_irq_handler;
+
engine->class = info->class;
engine->instance = info->instance;
__sprint_engine_name(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 9d59de5c559a..7fd035d45263 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -402,6 +402,7 @@ struct intel_engine_cs {
u32 irq_enable_mask; /* bitmask to enable ring interrupt */
void(*irq_enable)(struct intel_engine_cs *engine);
void(*irq_disable)(struct intel_engine_cs *engine);
+ void(*irq_handler)(struct intel_engine_cs *engine, u32 iir);
void (*sanitize)(struct intel_engine_cs *engine);
int (*resume)(struct intel_engine_cs *engine);
@@ -481,10 +482,9 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_PREEMPTION BIT(2)
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
#define I915_ENGINE_HAS_TIMESLICES BIT(4)
-#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5)
-#define I915_ENGINE_IS_VIRTUAL BIT(6)
-#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)
-#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)
+#define I915_ENGINE_IS_VIRTUAL BIT(5)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
+#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
unsigned int flags;
/*
@@ -588,12 +588,6 @@ intel_engine_has_timeslices(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_HAS_TIMESLICES;
}
-static inline bool
-intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
-{
- return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
-}
-
static inline bool
intel_engine_is_virtual(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 4ddd2099a931..ed62e4b549d2 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2394,6 +2394,45 @@ static void execlists_submission_tasklet(struct
tasklet_struct *t)
rcu_read_unlock();
}
+static void execlists_irq_handler(struct intel_engine_cs *engine, u32 iir)
+{
+ bool tasklet = false;
+
+ if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
+ u32 eir;
+
+ /* Upper 16b are the enabling mask, rsvd for internal errors */
+ eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0);
+ ENGINE_TRACE(engine, "CS error: %x\n", eir);
+
+ /* Disable the error interrupt until after the reset */
+ if (likely(eir)) {
+ ENGINE_WRITE(engine, RING_EMR, ~0u);
+ ENGINE_WRITE(engine, RING_EIR, eir);
+ WRITE_ONCE(engine->execlists.error_interrupt, eir);
+ tasklet = true;
+ }
+ }
+
+ if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) {
+ WRITE_ONCE(engine->execlists.yield,
+ ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI));
+
Re: [Intel-gfx] Fixes that failed to apply to v5.11-rc4
On Tue, 02 Feb 2021, Imre Deak wrote:
> Hi,
>
> On Tue, Feb 02, 2021 at 09:15:18AM +0200, Jani Nikula wrote:
>> On Mon, 18 Jan 2021, Jani Nikula wrote:
>> > The following commits have been marked as Cc: stable or fixing something
>> > in v5.11-rc4 or earlier, but failed to cherry-pick to
>> > drm-intel-fixes. Please see if they are worth backporting, and please do
>> > so if they are.
>> >
>> > Conflicts:
>> > dbe13ae1d6ab ("drm/i915/pmu: Don't grab wakeref when enabling events")
>> > 9bb36cf66091 ("drm/i915: Check for rq->hwsp validity after acquiring RCU
>> > lock")
>> > 5b4dc95cf7f5 ("drm/i915/gt: Prevent use of engine->wa_ctx after error")
>> > 6a3daee1b38e ("drm/i915/selftests: Fix some error codes")
>> > 67fba3f1c73b ("drm/i915/dp: Fix LTTPR vswing/pre-emp setting in
>> > non-transparent mode")
>> >
>> > Fails to build:
>> > 3170a21f7059 ("drm/i915: Only enable DFP 4:4:4->4:2:0 conversion when
>> > outputting YCbCr 4:4:4")
>> >
>> > BR,
>> > Jani.
>>
>> Update.
>>
>> Conflicts:
>> 5b4dc95cf7f5 ("drm/i915/gt: Prevent use of engine->wa_ctx after error")
>> 6a3daee1b38e ("drm/i915/selftests: Fix some error codes")
>> 67fba3f1c73b ("drm/i915/dp: Fix LTTPR vswing/pre-emp setting in
>> non-transparent mode")
>
> This depends on
> 1c6e527d6947 ("rm/i915/dp: Move intel_dp_set_signal_levels() to
> intel_dp_link_training.c")
>
>> 699390f7f026 ("drm/i915: Fix the PHY compliance test vs. hotplug mishap")
>> e7004ea4f5f5 ("drm/i915/gt: Close race between enable_breadcrumbs and
>> cancel_breadcrumbs")
>> fed387572040 ("drm/i915/display: Prevent double YUV range correction on HDR
>> planes")
>>
>> Fails to build:
>> 0713eb979d2c ("drm/i915: Disable atomics in L3 for gen9")
>> f8abfda84841 ("drm/i915: Fix the MST PBN divider calculation")
>
> and this one depends on
> a321fc2b4e60 ("rm/dp/mst: Export drm_dp_get_vc_payload_bw()")
Thanks, picked the 2+2 commits up.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
___
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[Intel-gfx] [PATCH 1/2] drm/i915: Remove notion of GEM from i915_gem_shrinker_taints_mutex
Since we dropped the use of dev->struct_mutex from inside the shrinker,
we no longer include that as part of our fs_reclaim tainting. We can
drop the i915 argument and rebrand it as a generic fs_reclaim tainter.
Signed-off-by: Chris Wilson
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 3 +--
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 14 --
drivers/gpu/drm/i915/gem/i915_gem_shrinker.h | 2 --
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c| 2 +-
drivers/gpu/drm/i915/i915_utils.c| 13 +
drivers/gpu/drm/i915/i915_utils.h| 2 ++
7 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 70f798405f7f..6cdff5fc5882 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -86,8 +86,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
mutex_init(&obj->mm.get_dma_page.lock);
if (IS_ENABLED(CONFIG_LOCKDEP) && i915_gem_object_is_shrinkable(obj))
- i915_gem_shrinker_taints_mutex(to_i915(obj->base.dev),
- &obj->mm.lock);
+ fs_reclaim_taints_mutex(&obj->mm.lock);
}
/**
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index c2dba1cd9532..b64a0788381f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -415,20 +415,6 @@ void i915_gem_driver_unregister__shrinker(struct
drm_i915_private *i915)
unregister_shrinker(&i915->mm.shrinker);
}
-void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
- struct mutex *mutex)
-{
- if (!IS_ENABLED(CONFIG_LOCKDEP))
- return;
-
- fs_reclaim_acquire(GFP_KERNEL);
-
- mutex_acquire(&mutex->dep_map, 0, 0, _RET_IP_);
- mutex_release(&mutex->dep_map, _RET_IP_);
-
- fs_reclaim_release(GFP_KERNEL);
-}
-
#define obj_to_i915(obj__) to_i915((obj__)->base.dev)
void i915_gem_object_make_unshrinkable(struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.h
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.h
index b397d7785789..a25754a51ac3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.h
@@ -25,7 +25,5 @@ unsigned long i915_gem_shrink(struct drm_i915_private *i915,
unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
void i915_gem_driver_register__shrinker(struct drm_i915_private *i915);
void i915_gem_driver_unregister__shrinker(struct drm_i915_private *i915);
-void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
- struct mutex *mutex);
#endif /* __I915_GEM_SHRINKER_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 04aa6601e984..d34770ae4c9a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -97,7 +97,7 @@ void i915_address_space_init(struct i915_address_space *vm,
int subclass)
*/
mutex_init(&vm->mutex);
lockdep_set_subclass(&vm->mutex, subclass);
- i915_gem_shrinker_taints_mutex(vm->i915, &vm->mutex);
+ fs_reclaim_taints_mutex(&vm->mutex);
GEM_BUG_ON(!vm->total);
drm_mm_init(&vm->mm, 0, vm->total);
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index c8cf3981ad7f..7638fb2a45f4 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1401,7 +1401,7 @@ void intel_gt_init_reset(struct intel_gt *gt)
* within the shrinker, we forbid ourselves from performing any
* fs-reclaim or taking related locks during reset.
*/
- i915_gem_shrinker_taints_mutex(gt->i915, >->reset.mutex);
+ fs_reclaim_taints_mutex(>->reset.mutex);
/* no GPU until we are ready! */
__set_bit(I915_WEDGED, >->reset.flags);
diff --git a/drivers/gpu/drm/i915/i915_utils.c
b/drivers/gpu/drm/i915/i915_utils.c
index f9e780dee9de..90c7f0c4838c 100644
--- a/drivers/gpu/drm/i915/i915_utils.c
+++ b/drivers/gpu/drm/i915/i915_utils.c
@@ -114,3 +114,16 @@ void set_timer_ms(struct timer_list *t, unsigned long
timeout)
/* Keep t->expires = 0 reserved to indicate a canceled timer. */
mod_timer(t, jiffies + timeout ?: 1);
}
+
+void fs_reclaim_taints_mutex(struct mutex *mutex)
+{
+ if (!IS_ENABLED(CONFIG_LOCKDEP))
+ return;
+
+ fs_reclaim_acquire(GFP_KERNEL);
+
+ mutex_acquire(&mutex->dep_map, 0, 0, _RET_IP_);
+ mutex_release(&mutex->dep_map, _RET_IP_);
+
+ fs_reclaim_release(GFP_KERNEL);
+}
diff --git a/drivers/gpu
[Intel-gfx] [PATCH 2/2] drm/i915: Lift marking a lock as used to utils
After calling lock_set_subclass() the lock _must_ be used, or else
lockdep's internal nr_used_locks becomes unbalanced. Extract the little
utility function to i915_utils.c
Signed-off-by: Chris Wilson
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 13 +
drivers/gpu/drm/i915/i915_utils.c | 15 +++
drivers/gpu/drm/i915/i915_utils.h | 7 +++
3 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 56fb9cece71b..f11ea72645ac 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -769,18 +769,7 @@ intel_engine_init_active(struct intel_engine_cs *engine,
unsigned int subclass)
spin_lock_init(&engine->active.lock);
lockdep_set_subclass(&engine->active.lock, subclass);
-
- /*
-* Due to an interesting quirk in lockdep's internal debug tracking,
-* after setting a subclass we must ensure the lock is used. Otherwise,
-* nr_unused_locks is incremented once too often.
-*/
-#ifdef CONFIG_DEBUG_LOCK_ALLOC
- local_irq_disable();
- lock_map_acquire(&engine->active.lock.dep_map);
- lock_map_release(&engine->active.lock.dep_map);
- local_irq_enable();
-#endif
+ mark_lock_used_irq(&engine->active.lock);
}
static struct intel_context *
diff --git a/drivers/gpu/drm/i915/i915_utils.c
b/drivers/gpu/drm/i915/i915_utils.c
index 90c7f0c4838c..894de60833ec 100644
--- a/drivers/gpu/drm/i915/i915_utils.c
+++ b/drivers/gpu/drm/i915/i915_utils.c
@@ -127,3 +127,18 @@ void fs_reclaim_taints_mutex(struct mutex *mutex)
fs_reclaim_release(GFP_KERNEL);
}
+
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+void __mark_lock_used_irq(struct lockdep_map *lock)
+{
+ /*
+* Due to an interesting quirk in lockdep's internal debug tracking,
+* after setting a subclass we must ensure the lock is used. Otherwise,
+* nr_unused_locks is incremented once too often.
+*/
+ local_irq_disable();
+ lock_map_acquire(lock);
+ lock_map_release(lock);
+ local_irq_enable();
+}
+#endif
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_utils.h
index 3f616d00de42..610616d6bf29 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -450,6 +450,13 @@ static inline bool timer_expired(const struct timer_list
*t)
return timer_active(t) && !timer_pending(t);
}
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+void __mark_lock_used_irq(struct lockdep_map *lock);
+#define mark_lock_used_irq(lock) __mark_lock_used_irq(&(lock)->dep_map)
+#else
+#define mark_lock_used_irq(lock)
+#endif
+
/*
* This is a lookalike for IS_ENABLED() that takes a kconfig value,
* e.g. CONFIG_DRM_I915_SPIN_REQUEST, and evaluates whether it is non-zero
--
2.20.1
___
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Re: [Intel-gfx] [PATCH] drm/i915: Remove notion of GEM from i915_gem_shrinker_taints_mutex
On Tue, 2021-02-02 at 15:29 +, Chris Wilson wrote: > Since we dropped the use of dev->struct_mutex from inside the > shrinker, > we no longer include that as part of our fs_reclaim tainting. We can > drop the i915 argument and rebrand it as a generic fs_reclaim > tainter. > > Signed-off-by: Chris Wilson > Cc: Thomas Hellström LGTM. Reviewed-by: Thomas Hellström ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Remove notion of GEM from i915_gem_shrinker_taints_mutex
Since we dropped the use of dev->struct_mutex from inside the shrinker,
we no longer include that as part of our fs_reclaim tainting. We can
drop the i915 argument and rebrand it as a generic fs_reclaim tainter.
Signed-off-by: Chris Wilson
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 3 +--
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 14 --
drivers/gpu/drm/i915/gem/i915_gem_shrinker.h | 2 --
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c| 2 +-
drivers/gpu/drm/i915/i915_utils.c| 13 +
drivers/gpu/drm/i915/i915_utils.h| 2 ++
7 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 70f798405f7f..6cdff5fc5882 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -86,8 +86,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
mutex_init(&obj->mm.get_dma_page.lock);
if (IS_ENABLED(CONFIG_LOCKDEP) && i915_gem_object_is_shrinkable(obj))
- i915_gem_shrinker_taints_mutex(to_i915(obj->base.dev),
- &obj->mm.lock);
+ fs_reclaim_taints_mutex(&obj->mm.lock);
}
/**
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index c2dba1cd9532..b64a0788381f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -415,20 +415,6 @@ void i915_gem_driver_unregister__shrinker(struct
drm_i915_private *i915)
unregister_shrinker(&i915->mm.shrinker);
}
-void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
- struct mutex *mutex)
-{
- if (!IS_ENABLED(CONFIG_LOCKDEP))
- return;
-
- fs_reclaim_acquire(GFP_KERNEL);
-
- mutex_acquire(&mutex->dep_map, 0, 0, _RET_IP_);
- mutex_release(&mutex->dep_map, _RET_IP_);
-
- fs_reclaim_release(GFP_KERNEL);
-}
-
#define obj_to_i915(obj__) to_i915((obj__)->base.dev)
void i915_gem_object_make_unshrinkable(struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.h
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.h
index b397d7785789..a25754a51ac3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.h
@@ -25,7 +25,5 @@ unsigned long i915_gem_shrink(struct drm_i915_private *i915,
unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
void i915_gem_driver_register__shrinker(struct drm_i915_private *i915);
void i915_gem_driver_unregister__shrinker(struct drm_i915_private *i915);
-void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
- struct mutex *mutex);
#endif /* __I915_GEM_SHRINKER_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 04aa6601e984..d34770ae4c9a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -97,7 +97,7 @@ void i915_address_space_init(struct i915_address_space *vm,
int subclass)
*/
mutex_init(&vm->mutex);
lockdep_set_subclass(&vm->mutex, subclass);
- i915_gem_shrinker_taints_mutex(vm->i915, &vm->mutex);
+ fs_reclaim_taints_mutex(&vm->mutex);
GEM_BUG_ON(!vm->total);
drm_mm_init(&vm->mm, 0, vm->total);
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index c8cf3981ad7f..7638fb2a45f4 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1401,7 +1401,7 @@ void intel_gt_init_reset(struct intel_gt *gt)
* within the shrinker, we forbid ourselves from performing any
* fs-reclaim or taking related locks during reset.
*/
- i915_gem_shrinker_taints_mutex(gt->i915, >->reset.mutex);
+ fs_reclaim_taints_mutex(>->reset.mutex);
/* no GPU until we are ready! */
__set_bit(I915_WEDGED, >->reset.flags);
diff --git a/drivers/gpu/drm/i915/i915_utils.c
b/drivers/gpu/drm/i915/i915_utils.c
index f9e780dee9de..90c7f0c4838c 100644
--- a/drivers/gpu/drm/i915/i915_utils.c
+++ b/drivers/gpu/drm/i915/i915_utils.c
@@ -114,3 +114,16 @@ void set_timer_ms(struct timer_list *t, unsigned long
timeout)
/* Keep t->expires = 0 reserved to indicate a canceled timer. */
mod_timer(t, jiffies + timeout ?: 1);
}
+
+void fs_reclaim_taints_mutex(struct mutex *mutex)
+{
+ if (!IS_ENABLED(CONFIG_LOCKDEP))
+ return;
+
+ fs_reclaim_acquire(GFP_KERNEL);
+
+ mutex_acquire(&mutex->dep_map, 0, 0, _RET_IP_);
+ mutex_release(&mutex->dep_map, _RET_IP_);
+
+ fs_reclaim_release(GFP_KERNEL);
+}
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drive
[Intel-gfx] [CI 02/14] drm/i915/gt: Move submission_method into intel_gt
Since we setup the submission method for the engines once, it is easy to
assign an enum and use that instead of probing into the backends.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h | 8 +++-
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 12
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 8
drivers/gpu/drm/i915/gt/intel_execlists_submission.h | 3 ---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +++
drivers/gpu/drm/i915/gt/intel_reset.c| 7 +++
drivers/gpu/drm/i915/gt/selftest_execlists.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c| 5 -
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h| 1 -
drivers/gpu/drm/i915/i915_perf.c | 10 +-
11 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 47ee8578e511..8d9184920c51 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -13,8 +13,9 @@
#include "i915_reg.h"
#include "i915_request.h"
#include "i915_selftest.h"
-#include "gt/intel_timeline.h"
#include "intel_engine_types.h"
+#include "intel_gt_types.h"
+#include "intel_timeline.h"
#include "intel_workarounds.h"
struct drm_printer;
@@ -262,6 +263,11 @@ void intel_engine_init_active(struct intel_engine_cs
*engine,
#define ENGINE_MOCK1
#define ENGINE_VIRTUAL 2
+static inline bool intel_engine_uses_guc(const struct intel_engine_cs *engine)
+{
+ return engine->gt->submission_method >= INTEL_SUBMISSION_GUC;
+}
+
static inline bool
intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 56fb9cece71b..dab8d734e272 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -891,12 +891,16 @@ int intel_engines_init(struct intel_gt *gt)
enum intel_engine_id id;
int err;
- if (intel_uc_uses_guc_submission(>->uc))
+ if (intel_uc_uses_guc_submission(>->uc)) {
+ gt->submission_method = INTEL_SUBMISSION_GUC;
setup = intel_guc_submission_setup;
- else if (HAS_EXECLISTS(gt->i915))
+ } else if (HAS_EXECLISTS(gt->i915)) {
+ gt->submission_method = INTEL_SUBMISSION_ELSP;
setup = intel_execlists_submission_setup;
- else
+ } else {
+ gt->submission_method = INTEL_SUBMISSION_RING;
setup = intel_ring_submission_setup;
+ }
for_each_engine(engine, gt, id) {
err = engine_setup_common(engine);
@@ -1467,7 +1471,7 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
}
- if (intel_engine_in_guc_submission_mode(engine)) {
+ if (intel_engine_uses_guc(engine)) {
/* nothing to print yet */
} else if (HAS_EXECLISTS(dev_priv)) {
struct i915_request * const *port, *rq;
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 5d824e1cfcba..4ddd2099a931 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1757,7 +1757,6 @@ process_csb(struct intel_engine_cs *engine, struct
i915_request **inactive)
*/
GEM_BUG_ON(!tasklet_is_locked(&execlists->tasklet) &&
!reset_in_progress(execlists));
- GEM_BUG_ON(!intel_engine_in_execlists_submission_mode(engine));
/*
* Note that csb_write, csb_status may be either in HWSP or mmio.
@@ -3897,13 +3896,6 @@ void intel_execlists_show_requests(struct
intel_engine_cs *engine,
spin_unlock_irqrestore(&engine->active.lock, flags);
}
-bool
-intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine)
-{
- return engine->set_default_submission ==
- execlists_set_default_submission;
-}
-
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_execlists.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
index a8fd7adefd82..f7bd3fccfee8 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
@@ -41,7 +41,4 @@ int intel_virtual_engine_attach_bond(struct intel_engine_cs
*engine,
const struct intel_engine_cs *master,
const struct intel_engine_cs *sibling);
-bool
-intel_engine_in_execlists_submission_mode
[Intel-gfx] [CI 06/14] drm/i915/selftests: Measure set-priority duration
As a topological sort, we expect it to run in linear graph time,
O(V+E). In removing the recursion, it is no longer a DFS but rather a
BFS, and performs as O(VE). Let's demonstrate how bad this is with a few
examples, and build a few test cases to verify a potential fix.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_scheduler.c | 4 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/i915_perf_selftests.h | 1 +
.../gpu/drm/i915/selftests/i915_scheduler.c | 672 ++
4 files changed, 678 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_scheduler.c
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 035e4be5d573..27bda7617b29 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -609,6 +609,10 @@ void i915_request_show_with_schedule(struct drm_printer *m,
rcu_read_unlock();
}
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/i915_scheduler.c"
+#endif
+
static void i915_global_scheduler_shrink(void)
{
kmem_cache_shrink(global.slab_dependencies);
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index a92c0e9b7e6b..2200a5baa68e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -26,6 +26,7 @@ selftest(gt_mocs, intel_mocs_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
selftest(gt_heartbeat, intel_heartbeat_live_selftests)
selftest(requests, i915_request_live_selftests)
+selftest(scheduler, i915_scheduler_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
selftest(mman, i915_gem_mman_live_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
index c2389f8a257d..137e35283fee 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
@@ -17,5 +17,6 @@
*/
selftest(engine_cs, intel_engine_cs_perf_selftests)
selftest(request, i915_request_perf_selftests)
+selftest(scheduler, i915_scheduler_perf_selftests)
selftest(blt, i915_gem_object_blt_perf_selftests)
selftest(region, intel_memory_region_perf_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
new file mode 100644
index ..d095fab2ccec
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
@@ -0,0 +1,672 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_selftest.h"
+
+#include "gt/intel_context.h"
+#include "gt/intel_gpu_commands.h"
+#include "gt/selftest_engine_heartbeat.h"
+#include "selftests/igt_spinner.h"
+#include "selftests/i915_random.h"
+
+static void scheduling_disable(struct intel_engine_cs *engine)
+{
+ engine->props.preempt_timeout_ms = 0;
+ engine->props.timeslice_duration_ms = 0;
+
+ st_engine_heartbeat_disable(engine);
+}
+
+static void scheduling_enable(struct intel_engine_cs *engine)
+{
+ st_engine_heartbeat_enable(engine);
+
+ engine->props.preempt_timeout_ms =
+ engine->defaults.preempt_timeout_ms;
+ engine->props.timeslice_duration_ms =
+ engine->defaults.timeslice_duration_ms;
+}
+
+static int first_engine(struct drm_i915_private *i915,
+ int (*chain)(struct intel_engine_cs *engine,
+unsigned long param,
+bool (*fn)(struct i915_request *rq,
+ unsigned long v,
+ unsigned long e)),
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ if (!intel_engine_has_scheduler(engine))
+ continue;
+
+ return chain(engine, param, fn);
+ }
+
+ return 0;
+}
+
+static int all_engines(struct drm_i915_private *i915,
+ int (*chain)(struct intel_engine_cs *engine,
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v,
+ unsigned long e)),
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_engine_cs *engine;
+ int err;
+
+ for_each_uabi_engine(engine, i915) {
+
[Intel-gfx] [CI 03/14] drm/i915/gt: Move CS interrupt handler to the backend
The different submission backends each have their own preferred
behaviour and interrupt setup. Let each handle their own interrupts.
This becomes more useful later as we to extract the use of auxiliary
state in the interrupt handler that is backend specific.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +---
.../drm/i915/gt/intel_execlists_submission.c | 40 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c| 82 ++-
drivers/gpu/drm/i915/gt/intel_gt_irq.h| 7 ++
.../gpu/drm/i915/gt/intel_ring_submission.c | 7 ++
drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 ++-
drivers/gpu/drm/i915/i915_irq.c | 8 +-
9 files changed, 103 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index dab8d734e272..2a453ba5f25a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -255,6 +255,11 @@ static void intel_engine_sanitize_mmio(struct
intel_engine_cs *engine)
intel_engine_set_hwsp_writemask(engine, ~0u);
}
+static void nop_irq_handler(struct intel_engine_cs *engine, u32 iir)
+{
+ GEM_DEBUG_WARN_ON(iir);
+}
+
static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
{
const struct engine_info *info = &intel_engines[id];
@@ -292,6 +297,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
engine->hw_id = info->hw_id;
engine->guc_id = MAKE_GUC_ID(info->class, info->instance);
+ engine->irq_handler = nop_irq_handler;
+
engine->class = info->class;
engine->instance = info->instance;
__sprint_engine_name(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 9d59de5c559a..7fd035d45263 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -402,6 +402,7 @@ struct intel_engine_cs {
u32 irq_enable_mask; /* bitmask to enable ring interrupt */
void(*irq_enable)(struct intel_engine_cs *engine);
void(*irq_disable)(struct intel_engine_cs *engine);
+ void(*irq_handler)(struct intel_engine_cs *engine, u32 iir);
void(*sanitize)(struct intel_engine_cs *engine);
int (*resume)(struct intel_engine_cs *engine);
@@ -481,10 +482,9 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_PREEMPTION BIT(2)
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
#define I915_ENGINE_HAS_TIMESLICES BIT(4)
-#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5)
-#define I915_ENGINE_IS_VIRTUAL BIT(6)
-#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)
-#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)
+#define I915_ENGINE_IS_VIRTUAL BIT(5)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
+#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
unsigned int flags;
/*
@@ -588,12 +588,6 @@ intel_engine_has_timeslices(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_HAS_TIMESLICES;
}
-static inline bool
-intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
-{
- return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
-}
-
static inline bool
intel_engine_is_virtual(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 4ddd2099a931..ed62e4b549d2 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2394,6 +2394,45 @@ static void execlists_submission_tasklet(struct
tasklet_struct *t)
rcu_read_unlock();
}
+static void execlists_irq_handler(struct intel_engine_cs *engine, u32 iir)
+{
+ bool tasklet = false;
+
+ if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
+ u32 eir;
+
+ /* Upper 16b are the enabling mask, rsvd for internal errors */
+ eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0);
+ ENGINE_TRACE(engine, "CS error: %x\n", eir);
+
+ /* Disable the error interrupt until after the reset */
+ if (likely(eir)) {
+ ENGINE_WRITE(engine, RING_EMR, ~0u);
+ ENGINE_WRITE(engine, RING_EIR, eir);
+ WRITE_ONCE(engine->execlists.error_interrupt, eir);
+ tasklet = true;
+ }
+ }
+
+ if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) {
+ WRITE_ONCE(engine->execlists.yield,
+ ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI));
+ ENGINE_TRACE(engine, "semaphore yield
[Intel-gfx] [CI 04/14] drm/i915: Replace engine->schedule() with a known request operation
Looking to the future, we want to set the scheduling attributes
explicitly and so replace the generic engine->schedule() with the more
direct i915_request_set_priority()
What it loses in removing the 'schedule' name from the function, it
gains in having an explicit entry point with a stated goal.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++-
drivers/gpu/drm/i915/gem/i915_gem_object.h| 5 ++-
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 29 +---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 --
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 +--
drivers/gpu/drm/i915/gt/intel_engine_types.h | 27 ---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 3 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 33 +--
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 11 +++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 +-
drivers/gpu/drm/i915/i915_request.c | 10 +++---
drivers/gpu/drm/i915/i915_request.h | 5 +++
drivers/gpu/drm/i915/i915_scheduler.c | 15 +
drivers/gpu/drm/i915/i915_scheduler.h | 3 +-
15 files changed, 64 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d8f10589e09e..aca964f7ba72 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13662,7 +13662,6 @@ int
intel_prepare_plane_fb(struct drm_plane *_plane,
struct drm_plane_state *_new_plane_state)
{
- struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
struct intel_plane *plane = to_intel_plane(_plane);
struct intel_plane_state *new_plane_state =
to_intel_plane_state(_new_plane_state);
@@ -13703,7 +13702,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
if (new_plane_state->uapi.fence) { /* explicit fencing */
i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
-&attr);
+I915_PRIORITY_DISPLAY);
ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
new_plane_state->uapi.fence,
i915_fence_timeout(dev_priv),
@@ -13725,7 +13724,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
if (ret)
return ret;
- i915_gem_object_wait_priority(obj, 0, &attr);
+ i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
if (!new_plane_state->uapi.fence) { /* implicit fencing */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 3411ad197fa6..325766abca21 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -549,15 +549,14 @@ static inline void __start_cpu_write(struct
drm_i915_gem_object *obj)
obj->cache_dirty = true;
}
-void i915_gem_fence_wait_priority(struct dma_fence *fence,
- const struct i915_sched_attr *attr);
+void i915_gem_fence_wait_priority(struct dma_fence *fence, int prio);
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
unsigned int flags,
long timeout);
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
unsigned int flags,
- const struct i915_sched_attr *attr);
+ int prio);
void __i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
enum fb_op_origin origin);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
index 4b9856d5ba14..d79bf16083bd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
@@ -91,22 +91,12 @@ i915_gem_object_wait_reservation(struct dma_resv *resv,
return timeout;
}
-static void fence_set_priority(struct dma_fence *fence,
- const struct i915_sched_attr *attr)
+static void fence_set_priority(struct dma_fence *fence, int prio)
{
- struct i915_request *rq;
- struct intel_engine_cs *engine;
-
if (dma_fence_is_signaled(fence) || !dma_fence_is_i915(fence))
return;
- rq = to_request(fence);
- engine = rq->engine;
-
- rcu_read_lock(); /* RCU serialisation for set-wedged protection */
- if (engine->schedule)
- engine->schedule(rq, attr);
- rcu_read_unlock();
+ i915_request_set_priority(to_request(fence)
[Intel-gfx] [CI 07/14] drm/i915/selftests: Exercise priority inheritance around an engine loop
Exercise rescheduling priority inheritance around a sequence of requests
that wrap around all the engines.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/selftests/i915_scheduler.c | 225 ++
1 file changed, 225 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
index d095fab2ccec..acc666f755d7 100644
--- a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
@@ -7,6 +7,7 @@
#include "gt/intel_context.h"
#include "gt/intel_gpu_commands.h"
+#include "gt/intel_ring.h"
#include "gt/selftest_engine_heartbeat.h"
#include "selftests/igt_spinner.h"
#include "selftests/i915_random.h"
@@ -504,10 +505,234 @@ static int igt_priority_chains(void *arg)
return igt_schedule_chains(arg, igt_priority);
}
+static struct i915_request *
+__write_timestamp(struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *obj,
+ int slot,
+ struct i915_request *prev)
+{
+ struct i915_request *rq = ERR_PTR(-EINVAL);
+ bool use_64b = INTEL_GEN(engine->i915) >= 8;
+ struct intel_context *ce;
+ struct i915_vma *vma;
+ int err = 0;
+ u32 *cs;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return ERR_CAST(ce);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_ce;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto out_ce;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unpin;
+ }
+
+ i915_vma_lock(vma);
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+ if (err)
+ goto out_request;
+
+ if (prev) {
+ err = i915_request_await_dma_fence(rq, &prev->fence);
+ if (err)
+ goto out_request;
+ }
+
+ if (engine->emit_init_breadcrumb) {
+ err = engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_request;
+ }
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto out_request;
+ }
+
+ *cs++ = MI_STORE_REGISTER_MEM + use_64b;
+ *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base));
+ *cs++ = lower_32_bits(vma->node.start) + sizeof(u32) * slot;
+ *cs++ = upper_32_bits(vma->node.start);
+ intel_ring_advance(rq, cs);
+
+ i915_request_get(rq);
+out_request:
+ i915_request_add(rq);
+out_unpin:
+ i915_vma_unpin(vma);
+out_ce:
+ intel_context_put(ce);
+ i915_request_put(prev);
+ return err ? ERR_PTR(err) : rq;
+}
+
+static struct i915_request *create_spinner(struct drm_i915_private *i915,
+ struct igt_spinner *spin)
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ struct intel_context *ce;
+ struct i915_request *rq;
+
+ if (igt_spinner_init(spin, engine->gt))
+ return ERR_PTR(-ENOMEM);
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return ERR_CAST(ce);
+
+ rq = igt_spinner_create_request(spin, ce, MI_NOOP);
+ intel_context_put(ce);
+ if (rq == ERR_PTR(-ENODEV))
+ continue;
+ if (IS_ERR(rq))
+ return rq;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ return rq;
+ }
+
+ return ERR_PTR(-ENODEV);
+}
+
+static bool has_timestamp(const struct drm_i915_private *i915)
+{
+ return INTEL_GEN(i915) >= 7;
+}
+
+static int __igt_schedule_cycle(struct drm_i915_private *i915,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_engine_cs *engine;
+ struct drm_i915_gem_object *obj;
+ struct igt_spinner spin;
+ struct i915_request *rq;
+ unsigned long count, n;
+ u32 *time, last;
+ int err;
+
+ /*
+* Queue a bunch of ordered requests (each waiting on the previous)
+* around the engines a couple of times. Each request will write
+* the timestamp it executes at into the scratch, with the expectation
+* that the timestamp will be in our desired execution order.
+*/
+
+ if (!i915->caps.scheduler || !has_timestamp(i915))
+ return 0;
+
+ obj = i915_gem_object_create_internal(i915, SZ_64K);
+ if (IS_ERR(obj))
+ return PT
[Intel-gfx] [CI 12/14] drm/i915: Extract request suspension from the execlists
Make the ability to suspend and resume a request and its dependents
generic.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 167 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 8 +-
drivers/gpu/drm/i915/i915_scheduler.c | 153
drivers/gpu/drm/i915/i915_scheduler.h | 10 ++
4 files changed, 169 insertions(+), 169 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 4add205ec30e..a971b3bee532 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1921,169 +1921,6 @@ static void post_process_csb(struct i915_request **port,
execlists_schedule_out(*port++);
}
-static void __execlists_hold(struct i915_request *rq)
-{
- LIST_HEAD(list);
-
- do {
- struct i915_dependency *p;
-
- if (i915_request_is_active(rq))
- __i915_request_unsubmit(rq);
-
- clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
- list_move_tail(&rq->sched.link, &rq->engine->active.hold);
- i915_request_set_hold(rq);
- RQ_TRACE(rq, "on hold\n");
-
- for_each_waiter(p, rq) {
- struct i915_request *w =
- container_of(p->waiter, typeof(*w), sched);
-
- if (p->flags & I915_DEPENDENCY_WEAK)
- continue;
-
- /* Leave semaphores spinning on the other engines */
- if (w->engine != rq->engine)
- continue;
-
- if (!i915_request_is_ready(w))
- continue;
-
- if (__i915_request_is_complete(w))
- continue;
-
- if (i915_request_on_hold(w))
- continue;
-
- list_move_tail(&w->sched.link, &list);
- }
-
- rq = list_first_entry_or_null(&list, typeof(*rq), sched.link);
- } while (rq);
-}
-
-static bool execlists_hold(struct intel_engine_cs *engine,
- struct i915_request *rq)
-{
- if (i915_request_on_hold(rq))
- return false;
-
- spin_lock_irq(&engine->active.lock);
-
- if (__i915_request_is_complete(rq)) { /* too late! */
- rq = NULL;
- goto unlock;
- }
-
- /*
-* Transfer this request onto the hold queue to prevent it
-* being resumbitted to HW (and potentially completed) before we have
-* released it. Since we may have already submitted following
-* requests, we need to remove those as well.
-*/
- GEM_BUG_ON(i915_request_on_hold(rq));
- GEM_BUG_ON(rq->engine != engine);
- __execlists_hold(rq);
- GEM_BUG_ON(list_empty(&engine->active.hold));
-
-unlock:
- spin_unlock_irq(&engine->active.lock);
- return rq;
-}
-
-static bool hold_request(const struct i915_request *rq)
-{
- struct i915_dependency *p;
- bool result = false;
-
- /*
-* If one of our ancestors is on hold, we must also be on hold,
-* otherwise we will bypass it and execute before it.
-*/
- rcu_read_lock();
- for_each_signaler(p, rq) {
- const struct i915_request *s =
- container_of(p->signaler, typeof(*s), sched);
-
- if (s->engine != rq->engine)
- continue;
-
- result = i915_request_on_hold(s);
- if (result)
- break;
- }
- rcu_read_unlock();
-
- return result;
-}
-
-static void __execlists_unhold(struct i915_request *rq)
-{
- LIST_HEAD(list);
-
- do {
- struct i915_dependency *p;
-
- RQ_TRACE(rq, "hold release\n");
-
- GEM_BUG_ON(!i915_request_on_hold(rq));
- GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
-
- i915_request_clear_hold(rq);
- list_move_tail(&rq->sched.link,
- i915_sched_lookup_priolist(rq->engine,
- rq_prio(rq)));
- set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
-
- /* Also release any children on this engine that are ready */
- for_each_waiter(p, rq) {
- struct i915_request *w =
- container_of(p->waiter, typeof(*w), sched);
-
- if (p->flags & I915_DEPENDENCY_WEAK)
- continue;
-
- /* Propagate any change in error status */
- if (rq->fence.error)
-
[Intel-gfx] [CI 09/14] drm/i915: Improve DFS for priority inheritance
The core of the scheduling algorithm is that we compute the topological
order of the fence DAG. Knowing that we have a DAG, we should be able to
use a DFS to compute the topological sort in linear time. However,
during the conversion of the recursive algorithm into an iterative one,
the memoization of how far we had progressed down a branch was
forgotten. The result was that instead of running in linear time, it was
running in geometric time and could easily run for a few hundred
milliseconds given a wide enough graph, not the microseconds as required.
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_scheduler.c | 58 -
drivers/gpu/drm/i915/i915_scheduler_types.h | 6 ++-
2 files changed, 39 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 27bda7617b29..9e88417bf451 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -242,6 +242,26 @@ void __i915_priolist_free(struct i915_priolist *p)
kmem_cache_free(global.slab_priorities, p);
}
+static struct i915_request *
+stack_push(struct i915_request *rq,
+ struct i915_request *prev,
+ struct list_head *pos)
+{
+ prev->sched.dfs.pos = pos;
+ rq->sched.dfs.prev = prev;
+ return rq;
+}
+
+static struct i915_request *
+stack_pop(struct i915_request *rq,
+ struct list_head **pos)
+{
+ rq = rq->sched.dfs.prev;
+ if (rq)
+ *pos = rq->sched.dfs.pos;
+ return rq;
+}
+
static inline bool need_preempt(int prio, int active)
{
/*
@@ -306,11 +326,10 @@ static void ipi_priority(struct i915_request *rq, int
prio)
static void __i915_request_set_priority(struct i915_request *rq, int prio)
{
struct intel_engine_cs *engine = rq->engine;
- struct i915_request *rn;
+ struct list_head *pos = &rq->sched.signalers_list;
struct list_head *plist;
- LIST_HEAD(dfs);
- list_add(&rq->sched.dfs, &dfs);
+ plist = i915_sched_lookup_priolist(engine, prio);
/*
* Recursively bump all dependent priorities to match the new request.
@@ -330,40 +349,31 @@ static void __i915_request_set_priority(struct
i915_request *rq, int prio)
* end result is a topological list of requests in reverse order, the
* last element in the list is the request we must execute first.
*/
- list_for_each_entry(rq, &dfs, sched.dfs) {
- struct i915_dependency *p;
-
- /* Also release any children on this engine that are ready */
- GEM_BUG_ON(rq->engine != engine);
-
- for_each_signaler(p, rq) {
+ rq->sched.dfs.prev = NULL;
+ do {
+ list_for_each_continue(pos, &rq->sched.signalers_list) {
+ struct i915_dependency *p =
+ list_entry(pos, typeof(*p), signal_link);
struct i915_request *s =
container_of(p->signaler, typeof(*s), sched);
- GEM_BUG_ON(s == rq);
-
if (rq_prio(s) >= prio)
continue;
if (__i915_request_is_complete(s))
continue;
- if (s->engine != rq->engine) {
+ if (s->engine != engine) {
ipi_priority(s, prio);
continue;
}
- list_move_tail(&s->sched.dfs, &dfs);
+ /* Remember our position along this branch */
+ rq = stack_push(s, rq, pos);
+ pos = &rq->sched.signalers_list;
}
- }
- plist = i915_sched_lookup_priolist(engine, prio);
-
- /* Fifo and depth-first replacement ensure our deps execute first */
- list_for_each_entry_safe_reverse(rq, rn, &dfs, sched.dfs) {
- GEM_BUG_ON(rq->engine != engine);
-
- INIT_LIST_HEAD(&rq->sched.dfs);
+ RQ_TRACE(rq, "set-priority:%d\n", prio);
WRITE_ONCE(rq->sched.attr.priority, prio);
/*
@@ -377,12 +387,13 @@ static void __i915_request_set_priority(struct
i915_request *rq, int prio)
if (!i915_request_is_ready(rq))
continue;
+ GEM_BUG_ON(rq->engine != engine);
if (i915_request_in_priority_queue(rq))
list_move_tail(&rq->sched.link, plist);
/* Defer (tasklet) submission until after all updates. */
kick_submission(engine, rq, prio);
- }
+ } while ((rq = stack_pop(rq, &pos)));
}
#define all_signalers_checked(p, rq) \
@@ -456,7 +467,6 @@ void i915_sched_node_init(struct i915_sched_node *no
[Intel-gfx] [CI 08/14] drm/i915/selftests: Force a rewind if at first we don't succeed
live_timeslice_rewind assumes a particular traversal and reordering
after the first timeslice yield. However, the outcome can be either
(A1, A2, B1) or (A1, B2, A2) depending on the path taken through the
dependency graph. So if we do not get the outcome we need at first, give
it a priority kick to force a rewind.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 21 +++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 951e2bf867e1..68e1398704a4 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -1107,6 +1107,7 @@ static int live_timeslice_rewind(void *arg)
struct i915_request *rq[3] = {};
struct intel_context *ce;
unsigned long timeslice;
+ unsigned long timeout;
int i, err = 0;
u32 *slot;
@@ -1173,11 +1174,29 @@ static int live_timeslice_rewind(void *arg)
/* ELSP[] = { { A:rq1, A:rq2 }, { B:rq1 } } */
ENGINE_TRACE(engine, "forcing tasklet for rewind\n");
- while (i915_request_is_active(rq[A2])) { /* semaphore yield! */
+ i = 0;
+ timeout = jiffies + HZ;
+ while (i915_request_is_active(rq[A2]) &&
+ time_before(jiffies, timeout)) { /* semaphore yield! */
/* Wait for the timeslice to kick in */
del_timer(&engine->execlists.timer);
tasklet_hi_schedule(&engine->execlists.tasklet);
intel_engine_flush_submission(engine);
+
+ /*
+* Unfortunately this assumes that during the
+* search of the wait tree it sees the requests
+* in a particular order. That order is not
+* strictly determined and it may pick either
+* A2 or B1 to immediately follow A1.
+*
+* Break the tie with a set-priority. This defeats
+* the goal of trying to cause a rewind with a
+* timeslice, but alas, a rewind is better than
+* none.
+*/
+ if (i++)
+ i915_request_set_priority(rq[B1], 1);
}
/* -> ELSP[] = { { A:rq1 }, { B:rq1 } } */
GEM_BUG_ON(!i915_request_is_active(rq[A1]));
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 10/14] drm/i915: Extract request submission from execlists
In the process of preparing to reuse the request submission logic for
other backends, lift it out of the execlists backend. It already
operates on the common structs, so just a matter of moving and renaming.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 55 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 30 +--
drivers/gpu/drm/i915/i915_scheduler.c | 82 +++
drivers/gpu/drm/i915/i915_scheduler.h | 2 +
4 files changed, 86 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 6b8984c64b60..62e83acc7221 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2452,59 +2452,6 @@ static void execlists_preempt(struct timer_list *timer)
execlists_kick(timer, preempt);
}
-static void queue_request(struct intel_engine_cs *engine,
- struct i915_request *rq)
-{
- GEM_BUG_ON(!list_empty(&rq->sched.link));
- list_add_tail(&rq->sched.link,
- i915_sched_lookup_priolist(engine, rq_prio(rq)));
- set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
-}
-
-static bool submit_queue(struct intel_engine_cs *engine,
-const struct i915_request *rq)
-{
- struct intel_engine_execlists *execlists = &engine->execlists;
-
- if (rq_prio(rq) <= execlists->queue_priority_hint)
- return false;
-
- execlists->queue_priority_hint = rq_prio(rq);
- return true;
-}
-
-static bool ancestor_on_hold(const struct intel_engine_cs *engine,
-const struct i915_request *rq)
-{
- GEM_BUG_ON(i915_request_on_hold(rq));
- return !list_empty(&engine->active.hold) && hold_request(rq);
-}
-
-static void execlists_submit_request(struct i915_request *request)
-{
- struct intel_engine_cs *engine = request->engine;
- unsigned long flags;
-
- /* Will be called from irq-context when using foreign fences. */
- spin_lock_irqsave(&engine->active.lock, flags);
-
- if (unlikely(ancestor_on_hold(engine, request))) {
- RQ_TRACE(request, "ancestor on hold\n");
- list_add_tail(&request->sched.link, &engine->active.hold);
- i915_request_set_hold(request);
- } else {
- queue_request(engine, request);
-
- GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
- GEM_BUG_ON(list_empty(&request->sched.link));
-
- if (submit_queue(engine, request))
- __execlists_kick(&engine->execlists);
- }
-
- spin_unlock_irqrestore(&engine->active.lock, flags);
-}
-
static int execlists_context_pre_pin(struct intel_context *ce,
struct i915_gem_ww_ctx *ww,
void **vaddr)
@@ -3124,7 +3071,7 @@ static bool can_preempt(struct intel_engine_cs *engine)
static void execlists_set_default_submission(struct intel_engine_cs *engine)
{
- engine->submit_request = execlists_submit_request;
+ engine->submit_request = i915_request_enqueue;
engine->execlists.tasklet.callback = execlists_submission_tasklet;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 7db2c9decf21..f5b8f89d30bc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -519,34 +519,6 @@ static int guc_request_alloc(struct i915_request *request)
return 0;
}
-static inline void queue_request(struct intel_engine_cs *engine,
-struct i915_request *rq,
-int prio)
-{
- GEM_BUG_ON(!list_empty(&rq->sched.link));
- list_add_tail(&rq->sched.link,
- i915_sched_lookup_priolist(engine, prio));
- set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
-}
-
-static void guc_submit_request(struct i915_request *rq)
-{
- struct intel_engine_cs *engine = rq->engine;
- unsigned long flags;
-
- /* Will be called from irq-context when using foreign fences. */
- spin_lock_irqsave(&engine->active.lock, flags);
-
- queue_request(engine, rq, rq_prio(rq));
-
- GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
- GEM_BUG_ON(list_empty(&rq->sched.link));
-
- tasklet_hi_schedule(&engine->execlists.tasklet);
-
- spin_unlock_irqrestore(&engine->active.lock, flags);
-}
-
static void sanitize_hwsp(struct intel_engine_cs *engine)
{
struct intel_timeline *tl;
@@ -615,7 +587,7 @@ static int guc_resume(struct intel_engine_cs *engine)
static void guc_set_default_submission(struct intel_engine_cs *engine)
{
- engine->submit_requ
[Intel-gfx] [CI 11/14] drm/i915: Extract request rewinding from execlists
In the process of preparing to reuse the request submission logic for
other backends, lift it out of the execlists backend.
While this operates on the common structs, we do have a bit of backend
knowledge, which is harmless for !lrc but still unsightly.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h| 3 -
.../drm/i915/gt/intel_execlists_submission.c | 58 ++-
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 3 +
drivers/gpu/drm/i915/gt/selftest_execlists.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 +-
drivers/gpu/drm/i915/i915_scheduler.c | 44 ++
drivers/gpu/drm/i915/i915_scheduler.h | 3 +
7 files changed, 56 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 8d9184920c51..cc2df80eb449 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -137,9 +137,6 @@ execlists_active_unlock_bh(struct intel_engine_execlists
*execlists)
local_bh_enable(); /* restore softirq, and kick ksoftirqd! */
}
-struct i915_request *
-execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
-
static inline u32
intel_read_status_page(const struct intel_engine_cs *engine, int reg)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 62e83acc7221..4add205ec30e 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -359,56 +359,6 @@ assert_priority_queue(const struct i915_request *prev,
return rq_prio(prev) >= rq_prio(next);
}
-static struct i915_request *
-__unwind_incomplete_requests(struct intel_engine_cs *engine)
-{
- struct i915_request *rq, *rn, *active = NULL;
- struct list_head *pl;
- int prio = I915_PRIORITY_INVALID;
-
- lockdep_assert_held(&engine->active.lock);
-
- list_for_each_entry_safe_reverse(rq, rn,
-&engine->active.requests,
-sched.link) {
- if (__i915_request_is_complete(rq)) {
- list_del_init(&rq->sched.link);
- continue;
- }
-
- __i915_request_unsubmit(rq);
-
- GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
- if (rq_prio(rq) != prio) {
- prio = rq_prio(rq);
- pl = i915_sched_lookup_priolist(engine, prio);
- }
- GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
-
- list_move(&rq->sched.link, pl);
- set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
-
- /* Check in case we rollback so far we wrap [size/2] */
- if (intel_ring_direction(rq->ring,
-rq->tail,
-rq->ring->tail + 8) > 0)
- rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE;
-
- active = rq;
- }
-
- return active;
-}
-
-struct i915_request *
-execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
-{
- struct intel_engine_cs *engine =
- container_of(execlists, typeof(*engine), execlists);
-
- return __unwind_incomplete_requests(engine);
-}
-
static void
execlists_context_status_change(struct i915_request *rq, unsigned long status)
{
@@ -1080,7 +1030,7 @@ static void defer_active(struct intel_engine_cs *engine)
{
struct i915_request *rq;
- rq = __unwind_incomplete_requests(engine);
+ rq = __i915_sched_rewind_requests(engine);
if (!rq)
return;
@@ -1292,7 +1242,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* the preemption, some of the unwound requests may
* complete!
*/
- __unwind_incomplete_requests(engine);
+ __i915_sched_rewind_requests(engine);
last = NULL;
} else if (timeslice_expired(engine, last)) {
@@ -2287,7 +2237,7 @@ static void execlists_capture(struct intel_engine_cs
*engine)
* which we return it to the queue for signaling.
*
* By removing them from the execlists queue, we also remove the
-* requests from being processed by __unwind_incomplete_requests()
+* requests from being processed by __intel_engine_rewind_requests()
* during the intel_engine_reset(), and so they will *not* be replayed
* afterwards.
*
@@ -2917,7 +2867,7 @@ static void execlists_reset_rewind(struct intel_engine_cs
*engine, bool stalled)
/* Push back any incomplete requests for replay afte
[Intel-gfx] [CI 14/14] drm/i915: Fix the iterative dfs for defering requests
The current implementation of walking the children of a deferred
requests lacks the backtracking required to reduce the dfs to linear.
Having pulled it from execlists into the common layer, we can reuse the
dfs code for priority inheritance.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_scheduler.c | 56 +++
1 file changed, 40 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 641141f3ce10..8dd999f09412 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -466,8 +466,10 @@ void i915_request_set_priority(struct i915_request *rq,
int prio)
void __i915_sched_defer_request(struct intel_engine_cs *engine,
struct i915_request *rq)
{
- struct list_head *pl;
- LIST_HEAD(list);
+ struct list_head *pos = &rq->sched.waiters_list;
+ const int prio = rq_prio(rq);
+ struct i915_request *rn;
+ LIST_HEAD(dfs);
lockdep_assert_held(&engine->active.lock);
GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags));
@@ -477,14 +479,11 @@ void __i915_sched_defer_request(struct intel_engine_cs
*engine,
* to those that are waiting upon it. So we traverse its chain of
* waiters and move any that are earlier than the request to after it.
*/
- pl = lookup_priolist(engine, rq_prio(rq));
+ rq->sched.dfs.prev = NULL;
do {
- struct i915_dependency *p;
-
- GEM_BUG_ON(i915_request_is_active(rq));
- list_move_tail(&rq->sched.link, pl);
-
- for_each_waiter(p, rq) {
+ list_for_each_continue(pos, &rq->sched.waiters_list) {
+ struct i915_dependency *p =
+ list_entry(pos, typeof(*p), wait_link);
struct i915_request *w =
container_of(p->waiter, typeof(*w), sched);
@@ -500,19 +499,44 @@ void __i915_sched_defer_request(struct intel_engine_cs
*engine,
__i915_request_has_started(w) &&
!__i915_request_is_complete(rq));
- if (!i915_request_is_ready(w))
+ if (!i915_request_in_priority_queue(w))
continue;
- if (rq_prio(w) < rq_prio(rq))
+ /*
+* We also need to reorder within the same priority.
+*
+* This is unlike priority-inheritance, where if the
+* signaler already has a higher priority [earlier
+* deadline] than us, we can ignore as it will be
+* scheduled first. If a waiter already has the
+* same priority, we still have to push it to the end
+* of the list. This unfortunately means we cannot
+* use the rq_deadline() itself as a 'visited' bit.
+*/
+ if (rq_prio(w) < prio)
continue;
- GEM_BUG_ON(rq_prio(w) > rq_prio(rq));
- GEM_BUG_ON(i915_request_is_active(w));
- list_move_tail(&w->sched.link, &list);
+ GEM_BUG_ON(rq_prio(w) != prio);
+
+ /* Remember our position along this branch */
+ rq = stack_push(w, rq, pos);
+ pos = &rq->sched.waiters_list;
}
- rq = list_first_entry_or_null(&list, typeof(*rq), sched.link);
- } while (rq);
+ /* Note list is reversed for waiters wrt signal hierarchy */
+ GEM_BUG_ON(rq->engine != engine);
+ GEM_BUG_ON(!i915_request_in_priority_queue(rq));
+ list_move(&rq->sched.link, &dfs);
+
+ /* Track our visit, and prevent duplicate processing */
+ clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
+ } while ((rq = stack_pop(rq, &pos)));
+
+ pos = lookup_priolist(engine, prio);
+ list_for_each_entry_safe(rq, rn, &dfs, sched.link) {
+ set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
+ list_add_tail(&rq->sched.link, pos);
+ }
}
static void queue_request(struct intel_engine_cs *engine,
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 05/14] drm/i915: Restructure priority inheritance
In anticipation of wanting to be able to call pi from underneath an
engine's active.lock, rework the priority inheritance to primarily work
along an engine's priority queue, delegating any other engine that the
chain may traverse to a worker. This reduces the global spinlock from
governing the entire multi-engine priority inheritance depth-first search,
to a smaller lock on each engine around a single list on that engine.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 3 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +
drivers/gpu/drm/i915/i915_scheduler.c | 356 +++---
drivers/gpu/drm/i915/i915_scheduler.h | 3 +
drivers/gpu/drm/i915/i915_scheduler_types.h | 23 +-
6 files changed, 249 insertions(+), 141 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 92a3c8a43e14..36c6b8d7287d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -582,6 +582,8 @@ void intel_engine_init_execlists(struct intel_engine_cs
*engine)
execlists->queue_priority_hint = INT_MIN;
execlists->queue = RB_ROOT_CACHED;
+
+ i915_sched_init_ipi(&execlists->ipi);
}
static void cleanup_status_page(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index 0b026cde9f09..48a91c0dbad6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -114,8 +114,7 @@ static void heartbeat(struct work_struct *wrk)
* but all other contexts, including the kernel
* context are stuck waiting for the signal.
*/
- } else if (intel_engine_has_scheduler(engine) &&
- rq->sched.attr.priority < I915_PRIORITY_BARRIER) {
+ } else if (rq->sched.attr.priority < I915_PRIORITY_BARRIER) {
/*
* Gradually raise the priority of the heartbeat to
* give high priority work [which presumably desires
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index cb81f0d93189..1b404fef40a6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -20,6 +20,7 @@
#include "i915_gem.h"
#include "i915_pmu.h"
#include "i915_priolist_types.h"
+#include "i915_scheduler_types.h"
#include "i915_selftest.h"
#include "intel_breadcrumbs_types.h"
#include "intel_sseu.h"
@@ -257,6 +258,8 @@ struct intel_engine_execlists {
struct rb_root_cached queue;
struct rb_root_cached virtual;
+ struct i915_sched_ipi ipi;
+
/**
* @csb_write: control register for Context Switch buffer
*
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 84a55df88687..035e4be5d573 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -17,7 +17,25 @@ static struct i915_global_scheduler {
struct kmem_cache *slab_priorities;
} global;
-static DEFINE_SPINLOCK(schedule_lock);
+/*
+ * Virtual engines complicate acquiring the engine timeline lock,
+ * as their rq->engine pointer is not stable until under that
+ * engine lock. The simple ploy we use is to take the lock then
+ * check that the rq still belongs to the newly locked engine.
+ */
+#define lock_engine_irqsave(rq, flags) ({ \
+ struct i915_request * const rq__ = (rq); \
+ struct intel_engine_cs *engine__ = READ_ONCE(rq__->engine); \
+\
+ spin_lock_irqsave(&engine__->active.lock, (flags)); \
+ while (engine__ != READ_ONCE((rq__)->engine)) { \
+ spin_unlock(&engine__->active.lock); \
+ engine__ = READ_ONCE(rq__->engine); \
+ spin_lock(&engine__->active.lock); \
+ } \
+\
+ engine__; \
+})
static struct i915_sched_node *node_get(struct i915_sched_node *node)
{
@@ -30,17 +48,104 @@ static void node_put(struct i915_sched_node *node)
i915_request_put(container_of(node, struct i915_request, sched));
}
+static inline int rq_prio(const struct i915_request *rq)
+{
+ return READ_ONCE(rq->sched.attr.priority);
+}
+
+static int ipi_get_prio(struct i915_request *rq)
+{
+ if (READ_ONCE(rq->sched.ipi_priority) == I915_PRIORITY_INVALID)
+ return I915_PRIORITY_INVALID;
+
+ return xchg(&rq->sched.ipi_priority, I915_PRIORITY_INVALID);
+}
+
+static void ipi_schedule(struct work_struct *wrk)
+{
+ struct i915_sched_ipi *ipi = container_of(wrk, typeof(*ipi), work);
+ struct i915_request *rq = xchg(&ipi->list, NULL);
+
+ do {
+
[Intel-gfx] [CI 13/14] drm/i915: Extract the ability to defer and rerun a request later
Lift the ability to defer a request until later from execlists into the
common layer.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 57 +++--
drivers/gpu/drm/i915/i915_scheduler.c | 63 +--
drivers/gpu/drm/i915/i915_scheduler.h | 5 +-
3 files changed, 67 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index a971b3bee532..b1761d937a5f 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -978,54 +978,6 @@ static void virtual_xfer_context(struct virtual_engine *ve,
}
}
-static void defer_request(struct i915_request *rq, struct list_head * const pl)
-{
- LIST_HEAD(list);
-
- /*
-* We want to move the interrupted request to the back of
-* the round-robin list (i.e. its priority level), but
-* in doing so, we must then move all requests that were in
-* flight and were waiting for the interrupted request to
-* be run after it again.
-*/
- do {
- struct i915_dependency *p;
-
- GEM_BUG_ON(i915_request_is_active(rq));
- list_move_tail(&rq->sched.link, pl);
-
- for_each_waiter(p, rq) {
- struct i915_request *w =
- container_of(p->waiter, typeof(*w), sched);
-
- if (p->flags & I915_DEPENDENCY_WEAK)
- continue;
-
- /* Leave semaphores spinning on the other engines */
- if (w->engine != rq->engine)
- continue;
-
- /* No waiter should start before its signaler */
- GEM_BUG_ON(i915_request_has_initial_breadcrumb(w) &&
- __i915_request_has_started(w) &&
- !__i915_request_is_complete(rq));
-
- if (!i915_request_is_ready(w))
- continue;
-
- if (rq_prio(w) < rq_prio(rq))
- continue;
-
- GEM_BUG_ON(rq_prio(w) > rq_prio(rq));
- GEM_BUG_ON(i915_request_is_active(w));
- list_move_tail(&w->sched.link, &list);
- }
-
- rq = list_first_entry_or_null(&list, typeof(*rq), sched.link);
- } while (rq);
-}
-
static void defer_active(struct intel_engine_cs *engine)
{
struct i915_request *rq;
@@ -1034,7 +986,14 @@ static void defer_active(struct intel_engine_cs *engine)
if (!rq)
return;
- defer_request(rq, i915_sched_lookup_priolist(engine, rq_prio(rq)));
+ /*
+* We want to move the interrupted request to the back of
+* the round-robin list (i.e. its priority level), but
+* in doing so, we must then move all requests that were in
+* flight and were waiting for the interrupted request to
+* be run after it again.
+*/
+ __i915_sched_defer_request(engine, rq);
}
static bool
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index a5df27061c3c..641141f3ce10 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -179,8 +179,8 @@ static void assert_priolists(struct intel_engine_execlists
* const execlists)
}
}
-struct list_head *
-i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio)
+static struct list_head *
+lookup_priolist(struct intel_engine_cs *engine, int prio)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
struct i915_priolist *p;
@@ -332,7 +332,7 @@ static void __i915_request_set_priority(struct i915_request
*rq, int prio)
struct list_head *pos = &rq->sched.signalers_list;
struct list_head *plist;
- plist = i915_sched_lookup_priolist(engine, prio);
+ plist = lookup_priolist(engine, prio);
/*
* Recursively bump all dependent priorities to match the new request.
@@ -463,12 +463,63 @@ void i915_request_set_priority(struct i915_request *rq,
int prio)
spin_unlock_irqrestore(&engine->active.lock, flags);
}
+void __i915_sched_defer_request(struct intel_engine_cs *engine,
+ struct i915_request *rq)
+{
+ struct list_head *pl;
+ LIST_HEAD(list);
+
+ lockdep_assert_held(&engine->active.lock);
+ GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags));
+
+ /*
+* When we defer a request, we must maintain its order with respect
+* to those that are waiting upon it. So we traverse its chain of
+* waiters and move any that are earlier than the reques
[Intel-gfx] [CI 01/14] drm/i915/gt: Move engine setup out of set_default_submission
Now that we no longer switch back and forth between guc and execlists,
we no longer need to restore the backend's vfunc and can leave them set
after initialisation. The only catch is that we lose the submission on
wedging and still need to reset the submit_request vfunc on unwedging.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 46 -
.../gpu/drm/i915/gt/intel_ring_submission.c | 4 --
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 50 ---
3 files changed, 44 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 45a8ac152b88..5d824e1cfcba 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3089,29 +3089,6 @@ static void execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->submit_request = execlists_submit_request;
engine->schedule = i915_schedule;
engine->execlists.tasklet.callback = execlists_submission_tasklet;
-
- engine->reset.prepare = execlists_reset_prepare;
- engine->reset.rewind = execlists_reset_rewind;
- engine->reset.cancel = execlists_reset_cancel;
- engine->reset.finish = execlists_reset_finish;
-
- engine->park = execlists_park;
- engine->unpark = NULL;
-
- engine->flags |= I915_ENGINE_SUPPORTS_STATS;
- if (!intel_vgpu_active(engine->i915)) {
- engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
- if (can_preempt(engine)) {
- engine->flags |= I915_ENGINE_HAS_PREEMPTION;
- if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
- engine->flags |= I915_ENGINE_HAS_TIMESLICES;
- }
- }
-
- if (intel_engine_has_preemption(engine))
- engine->emit_bb_start = gen8_emit_bb_start;
- else
- engine->emit_bb_start = gen8_emit_bb_start_noarb;
}
static void execlists_shutdown(struct intel_engine_cs *engine)
@@ -3142,6 +3119,14 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
engine->cops = &execlists_context_ops;
engine->request_alloc = execlists_request_alloc;
+ engine->reset.prepare = execlists_reset_prepare;
+ engine->reset.rewind = execlists_reset_rewind;
+ engine->reset.cancel = execlists_reset_cancel;
+ engine->reset.finish = execlists_reset_finish;
+
+ engine->park = execlists_park;
+ engine->unpark = NULL;
+
engine->emit_flush = gen8_emit_flush_xcs;
engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
@@ -3162,6 +3147,21 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
* until a more refined solution exists.
*/
}
+
+ engine->flags |= I915_ENGINE_SUPPORTS_STATS;
+ if (!intel_vgpu_active(engine->i915)) {
+ engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
+ if (can_preempt(engine)) {
+ engine->flags |= I915_ENGINE_HAS_PREEMPTION;
+ if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
+ engine->flags |= I915_ENGINE_HAS_TIMESLICES;
+ }
+ }
+
+ if (intel_engine_has_preemption(engine))
+ engine->emit_bb_start = gen8_emit_bb_start;
+ else
+ engine->emit_bb_start = gen8_emit_bb_start_noarb;
}
static void logical_ring_default_irqs(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 9c2c605d7a92..3cb2ce503544 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -969,14 +969,10 @@ static void gen6_bsd_submit_request(struct i915_request
*request)
static void i9xx_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = i9xx_submit_request;
-
- engine->park = NULL;
- engine->unpark = NULL;
}
static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
{
- i9xx_set_default_submission(engine);
engine->submit_request = gen6_bsd_submit_request;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 92688a9b6717..f72faa0b8339 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -608,35 +608,6 @@ static int guc_resume(struct intel_engine_cs *engine)
static void guc_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = guc_submit_request;
- engine->schedule = i915_schedule;
- engine->execl
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v14,1/2] drm/i915/display: Support PSR Multiple Instances
On Fri, 2021-01-29 at 11:45 +, Patchwork wrote: > == Series Details == > > Series: series starting with [v14,1/2] drm/i915/display: Support PSR > Multiple Instances > URL : https://patchwork.freedesktop.org/series/86445/ > State : warning > > == Summary == > > $ dim checkpatch origin/drm-tip > e7df7e13f87c drm/i915/display: Support PSR Multiple Instances > -:88: ERROR:COMPLEX_MACRO: Macros with complex values should be > enclosed in parentheses > #88: FILE: drivers/gpu/drm/i915/display/intel_display.h:420: > +#define for_each_intel_encoder_mask_can_psr(dev, intel_encoder, > encoder_mask) \ > + list_for_each_entry((intel_encoder), &(dev)- > >mode_config.encoder_list, base.head) \ > + for_each_if(((encoder_mask) & > drm_encoder_mask(&(intel_encoder)->base)) && \ > + intel_encoder_can_psr(intel_encoder)) > > -:88: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_encoder' - > possible side-effects? > #88: FILE: drivers/gpu/drm/i915/display/intel_display.h:420: > +#define for_each_intel_encoder_mask_can_psr(dev, intel_encoder, > encoder_mask) \ > + list_for_each_entry((intel_encoder), &(dev)- > >mode_config.encoder_list, base.head) \ > + for_each_if(((encoder_mask) & > drm_encoder_mask(&(intel_encoder)->base)) && \ > + intel_encoder_can_psr(intel_encoder)) > > -:97: ERROR:COMPLEX_MACRO: Macros with complex values should be > enclosed in parentheses > #97: FILE: drivers/gpu/drm/i915/display/intel_display.h:429: > +#define for_each_intel_encoder_can_psr(dev, intel_encoder) \ > + for_each_intel_encoder((dev), (intel_encoder)) \ > + for_each_if(intel_encoder_can_psr(intel_encoder)) > > -:97: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_encoder' - > possible side-effects? > #97: FILE: drivers/gpu/drm/i915/display/intel_display.h:429: > +#define for_each_intel_encoder_can_psr(dev, intel_encoder) \ > + for_each_intel_encoder((dev), (intel_encoder)) \ > + for_each_if(intel_encoder_can_psr(intel_encoder)) > > -:375: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - > possible side-effects? > #375: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1795: > +#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && \ > + (intel_dp)->psr.sink_support && \ > + (intel_dp)->psr.source_support) > > total: 2 errors, 0 warnings, 3 checks, 1730 lines checked > 02d0fee29897 drm/i915/display: Support Multiple Transcoders' PSR > status on debugfs > > The reported error related code are followed other intel display.h's macro style and it is intended code. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Fixes that failed to apply to v5.11-rc4
Hi,
On Tue, Feb 02, 2021 at 09:15:18AM +0200, Jani Nikula wrote:
> On Mon, 18 Jan 2021, Jani Nikula wrote:
> > The following commits have been marked as Cc: stable or fixing something
> > in v5.11-rc4 or earlier, but failed to cherry-pick to
> > drm-intel-fixes. Please see if they are worth backporting, and please do
> > so if they are.
> >
> > Conflicts:
> > dbe13ae1d6ab ("drm/i915/pmu: Don't grab wakeref when enabling events")
> > 9bb36cf66091 ("drm/i915: Check for rq->hwsp validity after acquiring RCU
> > lock")
> > 5b4dc95cf7f5 ("drm/i915/gt: Prevent use of engine->wa_ctx after error")
> > 6a3daee1b38e ("drm/i915/selftests: Fix some error codes")
> > 67fba3f1c73b ("drm/i915/dp: Fix LTTPR vswing/pre-emp setting in
> > non-transparent mode")
> >
> > Fails to build:
> > 3170a21f7059 ("drm/i915: Only enable DFP 4:4:4->4:2:0 conversion when
> > outputting YCbCr 4:4:4")
> >
> > BR,
> > Jani.
>
> Update.
>
> Conflicts:
> 5b4dc95cf7f5 ("drm/i915/gt: Prevent use of engine->wa_ctx after error")
> 6a3daee1b38e ("drm/i915/selftests: Fix some error codes")
> 67fba3f1c73b ("drm/i915/dp: Fix LTTPR vswing/pre-emp setting in
> non-transparent mode")
This depends on
1c6e527d6947 ("rm/i915/dp: Move intel_dp_set_signal_levels() to
intel_dp_link_training.c")
> 699390f7f026 ("drm/i915: Fix the PHY compliance test vs. hotplug mishap")
> e7004ea4f5f5 ("drm/i915/gt: Close race between enable_breadcrumbs and
> cancel_breadcrumbs")
> fed387572040 ("drm/i915/display: Prevent double YUV range correction on HDR
> planes")
>
> Fails to build:
> 0713eb979d2c ("drm/i915: Disable atomics in L3 for gen9")
> f8abfda84841 ("drm/i915: Fix the MST PBN divider calculation")
and this one depends on
a321fc2b4e60 ("rm/dp/mst: Export drm_dp_get_vc_payload_bw()")
>
> BR,
> Jani.
>
> --
> Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 19/57] drm/i915: Fix the iterative dfs for defering requests
On 01/02/2021 08:56, Chris Wilson wrote:
The current implementation of walking the children of a deferred
requests lacks the backtracking required to reduce the dfs to linear.
Having pulled it from execlists into the common layer, we can reuse the
dfs code for priority inheritance.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_scheduler.c | 56 +++
1 file changed, 40 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index bfd37ee801fd..694ca3a3b563 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -466,8 +466,10 @@ void i915_request_set_priority(struct i915_request *rq,
int prio)
void __i915_sched_defer_request(struct intel_engine_cs *engine,
struct i915_request *rq)
{
- struct list_head *pl;
- LIST_HEAD(list);
+ struct list_head *pos = &rq->sched.waiters_list;
+ const int prio = rq_prio(rq);
+ struct i915_request *rn;
+ LIST_HEAD(dfs);
lockdep_assert_held(&engine->active.lock);
GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags));
@@ -477,14 +479,11 @@ void __i915_sched_defer_request(struct intel_engine_cs
*engine,
* to those that are waiting upon it. So we traverse its chain of
* waiters and move any that are earlier than the request to after it.
*/
- pl = lookup_priolist(engine, rq_prio(rq));
+ rq->sched.dfs.prev = NULL;
do {
- struct i915_dependency *p;
-
- GEM_BUG_ON(i915_request_is_active(rq));
- list_move_tail(&rq->sched.link, pl);
-
- for_each_waiter(p, rq) {
+ list_for_each_continue(pos, &rq->sched.waiters_list) {
+ struct i915_dependency *p =
+ list_entry(pos, typeof(*p), wait_link);
struct i915_request *w =
container_of(p->waiter, typeof(*w), sched);
@@ -500,19 +499,44 @@ void __i915_sched_defer_request(struct intel_engine_cs *engine,
__i915_request_has_started(w) &&
!__i915_request_is_complete(rq));
- if (!i915_request_is_ready(w))
+ if (!i915_request_in_priority_queue(w))
continue;
- if (rq_prio(w) < rq_prio(rq))
+ /*
+* We also need to reorder within the same priority.
+*
+* This is unlike priority-inheritance, where if the
+* signaler already has a higher priority [earlier
+* deadline] than us, we can ignore as it will be
+* scheduled first. If a waiter already has the
+* same priority, we still have to push it to the end
+* of the list. This unfortunately means we cannot
+* use the rq_deadline() itself as a 'visited' bit.
rq_deadline only appears later but never mind.
+*/
+ if (rq_prio(w) < prio)
continue;
- GEM_BUG_ON(rq_prio(w) > rq_prio(rq));
- GEM_BUG_ON(i915_request_is_active(w));
- list_move_tail(&w->sched.link, &list);
+ GEM_BUG_ON(rq_prio(w) != prio);
+
+ /* Remember our position along this branch */
+ rq = stack_push(w, rq, pos);
+ pos = &rq->sched.waiters_list;
}
- rq = list_first_entry_or_null(&list, typeof(*rq), sched.link);
- } while (rq);
+ /* Note list is reversed for waiters wrt signal hierarchy */
+ GEM_BUG_ON(rq->engine != engine);
+ GEM_BUG_ON(!i915_request_in_priority_queue(rq));
+ list_move(&rq->sched.link, &dfs);
+
+ /* Track our visit, and prevent duplicate processing */
+ clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
+ } while ((rq = stack_pop(rq, &pos)));
+
+ pos = lookup_priolist(engine, prio);
+ list_for_each_entry_safe(rq, rn, &dfs, sched.link) {
+ set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
+ list_add_tail(&rq->sched.link, pos);
+ }
}
static void queue_request(struct intel_engine_cs *engine,
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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Re: [Intel-gfx] [PULL] topic/adl-s-enabling into drm-intel-next
Quoting Jani Nikula (2021-02-02 13:19:13) > On Mon, 01 Feb 2021, Lucas De Marchi wrote: > > Hi Rodrigo/Jani, > > > > Here are the changes to add basic Alder Lake S support in the driver, with > > patches touching both generic parts, gt and display. Remaining changes don't > > need a topic branch anymore and can be applied individually to each branch. > > Thanks, pulled to drm-intel-next, and Joonas pulled to drm-intel-gt-next > too. I pulled this exact same tag for clarity. We had two tags pointing at the exactly same commit and the other was missing the tag description. For future reference one pull request directed at multiple trees should be fine. Regards, Joonas > BR, > Jani. > > > > > > thanks > > Lucas De Marchi > > > > *** > > > > topic/adl-s-enabling-2021-02-01-1: > > > > Driver Changes: > > - Add basic support for Alder Lake S, to be shared between > > drm-intel-next and drm-intel-gt-next > > > > The following changes since commit fb5cfcaa2efbb4c71abb1dfbc8f4da727e0bfd89: > > > > Merge tag 'drm-intel-gt-next-2021-01-14' of > > git://anongit.freedesktop.org/drm/drm-intel into drm-next (2021-01-15 > > 15:03:36 +1000) > > > > are available in the Git repository at: > > > > git://anongit.freedesktop.org/drm/drm-intel > > tags/topic/adl-s-enabling-2021-02-01-1 > > > > for you to fetch changes up to 4043277ad18fc7cb9a79d0d043063fb5f42a6f06: > > > > drm/i915/adl_s: Add GT and CTX WAs for ADL-S (2021-02-01 07:59:11 -0800) > > > > > > Driver Changes: > > - Add basic support for Alder Lake S, to be shared between > > drm-intel-next and drm-intel-gt-next > > > > > > Aditya Swarup (8): > > drm/i915/tgl: Use TGL stepping info for applying WAs > > drm/i915/adl_s: Configure DPLL for ADL-S > > drm/i915/adl_s: Configure Port clock registers for ADL-S > > drm/i915/adl_s: Initialize display for ADL-S > > drm/i915/adl_s: Add adl-s ddc pin mapping > > drm/i915/adl_s: Add vbt port and aux channel settings for adls > > drm/i915/adl_s: Add display WAs for ADL-S > > drm/i915/adl_s: Add GT and CTX WAs for ADL-S > > > > Anusha Srivatsa (4): > > drm/i915/adl_s: Add PCH support > > drm/i915/adl_s: Add Interrupt Support > > drm/i915/adl_s: Add PHYs for Alderlake S > > drm/i915/adl_s: Load DMC > > > > Caz Yokoyama (2): > > drm/i915/adl_s: Add ADL-S platform info and PCI ids > > x86/gpu: Add Alderlake-S stolen memory support > > > > José Roberto de Souza (1): > > drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION > > > > Lucas De Marchi (1): > > drm/i915/adl_s: Add power wells > > > > Matt Roper (3): > > drm/i915/adl_s: Update combo PHY master/slave relationships > > drm/i915/adl_s: Update PHY_MISC programming > > drm/i915/adl_s: Re-use TGL GuC/HuC firmware > > > > Tejas Upadhyay (1): > > drm/i915/adl_s: Update memory bandwidth parameters > > > > arch/x86/kernel/early-quirks.c | 1 + > > drivers/gpu/drm/i915/display/intel_bios.c | 70 +++ > > drivers/gpu/drm/i915/display/intel_bw.c| 10 ++- > > drivers/gpu/drm/i915/display/intel_combo_phy.c | 23 +-- > > drivers/gpu/drm/i915/display/intel_csr.c | 10 ++- > > drivers/gpu/drm/i915/display/intel_ddi.c | 62 +++-- > > drivers/gpu/drm/i915/display/intel_display.c | 31 ++--- > > drivers/gpu/drm/i915/display/intel_display_power.c | 11 +-- > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 -- > > drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +- > > drivers/gpu/drm/i915/display/intel_psr.c | 4 +- > > drivers/gpu/drm/i915/display/intel_sprite.c| 8 +-- > > drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++ > > drivers/gpu/drm/i915/gt/intel_workarounds.c| 68 +++--- > > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +- > > drivers/gpu/drm/i915/i915_drv.h| 80 > > ++ > > drivers/gpu/drm/i915/i915_irq.c| 5 +- > > drivers/gpu/drm/i915/i915_pci.c| 13 > > drivers/gpu/drm/i915/i915_reg.h| 50 -- > > drivers/gpu/drm/i915/intel_device_info.c | 9 ++- > > drivers/gpu/drm/i915/intel_device_info.h | 1 + > > drivers/gpu/drm/i915/intel_pch.c | 8 ++- > > drivers/gpu/drm/i915/intel_pch.h | 3 + > > drivers/gpu/drm/i915/intel_pm.c| 2 +- > > include/drm/i915_pciids.h | 11 +++ > > 25 files changed, 417 insertions(+), 129 deletions(-) > > -- > Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.fre
Re: [Intel-gfx] [PATCH 17/57] drm/i915: Extract request suspension from the execlists
On 02/02/2021 13:26, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-02-02 13:15:52)
On 01/02/2021 08:56, Chris Wilson wrote:
+void __i915_sched_resume_request(struct intel_engine_cs *engine,
+ struct i915_request *rq)
+{
+ LIST_HEAD(list);
+
+ lockdep_assert_held(&engine->active.lock);
+
+ if (rq_prio(rq) > engine->execlists.queue_priority_hint) {
+ engine->execlists.queue_priority_hint = rq_prio(rq);
+ tasklet_hi_schedule(&engine->execlists.tasklet);
+ }
+
+ if (!i915_request_on_hold(rq))
+ return;
+
+ ENGINE_TRACE(engine, "resuming request %llx:%lld\n",
+ rq->fence.context, rq->fence.seqno);
+
+ /*
+ * Move this request back to the priority queue, and all of its
+ * children and grandchildren that were suspended along with it.
+ */
+ do {
+ struct i915_dependency *p;
+
+ RQ_TRACE(rq, "hold release\n");
+
+ GEM_BUG_ON(!i915_request_on_hold(rq));
+ GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
+
+ i915_request_clear_hold(rq);
+ list_del_init(&rq->sched.link);
+
+ queue_request(engine, rq);
+
+ /* Also release any children on this engine that are ready */
+ for_each_waiter(p, rq) {
+ struct i915_request *w =
+ container_of(p->waiter, typeof(*w), sched);
+
+ if (p->flags & I915_DEPENDENCY_WEAK)
+ continue;
+
+ /* Propagate any change in error status */
+ if (rq->fence.error)
+ i915_request_set_error_once(w, rq->fence.error);
+
+ if (w->engine != engine)
+ continue;
+
+ /* We also treat the on-hold status as a visited bit */
+ if (!i915_request_on_hold(w))
+ continue;
+
+ /* Check that no other parents are also on hold [BFS] */
+ if (hold_request(w))
+ continue;
hold_request() appears deleted in the patch so possible rebase error.
The secret is we get to de-duplicate after having duplicated
hold_request() in i915_scheduler in an earlier patch,
drm/i915: Extract request submission from execlists
Pfft ancient history long forgotten..
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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Re: [Intel-gfx] [PULL] topic/drm-device-pdev
Quoting Jani Nikula (2021-02-02 14:37:00) > > Hi Joonas - > > This is Thomas's drm_device.pdev removal for i915, the first three > patches from [1]. Let's merge to both drm-intel-next and > drm-intel-gt-next. This is now merged. Regards, Joonas > Zhenyu & Zhi, FYI, this touches gvt too, and it was getting a bit too > complicated to handle all the components separately. Hopefully you won't > have too many conflicts when backmerging. > > > topic/drm-device-pdev-2021-02-02: > Driver Changes: > - drm/i915: Remove references to struct drm_device.pdev > > BR, > Jani. > > [1] http://lore.kernel.org/r/20210128133127.2311-1-tzimmerm...@suse.de > > > The following changes since commit 4043277ad18fc7cb9a79d0d043063fb5f42a6f06: > > drm/i915/adl_s: Add GT and CTX WAs for ADL-S (2021-02-01 07:59:11 -0800) > > are available in the Git repository at: > > git://anongit.freedesktop.org/drm/drm-intel > tags/topic/drm-device-pdev-2021-02-02 > > for you to fetch changes up to 9ff06c38530099b197b6389193e8cc34ab60288f: > > drm/i915/gvt: Remove references to struct drm_device.pdev (2021-02-02 > 13:58:45 +0200) > > > Driver Changes: > - drm/i915: Remove references to struct drm_device.pdev > > > Thomas Zimmermann (3): > drm/i915: Remove references to struct drm_device.pdev > drm/i915/gt: Remove references to struct drm_device.pdev > drm/i915/gvt: Remove references to struct drm_device.pdev > > drivers/gpu/drm/i915/display/intel_bios.c | 2 +- > drivers/gpu/drm/i915/display/intel_cdclk.c | 14 +++--- > drivers/gpu/drm/i915/display/intel_csr.c | 2 +- > drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 +- > drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +- > drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +- > drivers/gpu/drm/i915/display/intel_lpe_audio.c | 5 +++-- > drivers/gpu/drm/i915/display/intel_opregion.c | 6 +++--- > drivers/gpu/drm/i915/display/intel_overlay.c | 2 +- > drivers/gpu/drm/i915/display/intel_panel.c | 4 ++-- > drivers/gpu/drm/i915/display/intel_quirks.c| 2 +- > drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +- > drivers/gpu/drm/i915/display/intel_vga.c | 8 > drivers/gpu/drm/i915/gem/i915_gem_phys.c | 6 +++--- > drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 2 +- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- > drivers/gpu/drm/i915/gt/intel_ggtt.c | 10 +- > drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +- > drivers/gpu/drm/i915/gt/intel_rc6.c| 4 ++-- > drivers/gpu/drm/i915/gt/intel_region_lmem.c| 8 > drivers/gpu/drm/i915/gt/intel_reset.c | 6 +++--- > drivers/gpu/drm/i915/gvt/cfg_space.c | 5 +++-- > drivers/gpu/drm/i915/gvt/firmware.c| 10 +- > drivers/gpu/drm/i915/gvt/gtt.c | 12 ++-- > drivers/gpu/drm/i915/gvt/gvt.c | 6 +++--- > drivers/gpu/drm/i915/gvt/kvmgt.c | 4 ++-- > drivers/gpu/drm/i915/i915_debugfs.c| 2 +- > drivers/gpu/drm/i915/i915_drv.c| 19 +-- > drivers/gpu/drm/i915/i915_drv.h| 2 +- > drivers/gpu/drm/i915/i915_gem_gtt.c| 5 ++--- > drivers/gpu/drm/i915/i915_getparam.c | 5 +++-- > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > drivers/gpu/drm/i915/i915_irq.c| 6 +++--- > drivers/gpu/drm/i915/i915_pmu.c| 2 +- > drivers/gpu/drm/i915/i915_suspend.c| 4 ++-- > drivers/gpu/drm/i915/i915_switcheroo.c | 4 ++-- > drivers/gpu/drm/i915/i915_vgpu.c | 2 +- > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > drivers/gpu/drm/i915/intel_runtime_pm.c| 2 +- > drivers/gpu/drm/i915/intel_uncore.c| 4 ++-- > drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 +- > 41 files changed, 97 insertions(+), 96 deletions(-) > > -- > Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 17/57] drm/i915: Extract request suspension from the execlists
Quoting Tvrtko Ursulin (2021-02-02 13:15:52)
>
> On 01/02/2021 08:56, Chris Wilson wrote:
> > Make the ability to suspend and resume a request and its dependents
> > generic.
> > +bool __i915_sched_suspend_request(struct intel_engine_cs *engine,
> > + struct i915_request *rq)
> > +{
> > + LIST_HEAD(list);
> > +
> > + lockdep_assert_held(&engine->active.lock);
> > + GEM_BUG_ON(rq->engine != engine);
> > +
> > + if (__i915_request_is_complete(rq)) /* too late! */
> > + return false;
> > +
> > + if (i915_request_on_hold(rq))
> > + return false;
>
> This was a GEM_BUG_ON before so not pure extraction / code movement.
It was part of making it generic to allow other callers.
-Chris
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Re: [Intel-gfx] [PATCH 17/57] drm/i915: Extract request suspension from the execlists
Quoting Tvrtko Ursulin (2021-02-02 13:15:52)
>
> On 01/02/2021 08:56, Chris Wilson wrote:
> > +void __i915_sched_resume_request(struct intel_engine_cs *engine,
> > + struct i915_request *rq)
> > +{
> > + LIST_HEAD(list);
> > +
> > + lockdep_assert_held(&engine->active.lock);
> > +
> > + if (rq_prio(rq) > engine->execlists.queue_priority_hint) {
> > + engine->execlists.queue_priority_hint = rq_prio(rq);
> > + tasklet_hi_schedule(&engine->execlists.tasklet);
> > + }
> > +
> > + if (!i915_request_on_hold(rq))
> > + return;
> > +
> > + ENGINE_TRACE(engine, "resuming request %llx:%lld\n",
> > + rq->fence.context, rq->fence.seqno);
> > +
> > + /*
> > + * Move this request back to the priority queue, and all of its
> > + * children and grandchildren that were suspended along with it.
> > + */
> > + do {
> > + struct i915_dependency *p;
> > +
> > + RQ_TRACE(rq, "hold release\n");
> > +
> > + GEM_BUG_ON(!i915_request_on_hold(rq));
> > + GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
> > +
> > + i915_request_clear_hold(rq);
> > + list_del_init(&rq->sched.link);
> > +
> > + queue_request(engine, rq);
> > +
> > + /* Also release any children on this engine that are ready */
> > + for_each_waiter(p, rq) {
> > + struct i915_request *w =
> > + container_of(p->waiter, typeof(*w), sched);
> > +
> > + if (p->flags & I915_DEPENDENCY_WEAK)
> > + continue;
> > +
> > + /* Propagate any change in error status */
> > + if (rq->fence.error)
> > + i915_request_set_error_once(w,
> > rq->fence.error);
> > +
> > + if (w->engine != engine)
> > + continue;
> > +
> > + /* We also treat the on-hold status as a visited bit
> > */
> > + if (!i915_request_on_hold(w))
> > + continue;
> > +
> > + /* Check that no other parents are also on hold [BFS]
> > */
> > + if (hold_request(w))
> > + continue;
>
> hold_request() appears deleted in the patch so possible rebase error.
The secret is we get to de-duplicate after having duplicated
hold_request() in i915_scheduler in an earlier patch,
drm/i915: Extract request submission from execlists
-Chris
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Re: [Intel-gfx] [PATCH 18/57] drm/i915: Extract the ability to defer and rerun a request later
On 01/02/2021 08:56, Chris Wilson wrote:
Lift the ability to defer a request until later from execlists into the
common layer.
Signed-off-by: Chris Wilson
---
.../drm/i915/gt/intel_execlists_submission.c | 57 +++--
drivers/gpu/drm/i915/i915_scheduler.c | 63 +--
drivers/gpu/drm/i915/i915_scheduler.h | 5 +-
3 files changed, 67 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 853021314786..b56e321ef003 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -978,54 +978,6 @@ static void virtual_xfer_context(struct virtual_engine *ve,
}
}
-static void defer_request(struct i915_request *rq, struct list_head * const pl)
-{
- LIST_HEAD(list);
-
- /*
-* We want to move the interrupted request to the back of
-* the round-robin list (i.e. its priority level), but
-* in doing so, we must then move all requests that were in
-* flight and were waiting for the interrupted request to
-* be run after it again.
-*/
- do {
- struct i915_dependency *p;
-
- GEM_BUG_ON(i915_request_is_active(rq));
- list_move_tail(&rq->sched.link, pl);
-
- for_each_waiter(p, rq) {
- struct i915_request *w =
- container_of(p->waiter, typeof(*w), sched);
-
- if (p->flags & I915_DEPENDENCY_WEAK)
- continue;
-
- /* Leave semaphores spinning on the other engines */
- if (w->engine != rq->engine)
- continue;
-
- /* No waiter should start before its signaler */
- GEM_BUG_ON(i915_request_has_initial_breadcrumb(w) &&
- __i915_request_has_started(w) &&
- !__i915_request_is_complete(rq));
-
- if (!i915_request_is_ready(w))
- continue;
-
- if (rq_prio(w) < rq_prio(rq))
- continue;
-
- GEM_BUG_ON(rq_prio(w) > rq_prio(rq));
- GEM_BUG_ON(i915_request_is_active(w));
- list_move_tail(&w->sched.link, &list);
- }
-
- rq = list_first_entry_or_null(&list, typeof(*rq), sched.link);
- } while (rq);
-}
-
static void defer_active(struct intel_engine_cs *engine)
{
struct i915_request *rq;
@@ -1034,7 +986,14 @@ static void defer_active(struct intel_engine_cs *engine)
if (!rq)
return;
- defer_request(rq, i915_sched_lookup_priolist(engine, rq_prio(rq)));
+ /*
+* We want to move the interrupted request to the back of
+* the round-robin list (i.e. its priority level), but
+* in doing so, we must then move all requests that were in
+* flight and were waiting for the interrupted request to
+* be run after it again.
+*/
+ __i915_sched_defer_request(engine, rq);
}
static bool
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 351c0c0055b5..bfd37ee801fd 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -179,8 +179,8 @@ static void assert_priolists(struct intel_engine_execlists
* const execlists)
}
}
-struct list_head *
-i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio)
+static struct list_head *
+lookup_priolist(struct intel_engine_cs *engine, int prio)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
struct i915_priolist *p;
@@ -332,7 +332,7 @@ static void __i915_request_set_priority(struct i915_request
*rq, int prio)
struct list_head *pos = &rq->sched.signalers_list;
struct list_head *plist;
- plist = i915_sched_lookup_priolist(engine, prio);
+ plist = lookup_priolist(engine, prio);
/*
* Recursively bump all dependent priorities to match the new request.
@@ -463,12 +463,63 @@ void i915_request_set_priority(struct i915_request *rq,
int prio)
spin_unlock_irqrestore(&engine->active.lock, flags);
}
+void __i915_sched_defer_request(struct intel_engine_cs *engine,
+ struct i915_request *rq)
+{
+ struct list_head *pl;
+ LIST_HEAD(list);
+
+ lockdep_assert_held(&engine->active.lock);
+ GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags));
+
+ /*
+* When we defer a request, we must maintain its order with respect
+* to those that are waiting upon it. So we traverse its chain of
+* waiters and move any that ar
Re: [Intel-gfx] [PATCH 17/57] drm/i915: Extract request suspension from the execlists
On 01/02/2021 08:56, Chris Wilson wrote:
Make the ability to suspend and resume a request and its dependents
generic.
Signed-off-by: Chris Wilson
---
.../drm/i915/gt/intel_execlists_submission.c | 167 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 8 +-
drivers/gpu/drm/i915/i915_scheduler.c | 153
drivers/gpu/drm/i915/i915_scheduler.h | 10 ++
4 files changed, 169 insertions(+), 169 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index b6dea80da533..853021314786 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1921,169 +1921,6 @@ static void post_process_csb(struct i915_request **port,
execlists_schedule_out(*port++);
}
-static void __execlists_hold(struct i915_request *rq)
-{
- LIST_HEAD(list);
-
- do {
- struct i915_dependency *p;
-
- if (i915_request_is_active(rq))
- __i915_request_unsubmit(rq);
-
- clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
- list_move_tail(&rq->sched.link, &rq->engine->active.hold);
- i915_request_set_hold(rq);
- RQ_TRACE(rq, "on hold\n");
-
- for_each_waiter(p, rq) {
- struct i915_request *w =
- container_of(p->waiter, typeof(*w), sched);
-
- if (p->flags & I915_DEPENDENCY_WEAK)
- continue;
-
- /* Leave semaphores spinning on the other engines */
- if (w->engine != rq->engine)
- continue;
-
- if (!i915_request_is_ready(w))
- continue;
-
- if (__i915_request_is_complete(w))
- continue;
-
- if (i915_request_on_hold(w))
- continue;
-
- list_move_tail(&w->sched.link, &list);
- }
-
- rq = list_first_entry_or_null(&list, typeof(*rq), sched.link);
- } while (rq);
-}
-
-static bool execlists_hold(struct intel_engine_cs *engine,
- struct i915_request *rq)
-{
- if (i915_request_on_hold(rq))
- return false;
-
- spin_lock_irq(&engine->active.lock);
-
- if (__i915_request_is_complete(rq)) { /* too late! */
- rq = NULL;
- goto unlock;
- }
-
- /*
-* Transfer this request onto the hold queue to prevent it
-* being resumbitted to HW (and potentially completed) before we have
-* released it. Since we may have already submitted following
-* requests, we need to remove those as well.
-*/
- GEM_BUG_ON(i915_request_on_hold(rq));
- GEM_BUG_ON(rq->engine != engine);
- __execlists_hold(rq);
- GEM_BUG_ON(list_empty(&engine->active.hold));
-
-unlock:
- spin_unlock_irq(&engine->active.lock);
- return rq;
-}
-
-static bool hold_request(const struct i915_request *rq)
-{
- struct i915_dependency *p;
- bool result = false;
-
- /*
-* If one of our ancestors is on hold, we must also be on hold,
-* otherwise we will bypass it and execute before it.
-*/
- rcu_read_lock();
- for_each_signaler(p, rq) {
- const struct i915_request *s =
- container_of(p->signaler, typeof(*s), sched);
-
- if (s->engine != rq->engine)
- continue;
-
- result = i915_request_on_hold(s);
- if (result)
- break;
- }
- rcu_read_unlock();
-
- return result;
-}
-
-static void __execlists_unhold(struct i915_request *rq)
-{
- LIST_HEAD(list);
-
- do {
- struct i915_dependency *p;
-
- RQ_TRACE(rq, "hold release\n");
-
- GEM_BUG_ON(!i915_request_on_hold(rq));
- GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
-
- i915_request_clear_hold(rq);
- list_move_tail(&rq->sched.link,
- i915_sched_lookup_priolist(rq->engine,
- rq_prio(rq)));
- set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
-
- /* Also release any children on this engine that are ready */
- for_each_waiter(p, rq) {
- struct i915_request *w =
- container_of(p->waiter, typeof(*w), sched);
-
- if (p->flags & I915_DEPENDENCY_WEAK)
- continue;
-
- /* Propagate any change in error status */
- if (rq
Re: [Intel-gfx] [PATCH 16/57] drm/i915: Extract request rewinding from execlists
On 01/02/2021 08:56, Chris Wilson wrote:
In the process of preparing to reuse the request submission logic for
other backends, lift it out of the execlists backend.
While this operates on the common structs, we do have a bit of backend
knowledge, which is harmless for !lrc but still unsightly.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h| 3 -
.../drm/i915/gt/intel_execlists_submission.c | 58 ++-
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 3 +
drivers/gpu/drm/i915/gt/selftest_execlists.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 +-
drivers/gpu/drm/i915/i915_scheduler.c | 44 ++
drivers/gpu/drm/i915/i915_scheduler.h | 3 +
7 files changed, 56 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 8d9184920c51..cc2df80eb449 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -137,9 +137,6 @@ execlists_active_unlock_bh(struct intel_engine_execlists
*execlists)
local_bh_enable(); /* restore softirq, and kick ksoftirqd! */
}
-struct i915_request *
-execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
-
static inline u32
intel_read_status_page(const struct intel_engine_cs *engine, int reg)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 51044387a8a2..b6dea80da533 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -359,56 +359,6 @@ assert_priority_queue(const struct i915_request *prev,
return rq_prio(prev) >= rq_prio(next);
}
-static struct i915_request *
-__unwind_incomplete_requests(struct intel_engine_cs *engine)
-{
- struct i915_request *rq, *rn, *active = NULL;
- struct list_head *pl;
- int prio = I915_PRIORITY_INVALID;
-
- lockdep_assert_held(&engine->active.lock);
-
- list_for_each_entry_safe_reverse(rq, rn,
-&engine->active.requests,
-sched.link) {
- if (__i915_request_is_complete(rq)) {
- list_del_init(&rq->sched.link);
- continue;
- }
-
- __i915_request_unsubmit(rq);
-
- GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
- if (rq_prio(rq) != prio) {
- prio = rq_prio(rq);
- pl = i915_sched_lookup_priolist(engine, prio);
- }
- GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
-
- list_move(&rq->sched.link, pl);
- set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
-
- /* Check in case we rollback so far we wrap [size/2] */
- if (intel_ring_direction(rq->ring,
-rq->tail,
-rq->ring->tail + 8) > 0)
- rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE;
-
- active = rq;
- }
-
- return active;
-}
-
-struct i915_request *
-execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
-{
- struct intel_engine_cs *engine =
- container_of(execlists, typeof(*engine), execlists);
-
- return __unwind_incomplete_requests(engine);
-}
-
static void
execlists_context_status_change(struct i915_request *rq, unsigned long status)
{
@@ -1080,7 +1030,7 @@ static void defer_active(struct intel_engine_cs *engine)
{
struct i915_request *rq;
- rq = __unwind_incomplete_requests(engine);
+ rq = __i915_sched_rewind_requests(engine);
if (!rq)
return;
@@ -1292,7 +1242,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* the preemption, some of the unwound requests may
* complete!
*/
- __unwind_incomplete_requests(engine);
+ __i915_sched_rewind_requests(engine);
last = NULL;
} else if (timeslice_expired(engine, last)) {
@@ -2287,7 +2237,7 @@ static void execlists_capture(struct intel_engine_cs
*engine)
* which we return it to the queue for signaling.
*
* By removing them from the execlists queue, we also remove the
-* requests from being processed by __unwind_incomplete_requests()
+* requests from being processed by __intel_engine_rewind_requests()
* during the intel_engine_reset(), and so they will *not* be replayed
* afterwards.
*
@@ -2878,7 +2828,7 @@ static void execlists_reset_rewind(struct intel_engine_cs
*engine, bool stalled)
/* Push back any incomplete request
Re: [Intel-gfx] [PATCH v6 0/5] drm: Move struct drm_device.pdev to legacy
On Thu, 28 Jan 2021, Thomas Zimmermann wrote: > V6 of the patchset fixes i915/selftests to do the assigment of pdev > in a later patch. This was forgotten in v5. > > The pdev field in struct drm_device points to a PCI device structure and > goes back to UMS-only days when all DRM drivers were for PCI devices. > Meanwhile we also support USB, SPI and platform devices. Each of those > uses the generic device stored in struct drm_device.dev. > > To reduce duplication and remove the special case of PCI, this patchset > converts all modesetting drivers from pdev to dev and makes pdev a field > for legacy UMS drivers. > > For PCI devices, the pointer in struct drm_device.dev can be upcasted to > struct pci_device; or tested for PCI with dev_is_pci(). In several places > the code can use the dev field directly. > > After converting all drivers and the DRM core, the pdev fields becomes > only relevant for legacy drivers. In a later patchset, we may want to > convert these as well and remove pdev entirely. Pushed patches 1-3 to topic branch topic/drm-device-pdev, and merged it to drm-intel-next [1]. Joonas will merge it to drm-intel-gt-next. Let's sort out patches 4-5 after the merge window. Thanks for the patches. BR, Jani. [1] http://lore.kernel.org/r/87y2g6fxxv@intel.com > > v6: > * also remove assignment in i915/selftests in later patch (Chris) > v5: > * remove assignment in later patch (Chris) > v4: > * merged several patches > * moved core changes into separate patch > * vmwgfx build fix > v3: > * merged several patches > * fix one pdev reference in nouveau (Jeremy) > * rebases > v2: > * move whitespace fixes into separate patches (Alex, Sam) > * move i915 gt/ and gvt/ changes into separate patches (Joonas) > > Thomas Zimmermann (5): > drm/i915: Remove references to struct drm_device.pdev > drm/i915/gt: Remove references to struct drm_device.pdev > drm/i915/gvt: Remove references to struct drm_device.pdev > drm/i915: Don't assign to struct drm_device.pdev > drm: Move struct drm_device.pdev to legacy section > > drivers/gpu/drm/i915/display/intel_bios.c | 2 +- > drivers/gpu/drm/i915/display/intel_cdclk.c| 14 ++--- > drivers/gpu/drm/i915/display/intel_csr.c | 2 +- > drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 +- > drivers/gpu/drm/i915/display/intel_fbdev.c| 2 +- > drivers/gpu/drm/i915/display/intel_gmbus.c| 2 +- > .../gpu/drm/i915/display/intel_lpe_audio.c| 5 +++-- > drivers/gpu/drm/i915/display/intel_opregion.c | 6 +++--- > drivers/gpu/drm/i915/display/intel_overlay.c | 2 +- > drivers/gpu/drm/i915/display/intel_panel.c| 4 ++-- > drivers/gpu/drm/i915/display/intel_quirks.c | 2 +- > drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +- > drivers/gpu/drm/i915/display/intel_vga.c | 8 > drivers/gpu/drm/i915/gem/i915_gem_phys.c | 6 +++--- > drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 2 +- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- > drivers/gpu/drm/i915/gt/intel_ggtt.c | 10 +- > drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +- > drivers/gpu/drm/i915/gt/intel_rc6.c | 4 ++-- > drivers/gpu/drm/i915/gt/intel_region_lmem.c | 8 > drivers/gpu/drm/i915/gt/intel_reset.c | 6 +++--- > drivers/gpu/drm/i915/gvt/cfg_space.c | 5 +++-- > drivers/gpu/drm/i915/gvt/firmware.c | 10 +- > drivers/gpu/drm/i915/gvt/gtt.c| 12 +-- > drivers/gpu/drm/i915/gvt/gvt.c| 6 +++--- > drivers/gpu/drm/i915/gvt/kvmgt.c | 4 ++-- > drivers/gpu/drm/i915/i915_debugfs.c | 2 +- > drivers/gpu/drm/i915/i915_drv.c | 20 +-- > drivers/gpu/drm/i915/i915_drv.h | 2 +- > drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++--- > drivers/gpu/drm/i915/i915_getparam.c | 5 +++-- > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > drivers/gpu/drm/i915/i915_irq.c | 6 +++--- > drivers/gpu/drm/i915/i915_pmu.c | 2 +- > drivers/gpu/drm/i915/i915_suspend.c | 4 ++-- > drivers/gpu/drm/i915/i915_switcheroo.c| 4 ++-- > drivers/gpu/drm/i915/i915_vgpu.c | 2 +- > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- > drivers/gpu/drm/i915/intel_uncore.c | 4 ++-- > .../gpu/drm/i915/selftests/mock_gem_device.c | 1 - > drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 +- > include/drm/drm_device.h | 6 +++--- > 43 files changed, 100 insertions(+), 101 deletions(-) > > > base-commit: 3836b7fdfad40e2bac5dc882332f42bed6942cf4 > prerequisite-patch-id: c2b2f08f0eccc9f5df0c0da49fa1d36267deb11d > -- > 2.30.0 > -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx ma
[Intel-gfx] [PULL] topic/drm-device-pdev
Hi Joonas - This is Thomas's drm_device.pdev removal for i915, the first three patches from [1]. Let's merge to both drm-intel-next and drm-intel-gt-next. Zhenyu & Zhi, FYI, this touches gvt too, and it was getting a bit too complicated to handle all the components separately. Hopefully you won't have too many conflicts when backmerging. topic/drm-device-pdev-2021-02-02: Driver Changes: - drm/i915: Remove references to struct drm_device.pdev BR, Jani. [1] http://lore.kernel.org/r/20210128133127.2311-1-tzimmerm...@suse.de The following changes since commit 4043277ad18fc7cb9a79d0d043063fb5f42a6f06: drm/i915/adl_s: Add GT and CTX WAs for ADL-S (2021-02-01 07:59:11 -0800) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/topic/drm-device-pdev-2021-02-02 for you to fetch changes up to 9ff06c38530099b197b6389193e8cc34ab60288f: drm/i915/gvt: Remove references to struct drm_device.pdev (2021-02-02 13:58:45 +0200) Driver Changes: - drm/i915: Remove references to struct drm_device.pdev Thomas Zimmermann (3): drm/i915: Remove references to struct drm_device.pdev drm/i915/gt: Remove references to struct drm_device.pdev drm/i915/gvt: Remove references to struct drm_device.pdev drivers/gpu/drm/i915/display/intel_bios.c | 2 +- drivers/gpu/drm/i915/display/intel_cdclk.c | 14 +++--- drivers/gpu/drm/i915/display/intel_csr.c | 2 +- drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 +- drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +- drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +- drivers/gpu/drm/i915/display/intel_lpe_audio.c | 5 +++-- drivers/gpu/drm/i915/display/intel_opregion.c | 6 +++--- drivers/gpu/drm/i915/display/intel_overlay.c | 2 +- drivers/gpu/drm/i915/display/intel_panel.c | 4 ++-- drivers/gpu/drm/i915/display/intel_quirks.c| 2 +- drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +- drivers/gpu/drm/i915/display/intel_vga.c | 8 drivers/gpu/drm/i915/gem/i915_gem_phys.c | 6 +++--- drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 10 +- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c| 4 ++-- drivers/gpu/drm/i915/gt/intel_region_lmem.c| 8 drivers/gpu/drm/i915/gt/intel_reset.c | 6 +++--- drivers/gpu/drm/i915/gvt/cfg_space.c | 5 +++-- drivers/gpu/drm/i915/gvt/firmware.c| 10 +- drivers/gpu/drm/i915/gvt/gtt.c | 12 ++-- drivers/gpu/drm/i915/gvt/gvt.c | 6 +++--- drivers/gpu/drm/i915/gvt/kvmgt.c | 4 ++-- drivers/gpu/drm/i915/i915_debugfs.c| 2 +- drivers/gpu/drm/i915/i915_drv.c| 19 +-- drivers/gpu/drm/i915/i915_drv.h| 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c| 5 ++--- drivers/gpu/drm/i915/i915_getparam.c | 5 +++-- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/i915_irq.c| 6 +++--- drivers/gpu/drm/i915/i915_pmu.c| 2 +- drivers/gpu/drm/i915/i915_suspend.c| 4 ++-- drivers/gpu/drm/i915/i915_switcheroo.c | 4 ++-- drivers/gpu/drm/i915/i915_vgpu.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 2 +- drivers/gpu/drm/i915/intel_runtime_pm.c| 2 +- drivers/gpu/drm/i915/intel_uncore.c| 4 ++-- drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 +- 41 files changed, 97 insertions(+), 96 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-misc-fixes
Hi Dave and Daniel, here's this week's PR for drm-misc-fixes. There are 3 patches for the bridge code and one for TTM. Best regards Thomas drm-misc-fixes-2021-02-02: * drm/bridge/lontium-lt9611uxc: EDID fixes; Don't handle hotplug events in IRQ handler * drm/ttm: Use _GFP_NOWARN for huge pages The following changes since commit f6b57101a6b31277a4bde1d8028c46e898bd2ff2: drm/vc4: Correct POS1_SCL for hvs5 (2021-01-25 11:53:44 +0100) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2021-02-02 for you to fetch changes up to 2b1b3e544f65f40df5eef99753e460a127910479: drm/ttm: Use __GFP_NOWARN for huge pages in ttm_pool_alloc_page (2021-01-28 13:01:52 +0100) * drm/bridge/lontium-lt9611uxc: EDID fixes; Don't handle hotplug events in IRQ handler * drm/ttm: Use _GFP_NOWARN for huge pages Dmitry Baryshkov (3): drm/bridge/lontium-lt9611uxc: fix waiting for EDID to become available drm/bridge/lontium-lt9611uxc: fix get_edid return code drm/bridge/lontium-lt9611uxc: move HPD notification out of IRQ handler Michel Dänzer (1): drm/ttm: Use __GFP_NOWARN for huge pages in ttm_pool_alloc_page drivers/gpu/drm/bridge/lontium-lt9611uxc.c | 57 +++--- drivers/gpu/drm/ttm/ttm_pool.c | 2 +- 2 files changed, 46 insertions(+), 13 deletions(-) -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/57] drm/i915/gt: Move submission_method into intel_gt
Quoting Tvrtko Ursulin (2021-02-02 12:03:02) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c > > b/drivers/gpu/drm/i915/gt/selftest_execlists.c > > index 5d7fac383add..9304a35384aa 100644 > > --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c > > +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c > > @@ -4715,7 +4715,7 @@ int intel_execlists_live_selftests(struct > > drm_i915_private *i915) > > SUBTEST(live_virtual_reset), > > }; > > > > - if (!HAS_EXECLISTS(i915)) > > + if (i915->gt.submission_method != INTEL_SUBMISSION_ELSP) > > return 0; > > > > if (intel_gt_is_wedged(&i915->gt)) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c > > b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c > > index 3350e7c995bc..6cd9f6bc240c 100644 > > --- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c > > +++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c > > @@ -291,7 +291,7 @@ int intel_ring_submission_live_selftests(struct > > drm_i915_private *i915) > > SUBTEST(live_ctx_switch_wa), > > }; > > > > - if (HAS_EXECLISTS(i915)) > > + if (i915->gt.submission_method > INTEL_SUBMISSION_RING) > > Not sure the above two hunks in selftests are an improvement, not seeing > how using enum ordering is better than a feature check. Wait 40 patches. > Mechanics looks fine. I'd prefer the selftests to remain as is but not > mandatory. The execlists tests are not suitable as-is for the guc. And they are in the habit of breaking the test to hide impedance mismatches with the guc. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/57] drm/i915/gt: Move submission_method into intel_gt
On 01/02/2021 08:56, Chris Wilson wrote:
Since we setup the submission method for the engines once, it is easy to
assign an enum and use that instead of probing into the backends.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h | 8 +++-
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 12
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 8
drivers/gpu/drm/i915/gt/intel_execlists_submission.h | 3 ---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +++
drivers/gpu/drm/i915/gt/intel_reset.c| 7 +++
drivers/gpu/drm/i915/gt/selftest_execlists.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c| 5 -
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h| 1 -
drivers/gpu/drm/i915/i915_perf.c | 10 +-
11 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 47ee8578e511..8d9184920c51 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -13,8 +13,9 @@
#include "i915_reg.h"
#include "i915_request.h"
#include "i915_selftest.h"
-#include "gt/intel_timeline.h"
#include "intel_engine_types.h"
+#include "intel_gt_types.h"
+#include "intel_timeline.h"
#include "intel_workarounds.h"
struct drm_printer;
@@ -262,6 +263,11 @@ void intel_engine_init_active(struct intel_engine_cs
*engine,
#define ENGINE_MOCK 1
#define ENGINE_VIRTUAL2
+static inline bool intel_engine_uses_guc(const struct intel_engine_cs *engine)
+{
+ return engine->gt->submission_method >= INTEL_SUBMISSION_GUC;
+}
+
static inline bool
intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 727128c0166a..3d1bf6b3c3bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -891,12 +891,16 @@ int intel_engines_init(struct intel_gt *gt)
enum intel_engine_id id;
int err;
- if (intel_uc_uses_guc_submission(>->uc))
+ if (intel_uc_uses_guc_submission(>->uc)) {
+ gt->submission_method = INTEL_SUBMISSION_GUC;
setup = intel_guc_submission_setup;
- else if (HAS_EXECLISTS(gt->i915))
+ } else if (HAS_EXECLISTS(gt->i915)) {
+ gt->submission_method = INTEL_SUBMISSION_ELSP;
setup = intel_execlists_submission_setup;
- else
+ } else {
+ gt->submission_method = INTEL_SUBMISSION_RING;
setup = intel_ring_submission_setup;
+ }
for_each_engine(engine, gt, id) {
err = engine_setup_common(engine);
@@ -1461,7 +1465,7 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
}
- if (intel_engine_in_guc_submission_mode(engine)) {
+ if (intel_engine_uses_guc(engine)) {
/* nothing to print yet */
} else if (HAS_EXECLISTS(dev_priv)) {
struct i915_request * const *port, *rq;
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 5d824e1cfcba..4ddd2099a931 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1757,7 +1757,6 @@ process_csb(struct intel_engine_cs *engine, struct
i915_request **inactive)
*/
GEM_BUG_ON(!tasklet_is_locked(&execlists->tasklet) &&
!reset_in_progress(execlists));
- GEM_BUG_ON(!intel_engine_in_execlists_submission_mode(engine));
/*
* Note that csb_write, csb_status may be either in HWSP or mmio.
@@ -3897,13 +3896,6 @@ void intel_execlists_show_requests(struct
intel_engine_cs *engine,
spin_unlock_irqrestore(&engine->active.lock, flags);
}
-bool
-intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine)
-{
- return engine->set_default_submission ==
- execlists_set_default_submission;
-}
-
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_execlists.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
index a8fd7adefd82..f7bd3fccfee8 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.h
@@ -41,7 +41,4 @@ int intel_virtual_engine_attach_bond(struct intel_engine_cs
*engine,
const struct intel_engine_cs *master,
const struct intel_engine_cs *sibling);
-bool
Re: [Intel-gfx] [PATCH 07/57] drm/i915/gt: Move engine setup out of set_default_submission
On 01/02/2021 08:56, Chris Wilson wrote:
Now that we no longer switch back and forth between guc and execlists,
we no longer need to restore the backend's vfunc and can leave them set
after initialisation. The only catch is that we lose the submission on
wedging and still need to reset the submit_request vfunc on unwedging.
Signed-off-by: Chris Wilson
---
.../drm/i915/gt/intel_execlists_submission.c | 46 -
.../gpu/drm/i915/gt/intel_ring_submission.c | 4 --
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 50 ---
3 files changed, 44 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 45a8ac152b88..5d824e1cfcba 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3089,29 +3089,6 @@ static void execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->submit_request = execlists_submit_request;
engine->schedule = i915_schedule;
engine->execlists.tasklet.callback = execlists_submission_tasklet;
-
- engine->reset.prepare = execlists_reset_prepare;
- engine->reset.rewind = execlists_reset_rewind;
- engine->reset.cancel = execlists_reset_cancel;
- engine->reset.finish = execlists_reset_finish;
-
- engine->park = execlists_park;
- engine->unpark = NULL;
-
- engine->flags |= I915_ENGINE_SUPPORTS_STATS;
- if (!intel_vgpu_active(engine->i915)) {
- engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
- if (can_preempt(engine)) {
- engine->flags |= I915_ENGINE_HAS_PREEMPTION;
- if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
- engine->flags |= I915_ENGINE_HAS_TIMESLICES;
- }
- }
-
- if (intel_engine_has_preemption(engine))
- engine->emit_bb_start = gen8_emit_bb_start;
- else
- engine->emit_bb_start = gen8_emit_bb_start_noarb;
}
static void execlists_shutdown(struct intel_engine_cs *engine)
@@ -3142,6 +3119,14 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
engine->cops = &execlists_context_ops;
engine->request_alloc = execlists_request_alloc;
+ engine->reset.prepare = execlists_reset_prepare;
+ engine->reset.rewind = execlists_reset_rewind;
+ engine->reset.cancel = execlists_reset_cancel;
+ engine->reset.finish = execlists_reset_finish;
+
+ engine->park = execlists_park;
+ engine->unpark = NULL;
+
engine->emit_flush = gen8_emit_flush_xcs;
engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
@@ -3162,6 +3147,21 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
* until a more refined solution exists.
*/
}
+
+ engine->flags |= I915_ENGINE_SUPPORTS_STATS;
+ if (!intel_vgpu_active(engine->i915)) {
+ engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
+ if (can_preempt(engine)) {
+ engine->flags |= I915_ENGINE_HAS_PREEMPTION;
+ if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
+ engine->flags |= I915_ENGINE_HAS_TIMESLICES;
+ }
+ }
+
+ if (intel_engine_has_preemption(engine))
+ engine->emit_bb_start = gen8_emit_bb_start;
+ else
+ engine->emit_bb_start = gen8_emit_bb_start_noarb;
}
static void logical_ring_default_irqs(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 9c2c605d7a92..3cb2ce503544 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -969,14 +969,10 @@ static void gen6_bsd_submit_request(struct i915_request
*request)
static void i9xx_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = i9xx_submit_request;
-
- engine->park = NULL;
- engine->unpark = NULL;
}
static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
{
- i9xx_set_default_submission(engine);
engine->submit_request = gen6_bsd_submit_request;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 92688a9b6717..f72faa0b8339 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -608,35 +608,6 @@ static int guc_resume(struct intel_engine_cs *engine)
static void guc_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = guc_submit_request;
- engine->schedule = i
Re: [Intel-gfx] Fixes that failed to apply to v5.11-rc4
On Tue, 02 Feb 2021, Chris Wilson wrote:
> Quoting Jani Nikula (2021-02-02 07:15:18)
>> On Mon, 18 Jan 2021, Jani Nikula wrote:
>> > The following commits have been marked as Cc: stable or fixing something
>> > in v5.11-rc4 or earlier, but failed to cherry-pick to
>> > drm-intel-fixes. Please see if they are worth backporting, and please do
>> > so if they are.
>> >
>> > Conflicts:
>> > dbe13ae1d6ab ("drm/i915/pmu: Don't grab wakeref when enabling events")
>> > 9bb36cf66091 ("drm/i915: Check for rq->hwsp validity after acquiring RCU
>> > lock")
>> > 5b4dc95cf7f5 ("drm/i915/gt: Prevent use of engine->wa_ctx after error")
>> > 6a3daee1b38e ("drm/i915/selftests: Fix some error codes")
>> > 67fba3f1c73b ("drm/i915/dp: Fix LTTPR vswing/pre-emp setting in
>> > non-transparent mode")
>> >
>> > Fails to build:
>> > 3170a21f7059 ("drm/i915: Only enable DFP 4:4:4->4:2:0 conversion when
>> > outputting YCbCr 4:4:4")
>> >
>> > BR,
>> > Jani.
>>
>> Update.
>>
>> Conflicts:
>> 5b4dc95cf7f5 ("drm/i915/gt: Prevent use of engine->wa_ctx after error")
>
> Already in 488751a0ef9b ("drm/i915/gt: Prevent use of engine->wa_ctx after
> error")
>
>> 6a3daee1b38e ("drm/i915/selftests: Fix some error codes")
>
> No user or even likely CI impact, not worth backporting [unless it turns
> up later as a prerequisite].
>
>> 67fba3f1c73b ("drm/i915/dp: Fix LTTPR vswing/pre-emp setting in
>> non-transparent mode")
>> 699390f7f026 ("drm/i915: Fix the PHY compliance test vs. hotplug mishap")
>> e7004ea4f5f5 ("drm/i915/gt: Close race between enable_breadcrumbs and
>> cancel_breadcrumbs")
>
> Required at least one other friend.
>
> There's another patch that we need in fixes for v5.10, so I'll include
> that: drm/i915/gem: Drop lru bumping on display unpinning
>
> I've put the 3 patches on fdo,
> https://cgit.freedesktop.org/~ickle/linux-2.6/log/?h=dif
>
> Hopefully they are a happy bunch.
Thanks, picked the 3 up.
> p.s. 5.11-rc6 kills CI.
Yeah, looks like a fix is in the works.
BR,
Jani.
[1] http://lore.kernel.org/r/8735yfd2q4@nanos.tec.linutronix.de
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] i915/perf: Store a mask of valid OA formats for a platform
== Series Details ==
Series: series starting with [1/3] i915/perf: Store a mask of valid OA formats
for a platform
URL : https://patchwork.freedesktop.org/series/86558/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9714_full -> Patchwork_19558_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19558_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@sysfs_clients@recycle-many}:
- shard-kbl: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/shard-kbl2/igt@sysfs_clie...@recycle-many.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/shard-kbl7/igt@sysfs_clie...@recycle-many.html
- shard-tglb: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/shard-tglb2/igt@sysfs_clie...@recycle-many.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/shard-tglb8/igt@sysfs_clie...@recycle-many.html
Known issues
Here are the changes found in Patchwork_19558_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@in-flight-suspend:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#1037] /
[i915#180])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/shard-kbl7/igt@gem_...@in-flight-suspend.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/shard-kbl6/igt@gem_...@in-flight-suspend.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/shard-iclb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-glk: NOTRUN -> [FAIL][9] ([i915#2842])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/shard-glk7/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842]) +3 similar
issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/shard-kbl2/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/shard-tglb6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/shard-glk1/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/shard-glk6/igt@gem_exec_fair@basic-pace-s...@rcs0.html
- shard-tglb: NOTRUN -> [FAIL][16] ([i915#2842])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/shard-tglb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2849])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html
* igt@gem_exec_reloc@basic-wide-active@rcs0:
- shard-kbl: NOTRUN -> [FAIL][19] ([i915#2389]) +4 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/shard-kbl1/igt@gem_exec_reloc@basic-wide-act...@rcs0.html
* igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][20] ([i915#2389])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/shard-iclb4/igt@gem_exec_reloc@basic-wide-act...@vcs1.html
* igt@gem_exec_schedule@u-fairslice@vcs0:
- shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#2803])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/shard-tglb7/igt@gem_exec_schedule@u-fairsl...@vcs0.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/shard-tglb7/igt@gem_exec_schedule@u-fairsl...@vcs0.html
* igt@gem_exec_whisper@basic-contexts-priority-all:
- shard-glk: [PASS][23] -> [DMESG-WARN][24] ([i915#118] /
[i915#95])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/shard-glk6/igt@gem_exec_whis...
Re: [Intel-gfx] [PULL] topic/adl-s-enabling into drm-intel-next
On Mon, 01 Feb 2021, Lucas De Marchi wrote: > Hi Rodrigo/Jani, > > Here are the changes to add basic Alder Lake S support in the driver, with > patches touching both generic parts, gt and display. Remaining changes don't > need a topic branch anymore and can be applied individually to each branch. Thanks, pulled to drm-intel-next, and Joonas pulled to drm-intel-gt-next too. BR, Jani. > > thanks > Lucas De Marchi > > *** > > topic/adl-s-enabling-2021-02-01-1: > > Driver Changes: > - Add basic support for Alder Lake S, to be shared between > drm-intel-next and drm-intel-gt-next > > The following changes since commit fb5cfcaa2efbb4c71abb1dfbc8f4da727e0bfd89: > > Merge tag 'drm-intel-gt-next-2021-01-14' of > git://anongit.freedesktop.org/drm/drm-intel into drm-next (2021-01-15 > 15:03:36 +1000) > > are available in the Git repository at: > > git://anongit.freedesktop.org/drm/drm-intel > tags/topic/adl-s-enabling-2021-02-01-1 > > for you to fetch changes up to 4043277ad18fc7cb9a79d0d043063fb5f42a6f06: > > drm/i915/adl_s: Add GT and CTX WAs for ADL-S (2021-02-01 07:59:11 -0800) > > > Driver Changes: > - Add basic support for Alder Lake S, to be shared between > drm-intel-next and drm-intel-gt-next > > > Aditya Swarup (8): > drm/i915/tgl: Use TGL stepping info for applying WAs > drm/i915/adl_s: Configure DPLL for ADL-S > drm/i915/adl_s: Configure Port clock registers for ADL-S > drm/i915/adl_s: Initialize display for ADL-S > drm/i915/adl_s: Add adl-s ddc pin mapping > drm/i915/adl_s: Add vbt port and aux channel settings for adls > drm/i915/adl_s: Add display WAs for ADL-S > drm/i915/adl_s: Add GT and CTX WAs for ADL-S > > Anusha Srivatsa (4): > drm/i915/adl_s: Add PCH support > drm/i915/adl_s: Add Interrupt Support > drm/i915/adl_s: Add PHYs for Alderlake S > drm/i915/adl_s: Load DMC > > Caz Yokoyama (2): > drm/i915/adl_s: Add ADL-S platform info and PCI ids > x86/gpu: Add Alderlake-S stolen memory support > > José Roberto de Souza (1): > drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION > > Lucas De Marchi (1): > drm/i915/adl_s: Add power wells > > Matt Roper (3): > drm/i915/adl_s: Update combo PHY master/slave relationships > drm/i915/adl_s: Update PHY_MISC programming > drm/i915/adl_s: Re-use TGL GuC/HuC firmware > > Tejas Upadhyay (1): > drm/i915/adl_s: Update memory bandwidth parameters > > arch/x86/kernel/early-quirks.c | 1 + > drivers/gpu/drm/i915/display/intel_bios.c | 70 +++ > drivers/gpu/drm/i915/display/intel_bw.c| 10 ++- > drivers/gpu/drm/i915/display/intel_combo_phy.c | 23 +-- > drivers/gpu/drm/i915/display/intel_csr.c | 10 ++- > drivers/gpu/drm/i915/display/intel_ddi.c | 62 +++-- > drivers/gpu/drm/i915/display/intel_display.c | 31 ++--- > drivers/gpu/drm/i915/display/intel_display_power.c | 11 +-- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 -- > drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +- > drivers/gpu/drm/i915/display/intel_psr.c | 4 +- > drivers/gpu/drm/i915/display/intel_sprite.c| 8 +-- > drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++ > drivers/gpu/drm/i915/gt/intel_workarounds.c| 68 +++--- > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +- > drivers/gpu/drm/i915/i915_drv.h| 80 > ++ > drivers/gpu/drm/i915/i915_irq.c| 5 +- > drivers/gpu/drm/i915/i915_pci.c| 13 > drivers/gpu/drm/i915/i915_reg.h| 50 -- > drivers/gpu/drm/i915/intel_device_info.c | 9 ++- > drivers/gpu/drm/i915/intel_device_info.h | 1 + > drivers/gpu/drm/i915/intel_pch.c | 8 ++- > drivers/gpu/drm/i915/intel_pch.h | 3 + > drivers/gpu/drm/i915/intel_pm.c| 2 +- > include/drm/i915_pciids.h | 11 +++ > 25 files changed, 417 insertions(+), 129 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH -fixes] drm/i915/display: Prevent double YUV range correction on HDR planes
On Tue, 02 Feb 2021, Ville Syrjala wrote:
> From: Andres Calderon Jaramillo
>
> Prevent the ICL HDR plane pipeline from performing YUV color range
> correction twice when the input is in limited range. This is done by
> removing the limited-range code from icl_program_input_csc().
>
> Before this patch the following could happen: user space gives us a YUV
> buffer in limited range; per the pipeline in [1], the plane would first
> go through a "YUV Range correct" stage that expands the range; the plane
> would then go through the "Input CSC" stage which would also expand the
> range because icl_program_input_csc() would use a matrix and an offset
> that assume limited-range input; this would ultimately cause dark and
> light colors to appear darker and lighter than they should respectively.
>
> This is an issue because if a buffer switches between being scanned out
> and being composited with the GPU, the user will see a color difference.
> If this switching happens quickly and frequently, the user will perceive
> this as a flickering.
>
> [1]
> https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-icllp-vol12-displayengine_0.pdf#page=281
>
> Cc: sta...@vger.kernel.org
> Signed-off-by: Andres Calderon Jaramillo
> Signed-off-by: Ville Syrjälä
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20201215224219.3896256-1-andre...@google.com
> (cherry picked from commit fed387572040e84ead53852a7820e30a30e515d0)
Thanks, pushed to drm-intel-fixes.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 65 +++-
> 2 files changed, 12 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 53a00cf3fa32..39396248f388 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4807,6 +4807,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state
> *crtc_state,
> plane_color_ctl |=
> PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> } else if (fb->format->is_yuv) {
> plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
> + if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> + plane_color_ctl |=
> PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> }
>
> return plane_color_ctl;
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 019a2d6d807a..3da2544fa1c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -618,13 +618,19 @@ skl_program_scaler(struct intel_plane *plane,
>
> /* Preoffset values for YUV to RGB Conversion */
> #define PREOFF_YUV_TO_RGB_HI 0x1800
> -#define PREOFF_YUV_TO_RGB_ME 0x1F00
> +#define PREOFF_YUV_TO_RGB_ME 0x
> #define PREOFF_YUV_TO_RGB_LO 0x1800
>
> #define ROFF(x) (((x) & 0x) << 16)
> #define GOFF(x) (((x) & 0x) << 0)
> #define BOFF(x) (((x) & 0x) << 16)
>
> +/*
> + * Programs the input color space conversion stage for ICL HDR planes.
> + * Note that it is assumed that this stage always happens after YUV
> + * range correction. Thus, the input to this stage is assumed to be
> + * in full-range YCbCr.
> + */
> static void
> icl_program_input_csc(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> @@ -672,52 +678,7 @@ icl_program_input_csc(struct intel_plane *plane,
> 0x0, 0x7800, 0x7F10,
> },
> };
> -
> - /* Matrix for Limited Range to Full Range Conversion */
> - static const u16 input_csc_matrix_lr[][9] = {
> - /*
> - * BT.601 Limted range YCbCr -> full range RGB
> - * The matrix required is :
> - * [1.164384, 0.000, 1.596027,
> - * 1.164384, -0.39175, -0.812813,
> - * 1.164384, 2.017232, 0.]
> - */
> - [DRM_COLOR_YCBCR_BT601] = {
> - 0x7CC8, 0x7950, 0x0,
> - 0x8D00, 0x7950, 0x9C88,
> - 0x0, 0x7950, 0x6810,
> - },
> - /*
> - * BT.709 Limited range YCbCr -> full range RGB
> - * The matrix required is :
> - * [1.164384, 0.000, 1.792741,
> - * 1.164384, -0.213249, -0.532909,
> - * 1.164384, 2.112402, 0.]
> - */
> - [DRM_COLOR_YCBCR_BT709] = {
> - 0x7E58, 0x7950, 0x0,
> - 0x, 0x7950, 0xADA8,
> - 0x0, 0x7950, 0x6870,
> - },
> - /*
> - * BT.2020 Limited range YCbCr -> full range RGB
> - * The matrix required is :
> - * [1.164, 0.000, 1.678,
>
Re: [Intel-gfx] [PATCH 04/57] drm/i915: Protect against request freeing during cancellation on wedging
Chris Wilson writes:
> As soon as we mark a request as completed, it may be retired. So when
> cancelling a request and marking it complete, make sure we first keep a
> reference to the request.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> .../drm/i915/gt/intel_execlists_submission.c | 19 +++
> drivers/gpu/drm/i915/gt/intel_reset.c | 15 ++-
> .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/mock_engine.c | 8 +---
> drivers/gpu/drm/i915/i915_request.c | 9 +++--
> drivers/gpu/drm/i915/i915_request.h | 2 +-
> 6 files changed, 31 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index e7593df6777d..45a8ac152b88 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2976,7 +2976,7 @@ static void execlists_reset_cancel(struct
> intel_engine_cs *engine)
>
> /* Mark all executing requests as skipped. */
> list_for_each_entry(rq, &engine->active.requests, sched.link)
> - i915_request_mark_eio(rq);
> + i915_request_put(i915_request_mark_eio(rq));
> intel_engine_signal_breadcrumbs(engine);
>
> /* Flush the queued requests to the timeline list (for retiring). */
> @@ -2984,8 +2984,10 @@ static void execlists_reset_cancel(struct
> intel_engine_cs *engine)
> struct i915_priolist *p = to_priolist(rb);
>
> priolist_for_each_request_consume(rq, rn, p) {
> - i915_request_mark_eio(rq);
> - __i915_request_submit(rq);
> + if (i915_request_mark_eio(rq)) {
> + __i915_request_submit(rq);
> + i915_request_put(rq);
> + }
> }
>
> rb_erase_cached(&p->node, &execlists->queue);
> @@ -2994,7 +2996,7 @@ static void execlists_reset_cancel(struct
> intel_engine_cs *engine)
>
> /* On-hold requests will be flushed to timeline upon their release */
> list_for_each_entry(rq, &engine->active.hold, sched.link)
> - i915_request_mark_eio(rq);
> + i915_request_put(i915_request_mark_eio(rq));
>
> /* Cancel all attached virtual engines */
> while ((rb = rb_first_cached(&execlists->virtual))) {
> @@ -3007,10 +3009,11 @@ static void execlists_reset_cancel(struct
> intel_engine_cs *engine)
> spin_lock(&ve->base.active.lock);
> rq = fetch_and_zero(&ve->request);
> if (rq) {
> - i915_request_mark_eio(rq);
> -
> - rq->engine = engine;
> - __i915_request_submit(rq);
> + if (i915_request_mark_eio(rq)) {
> + rq->engine = engine;
> + __i915_request_submit(rq);
> + i915_request_put(rq);
> + }
> i915_request_put(rq);
>
> ve->base.execlists.queue_priority_hint = INT_MIN;
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 107430e1e864..a82c4d7b23bc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -786,18 +786,15 @@ static void reset_finish(struct intel_gt *gt,
> intel_engine_mask_t awake)
>
> static void nop_submit_request(struct i915_request *request)
> {
> - struct intel_engine_cs *engine = request->engine;
> - unsigned long flags;
> -
> RQ_TRACE(request, "-EIO\n");
> - i915_request_set_error_once(request, -EIO);
>
> - spin_lock_irqsave(&engine->active.lock, flags);
> - __i915_request_submit(request);
> - i915_request_mark_complete(request);
> - spin_unlock_irqrestore(&engine->active.lock, flags);
> + request = i915_request_mark_eio(request);
> + if (request) {
> + i915_request_submit(request);
> + intel_engine_signal_breadcrumbs(request->engine);
>
> - intel_engine_signal_breadcrumbs(engine);
> + i915_request_put(request);
> + }
> }
>
> static void __intel_gt_set_wedged(struct intel_gt *gt)
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 8b7cc637c432..9c2c605d7a92 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -400,7 +400,7 @@ static void reset_cancel(struct intel_engine_cs *engine)
>
> /* Mark all submitted requests as skipped. */
> list_for_each_entry(request, &engine->active.requests, sched.link)
> - i915_request_mark_eio(request);
> + i915_request_put(i915_request_mark_eio(re
Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
> -Original Message-
> From: Ville Syrjälä
> Sent: 02 February 2021 12:42
> To: Surendrakumar Upadhyay, TejaskumarX
>
> Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during
> suspend/resume
>
> On Tue, Feb 02, 2021 at 08:31:48AM +0200, Ville Syrjälä wrote:
> > On Tue, Feb 02, 2021 at 05:52:28AM +, Surendrakumar Upadhyay,
> TejaskumarX wrote:
> > >
> > >
> > > > -Original Message-
> > > > From: Ville Syrjälä
> > > > Sent: 28 January 2021 04:46
> > > > To: Surendrakumar Upadhyay, TejaskumarX
> > > >
> > > > Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> > > > ; Roper, Matthew D
> > > >
> > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH
> > > > during suspend/resume
> > > >
> > > > On Wed, Jan 27, 2021 at 03:38:30PM +0530, Tejas Upadhyay wrote:
> > > > > For Legacy S3 suspend/resume GEN9 BC needs to enable and setup
> > > > > TGP PCH.
> > > > >
> > > > > Cc: Matt Roper
> > > > > Signed-off-by: Tejas Upadhyay
> > > > >
> > > > > ---
> > > > > drivers/gpu/drm/i915/i915_irq.c | 36
> > > > > -
> > > > > 1 file changed, 27 insertions(+), 9 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > > b/drivers/gpu/drm/i915/i915_irq.c index
> > > > > a31980f69120..6dcefc3e24ac
> > > > > 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > > @@ -3026,8 +3026,20 @@ static void gen8_irq_reset(struct
> > > > drm_i915_private *dev_priv)
> > > > > GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > > > > GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> > > > >
> > > > > - if (HAS_PCH_SPLIT(dev_priv))
> > > > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > > > + GEN3_IRQ_RESET(uncore, SDE);
> > > > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > > > ibx_irq_reset(dev_priv);
> > > > > +
> > > > > + /* Wa_14010685332:cnp/cmp,tgp,adp */
> > > > > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > > > + INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > > > + SBCLK_RUN_REFCLK_DIS,
> > > > SBCLK_RUN_REFCLK_DIS);
> > > > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > > > + SBCLK_RUN_REFCLK_DIS, 0);
> > > > > + }
> > > >
> > > > Time to refactor instead of copypasta.
> > > Do you expect below? :
> > >
> > > If ((INTEL_PCH_TYPE(dev_priv) == PCH_TGP) {
> > > intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > >SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > >SBCLK_RUN_REFCLK_DIS, 0);
> > > }
> >
> > I expect a new function instead of copy pasting this whole thing into
> > multiple places.
> >
> > That said even the current code doesn't make any sense to me.
> > Take for instance this part:
> > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > GEN3_IRQ_RESET(uncore, SDE); What is that PCH type
> > check doing there? What weird PCH type are we supposed to have that
> > doesn't need this?
> >
> > Also the Wa_14010685332 part looks a bit odd. Is it correct that icp
> > doesn't need that, but cnp and tgp both do somehow? Can we even have
> > cnp on icl+?
>
> Hmm. Looking at it a bit more, that w/a seems to have something to do with
> suspend/resume, so seems rather misplaced in irq_reset(). Should probably
> just move the whole thing into a more appropriate place.
>
GEN11+ needs these checks in irq_reset(). Please check irq_reset for GEN11. Now
that customer like dell are expecting TGP PCH with gen9bc platforms, I have
done similar PCH checking in irq_reset() for gen9bc. You mean these checks are
at wrong place for GEN11 irq_reset() as well? Or you want one function doing
these checks and calling it everywhere!
> --
> Ville Syrjälä
> Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] i915/perf: Store a mask of valid OA formats for a platform
== Series Details == Series: series starting with [1/3] i915/perf: Store a mask of valid OA formats for a platform URL : https://patchwork.freedesktop.org/series/86558/ State : success == Summary == CI Bug Log - changes from CI_DRM_9714 -> Patchwork_19558 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/index.html Known issues Here are the changes found in Patchwork_19558 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@sync-fork-gfx0: - fi-cfl-8700k: NOTRUN -> [SKIP][1] ([fdo#109271]) +25 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/fi-cfl-8700k/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html * igt@gem_huc_copy@huc-copy: - fi-cfl-8700k: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/fi-cfl-8700k/igt@gem_huc_c...@huc-copy.html * igt@gem_tiled_blits@basic: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/fi-tgl-y/igt@gem_tiled_bl...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/fi-tgl-y/igt@gem_tiled_bl...@basic.html * igt@i915_selftest@live@requests: - fi-icl-u2: [PASS][5] -> [DMESG-FAIL][6] ([i915#2759]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/fi-icl-u2/igt@i915_selftest@l...@requests.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/fi-icl-u2/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@sanitycheck: - fi-kbl-7500u: [PASS][7] -> [DMESG-WARN][8] ([i915#2605]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html * igt@kms_chamelium@vga-edid-read: - fi-cfl-8700k: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/fi-cfl-8700k/igt@kms_chamel...@vga-edid-read.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [PASS][10] -> [DMESG-WARN][11] ([i915#165]) +15 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-cfl-8700k: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/fi-cfl-8700k/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][13] ([i915#1602] / [i915#2029] / [i915#2369]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/fi-bdw-5557u/igt@run...@aborted.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][14] ([i915#402]) -> [PASS][15] +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/fi-tgl-y/igt@debugfs_test@read_all_entries.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@i915_pm_rpm@module-reload: - fi-kbl-guc: [FAIL][16] ([i915#2203]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/fi-kbl-guc/igt@i915_pm_...@module-reload.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/fi-kbl-guc/igt@i915_pm_...@module-reload.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [FAIL][18] -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9714/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19558/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203 [i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369 [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605 [i915#2759]: https://gitlab.freedesktop.org/drm/intel/issues/2759 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/40
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/display: Prevent double YUV range correction on HDR planes (rev3)
== Series Details == Series: drm/i915/display: Prevent double YUV range correction on HDR planes (rev3) URL : https://patchwork.freedesktop.org/series/84966/ State : failure == Summary == Applying: drm/i915/display: Prevent double YUV range correction on HDR planes Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display.c M drivers/gpu/drm/i915/display/intel_sprite.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_sprite.c Auto-merging drivers/gpu/drm/i915/display/intel_display.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_display.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 drm/i915/display: Prevent double YUV range correction on HDR planes When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH -fixes] drm/i915/display: Prevent double YUV range correction on HDR planes
From: Andres Calderon Jaramillo
Prevent the ICL HDR plane pipeline from performing YUV color range
correction twice when the input is in limited range. This is done by
removing the limited-range code from icl_program_input_csc().
Before this patch the following could happen: user space gives us a YUV
buffer in limited range; per the pipeline in [1], the plane would first
go through a "YUV Range correct" stage that expands the range; the plane
would then go through the "Input CSC" stage which would also expand the
range because icl_program_input_csc() would use a matrix and an offset
that assume limited-range input; this would ultimately cause dark and
light colors to appear darker and lighter than they should respectively.
This is an issue because if a buffer switches between being scanned out
and being composited with the GPU, the user will see a color difference.
If this switching happens quickly and frequently, the user will perceive
this as a flickering.
[1]
https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-icllp-vol12-displayengine_0.pdf#page=281
Cc: sta...@vger.kernel.org
Signed-off-by: Andres Calderon Jaramillo
Signed-off-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20201215224219.3896256-1-andre...@google.com
(cherry picked from commit fed387572040e84ead53852a7820e30a30e515d0)
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +
drivers/gpu/drm/i915/display/intel_sprite.c | 65 +++-
2 files changed, 12 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 53a00cf3fa32..39396248f388 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4807,6 +4807,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state
*crtc_state,
plane_color_ctl |=
PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
} else if (fb->format->is_yuv) {
plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
+ if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+ plane_color_ctl |=
PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
}
return plane_color_ctl;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 019a2d6d807a..3da2544fa1c0 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -618,13 +618,19 @@ skl_program_scaler(struct intel_plane *plane,
/* Preoffset values for YUV to RGB Conversion */
#define PREOFF_YUV_TO_RGB_HI 0x1800
-#define PREOFF_YUV_TO_RGB_ME 0x1F00
+#define PREOFF_YUV_TO_RGB_ME 0x
#define PREOFF_YUV_TO_RGB_LO 0x1800
#define ROFF(x) (((x) & 0x) << 16)
#define GOFF(x) (((x) & 0x) << 0)
#define BOFF(x) (((x) & 0x) << 16)
+/*
+ * Programs the input color space conversion stage for ICL HDR planes.
+ * Note that it is assumed that this stage always happens after YUV
+ * range correction. Thus, the input to this stage is assumed to be
+ * in full-range YCbCr.
+ */
static void
icl_program_input_csc(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -672,52 +678,7 @@ icl_program_input_csc(struct intel_plane *plane,
0x0, 0x7800, 0x7F10,
},
};
-
- /* Matrix for Limited Range to Full Range Conversion */
- static const u16 input_csc_matrix_lr[][9] = {
- /*
-* BT.601 Limted range YCbCr -> full range RGB
-* The matrix required is :
-* [1.164384, 0.000, 1.596027,
-* 1.164384, -0.39175, -0.812813,
-* 1.164384, 2.017232, 0.]
-*/
- [DRM_COLOR_YCBCR_BT601] = {
- 0x7CC8, 0x7950, 0x0,
- 0x8D00, 0x7950, 0x9C88,
- 0x0, 0x7950, 0x6810,
- },
- /*
-* BT.709 Limited range YCbCr -> full range RGB
-* The matrix required is :
-* [1.164384, 0.000, 1.792741,
-* 1.164384, -0.213249, -0.532909,
-* 1.164384, 2.112402, 0.]
-*/
- [DRM_COLOR_YCBCR_BT709] = {
- 0x7E58, 0x7950, 0x0,
- 0x, 0x7950, 0xADA8,
- 0x0, 0x7950, 0x6870,
- },
- /*
-* BT.2020 Limited range YCbCr -> full range RGB
-* The matrix required is :
-* [1.164, 0.000, 1.678,
-* 1.164, -0.1873, -0.6504,
-* 1.164, 2.1417, 0.]
-*/
- [DRM_COLOR_YCBCR_BT2020] = {
- 0x7D70, 0x7950, 0x0,
-
Re: [Intel-gfx] Fixes that failed to apply to v5.11-rc4
Quoting Jani Nikula (2021-02-02 07:15:18)
> On Mon, 18 Jan 2021, Jani Nikula wrote:
> > The following commits have been marked as Cc: stable or fixing something
> > in v5.11-rc4 or earlier, but failed to cherry-pick to
> > drm-intel-fixes. Please see if they are worth backporting, and please do
> > so if they are.
> >
> > Conflicts:
> > dbe13ae1d6ab ("drm/i915/pmu: Don't grab wakeref when enabling events")
> > 9bb36cf66091 ("drm/i915: Check for rq->hwsp validity after acquiring RCU
> > lock")
> > 5b4dc95cf7f5 ("drm/i915/gt: Prevent use of engine->wa_ctx after error")
> > 6a3daee1b38e ("drm/i915/selftests: Fix some error codes")
> > 67fba3f1c73b ("drm/i915/dp: Fix LTTPR vswing/pre-emp setting in
> > non-transparent mode")
> >
> > Fails to build:
> > 3170a21f7059 ("drm/i915: Only enable DFP 4:4:4->4:2:0 conversion when
> > outputting YCbCr 4:4:4")
> >
> > BR,
> > Jani.
>
> Update.
>
> Conflicts:
> 5b4dc95cf7f5 ("drm/i915/gt: Prevent use of engine->wa_ctx after error")
Already in 488751a0ef9b ("drm/i915/gt: Prevent use of engine->wa_ctx after
error")
> 6a3daee1b38e ("drm/i915/selftests: Fix some error codes")
No user or even likely CI impact, not worth backporting [unless it turns
up later as a prerequisite].
> 67fba3f1c73b ("drm/i915/dp: Fix LTTPR vswing/pre-emp setting in
> non-transparent mode")
> 699390f7f026 ("drm/i915: Fix the PHY compliance test vs. hotplug mishap")
> e7004ea4f5f5 ("drm/i915/gt: Close race between enable_breadcrumbs and
> cancel_breadcrumbs")
Required at least one other friend.
There's another patch that we need in fixes for v5.10, so I'll include
that: drm/i915/gem: Drop lru bumping on display unpinning
I've put the 3 patches on fdo,
https://cgit.freedesktop.org/~ickle/linux-2.6/log/?h=dif
Hopefully they are a happy bunch.
p.s. 5.11-rc6 kills CI.
-Chris
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