Re: [Intel-gfx] linux-next: build warning after merge of the pm tree

[Stephen Rothwell]

Hi all,

On Mon, 15 Feb 2021 11:39:39 +1100 Stephen Rothwell  
wrote:
>
> Hi all,
> 
> After merging the pm tree, today's linux-next build (x86_64 allmodconfig)
> produced this warning:
> 
> In file included from drivers/gpu/drm/gma500/mdfld_output.c:28:
> arch/x86/include/asm/intel_scu_ipc.h:23:12: warning: 'struct module' declared 
> inside parameter list will not be visible outside of this definition or 
> declaration
>23 | struct module *owner);
>   |^~
> arch/x86/include/asm/intel_scu_ipc.h:33:17: warning: 'struct module' declared 
> inside parameter list will not be visible outside of this definition or 
> declaration
>33 |  struct module *owner);
>   | ^~
> 
> Introduced by commit
> 
>   bfc838f8598e ("drm/gma500: Convert to use new SCU IPC API")
> 
> OK, these will go away when the drm-misc tree removes this file in commit
> 
>   e1da811218d2 ("drm/gma500: Remove Medfield support")
> 
> So, if you don't want to see these warnings in Linus' build testing,
> you need to make sure that the drm-misc tree is merged before the pm
> tree (or the drivers-x86 tree).  Or you need to include module.h in
> mdfld_output.c before intel_scu_ipc.h (or in intel_scu_ipc.h itself).

The above drm-misc commit is now in Linus' tree.

-- 
Cheers,
Stephen Rothwell


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[Intel-gfx] [PULL] gvt-next-fixes

[Zhenyu Wang]

Hi,

Looks last gvt pull missed -gt-next window before CNY holiday.
So here're left three changes for fixing ww locking, cmd parser
fix for i915 state use and one left cleanup fix.

Thanks!
--
The following changes since commit 81ce8f04aa96f7f6cae05770f68b5d15be91f5a2:

  drm/i915/gt: Correct surface base address for renderclear (2021-02-17 
06:19:04 -0500)

are available in the Git repository at:

  https://github.com/intel/gvt-linux tags/gvt-next-fixes-2021-02-22

for you to fetch changes up to 67f1120381df022a7016f4acc8d4880da9a66c03:

  drm/i915/gvt: Introduce per object locking in GVT scheduler. (2021-02-22 
16:42:14 +0800)


gvt-next-fixes-2021-02-22

- Fix to use i915 default state for cmd parser on all engines (Chris)
- Purge dev_priv->gt (Chris)
- Fix gvt object ww locking (Zhi)


Chris Wilson (2):
  drm/i915/gvt: Parse default state to update reg whitelist
  drm/i915/gvt: Purge dev_priv->gt

Zhi Wang (1):
  drm/i915/gvt: Introduce per object locking in GVT scheduler.

 drivers/gpu/drm/i915/gvt/cmd_parser.c | 93 ---
 drivers/gpu/drm/i915/gvt/execlist.c   |  8 ++-
 drivers/gpu/drm/i915/gvt/scheduler.c  | 52 +++-
 3 files changed, 64 insertions(+), 89 deletions(-)


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Re: [Intel-gfx] [PATCH v3 6/9] drm/i915/mso: add splitter state readout for platforms that support it

[Shankar, Uma]

> -Original Message-
> From: Intel-gfx  On Behalf Of Jani 
> Nikula
> Sent: Thursday, February 11, 2021 8:22 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Varide, Nischal 
> 
> Subject: [Intel-gfx] [PATCH v3 6/9] drm/i915/mso: add splitter state readout 
> for
> platforms that support it
> 
> Add splitter configuration to crtc state, and read it where supported. Also 
> add
> splitter state dumping. The stream splitter will be required for eDP MSO.
> 
> v3:
> - Convert segment timings to full panel timings.
> - Refer to splitter instead of mso in crtc state.
> - Dump splitter state.
> 
> v2: Add warning for mso being enabled on pipes other than A.
> 
> Cc: Nischal Varide 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c  | 37 +++
>  drivers/gpu/drm/i915/display/intel_display.c  | 31 +++-
>  .../drm/i915/display/intel_display_types.h|  7 
>  drivers/gpu/drm/i915/i915_drv.h   |  2 +
>  4 files changed, 75 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3c4003605f93..c9098297b6ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2132,6 +2132,41 @@ static void intel_ddi_power_up_lanes(struct
> intel_encoder *encoder,
>   }
>  }
> 
> +static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
> +  struct intel_crtc_state *pipe_config) {
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + u32 dss1;
> +
> + if (!HAS_MSO(i915))
> + return;
> +
> + dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
> +
> + pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
> + if (!pipe_config->splitter.enable)
> + return;
> +
> + /* Splitter enable is supported for pipe A only. */
> + if (drm_WARN_ON(&i915->drm, pipe != PIPE_A)) {
> + pipe_config->splitter.enable = false;
> + return;
> + }
> +
> + switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
> + case SPLITTER_CONFIGURATION_2_SEGMENT:
> + pipe_config->splitter.link_count = 2;
> + break;
> + case SPLITTER_CONFIGURATION_4_SEGMENT:
> + pipe_config->splitter.link_count = 4;
> + break;

Should we have a default case as well just for sanity along with a WARN, since 
it's very
unlikely that it gets hit.

> + }
> +
> + pipe_config->splitter.pixel_overlap =
> +REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); }
> +
>  static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state, @@ 
> -
> 3322,6 +3357,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>   intel_ddi_read_func_ctl(encoder, pipe_config);
>   }
> 
> + intel_ddi_mso_get_config(encoder, pipe_config);
> +
>   pipe_config->has_audio =
>   intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index beed08c00b6c..fe9985bd5786 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4856,8 +4856,30 @@ static void intel_crtc_readout_derived_state(struct
> intel_crtc_state *crtc_state
>   pipe_mode->crtc_clock /= 2;
>   }
> 
> - intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
> - intel_mode_from_crtc_timings(adjusted_mode, adjusted_mode);
> + if (crtc_state->splitter.enable) {

We can just add an else if case to if (crtc_state->bigjoiner) {

if (crtc_state->bigjoiner) {
...
} else if (crtc_state->splitter.enable) {
...
}

> + int n = crtc_state->splitter.link_count;
> + int overlap = crtc_state->splitter.pixel_overlap;
> +
> + /*
> +  * eDP MSO uses segment timings from EDID for transcoder
> +  * timings, but full mode for everything else.
> +  *
> +  * h_full = (h_segment - pixel_overlap) * link_count
> +  */
> + pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) 
> *
> n;
> + pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start -
> overlap) * n;
> + pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end -
> overlap) * n;
> + pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start -
> overlap) * n;
> + pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end -
> overlap) * n;
> + pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;
> + pipe_mode->crtc_cloc

Re: [Intel-gfx] [PATCH v3 7/9] drm/i915/mso: add splitter state check

[Shankar, Uma]

> -Original Message-
> From: Intel-gfx  On Behalf Of Jani 
> Nikula
> Sent: Thursday, February 11, 2021 8:22 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Varide, Nischal 
> 
> Subject: [Intel-gfx] [PATCH v3 7/9] drm/i915/mso: add splitter state check
> 
> For starters, we expect the state to be zero, as we don't enable MSO anywhere.
> 
> v2: Refer to splitter.

Looks Good to me.
Reviewed-by: Uma Shankar 

> Cc: Nischal Varide 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index fe9985bd5786..3059a07b8c36 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9326,6 +9326,10 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
>   PIPE_CONF_CHECK_I(dsc.dsc_split);
>   PIPE_CONF_CHECK_I(dsc.compressed_bpp);
> 
> + PIPE_CONF_CHECK_BOOL(splitter.enable);
> + PIPE_CONF_CHECK_I(splitter.link_count);
> + PIPE_CONF_CHECK_I(splitter.pixel_overlap);
> +
>   PIPE_CONF_CHECK_I(mst_master_transcoder);
> 
>   PIPE_CONF_CHECK_BOOL(vrr.enable);
> --
> 2.20.1
> 
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Re: [Intel-gfx] [PATCH v3 8/9] drm/i915/edp: modify fixed and downclock modes for MSO

[Shankar, Uma]

> -Original Message-
> From: Intel-gfx  On Behalf Of Jani 
> Nikula
> Sent: Thursday, February 11, 2021 8:22 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Varide, Nischal 
> 
> Subject: [Intel-gfx] [PATCH v3 8/9] drm/i915/edp: modify fixed and downclock
> modes for MSO
> 
> In the case of MSO (Multi-SST Operation), the EDID contains the timings for a 
> single
> panel segment. We'll want to hide the fact from userspace, and expose modes 
> that
> span the entire display.
> 
> Don't modify the EDID, as the userspace should not use that for modesetting, 
> only
> modify the actual modes.
> 
> v3: Use pixel overlap if available.

Looks Good to me.
Reviewed-by: Uma Shankar 

> v2: Rename intel_dp_mso_mode_fixup -> intel_edp_mso_mode_fixup
> 
> Cc: Nischal Varide 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 29 +
>  1 file changed, 29 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 48e65b9a967a..5d5b16f70ed2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3516,6 +3516,31 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp
> *intel_dp)
>   }
>  }
> 
> +static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
> +  struct drm_display_mode *mode) {
> + struct intel_dp *intel_dp = intel_attached_dp(connector);
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + int n = intel_dp->mso_link_count;
> + int overlap = intel_dp->mso_pixel_overlap;
> +
> + if (!mode || !n)
> + return;
> +
> + mode->hdisplay = (mode->hdisplay - overlap) * n;
> + mode->hsync_start = (mode->hsync_start - overlap) * n;
> + mode->hsync_end = (mode->hsync_end - overlap) * n;
> + mode->htotal = (mode->htotal - overlap) * n;
> + mode->clock *= n;
> +
> + drm_mode_set_name(mode);
> +
> + drm_dbg_kms(&i915->drm,
> + "[CONNECTOR:%d:%s] using generated MSO mode: ",
> + connector->base.base.id, connector->base.name);
> + drm_mode_debug_printmodeline(mode);
> +}
> +
>  static void intel_edp_mso_init(struct intel_dp *intel_dp)  {
>   struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -6493,6
> +6518,10 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
>   if (fixed_mode)
>   downclock_mode = intel_dp_drrs_init(intel_connector,
> fixed_mode);
> 
> + /* multiply the mode clock and horizontal timings for MSO */
> + intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
> + intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
> +
>   /* fallback to VBT if available for eDP */
>   if (!fixed_mode)
>   fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
> --
> 2.20.1
> 
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Re: [Intel-gfx] [PATCH 3/4] drm/i915/display: Remove some redundancy around CAN_PSR()

[Mun, Gwan-gyeong]

On Tue, 2021-02-09 at 10:14 -0800, José Roberto de Souza wrote:
> If source_support is set the platform supports PSR so no need to
> check
> it again at every CAN_PSR().
> 
> Also removing the intel_dp_is_edp() calls, if sink_support is set
> the sink connected is for sure a eDP panel.
> 
> Cc: Gwan-gyeong Mun 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h | 5 ++---
>  drivers/gpu/drm/i915/display/intel_dp.c    | 2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c   | 4 ++--
>  3 files changed, 5 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ebaa9d0ed376..4a46c4e9b0ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1793,9 +1793,8 @@ dp_to_i915(struct intel_dp *intel_dp)
> return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
>  }
>  
> -#define CAN_PSR(intel_dp)  (HAS_PSR(dp_to_i915(intel_dp)) && \
> -    (intel_dp)->psr.sink_support && \
> -    (intel_dp)->psr.source_support)
> +#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
> +  (intel_dp)->psr.source_support)
>  
>  static inline bool intel_encoder_can_psr(struct intel_encoder
> *encoder)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4f89e0de5dde..0a0cc61344c4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2358,7 +2358,7 @@ bool intel_dp_initial_fastset_check(struct
> intel_encoder *encoder,
> return false;
> }
>  
> -   if (CAN_PSR(intel_dp) && intel_dp_is_edp(intel_dp)) {
> +   if (CAN_PSR(intel_dp)) {
> drm_dbg_kms(&i915->drm, "Forcing full modeset to
> compute PSR state\n");
> crtc_state->uapi.mode_changed = true;
> return false;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8ad9fcff3a12..e0111b470570 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1962,7 +1962,7 @@ void intel_psr_short_pulse(struct intel_dp
> *intel_dp)
>   DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
>   DP_PSR_LINK_CRC_ERROR;
>  
> -   if (!CAN_PSR(intel_dp) || !intel_dp_is_edp(intel_dp))
> +   if (!CAN_PSR(intel_dp))
> return;
>  
> mutex_lock(&psr->lock);
> @@ -2012,7 +2012,7 @@ bool intel_psr_enabled(struct intel_dp
> *intel_dp)
>  {
> bool ret;
>  
> -   if (!CAN_PSR(intel_dp) || !intel_dp_is_edp(intel_dp))
> +   if (!CAN_PSR(intel_dp))
> return false;
>  
> mutex_lock(&intel_dp->psr.lock);
Reviewed-by: Gwan-gyeong Mun 
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Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Set source_support even if panel do not support PSR

[Mun, Gwan-gyeong]

On Tue, 2021-02-09 at 10:14 -0800, José Roberto de Souza wrote:
> This will set the right value of source_support when the port
> encoder/port supports PSR but sink don't.
> 
> This change will also be needed in future for panel replay as psr
> struct needs to be initialized even if disconnected or current sink
> don't support PSR.
> 
> Cc: Gwan-gyeong Mun 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index e0111b470570..6b3e2120161e 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1837,9 +1837,6 @@ void intel_psr_init(struct intel_dp *intel_dp)
> if (!HAS_PSR(dev_priv))
> return;
>  
> -   if (!intel_dp->psr.sink_support)
> -   return;
> -
> /*
>  * HSW spec explicitly says PSR is tied to port A.
>  * BDW+ platforms have a instance of PSR registers per
> transcoder but

Reviewed-by: Gwan-gyeong Mun 



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[Intel-gfx] [PATCH] drm/compat: more dummy implementations

[Daniel Vetter]

drm_noop really doesnt do much, and who cares about the permission checks.
So let's delete some code.

Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/drm_ioc32.c | 15 +++
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/drm_ioc32.c b/drivers/gpu/drm/drm_ioc32.c
index dc734d4828a1..33390f02f5eb 100644
--- a/drivers/gpu/drm/drm_ioc32.c
+++ b/drivers/gpu/drm/drm_ioc32.c
@@ -302,12 +302,8 @@ static int compat_drm_getstats(struct file *file, unsigned 
int cmd,
   unsigned long arg)
 {
drm_stats32_t __user *argp = (void __user *)arg;
-   int err;
-
-   err = drm_ioctl_kernel(file, drm_noop, NULL, 0);
-   if (err)
-   return err;
 
+   /* getstats is defunct, just clear */
if (clear_user(argp, sizeof(drm_stats32_t)))
return -EFAULT;
return 0;
@@ -820,13 +816,8 @@ typedef struct drm_update_draw32 {
 static int compat_drm_update_draw(struct file *file, unsigned int cmd,
  unsigned long arg)
 {
-   drm_update_draw32_t update32;
-
-   if (copy_from_user(&update32, (void __user *)arg, sizeof(update32)))
-   return -EFAULT;
-
-   return drm_ioctl_kernel(file, drm_noop, NULL,
-   DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY);
+   /* update_draw is defunct */
+   return 0;
 }
 #endif
 
-- 
2.30.0

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Re: [Intel-gfx] [PATCH v3 9/9] drm/i915/edp: enable eDP MSO during link training

[Shankar, Uma]

> -Original Message-
> From: Intel-gfx  On Behalf Of Jani 
> Nikula
> Sent: Thursday, February 11, 2021 8:22 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Varide, Nischal 
> 
> Subject: [Intel-gfx] [PATCH v3 9/9] drm/i915/edp: enable eDP MSO during link
> training
> 
> If the source and sink support MSO, enable it during link training.
> 
> v3: Adjust timings, refer to splitter

Changes Look Good to me.
Reviewed-by: Uma Shankar 

> v2: Limit MSO to pipe A using ->pipe_mask
> 
> Cc: Nischal Varide 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 37 
>  drivers/gpu/drm/i915/display/intel_display.c | 13 +++
>  drivers/gpu/drm/i915/display/intel_dp.c  | 34 --
>  3 files changed, 82 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c9098297b6ac..5a8d1abd208a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2167,6 +2167,34 @@ static void intel_ddi_mso_get_config(struct
> intel_encoder *encoder,
>   pipe_config->splitter.pixel_overlap =
> REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);  }
> 
> +static void intel_ddi_mso_configure(const struct intel_crtc_state
> +*crtc_state) {
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + u32 dss1 = 0;
> +
> + if (!HAS_MSO(i915))
> + return;
> +
> + if (crtc_state->splitter.enable) {
> + /* Splitter enable is supported for pipe A only. */
> + if (drm_WARN_ON(&i915->drm, pipe != PIPE_A))
> + return;
> +
> + dss1 |= SPLITTER_ENABLE;
> + dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
> + if (crtc_state->splitter.link_count == 2)
> + dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
> + else
> + dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
> + }
> +
> + intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
> +  SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
> +  OVERLAP_PIXELS_MASK, dss1);
> +}
> +
>  static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state, @@ 
> -
> 2260,6 +2288,11 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state
> *state,
>*/
>   intel_ddi_power_up_lanes(encoder, crtc_state);
> 
> + /*
> +  * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
> +  */
> + intel_ddi_mso_configure(crtc_state);
> +
>   /*
>* 7.g Configure and enable DDI_BUF_CTL
>* 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout @@ 
> -
> 4143,6 +4176,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum
> port port)
>   goto err;
> 
>   dig_port->hpd_pulse = intel_dp_hpd_pulse;
> +
> + /* Splitter enable for eDP MSO is supported for pipe A only. */
> + if (dig_port->dp.mso_link_count)
> + encoder->pipe_mask = BIT(PIPE_A);
>   }
> 
>   /* In theory we don't need the encoder->type check, but leave it just 
> in diff -
> -git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 3059a07b8c36..06b7edbe1187 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4917,6 +4917,19 @@ static int intel_crtc_compute_config(struct intel_crtc
> *crtc,
>   pipe_config->pipe_src_w /= 2;
>   }
> 
> + if (pipe_config->splitter.enable) {
> + int n = pipe_config->splitter.link_count;
> + int overlap = pipe_config->splitter.pixel_overlap;
> +
> + pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) 
> *
> n;
> + pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start -
> overlap) * n;
> + pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end -
> overlap) * n;
> + pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start -
> overlap) * n;
> + pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end -
> overlap) * n;
> + pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;
> + pipe_mode->crtc_clock *= n;
> + }
> +
>   intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
> 
>   if (INTEL_GEN(dev_priv) < 4) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5d5b16f70ed2..8f39da994d14 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>

[Intel-gfx] [PATCH] drm/compat: Clear bounce structures

[Daniel Vetter]

Some of them have gaps, or fields we don't clear. Native ioctl code
does full copies plus zero-extends on size mismatch, so nothing can
leak. But compat is more hand-rolled so need to be careful.

None of these matter for performance, so just memset.

Also I didn't fix up the CONFIG_DRM_LEGACY or CONFIG_DRM_AGP ioctl, those
are security holes anyway.

Reported-by: syzbot+620cf21140fc7e772...@syzkaller.appspotmail.com # vblank 
ioctl
Cc: syzbot+620cf21140fc7e772...@syzkaller.appspotmail.com
Cc: sta...@vger.kernel.org
Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/drm_ioc32.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/drm_ioc32.c b/drivers/gpu/drm/drm_ioc32.c
index f86448ab1fe0..dc734d4828a1 100644
--- a/drivers/gpu/drm/drm_ioc32.c
+++ b/drivers/gpu/drm/drm_ioc32.c
@@ -99,6 +99,8 @@ static int compat_drm_version(struct file *file, unsigned int 
cmd,
if (copy_from_user(&v32, (void __user *)arg, sizeof(v32)))
return -EFAULT;
 
+   memset(&v, 0, sizeof(v));
+
v = (struct drm_version) {
.name_len = v32.name_len,
.name = compat_ptr(v32.name),
@@ -137,6 +139,9 @@ static int compat_drm_getunique(struct file *file, unsigned 
int cmd,
 
if (copy_from_user(&uq32, (void __user *)arg, sizeof(uq32)))
return -EFAULT;
+
+   memset(&uq, 0, sizeof(uq));
+
uq = (struct drm_unique){
.unique_len = uq32.unique_len,
.unique = compat_ptr(uq32.unique),
@@ -265,6 +270,8 @@ static int compat_drm_getclient(struct file *file, unsigned 
int cmd,
if (copy_from_user(&c32, argp, sizeof(c32)))
return -EFAULT;
 
+   memset(&client, 0, sizeof(client));
+
client.idx = c32.idx;
 
err = drm_ioctl_kernel(file, drm_getclient, &client, 0);
@@ -852,6 +859,8 @@ static int compat_drm_wait_vblank(struct file *file, 
unsigned int cmd,
if (copy_from_user(&req32, argp, sizeof(req32)))
return -EFAULT;
 
+   memset(&req, 0, sizeof(req));
+
req.request.type = req32.request.type;
req.request.sequence = req32.request.sequence;
req.request.signal = req32.request.signal;
@@ -889,6 +898,8 @@ static int compat_drm_mode_addfb2(struct file *file, 
unsigned int cmd,
struct drm_mode_fb_cmd2 req64;
int err;
 
+   memset(&req64, 0, sizeof(req64));
+
if (copy_from_user(&req64, argp,
   offsetof(drm_mode_fb_cmd232_t, modifier)))
return -EFAULT;
-- 
2.30.0

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Re: [Intel-gfx] [RFC PATCH 2/9] drm/i915/spi: intel_spi_region map

[Jani Nikula]

On Wed, 17 Feb 2021, "Winkler, Tomas"  wrote:
>> On Tue, 16 Feb 2021, Tomas Winkler  wrote:
>> > Add the dGFX spi region map and convey it via mfd cell platform data
>> > to the spi child device.
>> >
>> > Cc: Rodrigo Vivi 
>> > Cc: Lucas De Marchi 
>> > Signed-off-by: Tomas Winkler 
>> > ---
>> >  drivers/gpu/drm/i915/spi/intel_spi.c | 9 +
>> > drivers/gpu/drm/i915/spi/intel_spi.h | 5 +
>> >  2 files changed, 14 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c
>> > b/drivers/gpu/drm/i915/spi/intel_spi.c
>> > index 07da7197bd5d..6f83f24f7208 100644
>> > --- a/drivers/gpu/drm/i915/spi/intel_spi.c
>> > +++ b/drivers/gpu/drm/i915/spi/intel_spi.c
>> > @@ -14,11 +14,20 @@ static const struct resource spi_resources[] = {
>> >DEFINE_RES_MEM_NAMED(GEN12_GUNIT_SPI_BASE, 0x80, "i915-
>> spi-mmio"),
>> > };
>> >
>> > +static const struct i915_spi_region regions[I915_SPI_REGIONS] = {
>> > +  [0] = { .name = "DESCRIPTOR", },
>> > +  [2] = { .name = "GSC", },
>> > +  [11] = { .name = "OptionROM", },
>> > +  [12] = { .name = "DAM", },
>> > +};
>> > +
>> >  static const struct mfd_cell intel_spi_cell = {
>> >.id = 2,
>> >.name = "i915-spi",
>> >.num_resources = ARRAY_SIZE(spi_resources),
>> >.resources = spi_resources,
>> > +  .platform_data = (void *)regions,
>> > +  .pdata_size= sizeof(regions),
>> >  };
>> >
>> >  void intel_spi_init(struct intel_spi *spi, struct drm_i915_private
>> > *dev_priv) diff --git a/drivers/gpu/drm/i915/spi/intel_spi.h
>> > b/drivers/gpu/drm/i915/spi/intel_spi.h
>> > index 276551fed993..6b5bf053f7d3 100644
>> > --- a/drivers/gpu/drm/i915/spi/intel_spi.h
>> > +++ b/drivers/gpu/drm/i915/spi/intel_spi.h
>> > @@ -8,6 +8,11 @@
>> >
>> >  struct drm_i915_private;
>> >
>> > +#define I915_SPI_REGIONS 13
>> > +struct i915_spi_region {
>> > +  const char *name;
>> > +};
>> 
>> Does this need to be exposed to the rest of i915? 
> This part is between the device which is part of i915 and the driver.
>>If we're trying to isolate
>> spi/, I'd prefer it if this header was the only header included from the 
>> rest of
>> i915, and contained the minimum required information.
>
>> As the driver has grown bigger, we've tried to minimize the interconnections
>> between the modules, and it's slow going. Let's try to keep the new parts
>> isolated.
>>
> So do you prefer we create another header or duplicate the structure 
> definition? 

I didn't see the struct being used in i915, or am I missing something?

Have a header that contains the interface exposed to the rest of i915,
and another header with stuff internal to spi/?

BR,
Jani.




-- 
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/compat: more dummy implementations

[Patchwork]

== Series Details ==

Series: drm/compat: more dummy implementations
URL   : https://patchwork.freedesktop.org/series/87280/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
49f0011150a1 drm/compat: more dummy implementations
-:6: WARNING:TYPO_SPELLING: 'doesnt' may be misspelled - perhaps 'doesn't'?
#6: 
drm_noop really doesnt do much, and who cares about the permission checks.
^^

-:44: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address 
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: 
Daniel Vetter '

total: 0 errors, 2 warnings, 0 checks, 28 lines checked


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Re: [Intel-gfx] [PATCH v2] drm/i915/display: Allow PSR2 selective fetch to be enabled at run-time

[Mun, Gwan-gyeong]

On Tue, 2021-02-09 at 12:50 -0800, José Roberto de Souza wrote:
> Right now CI is blacklisting module reload, so we need to be able to
> enable PSR2 selective fetch in run time to test this feature before
> enable it by default.
> Changes in IGT will also be needed.
> 
> v2:
> - Fixed handling of I915_PSR_DEBUG_ENABLE_SEL_FETCH in
> intel_psr_debug_set()
> 
> Cc: Gwan-gyeong Mun 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
>  drivers/gpu/drm/i915/display/intel_psr.c   | 8 +---
>  2 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ebaa9d0ed376..577f47aa6b3e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1425,6 +1425,7 @@ struct intel_psr {
>  #define I915_PSR_DEBUG_DISABLE 0x01
>  #define I915_PSR_DEBUG_ENABLE  0x02
>  #define I915_PSR_DEBUG_FORCE_PSR1  0x03
> +#define I915_PSR_DEBUG_ENABLE_SEL_FETCH0x4
>  #define I915_PSR_DEBUG_IRQ 0x10
>  
> u32 debug;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index bf214d0e2dec..43e9e362382b 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -684,7 +684,8 @@ static bool
> intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> struct intel_plane *plane;
> int i;
>  
> -   if (!dev_priv->params.enable_psr2_sel_fetch) {
> +   if (!dev_priv->params.enable_psr2_sel_fetch &&
> +   intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
> drm_dbg_kms(&dev_priv->drm,
>     "PSR2 sel fetch not enabled, disabled by
> parameter\n");
> return false;
> @@ -1448,7 +1449,8 @@ void intel_psr_update(struct intel_dp
> *intel_dp,
> enable = crtc_state->has_psr;
> psr2_enable = crtc_state->has_psr2;
>  
> -   if (enable == psr->enabled && psr2_enable == psr-
> >psr2_enabled) {
> +   if (enable == psr->enabled && psr2_enable == psr-
> >psr2_enabled &&
> +   crtc_state->enable_psr2_sel_fetch == psr-
> >psr2_sel_fetch_enabled) {
> /* Force a PSR exit when enabling CRC to avoid CRC
> timeouts */
> if (crtc_state->crc_enabled && psr->enabled)
> psr_force_hw_tracking_exit(intel_dp);
> @@ -1637,7 +1639,7 @@ int intel_psr_debug_set(struct intel_dp
> *intel_dp, u64 val)
> int ret;
>  
> if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
> -   mode > I915_PSR_DEBUG_FORCE_PSR1) {
> +   mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
> drm_dbg_kms(&dev_priv->drm, "Invalid debug mask
> %llx\n", val);
> return -EINVAL;
> }

Looks good to me.
Reviewed-by: Gwan-gyeong Mun 



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[Intel-gfx] [PATCH] drm/i915/display: Do not allow DC3CO if PSR SF is enabled

[Gwan-gyeong Mun]

Even though GEN12+ HW supports PSR + DC3CO, DMC's HW DC3CO exitmachanism
has an issue with using of SelectiveFecth and PSR2 ManualTracking.
And as new GEN12+ platform like RKL, ADL-S/P don't have PSR2 HW tracking,
Selective Fetch wiil be enabled by default.
Therefore if the system enables PSR SelectiveFetch / PSR ManualTracking,
it does not allow DC3CO dc state, in that case.

When this DC3CO exit issue is addressed while PSR SF is enabled,
this restriction should be removed.

Cc: José Roberto de Souza 
Cc: Anshuman Gupta 
Signed-off-by: Gwan-gyeong Mun 
---
 .../drm/i915/display/intel_display_power.c| 19 +--
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index f00c1750febd..b385b3f082f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -804,10 +804,12 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 
mask = DC_STATE_EN_UPTO_DC5;
 
-   if (INTEL_GEN(dev_priv) >= 12)
-   mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
- | DC_STATE_EN_DC9;
-   else if (IS_GEN(dev_priv, 11))
+   if (INTEL_GEN(dev_priv) >= 12) {
+   /* DMC's DC3CO exit machanism has an issue with SelectiveFecth 
*/
+   if (!dev_priv->params.enable_psr2_sel_fetch)
+   mask |=  DC_STATE_EN_DC3CO;
+   mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
+   } else if (IS_GEN(dev_priv, 11))
mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
else if (IS_GEN9_LP(dev_priv))
mask |= DC_STATE_EN_DC9;
@@ -4588,10 +4590,15 @@ static u32 get_allowed_dc_mask(const struct 
drm_i915_private *dev_priv,
 
switch (requested_dc) {
case 4:
-   mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
+   /* DMC's DC3CO exit machanism has an issue with SelectiveFecth 
*/
+   if (!dev_priv->params.enable_psr2_sel_fetch)
+   mask |=  DC_STATE_EN_DC3CO;
+   mask |= DC_STATE_EN_UPTO_DC6;
break;
case 3:
-   mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
+   if (!dev_priv->params.enable_psr2_sel_fetch)
+   mask |=  DC_STATE_EN_DC3CO;
+   mask |= DC_STATE_EN_UPTO_DC5;
break;
case 2:
mask |= DC_STATE_EN_UPTO_DC6;
-- 
2.30.0

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Re: [Intel-gfx] [RFC PATCH 2/9] drm/i915/spi: intel_spi_region map

[Winkler, Tomas]

> On Wed, 17 Feb 2021, "Winkler, Tomas"  wrote:
> >> On Tue, 16 Feb 2021, Tomas Winkler  wrote:
> >> > Add the dGFX spi region map and convey it via mfd cell platform
> >> > data to the spi child device.
> >> >
> >> > Cc: Rodrigo Vivi 
> >> > Cc: Lucas De Marchi 
> >> > Signed-off-by: Tomas Winkler 
> >> > ---
> >> >  drivers/gpu/drm/i915/spi/intel_spi.c | 9 +
> >> > drivers/gpu/drm/i915/spi/intel_spi.h | 5 +
> >> >  2 files changed, 14 insertions(+)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c
> >> > b/drivers/gpu/drm/i915/spi/intel_spi.c
> >> > index 07da7197bd5d..6f83f24f7208 100644
> >> > --- a/drivers/gpu/drm/i915/spi/intel_spi.c
> >> > +++ b/drivers/gpu/drm/i915/spi/intel_spi.c
> >> > @@ -14,11 +14,20 @@ static const struct resource spi_resources[] = {
> >> >  DEFINE_RES_MEM_NAMED(GEN12_GUNIT_SPI_BASE, 0x80, "i915-
> >> spi-mmio"),
> >> > };
> >> >
> >> > +static const struct i915_spi_region regions[I915_SPI_REGIONS] = {
> >> > +[0] = { .name = "DESCRIPTOR", },
> >> > +[2] = { .name = "GSC", },
> >> > +[11] = { .name = "OptionROM", },
> >> > +[12] = { .name = "DAM", },
> >> > +};
> >> > +
> >> >  static const struct mfd_cell intel_spi_cell = {
> >> >  .id = 2,
> >> >  .name = "i915-spi",
> >> >  .num_resources = ARRAY_SIZE(spi_resources),
> >> >  .resources = spi_resources,
> >> > +.platform_data = (void *)regions,
> >> > +.pdata_size= sizeof(regions),
> >> >  };
> >> >
> >> >  void intel_spi_init(struct intel_spi *spi, struct drm_i915_private
> >> > *dev_priv) diff --git a/drivers/gpu/drm/i915/spi/intel_spi.h
> >> > b/drivers/gpu/drm/i915/spi/intel_spi.h
> >> > index 276551fed993..6b5bf053f7d3 100644
> >> > --- a/drivers/gpu/drm/i915/spi/intel_spi.h
> >> > +++ b/drivers/gpu/drm/i915/spi/intel_spi.h
> >> > @@ -8,6 +8,11 @@
> >> >
> >> >  struct drm_i915_private;
> >> >
> >> > +#define I915_SPI_REGIONS 13
> >> > +struct i915_spi_region {
> >> > +const char *name;
> >> > +};
> >>
> >> Does this need to be exposed to the rest of i915?
> > This part is between the device which is part of i915 and the driver.
> >>If we're trying to isolate
> >> spi/, I'd prefer it if this header was the only header included from
> >>the rest of  i915, and contained the minimum required information.
> >
> >> As the driver has grown bigger, we've tried to minimize the
> >> interconnections between the modules, and it's slow going. Let's try
> >> to keep the new parts isolated.
> >>
> > So do you prefer we create another header or duplicate the structure
> definition?
> 
> I didn't see the struct being used in i915, or am I missing something?
This file is part of i915
 
> Have a header that contains the interface exposed to the rest of i915, and
> another header with stuff internal to spi/?

The spi `device` is part of i915 (as a mfd cell) and  struct i915_spi_region is 
 passed to the spi `driver` as platform_data of the device.
In order for driver to be able to understand  it needs to know ' struct 
i915_spi_region' 

Thanks
Tomas

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/compat: more dummy implementations

[Patchwork]

== Series Details ==

Series: drm/compat: more dummy implementations
URL   : https://patchwork.freedesktop.org/series/87280/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9793 -> Patchwork_19712


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/index.html

Known issues


  Here are the changes found in Patchwork_19712 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-bsw-n3050:   NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/fi-bsw-n3050/igt@amdgpu/amd_cs_...@sync-gfx0.html

  * igt@gem_huc_copy@huc-copy:
- fi-bxt-dsi: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/fi-bxt-dsi/igt@gem_huc_c...@huc-copy.html

  * igt@gem_tiled_blits@basic:
- fi-tgl-y:   [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar 
issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/fi-tgl-y/igt@gem_tiled_bl...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/fi-tgl-y/igt@gem_tiled_bl...@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-bxt-dsi: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/fi-bxt-dsi/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-bxt-dsi: NOTRUN -> [SKIP][6] ([fdo#109271]) +27 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/fi-bxt-dsi/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-bxt-dsi: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#533])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/fi-bxt-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  
 Possible fixes 

  * igt@i915_selftest@live@execlists:
- fi-bsw-n3050:   [INCOMPLETE][8] ([i915#2940]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [DMESG-WARN][10] ([i915#402]) -> [PASS][11] +2 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Participating hosts (43 -> 40)
--

  Additional (1): fi-bxt-dsi 
  Missing(4): fi-byt-j1900 fi-ctg-p8600 fi-bdw-samus fi-hsw-4200u 


Build changes
-

  * Linux: CI_DRM_9793 -> Patchwork_19712

  CI-20190529: 20190529
  CI_DRM_9793: 6c7aa00d5968abe675da4d933d6ec819fed58e69 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6010: e8fb87056cc4053dde25fe151df9ed3264adbf5a @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19712: 49f0011150a164ecc120679fbd1a8d76da94db57 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

49f0011150a1 drm/compat: more dummy implementations

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/index.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/compat: Clear bounce structures

[Patchwork]

== Series Details ==

Series: drm/compat: Clear bounce structures
URL   : https://patchwork.freedesktop.org/series/87281/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
3f5e3da95ed8 drm/compat: Clear bounce structures
-:69: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address 
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: 
Daniel Vetter '

total: 0 errors, 1 warnings, 0 checks, 41 lines checked


___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/compat: Clear bounce structures

[Patchwork]

== Series Details ==

Series: drm/compat: Clear bounce structures
URL   : https://patchwork.freedesktop.org/series/87281/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9793 -> Patchwork_19713


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/index.html

Known issues


  Here are the changes found in Patchwork_19713 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-bsw-n3050:   NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/fi-bsw-n3050/igt@amdgpu/amd_cs_...@sync-gfx0.html

  * igt@gem_huc_copy@huc-copy:
- fi-bxt-dsi: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/fi-bxt-dsi/igt@gem_huc_c...@huc-copy.html

  * igt@gem_mmap_gtt@basic:
- fi-tgl-y:   [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar 
issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/fi-tgl-y/igt@gem_mmap_...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/fi-tgl-y/igt@gem_mmap_...@basic.html

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-7500u:   [PASS][5] -> [DMESG-WARN][6] ([i915#2605])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/fi-kbl-7500u/igt@i915_pm_...@module-reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/fi-kbl-7500u/igt@i915_pm_...@module-reload.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-bxt-dsi: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/fi-bxt-dsi/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-bxt-dsi: NOTRUN -> [SKIP][8] ([fdo#109271]) +27 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/fi-bxt-dsi/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-bxt-dsi: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/fi-bxt-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  
 Possible fixes 

  * igt@i915_selftest@live@execlists:
- fi-bsw-n3050:   [INCOMPLETE][10] ([i915#2940]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [DMESG-WARN][12] ([i915#402]) -> [PASS][13] +1 
similar issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Participating hosts (43 -> 41)
--

  Additional (1): fi-bxt-dsi 
  Missing(3): fi-ctg-p8600 fi-bdw-samus fi-hsw-4200u 


Build changes
-

  * Linux: CI_DRM_9793 -> Patchwork_19713

  CI-20190529: 20190529
  CI_DRM_9793: 6c7aa00d5968abe675da4d933d6ec819fed58e69 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6010: e8fb87056cc4053dde25fe151df9ed3264adbf5a @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19713: 3f5e3da95ed8db893ddebc0cb5bde3ce9f1a221d @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3f5e3da95ed8 drm/compat: Clear bounce structures

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/index.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Do not allow DC3CO if PSR SF is enabled

[Patchwork]

== Series Details ==

Series: drm/i915/display: Do not allow DC3CO if PSR SF is enabled
URL   : https://patchwork.freedesktop.org/series/87283/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
64ad41f78f8f drm/i915/display: Do not allow DC3CO if PSR SF is enabled
-:12: WARNING:TYPO_SPELLING: 'wiil' may be misspelled - perhaps 'will'?
#12: 
Selective Fetch wiil be enabled by default.


-:35: CHECK:BRACES: braces {} should be used on all arms of this statement
#35: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:807:
+   if (INTEL_GEN(dev_priv) >= 12) {
[...]
+   } else if (IS_GEN(dev_priv, 11))
[...]
else if (IS_GEN9_LP(dev_priv))
[...]

total: 0 errors, 1 warnings, 1 checks, 33 lines checked


___
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Re: [Intel-gfx] i915 dma faults on Xen

[Jason Andryuk]

On Mon, Feb 22, 2021 at 5:18 AM Roger Pau Monné  wrote:
>
> On Fri, Feb 19, 2021 at 12:30:23PM -0500, Jason Andryuk wrote:
> > On Wed, Oct 21, 2020 at 9:59 AM Jan Beulich  wrote:
> > >
> > > On 21.10.2020 15:36, Jason Andryuk wrote:
> > > > On Wed, Oct 21, 2020 at 8:53 AM Jan Beulich  wrote:
> > > >>
> > > >> On 21.10.2020 14:45, Jason Andryuk wrote:
> > > >>> On Wed, Oct 21, 2020 at 5:58 AM Roger Pau Monné 
> > > >>>  wrote:
> > >  Hm, it's hard to tell what's going on. My limited experience with
> > >  IOMMU faults on broken systems there's a small range that initially
> > >  triggers those, and then the device goes wonky and starts accessing a
> > >  whole load of invalid addresses.
> > > 
> > >  You could try adding those manually using the rmrr Xen command line
> > >  option [0], maybe you can figure out which range(s) are missing?
> > > >>>
> > > >>> They seem to change, so it's hard to know.  Would there be harm in
> > > >>> adding one to cover the end of RAM ( 0x04,7c80, ) to (
> > > >>> 0xff,, )?  Maybe that would just quiet the pointless faults
> > > >>> while leaving the IOMMU enabled?
> > > >>
> > > >> While they may quieten the faults, I don't think those faults are
> > > >> pointless. They indicate some problem with the software (less
> > > >> likely the hardware, possibly the firmware) that you're using.
> > > >> Also there's the question of what the overall behavior is going
> > > >> to be when devices are permitted to access unpopulated address
> > > >> ranges. I assume you did check already that no devices have their
> > > >> BARs placed in that range?
> > > >
> > > > Isn't no-igfx already letting them try to read those unpopulated 
> > > > addresses?
> > >
> > > Yes, and it is for the reason that the documentation for the
> > > option says "If specifying `no-igfx` fixes anything, please
> > > report the problem." I imply from in in particular that one
> > > better wouldn't use it for non-development purposes of whatever
> > > kind.
> >
> > I stopped seeing these DMA faults, but I didn't know what made them go
> > away.  Then when working with an older 5.4.64 kernel, I saw them
> > again.  Eric bisected down to the 5.4.y version of mainline linux
> > commit:
> >
> > commit 8195400f7ea95399f721ad21f4d663a62c65036f
> > Author: Chris Wilson 
> > Date:   Mon Oct 19 11:15:23 2020 +0100
> >
> > drm/i915: Force VT'd workarounds when running as a guest OS
> >
> > If i915.ko is being used as a passthrough device, it does not know if
> > the host is using intel_iommu. Mixing the iommu and gfx causes a few
> > issues (such as scanout overfetch) which we need to workaround inside
> > the driver, so if we detect we are running under a hypervisor, also
> > assume the device access is being virtualised.
>
> So the commit above fixes the DMA faults seen on Linux when using a
> i915 gfx card?

Yes, DMA faults are not seen with this commit.  i915 behaves
differently when it detects VT-d active, and this commit sets the VT-d
behavior when running under any hypervisor.

Regards,
Jason
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Do not allow DC3CO if PSR SF is enabled

[Patchwork]

== Series Details ==

Series: drm/i915/display: Do not allow DC3CO if PSR SF is enabled
URL   : https://patchwork.freedesktop.org/series/87283/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9793 -> Patchwork_19714


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/index.html

Known issues


  Here are the changes found in Patchwork_19714 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-bxt-dsi: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/fi-bxt-dsi/igt@gem_huc_c...@huc-copy.html

  * igt@gem_ringfill@basic-all:
- fi-tgl-y:   [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +2 similar 
issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/fi-tgl-y/igt@gem_ringf...@basic-all.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/fi-tgl-y/igt@gem_ringf...@basic-all.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-bxt-dsi: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/fi-bxt-dsi/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-bxt-dsi: NOTRUN -> [SKIP][5] ([fdo#109271]) +27 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/fi-bxt-dsi/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-bxt-dsi: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#533])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/fi-bxt-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  
 Possible fixes 

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Participating hosts (43 -> 41)
--

  Additional (1): fi-bxt-dsi 
  Missing(3): fi-ctg-p8600 fi-bdw-samus fi-hsw-4200u 


Build changes
-

  * Linux: CI_DRM_9793 -> Patchwork_19714

  CI-20190529: 20190529
  CI_DRM_9793: 6c7aa00d5968abe675da4d933d6ec819fed58e69 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6010: e8fb87056cc4053dde25fe151df9ed3264adbf5a @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19714: 64ad41f78f8fb8dd7f52f6856cf07f6c99da6051 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

64ad41f78f8f drm/i915/display: Do not allow DC3CO if PSR SF is enabled

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/index.html
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[Intel-gfx] [PATCH] drivers: gnu: drm: i915: gvt: Fixed couple of spellings in the file gtt.c

[Bhaskar Chowdhury]

s/negtive/negative/
s/possilbe/possible/

Signed-off-by: Bhaskar Chowdhury 
---
 drivers/gpu/drm/i915/gvt/gtt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 897c007ea96a..dc5834bf4de2 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1159,8 +1159,8 @@ static inline void ppgtt_generate_shadow_entry(struct 
intel_gvt_gtt_entry *se,
  * @vgpu: target vgpu
  * @entry: target pfn's gtt entry
  *
- * Return 1 if 2MB huge gtt shadowing is possilbe, 0 if miscondition,
- * negtive if found err.
+ * Return 1 if 2MB huge gtt shadowing is possible, 0 if miscondition,
+ * negative if found err.
  */
 static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
struct intel_gvt_gtt_entry *entry)
--
2.26.2

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Re: [Intel-gfx] [PATCH RFC v1 5/6] xen-swiotlb: convert variables to arrays

[Boris Ostrovsky]

On 2/19/21 3:32 PM, Konrad Rzeszutek Wilk wrote:
> On Sun, Feb 07, 2021 at 04:56:01PM +0100, Christoph Hellwig wrote:
>> On Thu, Feb 04, 2021 at 09:40:23AM +0100, Christoph Hellwig wrote:
>>> So one thing that has been on my mind for a while:  I'd really like
>>> to kill the separate dma ops in Xen swiotlb.  If we compare xen-swiotlb
>>> to swiotlb the main difference seems to be:
>>>
>>>  - additional reasons to bounce I/O vs the plain DMA capable
>>>  - the possibility to do a hypercall on arm/arm64
>>>  - an extra translation layer before doing the phys_to_dma and vice
>>>versa
>>>  - an special memory allocator
>>>
>>> I wonder if inbetween a few jump labels or other no overhead enablement
>>> options and possibly better use of the dma_range_map we could kill
>>> off most of swiotlb-xen instead of maintaining all this code duplication?
>> So I looked at this a bit more.
>>
>> For x86 with XENFEAT_auto_translated_physmap (how common is that?)
> Juergen, Boris please correct me if I am wrong, but that 
> XENFEAT_auto_translated_physmap
> only works for PVH guests?


That's both HVM and PVH (for dom0 it's only PVH).


-boris



>
>> pfn_to_gfn is a nop, so plain phys_to_dma/dma_to_phys do work as-is.
>>
>> xen_arch_need_swiotlb always returns true for x86, and
>> range_straddles_page_boundary should never be true for the
>> XENFEAT_auto_translated_physmap case.
> Correct. The kernel should have no clue of what the real MFNs are
> for PFNs.
>> So as far as I can tell the mapping fast path for the
>> XENFEAT_auto_translated_physmap can be trivially reused from swiotlb.
>>
>> That leaves us with the next more complicated case, x86 or fully cache
>> coherent arm{,64} without XENFEAT_auto_translated_physmap.  In that case
>> we need to patch in a phys_to_dma/dma_to_phys that performs the MFN
>> lookup, which could be done using alternatives or jump labels.
>> I think if that is done right we should also be able to let that cover
>> the foreign pages in is_xen_swiotlb_buffer/is_swiotlb_buffer, but
>> in that worst case that would need another alternative / jump label.
>>
>> For non-coherent arm{,64} we'd also need to use alternatives or jump
>> labels to for the cache maintainance ops, but that isn't a hard problem
>> either.
>>
>>
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[Intel-gfx] ✓ Fi.CI.BAT: success for drivers: gnu: drm: i915: gvt: Fixed couple of spellings in the file gtt.c

[Patchwork]

== Series Details ==

Series: drivers: gnu: drm: i915: gvt: Fixed couple of spellings in the file 
gtt.c
URL   : https://patchwork.freedesktop.org/series/87286/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9793 -> Patchwork_19715


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/index.html

Known issues


  Here are the changes found in Patchwork_19715 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-bsw-n3050:   NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/fi-bsw-n3050/igt@amdgpu/amd_cs_...@sync-gfx0.html

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2:  [PASS][2] -> [FAIL][3] ([i915#1888])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html

  * igt@gem_flink_basic@bad-flink:
- fi-tgl-y:   [PASS][4] -> [DMESG-WARN][5] ([i915#402]) +1 similar 
issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html

  * igt@gem_huc_copy@huc-copy:
- fi-bxt-dsi: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/fi-bxt-dsi/igt@gem_huc_c...@huc-copy.html

  * igt@i915_pm_rpm@module-reload:
- fi-byt-j1900:   [PASS][7] -> [INCOMPLETE][8] ([i915#142] / 
[i915#2405])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/fi-byt-j1900/igt@i915_pm_...@module-reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/fi-byt-j1900/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][9] -> [INCOMPLETE][10] ([i915#2940])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/fi-bsw-nick/igt@i915_selftest@l...@execlists.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-bxt-dsi: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/fi-bxt-dsi/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-bxt-dsi: NOTRUN -> [SKIP][12] ([fdo#109271]) +27 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/fi-bxt-dsi/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-bxt-dsi: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/fi-bxt-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][14] ([i915#1436])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/fi-bsw-nick/igt@run...@aborted.html
- fi-byt-j1900:   NOTRUN -> [FAIL][15] ([i915#1814] / [i915#2505])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/fi-byt-j1900/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@execlists:
- fi-bsw-n3050:   [INCOMPLETE][16] ([i915#2940]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [DMESG-WARN][18] ([i915#402]) -> [PASS][19] +2 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
  [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel

Re: [Intel-gfx] [PATCH] drm/i915/display: Do not allow DC3CO if PSR SF is enabled

[Souza, Jose]

On Mon, 2021-02-22 at 13:24 +0200, Gwan-gyeong Mun wrote:
> Even though GEN12+ HW supports PSR + DC3CO, DMC's HW DC3CO exitmachanism

typo and missing space between exit and mechanism

> has an issue with using of SelectiveFecth and PSR2 ManualTracking.

manual tracking.

> And as new GEN12+ platform like RKL, ADL-S/P don't have PSR2 HW tracking,
> Selective Fetch wiil be enabled by default.
> Therefore if the system enables PSR SelectiveFetch / PSR ManualTracking,
> it does not allow DC3CO dc state, in that case.
> 
> When this DC3CO exit issue is addressed while PSR SF is enabled,
> this restriction should be removed.
> 
> Cc: José Roberto de Souza 
> Cc: Anshuman Gupta 
> Signed-off-by: Gwan-gyeong Mun 
> ---
>  .../drm/i915/display/intel_display_power.c| 19 +--
>  1 file changed, 13 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index f00c1750febd..b385b3f082f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -804,10 +804,12 @@ static u32 gen9_dc_mask(struct drm_i915_private 
> *dev_priv)
>  
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
>   mask = DC_STATE_EN_UPTO_DC5;
>  
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> - if (INTEL_GEN(dev_priv) >= 12)
> - mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
> -   | DC_STATE_EN_DC9;
> - else if (IS_GEN(dev_priv, 11))
> + if (INTEL_GEN(dev_priv) >= 12) {
> + /* DMC's DC3CO exit machanism has an issue with SelectiveFecth 
> */
> + if (!dev_priv->params.enable_psr2_sel_fetch)
> + mask |=  DC_STATE_EN_DC3CO;
> + mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
> + } else if (IS_GEN(dev_priv, 11))
>   mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
>   else if (IS_GEN9_LP(dev_priv))
>   mask |= DC_STATE_EN_DC9;
> @@ -4588,10 +4590,15 @@ static u32 get_allowed_dc_mask(const struct 
> drm_i915_private *dev_priv,
>  
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
>   switch (requested_dc) {
>   case 4:
> - mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
> + /* DMC's DC3CO exit machanism has an issue with SelectiveFecth 
> */
> + if (!dev_priv->params.enable_psr2_sel_fetch)
> + mask |=  DC_STATE_EN_DC3CO;
> + mask |= DC_STATE_EN_UPTO_DC6;
>   break;
>   case 3:
> - mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
> + if (!dev_priv->params.enable_psr2_sel_fetch)
> + mask |=  DC_STATE_EN_DC3CO;
> + mask |= DC_STATE_EN_UPTO_DC5;
>   break;

Doing this in the wrong place, would be much easier do it in 
tgl_dc3co_exitline_compute_config().

>   case 2:
>   mask |= DC_STATE_EN_UPTO_DC6;

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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Allow PSR2 selective fetch to be enabled at run-time (rev2)

[Souza, Jose]

On Wed, 2021-02-10 at 00:27 +, Patchwork wrote:
Patch Details
Series: drm/i915/display: Allow PSR2 selective fetch to be enabled at run-time 
(rev2)
URL:https://patchwork.freedesktop.org/series/86773/
State:  failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19645/index.html
CI Bug Log - changes from CI_DRM_9752_full -> Patchwork_19645_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_19645_full absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19645_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_19645_full:

IGT changes
Possible regressions

  *   igt@gem_exec_capture@capture@bcs0:
 *   shard-skl: 
PASS
 -> 
FAIL

Not related.

Patch pushed thanks for the review GG.

Known issues

Here are the changes found in Patchwork_19645_full that come from known issues:

IGT changes
Issues hit

  *   igt@gem_eio@unwedge-stress:

 *   shard-tglb: 
PASS
 -> 
TIMEOUT
 ([i915#1037] / [i915#3063])

 *   shard-iclb: 
PASS
 -> 
TIMEOUT
 ([i915#1037] / [i915#2481])

  *   igt@gem_exec_balancer@hang:

 *   shard-iclb: 
PASS
 -> 
INCOMPLETE
 ([i915#1895] / [i915#2295])
  *   igt@gem_exec_fair@basic-flow@rcs0:

 *   shard-tglb: 
PASS
 -> 
FAIL
 ([i915#2842])
  *   igt@gem_exec_fair@basic-none-solo@rcs0:

 *   shard-kbl: 
PASS
 -> 
FAIL
 ([i915#2842]) +1 similar issue
  *   igt@gem_exec_fair@basic-pace@vcs0:

 *   shard-glk: 
PASS
 -> 
FAIL
 ([i915#2842])
  *   igt@gem_exec_fair@basic-sync@rcs0:

 *   shard-kbl: 
PASS
 -> 
SKIP
 ([fdo#109271])
  *   igt@gem_exec_reloc@basic-wide-active@rcs0:

 *   shard-kbl: NOTRUN -> 
FAIL
 ([i915#2389]) +4 similar issues
  *   igt@gem_exec_reloc@basic-wide-active@vcs1:

 *   shard-iclb: NOTRUN -> 
FAIL
 ([i915#2389])
  *   igt@gem_exec_schedule@u-fairslice@bcs0:

 *   shard-iclb: 
PASS
 -> 
DMESG-WARN
 ([i915#2803])
  *   igt@gem_exec_schedule@u-fairslice@rcs0:

 *   shard-skl: 
PASS
 -> 
DMESG-WARN
 ([i915#1610] / [i915#2803])
  *   igt@gem_exec_schedule@u-fairslice@vcs0:

 *   shard-glk: 
PASS
 -> 
DMESG-WARN
 ([i915#1610] / [i915#2803])
  *   igt@gem_exec_whisper@basic-fds:

 *   shard-glk: 
PASS

Re: [Intel-gfx] [PATCH] drivers: gnu: drm: i915: gvt: Fixed couple of spellings in the file gtt.c

[Randy Dunlap]

On 2/22/21 12:18 AM, Bhaskar Chowdhury wrote:
> 
> s/negtive/negative/
> s/possilbe/possible/
> 
> Signed-off-by: Bhaskar Chowdhury 

Acked-by: Randy Dunlap 

> ---
>  drivers/gpu/drm/i915/gvt/gtt.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index 897c007ea96a..dc5834bf4de2 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -1159,8 +1159,8 @@ static inline void ppgtt_generate_shadow_entry(struct 
> intel_gvt_gtt_entry *se,
>   * @vgpu: target vgpu
>   * @entry: target pfn's gtt entry
>   *
> - * Return 1 if 2MB huge gtt shadowing is possilbe, 0 if miscondition,
> - * negtive if found err.
> + * Return 1 if 2MB huge gtt shadowing is possible, 0 if miscondition,
> + * negative if found err.
>   */
>  static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
>   struct intel_gvt_gtt_entry *entry)
> --


-- 
~Randy

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Re: [Intel-gfx] [PATCH] drivers: gnu: drm: i915: gvt: Fixed couple of spellings in the file gtt.c

[Randy Dunlap]

On 2/22/21 6:21 AM, Randy Dunlap wrote:
> On 2/22/21 12:18 AM, Bhaskar Chowdhury wrote:
>>
>> s/negtive/negative/
>> s/possilbe/possible/
>>
>> Signed-off-by: Bhaskar Chowdhury 
> 
> Acked-by: Randy Dunlap 

except the Subject has a typo in it.
s/gnu/gpu/

>> ---
>>  drivers/gpu/drm/i915/gvt/gtt.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
>> index 897c007ea96a..dc5834bf4de2 100644
>> --- a/drivers/gpu/drm/i915/gvt/gtt.c
>> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
>> @@ -1159,8 +1159,8 @@ static inline void ppgtt_generate_shadow_entry(struct 
>> intel_gvt_gtt_entry *se,
>>   * @vgpu: target vgpu
>>   * @entry: target pfn's gtt entry
>>   *
>> - * Return 1 if 2MB huge gtt shadowing is possilbe, 0 if miscondition,
>> - * negtive if found err.
>> + * Return 1 if 2MB huge gtt shadowing is possible, 0 if miscondition,
>> + * negative if found err.
>>   */
>>  static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
>>  struct intel_gvt_gtt_entry *entry)
>> --
> 
> 


-- 
~Randy
Reported-by: Randy Dunlap 
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Re: [Intel-gfx] i915 dma faults on Xen

[Roger Pau Monné]

On Fri, Feb 19, 2021 at 12:30:23PM -0500, Jason Andryuk wrote:
> On Wed, Oct 21, 2020 at 9:59 AM Jan Beulich  wrote:
> >
> > On 21.10.2020 15:36, Jason Andryuk wrote:
> > > On Wed, Oct 21, 2020 at 8:53 AM Jan Beulich  wrote:
> > >>
> > >> On 21.10.2020 14:45, Jason Andryuk wrote:
> > >>> On Wed, Oct 21, 2020 at 5:58 AM Roger Pau Monné  
> > >>> wrote:
> >  Hm, it's hard to tell what's going on. My limited experience with
> >  IOMMU faults on broken systems there's a small range that initially
> >  triggers those, and then the device goes wonky and starts accessing a
> >  whole load of invalid addresses.
> > 
> >  You could try adding those manually using the rmrr Xen command line
> >  option [0], maybe you can figure out which range(s) are missing?
> > >>>
> > >>> They seem to change, so it's hard to know.  Would there be harm in
> > >>> adding one to cover the end of RAM ( 0x04,7c80, ) to (
> > >>> 0xff,, )?  Maybe that would just quiet the pointless faults
> > >>> while leaving the IOMMU enabled?
> > >>
> > >> While they may quieten the faults, I don't think those faults are
> > >> pointless. They indicate some problem with the software (less
> > >> likely the hardware, possibly the firmware) that you're using.
> > >> Also there's the question of what the overall behavior is going
> > >> to be when devices are permitted to access unpopulated address
> > >> ranges. I assume you did check already that no devices have their
> > >> BARs placed in that range?
> > >
> > > Isn't no-igfx already letting them try to read those unpopulated 
> > > addresses?
> >
> > Yes, and it is for the reason that the documentation for the
> > option says "If specifying `no-igfx` fixes anything, please
> > report the problem." I imply from in in particular that one
> > better wouldn't use it for non-development purposes of whatever
> > kind.
> 
> I stopped seeing these DMA faults, but I didn't know what made them go
> away.  Then when working with an older 5.4.64 kernel, I saw them
> again.  Eric bisected down to the 5.4.y version of mainline linux
> commit:
> 
> commit 8195400f7ea95399f721ad21f4d663a62c65036f
> Author: Chris Wilson 
> Date:   Mon Oct 19 11:15:23 2020 +0100
> 
> drm/i915: Force VT'd workarounds when running as a guest OS
> 
> If i915.ko is being used as a passthrough device, it does not know if
> the host is using intel_iommu. Mixing the iommu and gfx causes a few
> issues (such as scanout overfetch) which we need to workaround inside
> the driver, so if we detect we are running under a hypervisor, also
> assume the device access is being virtualised.

So the commit above fixes the DMA faults seen on Linux when using a
i915 gfx card?

Thanks for digging into this.

Roger.
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/compat: more dummy implementations

[Patchwork]

== Series Details ==

Series: drm/compat: more dummy implementations
URL   : https://patchwork.freedesktop.org/series/87280/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9793_full -> Patchwork_19712_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19712_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@display-4x:
- shard-glk:  NOTRUN -> [SKIP][1] ([fdo#109271])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-glk2/igt@feature_discov...@display-4x.html
- shard-iclb: NOTRUN -> [SKIP][2] ([i915#1839])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-iclb6/igt@feature_discov...@display-4x.html

  * igt@gem_ctx_persistence@engines-hostile-preempt:
- shard-snb:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1 
similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-snb2/igt@gem_ctx_persiste...@engines-hostile-preempt.html

  * igt@gem_ctx_shared@q-in-order:
- shard-snb:  NOTRUN -> [SKIP][4] ([fdo#109271]) +194 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-snb2/igt@gem_ctx_sha...@q-in-order.html

  * igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: [PASS][5] -> [TIMEOUT][6] ([i915#3063])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-tglb5/igt@gem_...@in-flight-contexts-immediate.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-tglb2/igt@gem_...@in-flight-contexts-immediate.html

  * igt@gem_exec_balancer@hang:
- shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([i915#1895] / 
[i915#3031])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-iclb6/igt@gem_exec_balan...@hang.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-iclb1/igt@gem_exec_balan...@hang.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-tglb5/igt@gem_exec_fair@basic-f...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-tglb2/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-iclb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-iclb2/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2849])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_reloc@basic-many-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][16] ([i915#2389])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-iclb4/igt@gem_exec_reloc@basic-many-act...@vcs1.html

  * igt@gem_exec_reloc@basic-wide-active@rcs0:
- shard-kbl:  NOTRUN -> [FAIL][17] ([i915#2389]) +4 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-kbl1/igt@gem_exec_reloc@basic-wide-act...@rcs0.html

  * igt@gem_exec_schedule@u-fairslice-all:
- shard-tglb: [PASS][18] -> [DMESG-WARN][19] ([i915#2803])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-tglb1/igt@gem_exec_sched...@u-fairslice-all.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-tglb1/igt@gem_exec_sched...@u-fairslice-all.html

  * igt@gem_huc_copy@huc-copy:
- shard-glk:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#2190])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-glk2/igt@gem_huc_c...@huc-copy.html
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#2190])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-iclb6/igt@gem_huc_c...@huc-copy.html

  * igt@gem_pread@exhaustion:
- shard-kbl:  NOTRUN -> [WARN][22] ([i915#2658])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-kbl7/igt@gem_pr...@exhaustion.html
- shard-skl:  NOTRUN -> [WARN][23] ([i915#2658])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19712/shard-skl5/igt@gem_pr...@exhaustion.html

  * igt@gem_userptr_blits@input-checking:
- shard-apl:

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/compat: Clear bounce structures

[Patchwork]

== Series Details ==

Series: drm/compat: Clear bounce structures
URL   : https://patchwork.freedesktop.org/series/87281/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9793_full -> Patchwork_19713_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19713_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@display-4x:
- shard-glk:  NOTRUN -> [SKIP][1] ([fdo#109271])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-glk2/igt@feature_discov...@display-4x.html
- shard-iclb: NOTRUN -> [SKIP][2] ([i915#1839])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-iclb3/igt@feature_discov...@display-4x.html

  * igt@gem_ctx_persistence@process:
- shard-snb:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1 
similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-snb7/igt@gem_ctx_persiste...@process.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][4] ([i915#2846])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-apl7/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-kbl:  [PASS][5] -> [FAIL][6] ([i915#2842])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-kbl1/igt@gem_exec_fair@basic-none-r...@rcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-kbl2/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-kbl:  NOTRUN -> [FAIL][7] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-kbl6/igt@gem_exec_fair@basic-none-sh...@rcs0.html
- shard-iclb: [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-iclb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-iclb2/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none@vecs0:
- shard-apl:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-apl7/igt@gem_exec_fair@basic-n...@vecs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-apl6/igt@gem_exec_fair@basic-n...@vecs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-tglb2/igt@gem_exec_fair@basic-p...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-tglb2/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_reloc@basic-wide-active@rcs0:
- shard-snb:  NOTRUN -> [FAIL][14] ([i915#2389]) +5 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-snb7/igt@gem_exec_reloc@basic-wide-act...@rcs0.html

  * igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][15] ([i915#2389])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-iclb1/igt@gem_exec_reloc@basic-wide-act...@vcs1.html

  * igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-apl:  [PASS][16] -> [DMESG-WARN][17] ([i915#1610])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-apl1/igt@gem_exec_schedule@u-fairsl...@rcs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-apl2/igt@gem_exec_schedule@u-fairsl...@rcs0.html

  * igt@gem_huc_copy@huc-copy:
- shard-glk:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#2190])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-glk2/igt@gem_huc_c...@huc-copy.html
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#2190])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-iclb3/igt@gem_huc_c...@huc-copy.html

  * igt@gem_pread@exhaustion:
- shard-skl:  NOTRUN -> [WARN][20] ([i915#2658])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-skl1/igt@gem_pr...@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-kbl:  NOTRUN -> [WARN][21] ([i915#2658]) +1 similar issue
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-kbl6/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_userptr_blits@input-checking:
- shard-apl:  NOTRUN -> [DMESG-WARN][22] ([i915#3002]) +1 similar 
issue
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-apl8/igt@gem_userptr_bl...@input-checking.html
- shard-kbl:  NOTRUN -> [DMESG-WARN][23] ([i915#3002])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19713/shard-kbl7/igt@gem_userptr_bl...@input-checking.html

  * igt@

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Do not allow DC3CO if PSR SF is enabled

[Patchwork]

== Series Details ==

Series: drm/i915/display: Do not allow DC3CO if PSR SF is enabled
URL   : https://patchwork.freedesktop.org/series/87283/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9793_full -> Patchwork_19714_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_19714_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19714_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19714_full:

### IGT changes ###

 Warnings 

  * igt@runner@aborted:
- shard-apl:  ([FAIL][1], [FAIL][2]) ([i915#2724]) -> ([FAIL][3], 
[FAIL][4], [FAIL][5], [FAIL][6]) ([i915#2724] / [i915#3002])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-apl1/igt@run...@aborted.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-apl2/igt@run...@aborted.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/shard-apl6/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/shard-apl8/igt@run...@aborted.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/shard-apl1/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/shard-apl3/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_19714_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@display-4x:
- shard-glk:  NOTRUN -> [SKIP][7] ([fdo#109271])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/shard-glk3/igt@feature_discov...@display-4x.html
- shard-iclb: NOTRUN -> [SKIP][8] ([i915#1839])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/shard-iclb5/igt@feature_discov...@display-4x.html

  * igt@gem_ctx_persistence@process:
- shard-snb:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099]) +1 
similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/shard-snb5/igt@gem_ctx_persiste...@process.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][10] ([i915#2846])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/shard-apl3/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-apl:  [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-apl7/igt@gem_exec_fair@basic-n...@vcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/shard-apl2/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl:  [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar 
issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-tglb2/igt@gem_exec_fair@basic-p...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/shard-tglb7/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl:  [PASS][17] -> [SKIP][18] ([fdo#109271])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs1.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][19] -> [FAIL][20] ([i915#2849])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-snb:  NOTRUN -> [FAIL][21] ([i915#2389]) +2 similar issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/shard-snb2/igt@gem_exec_reloc@basic-many-act...@rcs0.html

  * igt@gem_exec_reloc@basic-wide-active@rcs0:
- shard-kbl:  NOTRUN -> [FAIL][22] ([i915#2389]) +4 similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19714/shard-kbl1/igt@gem_exec_reloc@basic-wide-act...@rcs0.html

  * igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#2803])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-tglb3/igt@gem_exec_schedule@u-fairsl...@rcs

[Intel-gfx] ✓ Fi.CI.IGT: success for drivers: gnu: drm: i915: gvt: Fixed couple of spellings in the file gtt.c

[Patchwork]

== Series Details ==

Series: drivers: gnu: drm: i915: gvt: Fixed couple of spellings in the file 
gtt.c
URL   : https://patchwork.freedesktop.org/series/87286/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9793_full -> Patchwork_19715_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19715_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@api_intel_bb@render-ccs:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2] ([i915#2588])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-tglb5/igt@api_intel...@render-ccs.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/shard-tglb8/igt@api_intel...@render-ccs.html

  * igt@feature_discovery@display-4x:
- shard-glk:  NOTRUN -> [SKIP][3] ([fdo#109271])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/shard-glk2/igt@feature_discov...@display-4x.html

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-skl:  [PASS][4] -> [INCOMPLETE][5] ([i915#198])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-skl4/igt@gem_ctx_isolation@preservation...@vecs0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/shard-skl6/igt@gem_ctx_isolation@preservation...@vecs0.html

  * igt@gem_ctx_persistence@close-replace-race:
- shard-kbl:  [PASS][6] -> [TIMEOUT][7] ([i915#2918])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-kbl1/igt@gem_ctx_persiste...@close-replace-race.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/shard-kbl2/igt@gem_ctx_persiste...@close-replace-race.html

  * igt@gem_ctx_persistence@engines-persistence:
- shard-snb:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) +3 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/shard-snb7/igt@gem_ctx_persiste...@engines-persistence.html

  * igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
- shard-hsw:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/shard-hsw1/igt@gem_ctx_persiste...@legacy-engines-hostile-preempt.html

  * igt@gem_eio@in-flight-suspend:
- shard-apl:  NOTRUN -> [DMESG-WARN][10] ([i915#180])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/shard-apl1/igt@gem_...@in-flight-suspend.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-iclb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/shard-iclb4/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl:  [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar 
issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-kbl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-tglb2/igt@gem_exec_fair@basic-p...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/shard-tglb2/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][17] ([i915#2842])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][18] -> [FAIL][19] ([i915#2849])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9793/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/shard-iclb2/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_reloc@basic-many-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][20] ([i915#2389])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/shard-iclb1/igt@gem_exec_reloc@basic-many-act...@vcs1.html

  * igt@gem_exec_reloc@basic-wide-active@rcs0:
- shard-snb:  NOTRUN -> [FAIL][21] ([i915#2389]) +5 similar issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/shard-snb6/igt@gem_exec_reloc@basic-wide-act...@rcs0.html
- shard-kbl:  NOTRUN -> [FAIL][22] ([i915#2389]) +4 similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19715/shard-kbl2/igt@gem_exec_reloc@basic-wide-act...@rcs0.html

  * igt@gem_exec_whisper@basic-normal-all:
- shard-glk:  [PASS][23] -> [DMESG-WARN][24] ([i915#118] / 
[i915#95]) +1 s

Re: [Intel-gfx] [PATCH v3 5/9] drm/i915/reg: add stream splitter configuration definitions

[Jani Nikula]

On Mon, 22 Feb 2021, "Shankar, Uma"  wrote:
>> -Original Message-
>> From: Intel-gfx  On Behalf Of Jani 
>> Nikula
>> Sent: Thursday, February 11, 2021 8:22 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; Varide, Nischal 
>> 
>> Subject: [Intel-gfx] [PATCH v3 5/9] drm/i915/reg: add stream splitter 
>> configuration
>> definitions
>> 
>> The splitter configuration is required for eDP MSO.
>
> Looks Good to me.
> Reviewed-by: Uma Shankar 

Thanks for the review, pushed up to and including this patch.

BR,
Jani.

>
>> Bspec: 50174
>> Cc: Nischal Varide 
>> Signed-off-by: Jani Nikula 
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>>  1 file changed, 3 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 224ad897af34..e5dd0203991b 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -11448,6 +11448,9 @@ enum skl_power_gate {
>>  #define  BIG_JOINER_ENABLE  (1 << 29)
>>  #define  MASTER_BIG_JOINER_ENABLE   (1 << 28)
>>  #define  VGA_CENTERING_ENABLE   (1 << 27)
>> +#define  SPLITTER_CONFIGURATION_MASKREG_GENMASK(26, 25)
>> +#define  SPLITTER_CONFIGURATION_2_SEGMENT
>>  REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
>> +#define  SPLITTER_CONFIGURATION_4_SEGMENT
>>  REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
>> 
>>  #define _ICL_PIPE_DSS_CTL2_PB   0x78204
>>  #define _ICL_PIPE_DSS_CTL2_PC   0x78404
>> --
>> 2.20.1
>> 
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v3 6/9] drm/i915/mso: add splitter state readout for platforms that support it

[Jani Nikula]

On Mon, 22 Feb 2021, "Shankar, Uma"  wrote:
>> -Original Message-
>> From: Intel-gfx  On Behalf Of Jani 
>> Nikula
>> Sent: Thursday, February 11, 2021 8:22 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; Varide, Nischal 
>> 
>> Subject: [Intel-gfx] [PATCH v3 6/9] drm/i915/mso: add splitter state readout 
>> for
>> platforms that support it
>> 
>> Add splitter configuration to crtc state, and read it where supported. Also 
>> add
>> splitter state dumping. The stream splitter will be required for eDP MSO.
>> 
>> v3:
>> - Convert segment timings to full panel timings.
>> - Refer to splitter instead of mso in crtc state.
>> - Dump splitter state.
>> 
>> v2: Add warning for mso being enabled on pipes other than A.
>> 
>> Cc: Nischal Varide 
>> Signed-off-by: Jani Nikula 
>> ---
>>  drivers/gpu/drm/i915/display/intel_ddi.c  | 37 +++
>>  drivers/gpu/drm/i915/display/intel_display.c  | 31 +++-
>>  .../drm/i915/display/intel_display_types.h|  7 
>>  drivers/gpu/drm/i915/i915_drv.h   |  2 +
>>  4 files changed, 75 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>> b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index 3c4003605f93..c9098297b6ac 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -2132,6 +2132,41 @@ static void intel_ddi_power_up_lanes(struct
>> intel_encoder *encoder,
>>  }
>>  }
>> 
>> +static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
>> + struct intel_crtc_state *pipe_config) {
>> +struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>> +struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> +enum pipe pipe = crtc->pipe;
>> +u32 dss1;
>> +
>> +if (!HAS_MSO(i915))
>> +return;
>> +
>> +dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
>> +
>> +pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
>> +if (!pipe_config->splitter.enable)
>> +return;
>> +
>> +/* Splitter enable is supported for pipe A only. */
>> +if (drm_WARN_ON(&i915->drm, pipe != PIPE_A)) {
>> +pipe_config->splitter.enable = false;
>> +return;
>> +}
>> +
>> +switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
>> +case SPLITTER_CONFIGURATION_2_SEGMENT:
>> +pipe_config->splitter.link_count = 2;
>> +break;
>> +case SPLITTER_CONFIGURATION_4_SEGMENT:
>> +pipe_config->splitter.link_count = 4;
>> +break;
>
> Should we have a default case as well just for sanity along with a WARN, 
> since it's very
> unlikely that it gets hit.

Ok.

>
>> +}
>> +
>> +pipe_config->splitter.pixel_overlap =
>> +REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); }
>> +
>>  static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>>struct intel_encoder *encoder,
>>const struct intel_crtc_state *crtc_state, @@ 
>> -
>> 3322,6 +3357,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>>  intel_ddi_read_func_ctl(encoder, pipe_config);
>>  }
>> 
>> +intel_ddi_mso_get_config(encoder, pipe_config);
>> +
>>  pipe_config->has_audio =
>>  intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index beed08c00b6c..fe9985bd5786 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -4856,8 +4856,30 @@ static void intel_crtc_readout_derived_state(struct
>> intel_crtc_state *crtc_state
>>  pipe_mode->crtc_clock /= 2;
>>  }
>> 
>> -intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
>> -intel_mode_from_crtc_timings(adjusted_mode, adjusted_mode);
>> +if (crtc_state->splitter.enable) {
>
> We can just add an else if case to if (crtc_state->bigjoiner) {
>
> if (crtc_state->bigjoiner) {
> ...
> } else if (crtc_state->splitter.enable) {
> ...
> }
>
>> +int n = crtc_state->splitter.link_count;
>> +int overlap = crtc_state->splitter.pixel_overlap;
>> +
>> +/*
>> + * eDP MSO uses segment timings from EDID for transcoder
>> + * timings, but full mode for everything else.
>> + *
>> + * h_full = (h_segment - pixel_overlap) * link_count
>> + */
>> +pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) 
>> *
>> n;
>> +pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start -
>> overlap) * n;
>> +pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end -
>> overlap) * n;
>> +pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start -
>> overlap) * n;
>> +pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_

Re: [Intel-gfx] [PATCH v3 6/9] drm/i915/mso: add splitter state readout for platforms that support it

[Shankar, Uma]

> -Original Message-
> From: Nikula, Jani 
> Sent: Monday, February 22, 2021 10:25 PM
> To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
> Cc: Varide, Nischal 
> Subject: RE: [Intel-gfx] [PATCH v3 6/9] drm/i915/mso: add splitter state 
> readout for
> platforms that support it
> 
> On Mon, 22 Feb 2021, "Shankar, Uma"  wrote:
> >> -Original Message-
> >> From: Intel-gfx  On Behalf
> >> Of Jani Nikula
> >> Sent: Thursday, February 11, 2021 8:22 PM
> >> To: intel-gfx@lists.freedesktop.org
> >> Cc: Nikula, Jani ; Varide, Nischal
> >> 
> >> Subject: [Intel-gfx] [PATCH v3 6/9] drm/i915/mso: add splitter state
> >> readout for platforms that support it
> >>
> >> Add splitter configuration to crtc state, and read it where
> >> supported. Also add splitter state dumping. The stream splitter will be 
> >> required for
> eDP MSO.
> >>
> >> v3:
> >> - Convert segment timings to full panel timings.
> >> - Refer to splitter instead of mso in crtc state.
> >> - Dump splitter state.
> >>
> >> v2: Add warning for mso being enabled on pipes other than A.
> >>
> >> Cc: Nischal Varide 
> >> Signed-off-by: Jani Nikula 
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_ddi.c  | 37 +++
> >>  drivers/gpu/drm/i915/display/intel_display.c  | 31 +++-
> >>  .../drm/i915/display/intel_display_types.h|  7 
> >>  drivers/gpu/drm/i915/i915_drv.h   |  2 +
> >>  4 files changed, 75 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> index 3c4003605f93..c9098297b6ac 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> @@ -2132,6 +2132,41 @@ static void intel_ddi_power_up_lanes(struct
> >> intel_encoder *encoder,
> >>}
> >>  }
> >>
> >> +static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
> >> +   struct intel_crtc_state *pipe_config) {
> >> +  struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> >> +  struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> >> +  enum pipe pipe = crtc->pipe;
> >> +  u32 dss1;
> >> +
> >> +  if (!HAS_MSO(i915))
> >> +  return;
> >> +
> >> +  dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
> >> +
> >> +  pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
> >> +  if (!pipe_config->splitter.enable)
> >> +  return;
> >> +
> >> +  /* Splitter enable is supported for pipe A only. */
> >> +  if (drm_WARN_ON(&i915->drm, pipe != PIPE_A)) {
> >> +  pipe_config->splitter.enable = false;
> >> +  return;
> >> +  }
> >> +
> >> +  switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
> >> +  case SPLITTER_CONFIGURATION_2_SEGMENT:
> >> +  pipe_config->splitter.link_count = 2;
> >> +  break;
> >> +  case SPLITTER_CONFIGURATION_4_SEGMENT:
> >> +  pipe_config->splitter.link_count = 4;
> >> +  break;
> >
> > Should we have a default case as well just for sanity along with a
> > WARN, since it's very unlikely that it gets hit.
> 
> Ok.
> 
> >
> >> +  }
> >> +
> >> +  pipe_config->splitter.pixel_overlap =
> >> +REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); }
> >> +
> >>  static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> >>  struct intel_encoder *encoder,
> >>  const struct intel_crtc_state *crtc_state, @@ 
> >> -
> >> 3322,6 +3357,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> >>intel_ddi_read_func_ctl(encoder, pipe_config);
> >>}
> >>
> >> +  intel_ddi_mso_get_config(encoder, pipe_config);
> >> +
> >>pipe_config->has_audio =
> >>intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> >> b/drivers/gpu/drm/i915/display/intel_display.c
> >> index beed08c00b6c..fe9985bd5786 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -4856,8 +4856,30 @@ static void
> >> intel_crtc_readout_derived_state(struct
> >> intel_crtc_state *crtc_state
> >>pipe_mode->crtc_clock /= 2;
> >>}
> >>
> >> -  intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
> >> -  intel_mode_from_crtc_timings(adjusted_mode, adjusted_mode);
> >> +  if (crtc_state->splitter.enable) {
> >
> > We can just add an else if case to if (crtc_state->bigjoiner) {
> >
> > if (crtc_state->bigjoiner) {
> > ...
> > } else if (crtc_state->splitter.enable) { ...
> > }
> >
> >> +  int n = crtc_state->splitter.link_count;
> >> +  int overlap = crtc_state->splitter.pixel_overlap;
> >> +
> >> +  /*
> >> +   * eDP MSO uses segment timings from EDID for transcoder
> >> +   * timings, but full mode for everything else.
> >> +   *
> >> +   * h_full = (h_segment - pixel_overlap) * link_count
> >> +   */
> 

Re: [Intel-gfx] [PATCH 01/12] drm/i915/bios: mass convert dev_priv to i915

[Ville Syrjälä]

On Wed, Feb 17, 2021 at 07:03:31PM +0200, Jani Nikula wrote:
> Time to just yank out the bandage. No functional changes.
> 
> Cc: Lucas De Marchi 
> Cc: Ville Syrjälä 
> Signed-off-by: Jani Nikula 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 766 +++---
>  1 file changed, 383 insertions(+), 383 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 7902d4c2673e..802c228b2940 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -211,7 +211,7 @@ get_lvds_fp_timing(const struct bdb_header *bdb,
>  
>  /* Parse general panel options */
>  static void
> -parse_panel_options(struct drm_i915_private *dev_priv,
> +parse_panel_options(struct drm_i915_private *i915,
>   const struct bdb_header *bdb)
>  {
>   const struct bdb_lvds_options *lvds_options;
> @@ -223,27 +223,27 @@ parse_panel_options(struct drm_i915_private *dev_priv,
>   if (!lvds_options)
>   return;
>  
> - dev_priv->vbt.lvds_dither = lvds_options->pixel_dither;
> + i915->vbt.lvds_dither = lvds_options->pixel_dither;
>  
> - ret = intel_opregion_get_panel_type(dev_priv);
> + ret = intel_opregion_get_panel_type(i915);
>   if (ret >= 0) {
> - drm_WARN_ON(&dev_priv->drm, ret > 0xf);
> + drm_WARN_ON(&i915->drm, ret > 0xf);
>   panel_type = ret;
> - drm_dbg_kms(&dev_priv->drm, "Panel type: %d (OpRegion)\n",
> + drm_dbg_kms(&i915->drm, "Panel type: %d (OpRegion)\n",
>   panel_type);
>   } else {
>   if (lvds_options->panel_type > 0xf) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(&i915->drm,
>   "Invalid VBT panel type 0x%x\n",
>   lvds_options->panel_type);
>   return;
>   }
>   panel_type = lvds_options->panel_type;
> - drm_dbg_kms(&dev_priv->drm, "Panel type: %d (VBT)\n",
> + drm_dbg_kms(&i915->drm, "Panel type: %d (VBT)\n",
>   panel_type);
>   }
>  
> - dev_priv->vbt.panel_type = panel_type;
> + i915->vbt.panel_type = panel_type;
>  
>   drrs_mode = (lvds_options->dps_panel_type_bits
>   >> (panel_type * 2)) & MODE_MASK;
> @@ -254,17 +254,17 @@ parse_panel_options(struct drm_i915_private *dev_priv,
>*/
>   switch (drrs_mode) {
>   case 0:
> - dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT;
> - drm_dbg_kms(&dev_priv->drm, "DRRS supported mode is static\n");
> + i915->vbt.drrs_type = STATIC_DRRS_SUPPORT;
> + drm_dbg_kms(&i915->drm, "DRRS supported mode is static\n");
>   break;
>   case 2:
> - dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT;
> - drm_dbg_kms(&dev_priv->drm,
> + i915->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT;
> + drm_dbg_kms(&i915->drm,
>   "DRRS supported mode is seamless\n");
>   break;
>   default:
> - dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> - drm_dbg_kms(&dev_priv->drm,
> + i915->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> + drm_dbg_kms(&i915->drm,
>   "DRRS not supported (VBT input)\n");
>   break;
>   }
> @@ -272,7 +272,7 @@ parse_panel_options(struct drm_i915_private *dev_priv,
>  
>  /* Try to find integrated panel timing data */
>  static void
> -parse_lfp_panel_dtd(struct drm_i915_private *dev_priv,
> +parse_lfp_panel_dtd(struct drm_i915_private *i915,
>   const struct bdb_header *bdb)
>  {
>   const struct bdb_lvds_lfp_data *lvds_lfp_data;
> @@ -280,7 +280,7 @@ parse_lfp_panel_dtd(struct drm_i915_private *dev_priv,
>   const struct lvds_dvo_timing *panel_dvo_timing;
>   const struct lvds_fp_timing *fp_timing;
>   struct drm_display_mode *panel_fixed_mode;
> - int panel_type = dev_priv->vbt.panel_type;
> + int panel_type = i915->vbt.panel_type;
>  
>   lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
>   if (!lvds_lfp_data)
> @@ -300,9 +300,9 @@ parse_lfp_panel_dtd(struct drm_i915_private *dev_priv,
>  
>   fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
>  
> - dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
> + i915->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
>  
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(&i915->drm,
>   "Found panel mode in BIOS VBT legacy lfp table:\n");
>   drm_mode_debug_printmodeline(panel_fixed_mode);
>  
> @@ -313,16 +313,16 @@ parse_lfp_panel_dtd(struct drm_i915_private *dev_priv,
>   /* check the resolution, just to be sure */
>   if (fp_timin

Re: [Intel-gfx] [PATCH 02/12] drm/i915/bios: store bdb version in i915

[Ville Syrjälä]

On Wed, Feb 17, 2021 at 07:03:32PM +0200, Jani Nikula wrote:
> We'll be needing the version in more places in the future, so avoid the
> need to pass it around. No functional changes.
> 
> Cc: Lucas De Marchi 
> Cc: Ville Syrjälä 
> Signed-off-by: Jani Nikula 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 28 +++
>  drivers/gpu/drm/i915/i915_drv.h   |  3 +++
>  2 files changed, 17 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 802c228b2940..a8712fe8bf3e 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -597,7 +597,7 @@ child_device_ptr(const struct bdb_general_definitions 
> *defs, int i)
>  }
>  
>  static void
> -parse_sdvo_device_mapping(struct drm_i915_private *i915, u8 bdb_version)
> +parse_sdvo_device_mapping(struct drm_i915_private *i915)
>  {
>   struct sdvo_device_mapping *mapping;
>   const struct display_device_data *devdata;
> @@ -1760,8 +1760,7 @@ static enum port dvo_port_to_port(struct 
> drm_i915_private *i915,
>  }
>  
>  static void parse_ddi_port(struct drm_i915_private *i915,
> -struct display_device_data *devdata,
> -u8 bdb_version)
> +struct display_device_data *devdata)
>  {
>   const struct child_device_config *child = &devdata->child;
>   struct ddi_vbt_port_info *info;
> @@ -1800,10 +1799,10 @@ static void parse_ddi_port(struct drm_i915_private 
> *i915,
>   info->supports_dp = is_dp;
>   info->supports_edp = is_edp;
>  
> - if (bdb_version >= 195)
> + if (i915->vbt.version >= 195)
>   info->supports_typec_usb = child->dp_usb_type_c;
>  
> - if (bdb_version >= 209)
> + if (i915->vbt.version >= 209)
>   info->supports_tbt = child->tbt;
>  
>   drm_dbg_kms(&i915->drm,
> @@ -1834,7 +1833,7 @@ static void parse_ddi_port(struct drm_i915_private 
> *i915,
>   sanitize_aux_ch(i915, port);
>   }
>  
> - if (bdb_version >= 158) {
> + if (i915->vbt.version >= 158) {
>   /* The VBT HDMI level shift values match the table we have. */
>   u8 hdmi_level_shift = child->hdmi_level_shifter_value;
>   drm_dbg_kms(&i915->drm,
> @@ -1845,7 +1844,7 @@ static void parse_ddi_port(struct drm_i915_private 
> *i915,
>   info->hdmi_level_shift_set = true;
>   }
>  
> - if (bdb_version >= 204) {
> + if (i915->vbt.version >= 204) {
>   int max_tmds_clock;
>  
>   switch (child->hdmi_max_data_rate) {
> @@ -1871,7 +1870,7 @@ static void parse_ddi_port(struct drm_i915_private 
> *i915,
>   }
>  
>   /* Parse the I_boost config for SKL and above */
> - if (bdb_version >= 196 && child->iboost) {
> + if (i915->vbt.version >= 196 && child->iboost) {
>   info->dp_boost_level = translate_iboost(child->dp_iboost_level);
>   drm_dbg_kms(&i915->drm,
>   "Port %c VBT (e)DP boost level: %d\n",
> @@ -1883,7 +1882,7 @@ static void parse_ddi_port(struct drm_i915_private 
> *i915,
>   }
>  
>   /* DP max link rate for CNL+ */
> - if (bdb_version >= 216) {
> + if (i915->vbt.version >= 216) {
>   switch (child->dp_max_link_rate) {
>   default:
>   case VBT_DP_MAX_LINK_RATE_HBR3:
> @@ -1907,18 +1906,18 @@ static void parse_ddi_port(struct drm_i915_private 
> *i915,
>   info->child = child;
>  }
>  
> -static void parse_ddi_ports(struct drm_i915_private *i915, u8 bdb_version)
> +static void parse_ddi_ports(struct drm_i915_private *i915)
>  {
>   struct display_device_data *devdata;
>  
>   if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915))
>   return;
>  
> - if (bdb_version < 155)
> + if (i915->vbt.version < 155)
>   return;
>  
>   list_for_each_entry(devdata, &i915->vbt.display_devices, node)
> - parse_ddi_port(i915, devdata, bdb_version);
> + parse_ddi_port(i915, devdata);
>  }
>  
>  static void
> @@ -2229,6 +2228,7 @@ void intel_bios_init(struct drm_i915_private *i915)
>   }
>  
>   bdb = get_bdb_header(vbt);
> + i915->vbt.version = bdb->version;
>  
>   drm_dbg_kms(&i915->drm,
>   "VBT signature \"%.*s\", BDB version %d\n",
> @@ -2252,8 +2252,8 @@ void intel_bios_init(struct drm_i915_private *i915)
>   parse_compression_parameters(i915, bdb);
>  
>   /* Further processing on pre-parsed data */
> - parse_sdvo_device_mapping(i915, bdb->version);
> - parse_ddi_ports(i915, bdb->version);
> + parse_sdvo_device_mapping(i915);
> + parse_ddi_ports(i915);
>  
>  out:
>   if (!vbt) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f8413b3b9da8..62be1465f52b 100644
> --- a/drivers/gpu/drm/i915/

Re: [Intel-gfx] [PATCH 03/12] drm/i915/bios: limit default outputs by platform on missing VBT

[Ville Syrjälä]

On Wed, Feb 17, 2021 at 07:03:33PM +0200, Jani Nikula wrote:
> Pre-DDI and non-CHV aren't using the information created here anyway, so
> don't bother setting the defaults for them. This should be a
> non-functional change, but is separated here to catch any regressions in
> a single commit.
> 
> Cc: Lucas De Marchi 
> Cc: Ville Syrjälä 
> Signed-off-by: Jani Nikula 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index a8712fe8bf3e..e9cb15aa2f5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2058,6 +2058,9 @@ init_vbt_missing_defaults(struct drm_i915_private *i915)
>  {
>   enum port port;
>  
> + if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915))
> + return;
> +
>   for_each_port(port) {
>   struct ddi_vbt_port_info *info =
>   &i915->vbt.ddi_port_info[port];
> -- 
> 2.20.1

-- 
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH v2] drm/i915/display: Do not allow DC3CO if PSR SF is enabled

[Gwan-gyeong Mun]

Even though GEN12+ HW supports PSR + DC3CO, DMC's HW DC3CO exit mechanism
has an issue with using of Selective Fecth and PSR2 manual tracking.
And as some GEN12+ platforms (RKL, ADL-S) don't support PSR2 HW tracking,
Selective Fetch will be enabled by default on that platforms.
Therefore if the system enables PSR Selective Fetch / PSR manual tracking,
it does not allow DC3CO dc state, in that case.

When this DC3CO exit issue is addressed while PSR Selective Fetch is
enabled, this restriction should be removed.

Cc: José Roberto de Souza 
Cc: Anshuman Gupta 
Signed-off-by: Gwan-gyeong Mun 
---
 drivers/gpu/drm/i915/display/intel_psr.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 7c6e561f86c1..7370de97e599 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -654,6 +654,14 @@ tgl_dc3co_exitline_compute_config(struct intel_dp 
*intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 exit_scanlines;
 
+   /*
+* DMC's DC3CO exit mechanism has an issue with Selective Fecth
+* TODO: when the issue is addressed, this restriction should be 
removed.
+*/
+   if (dev_priv->params.enable_psr2_sel_fetch ||
+   intel_dp->psr.debug == I915_PSR_DEBUG_ENABLE_SEL_FETCH)
+   return;
+
if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
return;
 
-- 
2.30.0

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Re: [Intel-gfx] [PATCH v2] drm/i915/display: Do not allow DC3CO if PSR SF is enabled

[Souza, Jose]

On Mon, 2021-02-22 at 21:05 +0200, Gwan-gyeong Mun wrote:
> Even though GEN12+ HW supports PSR + DC3CO, DMC's HW DC3CO exit mechanism
> has an issue with using of Selective Fecth and PSR2 manual tracking.
> And as some GEN12+ platforms (RKL, ADL-S) don't support PSR2 HW tracking,
> Selective Fetch will be enabled by default on that platforms.
> Therefore if the system enables PSR Selective Fetch / PSR manual tracking,
> it does not allow DC3CO dc state, in that case.
> 
> When this DC3CO exit issue is addressed while PSR Selective Fetch is
> enabled, this restriction should be removed.
> 
> Cc: José Roberto de Souza 
> Cc: Anshuman Gupta 
> Signed-off-by: Gwan-gyeong Mun 
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7c6e561f86c1..7370de97e599 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -654,6 +654,14 @@ tgl_dc3co_exitline_compute_config(struct intel_dp 
> *intel_dp,
>   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>   u32 exit_scanlines;
>  
> 
> 
> 
> + /*
> +  * DMC's DC3CO exit mechanism has an issue with Selective Fecth
> +  * TODO: when the issue is addressed, this restriction should be 
> removed.
> +  */
> + if (dev_priv->params.enable_psr2_sel_fetch ||
> + intel_dp->psr.debug == I915_PSR_DEBUG_ENABLE_SEL_FETCH)
> + return;

crtc_state->enable_psr2_sel_fetch is a much better alternative.


> +
>   if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
>   return;
>  
> 
> 
> 

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Do not allow DC3CO if PSR SF is enabled (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Do not allow DC3CO if PSR SF is enabled (rev2)
URL   : https://patchwork.freedesktop.org/series/87283/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9795 -> Patchwork_19716


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/index.html

Known issues


  Here are the changes found in Patchwork_19716 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y:   [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar 
issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][3] ([fdo#109271]) +34 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html

  
 Possible fixes 

  * igt@gem_flink_basic@basic:
- fi-tgl-y:   [DMESG-WARN][5] ([i915#402]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/fi-tgl-y/igt@gem_flink_ba...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/fi-tgl-y/igt@gem_flink_ba...@basic.html

  * igt@i915_module_load@reload:
- fi-kbl-7500u:   [DMESG-WARN][7] ([i915#2605]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/fi-kbl-7500u/igt@i915_module_l...@reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/fi-kbl-7500u/igt@i915_module_l...@reload.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [FAIL][9] ([i915#2128]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2128]: https://gitlab.freedesktop.org/drm/intel/issues/2128
  [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (44 -> 41)
--

  Additional (1): fi-snb-2600 
  Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus fi-hsw-4200u 


Build changes
-

  * Linux: CI_DRM_9795 -> Patchwork_19716

  CI-20190529: 20190529
  CI_DRM_9795: 5f1072de87a90be6d0ba8f4e4cffdbbe13166f03 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6011: 8c8499c29dd2aa189c3d687e057ba4df326b1732 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19716: 55bfe3430c7926e85bc07128be74ff2658486251 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

55bfe3430c79 drm/i915/display: Do not allow DC3CO if PSR SF is enabled

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/index.html
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[Intel-gfx] [PATCH] drm/i915/tgl+: Sanitize the DDI LANES/IO and AUX power domain names

[Imre Deak]

In Bspec the TGL TypeC ports are TC1-6, the AUX power well request flags
are USBC1-6/TBT1-6, so for clarity use these names in the port power
domain names instead of the D-I terminology (which Bspec uses only for
the ICL TypeC ports).

No functional change.

Cc: Souza Jose 
Signed-off-by: Imre Deak 
---
 .../drm/i915/display/intel_display_power.c| 212 --
 .../drm/i915/display/intel_display_power.h|  32 +++
 2 files changed, 130 insertions(+), 114 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index f00c1750febd..7e0eaa872350 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2886,24 +2886,24 @@ intel_display_power_put_mask_in_set(struct 
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_PIPE_B) |  \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |\
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) |\
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_G_LANES) |\
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_H_LANES) |\
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_I_LANES) |\
-   BIT_ULL(POWER_DOMAIN_AUX_D) |   \
-   BIT_ULL(POWER_DOMAIN_AUX_E) |   \
-   BIT_ULL(POWER_DOMAIN_AUX_F) |   \
-   BIT_ULL(POWER_DOMAIN_AUX_G) |   \
-   BIT_ULL(POWER_DOMAIN_AUX_H) |   \
-   BIT_ULL(POWER_DOMAIN_AUX_I) |   \
-   BIT_ULL(POWER_DOMAIN_AUX_D_TBT) |   \
-   BIT_ULL(POWER_DOMAIN_AUX_E_TBT) |   \
-   BIT_ULL(POWER_DOMAIN_AUX_F_TBT) |   \
-   BIT_ULL(POWER_DOMAIN_AUX_G_TBT) |   \
-   BIT_ULL(POWER_DOMAIN_AUX_H_TBT) |   \
-   BIT_ULL(POWER_DOMAIN_AUX_I_TBT) |   \
+   BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) |  \
+   BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) |  \
+   BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) |  \
+   BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) |  \
+   BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) |  \
+   BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) |  \
+   BIT_ULL(POWER_DOMAIN_AUX_USBC1) |   \
+   BIT_ULL(POWER_DOMAIN_AUX_USBC2) |   \
+   BIT_ULL(POWER_DOMAIN_AUX_USBC3) |   \
+   BIT_ULL(POWER_DOMAIN_AUX_USBC4) |   \
+   BIT_ULL(POWER_DOMAIN_AUX_USBC5) |   \
+   BIT_ULL(POWER_DOMAIN_AUX_USBC6) |   \
+   BIT_ULL(POWER_DOMAIN_AUX_TBT1) |\
+   BIT_ULL(POWER_DOMAIN_AUX_TBT2) |\
+   BIT_ULL(POWER_DOMAIN_AUX_TBT3) |\
+   BIT_ULL(POWER_DOMAIN_AUX_TBT4) |\
+   BIT_ULL(POWER_DOMAIN_AUX_TBT5) |\
+   BIT_ULL(POWER_DOMAIN_AUX_TBT6) |\
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO) |   \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2921,18 +2921,12 @@ intel_display_power_put_mask_in_set(struct 
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_AUX_C) |   \
BIT_ULL(POWER_DOMAIN_INIT))
 
-#define TGL_DDI_IO_D_TC1_POWER_DOMAINS (   \
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
-#define TGL_DDI_IO_E_TC2_POWER_DOMAINS (   \
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
-#define TGL_DDI_IO_F_TC3_POWER_DOMAINS (   \
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
-#define TGL_DDI_IO_G_TC4_POWER_DOMAINS (   \
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_G_IO))
-#define TGL_DDI_IO_H_TC5_POWER_DOMAINS (   \
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_H_IO))
-#define TGL_DDI_IO_I_TC6_POWER_DOMAINS (   \
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_I_IO))
+#define TGL_DDI_IO_TC1_POWER_DOMAINS   BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
+#define TGL_DDI_IO_TC2_POWER_DOMAINS   BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
+#define TGL_DDI_IO_TC3_POWER_DOMAINS   BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
+#define TGL_DDI_IO_TC4_POWER_DOMAINS   BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
+#define TGL_DDI_IO_TC5_POWER_DOMAINS   BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC5)
+#define TGL_DDI_IO_TC6_POWER_DOMAINS   BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC6)
 
 #define TGL_AUX_A_IO_POWER_DOMAINS (   \
BIT_ULL(POWER_DOMAIN_AUX_IO_A) |\
@@ -2941,44 +2935,34 @@ intel_display_power_put_mask_in_set(struct 
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_AUX_B))
 #define TGL_AUX_C_IO_POWER_DOMAINS (   \
BIT_ULL(POWER_DOMAIN_AUX_C))
-#define TGL_AUX_D_TC1_IO_POWER_DOMAINS (   \
-   BIT_ULL(POWER_DOMAIN_AUX_D))
-#define TGL_AUX_E_TC2_IO_POWER_DOMAINS (   \
-   BIT_ULL(POWER_DOMAIN_AUX_E))
-#define TGL_A

[Intel-gfx] 2021 X.Org Board of Directors Elections Nomination period is NOW

[Harry Wentland]

We are seeking nominations for candidates for election to the X.Org 
Foundation Board of Directors. All X.Org Foundation members are eligible 
for election to the board.


Nominations for the 2021 election are now open and will remain open 
until Sunday, the 7th of March.


The Board consists of directors elected from the membership. Each year, 
an election is held to bring the total number of directors to eight. The 
four members receiving the highest vote totals will serve as directors 
for two year terms.


The directors who received two year terms starting in 2020 were Eric 
Anholt, Mark Filion, Keith Packard, and Harry Wentland. They will 
continue to serve until their term ends in 2022. Current directors whose 
term expires in 2021 are Samuel Iglesias Gonsálvez, Manasi D Navare, 
Lyude Paul, and Daniel Vetter.


A director is expected to participate in the fortnightly IRC meeting to 
discuss current business and to attend the annual meeting of the X.Org 
Foundation, which will be held at a location determined in advance by 
the Board of Directors.


A member may nominate themselves or any other member they feel is 
qualified. Nominations should be sent to the Election Committee at 
elections at x.org.


Nominees shall be required to be current members of the X.Org 
Foundation, and submit a personal statement of up to 200 words that will 
be provided to prospective voters. The collected statements, along with 
the statement of contribution to the X.Org Foundation in the member's 
account page on http://members.x.org, will be made available to all 
voters to help them make their voting decisions.


Nominations must be received before the end of day on Sunday, the 7th of 
March.


Membership applications or renewals and completed personal statements 
must be received no later than the end of day on Thursday, the 11tth of 
March.


The slate of candidates will be published on Monday, the 15th of March 
and candidate Q&A will begin then.


** Election Schedule **

Nomination period Start: Mon 22nd February
Nomination period End: Sun 7th March
Deadline of X.Org membership application or renewal: Thu 11th March
Publication of Candidates & start of Candidate QA: Mon 15th March
Election Planned Start: Mon 22nd March anywhere on earth
Election Planned End: Sun 4th April anywhere on earth

** Election Committee **

* Eric Anholt
* Mark Filion
* Keith Packard
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Cheers,
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on behalf of the X.Org elections committee
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[Intel-gfx] [PATCH v3] drm/i915/display: Do not allow DC3CO if PSR SF is enabled

[Gwan-gyeong Mun]

Even though GEN12+ HW supports PSR + DC3CO, DMC's HW DC3CO exit mechanism
has an issue with using of Selective Fecth and PSR2 manual tracking.
And as some GEN12+ platforms (RKL, ADL-S) don't support PSR2 HW tracking,
Selective Fetch will be enabled by default on that platforms.
Therefore if the system enables PSR Selective Fetch / PSR manual tracking,
it does not allow DC3CO dc state, in that case.

When this DC3CO exit issue is addressed while PSR Selective Fetch is
enabled, this restriction should be removed.

v2: Address Jose's review comment.
  - Fix typo
  - Move check routine of DC3CO ability to
tgl_dc3co_exitline_compute_config()
v3: Change the check routine of enablement of psr2 sel fetch. (Jose)

Cc: José Roberto de Souza 
Cc: Anshuman Gupta 
Signed-off-by: Gwan-gyeong Mun 
---
 drivers/gpu/drm/i915/display/intel_psr.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 7c6e561f86c1..cd434285e3b7 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -654,6 +654,13 @@ tgl_dc3co_exitline_compute_config(struct intel_dp 
*intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 exit_scanlines;
 
+   /*
+* DMC's DC3CO exit mechanism has an issue with Selective Fecth
+* TODO: when the issue is addressed, this restriction should be 
removed.
+*/
+   if (crtc_state->enable_psr2_sel_fetch)
+   return;
+
if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
return;
 
-- 
2.30.0

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Re: [Intel-gfx] [PATCH v3] drm/i915/display: Do not allow DC3CO if PSR SF is enabled

[Souza, Jose]

On Mon, 2021-02-22 at 23:30 +0200, Gwan-gyeong Mun wrote:
> Even though GEN12+ HW supports PSR + DC3CO, DMC's HW DC3CO exit mechanism
> has an issue with using of Selective Fecth and PSR2 manual tracking.
> And as some GEN12+ platforms (RKL, ADL-S) don't support PSR2 HW tracking,
> Selective Fetch will be enabled by default on that platforms.
> Therefore if the system enables PSR Selective Fetch / PSR manual tracking,
> it does not allow DC3CO dc state, in that case.
> 
> When this DC3CO exit issue is addressed while PSR Selective Fetch is
> enabled, this restriction should be removed.
> 
> v2: Address Jose's review comment.
>   - Fix typo
>   - Move check routine of DC3CO ability to
> tgl_dc3co_exitline_compute_config()
> v3: Change the check routine of enablement of psr2 sel fetch. (Jose)

Reviewed-by: José Roberto de Souza 

> 
> Cc: José Roberto de Souza 
> Cc: Anshuman Gupta 
> Signed-off-by: Gwan-gyeong Mun 
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7c6e561f86c1..cd434285e3b7 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -654,6 +654,13 @@ tgl_dc3co_exitline_compute_config(struct intel_dp 
> *intel_dp,
>   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>   u32 exit_scanlines;
>  
> 
> 
> 
> + /*
> +  * DMC's DC3CO exit mechanism has an issue with Selective Fecth
> +  * TODO: when the issue is addressed, this restriction should be 
> removed.
> +  */
> + if (crtc_state->enable_psr2_sel_fetch)
> + return;
> +
>   if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
>   return;
>  
> 
> 
> 

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl+: Sanitize the DDI LANES/IO and AUX power domain names

[Patchwork]

== Series Details ==

Series: drm/i915/tgl+: Sanitize the DDI LANES/IO and AUX power domain names
URL   : https://patchwork.freedesktop.org/series/87299/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9795 -> Patchwork_19717


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/index.html

Known issues


  Here are the changes found in Patchwork_19717 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_mmap_gtt@basic:
- fi-tgl-y:   [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar 
issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/fi-tgl-y/igt@gem_mmap_...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/fi-tgl-y/igt@gem_mmap_...@basic.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][3] ([fdo#109271]) +34 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html

  
 Possible fixes 

  * igt@gem_flink_basic@basic:
- fi-tgl-y:   [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +1 similar 
issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/fi-tgl-y/igt@gem_flink_ba...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/fi-tgl-y/igt@gem_flink_ba...@basic.html

  * igt@i915_module_load@reload:
- fi-kbl-7500u:   [DMESG-WARN][7] ([i915#2605]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/fi-kbl-7500u/igt@i915_module_l...@reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/fi-kbl-7500u/igt@i915_module_l...@reload.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [FAIL][9] ([i915#2128]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2128]: https://gitlab.freedesktop.org/drm/intel/issues/2128
  [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (44 -> 41)
--

  Additional (1): fi-snb-2600 
  Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus fi-hsw-4200u 


Build changes
-

  * Linux: CI_DRM_9795 -> Patchwork_19717

  CI-20190529: 20190529
  CI_DRM_9795: 5f1072de87a90be6d0ba8f4e4cffdbbe13166f03 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6011: 8c8499c29dd2aa189c3d687e057ba4df326b1732 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19717: ce01ee7c643ef06a2951fba4cbbbf7622c0f3772 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ce01ee7c643e drm/i915/tgl+: Sanitize the DDI LANES/IO and AUX power domain names

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Do not allow DC3CO if PSR SF is enabled (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Do not allow DC3CO if PSR SF is enabled (rev2)
URL   : https://patchwork.freedesktop.org/series/87283/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9795_full -> Patchwork_19716_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_19716_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19716_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19716_full:

### IGT changes ###

 Warnings 

  * igt@runner@aborted:
- shard-apl:  ([FAIL][1], [FAIL][2], [FAIL][3]) ([i915#3002]) -> 
([FAIL][4], [FAIL][5], [FAIL][6], [FAIL][7]) ([fdo#109271] / [i915#1610] / 
[i915#2426] / [i915#2724] / [i915#716])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-apl1/igt@run...@aborted.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-apl1/igt@run...@aborted.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-apl3/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/shard-apl7/igt@run...@aborted.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/shard-apl6/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/shard-apl6/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/shard-apl1/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_19716_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_mm@all@replace:
- shard-skl:  [PASS][8] -> [INCOMPLETE][9] ([i915#2485])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-skl1/igt@drm_mm@a...@replace.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/shard-skl6/igt@drm_mm@a...@replace.html

  * igt@feature_discovery@psr2:
- shard-iclb: [PASS][10] -> [SKIP][11] ([i915#658])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-iclb2/igt@feature_discov...@psr2.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/shard-iclb5/igt@feature_discov...@psr2.html

  * igt@gem_create@create-massive:
- shard-kbl:  NOTRUN -> [DMESG-WARN][12] ([i915#3002])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/shard-kbl1/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099]) +5 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-mixed.html

  * igt@gem_exec_balancer@hang:
- shard-iclb: [PASS][14] -> [INCOMPLETE][15] ([i915#1895] / 
[i915#3031])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-iclb3/igt@gem_exec_balan...@hang.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/shard-iclb2/igt@gem_exec_balan...@hang.html

  * igt@gem_exec_create@forked:
- shard-glk:  [PASS][16] -> [DMESG-WARN][17] ([i915#118] / 
[i915#95])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-glk6/igt@gem_exec_cre...@forked.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/shard-glk6/igt@gem_exec_cre...@forked.html

  * igt@gem_exec_fair@basic-deadline:
- shard-kbl:  NOTRUN -> [FAIL][18] ([i915#2846])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/shard-kbl7/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk:  NOTRUN -> [FAIL][19] ([i915#2842])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/shard-glk9/igt@gem_exec_fair@basic-none-...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][20] -> [FAIL][21] ([i915#2842])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/shard-glk4/igt@gem_exec_fair@basic-throt...@rcs0.html
- shard-iclb: [PASS][22] -> [FAIL][23] ([i915#2849])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_reloc@basic-many-active@vcs0:
- shard-kbl:  NOTRUN -> [FAIL][24] ([i915#2389]) +9 similar issues
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19716/shard-kbl1/igt@gem_exec_relo

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Do not allow DC3CO if PSR SF is enabled (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Do not allow DC3CO if PSR SF is enabled (rev3)
URL   : https://patchwork.freedesktop.org/series/87283/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9795 -> Patchwork_19718


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/index.html

Known issues


  Here are the changes found in Patchwork_19718 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-y:   [PASS][1] -> [DMESG-WARN][2] ([i915#2411] / 
[i915#402])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html

  * igt@gem_linear_blits@basic:
- fi-tgl-y:   [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar 
issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/fi-tgl-y/igt@gem_linear_bl...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/fi-tgl-y/igt@gem_linear_bl...@basic.html

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-7500u:   [PASS][5] -> [DMESG-WARN][6] ([i915#2605])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/fi-kbl-7500u/igt@i915_pm_...@module-reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/fi-kbl-7500u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-kefka:   [PASS][7] -> [INCOMPLETE][8] ([i915#2940])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][9] ([fdo#109271]) +34 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@runner@aborted:
- fi-bsw-kefka:   NOTRUN -> [FAIL][11] ([i915#1436])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/fi-bsw-kefka/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_flink_basic@basic:
- fi-tgl-y:   [DMESG-WARN][12] ([i915#402]) -> [PASS][13] +1 
similar issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/fi-tgl-y/igt@gem_flink_ba...@basic.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/fi-tgl-y/igt@gem_flink_ba...@basic.html

  * igt@i915_module_load@reload:
- fi-kbl-7500u:   [DMESG-WARN][14] ([i915#2605]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/fi-kbl-7500u/igt@i915_module_l...@reload.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/fi-kbl-7500u/igt@i915_module_l...@reload.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [FAIL][16] ([i915#2128]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2128]: https://gitlab.freedesktop.org/drm/intel/issues/2128
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (44 -> 41)
--

  Additional (1): fi-snb-2600 
  Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus fi-hsw-4200u 


Build changes
-

  * Linux: CI_DRM_9795 -> Patchwork_19718

  CI-20190529: 20190529
  CI_DRM_9795: 5f1072de87a90be6d0ba8f4e4cffdbbe13166f03 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6011: 8c8499c29dd2aa189c3d687e057ba4df326b1732 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19718: faa9350c93d557e268c6b0a43e70077c14d8e8f4 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

faa9350c93d5 drm/i915/display: Do not allow DC3CO if PSR SF is enabled

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/index.html
___

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Sanitize the DDI LANES/IO and AUX power domain names

[Patchwork]

== Series Details ==

Series: drm/i915/tgl+: Sanitize the DDI LANES/IO and AUX power domain names
URL   : https://patchwork.freedesktop.org/series/87299/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9795_full -> Patchwork_19717_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19717_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19717_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19717_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rc6_residency@rc6-idle:
- shard-glk:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-glk7/igt@i915_pm_rc6_reside...@rc6-idle.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-glk1/igt@i915_pm_rc6_reside...@rc6-idle.html

  
 Warnings 

  * igt@runner@aborted:
- shard-kbl:  ([FAIL][3], [FAIL][4], [FAIL][5]) ([i915#2426] / 
[i915#2505] / [i915#2724] / [i915#3002]) -> ([FAIL][6], [FAIL][7], [FAIL][8], 
[FAIL][9], [FAIL][10]) ([i915#1814] / [i915#2292] / [i915#2505] / [i915#3002])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-kbl4/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-kbl1/igt@run...@aborted.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-kbl6/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-kbl4/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-kbl6/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-kbl4/igt@run...@aborted.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-kbl4/igt@run...@aborted.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-kbl7/igt@run...@aborted.html
- shard-apl:  ([FAIL][11], [FAIL][12], [FAIL][13]) ([i915#3002]) -> 
([FAIL][14], [FAIL][15], [FAIL][16], [FAIL][17]) ([i915#2724] / [i915#3002])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-apl1/igt@run...@aborted.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-apl1/igt@run...@aborted.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-apl3/igt@run...@aborted.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-apl2/igt@run...@aborted.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-apl6/igt@run...@aborted.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-apl1/igt@run...@aborted.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-apl1/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_19717_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@psr2:
- shard-iclb: [PASS][18] -> [SKIP][19] ([i915#658])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-iclb2/igt@feature_discov...@psr2.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-iclb6/igt@feature_discov...@psr2.html

  * igt@gem_create@create-massive:
- shard-snb:  NOTRUN -> [DMESG-WARN][20] ([i915#3002])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-snb6/igt@gem_cre...@create-massive.html
- shard-kbl:  NOTRUN -> [DMESG-WARN][21] ([i915#3002])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-kbl7/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_persistence@file:
- shard-hsw:  NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#1099])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-hsw1/igt@gem_ctx_persiste...@file.html

  * igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb:  NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#1099]) +6 
similar issues
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-mixed.html

  * igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][24] -> [TIMEOUT][25] ([i915#2481] / 
[i915#3070])
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-iclb5/igt@gem_...@unwedge-stress.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19717/shard-iclb8/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_create@forked:
- shard-glk:  [PASS][26] -> [DMESG-WARN][27] ([i915#118] / 
[i915#95])
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/sh

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Do not allow DC3CO if PSR SF is enabled (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Do not allow DC3CO if PSR SF is enabled (rev3)
URL   : https://patchwork.freedesktop.org/series/87283/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9795_full -> Patchwork_19718_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19718_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19718_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19718_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_capture@userptr:
- shard-kbl:  NOTRUN -> [FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-kbl6/igt@gem_exec_capt...@userptr.html

  
 Warnings 

  * igt@runner@aborted:
- shard-kbl:  ([FAIL][2], [FAIL][3], [FAIL][4]) ([i915#2426] / 
[i915#2505] / [i915#2724] / [i915#3002]) -> ([FAIL][5], [FAIL][6], [FAIL][7], 
[FAIL][8], [FAIL][9], [FAIL][10]) ([i915#1814] / [i915#2724] / [i915#3002])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-kbl4/igt@run...@aborted.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-kbl1/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-kbl6/igt@run...@aborted.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-kbl1/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-kbl4/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-kbl4/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-kbl4/igt@run...@aborted.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-kbl4/igt@run...@aborted.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-kbl7/igt@run...@aborted.html
- shard-apl:  ([FAIL][11], [FAIL][12], [FAIL][13]) ([i915#3002]) -> 
([FAIL][14], [FAIL][15], [FAIL][16]) ([i915#2724] / [i915#3002])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-apl1/igt@run...@aborted.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-apl1/igt@run...@aborted.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-apl3/igt@run...@aborted.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-apl7/igt@run...@aborted.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-apl2/igt@run...@aborted.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-apl2/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_19718_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@psr2:
- shard-iclb: [PASS][17] -> [SKIP][18] ([i915#658])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-iclb2/igt@feature_discov...@psr2.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-iclb6/igt@feature_discov...@psr2.html

  * igt@gem_create@create-massive:
- shard-snb:  NOTRUN -> [DMESG-WARN][19] ([i915#3002])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-snb5/igt@gem_cre...@create-massive.html
- shard-kbl:  NOTRUN -> [DMESG-WARN][20] ([i915#3002])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-kbl7/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_persistence@file:
- shard-hsw:  NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#1099])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-hsw4/igt@gem_ctx_persiste...@file.html

  * igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb:  NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#1099]) +6 
similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-mixed.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][23] ([i915#2846])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-apl8/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][24] -> [FAIL][25] ([i915#2842])
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9795/shard-tglb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19718/shard-tglb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk:  NOTRUN -> [FAIL][26] 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Do not allow DC3CO if PSR SF is enabled (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Do not allow DC3CO if PSR SF is enabled (rev4)
URL   : https://patchwork.freedesktop.org/series/87283/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9796 -> Patchwork_19719


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/index.html

Known issues


  Here are the changes found in Patchwork_19719 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [PASS][1] -> [DMESG-WARN][2] ([i915#1982] / 
[i915#402])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9796/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@prime_self_import@basic-with_one_bo:
- fi-tgl-y:   [PASS][3] -> [DMESG-WARN][4] ([i915#402])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9796/fi-tgl-y/igt@prime_self_import@basic-with_one_bo.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/fi-tgl-y/igt@prime_self_import@basic-with_one_bo.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2:  [FAIL][5] ([i915#1888]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9796/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html

  * igt@prime_vgem@basic-fence-flip:
- fi-tgl-y:   [DMESG-WARN][7] ([i915#402]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9796/fi-tgl-y/igt@prime_v...@basic-fence-flip.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/fi-tgl-y/igt@prime_v...@basic-fence-flip.html

  
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (45 -> 40)
--

  Missing(5): fi-ilk-m540 fi-hsw-4200u fi-ctg-p8600 fi-bdw-samus 
fi-snb-2600 


Build changes
-

  * Linux: CI_DRM_9796 -> Patchwork_19719

  CI-20190529: 20190529
  CI_DRM_9796: 03defca83287db9fbfd9dbee7f6d4bb071cb57ca @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6012: 232db375fcd86bef00badb1e3913630a2a5649d6 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19719: e955ee89ba803062cae7bb88000e6f8ae6eaa737 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

e955ee89ba80 drm/i915/display: Do not allow DC3CO if PSR SF is enabled

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/index.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Do not allow DC3CO if PSR SF is enabled (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Do not allow DC3CO if PSR SF is enabled (rev4)
URL   : https://patchwork.freedesktop.org/series/87283/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9796_full -> Patchwork_19719_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_19719_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19719_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19719_full:

### IGT changes ###

 Warnings 

  * igt@runner@aborted:
- shard-apl:  ([FAIL][1], [FAIL][2], [FAIL][3]) ([i915#180] / 
[i915#3002]) -> ([FAIL][4], [FAIL][5], [FAIL][6]) ([i915#3002])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9796/shard-apl3/igt@run...@aborted.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9796/shard-apl7/igt@run...@aborted.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9796/shard-apl1/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/shard-apl8/igt@run...@aborted.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/shard-apl1/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/shard-apl1/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_19719_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@chamelium:
- shard-iclb: NOTRUN -> [SKIP][7] ([fdo#111827])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/shard-iclb7/igt@feature_discov...@chamelium.html

  * igt@gem_create@create-massive:
- shard-snb:  NOTRUN -> [DMESG-WARN][8] ([i915#3002])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/shard-snb5/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl:  [PASS][9] -> [DMESG-WARN][10] ([i915#180])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9796/shard-apl2/igt@gem_ctx_isolation@preservation...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/shard-apl1/igt@gem_ctx_isolation@preservation...@rcs0.html

  * igt@gem_ctx_persistence@close-replace-race:
- shard-glk:  [PASS][11] -> [TIMEOUT][12] ([i915#2918])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9796/shard-glk2/igt@gem_ctx_persiste...@close-replace-race.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/shard-glk8/igt@gem_ctx_persiste...@close-replace-race.html

  * igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099]) +3 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-queued.html

  * igt@gem_eio@in-flight-contexts-immediate:
- shard-iclb: [PASS][14] -> [TIMEOUT][15] ([i915#3070])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9796/shard-iclb1/igt@gem_...@in-flight-contexts-immediate.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/shard-iclb5/igt@gem_...@in-flight-contexts-immediate.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][16] -> [FAIL][17] ([i915#2846])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9796/shard-glk4/igt@gem_exec_f...@basic-deadline.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/shard-glk6/igt@gem_exec_f...@basic-deadline.html
- shard-apl:  NOTRUN -> [FAIL][18] ([i915#2846])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/shard-apl2/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][19] -> [FAIL][20] ([i915#2842])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9796/shard-iclb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][21] ([i915#2842])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk:  [PASS][22] -> [FAIL][23] ([i915#2842])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9796/shard-glk9/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19719/shard-glk9/igt@gem_exec_fair@basic-pace-s...@rcs0.html
- shard-kbl:

Re: [Intel-gfx] [RFC PATCH 0/9] drm/i915/spi: discrete graphics internal spi

[Winkler, Tomas]

> - Ursprüngliche Mail -
> >> > I'm not sure whether we want to take that path.
> >
> > Hi Richard is there any way we can try to unclutter this ?
> 
> Of course there is a way. :-)
> Your use-case really seems to be special and MTD needs an improvement.
> Miquel, Vignesh and I just need to check more internals and corner cases in
> MTD.
> With some luck your patch can be used as-is with some minor adjustments
> on top.
Great, waiting for your comments. 
Thanks
Tomas

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