Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap
On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) wrote: > On 2/26/21 2:28 PM, Daniel Vetter wrote: > > So I think it stops gup. But I haven't verified at all. Would be good > > if Christian can check this with some direct io to a buffer in system > > memory. > > Hmm, > > Docs (again vm_normal_page() say) > > * VM_MIXEDMAP mappings can likewise contain memory with or without "struct > * page" backing, however the difference is that _all_ pages with a struct > * page (that is, those where pfn_valid is true) are refcounted and > considered > * normal pages by the VM. The disadvantage is that pages are refcounted > * (which can be slower and simply not an option for some PFNMAP > users). The > * advantage is that we don't have to follow the strict linearity rule of > * PFNMAP mappings in order to support COWable mappings. > > but it's true __vm_insert_mixed() ends up in the insert_pfn() path, so > the above isn't really true, which makes me wonder if and in that case > why there could any longer ever be a significant performance difference > between MIXEDMAP and PFNMAP. Yeah it's definitely confusing. I guess I'll hack up a patch and see what sticks. > BTW regarding the TTM hugeptes, I don't think we ever landed that devmap > hack, so they are (for the non-gup case) relying on > vma_is_special_huge(). For the gup case, I think the bug is still there. Maybe there's another devmap hack, but the ttm_vm_insert functions do use PFN_DEV and all that. And I think that stops gup_fast from trying to find the underlying page. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] add remap_pfn_range_notrack instead of reinventing it in i915
Hi all, i915 has some reason to want to avoid the track_pfn_remap overhead in remap_pfn_range. Add a function to the core VM to do just that rather than reinventing the functionality poorly in the driver. Note that the remap_io_sg path does get exercises when using Xorg on my Thinkpad X1, so this should be considered lightly tested, I've not managed to hit the remap_io_mapping path at all. Diffstat: drivers/gpu/drm/i915/i915_mm.c | 101 ++--- include/linux/mm.h |2 mm/memory.c| 52 - 3 files changed, 60 insertions(+), 95 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] mm: add remap_pfn_range_notrack
Add a version of remap_pfn_range that does not call track_pfn_range.
This will be used to fix horrible abuses of VM internals in the i915
driver.
Signed-off-by: Christoph Hellwig
---
include/linux/mm.h | 2 ++
mm/memory.c| 52 --
2 files changed, 34 insertions(+), 20 deletions(-)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 77e64e3eac80bd..fc3438daf5cfd8 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -2688,6 +2688,8 @@ unsigned long change_prot_numa(struct vm_area_struct *vma,
struct vm_area_struct *find_extend_vma(struct mm_struct *, unsigned long addr);
int remap_pfn_range(struct vm_area_struct *, unsigned long addr,
unsigned long pfn, unsigned long size, pgprot_t);
+int remap_pfn_range_notrack(struct vm_area_struct *vma, unsigned long addr,
+ unsigned long pfn, unsigned long size, pgprot_t prot);
int vm_insert_page(struct vm_area_struct *, unsigned long addr, struct page *);
int vm_insert_pages(struct vm_area_struct *vma, unsigned long addr,
struct page **pages, unsigned long *num);
diff --git a/mm/memory.c b/mm/memory.c
index c8e35762731861..d038c13f489b78 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -2266,26 +2266,17 @@ static inline int remap_p4d_range(struct mm_struct *mm,
pgd_t *pgd,
return 0;
}
-/**
- * remap_pfn_range - remap kernel memory to userspace
- * @vma: user vma to map to
- * @addr: target page aligned user address to start at
- * @pfn: page frame number of kernel physical memory address
- * @size: size of mapping area
- * @prot: page protection flags for this mapping
- *
- * Note: this is only safe if the mm semaphore is held when called.
- *
- * Return: %0 on success, negative error code otherwise.
+/*
+ * Variant of remap_pfn_range that does not call track_pfn_remap. The caller
+ * must have pre-validated the caching bits of the pgprot_t.
*/
-int remap_pfn_range(struct vm_area_struct *vma, unsigned long addr,
- unsigned long pfn, unsigned long size, pgprot_t prot)
+int remap_pfn_range_notrack(struct vm_area_struct *vma, unsigned long addr,
+ unsigned long pfn, unsigned long size, pgprot_t prot)
{
pgd_t *pgd;
unsigned long next;
unsigned long end = addr + PAGE_ALIGN(size);
struct mm_struct *mm = vma->vm_mm;
- unsigned long remap_pfn = pfn;
int err;
if (WARN_ON_ONCE(!PAGE_ALIGNED(addr)))
@@ -2315,10 +2306,6 @@ int remap_pfn_range(struct vm_area_struct *vma, unsigned
long addr,
vma->vm_pgoff = pfn;
}
- err = track_pfn_remap(vma, &prot, remap_pfn, addr, PAGE_ALIGN(size));
- if (err)
- return -EINVAL;
-
vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP;
BUG_ON(addr >= end);
@@ -2330,12 +2317,37 @@ int remap_pfn_range(struct vm_area_struct *vma,
unsigned long addr,
err = remap_p4d_range(mm, pgd, addr, next,
pfn + (addr >> PAGE_SHIFT), prot);
if (err)
- break;
+ return err;
} while (pgd++, addr = next, addr != end);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(remap_pfn_range_notrack);
+
+/**
+ * remap_pfn_range - remap kernel memory to userspace
+ * @vma: user vma to map to
+ * @addr: target page aligned user address to start at
+ * @pfn: page frame number of kernel physical memory address
+ * @size: size of mapping area
+ * @prot: page protection flags for this mapping
+ *
+ * Note: this is only safe if the mm semaphore is held when called.
+ *
+ * Return: %0 on success, negative error code otherwise.
+ */
+int remap_pfn_range(struct vm_area_struct *vma, unsigned long addr,
+ unsigned long pfn, unsigned long size, pgprot_t prot)
+{
+ int err;
+
+ err = track_pfn_remap(vma, &prot, pfn, addr, PAGE_ALIGN(size));
if (err)
- untrack_pfn(vma, remap_pfn, PAGE_ALIGN(size));
+ return -EINVAL;
+ err = remap_pfn_range_notrack(vma, addr, pfn, size, prot);
+ if (err)
+ untrack_pfn(vma, pfn, PAGE_ALIGN(size));
return err;
}
EXPORT_SYMBOL(remap_pfn_range);
--
2.29.2
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[Intel-gfx] [PATCH 2/2] i915: use remap_pfn_range_notrack
Use the remap_pfn_range_notrack helper instead of directly messing
with PTEs.
Signed-off-by: Christoph Hellwig
---
drivers/gpu/drm/i915/i915_mm.c | 101 +
1 file changed, 26 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_mm.c b/drivers/gpu/drm/i915/i915_mm.c
index 666808cb3a3260..a6bafac5ade0bd 100644
--- a/drivers/gpu/drm/i915/i915_mm.c
+++ b/drivers/gpu/drm/i915/i915_mm.c
@@ -28,55 +28,10 @@
#include "i915_drv.h"
-struct remap_pfn {
- struct mm_struct *mm;
- unsigned long pfn;
- pgprot_t prot;
-
- struct sgt_iter sgt;
- resource_size_t iobase;
-};
-
-static int remap_pfn(pte_t *pte, unsigned long addr, void *data)
-{
- struct remap_pfn *r = data;
-
- /* Special PTE are not associated with any struct page */
- set_pte_at(r->mm, addr, pte, pte_mkspecial(pfn_pte(r->pfn, r->prot)));
- r->pfn++;
-
- return 0;
-}
+#define EXPECTED_FLAGS (VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP)
#define use_dma(io) ((io) != -1)
-static inline unsigned long sgt_pfn(const struct remap_pfn *r)
-{
- if (use_dma(r->iobase))
- return (r->sgt.dma + r->sgt.curr + r->iobase) >> PAGE_SHIFT;
- else
- return r->sgt.pfn + (r->sgt.curr >> PAGE_SHIFT);
-}
-
-static int remap_sg(pte_t *pte, unsigned long addr, void *data)
-{
- struct remap_pfn *r = data;
-
- if (GEM_WARN_ON(!r->sgt.sgp))
- return -EINVAL;
-
- /* Special PTE are not associated with any struct page */
- set_pte_at(r->mm, addr, pte,
- pte_mkspecial(pfn_pte(sgt_pfn(r), r->prot)));
- r->pfn++; /* track insertions in case we need to unwind later */
-
- r->sgt.curr += PAGE_SIZE;
- if (r->sgt.curr >= r->sgt.max)
- r->sgt = __sgt_iter(__sg_next(r->sgt.sgp), use_dma(r->iobase));
-
- return 0;
-}
-
/**
* remap_io_mapping - remap an IO mapping to userspace
* @vma: user vma to map to
@@ -91,25 +46,12 @@ int remap_io_mapping(struct vm_area_struct *vma,
unsigned long addr, unsigned long pfn, unsigned long size,
struct io_mapping *iomap)
{
- struct remap_pfn r;
- int err;
-
-#define EXPECTED_FLAGS (VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP)
GEM_BUG_ON((vma->vm_flags & EXPECTED_FLAGS) != EXPECTED_FLAGS);
/* We rely on prevalidation of the io-mapping to skip track_pfn(). */
- r.mm = vma->vm_mm;
- r.pfn = pfn;
- r.prot = __pgprot((pgprot_val(iomap->prot) & _PAGE_CACHE_MASK) |
- (pgprot_val(vma->vm_page_prot) & ~_PAGE_CACHE_MASK));
-
- err = apply_to_page_range(r.mm, addr, size, remap_pfn, &r);
- if (unlikely(err)) {
- zap_vma_ptes(vma, addr, (r.pfn - pfn) << PAGE_SHIFT);
- return err;
- }
-
- return 0;
+ return remap_pfn_range_notrack(vma, addr, pfn, size,
+ __pgprot((pgprot_val(iomap->prot) & _PAGE_CACHE_MASK) |
+(pgprot_val(vma->vm_page_prot) & ~_PAGE_CACHE_MASK)));
}
/**
@@ -126,12 +68,7 @@ int remap_io_sg(struct vm_area_struct *vma,
unsigned long addr, unsigned long size,
struct scatterlist *sgl, resource_size_t iobase)
{
- struct remap_pfn r = {
- .mm = vma->vm_mm,
- .prot = vma->vm_page_prot,
- .sgt = __sgt_iter(sgl, use_dma(iobase)),
- .iobase = iobase,
- };
+ unsigned long pfn, len, remapped = 0;
int err;
/* We rely on prevalidation of the io-mapping to skip track_pfn(). */
@@ -140,11 +77,25 @@ int remap_io_sg(struct vm_area_struct *vma,
if (!use_dma(iobase))
flush_cache_range(vma, addr, size);
- err = apply_to_page_range(r.mm, addr, size, remap_sg, &r);
- if (unlikely(err)) {
- zap_vma_ptes(vma, addr, r.pfn << PAGE_SHIFT);
- return err;
- }
-
- return 0;
+ do {
+ if (use_dma(iobase)) {
+ if (!sg_dma_len(sgl))
+ break;
+ pfn = (sg_dma_address(sgl) + iobase) >> PAGE_SHIFT;
+ len = sg_dma_len(sgl);
+ } else {
+ pfn = page_to_pfn(sg_page(sgl));
+ len = sgl->length;
+ }
+
+ err = remap_pfn_range_notrack(vma, addr + remapped, pfn, len,
+ vma->vm_page_prot);
+ if (err)
+ break;
+ remapped += len;
+ } while ((sgl = __sg_next(sgl)));
+
+ if (err)
+ zap_vma_ptes(vma, addr, remapped);
+ return err;
}
--
2.29.2
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Re: [Intel-gfx] [PATCH 1/7] drm/i915: Fix TGL+ plane SAGV watermark programming
On Fri, Feb 26, 2021 at 05:31:58PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> When we switch between SAGV on vs. off we need to reprogram all
> plane wateramrks accordingly. Currently skl_wm_add_affected_planes()
> totally ignores the SAGV watermark and just assumes we will use
> the normal WM0.
>
> Fix this by utilizing skl_plane_wm_level() which picks the
> correct watermark based on use_sagv_wm. Thus we will force
> an update on all the planes whose watermark registers need
> to be reprogrammed.
Reviewed-by: Stanislav Lisovskiy
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 60 -
> 1 file changed, 37 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8cc67f9c4e58..2d0e3e7f11b8 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4748,11 +4748,10 @@ icl_get_total_relative_data_rate(struct
> intel_atomic_state *state,
> }
>
> static const struct skl_wm_level *
> -skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
> +skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
> enum plane_id plane_id,
> int level)
> {
> - const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
>
> if (level == 0 && pipe_wm->use_sagv_wm)
> @@ -5572,21 +5571,17 @@ void skl_write_plane_wm(struct intel_plane *plane,
> int level, max_level = ilk_wm_max_level(dev_priv);
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> - const struct skl_plane_wm *wm =
> - &crtc_state->wm.skl.optimal.planes[plane_id];
> + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> + const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> const struct skl_ddb_entry *ddb_y =
> &crtc_state->wm.skl.plane_ddb_y[plane_id];
> const struct skl_ddb_entry *ddb_uv =
> &crtc_state->wm.skl.plane_ddb_uv[plane_id];
>
> - for (level = 0; level <= max_level; level++) {
> - const struct skl_wm_level *wm_level;
> -
> - wm_level = skl_plane_wm_level(crtc_state, plane_id, level);
> -
> + for (level = 0; level <= max_level; level++)
> skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
> -wm_level);
> - }
> +skl_plane_wm_level(pipe_wm, plane_id,
> level));
> +
> skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
> &wm->trans_wm);
>
> @@ -5612,19 +5607,15 @@ void skl_write_cursor_wm(struct intel_plane *plane,
> int level, max_level = ilk_wm_max_level(dev_priv);
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> - const struct skl_plane_wm *wm =
> - &crtc_state->wm.skl.optimal.planes[plane_id];
> + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> + const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> const struct skl_ddb_entry *ddb =
> &crtc_state->wm.skl.plane_ddb_y[plane_id];
>
> - for (level = 0; level <= max_level; level++) {
> - const struct skl_wm_level *wm_level;
> -
> - wm_level = skl_plane_wm_level(crtc_state, plane_id, level);
> -
> + for (level = 0; level <= max_level; level++)
> skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
> -wm_level);
> - }
> +skl_plane_wm_level(pipe_wm, plane_id,
> level));
> +
> skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
>
> skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
> @@ -5964,6 +5955,29 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> }
> }
>
> +static bool skl_plane_selected_wm_equals(struct intel_plane *plane,
> + const struct skl_pipe_wm *old_pipe_wm,
> + const struct skl_pipe_wm *new_pipe_wm)
> +{
> + const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id];
> + const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id];
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> + int level, max_level = ilk_wm_max_level(i915);
> +
> + for (level = 0; level <= max_level; level++) {
> + /*
> + * We don't check uv_wm as the hardware doesn't actually
> + * use it. It only gets used for calculating the required
> + * ddb allocation.
> + */
> + if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm, level,
> plane->id),
> + skl_plane_wm_level(new_pipe_wm, level,
> plane->id)))
> +
Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap
Hi, On 3/1/21 9:28 AM, Daniel Vetter wrote: On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) wrote: On 2/26/21 2:28 PM, Daniel Vetter wrote: So I think it stops gup. But I haven't verified at all. Would be good if Christian can check this with some direct io to a buffer in system memory. Hmm, Docs (again vm_normal_page() say) * VM_MIXEDMAP mappings can likewise contain memory with or without "struct * page" backing, however the difference is that _all_ pages with a struct * page (that is, those where pfn_valid is true) are refcounted and considered * normal pages by the VM. The disadvantage is that pages are refcounted * (which can be slower and simply not an option for some PFNMAP users). The * advantage is that we don't have to follow the strict linearity rule of * PFNMAP mappings in order to support COWable mappings. but it's true __vm_insert_mixed() ends up in the insert_pfn() path, so the above isn't really true, which makes me wonder if and in that case why there could any longer ever be a significant performance difference between MIXEDMAP and PFNMAP. Yeah it's definitely confusing. I guess I'll hack up a patch and see what sticks. BTW regarding the TTM hugeptes, I don't think we ever landed that devmap hack, so they are (for the non-gup case) relying on vma_is_special_huge(). For the gup case, I think the bug is still there. Maybe there's another devmap hack, but the ttm_vm_insert functions do use PFN_DEV and all that. And I think that stops gup_fast from trying to find the underlying page. -Daniel Hmm perhaps it might, but I don't think so. The fix I tried out was to set PFN_DEV | PFN_MAP for huge PTEs which causes pfn_devmap() to be true, and then follow_devmap_pmd()->get_dev_pagemap() which returns NULL and gup_fast() backs off, in the end that would mean setting in stone that "if there is a huge devmap page table entry for which we haven't registered any devmap struct pages (get_dev_pagemap returns NULL), we should treat that as a "special" huge page table entry". From what I can tell, all code calling get_dev_pagemap() already does that, it's just a question of getting it accepted and formalizing it. /Thomas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/7] drm/i915: Zero out SAGV wm when we don't have enough DDB for it
On Fri, Feb 26, 2021 at 05:31:59PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Let's handle the SAGV WM0 more like the other wm levels and just
> totally zero it out when we don't have the DDB space to back it
> up.
Reviewed-by: Stanislav Lisovskiy
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 11 ++-
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2d0e3e7f11b8..c341fa957884 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3921,12 +3921,10 @@ static bool tgl_crtc_can_enable_sagv(const struct
> intel_crtc_state *crtc_state)
> return true;
>
> for_each_plane_id_on_crtc(crtc, plane_id) {
> - const struct skl_ddb_entry *plane_alloc =
> - &crtc_state->wm.skl.plane_ddb_y[plane_id];
> const struct skl_plane_wm *wm =
> &crtc_state->wm.skl.optimal.planes[plane_id];
>
> - if (skl_ddb_entry_size(plane_alloc) <
> wm->sagv_wm0.min_ddb_alloc)
> + if (wm->wm[0].plane_en && !wm->sagv_wm0.plane_en)
> return false;
> }
>
> @@ -4957,8 +4955,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> }
>
> /*
> - * Go back and disable the transition watermark if it turns out we
> - * don't have enough DDB blocks for it.
> + * Go back and disable the transition and SAGV watermarks
> + * if it turns out we don't have enough DDB blocks for them.
>*/
> for_each_plane_id_on_crtc(crtc, plane_id) {
> struct skl_plane_wm *wm =
> @@ -4966,6 +4964,9 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>
> if (wm->trans_wm.plane_res_b >= total[plane_id])
> memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
> +
> + if (wm->sagv_wm0.plane_res_b >= total[plane_id])
> + memset(&wm->sagv_wm0, 0, sizeof(wm->sagv_wm0));
> }
>
> return 0;
> --
> 2.26.2
>
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Re: [Intel-gfx] add remap_pfn_range_notrack instead of reinventing it in i915
On Mon, Mar 01, 2021 at 09:33:18AM +0100, Christoph Hellwig wrote: > Hi all, > > i915 has some reason to want to avoid the track_pfn_remap overhead in > remap_pfn_range. Add a function to the core VM to do just that rather > than reinventing the functionality poorly in the driver. It's not _notrack it's "rely on the tracking established by the struct io_mapping". Exporting a _notrack version to drivers sounds like not something we want to ever do. So I think you want a helper which takes the io_mapping, and not something that encourages drivers to go full stupid. > Note that the remap_io_sg path does get exercises when using Xorg on my > Thinkpad X1, so this should be considered lightly tested, I've not > managed to hit the remap_io_mapping path at all. Needs an older machine and old userspace. intel-gfx CI should still check whether it's all ok. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] add remap_pfn_range_notrack instead of reinventing it in i915
On Mon, Mar 01, 2021 at 09:44:13AM +0100, Daniel Vetter wrote: > On Mon, Mar 01, 2021 at 09:33:18AM +0100, Christoph Hellwig wrote: > > Hi all, > > > > i915 has some reason to want to avoid the track_pfn_remap overhead in > > remap_pfn_range. Add a function to the core VM to do just that rather > > than reinventing the functionality poorly in the driver. > > It's not _notrack it's "rely on the tracking established by the struct > io_mapping". Exporting a _notrack version to drivers sounds like not > something we want to ever do. So I think you want a helper which takes the > io_mapping, and not something that encourages drivers to go full stupid. As far as I can tell there is no struct io_mapping anywhere near remap_io_sg. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for HDCP 2.2 MST fixes
== Series Details == Series: HDCP 2.2 MST fixes URL : https://patchwork.freedesktop.org/series/87475/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9816 -> Patchwork_19734 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19734 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19734, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19734/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19734: ### IGT changes ### Possible regressions * igt@gem_linear_blits@basic: - fi-kbl-8809g: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9816/fi-kbl-8809g/igt@gem_linear_bl...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19734/fi-kbl-8809g/igt@gem_linear_bl...@basic.html Known issues Here are the changes found in Patchwork_19734 that come from known issues: ### IGT changes ### Issues hit * igt@gem_tiled_blits@basic: - fi-kbl-8809g: [PASS][3] -> [TIMEOUT][4] ([i915#2502]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9816/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19734/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9816/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19734/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html Possible fixes * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9816/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19734/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html Warnings * igt@runner@aborted: - fi-icl-u2: [FAIL][9] ([i915#1814]) -> [FAIL][10] ([i915#1569] / [i915#2426] / [k.org#202973]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9816/fi-icl-u2/igt@run...@aborted.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19734/fi-icl-u2/igt@run...@aborted.html [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [k.org#202973]: https://bugzilla.kernel.org/show_bug.cgi?id=202973 Participating hosts (41 -> 36) -- Missing(5): fi-ilk-m540 fi-byt-j1900 fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9816 -> Patchwork_19734 CI-20190529: 20190529 CI_DRM_9816: 7295445db2c0c10c9e0308e8bef521eb3b051d3a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6015: aa44cddf4ef689f8a3726fcbeedc03f08b12bd82 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19734: d3f3dc1c06f3896ad3fb94372479d9a2f0574fd6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d3f3dc1c06f3 drm/i915/hdcp: return correct error code cd063b741538 drm/i915/hdcp: recover link on stream enc enable/disable failure 7c3bc124485d drm/i915/hdcp: HDCP2.2 MST Link failure recovery == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19734/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] mm: add remap_pfn_range_notrack
== Series Details == Series: series starting with [1/2] mm: add remap_pfn_range_notrack URL : https://patchwork.freedesktop.org/series/87479/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4595e8c87551 mm: add remap_pfn_range_notrack -:21: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #21: FILE: include/linux/mm.h:2693: +int remap_pfn_range_notrack(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, unsigned long size, pgprot_t prot); -:51: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #51: FILE: mm/memory.c:2262: +int remap_pfn_range_notrack(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, unsigned long size, pgprot_t prot) total: 0 errors, 0 warnings, 2 checks, 88 lines checked 2abf3eefad4d i915: use remap_pfn_range_notrack ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] mm: add remap_pfn_range_notrack
== Series Details == Series: series starting with [1/2] mm: add remap_pfn_range_notrack URL : https://patchwork.freedesktop.org/series/87479/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gp
Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap
On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) wrote: > Hi, > > On 3/1/21 9:28 AM, Daniel Vetter wrote: > > On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) > > wrote: > > > On 2/26/21 2:28 PM, Daniel Vetter wrote: > > > > So I think it stops gup. But I haven't verified at all. Would be good > > > > if Christian can check this with some direct io to a buffer in system > > > > memory. > > > Hmm, > > > > > > Docs (again vm_normal_page() say) > > > > > >* VM_MIXEDMAP mappings can likewise contain memory with or without > > > "struct > > >* page" backing, however the difference is that _all_ pages with a > > > struct > > >* page (that is, those where pfn_valid is true) are refcounted and > > > considered > > >* normal pages by the VM. The disadvantage is that pages are refcounted > > >* (which can be slower and simply not an option for some PFNMAP > > > users). The > > >* advantage is that we don't have to follow the strict linearity rule > > > of > > >* PFNMAP mappings in order to support COWable mappings. > > > > > > but it's true __vm_insert_mixed() ends up in the insert_pfn() path, so > > > the above isn't really true, which makes me wonder if and in that case > > > why there could any longer ever be a significant performance difference > > > between MIXEDMAP and PFNMAP. > > Yeah it's definitely confusing. I guess I'll hack up a patch and see > > what sticks. > > > > > BTW regarding the TTM hugeptes, I don't think we ever landed that devmap > > > hack, so they are (for the non-gup case) relying on > > > vma_is_special_huge(). For the gup case, I think the bug is still there. > > Maybe there's another devmap hack, but the ttm_vm_insert functions do > > use PFN_DEV and all that. And I think that stops gup_fast from trying > > to find the underlying page. > > -Daniel > > Hmm perhaps it might, but I don't think so. The fix I tried out was to set > > PFN_DEV | PFN_MAP for huge PTEs which causes pfn_devmap() to be true, and > then > > follow_devmap_pmd()->get_dev_pagemap() which returns NULL and gup_fast() > backs off, > > in the end that would mean setting in stone that "if there is a huge devmap > page table entry for which we haven't registered any devmap struct pages > (get_dev_pagemap returns NULL), we should treat that as a "special" huge > page table entry". > > From what I can tell, all code calling get_dev_pagemap() already does that, > it's just a question of getting it accepted and formalizing it. Oh I thought that's already how it works, since I didn't spot anything else that would block gup_fast from falling over. I guess really would need some testcases to make sure direct i/o (that's the easiest to test) fails like we expect. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] -stable regression in Intel graphics, introduced in Linux 5.10.9
On Sun, Feb 28, 2021 at 09:05:45PM +0100, Diego Calleja wrote: > El domingo, 28 de febrero de 2021 16:14:54 (CET) Greg KH escribió: > > Is this the same issue reported here: > > > > https://lore.kernel.org/r/f1070486-891a-8ec0-0390-b9aeb0317...@redhat.com > > ? > > I just tested current mainline (which already contains the three commits > mentioned in the bugzilla), > and the problems have disappeared. I do not see all 3 commits in Linus's tree already, am I missing something? What are the git ids that you are looking at? thanks, greg k-h ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/7] drm/i915: Print wm changes if sagv_wm0 changes
On Fri, Feb 26, 2021 at 05:32:00PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Let's consider sagv_wm0 as well when deciding whether to dump > out the watermark changes. > > Cc: Stanislav Lisovskiy > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/intel_pm.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index c341fa957884..06c54adc609a 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5647,7 +5647,8 @@ static bool skl_plane_wm_equals(struct drm_i915_private > *dev_priv, > return false; > } > > - return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm); > + return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm) && > + skl_wm_level_equals(&wm1->sagv_wm0, &wm2->sagv_wm0); > } Reviewed-by: Stanislav Lisovskiy > > static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a, > -- > 2.26.2 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] add remap_pfn_range_notrack instead of reinventing it in i915
On Mon, Mar 01, 2021 at 09:45:59AM +0100, Christoph Hellwig wrote: > On Mon, Mar 01, 2021 at 09:44:13AM +0100, Daniel Vetter wrote: > > On Mon, Mar 01, 2021 at 09:33:18AM +0100, Christoph Hellwig wrote: > > > Hi all, > > > > > > i915 has some reason to want to avoid the track_pfn_remap overhead in > > > remap_pfn_range. Add a function to the core VM to do just that rather > > > than reinventing the functionality poorly in the driver. > > > > It's not _notrack it's "rely on the tracking established by the struct > > io_mapping". Exporting a _notrack version to drivers sounds like not > > something we want to ever do. So I think you want a helper which takes the > > io_mapping, and not something that encourages drivers to go full stupid. > > As far as I can tell there is no struct io_mapping anywhere near > remap_io_sg. Yeah that looks like real bad taste, but it is how this stuff is (or at least was, been years I've followed this closely) meant to work. Comment in the code still claims it's the way: /* We rely on prevalidation of the io-mapping to skip track_pfn(). */ If that's a lie and there's no iomapping for that range, then ugh. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/7] drm/i915: Stuff SAGV watermark into a sub-structure
On Fri, Feb 26, 2021 at 05:32:01PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We'll want a SAGV transition watermark as well. Prepare
> for that by collecting SAGV wm0 into a sub-strcture.
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Ville Syrjälä
Reviewed-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 +--
> .../drm/i915/display/intel_display_types.h| 4 ++-
> drivers/gpu/drm/i915/intel_pm.c | 30 +--
> 3 files changed, 20 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d0da88751c72..718e66f49332 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9387,7 +9387,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
> if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> &sw_plane_wm->wm[level]) ||
> (level == 0 &&
> skl_wm_level_equals(&hw_plane_wm->wm[level],
> -
> &sw_plane_wm->sagv_wm0)))
> +
> &sw_plane_wm->sagv.wm0)))
> continue;
>
> drm_err(&dev_priv->drm,
> @@ -9444,7 +9444,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
> if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> &sw_plane_wm->wm[level]) ||
> (level == 0 &&
> skl_wm_level_equals(&hw_plane_wm->wm[level],
> -
> &sw_plane_wm->sagv_wm0)))
> +
> &sw_plane_wm->sagv.wm0)))
> continue;
>
> drm_err(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 1a76e1d9de7a..6321cd3df81e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -732,7 +732,9 @@ struct skl_plane_wm {
> struct skl_wm_level wm[8];
> struct skl_wm_level uv_wm[8];
> struct skl_wm_level trans_wm;
> - struct skl_wm_level sagv_wm0;
> + struct {
> + struct skl_wm_level wm0;
> + } sagv;
> bool is_planar;
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 06c54adc609a..a1591d9189a0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3924,7 +3924,7 @@ static bool tgl_crtc_can_enable_sagv(const struct
> intel_crtc_state *crtc_state)
> const struct skl_plane_wm *wm =
> &crtc_state->wm.skl.optimal.planes[plane_id];
>
> - if (wm->wm[0].plane_en && !wm->sagv_wm0.plane_en)
> + if (wm->wm[0].plane_en && !wm->sagv.wm0.plane_en)
> return false;
> }
>
> @@ -4753,7 +4753,7 @@ skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
> const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
>
> if (level == 0 && pipe_wm->use_sagv_wm)
> - return &wm->sagv_wm0;
> + return &wm->sagv.wm0;
>
> return &wm->wm[level];
> }
> @@ -4965,8 +4965,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> if (wm->trans_wm.plane_res_b >= total[plane_id])
> memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
>
> - if (wm->sagv_wm0.plane_res_b >= total[plane_id])
> - memset(&wm->sagv_wm0, 0, sizeof(wm->sagv_wm0));
> + if (wm->sagv.wm0.plane_res_b >= total[plane_id])
> + memset(&wm->sagv.wm0, 0, sizeof(wm->sagv.wm0));
> }
>
> return 0;
> @@ -5316,7 +5316,7 @@ static void tgl_compute_sagv_wm(const struct
> intel_crtc_state *crtc_state,
> struct skl_plane_wm *plane_wm)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - struct skl_wm_level *sagv_wm = &plane_wm->sagv_wm0;
> + struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0;
> struct skl_wm_level *levels = plane_wm->wm;
> unsigned int latency = dev_priv->wm.skl_latency[0] +
> dev_priv->sagv_block_time_us;
>
> @@ -5648,7 +5648,7 @@ static bool skl_plane_wm_equals(struct drm_i915_private
> *dev_priv,
> }
>
> return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm) &&
> - skl_wm_level_equals(&wm1->sagv_wm0, &wm2->sagv_wm0);
> + skl_wm_level_equals(&wm1->sagv.wm0, &wm2->sagv.wm0);
> }
>
> static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
> @@ -5886,13 +5886,13 @@ skl_print_wm_ch
Re: [Intel-gfx] [PATCH 5/7] drm/i915: Introduce SAGV transtion watermark
On Fri, Feb 26, 2021 at 05:32:02PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Seems to me that if we calculate WM0 using the bumped up SAGV latency
> we need to calculate the transition watermark accordingly. Track it
> alongside the other watermarks.
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Ville Syrjälä
Reviewed-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 +-
> .../drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/drm/i915/intel_pm.c | 94 ---
> 3 files changed, 65 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 718e66f49332..e34e5a9da5c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9459,7 +9459,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> }
>
> if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
> - &sw_plane_wm->trans_wm)) {
> + &sw_plane_wm->trans_wm) &&
> + !skl_wm_level_equals(&hw_plane_wm->trans_wm,
> + &sw_plane_wm->sagv.trans_wm)) {
> drm_err(&dev_priv->drm,
> "mismatch in trans WM pipe %c cursor (expected
> e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> pipe_name(pipe),
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6321cd3df81e..e2365f2d07cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -734,6 +734,7 @@ struct skl_plane_wm {
> struct skl_wm_level trans_wm;
> struct {
> struct skl_wm_level wm0;
> + struct skl_wm_level trans_wm;
> } sagv;
> bool is_planar;
> };
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a1591d9189a0..9d9ba63fc395 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4758,6 +4758,18 @@ skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
> return &wm->wm[level];
> }
>
> +static const struct skl_wm_level *
> +skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
> +enum plane_id plane_id)
> +{
> + const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> +
> + if (pipe_wm->use_sagv_wm)
> + return &wm->sagv.trans_wm;
> +
> + return &wm->trans_wm;
> +}
> +
> static int
> skl_allocate_plane_ddb(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> @@ -4967,6 +4979,9 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>
> if (wm->sagv.wm0.plane_res_b >= total[plane_id])
> memset(&wm->sagv.wm0, 0, sizeof(wm->sagv.wm0));
> +
> + if (wm->sagv.trans_wm.plane_res_b >= total[plane_id])
> + memset(&wm->sagv.trans_wm, 0,
> sizeof(wm->sagv.trans_wm));
> }
>
> return 0;
> @@ -5325,12 +5340,11 @@ static void tgl_compute_sagv_wm(const struct
> intel_crtc_state *crtc_state,
>sagv_wm);
> }
>
> -static void skl_compute_transition_wm(const struct intel_crtc_state
> *crtc_state,
> - const struct skl_wm_params *wp,
> - struct skl_plane_wm *wm)
> +static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
> + struct skl_wm_level *trans_wm,
> + const struct skl_wm_level *wm0,
> + const struct skl_wm_params *wp)
> {
> - struct drm_device *dev = crtc_state->uapi.crtc->dev;
> - const struct drm_i915_private *dev_priv = to_i915(dev);
> u16 trans_min, trans_amount, trans_y_tile_min;
> u16 wm0_sel_res_b, trans_offset_b, res_blocks;
>
> @@ -5368,7 +5382,7 @@ static void skl_compute_transition_wm(const struct
> intel_crtc_state *crtc_state,
>* Result Blocks is Result Blocks minus 1 and it should work for the
>* current platforms.
>*/
> - wm0_sel_res_b = wm->wm[0].plane_res_b - 1;
> + wm0_sel_res_b = wm0->plane_res_b - 1;
>
> if (wp->y_tiled) {
> trans_y_tile_min =
> @@ -5384,8 +5398,8 @@ static void skl_compute_transition_wm(const struct
> intel_crtc_state *crtc_state,
>* computing the DDB we'll come back and disable it if that
>* assumption turns out to be false.
>*/
> - wm->trans_wm.plane_res_b = res_blocks + 1;
> - wm->trans_wm.plane_en = true;
> + trans_wm->plane_res_b = res_blocks + 1;
> + trans_wm->plane_en = true;
> }
>
> static int skl_build_plane_wm_single(struct intel_crtc_st
Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap
On 3/1/21 10:05 AM, Daniel Vetter wrote: On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) wrote: Hi, On 3/1/21 9:28 AM, Daniel Vetter wrote: On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) wrote: On 2/26/21 2:28 PM, Daniel Vetter wrote: So I think it stops gup. But I haven't verified at all. Would be good if Christian can check this with some direct io to a buffer in system memory. Hmm, Docs (again vm_normal_page() say) * VM_MIXEDMAP mappings can likewise contain memory with or without "struct * page" backing, however the difference is that _all_ pages with a struct * page (that is, those where pfn_valid is true) are refcounted and considered * normal pages by the VM. The disadvantage is that pages are refcounted * (which can be slower and simply not an option for some PFNMAP users). The * advantage is that we don't have to follow the strict linearity rule of * PFNMAP mappings in order to support COWable mappings. but it's true __vm_insert_mixed() ends up in the insert_pfn() path, so the above isn't really true, which makes me wonder if and in that case why there could any longer ever be a significant performance difference between MIXEDMAP and PFNMAP. Yeah it's definitely confusing. I guess I'll hack up a patch and see what sticks. BTW regarding the TTM hugeptes, I don't think we ever landed that devmap hack, so they are (for the non-gup case) relying on vma_is_special_huge(). For the gup case, I think the bug is still there. Maybe there's another devmap hack, but the ttm_vm_insert functions do use PFN_DEV and all that. And I think that stops gup_fast from trying to find the underlying page. -Daniel Hmm perhaps it might, but I don't think so. The fix I tried out was to set PFN_DEV | PFN_MAP for huge PTEs which causes pfn_devmap() to be true, and then follow_devmap_pmd()->get_dev_pagemap() which returns NULL and gup_fast() backs off, in the end that would mean setting in stone that "if there is a huge devmap page table entry for which we haven't registered any devmap struct pages (get_dev_pagemap returns NULL), we should treat that as a "special" huge page table entry". From what I can tell, all code calling get_dev_pagemap() already does that, it's just a question of getting it accepted and formalizing it. Oh I thought that's already how it works, since I didn't spot anything else that would block gup_fast from falling over. I guess really would need some testcases to make sure direct i/o (that's the easiest to test) fails like we expect. Yeah, IIRC the "| PFN_MAP" is the missing piece for TTM huge ptes. Otherwise pmd_devmap() will not return true and since there is no pmd_special() things break. /Thomas -Daniel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 6/7] drm/i915: Check tgl+ SAGV watermarks properly
On Fri, Feb 26, 2021 at 05:32:03PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We know which WM0 (normal vs. SAGV) we supposedly programmed
> into the hardware, so just check against that instead of accepting
> either watermark as valid.
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Ville Syrjälä
Reviewed-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 88 +---
> drivers/gpu/drm/i915/intel_pm.c | 4 +-
> drivers/gpu/drm/i915/intel_pm.h | 5 ++
> 3 files changed, 47 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e34e5a9da5c1..e2ef31a93407 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9377,41 +9377,40 @@ static void verify_wm_state(struct intel_crtc *crtc,
>
> /* planes */
> for_each_universal_plane(dev_priv, pipe, plane) {
> - struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
> -
> - hw_plane_wm = &hw->wm.planes[plane];
> - sw_plane_wm = &sw_wm->planes[plane];
> + const struct skl_wm_level *hw_wm_level, *sw_wm_level;
>
> /* Watermarks */
> for (level = 0; level <= max_level; level++) {
> - if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> - &sw_plane_wm->wm[level]) ||
> - (level == 0 &&
> skl_wm_level_equals(&hw_plane_wm->wm[level],
> -
> &sw_plane_wm->sagv.wm0)))
> + hw_wm_level = &hw->wm.planes[plane].wm[level];
> + sw_wm_level = skl_plane_wm_level(sw_wm, plane, level);
> +
> + if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
> continue;
>
> drm_err(&dev_priv->drm,
> "mismatch in WM pipe %c plane %d level %d
> (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> pipe_name(pipe), plane + 1, level,
> - sw_plane_wm->wm[level].plane_en,
> - sw_plane_wm->wm[level].plane_res_b,
> - sw_plane_wm->wm[level].plane_res_l,
> - hw_plane_wm->wm[level].plane_en,
> - hw_plane_wm->wm[level].plane_res_b,
> - hw_plane_wm->wm[level].plane_res_l);
> + sw_wm_level->plane_en,
> + sw_wm_level->plane_res_b,
> + sw_wm_level->plane_res_l,
> + hw_wm_level->plane_en,
> + hw_wm_level->plane_res_b,
> + hw_wm_level->plane_res_l);
> }
>
> - if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
> - &sw_plane_wm->trans_wm)) {
> + hw_wm_level = &hw->wm.planes[plane].trans_wm;
> + sw_wm_level = skl_plane_trans_wm(sw_wm, plane);
> +
> + if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
> drm_err(&dev_priv->drm,
> "mismatch in trans WM pipe %c plane %d
> (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> pipe_name(pipe), plane + 1,
> - sw_plane_wm->trans_wm.plane_en,
> - sw_plane_wm->trans_wm.plane_res_b,
> - sw_plane_wm->trans_wm.plane_res_l,
> - hw_plane_wm->trans_wm.plane_en,
> - hw_plane_wm->trans_wm.plane_res_b,
> - hw_plane_wm->trans_wm.plane_res_l);
> + sw_wm_level->plane_en,
> + sw_wm_level->plane_res_b,
> + sw_wm_level->plane_res_l,
> + hw_wm_level->plane_en,
> + hw_wm_level->plane_res_b,
> + hw_wm_level->plane_res_l);
> }
>
> /* DDB */
> @@ -9434,43 +9433,36 @@ static void verify_wm_state(struct intel_crtc *crtc,
>* once the plane becomes visible, we can skip this check
>*/
> if (1) {
> - struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
> -
> - hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
> - sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
> + const struct skl_wm_level *hw_wm_level, *sw_wm_level;
>
> /* Watermarks */
> for (level = 0; level <= max_level; level++) {
> - if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> - &sw_plane_wm->w
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] mm: add remap_pfn_range_notrack
== Series Details == Series: series starting with [1/2] mm: add remap_pfn_range_notrack URL : https://patchwork.freedesktop.org/series/87479/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9816 -> Patchwork_19735 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19735 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19735, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19735/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19735: ### IGT changes ### Possible regressions * igt@gem_exec_gttfill@basic: - fi-kbl-8809g: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9816/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19735/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html Known issues Here are the changes found in Patchwork_19735 that come from known issues: ### IGT changes ### Issues hit * igt@gem_linear_blits@basic: - fi-kbl-8809g: [PASS][3] -> [TIMEOUT][4] ([i915#2502]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9816/fi-kbl-8809g/igt@gem_linear_bl...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19735/fi-kbl-8809g/igt@gem_linear_bl...@basic.html * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9816/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19735/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][7] ([i915#1602] / [i915#2029] / [i915#2369]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19735/fi-bdw-5557u/igt@run...@aborted.html Possible fixes * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9816/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19735/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369 [i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (41 -> 37) -- Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9816 -> Patchwork_19735 CI-20190529: 20190529 CI_DRM_9816: 7295445db2c0c10c9e0308e8bef521eb3b051d3a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6015: aa44cddf4ef689f8a3726fcbeedc03f08b12bd82 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19735: 2abf3eefad4df507fb89f8f83c7b59cca6aadb05 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2abf3eefad4d i915: use remap_pfn_range_notrack 4595e8c87551 mm: add remap_pfn_range_notrack == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19735/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 7/7] drm/i915: Clean up verify_wm_state()
On Fri, Feb 26, 2021 at 05:32:04PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Get rid of the nonsense cursor special case in verify_wm_state()
> by just iterating through all the planes. And let's use the
> canonical [PLANE:..] style in the debug prints while at it.
Great move!
Reviewed-by: Stanislav Lisovskiy
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 88
> drivers/gpu/drm/i915/display/intel_display.h | 5 --
> 2 files changed, 17 insertions(+), 76 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e2ef31a93407..e0ecd8eea68d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9348,11 +9348,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
> struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
> struct skl_pipe_wm wm;
> } *hw;
> - struct skl_pipe_wm *sw_wm;
> - struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
> + const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
> + int level, max_level = ilk_wm_max_level(dev_priv);
> + struct intel_plane *plane;
> u8 hw_enabled_slices;
> - const enum pipe pipe = crtc->pipe;
> - int plane, level, max_level = ilk_wm_max_level(dev_priv);
>
> if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
> return;
> @@ -9362,7 +9361,6 @@ static void verify_wm_state(struct intel_crtc *crtc,
> return;
>
> skl_pipe_wm_get_hw_state(crtc, &hw->wm);
> - sw_wm = &new_crtc_state->wm.skl.optimal;
>
> skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
>
> @@ -9375,21 +9373,21 @@ static void verify_wm_state(struct intel_crtc *crtc,
> dev_priv->dbuf.enabled_slices,
> hw_enabled_slices);
>
> - /* planes */
> - for_each_universal_plane(dev_priv, pipe, plane) {
> + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> + const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
> const struct skl_wm_level *hw_wm_level, *sw_wm_level;
>
> /* Watermarks */
> for (level = 0; level <= max_level; level++) {
> - hw_wm_level = &hw->wm.planes[plane].wm[level];
> - sw_wm_level = skl_plane_wm_level(sw_wm, plane, level);
> + hw_wm_level = &hw->wm.planes[plane->id].wm[level];
> + sw_wm_level = skl_plane_wm_level(sw_wm, plane->id,
> level);
>
> if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
> continue;
>
> drm_err(&dev_priv->drm,
> - "mismatch in WM pipe %c plane %d level %d
> (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> - pipe_name(pipe), plane + 1, level,
> + "[PLANE:%d:%s] mismatch in WM%d (expected e=%d
> b=%u l=%u, got e=%d b=%u l=%u)\n",
> + plane->base.base.id, plane->base.name, level,
> sw_wm_level->plane_en,
> sw_wm_level->plane_res_b,
> sw_wm_level->plane_res_l,
> @@ -9398,13 +9396,13 @@ static void verify_wm_state(struct intel_crtc *crtc,
> hw_wm_level->plane_res_l);
> }
>
> - hw_wm_level = &hw->wm.planes[plane].trans_wm;
> - sw_wm_level = skl_plane_trans_wm(sw_wm, plane);
> + hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
> + sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);
>
> if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
> drm_err(&dev_priv->drm,
> - "mismatch in trans WM pipe %c plane %d
> (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> - pipe_name(pipe), plane + 1,
> + "[PLANE:%d:%s] mismatch in trans WM (expected
> e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> + plane->base.base.id, plane->base.name,
> sw_wm_level->plane_en,
> sw_wm_level->plane_res_b,
> sw_wm_level->plane_res_l,
> @@ -9414,65 +9412,13 @@ static void verify_wm_state(struct intel_crtc *crtc,
> }
>
> /* DDB */
> - hw_ddb_entry = &hw->ddb_y[plane];
> - sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
> + hw_ddb_entry = &hw->ddb_y[plane->id];
> + sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
>
> if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
>
Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap
Am 01.03.21 um 10:21 schrieb Thomas Hellström (Intel): On 3/1/21 10:05 AM, Daniel Vetter wrote: On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) wrote: Hi, On 3/1/21 9:28 AM, Daniel Vetter wrote: On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) wrote: On 2/26/21 2:28 PM, Daniel Vetter wrote: So I think it stops gup. But I haven't verified at all. Would be good if Christian can check this with some direct io to a buffer in system memory. Hmm, Docs (again vm_normal_page() say) * VM_MIXEDMAP mappings can likewise contain memory with or without "struct * page" backing, however the difference is that _all_ pages with a struct * page (that is, those where pfn_valid is true) are refcounted and considered * normal pages by the VM. The disadvantage is that pages are refcounted * (which can be slower and simply not an option for some PFNMAP users). The * advantage is that we don't have to follow the strict linearity rule of * PFNMAP mappings in order to support COWable mappings. but it's true __vm_insert_mixed() ends up in the insert_pfn() path, so the above isn't really true, which makes me wonder if and in that case why there could any longer ever be a significant performance difference between MIXEDMAP and PFNMAP. Yeah it's definitely confusing. I guess I'll hack up a patch and see what sticks. BTW regarding the TTM hugeptes, I don't think we ever landed that devmap hack, so they are (for the non-gup case) relying on vma_is_special_huge(). For the gup case, I think the bug is still there. Maybe there's another devmap hack, but the ttm_vm_insert functions do use PFN_DEV and all that. And I think that stops gup_fast from trying to find the underlying page. -Daniel Hmm perhaps it might, but I don't think so. The fix I tried out was to set PFN_DEV | PFN_MAP for huge PTEs which causes pfn_devmap() to be true, and then follow_devmap_pmd()->get_dev_pagemap() which returns NULL and gup_fast() backs off, in the end that would mean setting in stone that "if there is a huge devmap page table entry for which we haven't registered any devmap struct pages (get_dev_pagemap returns NULL), we should treat that as a "special" huge page table entry". From what I can tell, all code calling get_dev_pagemap() already does that, it's just a question of getting it accepted and formalizing it. Oh I thought that's already how it works, since I didn't spot anything else that would block gup_fast from falling over. I guess really would need some testcases to make sure direct i/o (that's the easiest to test) fails like we expect. Yeah, IIRC the "| PFN_MAP" is the missing piece for TTM huge ptes. Otherwise pmd_devmap() will not return true and since there is no pmd_special() things break. Is that maybe the issue we have seen with amdgpu and huge pages? Apart from that I'm lost guys, that devmap and gup stuff is not something I have a good knowledge of apart from a one mile high view. Christian. /Thomas -Daniel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] -stable regression in Intel graphics, introduced in Linux 5.10.9
On Mon, Mar 01, 2021 at 11:11:13AM +0100, Diego Calleja wrote:
> El lunes, 1 de marzo de 2021 10:09:10 (CET) Greg KH escribió:
> > I do not see all 3 commits in Linus's tree already, am I missing
> > something?
> >
> > What are the git ids that you are looking at?
>
> I used grep on the git log, the commits are there but seem to have different
> commit ids (except for the first one)
>
> commit e627d5923cae93fa4188f4c4afba6486169a1337
> Author: Chris Wilson
> Date: Tue Jan 19 11:07:57 2021 +
>
> drm/i915/gt: One more flush for Baytrail clear residuals
>
>
> commit d5109f739c9f14a3bda249cb48b16de1065932f0
> Author: Chris Wilson
> Date: Mon Jan 25 22:02:47 2021 +
>
> drm/i915/gt: Flush before changing register state
>
>
> commit 81ce8f04aa96f7f6cae05770f68b5d15be91f5a2
> Author: Chris Wilson
> Date: Wed Feb 10 12:27:28 2021 +
>
> drm/i915/gt: Correct surface base address for renderclear
>
>
Ugh, have I mentioned recently just how badly I think the drm developers
handle their git trees? It's a constant mess to unwind that stuff...
{sigh}
Now queued up.
greg k-h
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Re: [Intel-gfx] [RFC PATCH 0/9] drm/i915/spi: discrete graphics internal spi
On Wed, 17 Feb 2021, "Winkler, Tomas" wrote: >> >> On Tue, 16 Feb 2021, Tomas Winkler wrote: >> > Intel discrete graphic devices have internal spi storage, that holds >> > firmware and oprom images. The spi device is exposed to the user space >> > via mtd framework to be accessed during manufacturing. >> > The device is hardware locked after manufacturing and only read access >> > is provided. >> > >> > The i915 plays role of a multi function device (mfd) and spi device is >> > exposed as its child device. i915_spi platform driver binds to this >> > device. >> > >> > Because the graphic card may undergo reset at any time and basically >> > hot unplug all its child devices, this series also provides a fix to >> > the mtd framework to make the reset graceful. >> > >> > Tomas Winkler (9): >> > drm/i915/spi: add spi device for discrete graphics >> > drm/i915/spi: intel_spi_region map >> > drm/i915/spi: add driver for on-die spi device >> > drm/i915/spi: implement region enumeration >> > drm/i915/spi: implement spi access functions >> > drm/i915/spi: spi register with mtd >> > drm/i915/spi: mtd: implement access handlers >> > drm/i915/spi: serialize spi access >> > mtd: use refcount to prevent corruption >> > >> > drivers/gpu/drm/i915/Kconfig | 3 + >> > drivers/gpu/drm/i915/Makefile| 6 + >> > drivers/gpu/drm/i915/i915_drv.c | 9 + >> > drivers/gpu/drm/i915/i915_drv.h | 4 + >> > drivers/gpu/drm/i915/i915_reg.h | 1 + >> > drivers/gpu/drm/i915/spi/intel_spi.c | 62 +++ >> > drivers/gpu/drm/i915/spi/intel_spi.h | 24 + >> >> I'm open to discussion, but after glancing through the series I've got a gut >> feeling spi/ subdir should be purely about the separate module, and the >> above two files should be in i915/ directory instead. > > Maybe, I don't have strong feelings about that, it is just a decision from > which point you want to look at that. *shrug* No strong feelings either, and I don't think the decision is carved in stone. We can move them around later if we want. Up to you. BR, Jani. >> >> As it is, I think it's a bit confusing that spi/ is both about the spi >> kernel module >> and a singly .c file that's really part of i915.ko. Perhaps that messes up >> the >> conventional descending to subdirs in the kernel build too? > > The intention was to make this capsulated from the file system point of view. > In general the spi driver could be somewhere in mtd directory, but it doesn't > really fit exactly there either. > I don't have a strong opinion about that, if you do I yield. > > > Thanks > Tomas > -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap
On Mon, Mar 1, 2021 at 11:17 AM Christian König wrote: > > > > Am 01.03.21 um 10:21 schrieb Thomas Hellström (Intel): > > > > On 3/1/21 10:05 AM, Daniel Vetter wrote: > >> On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) > >> wrote: > >>> Hi, > >>> > >>> On 3/1/21 9:28 AM, Daniel Vetter wrote: > On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) > wrote: > > On 2/26/21 2:28 PM, Daniel Vetter wrote: > >> So I think it stops gup. But I haven't verified at all. Would be > >> good > >> if Christian can check this with some direct io to a buffer in > >> system > >> memory. > > Hmm, > > > > Docs (again vm_normal_page() say) > > > > * VM_MIXEDMAP mappings can likewise contain memory with or > > without "struct > > * page" backing, however the difference is that _all_ pages > > with a struct > > * page (that is, those where pfn_valid is true) are refcounted > > and > > considered > > * normal pages by the VM. The disadvantage is that pages are > > refcounted > > * (which can be slower and simply not an option for some PFNMAP > > users). The > > * advantage is that we don't have to follow the strict > > linearity rule of > > * PFNMAP mappings in order to support COWable mappings. > > > > but it's true __vm_insert_mixed() ends up in the insert_pfn() > > path, so > > the above isn't really true, which makes me wonder if and in that > > case > > why there could any longer ever be a significant performance > > difference > > between MIXEDMAP and PFNMAP. > Yeah it's definitely confusing. I guess I'll hack up a patch and see > what sticks. > > > BTW regarding the TTM hugeptes, I don't think we ever landed that > > devmap > > hack, so they are (for the non-gup case) relying on > > vma_is_special_huge(). For the gup case, I think the bug is still > > there. > Maybe there's another devmap hack, but the ttm_vm_insert functions do > use PFN_DEV and all that. And I think that stops gup_fast from trying > to find the underlying page. > -Daniel > >>> Hmm perhaps it might, but I don't think so. The fix I tried out was > >>> to set > >>> > >>> PFN_DEV | PFN_MAP for huge PTEs which causes pfn_devmap() to be > >>> true, and > >>> then > >>> > >>> follow_devmap_pmd()->get_dev_pagemap() which returns NULL and > >>> gup_fast() > >>> backs off, > >>> > >>> in the end that would mean setting in stone that "if there is a huge > >>> devmap > >>> page table entry for which we haven't registered any devmap struct > >>> pages > >>> (get_dev_pagemap returns NULL), we should treat that as a "special" > >>> huge > >>> page table entry". > >>> > >>> From what I can tell, all code calling get_dev_pagemap() already > >>> does that, > >>> it's just a question of getting it accepted and formalizing it. > >> Oh I thought that's already how it works, since I didn't spot anything > >> else that would block gup_fast from falling over. I guess really would > >> need some testcases to make sure direct i/o (that's the easiest to test) > >> fails like we expect. > > > > Yeah, IIRC the "| PFN_MAP" is the missing piece for TTM huge ptes. > > Otherwise pmd_devmap() will not return true and since there is no > > pmd_special() things break. > > Is that maybe the issue we have seen with amdgpu and huge pages? Yeah, essentially when you have a hugepte inserted by ttm, and it happens to point at system memory, then gup will work on that. And create all kinds of havoc. > Apart from that I'm lost guys, that devmap and gup stuff is not > something I have a good knowledge of apart from a one mile high view. I'm not really better, hence would be good to do a testcase and see. This should provoke it: - allocate nicely aligned bo in system memory - mmap, again nicely aligned to 2M - do some direct io from a filesystem into that mmap, that should trigger gup - before the gup completes free the mmap and bo so that ttm recycles the pages, which should trip up on the elevated refcount. If you wait until the direct io is completely, then I think nothing bad can be observed. Ofc if your amdgpu+hugepte issue is something else, then maybe we have another issue. Also usual caveat: I'm not an mm hacker either, so might be completely wrong. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [5.10.y regression] i915 clear-residuals mitigation is causing gfx issues
On Mon, Feb 15, 2021 at 03:26:59PM +0100, Greg Kroah-Hartman wrote:
> On Sun, Feb 14, 2021 at 05:00:44PM +0100, Hans de Goede wrote:
> > Hi,
> >
> > On 2/11/21 1:26 PM, Hans de Goede wrote:
> > > Hi,
> > >
> > > On 2/11/21 11:49 AM, Chris Wilson wrote:
> > >> Quoting Hans de Goede (2021-02-11 10:36:13)
> > >>> Hi,
> > >>>
> > >>> On 2/10/21 1:48 PM, Chris Wilson wrote:
> > Quoting Hans de Goede (2021-02-10 10:37:19)
> > > Hi,
> > >
> > > On 2/10/21 12:07 AM, Chris Wilson wrote:
> > >> Quoting Hans de Goede (2021-02-09 11:46:46)
> > >>> Hi,
> > >>>
> > >>> On 2/9/21 12:27 AM, Chris Wilson wrote:
> > Quoting Hans de Goede (2021-02-08 20:38:58)
> > > Hi All,
> > >
> > > We (Fedora) have been receiving reports from multiple users about
> > > gfx issues / glitches
> > > stating with 5.10.9. All reporters are users of Ivy Bridge /
> > > Haswell iGPUs and all
> > > reporters report that adding i915.mitigations=off to the cmdline
> > > fixes things, see:
> >
> > I tried to reproduce this on the w/e on hsw-gt1, to no avail; and
> > piglit
> > did not report any differences with and without mitigations. I
> > have yet
> > to test other platforms. So I don't yet have an alternative.
> > >>>
> > >>> Note the original / first reporter of:
> > >>>
> > >>> https://bugzilla.redhat.com/show_bug.cgi?id=1925346
> > >>>
> > >>> Is using hsw-gt2, so it seems that the problem is not just the
> > >>> enabling of
> > >>> the mitigations on ivy-bridge / bay-trail but that there actually is
> > >>> a regression on devices where the WA worked fine before...
> > >>
> > >> There have been 3 crashes uploaded related to v5.10.9, and in all 3
> > >> cases the ACTHD has been in the first page. This strongly suggests
> > >> that
> > >> the w/a is scribbling over address 0. And there's then a very good
> > >> chance that
> > >>
> > >> commit 29d35b73ead4e41aa0d1a954c9bfbdce659ec5d6
> > >> Author: Chris Wilson
> > >> Date: Mon Jan 25 12:50:33 2021 +
> > >>
> > >> drm/i915/gt: Always try to reserve GGTT address 0x0
> > >>
> > >> commit 489140b5ba2e7cc4b853c29e0591895ddb462a82 upstream.
> > >>
> > >> in v5.10.14 is sufficient to hide the issue.
> > >
> > > That one actually is already in v5.10.13 and the various reportes of
> > > these
> > > issues have already tested 5.10.13. They did mention that it took
> > > longer
> > > to reproduce with 5.10.13 then with 5.10.10, but that could also be
> > > due to:
> > >
> > > "drm/i915/gt: Clear CACHE_MODE prior to clearing residuals"
> > > https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.10.y&id=520d05a77b2866eb4cb9e548e1d8c8abcfe60ec5
> >
> > Started looking for scratch page overwrites, and found this little gem:
> > https://patchwork.freedesktop.org/patch/420436/?series=86947&rev=1
> >
> > Looks promising wrt the cause of overwriting random addresses -- and
> > I hope that is the explanation for the glitches/hangs. I have a hsw gt2
> > with gnome shell, piglit is happy, but I suspect it is all due to
> > placement and so will only occur at random.
> > >>>
> > >>> If you can give me a list of commits to cherry-pick then I can prepare
> > >>> a Fedora 5.10.y kernel which those added for the group of Fedora users
> > >>> who are hitting this to test.
> > >>
> > >> e627d5923cae ("drm/i915/gt: One more flush for Baytrail clear residuals")
> > >> d30bbd62b1bf ("drm/i915/gt: Flush before changing register state")
> > >> 1914911f4aa0 ("drm/i915/gt: Correct surface base address for
> > >> renderclear")
> > >
> > > Thanks, the test-kernel is building now. I will let you know when I have
> > > heard back from the Fedora users (this will likely take 1-2 days).
> >
> > I've heard back from 2 of the reporters who were seeing issues with 5.10.9+
> >
> > And I'm happy to report 5.10.15 + the 3 commits mentioned above
> > cherry-picked
> > on top fixes the graphics glitches for them.
> >
> > So if we can get these 3 commits into 5.10.y and 5.11.y then this should be
> > resolved.
>
> Great!
>
> Hopefully these will show up in Linus's tree soon...
I think I have the needed 3 commits now.
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Re: [Intel-gfx] -stable regression in Intel graphics, introduced in Linux 5.10.9
El domingo, 28 de febrero de 2021 16:14:54 (CET) Greg KH escribió: > Is this the same issue reported here: > > https://lore.kernel.org/r/f1070486-891a-8ec0-0390-b9aeb0317...@redhat.com > ? I just tested current mainline (which already contains the three commits mentioned in the bugzilla), and the problems have disappeared. Regards. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] -stable regression in Intel graphics, introduced in Linux 5.10.9
El lunes, 1 de marzo de 2021 10:09:10 (CET) Greg KH escribió: > I do not see all 3 commits in Linus's tree already, am I missing > something? > > What are the git ids that you are looking at? I used grep on the git log, the commits are there but seem to have different commit ids (except for the first one) commit e627d5923cae93fa4188f4c4afba6486169a1337 Author: Chris Wilson Date: Tue Jan 19 11:07:57 2021 + drm/i915/gt: One more flush for Baytrail clear residuals commit d5109f739c9f14a3bda249cb48b16de1065932f0 Author: Chris Wilson Date: Mon Jan 25 22:02:47 2021 + drm/i915/gt: Flush before changing register state commit 81ce8f04aa96f7f6cae05770f68b5d15be91f5a2 Author: Chris Wilson Date: Wed Feb 10 12:27:28 2021 + drm/i915/gt: Correct surface base address for renderclear ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] -stable regression in Intel graphics, introduced in Linux 5.10.9
Hi, There is a regression in Linux 5.10.9 that does not happen in 5.10.8. It is still there as of 5.11.1 This regression consists in graphics artifacts that will *only* start appearing after resuming from suspend. They don't happen immediately after resuming from suspend either, but after some minutes. My system has integrated intel graphics 00:02.0 VGA compatible controller: Intel Corporation 4th Generation Core Processor Family Integrated Graphics Controller (rev 06) (prog-if 00 [VGA controller]) CPU: Intel(R) Core(TM) i3-4170T CPU @ 3.20GHz For reference, this is the list of i915 commits that went into 5.10.9. commit ecca0c675bdecebdeb2f2eb76fb33520c441dacf Author: Chris Wilson Date: Mon Jan 11 22:52:19 2021 + drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail commit 09aa9e45863e9e25dfbf350bae89fc3c2964482c upstream. commit de3f572607c29f7fdd1bfd754646d08e32db0249 Author: Imre Deak Date: Wed Dec 9 17:39:52 2020 +0200 drm/i915/icl: Fix initing the DSI DSC power refcount during HW readout commit 2af5268180410b874fc06be91a1b2fbb22b1be0c upstream. commit 54c9246a47fa8559c3ec6da2048e976a4b8750f6 Author: Hans de Goede Date: Wed Nov 18 13:40:58 2020 +0100 drm/i915/dsi: Use unconditional msleep for the panel_on_delay when there is no reset-deassert MIPI-sequence commit 00cb645fd7e29bdd20967cd20fa8f77bcdf422f9 upstream. commit 0a34addcdbd9e03e3f3d09bcd5a1719d90b2d637 Author: Jani Nikula Date: Fri Jan 8 17:28:41 2021 +0200 drm/i915/backlight: fix CPU mode backlight takeover on LPT commit bb83d5fb550bb7db75b29e6342417fda2bbb691c upstream. commit 48b8c6689efa7cd65a72f620940a4f234b944b73 Author: Chris Wilson Date: Mon Jan 11 22:52:18 2021 + drm/i915/gt: Limit VFE threads based on GT commit ffaf97899c4a58b9fefb11534f730785443611a8 upstream. commit 481e27f050732b8c680f26287dd44967fddf9a79 Author: Chris Wilson Date: Mon Jan 11 22:52:20 2021 + drm/i915: Allow the sysadmin to override security mitigations commit 984cadea032b103c5824a5f29d0a36b3e9df6333 upstream. Regards ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/display/vlv_dsi: Do no shut down displays on reboot if a DSI panel is used
After the recently added commit fe0f1e3bfdfe ("drm/i915: Shut down
displays gracefully on reboot"), the DSI panel on a Cherry Trail based
Predia Basic tablet would no longer properly light up after reboot.
The backlight still turns back on after reboot, but the LCD shows an
all black display. The display is also all black during the time that
EFI / the GOP is managing it, so e.g. the grub menu also is not visible.
In this scenario the panel is initialized so that it appears to be working
and the fastboot code skips doing a modeset. Forcing a modeset by doing a
chvt to a text-console over ssh followed by echo-ing 1 and then 0 to
/sys/class/graphics/fb0/blank causes the panel to work again.
Add a QUIRK_SKIP_SHUTDOWN quirk which turns i915_driver_shutdown() into
a no-op when set; and set this on vlv/chv devices when a DSI panel is
detected, to work around this.
Admittedly this is a bit of a big hammer, but these platforms have been
around for quite some time now and they have always worked fine without
the new behavior to shutdown everything on shutdown/reboot. This approach
simply disables the recently introduced new shutdown behavior in this
specific case where it is known to cause problems. Which is a nice and
simple way to deal with this.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/display/vlv_dsi.c | 3 +++
drivers/gpu/drm/i915/i915_drv.c| 3 +++
drivers/gpu/drm/i915/i915_drv.h| 1 +
3 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
b/drivers/gpu/drm/i915/display/vlv_dsi.c
index f94025ec603a..792ef868b6af 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1949,6 +1949,9 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
vlv_dsi_add_properties(intel_connector);
+ /* Some BIOS-es fail to re-init the DSI panel on reboot if we turn it
off */
+ dev_priv->quirks |= QUIRK_SKIP_SHUTDOWN;
+
return;
err_cleanup_connector:
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8e9cb44e66e5..92f2af55af6d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1048,6 +1048,9 @@ static void intel_shutdown_encoders(struct
drm_i915_private *dev_priv)
void i915_driver_shutdown(struct drm_i915_private *i915)
{
+ if (i915->quirks & QUIRK_SKIP_SHUTDOWN)
+ return;
+
disable_rpm_wakeref_asserts(&i915->runtime_pm);
i915_gem_suspend(i915);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 26d69d06aa6d..272cd7cb22d4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -517,6 +517,7 @@ struct i915_psr {
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
#define QUIRK_INCREASE_T12_DELAY (1<<6)
#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
+#define QUIRK_SKIP_SHUTDOWN (1<<8)
struct intel_fbdev;
struct intel_fbc_work;
--
2.30.1
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display/vlv_dsi: Do no shut down displays on reboot if a DSI panel is used
== Series Details == Series: drm/i915/display/vlv_dsi: Do no shut down displays on reboot if a DSI panel is used URL : https://patchwork.freedesktop.org/series/87498/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3994974850ed drm/i915/display/vlv_dsi: Do no shut down displays on reboot if a DSI panel is used -:69: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #69: FILE: drivers/gpu/drm/i915/i915_drv.h:486: +#define QUIRK_SKIP_SHUTDOWN (1<<8) ^ total: 0 errors, 0 warnings, 1 checks, 25 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] 2021 X.Org Board of Directions Nomination period ends next Sunday
Unfortunately my previous email seems to not have been received by many people. I will send this email separately to each mailing list to hopefully get better coverage. The nomination period is currently ongoing. So far we have received 3 nominations and will need at least 4 to fill the vacant spots on the board. We hope you will consider putting your nomination forward. To nominate yourself or someone else please send the nomination, along with a personal statement to elections at x dot org. ** Election Schedule ** Nomination period Start: Mon 22nd February Nomination period End: Sun 7th March Deadline of X.Org membership application or renewal: Thu 11th March Publication of Candidates & start of Candidate QA: Mon 15th March Election Planned Start: Mon 22nd March anywhere on earth Election Planned End: Sun 4th April anywhere on earth ** Election Committee ** * Eric Anholt * Mark Filion * Keith Packard * Harry Wentland Cheers, Harry Wentland, on behalf of the X.Org elections committee ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/vlv_dsi: Do no shut down displays on reboot if a DSI panel is used
== Series Details ==
Series: drm/i915/display/vlv_dsi: Do no shut down displays on reboot if a DSI
panel is used
URL : https://patchwork.freedesktop.org/series/87498/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9818 -> Patchwork_19736
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_19736 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19736, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19736:
### IGT changes ###
Warnings
* igt@gem_tiled_blits@basic:
- fi-kbl-8809g: [TIMEOUT][1] ([i915#2502]) -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@workarounds:
- {fi-cml-drallion}: NOTRUN -> [INCOMPLETE][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/fi-cml-drallion/igt@i915_selftest@l...@workarounds.html
Known issues
Here are the changes found in Patchwork_19736 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +2 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-apl-guc: NOTRUN -> [SKIP][7] ([fdo#109271]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/fi-apl-guc/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-y: NOTRUN -> [SKIP][8] ([i915#2190])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/fi-icl-y/igt@gem_huc_c...@huc-copy.html
* igt@i915_hangman@error-state-basic:
- fi-apl-guc: NOTRUN -> [DMESG-WARN][9] ([i915#1610])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/fi-apl-guc/igt@i915_hang...@error-state-basic.html
* igt@i915_selftest@live@hangcheck:
- fi-icl-y: NOTRUN -> [INCOMPLETE][10] ([i915#2782] / [i915#926])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/fi-icl-y/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-y: NOTRUN -> [SKIP][11] ([fdo#109284] / [fdo#111827]) +8
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/fi-icl-y/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-bsw-n3050: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/fi-bsw-n3050/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-y: NOTRUN -> [SKIP][13] ([fdo#109285])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/fi-icl-y/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-icl-y: NOTRUN -> [SKIP][14] ([fdo#109278])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/fi-icl-y/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-bsw-n3050: NOTRUN -> [SKIP][15] ([fdo#109271]) +39 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/fi-bsw-n3050/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html
* igt@kms_psr@primary_mmap_gtt:
- fi-icl-y: NOTRUN -> [SKIP][16] ([fdo#110189]) +3 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/fi-icl-y/igt@kms_psr@primary_mmap_gtt.html
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> [FAIL][17] ([i915#2426])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/fi-apl-guc/igt@run...@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][18] ([i915#1602] / [i915#2029] /
[i915#2369])
[18]:
https
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/vlv_dsi: Do no shut down displays on reboot if a DSI panel is used
== Series Details == Series: drm/i915/display/vlv_dsi: Do no shut down displays on reboot if a DSI panel is used URL : https://patchwork.freedesktop.org/series/87498/ State : success == Summary == CI Bug Log - changes from CI_DRM_9818_full -> Patchwork_19736_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/index.html Changes --- No changes found Participating hosts (10 -> 8) -- Missing(2): pig-kbl-iris pig-icl-1065g7 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_9818 -> Patchwork_19736 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_9818: fb3b93df7979b1cf6b69ac801d1703c0bf1dde66 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6016: 2107b0a53692fb329175bc16169c3699712187aa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19736: 3994974850ed2374a0868f4365991853bef22c48 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19736/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [WARNING] v5.12-rc1 in intel_pipe_disable tracepoint
On my test box with latest v5.12-rc1, running with all trace events enabled, I consistently trigger this warning. It appears to get triggered by the trace_intel_pipe_disable() code. -- Steve [ cut here ] i915 :00:02.0: drm_WARN_ON_ONCE(drm_drv_uses_atomic_modeset(dev)) WARNING: CPU: 7 PID: 1258 at drivers/gpu/drm/drm_vblank.c:728 drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x319/0x330 [drm] Modules linked in: ebtable_filter ebtables bridge stp llc vsock vmw_vmci ipt_REJECT nf_reject_ipv4 iptable_filter ip6t_REJECT nf_reject_ipv6 xt_state xt_conntrack nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 ip6table_filter ip6_tables snd_hda_codec_hdmi snd_h ek snd_hda_codec_generic ledtrig_audio snd_hda_intel snd_intel_dspcfg snd_hda_codec joydev snd_hwdep intel_rapl_msr snd_hda_core hp_wmi i915 iTCO_wdt snd_seq intel_rapl_common iTCO_vendor_support wmi_bmof sparse_keymap snd_seq_device rfkill snd_pcm x86_pkg_t d_timer i2c_algo_bit drm_kms_helper mei_me intel_powerclamp snd mei soundcore i2c_i801 drm coretemp lpc_ich e1000e kvm_intel i2c_smbus kvm irqbypass crct10dif_pclmul crc32_pclmul crc32c_intel serio_raw ghash_clmulni_intel video tpm_infineon wmi ip_tables CPU: 7 PID: 1258 Comm: Xorg Tainted: GW 5.12.0-rc1-test+ #12 Hardware name: Hewlett-Packard HP Compaq Pro 6300 SFF/339A, BIOS K01 v03.03 07/14/2016 RIP: 0010:drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x319/0x330 [drm] Code: 4c 8b 6f 50 4d 85 ed 75 03 4c 8b 2f e8 60 92 45 c2 48 c7 c1 28 a5 3c c0 4c 89 ea 48 c7 c7 15 5a 3c c0 48 89 c6 e8 1f e7 7b c2 <0f> 0b e9 e2 fe ff ff e8 fb 6c 81 c2 66 66 2e 0f 1f 84 00 00 00 00 RSP: 0018:b77580ea7920 EFLAGS: 00010082 RAX: RBX: 8afe500c RCX: RDX: 0004 RSI: 833c86b8 RDI: 0001 RBP: b77580ea7990 R08: 00700c782173 R09: R10: 0001 R11: 0001 R12: R13: 8afe41c7eff0 R14: c05e0410 R15: 8afe456a2bf8 FS: 7f8f91869f00() GS:8afe5aa0() knlGS: CS: 0010 DS: ES: CR0: 80050033 CR2: 7f9523a6cad0 CR3: 01b78002 CR4: 001706e0 Call Trace: drm_get_last_vbltimestamp+0xaa/0xc0 [drm] drm_update_vblank_count+0x90/0x2d0 [drm] drm_crtc_accurate_vblank_count+0x3e/0xc0 [drm] intel_crtc_get_vblank_counter+0x43/0x50 [i915] trace_event_raw_event_intel_pipe_disable+0x87/0x110 [i915] intel_disable_pipe+0x1a8/0x210 [i915] ilk_crtc_disable+0x85/0x390 [i915] intel_old_crtc_state_disables.isra.0+0x5c/0x110 [i915] intel_atomic_commit_tail+0xf5d/0x1460 [i915] ? complete+0x18/0x40 intel_atomic_commit+0x345/0x3c0 [i915] drm_atomic_connector_commit_dpms+0xd7/0x100 [drm] set_property_atomic+0xcc/0x160 [drm] drm_mode_obj_set_property_ioctl+0xbd/0x100 [drm] ? drm_connector_set_obj_prop+0x90/0x90 [drm] drm_connector_property_set_ioctl+0x39/0x60 [drm] drm_ioctl_kernel+0xad/0x100 [drm] drm_ioctl+0x1ec/0x390 [drm] ? drm_connector_set_obj_prop+0x90/0x90 [drm] ? sched_clock_cpu+0x10/0xd0 ? lock_release+0x155/0x410 __x64_sys_ioctl+0x83/0xb0 do_syscall_64+0x33/0x40 entry_SYSCALL_64_after_hwframe+0x44/0xae RIP: 0033:0x7f8f91ce535b Code: 0f 1e fa 48 8b 05 2d 9b 0c 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 0f 1f 44 00 00 f3 0f 1e fa b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d fd 9a 0c 00 f7 d8 64 89 01 48 RSP: 002b:7ffcb4603378 EFLAGS: 0246 ORIG_RAX: 0010 RAX: ffda RBX: 7ffcb46033b0 RCX: 7f8f91ce535b RDX: 7ffcb46033b0 RSI: c01064ab RDI: 000e RBP: c01064ab R08: 55d68f44ba60 R09: R10: 55d68f44ba60 R11: 0246 R12: 55d68f5e0010 R13: 000e R14: R15: 55d68e2275c0 ---[ end trace d18216ba28a2f0e8 ]--- ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [WARNING] v5.12-rc1 in intel_pipe_disable tracepoint
On Mon, Mar 01, 2021 at 11:59:46AM -0500, Steven Rostedt wrote: > > On my test box with latest v5.12-rc1, running with all trace events > enabled, I consistently trigger this warning. > > It appears to get triggered by the trace_intel_pipe_disable() code. > > -- Steve > > [ cut here ] > i915 :00:02.0: drm_WARN_ON_ONCE(drm_drv_uses_atomic_modeset(dev)) > WARNING: CPU: 7 PID: 1258 at drivers/gpu/drm/drm_vblank.c:728 > drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x319/0x330 [drm] > Modules linked in: ebtable_filter ebtables bridge stp llc vsock vmw_vmci > ipt_REJECT nf_reject_ipv4 iptable_filter ip6t_REJECT nf_reject_ipv6 xt_state > xt_conntrack nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 ip6table_filter > ip6_tables snd_hda_codec_hdmi snd_h > ek snd_hda_codec_generic ledtrig_audio snd_hda_intel snd_intel_dspcfg > snd_hda_codec joydev snd_hwdep intel_rapl_msr snd_hda_core hp_wmi i915 > iTCO_wdt snd_seq intel_rapl_common iTCO_vendor_support wmi_bmof sparse_keymap > snd_seq_device rfkill snd_pcm x86_pkg_t > d_timer i2c_algo_bit drm_kms_helper mei_me intel_powerclamp snd mei soundcore > i2c_i801 drm coretemp lpc_ich e1000e kvm_intel i2c_smbus kvm irqbypass > crct10dif_pclmul crc32_pclmul crc32c_intel serio_raw ghash_clmulni_intel > video tpm_infineon wmi ip_tables > CPU: 7 PID: 1258 Comm: Xorg Tainted: GW 5.12.0-rc1-test+ #12 > Hardware name: Hewlett-Packard HP Compaq Pro 6300 SFF/339A, BIOS K01 v03.03 > 07/14/2016 > RIP: 0010:drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x319/0x330 > [drm] > Code: 4c 8b 6f 50 4d 85 ed 75 03 4c 8b 2f e8 60 92 45 c2 48 c7 c1 28 a5 3c > c0 4c 89 ea 48 c7 c7 15 5a 3c c0 48 89 c6 e8 1f e7 7b c2 <0f> 0b e9 e2 fe ff > ff e8 fb 6c 81 c2 66 66 2e 0f 1f 84 00 00 00 00 > RSP: 0018:b77580ea7920 EFLAGS: 00010082 > RAX: RBX: 8afe500c RCX: > RDX: 0004 RSI: 833c86b8 RDI: 0001 > RBP: b77580ea7990 R08: 00700c782173 R09: > R10: 0001 R11: 0001 R12: > R13: 8afe41c7eff0 R14: c05e0410 R15: 8afe456a2bf8 > FS: 7f8f91869f00() GS:8afe5aa0() knlGS: > CS: 0010 DS: ES: CR0: 80050033 > CR2: 7f9523a6cad0 CR3: 01b78002 CR4: 001706e0 > Call Trace: > drm_get_last_vbltimestamp+0xaa/0xc0 [drm] > drm_update_vblank_count+0x90/0x2d0 [drm] > drm_crtc_accurate_vblank_count+0x3e/0xc0 [drm] > intel_crtc_get_vblank_counter+0x43/0x50 [i915] > trace_event_raw_event_intel_pipe_disable+0x87/0x110 [i915] > intel_disable_pipe+0x1a8/0x210 [i915] Hmm. Yeah we do vblank_off() before pipe_disable() which wants to still grab the frame counter in the tracepoint. I think we could reorder those two without causing any problems. Either that or we put the tracepoint before vblank_off(). > ilk_crtc_disable+0x85/0x390 [i915] But this part is confusing me. intel_crtc_get_vblank_counter() is only supposed to do drm_crtc_accurate_vblank_count() fallback when the hardware lacks a working frame counter, and that should only be the case for ancient gen2 or semi-ancient i965gm TV output, ilk_crtc_disable() is not the function we should be calling in either of those cases. What hardware do you have? > intel_old_crtc_state_disables.isra.0+0x5c/0x110 [i915] > intel_atomic_commit_tail+0xf5d/0x1460 [i915] > ? complete+0x18/0x40 > intel_atomic_commit+0x345/0x3c0 [i915] > drm_atomic_connector_commit_dpms+0xd7/0x100 [drm] > set_property_atomic+0xcc/0x160 [drm] > drm_mode_obj_set_property_ioctl+0xbd/0x100 [drm] > ? drm_connector_set_obj_prop+0x90/0x90 [drm] > drm_connector_property_set_ioctl+0x39/0x60 [drm] > drm_ioctl_kernel+0xad/0x100 [drm] > drm_ioctl+0x1ec/0x390 [drm] > ? drm_connector_set_obj_prop+0x90/0x90 [drm] > ? sched_clock_cpu+0x10/0xd0 > ? lock_release+0x155/0x410 > __x64_sys_ioctl+0x83/0xb0 > do_syscall_64+0x33/0x40 > entry_SYSCALL_64_after_hwframe+0x44/0xae > RIP: 0033:0x7f8f91ce535b > Code: 0f 1e fa 48 8b 05 2d 9b 0c 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff > ff c3 66 0f 1f 44 00 00 f3 0f 1e fa b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff > 73 01 c3 48 8b 0d fd 9a 0c 00 f7 d8 64 89 01 48 > RSP: 002b:7ffcb4603378 EFLAGS: 0246 ORIG_RAX: 0010 > RAX: ffda RBX: 7ffcb46033b0 RCX: 7f8f91ce535b > RDX: 7ffcb46033b0 RSI: c01064ab RDI: 000e > RBP: c01064ab R08: 55d68f44ba60 R09: > R10: 55d68f44ba60 R11: 0246 R12: 55d68f5e0010 > R13: 000e R14: R15: 55d68e2275c0 > ---[ end trace d18216ba28a2f0e8 ]--- > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Ville Syrjälä Intel
Re: [Intel-gfx] [WARNING] v5.12-rc1 in intel_pipe_disable tracepoint
On Mon, 1 Mar 2021 19:20:59 +0200 Ville Syrjälä wrote: > > ilk_crtc_disable+0x85/0x390 [i915] > > But this part is confusing me. intel_crtc_get_vblank_counter() is > only supposed to do drm_crtc_accurate_vblank_count() fallback when > the hardware lacks a working frame counter, and that should only > be the case for ancient gen2 or semi-ancient i965gm TV output, > ilk_crtc_disable() is not the function we should be calling in > either of those cases. > > What hardware do you have? > According to "lspci -vvv" 00:02.0 VGA compatible controller: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor Graphics Controller (rev 09) (prog-if 00 [VGA controller]) DeviceName: Onboard VGA Subsystem: Hewlett-Packard Company Device 339a Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 00/16] Introduce Intel PXP
PXP (Protected Xe Path) is an i915 component, available on GEN12+, that helps to establish the hardware protected session and manage the status of the alive software session, as well as its life cycle. Several major functional changes compared to v1: - Termination is issued on runtime resume as well. - Protected objects and contexts are marked as invalid on termination. Invalid contexts are reported to userspace via RESET_STATS. - Trying to flip an invalid objects results in a black frame. I've done more testing compared to v1 (initial IGTs from Alan will be hitting the ML soon), but I still haven't stress-tested with userspace applications, so there might be bugs. I'll make sure to run more testing and fix everything before merge, but in the meantime I wanted to get forward with the reviews given that the current tests give me enough confidence that this isn't completely broken. Cc: Gaurav Kumar Cc: Chris Wilson Cc: Rodrigo Vivi Cc: Joonas Lahtinen Cc: Juston Li Cc: Alan Previn Cc: Lionel Landwerlin Anshuman Gupta (2): drm/i915/pxp: Add plane decryption support drm/i915/pxp: black pixels on pxp disabled Bommu Krishnaiah (2): drm/i915/uapi: introduce drm_i915_gem_create_ext drm/i915/pxp: User interface for Protected buffer Daniele Ceraolo Spurio (6): drm/i915/pxp: Define PXP component interface drm/i915/pxp: define PXP device flag and kconfig drm/i915/pxp: allocate a vcs context for pxp usage drm/i915/pxp: set KCR reg init during the boot time drm/i915/pxp: interface for creation of protected contexts drm/i915/pxp: enable PXP for integrated Gen12 Huang, Sean Z (5): drm/i915/pxp: Implement funcs to create the TEE channel drm/i915/pxp: Create the arbitrary session after boot drm/i915/pxp: Implement arb session teardown drm/i915/pxp: Implement PXP irq handler drm/i915/pxp: Enable PXP power management Vitaly Lubart (1): mei: pxp: export pavp client to me client bus drivers/gpu/drm/i915/Kconfig | 11 + drivers/gpu/drm/i915/Makefile | 9 + .../drm/i915/display/skl_universal_plane.c| 50 +++- drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 - drivers/gpu/drm/i915/gem/i915_gem_context.h | 18 ++ .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 + drivers/gpu/drm/i915/gem/i915_gem_create.c| 68 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 23 ++ drivers/gpu/drm/i915/gem/i915_gem_object.c| 6 + drivers/gpu/drm/i915/gem/i915_gem_object.h| 12 + .../gpu/drm/i915/gem/i915_gem_object_types.h | 13 + drivers/gpu/drm/i915/gt/intel_engine.h| 10 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 19 +- drivers/gpu/drm/i915/gt/intel_gt.c| 5 + drivers/gpu/drm/i915/gt/intel_gt_irq.c| 7 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 14 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + drivers/gpu/drm/i915/i915_drv.c | 4 +- drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_pci.c | 2 + drivers/gpu/drm/i915/i915_reg.h | 48 drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/pxp/intel_pxp.c | 215 drivers/gpu/drm/i915/pxp/intel_pxp.h | 70 ++ drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 166 + drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++ drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 153 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 33 +++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 99 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 33 +++ drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 140 +++ drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 18 ++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 199 +++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 17 ++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 38 +++ drivers/misc/mei/Kconfig | 2 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/pxp/Kconfig | 13 + drivers/misc/mei/pxp/Makefile | 7 + drivers/misc/mei/pxp/mei_pxp.c| 230 ++ drivers/misc/mei/pxp/mei_pxp.h| 18 ++ include/drm/i915_component.h | 1 + include/drm/i915_pxp_tee_interface.h | 45 include/uapi/drm/i915_drm.h | 92 +++ 44 files changed, 1972 insertions(+), 21 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c create mode 100644 drivers/gpu/
[Intel-gfx] [PATCH v2 01/16] drm/i915/pxp: Define PXP component interface
This will be used for communication between the i915 driver and the mei
one. Defining it in a stand-alone patch to avoid circualr dependedencies
between the patches modifying the 2 drivers.
Split out from an original patch from Huang, Sean Z
v2: rename the component struct (Rodrigo)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
---
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45
2 files changed, 46 insertions(+)
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 55c3b123581b..c1e2a43d2d1e 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -29,6 +29,7 @@
enum i915_component_type {
I915_COMPONENT_AUDIO = 1,
I915_COMPONENT_HDCP,
+ I915_COMPONENT_PXP
};
/* MAX_PORT is the number of port
diff --git a/include/drm/i915_pxp_tee_interface.h
b/include/drm/i915_pxp_tee_interface.h
new file mode 100644
index ..09b8389152af
--- /dev/null
+++ b/include/drm/i915_pxp_tee_interface.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart
+ */
+
+#ifndef _I915_PXP_TEE_INTERFACE_H_
+#define _I915_PXP_TEE_INTERFACE_H_
+
+#include
+#include
+
+/**
+ * struct i915_pxp_component_ops - ops for PXP services.
+ * @owner: Module providing the ops
+ * @send: sends data to PXP
+ * @receive: receives data from PXP
+ */
+struct i915_pxp_component_ops {
+ /**
+* @owner: owner of the module provding the ops
+*/
+ struct module *owner;
+
+ int (*send)(struct device *dev, const void *message, size_t size);
+ int (*recv)(struct device *dev, void *buffer, size_t size);
+};
+
+/**
+ * struct i915_pxp_component - Used for communication between i915 and TEE
+ * drivers for the PXP services
+ * @tee_dev: device that provide the PXP service from TEE Bus.
+ * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
+ */
+struct i915_pxp_component {
+ struct device *tee_dev;
+ const struct i915_pxp_component_ops *ops;
+
+ /* To protect the above members. */
+ struct mutex mutex;
+};
+
+#endif /* _I915_TEE_PXP_INTERFACE_H_ */
--
2.29.2
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[Intel-gfx] [PATCH v2 02/16] mei: pxp: export pavp client to me client bus
From: Vitaly Lubart
Export PAVP client to work with i915 driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index f5fd5b786607..0e0bcd0da852 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -47,3 +47,5 @@ config INTEL_MEI_TXE
Intel Bay Trail
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index f1c76f7ee804..d8e5165917f2 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index ..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index ..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index ..42021920bc84
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .recv = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_component *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_maste
[Intel-gfx] [PATCH v2 03/16] drm/i915/pxp: define PXP device flag and kconfig
Ahead of the PXP implementation, define the relevant define flag and
kconfig option.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Kconfig | 11 +++
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 1e1cb245fca7..c55e58bdbe0b 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -130,6 +130,17 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12+ platform"
+ depends on DRM_I915
+ depends on INTEL_MEI && INTEL_MEI_PXP
+ default y
+ help
+ PXP (Protected Xe Path) is an i915 component, available on GEN12+
+ GPUs, that helps to establish the hardware protected session and
+ manage the status of the alive software session, as well as its life
+ cycle.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f8413b3b9da8..ae3d92acddfd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1742,6 +1742,10 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
#define HAS_VRR(i915) (INTEL_GEN(i915) >= 12)
+#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \
+ INTEL_INFO(dev_priv)->has_pxp) && \
+ VDBOX_MASK(&dev_priv->gt)
+
/* Only valid when HAS_DISPLAY() is true */
#define INTEL_DISPLAY_ENABLED(dev_priv) \
(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),
!(dev_priv)->params.disable_display)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index d44f64b57b7a..8cd9cb841c3e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -126,6 +126,7 @@ enum intel_ppgtt_type {
func(has_logical_ring_elsq); \
func(has_master_unit_irq); \
func(has_pooled_eu); \
+ func(has_pxp); \
func(has_rc6); \
func(has_rc6p); \
func(has_rps); \
--
2.29.2
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[Intel-gfx] [PATCH v2 04/16] drm/i915/pxp: allocate a vcs context for pxp usage
The context is required to send the session termination commands to the
VCS, which will be implemented in a follow-up patch. We can also use the
presence of the context as a check of pxp initialization completion.
v2: use perma-pinned context (Chris)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 4 ++
drivers/gpu/drm/i915/gt/intel_engine.h | 10
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 19 ---
drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 64 ++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 35
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 15 +
8 files changed, 146 insertions(+), 9 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4554f10a0fc7..8bcdd708d5c9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -270,6 +270,10 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index c530839627bb..4719cdf541cf 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -21,6 +21,7 @@
struct drm_printer;
struct intel_gt;
+struct lock_class_key;
/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
* but keeps the logic simple. Indeed, the whole purpose of this macro is just
@@ -170,6 +171,8 @@ intel_write_status_page(struct intel_engine_cs *engine, int
reg, u32 value)
#define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32))
#define I915_GEM_HWS_SEQNO 0x40
#define I915_GEM_HWS_SEQNO_ADDR(I915_GEM_HWS_SEQNO *
sizeof(u32))
+#define I915_GEM_HWS_PXP 0x60
+#define I915_GEM_HWS_PXP_ADDR (I915_GEM_HWS_PXP * sizeof(u32))
#define I915_GEM_HWS_SCRATCH 0x80
#define I915_HWS_CSB_BUF0_INDEX0x10
@@ -232,6 +235,13 @@ ktime_t intel_engine_get_busy_time(struct intel_engine_cs
*engine,
u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
+struct intel_context *
+intel_engine_pinned_context_create(struct intel_engine_cs *engine,
+ unsigned int hwsp,
+ struct lock_class_key *key,
+ const char *name);
+void intel_engine_pinned_context_destroy(struct intel_context *ce);
+
void intel_engine_init_active(struct intel_engine_cs *engine,
unsigned int subclass);
#define ENGINE_PHYSICAL0
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 577ebd4a324f..5fb7c6202146 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -770,11 +770,11 @@ static int measure_breadcrumb_dw(struct intel_context *ce)
return dw;
}
-static struct intel_context *
-create_pinned_context(struct intel_engine_cs *engine,
- unsigned int hwsp,
- struct lock_class_key *key,
- const char *name)
+struct intel_context *
+intel_engine_pinned_context_create(struct intel_engine_cs *engine,
+ unsigned int hwsp,
+ struct lock_class_key *key,
+ const char *name)
{
struct intel_context *ce;
int err;
@@ -803,7 +803,7 @@ create_pinned_context(struct intel_engine_cs *engine,
return ce;
}
-static void destroy_pinned_context(struct intel_context *ce)
+void intel_engine_pinned_context_destroy(struct intel_context *ce)
{
struct intel_engine_cs *engine = ce->engine;
struct i915_vma *hwsp = engine->status_page.vma;
@@ -823,8 +823,9 @@ create_kernel_context(struct intel_engine_cs *engine)
{
static struct lock_class_key kernel;
- return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR,
-&kernel, "kernel_context");
+ return intel_engine_pinned_context_create(engine,
+ I915_GEM_HWS_SEQNO_ADDR,
+ &kernel, "kernel_context");
}
/**
@@ -928,7 +929,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
fput(engine->default_state);
if (engine->kernel_context)
-
[Intel-gfx] [PATCH v2 05/16] drm/i915/pxp: set KCR reg init during the boot time
Set the KCR init during the boot time, which is required by hardware,
to allow us doing further protection operation such as sending commands
to GPU or TEE.
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 29 +++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index c2b1c8ff845d..9b2a67f8ab8e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,24 @@
#include "gt/intel_context.h"
#include "i915_drv.h"
+/* KCR register definitions */
+#define KCR_INIT _MMIO(0x320f0)
+
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
+
+static void kcr_pxp_enable(struct intel_gt *gt)
+{
+ intel_uncore_write(gt->uncore, KCR_INIT,
+
_MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
+}
+
+static void kcr_pxp_disable(struct intel_gt *gt)
+{
+ intel_uncore_write(gt->uncore, KCR_INIT,
+
_MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
+}
+
static int create_vcs_context(struct intel_pxp *pxp)
{
static struct lock_class_key pxp_lock;
@@ -46,19 +64,28 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (!HAS_PXP(gt->i915))
return;
+ kcr_pxp_enable(gt);
+
ret = create_vcs_context(pxp);
if (ret)
- return;
+ goto out_kcr;
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content
support initialized\n");
return;
+
+out_kcr:
+ kcr_pxp_disable(gt);
}
void intel_pxp_fini(struct intel_pxp *pxp)
{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
if (!intel_pxp_is_enabled(pxp))
return;
destroy_vcs_context(pxp);
+
+ kcr_pxp_disable(gt);
}
--
2.29.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 06/16] drm/i915/pxp: Implement funcs to create the TEE channel
From: "Huang, Sean Z"
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(default) session.
v2: fix locking, don't pollute dev_priv (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 10 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 78 ++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 3 +
5 files changed, 107 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8bcdd708d5c9..7745f73ce3dc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -272,7 +272,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
- pxp/intel_pxp.o
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 9b2a67f8ab8e..a4497cd38609 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -3,6 +3,7 @@
* Copyright(c) 2020 Intel Corporation.
*/
#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
#include "gt/intel_context.h"
#include "i915_drv.h"
@@ -70,10 +71,16 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (ret)
goto out_kcr;
+ ret = intel_pxp_tee_component_init(pxp);
+ if (ret)
+ goto out_context;
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content
support initialized\n");
return;
+out_context:
+ destroy_vcs_context(pxp);
out_kcr:
kcr_pxp_disable(gt);
}
@@ -85,7 +92,10 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (!intel_pxp_is_enabled(pxp))
return;
+ intel_pxp_tee_component_fini(pxp);
+
destroy_vcs_context(pxp);
kcr_pxp_disable(gt);
+
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index ..3225a90dc5af
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
+
+static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
+{
+ return &kdev_to_i915(i915_kdev)->gt.pxp;
+}
+
+
+/**
+ * i915_pxp_tee_component_bind - bind function to pass the function pointers
to pxp_tee
+ * @i915_kdev: pointer to i915 kernel device
+ * @tee_kdev: pointer to tee kernel device
+ * @data: pointer to pxp_tee_master containing the function pointers
+ *
+ * This bind function is called during the system boot or resume from system
sleep.
+ *
+ * Return: return 0 if successful.
+ */
+static int i915_pxp_tee_component_bind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
+
+ pxp->pxp_component = data;
+ pxp->pxp_component->tee_dev = tee_kdev;
+
+ return 0;
+}
+
+static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
+
+ pxp->pxp_component = NULL;
+}
+
+static const struct component_ops i915_pxp_tee_component_ops = {
+ .bind = i915_pxp_tee_component_bind,
+ .unbind = i915_pxp_tee_component_unbind,
+};
+
+int intel_pxp_tee_component_init(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops,
+ I915_COMPONENT_PXP);
+ if (ret < 0) {
+ drm_err(&i915->drm, "Failed to add PXP component (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ if (!pxp->pxp_component)
+ return;
+
+ component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
new file mode 100644
index ..23d050a5d3e7
--- /dev/null
+++ b/drivers/gpu
[Intel-gfx] [PATCH v2 07/16] drm/i915/pxp: Create the arbitrary session after boot
From: "Huang, Sean Z"
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session will need to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
The session ID is exposed as part of the uapi so it can be used as part
of userspace commands.
v2: use gt->uncore->rpm (chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 82 +++
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 16 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 102 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 6 ++
include/uapi/drm/i915_drm.h | 4 +
9 files changed, 221 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7745f73ce3dc..d6d510e4875e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -273,6 +273,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index a4497cd38609..cbec9395bde9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -65,6 +65,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (!HAS_PXP(gt->i915))
return;
+ mutex_init(&pxp->mutex);
+
kcr_pxp_enable(gt);
ret = create_vcs_context(pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index e87550fb9821..3bede9306481 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -19,6 +19,11 @@ static inline bool intel_pxp_is_enabled(const struct
intel_pxp *pxp)
return pxp->ce;
}
+static inline bool intel_pxp_is_active(const struct intel_pxp *pxp)
+{
+ return pxp->arb_is_in_play;
+}
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
new file mode 100644
index ..6abc59a63e51
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "drm/i915_drm.h"
+#include "i915_drv.h"
+
+#include "intel_pxp.h"
+#include "intel_pxp_session.h"
+#include "intel_pxp_tee.h"
+#include "intel_pxp_types.h"
+
+#define ARB_SESSION I915_PROTECTED_CONTENT_DEFAULT_SESSION /* shorter define */
+
+#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
+
+static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ intel_wakeref_t wakeref;
+ u32 sip = 0;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+
+ return sip & BIT(id);
+}
+
+bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp)
+{
+ return intel_pxp_session_is_in_play(pxp, ARB_SESSION);
+}
+
+static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool
in_play)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ intel_wakeref_t wakeref;
+ u32 mask = BIT(id);
+ int ret;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ ret = intel_wait_for_register(gt->uncore,
+ GEN12_KCR_SIP,
+ mask,
+ in_play ? mask : 0,
+ 100);
+
+ return ret;
+}
+
+int intel_pxp_create_arb_session(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ int ret;
+
+ lockdep_assert_held(&pxp->mutex);
+
+ pxp->arb_is_in_play = false;
+
+ if (intel_pxp_session_is_in_play(pxp, ARB_SESSION)) {
+ drm_err(>->i915->drm, "arb session already in play at
creation time\n");
+ pxp->arb_is_in_play = true;
+ return -EEXIST;
+ }
+
+ ret =
[Intel-gfx] [PATCH v2 08/16] drm/i915/pxp: Implement arb session teardown
From: "Huang, Sean Z"
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. Additionally, we want to emit a
teardown operation to make sure we're clean on boot and resume
v2: emit in the ring, use high prio request (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 166 +++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 38 +
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +-
6 files changed, 225 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d6d510e4875e..8b605f326039 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -273,6 +273,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_cmd.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
new file mode 100644
index ..ffab09839cd3
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp.h"
+#include "intel_pxp_session.h"
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_gpu_commands.h"
+#include "gt/intel_ring.h"
+
+#include "i915_trace.h"
+
+/* PXP GPU command definitions */
+
+/* MI_SET_APPID */
+#define MI_SET_APPID_SESSION_ID(x)((x) << 0)
+
+/* MI_FLUSH_DW */
+#define MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE BIT(22)
+
+/* MI_WAIT */
+#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG BIT(9)
+#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG BIT(8)
+
+/* CRYPTO_KEY_EXCHANGE */
+#define CRYPTO_KEY_EXCHANGE ((0x3 << 29) | (0x01609 << 16))
+
+/* stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
+#define MFX_WAIT_PXP \
+ MFX_WAIT | \
+ MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | \
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG;
+
+static u32 *pxp_emit_session_selection(u32 *cs, u32 idx)
+{
+ *cs++ = MFX_WAIT_PXP;
+
+ /* pxp off */
+ *cs++ = MI_FLUSH_DW;
+ *cs++ = 0;
+ *cs++ = 0;
+
+ /* select session */
+ *cs++ = MI_SET_APPID | MI_SET_APPID_SESSION_ID(idx);
+
+ *cs++ = MFX_WAIT_PXP;
+
+ /* pxp on */
+ *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE;
+ *cs++ = 0;
+ *cs++ = 0;
+
+ *cs++ = MFX_WAIT_PXP;
+
+ return cs;
+}
+
+static u32 *pxp_emit_inline_termination(u32 *cs)
+{
+ /* session inline termination */
+ *cs++ = CRYPTO_KEY_EXCHANGE;
+ *cs++ = 0;
+
+ return cs;
+}
+
+static u32 *pxp_emit_wait(u32 *cs)
+{
+ /* wait for cmds to go through */
+ *cs++ = MFX_WAIT_PXP;
+ *cs++ = 0;
+
+ return cs;
+}
+
+/*
+ * if we ever need to terminate more than one session, we can submit multiple
+ * selections and terminations back-to-back with a single wait at the end
+ */
+#define SELECTION_LEN 10
+#define TERMINATION_LEN 2
+#define WAIT_LEN 2
+#define __SESSION_TERMINATION_LEN (SELECTION_LEN + TERMINATION_LEN)
+#define SESSION_TERMINATION_LEN(x) (__SESSION_TERMINATION_LEN * (x) + WAIT_LEN)
+
+static struct i915_request *pxp_request_create(struct intel_context *ce)
+{
+ struct i915_request *rq;
+
+ intel_context_enter(ce);
+ rq = __i915_request_create(ce, GFP_KERNEL);
+ intel_context_exit(ce);
+
+ return rq;
+}
+
+static void pxp_request_commit(struct i915_request *rq)
+{
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX };
+
+ trace_i915_request_add(rq);
+ __i915_request_commit(rq);
+ __i915_request_queue(rq, &attr);
+}
+
+int intel_pxp_submit_session_termination(struct intel_pxp *pxp, u32 id)
+{
+ struct i915_request *rq;
+ struct intel_context *ce = pxp->ce;
+ u32 *cs;
+ int err;
+
+ if (!intel_pxp_is_enabled(pxp))
+ return 0;
+
+ intel_engine_pm_get(ce->engine);
+ mutex_lock(&ce->timeline->mutex);
+
+ rq = pxp_request_create(ce);
+ if (IS_ERR(rq)) {
+ mutex_unlock(&ce->timeline->mutex);
+ err = PTR_ERR(rq);
+ goto out_pm;
+ }
+
+ if (ce->engine->emit_init_breadcrumb) {
+ err = ce->engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_rq;
+ }
+
+ cs = intel
[Intel-gfx] [PATCH v2 09/16] drm/i915/pxp: Implement PXP irq handler
From: "Huang, Sean Z"
The HW will generate a teardown interrupt when session termination is
required, which requires i915 to submit a terminating batch. Once the HW
is done with the termination it will generate another interrupt, at
which point it is safe to re-create the session.
v2: use struct completion instead of bool (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 34 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 ++
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 151 +++
drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 33
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 9 +-
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 10 +-
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 8 +
11 files changed, 268 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8b605f326039..5e9bd34dec38 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -274,6 +274,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_cmd.o \
+ pxp/intel_pxp_irq.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index d29126c458ba..0d3585efe2b8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -13,6 +13,7 @@
#include "intel_lrc_reg.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp_irq.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -64,6 +65,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>->rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(>->pxp, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
@@ -190,6 +194,9 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
+
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0);
}
void gen11_gt_irq_postinstall(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e5dd0203991b..97a6d0c638ec 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7958,6 +7958,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index cbec9395bde9..0ca1c2c16972 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -2,7 +2,9 @@
/*
* Copyright(c) 2020 Intel Corporation.
*/
+#include
#include "intel_pxp.h"
+#include "intel_pxp_irq.h"
#include "intel_pxp_tee.h"
#include "gt/intel_context.h"
#include "i915_drv.h"
@@ -67,12 +69,23 @@ void intel_pxp_init(struct intel_pxp *pxp)
mutex_init(&pxp->mutex);
+ /*
+* we'll use the completion to check if there is a termination pending,
+* so we start it as completed and we reinit it when a termination
+* is triggered.
+*/
+ init_completion(&pxp->termination);
+ complete_all(&pxp->termination);
+
kcr_pxp_enable(gt);
ret = create_vcs_context(pxp);
if (ret)
goto out_kcr;
+ intel_pxp_irq_init(pxp);
+ intel_pxp_irq_enable(pxp);
+
ret = intel_pxp_tee_component_init(pxp);
if (ret)
goto out_context;
@@ -94,10 +107,31 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (!intel_pxp_is_enabled(pxp))
return;
+ intel_pxp_irq_disable(pxp);
+
intel_pxp_tee_component_fini(pxp);
destroy_vcs_context(pxp);
kcr_pxp_disable(gt);
+}
+int intel_pxp_wait_for_termination_completion(struct intel_pxp *pxp)
+{
+ int ret;
+
+ if (!intel_pxp_is_enabled(pxp))
+ return 0;
+
+ ret = wait_for_completion_timeout(&pxp->termination,
+
[Intel-gfx] [PATCH v2 10/16] drm/i915/pxp: Enable PXP power management
From: "Huang, Sean Z"
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should unconditionally terminate the hardware
sessions and cleanup all the software states after the power cycle.
v2: runtime suspend also invalidates the keys
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 14 ++-
drivers/gpu/drm/i915/i915_drv.c | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 10 +-
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 99
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 33 +++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 28 --
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 8 ++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 1 +
9 files changed, 183 insertions(+), 13 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5e9bd34dec38..1a175c7f2a4e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -275,6 +275,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_irq.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 0bd303d2823e..16f03651a6b7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -19,6 +19,7 @@
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_pm.h"
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
@@ -260,6 +261,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uc_resume(>->uc);
+ intel_pxp_pm_resume(>->pxp);
+
user_forcewake(gt, false);
out_fw:
@@ -294,6 +297,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
user_forcewake(gt, true);
wait_for_suspend(gt);
+ intel_pxp_pm_prepare_suspend(>->pxp);
intel_uc_suspend(>->uc);
}
@@ -344,6 +348,7 @@ void intel_gt_suspend_late(struct intel_gt *gt)
void intel_gt_runtime_suspend(struct intel_gt *gt)
{
+ intel_pxp_runtime_suspend(>->pxp);
intel_uc_runtime_suspend(>->uc);
GT_TRACE(gt, "\n");
@@ -351,11 +356,18 @@ void intel_gt_runtime_suspend(struct intel_gt *gt)
int intel_gt_runtime_resume(struct intel_gt *gt)
{
+ int ret;
+
GT_TRACE(gt, "\n");
intel_gt_init_swizzling(gt);
intel_ggtt_restore_fences(gt->ggtt);
- return intel_uc_runtime_resume(>->uc);
+ ret = intel_uc_runtime_resume(>->uc);
+
+ if (!ret)
+ ret = intel_pxp_runtime_resume(>->pxp);
+
+ return ret;
}
ktime_t intel_gt_get_awake_time(const struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3edd5e47ad68..d0a39ec29d50 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -67,6 +67,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drm_client.h"
#include "i915_drv.h"
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
index 40115bf0b6bb..5b03b17eaa48 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
@@ -125,11 +125,13 @@ void intel_pxp_irq_enable(struct intel_pxp *pxp)
struct intel_gt *gt = pxp_to_gt(pxp);
spin_lock_irq(>->irq_lock);
- if (!pxp->irq_enabled) {
+
+ if (!pxp->irq_enabled)
WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_KCR));
- __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
- pxp->irq_enabled = true;
- }
+
+ __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
+ pxp->irq_enabled = true;
+
spin_unlock_irq(>->irq_lock);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index ..0dd2e100bab5
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp.h"
+#include "intel_pxp_irq.h"
+#include "intel_pxp_pm.h"
+#include "intel_pxp_session.h"
+
+static void __pxp_suspend(struct intel_pxp *pxp)
+{
+ if (!intel_pxp_is_enabled(pxp))
+ return;
+
+ intel_pxp_irq_disable(pxp);
+
+ pxp->global_state_attacked = false;
+ pxp->arb_is_in_play = false;
+ pxp-
[Intel-gfx] [PATCH v2 11/16] drm/i915/pxp: interface for creation of protected contexts
Usage of protected objects, coming in a follow-up patch, will be
restricted to protected contexts. Contexts can only be marked as
protected at creation time and they must be both bannable and not
recoverable.
When a PXP teardown occurs, all gem contexts marked as protected that
have been used at least once will be marked as invalid and all new
submissions using them will be rejected. All intel contexts within the
invalidated gem contexts will be marked banned.
A new flag has been added to the RESET_STATS ioctl to report the
invalidation to userspace.
v2: split to its own patch and improve doc (Chris), invalidate contexts
on teardown
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 ++-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 18 ++
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 13
drivers/gpu/drm/i915/pxp/intel_pxp.c | 38
drivers/gpu/drm/i915/pxp/intel_pxp.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 3 +
include/uapi/drm/i915_drm.h | 19 ++
8 files changed, 150 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ca37d93ef5e7..19ac24a3c42c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -76,6 +76,8 @@
#include "gt/intel_gpu_commands.h"
#include "gt/intel_ring.h"
+#include "pxp/intel_pxp.h"
+
#include "i915_drm_client.h"
#include "i915_gem_context.h"
#include "i915_globals.h"
@@ -2006,6 +2008,40 @@ static int set_priority(struct i915_gem_context *ctx,
return 0;
}
+static int set_protected(struct i915_gem_context *ctx,
+const struct drm_i915_gem_context_param *args)
+{
+ int ret = 0;
+
+ if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
+ ret = -ENODEV;
+ else if (ctx->client) /* can't change this after creation! */
+ ret = -EEXIST;
+ else if (args->size)
+ ret = -EINVAL;
+ else if (!args->value)
+ clear_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+ else if (i915_gem_context_is_recoverable(ctx) ||
+!i915_gem_context_is_bannable(ctx))
+ ret = -EPERM;
+ else
+ set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+
+ return ret;
+}
+
+static int get_protected(struct i915_gem_context *ctx,
+struct drm_i915_gem_context_param *args)
+{
+ if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
+ return -ENODEV;
+
+ args->size = 0;
+ args->value = i915_gem_context_can_use_protected_content(ctx);
+
+ return 0;
+}
+
static int ctx_setparam(struct drm_i915_file_private *fpriv,
struct i915_gem_context *ctx,
struct drm_i915_gem_context_param *args)
@@ -2038,6 +2074,8 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
ret = -EPERM;
else if (args->value)
i915_gem_context_set_bannable(ctx);
+ else if (i915_gem_context_can_use_protected_content(ctx))
+ ret = -EPERM; /* can't clear this for protected
contexts */
else
i915_gem_context_clear_bannable(ctx);
break;
@@ -2045,10 +2083,12 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
- else
+ else if (!args->value)
i915_gem_context_clear_recoverable(ctx);
+ else if (i915_gem_context_can_use_protected_content(ctx))
+ ret = -EPERM; /* can't set this for protected contexts
*/
+ else
+ i915_gem_context_set_recoverable(ctx);
break;
case I915_CONTEXT_PARAM_PRIORITY:
@@ -2075,6 +2115,10 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
ret = set_ringsize(ctx, args);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ ret = set_protected(ctx, args);
+ break;
+
case I915_CONTEXT_PARAM_BAN_PERIOD:
default:
ret = -EINVAL;
@@ -2532,6 +2576,10 @@ int i915_gem_context_getparam_ioctl(struct drm_device
*dev, void *data,
ret = get_ringsize(ctx, args);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ ret = get_protected(ctx, args);
+ break;
+
case I915_CONTEXT_PARAM_BAN_PERIO
[Intel-gfx] [PATCH v2 12/16] drm/i915/uapi: introduce drm_i915_gem_create_ext
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Matthew Auld
Cc: Telukuntla Sreedhar
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 41 ++-
drivers/gpu/drm/i915/i915_drv.c| 2 +-
include/uapi/drm/i915_drm.h| 47 ++
3 files changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 45d60e3d98e3..3ad3413c459f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -7,6 +7,7 @@
#include "gem/i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_user_extensions.h"
static int
i915_gem_create(struct drm_file *file,
@@ -91,6 +92,35 @@ i915_gem_dumb_create(struct drm_file *file,
&args->size, &args->handle);
}
+struct create_ext {
+ struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+struct create_ext *ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(&ext.param, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -102,10 +132,19 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ &ext_data);
+ if (ret)
+ return ret;
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d0a39ec29d50..a46b5672d4e7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1713,7 +1713,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 0f5456046c4c..9ebe8523aa0c 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAPDRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -729,6 +730,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+* Requested size for the object.
+
[Intel-gfx] [PATCH v2 13/16] drm/i915/pxp: User interface for Protected buffer
From: Bommu Krishnaiah
This api allow user mode to create Protected buffers. Only contexts
marked as protected are allowed to operate on protected buffers.
We only allow setting the flags at creation time.
All protected objects that have backing storage will be considered
invalid when the session is destroyed and they won't be usable anymore.
This is a rework of the original code by Bommu Krishnaiah. I've
authorship unchanged since significant chunks have not been modified.
v2: split context changes, fix defines and improve documentation (Chris),
add object invalidation logic
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Daniele Ceraolo Spurio
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_create.c| 27 +++--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 10 +
drivers/gpu/drm/i915/gem/i915_gem_object.c| 6 +++
drivers/gpu/drm/i915/gem/i915_gem_object.h| 12 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 13 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 40 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 13 ++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 5 +++
include/uapi/drm/i915_drm.h | 22 ++
9 files changed, 145 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 3ad3413c459f..d02e5938afbe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -5,6 +5,7 @@
#include "gem/i915_gem_ioctls.h"
#include "gem/i915_gem_region.h"
+#include "pxp/intel_pxp.h"
#include "i915_drv.h"
#include "i915_user_extensions.h"
@@ -13,7 +14,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -35,12 +37,17 @@ i915_gem_create(struct drm_file *file,
GEM_BUG_ON(size != obj->base.size);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
if (ret)
return ret;
+ if (user_flags & I915_GEM_OBJECT_PROTECTED)
+ intel_pxp_object_add(obj);
+
*handle_p = handle;
*size_p = size;
return 0;
@@ -89,11 +96,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
mem_type),
- &args->size, &args->handle);
+ &args->size, &args->handle, 0);
}
struct create_ext {
struct drm_i915_private *i915;
+ unsigned long user_flags;
};
static int __create_setparam(struct drm_i915_gem_object_param *args,
@@ -104,6 +112,19 @@ static int __create_setparam(struct
drm_i915_gem_object_param *args,
return -EINVAL;
}
+ switch (lower_32_bits(args->param)) {
+ case I915_OBJECT_PARAM_PROTECTED_CONTENT:
+ if (!intel_pxp_is_enabled(&ext_data->i915->gt.pxp))
+ return -ENODEV;
+ if (args->size) {
+ return -EINVAL;
+ } else if (args->data) {
+ ext_data->user_flags |= I915_GEM_OBJECT_PROTECTED;
+ return 0;
+ }
+ break;
+ }
+
return -EINVAL;
}
@@ -148,5 +169,5 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
- &args->size, &args->handle);
+ &args->size, &args->handle, ext_data.user_flags);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index e503c9f789c0..d10c4fcb6aec 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -20,6 +20,7 @@
#include "gt/intel_gt_buffer_pool.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_ring.h"
+#include "pxp/intel_pxp.h"
#include "pxp/intel_pxp.h"
@@ -500,6 +501,15 @@ eb_validate_vma(struct i915_execbuffer *eb,
entry->offset != gen8_canonical_addr(entry->offset &
I915_GTT_PAGE_MASK)))
return -EINVAL;
+ if (i915_gem_object_is_protected(vma->obj)) {
+ if (!intel_pxp_is_active(&vma->vm->gt->pxp))
+ return -ENODEV;
+ if
[Intel-gfx] [PATCH v2 14/16] drm/i915/pxp: Add plane decryption support
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PXP session is enabled.
2. Buffer object is protected.
v2:
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
v3:
- intel_pxp_gem_object_status() API changes.
v4: use intel_pxp_is_active (Daniele)
v5: rebase and use the new protected object status checker (Daniele)
Cc: Bommu Krishnaiah
Cc: Huang Sean Z
Cc: Gaurav Kumar
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 14 +++---
drivers/gpu/drm/i915/i915_reg.h| 1 +
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 1f335cb09149..e42f682cbb46 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -16,6 +16,7 @@
#include "intel_sprite.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
+#include "pxp/intel_pxp.h"
static const u32 skl_plane_formats[] = {
DRM_FORMAT_C8,
@@ -971,7 +972,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -1051,8 +1052,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
+ i915_gem_object_has_valid_protection(intel_fb_obj(fb)))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_plane_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 97a6d0c638ec..3fdbcfd59b0e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7223,6 +7223,7 @@ enum {
#define _PLANE_SURF_3(pipe)_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane)\
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLEDREG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.29.2
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[Intel-gfx] [PATCH v2 15/16] drm/i915/pxp: black pixels on pxp disabled
From: Anshuman Gupta
When protected sufaces has flipped and pxp session is disabled
display black pixels by using plane color CTM correction.
Cc: Ville Syrjälä
Cc: Gaurav Kumar
Cc: Shankar Uma
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
---
.../drm/i915/display/skl_universal_plane.c| 40 +++-
drivers/gpu/drm/i915/i915_reg.h | 46 +++
2 files changed, 84 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index e42f682cbb46..39986eed50f3 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -949,6 +949,33 @@ skl_main_to_aux_plane(const struct drm_framebuffer *fb,
int main_plane)
return 0;
}
+static void intel_load_plane_csc_black(struct intel_plane *intel_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
+ enum pipe pipe = intel_plane->pipe;
+ enum plane_id plane = intel_plane->id;
+ u16 postoff = 0;
+
+ drm_dbg_kms(&dev_priv->drm, "plane color CTM to black %s:%d\n",
+ intel_plane->base.name, plane);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 0), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 1), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 2), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 3), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 4), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 5), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 0), postoff);
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 1), postoff);
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 2), postoff);
+}
+
static void
skl_program_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -1053,13 +1080,22 @@ skl_program_plane(struct intel_plane *plane,
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+ plane_color_ctl = intel_de_read_fw(dev_priv, PLANE_COLOR_CTL(pipe,
plane_id));
if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
- i915_gem_object_has_valid_protection(intel_fb_obj(fb)))
+ i915_gem_object_has_valid_protection(intel_fb_obj(fb))) {
plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
- else
+ plane_color_ctl &= ~PLANE_COLOR_PLANE_CSC_ENABLE;
+ } else if (i915_gem_object_is_protected(intel_fb_obj(fb))) {
+ intel_load_plane_csc_black(plane);
+ plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
+ } else {
plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+ plane_color_ctl &= ~PLANE_COLOR_PLANE_CSC_ENABLE;
+ }
+ intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
+ plane_color_ctl);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3fdbcfd59b0e..6b739fc59849 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7102,6 +7102,7 @@ enum {
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_COLOR_PLANE_CSC_ENABLE (1 << 21) /* ICL+ */
#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
@@ -11164,6 +11165,51 @@ enum skl_power_gate {
_PAL_PREC_MULTI_SEG_DATA_A, \
_PAL_PREC_MULTI_SEG_DATA_B)
+#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
+
+/* Plane CSC Registers */
+#define _PLANE_CSC_RY_GY_1_A 0x70210
+#define _PLANE_CSC_RY_GY_2_A 0x70310
+
+#define _PLANE_CSC_RY_GY_1_B 0x71210
+#define _PLANE_CSC_RY_GY_2_B 0x71310
+
+#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
+ _PLANE_CSC_RY_GY_1_B)
+#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A,
\
+ _PLANE_INPUT_CSC_RY_GY_2_B)
[Intel-gfx] [PATCH v2 16/16] drm/i915/pxp: enable PXP for integrated Gen12
Note that discrete cards can support PXP as well, but we haven't tested
on those yet so keeping it disabled for now.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a9f24f2bda33..f380a92e5c7c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -880,6 +880,7 @@ static const struct intel_device_info jsl_info = {
}, \
TGL_CURSOR_OFFSETS, \
.has_global_mocs = 1, \
+ .has_pxp = 1, \
.display.has_dsb = 1
static const struct intel_device_info tgl_info = {
@@ -908,6 +909,7 @@ static const struct intel_device_info rkl_info = {
.memory_regions = REGION_SMEM | REGION_LMEM, \
.has_master_unit_irq = 1, \
.has_llc = 0, \
+ .has_pxp = 0, \
.has_snoop = 1, \
.is_dgfx = 1
--
2.29.2
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP (rev2)
== Series Details == Series: Introduce Intel PXP (rev2) URL : https://patchwork.freedesktop.org/series/86798/ State : warning == Summary == $ dim checkpatch origin/drm-tip d3a311348975 drm/i915/pxp: Define PXP component interface -:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #30: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 52 lines checked b39091843fc5 mei: pxp: export pavp client to me client bus -:33: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #33: new file mode 100644 -:161: WARNING:TRACING_LOGGING: Unnecessary ftrace-like logging - prefer using ftrace #161: FILE: drivers/misc/mei/pxp/mei_pxp.c:92: + dev_dbg(dev, "%s\n", __func__); -:176: WARNING:TRACING_LOGGING: Unnecessary ftrace-like logging - prefer using ftrace #176: FILE: drivers/misc/mei/pxp/mei_pxp.c:107: + dev_dbg(dev, "%s\n", __func__); total: 0 errors, 3 warnings, 0 checks, 277 lines checked 82f987002778 drm/i915/pxp: define PXP device flag and kconfig -:42: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #42: FILE: drivers/gpu/drm/i915/i915_drv.h:1745: +#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \ + INTEL_INFO(dev_priv)->has_pxp) && \ + VDBOX_MASK(&dev_priv->gt) -:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #42: FILE: drivers/gpu/drm/i915/i915_drv.h:1745: +#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \ + INTEL_INFO(dev_priv)->has_pxp) && \ + VDBOX_MASK(&dev_priv->gt) total: 1 errors, 0 warnings, 1 checks, 34 lines checked c827c2625593 drm/i915/pxp: allocate a vcs context for pxp usage -:168: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #168: new file mode 100644 -:192: ERROR:TRAILING_STATEMENTS: trailing statements should be on next line #192: FILE: drivers/gpu/drm/i915/pxp/intel_pxp.c:20: + for (engine = gt->engine_class[VIDEO_DECODE_CLASS][0]; !engine; engine++); -:228: WARNING:RETURN_VOID: void function return statements are not generally useful #228: FILE: drivers/gpu/drm/i915/pxp/intel_pxp.c:56: + return; +} total: 1 errors, 2 warnings, 0 checks, 233 lines checked e8d17e3b42bd drm/i915/pxp: set KCR reg init during the boot time 5ae54e4b7228 drm/i915/pxp: Implement funcs to create the TEE channel -:71: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #71: new file mode 100644 -:93: CHECK:LINE_SPACING: Please don't use multiple blank lines #93: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_tee.c:18: + + total: 0 errors, 1 warnings, 1 checks, 145 lines checked cf600c3c742a drm/i915/pxp: Create the arbitrary session after boot -:65: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #65: new file mode 100644 -:341: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment #341: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_types.h:20: + struct mutex mutex; -:354: CHECK:LINE_SPACING: Please don't use multiple blank lines #354: FILE: include/uapi/drm/i915_drm.h:2379: + total: 0 errors, 1 warnings, 2 checks, 288 lines checked 8113993a2d3e drm/i915/pxp: Implement arb session teardown -:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #30: new file mode 100644 -:65: ERROR:MULTISTATEMENT_MACRO_USE_DO_WHILE: Macros with multiple statements should be enclosed in a do - while loop #65: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c:31: +#define MFX_WAIT_PXP \ + MFX_WAIT | \ + MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | \ + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG; -:65: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon #65: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c:31: +#define MFX_WAIT_PXP \ + MFX_WAIT | \ + MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | \ + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG; total: 1 errors, 2 warnings, 0 checks, 258 lines checked ebfeffa20951 drm/i915/pxp: Implement PXP irq handler -:185: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #185: new file mode 100644 -:368: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #368: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_irq.h:22: +} +void intel_pxp_irq_enable(struct intel_pxp *pxp) -:371: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #371: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_irq.h:25: +} +void intel_pxp_irq_disable(struct intel_pxp *pxp) -:374: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #374: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_irq.h:28: +} +static inline void intel_pxp_irq_handler(struct
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce Intel PXP (rev2)
== Series Details == Series: Introduce Intel PXP (rev2) URL : https://patchwork.freedesktop.org/series/86798/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1323:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1437:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1491:15: warning: memset with byte count of 16777216 +./drivers/gpu/drm/i915/pxp/intel_pxp_irq.h:19:6: warning: symbol 'intel_pxp_irq_init' was not declared. Should it be static? +./drivers/gpu/drm/i915/pxp/intel_pxp_irq.h:22:6: warning: symbol 'intel_pxp_irq_enable' was not declared. Should it be static? +./drivers/gpu/drm/i915/pxp/intel_pxp_irq.h:25:6: warning: symbol 'intel_pxp_irq_disable' was not declared. Should it be static? +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block _
[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Intel PXP (rev2)
== Series Details == Series: Introduce Intel PXP (rev2) URL : https://patchwork.freedesktop.org/series/86798/ State : success == Summary == CI Bug Log - changes from CI_DRM_9818 -> Patchwork_19737 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/index.html Known issues Here are the changes found in Patchwork_19737 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-icl-y: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-icl-y/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-apl-guc: NOTRUN -> [SKIP][2] ([fdo#109271]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-apl-guc/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#1888]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_huc_copy@huc-copy: - fi-icl-y: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-icl-y/igt@gem_huc_c...@huc-copy.html * igt@i915_hangman@error-state-basic: - fi-apl-guc: NOTRUN -> [DMESG-WARN][6] ([i915#1610]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-apl-guc/igt@i915_hang...@error-state-basic.html * igt@kms_chamelium@dp-crc-fast: - fi-icl-y: NOTRUN -> [SKIP][7] ([fdo#109284] / [fdo#111827]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-icl-y/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@hdmi-crc-fast: - fi-bsw-n3050: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-bsw-n3050/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_force_connector_basic@force-load-detect: - fi-icl-y: NOTRUN -> [SKIP][9] ([fdo#109285]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-icl-y/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-icl-y: NOTRUN -> [SKIP][10] ([fdo#109278]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-icl-y/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: - fi-bsw-n3050: NOTRUN -> [SKIP][11] ([fdo#109271]) +39 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-bsw-n3050/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html * igt@kms_psr@primary_mmap_gtt: - fi-icl-y: NOTRUN -> [SKIP][12] ([fdo#110189]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-icl-y/igt@kms_psr@primary_mmap_gtt.html * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html * igt@runner@aborted: - fi-apl-guc: NOTRUN -> [FAIL][15] ([i915#2426]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-apl-guc/igt@run...@aborted.html Possible fixes * igt@fbdev@read: - fi-tgl-y: [DMESG-WARN][16] ([i915#402]) -> [PASS][17] +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-tgl-y/igt@fb...@read.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-tgl-y/igt@fb...@read.html * igt@gem_exec_gttfill@basic: - fi-kbl-8809g: [TIMEOUT][18] -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html * igt@gem_linear_blits@basic: - fi-kbl-8809g: [TIMEOUT][20] ([i915#2502]) -> [PASS][21] +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-kbl-8809g/igt@gem_linear_bl...@basic.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/fi-kbl-8809g/igt@gem_linear_bl...@basic.html * igt@kms_chamelium@hdmi-edid-read: - fi-kbl-7500u: [FAIL][22] ([i915#2128]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html [23]: https://intel-gfx-ci.01.org/tr
[Intel-gfx] ✓ Fi.CI.IGT: success for Introduce Intel PXP (rev2)
== Series Details == Series: Introduce Intel PXP (rev2) URL : https://patchwork.freedesktop.org/series/86798/ State : success == Summary == CI Bug Log - changes from CI_DRM_9818_full -> Patchwork_19737_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/index.html Changes --- No changes found Participating hosts (10 -> 8) -- Missing(2): pig-kbl-iris pig-icl-1065g7 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_9818 -> Patchwork_19737 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_9818: fb3b93df7979b1cf6b69ac801d1703c0bf1dde66 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6016: 2107b0a53692fb329175bc16169c3699712187aa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19737: 4f113650134a412185b462d93608cbfc3c7bf818 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19737/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] i915/perf: Start hrtimer only if sampling the OA buffer
SAMPLE_OA parameter enables sampling of OA buffer and results in a call
to init the OA buffer which initializes the OA unit head/tail pointers.
The OA_EXPONENT parameter controls the periodicity of the OA reports in
the OA buffer and results in starting a hrtimer.
Before gen12, all use cases required the use of the OA buffer and i915
enforced this setting when vetting out the parameters passed. In these
platforms the hrtimer was enabled if OA_EXPONENT was passed. This worked
fine since it was implied that SAMPLE_OA is always passed.
With gen12, this changed. Users can use perf without enabling the OA
buffer as in OAR use cases. While an OAR use case should ideally not
start the hrtimer, we see that passing an OA_EXPONENT parameter will
start the hrtimer even though SAMPLE_OA is not specified. This results
in an uninitialized OA buffer, so the head/tail pointers used to track
the buffer are zero.
This itself does not fail, but if we ran a use-case that SAMPLED the OA
buffer previously, then the OA_TAIL register is still pointing to an old
value. When the timer callback runs, it ends up calculating a
wrong/large number of available reports. Since we do a spinlock_irq_save
and start processing a large number of reports, NMI watchdog fires and
causes a crash.
Start the timer only if SAMPLE_OA is specified.
v2:
- Drop SAMPLE OA check when appending samples (Ashutosh)
- Prevent read if OA buffer is not being sampled
Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index c15bead2dac7..2fd2c13b76ac 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -595,7 +595,6 @@ static int append_oa_sample(struct i915_perf_stream *stream,
{
int report_size = stream->oa_buffer.format_size;
struct drm_i915_perf_record_header header;
- u32 sample_flags = stream->sample_flags;
header.type = DRM_I915_PERF_RECORD_SAMPLE;
header.pad = 0;
@@ -609,10 +608,8 @@ static int append_oa_sample(struct i915_perf_stream
*stream,
return -EFAULT;
buf += sizeof(header);
- if (sample_flags & SAMPLE_OA_REPORT) {
- if (copy_to_user(buf, report, report_size))
- return -EFAULT;
- }
+ if (copy_to_user(buf, report, report_size))
+ return -EFAULT;
(*offset) += header.size;
@@ -2669,7 +2666,7 @@ static void i915_oa_stream_enable(struct i915_perf_stream
*stream)
stream->perf->ops.oa_enable(stream);
- if (stream->periodic)
+ if (stream->sample_flags & SAMPLE_OA_REPORT)
hrtimer_start(&stream->poll_check_timer,
ns_to_ktime(stream->poll_oa_period),
HRTIMER_MODE_REL_PINNED);
@@ -2732,7 +2729,7 @@ static void i915_oa_stream_disable(struct
i915_perf_stream *stream)
{
stream->perf->ops.oa_disable(stream);
- if (stream->periodic)
+ if (stream->sample_flags & SAMPLE_OA_REPORT)
hrtimer_cancel(&stream->poll_check_timer);
}
@@ -3015,7 +3012,7 @@ static ssize_t i915_perf_read(struct file *file,
* disabled stream as an error. In particular it might otherwise lead
* to a deadlock for blocking file descriptors...
*/
- if (!stream->enabled)
+ if (!stream->enabled || !(stream->sample_flags & SAMPLE_OA_REPORT))
return -EIO;
if (!(file->f_flags & O_NONBLOCK)) {
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] i915/perf: Start hrtimer only if sampling the OA buffer
On Mon, 01 Mar 2021 16:01:41 -0800, Nerlige Ramappa, Umesh wrote:
>
> SAMPLE_OA parameter enables sampling of OA buffer and results in a call
> to init the OA buffer which initializes the OA unit head/tail pointers.
> The OA_EXPONENT parameter controls the periodicity of the OA reports in
> the OA buffer and results in starting a hrtimer.
>
> Before gen12, all use cases required the use of the OA buffer and i915
> enforced this setting when vetting out the parameters passed. In these
> platforms the hrtimer was enabled if OA_EXPONENT was passed. This worked
> fine since it was implied that SAMPLE_OA is always passed.
>
> With gen12, this changed. Users can use perf without enabling the OA
> buffer as in OAR use cases. While an OAR use case should ideally not
> start the hrtimer, we see that passing an OA_EXPONENT parameter will
> start the hrtimer even though SAMPLE_OA is not specified. This results
> in an uninitialized OA buffer, so the head/tail pointers used to track
> the buffer are zero.
>
> This itself does not fail, but if we ran a use-case that SAMPLED the OA
> buffer previously, then the OA_TAIL register is still pointing to an old
> value. When the timer callback runs, it ends up calculating a
> wrong/large number of available reports. Since we do a spinlock_irq_save
> and start processing a large number of reports, NMI watchdog fires and
> causes a crash.
>
> Start the timer only if SAMPLE_OA is specified.
> v2:
> - Drop SAMPLE OA check when appending samples (Ashutosh)
> - Prevent read if OA buffer is not being sampled
Reviewed-by: Ashutosh Dixit
> Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
> Signed-off-by: Umesh Nerlige Ramappa
> ---
> drivers/gpu/drm/i915/i915_perf.c | 13 +
> 1 file changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index c15bead2dac7..2fd2c13b76ac 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -595,7 +595,6 @@ static int append_oa_sample(struct i915_perf_stream
> *stream,
> {
> int report_size = stream->oa_buffer.format_size;
> struct drm_i915_perf_record_header header;
> - u32 sample_flags = stream->sample_flags;
>
> header.type = DRM_I915_PERF_RECORD_SAMPLE;
> header.pad = 0;
> @@ -609,10 +608,8 @@ static int append_oa_sample(struct i915_perf_stream
> *stream,
> return -EFAULT;
> buf += sizeof(header);
>
> - if (sample_flags & SAMPLE_OA_REPORT) {
> - if (copy_to_user(buf, report, report_size))
> - return -EFAULT;
> - }
> + if (copy_to_user(buf, report, report_size))
> + return -EFAULT;
>
> (*offset) += header.size;
>
> @@ -2669,7 +2666,7 @@ static void i915_oa_stream_enable(struct
> i915_perf_stream *stream)
>
> stream->perf->ops.oa_enable(stream);
>
> - if (stream->periodic)
> + if (stream->sample_flags & SAMPLE_OA_REPORT)
> hrtimer_start(&stream->poll_check_timer,
> ns_to_ktime(stream->poll_oa_period),
> HRTIMER_MODE_REL_PINNED);
> @@ -2732,7 +2729,7 @@ static void i915_oa_stream_disable(struct
> i915_perf_stream *stream)
> {
> stream->perf->ops.oa_disable(stream);
>
> - if (stream->periodic)
> + if (stream->sample_flags & SAMPLE_OA_REPORT)
> hrtimer_cancel(&stream->poll_check_timer);
> }
>
> @@ -3015,7 +3012,7 @@ static ssize_t i915_perf_read(struct file *file,
>* disabled stream as an error. In particular it might otherwise lead
>* to a deadlock for blocking file descriptors...
>*/
> - if (!stream->enabled)
> + if (!stream->enabled || !(stream->sample_flags & SAMPLE_OA_REPORT))
> return -EIO;
>
> if (!(file->f_flags & O_NONBLOCK)) {
> --
> 2.20.1
>
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for i915/perf: Start hrtimer only if sampling the OA buffer
== Series Details == Series: i915/perf: Start hrtimer only if sampling the OA buffer URL : https://patchwork.freedesktop.org/series/87524/ State : success == Summary == CI Bug Log - changes from CI_DRM_9818 -> Patchwork_19738 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/index.html Known issues Here are the changes found in Patchwork_19738 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-icl-y: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/fi-icl-y/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-apl-guc: NOTRUN -> [SKIP][2] ([fdo#109271]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/fi-apl-guc/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-icl-y: NOTRUN -> [SKIP][3] ([i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/fi-icl-y/igt@gem_huc_c...@huc-copy.html * igt@i915_hangman@error-state-basic: - fi-apl-guc: NOTRUN -> [DMESG-WARN][4] ([i915#1610]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/fi-apl-guc/igt@i915_hang...@error-state-basic.html * igt@kms_chamelium@dp-crc-fast: - fi-icl-y: NOTRUN -> [SKIP][5] ([fdo#109284] / [fdo#111827]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/fi-icl-y/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@hdmi-crc-fast: - fi-bsw-n3050: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/fi-bsw-n3050/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_force_connector_basic@force-load-detect: - fi-icl-y: NOTRUN -> [SKIP][7] ([fdo#109285]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/fi-icl-y/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-icl-y: NOTRUN -> [SKIP][8] ([fdo#109278]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/fi-icl-y/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: - fi-bsw-n3050: NOTRUN -> [SKIP][9] ([fdo#109271]) +39 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/fi-bsw-n3050/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html * igt@kms_psr@primary_mmap_gtt: - fi-icl-y: NOTRUN -> [SKIP][10] ([fdo#110189]) +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/fi-icl-y/igt@kms_psr@primary_mmap_gtt.html * igt@prime_vgem@basic-write: - fi-tgl-y: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-tgl-y/igt@prime_v...@basic-write.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/fi-tgl-y/igt@prime_v...@basic-write.html * igt@runner@aborted: - fi-apl-guc: NOTRUN -> [FAIL][13] ([i915#2426]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/fi-apl-guc/igt@run...@aborted.html Possible fixes * igt@fbdev@read: - fi-tgl-y: [DMESG-WARN][14] ([i915#402]) -> [PASS][15] +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-tgl-y/igt@fb...@read.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/fi-tgl-y/igt@fb...@read.html * igt@gem_exec_gttfill@basic: - fi-kbl-8809g: [TIMEOUT][16] -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html * igt@kms_chamelium@hdmi-edid-read: - fi-kbl-7500u: [FAIL][18] ([i915#2128]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 [i915#2128]: https://gitlab.freedesktop.org/
[Intel-gfx] ✓ Fi.CI.IGT: success for i915/perf: Start hrtimer only if sampling the OA buffer
== Series Details == Series: i915/perf: Start hrtimer only if sampling the OA buffer URL : https://patchwork.freedesktop.org/series/87524/ State : success == Summary == CI Bug Log - changes from CI_DRM_9818_full -> Patchwork_19738_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/index.html Changes --- No changes found Participating hosts (10 -> 8) -- Missing(2): pig-kbl-iris pig-icl-1065g7 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_9818 -> Patchwork_19738 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_9818: fb3b93df7979b1cf6b69ac801d1703c0bf1dde66 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6016: 2107b0a53692fb329175bc16169c3699712187aa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19738: 45970a8fbfdfc8a84e71aef847cbfa0bb3ac0966 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19738/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to
resolve VP8 hardware encoding system hang up on GT1 sku for
ChromiumOS projects
Reference: HSD#1508045018,1405586840, BSID#0575
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: William Tseng
Cc: Lee Shawn C
Signed-off-by: Cooper Chiou
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3b4a7da60f0b..a2a23bb359e8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -878,9 +878,46 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
}
+static void
+gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
+ unsigned int slice, subslice;
+ u32 mcr, mcr_mask;
+ GEM_BUG_ON(INTEL_GEN(i915) < 9);
+
+ /*
+* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml
+* Before any MMIO read into slice/subslice specific registers, MCR
+* packet control register needs to be programmed to point to any
+* enabled s/ss pair. Otherwise, incorrect values will be returned.
+* This means each subsequent MMIO read will be forwarded to an
+* specific s/ss combination, but this is OK since these registers
+* are consistent across s/ss in almost all cases. In the rare
+* occasions, such as INSTDONE, where this value is dependent
+* on s/ss combo, the read should be done with read_subslice_reg.
+*/
+ slice = fls(sseu->slice_mask) - 1;
+ GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
+ subslice = fls(intel_sseu_get_subslices(sseu, slice));
+ GEM_BUG_ON(!subslice);
+ subslice--;
+
+ mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+ mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
+
+ drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice,
mcr);
+
+ wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
+}
+
static void
gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
{
+ /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml */
+ if (!IS_COFFEELAKE(i915))
+ gen9_wa_init_mcr(i915, wal);
+
/* WaDisableKillLogic:bxt,skl,kbl */
if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915))
wa_write_or(wal,
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4] vfio/pci: Add support for opregion v2.1+
Before opregion version 2.0 VBT data is stored in opregion mailbox #4,
However, When VBT data exceeds 6KB size and cannot be within mailbox #4
starting from opregion v2.0+, Extended VBT region, next to opregion, is
used to hold the VBT data, so the total size will be opregion size plus
extended VBT region size.
since opregion v2.0 with physical host VBT address should not be
practically available for end user, it is not supported.
Cc: Zhenyu Wang
Signed-off-by: Swee Yee Fonn
Signed-off-by: Fred Gao
---
drivers/vfio/pci/vfio_pci_igd.c | 49 +
1 file changed, 49 insertions(+)
diff --git a/drivers/vfio/pci/vfio_pci_igd.c b/drivers/vfio/pci/vfio_pci_igd.c
index 53d97f459252..4edb8afcdbfc 100644
--- a/drivers/vfio/pci/vfio_pci_igd.c
+++ b/drivers/vfio/pci/vfio_pci_igd.c
@@ -21,6 +21,10 @@
#define OPREGION_SIZE (8 * 1024)
#define OPREGION_PCI_ADDR 0xfc
+#define OPREGION_RVDA 0x3ba
+#define OPREGION_RVDS 0x3c2
+#define OPREGION_VERSION 0x16
+
static size_t vfio_pci_igd_rw(struct vfio_pci_device *vdev, char __user *buf,
size_t count, loff_t *ppos, bool iswrite)
{
@@ -58,6 +62,7 @@ static int vfio_pci_igd_opregion_init(struct vfio_pci_device
*vdev)
u32 addr, size;
void *base;
int ret;
+ u16 version;
ret = pci_read_config_dword(vdev->pdev, OPREGION_PCI_ADDR, &addr);
if (ret)
@@ -83,6 +88,50 @@ static int vfio_pci_igd_opregion_init(struct vfio_pci_device
*vdev)
size *= 1024; /* In KB */
+ /*
+* Support opregion v2.1+
+* When VBT data exceeds 6KB size and cannot be within mailbox #4
+* Extended VBT region, next to opregion, is used to hold the VBT data.
+* RVDA (Relative Address of VBT Data from Opregion Base) and RVDS
+* (VBT Data Size) from opregion structure member are used to hold the
+* address from region base and size of VBT data while RVDA/RVDS
+* are not defined before opregion 2.0.
+*
+* opregion 2.0: rvda is the physical VBT address.
+*
+* opregion 2.1+: rvda is unsigned, relative offset from
+* opregion base, and should never point within opregion.
+*/
+ version = le16_to_cpu(*(__le16 *)(base + OPREGION_VERSION));
+ if (version >= 0x0200) {
+ u64 rvda;
+ u32 rvds;
+
+ rvda = le64_to_cpu(*(__le64 *)(base + OPREGION_RVDA));
+ rvds = le32_to_cpu(*(__le32 *)(base + OPREGION_RVDS));
+ if (rvda && rvds) {
+ /* no support for opregion v2.0 with physical VBT
address */
+ if (version == 0x0200) {
+ memunmap(base);
+ pci_err(vdev->pdev,
+ "IGD passthrough does not support
opregion\n"
+ "version 0x%x with physical rvda
0x%llx\n", version, rvda);
+ return -EINVAL;
+ }
+
+ if ((u32)rvda != size) {
+ memunmap(base);
+ pci_err(vdev->pdev,
+ "Extended VBT does not follow opregion
!\n"
+ "opregion version 0x%x:rvda 0x%llx\n",
version, rvda);
+ return -EINVAL;
+ }
+
+ /* region size for opregion v2.0+: opregion and VBT
size */
+ size += rvds;
+ }
+ }
+
if (size != OPREGION_SIZE) {
memunmap(base);
base = memremap(addr, size, MEMREMAP_WB);
--
2.24.1.1.gb6d4d82bd5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev4)
== Series Details == Series: drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev4) URL : https://patchwork.freedesktop.org/series/81764/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0c4bb5d01f88 drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 -:40: WARNING:LINE_SPACING: Missing a blank line after declarations #40: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:887: + u32 mcr, mcr_mask; + GEM_BUG_ON(INTEL_GEN(i915) < 9); total: 0 errors, 1 warnings, 0 checks, 46 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev4)
== Series Details ==
Series: drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
(rev4)
URL : https://patchwork.freedesktop.org/series/81764/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9819 -> Patchwork_19739
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/index.html
Known issues
Here are the changes found in Patchwork_19739 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@memory-alloc:
- fi-cml-u2: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2: NOTRUN -> [SKIP][2] ([i915#1208]) +1 similar issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-cml-u2: NOTRUN -> [SKIP][3] ([i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/fi-cml-u2/igt@gem_huc_c...@huc-copy.html
* igt@gem_tiled_blits@basic:
- fi-kbl-8809g: [PASS][4] -> [TIMEOUT][5] ([i915#2502])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9819/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [PASS][6] -> [INCOMPLETE][7] ([i915#2940])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9819/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
- fi-bsw-n3050: [PASS][8] -> [INCOMPLETE][9] ([i915#2940])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9819/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-cml-u2: NOTRUN -> [SKIP][10] ([i915#1004]) +2 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/fi-cml-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_chamelium@vga-edid-read:
- fi-cml-u2: NOTRUN -> [SKIP][11] ([fdo#109309]) +1 similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/fi-cml-u2/igt@kms_chamel...@vga-edid-read.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2: NOTRUN -> [SKIP][12] ([fdo#109285])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/fi-cml-u2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2: NOTRUN -> [SKIP][13] ([fdo#109278] / [i915#533])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/fi-cml-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> [FAIL][14] ([i915#1436])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/fi-bsw-kefka/igt@run...@aborted.html
- fi-bsw-n3050: NOTRUN -> [FAIL][15] ([i915#1436])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/fi-bsw-n3050/igt@run...@aborted.html
* igt@vgem_basic@setversion:
- fi-tgl-y: [PASS][16] -> [DMESG-WARN][17] ([i915#402]) +2
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9819/fi-tgl-y/igt@vgem_ba...@setversion.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/fi-tgl-y/igt@vgem_ba...@setversion.html
Possible fixes
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][18] ([i915#402]) -> [PASS][19] +1
similar issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9819/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1004]: https://gitlab.freedesktop.org/drm/intel/issues/1004
[i915#1021]: https://gitlab.freedesktop.org/drm/intel
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev4)
== Series Details == Series: drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev4) URL : https://patchwork.freedesktop.org/series/81764/ State : success == Summary == CI Bug Log - changes from CI_DRM_9819_full -> Patchwork_19739_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/index.html Changes --- No changes found Participating hosts (8 -> 8) -- No changes in participating hosts Build changes - * Linux: CI_DRM_9819 -> Patchwork_19739 CI_DRM_9819: 52e5817b130a97930caddaf02dcbaca717028b77 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6016: 2107b0a53692fb329175bc16169c3699712187aa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19739: 0c4bb5d01f88a9b44b35672067ff09b207a64506 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19739/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to
resolve VP8 hardware encoding system hang up on GT1 sku for
ChromiumOS projects
Slice specific MMIO read inaccurate so MGSR needs to be programmed
appropriately to get correct reads from these slicet-related MMIOs.
It dictates that before any MMIO read into Slice/Subslice specific
registers, MCR packet control register(0xFDC) needs to be programmed
to point to any enabled slice/subslice pair, especially GT1 fused sku
since this issue can be reproduced on VP8 hardware encoding via ffmpeg
on ChromiumOS devices.
When exit PC7, MGSR will reset so that we have to skip fused subslice ID.
Reference: HSD#1508045018,1405586840, BSID#0575
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: William Tseng
Cc: Lee Shawn C
Signed-off-by: Cooper Chiou
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3b4a7da60f0b..4ad598a727a6 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -878,9 +878,47 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
}
+static void
+gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
+ unsigned int slice, subslice;
+ u32 mcr, mcr_mask;
+
+ GEM_BUG_ON(INTEL_GEN(i915) < 9);
+
+ /*
+* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml
+* Before any MMIO read into slice/subslice specific registers, MCR
+* packet control register needs to be programmed to point to any
+* enabled s/ss pair. Otherwise, incorrect values will be returned.
+* This means each subsequent MMIO read will be forwarded to an
+* specific s/ss combination, but this is OK since these registers
+* are consistent across s/ss in almost all cases. In the rare
+* occasions, such as INSTDONE, where this value is dependent
+* on s/ss combo, the read should be done with read_subslice_reg.
+*/
+ slice = fls(sseu->slice_mask) - 1;
+ GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
+ subslice = fls(intel_sseu_get_subslices(sseu, slice));
+ GEM_BUG_ON(!subslice);
+ subslice--;
+
+ mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+ mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
+
+ drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice,
mcr);
+
+ wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
+}
+
static void
gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
{
+ /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml */
+ if (!IS_COFFEELAKE(i915))
+ gen9_wa_init_mcr(i915, wal);
+
/* WaDisableKillLogic:bxt,skl,kbl */
if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915))
wa_write_or(wal,
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for vfio/pci: Add support for opregion v2.0+ (rev4)
== Series Details ==
Series: vfio/pci: Add support for opregion v2.0+ (rev4)
URL : https://patchwork.freedesktop.org/series/84494/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9819 -> Patchwork_19740
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19740 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19740, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19740/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19740:
### IGT changes ###
Possible regressions
* igt@gem_exec_gttfill@basic:
- fi-kbl-8809g: [PASS][1] -> [TIMEOUT][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9819/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19740/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html
Known issues
Here are the changes found in Patchwork_19740 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@memory-alloc:
- fi-cml-u2: NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19740/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [PASS][4] -> [DMESG-WARN][5] ([i915#402]) +2 similar
issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9819/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19740/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2: NOTRUN -> [SKIP][6] ([i915#1208]) +1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19740/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-cml-u2: NOTRUN -> [SKIP][7] ([i915#2190])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19740/fi-cml-u2/igt@gem_huc_c...@huc-copy.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-cml-u2: NOTRUN -> [SKIP][8] ([i915#1004]) +2 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19740/fi-cml-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_chamelium@vga-edid-read:
- fi-cml-u2: NOTRUN -> [SKIP][9] ([fdo#109309]) +1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19740/fi-cml-u2/igt@kms_chamel...@vga-edid-read.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2: NOTRUN -> [SKIP][10] ([fdo#109285])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19740/fi-cml-u2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2: NOTRUN -> [SKIP][11] ([fdo#109278] / [i915#533])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19740/fi-cml-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
Possible fixes
* igt@gem_linear_blits@basic:
- fi-kbl-8809g: [TIMEOUT][12] ([i915#2502]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9819/fi-kbl-8809g/igt@gem_linear_bl...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19740/fi-kbl-8809g/igt@gem_linear_bl...@basic.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][14] ([i915#402]) -> [PASS][15] +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9819/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19740/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1004]: https://gitlab.freedesktop.org/drm/intel/issues/1004
[i915#1021]: https://gitlab.freedesktop.org/drm/intel/issues/1021
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1208]: https://gitlab.freedesktop.org/drm/intel/issues/1208
[i915#2190]: https://gitlab.freedesktop.org/drm/in
[Intel-gfx] ✓ Fi.CI.IGT: success for vfio/pci: Add support for opregion v2.0+ (rev4)
== Series Details == Series: vfio/pci: Add support for opregion v2.0+ (rev4) URL : https://patchwork.freedesktop.org/series/84494/ State : success == Summary == CI Bug Log - changes from CI_DRM_9819_full -> Patchwork_19740_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19740/index.html Changes --- No changes found Participating hosts (8 -> 8) -- No changes in participating hosts Build changes - * Linux: CI_DRM_9819 -> Patchwork_19740 CI_DRM_9819: 52e5817b130a97930caddaf02dcbaca717028b77 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6016: 2107b0a53692fb329175bc16169c3699712187aa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19740: 037079b93d89ddae6130fd4a0d43d5fb7a84cd45 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19740/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
Hi Tvrtko,
This WaProgramMgsrForCorrectSliceSpecificMmioReads info can be found on bspec
WA#0575 and it's necessary for GT subslice fuse sku on PC7 exit case while
running VP8 hw encode, it impacted CrOS projects since google disabled VP8 HW
encode feature on Gen9 sku, so that's why we need this patch.
Best Regards,
Cooper
>
> WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to
> resolve VP8 hardware encoding system hang up on GT1 sku for ChromiumOS
> projects
>
> Slice specific MMIO read inaccurate so MGSR needs to be programmed
> appropriately to get correct reads from these slicet-related MMIOs.
>
> It dictates that before any MMIO read into Slice/Subslice specific registers,
> MCR packet control register(0xFDC) needs to be programmed to point to
> any enabled slice/subslice pair, especially GT1 fused sku since this issue can
> be reproduced on VP8 hardware encoding via ffmpeg on ChromiumOS
> devices.
> When exit PC7, MGSR will reset so that we have to skip fused subslice ID.
>
> Reference: HSD#1508045018,1405586840, BSID#0575
>
> Cc: Ville Syrjälä
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Chris Wilson
> Cc: Tvrtko Ursulin
> Cc: William Tseng
> Cc: Lee Shawn C
>
> Signed-off-by: Cooper Chiou
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 38
> +
> 1 file changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3b4a7da60f0b..4ad598a727a6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -878,9 +878,47 @@ hsw_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
> wa_write_clr(wal, GEN7_FF_THREAD_MODE,
> GEN7_FF_VS_REF_CNT_FFME); }
>
> +static void
> +gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list
> +*wal) {
> + const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
> + unsigned int slice, subslice;
> + u32 mcr, mcr_mask;
> +
> + GEM_BUG_ON(INTEL_GEN(i915) < 9);
> +
> + /*
> + * WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml
> + * Before any MMIO read into slice/subslice specific registers, MCR
> + * packet control register needs to be programmed to point to any
> + * enabled s/ss pair. Otherwise, incorrect values will be returned.
> + * This means each subsequent MMIO read will be forwarded to an
> + * specific s/ss combination, but this is OK since these registers
> + * are consistent across s/ss in almost all cases. In the rare
> + * occasions, such as INSTDONE, where this value is dependent
> + * on s/ss combo, the read should be done with read_subslice_reg.
> + */
> + slice = fls(sseu->slice_mask) - 1;
> + GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
> + subslice = fls(intel_sseu_get_subslices(sseu, slice));
> + GEM_BUG_ON(!subslice);
> + subslice--;
> +
> + mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
> + mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
> +
> + drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice,
> +subslice, mcr);
> +
> + wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); }
> +
> static void
> gen9_gt_workarounds_init(struct drm_i915_private *i915, struct
> i915_wa_list *wal) {
> + /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml */
> + if (!IS_COFFEELAKE(i915))
> + gen9_wa_init_mcr(i915, wal);
> +
> /* WaDisableKillLogic:bxt,skl,kbl */
> if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915))
> wa_write_or(wal,
> --
> 2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev5)
== Series Details ==
Series: drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
(rev5)
URL : https://patchwork.freedesktop.org/series/81764/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9819 -> Patchwork_19741
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_19741 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19741, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19741/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19741:
### IGT changes ###
Warnings
* igt@i915_pm_rpm@module-reload:
- fi-glk-dsi: [DMESG-WARN][1] ([i915#1982]) -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9819/fi-glk-dsi/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19741/fi-glk-dsi/igt@i915_pm_...@module-reload.html
Known issues
Here are the changes found in Patchwork_19741 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@memory-alloc:
- fi-cml-u2: NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19741/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2: NOTRUN -> [SKIP][4] ([i915#1208]) +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19741/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-cml-u2: NOTRUN -> [SKIP][5] ([i915#2190])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19741/fi-cml-u2/igt@gem_huc_c...@huc-copy.html
* igt@gem_tiled_blits@basic:
- fi-kbl-8809g: [PASS][6] -> [TIMEOUT][7] ([i915#2502])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9819/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19741/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-cml-u2: NOTRUN -> [SKIP][8] ([i915#1004]) +2 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19741/fi-cml-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_chamelium@vga-edid-read:
- fi-cml-u2: NOTRUN -> [SKIP][9] ([fdo#109309]) +1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19741/fi-cml-u2/igt@kms_chamel...@vga-edid-read.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2: NOTRUN -> [SKIP][10] ([fdo#109285])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19741/fi-cml-u2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2: NOTRUN -> [SKIP][11] ([fdo#109278] / [i915#533])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19741/fi-cml-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y: [PASS][12] -> [DMESG-WARN][13] ([i915#402]) +1
similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9819/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19741/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
Possible fixes
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][14] ([i915#402]) -> [PASS][15] +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9819/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19741/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1004]: https://gitlab.freedesktop.org/drm/intel/issues/1004
[i915#1021]: https://gitlab.freedesktop.org/drm/intel/issues/1021
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1208]: https://gitlab.freedesktop.org/drm/intel/issues/1208
[i915#1982]: ht
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev5)
== Series Details == Series: drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev5) URL : https://patchwork.freedesktop.org/series/81764/ State : success == Summary == CI Bug Log - changes from CI_DRM_9819_full -> Patchwork_19741_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19741/index.html Changes --- No changes found Participating hosts (8 -> 8) -- No changes in participating hosts Build changes - * Linux: CI_DRM_9819 -> Patchwork_19741 CI_DRM_9819: 52e5817b130a97930caddaf02dcbaca717028b77 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6016: 2107b0a53692fb329175bc16169c3699712187aa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19741: 77d5bfff392b17179ccfeb0b99417cfcae07c728 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19741/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
