[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/display: Fix state mismatch in drm infoframe (rev3)
== Series Details == Series: drm/i915/display: Fix state mismatch in drm infoframe (rev3) URL : https://patchwork.freedesktop.org/series/89225/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4] drm/doc/rfc: i915 DG1 uAPI
On Tue, 20 Apr 2021 at 02:45, Matthew Auld wrote: > > Add an entry for the new uAPI needed for DG1. Also add the overall > upstream plan, including some notes for the TTM conversion. > > v2(Daniel): > - include the overall upstreaming plan > - add a note for mmap, there are differences here for TTM vs i915 > - bunch of other suggestions from Daniel > v3: > (Daniel) > - add a note for set/get caching stuff > - add some more docs for existing query and extensions stuff > - add an actual code example for regions query > - bunch of other stuff > (Jason) > - uAPI change(!): > - try a simpler design with the placements extension > - rather than have a generic setparam which can cover multiple > use cases, have each extension be responsible for one thing > only > v4: > (Daniel) > - add some more notes for ttm conversion > - bunch of other stuff > (Jason) > - uAPI change(!): > - drop all the extra rsvd members for the region_query and > region_info, just keep the bare minimum needed for padding Staying out of the ioctl's being over engineering, I hope they have a good future use case. The plan seems like a good plan. Acked-by: Dave Airlie Dave. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [V3] drm/i915/display: Fix state mismatch in drm infoframe
While reading the SDP infoframe, we are getting filtered with
the encoder type INTEL_OUTPUT_DDI which causes the infoframe
mismatch. This patch will drop encoder->type check as we can
mask individual infoframe type.
[1025.606556] i915 :00:02.0: [drm] *ERROR* mismatch in drm infoframe
[1025.607865] i915 :00:02.0: [drm] *ERROR* expected:
[1025.607879] i915 :00:02.0: HDMI infoframe: Dynamic Range and Mastering,
version 1, length 26
[1025.607889] i915 :00:02.0: length: 26
[1025.607898] i915 :00:02.0: metadata type: 0
[1025.608292] i915 :00:02.0: eotf: 2
[1025.608302] i915 :00:02.0: x[0]: 35400
[1025.608312] i915 :00:02.0: y[0]: 14599
[1025.609115] i915 :00:02.0: x[1]: 8500
[1025.609947] i915 :00:02.0: y[1]: 39850
[1025.609959] i915 :00:02.0: x[2]: 6550
[1025.609970] i915 :00:02.0: y[2]: 2300
[1025.609980] i915 :00:02.0: white point x: 15634
[1025.609989] i915 :00:02.0: white point y: 16450
[1025.610381] i915 :00:02.0: max_display_mastering_luminance: 1000
[1025.610392] i915 :00:02.0: min_display_mastering_luminance: 500
[1025.610401] i915 :00:02.0: max_cll: 500
[1025.610816] i915 :00:02.0: max_fall: 1000
[1025.612457] i915 :00:02.0: [drm] *ERROR* found:
[1025.614354] [ cut here ]
[1025.616244] pipe state doesn't match!
[1025.617640] WARNING: CPU: 6 PID: 2114 at
drivers/gpu/drm/i915/display/intel_display.c:9332
intel_atomic_commit_tail+0x14d4/0x17c0 [i915]
V2:
* Drop encoder->type check
V3:
* Remove internal reviews
Cc: Uma Shankar
Cc: Ville Syrjälä
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4ad12dde5938..280b0b5ee70e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3014,9 +3014,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
unsigned int type)
{
- if (encoder->type != INTEL_OUTPUT_DDI)
- return;
-
switch (type) {
case DP_SDP_VSC:
intel_read_dp_vsc_sdp(encoder, crtc_state,
--
2.20.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops (rev2)
== Series Details == Series: drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops (rev2) URL : https://patchwork.freedesktop.org/series/89374/ State : success == Summary == CI Bug Log - changes from CI_DRM_1 -> Patchwork_19978 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19978/index.html Known issues Here are the changes found in Patchwork_19978 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19978/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +9 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19978/fi-kbl-soraka/igt@amdgpu/amd_cs_...@sync-fork-compute0.html * igt@amdgpu/amd_prime@amd-to-i915: - fi-tgl-y: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19978/fi-tgl-y/igt@amdgpu/amd_pr...@amd-to-i915.html * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][4] ([i915#2283]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19978/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19978/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 Participating hosts (41 -> 38) -- Missing(3): fi-bdw-samus fi-bsw-cyan fi-apl-guc Build changes - * Linux: CI_DRM_1 -> Patchwork_19978 CI-20190529: 20190529 CI_DRM_1: 44407be4a35b68f51c6c64e57eb0cf797b9e2e5d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6072: 0a51f49df9f5ca535fc0206a27a6780de6b52320 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19978: 5f3807d8462ed91b9b161e83f9cd87e2a445d800 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5f3807d8462e drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19978/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops (rev2)
== Series Details == Series: drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops (rev2) URL : https://patchwork.freedesktop.org/series/89374/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops (rev2)
== Series Details == Series: drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops (rev2) URL : https://patchwork.freedesktop.org/series/89374/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5f3807d8462e drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops -:25: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #25: References: https://lore.kernel.org/intel-gfx/1460040732-31417-4-git-send-email-animesh.ma...@intel.com/ total: 0 errors, 1 warnings, 0 checks, 75 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops
On HP Fury G7 Workstations, graphics output is re-routed from Intel GFX
to discrete GFX after S3. This is not desirable, because userspace will
treat connected display as a new one, losing display settings.
The expected behavior is to let discrete GFX drives all external
displays.
The platform in question uses ACPI method \_SB.PCI0.HGME to enable MUX.
The method is inside the BXT _DSM, so add the _DSM and call it
accordingly.
I also tested some MUX-less and iGPU only laptops with the BXT _DSM, no
regression was found.
v2:
- Forward declare struct pci_dev.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3113
References:
https://lore.kernel.org/intel-gfx/1460040732-31417-4-git-send-email-animesh.ma...@intel.com/
Signed-off-by: Kai-Heng Feng
---
drivers/gpu/drm/i915/display/intel_acpi.c | 17 +
drivers/gpu/drm/i915/display/intel_acpi.h | 3 +++
drivers/gpu/drm/i915/i915_drv.c | 5 +
3 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c
b/drivers/gpu/drm/i915/display/intel_acpi.c
index 833d0c1be4f1..c7b57c22dce3 100644
--- a/drivers/gpu/drm/i915/display/intel_acpi.c
+++ b/drivers/gpu/drm/i915/display/intel_acpi.c
@@ -14,11 +14,16 @@
#define INTEL_DSM_REVISION_ID 1 /* For Calpella anyway... */
#define INTEL_DSM_FN_PLATFORM_MUX_INFO 1 /* No args */
+#define INTEL_DSM_FN_PLATFORM_BXT_MUX_INFO 0 /* No args */
static const guid_t intel_dsm_guid =
GUID_INIT(0x7ed873d3, 0xc2d0, 0x4e4f,
0xa8, 0x54, 0x0f, 0x13, 0x17, 0xb0, 0x1c, 0x2c);
+static const guid_t intel_bxt_dsm_guid =
+ GUID_INIT(0x3e5b41c6, 0xeb1d, 0x4260,
+ 0x9d, 0x15, 0xc7, 0x1f, 0xba, 0xda, 0xe4, 0x14);
+
static char *intel_dsm_port_name(u8 id)
{
switch (id) {
@@ -176,6 +181,18 @@ void intel_unregister_dsm_handler(void)
{
}
+void intel_bxt_dsm_detect(struct pci_dev *pdev)
+{
+ acpi_handle dhandle;
+
+ dhandle = ACPI_HANDLE(&pdev->dev);
+ if (!dhandle)
+ return;
+
+ acpi_evaluate_dsm(dhandle, &intel_bxt_dsm_guid, INTEL_DSM_REVISION_ID,
+ INTEL_DSM_FN_PLATFORM_BXT_MUX_INFO, NULL);
+}
+
/*
* ACPI Specification, Revision 5.0, Appendix B.3.2 _DOD (Enumerate All Devices
* Attached to the Display Adapter).
diff --git a/drivers/gpu/drm/i915/display/intel_acpi.h
b/drivers/gpu/drm/i915/display/intel_acpi.h
index e8b068661d22..d2d560d63bb3 100644
--- a/drivers/gpu/drm/i915/display/intel_acpi.h
+++ b/drivers/gpu/drm/i915/display/intel_acpi.h
@@ -6,15 +6,18 @@
#ifndef __INTEL_ACPI_H__
#define __INTEL_ACPI_H__
+struct pci_dev;
struct drm_i915_private;
#ifdef CONFIG_ACPI
void intel_register_dsm_handler(void);
void intel_unregister_dsm_handler(void);
+void intel_bxt_dsm_detect(struct pci_dev *pdev);
void intel_acpi_device_id_update(struct drm_i915_private *i915);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
+static inline void intel_bxt_dsm_detect(struct pci_dev *pdev) { return; }
static inline
void intel_acpi_device_id_update(struct drm_i915_private *i915) { return; }
#endif /* CONFIG_ACPI */
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 785dcf20c77b..57b12068aab4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -853,6 +853,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (ret)
goto out_cleanup_gem;
+ intel_bxt_dsm_detect(pdev);
+
i915_driver_register(i915);
enable_rpm_wakeref_asserts(&i915->runtime_pm);
@@ -1215,6 +1217,7 @@ int i915_suspend_switcheroo(struct drm_i915_private
*i915, pm_message_t state)
static int i915_drm_resume(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
int ret;
disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
@@ -1271,6 +1274,8 @@ static int i915_drm_resume(struct drm_device *dev)
intel_gvt_resume(dev_priv);
+ intel_bxt_dsm_detect(pdev);
+
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
return 0;
--
2.30.2
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Re: [Intel-gfx] [PATCH] vfio/gvt: fix DRM_I915_GVT dependency on VFIO_MDEV
On 2021.04.22 10:58:10 -0300, Jason Gunthorpe wrote:
> On Thu, Apr 22, 2021 at 03:35:33PM +0200, Arnd Bergmann wrote:
> > From: Arnd Bergmann
> >
> > The Kconfig dependency is incomplete since DRM_I915_GVT is a 'bool'
> > symbol that depends on the 'tristate' VFIO_MDEV. This allows a
> > configuration with VFIO_MDEV=m, DRM_I915_GVT=y and DRM_I915=y that
> > causes a link failure:
> >
> > x86_64-linux-ld: drivers/gpu/drm/i915/gvt/gvt.o: in function
> > `available_instances_show':
> > gvt.c:(.text+0x67a): undefined reference to `mtype_get_parent_dev'
> > x86_64-linux-ld: gvt.c:(.text+0x6a5): undefined reference to
> > `mtype_get_type_group_id'
> > x86_64-linux-ld: drivers/gpu/drm/i915/gvt/gvt.o: in function
> > `description_show':
> > gvt.c:(.text+0x76e): undefined reference to `mtype_get_parent_dev'
> > x86_64-linux-ld: gvt.c:(.text+0x799): undefined reference to
> > `mtype_get_type_group_id'
> >
> > Clarify the dependency by specifically disallowing the broken
> > configuration. If VFIO_MDEV is built-in, it will work, but if
> > VFIO_MDEV=m, the i915 driver cannot be built-in here.
> >
> > Fixes: 07e543f4f9d1 ("vfio/gvt: Make DRM_I915_GVT depend on VFIO_MDEV")
> > Fixes: 9169cff168ff ("vfio/mdev: Correct the function signatures for the
> > mdev_type_attributes")
> > Signed-off-by: Arnd Bergmann
> > ---
> > drivers/gpu/drm/i915/Kconfig | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Oh kconfig stuff like this makes my head hurt, thanks for finding it
>
> I also can't see an alternative to this ugly thing, besides having the
> i915 guys properly modularize this code someday
>
> Reviewed-by: Jason Gunthorpe
>
I don't really want this mess to propagate further. We should move
mdev related stuff to kvmgt module instead, so not pretend any more to
possibly use that for other hypervisor..
Sorry that I didn't realize this issue when Jason proposed this. Let
me do the left cleanup.
Thanks
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Re: [Intel-gfx] [PATCH v3 03/20] drm/dp: Move i2c init to drm_dp_aux_init, add __must_check and fini
On Thu, 2021-04-22 at 18:33 -0400, Lyude Paul wrote: > OK - talked with Ville a bit on this and did some of my own research, I > actually think that moving i2c to drm_dp_aux_init() is the right decision > for > the time being. The reasoning behind this being that as shown by my previous > work of fixing drivers that call drm_dp_aux_register() too early - it seems > like there's already been drivers that have been working just fine with > setting up the i2c device before DRM registration. > > In the future, it'd probably be better if we can split up i2c_add_adapter() > into an init and register function - but we'll have to talk with the i2c > maintainers to see if this is acceptable w/ them Actually - I think adding the ability to refcount dp aux adapters might be a better solution so I'm going to try that! > > On Thu, 2021-04-22 at 13:18 -0400, Lyude Paul wrote: > > On Tue, 2021-04-20 at 02:16 +0300, Ville Syrjälä wrote: > > > > > > The init vs. register split is intentional. Registering the thing > > > and allowing userspace access to it before the rest of the driver > > > is ready isn't particularly great. For a while now we've tried to > > > move towards an architecture where the driver is fully initialzied > > > before anything gets exposed to userspace. > > > > Yeah-thank you for pointing this out. Thierry - do you think there's an > > alternate solution we could go with in Tegra to fix the get_device() issue > > that wouldn't require us trying to expose the i2c adapter early? > > > > > > > > -- Cheers, Lyude Paul (she/her) Software Engineer at Red Hat ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 16/16] of: Add plumbing for restricted DMA pool
On Thu, Apr 22, 2021 at 4:17 PM Claire Chang wrote:
>
> If a device is not behind an IOMMU, we look up the device node and set
> up the restricted DMA when the restricted-dma-pool is presented.
>
> Signed-off-by: Claire Chang
> ---
> drivers/of/address.c| 25 +
> drivers/of/device.c | 3 +++
> drivers/of/of_private.h | 5 +
> 3 files changed, 33 insertions(+)
>
> diff --git a/drivers/of/address.c b/drivers/of/address.c
> index 54f221dde267..fff3adfe4986 100644
> --- a/drivers/of/address.c
> +++ b/drivers/of/address.c
> @@ -8,6 +8,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -1109,6 +1110,30 @@ bool of_dma_is_coherent(struct device_node *np)
> }
> EXPORT_SYMBOL_GPL(of_dma_is_coherent);
>
> +int of_dma_set_restricted_buffer(struct device *dev)
> +{
> + struct device_node *node;
> + int count, i;
> +
> + if (!dev->of_node)
> + return 0;
> +
> + count = of_property_count_elems_of_size(dev->of_node, "memory-region",
> + sizeof(phandle));
> + for (i = 0; i < count; i++) {
> + node = of_parse_phandle(dev->of_node, "memory-region", i);
> + /* There might be multiple memory regions, but only one
> +* restriced-dma-pool region is allowed.
> +*/
> + if (of_device_is_compatible(node, "restricted-dma-pool") &&
> + of_device_is_available(node))
> + return of_reserved_mem_device_init_by_idx(
> + dev, dev->of_node, i);
> + }
> +
> + return 0;
> +}
> +
> /**
> * of_mmio_is_nonposted - Check if device uses non-posted MMIO
> * @np:device node
> diff --git a/drivers/of/device.c b/drivers/of/device.c
> index c5a9473a5fb1..d8d865223e51 100644
> --- a/drivers/of/device.c
> +++ b/drivers/of/device.c
> @@ -165,6 +165,9 @@ int of_dma_configure_id(struct device *dev, struct
> device_node *np,
>
> arch_setup_dma_ops(dev, dma_start, size, iommu, coherent);
>
> + if (!iommu)
> + return of_dma_set_restricted_buffer(dev);
> +
> return 0;
> }
> EXPORT_SYMBOL_GPL(of_dma_configure_id);
> diff --git a/drivers/of/of_private.h b/drivers/of/of_private.h
> index d717efbd637d..e9237f5eff48 100644
> --- a/drivers/of/of_private.h
> +++ b/drivers/of/of_private.h
> @@ -163,12 +163,17 @@ struct bus_dma_region;
> #if defined(CONFIG_OF_ADDRESS) && defined(CONFIG_HAS_DMA)
> int of_dma_get_range(struct device_node *np,
> const struct bus_dma_region **map);
> +int of_dma_set_restricted_buffer(struct device *dev);
> #else
> static inline int of_dma_get_range(struct device_node *np,
> const struct bus_dma_region **map)
> {
> return -ENODEV;
> }
> +static inline int of_dma_get_restricted_buffer(struct device *dev)
This one should be of_dma_set_restricted_buffer. Sorry for the typo.
> +{
> + return -ENODEV;
> +}
> #endif
>
> #endif /* _LINUX_OF_PRIVATE_H */
> --
> 2.31.1.368.gbe11c130af-goog
>
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/fbc: Avoid GLK+ FBC corruption (rev2)
== Series Details == Series: drm/i915/fbc: Avoid GLK+ FBC corruption (rev2) URL : https://patchwork.freedesktop.org/series/89379/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9998_full -> Patchwork_19977_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19977_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19977_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19977_full: ### IGT changes ### Possible regressions * igt@kms_async_flips@test-time-stamp: - shard-kbl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-kbl2/igt@kms_async_fl...@test-time-stamp.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/shard-kbl1/igt@kms_async_fl...@test-time-stamp.html - shard-glk: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-glk8/igt@kms_async_fl...@test-time-stamp.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/shard-glk7/igt@kms_async_fl...@test-time-stamp.html * igt@kms_big_fb@y-tiled-16bpp-rotate-0: - shard-iclb: [PASS][5] -> [FAIL][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-iclb3/igt@kms_big...@y-tiled-16bpp-rotate-0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/shard-iclb4/igt@kms_big...@y-tiled-16bpp-rotate-0.html Known issues Here are the changes found in Patchwork_19977_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@process: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/shard-snb5/igt@gem_ctx_persiste...@process.html * igt@gem_ctx_sseu@mmap-args: - shard-tglb: NOTRUN -> [SKIP][8] ([i915#280]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/shard-tglb6/igt@gem_ctx_s...@mmap-args.html * igt@gem_exec_capture@pi@vecs0: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#198] / [i915#2624]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-skl10/igt@gem_exec_capture@p...@vecs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/shard-skl6/igt@gem_exec_capture@p...@vecs0.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/shard-tglb5/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: NOTRUN -> [FAIL][13] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/shard-kbl7/igt@gem_exec_fair@basic-n...@vecs0.html - shard-apl: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-apl6/igt@gem_exec_fair@basic-n...@vecs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/shard-apl6/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/shard-iclb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html - shard-glk: NOTRUN -> [FAIL][17] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/shard-glk4/igt@gem_exec_fair@basic-pace-s...@rcs0.html - shard-tglb: NOTRUN -> [FAIL][18] ([i915#2842]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/shard-tglb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][19] -> [FAIL][20] ([i915#2842]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-kbl7/igt@gem_exec_fair@basic-p...@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/shard-kbl3/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][21] -> [FAIL][22] ([i915#2842]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: -
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: Avoid GLK+ FBC corruption (rev2)
== Series Details ==
Series: drm/i915/fbc: Avoid GLK+ FBC corruption (rev2)
URL : https://patchwork.freedesktop.org/series/89379/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9998 -> Patchwork_19977
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/index.html
Known issues
Here are the changes found in Patchwork_19977 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][1] ([i915#3303]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#3180]: https://gitlab.freedesktop.org/drm/intel/issues/3180
[i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
[i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
Participating hosts (42 -> 40)
--
Missing(2): fi-bsw-cyan fi-bdw-samus
Build changes
-
* IGT: IGT_6072 -> IGTPW_5754
* Linux: CI_DRM_9998 -> Patchwork_19977
CI-20190529: 20190529
CI_DRM_9998: b60045f9e62eee599257a084e4481bae7fe7ef9f @
git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5754: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5754/index.html
IGT_6072: 0a51f49df9f5ca535fc0206a27a6780de6b52320 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19977: 7075a82fab2972f135590cd4318091d0be292827 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7075a82fab29 drm/i915: Remove redundant DIRTYFB frontbuffer flushes
4470ff5c03e5 drm/i915/fbc: Don't nuke manually around flips
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19977/index.html
___
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/fbc: Avoid GLK+ FBC corruption (rev2)
== Series Details == Series: drm/i915/fbc: Avoid GLK+ FBC corruption (rev2) URL : https://patchwork.freedesktop.org/series/89379/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/fbc: Avoid GLK+ FBC corruption
== Series Details == Series: drm/i915/fbc: Avoid GLK+ FBC corruption URL : https://patchwork.freedesktop.org/series/89379/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9998_full -> Patchwork_19976_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19976_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19976_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19976_full: ### IGT changes ### Possible regressions * igt@kms_async_flips@test-time-stamp: - shard-kbl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-kbl2/igt@kms_async_fl...@test-time-stamp.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/shard-kbl6/igt@kms_async_fl...@test-time-stamp.html - shard-glk: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-glk8/igt@kms_async_fl...@test-time-stamp.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/shard-glk7/igt@kms_async_fl...@test-time-stamp.html * igt@kms_ccs@pipe-a-crc-sprite-planes-basic: - shard-iclb: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-iclb1/igt@kms_...@pipe-a-crc-sprite-planes-basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/shard-iclb6/igt@kms_...@pipe-a-crc-sprite-planes-basic.html Known issues Here are the changes found in Patchwork_19976_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@process: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/shard-snb2/igt@gem_ctx_persiste...@process.html * igt@gem_ctx_sseu@mmap-args: - shard-tglb: NOTRUN -> [SKIP][8] ([i915#280]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/shard-tglb2/igt@gem_ctx_s...@mmap-args.html * igt@gem_exec_capture@pi@vecs0: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#198] / [i915#2624]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-skl10/igt@gem_exec_capture@p...@vecs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/shard-skl6/igt@gem_exec_capture@p...@vecs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-apl6/igt@gem_exec_fair@basic-n...@vecs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html - shard-glk: NOTRUN -> [FAIL][16] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/shard-glk6/igt@gem_exec_fair@basic-pace-s...@rcs0.html - shard-tglb: NOTRUN -> [FAIL][17] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/shard-tglb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][18] -> [FAIL][19] ([i915#2842]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs1.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/shard-kbl3/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][20] -> [FAIL][21] ([i915#2842]) +3 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html - shard-iclb: [PASS][22] -> [FAIL][23] ([i915#2849]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html [23]: https://intel-gfx-ci.01.org/tr
Re: [Intel-gfx] [PATCH v3 03/20] drm/dp: Move i2c init to drm_dp_aux_init, add __must_check and fini
OK - talked with Ville a bit on this and did some of my own research, I actually think that moving i2c to drm_dp_aux_init() is the right decision for the time being. The reasoning behind this being that as shown by my previous work of fixing drivers that call drm_dp_aux_register() too early - it seems like there's already been drivers that have been working just fine with setting up the i2c device before DRM registration. In the future, it'd probably be better if we can split up i2c_add_adapter() into an init and register function - but we'll have to talk with the i2c maintainers to see if this is acceptable w/ them On Thu, 2021-04-22 at 13:18 -0400, Lyude Paul wrote: > On Tue, 2021-04-20 at 02:16 +0300, Ville Syrjälä wrote: > > > > The init vs. register split is intentional. Registering the thing > > and allowing userspace access to it before the rest of the driver > > is ready isn't particularly great. For a while now we've tried to > > move towards an architecture where the driver is fully initialzied > > before anything gets exposed to userspace. > > Yeah-thank you for pointing this out. Thierry - do you think there's an > alternate solution we could go with in Tegra to fix the get_device() issue > that wouldn't require us trying to expose the i2c adapter early? > > > > -- Cheers, Lyude Paul (she/her) Software Engineer at Red Hat ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 (rev2)
== Series Details == Series: drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 (rev2) URL : https://patchwork.freedesktop.org/series/89348/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9998_full -> Patchwork_19974_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19974_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19974_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19974_full: ### IGT changes ### Possible regressions * igt@kms_plane_cursor@pipe-a-viewport-size-64: - shard-tglb: [PASS][1] -> [FAIL][2] +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-tglb3/igt@kms_plane_cur...@pipe-a-viewport-size-64.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/shard-tglb1/igt@kms_plane_cur...@pipe-a-viewport-size-64.html Known issues Here are the changes found in Patchwork_19974_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: NOTRUN -> [DMESG-WARN][3] ([i915#180]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/shard-kbl7/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2410]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/shard-tglb5/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_ctx_persistence@process: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/shard-snb6/igt@gem_ctx_persiste...@process.html * igt@gem_exec_create@forked: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-glk7/igt@gem_exec_cre...@forked.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/shard-glk1/igt@gem_exec_cre...@forked.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/shard-tglb6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-kbl7/igt@gem_exec_fair@basic-p...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/shard-kbl6/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][13] -> [SKIP][14] ([fdo#109271]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][15] ([i915#2389]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/shard-apl8/igt@gem_exec_reloc@basic-wide-act...@bcs0.html * igt@gem_mmap_gtt@big-copy-odd: - shard-skl: [PASS][16] -> [FAIL][17] ([i915#307]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-skl9/igt@gem_mmap_...@big-copy-odd.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/shard-skl10/igt@gem_mmap_...@big-copy-odd.html * igt@gem_mmap_gtt@cpuset-big-copy-xy: - shard-glk: [PASS][18] -> [FAIL][19] ([i915#307]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-glk8/igt@gem_mmap_...@cpuset-big-copy-xy.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/shard-glk7/igt@gem_mmap_...@cpuset-big-copy-xy.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-apl: [PASS][20] -> [FAIL][21] ([i915#644]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-apl2/igt@gem_pp...@flink-and-close-vma-leak.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/shard-apl3/igt@gem_pp...@flink-and-close-vma-leak.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][22] ([i915#2658]) [22]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Make preempt timeout for banned contexts configurable
== Series Details == Series: drm/i915: Make preempt timeout for banned contexts configurable URL : https://patchwork.freedesktop.org/series/89369/ State : success == Summary == CI Bug Log - changes from CI_DRM_9998_full -> Patchwork_19973_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19973_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: NOTRUN -> [DMESG-WARN][1] ([i915#180]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-kbl7/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_ctx_persistence@process: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-snb5/igt@gem_ctx_persiste...@process.html * igt@gem_eio@in-flight-1us: - shard-skl: [PASS][3] -> [TIMEOUT][4] ([i915#3063]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-skl4/igt@gem_...@in-flight-1us.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-skl6/igt@gem_...@in-flight-1us.html * igt@gem_exec_create@forked: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-glk7/igt@gem_exec_cre...@forked.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-glk1/igt@gem_exec_cre...@forked.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-tglb6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2849]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_mmap_offset@clear: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#3160]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-skl1/igt@gem_mmap_off...@clear.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-skl9/igt@gem_mmap_off...@clear.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][13] ([i915#2658]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-apl3/igt@gem_pr...@exhaustion.html - shard-skl: NOTRUN -> [WARN][14] ([i915#2658]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-skl8/igt@gem_pr...@exhaustion.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][15] ([i915#3002]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-apl1/igt@gem_userptr_bl...@input-checking.html - shard-kbl: NOTRUN -> [DMESG-WARN][16] ([i915#3002]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-kbl3/igt@gem_userptr_bl...@input-checking.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#658]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-skl8/igt@i915_pm...@dc3co-vpb-simulation.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][18] -> [FAIL][19] ([i915#2574]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/shard-tglb6/igt@kms_async_fl...@test-time-stamp.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-tglb5/igt@kms_async_fl...@test-time-stamp.html * igt@kms_big_joiner@basic: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#2705]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-apl1/igt@kms_big_joi...@basic.html * igt@kms_ccs@pipe-c-ccs-on-another-bo: - shard-skl: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111304]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-skl8/igt@kms_...@pipe-c-ccs-on-another-bo.html * igt@kms_chamelium@hdmi-edid-change-during-suspend: - shard-apl: NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827]) +19 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/shard-apl1/igt@kms_chamel...@hdmi-edid-change-during-suspend.html * igt@kms_chamelium@hdmi-hpd-enable-disable-mode: - shard-snb: NOTRUN -> [SKIP][23] ([fdo#109271] / [fdo#111827]) +16 similar issues [23]: https://intel-gfx-ci.01.org/tre
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: Avoid GLK+ FBC corruption
== Series Details ==
Series: drm/i915/fbc: Avoid GLK+ FBC corruption
URL : https://patchwork.freedesktop.org/series/89379/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9998 -> Patchwork_19976
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/index.html
Known issues
Here are the changes found in Patchwork_19976 that come from known issues:
### IGT changes ###
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [FAIL][1] ([i915#1888]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][3] ([i915#3303]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
[i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
Participating hosts (42 -> 39)
--
Missing(3): fi-icl-y fi-bsw-cyan fi-bdw-samus
Build changes
-
* IGT: IGT_6072 -> IGTPW_5754
* Linux: CI_DRM_9998 -> Patchwork_19976
CI-20190529: 20190529
CI_DRM_9998: b60045f9e62eee599257a084e4481bae7fe7ef9f @
git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5754: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5754/index.html
IGT_6072: 0a51f49df9f5ca535fc0206a27a6780de6b52320 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19976: f489fdca8258c6c521baa9b671cb055515db683b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f489fdca8258 drm/i915: Remove redundant DIRTYFB frontbuffer flushes
c96da321a830 drm/i915/fbc: Don't nuke manually around flips
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19976/index.html
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/fbc: Avoid GLK+ FBC corruption
== Series Details == Series: drm/i915/fbc: Avoid GLK+ FBC corruption URL : https://patchwork.freedesktop.org/series/89379/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection
On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote: > On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Currently we try to detect a symmetric memory configurations > > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is > > either only set on a very specific subset of machines or it > > just does not exist (it's not mentioned in any public chipset > > datasheets I've found). As it happens my CL/CTG machines never > > set said bit, even if I populate the channels with identical > > sticks. > > > > So let's do the L-shaped memory detection the same way as the > > desktop variants, ie. just look at the DRAM rank boundary > > registers to see if both channels have an identical size. > > > > With this my CL/CTG no longer claim L-shaped memory when I use > > identical sticks. Also tested with non-matching sticks just to > > make sure the L-shaped memory is still properly detected. > > > > And for completeness let's update the debugfs code to dump > > the correct set of registers on each platform. > > > > Cc: Chris Wilson > > Signed-off-by: Ville Syrjälä > > Did you check this with the swapping igt? I have some vague memories of > bug reports where somehow the machine was acting like it's L-shaped memory > despite that banks were populated equally. I've iirc tried all kinds of > tricks to figure it out, all to absolutely no avail. BTW looking at the patches/dumps in eg. https://bugs.freedesktop.org/show_bug.cgi?id=28813 I can't immediately see a single thing that is actually using the correct register offsets for cl/ctg. So I'm a bit sceptical about how well this was researched in the past. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/fbc: Don't nuke manually around flips
From: Ville Syrjälä
Apparently we have discovered another way to hit the dreaded
top of screen FBC corruption on GLK. Previously we thought it
was limited to some combination of FBC nuke+disable+plane update
during the same frame, for which we have the extra vblank wait
as a workaround. But looks like it can be hit even if the plane
update happens during a different frame.
Skipping the extra manual nuke immediately after page flips seems
to cure this. The manual nuke shouldn't be needed anyway since the
flip itself will already cause a nuke. I suppose this means it might
still be possible to hit this if you mix page flips and frontbuffer
rendering in clever ways, but at least it's a bit less likely now.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 91dad8004c34..4fc3633eb614 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -232,7 +232,8 @@ static void intel_fbc_recompress(struct drm_i915_private
*dev_priv)
static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc_reg_params *params = &fbc->params;
u32 dpfc_ctl;
int threshold = dev_priv->fbc.threshold;
@@ -275,7 +276,8 @@ static void ilk_fbc_activate(struct drm_i915_private
*dev_priv)
/* enable it... */
intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
- intel_fbc_recompress(dev_priv);
+ if (!fbc->active)
+ intel_fbc_recompress(dev_priv);
}
static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
@@ -297,7 +299,8 @@ static bool ilk_fbc_is_active(struct drm_i915_private
*dev_priv)
static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc_reg_params *params = &fbc->params;
u32 dpfc_ctl;
int threshold = dev_priv->fbc.threshold;
@@ -349,7 +352,8 @@ static void gen7_fbc_activate(struct drm_i915_private
*dev_priv)
intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
- intel_fbc_recompress(dev_priv);
+ if (!fbc->active)
+ intel_fbc_recompress(dev_priv);
}
static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
@@ -368,9 +372,6 @@ static void intel_fbc_hw_activate(struct drm_i915_private
*dev_priv)
trace_intel_fbc_activate(fbc->crtc);
- fbc->active = true;
- fbc->activated = true;
-
if (DISPLAY_VER(dev_priv) >= 7)
gen7_fbc_activate(dev_priv);
else if (DISPLAY_VER(dev_priv) >= 5)
@@ -379,6 +380,9 @@ static void intel_fbc_hw_activate(struct drm_i915_private
*dev_priv)
g4x_fbc_activate(dev_priv);
else
i8xx_fbc_activate(dev_priv);
+
+ fbc->active = true;
+ fbc->activated = true;
}
static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
--
2.26.3
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[Intel-gfx] [PATCH 2/2] drm/i915: Remove redundant DIRTYFB frontbuffer flushes
From: Ville Syrjälä
The frontbuffer tracking code is supposed to handle plane
updates via ORIGIN_FLIP. Right now we're also doing internal
ORIGIN_DIRTYFB flushes for some reason. Can't see the point
so get rid of them.
In fact on GLK+ these are acively harmful and only risk angering
the hardware and causing FBC to scan out corrupted data. The
hardware flip nuke mechanism will take care of things for FBC.
With all the redundant manual nukes removed at least workloads
that don't do any frontbuffer rendering should be safe from
hitting that corruption.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a10e26380ef3..bd48272311d2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1718,8 +1718,6 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
intel_plane_copy_uapi_to_hw_state(intel_state, intel_state,
intel_crtc);
- intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
-
atomic_or(to_intel_plane(primary)->frontbuffer_bit,
&to_intel_frontbuffer(fb)->bits);
}
@@ -10633,7 +10631,6 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
return ret;
i915_gem_object_wait_priority(obj, 0, &attr);
- i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
if (!new_plane_state->uapi.fence) { /* implicit fencing */
struct dma_fence *fence;
--
2.26.3
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[Intel-gfx] [PATCH 0/2] drm/i915/fbc: Avoid GLK+ FBC corruption
From: Ville Syrjälä Remove redundant manual FBC nukes to avoid the GLK+ FBC nuke+disable+plane update fail and causing the top of the screen to become corrupted. A 100% workaround likely needs yet another vblank wait, but that's not entirely trivial to do without hurting interactivity, so for now at least try to avoid the issue for purely page flipped workloads. Test-with: 20210420104704.5018-1-ville.syrj...@linux.intel.com Ville Syrjälä (2): drm/i915/fbc: Don't nuke manually around flips drm/i915: Remove redundant DIRTYFB frontbuffer flushes drivers/gpu/drm/i915/display/intel_display.c | 3 --- drivers/gpu/drm/i915/display/intel_fbc.c | 18 +++--- 2 files changed, 11 insertions(+), 10 deletions(-) -- 2.26.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 03/20] drm/dp: Move i2c init to drm_dp_aux_init, add __must_check and fini
On Tue, 2021-04-20 at 02:16 +0300, Ville Syrjälä wrote: > > The init vs. register split is intentional. Registering the thing > and allowing userspace access to it before the rest of the driver > is ready isn't particularly great. For a while now we've tried to > move towards an architecture where the driver is fully initialzied > before anything gets exposed to userspace. Yeah-thank you for pointing this out. Thierry - do you think there's an alternate solution we could go with in Tegra to fix the get_device() issue that wouldn't require us trying to expose the i2c adapter early? > -- Cheers, Lyude Paul (she/her) Software Engineer at Red Hat ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops
== Series Details == Series: drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops URL : https://patchwork.freedesktop.org/series/89374/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h LD [M] drivers/gpu/drm/i915/i915.o HDRTEST drivers/gpu/drm/i915/display/intel_acpi.h In file included from : ./drivers/gpu/drm/i915/display/intel_acpi.h:14:34: error: ‘struct pci_dev’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] void intel_bxt_dsm_detect(struct pci_dev *pdev); ^~~ cc1: all warnings being treated as errors drivers/gpu/drm/i915/Makefile:314: recipe for target 'drivers/gpu/drm/i915/display/intel_acpi.hdrtest' failed make[4]: *** [drivers/gpu/drm/i915/display/intel_acpi.hdrtest] Error 1 scripts/Makefile.build:514: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:514: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:514: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1851: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 (rev2)
== Series Details ==
Series: drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0
(rev2)
URL : https://patchwork.freedesktop.org/series/89348/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9998 -> Patchwork_19974
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/index.html
Known issues
Here are the changes found in Patchwork_19974 that come from known issues:
### IGT changes ###
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [FAIL][1] ([i915#1888]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][3] ([i915#3303]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
[i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
Participating hosts (42 -> 40)
--
Missing(2): fi-bsw-cyan fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9998 -> Patchwork_19974
CI-20190529: 20190529
CI_DRM_9998: b60045f9e62eee599257a084e4481bae7fe7ef9f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6072: 0a51f49df9f5ca535fc0206a27a6780de6b52320 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19974: edde6f8b3cdbc4614773ea320db5d8b79cdfc86e @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
edde6f8b3cdb drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from
A0
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19974/index.html
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Re: [Intel-gfx] [PULL] drm-misc-next-fixes
On Thu, Apr 22, 2021 at 12:33 PM Maxime Ripard wrote: > > Hi Dave, Daniel, > > Here's this week drm-misc-next-fixes PR, for the next merge window > Can we also cherry-pick this patch: https://cgit.freedesktop.org/drm/drm-misc/commit/?id=d510c88cfbb294d2b1e2d0b71576e9b79d0e2e83 It should have really gone into drm-misc-next-fixes rather than drm-misc-next, but I misjudged the timing. Thanks, Alex > Thanks! > Maxime > > drm-misc-next-fixes-2021-04-22: > A few fixes for the next merge window, with some build fixes for anx7625 > and lt8912b bridges, incorrect error handling for lt8912b and TTM, and > one fix for TTM page limit accounting. > The following changes since commit 9c0fed84d5750e1eea6c664e073ffa2534a17743: > > Merge tag 'drm-intel-next-2021-04-01' of > git://anongit.freedesktop.org/drm/drm-intel into drm-next (2021-04-08 > 14:02:21 +1000) > > are available in the Git repository at: > > git://anongit.freedesktop.org/drm/drm-misc > tags/drm-misc-next-fixes-2021-04-22 > > for you to fetch changes up to a4394b6d0a273941a75ebe86a86d6416d536ed0f: > > drm/ttm: Don't count pages in SG BOs against pages_limit (2021-04-21 > 15:35:20 +0200) > > > A few fixes for the next merge window, with some build fixes for anx7625 > and lt8912b bridges, incorrect error handling for lt8912b and TTM, and > one fix for TTM page limit accounting. > > > Adrien Grassein (1): > drm/bridge: lt8912b: fix incorrect handling of of_* return values > > Christian König (1): > drm/ttm: fix return value check > > Felix Kuehling (1): > drm/ttm: Don't count pages in SG BOs against pages_limit > > Randy Dunlap (2): > drm: bridge: fix ANX7625 use of mipi_dsi_() functions > drm: bridge: fix LONTIUM use of mipi_dsi_() functions > > drivers/gpu/drm/bridge/Kconfig | 3 +++ > drivers/gpu/drm/bridge/analogix/Kconfig | 1 + > drivers/gpu/drm/bridge/lontium-lt8912b.c | 32 > +--- > drivers/gpu/drm/ttm/ttm_tt.c | 29 +++-- > 4 files changed, 40 insertions(+), 25 deletions(-) > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-misc-next-fixes
Hi Dave, Daniel, Here's this week drm-misc-next-fixes PR, for the next merge window Thanks! Maxime drm-misc-next-fixes-2021-04-22: A few fixes for the next merge window, with some build fixes for anx7625 and lt8912b bridges, incorrect error handling for lt8912b and TTM, and one fix for TTM page limit accounting. The following changes since commit 9c0fed84d5750e1eea6c664e073ffa2534a17743: Merge tag 'drm-intel-next-2021-04-01' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2021-04-08 14:02:21 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-fixes-2021-04-22 for you to fetch changes up to a4394b6d0a273941a75ebe86a86d6416d536ed0f: drm/ttm: Don't count pages in SG BOs against pages_limit (2021-04-21 15:35:20 +0200) A few fixes for the next merge window, with some build fixes for anx7625 and lt8912b bridges, incorrect error handling for lt8912b and TTM, and one fix for TTM page limit accounting. Adrien Grassein (1): drm/bridge: lt8912b: fix incorrect handling of of_* return values Christian König (1): drm/ttm: fix return value check Felix Kuehling (1): drm/ttm: Don't count pages in SG BOs against pages_limit Randy Dunlap (2): drm: bridge: fix ANX7625 use of mipi_dsi_() functions drm: bridge: fix LONTIUM use of mipi_dsi_() functions drivers/gpu/drm/bridge/Kconfig | 3 +++ drivers/gpu/drm/bridge/analogix/Kconfig | 1 + drivers/gpu/drm/bridge/lontium-lt8912b.c | 32 +--- drivers/gpu/drm/ttm/ttm_tt.c | 29 +++-- 4 files changed, 40 insertions(+), 25 deletions(-) signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 (rev2)
== Series Details == Series: drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 (rev2) URL : https://patchwork.freedesktop.org/series/89348/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops
On HP Fury G7 Workstations, graphics output is re-routed from Intel GFX
to discrete GFX after S3. This is not desirable, because userspace will
treat connected display as a new one, losing display settings.
The expected behavior is to let discrete GFX drives all external
displays.
The platform in question uses ACPI method \_SB.PCI0.HGME to enable MUX.
The method is inside the BXT _DSM, so add the _DSM and call it
accordingly.
I also tested some MUX-less and iGPU only laptops with the BXT _DSM, no
regression was found.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3113
References:
https://lore.kernel.org/intel-gfx/1460040732-31417-4-git-send-email-animesh.ma...@intel.com/
Signed-off-by: Kai-Heng Feng
---
drivers/gpu/drm/i915/display/intel_acpi.c | 17 +
drivers/gpu/drm/i915/display/intel_acpi.h | 2 ++
drivers/gpu/drm/i915/i915_drv.c | 5 +
3 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c
b/drivers/gpu/drm/i915/display/intel_acpi.c
index 833d0c1be4f1..c7b57c22dce3 100644
--- a/drivers/gpu/drm/i915/display/intel_acpi.c
+++ b/drivers/gpu/drm/i915/display/intel_acpi.c
@@ -14,11 +14,16 @@
#define INTEL_DSM_REVISION_ID 1 /* For Calpella anyway... */
#define INTEL_DSM_FN_PLATFORM_MUX_INFO 1 /* No args */
+#define INTEL_DSM_FN_PLATFORM_BXT_MUX_INFO 0 /* No args */
static const guid_t intel_dsm_guid =
GUID_INIT(0x7ed873d3, 0xc2d0, 0x4e4f,
0xa8, 0x54, 0x0f, 0x13, 0x17, 0xb0, 0x1c, 0x2c);
+static const guid_t intel_bxt_dsm_guid =
+ GUID_INIT(0x3e5b41c6, 0xeb1d, 0x4260,
+ 0x9d, 0x15, 0xc7, 0x1f, 0xba, 0xda, 0xe4, 0x14);
+
static char *intel_dsm_port_name(u8 id)
{
switch (id) {
@@ -176,6 +181,18 @@ void intel_unregister_dsm_handler(void)
{
}
+void intel_bxt_dsm_detect(struct pci_dev *pdev)
+{
+ acpi_handle dhandle;
+
+ dhandle = ACPI_HANDLE(&pdev->dev);
+ if (!dhandle)
+ return;
+
+ acpi_evaluate_dsm(dhandle, &intel_bxt_dsm_guid, INTEL_DSM_REVISION_ID,
+ INTEL_DSM_FN_PLATFORM_BXT_MUX_INFO, NULL);
+}
+
/*
* ACPI Specification, Revision 5.0, Appendix B.3.2 _DOD (Enumerate All Devices
* Attached to the Display Adapter).
diff --git a/drivers/gpu/drm/i915/display/intel_acpi.h
b/drivers/gpu/drm/i915/display/intel_acpi.h
index e8b068661d22..0dd456335bd0 100644
--- a/drivers/gpu/drm/i915/display/intel_acpi.h
+++ b/drivers/gpu/drm/i915/display/intel_acpi.h
@@ -11,10 +11,12 @@ struct drm_i915_private;
#ifdef CONFIG_ACPI
void intel_register_dsm_handler(void);
void intel_unregister_dsm_handler(void);
+void intel_bxt_dsm_detect(struct pci_dev *pdev);
void intel_acpi_device_id_update(struct drm_i915_private *i915);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
+static inline void intel_bxt_dsm_detect(struct pci_dev *pdev) { return; }
static inline
void intel_acpi_device_id_update(struct drm_i915_private *i915) { return; }
#endif /* CONFIG_ACPI */
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 785dcf20c77b..57b12068aab4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -853,6 +853,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (ret)
goto out_cleanup_gem;
+ intel_bxt_dsm_detect(pdev);
+
i915_driver_register(i915);
enable_rpm_wakeref_asserts(&i915->runtime_pm);
@@ -1215,6 +1217,7 @@ int i915_suspend_switcheroo(struct drm_i915_private
*i915, pm_message_t state)
static int i915_drm_resume(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
int ret;
disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
@@ -1271,6 +1274,8 @@ static int i915_drm_resume(struct drm_device *dev)
intel_gvt_resume(dev_priv);
+ intel_bxt_dsm_detect(pdev);
+
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
return 0;
--
2.30.2
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Re: [Intel-gfx] [PATCH] drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0
On Thu, 2021-04-22 at 07:39 -0700, Souza, Jose wrote:
> On Thu, 2021-04-22 at 12:54 +0300, Gwan-gyeong Mun wrote:
> > TGL PSR2 hardware tracking shows momentary flicker and screen shift
> > if
> > TGL Display stepping is B1 from A0.
> > It has been fixed from TGL Display stepping C0.
> >
> > HSDES: 18015970021
> > HSDES: 2209313811
> > BSpec: 55378
> >
> > Cc: José Roberto de Souza
> > Signed-off-by: Gwan-gyeong Mun
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 6 ++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 4ad756e238c5..2cc9eeab4baf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -739,6 +739,12 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> > return false;
> > }
> >
> >
> >
> >
> >
> >
> >
> >
> > + /* Wa_2209313811 */
> > + if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
>
> Missing to check if manual tracking is being used, in this case we
> can enable PSR2 in those display steppings.
Thanks for reviewing. I'll update it in V2.
>
> > + drm_dbg_kms(&dev_priv->drm, "PSR2 is not supported
> > this Display stepping\n");
> > + return false;
> > + }
> > +
> > /* Wa_16011181250 */
> > if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv)) {
> > drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for
> > this platform\n");
>
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Re: [Intel-gfx] [PATCH v2] drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0
On Thu, 2021-04-22 at 19:05 +0300, Gwan-gyeong Mun wrote:
> TGL PSR2 hardware tracking shows momentary flicker and screen shift if
> TGL Display stepping is B1 from A0.
> It has been fixed from TGL Display stepping C0.
>
> HSDES: 18015970021
> HSDES: 2209313811
> BSpec: 55378
>
> v2: Add checking of PSR2 manual tracking (Jose)
>
Reviewed-by: José Roberto de Souza
> Cc: José Roberto de Souza
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4ad756e238c5..17cbdd7805a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -817,6 +817,13 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> }
> }
>
>
>
>
> + /* Wa_2209313811 */
> + if (!crtc_state->enable_psr2_sel_fetch &&
> + IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
> + drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported
> this Display stepping\n");
> + return false;
> + }
> +
> if (!crtc_state->enable_psr2_sel_fetch &&
> (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
> drm_dbg_kms(&dev_priv->drm,
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[Intel-gfx] [PATCH v2] drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0
TGL PSR2 hardware tracking shows momentary flicker and screen shift if
TGL Display stepping is B1 from A0.
It has been fixed from TGL Display stepping C0.
HSDES: 18015970021
HSDES: 2209313811
BSpec: 55378
v2: Add checking of PSR2 manual tracking (Jose)
Cc: José Roberto de Souza
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_psr.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 4ad756e238c5..17cbdd7805a2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -817,6 +817,13 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
}
}
+ /* Wa_2209313811 */
+ if (!crtc_state->enable_psr2_sel_fetch &&
+ IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
+ drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported
this Display stepping\n");
+ return false;
+ }
+
if (!crtc_state->enable_psr2_sel_fetch &&
(crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
drm_dbg_kms(&dev_priv->drm,
--
2.30.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make preempt timeout for banned contexts configurable
== Series Details ==
Series: drm/i915: Make preempt timeout for banned contexts configurable
URL : https://patchwork.freedesktop.org/series/89369/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9998 -> Patchwork_19973
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/index.html
Known issues
Here are the changes found in Patchwork_19973 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u: [PASS][3] -> [INCOMPLETE][4] ([i915#146] / [i915#198])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][5] ([i915#1602] / [i915#2029])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/fi-bdw-5557u/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [FAIL][6] ([i915#1888]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][8] ([i915#3303]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9998/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
[i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
Participating hosts (42 -> 39)
--
Missing(3): fi-icl-y fi-bsw-cyan fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9998 -> Patchwork_19973
CI-20190529: 20190529
CI_DRM_9998: b60045f9e62eee599257a084e4481bae7fe7ef9f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6072: 0a51f49df9f5ca535fc0206a27a6780de6b52320 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19973: d5c87e77c34ab9a51ff25940e9aab9411ab8ee08 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d5c87e77c34a drm/i915: Make preempt timeout for banned contexts configurable
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19973/index.html
___
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[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel, One GVT fix and one display link training fix targeting stable 5.11. Here goes drm-intel-fixes-2021-04-22: - GVT's BDW regression fix for cmd parser (Zhenyu) - Fix modesetting in case of unexpected AUX timeouts (Imre) Thanks, Rodrigo. The following changes since commit bf05bf16c76bb44ab5156223e1e58e26dfe30a88: Linux 5.12-rc8 (2021-04-18 14:45:32 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2021-04-22 for you to fetch changes up to 2d292995bb8f49a2596bef522679c1e1454f3230: Merge tag 'gvt-fixes-2021-04-20' of https://github.com/intel/gvt-linux into drm-intel-fixes (2021-04-20 09:41:32 -0400) - GVT's BDW regression fix for cmd parser (Zhenyu) - Fix modesetting in case of unexpected AUX timeouts (Imre) Imre Deak (1): drm/i915: Fix modesetting in case of unexpected AUX timeouts Rodrigo Vivi (1): Merge tag 'gvt-fixes-2021-04-20' of https://github.com/intel/gvt-linux into drm-intel-fixes Zhenyu Wang (1): drm/i915/gvt: Fix BDW command parser regression drivers/gpu/drm/i915/display/intel_dp_link_training.c | 3 ++- drivers/gpu/drm/i915/gvt/cmd_parser.c | 19 +-- 2 files changed, 15 insertions(+), 7 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Make preempt timeout for banned contexts configurable
== Series Details == Series: drm/i915: Make preempt timeout for banned contexts configurable URL : https://patchwork.freedesktop.org/series/89369/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0
== Series Details == Series: drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 URL : https://patchwork.freedesktop.org/series/89348/ State : success == Summary == CI Bug Log - changes from CI_DRM_9997_full -> Patchwork_19972_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19972_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][1] ([i915#3354]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-snb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_create@madvise: - shard-glk: [PASS][2] -> [DMESG-WARN][3] ([i915#118] / [i915#95]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9997/shard-glk6/igt@gem_exec_cre...@madvise.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-glk9/igt@gem_exec_cre...@madvise.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: [PASS][4] -> [FAIL][5] ([i915#2846]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9997/shard-kbl1/igt@gem_exec_f...@basic-deadline.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-kbl4/igt@gem_exec_f...@basic-deadline.html - shard-glk: [PASS][6] -> [FAIL][7] ([i915#2846]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9997/shard-glk1/igt@gem_exec_f...@basic-deadline.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-glk9/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9997/shard-kbl2/igt@gem_exec_fair@basic-none-r...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-kbl7/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9997/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][12] ([i915#2389]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-apl2/igt@gem_exec_reloc@basic-wide-act...@bcs0.html * igt@gem_exec_reloc@basic-wide-active@rcs0: - shard-snb: NOTRUN -> [FAIL][13] ([i915#2389]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-snb5/igt@gem_exec_reloc@basic-wide-act...@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-apl1/igt@gem_huc_c...@huc-copy.html * igt@gem_mmap_gtt@big-copy-odd: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#307]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9997/shard-skl7/igt@gem_mmap_...@big-copy-odd.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-skl2/igt@gem_mmap_...@big-copy-odd.html * igt@gem_pwrite@basic-exhaustion: - shard-iclb: NOTRUN -> [WARN][17] ([i915#2658]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-iclb4/igt@gem_pwr...@basic-exhaustion.html * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#768]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-iclb4/igt@gem_render_c...@y-tiled-mc-ccs-to-vebox-yf-tiled.html * igt@gem_userptr_blits@dmabuf-sync: - shard-iclb: NOTRUN -> [SKIP][19] ([i915#3323]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-iclb4/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@set-cache-level: - shard-snb: NOTRUN -> [FAIL][20] ([i915#3324]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-snb2/igt@gem_userptr_bl...@set-cache-level.html * igt@gem_userptr_blits@vma-merge: - shard-apl: NOTRUN -> [FAIL][21] ([i915#3318]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-apl2/igt@gem_userptr_bl...@vma-merge.html * igt@gen7_exec_parse@basic-offset: - shard-apl: NOTRUN -> [SKIP][22] ([fdo#109271]) +216 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-apl1/igt@gen7_exec_pa...@basic-offset.html * igt@gen9_exec_parse@bb-large: - shard-apl: NOTRUN -> [FAIL][23] ([i915#3296]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/shard-apl2/igt@gen9_exec_pa...@bb-lar
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make preempt timeout for banned contexts configurable
== Series Details == Series: drm/i915: Make preempt timeout for banned contexts configurable URL : https://patchwork.freedesktop.org/series/89369/ State : warning == Summary == $ dim checkpatch origin/drm-tip d5c87e77c34a drm/i915: Make preempt timeout for banned contexts configurable -:130: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #130: FILE: drivers/gpu/drm/i915/gt/sysfs_engines.c:436: +banned_context_timeout_show(struct kobject *kobj, struct kobj_attribute *attr, +char *buf) -:139: WARNING:LEADING_SPACE: please, no spaces at the start of a line #139: FILE: drivers/gpu/drm/i915/gt/sysfs_engines.c:445: + banned_context_timeout_store);$ total: 0 errors, 1 warnings, 1 checks, 118 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Make preempt timeout for banned contexts configurable
From: Tvrtko Ursulin
When we ban a context, for instance when userspace marked itself as non-
persistent and has exited, we apply a 1ms grace period after which any
belonging workload still on the GPU (did not preempt) will be forcibly
terminated (using engine reset).
For some workloads period between preemptible points can be longer than
this default which results in preempt timeout reset messages, even though
the process would actually gracefully exit if given enough time.
Coupled with the fact that error messages during normal operation, even if
harmless, can be frowned upon, we are left with two options. We could
either increase the timeout for everyone, or we could allow it to be
configured.
Given how rapid response to banned contexts (which can be for many reasons
including deliberate denial of service attempts) is preferrable this patch
opts for the latter.
The default timeout is left at 1ms but can now be configured either at
kernel build time via CONFIG_DRM_I915_BANNED_CONTEXT_TIMEOUT, or at
runtime using engine sysfs controls, with the added one being named
banned_context_timeout_ms.
Signed-off-by: Tvrtko Ursulin
Cc: Zhen Han
---
drivers/gpu/drm/i915/Kconfig.profile | 13 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
.../drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/sysfs_engines.c | 54 +++
5 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 39328567c200..0be56c7084ff 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -119,3 +119,16 @@ config DRM_I915_TIMESLICE_DURATION
/sys/class/drm/card?/engine/*/timeslice_duration_ms
May be 0 to disable timeslicing.
+
+config DRM_I915_BANNED_CONTEXT_TIMEOUT
+ int "Banned context timeout (ms)"
+ default 1 # milliseconds
+ help
+ How long to wait (in milliseconds) for a banned context to cleanly
+ terminate their workloads. If the context does not yield inside the
+ configured time it will be forcibly reset.
+
+ This is adjustable via
+ /sys/class/drm/card?/engine/*/banned_context_timeout_ms
+
+ If configured to zero a 1ms minimum will still apply.
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 6dbdbde00f14..80b973367db8 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -306,6 +306,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
CONFIG_DRM_I915_STOP_TIMEOUT;
engine->props.timeslice_duration_ms =
CONFIG_DRM_I915_TIMESLICE_DURATION;
+ engine->props.banned_context_timeout_ms =
+ min(1, CONFIG_DRM_I915_BANNED_CONTEXT_TIMEOUT);
/* Override to uninterruptible for OpenCL workloads. */
if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS)
@@ -1623,6 +1625,7 @@ static void print_properties(struct intel_engine_cs
*engine,
P(preempt_timeout_ms),
P(stop_timeout_ms),
P(timeslice_duration_ms),
+ P(banned_context_timeout_ms),
{},
#undef P
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 883bafc44902..ec4f16b0308a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -549,6 +549,7 @@ struct intel_engine_cs {
unsigned long preempt_timeout_ms;
unsigned long stop_timeout_ms;
unsigned long timeslice_duration_ms;
+ unsigned long banned_context_timeout_ms;
} props, defaults;
I915_SELFTEST_DECLARE(struct fault_attr reset_timeout);
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index de124870af44..e2c4e4230979 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1209,7 +1209,7 @@ static unsigned long active_preempt_timeout(struct
intel_engine_cs *engine,
/* Force a fast reset for terminated contexts (ignoring sysfs!) */
if (unlikely(intel_context_is_banned(rq->context) || bad_request(rq)))
- return 1;
+ return engine->props.banned_context_timeout_ms;
return READ_ONCE(engine->props.preempt_timeout_ms);
}
diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c
b/drivers/gpu/drm/i915/gt/sysfs_engines.c
index 967031056202..cce9ab8a3309 100644
--- a/drivers/gpu/drm/i915/gt/sysfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c
@@ -411,6 +411,52 @@ heartbeat_default(struct kobject *kobj, struct
kobj_attribute *att
Re: [Intel-gfx] [PATCH] vfio/gvt: fix DRM_I915_GVT dependency on VFIO_MDEV
Cc: gvt list & maintainers
On Thu, 22 Apr 2021, Jason Gunthorpe wrote:
> On Thu, Apr 22, 2021 at 03:35:33PM +0200, Arnd Bergmann wrote:
>> From: Arnd Bergmann
>>
>> The Kconfig dependency is incomplete since DRM_I915_GVT is a 'bool'
>> symbol that depends on the 'tristate' VFIO_MDEV. This allows a
>> configuration with VFIO_MDEV=m, DRM_I915_GVT=y and DRM_I915=y that
>> causes a link failure:
>>
>> x86_64-linux-ld: drivers/gpu/drm/i915/gvt/gvt.o: in function
>> `available_instances_show':
>> gvt.c:(.text+0x67a): undefined reference to `mtype_get_parent_dev'
>> x86_64-linux-ld: gvt.c:(.text+0x6a5): undefined reference to
>> `mtype_get_type_group_id'
>> x86_64-linux-ld: drivers/gpu/drm/i915/gvt/gvt.o: in function
>> `description_show':
>> gvt.c:(.text+0x76e): undefined reference to `mtype_get_parent_dev'
>> x86_64-linux-ld: gvt.c:(.text+0x799): undefined reference to
>> `mtype_get_type_group_id'
>>
>> Clarify the dependency by specifically disallowing the broken
>> configuration. If VFIO_MDEV is built-in, it will work, but if
>> VFIO_MDEV=m, the i915 driver cannot be built-in here.
>>
>> Fixes: 07e543f4f9d1 ("vfio/gvt: Make DRM_I915_GVT depend on VFIO_MDEV")
>> Fixes: 9169cff168ff ("vfio/mdev: Correct the function signatures for the
>> mdev_type_attributes")
>> Signed-off-by: Arnd Bergmann
>> ---
>> drivers/gpu/drm/i915/Kconfig | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Oh kconfig stuff like this makes my head hurt, thanks for finding it
>
> I also can't see an alternative to this ugly thing, besides having the
> i915 guys properly modularize this code someday
>
> Reviewed-by: Jason Gunthorpe
>
> Jason
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH v2] drm/i915: Simplify CCS and UV plane alignment handling
look ok to me.
Reviewed-by: Juha-Pekka Heikkila
On 21.4.2021 20.32, Imre Deak wrote:
We can handle the surface alignment of CCS and UV color planes for all
modifiers at one place, so do this. An AUX color plane can be a CCS or a
UV plane, use only the more specific query functions and remove
is_aux_plane() becoming redundant.
While at it add a TODO for linear UV color plane alignments. The spec
requires this to be stride-in-bytes * 64 on all platforms, whereas the
driver uses an alignment of 4k for gen<12 and 256k for gen>=12 for
linear UV planes.
v2:
- Restore previous alignment for linear UV surfaces.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 27 +---
drivers/gpu/drm/i915/display/intel_fb.c | 8 --
drivers/gpu/drm/i915/display/intel_fb.h | 1 -
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a10e26380ef3d..e246e5cf75866 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -973,10 +973,26 @@ unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
struct drm_i915_private *dev_priv = to_i915(fb->dev);
/* AUX_DIST needs only 4K alignment */
- if ((DISPLAY_VER(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
- is_ccs_plane(fb, color_plane))
+ if (is_ccs_plane(fb, color_plane))
return 4096;
+ if (is_semiplanar_uv_plane(fb, color_plane)) {
+ /*
+* TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
+* alignment for linear UV planes on all platforms.
+*/
+ if (DISPLAY_VER(dev_priv) >= 12) {
+ if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
+ return intel_linear_alignment(dev_priv);
+
+ return intel_tile_row_size(fb, color_plane);
+ }
+
+ return 4096;
+ }
+
+ drm_WARN_ON(&dev_priv->drm, color_plane != 0);
+
switch (fb->modifier) {
case DRM_FORMAT_MOD_LINEAR:
return intel_linear_alignment(dev_priv);
@@ -985,19 +1001,12 @@ unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- if (is_semiplanar_uv_plane(fb, color_plane))
- return intel_tile_row_size(fb, color_plane);
- fallthrough;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
- if (DISPLAY_VER(dev_priv) >= 12 &&
- is_semiplanar_uv_plane(fb, color_plane))
- return intel_tile_row_size(fb, color_plane);
- fallthrough;
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
default:
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 0ec9ad7220a14..c8aaca3e79e97 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -30,14 +30,6 @@ bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb,
int plane)
plane == 2;
}
-bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
-{
- if (is_ccs_modifier(fb->modifier))
- return is_ccs_plane(fb, plane);
-
- return plane == 1;
-}
-
bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
{
return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index 6acf792a8c44a..13244ec1ad214 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -19,7 +19,6 @@ struct intel_plane_state;
bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
-bool is_aux_plane(const struct drm_framebuffer *fb, int plane);
bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int
color_plane);
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane);
___
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Re: [Intel-gfx] [PATCH] drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0
On Thu, 2021-04-22 at 12:54 +0300, Gwan-gyeong Mun wrote:
> TGL PSR2 hardware tracking shows momentary flicker and screen shift if
> TGL Display stepping is B1 from A0.
> It has been fixed from TGL Display stepping C0.
>
> HSDES: 18015970021
> HSDES: 2209313811
> BSpec: 55378
>
> Cc: José Roberto de Souza
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4ad756e238c5..2cc9eeab4baf 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -739,6 +739,12 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> return false;
> }
>
>
>
>
>
>
>
>
> + /* Wa_2209313811 */
> + if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
Missing to check if manual tracking is being used, in this case we can enable
PSR2 in those display steppings.
> + drm_dbg_kms(&dev_priv->drm, "PSR2 is not supported this Display
> stepping\n");
> + return false;
> + }
> +
> /* Wa_16011181250 */
> if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv)) {
> drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this
> platform\n");
___
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection
On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
> On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Currently we try to detect a symmetric memory configurations
> > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
> > either only set on a very specific subset of machines or it
> > just does not exist (it's not mentioned in any public chipset
> > datasheets I've found). As it happens my CL/CTG machines never
> > set said bit, even if I populate the channels with identical
> > sticks.
> >
> > So let's do the L-shaped memory detection the same way as the
> > desktop variants, ie. just look at the DRAM rank boundary
> > registers to see if both channels have an identical size.
> >
> > With this my CL/CTG no longer claim L-shaped memory when I use
> > identical sticks. Also tested with non-matching sticks just to
> > make sure the L-shaped memory is still properly detected.
> >
> > And for completeness let's update the debugfs code to dump
> > the correct set of registers on each platform.
> >
> > Cc: Chris Wilson
> > Signed-off-by: Ville Syrjälä
>
> Did you check this with the swapping igt? I have some vague memories of
> bug reports where somehow the machine was acting like it's L-shaped memory
> despite that banks were populated equally. I've iirc tried all kinds of
> tricks to figure it out, all to absolutely no avail.
Did you have a specific test in mind? I ran a bunch of things
that seemed swizzle related. All passed just fine.
Chris did have similar concerns and suggested we should have
better tests. I guess what I should try to do is some selftests
which make sure we test both high and low physical addresses
and check the swizzle pattern is as expected. But haven't
found the time to do that yet.
>
> tbh I'd just not touch this, not really worth it.
It's totally worth it to get gen4 machines working again.
> -Daniel
> > ---
> > drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 16
> > drivers/gpu/drm/i915/i915_reg.h | 4
> > 3 files changed, 24 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > index 0fa6c38893f7..754f20768de5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > @@ -693,14 +693,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt
> > *ggtt)
> > swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
> > swizzle_y = I915_BIT_6_SWIZZLE_9_17;
> > }
> > - break;
> > - }
> >
> > - /* check for L-shaped memory aka modified enhanced addressing */
> > - if (IS_GEN(i915, 4) &&
> > - !(intel_uncore_read(uncore, DCC2) &
> > DCC2_MODIFIED_ENHANCED_DISABLE)) {
> > - swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> > - swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> > + /* check for L-shaped memory aka modified enhanced
> > addressing */
> > + if (IS_GEN(i915, 4) &&
> > + intel_uncore_read16(uncore, C0DRB3_CL) !=
> > + intel_uncore_read16(uncore, C1DRB3_CL)) {
> > + swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> > + swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> > + }
> > + break;
> > }
> >
> > if (dcc == 0x) {
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 8dd374691102..6de11ffcde38 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -621,10 +621,18 @@ static int i915_swizzle_info(struct seq_file *m, void
> > *data)
> >intel_uncore_read(uncore, DCC));
> > seq_printf(m, "DDC2 = 0x%08x\n",
> >intel_uncore_read(uncore, DCC2));
> > - seq_printf(m, "C0DRB3 = 0x%04x\n",
> > - intel_uncore_read16(uncore, C0DRB3_BW));
> > - seq_printf(m, "C1DRB3 = 0x%04x\n",
> > - intel_uncore_read16(uncore, C1DRB3_BW));
> > +
> > + if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv))
> > {
> > + seq_printf(m, "C0DRB3 = 0x%04x\n",
> > + intel_uncore_read16(uncore, C0DRB3_BW));
> > + seq_printf(m, "C1DRB3 = 0x%04x\n",
> > + intel_uncore_read16(uncore, C1DRB3_BW));
> > + } else if (IS_GEN(dev_priv, 4)) {
> > + seq_printf(m, "C0DRB3 = 0x%04x\n",
> > + intel_uncore_read16(uncore, C0DRB3_CL));
> > + seq_printf(m,
Re: [Intel-gfx] [PATCH v3 01/20] drm/amdgpu: Add error handling to amdgpu_dm_initialize_dp_connector()
Thanks for the change!
Reviewed-by: Mikita Lipski
On 2021-04-19 6:55 p.m., Lyude Paul wrote:
While working on moving i2c device registration into drm_dp_aux_init() - I
realized that in order to do so we need to make sure that drivers calling
drm_dp_aux_init() handle any errors it could possibly return. In the
process of doing that, I noticed that the majority of AMD's code for DP
connector creation doesn't attempt to do any real error handling.
So, let's fix this and also cleanup amdgpu_dm_initialize_dp_connector()
while we're at it. This way we can handle the error codes from
drm_dp_aux_init().
Signed-off-by: Lyude Paul
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29 +++-
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 44 +++
.../display/amdgpu_dm/amdgpu_dm_mst_types.h | 6 +--
3 files changed, 45 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a0c8c41e4e57..fc5d315bbb05 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7608,10 +7608,9 @@ static int amdgpu_dm_connector_init(struct
amdgpu_display_manager *dm,
aconnector->i2c = i2c;
res = i2c_add_adapter(&i2c->base);
-
if (res) {
DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
- goto out_free;
+ goto fail_free;
}
connector_type = to_drm_connector_type(link->connector_signal);
@@ -7625,8 +7624,7 @@ static int amdgpu_dm_connector_init(struct
amdgpu_display_manager *dm,
if (res) {
DRM_ERROR("connector_init failed\n");
- aconnector->connector_id = -1;
- goto out_free;
+ goto fail_id;
}
drm_connector_helper_add(
@@ -7643,15 +7641,22 @@ static int amdgpu_dm_connector_init(struct
amdgpu_display_manager *dm,
drm_connector_attach_encoder(
&aconnector->base, &aencoder->base);
- if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
- || connector_type == DRM_MODE_CONNECTOR_eDP)
- amdgpu_dm_initialize_dp_connector(dm, aconnector,
link->link_index);
-
-out_free:
- if (res) {
- kfree(i2c);
- aconnector->i2c = NULL;
+ if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
+ connector_type == DRM_MODE_CONNECTOR_eDP) {
+ res = amdgpu_dm_initialize_dp_connector(dm, aconnector,
link->link_index);
+ if (res)
+ goto fail_cleanup;
}
+
+ return 0;
+fail_cleanup:
+ drm_connector_cleanup(&aconnector->base);
+fail_id:
+ aconnector->connector_id = -1;
+fail_free:
+ kfree(i2c);
+ aconnector->i2c = NULL;
+
return res;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 73cdb9fe981a..3dee9cce9c9e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -425,33 +425,39 @@ static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
.add_connector = dm_dp_add_mst_connector,
};
-void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
- struct amdgpu_dm_connector *aconnector,
- int link_index)
+int amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
+ struct amdgpu_dm_connector *aconnector,
+ int link_index)
{
- aconnector->dm_dp_aux.aux.name =
- kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
- link_index);
- aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
- aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
+ struct amdgpu_dm_dp_aux *dm_aux = &aconnector->dm_dp_aux;
+ int ret;
- drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
- drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
- &aconnector->base);
+ dm_aux->aux.name = kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
link_index);
+ if (!dm_aux->aux.name)
+ return -ENOMEM;
+
+ dm_aux->aux.transfer = dm_dp_aux_transfer;
+ dm_aux->ddc_service = aconnector->dc_link->ddc;
+
+ drm_dp_aux_init(&dm_aux->aux);
+ drm_dp_cec_register_connector(&dm_aux->aux, &aconnector->base);
if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
- return;
+ return 0;
aconnector->mst_mgr.cbs = &dm_mst_cbs;
- drm_dp_mst_topology_mgr_init(
- &aconnector->mst_mgr,
- adev_to_drm(dm->adev),
- &aconnector->dm_dp_aux.a
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0
== Series Details ==
Series: drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0
URL : https://patchwork.freedesktop.org/series/89348/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9997 -> Patchwork_19972
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/index.html
Known issues
Here are the changes found in Patchwork_19972 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][2] -> [INCOMPLETE][3] ([i915#2782] /
[i915#2940])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9997/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][4] ([i915#1436])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/fi-bsw-nick/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][5] ([i915#2782] / [i915#2940]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9997/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][7] ([i915#3303]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9997/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
Participating hosts (42 -> 39)
--
Missing(3): fi-rkl-11500t fi-bsw-cyan fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9997 -> Patchwork_19972
CI-20190529: 20190529
CI_DRM_9997: a16224638a4d831ce3614cf10a0711ba34895265 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6072: 0a51f49df9f5ca535fc0206a27a6780de6b52320 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19972: 17a80ce652ed837723ffa33f3ac030154634a77a @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
17a80ce652ed drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from
A0
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19972/index.html
___
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/display/xelpd: Do not program EDP_Y_COORDINATE_ENABLE
Looks good to me.
Reviewed-by: Gwan-gyeong Mun
On Wed, 2021-04-21 at 15:02 -0700, José Roberto de Souza wrote:
> EDP_Y_COORDINATE_ENABLE became a reserved register in display 13.
> EDP_Y_COORDINATE_VALID have the same fate as EDP_Y_COORDINATE_ENABLE
> but as we don't need it, removing the macro definition of it.
>
> BSpec: 50422
> Cc: Gwan-gyeong Mun
> Cc: Anusha Srivatsa
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 3 +--
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4ad756e238c5..66335ec6b7d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -524,7 +524,7 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
> val = psr_compute_idle_frames(intel_dp) <<
> EDP_PSR2_IDLE_FRAME_SHIFT;
>
> val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> - if (DISPLAY_VER(dev_priv) >= 10)
> + if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
> val |= EDP_Y_COORDINATE_ENABLE;
>
> val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency
> + 1);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 66a902b3bb8e..e18576c94cef 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4569,8 +4569,7 @@ enum {
> #define EDP_SU_TRACK_ENABLE (1 << 30)
> #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
> #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
> -#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and
> CNL+ */
> -#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and
> CNL+ */
> +#define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display
> 10, 11 and 12 */
> #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
> #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
> #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES8
___
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Re: [Intel-gfx] [PATCH 1/2] drm: Rename DP_PSR_SELECTIVE_UPDATE to better mach eDP spec
The changed name looks more accurate to the edp 1.4b spec. Looks good to me. Reviewed-by: Gwan-gyeong Mun On Wed, 2021-04-21 at 15:02 -0700, José Roberto de Souza wrote: > DP_PSR_EN_CFG bit 5 aka "Selective Update Region Scan Line Capture > Indication" in eDP spec has a ambiguous name, so renaming to better > match specification. > > While at it, replacing bit shit by BIT() macro and adding the version > some registers were added to eDP specification. > > Cc: > Cc: Rodrigo Vivi > Cc: Jani Nikula > Cc: Gwan-gyeong Mun > Signed-off-by: José Roberto de Souza > --- > include/drm/drm_dp_helper.h | 16 > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 1e85c2021f2f..d6f6a084a190 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -687,14 +687,14 @@ struct drm_device; > #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ > # define DP_DECOMPRESSION_EN (1 << 0) > > -#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ > -# define DP_PSR_ENABLE (1 << 0) > -# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) > -# define DP_PSR_CRC_VERIFICATION (1 << 2) > -# define DP_PSR_FRAME_CAPTURE (1 << 3) > -# define DP_PSR_SELECTIVE_UPDATE (1 << 4) > -# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) > -# define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */ > +#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ > +# define DP_PSR_ENABLE BIT(0) > +# define DP_PSR_MAIN_LINK_ACTIVE BIT(1) > +# define DP_PSR_CRC_VERIFICATION BIT(2) > +# define DP_PSR_FRAME_CAPTURE BIT(3) > +# define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */ > +# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORSBIT(5) /* eDP > 1.4a */ > +# define DP_PSR_ENABLE_PSR2BIT(6) /* eDP 1.4a */ > > #define DP_ADAPTER_CTRL 0x1a0 > # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0
== Series Details == Series: drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 URL : https://patchwork.freedesktop.org/series/89348/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Fix state mismatch in drm infoframe (rev2)
== Series Details ==
Series: drm/i915/display: Fix state mismatch in drm infoframe (rev2)
URL : https://patchwork.freedesktop.org/series/89225/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9997 -> Patchwork_19971
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19971 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19971, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19971/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19971:
### CI changes ###
Possible regressions
* boot:
- fi-hsw-4770:[PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9997/fi-hsw-4770/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19971/fi-hsw-4770/boot.html
Known issues
Here are the changes found in Patchwork_19971 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19971/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][4] ([i915#1602] / [i915#2029])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19971/fi-bdw-5557u/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][5] ([i915#2782] / [i915#2940]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9997/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19971/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][7] ([i915#3303]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9997/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19971/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3180]: https://gitlab.freedesktop.org/drm/intel/issues/3180
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
Participating hosts (42 -> 40)
--
Missing(2): fi-bsw-cyan fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9997 -> Patchwork_19971
CI-20190529: 20190529
CI_DRM_9997: a16224638a4d831ce3614cf10a0711ba34895265 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6072: 0a51f49df9f5ca535fc0206a27a6780de6b52320 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19971: fa9c189f7c4a50d91f70f95dda916fe4b7448442 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fa9c189f7c4a drm/i915/display: Fix state mismatch in drm infoframe
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19971/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0
TGL PSR2 hardware tracking shows momentary flicker and screen shift if
TGL Display stepping is B1 from A0.
It has been fixed from TGL Display stepping C0.
HSDES: 18015970021
HSDES: 2209313811
BSpec: 55378
Cc: José Roberto de Souza
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 4ad756e238c5..2cc9eeab4baf 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -739,6 +739,12 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
return false;
}
+ /* Wa_2209313811 */
+ if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
+ drm_dbg_kms(&dev_priv->drm, "PSR2 is not supported this Display
stepping\n");
+ return false;
+ }
+
/* Wa_16011181250 */
if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv)) {
drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this
platform\n");
--
2.30.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection
On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we try to detect a symmetric memory configurations
> using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
> either only set on a very specific subset of machines or it
> just does not exist (it's not mentioned in any public chipset
> datasheets I've found). As it happens my CL/CTG machines never
> set said bit, even if I populate the channels with identical
> sticks.
>
> So let's do the L-shaped memory detection the same way as the
> desktop variants, ie. just look at the DRAM rank boundary
> registers to see if both channels have an identical size.
>
> With this my CL/CTG no longer claim L-shaped memory when I use
> identical sticks. Also tested with non-matching sticks just to
> make sure the L-shaped memory is still properly detected.
>
> And for completeness let's update the debugfs code to dump
> the correct set of registers on each platform.
>
> Cc: Chris Wilson
> Signed-off-by: Ville Syrjälä
Did you check this with the swapping igt? I have some vague memories of
bug reports where somehow the machine was acting like it's L-shaped memory
despite that banks were populated equally. I've iirc tried all kinds of
tricks to figure it out, all to absolutely no avail.
tbh I'd just not touch this, not really worth it.
-Daniel
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ---
> drivers/gpu/drm/i915/i915_debugfs.c | 16
> drivers/gpu/drm/i915/i915_reg.h | 4
> 3 files changed, 24 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> index 0fa6c38893f7..754f20768de5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> @@ -693,14 +693,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
> swizzle_y = I915_BIT_6_SWIZZLE_9_17;
> }
> - break;
> - }
>
> - /* check for L-shaped memory aka modified enhanced addressing */
> - if (IS_GEN(i915, 4) &&
> - !(intel_uncore_read(uncore, DCC2) &
> DCC2_MODIFIED_ENHANCED_DISABLE)) {
> - swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> - swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> + /* check for L-shaped memory aka modified enhanced
> addressing */
> + if (IS_GEN(i915, 4) &&
> + intel_uncore_read16(uncore, C0DRB3_CL) !=
> + intel_uncore_read16(uncore, C1DRB3_CL)) {
> + swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> + swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> + }
> + break;
> }
>
> if (dcc == 0x) {
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 8dd374691102..6de11ffcde38 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -621,10 +621,18 @@ static int i915_swizzle_info(struct seq_file *m, void
> *data)
> intel_uncore_read(uncore, DCC));
> seq_printf(m, "DDC2 = 0x%08x\n",
> intel_uncore_read(uncore, DCC2));
> - seq_printf(m, "C0DRB3 = 0x%04x\n",
> -intel_uncore_read16(uncore, C0DRB3_BW));
> - seq_printf(m, "C1DRB3 = 0x%04x\n",
> -intel_uncore_read16(uncore, C1DRB3_BW));
> +
> + if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv))
> {
> + seq_printf(m, "C0DRB3 = 0x%04x\n",
> +intel_uncore_read16(uncore, C0DRB3_BW));
> + seq_printf(m, "C1DRB3 = 0x%04x\n",
> +intel_uncore_read16(uncore, C1DRB3_BW));
> + } else if (IS_GEN(dev_priv, 4)) {
> + seq_printf(m, "C0DRB3 = 0x%04x\n",
> +intel_uncore_read16(uncore, C0DRB3_CL));
> + seq_printf(m, "C1DRB3 = 0x%04x\n",
> +intel_uncore_read16(uncore, C1DRB3_CL));
> + }
> } else if (INTEL_GEN(dev_priv) >= 6) {
> seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
> intel_uncore_read(uncore, MAD_DIMM_C0));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0587b2455ea1..055c258179a1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3790,6 +3790,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define C0DRB3_BW_MMIO(MCHBAR_MIRROR_BASE + 0x206)
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/display: Fix state mismatch in drm infoframe (rev2)
== Series Details == Series: drm/i915/display: Fix state mismatch in drm infoframe (rev2) URL : https://patchwork.freedesktop.org/series/89225/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Restricted DMA
== Series Details == Series: Restricted DMA URL : https://patchwork.freedesktop.org/series/89341/ State : failure == Summary == Applying: swiotlb: Fix the type of index error: sha1 information is lacking or useless (kernel/dma/swiotlb.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 swiotlb: Fix the type of index When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm: Rename DP_PSR_SELECTIVE_UPDATE to better mach eDP spec
== Series Details == Series: series starting with [1/2] drm: Rename DP_PSR_SELECTIVE_UPDATE to better mach eDP spec URL : https://patchwork.freedesktop.org/series/89328/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9995_full -> Patchwork_19969_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19969_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19969_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19969_full: ### IGT changes ### Possible regressions * igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9995/shard-skl4/igt@kms_cursor_leg...@short-flip-before-cursor-atomic-transitions.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19969/shard-skl6/igt@kms_cursor_leg...@short-flip-before-cursor-atomic-transitions.html Known issues Here are the changes found in Patchwork_19969_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@process: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19969/shard-snb2/igt@gem_ctx_persiste...@process.html * igt@gem_eio@in-flight-1us: - shard-skl: [PASS][4] -> [TIMEOUT][5] ([i915#3063]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9995/shard-skl8/igt@gem_...@in-flight-1us.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19969/shard-skl1/igt@gem_...@in-flight-1us.html * igt@gem_eio@unwedge-stress: - shard-iclb: [PASS][6] -> [TIMEOUT][7] ([i915#2369] / [i915#2481] / [i915#3070]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9995/shard-iclb3/igt@gem_...@unwedge-stress.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19969/shard-iclb3/igt@gem_...@unwedge-stress.html - shard-snb: NOTRUN -> [FAIL][8] ([i915#3354]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19969/shard-snb6/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9995/shard-iclb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19969/shard-iclb4/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9995/shard-tglb3/igt@gem_exec_fair@basic-p...@vecs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19969/shard-tglb1/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2849]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9995/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19969/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][15] ([i915#2389]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19969/shard-apl8/igt@gem_exec_reloc@basic-wide-act...@bcs0.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][16] ([i915#2389]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19969/shard-iclb1/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19969/shard-apl3/igt@gem_huc_c...@huc-copy.html * igt@gem_userptr_blits@set-cache-level: - shard-snb: NOTRUN -> [FAIL][18] ([i915#3324]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19969/shard-snb5/igt@gem_userptr_bl...@set-cache-level.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][19] ([i915#2724]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19969/shard-snb7/igt@gem_userptr_bl...@vma-merge.html - shard-skl: NOTRUN -> [FAIL][20] ([i915#3318]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19969/shard-skl8/igt@gem_userptr_bl...@vma-merge.html * igt@gem_vm_create@destroy-race: - shard-tglb: [PASS][21] -> [TIMEOUT][22] ([i915#2795]) [21]: http
[Intel-gfx] [V2] drm/i915/display: Fix state mismatch in drm infoframe
While reading the SDP infoframe, we are getting filtered with
the encoder type INTEL_OUTPUT_DDI which causes the infoframe
mismatch. This patch will drop encoder->type check as we can
mask individual infoframe type.
[1025.606556] i915 :00:02.0: [drm] *ERROR* mismatch in drm infoframe
[1025.607865] i915 :00:02.0: [drm] *ERROR* expected:
[1025.607879] i915 :00:02.0: HDMI infoframe: Dynamic Range and Mastering,
version 1, length 26
[1025.607889] i915 :00:02.0: length: 26
[1025.607898] i915 :00:02.0: metadata type: 0
[1025.608292] i915 :00:02.0: eotf: 2
[1025.608302] i915 :00:02.0: x[0]: 35400
[1025.608312] i915 :00:02.0: y[0]: 14599
[1025.609115] i915 :00:02.0: x[1]: 8500
[1025.609947] i915 :00:02.0: y[1]: 39850
[1025.609959] i915 :00:02.0: x[2]: 6550
[1025.609970] i915 :00:02.0: y[2]: 2300
[1025.609980] i915 :00:02.0: white point x: 15634
[1025.609989] i915 :00:02.0: white point y: 16450
[1025.610381] i915 :00:02.0: max_display_mastering_luminance: 1000
[1025.610392] i915 :00:02.0: min_display_mastering_luminance: 500
[1025.610401] i915 :00:02.0: max_cll: 500
[1025.610816] i915 :00:02.0: max_fall: 1000
[1025.612457] i915 :00:02.0: [drm] *ERROR* found:
[1025.614354] [ cut here ]
[1025.616244] pipe state doesn't match!
[1025.617640] WARNING: CPU: 6 PID: 2114 at
drivers/gpu/drm/i915/display/intel_display.c:9332
intel_atomic_commit_tail+0x14d4/0x17c0 [i915]
V2:
* Drop encoder->type check
Cc: Uma Shankar
Cc: Ville Syrjälä
Signed-off-by: Bhanuprakash Modem
Reviewed-by: Uma Shankar (V1)
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4ad12dde5938..280b0b5ee70e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3014,9 +3014,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
unsigned int type)
{
- if (encoder->type != INTEL_OUTPUT_DDI)
- return;
-
switch (type) {
case DP_SDP_VSC:
intel_read_dp_vsc_sdp(encoder, crtc_state,
--
2.20.1
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Re: [Intel-gfx] [PATCH v2 0/9] drm: Add privacy-screen class and connector properties
On Thursday, April 22nd, 2021 at 10:54 AM, Hans de Goede wrote: > I guess Marco was waiting for the kernel bits too land before submitting > these, > but I agree that it would probably be good to have these submitted now, we > can mark them as WIP to avoid them getting merged before the kernel side > is finalized. Yes, this is how it should be done, see [1]. In particular: > The userspace side must be fully reviewed and tested to the standards > of that userspace project. And yeah, the user-space side still can't be merged before the kernel side: > The kernel patch can only be merged after all the above requirements > are met, but it must be merged to either drm-next or drm-misc-next > before the userspace patches land. [1]: https://dri.freedesktop.org/docs/drm/gpu/drm-uapi.html#open-source-userspace-requirements ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 0/9] drm: Add privacy-screen class and connector properties
Hi, On 4/22/21 10:51 AM, Simon Ser wrote: > Hi, > > On Wednesday, April 21st, 2021 at 10:47 PM, Hans de Goede > wrote: > >> There now is GNOME userspace code using the new properties: >> https://hackmd.io/@3v1n0/rkyIy3BOw > > Thanks for working on this. > > Can these patches be submitted as merge requests against the upstream > projects? It would be nice to get some feedback from the maintainers, > and be able to easily leave some comments there as well. I guess Marco was waiting for the kernel bits too land before submitting these, but I agree that it would probably be good to have these submitted now, we can mark them as WIP to avoid them getting merged before the kernel side is finalized. Marco, can you take care of submitting WIP merge-reqs for these? Regards, Hans ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 0/9] drm: Add privacy-screen class and connector properties
Hi, On Wednesday, April 21st, 2021 at 10:47 PM, Hans de Goede wrote: > There now is GNOME userspace code using the new properties: > https://hackmd.io/@3v1n0/rkyIy3BOw Thanks for working on this. Can these patches be submitted as merge requests against the upstream projects? It would be nice to get some feedback from the maintainers, and be able to easily leave some comments there as well. Thanks, Simon ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix docbook descriptions for i915_cmd_parser
On Wed, Apr 21, 2021 at 04:39:10PM +0200, Maarten Lankhorst wrote:
> Op 21-04-2021 om 16:32 schreef Daniel Vetter:
> > On Wed, Apr 21, 2021 at 2:03 PM Maarten Lankhorst
> > wrote:
> >> Fixes the following htmldocs warnings:
> >> drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function
> >> parameter 'trampoline' description in 'intel_engine_cmd_parser'
> >> drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter
> >> or member 'jump_whitelist' not described in 'intel_engine_cmd_parser'
> >> drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter
> >> or member 'shadow_map' not described in 'intel_engine_cmd_parser'
> >> drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter
> >> or member 'batch_map' not described in 'intel_engine_cmd_parser'
> >> drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function
> >> parameter 'trampoline' description in 'intel_engine_cmd_parser'
> >>
> >> Reported-by: Stephen Rothwell
> >> Signed-off-by: Maarten Lankhorst
> >> ---
> >> drivers/gpu/drm/i915/i915_cmd_parser.c | 16 +++-
> >> 1 file changed, 15 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
> >> b/drivers/gpu/drm/i915/i915_cmd_parser.c
> >> index e6f1e93a..afb9b7516999 100644
> >> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> >> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> >> @@ -1369,6 +1369,18 @@ static int check_bbstart(u32 *cmd, u32 offset, u32
> >> length,
> >> return 0;
> >> }
> >>
> >> +/**
> >> + * intel_engine_cmd_parser_alloc_jump_whitelist() - preallocate jump
> >> whitelist for intel_engine_cmd_parser()
> >> + * @batch_length: length of the commands in batch_obj
> >> + * @trampoline: Whether jump trampolines are used.
> >> + *
> >> + * Preallocates a jump whitelist for parsing the cmd buffer in
> >> intel_engine_cmd_parser().
> >> + * This has to be preallocated, because the command parser runs in
> >> signaling context,
> >> + * and may not allocate any memory.
> >> + *
> >> + * Return: NULL or pointer to a jump whitelist, or ERR_PTR() on failure.
> >> Use
> >> + * IS_ERR() to check for errors. Must bre freed() with kfree().
> > IS_ERR_OR_NULL or needs an actual bugfix in the code since we're not
> > consistent. Also s/bre/be/
> We're sort of consistent, NULL is a valid return code. IS_ERR is only on
> faliure. :)
Maybe explain that and then Reviewed-by: Daniel Vetter
Cheers, Daniel
> > -Daniel
> >
> >> + */
> >> unsigned long *intel_engine_cmd_parser_alloc_jump_whitelist(u32
> >> batch_length,
> >> bool
> >> trampoline)
> >> {
> >> @@ -1401,7 +1413,9 @@ unsigned long
> >> *intel_engine_cmd_parser_alloc_jump_whitelist(u32 batch_length,
> >> * @batch_offset: byte offset in the batch at which execution starts
> >> * @batch_length: length of the commands in batch_obj
> >> * @shadow: validated copy of the batch buffer in question
> >> - * @trampoline: whether to emit a conditional trampoline at the end of
> >> the batch
> >> + * @jump_whitelist: buffer preallocated with
> >> intel_engine_cmd_parser_alloc_jump_whitelist()
> >> + * @shadow_map: mapping to @shadow vma
> >> + * @batch_map: mapping to @batch vma
> >> *
> >> * Parses the specified batch buffer looking for privilege violations as
> >> * described in the overview.
> >> --
> >> 2.31.0
> >>
> >
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] [PATCH v5 16/16] of: Add plumbing for restricted DMA pool
If a device is not behind an IOMMU, we look up the device node and set
up the restricted DMA when the restricted-dma-pool is presented.
Signed-off-by: Claire Chang
---
drivers/of/address.c| 25 +
drivers/of/device.c | 3 +++
drivers/of/of_private.h | 5 +
3 files changed, 33 insertions(+)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index 54f221dde267..fff3adfe4986 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1109,6 +1110,30 @@ bool of_dma_is_coherent(struct device_node *np)
}
EXPORT_SYMBOL_GPL(of_dma_is_coherent);
+int of_dma_set_restricted_buffer(struct device *dev)
+{
+ struct device_node *node;
+ int count, i;
+
+ if (!dev->of_node)
+ return 0;
+
+ count = of_property_count_elems_of_size(dev->of_node, "memory-region",
+ sizeof(phandle));
+ for (i = 0; i < count; i++) {
+ node = of_parse_phandle(dev->of_node, "memory-region", i);
+ /* There might be multiple memory regions, but only one
+* restriced-dma-pool region is allowed.
+*/
+ if (of_device_is_compatible(node, "restricted-dma-pool") &&
+ of_device_is_available(node))
+ return of_reserved_mem_device_init_by_idx(
+ dev, dev->of_node, i);
+ }
+
+ return 0;
+}
+
/**
* of_mmio_is_nonposted - Check if device uses non-posted MMIO
* @np:device node
diff --git a/drivers/of/device.c b/drivers/of/device.c
index c5a9473a5fb1..d8d865223e51 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -165,6 +165,9 @@ int of_dma_configure_id(struct device *dev, struct
device_node *np,
arch_setup_dma_ops(dev, dma_start, size, iommu, coherent);
+ if (!iommu)
+ return of_dma_set_restricted_buffer(dev);
+
return 0;
}
EXPORT_SYMBOL_GPL(of_dma_configure_id);
diff --git a/drivers/of/of_private.h b/drivers/of/of_private.h
index d717efbd637d..e9237f5eff48 100644
--- a/drivers/of/of_private.h
+++ b/drivers/of/of_private.h
@@ -163,12 +163,17 @@ struct bus_dma_region;
#if defined(CONFIG_OF_ADDRESS) && defined(CONFIG_HAS_DMA)
int of_dma_get_range(struct device_node *np,
const struct bus_dma_region **map);
+int of_dma_set_restricted_buffer(struct device *dev);
#else
static inline int of_dma_get_range(struct device_node *np,
const struct bus_dma_region **map)
{
return -ENODEV;
}
+static inline int of_dma_get_restricted_buffer(struct device *dev)
+{
+ return -ENODEV;
+}
#endif
#endif /* _LINUX_OF_PRIVATE_H */
--
2.31.1.368.gbe11c130af-goog
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[Intel-gfx] [PATCH v5 15/16] dt-bindings: of: Add restricted DMA pool
Introduce the new compatible string, restricted-dma-pool, for restricted
DMA. One can specify the address and length of the restricted DMA memory
region by restricted-dma-pool in the reserved-memory node.
Signed-off-by: Claire Chang
---
.../reserved-memory/reserved-memory.txt | 24 +++
1 file changed, 24 insertions(+)
diff --git
a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
index e8d3096d922c..fc9a12c2f679 100644
--- a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
+++ b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
@@ -51,6 +51,20 @@ compatible (optional) - standard definition
used as a shared pool of DMA buffers for a set of devices. It can
be used by an operating system to instantiate the necessary pool
management subsystem if necessary.
+- restricted-dma-pool: This indicates a region of memory meant to be
+ used as a pool of restricted DMA buffers for a set of devices. The
+ memory region would be the only region accessible to those devices.
+ When using this, the no-map and reusable properties must not be set,
+ so the operating system can create a virtual mapping that will be
used
+ for synchronization. The main purpose for restricted DMA is to
+ mitigate the lack of DMA access control on systems without an IOMMU,
+ which could result in the DMA accessing the system memory at
+ unexpected times and/or unexpected addresses, possibly leading to
data
+ leakage or corruption. The feature on its own provides a basic level
+ of protection against the DMA overwriting buffer contents at
+ unexpected times. However, to protect against general data leakage
and
+ system memory corruption, the system needs to provide way to lock
down
+ the memory access, e.g., MPU.
- vendor specific string in the form ,[-]
no-map (optional) - empty property
- Indicates the operating system must not create a virtual mapping
@@ -120,6 +134,11 @@ one for multimedia processing (named
multimedia-memory@7700, 64MiB).
compatible = "acme,multimedia-memory";
reg = <0x7700 0x400>;
};
+
+ restricted_dma_mem_reserved: restricted_dma_mem_reserved {
+ compatible = "restricted-dma-pool";
+ reg = <0x5000 0x40>;
+ };
};
/* ... */
@@ -138,4 +157,9 @@ one for multimedia processing (named
multimedia-memory@7700, 64MiB).
memory-region = <&multimedia_reserved>;
/* ... */
};
+
+ pcie_device: pcie_device@0,0 {
+ memory-region = <&restricted_dma_mem_reserved>;
+ /* ... */
+ };
};
--
2.31.1.368.gbe11c130af-goog
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[Intel-gfx] [PATCH v5 14/16] dma-direct: Allocate memory from restricted DMA pool if available
The restricted DMA pool is preferred if available.
The restricted DMA pools provide a basic level of protection against the
DMA overwriting buffer contents at unexpected times. However, to protect
against general data leakage and system memory corruption, the system
needs to provide a way to lock down the memory access, e.g., MPU.
Signed-off-by: Claire Chang
---
kernel/dma/direct.c | 35 ++-
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index 7a27f0510fcc..29523d2a9845 100644
--- a/kernel/dma/direct.c
+++ b/kernel/dma/direct.c
@@ -78,6 +78,10 @@ static bool dma_coherent_ok(struct device *dev, phys_addr_t
phys, size_t size)
static void __dma_direct_free_pages(struct device *dev, struct page *page,
size_t size)
{
+#ifdef CONFIG_DMA_RESTRICTED_POOL
+ if (swiotlb_free(dev, page, size))
+ return;
+#endif
dma_free_contiguous(dev, page, size);
}
@@ -92,7 +96,17 @@ static struct page *__dma_direct_alloc_pages(struct device
*dev, size_t size,
gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
&phys_limit);
- page = dma_alloc_contiguous(dev, size, gfp);
+
+#ifdef CONFIG_DMA_RESTRICTED_POOL
+ page = swiotlb_alloc(dev, size);
+ if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
+ __dma_direct_free_pages(dev, page, size);
+ page = NULL;
+ }
+#endif
+
+ if (!page)
+ page = dma_alloc_contiguous(dev, size, gfp);
if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
dma_free_contiguous(dev, page, size);
page = NULL;
@@ -148,7 +162,7 @@ void *dma_direct_alloc(struct device *dev, size_t size,
gfp |= __GFP_NOWARN;
if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
- !force_dma_unencrypted(dev)) {
+ !force_dma_unencrypted(dev) && !is_dev_swiotlb_force(dev)) {
page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
if (!page)
return NULL;
@@ -161,8 +175,8 @@ void *dma_direct_alloc(struct device *dev, size_t size,
}
if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
- !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
- !dev_is_dma_coherent(dev))
+ !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && !dev_is_dma_coherent(dev) &&
+ !is_dev_swiotlb_force(dev))
return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
/*
@@ -172,7 +186,9 @@ void *dma_direct_alloc(struct device *dev, size_t size,
if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
!gfpflags_allow_blocking(gfp) &&
(force_dma_unencrypted(dev) ||
-(IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
!dev_is_dma_coherent(dev
+(IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
+ !dev_is_dma_coherent(dev))) &&
+ !is_dev_swiotlb_force(dev))
return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
/* we always manually zero the memory once we are done */
@@ -253,15 +269,15 @@ void dma_direct_free(struct device *dev, size_t size,
unsigned int page_order = get_order(size);
if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
- !force_dma_unencrypted(dev)) {
+ !force_dma_unencrypted(dev) && !is_dev_swiotlb_force(dev)) {
/* cpu_addr is a struct page cookie, not a kernel address */
dma_free_contiguous(dev, cpu_addr, size);
return;
}
if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
- !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
- !dev_is_dma_coherent(dev)) {
+ !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && !dev_is_dma_coherent(dev) &&
+ !is_dev_swiotlb_force(dev)) {
arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
return;
}
@@ -289,7 +305,8 @@ struct page *dma_direct_alloc_pages(struct device *dev,
size_t size,
void *ret;
if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
- force_dma_unencrypted(dev) && !gfpflags_allow_blocking(gfp))
+ force_dma_unencrypted(dev) && !gfpflags_allow_blocking(gfp) &&
+ !is_dev_swiotlb_force(dev))
return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
page = __dma_direct_alloc_pages(dev, size, gfp);
--
2.31.1.368.gbe11c130af-goog
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[Intel-gfx] [PATCH v5 13/16] swiotlb: Add restricted DMA alloc/free support.
Add the functions, swiotlb_{alloc,free} to support the memory allocation
from restricted DMA pool.
Signed-off-by: Claire Chang
---
include/linux/swiotlb.h | 4
kernel/dma/swiotlb.c| 35 +--
2 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h
index 0c5a18d9cf89..e8cf49bd90c5 100644
--- a/include/linux/swiotlb.h
+++ b/include/linux/swiotlb.h
@@ -134,6 +134,10 @@ unsigned int swiotlb_max_segment(void);
size_t swiotlb_max_mapping_size(struct device *dev);
bool is_swiotlb_active(struct device *dev);
void __init swiotlb_adjust_size(unsigned long size);
+#ifdef CONFIG_DMA_RESTRICTED_POOL
+struct page *swiotlb_alloc(struct device *dev, size_t size);
+bool swiotlb_free(struct device *dev, struct page *page, size_t size);
+#endif /* CONFIG_DMA_RESTRICTED_POOL */
#else
#define swiotlb_force SWIOTLB_NO_FORCE
static inline bool is_swiotlb_buffer(struct device *dev, phys_addr_t paddr)
diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c
index af0feb8eaead..274272c79080 100644
--- a/kernel/dma/swiotlb.c
+++ b/kernel/dma/swiotlb.c
@@ -454,8 +454,9 @@ static int find_slots(struct device *dev, phys_addr_t
orig_addr,
index = wrap = wrap_index(mem, ALIGN(mem->index, stride));
do {
- if ((slot_addr(tbl_dma_addr, index) & iotlb_align_mask) !=
- (orig_addr & iotlb_align_mask)) {
+ if (orig_addr &&
+ (slot_addr(tbl_dma_addr, index) & iotlb_align_mask) !=
+ (orig_addr & iotlb_align_mask)) {
index = wrap_index(mem, index + 1);
continue;
}
@@ -695,6 +696,36 @@ late_initcall(swiotlb_create_default_debugfs);
#endif
#ifdef CONFIG_DMA_RESTRICTED_POOL
+struct page *swiotlb_alloc(struct device *dev, size_t size)
+{
+ struct io_tlb_mem *mem = dev->dma_io_tlb_mem;
+ phys_addr_t tlb_addr;
+ int index;
+
+ if (!mem)
+ return NULL;
+
+ index = find_slots(dev, 0, size);
+ if (index == -1)
+ return NULL;
+
+ tlb_addr = slot_addr(mem->start, index);
+
+ return pfn_to_page(PFN_DOWN(tlb_addr));
+}
+
+bool swiotlb_free(struct device *dev, struct page *page, size_t size)
+{
+ phys_addr_t tlb_addr = page_to_phys(page);
+
+ if (!is_swiotlb_buffer(dev, tlb_addr))
+ return false;
+
+ release_slots(dev, tlb_addr);
+
+ return true;
+}
+
static int rmem_swiotlb_device_init(struct reserved_mem *rmem,
struct device *dev)
{
--
2.31.1.368.gbe11c130af-goog
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[Intel-gfx] [PATCH v5 12/16] dma-direct: Add a new wrapper __dma_direct_free_pages()
Add a new wrapper __dma_direct_free_pages() that will be useful later
for swiotlb_free().
Signed-off-by: Claire Chang
---
kernel/dma/direct.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index 7a88c34d0867..7a27f0510fcc 100644
--- a/kernel/dma/direct.c
+++ b/kernel/dma/direct.c
@@ -75,6 +75,12 @@ static bool dma_coherent_ok(struct device *dev, phys_addr_t
phys, size_t size)
min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
}
+static void __dma_direct_free_pages(struct device *dev, struct page *page,
+ size_t size)
+{
+ dma_free_contiguous(dev, page, size);
+}
+
static struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
gfp_t gfp)
{
@@ -237,7 +243,7 @@ void *dma_direct_alloc(struct device *dev, size_t size,
return NULL;
}
out_free_pages:
- dma_free_contiguous(dev, page, size);
+ __dma_direct_free_pages(dev, page, size);
return NULL;
}
@@ -273,7 +279,7 @@ void dma_direct_free(struct device *dev, size_t size,
else if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED))
arch_dma_clear_uncached(cpu_addr, size);
- dma_free_contiguous(dev, dma_direct_to_page(dev, dma_addr), size);
+ __dma_direct_free_pages(dev, dma_direct_to_page(dev, dma_addr), size);
}
struct page *dma_direct_alloc_pages(struct device *dev, size_t size,
@@ -310,7 +316,7 @@ struct page *dma_direct_alloc_pages(struct device *dev,
size_t size,
*dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
return page;
out_free_pages:
- dma_free_contiguous(dev, page, size);
+ __dma_direct_free_pages(dev, page, size);
return NULL;
}
@@ -329,7 +335,7 @@ void dma_direct_free_pages(struct device *dev, size_t size,
if (force_dma_unencrypted(dev))
set_memory_encrypted((unsigned long)vaddr, 1 << page_order);
- dma_free_contiguous(dev, page, size);
+ __dma_direct_free_pages(dev, page, size);
}
#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
--
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[Intel-gfx] [PATCH v5 11/16] swiotlb: Refactor swiotlb_tbl_unmap_single
Add a new function, release_slots, to make the code reusable for supporting
different bounce buffer pools, e.g. restricted DMA pool.
Signed-off-by: Claire Chang
---
kernel/dma/swiotlb.c | 35 ---
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c
index b7d634d7a7eb..af0feb8eaead 100644
--- a/kernel/dma/swiotlb.c
+++ b/kernel/dma/swiotlb.c
@@ -547,27 +547,15 @@ phys_addr_t swiotlb_tbl_map_single(struct device *dev,
phys_addr_t orig_addr,
return tlb_addr;
}
-/*
- * tlb_addr is the physical address of the bounce buffer to unmap.
- */
-void swiotlb_tbl_unmap_single(struct device *hwdev, phys_addr_t tlb_addr,
- size_t mapping_size, enum dma_data_direction dir,
- unsigned long attrs)
+static void release_slots(struct device *dev, phys_addr_t tlb_addr)
{
- struct io_tlb_mem *mem = get_io_tlb_mem(hwdev);
+ struct io_tlb_mem *mem = get_io_tlb_mem(dev);
unsigned long flags;
- unsigned int offset = swiotlb_align_offset(hwdev, tlb_addr);
+ unsigned int offset = swiotlb_align_offset(dev, tlb_addr);
int index = (tlb_addr - offset - mem->start) >> IO_TLB_SHIFT;
int nslots = nr_slots(mem->slots[index].alloc_size + offset);
int count, i;
- /*
-* First, sync the memory before unmapping the entry
-*/
- if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
- (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL))
- swiotlb_bounce(hwdev, tlb_addr, mapping_size, DMA_FROM_DEVICE);
-
/*
* Return the buffer to the free list by setting the corresponding
* entries to indicate the number of contiguous entries available.
@@ -602,6 +590,23 @@ void swiotlb_tbl_unmap_single(struct device *hwdev,
phys_addr_t tlb_addr,
spin_unlock_irqrestore(&mem->lock, flags);
}
+/*
+ * tlb_addr is the physical address of the bounce buffer to unmap.
+ */
+void swiotlb_tbl_unmap_single(struct device *dev, phys_addr_t tlb_addr,
+ size_t mapping_size, enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ /*
+* First, sync the memory before unmapping the entry
+*/
+ if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
+ (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL))
+ swiotlb_bounce(dev, tlb_addr, mapping_size, DMA_FROM_DEVICE);
+
+ release_slots(dev, tlb_addr);
+}
+
void swiotlb_sync_single_for_device(struct device *dev, phys_addr_t tlb_addr,
size_t size, enum dma_data_direction dir)
{
--
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[Intel-gfx] [PATCH v5 10/16] swiotlb: Move alloc_size to find_slots
Move the maintenance of alloc_size to find_slots for better code
reusability later.
Signed-off-by: Claire Chang
---
kernel/dma/swiotlb.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c
index 96ff36d8ec53..b7d634d7a7eb 100644
--- a/kernel/dma/swiotlb.c
+++ b/kernel/dma/swiotlb.c
@@ -479,8 +479,11 @@ static int find_slots(struct device *dev, phys_addr_t
orig_addr,
return -1;
found:
- for (i = index; i < index + nslots; i++)
+ for (i = index; i < index + nslots; i++) {
mem->slots[i].list = 0;
+ mem->slots[i].alloc_size =
+ alloc_size - ((i - index) << IO_TLB_SHIFT);
+ }
for (i = index - 1;
io_tlb_offset(i) != IO_TLB_SEGSIZE - 1 &&
mem->slots[i].list; i--)
@@ -535,11 +538,8 @@ phys_addr_t swiotlb_tbl_map_single(struct device *dev,
phys_addr_t orig_addr,
* This is needed when we sync the memory. Then we sync the buffer if
* needed.
*/
- for (i = 0; i < nr_slots(alloc_size + offset); i++) {
+ for (i = 0; i < nr_slots(alloc_size + offset); i++)
mem->slots[index + i].orig_addr = slot_addr(orig_addr, i);
- mem->slots[index + i].alloc_size =
- alloc_size - (i << IO_TLB_SHIFT);
- }
tlb_addr = slot_addr(mem->start, index) + offset;
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL))
--
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[Intel-gfx] [PATCH v5 09/16] swiotlb: Bounce data from/to restricted DMA pool if available
Regardless of swiotlb setting, the restricted DMA pool is preferred if
available.
The restricted DMA pools provide a basic level of protection against the
DMA overwriting buffer contents at unexpected times. However, to protect
against general data leakage and system memory corruption, the system
needs to provide a way to lock down the memory access, e.g., MPU.
Note that is_dev_swiotlb_force doesn't check if
swiotlb_force == SWIOTLB_FORCE. Otherwise the memory allocation behavior
with default swiotlb will be changed by the following patche
("dma-direct: Allocate memory from restricted DMA pool if available").
Signed-off-by: Claire Chang
---
include/linux/swiotlb.h | 13 +
kernel/dma/direct.h | 3 ++-
kernel/dma/swiotlb.c| 8
3 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h
index c530c976d18b..0c5a18d9cf89 100644
--- a/include/linux/swiotlb.h
+++ b/include/linux/swiotlb.h
@@ -120,6 +120,15 @@ static inline bool is_swiotlb_buffer(struct device *dev,
phys_addr_t paddr)
return mem && paddr >= mem->start && paddr < mem->end;
}
+static inline bool is_dev_swiotlb_force(struct device *dev)
+{
+#ifdef CONFIG_DMA_RESTRICTED_POOL
+ if (dev->dma_io_tlb_mem)
+ return true;
+#endif /* CONFIG_DMA_RESTRICTED_POOL */
+ return false;
+}
+
void __init swiotlb_exit(void);
unsigned int swiotlb_max_segment(void);
size_t swiotlb_max_mapping_size(struct device *dev);
@@ -131,6 +140,10 @@ static inline bool is_swiotlb_buffer(struct device *dev,
phys_addr_t paddr)
{
return false;
}
+static inline bool is_dev_swiotlb_force(struct device *dev)
+{
+ return false;
+}
static inline void swiotlb_exit(void)
{
}
diff --git a/kernel/dma/direct.h b/kernel/dma/direct.h
index 13e9e7158d94..f94813674e23 100644
--- a/kernel/dma/direct.h
+++ b/kernel/dma/direct.h
@@ -87,7 +87,8 @@ static inline dma_addr_t dma_direct_map_page(struct device
*dev,
phys_addr_t phys = page_to_phys(page) + offset;
dma_addr_t dma_addr = phys_to_dma(dev, phys);
- if (unlikely(swiotlb_force == SWIOTLB_FORCE))
+ if (unlikely(swiotlb_force == SWIOTLB_FORCE) ||
+ is_dev_swiotlb_force(dev))
return swiotlb_map(dev, phys, size, dir, attrs);
if (unlikely(!dma_capable(dev, dma_addr, size, true))) {
diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c
index 1d221343f1c8..96ff36d8ec53 100644
--- a/kernel/dma/swiotlb.c
+++ b/kernel/dma/swiotlb.c
@@ -344,7 +344,7 @@ void __init swiotlb_exit(void)
static void swiotlb_bounce(struct device *dev, phys_addr_t tlb_addr, size_t
size,
enum dma_data_direction dir)
{
- struct io_tlb_mem *mem = io_tlb_default_mem;
+ struct io_tlb_mem *mem = get_io_tlb_mem(dev);
int index = (tlb_addr - mem->start) >> IO_TLB_SHIFT;
phys_addr_t orig_addr = mem->slots[index].orig_addr;
size_t alloc_size = mem->slots[index].alloc_size;
@@ -426,7 +426,7 @@ static unsigned int wrap_index(struct io_tlb_mem *mem,
unsigned int index)
static int find_slots(struct device *dev, phys_addr_t orig_addr,
size_t alloc_size)
{
- struct io_tlb_mem *mem = io_tlb_default_mem;
+ struct io_tlb_mem *mem = get_io_tlb_mem(dev);
unsigned long boundary_mask = dma_get_seg_boundary(dev);
dma_addr_t tbl_dma_addr =
phys_to_dma_unencrypted(dev, mem->start) & boundary_mask;
@@ -503,7 +503,7 @@ phys_addr_t swiotlb_tbl_map_single(struct device *dev,
phys_addr_t orig_addr,
size_t mapping_size, size_t alloc_size,
enum dma_data_direction dir, unsigned long attrs)
{
- struct io_tlb_mem *mem = io_tlb_default_mem;
+ struct io_tlb_mem *mem = get_io_tlb_mem(dev);
unsigned int offset = swiotlb_align_offset(dev, orig_addr);
unsigned int i;
int index;
@@ -554,7 +554,7 @@ void swiotlb_tbl_unmap_single(struct device *hwdev,
phys_addr_t tlb_addr,
size_t mapping_size, enum dma_data_direction dir,
unsigned long attrs)
{
- struct io_tlb_mem *mem = io_tlb_default_mem;
+ struct io_tlb_mem *mem = get_io_tlb_mem(hwdev);
unsigned long flags;
unsigned int offset = swiotlb_align_offset(hwdev, tlb_addr);
int index = (tlb_addr - offset - mem->start) >> IO_TLB_SHIFT;
--
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[Intel-gfx] [PATCH v5 08/16] swiotlb: Update is_swiotlb_active to add a struct device argument
Update is_swiotlb_active to add a struct device argument. This will be
useful later to allow for restricted DMA pool.
Signed-off-by: Claire Chang
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_ttm.c| 2 +-
drivers/pci/xen-pcifront.c | 2 +-
include/linux/swiotlb.h | 4 ++--
kernel/dma/direct.c | 2 +-
kernel/dma/swiotlb.c | 4 ++--
6 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index ce6b664b10aa..7d48c433446b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -42,7 +42,7 @@ static int i915_gem_object_get_pages_internal(struct
drm_i915_gem_object *obj)
max_order = MAX_ORDER;
#ifdef CONFIG_SWIOTLB
- if (is_swiotlb_active()) {
+ if (is_swiotlb_active(NULL)) {
unsigned int max_segment;
max_segment = swiotlb_max_segment();
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c
b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index e8b506a6685b..2a2ae6d6cf6d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -321,7 +321,7 @@ nouveau_ttm_init(struct nouveau_drm *drm)
}
#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
- need_swiotlb = is_swiotlb_active();
+ need_swiotlb = is_swiotlb_active(NULL);
#endif
ret = ttm_device_init(&drm->ttm.bdev, &nouveau_bo_driver, drm->dev->dev,
diff --git a/drivers/pci/xen-pcifront.c b/drivers/pci/xen-pcifront.c
index b7a8f3a1921f..6d548ce53ce7 100644
--- a/drivers/pci/xen-pcifront.c
+++ b/drivers/pci/xen-pcifront.c
@@ -693,7 +693,7 @@ static int pcifront_connect_and_init_dma(struct
pcifront_device *pdev)
spin_unlock(&pcifront_dev_lock);
- if (!err && !is_swiotlb_active()) {
+ if (!err && !is_swiotlb_active(NULL)) {
err = pci_xen_swiotlb_init_late();
if (err)
dev_err(&pdev->xdev->dev, "Could not setup SWIOTLB!\n");
diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h
index 2a6cca07540b..c530c976d18b 100644
--- a/include/linux/swiotlb.h
+++ b/include/linux/swiotlb.h
@@ -123,7 +123,7 @@ static inline bool is_swiotlb_buffer(struct device *dev,
phys_addr_t paddr)
void __init swiotlb_exit(void);
unsigned int swiotlb_max_segment(void);
size_t swiotlb_max_mapping_size(struct device *dev);
-bool is_swiotlb_active(void);
+bool is_swiotlb_active(struct device *dev);
void __init swiotlb_adjust_size(unsigned long size);
#else
#define swiotlb_force SWIOTLB_NO_FORCE
@@ -143,7 +143,7 @@ static inline size_t swiotlb_max_mapping_size(struct device
*dev)
return SIZE_MAX;
}
-static inline bool is_swiotlb_active(void)
+static inline bool is_swiotlb_active(struct device *dev)
{
return false;
}
diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index 84c9feb5474a..7a88c34d0867 100644
--- a/kernel/dma/direct.c
+++ b/kernel/dma/direct.c
@@ -495,7 +495,7 @@ int dma_direct_supported(struct device *dev, u64 mask)
size_t dma_direct_max_mapping_size(struct device *dev)
{
/* If SWIOTLB is active, use its maximum mapping size */
- if (is_swiotlb_active() &&
+ if (is_swiotlb_active(dev) &&
(dma_addressing_limited(dev) || swiotlb_force == SWIOTLB_FORCE))
return swiotlb_max_mapping_size(dev);
return SIZE_MAX;
diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c
index ffbb8724e06c..1d221343f1c8 100644
--- a/kernel/dma/swiotlb.c
+++ b/kernel/dma/swiotlb.c
@@ -659,9 +659,9 @@ size_t swiotlb_max_mapping_size(struct device *dev)
return ((size_t)IO_TLB_SIZE) * IO_TLB_SEGSIZE;
}
-bool is_swiotlb_active(void)
+bool is_swiotlb_active(struct device *dev)
{
- return io_tlb_default_mem != NULL;
+ return get_io_tlb_mem(dev) != NULL;
}
EXPORT_SYMBOL_GPL(is_swiotlb_active);
--
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[Intel-gfx] [PATCH v5 07/16] swiotlb: Update is_swiotlb_buffer to add a struct device argument
Update is_swiotlb_buffer to add a struct device argument. This will be
useful later to allow for restricted DMA pool.
Signed-off-by: Claire Chang
---
drivers/iommu/dma-iommu.c | 12 ++--
drivers/xen/swiotlb-xen.c | 2 +-
include/linux/swiotlb.h | 6 +++---
kernel/dma/direct.c | 6 +++---
kernel/dma/direct.h | 6 +++---
5 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index 7bcdd1205535..a5df35bfd150 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -504,7 +504,7 @@ static void __iommu_dma_unmap_swiotlb(struct device *dev,
dma_addr_t dma_addr,
__iommu_dma_unmap(dev, dma_addr, size);
- if (unlikely(is_swiotlb_buffer(phys)))
+ if (unlikely(is_swiotlb_buffer(dev, phys)))
swiotlb_tbl_unmap_single(dev, phys, size, dir, attrs);
}
@@ -575,7 +575,7 @@ static dma_addr_t __iommu_dma_map_swiotlb(struct device
*dev, phys_addr_t phys,
}
iova = __iommu_dma_map(dev, phys, aligned_size, prot, dma_mask);
- if (iova == DMA_MAPPING_ERROR && is_swiotlb_buffer(phys))
+ if (iova == DMA_MAPPING_ERROR && is_swiotlb_buffer(dev, phys))
swiotlb_tbl_unmap_single(dev, phys, org_size, dir, attrs);
return iova;
}
@@ -781,7 +781,7 @@ static void iommu_dma_sync_single_for_cpu(struct device
*dev,
if (!dev_is_dma_coherent(dev))
arch_sync_dma_for_cpu(phys, size, dir);
- if (is_swiotlb_buffer(phys))
+ if (is_swiotlb_buffer(dev, phys))
swiotlb_sync_single_for_cpu(dev, phys, size, dir);
}
@@ -794,7 +794,7 @@ static void iommu_dma_sync_single_for_device(struct device
*dev,
return;
phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
- if (is_swiotlb_buffer(phys))
+ if (is_swiotlb_buffer(dev, phys))
swiotlb_sync_single_for_device(dev, phys, size, dir);
if (!dev_is_dma_coherent(dev))
@@ -815,7 +815,7 @@ static void iommu_dma_sync_sg_for_cpu(struct device *dev,
if (!dev_is_dma_coherent(dev))
arch_sync_dma_for_cpu(sg_phys(sg), sg->length, dir);
- if (is_swiotlb_buffer(sg_phys(sg)))
+ if (is_swiotlb_buffer(dev, sg_phys(sg)))
swiotlb_sync_single_for_cpu(dev, sg_phys(sg),
sg->length, dir);
}
@@ -832,7 +832,7 @@ static void iommu_dma_sync_sg_for_device(struct device *dev,
return;
for_each_sg(sgl, sg, nelems, i) {
- if (is_swiotlb_buffer(sg_phys(sg)))
+ if (is_swiotlb_buffer(dev, sg_phys(sg)))
swiotlb_sync_single_for_device(dev, sg_phys(sg),
sg->length, dir);
diff --git a/drivers/xen/swiotlb-xen.c b/drivers/xen/swiotlb-xen.c
index 4c89afc0df62..0c6ed09f8513 100644
--- a/drivers/xen/swiotlb-xen.c
+++ b/drivers/xen/swiotlb-xen.c
@@ -100,7 +100,7 @@ static int is_xen_swiotlb_buffer(struct device *dev,
dma_addr_t dma_addr)
* in our domain. Therefore _only_ check address within our domain.
*/
if (pfn_valid(PFN_DOWN(paddr)))
- return is_swiotlb_buffer(paddr);
+ return is_swiotlb_buffer(dev, paddr);
return 0;
}
diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h
index b469f04cca26..2a6cca07540b 100644
--- a/include/linux/swiotlb.h
+++ b/include/linux/swiotlb.h
@@ -113,9 +113,9 @@ static inline struct io_tlb_mem *get_io_tlb_mem(struct
device *dev)
return io_tlb_default_mem;
}
-static inline bool is_swiotlb_buffer(phys_addr_t paddr)
+static inline bool is_swiotlb_buffer(struct device *dev, phys_addr_t paddr)
{
- struct io_tlb_mem *mem = io_tlb_default_mem;
+ struct io_tlb_mem *mem = get_io_tlb_mem(dev);
return mem && paddr >= mem->start && paddr < mem->end;
}
@@ -127,7 +127,7 @@ bool is_swiotlb_active(void);
void __init swiotlb_adjust_size(unsigned long size);
#else
#define swiotlb_force SWIOTLB_NO_FORCE
-static inline bool is_swiotlb_buffer(phys_addr_t paddr)
+static inline bool is_swiotlb_buffer(struct device *dev, phys_addr_t paddr)
{
return false;
}
diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index f737e3347059..84c9feb5474a 100644
--- a/kernel/dma/direct.c
+++ b/kernel/dma/direct.c
@@ -343,7 +343,7 @@ void dma_direct_sync_sg_for_device(struct device *dev,
for_each_sg(sgl, sg, nents, i) {
phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
- if (unlikely(is_swiotlb_buffer(paddr)))
+ if (unlikely(is_swiotlb_buffer(dev, paddr)))
swiotlb_sync_single_for_device(dev, paddr, sg->length,
dir);
@@ -369,7 +369,7 @@ void dma_direct_sync_sg_for_cpu(struct device
[Intel-gfx] [PATCH v5 06/16] swiotlb: Add a new get_io_tlb_mem getter
Add a new getter, get_io_tlb_mem, to help select the io_tlb_mem struct.
The restricted DMA pool is preferred if available.
Signed-off-by: Claire Chang
---
include/linux/swiotlb.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h
index 03ad6e3b4056..b469f04cca26 100644
--- a/include/linux/swiotlb.h
+++ b/include/linux/swiotlb.h
@@ -2,6 +2,7 @@
#ifndef __LINUX_SWIOTLB_H
#define __LINUX_SWIOTLB_H
+#include
#include
#include
#include
@@ -102,6 +103,16 @@ struct io_tlb_mem {
};
extern struct io_tlb_mem *io_tlb_default_mem;
+static inline struct io_tlb_mem *get_io_tlb_mem(struct device *dev)
+{
+#ifdef CONFIG_DMA_RESTRICTED_POOL
+ if (dev && dev->dma_io_tlb_mem)
+ return dev->dma_io_tlb_mem;
+#endif /* CONFIG_DMA_RESTRICTED_POOL */
+
+ return io_tlb_default_mem;
+}
+
static inline bool is_swiotlb_buffer(phys_addr_t paddr)
{
struct io_tlb_mem *mem = io_tlb_default_mem;
--
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[Intel-gfx] [PATCH v5 05/16] swiotlb: Add restricted DMA pool initialization
Add the initialization function to create restricted DMA pools from
matching reserved-memory nodes.
Signed-off-by: Claire Chang
---
include/linux/device.h | 4 +++
include/linux/swiotlb.h | 3 +-
kernel/dma/swiotlb.c| 80 +
3 files changed, 86 insertions(+), 1 deletion(-)
diff --git a/include/linux/device.h b/include/linux/device.h
index 38a2071cf776..4987608ea4ff 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -416,6 +416,7 @@ struct dev_links_info {
* @dma_pools: Dma pools (if dma'ble device).
* @dma_mem: Internal for coherent mem override.
* @cma_area: Contiguous memory area for dma allocations
+ * @dma_io_tlb_mem: Internal for swiotlb io_tlb_mem override.
* @archdata: For arch-specific additions.
* @of_node: Associated device tree node.
* @fwnode:Associated device node supplied by platform firmware.
@@ -521,6 +522,9 @@ struct device {
#ifdef CONFIG_DMA_CMA
struct cma *cma_area; /* contiguous memory area for dma
allocations */
+#endif
+#ifdef CONFIG_DMA_RESTRICTED_POOL
+ struct io_tlb_mem *dma_io_tlb_mem;
#endif
/* arch specific additions */
struct dev_archdata archdata;
diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h
index 216854a5e513..03ad6e3b4056 100644
--- a/include/linux/swiotlb.h
+++ b/include/linux/swiotlb.h
@@ -72,7 +72,8 @@ extern enum swiotlb_force swiotlb_force;
* range check to see if the memory was in fact allocated by this
* API.
* @nslabs:The number of IO TLB blocks (in groups of 64) between @start and
- * @end. This is command line adjustable via setup_io_tlb_npages.
+ * @end. For default swiotlb, this is command line adjustable via
+ * setup_io_tlb_npages.
* @used: The number of used IO TLB block.
* @list: The free list describing the number of free entries available
* from each index.
diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c
index 57a9adb920bf..ffbb8724e06c 100644
--- a/kernel/dma/swiotlb.c
+++ b/kernel/dma/swiotlb.c
@@ -39,6 +39,13 @@
#ifdef CONFIG_DEBUG_FS
#include
#endif
+#ifdef CONFIG_DMA_RESTRICTED_POOL
+#include
+#include
+#include
+#include
+#include
+#endif
#include
#include
@@ -681,3 +688,76 @@ static int __init swiotlb_create_default_debugfs(void)
late_initcall(swiotlb_create_default_debugfs);
#endif
+
+#ifdef CONFIG_DMA_RESTRICTED_POOL
+static int rmem_swiotlb_device_init(struct reserved_mem *rmem,
+ struct device *dev)
+{
+ struct io_tlb_mem *mem = rmem->priv;
+ unsigned long nslabs = rmem->size >> IO_TLB_SHIFT;
+
+ if (dev->dma_io_tlb_mem)
+ return 0;
+
+ /* Since multiple devices can share the same pool, the private data,
+* io_tlb_mem struct, will be initialized by the first device attached
+* to it.
+*/
+ if (!mem) {
+ mem = kzalloc(struct_size(mem, slots, nslabs), GFP_KERNEL);
+ if (!mem)
+ return -ENOMEM;
+#ifdef CONFIG_ARM
+ if (!PageHighMem(pfn_to_page(PHYS_PFN(rmem->base {
+ kfree(mem);
+ return -EINVAL;
+ }
+#endif /* CONFIG_ARM */
+ swiotlb_init_io_tlb_mem(mem, rmem->base, nslabs, false);
+
+ rmem->priv = mem;
+ }
+
+#ifdef CONFIG_DEBUG_FS
+ if (!io_tlb_default_mem->debugfs)
+ io_tlb_default_mem->debugfs =
+ debugfs_create_dir("swiotlb", NULL);
+
+ swiotlb_create_debugfs(mem, rmem->name, io_tlb_default_mem->debugfs);
+#endif /* CONFIG_DEBUG_FS */
+
+ dev->dma_io_tlb_mem = mem;
+
+ return 0;
+}
+
+static void rmem_swiotlb_device_release(struct reserved_mem *rmem,
+ struct device *dev)
+{
+ if (dev)
+ dev->dma_io_tlb_mem = NULL;
+}
+
+static const struct reserved_mem_ops rmem_swiotlb_ops = {
+ .device_init = rmem_swiotlb_device_init,
+ .device_release = rmem_swiotlb_device_release,
+};
+
+static int __init rmem_swiotlb_setup(struct reserved_mem *rmem)
+{
+ unsigned long node = rmem->fdt_node;
+
+ if (of_get_flat_dt_prop(node, "reusable", NULL) ||
+ of_get_flat_dt_prop(node, "linux,cma-default", NULL) ||
+ of_get_flat_dt_prop(node, "linux,dma-default", NULL) ||
+ of_get_flat_dt_prop(node, "no-map", NULL))
+ return -EINVAL;
+
+ rmem->ops = &rmem_swiotlb_ops;
+ pr_info("Reserved memory: created device swiotlb memory pool at %pa,
size %ld MiB\n",
+ &rmem->base, (unsigned long)rmem->size / SZ_1M);
+ return 0;
+}
+
+RESERVEDMEM_OF_DECLARE(dma, "restricted-dma-pool", rmem_swiotlb_setup);
+#endif /* CONFIG_DMA_RESTRICTED_POOL */
--
2.31.1.368.gbe11c130af-goog
___
[Intel-gfx] [PATCH v5 04/16] swiotlb: Add DMA_RESTRICTED_POOL
Add a new kconfig symbol, DMA_RESTRICTED_POOL, for restricted DMA pool. Signed-off-by: Claire Chang --- kernel/dma/Kconfig | 14 ++ 1 file changed, 14 insertions(+) diff --git a/kernel/dma/Kconfig b/kernel/dma/Kconfig index 77b405508743..3e961dc39634 100644 --- a/kernel/dma/Kconfig +++ b/kernel/dma/Kconfig @@ -80,6 +80,20 @@ config SWIOTLB bool select NEED_DMA_MAP_STATE +config DMA_RESTRICTED_POOL + bool "DMA Restricted Pool" + depends on OF && OF_RESERVED_MEM + select SWIOTLB + help + This enables support for restricted DMA pools which provide a level of + DMA memory protection on systems with limited hardware protection + capabilities, such as those lacking an IOMMU. + + For more information see + + and . + If unsure, say "n". + # # Should be selected if we can mmap non-coherent mappings to userspace. # The only thing that is really required is a way to set an uncached bit -- 2.31.1.368.gbe11c130af-goog ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 03/16] swiotlb: Refactor swiotlb_create_debugfs
Split the debugfs creation to make the code reusable for supporting
different bounce buffer pools, e.g. restricted DMA pool.
Signed-off-by: Claire Chang
---
kernel/dma/swiotlb.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c
index 3f1adee35097..57a9adb920bf 100644
--- a/kernel/dma/swiotlb.c
+++ b/kernel/dma/swiotlb.c
@@ -660,18 +660,24 @@ EXPORT_SYMBOL_GPL(is_swiotlb_active);
#ifdef CONFIG_DEBUG_FS
-static int __init swiotlb_create_debugfs(void)
+static void swiotlb_create_debugfs(struct io_tlb_mem *mem, const char *name,
+ struct dentry *node)
{
- struct io_tlb_mem *mem = io_tlb_default_mem;
-
if (!mem)
- return 0;
- mem->debugfs = debugfs_create_dir("swiotlb", NULL);
+ return;
+
+ mem->debugfs = debugfs_create_dir(name, node);
debugfs_create_ulong("io_tlb_nslabs", 0400, mem->debugfs, &mem->nslabs);
debugfs_create_ulong("io_tlb_used", 0400, mem->debugfs, &mem->used);
+}
+
+static int __init swiotlb_create_default_debugfs(void)
+{
+ swiotlb_create_debugfs(io_tlb_default_mem, "swiotlb", NULL);
+
return 0;
}
-late_initcall(swiotlb_create_debugfs);
+late_initcall(swiotlb_create_default_debugfs);
#endif
--
2.31.1.368.gbe11c130af-goog
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[Intel-gfx] [PATCH v5 01/16] swiotlb: Fix the type of index
Fix the type of index from unsigned int to int since find_slots() might
return -1.
Fixes: 0774983bc923 ("swiotlb: refactor swiotlb_tbl_map_single")
Signed-off-by: Claire Chang
---
kernel/dma/swiotlb.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c
index 0a5b6f7e75bc..8635a57f88e9 100644
--- a/kernel/dma/swiotlb.c
+++ b/kernel/dma/swiotlb.c
@@ -499,7 +499,8 @@ phys_addr_t swiotlb_tbl_map_single(struct device *dev,
phys_addr_t orig_addr,
{
struct io_tlb_mem *mem = io_tlb_default_mem;
unsigned int offset = swiotlb_align_offset(dev, orig_addr);
- unsigned int index, i;
+ unsigned int i;
+ int index;
phys_addr_t tlb_addr;
if (!mem)
--
2.31.1.368.gbe11c130af-goog
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[Intel-gfx] [PATCH v5 02/16] swiotlb: Refactor swiotlb init functions
Add a new function, swiotlb_init_io_tlb_mem, for the io_tlb_mem struct
initialization to make the code reusable.
Note that we now also call set_memory_decrypted in swiotlb_init_with_tbl.
Signed-off-by: Claire Chang
---
kernel/dma/swiotlb.c | 51 ++--
1 file changed, 25 insertions(+), 26 deletions(-)
diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c
index 8635a57f88e9..3f1adee35097 100644
--- a/kernel/dma/swiotlb.c
+++ b/kernel/dma/swiotlb.c
@@ -166,9 +166,30 @@ void __init swiotlb_update_mem_attributes(void)
memset(vaddr, 0, bytes);
}
-int __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose)
+static void swiotlb_init_io_tlb_mem(struct io_tlb_mem *mem, phys_addr_t start,
+ unsigned long nslabs, bool late_alloc)
{
+ void *vaddr = phys_to_virt(start);
unsigned long bytes = nslabs << IO_TLB_SHIFT, i;
+
+ mem->nslabs = nslabs;
+ mem->start = start;
+ mem->end = mem->start + bytes;
+ mem->index = 0;
+ mem->late_alloc = late_alloc;
+ spin_lock_init(&mem->lock);
+ for (i = 0; i < mem->nslabs; i++) {
+ mem->slots[i].list = IO_TLB_SEGSIZE - io_tlb_offset(i);
+ mem->slots[i].orig_addr = INVALID_PHYS_ADDR;
+ mem->slots[i].alloc_size = 0;
+ }
+
+ set_memory_decrypted((unsigned long)vaddr, bytes >> PAGE_SHIFT);
+ memset(vaddr, 0, bytes);
+}
+
+int __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose)
+{
struct io_tlb_mem *mem;
size_t alloc_size;
@@ -184,16 +205,8 @@ int __init swiotlb_init_with_tbl(char *tlb, unsigned long
nslabs, int verbose)
if (!mem)
panic("%s: Failed to allocate %zu bytes align=0x%lx\n",
__func__, alloc_size, PAGE_SIZE);
- mem->nslabs = nslabs;
- mem->start = __pa(tlb);
- mem->end = mem->start + bytes;
- mem->index = 0;
- spin_lock_init(&mem->lock);
- for (i = 0; i < mem->nslabs; i++) {
- mem->slots[i].list = IO_TLB_SEGSIZE - io_tlb_offset(i);
- mem->slots[i].orig_addr = INVALID_PHYS_ADDR;
- mem->slots[i].alloc_size = 0;
- }
+
+ swiotlb_init_io_tlb_mem(mem, __pa(tlb), nslabs, false);
io_tlb_default_mem = mem;
if (verbose)
@@ -280,7 +293,6 @@ swiotlb_late_init_with_default_size(size_t default_size)
int
swiotlb_late_init_with_tbl(char *tlb, unsigned long nslabs)
{
- unsigned long bytes = nslabs << IO_TLB_SHIFT, i;
struct io_tlb_mem *mem;
if (swiotlb_force == SWIOTLB_NO_FORCE)
@@ -295,20 +307,7 @@ swiotlb_late_init_with_tbl(char *tlb, unsigned long nslabs)
if (!mem)
return -ENOMEM;
- mem->nslabs = nslabs;
- mem->start = virt_to_phys(tlb);
- mem->end = mem->start + bytes;
- mem->index = 0;
- mem->late_alloc = 1;
- spin_lock_init(&mem->lock);
- for (i = 0; i < mem->nslabs; i++) {
- mem->slots[i].list = IO_TLB_SEGSIZE - io_tlb_offset(i);
- mem->slots[i].orig_addr = INVALID_PHYS_ADDR;
- mem->slots[i].alloc_size = 0;
- }
-
- set_memory_decrypted((unsigned long)tlb, bytes >> PAGE_SHIFT);
- memset(tlb, 0, bytes);
+ swiotlb_init_io_tlb_mem(mem, virt_to_phys(tlb), nslabs, true);
io_tlb_default_mem = mem;
swiotlb_print_info();
--
I'm not 100% sure if set_memory_decrypted is safe to call in
swiotlb_init_with_tbl, but I didn't hit any issue booting with this.
2.31.1.368.gbe11c130af-goog
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[Intel-gfx] [PATCH v5 00/16] Restricted DMA
This series implements mitigations for lack of DMA access control on systems without an IOMMU, which could result in the DMA accessing the system memory at unexpected times and/or unexpected addresses, possibly leading to data leakage or corruption. For example, we plan to use the PCI-e bus for Wi-Fi and that PCI-e bus is not behind an IOMMU. As PCI-e, by design, gives the device full access to system memory, a vulnerability in the Wi-Fi firmware could easily escalate to a full system exploit (remote wifi exploits: [1a], [1b] that shows a full chain of exploits; [2], [3]). To mitigate the security concerns, we introduce restricted DMA. Restricted DMA utilizes the existing swiotlb to bounce streaming DMA in and out of a specially allocated region and does memory allocation from the same region. The feature on its own provides a basic level of protection against the DMA overwriting buffer contents at unexpected times. However, to protect against general data leakage and system memory corruption, the system needs to provide a way to restrict the DMA to a predefined memory region (this is usually done at firmware level, e.g. MPU in ATF on some ARM platforms [4]). [1a] https://googleprojectzero.blogspot.com/2017/04/over-air-exploiting-broadcoms-wi-fi_4.html [1b] https://googleprojectzero.blogspot.com/2017/04/over-air-exploiting-broadcoms-wi-fi_11.html [2] https://blade.tencent.com/en/advisories/qualpwn/ [3] https://www.bleepingcomputer.com/news/security/vulnerabilities-found-in-highly-popular-firmware-for-wifi-chips/ [4] https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c#L132 v5: Rebase on latest linux-next v4: - Fix spinlock bad magic - Use rmem->name for debugfs entry - Address the comments in v3 v3: Using only one reserved memory region for both streaming DMA and memory allocation. https://lore.kernel.org/patchwork/cover/1360992/ v2: Building on top of swiotlb. https://lore.kernel.org/patchwork/cover/1280705/ v1: Using dma_map_ops. https://lore.kernel.org/patchwork/cover/1271660/ Claire Chang (16): swiotlb: Fix the type of index swiotlb: Refactor swiotlb init functions swiotlb: Refactor swiotlb_create_debugfs swiotlb: Add DMA_RESTRICTED_POOL swiotlb: Add restricted DMA pool initialization swiotlb: Add a new get_io_tlb_mem getter swiotlb: Update is_swiotlb_buffer to add a struct device argument swiotlb: Update is_swiotlb_active to add a struct device argument swiotlb: Bounce data from/to restricted DMA pool if available swiotlb: Move alloc_size to find_slots swiotlb: Refactor swiotlb_tbl_unmap_single dma-direct: Add a new wrapper __dma_direct_free_pages() swiotlb: Add restricted DMA alloc/free support. dma-direct: Allocate memory from restricted DMA pool if available dt-bindings: of: Add restricted DMA pool of: Add plumbing for restricted DMA pool .../reserved-memory/reserved-memory.txt | 24 ++ drivers/gpu/drm/i915/gem/i915_gem_internal.c | 2 +- drivers/gpu/drm/nouveau/nouveau_ttm.c | 2 +- drivers/iommu/dma-iommu.c | 12 +- drivers/of/address.c | 25 ++ drivers/of/device.c | 3 + drivers/of/of_private.h | 5 + drivers/pci/xen-pcifront.c| 2 +- drivers/xen/swiotlb-xen.c | 2 +- include/linux/device.h| 4 + include/linux/swiotlb.h | 41 ++- kernel/dma/Kconfig| 14 + kernel/dma/direct.c | 57 +++-- kernel/dma/direct.h | 9 +- kernel/dma/swiotlb.c | 242 +- 15 files changed, 347 insertions(+), 97 deletions(-) -- 2.31.1.368.gbe11c130af-goog ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
