[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/11] drm/amdgpu: Comply with implicit fencing rules
== Series Details == Series: series starting with [01/11] drm/amdgpu: Comply with implicit fencing rules URL : https://patchwork.freedesktop.org/series/90401/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10119_full -> Patchwork_20167_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20167_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20167_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20167_full: ### IGT changes ### Possible regressions * igt@perf@non-zero-reason: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10119/shard-skl3/igt@p...@non-zero-reason.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20167/shard-skl2/igt@p...@non-zero-reason.html Known issues Here are the changes found in Patchwork_20167_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20167/shard-kbl4/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-kbl: NOTRUN -> [DMESG-WARN][4] ([i915#180]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20167/shard-kbl3/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_ctx_persistence@clone: - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20167/shard-snb5/igt@gem_ctx_persiste...@clone.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2846]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10119/shard-kbl3/igt@gem_exec_f...@basic-deadline.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20167/shard-kbl3/igt@gem_exec_f...@basic-deadline.html - shard-skl: NOTRUN -> [FAIL][8] ([i915#2846]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20167/shard-skl3/igt@gem_exec_f...@basic-deadline.html - shard-apl: NOTRUN -> [FAIL][9] ([i915#2846]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20167/shard-apl6/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10119/shard-glk5/igt@gem_exec_fair@basic-none-...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20167/shard-glk1/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10119/shard-kbl2/igt@gem_exec_fair@basic-pace-s...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20167/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: NOTRUN -> [FAIL][14] ([i915#2876]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20167/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html - shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10119/shard-tglb8/igt@gem_exec_fair@basic-p...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20167/shard-tglb3/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy: - shard-skl: NOTRUN -> [INCOMPLETE][17] ([i915#198] / [i915#3468]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20167/shard-skl3/igt@gem_mmap_...@cpuset-basic-small-copy-xy.html * igt@gem_mmap_gtt@fault-concurrent-x: - shard-snb: NOTRUN -> [INCOMPLETE][18] ([i915#3468] / [i915#3485]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20167/shard-snb2/igt@gem_mmap_...@fault-concurrent-x.html - shard-kbl: NOTRUN -> [INCOMPLETE][19] ([i915#3468]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20167/shard-kbl3/igt@gem_mmap_...@fault-concurrent-x.html * igt@gem_mmap_gtt@fault-concurrent-y: - shard-snb: NOTRUN -> [INCOMPLETE][20] ([i915#3468]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20167/shard-snb6/igt@gem_mmap_...@fault-concurrent-y.html - shard-skl: NOTRUN -> [INCOMPLETE][21] ([i915#3468]) [21]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Use list_entry to access list members
== Series Details ==
Series: drm/i915/gem: Use list_entry to access list members
URL : https://patchwork.freedesktop.org/series/90449/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10123 -> Patchwork_20176
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20176/index.html
Known issues
Here are the changes found in Patchwork_20176 that come from known issues:
### IGT changes ###
Warnings
* igt@i915_selftest@live@execlists:
- fi-cfl-8109u: [DMESG-FAIL][1] ([i915#3462]) -> [INCOMPLETE][2]
([i915#3462])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10123/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20176/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
- fi-icl-u2: [INCOMPLETE][3] ([i915#2782] / [i915#3462]) ->
[DMESG-FAIL][4] ([i915#3462])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10123/fi-icl-u2/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20176/fi-icl-u2/igt@i915_selftest@l...@execlists.html
- fi-bsw-kefka: [DMESG-FAIL][5] ([i915#3462]) -> [INCOMPLETE][6]
([i915#2782] / [i915#2940] / [i915#3462])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10123/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20176/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-bsw-kefka: [FAIL][7] ([i915#1436]) -> [FAIL][8] ([fdo#109271] /
[i915#1436])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10123/fi-bsw-kefka/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20176/fi-bsw-kefka/igt@run...@aborted.html
- fi-skl-6600u: [FAIL][9] ([i915#1436] / [i915#3363]) -> [FAIL][10]
([i915#1436] / [i915#2426] / [i915#3363])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10123/fi-skl-6600u/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20176/fi-skl-6600u/igt@run...@aborted.html
- fi-cfl-8109u: [FAIL][11] ([i915#2426] / [i915#3363]) -> [FAIL][12]
([i915#3363])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10123/fi-cfl-8109u/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20176/fi-cfl-8109u/igt@run...@aborted.html
- fi-icl-u2: [FAIL][13] ([i915#2782] / [i915#3363]) -> [FAIL][14]
([i915#2426] / [i915#2782] / [i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10123/fi-icl-u2/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20176/fi-icl-u2/igt@run...@aborted.html
- fi-glk-dsi: [FAIL][15] ([i915#3363] / [k.org#202321]) ->
[FAIL][16] ([i915#2426] / [i915#3363] / [k.org#202321])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10123/fi-glk-dsi/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20176/fi-glk-dsi/igt@run...@aborted.html
- fi-bsw-nick:[FAIL][17] ([i915#1436]) -> [FAIL][18] ([fdo#109271]
/ [i915#1436])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10123/fi-bsw-nick/igt@run...@aborted.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20176/fi-bsw-nick/igt@run...@aborted.html
- fi-kbl-soraka: [FAIL][19] ([i915#1436] / [i915#3363]) -> [FAIL][20]
([i915#1436] / [i915#2426] / [i915#3363])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10123/fi-kbl-soraka/igt@run...@aborted.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20176/fi-kbl-soraka/igt@run...@aborted.html
- fi-kbl-guc: [FAIL][21] ([i915#1436] / [i915#3363]) -> [FAIL][22]
([i915#1436] / [i915#2426] / [i915#3363])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10123/fi-kbl-guc/igt@run...@aborted.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20176/fi-kbl-guc/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (42 -> 39)
--
Missing
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gem: Use list_entry to access list members
== Series Details == Series: drm/i915/gem: Use list_entry to access list members URL : https://patchwork.freedesktop.org/series/90449/ State : warning == Summary == $ dim checkpatch origin/drm-tip ea9ca76d0bd2 drm/i915/gem: Use list_entry to access list members -:22: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #22: FILE: drivers/gpu/drm/i915/gvt/dmabuf.c:152: + dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj, list); -:34: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!dmabuf_obj->info" #34: FILE: drivers/gpu/drm/i915/gvt/dmabuf.c:361: + if (dmabuf_obj->info == NULL) total: 0 errors, 0 warnings, 2 checks, 41 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gem: Use list_entry to access list members
Use list_entry() instead of container_of() to access list members.
Also drop unnecessary and misleading NULL checks on the result of
list_entry().
Signed-off-by: Guenter Roeck
---
drivers/gpu/drm/i915/gvt/dmabuf.c | 17 +
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c
b/drivers/gpu/drm/i915/gvt/dmabuf.c
index d4f883f35b95..4241af5074a9 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.c
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -148,7 +148,7 @@ static void dmabuf_gem_object_free(struct kref *kref)
if (vgpu && vgpu->active && !list_empty(>dmabuf_obj_list_head)) {
list_for_each(pos, >dmabuf_obj_list_head) {
- dmabuf_obj = container_of(pos,
+ dmabuf_obj = list_entry(pos,
struct intel_vgpu_dmabuf_obj, list);
if (dmabuf_obj == obj) {
list_del(pos);
@@ -357,10 +357,8 @@ pick_dmabuf_by_info(struct intel_vgpu *vgpu,
struct intel_vgpu_dmabuf_obj *ret = NULL;
list_for_each(pos, >dmabuf_obj_list_head) {
- dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
- list);
- if ((dmabuf_obj == NULL) ||
- (dmabuf_obj->info == NULL))
+ dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj,
list);
+ if (dmabuf_obj->info == NULL)
continue;
fb_info = (struct intel_vgpu_fb_info *)dmabuf_obj->info;
@@ -387,11 +385,7 @@ pick_dmabuf_by_num(struct intel_vgpu *vgpu, u32 id)
struct intel_vgpu_dmabuf_obj *ret = NULL;
list_for_each(pos, >dmabuf_obj_list_head) {
- dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
- list);
- if (!dmabuf_obj)
- continue;
-
+ dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj,
list);
if (dmabuf_obj->dmabuf_id == id) {
ret = dmabuf_obj;
break;
@@ -600,8 +594,7 @@ void intel_vgpu_dmabuf_cleanup(struct intel_vgpu *vgpu)
mutex_lock(>dmabuf_lock);
list_for_each_safe(pos, n, >dmabuf_obj_list_head) {
- dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
- list);
+ dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj,
list);
dmabuf_obj->vgpu = NULL;
idr_remove(>object_idr, dmabuf_obj->dmabuf_id);
--
2.25.1
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[Intel-gfx] i915 gvt broke drm-tip; Fix ASAP
Hi,
after creating drm-tip today as part of [1], building drm-tip is now
broken with the error message shown below.
Some register constants appear to be missing from the GVT code. Please
fix ASAP.
Best regards
Thomas
tzimmermann@linux-uq9g:~/Projekte/linux> LANG= make -j8 W=1 O=build-x86_64/
make[1]: Entering directory '/home/tzimmermann/Projekte/linux/build-x86_64'
GEN Makefile
DESCEND objtool
CALL../scripts/atomic/check-atomics.sh
CALL../scripts/checksyscalls.sh
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/via/via_irq.o
CC [M] drivers/gpu/drm/via/via_drv.o
CC [M] drivers/gpu/drm/i915/gvt/handlers.o
CC [M] drivers/gpu/drm/via/via_map.o
CC [M] drivers/gpu/drm/vgem/vgem_drv.o
../drivers/gpu/drm/i915/gvt/handlers.c: In function 'init_skl_mmio_info':
../drivers/gpu/drm/i915/gvt/handlers.c:3345:9: error: 'CSR_SSP_BASE'
undeclared (first use in this function); did you mean 'MSR_FS_BASE'?
3345 | MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
| ^~~~
../drivers/gpu/drm/i915/gvt/handlers.c:2120:48: note: in definition of
macro 'MMIO_F'
2120 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
|^~~
../drivers/gpu/drm/i915/gvt/handlers.c:3345:2: note: in expansion of
macro 'MMIO_D'
3345 | MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
| ^~
../drivers/gpu/drm/i915/gvt/handlers.c:3345:9: note: each undeclared
identifier is reported only once for each function it appears in
3345 | MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
| ^~~~
../drivers/gpu/drm/i915/gvt/handlers.c:2120:48: note: in definition of
macro 'MMIO_F'
2120 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
|^~~
../drivers/gpu/drm/i915/gvt/handlers.c:3345:2: note: in expansion of
macro 'MMIO_D'
3345 | MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
| ^~
../drivers/gpu/drm/i915/gvt/handlers.c:3346:9: error: 'CSR_HTP_SKL'
undeclared (first use in this function); did you mean 'DMC_HTP_SKL'?
3346 | MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
| ^~~
../drivers/gpu/drm/i915/gvt/handlers.c:2120:48: note: in definition of
macro 'MMIO_F'
2120 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
|^~~
../drivers/gpu/drm/i915/gvt/handlers.c:3346:2: note: in expansion of
macro 'MMIO_D'
3346 | MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
| ^~
../drivers/gpu/drm/i915/gvt/handlers.c:3347:9: error: 'CSR_LAST_WRITE'
undeclared (first use in this function); did you mean 'DMC_LAST_WRITE'?
3347 | MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS);
| ^~
../drivers/gpu/drm/i915/gvt/handlers.c:2120:48: note: in definition of
macro 'MMIO_F'
2120 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
|^~~
../drivers/gpu/drm/i915/gvt/handlers.c:3347:2: note: in expansion of
macro 'MMIO_D'
3347 | MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS);
| ^~
CC [M] drivers/gpu/drm/via/via_mm.o
CC [M] drivers/gpu/drm/via/via_dma.o
In file included from ../drivers/gpu/drm/i915/i915_drv.h:64,
from ../drivers/gpu/drm/i915/gvt/handlers.c:39:
../drivers/gpu/drm/i915/gvt/handlers.c: At top level:
../drivers/gpu/drm/i915/gvt/handlers.c:3658:21: error:
'CSR_MMIO_START_RANGE' undeclared here (not in a function); did you mean
'DMC_MMIO_START_RANGE'?
3658 | {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
| ^~~~
../drivers/gpu/drm/i915/i915_reg.h:185:47: note: in definition of macro
'_MMIO'
185 | #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
| ^
make[5]: *** [../scripts/Makefile.build:272:
drivers/gpu/drm/i915/gvt/handlers.o] Error 1
[1]
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=304ba5dca49a21e6f4040494c669134787145118
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: fix typo when returning table
== Series Details == Series: drm/i915/display: fix typo when returning table URL : https://patchwork.freedesktop.org/series/90385/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10116_full -> Patchwork_20166_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20166_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20166_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20166_full: ### IGT changes ### Possible regressions * igt@perf@non-zero-reason: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10116/shard-skl7/igt@p...@non-zero-reason.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20166/shard-skl3/igt@p...@non-zero-reason.html ### Piglit changes ### Possible regressions * object namespace pollution@texture with glclear (NEW): - pig-skl-6260u: NOTRUN -> [INCOMPLETE][3] +2 similar issues [3]: None * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 42 1 8 4: - pig-glk-j5005: NOTRUN -> [INCOMPLETE][4] [4]: None New tests - New tests have been introduced between CI_DRM_10116_full and Patchwork_20166_full: ### New Piglit tests (3) ### * object namespace pollution@texture with glbitmap: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * object namespace pollution@texture with glblitframebuffer: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * object namespace pollution@texture with glclear: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_20166_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][5] ([i915#3002]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20166/shard-snb6/igt@gem_cre...@create-massive.html - shard-kbl: NOTRUN -> [DMESG-WARN][6] ([i915#3002]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20166/shard-kbl3/igt@gem_cre...@create-massive.html - shard-skl: NOTRUN -> [DMESG-WARN][7] ([i915#3002]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20166/shard-skl3/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-mixed-process: - shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20166/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-mixed-process.html * igt@gem_ctx_ringsize@active@bcs0: - shard-skl: NOTRUN -> [INCOMPLETE][9] ([i915#3316]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20166/shard-skl5/igt@gem_ctx_ringsize@act...@bcs0.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][10] -> [TIMEOUT][11] ([i915#2369] / [i915#3063]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10116/shard-tglb7/igt@gem_...@unwedge-stress.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20166/shard-tglb3/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][12] ([i915#2846]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20166/shard-skl4/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10116/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20166/shard-iclb6/igt@gem_exec_fair@basic-none-sh...@rcs0.html - shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10116/shard-tglb2/igt@gem_exec_fair@basic-none-sh...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20166/shard-tglb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html - shard-glk: [PASS][17] -> [FAIL][18] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10116/shard-glk3/igt@gem_exec_fair@basic-none-sh...@rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20166/shard-glk3/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][19] ([i915#2842]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20166/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html *
[Intel-gfx] ✓ Fi.CI.IGT: success for More DMC cleanup (rev2)
== Series Details ==
Series: More DMC cleanup (rev2)
URL : https://patchwork.freedesktop.org/series/90379/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10116_full -> Patchwork_20165_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20165_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane@pixel-format@pipe-a-planes}:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10116/shard-tglb1/igt@kms_plane@pixel-for...@pipe-a-planes.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20165/shard-tglb3/igt@kms_plane@pixel-for...@pipe-a-planes.html
Known issues
Here are the changes found in Patchwork_20165_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_create@create-massive:
- shard-skl: NOTRUN -> [DMESG-WARN][3] ([i915#3002])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20165/shard-skl4/igt@gem_cre...@create-massive.html
* igt@gem_ctx_persistence@legacy-engines-mixed-process:
- shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +2
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20165/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-mixed-process.html
* igt@gem_ctx_ringsize@active@bcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][5] ([i915#3316])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20165/shard-skl9/igt@gem_ctx_ringsize@act...@bcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-skl: NOTRUN -> [FAIL][6] ([i915#2846])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20165/shard-skl7/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10116/shard-glk3/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20165/shard-glk4/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][9] ([i915#2842])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20165/shard-kbl4/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar
issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10116/shard-kbl4/igt@gem_exec_fair@basic-n...@vecs0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20165/shard-kbl3/igt@gem_exec_fair@basic-n...@vecs0.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#2190])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20165/shard-kbl4/igt@gem_huc_c...@huc-copy.html
* igt@gem_mmap_gtt@big-copy:
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#307])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10116/shard-glk4/igt@gem_mmap_...@big-copy.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20165/shard-glk5/igt@gem_mmap_...@big-copy.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy:
- shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#198] /
[i915#3468])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10116/shard-skl6/igt@gem_mmap_...@cpuset-basic-small-copy.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20165/shard-skl4/igt@gem_mmap_...@cpuset-basic-small-copy.html
- shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([i915#3468])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10116/shard-tglb1/igt@gem_mmap_...@cpuset-basic-small-copy.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20165/shard-tglb5/igt@gem_mmap_...@cpuset-basic-small-copy.html
* igt@gem_mmap_gtt@cpuset-medium-copy-xy:
- shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([i915#3468] /
[i915#750])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10116/shard-tglb2/igt@gem_mmap_...@cpuset-medium-copy-xy.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20165/shard-tglb7/igt@gem_mmap_...@cpuset-medium-copy-xy.html
- shard-glk: [PASS][21] -> [INCOMPLETE][22] ([i915#3468])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10116/shard-glk9/igt@gem_mmap_...@cpuset-medium-copy-xy.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20165/shard-glk1/igt@gem_mmap_...@cpuset-medium-copy-xy.html
* igt@gem_mmap_gtt@fault-concurrent:
- shard-skl: NOTRUN ->
Re: [Intel-gfx] [Mesa-dev] [PATCH 01/11] drm/amdgpu: Comply with implicit fencing rules
Am 21.05.21 um 20:31 schrieb Daniel Vetter: [SNIP] We could provide an IOCTL for the BO to change the flag. That's not the semantics we need. But could we first figure out the semantics we want to use here? Cause I'm pretty sure we don't actually need those changes at all and as said before I'm certainly NAKing things which break existing use cases. Please read how other drivers do this and at least _try_ to understand it. I'm really loosing my patience here with you NAKing patches you're not even understanding (or did you actually read and fully understand the entire story I typed up here, and your NAK is on the entire thing?). There's not much useful conversation to be had with that approach. And with drivers I mean kernel + userspace here. Well to be honest I did fully read that, but I was just to emotionally attached to answer more appropriately in that moment. And I'm sorry that I react emotional on that, but it is really frustrating that I'm not able to convince you that we have a major problem which affects all drivers and not just amdgpu. Regarding the reason why I'm NAKing this particular patch, you are breaking existing uAPI for RADV with that. And as a maintainer of the driver I have simply no other choice than saying halt, stop we can't do it like this. I'm perfectly aware that I've some holes in the understanding of how ANV or other Vulkan/OpenGL stacks work. But you should probably also admit that you have some holes how amdgpu works or otherwise I can't imagine why you suggest a patch which simply breaks RADV. I mean we are working together for years now and I think you know me pretty well, do you really think I scream bloody hell we can't do this without a good reason? So let's stop throwing halve backed solutions at each other and discuss what we can do to solve the different problems we are both seeing here. That's the other frustration part: You're trying to fix this purely in the kernel. This is exactly one of these issues why we require open source userspace, so that we can fix the issues correctly across the entire stack. And meanwhile you're steadfastily refusing to even look at that the userspace side of the picture. Well I do fully understand the userspace side of the picture for the AMD stack. I just don't think we should give userspace that much control over the fences in the dma_resv object without untangling them from resource management. And RADV is exercising exclusive sync for amdgpu already. You can do submission to both the GFX, Compute and SDMA queues in Vulkan and those currently won't over-synchronize. When you then send a texture generated by multiple engines to the Compositor the kernel will correctly inserts waits for all submissions of the other process. So this already works for RADV and completely without the IOCTL Jason proposed. IIRC we also have unit tests which exercised that feature for the video decoding use case long before RADV even existed. And yes I have to admit that I haven't thought about interaction with other drivers when I came up with this because the rules of that interaction wasn't clear to me at that time. Also I thought through your tlb issue, why are you even putting these tlb flush fences into the shard dma_resv slots? If you store them somewhere else in the amdgpu private part, the oversync issues goes away - in your ttm bo move callback, you can just make your bo copy job depend on them too (you have to anyway) - even for p2p there's not an issue here, because you have the ->move_notify callback, and can then lift the tlb flush fences from your private place to the shared slots so the exporter can see them. Because adding a shared fence requires that this shared fence signals after the exclusive fence. And this is a perfect example to explain why this is so problematic and also why why we currently stumble over that only in amdgpu. In TTM we have a feature which allows evictions to be pipelined and don't wait for the evicting DMA operation. Without that driver will stall waiting for their allocations to finish when we need to allocate memory. For certain use cases this gives you a ~20% fps increase under memory pressure, so it is a really important feature. This works by adding the fence of the last eviction DMA operation to BOs when their backing store is newly allocated. That's what the ttm_bo_add_move_fence() function you stumbled over is good for: https://elixir.bootlin.com/linux/v5.13-rc2/source/drivers/gpu/drm/ttm/ttm_bo.c#L692 Now the problem is it is possible that the application is terminated before it can complete it's command submission. But since resource management only waits for the shared fences when there are some there is a chance that we free up memory while it is still in use. Because of this we have some rather crude workarounds in amdgpu. For example IIRC we manual wait for any potential exclusive fence before freeing memory. We
Re: [Intel-gfx] [PATCH] drm/i915/gvt: Add missing macro name changes
On Fri, May 21, 2021 at 10:40:47AM -0700, Anusha Srivatsa wrote:
Propogate changes to macros name containing CSR_*
to DMC_* from display side.
Fixes: 0633cdcbaa77 ("drm/i915/dmc: Rename macro names containing csr")
Cc: intel-gvt-...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/gvt/handlers.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index dda320749c65..33496397a74f 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -3342,9 +3342,9 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
- MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
- MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
- MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS);
+ MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
+ MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
+ MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
@@ -3655,7 +3655,7 @@ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
* otherwise, need to update cmd_reg_handler in cmd_parser.c
*/
static struct gvt_mmio_block mmio_blocks[] = {
- {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
+ {D_SKL_PLUS, _MMIO(DMC_MMIO_START_RANGE), 0x3000, NULL, NULL},
{D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x4, NULL, NULL},
{D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
pvinfo_mmio_read, pvinfo_mmio_write},
--
2.25.0
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