Re: [Intel-gfx] [PATCH] drm/i915: Add relocation exceptions for two other platforms
On Thu, 27 May 2021 at 20:04, Daniel Vetter wrote: > > On Wed, May 26, 2021 at 10:35:49AM +1000, Dave Airlie wrote: > > On Wed, 12 May 2021 at 03:05, Daniel Vetter wrote: > > > On Tue, May 11, 2021 at 10:31:39AM +0200, Zbigniew Kempczyński wrote: > > > > We have established previously we stop using relocations starting > > > > from gen12 platforms with Tigerlake as an exception. Unfortunately > > > > we need extend transition period and support relocations for two > > > > other igfx platforms - Rocketlake and Alderlake. > > > > > > > > Signed-off-by: Zbigniew Kempczyński > > > > Cc: Dave Airlie > > > > Cc: Daniel Vetter > > > > Cc: Jason Ekstrand > > > > > > So the annoying thing here is that now media-driver is fixed: > > > > > > https://github.com/intel/media-driver/commit/144020c37770083974bedf59902b70b8f444c799 > > > > > > Which means igt is really the only thing left. > > > > > > Dave, is this still ok for an acked exception, or is this now leaning > > > towards "just fix igt"? > > > > Oh that isn't great is it, I had thought it was the media-driver, > > keeping a big uAPI like this open just for the test code seems a bit > > silly. I get the tests are testing more than just relocs, but it's a > > pretty big interface to leave lying around if we can avoid it. > > So since we need to do the work anyway for DG1+ what about some interim > hack? Currently ADL still has the require_force_probe flag set. We could > re-enable relocations just for ADL, only while this flag is set. This > gives us a bunch of wiggle room, unblocks everything else (CI is a bit on > fire right now due to this and practially unuseable on ADL gem areay) and > we'll still make sure that when ADL is all done we wont expose relocations > just for igt. > > Thoughts? I can handle that as a compromise, though I'd not want to block ADL getting out of alpha over some IGT that needs porting. Dave. > -Daniel > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Add relocation exceptions for two other platforms
On Tue, Jun 1, 2021 at 9:19 AM Dave Airlie wrote: > On Thu, 27 May 2021 at 20:04, Daniel Vetter wrote: > > On Wed, May 26, 2021 at 10:35:49AM +1000, Dave Airlie wrote: > > > On Wed, 12 May 2021 at 03:05, Daniel Vetter wrote: > > > > On Tue, May 11, 2021 at 10:31:39AM +0200, Zbigniew Kempczyński wrote: > > > > > We have established previously we stop using relocations starting > > > > > from gen12 platforms with Tigerlake as an exception. Unfortunately > > > > > we need extend transition period and support relocations for two > > > > > other igfx platforms - Rocketlake and Alderlake. > > > > > > > > > > Signed-off-by: Zbigniew Kempczyński > > > > > Cc: Dave Airlie > > > > > Cc: Daniel Vetter > > > > > Cc: Jason Ekstrand > > > > > > > > So the annoying thing here is that now media-driver is fixed: > > > > > > > > https://github.com/intel/media-driver/commit/144020c37770083974bedf59902b70b8f444c799 > > > > > > > > Which means igt is really the only thing left. > > > > > > > > Dave, is this still ok for an acked exception, or is this now leaning > > > > towards "just fix igt"? > > > > > > Oh that isn't great is it, I had thought it was the media-driver, > > > keeping a big uAPI like this open just for the test code seems a bit > > > silly. I get the tests are testing more than just relocs, but it's a > > > pretty big interface to leave lying around if we can avoid it. > > > > So since we need to do the work anyway for DG1+ what about some interim > > hack? Currently ADL still has the require_force_probe flag set. We could > > re-enable relocations just for ADL, only while this flag is set. This > > gives us a bunch of wiggle room, unblocks everything else (CI is a bit on > > fire right now due to this and practially unuseable on ADL gem areay) and > > we'll still make sure that when ADL is all done we wont expose relocations > > just for igt. > > > > Thoughts? > > I can handle that as a compromise, though I'd not want to block ADL > getting out of alpha over some IGT that needs porting. Uh given that EHL/JSL are still in require_force_probe = true mode because of a random igt (and shipping since a while) ... I guess worst case if it's not sorted in a few months latest we can undo that again. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 01/15] drm/i915: Untangle the vma pages_mutex
Any sleeping dma_resv lock taken while the vma pages_mutex is held
will cause a lockdep splat.
Move the i915_gem_object_pin_pages() call out of the pages_mutex
critical section.
Signed-off-by: Thomas Hellström
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_vma.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index b319fd3f91cc..0f227f28b280 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -800,32 +800,37 @@ static bool try_qad_pin(struct i915_vma *vma, unsigned
int flags)
static int vma_get_pages(struct i915_vma *vma)
{
int err = 0;
+ bool pinned_pages = false;
if (atomic_add_unless(&vma->pages_count, 1, 0))
return 0;
+ if (vma->obj) {
+ err = i915_gem_object_pin_pages(vma->obj);
+ if (err)
+ return err;
+ pinned_pages = true;
+ }
+
/* Allocations ahoy! */
- if (mutex_lock_interruptible(&vma->pages_mutex))
- return -EINTR;
+ if (mutex_lock_interruptible(&vma->pages_mutex)) {
+ err = -EINTR;
+ goto unpin;
+ }
if (!atomic_read(&vma->pages_count)) {
- if (vma->obj) {
- err = i915_gem_object_pin_pages(vma->obj);
- if (err)
- goto unlock;
- }
-
err = vma->ops->set_pages(vma);
- if (err) {
- if (vma->obj)
- i915_gem_object_unpin_pages(vma->obj);
+ if (err)
goto unlock;
- }
+ pinned_pages = false;
}
atomic_inc(&vma->pages_count);
unlock:
mutex_unlock(&vma->pages_mutex);
+unpin:
+ if (pinned_pages)
+ __i915_gem_object_unpin_pages(vma->obj);
return err;
}
--
2.31.1
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[Intel-gfx] [PATCH v9 00/15] Move LMEM (VRAM) management over to TTM
This is an initial patch series to move discrete memory management over to TTM. It will be followed up shortly with adding more functionality. The buddy allocator is temporarily removed along with its selftests and It is replaced with the TTM range manager and some selftests are adjusted to account for introduced fragmentation. Work is ongoing to reintroduce the buddy allocator as a TTM resource manager. A new memcpy ttm move is introduced that uses kmap_local() functionality rather than vmap(). Among other things stated in the patch commit message it helps us deal with page-pased LMEM memory. It is generic enough to replace the ttm memcpy move with some additional work if so desired. On x86 it also enables prefetching reads from write-combined memory. Finally the old i915 gem object LMEM backend is replaced with a i915 gem object TTM backend and some additional i915 gem object ops are introduced to support the added functionality. Currently it is used only to support management and eviction of the LMEM region, but work is underway to extend the support to system memory. In this way we use TTM the way it was originally intended, having the GPU binding taken care of by driver code. Intention is to follow up with - System memory support - Pipelined accelerated moves / migration - Re-added buddy allocator in the TTM framework v2: - Add patches to move pagefaulting over to TTM - Break out TTM changes to separate patches - Address various review comments as detailed in the affected patches v3: - Drop TTM pagefaulting patches for now due changing approach due to a NAK. - Address feedback on TTM patches - Move the new TTM memcpy functionality into TTM. - Move fast WC memcpy to drm - Various fixes all over the place as shown in patch commit messages. v4: - Re-add TTM pagefaulting patches. - Addressed review feedback mainly from Matthew Auld - Fixed the mock ttm device code that was using an incorrect approach. v5: - Cleanups in the TTM pagefaulting patches. - Just add the WC memcpy to DRM without removing from i915 (Suggested by Daniel Vetter). - Various minor fixes as reported in patch log messages. v6: - Fix a merge conflict causing build error. v7: - Fix the WC memcpy compilation and perform a fallback memcpy in addition to warning in interrupt (Suggested by Christian König) - Renistate check for ttm_tt_is_populated() on swapout. v8: - Added a couple of acks and r-bs - pgoff_t -> u32 in interface of ttm_move_memcpy. - Fix missing export in !X86 WC memcpy. v9: - Fix a NULL pointer deref if bo->ttm == NULL Cc: Christian König Maarten Lankhorst (3): drm/i915: Disable mmap ioctl for gen12+ drm/vma: Add a driver_private member to vma_node. drm/i915: Use ttm mmap handling for ttm bo's. Thomas Hellström (12): drm/i915: Untangle the vma pages_mutex drm/i915: Don't free shared locks while shared drm/i915: Fix i915_sg_page_sizes to record dma segments rather than physical pages drm/i915/ttm Initialize the ttm device and memory managers drm/i915/ttm: Embed a ttm buffer object in the i915 gem object drm/ttm: Add a generic TTM memcpy move for page-based iomem drm: Add a prefetching memcpy_from_wc drm/ttm: Use drm_memcpy_from_wc for TTM bo moves drm/ttm: Document and optimize ttm_bo_pipeline_gutting() drm/ttm, drm/amdgpu: Allow the driver some control over swapping drm/i915/ttm: Introduce a TTM i915 gem object backend drm/i915/lmem: Verify checks for lmem residency Documentation/gpu/drm-mm.rst | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 + drivers/gpu/drm/drm_cache.c | 148 drivers/gpu/drm/drm_drv.c | 2 + drivers/gpu/drm/drm_gem.c | 9 - drivers/gpu/drm/i915/Kconfig | 1 + drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_create.c| 9 +- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 2 +- drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 71 +- drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 5 - drivers/gpu/drm/i915/gem/i915_gem_mman.c | 90 +- drivers/gpu/drm/i915/gem/i915_gem_object.c| 149 +++- drivers/gpu/drm/i915/gem/i915_gem_object.h| 19 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 52 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 6 +- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_region.c| 126 +-- drivers/gpu/drm/i915/gem/i915_gem_region.h| 4 - drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 10 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.h| 9 +- drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 647 ++ drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 48 ++ drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 2 +- .../drm/i915/gem/selftests/i915_gem_mman.c| 90 +- drivers/gpu/dr
[Intel-gfx] [PATCH v9 02/15] drm/i915: Don't free shared locks while shared
We are currently sharing the VM reservation locks across a number of
gem objects with page-table memory. Since TTM will individiualize the
reservation locks when freeing objects, including accessing the shared
locks, make sure that the shared locks are not freed until that is done.
For PPGTT we add an additional refcount, for GGTT we take additional
measures to make sure objects sharing the GGTT reservation lock are
freed at GGTT takedown
Signed-off-by: Thomas Hellström
Reviewed-by: Maarten Lankhorst
---
v2: Try harder to make sure objects sharing the GGTT reservation lock are
freed at GGTT takedown.
v3: Use a pointer to the vm to indicate that an object shares a reservation
object from that vm, rather than a pointer to the reservation object itself.
---
drivers/gpu/drm/i915/gem/i915_gem_object.c| 3 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 4 ++
drivers/gpu/drm/i915/gt/intel_ggtt.c | 19 ++--
drivers/gpu/drm/i915/gt/intel_gtt.c | 45 +++
drivers/gpu/drm/i915/gt/intel_gtt.h | 28 +++-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 5 +++
7 files changed, 93 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 28144410df86..2be6109d0093 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -252,6 +252,9 @@ static void __i915_gem_free_objects(struct drm_i915_private
*i915,
if (obj->mm.n_placements > 1)
kfree(obj->mm.placements);
+ if (obj->shares_resv_from)
+ i915_vm_resv_put(obj->shares_resv_from);
+
/* But keep the pointer alive for RCU-protected lookups */
call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
cond_resched();
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0727d0c76aa0..0415f99b6b95 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -149,6 +149,10 @@ struct drm_i915_gem_object {
* when i915_gem_ww_ctx_backoff() or i915_gem_ww_ctx_fini() are called.
*/
struct list_head obj_link;
+ /**
+* @shared_resv_from: The object shares the resv from this vm.
+*/
+ struct i915_address_space *shares_resv_from;
union {
struct rcu_head rcu;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 35069ca5d7de..10c23a749a95 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -746,7 +746,6 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
mutex_unlock(&ggtt->vm.mutex);
i915_address_space_fini(&ggtt->vm);
- dma_resv_fini(&ggtt->vm.resv);
arch_phys_wc_del(ggtt->mtrr);
@@ -768,6 +767,19 @@ void i915_ggtt_driver_release(struct drm_i915_private
*i915)
ggtt_cleanup_hw(ggtt);
}
+/**
+ * i915_ggtt_driver_late_release - Cleanup of GGTT that needs to be done after
+ * all free objects have been drained.
+ * @i915: i915 device
+ */
+void i915_ggtt_driver_late_release(struct drm_i915_private *i915)
+{
+ struct i915_ggtt *ggtt = &i915->ggtt;
+
+ GEM_WARN_ON(kref_read(&ggtt->vm.resv_ref) != 1);
+ dma_resv_fini(&ggtt->vm._resv);
+}
+
static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
{
snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
@@ -829,6 +841,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64
size)
return -ENOMEM;
}
+ kref_init(&ggtt->vm.resv_ref);
ret = setup_scratch_page(&ggtt->vm);
if (ret) {
drm_err(&i915->drm, "Scratch setup failed\n");
@@ -1135,7 +1148,7 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct
intel_gt *gt)
ggtt->vm.gt = gt;
ggtt->vm.i915 = i915;
ggtt->vm.dma = i915->drm.dev;
- dma_resv_init(&ggtt->vm.resv);
+ dma_resv_init(&ggtt->vm._resv);
if (INTEL_GEN(i915) <= 5)
ret = i915_gmch_probe(ggtt);
@@ -1144,7 +1157,7 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct
intel_gt *gt)
else
ret = gen8_gmch_probe(ggtt);
if (ret) {
- dma_resv_fini(&ggtt->vm.resv);
+ dma_resv_fini(&ggtt->vm._resv);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 9b98f9d9faa3..94849567143d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -22,8 +22,11 @@ struct drm_i915_gem_object *alloc_pt_lmem(struct
i915_address_space *vm, int sz)
* object underneath, with the idea that one object_lock() will lock
* t
[Intel-gfx] [PATCH v9 05/15] drm/i915/ttm: Embed a ttm buffer object in the i915 gem object
Embed a struct ttm_buffer_object into the i915 gem object, making sure
we alias the gem object part. It's a bit unfortunate that the
struct ttm_buffer_ojbect embeds a gem object since we otherwise could
make the TTM part private to the TTM backend, and use the usual
i915 gem object for the other backends.
To make this a bit more storage efficient for the other backends,
we'd have to use a pointer for the gem object which would require
a lot of changes in the driver. We postpone that for later.
Signed-off-by: Thomas Hellström
Acked-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 7 +++
drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 12 +++-
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 2be6109d0093..5706d471692d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -62,6 +62,13 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_object_ops *ops,
struct lock_class_key *key, unsigned flags)
{
+ /*
+* A gem object is embedded both in a struct ttm_buffer_object :/ and
+* in a drm_i915_gem_object. Make sure they are aliased.
+*/
+ BUILD_BUG_ON(offsetof(typeof(*obj), base) !=
+offsetof(typeof(*obj), __do_not_access.base));
+
spin_lock_init(&obj->vma.lock);
INIT_LIST_HEAD(&obj->vma.list);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index f5b46d11e6e6..d047ea126029 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -10,6 +10,7 @@
#include
#include
+#include
#include
#include "i915_active.h"
@@ -99,7 +100,16 @@ struct i915_gem_object_page_iter {
};
struct drm_i915_gem_object {
- struct drm_gem_object base;
+ /*
+* We might have reason to revisit the below since it wastes
+* a lot of space for non-ttm gem objects.
+* In any case, always use the accessors for the ttm_buffer_object
+* when accessing it.
+*/
+ union {
+ struct drm_gem_object base;
+ struct ttm_buffer_object __do_not_access;
+ };
const struct drm_i915_gem_object_ops *ops;
--
2.31.1
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[Intel-gfx] [PATCH v9 03/15] drm/i915: Fix i915_sg_page_sizes to record dma segments rather than physical pages
All users of this function actually want the dma segment sizes, but that's
not what's calculated. Fix that and rename the function to
i915_sg_dma_sizes to reflect what's calculated.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_phys.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 2 +-
drivers/gpu/drm/i915/i915_scatterlist.h | 16
4 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index ccede73c6465..616c3a2f1baf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -209,7 +209,7 @@ static int i915_gem_object_get_pages_dmabuf(struct
drm_i915_gem_object *obj)
if (IS_ERR(pages))
return PTR_ERR(pages);
- sg_page_sizes = i915_sg_page_sizes(pages->sgl);
+ sg_page_sizes = i915_sg_dma_sizes(pages->sgl);
__i915_gem_object_set_pages(obj, pages, sg_page_sizes);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index 51a05e62875d..be72ad0634ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -207,7 +207,7 @@ static int i915_gem_object_shmem_to_phys(struct
drm_i915_gem_object *obj)
err_xfer:
if (!IS_ERR_OR_NULL(pages)) {
- unsigned int sg_page_sizes = i915_sg_page_sizes(pages->sgl);
+ unsigned int sg_page_sizes = i915_sg_dma_sizes(pages->sgl);
__i915_gem_object_set_pages(obj, pages, sg_page_sizes);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index a657b99ec760..602f0ed983ec 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -173,7 +173,7 @@ static int i915_gem_userptr_get_pages(struct
drm_i915_gem_object *obj)
goto err;
}
- sg_page_sizes = i915_sg_page_sizes(st->sgl);
+ sg_page_sizes = i915_sg_dma_sizes(st->sgl);
__i915_gem_object_set_pages(obj, st, sg_page_sizes);
diff --git a/drivers/gpu/drm/i915/i915_scatterlist.h
b/drivers/gpu/drm/i915/i915_scatterlist.h
index 9cb26a224034..b96baad66a3a 100644
--- a/drivers/gpu/drm/i915/i915_scatterlist.h
+++ b/drivers/gpu/drm/i915/i915_scatterlist.h
@@ -101,15 +101,23 @@ static inline struct scatterlist *__sg_next(struct
scatterlist *sg)
(((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
(__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
-static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
+/**
+ * i915_sg_dma_sizes - Record the dma segment sizes of a scatterlist
+ * @sg: The scatterlist
+ *
+ * Return: An unsigned int with segment sizes logically or'ed together.
+ * A caller can use this information to determine what hardware page table
+ * entry sizes can be used to map the memory represented by the scatterlist.
+ */
+static inline unsigned int i915_sg_dma_sizes(struct scatterlist *sg)
{
unsigned int page_sizes;
page_sizes = 0;
- while (sg) {
+ while (sg && sg_dma_len(sg)) {
GEM_BUG_ON(sg->offset);
- GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
- page_sizes |= sg->length;
+ GEM_BUG_ON(!IS_ALIGNED(sg_dma_len(sg), PAGE_SIZE));
+ page_sizes |= sg_dma_len(sg);
sg = __sg_next(sg);
}
--
2.31.1
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[Intel-gfx] [PATCH v9 04/15] drm/i915/ttm Initialize the ttm device and memory managers
Temporarily remove the buddy allocator and related selftests
and hook up the TTM range manager for i915 regions.
Also modify the mock region selftests somewhat to account for a
fragmenting manager.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld #v2
---
v2:
- Fix an error unwind in lmem_get_pages() (Reported by Matthew Auld)
- Break out and modify usage of i915_sg_dma_sizes() (Reported by Mattew Auld)
- Break out TTM changes to a separate patch (Reported by Christian König)
v3:
- Fix the same error unwind in mock_region_get_pages()
(Reported by Matthew Auld)
- Don't rely on new TTM functionality, but create a mock TTM device,
(Reported by Christian König)
v4:
- Use mock_gem_device rather than creating a separate ttm_device per
region.
---
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 59 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 6 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c| 120 ---
drivers/gpu/drm/i915/gem/i915_gem_region.h| 4 -
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 10 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.h| 9 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 -
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 27 +-
drivers/gpu/drm/i915/i915_buddy.c | 435 --
drivers/gpu/drm/i915/i915_buddy.h | 131 ---
drivers/gpu/drm/i915/i915_drv.c | 8 +
drivers/gpu/drm/i915/i915_drv.h | 8 +-
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_globals.c | 1 -
drivers/gpu/drm/i915/i915_globals.h | 1 -
drivers/gpu/drm/i915/i915_scatterlist.c | 70 ++
drivers/gpu/drm/i915/i915_scatterlist.h | 4 +
drivers/gpu/drm/i915/intel_memory_region.c| 180 ++--
drivers/gpu/drm/i915/intel_memory_region.h| 44 +-
drivers/gpu/drm/i915/intel_region_ttm.c | 220 +
drivers/gpu/drm/i915/intel_region_ttm.h | 32 +
drivers/gpu/drm/i915/selftests/i915_buddy.c | 789 --
.../drm/i915/selftests/i915_mock_selftests.h | 1 -
.../drm/i915/selftests/intel_memory_region.c | 133 +--
.../gpu/drm/i915/selftests/mock_gem_device.c | 10 +
drivers/gpu/drm/i915/selftests/mock_region.c | 70 +-
30 files changed, 631 insertions(+), 1754 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/i915_buddy.c
delete mode 100644 drivers/gpu/drm/i915/i915_buddy.h
create mode 100644 drivers/gpu/drm/i915/intel_region_ttm.c
create mode 100644 drivers/gpu/drm/i915/intel_region_ttm.h
delete mode 100644 drivers/gpu/drm/i915/selftests/i915_buddy.c
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 93f4d059fc89..61ff5c178714 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -27,6 +27,7 @@ config DRM_I915
select SND_HDA_I915 if SND_HDA_CORE
select CEC_CORE if CEC_NOTIFIER
select VMAP_PFN
+ select DRM_TTM
help
Choose this option if you have a system that has "Intel Graphics
Media Accelerator" or "HD Graphics" integrated graphics,
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6947495bf34b..4f22cac1c49b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -50,6 +50,7 @@ i915-y += i915_drv.o \
intel_memory_region.o \
intel_pch.o \
intel_pm.o \
+ intel_region_ttm.o \
intel_runtime_pm.o \
intel_sideband.o \
intel_step.o \
@@ -160,7 +161,6 @@ gem-y += \
i915-y += \
$(gem-y) \
i915_active.o \
- i915_buddy.o \
i915_cmd_parser.o \
i915_gem_evict.o \
i915_gem_gtt.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index f44bdd08f7cb..3b4aa28a076d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -4,16 +4,71 @@
*/
#include "intel_memory_region.h"
+#include "intel_region_ttm.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
+static void lmem_put_pages(struct drm_i915_gem_object *obj,
+ struct sg_table *pages)
+{
+ intel_region_ttm_node_free(obj->mm.region, obj->mm.st_mm_node);
+ obj->mm.dirty = false;
+ sg_free_table(pages);
+ kfree(pages);
+}
+
+static int lmem_get_pages(struct drm_i915_gem_object *obj)
+{
+ unsigned int flags;
+ struct sg_table *pages;
+
+ flags = I915_ALLOC_MIN_PAGE_SIZE;
+ if (obj->flags & I915_BO_ALLOC_CONTIGUOUS)
+ flags |= I915_ALLOC_CONTIGUOUS;
+
+ obj->mm.st_mm_node = intel_region_ttm_node_alloc(obj->mm.region,
+
[Intel-gfx] [PATCH v9 06/15] drm/ttm: Add a generic TTM memcpy move for page-based iomem
The internal ttm_bo_util memcpy uses ioremap functionality, and while it
probably might be possible to use it for copying in- and out of
sglist represented io memory, using io_mem_reserve() / io_mem_free()
callbacks, that would cause problems with fault().
Instead, implement a method mapping page-by-page using kmap_local()
semantics. As an additional benefit we then avoid the occasional global
TLB flushes of ioremap() and consuming ioremap space, elimination of a
critical point of failure and with a slight change of semantics we could
also push the memcpy out async for testing and async driver development
purposes.
A special linear iomem iterator is introduced internally to mimic the
old ioremap behaviour for code-paths that can't immediately be ported
over. This adds to the code size and should be considered a temporary
solution.
Looking at the code we have a lot of checks for iomap tagged pointers.
Ideally we should extend the core memremap functions to also accept
uncached memory and kmap_local functionality. Then we could strip a
lot of code.
Cc: Christian König
Signed-off-by: Thomas Hellström
Reviewed-by: Christian König
---
v3:
- Split up in various TTM files and addressed review comments by
Christian König. Tested and fixed legacy iomap memcpy path on i915.
v4:
- Fix an uninitialized variable
Reported by: kernel test robot
Reported by: Dan Carpenter
- Minor change to the ttm_move_memcpy() interface.
- Gracefully handle lack of memremap() support on memcpy
(Reported by Matthew Auld)
- Minor style fix (Reported by Matthew Auld)
v8:
- Change num_pages from pgoff_t to uint32_t (Suggested by Christian König)
v9:
- Fix a NULL pointer deref in ttm_kmap_iter_tt_init if tt is NULL.
---
drivers/gpu/drm/ttm/ttm_bo_util.c | 280 ++---
drivers/gpu/drm/ttm/ttm_module.c | 35
drivers/gpu/drm/ttm/ttm_resource.c | 193
drivers/gpu/drm/ttm/ttm_tt.c | 45 +
include/drm/ttm/ttm_bo_driver.h| 28 +++
include/drm/ttm/ttm_caching.h | 2 +
include/drm/ttm/ttm_kmap_iter.h| 61 +++
include/drm/ttm/ttm_resource.h | 61 +++
include/drm/ttm/ttm_tt.h | 16 ++
9 files changed, 539 insertions(+), 182 deletions(-)
create mode 100644 include/drm/ttm/ttm_kmap_iter.h
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index ae8b61460724..a800998a12b0 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -72,190 +72,126 @@ void ttm_mem_io_free(struct ttm_device *bdev,
mem->bus.addr = NULL;
}
-static int ttm_resource_ioremap(struct ttm_device *bdev,
- struct ttm_resource *mem,
- void **virtual)
+/**
+ * ttm_move_memcpy - Helper to perform a memcpy ttm move operation.
+ * @bo: The struct ttm_buffer_object.
+ * @new_mem: The struct ttm_resource we're moving to (copy destination).
+ * @new_iter: A struct ttm_kmap_iter representing the destination resource.
+ * @src_iter: A struct ttm_kmap_iter representing the source resource.
+ *
+ * This function is intended to be able to move out async under a
+ * dma-fence if desired.
+ */
+void ttm_move_memcpy(struct ttm_buffer_object *bo,
+u32 num_pages,
+struct ttm_kmap_iter *dst_iter,
+struct ttm_kmap_iter *src_iter)
{
- int ret;
- void *addr;
-
- *virtual = NULL;
- ret = ttm_mem_io_reserve(bdev, mem);
- if (ret || !mem->bus.is_iomem)
- return ret;
+ const struct ttm_kmap_iter_ops *dst_ops = dst_iter->ops;
+ const struct ttm_kmap_iter_ops *src_ops = src_iter->ops;
+ struct ttm_tt *ttm = bo->ttm;
+ struct dma_buf_map src_map, dst_map;
+ pgoff_t i;
- if (mem->bus.addr) {
- addr = mem->bus.addr;
- } else {
- size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
+ /* Single TTM move. NOP */
+ if (dst_ops->maps_tt && src_ops->maps_tt)
+ return;
- if (mem->bus.caching == ttm_write_combined)
- addr = ioremap_wc(mem->bus.offset, bus_size);
-#ifdef CONFIG_X86
- else if (mem->bus.caching == ttm_cached)
- addr = ioremap_cache(mem->bus.offset, bus_size);
-#endif
- else
- addr = ioremap(mem->bus.offset, bus_size);
- if (!addr) {
- ttm_mem_io_free(bdev, mem);
- return -ENOMEM;
+ /* Don't move nonexistent data. Clear destination instead. */
+ if (src_ops->maps_tt && (!ttm || !ttm_tt_is_populated(ttm))) {
+ if (ttm && !(ttm->page_flags & TTM_PAGE_FLAG_ZERO_ALLOC))
+ return;
+
+ for (i = 0; i < num_pages; ++i) {
+ dst_ops->map_local(dst_iter, &dst_map, i);
+ if (dst_map.is_iomem)
+
[Intel-gfx] [PATCH v9 09/15] drm/ttm: Document and optimize ttm_bo_pipeline_gutting()
If the bo is idle when calling ttm_bo_pipeline_gutting(), we unnecessarily
create a ghost object and push it out to delayed destroy.
Fix this by adding a path for idle, and document the function.
Also avoid having the bo end up in a bad state vulnerable to user-space
triggered kernel BUGs if the call to ttm_tt_create() fails.
Finally reuse ttm_bo_pipeline_gutting() in ttm_bo_evict().
Cc: Christian König
Signed-off-by: Thomas Hellström
Reviewed-by: Christian König
---
v4:
- Clarify why we mark bo for clearing after ttm_bo_pipeline_gutting()
(Reported by Matthew Auld)
v5:
- Make ttm_tt_mark_for_clear() inline (Suggested by Christian König)
---
drivers/gpu/drm/ttm/ttm_bo.c | 20 +--
drivers/gpu/drm/ttm/ttm_bo_util.c | 55 ---
include/drm/ttm/ttm_tt.h | 13
3 files changed, 74 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 51a94fd63bd7..be0406466460 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -501,10 +501,15 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo,
bdev->funcs->evict_flags(bo, &placement);
if (!placement.num_placement && !placement.num_busy_placement) {
- ttm_bo_wait(bo, false, false);
+ ret = ttm_bo_wait(bo, true, false);
+ if (ret)
+ return ret;
- ttm_bo_cleanup_memtype_use(bo);
- return ttm_tt_create(bo, false);
+ /*
+* Since we've already synced, this frees backing store
+* immediately.
+*/
+ return ttm_bo_pipeline_gutting(bo);
}
ret = ttm_bo_mem_space(bo, &placement, &evict_mem, ctx);
@@ -976,13 +981,8 @@ int ttm_bo_validate(struct ttm_buffer_object *bo,
/*
* Remove the backing store if no placement is given.
*/
- if (!placement->num_placement && !placement->num_busy_placement) {
- ret = ttm_bo_pipeline_gutting(bo);
- if (ret)
- return ret;
-
- return ttm_tt_create(bo, false);
- }
+ if (!placement->num_placement && !placement->num_busy_placement)
+ return ttm_bo_pipeline_gutting(bo);
/*
* Check whether we need to move buffer.
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 30bafac416a5..d0db63a7f00c 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -565,26 +565,73 @@ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object
*bo,
}
EXPORT_SYMBOL(ttm_bo_move_accel_cleanup);
+/**
+ * ttm_bo_pipeline_gutting - purge the contents of a bo
+ * @bo: The buffer object
+ *
+ * Purge the contents of a bo, async if the bo is not idle.
+ * After a successful call, the bo is left unpopulated in
+ * system placement. The function may wait uninterruptible
+ * for idle on OOM.
+ *
+ * Return: 0 if successful, negative error code on failure.
+ */
int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo)
{
static const struct ttm_place sys_mem = { .mem_type = TTM_PL_SYSTEM };
struct ttm_buffer_object *ghost;
+ struct ttm_tt *ttm;
int ret;
- ret = ttm_buffer_object_transfer(bo, &ghost);
+ /* If already idle, no need for ghost object dance. */
+ ret = ttm_bo_wait(bo, false, true);
+ if (ret != -EBUSY) {
+ if (!bo->ttm) {
+ /* See comment below about clearing. */
+ ret = ttm_tt_create(bo, true);
+ if (ret)
+ return ret;
+ } else {
+ ttm_tt_unpopulate(bo->bdev, bo->ttm);
+ if (bo->type == ttm_bo_type_device)
+ ttm_tt_mark_for_clear(bo->ttm);
+ }
+ ttm_resource_free(bo, &bo->mem);
+ ttm_resource_alloc(bo, &sys_mem, &bo->mem);
+
+ return 0;
+ }
+
+ /*
+* We need an unpopulated ttm_tt after giving our current one,
+* if any, to the ghost object. And we can't afford to fail
+* creating one *after* the operation. If the bo subsequently gets
+* resurrected, make sure it's cleared (if ttm_bo_type_device)
+* to avoid leaking sensitive information to user-space.
+*/
+
+ ttm = bo->ttm;
+ bo->ttm = NULL;
+ ret = ttm_tt_create(bo, true);
+ swap(bo->ttm, ttm);
if (ret)
return ret;
+ ret = ttm_buffer_object_transfer(bo, &ghost);
+ if (ret) {
+ ttm_tt_destroy(bo->bdev, ttm);
+ return ret;
+ }
+
ret = dma_resv_copy_fences(&ghost->base._resv, bo->base.resv);
/* Last resort, wait for the BO to be idle when we are OOM */
if (ret)
ttm_bo_wait(bo,
[Intel-gfx] [PATCH v9 08/15] drm/ttm: Use drm_memcpy_from_wc for TTM bo moves
Use fast wc memcpy for reading out of wc memory for TTM bo moves.
Cc: Dave Airlie
Cc: Christian König
Cc: Daniel Vetter
Signed-off-by: Thomas Hellström
Reviewed-by: Christian König #v4
--
v4:
- Clarify when we try drm_memcpy_from_wc_dbm (Reported by Matthew Auld)
- Be paranoid about when drm_memcpy_from_wc_dbm may fail (Reported by
Matthew Auld)
v5:
- Rebase on change to drm_memcpy_from_wc (Suggested by Daniel Vetter)
---
drivers/gpu/drm/ttm/ttm_bo_util.c | 19 +++
1 file changed, 3 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index a800998a12b0..30bafac416a5 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -31,6 +31,7 @@
#include
#include
+#include
#include
#include
#include
@@ -118,22 +119,8 @@ void ttm_move_memcpy(struct ttm_buffer_object *bo,
dst_ops->map_local(dst_iter, &dst_map, i);
src_ops->map_local(src_iter, &src_map, i);
- if (!src_map.is_iomem && !dst_map.is_iomem) {
- memcpy(dst_map.vaddr, src_map.vaddr, PAGE_SIZE);
- } else if (!src_map.is_iomem) {
- dma_buf_map_memcpy_to(&dst_map, src_map.vaddr,
- PAGE_SIZE);
- } else if (!dst_map.is_iomem) {
- memcpy_fromio(dst_map.vaddr, src_map.vaddr_iomem,
- PAGE_SIZE);
- } else {
- int j;
- u32 __iomem *src = src_map.vaddr_iomem;
- u32 __iomem *dst = dst_map.vaddr_iomem;
-
- for (j = 0; j < (PAGE_SIZE / sizeof(u32)); ++j)
- iowrite32(ioread32(src++), dst++);
- }
+ drm_memcpy_from_wc(&dst_map, &src_map, PAGE_SIZE);
+
if (src_ops->unmap_local)
src_ops->unmap_local(src_iter, &src_map);
if (dst_ops->unmap_local)
--
2.31.1
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[Intel-gfx] [PATCH v9 07/15] drm: Add a prefetching memcpy_from_wc
Reading out of write-combining mapped memory is typically very slow
since the CPU doesn't prefetch. However some archs have special
instructions to do this.
So add a best-effort memcpy_from_wc taking dma-buf-map pointer
arguments that attempts to use a fast prefetching memcpy and
otherwise falls back to ordinary memcopies, taking the iomem tagging
into account.
The code is largely copied from i915_memcpy_from_wc.
Cc: Daniel Vetter
Cc: Christian König
Suggested-by: Daniel Vetter
Signed-off-by: Thomas Hellström
Acked-by: Christian König
Acked-by: Daniel Vetter
---
v7:
- Perform a memcpy even if warning with in_interrupt(). Suggested by
Christian König.
- Fix compilation failure on !X86 (Reported by kernel test robot
l...@intel.com)
v8:
- Skip kerneldoc for drm_memcpy_init_early()
- Export drm_memcpy_from_wc() also for non-x86.
---
Documentation/gpu/drm-mm.rst | 2 +-
drivers/gpu/drm/drm_cache.c | 148 +++
drivers/gpu/drm/drm_drv.c| 2 +
include/drm/drm_cache.h | 7 ++
4 files changed, 158 insertions(+), 1 deletion(-)
diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst
index 21be6deadc12..c66058c5bce7 100644
--- a/Documentation/gpu/drm-mm.rst
+++ b/Documentation/gpu/drm-mm.rst
@@ -469,7 +469,7 @@ DRM MM Range Allocator Function References
.. kernel-doc:: drivers/gpu/drm/drm_mm.c
:export:
-DRM Cache Handling
+DRM Cache Handling and Fast WC memcpy()
==
.. kernel-doc:: drivers/gpu/drm/drm_cache.c
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 79a50ef1250f..546599f19a93 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -28,6 +28,7 @@
* Authors: Thomas Hellström
*/
+#include
#include
#include
#include
@@ -35,6 +36,9 @@
#include
+/* A small bounce buffer that fits on the stack. */
+#define MEMCPY_BOUNCE_SIZE 128
+
#if defined(CONFIG_X86)
#include
@@ -209,3 +213,147 @@ bool drm_need_swiotlb(int dma_bits)
return max_iomem > ((u64)1 << dma_bits);
}
EXPORT_SYMBOL(drm_need_swiotlb);
+
+static void memcpy_fallback(struct dma_buf_map *dst,
+ const struct dma_buf_map *src,
+ unsigned long len)
+{
+ if (!dst->is_iomem && !src->is_iomem) {
+ memcpy(dst->vaddr, src->vaddr, len);
+ } else if (!src->is_iomem) {
+ dma_buf_map_memcpy_to(dst, src->vaddr, len);
+ } else if (!dst->is_iomem) {
+ memcpy_fromio(dst->vaddr, src->vaddr_iomem, len);
+ } else {
+ /*
+* Bounce size is not performance tuned, but using a
+* bounce buffer like this is significantly faster than
+* resorting to ioreadxx() + iowritexx().
+*/
+ char bounce[MEMCPY_BOUNCE_SIZE];
+ void __iomem *_src = src->vaddr_iomem;
+ void __iomem *_dst = dst->vaddr_iomem;
+
+ while (len >= MEMCPY_BOUNCE_SIZE) {
+ memcpy_fromio(bounce, _src, MEMCPY_BOUNCE_SIZE);
+ memcpy_toio(_dst, bounce, MEMCPY_BOUNCE_SIZE);
+ _src += MEMCPY_BOUNCE_SIZE;
+ _dst += MEMCPY_BOUNCE_SIZE;
+ len -= MEMCPY_BOUNCE_SIZE;
+ }
+ if (len) {
+ memcpy_fromio(bounce, _src, MEMCPY_BOUNCE_SIZE);
+ memcpy_toio(_dst, bounce, MEMCPY_BOUNCE_SIZE);
+ }
+ }
+}
+
+#ifdef CONFIG_X86
+
+static DEFINE_STATIC_KEY_FALSE(has_movntdqa);
+
+static void __memcpy_ntdqa(void *dst, const void *src, unsigned long len)
+{
+ kernel_fpu_begin();
+
+ while (len >= 4) {
+ asm("movntdqa (%0), %%xmm0\n"
+ "movntdqa 16(%0), %%xmm1\n"
+ "movntdqa 32(%0), %%xmm2\n"
+ "movntdqa 48(%0), %%xmm3\n"
+ "movaps %%xmm0, (%1)\n"
+ "movaps %%xmm1, 16(%1)\n"
+ "movaps %%xmm2, 32(%1)\n"
+ "movaps %%xmm3, 48(%1)\n"
+ :: "r" (src), "r" (dst) : "memory");
+ src += 64;
+ dst += 64;
+ len -= 4;
+ }
+ while (len--) {
+ asm("movntdqa (%0), %%xmm0\n"
+ "movaps %%xmm0, (%1)\n"
+ :: "r" (src), "r" (dst) : "memory");
+ src += 16;
+ dst += 16;
+ }
+
+ kernel_fpu_end();
+}
+
+/*
+ * __drm_memcpy_from_wc copies @len bytes from @src to @dst using
+ * non-temporal instructions where available. Note that all arguments
+ * (@src, @dst) must be aligned to 16 bytes and @len must be a multiple
+ * of 16.
+ */
+static void __drm_memcpy_from_wc(void *dst, const void *src, unsigned long len)
+{
+ if (unlikely(((unsigned long)dst | (unsigned long)src | len) & 15))
+ memcpy(dst, src, len);
+ els
[Intel-gfx] [PATCH v9 10/15] drm/ttm, drm/amdgpu: Allow the driver some control over swapping
We are calling the eviction_valuable driver callback at eviction time to
determine whether we actually can evict a buffer object.
The upcoming i915 TTM backend needs the same functionality for swapout,
and that might actually be beneficial to other drivers as well.
Add an eviction_valuable call also in the swapout path. Try to keep the
current behaviour for all drivers by returning true if the buffer object
is already in the TTM_PL_SYSTEM placement. We change behaviour for the
case where a buffer object is in a TT backed placement when swapped out,
in which case the drivers normal eviction_valuable path is run.
Reviewed-by: Maarten Lankhorst
Cc: Christian König
Signed-off-by: Thomas Hellström
Acked-by: Christian König
---
v3:
- Don't export ttm_tt_unpopulate
- Fix confusion reading the locked pointer instead of the value
pointed to in ttm_bo_evict_swapout_allowable (Reported by
Maarten Lankhorst)
v5:
- Use memset() rather than = {} (Suggested by Christian König)
- Remove check for ttm_tt_is_populated in the swapout code in the hope
it will be fixed elsewhere (Suggested by Christian König)
v7:
- Re-add the check for ttm_tt_is_populated in the swapout code.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 +++
drivers/gpu/drm/ttm/ttm_bo.c| 46 -
2 files changed, 34 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 80437b6ba5f3..5116065748a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1328,6 +1328,10 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct
ttm_buffer_object *bo,
struct dma_fence *f;
int i;
+ /* Swapout? */
+ if (bo->mem.mem_type == TTM_PL_SYSTEM)
+ return true;
+
if (bo->type == ttm_bo_type_kernel &&
!amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
return false;
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index be0406466460..98c41bf6a07d 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -536,6 +536,10 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo,
bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
const struct ttm_place *place)
{
+ dma_resv_assert_held(bo->base.resv);
+ if (bo->mem.mem_type == TTM_PL_SYSTEM)
+ return true;
+
/* Don't evict this BO if it's outside of the
* requested placement range
*/
@@ -558,7 +562,9 @@ EXPORT_SYMBOL(ttm_bo_eviction_valuable);
* b. Otherwise, trylock it.
*/
static bool ttm_bo_evict_swapout_allowable(struct ttm_buffer_object *bo,
- struct ttm_operation_ctx *ctx, bool *locked, bool *busy)
+ struct ttm_operation_ctx *ctx,
+ const struct ttm_place *place,
+ bool *locked, bool *busy)
{
bool ret = false;
@@ -576,6 +582,14 @@ static bool ttm_bo_evict_swapout_allowable(struct
ttm_buffer_object *bo,
*busy = !ret;
}
+ if (ret && place && !bo->bdev->funcs->eviction_valuable(bo, place)) {
+ ret = false;
+ if (*locked) {
+ dma_resv_unlock(bo->base.resv);
+ *locked = false;
+ }
+ }
+
return ret;
}
@@ -630,20 +644,14 @@ int ttm_mem_evict_first(struct ttm_device *bdev,
list_for_each_entry(bo, &man->lru[i], lru) {
bool busy;
- if (!ttm_bo_evict_swapout_allowable(bo, ctx, &locked,
- &busy)) {
+ if (!ttm_bo_evict_swapout_allowable(bo, ctx, place,
+ &locked, &busy)) {
if (busy && !busy_bo && ticket !=
dma_resv_locking_ctx(bo->base.resv))
busy_bo = bo;
continue;
}
- if (place && !bdev->funcs->eviction_valuable(bo,
- place)) {
- if (locked)
- dma_resv_unlock(bo->base.resv);
- continue;
- }
if (!ttm_bo_get_unless_zero(bo)) {
if (locked)
dma_resv_unlock(bo->base.resv);
@@ -1140,10 +1148,19 @@ EXPORT_SYMBOL(ttm_bo_wait);
int ttm_bo_swapout(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx,
gfp_t gfp_flags)
{
+ struct ttm_place place;
bool locked;
int re
[Intel-gfx] [PATCH v9 11/15] drm/i915/ttm: Introduce a TTM i915 gem object backend
Most logical place to introduce TTM buffer objects is as an i915
gem object backend. We need to add some ops to account for added
functionality like delayed delete and LRU list manipulation.
Initially we support only LMEM and SYSTEM memory, but SYSTEM
(which in this case means evicted LMEM objects) is not
visible to i915 GEM yet. The plan is to move the i915 gem system region
over to the TTM system memory type in upcoming patches.
We set up GPU bindings directly both from LMEM and from the system region,
as there is no need to use the legacy TTM_TT memory type. We reserve
that for future porting of GGTT bindings to TTM.
Remove the old lmem backend.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
v2:
- Break out needed TTM functionality to a separate patch (Reported by
Christian König).
- Fix an unhandled error (Reported by Matthew Auld and Maarten Lankhorst)
- Remove a stray leftover sg_table allocation (Reported by Matthew Auld)
- Use ttm_tt_unpopulate() rather than ttm_tt_destroy() in the purge path
as some TTM functionality relies on having a ttm_tt present for !is_iomem.
v3:
- Use ttm_bo_type_device for userspace visible objects so that TTM can
allocate an address space offset for mmap'ing.
- Fix up the destruction path (Reported by Matthew Auld)
- Use ttm_bo_validate() for purging (Reported by Christian König)
- Create ttm_tts write-combined as they are currently for eviction only and
we want to maintain consistent write-combined caching for bos that are
not in system only. (Suggested by Daniel Vetter)
- Make struct ttm_placements static.
- Add the ttm device funcs/ops to i915_gem_ttm.h for the region code.
- Rename new->dst and old->src. Check for swapin in the move callback.
v4:
- Adapt to small interface change in ttm_move_memcpy.
- Use a function to pull out the ttm driver from the backend.
v6:
- Remove the ttm device verify_access assignment. The member is gone
upstream.
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_create.c| 9 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 84 ---
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 5 -
drivers/gpu/drm/i915/gem/i915_gem_object.c| 125 ++--
drivers/gpu/drm/i915/gem/i915_gem_object.h| 9 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 27 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c| 6 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 540 ++
drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 48 ++
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 3 +-
drivers/gpu/drm/i915/i915_gem.c | 5 +-
drivers/gpu/drm/i915/intel_memory_region.c| 1 -
drivers/gpu/drm/i915/intel_memory_region.h| 1 -
drivers/gpu/drm/i915/intel_region_ttm.c | 8 +-
drivers/gpu/drm/i915/intel_region_ttm.h | 11 +-
16 files changed, 730 insertions(+), 153 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4f22cac1c49b..f57dfc74d6ce 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -155,6 +155,7 @@ gem-y += \
gem/i915_gem_stolen.o \
gem/i915_gem_throttle.o \
gem/i915_gem_tiling.o \
+ gem/i915_gem_ttm.o \
gem/i915_gem_userptr.o \
gem/i915_gem_wait.o \
gem/i915_gemfs.o
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 548ddf39d853..93bf63bbaff1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -85,13 +85,10 @@ i915_gem_setup(struct drm_i915_gem_object *obj, u64 size)
return -E2BIG;
/*
-* For now resort to CPU based clearing for device local-memory, in the
-* near future this will use the blitter engine for accelerated, GPU
-* based clearing.
+* I915_BO_ALLOC_USER will make sure the object is cleared before
+* any user access.
*/
- flags = 0;
- if (mr->type == INTEL_MEMORY_LOCAL)
- flags = I915_BO_ALLOC_CPU_CLEAR;
+ flags = I915_BO_ALLOC_USER;
ret = mr->ops->init_object(mr, obj, size, flags);
if (ret)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 3b4aa28a076d..2b8cd15de1d9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -4,74 +4,10 @@
*/
#include "intel_memory_region.h"
-#include "intel_region_ttm.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
-static void lmem_put_pages(struct drm_i915_gem_object *obj,
- struct sg_table *pages)
-{
- intel_region_ttm_node_free(obj->mm.region, obj->mm.st_mm_node);
- obj->mm.dirty = false;
- sg_free_
[Intel-gfx] [PATCH v9 12/15] drm/i915/lmem: Verify checks for lmem residency
Since objects can be migrated or evicted when not pinned or locked,
update the checks for lmem residency or future residency so that
the value returned is not immediately stale.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
v2: Simplify i915_gem_object_migratable() (Reported by Mattew Auld)
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 42 +++-
drivers/gpu/drm/i915/gem/i915_gem_object.c | 18 +
drivers/gpu/drm/i915/gem/i915_gem_object.h | 4 ++
4 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index caf0414e0b50..f947295d7e53 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11756,7 +11756,7 @@ intel_user_framebuffer_create(struct drm_device *dev,
/* object is backed with LMEM for discrete */
i915 = to_i915(obj->base.dev);
- if (HAS_LMEM(i915) && !i915_gem_object_is_lmem(obj)) {
+ if (HAS_LMEM(i915) && !i915_gem_object_validates_to_lmem(obj)) {
/* object is "remote", not in local memory */
i915_gem_object_put(obj);
return ERR_PTR(-EREMOTE);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 2b8cd15de1d9..d539dffa1554 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -23,10 +23,50 @@ i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
return io_mapping_map_wc(&obj->mm.region->iomap, offset, size);
}
+/**
+ * i915_gem_object_validates_to_lmem - Whether the object is resident in
+ * lmem when pages are present.
+ * @obj: The object to check.
+ *
+ * Migratable objects residency may change from under us if the object is
+ * not pinned or locked. This function is intended to be used to check whether
+ * the object can only reside in lmem when pages are present.
+ *
+ * Return: Whether the object is always resident in lmem when pages are
+ * present.
+ */
+bool i915_gem_object_validates_to_lmem(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *mr = READ_ONCE(obj->mm.region);
+
+ return !i915_gem_object_migratable(obj) &&
+ mr && (mr->type == INTEL_MEMORY_LOCAL ||
+ mr->type == INTEL_MEMORY_STOLEN_LOCAL);
+}
+
+/**
+ * i915_gem_object_is_lmem - Whether the object is resident in
+ * lmem
+ * @obj: The object to check.
+ *
+ * Even if an object is allowed to migrate and change memory region,
+ * this function checks whether it will always be present in lmem when
+ * valid *or* if that's not the case, whether it's currently resident in lmem.
+ * For migratable and evictable objects, the latter only makes sense when
+ * the object is locked.
+ *
+ * Return: Whether the object migratable but resident in lmem, or not
+ * migratable and will be present in lmem when valid.
+ */
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
{
- struct intel_memory_region *mr = obj->mm.region;
+ struct intel_memory_region *mr = READ_ONCE(obj->mm.region);
+#ifdef CONFIG_LOCKDEP
+ if (i915_gem_object_migratable(obj) &&
+ i915_gem_object_evictable(obj))
+ assert_object_held(obj);
+#endif
return mr && (mr->type == INTEL_MEMORY_LOCAL ||
mr->type == INTEL_MEMORY_STOLEN_LOCAL);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 16eac5ea9238..cf18c430d51f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -457,6 +457,24 @@ bool i915_gem_object_evictable(struct drm_i915_gem_object
*obj)
return pin_count == 0;
}
+/**
+ * i915_gem_object_migratable - Whether the object is migratable out of the
+ * current region.
+ * @obj: Pointer to the object.
+ *
+ * Return: Whether the object is allowed to be resident in other
+ * regions than the current while pages are present.
+ */
+bool i915_gem_object_migratable(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *mr = READ_ONCE(obj->mm.region);
+
+ if (!mr)
+ return false;
+
+ return obj->mm.n_placements > 1;
+}
+
void i915_gem_init__objects(struct drm_i915_private *i915)
{
INIT_WORK(&i915->mm.free_work, __i915_gem_free_work);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index ae5930e307d5..a3ad8cf4eefd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -596,6 +596,10 @@ void __i915_gem_free_object(struct drm_i915_gem_object
*obj);
bool i915_gem_object_evictable(struct drm_i915_gem_object *obj);
+bool i915_gem_object_migratable(struct drm_i915_gem_object *obj);
+
+bool i915_gem_objec
[Intel-gfx] [PATCH v9 13/15] drm/i915: Disable mmap ioctl for gen12+
From: Maarten Lankhorst
The platform should exclusively use mmap_offset, one less path to worry
about for discrete.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index f6fe5cb01438..fd1c9714f8d8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -56,10 +56,17 @@ int
i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
+ struct drm_i915_private *i915 = to_i915(dev);
struct drm_i915_gem_mmap *args = data;
struct drm_i915_gem_object *obj;
unsigned long addr;
+ /* mmap ioctl is disallowed for all platforms after TGL-LP. This also
+* covers all platforms with local memory.
+*/
+ if (INTEL_GEN(i915) >= 12 && !IS_TIGERLAKE(i915))
+ return -EOPNOTSUPP;
+
if (args->flags & ~(I915_MMAP_WC))
return -EINVAL;
--
2.31.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 14/15] drm/vma: Add a driver_private member to vma_node.
From: Maarten Lankhorst
This allows drivers to distinguish between different types of vma_node's.
The readonly flag was unused and is thus removed.
This is a temporary solution, until i915 is converted completely to
use ttm for bo's.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
Acked-by: Daniel Vetter #irc
---
drivers/gpu/drm/drm_gem.c | 9 -
include/drm/drm_vma_manager.h | 2 +-
2 files changed, 1 insertion(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 9989425e9875..e710e79069f6 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -1149,15 +1149,6 @@ int drm_gem_mmap(struct file *filp, struct
vm_area_struct *vma)
return -EACCES;
}
- if (node->readonly) {
- if (vma->vm_flags & VM_WRITE) {
- drm_gem_object_put(obj);
- return -EINVAL;
- }
-
- vma->vm_flags &= ~VM_MAYWRITE;
- }
-
ret = drm_gem_mmap_obj(obj, drm_vma_node_size(node) << PAGE_SHIFT,
vma);
diff --git a/include/drm/drm_vma_manager.h b/include/drm/drm_vma_manager.h
index 76ac5e97a559..4f8c35206f7c 100644
--- a/include/drm/drm_vma_manager.h
+++ b/include/drm/drm_vma_manager.h
@@ -53,7 +53,7 @@ struct drm_vma_offset_node {
rwlock_t vm_lock;
struct drm_mm_node vm_node;
struct rb_root vm_files;
- bool readonly:1;
+ void *driver_private;
};
struct drm_vma_offset_manager {
--
2.31.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 15/15] drm/i915: Use ttm mmap handling for ttm bo's.
From: Maarten Lankhorst
Use the ttm handlers for servicing page faults, and vm_access.
We do our own validation of read-only access, otherwise use the
ttm handlers as much as possible.
Because the ttm handlers expect the vma_node at vma->base, we slightly
need to massage the mmap handlers to look at vma_node->driver_private
to fetch the bo, if it's NULL, we assume i915's normal mmap_offset uapi
is used.
This is the easiest way to achieve compatibility without changing ttm's
semantics.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
- Fixed some minor style issues. (Thomas Hellström)
- Added a mutex Destroy (Thomas Hellström)
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 83
drivers/gpu/drm/i915/gem/i915_gem_object.h| 6 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 121 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 90 ++---
drivers/gpu/drm/i915/selftests/igt_mmap.c | 25 +++-
drivers/gpu/drm/i915/selftests/igt_mmap.h | 12 +-
8 files changed, 251 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index fd1c9714f8d8..d1de97e4adfd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -19,6 +19,7 @@
#include "i915_gem_mman.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
+#include "i915_gem_ttm.h"
#include "i915_vma.h"
static inline bool
@@ -622,6 +623,8 @@ mmap_offset_attach(struct drm_i915_gem_object *obj,
struct i915_mmap_offset *mmo;
int err;
+ GEM_BUG_ON(obj->ops->mmap_offset || obj->ops->mmap_ops);
+
mmo = lookup_mmo(obj, mmap_type);
if (mmo)
goto out;
@@ -664,40 +667,47 @@ mmap_offset_attach(struct drm_i915_gem_object *obj,
}
static int
-__assign_mmap_offset(struct drm_file *file,
-u32 handle,
+__assign_mmap_offset(struct drm_i915_gem_object *obj,
enum i915_mmap_type mmap_type,
-u64 *offset)
+u64 *offset, struct drm_file *file)
{
- struct drm_i915_gem_object *obj;
struct i915_mmap_offset *mmo;
- int err;
- obj = i915_gem_object_lookup(file, handle);
- if (!obj)
- return -ENOENT;
+ if (i915_gem_object_never_mmap(obj))
+ return -ENODEV;
- if (i915_gem_object_never_mmap(obj)) {
- err = -ENODEV;
- goto out;
+ if (obj->ops->mmap_offset) {
+ *offset = obj->ops->mmap_offset(obj);
+ return 0;
}
if (mmap_type != I915_MMAP_TYPE_GTT &&
!i915_gem_object_has_struct_page(obj) &&
- !i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_IOMEM)) {
- err = -ENODEV;
- goto out;
- }
+ !i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_IOMEM))
+ return -ENODEV;
mmo = mmap_offset_attach(obj, mmap_type, file);
- if (IS_ERR(mmo)) {
- err = PTR_ERR(mmo);
- goto out;
- }
+ if (IS_ERR(mmo))
+ return PTR_ERR(mmo);
*offset = drm_vma_node_offset_addr(&mmo->vma_node);
- err = 0;
-out:
+ return 0;
+}
+
+static int
+__assign_mmap_offset_handle(struct drm_file *file,
+ u32 handle,
+ enum i915_mmap_type mmap_type,
+ u64 *offset)
+{
+ struct drm_i915_gem_object *obj;
+ int err;
+
+ obj = i915_gem_object_lookup(file, handle);
+ if (!obj)
+ return -ENOENT;
+
+ err = __assign_mmap_offset(obj, mmap_type, offset, file);
i915_gem_object_put(obj);
return err;
}
@@ -717,7 +727,7 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
else
mmap_type = I915_MMAP_TYPE_GTT;
- return __assign_mmap_offset(file, handle, mmap_type, offset);
+ return __assign_mmap_offset_handle(file, handle, mmap_type, offset);
}
/**
@@ -785,7 +795,7 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void
*data,
return -EINVAL;
}
- return __assign_mmap_offset(file, args->handle, type, &args->offset);
+ return __assign_mmap_offset_handle(file, args->handle, type,
&args->offset);
}
static void vm_open(struct vm_area_struct *vma)
@@ -889,8 +899,18 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct
*vma)
* destroyed and will be invalid when the vma manager lock
* is released.
*/
- mmo = container_of(node, struct i915_mmap_offset, vma_node);
- obj = i915_gem_object_get_rcu(mmo->obj);
+ if (!node->driver_private) {
+ mmo =
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Move LMEM (VRAM) management over to TTM (rev5)
== Series Details == Series: Move LMEM (VRAM) management over to TTM (rev5) URL : https://patchwork.freedesktop.org/series/90681/ State : warning == Summary == $ dim checkpatch origin/drm-tip 325ee27eefe0 drm/i915: Untangle the vma pages_mutex b8ec60cc312c drm/i915: Don't free shared locks while shared f5f8f63758fb drm/i915: Fix i915_sg_page_sizes to record dma segments rather than physical pages eb3b2aa36f72 drm/i915/ttm Initialize the ttm device and memory managers -:480: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #480: deleted file mode 100644 total: 0 errors, 1 warnings, 0 checks, 1531 lines checked 4d3bb3c2ab3c drm/i915/ttm: Embed a ttm buffer object in the i915 gem object dd2260a61f1a drm/ttm: Add a generic TTM memcpy move for page-based iomem -:385: CHECK:ARCH_DEFINES: architecture specific defines should be avoided #385: FILE: drivers/gpu/drm/ttm/ttm_module.c:56: +#if defined(__i386__) || defined(__x86_64__) -:731: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #731: new file mode 100644 total: 0 errors, 1 warnings, 1 checks, 843 lines checked 15abc533f931 drm: Add a prefetching memcpy_from_wc 228add660c36 drm/ttm: Use drm_memcpy_from_wc for TTM bo moves e053c57e6840 drm/ttm: Document and optimize ttm_bo_pipeline_gutting() 38c66ced103f drm/ttm, drm/amdgpu: Allow the driver some control over swapping c777141dc2f3 drm/i915/ttm: Introduce a TTM i915 gem object backend -:449: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #449: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 1042 lines checked 3049c2ef413f drm/i915/lmem: Verify checks for lmem residency 76afa15acac3 drm/i915: Disable mmap ioctl for gen12+ 6cf6f92c1646 drm/vma: Add a driver_private member to vma_node. 324ad89a4002 drm/i915: Use ttm mmap handling for ttm bo's. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Move LMEM (VRAM) management over to TTM (rev5)
== Series Details == Series: Move LMEM (VRAM) management over to TTM (rev5) URL : https://patchwork.freedesktop.org/series/90681/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdg
[Intel-gfx] [PATCH] drm/i915: Add relocation exceptions for two other platforms
We have established previously we stop using relocations starting
from gen12 platforms with Tigerlake as an exception. We keep this
statement but we want to enable relocations conditionally for
Rocketlake and Alderlake under require_force_probe flag set.
Keeping relocations under require_force_probe flag is interim solution
until IGTs will be rewritten to use softpin.
Signed-off-by: Zbigniew Kempczyński
Cc: Dave Airlie
Cc: Daniel Vetter
Cc: Jason Ekstrand
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 26 +++
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 297143511f99..c0562dd14837 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -491,16 +491,32 @@ eb_unreserve_vma(struct eb_vma *ev)
ev->flags &= ~__EXEC_OBJECT_RESERVED;
}
+static inline bool
+platform_has_relocs_enabled(const struct i915_execbuffer *eb)
+{
+ /*
+* Relocations are disallowed starting from gen12 with Tigerlake
+* as an exception. We allow temporarily use relocations for Rocketlake
+* and Alderlake when require_force_probe flag is set.
+*/
+
+ if (INTEL_GEN(eb->i915) < 12 || IS_TIGERLAKE(eb->i915))
+ return true;
+
+ if (INTEL_INFO(eb->i915)->require_force_probe &&
+(IS_ROCKETLAKE(eb->i915) || IS_ALDERLAKE_S(eb->i915) ||
+ IS_ALDERLAKE_P(eb->i915)))
+ return true;
+
+ return false;
+}
+
static int
eb_validate_vma(struct i915_execbuffer *eb,
struct drm_i915_gem_exec_object2 *entry,
struct i915_vma *vma)
{
- /* Relocations are disallowed for all platforms after TGL-LP. This
-* also covers all platforms with local memory.
-*/
- if (entry->relocation_count &&
- INTEL_GEN(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
+ if (entry->relocation_count && !platform_has_relocs_enabled(eb))
return -EINVAL;
if (unlikely(entry->flags & eb->invalid_flags))
--
2.26.0
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[Intel-gfx] ✓ Fi.CI.BAT: success for Move LMEM (VRAM) management over to TTM (rev5)
== Series Details ==
Series: Move LMEM (VRAM) management over to TTM (rev5)
URL : https://patchwork.freedesktop.org/series/90681/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10153 -> Patchwork_20243
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20243:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_tiled_fence_blits@basic:
- {fi-rkl-11500t}:[FAIL][1] ([i915#3277]) -> [FAIL][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-rkl-11500t/igt@gem_tiled_fence_bl...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/fi-rkl-11500t/igt@gem_tiled_fence_bl...@basic.html
* igt@kms_busy@basic:
- {fi-rkl-11500t}:NOTRUN -> [SKIP][3] +4 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/fi-rkl-11500t/igt@kms_b...@basic.html
* igt@prime_self_import@basic-with_two_bos:
- {fi-rkl-11500t}:[PASS][4] -> [FAIL][5] +4 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-rkl-11500t/igt@prime_self_import@basic-with_two_bos.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/fi-rkl-11500t/igt@prime_self_import@basic-with_two_bos.html
* igt@prime_vgem@basic-fence-flip:
- {fi-rkl-11500t}:[PASS][6] -> [SKIP][7] +2 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-rkl-11500t/igt@prime_v...@basic-fence-flip.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/fi-rkl-11500t/igt@prime_v...@basic-fence-flip.html
* igt@prime_vgem@basic-read:
- {fi-rkl-11500t}:[SKIP][8] ([i915#3291]) -> [SKIP][9] +2 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-rkl-11500t/igt@prime_v...@basic-read.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/fi-rkl-11500t/igt@prime_v...@basic-read.html
* igt@prime_vgem@basic-userptr:
- {fi-rkl-11500t}:[SKIP][10] ([i915#3301]) -> [SKIP][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-rkl-11500t/igt@prime_v...@basic-userptr.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/fi-rkl-11500t/igt@prime_v...@basic-userptr.html
Known issues
Here are the changes found in Patchwork_20243 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][12] ([fdo#109271]) +17 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: NOTRUN -> [WARN][13] ([i915#2283])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html
* igt@i915_selftest@live@execlists:
- fi-bdw-5557u: NOTRUN -> [DMESG-FAIL][14] ([i915#3462])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/fi-bdw-5557u/igt@i915_selftest@l...@execlists.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-tgl-u2: [PASS][16] -> [FAIL][17] ([i915#2416])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-tgl-u2/igt@kms_frontbuffer_track...@basic.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/fi-tgl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@kms_psr@cursor_plane_move:
- fi-bdw-5557u: NOTRUN -> [SKIP][18] ([fdo#109271]) +9 similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/fi-bdw-5557u/igt@kms_psr@cursor_plane_move.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][19] ([i915#2782]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-guc: [FAIL][21] ([i915#3049]) -> [SKIP][22] ([fdo#109271])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-s
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add relocation exceptions for two other platforms (rev3)
== Series Details == Series: drm/i915: Add relocation exceptions for two other platforms (rev3) URL : https://patchwork.freedesktop.org/series/89594/ State : warning == Summary == $ dim checkpatch origin/drm-tip 07cc51d80ac1 drm/i915: Add relocation exceptions for two other platforms -:44: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #44: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:507: + if (INTEL_INFO(eb->i915)->require_force_probe && +(IS_ROCKETLAKE(eb->i915) || IS_ALDERLAKE_S(eb->i915) || total: 0 errors, 0 warnings, 1 checks, 37 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/gem: Use list_entry to access list members
On 2021.05.23 10:23:04 -0700, Guenter Roeck wrote:
> Use list_entry() instead of container_of() to access list members.
> Also drop unnecessary and misleading NULL checks on the result of
> list_entry().
>
> Signed-off-by: Guenter Roeck
> ---
> v2: Checkpatch fixes:
> - Fix alignment
> - Replace comparison against NULL with !
>
> drivers/gpu/drm/i915/gvt/dmabuf.c | 18 +-
> 1 file changed, 5 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c
> b/drivers/gpu/drm/i915/gvt/dmabuf.c
> index d4f883f35b95..e3f488681484 100644
> --- a/drivers/gpu/drm/i915/gvt/dmabuf.c
> +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
> @@ -148,8 +148,7 @@ static void dmabuf_gem_object_free(struct kref *kref)
>
> if (vgpu && vgpu->active && !list_empty(&vgpu->dmabuf_obj_list_head)) {
> list_for_each(pos, &vgpu->dmabuf_obj_list_head) {
> - dmabuf_obj = container_of(pos,
> - struct intel_vgpu_dmabuf_obj, list);
> + dmabuf_obj = list_entry(pos, struct
> intel_vgpu_dmabuf_obj, list);
> if (dmabuf_obj == obj) {
> list_del(pos);
> intel_gvt_hypervisor_put_vfio_device(vgpu);
> @@ -357,10 +356,8 @@ pick_dmabuf_by_info(struct intel_vgpu *vgpu,
> struct intel_vgpu_dmabuf_obj *ret = NULL;
>
> list_for_each(pos, &vgpu->dmabuf_obj_list_head) {
> - dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
> - list);
> - if ((dmabuf_obj == NULL) ||
> - (dmabuf_obj->info == NULL))
> + dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj,
> list);
> + if (!dmabuf_obj->info)
> continue;
>
> fb_info = (struct intel_vgpu_fb_info *)dmabuf_obj->info;
> @@ -387,11 +384,7 @@ pick_dmabuf_by_num(struct intel_vgpu *vgpu, u32 id)
> struct intel_vgpu_dmabuf_obj *ret = NULL;
>
> list_for_each(pos, &vgpu->dmabuf_obj_list_head) {
> - dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
> - list);
> - if (!dmabuf_obj)
> - continue;
> -
> + dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj,
> list);
> if (dmabuf_obj->dmabuf_id == id) {
> ret = dmabuf_obj;
> break;
> @@ -600,8 +593,7 @@ void intel_vgpu_dmabuf_cleanup(struct intel_vgpu *vgpu)
>
> mutex_lock(&vgpu->dmabuf_lock);
> list_for_each_safe(pos, n, &vgpu->dmabuf_obj_list_head) {
> - dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
> - list);
> + dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj,
> list);
> dmabuf_obj->vgpu = NULL;
>
> idr_remove(&vgpu->object_idr, dmabuf_obj->dmabuf_id);
> --
Sorry for late reply! Looks good to me.
Reviewed-by: Zhenyu Wang
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Re: [Intel-gfx] linux-next: build failure after merge of the i2c tree
Hi Stephen,
> After merging the i2c tree, today's linux-next build (x86_64 allmodconfig)
> failed like this:
>
> In file included from drivers/gpu/drm/i915/i915_gem.c:1250:
> drivers/gpu/drm/i915/selftests/i915_gem.c:97:13: error: conflicting types for
> 'pm_suspend'
>97 | static void pm_suspend(struct drm_i915_private *i915)
> | ^~
> In file included from include/linux/regulator/consumer.h:35,
> from include/linux/i2c.h:18,
> from drivers/gpu/drm/i915/i915_drv.h:39,
> from drivers/gpu/drm/i915/gt/intel_context.h:14,
> from drivers/gpu/drm/i915/gem/i915_gem_context.h:12,
> from drivers/gpu/drm/i915/i915_gem.c:44:
> include/linux/suspend.h:331:12: note: previous declaration of 'pm_suspend'
> was here
> 331 | extern int pm_suspend(suspend_state_t state);
> |^~
>
> Caused by commit
>
> 5a7b95fb993e ("i2c: core: support bus regulator controlling in adapter")
>
> interacting with commit
>
> 3f51b7e1f36a ("drm/i915/selftests: Add a simple exerciser for
> suspend/hibernate")
>
> from Linus' tree (v4.20-rc1)
Thank you very much for taking care of this!
> I have added the following merge fix patch:
>
> From: Stephen Rothwell
> Date: Tue, 1 Jun 2021 10:25:49 +1000
> Subject: [PATCH] drm/i915/selftests: Avoid name clash with pm_ global
> functions
>
> Signed-off-by: Stephen Rothwell
Looks like the proper solution to me. I think this should be added to
the i915 tree. D'accord everyone?
Reviewed-by: Wolfram Sang
Kind regards,
Wolfram
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Re: [Intel-gfx] linux-next: build failure after merge of the i2c tree
On Tue, Jun 1, 2021 at 4:55 PM Wolfram Sang wrote:
>
> Hi Stephen,
>
> > After merging the i2c tree, today's linux-next build (x86_64 allmodconfig)
> > failed like this:
> >
> > In file included from drivers/gpu/drm/i915/i915_gem.c:1250:
> > drivers/gpu/drm/i915/selftests/i915_gem.c:97:13: error: conflicting types
> > for 'pm_suspend'
> >97 | static void pm_suspend(struct drm_i915_private *i915)
> > | ^~
> > In file included from include/linux/regulator/consumer.h:35,
> > from include/linux/i2c.h:18,
> > from drivers/gpu/drm/i915/i915_drv.h:39,
> > from drivers/gpu/drm/i915/gt/intel_context.h:14,
> > from drivers/gpu/drm/i915/gem/i915_gem_context.h:12,
> > from drivers/gpu/drm/i915/i915_gem.c:44:
> > include/linux/suspend.h:331:12: note: previous declaration of 'pm_suspend'
> > was here
> > 331 | extern int pm_suspend(suspend_state_t state);
> > |^~
> >
> > Caused by commit
> >
> > 5a7b95fb993e ("i2c: core: support bus regulator controlling in adapter")
> >
> > interacting with commit
> >
> > 3f51b7e1f36a ("drm/i915/selftests: Add a simple exerciser for
> > suspend/hibernate")
> >
> > from Linus' tree (v4.20-rc1)
>
> Thank you very much for taking care of this!
>
Hi, this issue is fixed in
https://cgit.freedesktop.org/drm-intel/commit/?h=drm-intel-gt-next&id=5b11705608898c31a1cae5340555ee60d5a4fa45
And I think the pull request is in
https://lists.freedesktop.org/archives/intel-gfx/2021-May/267588.html
Thanks
>
> > I have added the following merge fix patch:
> >
> > From: Stephen Rothwell
> > Date: Tue, 1 Jun 2021 10:25:49 +1000
> > Subject: [PATCH] drm/i915/selftests: Avoid name clash with pm_ global
> > functions
> >
> > Signed-off-by: Stephen Rothwell
>
> Looks like the proper solution to me. I think this should be added to
> the i915 tree. D'accord everyone?
>
> Reviewed-by: Wolfram Sang
>
> Kind regards,
>
>Wolfram
>
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Re: [Intel-gfx] [PATCH -next] drm/i915: use DEVICE_ATTR_RO macro
On 28/05/2021 11:04, YueHaibing wrote:
Use DEVICE_ATTR_RO() helper instead of plain DEVICE_ATTR(),
which makes the code a bit shorter and easier to read.
Signed-off-by: YueHaibing
---
drivers/gpu/drm/i915/i915_pmu.c | 8 +++-
drivers/gpu/drm/i915/i915_sysfs.c | 30 +++---
2 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 41651ac255fa..fb215929b05b 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -834,15 +834,13 @@ static ssize_t i915_pmu_event_show(struct device *dev,
return sprintf(buf, "config=0x%lx\n", eattr->val);
}
-static ssize_t
-i915_pmu_get_attr_cpumask(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static ssize_t cpumask_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
return cpumap_print_to_pagebuf(true, buf, &i915_pmu_cpumask);
}
-static DEVICE_ATTR(cpumask, 0444, i915_pmu_get_attr_cpumask, NULL);
+static DEVICE_ATTR_RO(cpumask);
static struct attribute *i915_cpumask_attrs[] = {
&dev_attr_cpumask.attr,
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 4c6b5d52b5ca..183517d1a73d 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -58,8 +58,8 @@ static u32 calc_residency(struct drm_i915_private *dev_priv,
return DIV_ROUND_CLOSEST_ULL(res, 1000);
}
-static ssize_t
-show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
+static ssize_t rc6_enable_show(struct device *kdev,
+ struct device_attribute *attr, char *buf)
{
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
unsigned int mask;
@@ -75,43 +75,43 @@ show_rc6_mask(struct device *kdev, struct device_attribute
*attr, char *buf)
return sysfs_emit(buf, "%x\n", mask);
}
-static ssize_t
-show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
+static ssize_t rc6_residency_ms_show(struct device *kdev,
+struct device_attribute *attr, char *buf)
{
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6);
return sysfs_emit(buf, "%u\n", rc6_residency);
}
-static ssize_t
-show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
+static ssize_t rc6p_residency_ms_show(struct device *kdev,
+ struct device_attribute *attr, char *buf)
{
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p);
return sysfs_emit(buf, "%u\n", rc6p_residency);
}
-static ssize_t
-show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
+static ssize_t rc6pp_residency_ms_show(struct device *kdev,
+ struct device_attribute *attr, char *buf)
{
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp);
return sysfs_emit(buf, "%u\n", rc6pp_residency);
}
-static ssize_t
-show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char
*buf)
+static ssize_t media_rc6_residency_ms_show(struct device *kdev,
+ struct device_attribute *attr, char
*buf)
{
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6);
return sysfs_emit(buf, "%u\n", rc6_residency);
}
-static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
-static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
-static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
-static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
-static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
+static DEVICE_ATTR_RO(rc6_enable);
+static DEVICE_ATTR_RO(rc6_residency_ms);
+static DEVICE_ATTR_RO(rc6p_residency_ms);
+static DEVICE_ATTR_RO(rc6pp_residency_ms);
+static DEVICE_ATTR_RO(media_rc6_residency_ms);
static struct attribute *rc6_attrs[] = {
&dev_attr_rc6_enable.attr,
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add relocation exceptions for two other platforms (rev3)
== Series Details ==
Series: drm/i915: Add relocation exceptions for two other platforms (rev3)
URL : https://patchwork.freedesktop.org/series/89594/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10153 -> Patchwork_20244
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/index.html
Known issues
Here are the changes found in Patchwork_20244 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: NOTRUN -> [WARN][1] ([i915#2283])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html
* igt@i915_selftest@live@execlists:
- fi-bdw-5557u: NOTRUN -> [DMESG-FAIL][2] ([i915#3462])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/fi-bdw-5557u/igt@i915_selftest@l...@execlists.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_psr@cursor_plane_move:
- fi-bdw-5557u: NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/fi-bdw-5557u/igt@kms_psr@cursor_plane_move.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][5] ([i915#3303]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-guc: [FAIL][7] ([i915#3049]) -> [SKIP][8] ([fdo#109271])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_selftest@live@execlists:
- fi-icl-u2: [DMESG-FAIL][9] ([i915#3462]) -> [INCOMPLETE][10]
([i915#2782] / [i915#3462])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-icl-u2/igt@i915_selftest@l...@execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/fi-icl-u2/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-cfl-8700k: [FAIL][11] ([i915#2426] / [i915#3363]) -> [FAIL][12]
([i915#3363])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-cfl-8700k/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/fi-cfl-8700k/igt@run...@aborted.html
- fi-icl-u2: [FAIL][13] ([i915#2426] / [i915#2782] / [i915#3363])
-> [FAIL][14] ([i915#2782] / [i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-icl-u2/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/fi-icl-u2/igt@run...@aborted.html
- fi-bdw-5557u: [FAIL][15] ([i915#1602] / [i915#2029]) -> [FAIL][16]
([i915#3462])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-bdw-5557u/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/fi-bdw-5557u/igt@run...@aborted.html
- fi-kbl-soraka: [FAIL][17] ([i915#1436] / [i915#3363]) -> [FAIL][18]
([i915#1436] / [i915#2426] / [i915#3363])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-kbl-soraka/igt@run...@aborted.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/fi-kbl-soraka/igt@run...@aborted.html
- fi-kbl-guc: [FAIL][19] ([i915#1436] / [i915#3363]) -> [FAIL][20]
([i915#1436] / [i915#2426] / [i915#3363])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-kbl-guc/igt@run...@aborted.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/fi-kbl-guc/igt@run...@aborted.html
- fi-cml-u2: [FAIL][21] ([i915#3363] / [i915#3462]) -> [FAIL][22]
([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-cml-u2/igt@run...@aborted.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/fi-cml-u2/igt@run...@aborted.html
- fi-bxt-dsi: [FAIL][23] ([i915#2426] / [i915#3363]) -> [FAIL][24]
([i915#3363])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/fi-bxt-dsi/igt@run...@aborted.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/fi-bxt-dsi/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest()
[Don't see this on intel-gfx so I have to reply with top post.]
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
-Original Message-
From: Zhihao Cheng
Sent: Saturday, May 29, 2021 5:33 AM
To: jani.nik...@linux.intel.com; joonas.lahti...@linux.intel.com; Vivi, Rodrigo
; airl...@linux.ie; dan...@ffwll.ch;
ch...@chris-wilson.co.uk; Ursulin, Tvrtko
Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
linux-ker...@vger.kernel.org; chengzhih...@huawei.com; yuku...@huawei.com
Subject: [PATCH] drm/i915/selftests: Fix return value check in
live_breadcrumbs_smoketest()
In case of error, the function live_context() returns ERR_PTR() and never
returns NULL. The NULL test in the return value check should be replaced with
IS_ERR().
Fixes: 52c0fdb25c7c9 ("drm/i915: Replace global breadcrumbs ...")
Reported-by: Hulk Robot
Signed-off-by: Zhihao Cheng
---
drivers/gpu/drm/i915/selftests/i915_request.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index ee8e753d98ce..eae0abd614cb 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -1592,8 +1592,8 @@ static int live_breadcrumbs_smoketest(void *arg)
for (n = 0; n < smoke[0].ncontexts; n++) {
smoke[0].contexts[n] = live_context(i915, file);
- if (!smoke[0].contexts[n]) {
- ret = -ENOMEM;
+ if (IS_ERR(smoke[0].contexts[n])) {
+ ret = PTR_ERR(smoke[0].contexts[n]);
goto out_contexts;
}
}
--
2.25.4
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Re: [Intel-gfx] linux-next: build failure after merge of the i2c tree
> Hi, this issue is fixed in > https://cgit.freedesktop.org/drm-intel/commit/?h=drm-intel-gt-next&id=5b11705608898c31a1cae5340555ee60d5a4fa45 > > And I think the pull request is in > https://lists.freedesktop.org/archives/intel-gfx/2021-May/267588.html Thanks for the heads up. So, I'll wait with my pull request for the next merge window until drm has landed first. signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Only set bind_async_flags when concurrent access wa is not active, v3.
We need to make the BSW workaround actually work. We correctly fixed
the mutex nesting, but forgot to kill the worker.
The worker is killed by clearing async_flags, and just running bind_vma
synchronously. This still needs the stash, because we cannot allocate
and pin with vm->mutex already held.
Changes since v1:
- Fix null pointer dereference when we forget to pass the work stash,
it's still required to prealloc all on affected platforms.
Changes since v2:
- Clear bind_async_flags correctly on ggtt w/a.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 4 +++-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 4 +++-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 --
drivers/gpu/drm/i915/i915_vma.c | 4 ++--
4 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 1aee5e6b1b23..de3aa79b788e 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -433,7 +433,9 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen6_pte_t));
ppgtt->base.vm.top = 1;
- ppgtt->base.vm.bind_async_flags = I915_VMA_LOCAL_BIND;
+ if (!intel_vm_no_concurrent_access_wa(gt->i915))
+ ppgtt->base.vm.bind_async_flags = I915_VMA_LOCAL_BIND;
+
ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index e3a8924d2286..aa58b0e48ae1 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -732,7 +732,9 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
goto err_free_pd;
}
- ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
+ if (!intel_vm_no_concurrent_access_wa(gt->i915))
+ ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
+
ppgtt->vm.insert_entries = gen8_ppgtt_insert;
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
ppgtt->vm.clear_range = gen8_ppgtt_clear;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 35069ca5d7de..aafcd0b2ab9b 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -914,8 +914,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
if (intel_vm_no_concurrent_access_wa(i915)) {
ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
ggtt->vm.insert_page= bxt_vtd_ggtt_insert_page__BKL;
- ggtt->vm.bind_async_flags =
- I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
}
ggtt->invalidate = gen8_ggtt_invalidate;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index b319fd3f91cc..d550ee911e68 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -436,7 +436,7 @@ int i915_vma_bind(struct i915_vma *vma,
work->pinned = i915_gem_object_get(vma->obj);
}
} else {
- vma->ops->bind_vma(vma->vm, NULL, vma, cache_level, bind_flags);
+ vma->ops->bind_vma(vma->vm, work ? &work->stash : NULL, vma,
cache_level, bind_flags);
}
atomic_or(bind_flags, &vma->flags);
@@ -895,7 +895,7 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
if (flags & PIN_GLOBAL)
wakeref = intel_runtime_pm_get(&vma->vm->i915->runtime_pm);
- if (flags & vma->vm->bind_async_flags) {
+ if ((flags & vma->vm->bind_async_flags) || vma->vm->allocate_va_range) {
/* lock VM */
err = i915_vm_lock_objects(vma->vm, ww);
if (err)
--
2.31.0
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Re: [Intel-gfx] [RFC PATCH 60/97] drm/i915: Track 'serial' counts for virtual engines
On 27/05/2021 18:01, John Harrison wrote: On 5/27/2021 01:53, Tvrtko Ursulin wrote: On 26/05/2021 19:45, John Harrison wrote: On 5/26/2021 01:40, Tvrtko Ursulin wrote: On 25/05/2021 18:52, Matthew Brost wrote: On Tue, May 25, 2021 at 11:16:12AM +0100, Tvrtko Ursulin wrote: On 06/05/2021 20:14, Matthew Brost wrote: From: John Harrison The serial number tracking of engines happens at the backend of request submission and was expecting to only be given physical engines. However, in GuC submission mode, the decomposition of virtual to physical engines does not happen in i915. Instead, requests are submitted to their virtual engine mask all the way through to the hardware (i.e. to GuC). This would mean that the heart beat code thinks the physical engines are idle due to the serial number not incrementing. This patch updates the tracking to decompose virtual engines into their physical constituents and tracks the request against each. This is not entirely accurate as the GuC will only be issuing the request to one physical engine. However, it is the best that i915 can do given that it has no knowledge of the GuC's scheduling decisions. Commit text sounds a bit defeatist. I think instead of making up the serial counts, which has downsides (could you please document in the commit what they are), we should think how to design things properly. IMO, I don't think fixing serial counts is the scope of this series. We should focus on getting GuC submission in not cleaning up all the crap that is in the i915. Let's make a note of this though so we can revisit later. I will say again - commit message implies it is introducing an unspecified downside by not fully fixing an also unspecified issue. It is completely reasonable, and customary even, to ask for both to be documented in the commit message. Not sure what exactly is 'unspecified'. I thought the commit message described both the problem (heartbeat not running when using virtual engines) and the result (heartbeat running on more engines than strictly necessary). But in greater detail... The serial number tracking is a hack for the heartbeat code to know whether an engine is busy or idle, and therefore whether it should be pinged for aliveness. Whenever a submission is made to an engine, the serial number is incremented. The heartbeat code keeps a copy of the value. If the value has changed, the engine is busy and needs to be pinged. This works fine for execlist mode where virtual engine decomposition is done inside i915. It fails miserably for GuC mode where the decomposition is done by the hardware. The reason being that the heartbeat code only looks at physical engines but the serial count is only incremented on the virtual engine. Thus, the heartbeat sees everything as idle and does not ping. So hangcheck does not work. Or it works because GuC does it anyway. Either way, that's one thing to explicitly state in the commit message. This patch decomposes the virtual engines for the sake of incrementing the serial count on each sub-engine in order to keep the heartbeat code happy. The downside is that now the heartbeat sees all sub-engines as busy rather than only the one the submission actually ends up on. There really isn't much that can be done about that. The heartbeat code is in i915 not GuC, the scheduler is in GuC not i915. The only way to improve it is to either move the heartbeat code into GuC as well and completely disable the i915 side, or add some way for i915 to interrogate GuC as to which engines are or are not active. Technically, we do have both. GuC has (or at least had) an option to force a context switch on every execution quantum pre-emption. However, that is much, much, more heavy weight than the heartbeat. For the latter, we do (almost) have the engine usage statistics for PMU and such like. I'm not sure how much effort it would be to wire that up to the heartbeat code instead of using the serial count. In short, the serial count is ever so slightly inefficient in that it causes heartbeat pings on engines which are idle. On the other hand, it is way more efficient and simpler than the current alternatives. And the hack to make hangcheck work creates this inefficiency where heartbeats are sent to idle engines. Which is probably fine just needs to be explained. Does that answer the questions? With the two points I re-raise clearly explained, possibly even patch title changed, yeah. I am just wanting for it to be more easily obvious to patch reader what it is functionally about - not just what implementation details have been change but why as well. My understanding is that we don't explain every piece of code in minute detail in every checkin email that touches it. I thought my description was already pretty verbose. I've certainly seen way less informative checkins that apparently made it through review without issue. Regarding the problem statement, I
[Intel-gfx] [PATCH v2] drm/i915/display: Introduce new intel_psr_pause/resume function
This introduces the following function that can exit and activate a psr
source when intel_psr is already enabled.
- intel_psr_pause(): Pause current PSR. It deactivates current psr state.
- intel_psr_resume(): Resume paused PSR. It activates paused psr state.
v2: Address Jose's review comment.
- Remove unneeded changes around the intel_psr_enable().
- Add intel_psr_post_exit() which processes waiting until PSR is idle
and WA for SelectiveFetch.
Cc: José Roberto de Souza
Cc: Stanislav Lisovskiy
Cc: Ville Syrjälä
Signed-off-by: Gwan-gyeong Mun
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 84 ---
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
3 files changed, 76 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index b8d1f702d808..ee7cbdd7db87 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1482,6 +1482,7 @@ struct intel_psr {
bool sink_support;
bool source_support;
bool enabled;
+ bool paused;
enum pipe pipe;
enum transcoder transcoder;
bool active;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 000e1ffe8c05..4ff71e529cd3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1113,6 +1113,7 @@ static void intel_psr_enable_locked(struct intel_dp
*intel_dp,
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp);
intel_dp->psr.enabled = true;
+ intel_dp->psr.paused = false;
intel_psr_activate(intel_dp);
}
@@ -1182,22 +1183,12 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
intel_dp->psr.active = false;
}
-static void intel_psr_disable_locked(struct intel_dp *intel_dp)
+static void intel_psr_post_exit(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
i915_reg_t psr_status;
u32 psr_status_mask;
- lockdep_assert_held(&intel_dp->psr.lock);
-
- if (!intel_dp->psr.enabled)
- return;
-
- drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
- intel_dp->psr.psr2_enabled ? "2" : "1");
-
- intel_psr_exit(intel_dp);
-
if (intel_dp->psr.psr2_enabled) {
psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
@@ -1217,6 +1208,22 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
+}
+
+static void intel_psr_disable_locked(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ lockdep_assert_held(&intel_dp->psr.lock);
+
+ if (!intel_dp->psr.enabled)
+ return;
+
+ drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
+ intel_dp->psr.psr2_enabled ? "2" : "1");
+
+ intel_psr_exit(intel_dp);
+ intel_psr_post_exit(intel_dp);
/* Disable PSR on Sink */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
@@ -1254,6 +1261,61 @@ void intel_psr_disable(struct intel_dp *intel_dp,
cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
}
+/**
+ * intel_psr_pause - Pause PSR
+ * @intel_dp: Intel DP
+ *
+ * This function need to be called after enabling psr.
+ */
+void intel_psr_pause(struct intel_dp *intel_dp)
+{
+ struct intel_psr *psr = &intel_dp->psr;
+
+ if (!CAN_PSR(intel_dp))
+ return;
+
+ mutex_lock(&psr->lock);
+
+ if (!psr->active) {
+ mutex_unlock(&psr->lock);
+ return;
+ }
+
+ intel_psr_exit(intel_dp);
+ intel_psr_post_exit(intel_dp);
+ psr->paused = true;
+
+ mutex_unlock(&psr->lock);
+
+ cancel_work_sync(&psr->work);
+ cancel_delayed_work_sync(&psr->dc3co_work);
+}
+
+/**
+ * intel_psr_resume - Resume PSR
+ * @intel_dp: Intel DP
+ *
+ * This function need to be called after pausing psr.
+ */
+void intel_psr_resume(struct intel_dp *intel_dp)
+{
+ struct intel_psr *psr = &intel_dp->psr;
+
+ if (!CAN_PSR(intel_dp))
+ return;
+
+ mutex_lock(&psr->lock);
+
+ if (!psr->paused)
+ goto unlock;
+
+ psr->paused = false;
+ intel_psr_activate(intel_dp);
+
+unlock:
+ mutex_unlock(&psr->lock);
+}
+
static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
b/drivers/gpu/drm/i915/display
[Intel-gfx] [PATCH 3/9] drm/i915/xelpd: Add support for Logarithmic gamma mode
XE_LPD hardware introduced a new gamma mode i.e, Logarithmic
gamma mode. Added support for the same.
Signed-off-by: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 111 -
drivers/gpu/drm/i915/i915_reg.h| 1 +
include/drm/drm_crtc.h | 3 +
3 files changed, 110 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 0b59d8a89761..12cacd3aeead 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -75,6 +75,21 @@
#define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
+#define GAMMA_MODE_LEGACY_PALETTE_8BIT BIT(0)
+#define GAMMA_MODE_PRECISION_PALETTE_10BIT BIT(1)
+#define GAMMA_MODE_INTERPOLATED_12BIT BIT(2)
+#define GAMMA_MODE_MULTI_SEGMENTED_12BIT BIT(3)
+#define GAMMA_MODE_SPLIT_12BIT BIT(4)
+#define GAMMA_MODE_LOGARITHMIC_12BIT BIT(5) /* D13+ */
+
+#define INTEL_GAMMA_MODE_MASK (\
+ GAMMA_MODE_LEGACY_PALETTE_8BIT | \
+ GAMMA_MODE_PRECISION_PALETTE_10BIT | \
+ GAMMA_MODE_INTERPOLATED_12BIT | \
+ GAMMA_MODE_MULTI_SEGMENTED_12BIT | \
+ GAMMA_MODE_SPLIT_12BIT \
+ GAMMA_MODE_LOGARITHMIC_12BIT)
+
/* Nop pre/post offsets */
static const u16 ilk_csc_off_zero[3] = {};
@@ -929,12 +944,20 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
const struct drm_color_lut *color)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
enum pipe pipe = crtc->pipe;
- /* FIXME LUT entries are 16 bit only, so we can prog 0x max */
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red);
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green);
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ if (DISPLAY_VER(i915) >= 13) {
+ /* MAx val from UAPI is 16bit only, so setting fixed for GC max
*/
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), 1 <<
16);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), 1 <<
16);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), 1 <<
16);
+ } else {
+ /* FIXME LUT entries are 16 bit only, so we can prog 0x max
*/
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0),
color->red);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1),
color->green);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2),
color->blue);
+ }
}
static void
@@ -1585,6 +1608,9 @@ static u32 icl_gamma_mode(const struct intel_crtc_state
*crtc_state)
if (!crtc_state->hw.gamma_lut ||
crtc_state_is_legacy_gamma(crtc_state))
gamma_mode |= GAMMA_MODE_MODE_8BIT;
+ else if (crtc_state->uapi.gamma_mode_type ==
+GAMMA_MODE_LOGARITHMIC_12BIT)
+ gamma_mode |= GAMMA_MODE_MODE_12BIT_LOGARITHMIC;
else
gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
@@ -1607,12 +1633,33 @@ static u32 icl_csc_mode(const struct intel_crtc_state
*crtc_state)
static int icl_color_check(struct intel_crtc_state *crtc_state)
{
+ struct drm_device *dev = crtc_state->uapi.crtc->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_property *property =
crtc_state->uapi.crtc->gamma_mode_property;
+ struct drm_property_enum *prop_enum;
+ u32 index = 0;
int ret;
ret = check_luts(crtc_state);
if (ret)
return ret;
+ if (DISPLAY_VER(dev_priv) >= 13) {
+ list_for_each_entry(prop_enum, &property->enum_list, head) {
+ if (prop_enum->value == crtc_state->uapi.gamma_mode) {
+ if (!strcmp(prop_enum->name,
+ "logarithmic gamma")) {
+ crtc_state->uapi.gamma_mode_type =
+ GAMMA_MODE_LOGARITHMIC_12BIT;
+ drm_dbg_kms(dev,
+ "logarithmic gamma
enabled\n");
+ }
+ break;
+ }
+ index++;
+ }
+ }
+
crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
crtc_state->csc_mode = icl_csc_mode(crtc_state);
@@ -2325,6 +2372,58 @@ static const struct drm_color_lut_range
d13_logarithmic_gamma[] = {
},
};
+static void
+d13_program_logarithmic_gamma_lut(const struct intel_crtc_state *
[Intel-gfx] [PATCH 2/9] drm/i915/xelpd: Define color lut range structure
This defines the color lut ranges for logarithmic gamma which
is being introduced from XE_LPD onwards.
Signed-off-by: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 250 -
1 file changed, 246 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index dab892d2251b..0b59d8a89761 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2093,6 +2093,238 @@ static void icl_read_luts(struct intel_crtc_state
*crtc_state)
}
}
+#define D13_GAMMA_CAPABILITY_FLAG (DRM_MODE_LUT_GAMMA | \
+DRM_MODE_LUT_REFLECT_NEGATIVE | \
+DRM_MODE_LUT_INTERPOLATE | \
+DRM_MODE_LUT_NON_DECREASING)
+ /* FIXME input bpc? */
+static const struct drm_color_lut_range d13_logarithmic_gamma[] = {
+ /* segment 0 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = 0, .end = 0,
+ .min = 0, .max = 0,
+ },
+ /* segment 1 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = 0, .end = (1 << 0),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 2 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 2,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 0), .end = (1 << 1),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 3 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 2,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 1), .end = (1 << 2),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 4 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 2,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 2), .end = (1 << 3),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 5 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 2,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 3), .end = (1 << 4),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 6 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 4,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 4), .end = (1 << 5),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 7 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 4,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 5), .end = (1 << 6),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 8 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 4,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 6), .end = (1 << 7),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 9 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 8,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 7), .end = (1 << 8),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 10 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 8,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 8), .end = (1 << 9),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 11 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 8,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 9), .end = (1 << 10),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 12 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 16,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 10), .end = (1 << 11),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 13 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 16,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 11), .end = (1 << 12),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 14 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 16,
+ .input_bpc = 2
[Intel-gfx] [PATCH 6/9] drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode
Only Enable Logarithmic Gamma if client caps for advance gamma mode
is enabled. Fallback to 10bit gamma in case its not supported.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index cae96fbec1a7..18b51b9cc2aa 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1606,13 +1606,17 @@ static u32 icl_gamma_mode(const struct intel_crtc_state
*crtc_state)
gamma_mode |= POST_CSC_GAMMA_ENABLE;
if (!crtc_state->hw.gamma_lut ||
- crtc_state_is_legacy_gamma(crtc_state))
+ crtc_state_is_legacy_gamma(crtc_state)) {
gamma_mode |= GAMMA_MODE_MODE_8BIT;
- else if (crtc_state->uapi.gamma_mode_type ==
-GAMMA_MODE_LOGARITHMIC_12BIT)
- gamma_mode |= GAMMA_MODE_MODE_12BIT_LOGARITHMIC;
- else
+ } else if (crtc_state->uapi.gamma_mode_type ==
+GAMMA_MODE_LOGARITHMIC_12BIT) {
+ if (crtc_state->uapi.advance_gamma_mode_active)
+ gamma_mode |= GAMMA_MODE_MODE_12BIT_LOGARITHMIC;
+ else
+ gamma_mode |= GAMMA_MODE_MODE_10BIT;
+ } else {
gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
+ }
return gamma_mode;
}
--
2.26.2
___
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[Intel-gfx] [PATCH 4/9] drm/i915/xelpd: Attach gamma mode property
Attach the gamma mode property to allow userspace set the gamma mode
and provide the luts for the same.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 12cacd3aeead..cae96fbec1a7 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2458,6 +2458,7 @@ void intel_color_init(struct intel_crtc *crtc)
"logarithmic gamma",
d13_logarithmic_gamma,
sizeof(d13_logarithmic_gamma));
+ drm_crtc_attach_gamma_mode_property(&crtc->base);
} else if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.color_check = icl_color_check;
} else if (DISPLAY_VER(dev_priv) >= 10) {
--
2.26.2
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[Intel-gfx] [PATCH 1/9] drm: Add gamma mode property
Add a gamma mode property to enable various kind of
gamma modes supported by platforms like: Interpolated, Split,
Multi Segmented, Logarithmic etc. Userspace can get this property
and should be able to get the platform capabilities wrt various
gamma modes possible and the possible ranges.
It can select one of the modes exposed as blob_id as an
enum and set the respective mode.
It can then create the LUT and send it to driver using
already available GAMMA_LUT property as blob.
Note: This is based on design by Ville and is being carried forward
based on his original idea.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_uapi.c | 5 +++
drivers/gpu/drm/drm_color_mgmt.c | 75 +++
include/drm/drm_color_mgmt.h | 8
include/drm/drm_crtc.h| 14 ++
include/uapi/drm/drm_mode.h | 43 ++
5 files changed, 145 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 438e9585b225..a5470a0ebbe6 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -471,6 +471,9 @@ static int drm_atomic_crtc_set_property(struct drm_crtc
*crtc,
&replaced);
state->color_mgmt_changed |= replaced;
return ret;
+ } else if (property == crtc->gamma_mode_property) {
+ state->gamma_mode = val;
+ state->color_mgmt_changed |= true;
} else if (property == config->prop_out_fence_ptr) {
s32 __user *fence_ptr = u64_to_user_ptr(val);
@@ -510,6 +513,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
*val = (state->mode_blob) ? state->mode_blob->base.id : 0;
else if (property == config->prop_vrr_enabled)
*val = state->vrr_enabled;
+ else if (property == crtc->gamma_mode_property)
+ *val = state->gamma_mode;
else if (property == config->degamma_lut_property)
*val = (state->degamma_lut) ? state->degamma_lut->base.id : 0;
else if (property == config->ctm_property)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index bb14f488c8f6..766d0fd14daa 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -187,6 +187,81 @@ void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
}
EXPORT_SYMBOL(drm_crtc_enable_color_mgmt);
+void drm_crtc_attach_gamma_mode_property(struct drm_crtc *crtc)
+{
+ if (!crtc->gamma_mode_property)
+ return;
+
+ drm_object_attach_property(&crtc->base,
+ crtc->gamma_mode_property, 0);
+}
+EXPORT_SYMBOL(drm_crtc_attach_gamma_mode_property);
+
+int drm_color_create_gamma_mode_property(struct drm_crtc *crtc,
+int num_values)
+{
+ struct drm_property *prop;
+
+ prop = drm_property_create(crtc->dev,
+ DRM_MODE_PROP_ENUM,
+ "GAMMA_MODE", num_values);
+ if (!prop)
+ return -ENOMEM;
+
+ crtc->gamma_mode_property = prop;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_color_create_gamma_mode_property);
+
+int drm_color_add_gamma_mode_range(struct drm_crtc *crtc,
+ const char *name,
+ const struct drm_color_lut_range *ranges,
+ size_t length)
+{
+ struct drm_property_blob *blob;
+ struct drm_property *prop;
+ int num_ranges = length / sizeof(ranges[0]);
+ int i, ret, num_types_0;
+
+ prop = crtc->gamma_mode_property;
+ if (!prop)
+ return -EINVAL;
+
+ if (length == 0 && name)
+ return drm_property_add_enum(prop, 0, name);
+
+ if (WARN_ON(length == 0 || length % sizeof(ranges[0]) != 0))
+ return -EINVAL;
+
+ num_types_0 = hweight8(ranges[0].flags & (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_DEGAMMA));
+ if (num_types_0 == 0)
+ return -EINVAL;
+
+ for (i = 1; i < num_ranges; i++) {
+ int num_types = hweight8(ranges[i].flags & (DRM_MODE_LUT_GAMMA |
+DRM_MODE_LUT_DEGAMMA));
+
+ /* either all ranges have DEGAMMA|GAMMA or none have it */
+ if (num_types_0 != num_types)
+ return -EINVAL;
+ }
+
+ blob = drm_property_create_blob(crtc->dev, length, ranges);
+ if (IS_ERR(blob))
+ return PTR_ERR(blob);
+
+ ret = drm_property_add_enum(prop, blob->base.id, name);
+ if (ret) {
+ drm_property_blob_put(blob);
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_color_add_gamma_mode_range);
+
/**
* drm_mode_crtc_set_gamma_size - set the gamma table size
* @crtc: CRTC to set the gam
[Intel-gfx] [PATCH 0/9] Enhance pipe color support for multi segmented luts
Modern hardwares have multi segmented lut approach to prioritize the darker regions of the spectrum. This series introduces a new UAPI to define the lut ranges supported by the respective hardware. This also enables Pipe Color Management Support for Intel's XE_LPD hw. Enable Support for Pipe Degamma with the increased lut samples supported by hardware. This also adds support for newly introduced Logarithmic Gamma for XE_LPD. Also added the gamma readout support. The Logarithmic gamma implementation on XE_LPD is non linear and adds 25 segments with non linear lut samples in each segment. The expectation is userspace will create the luts as per this distribution and pass the final samples to driver to be programmed in hardware. +-+--+ | x | 2 pow x segment|No of Entries | | 0 | 1 | | 0 | 1 | 1 | | 1 | 2 | 2 | | 2 | 4 | 2 | | 3 | 8 | 2 | | 4 | 16 | 2 | | 5 | 32 | 4 | | 6 | 64 | 4 | | 7 | 128| 4 | | 8 | 256| 8 | | 9 | 512| 8 | | 10 | 1024 | 8 | | 11 | 2048 | 16 | | 12 | 4096 | 16 | | 13 | 8192 | 16 | | 14 | 16384 | 32 | | 15 | 32768 | 32 | | 16 | 65536 | 64 | | 17 | 131072 | 64 | | 18 | 262144 | 64 | | 19 | 524288 | 32 | | 20 | 1048576| 32 | | 21 | 2097152| 32 | | 22 | 4194304| 32 | | 23 | 8388608| 32 | | 24 | 16777216 | 1 | | | Total Entries | 511| -+-++ Credits: Special mention and credits to Ville Syrjala for coming up with a design for this feature and inputs. This series is based on his original design. Note: Userspace support for this new UAPI will be done on Chrome and plan is to get this supported on mutter as well. We will notify the list once we have that ready for review. Uma Shankar (9): drm: Add gamma mode property drm/i915/xelpd: Define color lut range structure drm/i915/xelpd: Add support for Logarithmic gamma mode drm/i915/xelpd: Attach gamma mode property drm: Add Client Cap for advance gamma mode drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode drm/i915/xelpd: Enable Pipe Degamma drm/i915/xelpd: Add Pipe Color Lut caps to platform config drm/i915/xelpd: Enable XE_LPD Gamma Lut readout drivers/gpu/drm/drm_atomic_uapi.c | 8 + drivers/gpu/drm/drm_color_mgmt.c | 75 drivers/gpu/drm/drm_ioctl.c| 5 + drivers/gpu/drm/i915/display/intel_color.c | 454 - drivers/gpu/drm/i915/i915_pci.c| 3 +- drivers/gpu/drm/i915/i915_reg.h| 7 + include/drm/drm_atomic.h | 1 + include/drm/drm_color_mgmt.h | 8 + include/drm/drm_crtc.h | 25 ++ include/drm/drm_file.h | 8 + include/uapi/drm/drm.h | 8 + include/uapi/drm/drm_mode.h| 43 ++ 12 files changed, 630 insertions(+), 15 deletions(-) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/9] drm/i915/xelpd: Enable Pipe Degamma
Enable Pipe Degamma for XE_LPD. Extend the legacy implementation
to incorparate the extended lut size for XE_LPD.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 18b51b9cc2aa..a8b771f22880 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -829,6 +829,12 @@ static void glk_load_degamma_lut(const struct
intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
+ u32 extended_lut_size = 0;
+
+ if (DISPLAY_VER(dev_priv) >= 13)
+ extended_lut_size = 131;
+ else
+ extended_lut_size = 35;
/*
* When setting the auto-increment bit, the hardware seems to
@@ -841,8 +847,8 @@ static void glk_load_degamma_lut(const struct
intel_crtc_state *crtc_state)
for (i = 0; i < lut_size; i++) {
/*
-* First 33 entries represent range from 0 to 1.0
-* 34th and 35th entry will represent extended range
+* First lut_size entries represent range from 0 to 1.0
+* 3 additional lut entries will represent extended range
* inputs 3.0 and 7.0 respectively, currently clamped
* at 1.0. Since the precision is 16bit, the user
* value can be directly filled to register.
@@ -858,7 +864,7 @@ static void glk_load_degamma_lut(const struct
intel_crtc_state *crtc_state)
}
/* Clamp values > 1.0. */
- while (i++ < 35)
+ while (i++ < extended_lut_size)
intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/9] drm: Add Client Cap for advance gamma mode
Introduced a client cap for advance cap mode capability. Userspace
should set this to get to be able to use the new gamma_mode property.
If this is not set, driver will work in legacy mode.
Note: This is suggested by Ville and based on his idea, the new
gamma mode handling is designed.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_uapi.c | 3 +++
drivers/gpu/drm/drm_ioctl.c | 5 +
include/drm/drm_atomic.h | 1 +
include/drm/drm_crtc.h| 8
include/drm/drm_file.h| 8
include/uapi/drm/drm.h| 8
6 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index a5470a0ebbe6..7ee35bc14455 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -1036,6 +1036,8 @@ int drm_atomic_set_property(struct drm_atomic_state
*state,
break;
}
+ crtc_state->advance_gamma_mode_active =
+ state->advance_gamma_mode_active;
ret = drm_atomic_crtc_set_property(crtc,
crtc_state, prop, prop_value);
break;
@@ -1372,6 +1374,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
state->acquire_ctx = &ctx;
state->allow_modeset = !!(arg->flags & DRM_MODE_ATOMIC_ALLOW_MODESET);
+ state->advance_gamma_mode_active = file_priv->advance_gamma_mode_active;
retry:
copied_objs = 0;
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 53d314103a37..d51f72213882 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -361,6 +361,11 @@ drm_setclientcap(struct drm_device *dev, void *data,
struct drm_file *file_priv)
return -EINVAL;
file_priv->writeback_connectors = req->value;
break;
+ case DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES:
+ if (req->value > 1)
+ return -EINVAL;
+ file_priv->advance_gamma_mode_active = req->value;
+ break;
default:
return -EINVAL;
}
diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
index ac5a28eff2c8..5a398a249c80 100644
--- a/include/drm/drm_atomic.h
+++ b/include/drm/drm_atomic.h
@@ -379,6 +379,7 @@ struct drm_atomic_state {
* states.
*/
bool duplicated : 1;
+ bool advance_gamma_mode_active : 1;
struct __drm_planes_state *planes;
struct __drm_crtcs_state *crtcs;
int num_connector;
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 5a594f134a81..f4339fbad086 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -170,6 +170,11 @@ struct drm_crtc_state {
*/
bool color_mgmt_changed : 1;
+ /**
+* This is to indicate advance gamma mode support
+*/
+ bool advance_gamma_mode_active : 1;
+
/**
* @no_vblank:
*
@@ -1036,6 +1041,9 @@ struct drm_crtc {
*/
bool enabled;
+ /** To handle advance gamma mode support */
+ bool advance_gamma_mode_active : 1;
+
/**
* @mode:
*
diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h
index b81b3bfb08c8..4af3e1a2a158 100644
--- a/include/drm/drm_file.h
+++ b/include/drm/drm_file.h
@@ -201,6 +201,14 @@ struct drm_file {
*/
bool writeback_connectors;
+ /**
+* This is to enable advance gamma modes using
+* gamma_mode property
+*
+* True if client understands advance gamma
+*/
+ bool advance_gamma_mode_active : 1;
+
/**
* @was_master:
*
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 67b94bc3c885..661efdf0c969 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -816,6 +816,14 @@ struct drm_get_cap {
*/
#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS5
+/**
+ * Add support for advance gamma mode UAPI
+ * If set to 1, DRM will enable advance gamma mode
+ * UAPI to process the gamma mode based on extended
+ * range and segments.
+ */
+#define DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES 6
+
/* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
struct drm_set_client_cap {
__u64 capability;
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 8/9] drm/i915/xelpd: Add Pipe Color Lut caps to platform config
XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for
extended range. It has 511 entries for gamma with additional 2 entries
for extended range.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 97c98f4fb265..844d08e37ec5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -947,7 +947,8 @@ static const struct intel_device_info adl_s_info = {
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
.dbuf.size = 4096, \
- .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
BIT(DBUF_S4)
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
BIT(DBUF_S4), \
+ .color = { .degamma_lut_size = 128, .gamma_lut_size = 513 }
static const struct intel_device_info adl_p_info = {
GEN12_FEATURES,
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 9/9] drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
Enable support for Logarithmic gamma readout for XE_LPD.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 72 ++
drivers/gpu/drm/i915/i915_reg.h| 6 ++
2 files changed, 78 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index a8b771f22880..1238fe05b358 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -486,6 +486,17 @@ static void icl_lut_multi_seg_pack(struct drm_color_lut
*entry, u32 ldw, u32 udw
REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
}
+static void d13_lut_logarithmic_pack(struct drm_color_lut *entry,
+u32 ldw, u32 udw)
+{
+ entry->red = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_RED_UDW_MASK, udw) << 6
|
+
REG_FIELD_GET(PAL_PREC_LOGARITHMIC_RED_LDW_MASK, ldw);
+ entry->green = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_GREEN_UDW_MASK, udw)
<< 6 |
+
REG_FIELD_GET(PAL_PREC_LOGARITHMIC_GREEN_LDW_MASK, ldw);
+ entry->blue = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_BLUE_UDW_MASK, udw) <<
6 |
+
REG_FIELD_GET(PAL_PREC_LOGARITHMIC_BLUE_LDW_MASK, ldw);
+}
+
static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -2434,6 +2445,66 @@ static void d13_load_luts(const struct intel_crtc_state
*crtc_state)
intel_dsb_commit(crtc_state);
}
+static struct drm_property_blob *
+d13_read_lut_logarithmic(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *lut;
+ u32 gamma_max_val = 0x;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ lut = blob->data;
+
+ intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
+ PAL_PREC_AUTO_INCREMENT);
+
+ for (i = 0; i < lut_size - 3; i++) {
+ u32 ldw = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
+ u32 udw = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
+
+ d13_lut_logarithmic_pack(&lut[i], ldw, udw);
+ }
+
+ /* All the extended ranges are now limited to last value of 1.0 */
+ while (i < lut_size) {
+ lut[i].red = gamma_max_val;
+ lut[i].green = gamma_max_val;
+ lut[i].blue = gamma_max_val;
+ i++;
+ };
+
+ intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
+
+ return blob;
+}
+
+static void d13_read_luts(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
+ return;
+
+ switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
+ case GAMMA_MODE_MODE_8BIT:
+ crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
+ break;
+ case GAMMA_MODE_MODE_12BIT_LOGARITHMIC:
+ crtc_state->hw.gamma_lut = d13_read_lut_logarithmic(crtc);
+ break;
+ default:
+ crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc,
PAL_PREC_INDEX_VALUE(0));
+ }
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2488,6 +2559,7 @@ void intel_color_init(struct intel_crtc *crtc)
if (DISPLAY_VER(dev_priv) >= 13) {
dev_priv->display.load_luts = d13_load_luts;
+ dev_priv->display.read_luts = d13_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
dev_priv->display.read_luts = icl_read_luts;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 957f97edf035..dc10b5e2ff3c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7750,6 +7750,12 @@ enum {
#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
#define GAMMA_MODE_MODE_12BIT_LOGARITHMIC (3 << 0) /* D13+ + */
+#define PAL_PREC_LOGARITHMIC_RED_LDW_MASK REG_GENMASK(29, 24)
+#define PAL_PREC_LOGARITHMIC_RED_UDW_MASK REG_GENMASK(29, 20)
+#define PAL_PREC_LOGARITHMIC_GREEN_LDW_MASK REG_GENMASK(19, 14)
+#define PAL_PREC_LOGARITHMIC_GREEN_UDW_MASK REG_GENMASK(19, 10)
+#define PAL_PREC_LOGA
Re: [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
On 27/05/2021 11:27, Daniel Vetter wrote:
On Thu, May 27, 2021 at 11:22:16AM +0100, Tvrtko Ursulin wrote:
On 27/05/2021 11:13, Daniel Vetter wrote:
On Wed, May 26, 2021 at 11:20:13AM +0100, Tvrtko Ursulin wrote:
On 25/05/2021 15:47, Daniel Vetter wrote:
On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote:
+ dri-devel as per process
On 25/05/2021 14:55, Tejas Upadhyay wrote:
v2: Only declare timeslicing if we can safely preempt userspace.
Commit message got butchered up somehow so you'll need to fix that at some
point.
Regards,
Tvrtko
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 +
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 3cca7ea2d6ea..12d165566ed2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915)
MAP(HAS_PREEMPTION, PREEMPTION),
MAP(HAS_SEMAPHORES, SEMAPHORES),
MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS),
+ MAP(TIMESLICE_BIT, TIMESLICING),
#undef MAP
};
struct intel_engine_cs *engine;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index c2c7759b7d2e..af2212d6113c 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_PREEMPTION(1ul << 2)
#define I915_SCHEDULER_CAP_SEMAPHORES(1ul << 3)
#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
+#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5)
Since this is uapi I think we should at least have some nice kerneldoc
that explains what exactly this is, what for (link to userspace) and all
that. Ideally also minimally filing in the gaps in our uapi docs for stuff
this references.
IIUC there is no userspace apart from IGT needing it not to fail scheduling
tests on ADL.
Current tests use "has preemption + has semaphores" as a proxy to answer the
"does the kernel support timeslicing" question. This stops working with the
Guc backend because GuC decided not to support semaphores (for reasons yet
unknown, see other thread), so explicit "has timeslicing" flag is needed in
order for tests to know that GuC is supposed to support timeslicing, even if
it doesn't use semaphores for inter-ring synchronisation.
Since this if for igt only: Cant we do just extend the check in igt with
an || GEN >= 12? I really hope that our future hw will continue to support
timeslicing ...
Not the gen 12 check, but possible I think. Explicit feature test would be
better, but if definitely not allowed then along the lines of:
has_timeslicing =
(has_preemption && has_semaphores) || uses_guc_submission;
That works too. Otoh what exactly is the "uses guc submission" flag and
why do we have that? I've seen media use it as a stand-in for "does the
kernel want bonded or parallel ctx?". Maybe another thing to check.
Another option, if you really think the feature flag is the best approach
(because future hw will drop timeslicing for some reason), then debugfs is
the place of igt-only api.
Maybe check and potentially remove all I915_SCHEDULER_CAP_.. flags. It
could be another easy pickings with a lot of IGT work type endeavour.
Regards,
Tvrtko
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[Intel-gfx] [PATCH 00/21] Add Support for Plane Color Lut and CSC features
This is how a typical display color hardware pipeline looks like: +---+ |RAM| | +--++-++-+ | | | FB 1 || FB 2 || FB N| | | +--++-++-+ | +---+ | Plane Color Hardware Block | ++ | +---v-+ +---v---+ +---v--+ | | | Plane A | | Plane B | | Plane N | | | | DeGamma | | Degamma | | Degamma | | | +---+-+ +---+---+ +---+--+ | | | | || | +---v-+ +---v---+ +---v--+ | | |Plane A | | Plane B | | Plane N | | | |CSC/CTM | | CSC/CTM | | CSC/CTM | | | +---+-+ ++--+ ++-+ | | | | | | | +---v-+ +v--+ +v-+ | | | Plane A | | Plane B | | Plane N | | | | Gamma | | Gamma | | Gamma| | | +---+-+ ++--+ ++-+ | | | | | | ++ +--v--v---v---| || || || Pipe Blender|| +++ ||| |+---v--+ | || Pipe DeGamma| | || | | |+---+--+ | ||Pipe Color | |+---v--+ Hardware| || Pipe CSC/CTM| | || | | |+---+--+ | ||| |+---v--+ | || Pipe Gamma | | || | | |+---+--+ | ||| +-+ | v Pipe Output This patch series adds properties for plane color features. It adds properties for degamma used to linearize data and CSC used for gamut conversion. It also includes Gamma support used to again non-linearize data as per panel supported color space. These can be utilize by user space to convert planes from one format to another, one color space to another etc. Userspace can take smart blending decisions and utilize these hardware supported plane color features to get accurate color profile. The same can help in consistent color quality from source to panel taking advantage of advanced color features in hardware. These patches add the property interfaces and enable helper functions. This series adds Intel's XE_LPD hw specific plane gamma feature. We can build up and add other platform/hardware specific implementation on top of this series. Credits: Special mention and credits to Ville Syrjala for coming up with a design for this feature and inputs. This series is based on his original design and idea. Note: Userspace support for this new UAPI will be done on Chrome. We will notify the list once we have that ready for review. ToDo: State readout for this feature will be added next. Uma Shankar (21): drm: Add Enhanced Gamma and color lut range attributes drm: Add Plane Degamma Mode property drm: Add Plane Degamma Lut property drm/i915/xelpd: Define Degamma Lut range struct for HDR planes drm/i915/xelpd: Add register definitions for Plane Degamma drm/i915/xelpd: Enable plane color features drm/i915/xelpd: Add color capabilities of SDR planes drm/i915/xelpd: Program Plane Degamma Registers drm/i915/xelpd: Add plane color check to glk_plane_color_ctl drm/i915/xelpd: Initialize plane color features drm/i915/xelpd: Load plane color luts from atomic flip drm: Add Plane CTM property drm: Add helper to attach Plane ctm property drm/i915/xelpd: Define Plane CSC Registers drm/i915/xelpd: Enable Plane CSC drm: Add Plane Gamma Mode property drm: Add Plane Gamma Lut property drm/i915/xelpd: Define and Initialize Plane Gamma Lut range drm/i915/xelpd: Add register definitions for Plane Gamma drm/i915/xelpd: Program Plane Gamma Registers drm/i915/xelpd: Enable plane gamma Documentation/gpu/drm-kms.rst | 90 +++ drivers/gpu/drm/drm_atomic.c | 1 + drivers/gpu/drm/drm_atomic_state_helper.c | 12 + drivers/gpu/drm/drm_atomic_uapi.c | 38 ++ drivers/gpu/drm/drm_color_mgmt.c | 177 +- .../gpu/drm/i915/display/intel_atomic_plane.c | 6 + .../gpu/drm/i915/display/intel_atomic_plane.h | 2 + drivers/gpu/drm/i915/display/intel_color.c| 513 ++ drivers/
[Intel-gfx] [PATCH 01/21] drm: Add Enhanced Gamma and color lut range attributes
Existing LUT precision structure is having only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values.
This also defines a new structure to define color lut ranges,
along with related macro definitions and enums. This will help
describe multi segmented lut ranges in the hardware.
Signed-off-by: Uma Shankar
---
include/uapi/drm/drm_mode.h | 58 +
1 file changed, 58 insertions(+)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 9b6722d45f36..d0ce48d2e732 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -819,6 +819,64 @@ struct hdr_output_metadata {
};
};
+/*
+ * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and means the LUT
+ * can be used for either purpose, but not simultaneously. To expose
+ * modes that support gamma and degamma simultaneously the gamma mode
+ * must declare distinct DRM_MODE_LUT_GAMMA and DRM_MODE_LUT_DEGAMMA
+ * ranges.
+ */
+/* LUT is for gamma (after CTM) */
+#define DRM_MODE_LUT_GAMMA BIT(0)
+/* LUT is for degamma (before CTM) */
+#define DRM_MODE_LUT_DEGAMMA BIT(1)
+/* linearly interpolate between the points */
+#define DRM_MODE_LUT_INTERPOLATE BIT(2)
+/*
+ * the last value of the previous range is the
+ * first value of the current range.
+ */
+#define DRM_MODE_LUT_REUSE_LAST BIT(3)
+/* the curve must be non-decreasing */
+#define DRM_MODE_LUT_NON_DECREASING BIT(4)
+/* the curve is reflected across origin for negative inputs */
+#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5)
+/* the same curve (red) is used for blue and green channels as well */
+#define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6)
+
+struct drm_color_lut_range {
+ /* DRM_MODE_LUT_* */
+ __u32 flags;
+ /* number of points on the curve */
+ __u16 count;
+ /* input/output bits per component */
+ __u8 input_bpc, output_bpc;
+ /* input start/end values */
+ __s32 start, end;
+ /* output min/max values */
+ __s32 min, max;
+};
+
+enum lut_type {
+ LUT_TYPE_DEGAMMA = 0,
+ LUT_TYPE_GAMMA = 1,
+};
+
+/*
+ * Creating 64 bit palette entries for better data
+ * precision. This will be required for HDR and
+ * similar color processing usecases.
+ */
+struct drm_color_lut_ext {
+ /*
+* Data is U32.32 fixed point format.
+*/
+ __u64 red;
+ __u64 green;
+ __u64 blue;
+ __u64 reserved;
+};
+
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
--
2.26.2
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[Intel-gfx] [PATCH 03/21] drm: Add Plane Degamma Lut property
Add Plane Degamma Lut as a blob property. User will calculate
the lut values, create the blob and send it to driver using
this property. Lut calculation will be based on the gamma mode
chosen out of the gamma mode exposed.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_state_helper.c | 4
drivers/gpu/drm/drm_atomic_uapi.c | 10 ++
drivers/gpu/drm/drm_color_mgmt.c | 19 +++
include/drm/drm_plane.h | 14 ++
4 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index f26b03853711..6e358067cb7a 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -312,6 +312,9 @@ void __drm_atomic_helper_plane_duplicate_state(struct
drm_plane *plane,
state->commit = NULL;
state->fb_damage_clips = NULL;
+ if (state->degamma_lut)
+ drm_property_blob_get(state->degamma_lut);
+
state->color_mgmt_changed = false;
}
EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state);
@@ -359,6 +362,7 @@ void __drm_atomic_helper_plane_destroy_state(struct
drm_plane_state *state)
drm_crtc_commit_put(state->commit);
drm_property_blob_put(state->fb_damage_clips);
+ drm_property_blob_put(state->degamma_lut);
}
EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state);
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 40fa05fa33dc..ce3cb65d415e 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -597,6 +597,13 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
state->color_range = val;
} else if (property == plane->degamma_mode_property) {
state->degamma_mode = val;
+ } else if (property == plane->degamma_lut_property) {
+ ret = drm_atomic_replace_property_blob_from_id(dev,
+ &state->degamma_lut,
+ val, -1, sizeof(struct
drm_color_lut_ext),
+ &replaced);
+ state->color_mgmt_changed |= replaced;
+ return ret;
} else if (property == config->prop_fb_damage_clips) {
ret = drm_atomic_replace_property_blob_from_id(dev,
&state->fb_damage_clips,
@@ -665,6 +672,9 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
*val = state->color_range;
} else if (property == plane->degamma_mode_property) {
*val = state->degamma_mode;
+ } else if (property == plane->degamma_lut_property) {
+ *val = (state->degamma_lut) ?
+ state->degamma_lut->base.id : 0;
} else if (property == config->prop_fb_damage_clips) {
*val = (state->fb_damage_clips) ?
state->fb_damage_clips->base.id : 0;
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 085ed0d0db00..29d0fc1e52b5 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -596,6 +596,12 @@ EXPORT_SYMBOL(drm_plane_create_color_properties);
* to query and get the plane degamma color caps and choose the
* appropriate degamma mode and create lut values accordingly
*
+ * degamma_lut_property:
+ * Blob property which allows a userspace to provide LUT values
+ * to apply degamma curve using the h/w plane degamma processing
+ * engine, thereby making the content as linear for further color
+ * processing.
+ *
*/
int drm_plane_create_color_mgmt_properties(struct drm_device *dev,
struct drm_plane *plane,
@@ -610,6 +616,13 @@ int drm_plane_create_color_mgmt_properties(struct
drm_device *dev,
plane->degamma_mode_property = prop;
+ prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
+ "PLANE_DEGAMMA_LUT", 0);
+ if (!prop)
+ return -ENOMEM;
+
+ plane->degamma_lut_property = prop;
+
return 0;
}
EXPORT_SYMBOL(drm_plane_create_color_mgmt_properties);
@@ -621,6 +634,12 @@ void drm_plane_attach_degamma_properties(struct drm_plane
*plane)
drm_object_attach_property(&plane->base,
plane->degamma_mode_property, 0);
+
+ if (!plane->degamma_lut_property)
+ return;
+
+ drm_object_attach_property(&plane->base,
+ plane->degamma_lut_property, 0);
}
EXPORT_SYMBOL(drm_plane_attach_degamma_properties);
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index e476a5939f8e..bbd0033ed1d2 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -244,6 +244,14 @@ struct drm_plane_state {
*/
u32 degamm
[Intel-gfx] [PATCH 02/21] drm: Add Plane Degamma Mode property
Add Plane Degamma Mode as an enum property. Create a helper
function for all plane color management features.
This is an enum property with values as blob_id's and exposes
the various gamma modes supported and the lut ranges. Getting
the blob id in userspace, user can get the mode supported and
also the range of gamma mode supported with number of lut
coefficients. It can then set one of the modes using this
enum property.
Lut values will be sent through separate GAMMA_LUT blob property.
Signed-off-by: Uma Shankar
---
Documentation/gpu/drm-kms.rst | 90 ++
drivers/gpu/drm/drm_atomic.c | 1 +
drivers/gpu/drm/drm_atomic_state_helper.c | 2 +
drivers/gpu/drm/drm_atomic_uapi.c | 4 +
drivers/gpu/drm/drm_color_mgmt.c | 93 ++-
include/drm/drm_mode_object.h | 2 +-
include/drm/drm_plane.h | 23 ++
7 files changed, 212 insertions(+), 3 deletions(-)
diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index 87e5023e3f55..752be545e7d7 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -514,9 +514,99 @@ Damage Tracking Properties
Color Management Properties
---
+Below is how a typical hardware pipeline for color
+will look like:
+
+.. kernel-render:: DOT
+ :alt: Display Color Pipeline
+ :caption: Display Color Pipeline Overview
+
+ digraph "KMS" {
+ node [shape=box]
+
+ subgraph cluster_static {
+ style=dashed
+ label="Display Color Hardware Blocks"
+
+ node [bgcolor=grey style=filled]
+ "Plane Degamma A" -> "Plane CSC/CTM A"
+ "Plane CSC/CTM A" -> "Plane Gamma A"
+ "Pipe Blender" [color=lightblue,style=filled, width=5.25,
height=0.75];
+ "Plane Gamma A" -> "Pipe Blender"
+ "Pipe Blender" -> "Pipe DeGamma"
+ "Pipe DeGamma" -> "Pipe CSC/CTM"
+ "Pipe CSC/CTM" -> "Pipe Gamma"
+ "Pipe Gamma" -> "Pipe Output"
+ }
+
+ subgraph cluster_static {
+ style=dashed
+
+ node [shape=box]
+ "Plane Degamma B" -> "Plane CSC/CTM B"
+ "Plane CSC/CTM B" -> "Plane Gamma B"
+ "Plane Gamma B" -> "Pipe Blender"
+ }
+
+ subgraph cluster_static {
+ style=dashed
+
+ node [shape=box]
+ "Plane Degamma C" -> "Plane CSC/CTM C"
+ "Plane CSC/CTM C" -> "Plane Gamma C"
+ "Plane Gamma C" -> "Pipe Blender"
+ }
+
+ subgraph cluster_fb {
+ style=dashed
+ label="RAM"
+
+ node [shape=box width=1.7 height=0.2]
+
+ "FB 1" -> "Plane Degamma A"
+ "FB 2" -> "Plane Degamma B"
+ "FB 3" -> "Plane Degamma C"
+ }
+ }
+
+In real world usecases,
+
+1. Plane Degamma can be used to linearize a non linear gamma
+encoded framebuffer. This is needed to do any linear math like
+color space conversion. For ex, linearize frames encoded in SRGB
+or by HDR curve.
+
+2. Later Plane CTM block can convert the content to some different
+colorspace. For ex, SRGB to BT2020 etc.
+
+3. Plane Gamma block can be used later to re-apply the non-linear
+curve. This can also be used to apply Tone Mapping for HDR usecases.
+
+All the layers or framebuffers need to be converted to same color
+space and format before blending. The plane color hardware blocks
+can help with this. Once the Data is blended, similar color processing
+can be done on blended output using pipe color hardware blocks.
+
+DRM Properties have been created to define and expose all these
+hardware blocks to userspace. A userspace application (compositor
+or any color app) can use these interfaces and define policies to
+efficiently use the display hardware for such color operations.
+
+Pipe Color Management Properties
+-
+
.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
:doc: overview
+Plane Color Management Properties
+-
+
+.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
+ :doc: Plane Color Properties
+
+.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
+ :doc: export
+
Tile Group Property
---
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index a8bbb021684b..8892d03602f7 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -708,6 +708,7 @@ static void drm_atomic_plane_print_state(struct drm_printer
*p,
drm_get_color_encoding_name(state->color_encoding));
drm_printf(p, "\tcolor-range=%s\n",
drm_get_color_range_name(state->color_range));
+ drm_printf(p, "\tcolor_mgmt_changed=%d\n", state->color_mgmt_changed);
if (plane->funcs->atomic_print_state)
plane->funcs->atomic_print_state(p, state);
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index ddcf5c2c8e6a..
[Intel-gfx] [PATCH 04/21] drm/i915/xelpd: Define Degamma Lut range struct for HDR planes
Define the structure with XE_LPD degamma lut ranges. HDR and SDR
planes have different capabilities, implemented respective
structure for the HDR planes.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 52 ++
1 file changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index dab892d2251b..c735d06a6b54 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2093,6 +2093,58 @@ static void icl_read_luts(struct intel_crtc_state
*crtc_state)
}
}
+ /* FIXME input bpc? */
+__maybe_unused
+static const struct drm_color_lut_range d13_degamma_hdr[] = {
+ /* segment 1 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 128,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = 0, .end = (1 << 24) - 1,
+ .min = 0, .max = (1 << 24) - 1,
+ },
+ /* segment 2 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_REUSE_LAST |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 24) - 1, .end = 1 << 24,
+ .min = 0, .max = (1 << 27) - 1,
+ },
+ /* Segment 3 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_REUSE_LAST |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = 1 << 24, .end = 3 << 24,
+ .min = 0, .max = (1 << 27) - 1,
+ },
+ /* Segment 4 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_REUSE_LAST |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = 3 << 24, .end = 7 << 24,
+ .min = 0, .max = (1 << 27) - 1,
+ },
+};
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
--
2.26.2
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[Intel-gfx] [PATCH 05/21] drm/i915/xelpd: Add register definitions for Plane Degamma
Add macros to define Plane Degamma registers
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 52 +
1 file changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24307c49085f..9431913969f3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -262,6 +262,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
DISPLAY_MMIO_BASE(dev_priv))
+/* Plane Gamma Registers */
+#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
+
#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
#define _MASKED_FIELD(mask, value) ({ \
if (__builtin_constant_p(mask))\
@@ -11300,6 +11303,55 @@ enum skl_power_gate {
_PAL_PREC_MULTI_SEG_DATA_A, \
_PAL_PREC_MULTI_SEG_DATA_B)
+/* Display13 Plane Degmma Reg */
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A 0x701d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B 0x711d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A 0x702d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B 0x712d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, \
+
_PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, \
+
_PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B)
+#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) \
+ _MMIO_PLANE_GAMC(plane, i,
_PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A 0x701d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B 0x711d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A 0x702d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B 0x712d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, \
+
_PLANE_PRE_CSC_GAMC_DATA_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, \
+
_PLANE_PRE_CSC_GAMC_DATA_ENH_2_B)
+#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i)\
+ _MMIO_PLANE_GAMC(plane, i,
_PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_INDEX_1_A 0x704d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_1_B 0x714d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_2_A 0x705d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_2_B 0x715d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_INDEX_1_A, \
+ _PLANE_PRE_CSC_GAMC_INDEX_1_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_INDEX_2_A, \
+ _PLANE_PRE_CSC_GAMC_INDEX_2_B)
+#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) \
+ _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_INDEX_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_DATA_1_A 0x704d4
+#define _PLANE_PRE_CSC_GAMC_DATA_1_B 0x714d4
+#define _PLANE_PRE_CSC_GAMC_DATA_2_A 0x705d4
+#define _PLANE_PRE_CSC_GAMC_DATA_2_B 0x715d4
+#define _PLANE_PRE_CSC_GAMC_DATA_1(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_DATA_1_A, \
+ _PLANE_PRE_CSC_GAMC_DATA_1_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_2(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_DATA_2_A, \
+ _PLANE_PRE_CSC_GAMC_DATA_2_B)
+#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i)\
+ _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_DATA_2(pipe))
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
--
2.26.2
___
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[Intel-gfx] [PATCH 06/21] drm/i915/xelpd: Enable plane color features
Enable and initialize plane color features.
Also initialize the color features of HDR planes.
Signed-off-by: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 22 +-
drivers/gpu/drm/i915/display/intel_color.h | 2 ++
drivers/gpu/drm/i915/i915_drv.h| 3 +++
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index c735d06a6b54..00a0d45632fe 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -25,6 +25,7 @@
#include "intel_color.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include
#define CTM_COEFF_SIGN (1ULL << 63)
@@ -2094,7 +2095,6 @@ static void icl_read_luts(struct intel_crtc_state
*crtc_state)
}
/* FIXME input bpc? */
-__maybe_unused
static const struct drm_color_lut_range d13_degamma_hdr[] = {
/* segment 1 */
{
@@ -2145,6 +2145,26 @@ static const struct drm_color_lut_range
d13_degamma_hdr[] = {
},
};
+int intel_plane_color_init(struct drm_plane *plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->dev);
+ int ret = 0;
+
+ if (DISPLAY_VER(dev_priv) >= 13) {
+ drm_plane_create_color_mgmt_properties(plane->dev, plane, 2);
+ ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "no
degamma",
+ NULL, 0,
+
LUT_TYPE_DEGAMMA);
+ ret = drm_plane_color_add_gamma_degamma_mode_range(plane,
"plane degamma",
+
d13_degamma_hdr,
+
sizeof(d13_degamma_hdr),
+
LUT_TYPE_DEGAMMA);
+ drm_plane_attach_degamma_properties(plane);
+ }
+
+ return ret;
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_color.h
b/drivers/gpu/drm/i915/display/intel_color.h
index 173727aaa24d..b8850bb1b0c9 100644
--- a/drivers/gpu/drm/i915/display/intel_color.h
+++ b/drivers/gpu/drm/i915/display/intel_color.h
@@ -10,6 +10,7 @@
struct intel_crtc_state;
struct intel_crtc;
+struct drm_plane;
struct drm_property_blob;
void intel_color_init(struct intel_crtc *crtc);
@@ -21,5 +22,6 @@ int intel_color_get_gamma_bit_precision(const struct
intel_crtc_state *crtc_stat
bool intel_color_lut_equal(struct drm_property_blob *blob1,
struct drm_property_blob *blob2,
u32 gamma_mode, u32 bit_precision);
+int intel_plane_color_init(struct drm_plane *plane);
#endif /* __INTEL_COLOR_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0f6d27da69ac..f955f039edba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -326,6 +326,9 @@ struct drm_i915_display_funcs {
*/
void (*load_luts)(const struct intel_crtc_state *crtc_state);
void (*read_luts)(struct intel_crtc_state *crtc_state);
+ /* Add Plane Color callbacks */
+ void (*load_plane_csc_matrix)(const struct drm_plane_state
*plane_state);
+ void (*load_plane_luts)(const struct drm_plane_state *plane_state);
};
struct intel_dmc {
--
2.26.2
___
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[Intel-gfx] [PATCH 07/21] drm/i915/xelpd: Add color capabilities of SDR planes
Add the Color capabilities of SDR planes.
Signed-off-by: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 67 --
1 file changed, 63 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 00a0d45632fe..4908e825f3cc 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -25,6 +25,7 @@
#include "intel_color.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_sprite.h"
#include
#define CTM_COEFF_SIGN (1ULL << 63)
@@ -2145,6 +2146,57 @@ static const struct drm_color_lut_range
d13_degamma_hdr[] = {
},
};
+ /* FIXME input bpc? */
+static const struct drm_color_lut_range d13_degamma_sdr[] = {
+ /* segment 1 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 32,
+ .input_bpc = 16, .output_bpc = 16,
+ .start = 0, .end = (1 << 16) - (1 << 16) / 33,
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 2 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_REUSE_LAST |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 1,
+ .input_bpc = 16, .output_bpc = 16,
+ .start = (1 << 16) - (1 << 16) / 33, .end = 1 << 16,
+ .min = 0, .max = 1 << 16,
+ },
+ /* Segment 3 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_REUSE_LAST |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 1,
+ .input_bpc = 16, .output_bpc = 16,
+ .start = 1 << 16, .end = 3 << 16,
+ .min = 0, .max = (8 << 16) - 1,
+ },
+ /* Segment 4 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_REUSE_LAST |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 1,
+ .input_bpc = 16, .output_bpc = 16,
+ .start = 3 << 16, .end = 7 << 16,
+ .min = 0, .max = (8 << 16) - 1,
+ },
+};
+
int intel_plane_color_init(struct drm_plane *plane)
{
struct drm_i915_private *dev_priv = to_i915(plane->dev);
@@ -2155,10 +2207,17 @@ int intel_plane_color_init(struct drm_plane *plane)
ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "no
degamma",
NULL, 0,
LUT_TYPE_DEGAMMA);
- ret = drm_plane_color_add_gamma_degamma_mode_range(plane,
"plane degamma",
-
d13_degamma_hdr,
-
sizeof(d13_degamma_hdr),
-
LUT_TYPE_DEGAMMA);
+ if (icl_is_hdr_plane(dev_priv, to_intel_plane(plane)->id))
+ ret =
drm_plane_color_add_gamma_degamma_mode_range(plane, "plane degamma",
+
d13_degamma_hdr,
+
sizeof(d13_degamma_hdr),
+
LUT_TYPE_DEGAMMA);
+ else
+ ret =
drm_plane_color_add_gamma_degamma_mode_range(plane,
+
"plane degamma",
+
d13_degamma_sdr,
+
sizeof(d13_degamma_sdr),
+
LUT_TYPE_DEGAMMA);
drm_plane_attach_degamma_properties(plane);
}
--
2.26.2
___
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[Intel-gfx] [PATCH 08/21] drm/i915/xelpd: Program Plane Degamma Registers
Extract the LUT and program plane degamma registers.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 116 +
drivers/gpu/drm/i915/i915_reg.h| 2 +
2 files changed, 118 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 4908e825f3cc..4e5733573fd8 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -126,6 +126,29 @@ static bool crtc_state_is_legacy_gamma(const struct
intel_crtc_state *crtc_state
lut_is_legacy(crtc_state->hw.gamma_lut);
}
+/*
+ * Added to accommodate enhanced LUT precision.
+ * Max LUT precision is 32 bits.
+ */
+static u64 drm_color_lut_extract_ext(u64 user_input, u32 bit_precision)
+{
+ u64 val = user_input & 0x;
+ u32 max;
+
+ if (bit_precision > 32)
+ return 0;
+
+ max = 0x >> (32 - bit_precision);
+ /* Round only if we're not using full precision. */
+ if (bit_precision < 32) {
+ val += 1UL << (32 - bit_precision - 1);
+ val >>= 32 - bit_precision;
+ }
+
+ return ((user_input & 0x) |
+ clamp_val(val, 0, max));
+}
+
/*
* When using limited range, multiply the matrix given by userspace by
* the matrix that we would use for the limited range.
@@ -2197,6 +2220,97 @@ static const struct drm_color_lut_range
d13_degamma_sdr[] = {
},
};
+static void d13_program_plane_degamma_lut(const struct drm_plane_state *state,
+ struct drm_color_lut_ext *degamma_lut,
+ u32 offset)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ u32 i, lut_size;
+
+ if (icl_is_hdr_plane(dev_priv, plane)) {
+ lut_size = 128;
+
+ intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe,
plane, 0),
+ PLANE_PAL_PREC_AUTO_INCREMENT);
+
+ if (degamma_lut) {
+ for (i = 0; i < lut_size; i++) {
+ u64 word =
drm_color_lut_extract_ext(degamma_lut[i].green, 24);
+ u32 lut_val = (word & 0xff);
+
+ intel_de_write(dev_priv,
PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ lut_val);
+ }
+
+ /* Program the max register to clamp values > 1.0. */
+ while (i < 131)
+ intel_de_write(dev_priv,
PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ degamma_lut[i++].green);
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+
+ intel_de_write(dev_priv,
PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
+ }
+
+ do {
+ intel_de_write(dev_priv,
PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ 1 << 24);
+ } while (i++ < 130);
+ }
+
+ intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe,
plane, 0), 0);
+ } else {
+ lut_size = 32;
+
+ /*
+* First 3 planes are HDR, so reduce by 3 to get to the right
+* SDR plane offset
+*/
+ plane = plane - 3;
+
+ intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_INDEX(pipe, plane,
0),
+ PLANE_PAL_PREC_AUTO_INCREMENT);
+
+ if (degamma_lut) {
+ for (i = 0; i < lut_size; i++)
+ intel_de_write(dev_priv,
PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ degamma_lut[i].green);
+ /* Program the max register to clamp values > 1.0. */
+ while (i < 35)
+ intel_de_write(dev_priv,
PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ degamma_lut[i++].green);
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 16) - 1)) / (lut_size - 1);
+
+ intel_de_write(dev_priv,
PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), v);
+ }
+
+ do {
+ intel_de_write(dev_priv,
PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ 1
[Intel-gfx] [PATCH 09/21] drm/i915/xelpd: Add plane color check to glk_plane_color_ctl
Extended glk_plane_color_ctl to have plane color checks. This helps
enabling the degamma or gamma block based on user inputs.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 92a4fd508e92..ae439dca4b3c 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -960,6 +960,11 @@ static u32 glk_plane_color_ctl(const struct
intel_crtc_state *crtc_state,
u32 plane_color_ctl = 0;
plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
+
+ /* FIXME needs hw.degamma_lut */
+ if (plane_state->uapi.degamma_lut)
+ plane_color_ctl |= PLANE_PRE_CSC_GAMMA_ENABLE;
+
plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
--
2.26.2
___
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[Intel-gfx] [PATCH 10/21] drm/i915/xelpd: Initialize plane color features
Initialize plane color features for XE_LPD. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_atomic_plane.h | 1 + drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h index dc4d05e75e1c..c809f522a710 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h @@ -65,5 +65,6 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, bool can_position); void intel_plane_set_invisible(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state); +int intel_plane_color_init(struct drm_plane *plane); #endif /* __INTEL_ATOMIC_PLANE_H__ */ diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index ae439dca4b3c..aadb984fdf77 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2184,6 +2184,8 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, BIT(DRM_SCALING_FILTER_DEFAULT) | BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); + intel_plane_color_init(&plane->base); + drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); return plane; -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/21] drm/i915/xelpd: Load plane color luts from atomic flip
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 3 +++
drivers/gpu/drm/i915/display/intel_atomic_plane.h | 1 +
drivers/gpu/drm/i915/display/intel_color.c| 9 +
3 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 36f52a1d7552..5de9c98beaf6 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -513,6 +513,9 @@ void skl_update_planes_on_crtc(struct intel_atomic_state
*state,
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
+ if (new_plane_state->uapi.color_mgmt_changed)
+ intel_color_load_plane_luts(&new_plane_state->uapi);
+
if (new_plane_state->uapi.visible ||
new_plane_state->planar_slave) {
intel_update_plane(plane, new_crtc_state,
new_plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index c809f522a710..1ba3b524cee2 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -66,5 +66,6 @@ int intel_atomic_plane_check_clipping(struct
intel_plane_state *plane_state,
void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
int intel_plane_color_init(struct drm_plane *plane);
+void intel_color_load_plane_luts(const struct drm_plane_state *plane_state);
#endif /* __INTEL_ATOMIC_PLANE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 4e5733573fd8..6d57a47d8a60 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -22,6 +22,7 @@
*
*/
+#include "intel_atomic_plane.h"
#include "intel_color.h"
#include "intel_de.h"
#include "intel_display_types.h"
@@ -2311,6 +2312,14 @@ static void d13_plane_load_luts(const struct
drm_plane_state *plane_state)
}
}
+void intel_color_load_plane_luts(const struct drm_plane_state *plane_state)
+{
+ struct drm_device *dev = plane_state->plane->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ dev_priv->display.load_plane_luts(plane_state);
+}
+
int intel_plane_color_init(struct drm_plane *plane)
{
struct drm_i915_private *dev_priv = to_i915(plane->dev);
--
2.26.2
___
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[Intel-gfx] [PATCH 12/21] drm: Add Plane CTM property
Add a blob property for plane CSC usage.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_state_helper.c | 3 +++
drivers/gpu/drm/drm_atomic_uapi.c | 10 ++
drivers/gpu/drm/drm_color_mgmt.c | 11 +++
include/drm/drm_plane.h | 15 +++
4 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index 6e358067cb7a..fafb8af1c9cb 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -314,6 +314,8 @@ void __drm_atomic_helper_plane_duplicate_state(struct
drm_plane *plane,
if (state->degamma_lut)
drm_property_blob_get(state->degamma_lut);
+ if (state->ctm)
+ drm_property_blob_get(state->ctm);
state->color_mgmt_changed = false;
}
@@ -363,6 +365,7 @@ void __drm_atomic_helper_plane_destroy_state(struct
drm_plane_state *state)
drm_property_blob_put(state->fb_damage_clips);
drm_property_blob_put(state->degamma_lut);
+ drm_property_blob_put(state->ctm);
}
EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state);
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index ce3cb65d415e..6af2afe362ff 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -604,6 +604,14 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
&replaced);
state->color_mgmt_changed |= replaced;
return ret;
+ } else if (property == plane->ctm_property) {
+ ret = drm_atomic_replace_property_blob_from_id(dev,
+ &state->ctm,
+ val,
+ sizeof(struct drm_color_ctm), -1,
+ &replaced);
+ state->color_mgmt_changed |= replaced;
+ return ret;
} else if (property == config->prop_fb_damage_clips) {
ret = drm_atomic_replace_property_blob_from_id(dev,
&state->fb_damage_clips,
@@ -675,6 +683,8 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
} else if (property == plane->degamma_lut_property) {
*val = (state->degamma_lut) ?
state->degamma_lut->base.id : 0;
+ } else if (property == plane->ctm_property) {
+ *val = (state->ctm) ? state->ctm->base.id : 0;
} else if (property == config->prop_fb_damage_clips) {
*val = (state->fb_damage_clips) ?
state->fb_damage_clips->base.id : 0;
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 29d0fc1e52b5..83832adf3adf 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -602,6 +602,10 @@ EXPORT_SYMBOL(drm_plane_create_color_properties);
* engine, thereby making the content as linear for further color
* processing.
*
+ * ctm_property:
+ * Blob property which allows a userspace to provide CTM coefficients
+ * to do color space conversion or any other enhancement by doing a
+ * matrix multiplication using the h/w CTM processing engine
*/
int drm_plane_create_color_mgmt_properties(struct drm_device *dev,
struct drm_plane *plane,
@@ -623,6 +627,13 @@ int drm_plane_create_color_mgmt_properties(struct
drm_device *dev,
plane->degamma_lut_property = prop;
+ prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
+ "PLANE_CTM", 0);
+ if (!prop)
+ return -ENOMEM;
+
+ plane->ctm_property = prop;
+
return 0;
}
EXPORT_SYMBOL(drm_plane_create_color_mgmt_properties);
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index bbd0033ed1d2..83d11918333b 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -252,6 +252,14 @@ struct drm_plane_state {
*/
struct drm_property_blob *degamma_lut;
+ /**
+* @ctm:
+*
+* Color transformation matrix. See drm_plane_enable_color_mgmt(). The
+* blob (if not NULL) is a &struct drm_color_ctm.
+*/
+ struct drm_property_blob *ctm;
+
u8 color_mgmt_changed : 1;
};
@@ -776,6 +784,13 @@ struct drm_plane {
* used to convert the framebuffer's colors to linear gamma.
*/
struct drm_property *degamma_lut_property;
+
+ /**
+* @plane_ctm_property: Optional Plane property to set the
+* matrix used to convert colors after the lookup in the
+* degamma LUT.
+*/
+ struct drm_property *ctm_property;
};
#define obj_to_plane(x) container_of(x, struct drm_plane, base)
--
2.26.2
[Intel-gfx] [PATCH 13/21] drm: Add helper to attach Plane ctm property
Add a DRM helper to attach ctm property.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_color_mgmt.c | 10 ++
include/drm/drm_plane.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 83832adf3adf..5c3138497b9c 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -654,6 +654,16 @@ void drm_plane_attach_degamma_properties(struct drm_plane
*plane)
}
EXPORT_SYMBOL(drm_plane_attach_degamma_properties);
+void drm_plane_attach_ctm_property(struct drm_plane *plane)
+{
+ if (!plane->ctm_property)
+ return;
+
+ drm_object_attach_property(&plane->base,
+ plane->ctm_property, 0);
+}
+EXPORT_SYMBOL(drm_plane_attach_ctm_property);
+
int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane,
const char *name,
const struct
drm_color_lut_range *ranges,
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 83d11918333b..4557f59cf3cf 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -886,6 +886,7 @@ int drm_plane_create_color_mgmt_properties(struct
drm_device *dev,
struct drm_plane *plane,
int num_values);
void drm_plane_attach_degamma_properties(struct drm_plane *plane);
+void drm_plane_attach_ctm_property(struct drm_plane *plane);
int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane,
const char *name,
const struct
drm_color_lut_range *ranges,
--
2.26.2
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/21] drm/i915/xelpd: Define Plane CSC Registers
Define Register macros for plane CSC.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 43 +
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ede7dca440e2..df8500a86e9d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7397,6 +7397,49 @@ enum {
#define PLANE_COLOR_CTL(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
+/* Plane CSC Registers */
+#define _PLANE_CSC_RY_GY_1_A 0x70210
+#define _PLANE_CSC_RY_GY_2_A 0x70310
+
+#define _PLANE_CSC_RY_GY_1_B 0x71210
+#define _PLANE_CSC_RY_GY_2_B 0x71310
+
+#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
+ _PLANE_CSC_RY_GY_1_B)
+#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A,
\
+ _PLANE_INPUT_CSC_RY_GY_2_B)
+#define PLANE_CSC_COEFF(pipe, plane, index)_MMIO_PLANE(plane, \
+
_PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
+
_PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
+#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
+
+#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
+#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
+
+#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
+ _PLANE_CSC_PREOFF_HI_1_B)
+#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
+ _PLANE_CSC_PREOFF_HI_2_B)
+#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane,
_PLANE_CSC_PREOFF_HI_1(pipe) + \
+ (index) * 4,
_PLANE_CSC_PREOFF_HI_2(pipe) + \
+ (index) * 4)
+
+#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
+#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
+
+#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
+#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
+
+#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
+ _PLANE_CSC_POSTOFF_HI_1_B)
+#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
+ _PLANE_CSC_POSTOFF_HI_2_B)
+#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane,
_PLANE_CSC_POSTOFF_HI_1(pipe) + \
+ (index) * 4,
_PLANE_CSC_POSTOFF_HI_2(pipe) + \
+ (index) * 4)
+
#define _SEL_FETCH_PLANE_BASE_1_A 0x70890
#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0
#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0
--
2.26.2
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 15/21] drm/i915/xelpd: Enable Plane CSC
Implement plane CSC for ICL+
Signed-off-by: Uma Shankar
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 5 +-
drivers/gpu/drm/i915/display/intel_color.c| 82 +++
.../drm/i915/display/skl_universal_plane.c| 4 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 91 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 5de9c98beaf6..ec7646790892 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -499,6 +499,7 @@ void skl_update_planes_on_crtc(struct intel_atomic_state
*state,
intel_atomic_get_new_crtc_state(state, crtc);
struct skl_ddb_entry entries_y[I915_MAX_PLANES];
struct skl_ddb_entry entries_uv[I915_MAX_PLANES];
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 update_mask = new_crtc_state->update_planes;
struct intel_plane *plane;
@@ -513,8 +514,10 @@ void skl_update_planes_on_crtc(struct intel_atomic_state
*state,
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
- if (new_plane_state->uapi.color_mgmt_changed)
+ if (new_plane_state->uapi.color_mgmt_changed) {
intel_color_load_plane_luts(&new_plane_state->uapi);
+
dev_priv->display.load_plane_csc_matrix(&new_plane_state->uapi);
+ }
if (new_plane_state->uapi.visible ||
new_plane_state->planar_slave) {
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 6d57a47d8a60..8b4f653b213d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2119,6 +2119,83 @@ static void icl_read_luts(struct intel_crtc_state
*crtc_state)
}
}
+static void icl_load_plane_csc_matrix(const struct drm_plane_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ struct drm_color_ctm *ctm;
+ const u64 *input;
+ u16 coeffs[9] = {};
+ u16 postoff = 0;
+ int i;
+
+ if (!icl_is_hdr_plane(dev_priv, plane) || !state->ctm)
+ return;
+
+ ctm = state->ctm->data;
+ input = ctm->matrix;
+
+ /*
+* Convert fixed point S31.32 input to format supported by the
+* hardware.
+*/
+ for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
+ u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
+
+ /*
+* Clamp input value to min/max supported by
+* hardware.
+*/
+ abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
+
+ /* sign bit */
+ if (CTM_COEFF_NEGATIVE(input[i]))
+ coeffs[i] |= 1 << 15;
+
+ if (abs_coeff < CTM_COEFF_0_125)
+ coeffs[i] |= (3 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 12);
+ else if (abs_coeff < CTM_COEFF_0_25)
+ coeffs[i] |= (2 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 11);
+ else if (abs_coeff < CTM_COEFF_0_5)
+ coeffs[i] |= (1 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 10);
+ else if (abs_coeff < CTM_COEFF_1_0)
+ coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
+ else if (abs_coeff < CTM_COEFF_2_0)
+ coeffs[i] |= (7 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 8);
+ else
+ coeffs[i] |= (6 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 7);
+ }
+
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 0),
+ coeffs[0] << 16 | coeffs[1]);
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 1),
+ coeffs[2] << 16);
+
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 2),
+ coeffs[3] << 16 | coeffs[4]);
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 3),
+ coeffs[5] << 16);
+
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 4),
+ coeffs[6] << 16 | coeffs[7]);
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 5),
+ coeffs[8] << 16);
+
+ intel_de_write(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
+ intel_de_write(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
+ intel_de_write(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
+
+ intel_de_write(dev
[Intel-gfx] [PATCH 16/21] drm: Add Plane Gamma Mode property
Add Plane Gamma Mode as a blob property. This is an enum property
with values as blob_id's and exposes the various gamma modes
supported and the lut ranges. Getting the blob id in userspace,
user can get the mode supported and also the range of gamma mode
supported with number of lut coefficients. It can then set one of
the modes using this enum property.
Lut values will be sent through a separate GAMMA_LUT blob property.
Signed-off-by: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/drm_atomic_uapi.c | 4
drivers/gpu/drm/drm_color_mgmt.c | 26 ++
include/drm/drm_plane.h | 14 ++
3 files changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 6af2afe362ff..6e3958491d10 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -612,6 +612,8 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
&replaced);
state->color_mgmt_changed |= replaced;
return ret;
+ } else if (property == plane->gamma_mode_property) {
+ state->gamma_mode = val;
} else if (property == config->prop_fb_damage_clips) {
ret = drm_atomic_replace_property_blob_from_id(dev,
&state->fb_damage_clips,
@@ -685,6 +687,8 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
state->degamma_lut->base.id : 0;
} else if (property == plane->ctm_property) {
*val = (state->ctm) ? state->ctm->base.id : 0;
+ } else if (property == plane->gamma_mode_property) {
+ *val = state->gamma_mode;
} else if (property == config->prop_fb_damage_clips) {
*val = (state->fb_damage_clips) ?
state->fb_damage_clips->base.id : 0;
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 5c3138497b9c..02367e691cf3 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -606,6 +606,13 @@ EXPORT_SYMBOL(drm_plane_create_color_properties);
* Blob property which allows a userspace to provide CTM coefficients
* to do color space conversion or any other enhancement by doing a
* matrix multiplication using the h/w CTM processing engine
+ *
+ * gamma_mode_property:
+ * Blob property which advertizes the possible gamma modes and
+ * lut ranges supported by the platform. This allows userspace
+ * to query and get the plane gamma color caps and choose the
+ * appropriate gamma mode and create lut values accordingly
+ *
*/
int drm_plane_create_color_mgmt_properties(struct drm_device *dev,
struct drm_plane *plane,
@@ -634,6 +641,13 @@ int drm_plane_create_color_mgmt_properties(struct
drm_device *dev,
plane->ctm_property = prop;
+ prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
+ "PLANE_GAMMA_MODE", num_values);
+ if (!prop)
+ return -ENOMEM;
+
+ plane->gamma_mode_property = prop;
+
return 0;
}
EXPORT_SYMBOL(drm_plane_create_color_mgmt_properties);
@@ -664,6 +678,16 @@ void drm_plane_attach_ctm_property(struct drm_plane *plane)
}
EXPORT_SYMBOL(drm_plane_attach_ctm_property);
+void drm_plane_attach_gamma_properties(struct drm_plane *plane)
+{
+ if (!plane->gamma_mode_property)
+ return;
+
+ drm_object_attach_property(&plane->base,
+ plane->gamma_mode_property, 0);
+}
+EXPORT_SYMBOL(drm_plane_attach_gamma_properties);
+
int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane,
const char *name,
const struct
drm_color_lut_range *ranges,
@@ -676,6 +700,8 @@ int drm_plane_color_add_gamma_degamma_mode_range(struct
drm_plane *plane,
if (type == LUT_TYPE_DEGAMMA)
prop = plane->degamma_mode_property;
+ else
+ prop = plane->gamma_mode_property;
if (!prop)
return -EINVAL;
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 4557f59cf3cf..a7b7c8599702 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -260,6 +260,13 @@ struct drm_plane_state {
*/
struct drm_property_blob *ctm;
+ /**
+* @gamma_mode: This is a blob_id and exposes the platform capabilities
+* wrt to various gamma modes and the respective lut ranges. This also
+* helps user select a gamma mode amongst the supported ones.
+*/
+ u32 gamma_mode;
+
u8 color_mgmt_changed : 1;
};
@@ -791,6 +798,12 @@ struct drm_plane {
* degamma LUT.
*/
struct drm_property *ctm_property;
+
+ /*
[Intel-gfx] [PATCH 17/21] drm: Add Plane Gamma Lut property
Add Plane Gamma Lut as a blob property.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_state_helper.c | 3 +++
drivers/gpu/drm/drm_atomic_uapi.c | 10 ++
drivers/gpu/drm/drm_color_mgmt.c | 18 ++
include/drm/drm_plane.h | 14 ++
4 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index fafb8af1c9cb..7ddf6e4b956b 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -316,6 +316,8 @@ void __drm_atomic_helper_plane_duplicate_state(struct
drm_plane *plane,
drm_property_blob_get(state->degamma_lut);
if (state->ctm)
drm_property_blob_get(state->ctm);
+ if (state->gamma_lut)
+ drm_property_blob_get(state->gamma_lut);
state->color_mgmt_changed = false;
}
@@ -366,6 +368,7 @@ void __drm_atomic_helper_plane_destroy_state(struct
drm_plane_state *state)
drm_property_blob_put(state->fb_damage_clips);
drm_property_blob_put(state->degamma_lut);
drm_property_blob_put(state->ctm);
+ drm_property_blob_put(state->gamma_lut);
}
EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state);
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 6e3958491d10..4f5b7f76208d 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -614,6 +614,13 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
return ret;
} else if (property == plane->gamma_mode_property) {
state->gamma_mode = val;
+ } else if (property == plane->gamma_lut_property) {
+ ret = drm_atomic_replace_property_blob_from_id(dev,
+ &state->gamma_lut,
+ val, -1, sizeof(struct
drm_color_lut_ext),
+ &replaced);
+ state->color_mgmt_changed |= replaced;
+ return ret;
} else if (property == config->prop_fb_damage_clips) {
ret = drm_atomic_replace_property_blob_from_id(dev,
&state->fb_damage_clips,
@@ -689,6 +696,9 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
*val = (state->ctm) ? state->ctm->base.id : 0;
} else if (property == plane->gamma_mode_property) {
*val = state->gamma_mode;
+ } else if (property == plane->gamma_lut_property) {
+ *val = (state->gamma_lut) ?
+ state->gamma_lut->base.id : 0;
} else if (property == config->prop_fb_damage_clips) {
*val = (state->fb_damage_clips) ?
state->fb_damage_clips->base.id : 0;
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 02367e691cf3..b5b3ff7f654d 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -613,6 +613,11 @@ EXPORT_SYMBOL(drm_plane_create_color_properties);
* to query and get the plane gamma color caps and choose the
* appropriate gamma mode and create lut values accordingly
*
+ * gamma_lut_property:
+ * Blob property which allows a userspace to provide LUT values
+ * to apply gamma curve using the h/w plane degamma processing
+ * engine, thereby making the content as non-linear.
+ *
*/
int drm_plane_create_color_mgmt_properties(struct drm_device *dev,
struct drm_plane *plane,
@@ -648,6 +653,13 @@ int drm_plane_create_color_mgmt_properties(struct
drm_device *dev,
plane->gamma_mode_property = prop;
+ prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
+ "PLANE_GAMMA_LUT", 0);
+ if (!prop)
+ return -ENOMEM;
+
+ plane->gamma_lut_property = prop;
+
return 0;
}
EXPORT_SYMBOL(drm_plane_create_color_mgmt_properties);
@@ -685,6 +697,12 @@ void drm_plane_attach_gamma_properties(struct drm_plane
*plane)
drm_object_attach_property(&plane->base,
plane->gamma_mode_property, 0);
+
+ if (!plane->gamma_lut_property)
+ return;
+
+ drm_object_attach_property(&plane->base,
+ plane->gamma_lut_property, 0);
}
EXPORT_SYMBOL(drm_plane_attach_gamma_properties);
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index a7b7c8599702..8989bb1aa46c 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -267,6 +267,14 @@ struct drm_plane_state {
*/
u32 gamma_mode;
+ /* @gamma_lut:
+*
+* Lookup table for converting framebuffer pixel data after applying the
+* color conversion matrix @ctm. See drm_plane_enable_color_mgmt(). The
+* bl
[Intel-gfx] [PATCH 18/21] drm/i915/xelpd: Define and Initialize Plane Gamma Lut range
Define the structure with XE_LPD gamma lut ranges. HDR and SDR planes
have different capabilities, implemented respective structure for
the HDR planes. Degamma and GAMMA has same Lut caps for SDR planes,
extended the same.
Initialize the mode range caps as well.
Signed-off-by: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 112 ++---
1 file changed, 99 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 8b4f653b213d..7f091dd0bb19 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2248,7 +2248,7 @@ static const struct drm_color_lut_range d13_degamma_hdr[]
= {
};
/* FIXME input bpc? */
-static const struct drm_color_lut_range d13_degamma_sdr[] = {
+static const struct drm_color_lut_range d13_gamma_degamma_sdr[] = {
/* segment 1 */
{
.flags = (DRM_MODE_LUT_GAMMA |
@@ -2298,6 +2298,63 @@ static const struct drm_color_lut_range
d13_degamma_sdr[] = {
},
};
+ /* FIXME input bpc? */
+static const struct drm_color_lut_range d13_gamma_hdr[] = {
+ /*
+* ToDo: Add Segment 1
+* There is an optional fine segment added with 9 lut values
+* Will be added later
+*/
+
+ /* segment 2 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = 0, .end = (1 << 24) - 1,
+ .min = 0, .max = (1 << 24) - 1,
+ },
+ /* segment 3 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_REUSE_LAST |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 24) - 1, .end = 1 << 24,
+ .min = 0, .max = 1 << 24,
+ },
+ /* Segment 4 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_REUSE_LAST |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = 1 << 24, .end = 3 << 24,
+ .min = 0, .max = (3 << 24),
+ },
+ /* Segment 5 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_REUSE_LAST |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = 3 << 24, .end = 7 << 24,
+ .min = 0, .max = (7 << 24),
+ },
+};
+
static void d13_program_plane_degamma_lut(const struct drm_plane_state *state,
struct drm_color_lut_ext *degamma_lut,
u32 offset)
@@ -2407,26 +2464,55 @@ int intel_plane_color_init(struct drm_plane *plane)
ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "no
degamma",
NULL, 0,
LUT_TYPE_DEGAMMA);
- if (icl_is_hdr_plane(dev_priv, to_intel_plane(plane)->id))
+ if (ret)
+ return ret;
+
+ ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "no
gamma",
+ NULL, 0,
+
LUT_TYPE_GAMMA);
+ if (ret)
+ return ret;
+
+ if (icl_is_hdr_plane(dev_priv, to_intel_plane(plane)->id)) {
ret =
drm_plane_color_add_gamma_degamma_mode_range(plane, "plane degamma",
d13_degamma_hdr,
sizeof(d13_degamma_hdr),
LUT_TYPE_DEGAMMA);
- else
- ret =
drm_plane_color_add_gamma_degamma_mode_range(plane,
-
"plane degamma",
-
[Intel-gfx] [PATCH 19/21] drm/i915/xelpd: Add register definitions for Plane Gamma
Add macros to define Plane Gamma registers
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 73 +
1 file changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a8e35357aea0..2ebc92104f64 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11398,6 +11398,79 @@ enum skl_power_gate {
_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \
_PLANE_PRE_CSC_GAMC_DATA_2(pipe))
+/* Display13 Plane Gamma Reg */
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A0x70160
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B0x71160
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A0x70260
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B0x71260
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe)_PIPE(pipe,
_PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A, \
+
_PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe)_PIPE(pipe,
_PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A, \
+
_PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, i) \
+ _MMIO_PLANE_GAMC(plane, i,
_PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A 0x70164
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B 0x71164
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A 0x70264
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B 0x71264
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A, \
+
_PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A, \
+
_PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_SEG0_DATA_ENH(pipe, plane, i) \
+ _MMIO_PLANE_GAMC(plane, i,
_PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A 0x701d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B 0x711d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A 0x702d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B 0x712d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_INDEX_ENH_1_A, \
+
_PLANE_POST_CSC_GAMC_INDEX_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_INDEX_ENH_2_A, \
+
_PLANE_POST_CSC_GAMC_INDEX_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, i) \
+ _MMIO_PLANE_GAMC(plane, i,
_PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_A 0x701dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_B 0x711dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_A 0x702dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_B 0x712dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_DATA_ENH_1_A, \
+
_PLANE_POST_CSC_GAMC_DATA_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_DATA_ENH_2_A, \
+
_PLANE_POST_CSC_GAMC_DATA_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, i) \
+ _MMIO_PLANE_GAMC(plane, i,
_PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_INDEX_1_A 0x704d8
+#define _PLANE_POST_CSC_GAMC_INDEX_1_B 0x714d8
+#define _PLANE_POST_CSC_GAMC_INDEX_2_A 0x705d8
+#define _PLANE_POST_CSC_GAMC_INDEX_2_B 0x715d8
+#define _PLANE_POST_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_INDEX_1_A, \
+ _PLANE_POST_CSC_GAMC_INDEX_1_B)
+#define _PLANE_POST_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_INDEX_2_A, \
+ _PLANE_POST_CSC_GAMC_INDEX_2_B)
+#define PLANE_POST_CSC_GAMC_INDEX(pipe, plane, i) \
+ _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_1(pipe), \
+ _PLANE_POST_CSC_GAMC_INDEX_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_DATA_1_A 0x704dc
+#define _PLANE_POST_CSC_GAMC_DATA_1_B 0x714dc
+#define _PLANE_POST_CSC_GAMC_DATA_2_A 0x705dc
+#define _PLANE_POST_CSC_GAMC_DATA_2_B 0x715dc
+#define _PLANE_POST_CSC_GAMC_DATA_1(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_DATA_1_A, \
+ _PLAN
[Intel-gfx] [PATCH 20/21] drm/i915/xelpd: Program Plane Gamma Registers
Extract the LUT and program plane gamma registers.
Enabled multi segmented lut as well.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 89 ++
drivers/gpu/drm/i915/i915_reg.h| 9 ++-
2 files changed, 94 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 7f091dd0bb19..daf2148fb2df 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -27,6 +27,9 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_sprite.h"
+
+#include "skl_universal_plane.h"
+
#include
#define CTM_COEFF_SIGN (1ULL << 63)
@@ -2434,16 +2437,102 @@ static void d13_program_plane_degamma_lut(const struct
drm_plane_state *state,
}
}
+static void d13_program_plane_gamma_lut(const struct drm_plane_state *state,
+ struct drm_color_lut_ext *gamma_lut,
+ u32 offset)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ u32 i, lut_size;
+
+ if (icl_is_hdr_plane(dev_priv, plane)) {
+ intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe,
plane, 0),
+ offset | PLANE_PAL_PREC_AUTO_INCREMENT);
+ if (gamma_lut) {
+ lut_size = 32;
+ for (i = 0; i < lut_size; i++) {
+ u64 word =
drm_color_lut_extract_ext(gamma_lut[i].green, 24);
+ u32 lut_val = (word & 0xff);
+
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ lut_val);
+ }
+
+ do {
+ /* Program the max register to clamp values >
1.0. */
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ gamma_lut[i].green);
+ } while (i++ < 34);
+ } else {
+ lut_size = 32;
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
+ }
+
+ do {
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ 1 << 24);
+ } while (i++ < 34);
+ }
+
+ intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe,
plane, 0), 0);
+ } else {
+ lut_size = 32;
+ /*
+* First 3 planes are HDR, so reduce by 3 to get to the right
+* SDR plane offset
+*/
+ plane = plane - 3;
+
+ intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_INDEX(pipe, plane,
0),
+ offset | PLANE_PAL_PREC_AUTO_INCREMENT);
+
+ if (gamma_lut) {
+ for (i = 0; i < lut_size; i++)
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0),
+ gamma_lut[i].green & 0x);
+ /* Program the max register to clamp values > 1.0. */
+ while (i < 35)
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0),
+ gamma_lut[i++].green & 0x3);
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 16) - 1)) / (lut_size - 1);
+
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0), v);
+ }
+
+ do {
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0),
+ (1 << 16));
+ } while (i++ < 34);
+ }
+
+ intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_INDEX(pipe, plane,
0), 0);
+ }
+}
+
static void d13_plane_load_luts(const struct drm_plane_state *plane_state)
{
const struct drm_property_blob *degamma_lut_blob =
plane_state->degamma_lut;
+ const struct drm_property_blob *gamma_lut_blob =
+ plane_state->gamma_lut;
struct drm_color_lut_ext *degamma_lut = NULL;
+ struct drm_
[Intel-gfx] [PATCH 21/21] drm/i915/xelpd: Enable plane gamma
Enable plane gamma feature in check callbacks. Decide based on the user input. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 6ba670b6a5c9..5d527d12ec45 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -959,7 +959,9 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); u32 plane_color_ctl = 0; - plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; + /* FIXME needs hw.gamma_lut */ + if (!plane_state->uapi.gamma_lut) + plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; /* FIXME needs hw.degamma_lut */ if (plane_state->uapi.degamma_lut) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC v3 0/2] lpsp with hdmi/dp outputs
v2 link: https://patchwork.freedesktop.org/series/77866/ Anshuman Gupta (2): drm/i915/dg1: Adjust the AUDIO power domain drm/i915/display: Use AUDIO_VERBS for crtc power domain mask drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/intel_display_power.c| 382 +- .../drm/i915/display/intel_display_power.h| 1 + 4 files changed, 384 insertions(+), 3 deletions(-) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC v3 2/2] drm/i915/display: Use AUDIO_VERBS for crtc power domain mask
Use POWER_DOMAIN_AUDIO_VERBS power domain instead of POWER_DOMAIN_AUDIO in crtc power domain mask. It will save the power in use cases when DP/HDMI connectors configured with PIPE_A without any audio playback. Cc: Ville Syrjälä Cc: Kai Vehmanen Cc: Uma Shankar Cc: Imre Deak Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 3d8918674153..55c392114272 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3494,7 +3494,7 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, if (cpu_transcoder == TRANSCODER_EDP) return false; - if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) + if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_VERBS)) return false; return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0bb2e582c87f..c24465739af5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3829,7 +3829,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) } if (HAS_DDI(dev_priv) && crtc_state->has_audio) - mask |= BIT_ULL(POWER_DOMAIN_AUDIO); + mask |= BIT_ULL(POWER_DOMAIN_AUDIO_VERBS); if (crtc_state->shared_dpll) mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain
DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power well. Adjusting the power domain accordingly to POWER_DOMAIN_AUDIO_VERBS for audio detection and POWER_DOMAIN_AUDIO for audio playback. Cc: Ville Syrjälä Cc: Kai Vehmanen Cc: Uma Shankar Cc: Imre Deak Signed-off-by: Anshuman Gupta --- .../drm/i915/display/intel_display_power.c| 382 +- .../drm/i915/display/intel_display_power.h| 1 + 2 files changed, 382 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 2f7d1664c473..da5894138e8b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -106,6 +106,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) return "PORT_OTHER"; case POWER_DOMAIN_VGA: return "VGA"; + case POWER_DOMAIN_AUDIO_VERBS: + return "AUDIO_VERBS"; case POWER_DOMAIN_AUDIO: return "AUDIO"; case POWER_DOMAIN_AUX_A: @@ -2499,6 +2501,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_PORT_DSI) |\ BIT_ULL(POWER_DOMAIN_PORT_CRT) |\ BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_AUX_B) | \ BIT_ULL(POWER_DOMAIN_AUX_C) | \ @@ -2549,6 +2552,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\ BIT_ULL(POWER_DOMAIN_PORT_DSI) |\ BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_AUX_B) | \ BIT_ULL(POWER_DOMAIN_AUX_C) | \ @@ -2582,6 +2586,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\ BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */\ BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_INIT)) @@ -2598,6 +2603,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\ BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */\ BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_INIT)) @@ -2616,6 +2622,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_AUX_B) | \ BIT_ULL(POWER_DOMAIN_AUX_C) | \ BIT_ULL(POWER_DOMAIN_AUX_D) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_VGA) | \ BIT_ULL(POWER_DOMAIN_INIT)) @@ -2651,6 +2658,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\ BIT_ULL(POWER_DOMAIN_AUX_B) | \ BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_VGA) | \ BIT_ULL(POWER_DOMAIN_INIT)) @@ -2684,6 +2692,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\ BIT_ULL(POWER_DOMAIN_AUX_B) | \ BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_VGA) | \ BIT_ULL(POWER_DOMAIN_INIT)) @@ -2739,6 +2748,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_AUX_C) | \ BIT_ULL(POWER_DOMAIN_AUX_D) | \ BIT_ULL(POWER_DOMAIN_AUX_F) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_VGA) | \ BIT_ULL(POWER_DOMAIN_INIT)) @@ -2821,6 +2831,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DO
[Intel-gfx] ✗ Fi.CI.IGT: failure for Move LMEM (VRAM) management over to TTM (rev5)
== Series Details == Series: Move LMEM (VRAM) management over to TTM (rev5) URL : https://patchwork.freedesktop.org/series/90681/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10153_full -> Patchwork_20243_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20243_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20243_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20243_full: ### IGT changes ### Possible regressions * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: NOTRUN -> [SKIP][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-iclb1/igt@kms_plane_low...@pipe-a-tiling-y.html Warnings * igt@perf@polling-parameterized: - shard-skl: [FAIL][2] ([i915#1542]) -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-skl6/igt@p...@polling-parameterized.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-skl4/igt@p...@polling-parameterized.html ### Piglit changes ### Possible regressions * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 8 128 4 (NEW): - pig-glk-j5005: NOTRUN -> [INCOMPLETE][4] +1 similar issue [4]: None New tests - New tests have been introduced between CI_DRM_10153_full and Patchwork_20243_full: ### New Piglit tests (2) ### * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 8 128 4: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 8 128 7: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_20243_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-hostile@rcs0: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2410]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-glk9/igt@gem_ctx_persistence@engines-host...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-glk4/igt@gem_ctx_persistence@engines-host...@rcs0.html - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2410]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-tglb6/igt@gem_ctx_persistence@engines-host...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-tglb5/igt@gem_ctx_persistence@engines-host...@rcs0.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][10] ([i915#3354]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-snb6/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][11] ([i915#2846]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-apl1/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-glk: NOTRUN -> [FAIL][12] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-glk6/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-glk8/igt@gem_exec_fair@basic-pace-s...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-glk4/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2849]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_params@secure-non-master: - shard-iclb: NOTRUN -> [SKIP][17] ([fdo#112283]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-iclb1/igt@gem_exec_par...@secure-non-master.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][18] ([i915#2389]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-iclb2/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@gem_me
Re: [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function
The v2 patch which addressed Jose's comments was floated to
https://patchwork.freedesktop.org/series/90819/
On Fri, 2021-05-21 at 14:52 -0700, Souza, Jose wrote:
> On Fri, 2021-05-21 at 11:58 +0100, Mun, Gwan-gyeong wrote:
> > On Tue, 2021-05-18 at 14:06 +0300, Ville Syrjälä wrote:
> > > On Tue, May 18, 2021 at 09:33:09AM +, Mun, Gwan-gyeong wrote:
> > > > Hi Ville,
> > > > initially, intel_psr_pause() called intel_psr_disable_locked()
> > > > instead
> > > > of intel_psr_exit().
> > > > In intel_psr_resume(), _intel_psr_enable_locked() was called
> > > > instead
> > > > of
> > > > intel_psr_activate().
> > > > Can you share what problem the initial code caused when calling
> > > > intel_psr_pause() / intel_psr_resume()?
> > >
> > > It was doing illegal stuff with crtc->state/etc. That was oopsing.
> > > The other problem was that IIRC it was going to do DPCD accesses
> > > while the cdclk code was already holding the aux mutexes. I moved
> > > it
> > > out from under the lock, but I think we might actually want it
> > > inside
> > > the lock since we'll need that to prevent PSR during all AUX
> > > transfers
> > > anyway. Putting it back inside the lock should also make it less
> > > racy
> > > I guess.
> > >
> > > >
> > > > In addition, intel_psr_exit() /intel_psr_activate() function
> > > > disable
> > > > /
> > > > enable only the PSR source.
> > > > So, if disable/enable for PSR Sink Device is not called together,
> > > > there
> > > > will be a problem that the PSR state machine of sink and source
> > > > is
> > > > different.
> > > > What do you think?
> > >
> > > If possible I wouldn't want it touch the sink at all. It should
> > > basically be no different to eg. enabling the vblank interrupt.
> > >
> >
> > Hi Ville and Stan,
> > Thanks, Ville, for explaining.
> >
> > intel_psr_pause() and intel_psr_resume() are an api added to use when
> > reactivating (disable and enable) the psr functionality without
> > intel_crtc_state and drm_connector_state, as described in the commit
> > log.
> > And in order to deactivate and activate psr normally, we must
> > deactivate the psr functionality of the sink as well, and at this
> > time,
> > sink psr deactivate using dpcd.
> >
> > And in the part explaining disabling psr in cdclk setting in bspec,
> > the
> > following procedure is explained for disabling psr.
> > 1. Temporarily disable PSR1, PSR2, and GTC.
> > 2. Wait for disabling status from those functions.
> > 3. Wait for any pending Aux transactions to complete, and do not
> > start
> > any new Aux transaction.
> > ...
>
> I don't think we need to disable, psr_exit() + wait until PSR is idle
> is enough, all other stuff can be left as is.
>
> >
> > So, in my opinion, when the cdclk setting is called from
> > intel_atomic_commit_tail() with functions such as
> > intel_set_cdclk_pre_plane_update() /
> > intel_set_cdclk_post_plane_update(),
> > if psr deactivation/activation is necessary, it seems that
> > intel_set_cdclk_pre_plane_update() /
> > intel_set_cdclk_post_plane_update() should be called with
> > intel_psr_enable() / intel_psr_disable() functions together. What do
> > you think?
> >
> > Br,
> > G.G.
> > > >
> > > > On Mon, 2021-05-17 at 09:58 -0700, Souza, Jose wrote:
> > > > > On Fri, 2021-05-14 at 20:10 -0700, Matt Roper wrote:
> > > > > > From: Gwan-gyeong Mun
> > > > > >
> > > > > > This introduces the following function that can enable and
> > > > > > disable
> > > > > > psr
> > > > > > without intel_crtc_state/drm_connector_state when intel_psr
> > > > > > is
> > > > > > already
> > > > > > enabled with current intel_crtc_state and drm_connector_state
> > > > > > information.
> > > > > >
> > > > > > - intel_psr_pause(): Pause current PSR. it deactivates
> > > > > > current
> > > > > > psr
> > > > > > state.
> > > > > > - intel_psr_resume(): Resume paused PSR without
> > > > > > intel_crtc_state
> > > > > > and
> > > > > > drm_connector_state. It activates
> > > > > > paused
> > > > > > psr
> > > > > > state.
> > > > > >
> > > > > > Cc: José Roberto de Souza
> > > > > > Cc: Stanislav Lisovskiy
> > > > > > Cc: Ville Syrjälä
> > > > > > Signed-off-by: Gwan-gyeong Mun
> > > > > > Signed-off-by: Matt Roper
> > > > > > ---
> > > > > > .../drm/i915/display/intel_display_types.h | 1 +
> > > > > > drivers/gpu/drm/i915/display/intel_psr.c | 93
> > > > > > -
> > > > > > --
> > > > > > drivers/gpu/drm/i915/display/intel_psr.h | 2 +
> > > > > > 3 files changed, 82 insertions(+), 14 deletions(-)
> > > > > >
> > > > > > diff --git
> > > > > > a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > index b8d1f702d808..ee7cbdd7db87 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > @@ -1482,6 +1482,7 @@ struct intel_psr {
> > > > > >
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest()
== Series Details == Series: drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest() URL : https://patchwork.freedesktop.org/series/90817/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9f93f64b2ec8 drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest() -:19: WARNING:BAD_SIGN_OFF: Unexpected content after email: 'intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; chengzhih...@huawei.com; yuku...@huawei.com', should be: 'intel-gfx@lists.freedesktop.org; (dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; chengzhih...@huawei.com; yuku...@huawei.com)' #19: Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; chengzhih...@huawei.com; yuku...@huawei.com -:20: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #20: Subject: [PATCH] drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest() total: 0 errors, 2 warnings, 0 checks, 10 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest()
== Series Details ==
Series: drm/i915/selftests: Fix return value check in
live_breadcrumbs_smoketest()
URL : https://patchwork.freedesktop.org/series/90817/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20245
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/index.html
Known issues
Here are the changes found in Patchwork_20245 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][2] ([i915#3303]) -> [PASS][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
- fi-snb-2600:[INCOMPLETE][4] ([i915#2782]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][6] ([i915#1372]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
Warnings
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[INCOMPLETE][8] ([i915#2782] / [i915#2940] /
[i915#3462]) -> [DMESG-FAIL][9] ([i915#3462])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
- fi-icl-u2: [INCOMPLETE][10] ([i915#2782] / [i915#3462]) ->
[DMESG-FAIL][11] ([i915#3462])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-icl-u2/igt@i915_selftest@l...@execlists.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-icl-u2/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][12] ([i915#1436] / [i915#3363]) -> [FAIL][13]
([i915#1436] / [i915#2426] / [i915#3363])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-skl-6600u/igt@run...@aborted.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-skl-6600u/igt@run...@aborted.html
- fi-icl-u2: [FAIL][14] ([i915#2782] / [i915#3363]) -> [FAIL][15]
([i915#2426] / [i915#2782] / [i915#3363])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-icl-u2/igt@run...@aborted.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-icl-u2/igt@run...@aborted.html
- fi-kbl-7500u: [FAIL][16] ([i915#1436] / [i915#3363]) -> [FAIL][17]
([i915#1436] / [i915#2426] / [i915#3363])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@run...@aborted.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-kbl-7500u/igt@run...@aborted.html
- fi-skl-6700k2: [FAIL][18] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][19] ([i915#1436] / [i915#3363])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-skl-6700k2/igt@run...@aborted.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-skl-6700k2/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
Participating hosts (47 -> 42)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_
Re: [Intel-gfx] [PATCH] drm/i915: Use DRIVER_NAME for tracing unattached requests
On 31/05/2021 08:53, Daniel Vetter wrote:
On Thu, May 20, 2021 at 4:28 PM Daniel Vetter wrote:
On Thu, May 20, 2021 at 08:35:14AM +0100, Matthew Auld wrote:
From: Chris Wilson
The first tracepoint for a request is trace_dma_fence_init called before
we have associated the request with a device. The tracepoint uses
fence->ops->get_driver_name() as a pretty name, and as we try to report
the device name this oopses as it is then NULL. Support the early
tracepoint by reporting the DRIVER_NAME instead of the actual device
name.
Note that rq->engine remains during the course of request recycling
(SLAB_TYPESAFE_BY_RCU). For the physical engines, the pointer remains
valid, however a virtual engine may be destroyed after the request is
retired. If we process a preempt-to-busy completed request along the
virtual engine, we should make sure we mark the request as no longer
belonging to the virtual engine to remove the dangling pointers from the
tracepoint.
Why can't we assign the request beforehand? The idea behind these
tracepoints is that they actually match up, if trace_dma_fence_init is
different, then we're breaking that.
Ok I looked a bit more and pondered this a bit, and the initial
tracepoint is called from dma_fence_init, where we haven't yet set up
rq->engine properly. So that part makes sense, but should have a
bigger comment that explains this a bit more and why we can't solve
this in a neater way. Probably should also drop the unlikely(), this
isn't a performance critical path, ever.
The other changes thgouh feel like they should be split out into a
separate path, since they solve a conceptually totally different
issue: SLAB_TYPESAFE_BY_RCU recycling.
Hmm, I thought it all stems from having to tread very carefully around
SLAB_TYPESAFE_BY_RCU? If this were "normal" code, we would just allocate
the rq, initialise it properly, including the rq->engine, and only then
do the dma_fence_init? Or am I missing something?
I'm happy to split it though. And I think that bit at least fixes the
user reported issue I think.
And I'm honestly not sure about
that one whether it's even correct, there's another patch floating
around that sprinkles rcu_read_lock around some of these accesssors,
and that would be a breakage of dma_fence interaces where outside of
i915 rcu isn't required for this stuff. So imo should be split out,
and come with a wider analysis of what's going on there and why and
how exactly i915 works.
In generally SLAB_TYPESAFE_BY_RCU is extremely dangerous and I'm
frankly not sure we have the perf data (outside of contrived
microbenchmarks) showing that it's needed and justifies all the costs
it's encurring.
Right, I can try to search the git history.
-Daniel
-Daniel
Fixes: 855e39e65cfc ("drm/i915: Initialise basic fence before acquiring seqno")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Chintan M Patel
Cc: Andi Shyti
Cc: # v5.7+
Signed-off-by: Matthew Auld
---
.../drm/i915/gt/intel_execlists_submission.c | 20 ++-
drivers/gpu/drm/i915/i915_request.c | 7 ++-
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index de124870af44..75604e927d34 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3249,6 +3249,18 @@ static struct list_head *virtual_queue(struct
virtual_engine *ve)
return &ve->base.execlists.default_priolist.requests;
}
+static void
+virtual_submit_completed(struct virtual_engine *ve, struct i915_request *rq)
+{
+ GEM_BUG_ON(!__i915_request_is_complete(rq));
+ GEM_BUG_ON(rq->engine != &ve->base);
+
+ __i915_request_submit(rq);
+
+ /* Remove the dangling pointer to the stale virtual engine */
+ WRITE_ONCE(rq->engine, ve->siblings[0]);
+}
+
static void rcu_virtual_context_destroy(struct work_struct *wrk)
{
struct virtual_engine *ve =
@@ -3265,8 +3277,7 @@ static void rcu_virtual_context_destroy(struct
work_struct *wrk)
old = fetch_and_zero(&ve->request);
if (old) {
- GEM_BUG_ON(!__i915_request_is_complete(old));
- __i915_request_submit(old);
+ virtual_submit_completed(ve, old);
i915_request_put(old);
}
@@ -3538,13 +3549,12 @@ static void virtual_submit_request(struct i915_request
*rq)
/* By the time we resubmit a request, it may be completed */
if (__i915_request_is_complete(rq)) {
- __i915_request_submit(rq);
+ virtual_submit_completed(ve, rq);
goto unlock;
}
if (ve->request) { /* background completion from preempt-to-busy */
- GEM_BUG_ON(!__i915_request_is_complete(ve->request));
- __i915_request_submit(ve->request);
+ virtual_submit_complete
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Only set bind_async_flags when concurrent access wa is not active, v3.
== Series Details == Series: drm/i915: Only set bind_async_flags when concurrent access wa is not active, v3. URL : https://patchwork.freedesktop.org/series/90818/ State : warning == Summary == $ dim checkpatch origin/drm-tip 48e0a3099384 drm/i915: Only set bind_async_flags when concurrent access wa is not active, v3. -:74: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #74: FILE: drivers/gpu/drm/i915/i915_vma.c:439: + vma->ops->bind_vma(vma->vm, work ? &work->stash : NULL, vma, cache_level, bind_flags); total: 0 errors, 1 warnings, 0 checks, 44 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add relocation exceptions for two other platforms (rev3)
== Series Details == Series: drm/i915: Add relocation exceptions for two other platforms (rev3) URL : https://patchwork.freedesktop.org/series/89594/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10153_full -> Patchwork_20244_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20244_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20244_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20244_full: ### IGT changes ### Possible regressions * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: NOTRUN -> [SKIP][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-iclb8/igt@kms_plane_low...@pipe-a-tiling-y.html ### Piglit changes ### Possible regressions * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 8 128 4 (NEW): - pig-glk-j5005: NOTRUN -> [INCOMPLETE][2] +1 similar issue [2]: None New tests - New tests have been introduced between CI_DRM_10153_full and Patchwork_20244_full: ### New Piglit tests (2) ### * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 8 128 4: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 8 128 7: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_20244_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-clear: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#3160]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-glk6/igt@gem_cre...@create-clear.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-glk7/igt@gem_cre...@create-clear.html * igt@gem_ctx_persistence@engines-hostile@rcs0: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2410]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-glk9/igt@gem_ctx_persistence@engines-host...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-glk9/igt@gem_ctx_persistence@engines-host...@rcs0.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2410]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-tglb5/igt@gem_ctx_persiste...@many-contexts.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-tglb7/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][10] ([i915#3354]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-snb5/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][11] ([i915#2846]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-apl1/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-glk2/igt@gem_exec_fair@basic-throt...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_params@secure-non-master: - shard-iclb: NOTRUN -> [SKIP][14] ([fdo#112283]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-iclb8/igt@gem_exec_par...@secure-non-master.html * igt@gem_media_vme: - shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271]) +37 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-skl8/igt@gem_media_vme.html * igt@gem_mmap_gtt@cpuset-basic-small-copy: - shard-skl: [PASS][16] -> [INCOMPLETE][17] ([i915#198] / [i915#3468]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-skl1/igt@gem_mmap_...@cpuset-basic-small-copy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-skl3/igt@gem_mmap_...@cpuset-basic-small-copy.html * igt@gem_mmap_gtt@cpuset-basic-small-copy-odd: - shard-apl: NOTRUN -> [INCOMPLETE][18] ([i915#3468]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-apl3/igt@gem_mmap_...@cpuse
[Intel-gfx] [PATCH i-g-t] [RFC] tests/kms_plane_alpha_blend: Fix coverage-vs-premult-vs-constant tests
Few Gen11 systems show CRC mismatch. Make coverage-vs-premult-vs-constant
code similar to constant_alpha_min or basic_alpha
Signed-off-by: Vidya Srinivas
---
tests/kms_plane_alpha_blend.c | 4
1 file changed, 4 deletions(-)
diff --git a/tests/kms_plane_alpha_blend.c b/tests/kms_plane_alpha_blend.c
index a37cb27c7d62..224d79bd1749 100644
--- a/tests/kms_plane_alpha_blend.c
+++ b/tests/kms_plane_alpha_blend.c
@@ -447,10 +447,6 @@ static void coverage_premult_constant(data_t *data, enum
pipe pipe, igt_plane_t
igt_display_t *display = &data->display;
igt_crc_t ref_crc = {}, crc = {};
- /* Set a background color on the primary fb for testing */
- if (plane->type != DRM_PLANE_TYPE_PRIMARY)
- igt_plane_set_fb(igt_pipe_get_plane_type(&display->pipes[pipe],
DRM_PLANE_TYPE_PRIMARY), &data->gray_fb);
-
igt_plane_set_prop_enum(plane, IGT_PLANE_PIXEL_BLEND_MODE, "Coverage");
igt_plane_set_fb(plane, &data->argb_fb_cov_7e);
igt_display_commit2(display, COMMIT_ATOMIC);
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Only set bind_async_flags when concurrent access wa is not active, v3.
== Series Details ==
Series: drm/i915: Only set bind_async_flags when concurrent access wa is not
active, v3.
URL : https://patchwork.freedesktop.org/series/90818/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20246
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20246 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20246, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20246:
### IGT changes ###
Possible regressions
* igt@gem_ctx_create@basic-files:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
Known issues
Here are the changes found in Patchwork_20246 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-jsl-1}: [DMESG-WARN][3] ([i915#1222]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-jsl-1/igt@i915_selftest@live@gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-jsl-1/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][5] ([i915#1372]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
Warnings
* igt@i915_selftest@live@execlists:
- fi-tgl-u2: [INCOMPLETE][7] ([i915#3462]) -> [DMESG-FAIL][8]
([i915#3462])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-tgl-u2/igt@i915_selftest@l...@execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-tgl-u2/igt@i915_selftest@l...@execlists.html
- fi-cml-s: [DMESG-FAIL][9] ([i915#3462]) -> [INCOMPLETE][10]
([i915#3462])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cml-s/igt@i915_selftest@l...@execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-cml-s/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-glk-dsi: [FAIL][11] ([i915#2426] / [i915#3363] /
[k.org#202321]) -> [FAIL][12] ([i915#3363] / [k.org#202321])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-glk-dsi/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-r: [FAIL][13] ([i915#1436] / [i915#3363]) -> [FAIL][14]
([i915#1569] / [i915#192] / [i915#193] / [i915#194] / [i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-r/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-kbl-r/igt@run...@aborted.html
- fi-kbl-soraka: [FAIL][15] ([i915#1436] / [i915#3363]) -> [FAIL][16]
([i915#1436] / [i915#2426] / [i915#3363])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-soraka/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-kbl-soraka/igt@run...@aborted.html
- fi-cml-u2: [FAIL][17] ([i915#3363] / [i915#3462]) -> [FAIL][18]
([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cml-u2/igt@run...@aborted.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-cml-u2/igt@run...@aborted.html
- fi-bxt-dsi: [FAIL][19] ([i915#3363]) -> [FAIL][20] ([i915#2426] /
[i915#3363])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-bxt-dsi/igt@run...@aborted.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-bxt-dsi/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1222]: https://gitlab.freedesktop.org/drm/intel/issues/1222
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569
[i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192
[i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193
[i915#194]: https://gitla
Re: [Intel-gfx] [PATCH 1/2] drm/i915/xelpd: Enabling dithering after the CC1
-Original Message-
From: Modem, Bhanuprakash
Sent: Wednesday, May 26, 2021 9:29 PM
To: Jani Nikula ; intel-gfx@lists.freedesktop.org;
Varide, Nischal ; Shankar, Uma
; Gupta, Anshuman
Subject: RE: [Intel-gfx] [PATCH 1/2] drm/i915/xelpd: Enabling dithering after
the CC1
> From: Jani Nikula
> Sent: Wednesday, May 26, 2021 7:34 PM
> To: Modem, Bhanuprakash ; intel-
> g...@lists.freedesktop.org; Varide, Nischal ;
> Shankar, Uma ; Gupta, Anshuman
>
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/xelpd: Enabling
> dithering after the CC1
>
> On Wed, 26 May 2021, Bhanuprakash Modem wrote:
> > From: Nischal Varide
> >
> > If the panel is 12bpc then Dithering is not enabled in the Legacy
> > dithering block , instead its Enabled after the C1 CC1 pipe post
> > color space conversion.For a 6bpc pannel Dithering is enabled in
> > Legacy block.
> >
> > Signed-off-by: Nischal Varide
>
> When you're sending someone else's patches, you need to add your own
> Signed-off-by here.
Patch 2/2 in this series has a dependency on this patch. And I haven't made any
changes in this patch, so not added my Signed-off-by :-)
- Bhanu
>
> > ---
> > drivers/gpu/drm/i915/display/intel_color.c | 15 +++
> > drivers/gpu/drm/i915/display/intel_display.c | 7 ++-
> > drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> > 3 files changed, 23 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> > index dab892d2251b..4ad5bd849695 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -1605,6 +1605,20 @@ static u32 icl_csc_mode(const struct
> > intel_crtc_state
> *crtc_state)
> > return csc_mode;
> > }
> >
> > +static u32 dither_after_cc1_12bpc(const struct intel_crtc_state
> *crtc_state)
> > +{
> > + u32 gamma_mode = crtc_state->gamma_mode;
> > + struct drm_i915_private *i915 =
> > +to_i915(crtc_state->uapi.crtc->dev);
> > +
> > + if (DISPLAY_VER(i915) >= 13) {
> > + if (!crtc_state->dither_force_disable &&
> > + (crtc_state->pipe_bpp == 36))
> > + gamma_mode |= GAMMA_MODE_DITHER_AFTER_CC1;
> > + }
> > +
> > + return gamma_mode;
> > +}
> > +
> > static int icl_color_check(struct intel_crtc_state *crtc_state) {
> > int ret;
> > @@ -1615,6 +1629,7 @@ static int icl_color_check(struct
> > intel_crtc_state
> *crtc_state)
> >
> > crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
> >
> > + crtc_state->gamma_mode = dither_after_cc1_12bpc(crtc_state);
>
> We don't really do the kind of thing where you need a sequence of
> calls where one depends on the other, adding to the same state member.
> At a glance, this just looks wrong, superficially overwriting the
> previously set value. I'd just add the check at the end of icl_gamma_mode().
Yes ,agree and will do the needful here.
>
> > crtc_state->csc_mode = icl_csc_mode(crtc_state);
> >
> > crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> > index 0bb2e582c87f..1a658bdaeab6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -5741,7 +5741,12 @@ static void bdw_set_pipemisc(const struct
> intel_crtc_state *crtc_state)
> > break;
> > }
> >
> > - if (crtc_state->dither)
> > + /*
> > +* If 12bpc panel then, Enables dithering after the CC1 pipe
> > +* post color space conversion and not here
> > +*/
> > +
> > + if (crtc_state->dither && (crtc_state->pipe_bpp != 36))
>
> This now duplicates the pipe_bpp condition in two places, which seems
> a bit fragile. Maybe the check should be on gamma_mode? It would
> remove the need for the whole comment above.
There are two bits for controlling the dithering one at pipe level and other at
gamma level,
So the checks at two places .
> > val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
> >
> > if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> > index 4dbe79009c0e..5700097475c0 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6155,7 +6155,7 @@ enum {
> > #define PIPEMISC_DITHER_8_BPC(0 << 5)
> > #define PIPEMISC_DITHER_10_BPC (1 << 5)
> > #define PIPEMISC_DITHER_6_BPC(2 << 5)
> > -#define PIPEMISC_DITHER_12_BPC (3 << 5)
> > +#define PIPEMISC_DITHER_12_BPC (4 << 5)
>
> We already use the macro. You can't just replace this like this
> without an explanation. Why would this not break existing stuff?
>
> > #define PIPEMISC_DITHER_ENABLE (1 << 4)
> > #define PIPEMISC_DITHER_TYPE_MASK(3 << 2)
> > #define PI
Re: [Intel-gfx] [PATCH] drm/i915: Use DRIVER_NAME for tracing unattached requests
On Tue, Jun 1, 2021 at 1:13 PM Matthew Auld wrote: > On 31/05/2021 08:53, Daniel Vetter wrote: > > On Thu, May 20, 2021 at 4:28 PM Daniel Vetter wrote: > >> > >> On Thu, May 20, 2021 at 08:35:14AM +0100, Matthew Auld wrote: > >>> From: Chris Wilson > >>> > >>> The first tracepoint for a request is trace_dma_fence_init called before > >>> we have associated the request with a device. The tracepoint uses > >>> fence->ops->get_driver_name() as a pretty name, and as we try to report > >>> the device name this oopses as it is then NULL. Support the early > >>> tracepoint by reporting the DRIVER_NAME instead of the actual device > >>> name. > >>> > >>> Note that rq->engine remains during the course of request recycling > >>> (SLAB_TYPESAFE_BY_RCU). For the physical engines, the pointer remains > >>> valid, however a virtual engine may be destroyed after the request is > >>> retired. If we process a preempt-to-busy completed request along the > >>> virtual engine, we should make sure we mark the request as no longer > >>> belonging to the virtual engine to remove the dangling pointers from the > >>> tracepoint. > >> > >> Why can't we assign the request beforehand? The idea behind these > >> tracepoints is that they actually match up, if trace_dma_fence_init is > >> different, then we're breaking that. > > > > Ok I looked a bit more and pondered this a bit, and the initial > > tracepoint is called from dma_fence_init, where we haven't yet set up > > rq->engine properly. So that part makes sense, but should have a > > bigger comment that explains this a bit more and why we can't solve > > this in a neater way. Probably should also drop the unlikely(), this > > isn't a performance critical path, ever. > > > > The other changes thgouh feel like they should be split out into a > > separate path, since they solve a conceptually totally different > > issue: SLAB_TYPESAFE_BY_RCU recycling. > > Hmm, I thought it all stems from having to tread very carefully around > SLAB_TYPESAFE_BY_RCU? If this were "normal" code, we would just allocate > the rq, initialise it properly, including the rq->engine, and only then > do the dma_fence_init? Or am I missing something? Uh, if this is the bug it's a lot more scary. SLAB_TYPESAFE_BY_RCU should only rear it's ugly head if we do clever tricks where we access pointers to dma_fence under rcu alone, _without_ holding a full dma_fence reference. As soon as we have a full reference (and checked that the reference is to the right fence, since we could race) then all this recycle issues are gonne since the kref_t provides the right barrier here. If we hit any of the dma_fence tracepoints without a full reference held then I think that's a bug an needs to be fixed. Maybe we should have a debug WARN_ON(!kref(dma_fence)>0)); in these tracepoints somewhere to prevent this. Doing real dma_fence ops without a refcount held is really too much clever imo, and even if we'd find some microbenchmark showing that e.g. the dma_fence_get/put around some dma_fence function we're calling is measurable, it's not worth the cost in bugfixes like this one here. And when we do hold a full reference, then the only problem I've found is that we call dma_fence_init before the request is fully set up, which is at least semi-reasonable and can easily be checked for and explained with a comment. I thought I looked at the code, and reordering the request init to not have this problem looked tricky. Another issue which would also be very questionable design that we need to re-analyze would be if the engine can disappear before the last reference for the dma_fence has been dropped. I'd also just call this a bug in our refcounting, this should be impossible, but I haven't checked. In all these cases SLAB_TYPESAFE_BY_RCU shouldn't make the situation worse, and if it does, it's a separate issue really. > I'm happy to split it though. And I think that bit at least fixes the > user reported issue I think. So thinking about this some more, if you think this can be easily fixed by pushing the dma_fence_init past the initialization of rq->engine, then that would probably be the cleanest fix of all of them. Assuming none of the above consideration point at further trouble (but then further trouble probably needs separate patches to address them). > > And I'm honestly not sure about > > that one whether it's even correct, there's another patch floating > > around that sprinkles rcu_read_lock around some of these accesssors, > > and that would be a breakage of dma_fence interaces where outside of > > i915 rcu isn't required for this stuff. So imo should be split out, > > and come with a wider analysis of what's going on there and why and > > how exactly i915 works. > > > > In generally SLAB_TYPESAFE_BY_RCU is extremely dangerous and I'm > > frankly not sure we have the perf data (outside of contrived > > microbenchmarks) showing that it's needed and justifies all the costs > > it's encurring. > > Right, I can try to sea
Re: [Intel-gfx] [PATCH] drm/i915: Add relocation exceptions for two other platforms
On Tue, 01 Jun 2021, Zbigniew Kempczyński
wrote:
> We have established previously we stop using relocations starting
> from gen12 platforms with Tigerlake as an exception. We keep this
> statement but we want to enable relocations conditionally for
> Rocketlake and Alderlake under require_force_probe flag set.
>
> Keeping relocations under require_force_probe flag is interim solution
> until IGTs will be rewritten to use softpin.
>
> Signed-off-by: Zbigniew Kempczyński
> Cc: Dave Airlie
> Cc: Daniel Vetter
> Cc: Jason Ekstrand
> ---
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 26 +++
> 1 file changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 297143511f99..c0562dd14837 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -491,16 +491,32 @@ eb_unreserve_vma(struct eb_vma *ev)
> ev->flags &= ~__EXEC_OBJECT_RESERVED;
> }
>
> +static inline bool
Please don't use the inline keyword in .c files. Let the compiler do its
job.
BR,
Jani.
> +platform_has_relocs_enabled(const struct i915_execbuffer *eb)
> +{
> + /*
> + * Relocations are disallowed starting from gen12 with Tigerlake
> + * as an exception. We allow temporarily use relocations for Rocketlake
> + * and Alderlake when require_force_probe flag is set.
> + */
> +
> + if (INTEL_GEN(eb->i915) < 12 || IS_TIGERLAKE(eb->i915))
> + return true;
> +
> + if (INTEL_INFO(eb->i915)->require_force_probe &&
> + (IS_ROCKETLAKE(eb->i915) || IS_ALDERLAKE_S(eb->i915) ||
> + IS_ALDERLAKE_P(eb->i915)))
> + return true;
> +
> + return false;
> +}
> +
> static int
> eb_validate_vma(struct i915_execbuffer *eb,
> struct drm_i915_gem_exec_object2 *entry,
> struct i915_vma *vma)
> {
> - /* Relocations are disallowed for all platforms after TGL-LP. This
> - * also covers all platforms with local memory.
> - */
> - if (entry->relocation_count &&
> - INTEL_GEN(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
> + if (entry->relocation_count && !platform_has_relocs_enabled(eb))
> return -EINVAL;
>
> if (unlikely(entry->flags & eb->invalid_flags))
--
Jani Nikula, Intel Open Source Graphics Center
___
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Re: [Intel-gfx] [PATCH v9 07/15] drm: Add a prefetching memcpy_from_wc
On Tue, 01 Jun 2021, Thomas Hellström wrote:
> Reading out of write-combining mapped memory is typically very slow
> since the CPU doesn't prefetch. However some archs have special
> instructions to do this.
>
> So add a best-effort memcpy_from_wc taking dma-buf-map pointer
> arguments that attempts to use a fast prefetching memcpy and
> otherwise falls back to ordinary memcopies, taking the iomem tagging
> into account.
>
> The code is largely copied from i915_memcpy_from_wc.
>
> Cc: Daniel Vetter
> Cc: Christian König
> Suggested-by: Daniel Vetter
> Signed-off-by: Thomas Hellström
> Acked-by: Christian König
> Acked-by: Daniel Vetter
> ---
> v7:
> - Perform a memcpy even if warning with in_interrupt(). Suggested by
> Christian König.
> - Fix compilation failure on !X86 (Reported by kernel test robot
> l...@intel.com)
> v8:
> - Skip kerneldoc for drm_memcpy_init_early()
> - Export drm_memcpy_from_wc() also for non-x86.
> ---
> Documentation/gpu/drm-mm.rst | 2 +-
> drivers/gpu/drm/drm_cache.c | 148 +++
> drivers/gpu/drm/drm_drv.c| 2 +
> include/drm/drm_cache.h | 7 ++
> 4 files changed, 158 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst
> index 21be6deadc12..c66058c5bce7 100644
> --- a/Documentation/gpu/drm-mm.rst
> +++ b/Documentation/gpu/drm-mm.rst
> @@ -469,7 +469,7 @@ DRM MM Range Allocator Function References
> .. kernel-doc:: drivers/gpu/drm/drm_mm.c
> :export:
>
> -DRM Cache Handling
> +DRM Cache Handling and Fast WC memcpy()
> ==
The title underline needs to be as long as the title.
BR,
Jani.
>
> .. kernel-doc:: drivers/gpu/drm/drm_cache.c
> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> index 79a50ef1250f..546599f19a93 100644
> --- a/drivers/gpu/drm/drm_cache.c
> +++ b/drivers/gpu/drm/drm_cache.c
> @@ -28,6 +28,7 @@
> * Authors: Thomas Hellström
> */
>
> +#include
> #include
> #include
> #include
> @@ -35,6 +36,9 @@
>
> #include
>
> +/* A small bounce buffer that fits on the stack. */
> +#define MEMCPY_BOUNCE_SIZE 128
> +
> #if defined(CONFIG_X86)
> #include
>
> @@ -209,3 +213,147 @@ bool drm_need_swiotlb(int dma_bits)
> return max_iomem > ((u64)1 << dma_bits);
> }
> EXPORT_SYMBOL(drm_need_swiotlb);
> +
> +static void memcpy_fallback(struct dma_buf_map *dst,
> + const struct dma_buf_map *src,
> + unsigned long len)
> +{
> + if (!dst->is_iomem && !src->is_iomem) {
> + memcpy(dst->vaddr, src->vaddr, len);
> + } else if (!src->is_iomem) {
> + dma_buf_map_memcpy_to(dst, src->vaddr, len);
> + } else if (!dst->is_iomem) {
> + memcpy_fromio(dst->vaddr, src->vaddr_iomem, len);
> + } else {
> + /*
> + * Bounce size is not performance tuned, but using a
> + * bounce buffer like this is significantly faster than
> + * resorting to ioreadxx() + iowritexx().
> + */
> + char bounce[MEMCPY_BOUNCE_SIZE];
> + void __iomem *_src = src->vaddr_iomem;
> + void __iomem *_dst = dst->vaddr_iomem;
> +
> + while (len >= MEMCPY_BOUNCE_SIZE) {
> + memcpy_fromio(bounce, _src, MEMCPY_BOUNCE_SIZE);
> + memcpy_toio(_dst, bounce, MEMCPY_BOUNCE_SIZE);
> + _src += MEMCPY_BOUNCE_SIZE;
> + _dst += MEMCPY_BOUNCE_SIZE;
> + len -= MEMCPY_BOUNCE_SIZE;
> + }
> + if (len) {
> + memcpy_fromio(bounce, _src, MEMCPY_BOUNCE_SIZE);
> + memcpy_toio(_dst, bounce, MEMCPY_BOUNCE_SIZE);
> + }
> + }
> +}
> +
> +#ifdef CONFIG_X86
> +
> +static DEFINE_STATIC_KEY_FALSE(has_movntdqa);
> +
> +static void __memcpy_ntdqa(void *dst, const void *src, unsigned long len)
> +{
> + kernel_fpu_begin();
> +
> + while (len >= 4) {
> + asm("movntdqa (%0), %%xmm0\n"
> + "movntdqa 16(%0), %%xmm1\n"
> + "movntdqa 32(%0), %%xmm2\n"
> + "movntdqa 48(%0), %%xmm3\n"
> + "movaps %%xmm0, (%1)\n"
> + "movaps %%xmm1, 16(%1)\n"
> + "movaps %%xmm2, 32(%1)\n"
> + "movaps %%xmm3, 48(%1)\n"
> + :: "r" (src), "r" (dst) : "memory");
> + src += 64;
> + dst += 64;
> + len -= 4;
> + }
> + while (len--) {
> + asm("movntdqa (%0), %%xmm0\n"
> + "movaps %%xmm0, (%1)\n"
> + :: "r" (src), "r" (dst) : "memory");
> + src += 16;
> + dst += 16;
> + }
> +
> + kernel_fpu_end();
> +}
> +
> +/*
> + * __drm_memcpy_from_wc copies @len bytes from @src to @dst using
> + * non-temporal instructions where available. Note that all arguments
> + * (@sr
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add relocation exceptions for two other platforms (rev3)
On Tue, Jun 01, 2021 at 11:36:54AM +, Patchwork wrote: >Patch Details > >Series: drm/i915: Add relocation exceptions for two other platforms > (rev3) >URL: https://patchwork.freedesktop.org/series/89594/ > >State: failure > >Details: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/index.html > > CI Bug Log - changes from CI_DRM_10153_full -> Patchwork_20244_full > > Summary > >FAILURE > >Serious unknown changes coming with Patchwork_20244_full absolutely need >to be >verified manually. > >If you think the reported changes have nothing to do with the changes >introduced in Patchwork_20244_full, please notify your bug team to allow >them >to document this new failure mode, which will reduce false positives in >CI. > > Possible new issues > >Here are the unknown changes that may have been introduced in >Patchwork_20244_full: > > IGT changes > > Possible regressions > > * igt@kms_plane_lowres@pipe-a-tiling-y: > * shard-iclb: NOTRUN -> SKIP > > Piglit changes > > Possible regressions > > * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 >8 128 4 (NEW): > * pig-glk-j5005: NOTRUN -> INCOMPLETE +1 similar issue I don't think change is related to regression mentiontioned above. -- Zbigniew > > New tests > >New tests have been introduced between CI_DRM_10153_full and >Patchwork_20244_full: > > New Piglit tests (2) > > * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 >8 128 4: > > * Statuses : 1 incomplete(s) > * Exec time: [0.0] s > * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 >8 128 7: > > * Statuses : 1 incomplete(s) > * Exec time: [0.0] s > > Known issues > >Here are the changes found in Patchwork_20244_full that come from known >issues: > > IGT changes > > Issues hit > > * igt@gem_create@create-clear: > > * shard-glk: PASS -> FAIL ([i915#3160]) > * igt@gem_ctx_persistence@engines-hostile@rcs0: > > * shard-glk: PASS -> FAIL ([i915#2410]) > * igt@gem_ctx_persistence@legacy-engines-mixed: > > * shard-snb: NOTRUN -> SKIP ([fdo#109271] / [i915#1099]) +8 similar > issues > * igt@gem_ctx_persistence@many-contexts: > > * shard-tglb: PASS -> FAIL ([i915#2410]) > * igt@gem_eio@unwedge-stress: > > * shard-snb: NOTRUN -> FAIL ([i915#3354]) > * igt@gem_exec_fair@basic-deadline: > > * shard-apl: NOTRUN -> FAIL ([i915#2846]) > * igt@gem_exec_fair@basic-throttle@rcs0: > > * shard-glk: PASS -> FAIL ([i915#2842]) > * igt@gem_exec_params@secure-non-master: > > * shard-iclb: NOTRUN -> SKIP ([fdo#112283]) > * igt@gem_media_vme: > > * shard-skl: NOTRUN -> SKIP ([fdo#109271]) +37 similar issues > * igt@gem_mmap_gtt@cpuset-basic-small-copy: > > * shard-skl: PASS -> INCOMPLETE ([i915#198] / [i915#3468]) > * igt@gem_mmap_gtt@cpuset-basic-small-copy-odd: > > * shard-apl: NOTRUN -> INCOMPLETE ([i915#3468]) +1 similar issue > * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy: > > * shard-tglb: PASS -> INCOMPLETE ([i915#3468]) > * igt@gem_mmap_gtt@fault-concurrent-y: > > * shard-snb: NOTRUN -> INCOMPLETE ([i915#3468]) +1 similar issue > * igt@gem_pread@exhaustion: > > * shard-snb: NOTRUN -> WARN ([i915#2658]) > > * shard-skl: NOTRUN -> WARN ([i915#2658]) > > * igt@gem_userptr_blits@dmabuf-sync: > > * shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#3323]) > * igt@gem_userptr_blits@input-checking: > > * shard-snb: NOTRUN -> DMESG-WARN ([i915#3002]) > * igt@gem_userptr_blits@invalid-mmap-offset-unsync: > > * shard-iclb: NOTRUN -> SKIP ([i915#3297]) > * igt@gen9_exec_parse@batch-zero-length: > > * shard-iclb: NOTRUN -> SKIP ([fdo#112306]) > * igt@gen9_exec_parse@bb-large: > > * shard-apl: NOTRUN -> FAIL ([i915#3296]) > * igt@i915_pm_rpm@modeset-lpsp-stress: > > * shard-apl: NOTRUN -> SKIP ([fdo#109271]) +181 similar issues > * igt@i915_suspend@forcewake: > > * shard-kbl: PASS -> DMESG-WARN ([i915#180]) +3 similar issues > * igt@kms_big_fb@linear-16bpp-rotate-90: > > * shard-iclb: NOTRUN -> SKIP ([fdo#110725] / [fdo#111614]) > * igt@kms_color@pipe-b-ctm-0-5: > > * shard-skl: PASS -> DMESG-WARN ([i915#1982]) > * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: > > * shard-snb: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +33 > similar issues > > * shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) > >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Introduce new intel_psr_pause/resume function
== Series Details ==
Series: drm/i915/display: Introduce new intel_psr_pause/resume function
URL : https://patchwork.freedesktop.org/series/90819/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20247
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/index.html
Known issues
Here are the changes found in Patchwork_20247 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][1] ([i915#3303]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][3] ([i915#1372]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
Warnings
* igt@i915_selftest@live@execlists:
- fi-icl-u2: [INCOMPLETE][5] ([i915#2782] / [i915#3462]) ->
[DMESG-FAIL][6] ([i915#3462])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-icl-u2/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-icl-u2/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-icl-u2: [FAIL][7] ([i915#2782] / [i915#3363]) -> [FAIL][8]
([i915#2426] / [i915#2782] / [i915#3363])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-icl-u2/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-icl-u2/igt@run...@aborted.html
- fi-kbl-r: [FAIL][9] ([i915#1436] / [i915#3363]) -> [FAIL][10]
([i915#1436] / [i915#2426] / [i915#3363])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-r/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-kbl-r/igt@run...@aborted.html
- fi-kbl-soraka: [FAIL][11] ([i915#1436] / [i915#3363]) -> [FAIL][12]
([i915#1436] / [i915#2426] / [i915#3363])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-soraka/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-kbl-soraka/igt@run...@aborted.html
- fi-kbl-7500u: [FAIL][13] ([i915#1436] / [i915#3363]) -> [FAIL][14]
([i915#1436] / [i915#2426] / [i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-kbl-7500u/igt@run...@aborted.html
- fi-cfl-guc: [FAIL][15] ([i915#2426] / [i915#3363]) -> [FAIL][16]
([i915#3363])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cfl-guc/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-cfl-guc/igt@run...@aborted.html
- fi-kbl-7567u: [FAIL][17] ([i915#1436] / [i915#3363]) -> [FAIL][18]
([i915#1436] / [i915#2426] / [i915#3363])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7567u/igt@run...@aborted.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-kbl-7567u/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
Participating hosts (47 -> 41)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-kbl-guc fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_10154 -> Patchwork_20247
CI-20190529: 20190529
CI_DRM_10154: 810010ed3d29e0500d452a90010a88a0879f2b45 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6097: f823d8ec14b34a6dd2c0804c684b07b0a50f7bb7 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20247: fb189a25c075a0ca12cc40723571630361a4b10d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fb189a25c075 drm/i915/display: Introduce new intel_psr_pause/resume function
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enhance pipe color support for multi segmented luts
== Series Details == Series: Enhance pipe color support for multi segmented luts URL : https://patchwork.freedesktop.org/series/90821/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd
[Intel-gfx] [PATCH v2 1/2] drm/i915/display: Introduce new intel_psr_pause/resume function
This introduces the following function that can exit and activate a psr
source when intel_psr is already enabled.
- intel_psr_pause(): Pause current PSR. It deactivates current psr state.
- intel_psr_resume(): Resume paused PSR. It activates paused psr state.
v2: Address Jose's review comment.
- Remove unneeded changes around the intel_psr_enable().
- Add intel_psr_post_exit() which processes waiting until PSR is idle
and WA for SelectiveFetch.
Cc: José Roberto de Souza
Cc: Stanislav Lisovskiy
Cc: Ville Syrjälä
Signed-off-by: Gwan-gyeong Mun
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 84 ---
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
3 files changed, 76 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index b8d1f702d808..ee7cbdd7db87 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1482,6 +1482,7 @@ struct intel_psr {
bool sink_support;
bool source_support;
bool enabled;
+ bool paused;
enum pipe pipe;
enum transcoder transcoder;
bool active;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 000e1ffe8c05..4ff71e529cd3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1113,6 +1113,7 @@ static void intel_psr_enable_locked(struct intel_dp
*intel_dp,
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp);
intel_dp->psr.enabled = true;
+ intel_dp->psr.paused = false;
intel_psr_activate(intel_dp);
}
@@ -1182,22 +1183,12 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
intel_dp->psr.active = false;
}
-static void intel_psr_disable_locked(struct intel_dp *intel_dp)
+static void intel_psr_post_exit(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
i915_reg_t psr_status;
u32 psr_status_mask;
- lockdep_assert_held(&intel_dp->psr.lock);
-
- if (!intel_dp->psr.enabled)
- return;
-
- drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
- intel_dp->psr.psr2_enabled ? "2" : "1");
-
- intel_psr_exit(intel_dp);
-
if (intel_dp->psr.psr2_enabled) {
psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
@@ -1217,6 +1208,22 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
+}
+
+static void intel_psr_disable_locked(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ lockdep_assert_held(&intel_dp->psr.lock);
+
+ if (!intel_dp->psr.enabled)
+ return;
+
+ drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
+ intel_dp->psr.psr2_enabled ? "2" : "1");
+
+ intel_psr_exit(intel_dp);
+ intel_psr_post_exit(intel_dp);
/* Disable PSR on Sink */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
@@ -1254,6 +1261,61 @@ void intel_psr_disable(struct intel_dp *intel_dp,
cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
}
+/**
+ * intel_psr_pause - Pause PSR
+ * @intel_dp: Intel DP
+ *
+ * This function need to be called after enabling psr.
+ */
+void intel_psr_pause(struct intel_dp *intel_dp)
+{
+ struct intel_psr *psr = &intel_dp->psr;
+
+ if (!CAN_PSR(intel_dp))
+ return;
+
+ mutex_lock(&psr->lock);
+
+ if (!psr->active) {
+ mutex_unlock(&psr->lock);
+ return;
+ }
+
+ intel_psr_exit(intel_dp);
+ intel_psr_post_exit(intel_dp);
+ psr->paused = true;
+
+ mutex_unlock(&psr->lock);
+
+ cancel_work_sync(&psr->work);
+ cancel_delayed_work_sync(&psr->dc3co_work);
+}
+
+/**
+ * intel_psr_resume - Resume PSR
+ * @intel_dp: Intel DP
+ *
+ * This function need to be called after pausing psr.
+ */
+void intel_psr_resume(struct intel_dp *intel_dp)
+{
+ struct intel_psr *psr = &intel_dp->psr;
+
+ if (!CAN_PSR(intel_dp))
+ return;
+
+ mutex_lock(&psr->lock);
+
+ if (!psr->paused)
+ goto unlock;
+
+ psr->paused = false;
+ intel_psr_activate(intel_dp);
+
+unlock:
+ mutex_unlock(&psr->lock);
+}
+
static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
b/drivers/gpu/drm/i915/display
[Intel-gfx] [PATCH v2 2/2] drm/i915: Disable PSR around cdclk changes
From: Ville Syrjälä
AUX logic is often clocked from cdclk. Disable PSR to make sure
there are no hw initiated AUX transactions in flight while we
change the cdclk frequency.
Cc: Mika Kahola
Signed-off-by: Ville Syrjälä
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4656a6edc3be..618a9e1e2b0c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -28,6 +28,7 @@
#include "intel_cdclk.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_psr.h"
#include "intel_sideband.h"
/**
@@ -1908,6 +1909,12 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_psr_pause(intel_dp);
+ }
+
/*
* Lock aux/gmbus while we change cdclk in case those
* functions use cdclk. Not all platforms/ports do,
@@ -1930,6 +1937,12 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
}
mutex_unlock(&dev_priv->gmbus_mutex);
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_psr_resume(intel_dp);
+ }
+
if (drm_WARN(&dev_priv->drm,
intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
"cdclk state doesn't match!\n")) {
--
2.31.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/display: Introduce new intel_psr_pause/resume function
Another patchset has been uploaded. Please ignore this patch.
On Tue, 2021-06-01 at 12:53 +0300, Gwan-gyeong Mun wrote:
> This introduces the following function that can exit and activate a
> psr
> source when intel_psr is already enabled.
>
> - intel_psr_pause(): Pause current PSR. It deactivates current psr
> state.
> - intel_psr_resume(): Resume paused PSR. It activates paused psr
> state.
>
> v2: Address Jose's review comment.
> - Remove unneeded changes around the intel_psr_enable().
> - Add intel_psr_post_exit() which processes waiting until PSR is
> idle
> and WA for SelectiveFetch.
>
> Cc: José Roberto de Souza
> Cc: Stanislav Lisovskiy
> Cc: Ville Syrjälä
> Signed-off-by: Gwan-gyeong Mun
> Signed-off-by: Matt Roper
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 84 -
> --
> drivers/gpu/drm/i915/display/intel_psr.h | 2 +
> 3 files changed, 76 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b8d1f702d808..ee7cbdd7db87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1482,6 +1482,7 @@ struct intel_psr {
> bool sink_support;
> bool source_support;
> bool enabled;
> + bool paused;
> enum pipe pipe;
> enum transcoder transcoder;
> bool active;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 000e1ffe8c05..4ff71e529cd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1113,6 +1113,7 @@ static void intel_psr_enable_locked(struct
> intel_dp *intel_dp,
> intel_psr_enable_sink(intel_dp);
> intel_psr_enable_source(intel_dp);
> intel_dp->psr.enabled = true;
> + intel_dp->psr.paused = false;
>
> intel_psr_activate(intel_dp);
> }
> @@ -1182,22 +1183,12 @@ static void intel_psr_exit(struct intel_dp
> *intel_dp)
> intel_dp->psr.active = false;
> }
>
> -static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> +static void intel_psr_post_exit(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> i915_reg_t psr_status;
> u32 psr_status_mask;
>
> - lockdep_assert_held(&intel_dp->psr.lock);
> -
> - if (!intel_dp->psr.enabled)
> - return;
> -
> - drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
> - intel_dp->psr.psr2_enabled ? "2" : "1");
> -
> - intel_psr_exit(intel_dp);
> -
> if (intel_dp->psr.psr2_enabled) {
> psr_status = EDP_PSR2_STATUS(intel_dp-
> >psr.transcoder);
> psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
> @@ -1217,6 +1208,22 @@ static void intel_psr_disable_locked(struct
> intel_dp *intel_dp)
> IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> +}
> +
> +static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + lockdep_assert_held(&intel_dp->psr.lock);
> +
> + if (!intel_dp->psr.enabled)
> + return;
> +
> + drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
> + intel_dp->psr.psr2_enabled ? "2" : "1");
> +
> + intel_psr_exit(intel_dp);
> + intel_psr_post_exit(intel_dp);
>
> /* Disable PSR on Sink */
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
> @@ -1254,6 +1261,61 @@ void intel_psr_disable(struct intel_dp
> *intel_dp,
> cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
> }
>
> +/**
> + * intel_psr_pause - Pause PSR
> + * @intel_dp: Intel DP
> + *
> + * This function need to be called after enabling psr.
> + */
> +void intel_psr_pause(struct intel_dp *intel_dp)
> +{
> + struct intel_psr *psr = &intel_dp->psr;
> +
> + if (!CAN_PSR(intel_dp))
> + return;
> +
> + mutex_lock(&psr->lock);
> +
> + if (!psr->active) {
> + mutex_unlock(&psr->lock);
> + return;
> + }
> +
> + intel_psr_exit(intel_dp);
> + intel_psr_post_exit(intel_dp);
> + psr->paused = true;
> +
> + mutex_unlock(&psr->lock);
> +
> + cancel_work_sync(&psr->work);
> + cancel_delayed_work_sync(&psr->dc3co_work);
> +}
> +
> +/**
> + * intel_psr_resume - Resume PSR
> + * @intel_dp: Intel DP
> + *
> + * This function need to be called after pausing psr.
> + */
> +void intel_psr_resume(struct intel_dp *intel_dp)
> +{
> + struct intel_psr *psr = &intel_dp->psr;
> +
> + if (!CAN_PSR(intel_dp))
> + return;
> +
> +
Re: [Intel-gfx] [PATCH v7 14/15] dt-bindings: of: Add restricted DMA pool
On Thu, May 27, 2021 at 07:29:20PM +0800, Claire Chang wrote:
> On Wed, May 26, 2021 at 11:53 PM Will Deacon wrote:
> >
> > On Wed, May 26, 2021 at 01:13:22PM +0100, Will Deacon wrote:
> > > On Tue, May 18, 2021 at 02:42:14PM +0800, Claire Chang wrote:
> > > > @@ -138,4 +160,9 @@ one for multimedia processing (named
> > > > multimedia-memory@7700, 64MiB).
> > > > memory-region = <&multimedia_reserved>;
> > > > /* ... */
> > > > };
> > > > +
> > > > + pcie_device: pcie_device@0,0 {
> > > > + memory-region = <&restricted_dma_mem_reserved>;
> > > > + /* ... */
> > > > + };
> > >
> > > I still don't understand how this works for individual PCIe devices -- how
> > > is dev->of_node set to point at the node you have above?
> > >
> > > I tried adding the memory-region to the host controller instead, and then
> > > I see it crop up in dmesg:
> > >
> > > | pci-host-generic 4000.pci: assigned reserved memory node
> > > restricted_dma_mem_reserved
> > >
> > > but none of the actual PCI devices end up with 'dma_io_tlb_mem' set, and
> > > so the restricted DMA area is not used. In fact, swiotlb isn't used at
> > > all.
> > >
> > > What am I missing to make this work with PCIe devices?
> >
> > Aha, looks like we're just missing the logic to inherit the DMA
> > configuration. The diff below gets things working for me.
>
> I guess what was missing is the reg property in the pcie_device node.
> Will update the example dts.
Thanks. I still think something like my diff makes sense, if you wouldn't mind
including
it, as it allows restricted DMA to be used for situations where the PCIe
topology is not static.
Perhaps we should prefer dev->of_node if it exists, but then use the node
of the host bridge's parent node otherwise?
Will
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[Intel-gfx] [PATCH 1/1] drm/i915/selftests: Fix error return code in live_parallel_switch()
The error code returned from intel_context_create() should be propagated
instead of 0, as done elsewhere in this function.
Fixes: 50d16d44cce4 ("drm/i915/selftests: Exercise context switching in
parallel")
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 5fef592390cb..7db9e31da385 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -338,8 +338,10 @@ static int live_parallel_switch(void *arg)
continue;
ce = intel_context_create(data[m].ce[0]->engine);
- if (IS_ERR(ce))
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
goto out;
+ }
err = intel_context_pin(ce);
if (err) {
--
2.25.1
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Re: [Intel-gfx] [PATCH 1/1] drm/i915/hdcp: Simplify code in intel_hdcp_auth_downstream()
On 2021/5/27 18:04, Jani Nikula wrote:
> On Thu, 27 May 2021, Zhen Lei wrote:
>> If intel_hdcp_validate_v_prime() has been successful within the allowed
>> number of tries, we can directly call drm_dbg_kms() and "goto out" without
>> jumping out of the loop and repeatedly judging whether the operation is
>> successful. This can help us reduce an unnecessary if judgment. And it's
>> a little clearer to read.
>
> Generally I think the "happy day scenario" should be at the topmost
> indentation level and not buried in the ifs with a goto exit.
for (xxx) {
if (a == b)
return found;
}
At least this way of writing is common.
>
> BR,
> Jani.
>
>>
>> No functional change.
>>
>> Signed-off-by: Zhen Lei
>> ---
>> drivers/gpu/drm/i915/display/intel_hdcp.c | 24 ++-
>> 1 file changed, 10 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
>> b/drivers/gpu/drm/i915/display/intel_hdcp.c
>> index d8570e14fe60..c32a854eda66 100644
>> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
>> @@ -663,13 +663,13 @@ int intel_hdcp_auth_downstream(struct intel_connector
>> *connector)
>>
>> ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo);
>> if (ret)
>> -goto err;
>> +goto out;
>>
>> if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm, ksv_fifo,
>> num_downstream) > 0) {
>> drm_err(&dev_priv->drm, "Revoked Ksv(s) in ksv_fifo\n");
>> ret = -EPERM;
>> -goto err;
>> +goto out;
>> }
>>
>> /*
>> @@ -680,20 +680,16 @@ int intel_hdcp_auth_downstream(struct intel_connector
>> *connector)
>> ret = intel_hdcp_validate_v_prime(connector, shim,
>>ksv_fifo, num_downstream,
>>bstatus);
>> -if (!ret)
>> -break;
>> -}
>> -
>> -if (i == tries) {
>> -drm_dbg_kms(&dev_priv->drm,
>> -"V Prime validation failed.(%d)\n", ret);
>> -goto err;
>> +if (!ret) {
>> +drm_dbg_kms(&dev_priv->drm,
>> +"HDCP is enabled (%d downstream devices)\n",
>> +num_downstream);
>> +goto out;
>> +}
>> }
>>
>> -drm_dbg_kms(&dev_priv->drm, "HDCP is enabled (%d downstream devices)\n",
>> -num_downstream);
>> -ret = 0;
>> -err:
>> +drm_dbg_kms(&dev_priv->drm, "V Prime validation failed.(%d)\n", ret);
>> +out:
>> kfree(ksv_fifo);
>> return ret;
>> }
>
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Re: [Intel-gfx] Bug: 5.12.5 - list_add double add at __i915_gem_object_make_shrinkable+0xa6/0xe0
On Mon, 2021-05-24 at 14:38 +0100, Matthew Auld wrote:
> On Mon, 24 May 2021 at 13:05, Hillf Danton wrote:
> >
> > On Sun, 23 May 2021 12:47:34 -0700 Philippe Troin wrote:
> > > Found the following bug on a FUJITSU LIFEBOOK S6520.
> > >
> > > The kernel crash happens when selecting a user from the gdm login
> > > screen right after boot.
> > > The same hardware has no problems with 5.11.21.
>
> The trace looks similar to something that was fixed in 8777d17b68dc
> ("drm/i915/gem: Pin the L-shape quirked object as unshrinkable") which
> should now be in drm-tip. Could you try that? Otherwise could you
> please file a new bug report at
> https://gitlab.freedesktop.org/drm/intel/?
I verified that drm-tip is working as of
d6d3a2a996af7a82e567e96a19410ac9d7246794.
This issue was tracked in the Fedora bugzilla at
https://bugzilla.redhat.com/show_bug.cgi?id=1963782
Thanks.
Phil.
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[Intel-gfx] [PATCH] drm/i915/gem: Remove the repeated declaration
Function 'i915_gem_object_truncate' is declared twice, so remove the repeated declaration. Cc: Jani Nikula Cc: Joonas Lahtinen Cc: Rodrigo Vivi Signed-off-by: Shaokun Zhang --- drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index 2ebd79537aea..9226f122c329 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -79,7 +79,6 @@ void i915_gem_flush_free_objects(struct drm_i915_private *i915); struct sg_table * __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj); -void i915_gem_object_truncate(struct drm_i915_gem_object *obj); /** * i915_gem_object_lookup_rcu - look up a temporary GEM object from its handle -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 14/15] dt-bindings: of: Add restricted DMA pool
On Thu, May 27, 2021 at 08:48:59PM +0800, Claire Chang wrote:
> On Thu, May 27, 2021 at 7:35 PM Will Deacon wrote:
> >
> > On Thu, May 27, 2021 at 07:29:20PM +0800, Claire Chang wrote:
> > > On Wed, May 26, 2021 at 11:53 PM Will Deacon wrote:
> > > >
> > > > On Wed, May 26, 2021 at 01:13:22PM +0100, Will Deacon wrote:
> > > > > On Tue, May 18, 2021 at 02:42:14PM +0800, Claire Chang wrote:
> > > > > > @@ -138,4 +160,9 @@ one for multimedia processing (named
> > > > > > multimedia-memory@7700, 64MiB).
> > > > > > memory-region = <&multimedia_reserved>;
> > > > > > /* ... */
> > > > > > };
> > > > > > +
> > > > > > + pcie_device: pcie_device@0,0 {
> > > > > > + memory-region = <&restricted_dma_mem_reserved>;
> > > > > > + /* ... */
> > > > > > + };
> > > > >
> > > > > I still don't understand how this works for individual PCIe devices
> > > > > -- how
> > > > > is dev->of_node set to point at the node you have above?
> > > > >
> > > > > I tried adding the memory-region to the host controller instead, and
> > > > > then
> > > > > I see it crop up in dmesg:
> > > > >
> > > > > | pci-host-generic 4000.pci: assigned reserved memory node
> > > > > restricted_dma_mem_reserved
> > > > >
> > > > > but none of the actual PCI devices end up with 'dma_io_tlb_mem' set,
> > > > > and
> > > > > so the restricted DMA area is not used. In fact, swiotlb isn't used
> > > > > at all.
> > > > >
> > > > > What am I missing to make this work with PCIe devices?
> > > >
> > > > Aha, looks like we're just missing the logic to inherit the DMA
> > > > configuration. The diff below gets things working for me.
> > >
> > > I guess what was missing is the reg property in the pcie_device node.
> > > Will update the example dts.
> >
> > Thanks. I still think something like my diff makes sense, if you wouldn't
> > mind including
> > it, as it allows restricted DMA to be used for situations where the PCIe
> > topology is not static.
> >
> > Perhaps we should prefer dev->of_node if it exists, but then use the node
> > of the host bridge's parent node otherwise?
>
> Sure. Let me add in the next version.
Brill, thanks! I'll take it for a spin once it lands on the list.
Will
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Re: [Intel-gfx] [PATCH v7 14/15] dt-bindings: of: Add restricted DMA pool
On Wed, May 26, 2021 at 01:13:22PM +0100, Will Deacon wrote:
> On Tue, May 18, 2021 at 02:42:14PM +0800, Claire Chang wrote:
> > @@ -138,4 +160,9 @@ one for multimedia processing (named
> > multimedia-memory@7700, 64MiB).
> > memory-region = <&multimedia_reserved>;
> > /* ... */
> > };
> > +
> > + pcie_device: pcie_device@0,0 {
> > + memory-region = <&restricted_dma_mem_reserved>;
> > + /* ... */
> > + };
>
> I still don't understand how this works for individual PCIe devices -- how
> is dev->of_node set to point at the node you have above?
>
> I tried adding the memory-region to the host controller instead, and then
> I see it crop up in dmesg:
>
> | pci-host-generic 4000.pci: assigned reserved memory node
> restricted_dma_mem_reserved
>
> but none of the actual PCI devices end up with 'dma_io_tlb_mem' set, and
> so the restricted DMA area is not used. In fact, swiotlb isn't used at all.
>
> What am I missing to make this work with PCIe devices?
Aha, looks like we're just missing the logic to inherit the DMA
configuration. The diff below gets things working for me.
Will
--->8
diff --git a/drivers/of/address.c b/drivers/of/address.c
index c562a9ff5f0b..bf499fdd6e93 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -1113,25 +1113,25 @@ bool of_dma_is_coherent(struct device_node *np)
}
EXPORT_SYMBOL_GPL(of_dma_is_coherent);
-int of_dma_set_restricted_buffer(struct device *dev)
+int of_dma_set_restricted_buffer(struct device *dev, struct device_node *np)
{
- struct device_node *node;
int count, i;
- if (!dev->of_node)
+ if (!np)
return 0;
- count = of_property_count_elems_of_size(dev->of_node, "memory-region",
+ count = of_property_count_elems_of_size(np, "memory-region",
sizeof(phandle));
for (i = 0; i < count; i++) {
- node = of_parse_phandle(dev->of_node, "memory-region", i);
+ struct device_node *node;
+
+ node = of_parse_phandle(np, "memory-region", i);
/* There might be multiple memory regions, but only one
-* restriced-dma-pool region is allowed.
+* restricted-dma-pool region is allowed.
*/
if (of_device_is_compatible(node, "restricted-dma-pool") &&
of_device_is_available(node))
- return of_reserved_mem_device_init_by_idx(
- dev, dev->of_node, i);
+ return of_reserved_mem_device_init_by_idx(dev, np, i);
}
return 0;
diff --git a/drivers/of/device.c b/drivers/of/device.c
index d8d865223e51..2defdca418ec 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -166,7 +166,7 @@ int of_dma_configure_id(struct device *dev, struct
device_node *np,
arch_setup_dma_ops(dev, dma_start, size, iommu, coherent);
if (!iommu)
- return of_dma_set_restricted_buffer(dev);
+ return of_dma_set_restricted_buffer(dev, np);
return 0;
}
diff --git a/drivers/of/of_private.h b/drivers/of/of_private.h
index 9fc874548528..8fde97565d11 100644
--- a/drivers/of/of_private.h
+++ b/drivers/of/of_private.h
@@ -163,14 +163,15 @@ struct bus_dma_region;
#if defined(CONFIG_OF_ADDRESS) && defined(CONFIG_HAS_DMA)
int of_dma_get_range(struct device_node *np,
const struct bus_dma_region **map);
-int of_dma_set_restricted_buffer(struct device *dev);
+int of_dma_set_restricted_buffer(struct device *dev, struct device_node *np);
#else
static inline int of_dma_get_range(struct device_node *np,
const struct bus_dma_region **map)
{
return -ENODEV;
}
-static inline int of_dma_set_restricted_buffer(struct device *dev)
+static inline int of_dma_set_restricted_buffer(struct device *dev,
+ struct device_node *np)
{
return -ENODEV;
}
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[Intel-gfx] [PATCH] drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest()
In case of error, the function live_context() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().
Fixes: 52c0fdb25c7c9 ("drm/i915: Replace global breadcrumbs ...")
Reported-by: Hulk Robot
Signed-off-by: Zhihao Cheng
---
drivers/gpu/drm/i915/selftests/i915_request.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index ee8e753d98ce..eae0abd614cb 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -1592,8 +1592,8 @@ static int live_breadcrumbs_smoketest(void *arg)
for (n = 0; n < smoke[0].ncontexts; n++) {
smoke[0].contexts[n] = live_context(i915, file);
- if (!smoke[0].contexts[n]) {
- ret = -ENOMEM;
+ if (IS_ERR(smoke[0].contexts[n])) {
+ ret = PTR_ERR(smoke[0].contexts[n]);
goto out_contexts;
}
}
--
2.25.4
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[Intel-gfx] [PATCH] INTEL_DII: drm/i915/adl_p: Same slices mask is not same Dbuf state
We currently treat same slice mask as a same DBuf state and skip updating the Dbuf slices, if we detect that. This is wrong as if we have a multi to single pipe change or vice versa, that would be treated as a same Dbuf state and thus no changes required, so we don't get Mbus updated, causing issues. Solution: check also mbus_join, in addition to slices mask. Cc: Ville Syrjälä Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/intel_pm.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 00f3dead20ad..804d83486e81 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8093,7 +8093,8 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state) intel_atomic_get_old_dbuf_state(state); if (!new_dbuf_state || - new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices) + ((new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices) + && (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))) return; WARN_ON(!new_dbuf_state->base.changed); @@ -8113,7 +8114,8 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state) intel_atomic_get_old_dbuf_state(state); if (!new_dbuf_state || - new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices) + ((new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices) + && (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))) return; WARN_ON(!new_dbuf_state->base.changed); -- 2.24.1.485.gad05a3d8e5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/1] drm/i915/hdcp: Simplify code in intel_hdcp_auth_downstream()
If intel_hdcp_validate_v_prime() has been successful within the allowed
number of tries, we can directly call drm_dbg_kms() and "goto out" without
jumping out of the loop and repeatedly judging whether the operation is
successful. This can help us reduce an unnecessary if judgment. And it's
a little clearer to read.
No functional change.
Signed-off-by: Zhen Lei
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 24 ++-
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index d8570e14fe60..c32a854eda66 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -663,13 +663,13 @@ int intel_hdcp_auth_downstream(struct intel_connector
*connector)
ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo);
if (ret)
- goto err;
+ goto out;
if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm, ksv_fifo,
num_downstream) > 0) {
drm_err(&dev_priv->drm, "Revoked Ksv(s) in ksv_fifo\n");
ret = -EPERM;
- goto err;
+ goto out;
}
/*
@@ -680,20 +680,16 @@ int intel_hdcp_auth_downstream(struct intel_connector
*connector)
ret = intel_hdcp_validate_v_prime(connector, shim,
ksv_fifo, num_downstream,
bstatus);
- if (!ret)
- break;
- }
-
- if (i == tries) {
- drm_dbg_kms(&dev_priv->drm,
- "V Prime validation failed.(%d)\n", ret);
- goto err;
+ if (!ret) {
+ drm_dbg_kms(&dev_priv->drm,
+ "HDCP is enabled (%d downstream devices)\n",
+ num_downstream);
+ goto out;
+ }
}
- drm_dbg_kms(&dev_priv->drm, "HDCP is enabled (%d downstream devices)\n",
- num_downstream);
- ret = 0;
-err:
+ drm_dbg_kms(&dev_priv->drm, "V Prime validation failed.(%d)\n", ret);
+out:
kfree(ksv_fifo);
return ret;
}
--
2.25.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for Enhance pipe color support for multi segmented luts
== Series Details ==
Series: Enhance pipe color support for multi segmented luts
URL : https://patchwork.freedesktop.org/series/90821/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20248
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/index.html
Known issues
Here are the changes found in Patchwork_20248 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][1] ([i915#3303]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][3] ([i915#1372]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
Warnings
* igt@runner@aborted:
- fi-cfl-8700k: [FAIL][5] ([i915#3363]) -> [FAIL][6] ([i915#2426] /
[i915#3363])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cfl-8700k/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-cfl-8700k/igt@run...@aborted.html
- fi-glk-dsi: [FAIL][7] ([i915#2426] / [i915#3363] /
[k.org#202321]) -> [FAIL][8] ([i915#3363] / [k.org#202321])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-glk-dsi/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-soraka: [FAIL][9] ([i915#1436] / [i915#3363]) -> [FAIL][10]
([i915#1436] / [i915#2426] / [i915#3363])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-soraka/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-kbl-soraka/igt@run...@aborted.html
- fi-kbl-guc: [FAIL][11] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][12] ([i915#1436] / [i915#3363])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-guc/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-kbl-guc/igt@run...@aborted.html
- fi-cfl-guc: [FAIL][13] ([i915#2426] / [i915#3363]) -> [FAIL][14]
([i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cfl-guc/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-cfl-guc/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (47 -> 42)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_10154 -> Patchwork_20248
CI-20190529: 20190529
CI_DRM_10154: 810010ed3d29e0500d452a90010a88a0879f2b45 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6097: f823d8ec14b34a6dd2c0804c684b07b0a50f7bb7 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20248: 69e66620a121b94c53f9b381c048c32f45eb4fe2 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
69e66620a121 drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
6a09b3df0e61 drm/i915/xelpd: Add Pipe Color Lut caps to platform config
185822ca6347 drm/i915/xelpd: Enable Pipe Degamma
0a9c33e8f72b drm/i915/xelpd: logarithmic gamma enabled only with advance gamma
mode
7709e4e8ae04 drm: Add Client Cap for advance gamma mode
0db66299eaaf drm/i915/xelpd: Attach gamma mode property
0abd23286aa0 drm/i915/xelpd: Add support for Logarithmic gamma mode
fbd5ad2e2de9 drm/i915/xelpd: Define color lut range structure
cbbd9a9e8e24 drm: Add gamma mode property
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/index.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add Support for Plane Color Lut and CSC features
== Series Details == Series: Add Support for Plane Color Lut and CSC features URL : https://patchwork.freedesktop.org/series/90825/ State : warning == Summary == $ dim checkpatch origin/drm-tip 68c5484bfdad drm: Add Enhanced Gamma and color lut range attributes a1e53948f9d0 drm: Add Plane Degamma Mode property 684c709fb80f drm: Add Plane Degamma Lut property -:45: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #45: FILE: drivers/gpu/drm/drm_atomic_uapi.c:602: + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->degamma_lut, total: 0 errors, 0 warnings, 1 checks, 101 lines checked 2bf36d661d4d drm/i915/xelpd: Define Degamma Lut range struct for HDR planes 0c1eabc62705 drm/i915/xelpd: Add register definitions for Plane Degamma -:37: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #37: FILE: drivers/gpu/drm/i915/i915_reg.h:11315: +#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \ + _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)) -:49: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #49: FILE: drivers/gpu/drm/i915/i915_reg.h:11327: +#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i)\ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \ + _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe)) -:61: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #61: FILE: drivers/gpu/drm/i915/i915_reg.h:11339: +#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \ + _PLANE_PRE_CSC_GAMC_INDEX_2(pipe)) -:73: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #73: FILE: drivers/gpu/drm/i915/i915_reg.h:11351: +#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i)\ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \ + _PLANE_PRE_CSC_GAMC_DATA_2(pipe)) total: 0 errors, 0 warnings, 4 checks, 64 lines checked 258e15146869 drm/i915/xelpd: Enable plane color features b7ea85214efd drm/i915/xelpd: Add color capabilities of SDR planes 66e7c29201d7 drm/i915/xelpd: Program Plane Degamma Registers -:68: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #68: FILE: drivers/gpu/drm/i915/display/intel_color.c:2243: + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), -:74: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #74: FILE: drivers/gpu/drm/i915/display/intel_color.c:2249: + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), -:80: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #80: FILE: drivers/gpu/drm/i915/display/intel_color.c:2255: + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v); -:84: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #84: FILE: drivers/gpu/drm/i915/display/intel_color.c:2259: + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), -:114: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #114: FILE: drivers/gpu/drm/i915/display/intel_color.c:2289: + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), v); total: 0 errors, 5 warnings, 0 checks, 148 lines checked ae7be4f9a5ff drm/i915/xelpd: Add plane color check to glk_plane_color_ctl 1f1fa094a94e drm/i915/xelpd: Initialize plane color features ab01acc58f9c drm/i915/xelpd: Load plane color luts from atomic flip 66d7c2419b53 drm: Add Plane CTM property -:41: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #41: FILE: drivers/gpu/drm/drm_atomic_uapi.c:609: + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->ctm, total: 0 errors, 0 warnings, 1 checks, 87 lines checked 08ee867daa81 drm: Add helper to attach Plane ctm property 9d7042c9e95e drm/i915/xelpd: Define Plane CSC Registers -:29: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #29: FILE: drivers/gpu/drm/i915/i915_reg.h:7411: +#define PLANE_CSC_COEFF(pipe, plane, index)_MMIO_PLANE(plane, \ + _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ + _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) -:29: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #29: FILE: drivers/gpu/drm/i915/i915_reg.h:7411: +#define PLANE_CSC_COEFF(pipe, plane, index)_MMIO_PLANE(plane, \ + _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ +
