Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/7] lib/i915/gem_mman: add FIXED mmap mode
On Tue, 27 Jul 2021 19:01:24 -0700, Dixit, Ashutosh wrote: > > On Mon, 26 Jul 2021 05:03:04 -0700, Matthew Auld wrote: > > > > diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c > > index 4b4f2114..e2514f0c 100644 > > --- a/lib/i915/gem_mman.c > > +++ b/lib/i915/gem_mman.c > > @@ -497,6 +497,43 @@ void *gem_mmap_offset__cpu(int fd, uint32_t handle, > > uint64_t offset, > > return ptr; > > } > > > > +#define LOCAL_I915_MMAP_OFFSET_FIXED 4 > > Cc: @Petri Latvala > > This use of LOCAL declarations is more related to the methodology we follow > in IGT rather than this patch. We have seen in the past that such LOCAL's > linger on in the code for months and years till someone decides to clean > them so the question is can we prevent these LOCAL's from getting > introduced in the first place. > > One reason for these is that we sync IGT headers with drm-next whereas IGT > is used to test drm-tip. So the delta between the two results in such > LOCAL's as in this case. > > My proposal is that even if we don't start sync'ing IGT headers with > drm-tip (instead of drm-next) we allow direct modification of the headers > when needed to avoid introducing such LOCAL's. So in the above case we > would add: > > #define I915_MMAP_OFFSET_FIXED 4 > > to i915_drm.h as part of this patch and then just use > I915_MMAP_OFFSET_FIXED. If another sync happens from drm-next before this > #define has appeared there, the compile will break and whoever syncs will > need to add this again to i915_drm.h. > > What do people think about a scheme such as this? The other, perhaps > better, option of course is to sync the headers directly with drm-tip > (whenever and as often as needed). But the goal in both cases is to avoid > LOCAL's, or other things like #ifndef's distributed throughout multiple > source files which we also do in such cases. A centralized internal header > to contain such declarations might not be so bad. Thanks. I have submitted a patch based on this last statement here: https://patchwork.freedesktop.org/series/93096/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/1] drm/i915: dgfx cards need to wait on pcode's uncore init done
== Series Details ==
Series: series starting with [1/1] drm/i915: dgfx cards need to wait on pcode's
uncore init done
URL : https://patchwork.freedesktop.org/series/93075/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10405_full -> Patchwork_20720_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20720_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20720_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20720_full:
### IGT changes ###
Possible regressions
* igt@kms_selftest@all@damage_iter_no_damage:
- shard-apl: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/shard-apl2/igt@kms_selftest@all@damage_iter_no_damage.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_busy@basic-hang:
- {shard-rkl}:NOTRUN -> [SKIP][2] +1 similar issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/shard-rkl-1/igt@kms_b...@basic-hang.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- {shard-rkl}:[SKIP][3] ([i915#1849]) -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-rkl-5/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/shard-rkl-6/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html
Known issues
Here are the changes found in Patchwork_20720_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#658])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-iclb2/igt@feature_discov...@psr2.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/shard-iclb8/igt@feature_discov...@psr2.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +2 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-kbl7/igt@gem_ctx_isolation@preservation...@bcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/shard-kbl7/igt@gem_ctx_isolation@preservation...@bcs0.html
- shard-apl: NOTRUN -> [DMESG-WARN][9] ([i915#180]) +3 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/shard-apl8/igt@gem_ctx_isolation@preservation...@bcs0.html
* igt@gem_ctx_persistence@process:
- shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1099]) +4
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/shard-snb2/igt@gem_ctx_persiste...@process.html
* igt@gem_ctx_shared@q-in-order:
- shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271]) +209 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/shard-snb2/igt@gem_ctx_sha...@q-in-order.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842] / [i915#3468])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-glk7/igt@gem_exec_fair@basic-n...@vecs0.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/shard-glk1/igt@gem_exec_fair@basic-n...@vecs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][14] -> [FAIL][15] ([i915#2851])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-kbl7/igt@gem_exec_fair@basic-p...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/shard-kbl3/igt@gem_exec_fair@basic-p...@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2842]) +1 similar
issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/shard-iclb8/igt@gem_exec_fair@basic-p...@vcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][18] -> [FAIL][19] ([i915#2842]) +2 similar
issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/shard-glk1/igt@gem_exec_fair@basic-throt...@rcs0.html
* igt@gem_exec_whisper@basic-contexts-forked-all:
- shard-glk: [PASS][20] -> [DMESG-WARN][21] ([i915#118] /
[i915#95]) +1 similar issue
[20]:
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adl_p: Allow underrun recovery when possible (rev2)
On Wed, Jul 28, 2021 at 02:29:18AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/adl_p: Allow underrun recovery when possible (rev2)
> URL : https://patchwork.freedesktop.org/series/93054/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_10405_full -> Patchwork_20717_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_20717_full absolutely need to
> be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_20717_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_20717_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@kms_selftest@all@damage_iter_no_damage:
> - shard-apl: NOTRUN -> [INCOMPLETE][1]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-apl7/igt@kms_selftest@all@damage_iter_no_damage.html
This seems to be a regression on all platforms that started in
CI_DRM_10402; it's not related to this series.
Patch applied to di-next; thanks Stan for the review.
Matt
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@i915_selftest@live@execlists:
> - {shard-rkl}:[PASS][2] -> [DMESG-FAIL][3]
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-rkl-5/igt@i915_selftest@l...@execlists.html
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-rkl-5/igt@i915_selftest@l...@execlists.html
>
> * igt@runner@aborted:
> - {shard-rkl}:([FAIL][4], [FAIL][5], [FAIL][6], [FAIL][7])
> ([i915#3002] / [i915#3810] / [i915#3811]) -> ([FAIL][8], [FAIL][9],
> [FAIL][10]) ([i915#3002] / [i915#3811])
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-rkl-5/igt@run...@aborted.html
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-rkl-2/igt@run...@aborted.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-rkl-1/igt@run...@aborted.html
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-rkl-1/igt@run...@aborted.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-rkl-6/igt@run...@aborted.html
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-rkl-5/igt@run...@aborted.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-rkl-5/igt@run...@aborted.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_20717_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@feature_discovery@psr2:
> - shard-iclb: [PASS][11] -> [SKIP][12] ([i915#658])
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-iclb2/igt@feature_discov...@psr2.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-iclb4/igt@feature_discov...@psr2.html
>
> * igt@gem_ctx_persistence@engines-hostile-preempt:
> - shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099])
> +3 similar issues
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-snb5/igt@gem_ctx_persiste...@engines-hostile-preempt.html
>
> * igt@gem_eio@unwedge-stress:
> - shard-tglb: [PASS][14] -> [TIMEOUT][15] ([i915#2369] /
> [i915#3063] / [i915#3648])
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-tglb1/igt@gem_...@unwedge-stress.html
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-tglb5/igt@gem_...@unwedge-stress.html
>
> * igt@gem_exec_fair@basic-none-vip@rcs0:
> - shard-kbl: [PASS][16] -> [FAIL][17] ([i915#2842])
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-kbl7/igt@gem_exec_fair@basic-none-...@rcs0.html
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-kbl4/igt@gem_exec_fair@basic-none-...@rcs0.html
>
> * igt@gem_exec_fair@basic-pace@vcs0:
> - shard-iclb: [PASS][18] -> [FAIL][19] ([i915#2842]) +1 similar
> issue
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs0.html
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs0.html
>
> * igt@gem_exec_fair@basic-throttle@rcs0:
> - shard-glk: [PASS][20] -> [FAIL][21] ([i915#2842]) +2 similar
> issues
>[20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html
>
Re: [Intel-gfx] [PATCH 08/15] drm/i915/guc/slpc: Add methods to set min/max frequency
On 7/27/2021 8:24 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Add param set h2g helpers to set the min and max frequencies
s/h2g/H2G
for use by SLPC.
v2: Address review comments (Michal W)
v3: Check for positive error code (Michal W)
Signed-off-by: Sundaresan Sujaritha
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 89 -
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 +
2 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index f5808d2acbca..63656640189c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -109,6 +109,21 @@ static u32 slpc_get_state(struct intel_guc_slpc *slpc)
return data->header.global_state;
}
+static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
+{
+ u32 request[] = {
+ INTEL_GUC_ACTION_SLPC_REQUEST,
+ SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),
+ id,
+ value,
+ };
+ int ret;
+
+ ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
+
+ return ret > 0 ? -EPROTO : ret;
+}
+
static bool slpc_is_running(struct intel_guc_slpc *slpc)
{
return (slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING);
@@ -118,7 +133,7 @@ static int guc_action_slpc_query(struct intel_guc *guc, u32
offset)
{
u32 request[] = {
INTEL_GUC_ACTION_SLPC_REQUEST,
- SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
+ SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
this should be fixed in original patch
offset,
0,
};
@@ -146,6 +161,15 @@ static int slpc_query_task_state(struct intel_guc_slpc
*slpc)
return ret;
}
+static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
+{
+ struct intel_guc *guc = slpc_to_guc(slpc);
+
+ GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+
+ return guc_action_slpc_set_param(guc, id, value);
+}
+
static const char *slpc_global_state_to_string(enum slpc_global_state state)
{
const char *str = NULL;
@@ -251,6 +275,69 @@ static u32 slpc_decode_max_freq(struct intel_guc_slpc
*slpc)
GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
}
+/**
+ * intel_guc_slpc_set_max_freq() - Set max frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to update the max frequency
+ * limit for unslice.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
+{
+ struct drm_i915_private *i915 = slpc_to_i915(slpc);
+ intel_wakeref_t wakeref;
+ int ret;
+
+ with_intel_runtime_pm(>runtime_pm, wakeref) {
+ ret = slpc_set_param(slpc,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ val);
+ if (ret) {
+ drm_err(>drm,
+ "Set max frequency unslice returned (%pe)\n",
ERR_PTR(ret));
maybe generic error reporting could be moved to slpc_set_param() ?
+ /* Return standardized err code for sysfs */
+ ret = -EIO;
at this point we don't know if this function is for sysfs only
I would sanitize error in "store" hook if really needed
ssize_t slpc_max_freq_store(... const char *buf, size_t count)
{
...
err = intel_guc_slpc_set_max_freq(slpc, val);
return err ? -EIO : count;
that's the problem, sysfs wrapper will need to check for -EIO and
-EINVAL, we want the ability to return either.
Thanks,
Vinay.
}
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to update the min unslice
+ * frequency.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
+{
+ int ret;
+ struct intel_guc *guc = slpc_to_guc(slpc);
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+ intel_wakeref_t wakeref;
+
+ with_intel_runtime_pm(>runtime_pm, wakeref) {
+ ret = slpc_set_param(slpc,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ val);
+ if (ret) {
+ drm_err(>drm,
+ "Set min frequency for unslice returned
(%pe)\n", ERR_PTR(ret));
+ /* Return standardized err code for sysfs */
+ ret = -EIO;
+ }
+ }
same here
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,01/28] drm/i915/display: remove PORT_F workaround for CNL (rev2)
== Series Details ==
Series: series starting with [CI,01/28] drm/i915/display: remove PORT_F
workaround for CNL (rev2)
URL : https://patchwork.freedesktop.org/series/93056/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10405_full -> Patchwork_20719_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20719_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20719_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20719_full:
### IGT changes ###
Possible regressions
* igt@kms_selftest@all@damage_iter_no_damage:
- shard-apl: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/shard-apl1/igt@kms_selftest@all@damage_iter_no_damage.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {shard-rkl}:([FAIL][2], [FAIL][3], [FAIL][4], [FAIL][5])
([i915#3002] / [i915#3810] / [i915#3811]) -> ([FAIL][6], [FAIL][7], [FAIL][8],
[FAIL][9]) ([i915#2029] / [i915#3002] / [i915#3810] / [i915#3811])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-rkl-5/igt@run...@aborted.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-rkl-2/igt@run...@aborted.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-rkl-1/igt@run...@aborted.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-rkl-1/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/shard-rkl-1/igt@run...@aborted.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/shard-rkl-1/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/shard-rkl-6/igt@run...@aborted.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/shard-rkl-2/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_20719_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][10] -> [SKIP][11] ([i915#658])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-iclb2/igt@feature_discov...@psr2.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/shard-iclb8/igt@feature_discov...@psr2.html
* igt@gem_ctx_persistence@engines-queued:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1099]) +6
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/shard-snb6/igt@gem_ctx_persiste...@engines-queued.html
* igt@gem_eio@in-flight-suspend:
- shard-kbl: [PASS][13] -> [INCOMPLETE][14] ([i915#155])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-kbl7/igt@gem_...@in-flight-suspend.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/shard-kbl4/igt@gem_...@in-flight-suspend.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][15] -> [TIMEOUT][16] ([i915#2369] /
[i915#3063] / [i915#3648])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-tglb1/igt@gem_...@unwedge-stress.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/shard-tglb1/igt@gem_...@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#2846])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-glk2/igt@gem_exec_f...@basic-deadline.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/shard-glk6/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][19] -> [FAIL][20] ([i915#2842])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][21] -> [FAIL][22] ([i915#2842]) +2 similar
issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-glk: [PASS][23] -> [FAIL][24] ([i915#2842] / [i915#3468])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-glk7/igt@gem_exec_fair@basic-n...@vecs0.html
[24]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adl_p: Allow underrun recovery when possible (rev2)
== Series Details ==
Series: drm/i915/adl_p: Allow underrun recovery when possible (rev2)
URL : https://patchwork.freedesktop.org/series/93054/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10405_full -> Patchwork_20717_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20717_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20717_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20717_full:
### IGT changes ###
Possible regressions
* igt@kms_selftest@all@damage_iter_no_damage:
- shard-apl: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-apl7/igt@kms_selftest@all@damage_iter_no_damage.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@execlists:
- {shard-rkl}:[PASS][2] -> [DMESG-FAIL][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-rkl-5/igt@i915_selftest@l...@execlists.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-rkl-5/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- {shard-rkl}:([FAIL][4], [FAIL][5], [FAIL][6], [FAIL][7])
([i915#3002] / [i915#3810] / [i915#3811]) -> ([FAIL][8], [FAIL][9], [FAIL][10])
([i915#3002] / [i915#3811])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-rkl-5/igt@run...@aborted.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-rkl-2/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-rkl-1/igt@run...@aborted.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-rkl-1/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-rkl-6/igt@run...@aborted.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-rkl-5/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-rkl-5/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_20717_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][11] -> [SKIP][12] ([i915#658])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-iclb2/igt@feature_discov...@psr2.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-iclb4/igt@feature_discov...@psr2.html
* igt@gem_ctx_persistence@engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099]) +3
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-snb5/igt@gem_ctx_persiste...@engines-hostile-preempt.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][14] -> [TIMEOUT][15] ([i915#2369] /
[i915#3063] / [i915#3648])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-tglb1/igt@gem_...@unwedge-stress.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-tglb5/igt@gem_...@unwedge-stress.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl: [PASS][16] -> [FAIL][17] ([i915#2842])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-kbl7/igt@gem_exec_fair@basic-none-...@rcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-kbl4/igt@gem_exec_fair@basic-none-...@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [PASS][18] -> [FAIL][19] ([i915#2842]) +1 similar
issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][20] -> [FAIL][21] ([i915#2842]) +2 similar
issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-glk4/igt@gem_exec_fair@basic-throt...@rcs0.html
- shard-iclb: [PASS][22] -> [FAIL][23] ([i915#2849])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/7] lib/i915/gem_mman: add FIXED mmap mode
On Mon, 26 Jul 2021 05:03:04 -0700, Matthew Auld wrote: > > diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c > index 4b4f2114..e2514f0c 100644 > --- a/lib/i915/gem_mman.c > +++ b/lib/i915/gem_mman.c > @@ -497,6 +497,43 @@ void *gem_mmap_offset__cpu(int fd, uint32_t handle, > uint64_t offset, > return ptr; > } > > +#define LOCAL_I915_MMAP_OFFSET_FIXED 4 Cc: @Petri Latvala This use of LOCAL declarations is more related to the methodology we follow in IGT rather than this patch. We have seen in the past that such LOCAL's linger on in the code for months and years till someone decides to clean them so the question is can we prevent these LOCAL's from getting introduced in the first place. One reason for these is that we sync IGT headers with drm-next whereas IGT is used to test drm-tip. So the delta between the two results in such LOCAL's as in this case. My proposal is that even if we don't start sync'ing IGT headers with drm-tip (instead of drm-next) we allow direct modification of the headers when needed to avoid introducing such LOCAL's. So in the above case we would add: #define I915_MMAP_OFFSET_FIXED 4 to i915_drm.h as part of this patch and then just use I915_MMAP_OFFSET_FIXED. If another sync happens from drm-next before this #define has appeared there, the compile will break and whoever syncs will need to add this again to i915_drm.h. What do people think about a scheme such as this? The other, perhaps better, option of course is to sync the headers directly with drm-tip (whenever and as often as needed). But the goal in both cases is to avoid LOCAL's, or other things like #ifndef's distributed throughout multiple source files which we also do in such cases. A centralized internal header to contain such declarations might not be so bad. Thanks. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 12/15] drm/i915/guc/slpc: Cache platform frequency limits
On 7/27/2021 9:00 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Cache rp0, rp1 and rpn platform limits into SLPC structure
for range checking while setting min/max frequencies.
Also add "soft" limits which keep track of frequency changes
made from userland. These are initially set to platform min
and max.
v2: Address review comments (Michal W)
v3: Formatting (Michal W)
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 97 +++
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 11 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +
3 files changed, 111 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index c79dba60b2e6..a98cbf274862 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -94,6 +94,9 @@ static int slpc_shared_data_init(struct intel_guc_slpc *slpc)
return err;
}
+ slpc->max_freq_softlimit = 0;
+ slpc->min_freq_softlimit = 0;
+
return err;
}
@@ -124,6 +127,18 @@ static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
return ret > 0 ? -EPROTO : ret;
}
+static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)
+{
+ u32 request[] = {
+ INTEL_GUC_ACTION_SLPC_REQUEST,
+ SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 2),
+ id,
+ };
+
+ return intel_guc_send(guc, request, ARRAY_SIZE(request));
+}
+
+
static bool slpc_is_running(struct intel_guc_slpc *slpc)
{
return (slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING);
@@ -170,6 +185,16 @@ static int slpc_set_param(struct intel_guc_slpc *slpc, u8
id, u32 value)
return guc_action_slpc_set_param(guc, id, value);
}
+static int slpc_unset_param(struct intel_guc_slpc *slpc,
+ u8 id)
+{
+ struct intel_guc *guc = slpc_to_guc(slpc);
+
+ GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+
+ return guc_action_slpc_unset_param(guc, id);
+}
+
static const char *slpc_global_state_to_string(enum slpc_global_state state)
{
const char *str = NULL;
@@ -406,6 +431,55 @@ void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
GEN6_PMINTRMSK, pm_intrmsk_mbz, 0);
}
+static int intel_guc_slpc_set_softlimits(struct intel_guc_slpc *slpc)
nit: "intel_" prefix not needed for static function
ok.
+{
+ int ret = 0;
+
+ /* Softlimits are initially equivalent to platform limits
+* unless they have deviated from defaults, in which case,
+* we retain the values and set min/max accordingly.
+*/
fix style for multi-line comment
done.
+ if (!slpc->max_freq_softlimit)
+ slpc->max_freq_softlimit = slpc->rp0_freq;
+ else if (slpc->max_freq_softlimit != slpc->rp0_freq)
+ ret = intel_guc_slpc_set_max_freq(slpc,
+ slpc->max_freq_softlimit);
+
+ if (!slpc->min_freq_softlimit)
+ slpc->min_freq_softlimit = slpc->min_freq;
+ else if (slpc->min_freq_softlimit != slpc->min_freq)
+ ret = intel_guc_slpc_set_min_freq(slpc,
+ slpc->min_freq_softlimit);
+
+ return ret;
+}
+
+static void intel_guc_slpc_ignore_eff_freq(struct intel_guc_slpc *slpc, bool
ignore)
+{
+ if (ignore) {
+ /* A failure here does not affect the algorithm in a fatal way
*/
is this comment just for "ignore" case or whole function ? (as you don't
check for errors in "else" case anyway)
moved it above.
+ slpc_set_param(slpc,
+ SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
+ ignore);
+ slpc_set_param(slpc,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ slpc->min_freq);
+ } else {
+ slpc_unset_param(slpc,
+ SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY);
+ slpc_unset_param(slpc,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ);
+ }
+}
+
+static void intel_guc_slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
+{
+ /* Force slpc to used platform rp0 */
s/slpc/SLPC
ok.
+ slpc_set_param(slpc,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ slpc->rp0_freq);
hmm, likely indent is wrong, did you run checkpatch.pl ?
Fixed.
+}
+
/*
* intel_guc_slpc_enable() - Start SLPC
* @slpc: pointer to intel_guc_slpc.
@@ -423,6 +497,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
{
struct drm_i915_private *i915 = slpc_to_i915(slpc);
struct slpc_shared_data *data;
+ u32 rp_state_cap;
int ret;
GEM_BUG_ON(!slpc->vma);
@@ -460,6 +535,28 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
Re: [Intel-gfx] [PATCH 07/15] drm/i915/guc/slpc: Remove BUG_ON in guc_submission_disable
On Tue, Jul 27, 2021 at 06:01:18PM -0700, Belgaumkar, Vinay wrote:
>
>
> On 7/27/2021 5:20 PM, Matthew Brost wrote:
> > On Mon, Jul 26, 2021 at 12:07:52PM -0700, Vinay Belgaumkar wrote:
> > > The assumption when it was added was there would be no wakerefs
> > > held. However, if we fail to enable SLPC, we will still be
> > > holding a wakeref.
> > >
> >
> > So this is if intel_guc_slpc_enable() fails, right? Not seeing where the
> > wakeref is taken. It also seems wrong not to drop the wakeref before
> > calling intel_guc_submission_disable, hence the GEM_BUG_ON in this
> > function.
> >
> > Can you explain this bit more?
>
> I should change the desc a little. The BUG_ON assumed GT would not be awake
> i.e at shutdown, and there would be 0 GT_PM references. However, this
> slpc_enable is in gt_resume path (gt_init_hw calls uc_init_hw). Here,
> gt_pm_get reference is held, so it will result in BUG_ON when
> submission_disable is called.
>
Ok, I see the code path. With a better commit message:
Reviewed-by: Matthew Brost
> Thanks,
> Vinay.
> >
> > Matt
> >
> > > Signed-off-by: Vinay Belgaumkar
> > > ---
> > > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4
> > > 1 file changed, 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > index b6338742a594..48cbd800ca54 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > @@ -2523,10 +2523,6 @@ void intel_guc_submission_enable(struct intel_guc
> > > *guc)
> > > void intel_guc_submission_disable(struct intel_guc *guc)
> > > {
> > > - struct intel_gt *gt = guc_to_gt(guc);
> > > -
> > > - GEM_BUG_ON(gt->awake); /* GT should be parked first */
> > > -
> > > /* Note: By the time we're here, GuC may have already been
> > > reset */
> > > }
> > > --
> > > 2.25.0
> > >
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/15] drm/i915/guc/slpc: Remove BUG_ON in guc_submission_disable
On 7/27/2021 5:20 PM, Matthew Brost wrote:
On Mon, Jul 26, 2021 at 12:07:52PM -0700, Vinay Belgaumkar wrote:
The assumption when it was added was there would be no wakerefs
held. However, if we fail to enable SLPC, we will still be
holding a wakeref.
So this is if intel_guc_slpc_enable() fails, right? Not seeing where the
wakeref is taken. It also seems wrong not to drop the wakeref before
calling intel_guc_submission_disable, hence the GEM_BUG_ON in this
function.
Can you explain this bit more?
I should change the desc a little. The BUG_ON assumed GT would not be
awake i.e at shutdown, and there would be 0 GT_PM references. However,
this slpc_enable is in gt_resume path (gt_init_hw calls uc_init_hw).
Here, gt_pm_get reference is held, so it will result in BUG_ON when
submission_disable is called.
Thanks,
Vinay.
Matt
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b6338742a594..48cbd800ca54 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2523,10 +2523,6 @@ void intel_guc_submission_enable(struct intel_guc *guc)
void intel_guc_submission_disable(struct intel_guc *guc)
{
- struct intel_gt *gt = guc_to_gt(guc);
-
- GEM_BUG_ON(gt->awake); /* GT should be parked first */
-
/* Note: By the time we're here, GuC may have already been reset */
}
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/15] drm/i915/guc/slpc: Remove BUG_ON in guc_submission_disable
On Mon, Jul 26, 2021 at 12:07:52PM -0700, Vinay Belgaumkar wrote:
> The assumption when it was added was there would be no wakerefs
> held. However, if we fail to enable SLPC, we will still be
> holding a wakeref.
>
So this is if intel_guc_slpc_enable() fails, right? Not seeing where the
wakeref is taken. It also seems wrong not to drop the wakeref before
calling intel_guc_submission_disable, hence the GEM_BUG_ON in this
function.
Can you explain this bit more?
Matt
> Signed-off-by: Vinay Belgaumkar
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index b6338742a594..48cbd800ca54 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -2523,10 +2523,6 @@ void intel_guc_submission_enable(struct intel_guc *guc)
>
> void intel_guc_submission_disable(struct intel_guc *guc)
> {
> - struct intel_gt *gt = guc_to_gt(guc);
> -
> - GEM_BUG_ON(gt->awake); /* GT should be parked first */
> -
> /* Note: By the time we're here, GuC may have already been reset */
> }
>
> --
> 2.25.0
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 11/15] drm/i915/guc/slpc: Enable ARAT timer interrupt
On 7/27/2021 8:40 AM, Matthew Brost wrote:
On Mon, Jul 26, 2021 at 12:07:56PM -0700, Vinay Belgaumkar wrote:
This interrupt is enabled during RPS initialization, and
now needs to be done by SLPC code. It allows ARAT timer
expiry interrupts to get forwarded to GuC.
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 16
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 ++
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8
3 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 995d3d4807a3..c79dba60b2e6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -392,6 +392,20 @@ int intel_guc_slpc_get_min_freq(struct intel_guc_slpc
*slpc, u32 *val)
return ret;
}
+void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
+{
+ u32 pm_intrmsk_mbz = 0;
+
+ /* Allow GuC to receive ARAT timer expiry event.
I've been berated for using comments like this this by other engineers.
I personally don't care at all (nor does checkpatch) but if you want to
avoid the wrath of others I'd change this to what I have below:
/*
* Allow GuC to receive ARAT timer expiry event.
* This interrupt register is setup by RPS code
* when host based Turbo is enabled.
*/
Same goes for comment below of same style.
Either way, patch looks good to me. With that:
Reviewed-by: Matthew Brost
Fixed.
Thanks,
Vinay.
+* This interrupt register is setup by RPS code
+* when host based Turbo is enabled.
+*/
+ pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
+
+ intel_uncore_rmw(gt->uncore,
+ GEN6_PMINTRMSK, pm_intrmsk_mbz, 0);
+}
+
/*
* intel_guc_slpc_enable() - Start SLPC
* @slpc: pointer to intel_guc_slpc.
@@ -439,6 +453,8 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
slpc_query_task_state(slpc);
+ intel_guc_pm_intrmsk_enable(>gt);
+
/* min and max frequency limits being used by SLPC */
drm_info(>drm, "SLPC min freq: %u Mhz, max is %u Mhz\n",
slpc_decode_min_freq(slpc),
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index d133c8020c16..f128143cc1d8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -9,6 +9,7 @@
#include "intel_guc_submission.h"
#include "intel_guc_slpc_types.h"
+struct intel_gt;
struct drm_printer;
static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc)
@@ -35,5 +36,6 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc,
u32 val);
int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val);
int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val);
int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p);
+void intel_guc_pm_intrmsk_enable(struct intel_gt *gt);
#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index b98c14f8c229..9238bc076605 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -652,6 +652,7 @@ void intel_uc_suspend(struct intel_uc *uc)
static int __uc_resume(struct intel_uc *uc, bool enable_communication)
{
struct intel_guc *guc = >guc;
+ struct intel_gt *gt = guc_to_gt(guc);
int err;
if (!intel_guc_is_fw_running(guc))
@@ -663,6 +664,13 @@ static int __uc_resume(struct intel_uc *uc, bool
enable_communication)
if (enable_communication)
guc_enable_communication(guc);
+ /* If we are only resuming GuC communication but not reloading
+* GuC, we need to ensure the ARAT timer interrupt is enabled
+* again. In case of GuC reload, it is enabled during SLPC enable.
+*/
+ if (enable_communication && intel_uc_uses_guc_slpc(uc))
+ intel_guc_pm_intrmsk_enable(gt);
+
err = intel_guc_resume(guc);
if (err) {
DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/15] drm/i915/guc/slpc: Add debugfs for SLPC info
On 7/27/2021 8:37 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
This prints out relevant SLPC info from the SLPC shared structure.
We will send a h2g message which forces SLPC to update the
s/h2g/H2G
ok.
shared data structure with latest information before reading it.
v2: Address review comments (Michal W)
v3: Remove unnecessary tasks from slpc_info (Michal W)
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
.../gpu/drm/i915/gt/uc/intel_guc_debugfs.c| 22 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 29 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 4 ++-
3 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
index 72ddfff42f7d..3244e54b1337 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
@@ -12,6 +12,7 @@
#include "gt/uc/intel_guc_ct.h"
#include "gt/uc/intel_guc_ads.h"
#include "gt/uc/intel_guc_submission.h"
+#include "gt/uc/intel_guc_slpc.h"
static int guc_info_show(struct seq_file *m, void *data)
{
@@ -50,11 +51,32 @@ static int guc_registered_contexts_show(struct seq_file *m,
void *data)
}
DEFINE_GT_DEBUGFS_ATTRIBUTE(guc_registered_contexts);
+static int guc_slpc_info_show(struct seq_file *m, void *unused)
+{
+ struct intel_guc *guc = m->private;
+ struct intel_guc_slpc *slpc = >slpc;
+ struct drm_printer p = drm_seq_file_printer(m);
+
+ if (!intel_guc_slpc_is_used(guc))
+ return -ENODEV;
+
+ return intel_guc_slpc_info(slpc, );
+}
+DEFINE_GT_DEBUGFS_ATTRIBUTE(guc_slpc_info);
+
+static bool intel_eval_slpc_support(void *data)
+{
+ struct intel_guc *guc = (struct intel_guc *)data;
+
+ return intel_guc_slpc_is_used(guc);
+}
+
void intel_guc_debugfs_register(struct intel_guc *guc, struct dentry *root)
{
static const struct debugfs_gt_file files[] = {
{ "guc_info", _info_fops, NULL },
{ "guc_registered_contexts", _registered_contexts_fops,
NULL },
+ { "guc_slpc_info", _slpc_info_fops,
_eval_slpc_support},
};
if (!intel_guc_is_supported(guc))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index c653bba3b5eb..995d3d4807a3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -448,6 +448,35 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
return 0;
}
+int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p)
nit: intel_guc_slpc_print_info ?
ok.
+{
+ struct drm_i915_private *i915 = guc_to_gt(slpc_to_guc(slpc))->i915;
use slpc_to_i915()
ok.
+ struct slpc_shared_data *data = slpc->vaddr;
+ struct slpc_task_state_data *slpc_tasks;
+ intel_wakeref_t wakeref;
+ int ret = 0;
+
+ GEM_BUG_ON(!slpc->vma);
+
+ with_intel_runtime_pm(>runtime_pm, wakeref) {
+ ret = slpc_query_task_state(slpc);
+
+ if (!ret) {
+ slpc_tasks = >task_state_data;
+
+ drm_printf(p, "\tSLPC state: %s\n",
slpc_get_state_string(slpc));
+ drm_printf(p, "\tGTPERF task active: %s\n",
+ yesno(slpc_tasks->status &
SLPC_GTPERF_TASK_ENABLED));
+ drm_printf(p, "\tMax freq: %u MHz\n",
+ slpc_decode_max_freq(slpc));
+ drm_printf(p, "\tMin freq: %u MHz\n",
+ slpc_decode_min_freq(slpc));
+ }
+ }
+
+ return ret;
+}
+
void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
{
if (!slpc->vma)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index 92d7afd44f07..d133c8020c16 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -9,6 +9,8 @@
#include "intel_guc_submission.h"
#include "intel_guc_slpc_types.h"
+struct drm_printer;
+
static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc)
{
return guc->slpc_supported;
@@ -25,7 +27,6 @@ static inline bool intel_guc_slpc_is_used(struct intel_guc
*guc)
}
void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc);
-
this should be fixed in earlier patch
with all that fixed,
Done.
Thanks,
Vinay.
Reviewed-by: Michal Wajdeczko
int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
@@ -33,5 +34,6 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc,
u32 val);
int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc,
Re: [Intel-gfx] [PATCH 09/15] drm/i915/guc/slpc: Add get max/min freq hooks
On 7/27/2021 8:32 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Add helpers to read the min/max frequency being used
by SLPC. This is done by send a H2G command which forces
SLPC to update the shared data struct which can then be
read. These helpers will be used in a sysfs patch later
on.
v2: Address review comments (Michal W)
v3: Return err in case of query failure (Michal W)
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 54 +
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 +
2 files changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 63656640189c..c653bba3b5eb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -306,6 +306,33 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc
*slpc, u32 val)
return ret;
}
+/**
+ * intel_guc_slpc_get_max_freq() - Get max frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: pointer to val which will hold max frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to read the max frequency
+ * limit for unslice.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val)
+{
+ struct drm_i915_private *i915 = slpc_to_i915(slpc);
+ intel_wakeref_t wakeref;
+ int ret = 0;
+
+ with_intel_runtime_pm(>runtime_pm, wakeref) {
+ /* Force GuC to update task data */
+ ret = slpc_query_task_state(slpc);
+
+ if (!ret)
+ *val = slpc_decode_max_freq(slpc);
+ }
+
+ return ret;
+}
+
/**
* intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
* @slpc: pointer to intel_guc_slpc.
@@ -338,6 +365,33 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc
*slpc, u32 val)
return ret;
}
+/**
+ * intel_guc_slpc_get_min_freq() - Get min frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: pointer to val which will hold min frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to read the min frequency
+ * limit for unslice.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val)
+{
+ intel_wakeref_t wakeref;
+ struct drm_i915_private *i915 = guc_to_gt(slpc_to_guc(slpc))->i915;
use slpc_to_i915() and in this order:
struct drm_i915_private *i915 = slpc_to_i915(slpc);
intel_wakeref_t wakeref;
int ret = 0;
with that fixed,
Reviewed-by: Michal Wajdeczko
done.
Thanks,
vinay.
+ int ret = 0;
+
+ with_intel_runtime_pm(>runtime_pm, wakeref) {
+ /* Force GuC to update task data */
+ ret = slpc_query_task_state(slpc);
+
+ if (!ret)
+ *val = slpc_decode_min_freq(slpc);
+ }
+
+ return ret;
+}
+
/*
* intel_guc_slpc_enable() - Start SLPC
* @slpc: pointer to intel_guc_slpc.
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index e594510497ec..92d7afd44f07 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -31,5 +31,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val);
int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val);
+int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val);
+int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val);
#endif
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/10] drm/i915/bios: Enable parse of two integrated panels PSR data
On Wed, Jul 21, 2021 at 10:43:34PM -0700, José Roberto de Souza wrote:
> Continuing the conversion from single integrated VBT data to two, now
> handling PSR data.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 73 +--
> drivers/gpu/drm/i915/display/intel_bios.h | 2 +
> drivers/gpu/drm/i915/display/intel_psr.c | 30 ++
> drivers/gpu/drm/i915/i915_drv.h | 34 +--
> 4 files changed, 77 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index f0d49af8be036..de690e96de723 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -729,15 +729,12 @@ parse_driver_features(struct drm_i915_private *i915,
> driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS)
> i915->vbt.int_lvds_support = 0;
> }
> -
> - if (bdb->version < 228)
> - i915->vbt.psr.enable = driver->psr_enabled;
> }
>
> static void
> -parse_driver_features_drrs_only(struct drm_i915_private *i915,
> - const struct bdb_header *bdb,
> - struct ddi_vbt_port_info *info)
> +parse_driver_features_drrs_psr_only(struct drm_i915_private *i915,
> + const struct bdb_header *bdb,
> + struct ddi_vbt_port_info *info)
> {
> const struct bdb_driver_features *driver;
>
> @@ -757,6 +754,8 @@ parse_driver_features_drrs_only(struct drm_i915_private
> *i915,
>*/
> if (!driver->drrs_enabled)
> info->drrs_type = DRRS_NOT_SUPPORTED;
> +
> + info->psr.enable = driver->psr_enabled;
> }
>
> static void
> @@ -774,7 +773,7 @@ parse_power_conservation_features(struct drm_i915_private
> *i915,
> if (!power)
> return;
>
> - i915->vbt.psr.enable = power->psr & BIT(panel_index);
> + info->psr.enable = power->psr & BIT(panel_index);
>
> /*
>* If DRRS is not supported, drrs_type has to be set to 0.
> @@ -905,11 +904,11 @@ parse_edp(struct drm_i915_private *i915, const struct
> bdb_header *bdb,
> }
>
> static void
> -parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb)
> +parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb,
> + struct ddi_vbt_port_info *info, int panel_index)
> {
> const struct bdb_psr *psr;
> const struct psr_table *psr_table;
> - int panel_type = i915->vbt.panel_type;
>
> psr = find_section(bdb, BDB_PSR);
> if (!psr) {
> @@ -917,27 +916,27 @@ parse_psr(struct drm_i915_private *i915, const struct
> bdb_header *bdb)
> return;
> }
>
> - psr_table = >psr_table[panel_type];
> + psr_table = >psr_table[panel_index];
>
> - i915->vbt.psr.full_link = psr_table->full_link;
> - i915->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
> + info->psr.full_link = psr_table->full_link;
> + info->psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
>
> /* Allowed VBT values goes from 0 to 15 */
> - i915->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
> + info->psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
> psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
>
> switch (psr_table->lines_to_wait) {
> case 0:
> - i915->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
> + info->psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
> break;
> case 1:
> - i915->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
> + info->psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
> break;
> case 2:
> - i915->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
> + info->psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
> break;
> case 3:
> - i915->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
> + info->psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
> break;
> default:
> drm_dbg_kms(>drm,
> @@ -954,13 +953,13 @@ parse_psr(struct drm_i915_private *i915, const struct
> bdb_header *bdb)
> (DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) {
> switch (psr_table->tp1_wakeup_time) {
> case 0:
> - i915->vbt.psr.tp1_wakeup_time_us = 500;
> + info->psr.tp1_wakeup_time_us = 500;
> break;
> case 1:
> - i915->vbt.psr.tp1_wakeup_time_us = 100;
> + info->psr.tp1_wakeup_time_us = 100;
> break;
> case 3:
> - i915->vbt.psr.tp1_wakeup_time_us = 0;
> + info->psr.tp1_wakeup_time_us = 0;
>
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adlp: Add workaround to disable CMTG clock gating
== Series Details ==
Series: drm/i915/adlp: Add workaround to disable CMTG clock gating
URL : https://patchwork.freedesktop.org/series/93067/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10404_full -> Patchwork_20716_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20716_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20716_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20716_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_schedule@independent@vcs1:
- shard-tglb: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-tglb1/igt@gem_exec_schedule@independ...@vcs1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-tglb6/igt@gem_exec_schedule@independ...@vcs1.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- {shard-rkl}:[SKIP][3] ([i915#1845]) -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-1/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-6/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html
* igt@runner@aborted:
- {shard-rkl}:([FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8])
([i915#2029] / [i915#3002] / [i915#3810] / [i915#3811]) -> ([FAIL][9],
[FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13]) ([i915#2029] / [i915#3002] /
[i915#3621] / [i915#3810] / [i915#3811])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-6/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-1/igt@run...@aborted.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-5/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-2/igt@run...@aborted.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-1/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-6/igt@run...@aborted.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-2/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-6/igt@run...@aborted.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-6/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_20716_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1099]) +6
similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-snb7/igt@gem_ctx_persiste...@engines-hostile-preempt.html
* igt@gem_eio@in-flight-suspend:
- shard-kbl: [PASS][15] -> [INCOMPLETE][16] ([i915#155])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-kbl7/igt@gem_...@in-flight-suspend.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-kbl3/igt@gem_...@in-flight-suspend.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#2846])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-glk1/igt@gem_exec_f...@basic-deadline.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-glk9/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl: [PASS][19] -> [FAIL][20] ([i915#2842])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-kbl4/igt@gem_exec_fair@basic-none-...@rcs0.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-kbl6/igt@gem_exec_fair@basic-none-...@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][21] -> [FAIL][22] ([i915#2842])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][23] -> [FAIL][24] ([i915#2842]) +1 similar
issue
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-tglb7/igt@gem_exec_fair@basic-p...@bcs0.html
[24]:
Re: [Intel-gfx] [PATCH 03/15] drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled
On Tue, Jul 27, 2021 at 03:48:23PM -0700, Belgaumkar, Vinay wrote:
>
>
> On 7/27/2021 3:44 PM, Matthew Brost wrote:
> > On Mon, Jul 26, 2021 at 12:07:48PM -0700, Vinay Belgaumkar wrote:
> > > Also ensure uc_init is called before we initialize RPS so that we
> > > can check for SLPC support. We do not need to enable up/down
> > > interrupts when SLPC is enabled. However, we still need the ARAT
> > > interrupt, which will be enabled separately later.
> > >
> >
> > Do we not need a check for rps_uses_slpc in intel_rps_enable? I guessing
> > there is a reason why we don't but can't seem to figure that out.
>
> Yeah, it's due to this check in there -
> if (rps->max_freq <= rps->min_freq)
> /* leave disabled, no room for dynamic reclocking */;
>
> With slpc, rps->max_freq and rps->min freq remain uninitialized, so the if
> condition just falls through and returns with this-
> if (!enabled)
I'd add a comment explaining that or add an explict check.
With that:
Reviewed-by: Matthew Brost
> return;
>
> Thanks,
> Vinay.
>
> >
> > Matt
> >
> > > Signed-off-by: Vinay Belgaumkar
> > > Signed-off-by: Sundaresan Sujaritha
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
> > > drivers/gpu/drm/i915/gt/intel_rps.c | 20
> > > 2 files changed, 21 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > index a64aa43f7cd9..04dd69bcf6cb 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > @@ -41,8 +41,8 @@ void intel_gt_init_early(struct intel_gt *gt, struct
> > > drm_i915_private *i915)
> > > intel_gt_init_timelines(gt);
> > > intel_gt_pm_init_early(gt);
> > > - intel_rps_init_early(>rps);
> > > intel_uc_init_early(>uc);
> > > + intel_rps_init_early(>rps);
> > > }
> > > int intel_gt_probe_lmem(struct intel_gt *gt)
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> > > b/drivers/gpu/drm/i915/gt/intel_rps.c
> > > index 0c8e7f2b06f0..e858eeb2c59d 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> > > @@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct
> > > intel_rps *rps)
> > > return rps_to_gt(rps)->uncore;
> > > }
> > > +static bool rps_uses_slpc(struct intel_rps *rps)
> > > +{
> > > + struct intel_gt *gt = rps_to_gt(rps);
> > > +
> > > + return intel_uc_uses_guc_slpc(>uc);
> > > +}
> > > +
> > > static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask)
> > > {
> > > return mask & ~rps->pm_intrmsk_mbz;
> > > @@ -167,6 +174,8 @@ static void rps_enable_interrupts(struct intel_rps
> > > *rps)
> > > {
> > > struct intel_gt *gt = rps_to_gt(rps);
> > > + GEM_BUG_ON(rps_uses_slpc(rps));
> > > +
> > > GT_TRACE(gt, "interrupts:on rps->pm_events: %x,
> > > rps_pm_mask:%x\n",
> > >rps->pm_events, rps_pm_mask(rps, rps->last_freq));
> > > @@ -771,6 +780,8 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val)
> > > struct drm_i915_private *i915 = rps_to_i915(rps);
> > > u32 swreq;
> > > + GEM_BUG_ON(rps_uses_slpc(rps));
> > > +
> > > if (GRAPHICS_VER(i915) >= 9)
> > > swreq = GEN9_FREQUENCY(val);
> > > else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> > > @@ -861,6 +872,9 @@ void intel_rps_park(struct intel_rps *rps)
> > > {
> > > int adj;
> > > + if (!intel_rps_is_enabled(rps))
> > > + return;
> > > +
> > > GEM_BUG_ON(atomic_read(>num_waiters));
> > > if (!intel_rps_clear_active(rps))
> > > @@ -1829,6 +1843,9 @@ void intel_rps_init(struct intel_rps *rps)
> > > {
> > > struct drm_i915_private *i915 = rps_to_i915(rps);
> > > + if (rps_uses_slpc(rps))
> > > + return;
> > > +
> > > if (IS_CHERRYVIEW(i915))
> > > chv_rps_init(rps);
> > > else if (IS_VALLEYVIEW(i915))
> > > @@ -1885,6 +1902,9 @@ void intel_rps_init(struct intel_rps *rps)
> > > void intel_rps_sanitize(struct intel_rps *rps)
> > > {
> > > + if (rps_uses_slpc(rps))
> > > + return;
> > > +
> > > if (GRAPHICS_VER(rps_to_i915(rps)) >= 6)
> > > rps_disable_interrupts(rps);
> > > }
> > > --
> > > 2.25.0
> > >
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/15] drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled
On 7/27/2021 3:44 PM, Matthew Brost wrote:
On Mon, Jul 26, 2021 at 12:07:48PM -0700, Vinay Belgaumkar wrote:
Also ensure uc_init is called before we initialize RPS so that we
can check for SLPC support. We do not need to enable up/down
interrupts when SLPC is enabled. However, we still need the ARAT
interrupt, which will be enabled separately later.
Do we not need a check for rps_uses_slpc in intel_rps_enable? I guessing
there is a reason why we don't but can't seem to figure that out.
Yeah, it's due to this check in there -
if (rps->max_freq <= rps->min_freq)
/* leave disabled, no room for dynamic reclocking */;
With slpc, rps->max_freq and rps->min freq remain uninitialized, so the
if condition just falls through and returns with this-
if (!enabled)
return;
Thanks,
Vinay.
Matt
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 20
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index a64aa43f7cd9..04dd69bcf6cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -41,8 +41,8 @@ void intel_gt_init_early(struct intel_gt *gt, struct
drm_i915_private *i915)
intel_gt_init_timelines(gt);
intel_gt_pm_init_early(gt);
- intel_rps_init_early(>rps);
intel_uc_init_early(>uc);
+ intel_rps_init_early(>rps);
}
int intel_gt_probe_lmem(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 0c8e7f2b06f0..e858eeb2c59d 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps
*rps)
return rps_to_gt(rps)->uncore;
}
+static bool rps_uses_slpc(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+
+ return intel_uc_uses_guc_slpc(>uc);
+}
+
static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask)
{
return mask & ~rps->pm_intrmsk_mbz;
@@ -167,6 +174,8 @@ static void rps_enable_interrupts(struct intel_rps *rps)
{
struct intel_gt *gt = rps_to_gt(rps);
+ GEM_BUG_ON(rps_uses_slpc(rps));
+
GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n",
rps->pm_events, rps_pm_mask(rps, rps->last_freq));
@@ -771,6 +780,8 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val)
struct drm_i915_private *i915 = rps_to_i915(rps);
u32 swreq;
+ GEM_BUG_ON(rps_uses_slpc(rps));
+
if (GRAPHICS_VER(i915) >= 9)
swreq = GEN9_FREQUENCY(val);
else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
@@ -861,6 +872,9 @@ void intel_rps_park(struct intel_rps *rps)
{
int adj;
+ if (!intel_rps_is_enabled(rps))
+ return;
+
GEM_BUG_ON(atomic_read(>num_waiters));
if (!intel_rps_clear_active(rps))
@@ -1829,6 +1843,9 @@ void intel_rps_init(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
+ if (rps_uses_slpc(rps))
+ return;
+
if (IS_CHERRYVIEW(i915))
chv_rps_init(rps);
else if (IS_VALLEYVIEW(i915))
@@ -1885,6 +1902,9 @@ void intel_rps_init(struct intel_rps *rps)
void intel_rps_sanitize(struct intel_rps *rps)
{
+ if (rps_uses_slpc(rps))
+ return;
+
if (GRAPHICS_VER(rps_to_i915(rps)) >= 6)
rps_disable_interrupts(rps);
}
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/15] drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled
On Mon, Jul 26, 2021 at 12:07:48PM -0700, Vinay Belgaumkar wrote:
> Also ensure uc_init is called before we initialize RPS so that we
> can check for SLPC support. We do not need to enable up/down
> interrupts when SLPC is enabled. However, we still need the ARAT
> interrupt, which will be enabled separately later.
>
Do we not need a check for rps_uses_slpc in intel_rps_enable? I guessing
there is a reason why we don't but can't seem to figure that out.
Matt
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_rps.c | 20
> 2 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index a64aa43f7cd9..04dd69bcf6cb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -41,8 +41,8 @@ void intel_gt_init_early(struct intel_gt *gt, struct
> drm_i915_private *i915)
> intel_gt_init_timelines(gt);
> intel_gt_pm_init_early(gt);
>
> - intel_rps_init_early(>rps);
> intel_uc_init_early(>uc);
> + intel_rps_init_early(>rps);
> }
>
> int intel_gt_probe_lmem(struct intel_gt *gt)
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 0c8e7f2b06f0..e858eeb2c59d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps
> *rps)
> return rps_to_gt(rps)->uncore;
> }
>
> +static bool rps_uses_slpc(struct intel_rps *rps)
> +{
> + struct intel_gt *gt = rps_to_gt(rps);
> +
> + return intel_uc_uses_guc_slpc(>uc);
> +}
> +
> static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask)
> {
> return mask & ~rps->pm_intrmsk_mbz;
> @@ -167,6 +174,8 @@ static void rps_enable_interrupts(struct intel_rps *rps)
> {
> struct intel_gt *gt = rps_to_gt(rps);
>
> + GEM_BUG_ON(rps_uses_slpc(rps));
> +
> GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n",
>rps->pm_events, rps_pm_mask(rps, rps->last_freq));
>
> @@ -771,6 +780,8 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val)
> struct drm_i915_private *i915 = rps_to_i915(rps);
> u32 swreq;
>
> + GEM_BUG_ON(rps_uses_slpc(rps));
> +
> if (GRAPHICS_VER(i915) >= 9)
> swreq = GEN9_FREQUENCY(val);
> else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> @@ -861,6 +872,9 @@ void intel_rps_park(struct intel_rps *rps)
> {
> int adj;
>
> + if (!intel_rps_is_enabled(rps))
> + return;
> +
> GEM_BUG_ON(atomic_read(>num_waiters));
>
> if (!intel_rps_clear_active(rps))
> @@ -1829,6 +1843,9 @@ void intel_rps_init(struct intel_rps *rps)
> {
> struct drm_i915_private *i915 = rps_to_i915(rps);
>
> + if (rps_uses_slpc(rps))
> + return;
> +
> if (IS_CHERRYVIEW(i915))
> chv_rps_init(rps);
> else if (IS_VALLEYVIEW(i915))
> @@ -1885,6 +1902,9 @@ void intel_rps_init(struct intel_rps *rps)
>
> void intel_rps_sanitize(struct intel_rps *rps)
> {
> + if (rps_uses_slpc(rps))
> + return;
> +
> if (GRAPHICS_VER(rps_to_i915(rps)) >= 6)
> rps_disable_interrupts(rps);
> }
> --
> 2.25.0
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/15] drm/i915/guc/slpc: Add methods to set min/max frequency
On 7/27/2021 8:24 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Add param set h2g helpers to set the min and max frequencies
s/h2g/H2G
for use by SLPC.
v2: Address review comments (Michal W)
v3: Check for positive error code (Michal W)
Signed-off-by: Sundaresan Sujaritha
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 89 -
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 +
2 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index f5808d2acbca..63656640189c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -109,6 +109,21 @@ static u32 slpc_get_state(struct intel_guc_slpc *slpc)
return data->header.global_state;
}
+static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
+{
+ u32 request[] = {
+ INTEL_GUC_ACTION_SLPC_REQUEST,
+ SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),
+ id,
+ value,
+ };
+ int ret;
+
+ ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
+
+ return ret > 0 ? -EPROTO : ret;
+}
+
static bool slpc_is_running(struct intel_guc_slpc *slpc)
{
return (slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING);
@@ -118,7 +133,7 @@ static int guc_action_slpc_query(struct intel_guc *guc, u32
offset)
{
u32 request[] = {
INTEL_GUC_ACTION_SLPC_REQUEST,
- SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
+ SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
this should be fixed in original patch
ok.
offset,
0,
};
@@ -146,6 +161,15 @@ static int slpc_query_task_state(struct intel_guc_slpc
*slpc)
return ret;
}
+static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
+{
+ struct intel_guc *guc = slpc_to_guc(slpc);
+
+ GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+
+ return guc_action_slpc_set_param(guc, id, value);
+}
+
static const char *slpc_global_state_to_string(enum slpc_global_state state)
{
const char *str = NULL;
@@ -251,6 +275,69 @@ static u32 slpc_decode_max_freq(struct intel_guc_slpc
*slpc)
GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
}
+/**
+ * intel_guc_slpc_set_max_freq() - Set max frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to update the max frequency
+ * limit for unslice.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
+{
+ struct drm_i915_private *i915 = slpc_to_i915(slpc);
+ intel_wakeref_t wakeref;
+ int ret;
+
+ with_intel_runtime_pm(>runtime_pm, wakeref) {
+ ret = slpc_set_param(slpc,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ val);
+ if (ret) {
+ drm_err(>drm,
+ "Set max frequency unslice returned (%pe)\n",
ERR_PTR(ret));
maybe generic error reporting could be moved to slpc_set_param() ?
+ /* Return standardized err code for sysfs */
+ ret = -EIO;
at this point we don't know if this function is for sysfs only
I would sanitize error in "store" hook if really needed
ok.
ssize_t slpc_max_freq_store(... const char *buf, size_t count)
{
...
err = intel_guc_slpc_set_max_freq(slpc, val);
return err ? -EIO : count;
}
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to update the min unslice
+ * frequency.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
+{
+ int ret;
+ struct intel_guc *guc = slpc_to_guc(slpc);
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+ intel_wakeref_t wakeref;
+
+ with_intel_runtime_pm(>runtime_pm, wakeref) {
+ ret = slpc_set_param(slpc,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ val);
+ if (ret) {
+ drm_err(>drm,
+ "Set min frequency for unslice returned
(%pe)\n", ERR_PTR(ret));
+ /* Return standardized err code for sysfs */
+ ret = -EIO;
+ }
+ }
same here
Fixed.
Thanks,
Vinay.
Michal
+
+ return ret;
+}
+
/*
* intel_guc_slpc_enable() - Start SLPC
* @slpc:
Re: [Intel-gfx] [PATCH 14/15] drm/i915/guc/slpc: Add SLPC selftest
On 7/27/2021 12:16 PM, Matthew Brost wrote:
On Mon, Jul 26, 2021 at 12:07:59PM -0700, Vinay Belgaumkar wrote:
Tests that exercise the SLPC get/set frequency interfaces.
Clamp_max will set max frequency to multiple levels and check
that SLPC requests frequency lower than or equal to it.
Clamp_min will set min frequency to different levels and check
if SLPC requests are higher or equal to those levels.
v2: Address review comments (Michal W)
v3: Checkpatch() corrections
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/intel_rps.c | 1 +
drivers/gpu/drm/i915/gt/selftest_slpc.c | 311 ++
drivers/gpu/drm/i915/gt/selftest_slpc.h | 12 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
4 files changed, 325 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_slpc.c
create mode 100644 drivers/gpu/drm/i915/gt/selftest_slpc.h
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 48d4147165a9..6237332835fe 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2318,4 +2318,5 @@ EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_rps.c"
+#include "selftest_slpc.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c
b/drivers/gpu/drm/i915/gt/selftest_slpc.c
new file mode 100644
index ..5018f686686f
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "selftest_slpc.h"
+
+#define NUM_STEPS 5
+#define H2G_DELAY 5
+#define delay_for_h2g() usleep_range(H2G_DELAY, H2G_DELAY + 1)
+
+static int set_min_freq(struct intel_guc_slpc *slpc, u32 freq)
+{
+ int ret;
+
+ ret = intel_guc_slpc_set_min_freq(slpc, freq);
+ if (ret)
+ pr_err("Could not set min frequency to [%u]\n", freq);
+ else /* Delay to ensure h2g completes */
+ delay_for_h2g();
+
+ return ret;
+}
+
+static int set_max_freq(struct intel_guc_slpc *slpc, u32 freq)
+{
+ int ret;
+
+ ret = intel_guc_slpc_set_max_freq(slpc, freq);
+ if (ret)
+ pr_err("Could not set maximum frequency [%u]\n",
+ freq);
+ else /* Delay to ensure h2g completes */
+ delay_for_h2g();
+
+ return ret;
+}
+
+int live_slpc_clamp_min(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct intel_gt *gt = >gt;
+ struct intel_guc_slpc *slpc = >uc.guc.slpc;
+ struct intel_rps *rps = >rps;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ struct igt_spinner spin;
+ u32 slpc_min_freq, slpc_max_freq;
+ int err = 0;
+
+ if (!intel_uc_uses_guc_slpc(>uc))
+ return 0;
+
+ if (igt_spinner_init(, gt))
+ return -ENOMEM;
+
+ if (intel_guc_slpc_get_max_freq(slpc, _max_freq)) {
+ pr_err("Could not get SLPC max freq\n");
+ return -EIO;
+ }
+
+ if (intel_guc_slpc_get_min_freq(slpc, _min_freq)) {
+ pr_err("Could not get SLPC min freq\n");
+ return -EIO;
+ }
+
+ if (slpc_min_freq == slpc_max_freq) {
+ pr_err("Min/Max are fused to the same value\n");
+ return -EINVAL;
+ }
+
+ intel_gt_pm_wait_for_idle(gt);
+ intel_gt_pm_get(gt);
+ for_each_engine(engine, gt, id) {
+ struct i915_request *rq;
+ u32 step, min_freq, req_freq;
+ u32 act_freq, max_act_freq;
+
+ if (!intel_engine_can_store_dword(engine))
+ continue;
+
+ /* Go from min to max in 5 steps */
+ step = (slpc_max_freq - slpc_min_freq) / NUM_STEPS;
+ max_act_freq = slpc_min_freq;
+ for (min_freq = slpc_min_freq; min_freq < slpc_max_freq;
+ min_freq += step) {
+ err = set_min_freq(slpc, min_freq);
+ if (err)
+ break;
+
+ st_engine_heartbeat_disable(engine);
+
+ rq = igt_spinner_create_request(,
+ engine->kernel_context,
+ MI_NOOP);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ st_engine_heartbeat_enable(engine);
+ break;
+ }
+
+ i915_request_add(rq);
+
+ if (!igt_wait_for_spinner(, rq)) {
+ pr_err("%s: Spinner did not start\n",
+ engine->name);
+ igt_spinner_end();
+
Re: [Intel-gfx] [PATCH 1/1] drm/i915/dmc: Bump ADLP DMC version to v2.11
On Tue, 2021-07-27 at 11:55 -0700, Anusha Srivatsa wrote: > Release notes mention that this verion has: > - Fixes for DC6v issue. > - Flip queue enabled on pipe C and pipe D. Reviewed-by: José Roberto de Souza > > Cc: Imre Deak > Signed-off-by: Anusha Srivatsa > --- > drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c > b/drivers/gpu/drm/i915/display/intel_dmc.c > index 9895fd957df9..601c30b92739 100644 > --- a/drivers/gpu/drm/i915/display/intel_dmc.c > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c > @@ -45,8 +45,8 @@ > > #define GEN12_DMC_MAX_FW_SIZEICL_DMC_MAX_FW_SIZE > > -#define ADLP_DMC_PATHDMC_PATH(adlp, 2, 10) > -#define ADLP_DMC_VERSION_REQUIREDDMC_VERSION(2, 10) > +#define ADLP_DMC_PATHDMC_PATH(adlp, 2, 11) > +#define ADLP_DMC_VERSION_REQUIREDDMC_VERSION(2, 11) > MODULE_FIRMWARE(ADLP_DMC_PATH); > > #define ADLS_DMC_PATHDMC_PATH(adls, 2, 01) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,01/11] drm/i915: Check for nomodeset in i915_init() first
== Series Details ==
Series: series starting with [v2,01/11] drm/i915: Check for nomodeset in
i915_init() first
URL : https://patchwork.freedesktop.org/series/93066/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10404_full -> Patchwork_20715_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20715_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20715_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20715_full:
### IGT changes ###
Possible regressions
* igt@sysfs_heartbeat_interval@precise@rcs0:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-tglb1/igt@sysfs_heartbeat_interval@prec...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/shard-tglb6/igt@sysfs_heartbeat_interval@prec...@rcs0.html
Warnings
* igt@i915_pm_rpm@pm-tiling:
- shard-iclb: [SKIP][3] ([i915#579]) -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-iclb5/igt@i915_pm_...@pm-tiling.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/shard-iclb7/igt@i915_pm_...@pm-tiling.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- {shard-rkl}:[SKIP][5] ([i915#1845]) -> [DMESG-WARN][6] +1 similar
issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-5/igt@kms_vbl...@pipe-a-ts-continuation-dpms-suspend.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/shard-rkl-6/igt@kms_vbl...@pipe-a-ts-continuation-dpms-suspend.html
* igt@runner@aborted:
- {shard-rkl}:([FAIL][7], [FAIL][8], [FAIL][9], [FAIL][10])
([i915#2029] / [i915#3002] / [i915#3810] / [i915#3811]) -> ([FAIL][11],
[FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15]) ([i915#2029] / [i915#3002] /
[i915#3621] / [i915#3810] / [i915#3811])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-6/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-1/igt@run...@aborted.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-5/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-2/igt@run...@aborted.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/shard-rkl-1/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/shard-rkl-5/igt@run...@aborted.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/shard-rkl-5/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/shard-rkl-6/igt@run...@aborted.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/shard-rkl-2/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_20715_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1099]) +2
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/shard-snb6/igt@gem_ctx_persiste...@engines-hostile-preempt.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: [PASS][17] -> [TIMEOUT][18] ([i915#3063])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-tglb1/igt@gem_...@in-flight-contexts-immediate.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/shard-tglb7/igt@gem_...@in-flight-contexts-immediate.html
* igt@gem_eio@in-flight-suspend:
- shard-kbl: [PASS][19] -> [INCOMPLETE][20] ([i915#155])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-kbl7/igt@gem_...@in-flight-suspend.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/shard-kbl4/igt@gem_...@in-flight-suspend.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][21] -> [FAIL][22] ([i915#2846])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-glk1/igt@gem_exec_f...@basic-deadline.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/shard-glk1/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-kbl: [PASS][23] -> [FAIL][24] ([i915#2842])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs1.html
Re: [Intel-gfx] [PATCH i-g-t 5/7] lib/ioctl_wrappers: update mmap_{read, write} for discrete
On Mon, 26 Jul 2021 05:03:08 -0700, Matthew Auld wrote:
>
> We can no longer just call get_caching or set_domain, and the mmap mode
> must be FIXED. This should bring back gem_exec_basic and a few others in
> CI on DG1.
We should probably also similarly update mmap_{read, write} in
lib/intel_bufops.c.
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/10] drm/i915/bios: Enable parse of two integrated panels eDP data
On Wed, Jul 21, 2021 at 10:43:33PM -0700, José Roberto de Souza wrote:
> Continuing the conversion from single integrated VBT data to two, now
> handling eDP data.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/display/g4x_dp.c | 9 +--
> drivers/gpu/drm/i915/display/intel_bios.c | 62 +---
> drivers/gpu/drm/i915/display/intel_bios.h | 1 +
> drivers/gpu/drm/i915/display/intel_ddi.c | 9 +--
> .../drm/i915/display/intel_ddi_buf_trans.c| 71 ++-
> drivers/gpu/drm/i915/display/intel_dp.c | 7 +-
> drivers/gpu/drm/i915/display/intel_pps.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.h | 24 +++
> 8 files changed, 101 insertions(+), 86 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> b/drivers/gpu/drm/i915/display/g4x_dp.c
> index de0f358184aa3..273bc5295ae33 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -340,6 +340,7 @@ static void intel_dp_get_config(struct intel_encoder
> *encoder,
> u32 tmp, flags = 0;
> enum port port = encoder->port;
> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
>
> if (encoder->type == INTEL_OUTPUT_EDP)
> pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
> @@ -396,8 +397,8 @@ static void intel_dp_get_config(struct intel_encoder
> *encoder,
> intel_dotclock_calculate(pipe_config->port_clock,
>_config->dp_m_n);
>
> - if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
> - pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
> + if (intel_dp_is_edp(intel_dp) && vbt_edp_info->bpp &&
> + pipe_config->pipe_bpp > vbt_edp_info->bpp) {
> /*
>* This is a big fat ugly hack.
>*
> @@ -413,8 +414,8 @@ static void intel_dp_get_config(struct intel_encoder
> *encoder,
>*/
> drm_dbg_kms(_priv->drm,
> "pipe has %d bpp for eDP panel, overriding
> BIOS-provided max %d bpp\n",
> - pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
> - dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
> + pipe_config->pipe_bpp, vbt_edp_info->bpp);
> + vbt_edp_info->bpp = pipe_config->pipe_bpp;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 6770ed8b260be..f0d49af8be036 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -786,45 +786,45 @@ parse_power_conservation_features(struct
> drm_i915_private *i915,
> info->drrs_type = DRRS_NOT_SUPPORTED;
>
> if (bdb->version >= 232)
> - i915->vbt.edp.hobl = power->hobl & BIT(panel_index);
> + info->edp.hobl = power->hobl & BIT(panel_index);
> }
>
> static void
> -parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb)
> +parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb,
> + struct ddi_vbt_port_info *info, int panel_index)
> {
> const struct bdb_edp *edp;
> const struct edp_power_seq *edp_pps;
> const struct edp_fast_link_params *edp_link_params;
> - int panel_type = i915->vbt.panel_type;
>
> edp = find_section(bdb, BDB_EDP);
> if (!edp)
> return;
>
> - switch ((edp->color_depth >> (panel_type * 2)) & 3) {
> + switch ((edp->color_depth >> (panel_index * 2)) & 3) {
> case EDP_18BPP:
> - i915->vbt.edp.bpp = 18;
> + info->edp.bpp = 18;
> break;
> case EDP_24BPP:
> - i915->vbt.edp.bpp = 24;
> + info->edp.bpp = 24;
> break;
> case EDP_30BPP:
> - i915->vbt.edp.bpp = 30;
> + info->edp.bpp = 30;
> break;
> }
>
> /* Get the eDP sequencing and link info */
> - edp_pps = >power_seqs[panel_type];
> - edp_link_params = >fast_link_params[panel_type];
> + edp_pps = >power_seqs[panel_index];
> + edp_link_params = >fast_link_params[panel_index];
>
> - i915->vbt.edp.pps = *edp_pps;
> + info->edp.pps = *edp_pps;
>
> switch (edp_link_params->rate) {
> case EDP_RATE_1_62:
> - i915->vbt.edp.rate = DP_LINK_BW_1_62;
> + info->edp.rate = DP_LINK_BW_1_62;
> break;
> case EDP_RATE_2_7:
> - i915->vbt.edp.rate = DP_LINK_BW_2_7;
> + info->edp.rate = DP_LINK_BW_2_7;
> break;
> default:
> drm_dbg_kms(>drm,
> @@ -835,13 +835,13 @@ parse_edp(struct drm_i915_private *i915, const struct
> bdb_header *bdb)
>
>
[Intel-gfx] ✓ Fi.CI.BAT: success for Bump DMC version on ADLP to v2.11
== Series Details == Series: Bump DMC version on ADLP to v2.11 URL : https://patchwork.freedesktop.org/series/93081/ State : success == Summary == CI Bug Log - changes from CI_DRM_10406 -> Patchwork_20721 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20721/index.html Changes --- No changes found Participating hosts (41 -> 35) -- Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-bdw-samus bat-jsl-1 Build changes - * Linux: CI_DRM_10406 -> Patchwork_20721 CI-20190529: 20190529 CI_DRM_10406: 8b4ebf451f253cbffd08d98d14c7f0dba32f84c5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6153: a5dffe7499a2f7189718ddf1ccf49060b7c1529d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20721: 6f2260b088fc8c106102de79e61aba11ee32fd95 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6f2260b088fc drm/i915/dmc: Bump ADLP DMC version to v2.11 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20721/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/15] drm/i915/guc/slpc: Enable SLPC and add related H2G events
On 7/27/2021 1:19 PM, Michal Wajdeczko wrote:
On 27.07.2021 22:00, Belgaumkar, Vinay wrote:
On 7/27/2021 8:12 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Add methods for interacting with GuC for enabling SLPC. Enable
SLPC after GuC submission has been established. GuC load will
fail if SLPC cannot be successfully initialized. Add various
helper methods to set/unset the parameters for SLPC. They can
be set using H2G calls or directly setting bits in the shared
data structure.
v2: Address several review comments, add new helpers for
decoding the SLPC min/max frequencies. Use masks instead of hardcoded
constants. (Michal W)
v3: Split global_state_to_string function, and check for positive
non-zero return value from intel_guc_send() (Michal W)
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 237 ++
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 2 +
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8 +
3 files changed, 247 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index bae4e33db0f8..f5808d2acbca 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -45,6 +45,40 @@ void intel_guc_slpc_init_early(struct
intel_guc_slpc *slpc)
guc->slpc_selected = __guc_slpc_selected(guc);
}
+static void slpc_mem_set_param(struct slpc_shared_data *data,
+ u32 id, u32 value)
+{
+ GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS);
+ /*
+ * When the flag bit is set, corresponding value will be read
+ * and applied by slpc.
s/slpc/SLPC
ok.
+ */
+ data->override_params.bits[id >> 5] |= (1 << (id % 32));
+ data->override_params.values[id] = value;
+}
+
+static void slpc_mem_set_enabled(struct slpc_shared_data *data,
+ u8 enable_id, u8 disable_id)
+{
+ /*
+ * Enabling a param involves setting the enable_id
+ * to 1 and disable_id to 0.
+ */
+ slpc_mem_set_param(data, enable_id, 1);
+ slpc_mem_set_param(data, disable_id, 0);
+}
+
+static void slpc_mem_set_disabled(struct slpc_shared_data *data,
+ u8 enable_id, u8 disable_id)
+{
+ /*
+ * Disabling a param involves setting the enable_id
+ * to 0 and disable_id to 1.
+ */
+ slpc_mem_set_param(data, disable_id, 1);
+ slpc_mem_set_param(data, enable_id, 0);
+}
+
static int slpc_shared_data_init(struct intel_guc_slpc *slpc)
{
struct intel_guc *guc = slpc_to_guc(slpc);
@@ -63,6 +97,129 @@ static int slpc_shared_data_init(struct
intel_guc_slpc *slpc)
return err;
}
+static u32 slpc_get_state(struct intel_guc_slpc *slpc)
+{
+ struct slpc_shared_data *data;
+
+ GEM_BUG_ON(!slpc->vma);
+
+ drm_clflush_virt_range(slpc->vaddr, sizeof(u32));
+ data = slpc->vaddr;
+
+ return data->header.global_state;
+}
+
+static bool slpc_is_running(struct intel_guc_slpc *slpc)
+{
+ return (slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING);
extra ( ) not needed
ok.
+}
+
+static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
+{
+ u32 request[] = {
+ INTEL_GUC_ACTION_SLPC_REQUEST,
+ SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
+ offset,
+ 0,
+ };
+ int ret;
+
+ ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
+
+ return ret > 0 ? -EPROTO : ret;
+}
+
+static int slpc_query_task_state(struct intel_guc_slpc *slpc)
+{
+ struct intel_guc *guc = slpc_to_guc(slpc);
+ struct drm_i915_private *i915 = slpc_to_i915(slpc);
+ u32 shared_data_gtt_offset = intel_guc_ggtt_offset(guc, slpc->vma);
just "offset" ? or maybe pass directly in call below ?
ok.
+ int ret;
+
+ ret = guc_action_slpc_query(guc, shared_data_gtt_offset);
+ if (ret)
+ drm_err(>drm, "Query task state data returned (%pe)\n",
"Failed to query task state (%pe)\n" ?
ok.
+ ERR_PTR(ret));
+
+ drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
+
+ return ret;
+}
+
+static const char *slpc_global_state_to_string(enum
slpc_global_state state)
+{
+ const char *str = NULL;
+
+ switch (state) {
+ case SLPC_GLOBAL_STATE_NOT_RUNNING:
+ str = "not running";
+ break;
+ case SLPC_GLOBAL_STATE_INITIALIZING:
+ str = "initializing";
+ break;
+ case SLPC_GLOBAL_STATE_RESETTING:
+ str = "resetting";
+ break;
+ case SLPC_GLOBAL_STATE_RUNNING:
+ str = "running";
+ break;
+ case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
+ str = "shutting down";
+ break;
+ case SLPC_GLOBAL_STATE_ERROR:
+ str = "error";
+ break;
+ default:
+ str = "unknown";
nit: you can do early returns to simplify the code
ok.
+ break;
+ }
+
+ return str;
+}
+
+static const char *slpc_get_state_string(struct
Re: [Intel-gfx] [PATCH 06/15] drm/i915/guc/slpc: Enable SLPC and add related H2G events
On 27.07.2021 22:00, Belgaumkar, Vinay wrote:
>
>
> On 7/27/2021 8:12 AM, Michal Wajdeczko wrote:
>>
>>
>> On 26.07.2021 21:07, Vinay Belgaumkar wrote:
>>> Add methods for interacting with GuC for enabling SLPC. Enable
>>> SLPC after GuC submission has been established. GuC load will
>>> fail if SLPC cannot be successfully initialized. Add various
>>> helper methods to set/unset the parameters for SLPC. They can
>>> be set using H2G calls or directly setting bits in the shared
>>> data structure.
>>>
>>> v2: Address several review comments, add new helpers for
>>> decoding the SLPC min/max frequencies. Use masks instead of hardcoded
>>> constants. (Michal W)
>>>
>>> v3: Split global_state_to_string function, and check for positive
>>> non-zero return value from intel_guc_send() (Michal W)
>>>
>>> Signed-off-by: Vinay Belgaumkar
>>> Signed-off-by: Sundaresan Sujaritha
>>> ---
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 237 ++
>>> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 2 +
>>> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8 +
>>> 3 files changed, 247 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>>> index bae4e33db0f8..f5808d2acbca 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>>> @@ -45,6 +45,40 @@ void intel_guc_slpc_init_early(struct
>>> intel_guc_slpc *slpc)
>>> guc->slpc_selected = __guc_slpc_selected(guc);
>>> }
>>> +static void slpc_mem_set_param(struct slpc_shared_data *data,
>>> + u32 id, u32 value)
>>> +{
>>> + GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS);
>>> + /*
>>> + * When the flag bit is set, corresponding value will be read
>>> + * and applied by slpc.
>>
>> s/slpc/SLPC
> ok.
>
>>
>>> + */
>>> + data->override_params.bits[id >> 5] |= (1 << (id % 32));
>>> + data->override_params.values[id] = value;
>>> +}
>>> +
>>> +static void slpc_mem_set_enabled(struct slpc_shared_data *data,
>>> + u8 enable_id, u8 disable_id)
>>> +{
>>> + /*
>>> + * Enabling a param involves setting the enable_id
>>> + * to 1 and disable_id to 0.
>>> + */
>>> + slpc_mem_set_param(data, enable_id, 1);
>>> + slpc_mem_set_param(data, disable_id, 0);
>>> +}
>>> +
>>> +static void slpc_mem_set_disabled(struct slpc_shared_data *data,
>>> + u8 enable_id, u8 disable_id)
>>> +{
>>> + /*
>>> + * Disabling a param involves setting the enable_id
>>> + * to 0 and disable_id to 1.
>>> + */
>>> + slpc_mem_set_param(data, disable_id, 1);
>>> + slpc_mem_set_param(data, enable_id, 0);
>>> +}
>>> +
>>> static int slpc_shared_data_init(struct intel_guc_slpc *slpc)
>>> {
>>> struct intel_guc *guc = slpc_to_guc(slpc);
>>> @@ -63,6 +97,129 @@ static int slpc_shared_data_init(struct
>>> intel_guc_slpc *slpc)
>>> return err;
>>> }
>>> +static u32 slpc_get_state(struct intel_guc_slpc *slpc)
>>> +{
>>> + struct slpc_shared_data *data;
>>> +
>>> + GEM_BUG_ON(!slpc->vma);
>>> +
>>> + drm_clflush_virt_range(slpc->vaddr, sizeof(u32));
>>> + data = slpc->vaddr;
>>> +
>>> + return data->header.global_state;
>>> +}
>>> +
>>> +static bool slpc_is_running(struct intel_guc_slpc *slpc)
>>> +{
>>> + return (slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING);
>>
>> extra ( ) not needed
>
> ok.
>
>>
>>> +}
>>> +
>>> +static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
>>> +{
>>> + u32 request[] = {
>>> + INTEL_GUC_ACTION_SLPC_REQUEST,
>>> + SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
>>> + offset,
>>> + 0,
>>> + };
>>> + int ret;
>>> +
>>> + ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
>>> +
>>> + return ret > 0 ? -EPROTO : ret;
>>> +}
>>> +
>>> +static int slpc_query_task_state(struct intel_guc_slpc *slpc)
>>> +{
>>> + struct intel_guc *guc = slpc_to_guc(slpc);
>>> + struct drm_i915_private *i915 = slpc_to_i915(slpc);
>>> + u32 shared_data_gtt_offset = intel_guc_ggtt_offset(guc, slpc->vma);
>>
>> just "offset" ? or maybe pass directly in call below ?
>
> ok.
>
>>
>>> + int ret;
>>> +
>>> + ret = guc_action_slpc_query(guc, shared_data_gtt_offset);
>>> + if (ret)
>>> + drm_err(>drm, "Query task state data returned (%pe)\n",
>>
>> "Failed to query task state (%pe)\n" ?
>
> ok.
>>
>>> + ERR_PTR(ret));
>>> +
>>> + drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +static const char *slpc_global_state_to_string(enum
>>> slpc_global_state state)
>>> +{
>>> + const char *str = NULL;
>>> +
>>> + switch (state) {
>>> + case SLPC_GLOBAL_STATE_NOT_RUNNING:
>>> + str = "not running";
>>> + break;
>>> + case SLPC_GLOBAL_STATE_INITIALIZING:
>>> + str = "initializing";
>>> + break;
>>> + case
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix the 12 BPC bits for PIPE_MISC reg (rev2)
== Series Details ==
Series: drm/i915: Fix the 12 BPC bits for PIPE_MISC reg (rev2)
URL : https://patchwork.freedesktop.org/series/92690/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10403_full -> Patchwork_20714_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20714_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20714_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20714_full:
### IGT changes ###
Possible regressions
* igt@kms_selftest@all@damage_iter_no_damage:
- shard-snb: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/shard-snb7/igt@kms_selftest@all@damage_iter_no_damage.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_busy@extended-modeset-hang-newfb-with-reset:
- {shard-rkl}:NOTRUN -> [SKIP][2] +1 similar issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/shard-rkl-2/igt@kms_b...@extended-modeset-hang-newfb-with-reset.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- {shard-rkl}:[SKIP][3] ([i915#1849]) -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10403/shard-rkl-1/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/shard-rkl-6/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- {shard-rkl}:[SKIP][5] ([i915#1845]) -> [DMESG-WARN][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10403/shard-rkl-2/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/shard-rkl-6/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html
* igt@runner@aborted:
- {shard-rkl}:([FAIL][7], [FAIL][8], [FAIL][9]) ([i915#3002] /
[i915#3810]) -> ([FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14])
([i915#2029] / [i915#3002] / [i915#3621] / [i915#3810] / [i915#3811])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10403/shard-rkl-1/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10403/shard-rkl-5/igt@run...@aborted.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10403/shard-rkl-2/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/shard-rkl-1/igt@run...@aborted.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/shard-rkl-2/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/shard-rkl-2/igt@run...@aborted.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/shard-rkl-6/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/shard-rkl-6/igt@run...@aborted.html
New tests
-
New tests have been introduced between CI_DRM_10403_full and
Patchwork_20714_full:
### New IGT tests (1) ###
* igt@kms_busy@extended-pageflip-hang-oldfb@pipe-b:
- Statuses : 1 pass(s)
- Exec time: [0.14] s
Known issues
Here are the changes found in Patchwork_20714_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#1099]) +4
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-queued.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [PASS][16] -> [FAIL][17] ([i915#2842]) +1 similar
issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10403/shard-glk6/igt@gem_exec_fair@basic-n...@vcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/shard-glk2/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [PASS][18] -> [FAIL][19] ([i915#2842])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10403/shard-kbl4/igt@gem_exec_fair@basic-n...@vecs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/shard-kbl2/igt@gem_exec_fair@basic-n...@vecs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [PASS][20] -> [FAIL][21] ([i915#2842])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10403/shard-tglb3/igt@gem_exec_fair@basic-p...@rcs0.html
[21]:
Re: [Intel-gfx] [PATCH 06/15] drm/i915/guc/slpc: Enable SLPC and add related H2G events
On 7/27/2021 8:12 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Add methods for interacting with GuC for enabling SLPC. Enable
SLPC after GuC submission has been established. GuC load will
fail if SLPC cannot be successfully initialized. Add various
helper methods to set/unset the parameters for SLPC. They can
be set using H2G calls or directly setting bits in the shared
data structure.
v2: Address several review comments, add new helpers for
decoding the SLPC min/max frequencies. Use masks instead of hardcoded
constants. (Michal W)
v3: Split global_state_to_string function, and check for positive
non-zero return value from intel_guc_send() (Michal W)
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 237 ++
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 2 +
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8 +
3 files changed, 247 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index bae4e33db0f8..f5808d2acbca 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -45,6 +45,40 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
guc->slpc_selected = __guc_slpc_selected(guc);
}
+static void slpc_mem_set_param(struct slpc_shared_data *data,
+ u32 id, u32 value)
+{
+ GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS);
+ /*
+* When the flag bit is set, corresponding value will be read
+* and applied by slpc.
s/slpc/SLPC
ok.
+*/
+ data->override_params.bits[id >> 5] |= (1 << (id % 32));
+ data->override_params.values[id] = value;
+}
+
+static void slpc_mem_set_enabled(struct slpc_shared_data *data,
+ u8 enable_id, u8 disable_id)
+{
+ /*
+* Enabling a param involves setting the enable_id
+* to 1 and disable_id to 0.
+*/
+ slpc_mem_set_param(data, enable_id, 1);
+ slpc_mem_set_param(data, disable_id, 0);
+}
+
+static void slpc_mem_set_disabled(struct slpc_shared_data *data,
+ u8 enable_id, u8 disable_id)
+{
+ /*
+* Disabling a param involves setting the enable_id
+* to 0 and disable_id to 1.
+*/
+ slpc_mem_set_param(data, disable_id, 1);
+ slpc_mem_set_param(data, enable_id, 0);
+}
+
static int slpc_shared_data_init(struct intel_guc_slpc *slpc)
{
struct intel_guc *guc = slpc_to_guc(slpc);
@@ -63,6 +97,129 @@ static int slpc_shared_data_init(struct intel_guc_slpc
*slpc)
return err;
}
+static u32 slpc_get_state(struct intel_guc_slpc *slpc)
+{
+ struct slpc_shared_data *data;
+
+ GEM_BUG_ON(!slpc->vma);
+
+ drm_clflush_virt_range(slpc->vaddr, sizeof(u32));
+ data = slpc->vaddr;
+
+ return data->header.global_state;
+}
+
+static bool slpc_is_running(struct intel_guc_slpc *slpc)
+{
+ return (slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING);
extra ( ) not needed
ok.
+}
+
+static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
+{
+ u32 request[] = {
+ INTEL_GUC_ACTION_SLPC_REQUEST,
+ SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
+ offset,
+ 0,
+ };
+ int ret;
+
+ ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
+
+ return ret > 0 ? -EPROTO : ret;
+}
+
+static int slpc_query_task_state(struct intel_guc_slpc *slpc)
+{
+ struct intel_guc *guc = slpc_to_guc(slpc);
+ struct drm_i915_private *i915 = slpc_to_i915(slpc);
+ u32 shared_data_gtt_offset = intel_guc_ggtt_offset(guc, slpc->vma);
just "offset" ? or maybe pass directly in call below ?
ok.
+ int ret;
+
+ ret = guc_action_slpc_query(guc, shared_data_gtt_offset);
+ if (ret)
+ drm_err(>drm, "Query task state data returned (%pe)\n",
"Failed to query task state (%pe)\n" ?
ok.
+ ERR_PTR(ret));
+
+ drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
+
+ return ret;
+}
+
+static const char *slpc_global_state_to_string(enum slpc_global_state state)
+{
+ const char *str = NULL;
+
+ switch (state) {
+ case SLPC_GLOBAL_STATE_NOT_RUNNING:
+ str = "not running";
+ break;
+ case SLPC_GLOBAL_STATE_INITIALIZING:
+ str = "initializing";
+ break;
+ case SLPC_GLOBAL_STATE_RESETTING:
+ str = "resetting";
+ break;
+ case SLPC_GLOBAL_STATE_RUNNING:
+ str = "running";
+ break;
+ case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
+ str = "shutting down";
+ break;
+ case SLPC_GLOBAL_STATE_ERROR:
+ str = "error";
+
Re: [Intel-gfx] [PATCH 15/15] drm/i915/guc/rc: Setup and enable GUCRC feature
On Tue, Jul 27, 2021 at 09:18:08AM -0700, Belgaumkar, Vinay wrote: > > > On 7/27/2021 8:37 AM, Matt Roper wrote: > > On Mon, Jul 26, 2021 at 12:08:00PM -0700, Vinay Belgaumkar wrote: > > > This feature hands over the control of HW RC6 to the GuC. > > > GuC decides when to put HW into RC6 based on it's internal > > > busyness algorithms. > > > > > > GUCRC needs GuC submission to be enabled, and only > > > supported on Gen12+ for now. > > > > > > When GUCRC is enabled, do not set HW RC6. Use a H2G message > > > to tell GuC to enable GUCRC. When disabling RC6, tell GuC to > > > revert RC6 control back to KMD. > > > > > > v2: Address comments (Michal W) > > > > > > Reviewed-by: Michal Wajdeczko > > > Signed-off-by: Vinay Belgaumkar > > > --- > > > drivers/gpu/drm/i915/Makefile | 1 + > > > drivers/gpu/drm/i915/gt/intel_rc6.c | 22 +++-- > > > .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 6 ++ > > > drivers/gpu/drm/i915/gt/uc/intel_guc.c| 1 + > > > drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 + > > > drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 80 +++ > > > drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h | 31 +++ > > > drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 + > > > 8 files changed, 140 insertions(+), 5 deletions(-) > > > create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c > > > create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h > > > > > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > > > index d8eac4468df9..3fc17f20d88e 100644 > > > --- a/drivers/gpu/drm/i915/Makefile > > > +++ b/drivers/gpu/drm/i915/Makefile > > > @@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \ > > > gt/uc/intel_guc_fw.o \ > > > gt/uc/intel_guc_log.o \ > > > gt/uc/intel_guc_log_debugfs.o \ > > > + gt/uc/intel_guc_rc.o \ > > > gt/uc/intel_guc_slpc.o \ > > > gt/uc/intel_guc_submission.o \ > > > gt/uc/intel_huc.o \ > > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c > > > b/drivers/gpu/drm/i915/gt/intel_rc6.c > > > index 259d7eb4e165..299fcf10b04b 100644 > > > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c > > > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c > > > @@ -98,11 +98,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) > > > set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60); > > > set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60); > > > > Do steps 2b and 2c above this still apply to gucrc? Are those still > > controlling the behavior of gucrc or does the GuC firmware just > > overwrite them with its own values? If they're still impacting the > > behavior when gucrc is enabled, is there any updated guidance on how the > > values should be set? It seems that there isn't any guidance in the > > bspec for the last several platforms, so we've pretty much been re-using > > old values without knowing if there's additional adjustment that should > > be done for the newer platforms. > > > > If the tuning values the driver sets get ignored/overwritten during GuC > > operation, maybe we should add a new gucrc_rc6_enable() that gets used > > instead of gen11_rc6_enable() and drops the unnecessary steps to help > > clarify what's truly important? > > Yeah, 2b does get overwritten by guc, but we still need 2c. > > > > > > > > - /* 3a: Enable RC6 */ > > > - rc6->ctl_enable = > > > - GEN6_RC_CTL_HW_ENABLE | > > > - GEN6_RC_CTL_RC6_ENABLE | > > > - GEN6_RC_CTL_EI_MODE(1); > > > + /* 3a: Enable RC6 > > > + * > > > + * With GUCRC, we do not enable bit 31 of RC_CTL, > > > + * thus allowing GuC to control RC6 entry/exit fully instead. > > > + * We will not set the HW ENABLE and EI bits > > > + */ > > > + if (!intel_guc_rc_enable(>uc.guc)) > > > + rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE; > > > + else > > > + rc6->ctl_enable = > > > + GEN6_RC_CTL_HW_ENABLE | > > > + GEN6_RC_CTL_RC6_ENABLE | > > > + GEN6_RC_CTL_EI_MODE(1); > > > pg_enable = > > > GEN9_RENDER_PG_ENABLE | > > > > We should probably clarify in the commit message that gucrc doesn't > > cover powergating and leaves that under driver control. Maybe we should > > even pull this out into its own function rather than leaving it in the > > "rc6 enable" function since it really is its own thing? > > I have a note in the summary patch about this, will pull it into this patch > header as well. > > There is already a separate effort underway from Suja to decouple RC6 and > coarse power gate enabling. Might become more streamlined after that. > > For now, I can have an if check around 2b so that there is more clarity? Yeah, if there's already a separate refactoring effort happening, then just adding an 'if' check to help clarify which parts of this function actually have an effect with gucrc is probably good enough for now.
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/1] drm/i915: dgfx cards need to wait on pcode's uncore init done
== Series Details ==
Series: series starting with [1/1] drm/i915: dgfx cards need to wait on pcode's
uncore init done
URL : https://patchwork.freedesktop.org/series/93075/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10405 -> Patchwork_20720
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/index.html
Known issues
Here are the changes found in Patchwork_20720 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +25 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: NOTRUN -> [WARN][2] ([i915#3718])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html
* igt@i915_pm_rpm@basic-rte:
- fi-bdw-5557u: NOTRUN -> [FAIL][3] ([i915#579])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/fi-bdw-5557u/igt@i915_pm_...@basic-rte.html
Possible fixes
* igt@i915_selftest@live@migrate:
- {fi-hsw-gt1}: [FAIL][4] -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/fi-hsw-gt1/igt@i915_selftest@l...@migrate.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/fi-hsw-gt1/igt@i915_selftest@l...@migrate.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][6] ([i915#1372]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (41 -> 35)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-bdw-samus
bat-jsl-1
Build changes
-
* Linux: CI_DRM_10405 -> Patchwork_20720
CI-20190529: 20190529
CI_DRM_10405: 6db19b5e1fac016d9dffa6ce54aa21f3200c5c8d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6153: a5dffe7499a2f7189718ddf1ccf49060b7c1529d @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20720: 073d8955a1b057132f5d1f8a4343f1f703865ea0 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
073d8955a1b0 drm/i915: dgfx cards need to wait on pcode's uncore init done
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 29/33] drm/i915/selftest: Increase some timeouts in live_requests
On 7/26/2021 17:23, Matthew Brost wrote: Requests may take slightly longer with GuC submission, let's increase the timeouts in live_requests. Signed-off-by: Matthew Brost Was already reviewed in previous series. Repeating here for patchwork: Reviewed-by: John Harrison --- drivers/gpu/drm/i915/selftests/i915_request.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index bd5c96a77ba3..d67710d10615 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -1313,7 +1313,7 @@ static int __live_parallel_engine1(void *arg) i915_request_add(rq); err = 0; - if (i915_request_wait(rq, 0, HZ / 5) < 0) + if (i915_request_wait(rq, 0, HZ) < 0) err = -ETIME; i915_request_put(rq); if (err) @@ -1419,7 +1419,7 @@ static int __live_parallel_spin(void *arg) } igt_spinner_end(); - if (err == 0 && i915_request_wait(rq, 0, HZ / 5) < 0) + if (err == 0 && i915_request_wait(rq, 0, HZ) < 0) err = -EIO; i915_request_put(rq); ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 14/15] drm/i915/guc/slpc: Add SLPC selftest
On Mon, Jul 26, 2021 at 12:07:59PM -0700, Vinay Belgaumkar wrote:
> Tests that exercise the SLPC get/set frequency interfaces.
>
> Clamp_max will set max frequency to multiple levels and check
> that SLPC requests frequency lower than or equal to it.
>
> Clamp_min will set min frequency to different levels and check
> if SLPC requests are higher or equal to those levels.
>
> v2: Address review comments (Michal W)
> v3: Checkpatch() corrections
>
> Signed-off-by: Vinay Belgaumkar
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 1 +
> drivers/gpu/drm/i915/gt/selftest_slpc.c | 311 ++
> drivers/gpu/drm/i915/gt/selftest_slpc.h | 12 +
> .../drm/i915/selftests/i915_live_selftests.h | 1 +
> 4 files changed, 325 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/gt/selftest_slpc.c
> create mode 100644 drivers/gpu/drm/i915/gt/selftest_slpc.h
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 48d4147165a9..6237332835fe 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2318,4 +2318,5 @@ EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
>
> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> #include "selftest_rps.c"
> +#include "selftest_slpc.c"
> #endif
> diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c
> b/drivers/gpu/drm/i915/gt/selftest_slpc.c
> new file mode 100644
> index ..5018f686686f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
> @@ -0,0 +1,311 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include "selftest_slpc.h"
> +
> +#define NUM_STEPS 5
> +#define H2G_DELAY 5
> +#define delay_for_h2g() usleep_range(H2G_DELAY, H2G_DELAY + 1)
> +
> +static int set_min_freq(struct intel_guc_slpc *slpc, u32 freq)
> +{
> + int ret;
> +
> + ret = intel_guc_slpc_set_min_freq(slpc, freq);
> + if (ret)
> + pr_err("Could not set min frequency to [%u]\n", freq);
> + else /* Delay to ensure h2g completes */
> + delay_for_h2g();
> +
> + return ret;
> +}
> +
> +static int set_max_freq(struct intel_guc_slpc *slpc, u32 freq)
> +{
> + int ret;
> +
> + ret = intel_guc_slpc_set_max_freq(slpc, freq);
> + if (ret)
> + pr_err("Could not set maximum frequency [%u]\n",
> + freq);
> + else /* Delay to ensure h2g completes */
> + delay_for_h2g();
> +
> + return ret;
> +}
> +
> +int live_slpc_clamp_min(void *arg)
> +{
> + struct drm_i915_private *i915 = arg;
> + struct intel_gt *gt = >gt;
> + struct intel_guc_slpc *slpc = >uc.guc.slpc;
> + struct intel_rps *rps = >rps;
> + struct intel_engine_cs *engine;
> + enum intel_engine_id id;
> + struct igt_spinner spin;
> + u32 slpc_min_freq, slpc_max_freq;
> + int err = 0;
> +
> + if (!intel_uc_uses_guc_slpc(>uc))
> + return 0;
> +
> + if (igt_spinner_init(, gt))
> + return -ENOMEM;
> +
> + if (intel_guc_slpc_get_max_freq(slpc, _max_freq)) {
> + pr_err("Could not get SLPC max freq\n");
> + return -EIO;
> + }
> +
> + if (intel_guc_slpc_get_min_freq(slpc, _min_freq)) {
> + pr_err("Could not get SLPC min freq\n");
> + return -EIO;
> + }
> +
> + if (slpc_min_freq == slpc_max_freq) {
> + pr_err("Min/Max are fused to the same value\n");
> + return -EINVAL;
> + }
> +
> + intel_gt_pm_wait_for_idle(gt);
> + intel_gt_pm_get(gt);
> + for_each_engine(engine, gt, id) {
> + struct i915_request *rq;
> + u32 step, min_freq, req_freq;
> + u32 act_freq, max_act_freq;
> +
> + if (!intel_engine_can_store_dword(engine))
> + continue;
> +
> + /* Go from min to max in 5 steps */
> + step = (slpc_max_freq - slpc_min_freq) / NUM_STEPS;
> + max_act_freq = slpc_min_freq;
> + for (min_freq = slpc_min_freq; min_freq < slpc_max_freq;
> + min_freq += step) {
> + err = set_min_freq(slpc, min_freq);
> + if (err)
> + break;
> +
> + st_engine_heartbeat_disable(engine);
> +
> + rq = igt_spinner_create_request(,
> + engine->kernel_context,
> + MI_NOOP);
> + if (IS_ERR(rq)) {
> + err = PTR_ERR(rq);
> + st_engine_heartbeat_enable(engine);
> + break;
> + }
> +
> + i915_request_add(rq);
> +
> + if (!igt_wait_for_spinner(, rq)) {
> + pr_err("%s: Spinner did not start\n",
> +
Re: [Intel-gfx] [PATCH 25/33] drm/i915/guc: Support request cancellation
On 7/26/2021 5:23 PM, Matthew Brost wrote:
This adds GuC backend support for i915_request_cancel(), which in turn
makes CONFIG_DRM_I915_REQUEST_TIMEOUT work.
This implementation makes use of fence while there are likely simplier
options. A fence was chosen because of another feature coming soon
which requires a user to block on a context until scheduling is
disabled. In that case we return the fence to the user and the user can
wait on that fence.
v2:
(Daniele)
- A comment about locking the blocked incr / decr
- A comments about the use of the fence
- Update commit message explaining why fence
- Delete redundant check blocked count in unblock function
- Ring buffer implementation
- Comment about blocked in submission path
- Shorter rpm path
v3:
(Checkpatch)
- Fix typos in commit message
(Daniel)
- Rework to simplier locking structure in guc_context_block / unblock
Signed-off-by: Matthew Brost
Cc: Tvrtko Ursulin
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/intel_context.c | 13 ++
drivers/gpu/drm/i915/gt/intel_context.h | 7 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 9 +-
.../drm/i915/gt/intel_execlists_submission.c | 18 ++
.../gpu/drm/i915/gt/intel_ring_submission.c | 16 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 188 ++
drivers/gpu/drm/i915/i915_request.c | 14 +-
7 files changed, 251 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 237b70e98744..477c42d7d693 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -366,6 +366,12 @@ static int __intel_context_active(struct i915_active
*active)
return 0;
}
+static int sw_fence_dummy_notify(struct i915_sw_fence *sf,
+enum i915_sw_fence_notify state)
+{
+ return NOTIFY_DONE;
+}
+
void
intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine)
{
@@ -399,6 +405,13 @@ intel_context_init(struct intel_context *ce, struct
intel_engine_cs *engine)
ce->guc_id = GUC_INVALID_LRC_ID;
INIT_LIST_HEAD(>guc_id_link);
+ /*
+* Initialize fence to be complete as this is expected to be complete
+* unless there is a pending schedule disable outstanding.
+*/
+ i915_sw_fence_init(>guc_blocked, sw_fence_dummy_notify);
+ i915_sw_fence_commit(>guc_blocked);
+
i915_active_init(>active,
__intel_context_active, __intel_context_retire, 0);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index 814d9277096a..876bdb08303c 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -70,6 +70,13 @@ intel_context_is_pinned(struct intel_context *ce)
return atomic_read(>pin_count);
}
+static inline void intel_context_cancel_request(struct intel_context *ce,
+ struct i915_request *rq)
+{
+ GEM_BUG_ON(!ce->ops->cancel_request);
+ return ce->ops->cancel_request(ce, rq);
+}
+
/**
* intel_context_unlock_pinned - Releases the earlier locking of 'pinned'
status
* @ce - the context
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 57c19ee3e313..a5bc876face7 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -13,6 +13,7 @@
#include
#include "i915_active_types.h"
+#include "i915_sw_fence.h"
#include "i915_utils.h"
#include "intel_engine_types.h"
#include "intel_sseu.h"
@@ -42,6 +43,9 @@ struct intel_context_ops {
void (*unpin)(struct intel_context *ce);
void (*post_unpin)(struct intel_context *ce);
+ void (*cancel_request)(struct intel_context *ce,
+ struct i915_request *rq);
+
void (*enter)(struct intel_context *ce);
void (*exit)(struct intel_context *ce);
@@ -156,7 +160,7 @@ struct intel_context {
* sched_state: scheduling state of this context using GuC
* submission
*/
- u8 sched_state;
+ u16 sched_state;
/*
* fences: maintains of list of requests that have a submit
* fence related to GuC submission
@@ -184,6 +188,9 @@ struct intel_context {
* GuC ID link - in list when unpinned but guc_id still valid in GuC
*/
struct list_head guc_id_link;
+
+ /* GuC context blocked fence */
+ struct i915_sw_fence guc_blocked;
};
#endif /* __INTEL_CONTEXT_TYPES__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index b4a876736074..de5f9c86b9a4 100644
Re: [Intel-gfx] [PATCH v3 06/30] drm/i915/xehp: handle new steering options
On Fri, 2021-07-23 at 10:42 -0700, Matt Roper wrote:
> From: Daniele Ceraolo Spurio
>
> Xe_HP is more modular then its predecessors and as a consequence it
then -> than
> has
> more types of replicated registers. As with l3bank regions on
> previous
> platforms, we may need to explicitly re-steer accesses to these new
> types of ranges at runtime if we can't find a single default steering
> value that satisfies the fusing of all types.
>
> Bspec: 66534
> Cc: Tvrtko Ursulin
> Signed-off-by: Daniele Ceraolo Spurio <
> daniele.ceraolospu...@intel.com>
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 40 -
> drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
> drivers/gpu/drm/i915/gt/intel_gt_types.h| 7 ++
> drivers/gpu/drm/i915/gt/intel_region_lmem.c | 1 +
> drivers/gpu/drm/i915/gt/intel_sseu.c| 18 +
> drivers/gpu/drm/i915/gt/intel_sseu.h| 6 ++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 89
> +++--
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 4 +
> drivers/gpu/drm/i915/intel_device_info.h| 1 +
> 11 files changed, 165 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 46441607d18b..0ee33a31a3cd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -89,6 +89,13 @@ static const struct intel_mmio_range
> icl_l3bank_steering_table[] = {
> {},
> };
>
> +static u16 slicemask(struct intel_gt *gt, int count)
> +{
> + u64 dss_mask = intel_sseu_get_subslices(>info.sseu, 0);
> +
> + return intel_slicemask_from_dssmask(dss_mask, count);
> +}
> +
> int intel_gt_init_mmio(struct intel_gt *gt)
> {
> intel_gt_init_clock_frequency(gt);
> @@ -96,11 +103,24 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> intel_uc_init_mmio(>uc);
> intel_sseu_info_init(gt);
>
> - if (GRAPHICS_VER(gt->i915) >= 11) {
> + /*
> + * An mslice is unavailable only if both the meml3 for the
> slice is
> + * disabled *and* all of the DSS in the slice (quadrant) are
> disabled.
> + */
> + if (HAS_MSLICES(gt->i915))
> + gt->info.mslice_mask =
> + slicemask(gt, GEN_DSS_PER_MSLICE) |
> + (intel_uncore_read(gt->uncore,
> GEN10_MIRROR_FUSE3) &
> + GEN12_MEML3_EN_MASK);
> +
> + if (GRAPHICS_VER(gt->i915) >= 11 &&
> +GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50)) {
gt->i915 is referenced many times. It is better to define
i915 = gt->i915;
> gt->steering_table[L3BANK] = icl_l3bank_steering_table;
> gt->info.l3bank_mask =
> ~intel_uncore_read(gt->uncore,
> GEN10_MIRROR_FUSE3) &
> GEN10_L3BANK_MASK;
> + } else if (HAS_MSLICES(gt->i915)) {
> + MISSING_CASE(INTEL_INFO(gt->i915)->platform);
> }
>
> return intel_engines_init_mmio(gt);
> @@ -785,6 +805,24 @@ static void intel_gt_get_valid_steering(struct
> intel_gt *gt,
> *sliceid = 0; /* unused */
> *subsliceid = __ffs(gt->info.l3bank_mask);
> break;
> + case MSLICE:
> + GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be
> impossible! */
> +
> + *sliceid = __ffs(gt->info.mslice_mask);
> + *subsliceid = 0;/* unused */
> + break;
> + case LNCF:
> + GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be
> impossible! */
> +
> + /*
> + * 0xFDC[29:28] selects the mslice to steer to and
> 0xFDC[27]
> + * selects which LNCF within the mslice to steer
> to. An LNCF
> + * is always present if its mslice is present, so we
> can safely
> + * just steer to LNCF 0 in all cases.
> + */
> + *sliceid = __ffs(gt->info.mslice_mask) << 1;
> + *subsliceid = 0;/* unused */
> + break;
> default:
> MISSING_CASE(type);
> *sliceid = 0;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
> b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 74e771871a9b..24b78398a587 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -84,6 +84,7 @@ static inline bool
> intel_gt_needs_read_steering(struct intel_gt *gt,
> }
>
> u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);
> +u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
Shoulde this function declaration be included in this patch? I don't
find corresponding body in this patch.
-caz
>
> void intel_gt_info_print(const struct intel_gt_info *info,
>struct drm_printer *p);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
>
Re: [Intel-gfx] [PATCH 04/15] drm/i915/guc/slpc: Adding SLPC communication interfaces
On 7/27/2021 6:59 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Add constants and params that are needed to configure SLPC.
v2: Add a new abi header for SLPC. Replace bitfields with
genmasks. Address other comments from Michal W.
v3: Add slpc H2G format in abi, other review commments (Michal W)
v4: Update status bits according to latest spec
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 1 -
.../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 235 ++
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 3 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 7 +
4 files changed, 245 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index d832c8f11c11..ca538e5de940 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -135,7 +135,6 @@ enum intel_guc_action {
INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007,
INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,
INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
- INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
new file mode 100644
index ..70b300d4a536
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
@@ -0,0 +1,235 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _GUC_ACTIONS_SLPC_ABI_H_
+#define _GUC_ACTIONS_SLPC_ABI_H_
+
+#include
+
+/**
+ * DOC: SLPC SHARED DATA STRUCTURE
+ *
+ *
++--+--+
+ * | CL | Bytes| Description
|
+ *
++==+==+
+ * | 1 | 0-3 | SHARED DATA SIZE
|
+ * |
+--+--+
+ * || 4-7 | GLOBAL STATE
|
+ * |
+--+--+
+ * || 8-11 | DISPLAY DATA ADDRESS
|
+ * |
+--+--+
+ * || 12:63| PADDING
|
+ *
++--+--+
+ * || 0:63 | PADDING(PLATFORM INFO)
|
+ *
++--+--+
+ * | 3 | 0-3 | TASK STATE DATA
|
+ * +
+--+--+
+ * || 4:63 | PADDING
|
+ *
++--+--+
+ * |4-21|0:1087| OVERRIDE PARAMS AND BIT FIELDS
|
+ *
++--+--+
+ * || | PADDING + EXTRA RESERVED PAGE
|
+ *
++--+--+
+ */
+
+/*
+ * SLPC exposes certain parameters for global configuration by the host.
+ * These are referred to as override parameters, because in most cases
+ * the host will not need to modify the default values used by SLPC.
+ * SLPC remembers the default values which allows the host to easily restore
+ * them by simply unsetting the override. The host can set or unset override
+ * parameters during SLPC (re-)initialization using the SLPC Reset event.
+ * The host can also set or unset override parameters on the fly using the
+ * Parameter Set and Parameter Unset events
+ */
+
+#define SLPC_MAX_OVERRIDE_PARAMETERS 256
+#define SLPC_OVERRIDE_BITFIELD_SIZE \
+ (SLPC_MAX_OVERRIDE_PARAMETERS / 32)
+
+#define SLPC_PAGE_SIZE_BYTES 4096
+#define SLPC_CACHELINE_SIZE_BYTES 64
+#define SLPC_SHARED_DATA_SIZE_BYTE_HEADER SLPC_CACHELINE_SIZE_BYTES
+#define SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO
SLPC_CACHELINE_SIZE_BYTES
+#define SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE SLPC_CACHELINE_SIZE_BYTES
+#define SLPC_SHARED_DATA_MODE_DEFN_TABLE_SIZE SLPC_PAGE_SIZE_BYTES
+#define SLPC_SHARED_DATA_SIZE_BYTE_MAX (2 * SLPC_PAGE_SIZE_BYTES)
+
+/*
+ * Cacheline size
Re: [Intel-gfx] [PATCH v3 01/30] drm/i915/xehpsdv: Correct parameters for IS_XEHPSDV_GT_STEP()
On Tue, 2021-07-27 at 11:38 -0700, Matt Roper wrote:
> On Tue, Jul 27, 2021 at 11:34:28AM -0700, Yokoyama, Caz wrote:
> > On Fri, 2021-07-23 at 10:42 -0700, Matt Roper wrote:
> > > During a rebase the parameters were partially renamed, but not
> > > completely. Since the subsequent patches that start using this
> > > macro
> > > haven't landed on an upstream tree yet this didn't cause a build
> > > failure.
> > >
> > > Fixes: 086df54e20be ("drm/i915/xehpsdv: add initial XeHP SDV
> > > definitions")
> > > Signed-off-by: Matt Roper
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index d118834a4ed9..d44d0050beec 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1562,8 +1562,8 @@ IS_SUBPLATFORM(const struct
> > > drm_i915_private
> > > *i915,
> > > (IS_ALDERLAKE_P(__i915) && \
> > >IS_GT_STEP(__i915, since, until))
> > >
> > > -#define IS_XEHPSDV_GT_STEP(p, since, until) \
> > > - (IS_XEHPSDV(p) && IS_GT_STEP(__i915, since, until))
> > > +#define IS_XEHPSDV_GT_STEP(__i915, since, until) \
> > > + (IS_XEHPSDV(__i915) && IS_GT_STEP(__i915, since, until))
> > Is your comment saying that the first parameter
> > of IS_XEHPSDV_GT_STEP(), p or __i915 must be the first parameter of
> > both IS_XEHPSDV() and IS_GT_STEP()? The older code is a bug,
> > correct?
> > -caz
>
> We can name the parameter anything we want, it just has to be used
> consistently throughout the macro. Defining the parameter as 'p' but
> then passing a different undefined name '__i915' into IS_GT_STEP
> won't
> work (but it will only start causing compile errors when we land
> workarounds and such that start using the macro).
Reviewed-by: Caz Yokoyama
-caz
>
>
> Matt
>
> > > /*
> > > * DG2 hardware steppings are a bit unusual. The hardware
> > > design
> > > was forked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/1] Bump DMC version on ADLP to v2.11
Adding PR for CI to pickthe firmware: The following changes since commit 168452ee695b5edb9deb641059bc110b9c5e8fc7: Merge tag 'iwlwifi-fw-2021-07-19' of git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/linux-firmware into main (2021-07-19 14:35:47 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware adlp_dmc_2_11 for you to fetch changes up to e5b34bc00848422a9d9907694202f1e29c5e9671: i915: Bump DMC version for ADLP to v2.11 (2021-07-27 11:20:31 -0700) Anusha Srivatsa (1): i915: Bump DMC version for ADLP to v2.11 WHENCE| 3 +++ i915/adlp_dmc_ver2_11.bin | Bin 0 -> 72024 bytes 2 files changed, 3 insertions(+) create mode 100644 i915/adlp_dmc_ver2_11.bin Anusha Srivatsa (1): drm/i915/dmc: Bump ADLP DMC version to v2.11 drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.32.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/1] drm/i915/dmc: Bump ADLP DMC version to v2.11
Release notes mention that this verion has: - Fixes for DC6v issue. - Flip queue enabled on pipe C and pipe D. Cc: Imre Deak Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 9895fd957df9..601c30b92739 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -45,8 +45,8 @@ #define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE -#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 10) -#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 10) +#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 11) +#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 11) MODULE_FIRMWARE(ADLP_DMC_PATH); #define ADLS_DMC_PATH DMC_PATH(adls, 2, 01) -- 2.32.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/15] drm/i915/guc/slpc: Initial definitions for SLPC
On 7/27/2021 6:43 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Add macros to check for SLPC support. This feature is currently supported
for Gen12+ and enabled whenever GuC submission is enabled/selected.
Include templates for SLPC init/fini and enable.
v2: Move SLPC helper functions to intel_guc_slpc.c/.h. Define basic
template for SLPC structure in intel_guc_slpc_types.h. Fix copyright (Michal W)
v3: Review comments (Michal W)
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
Signed-off-by: Daniele Ceraolo Spurio
drm/i915/guc/slpc: Lay out slpc init/enable/fini
Declare init/fini and enable function templates.
v2: Rebase
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 45 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 33 ++
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 12 +
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 ++-
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 +
8 files changed, 103 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index ab7679957623..d8eac4468df9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \
gt/uc/intel_guc_fw.o \
gt/uc/intel_guc_log.o \
gt/uc/intel_guc_log_debugfs.o \
+ gt/uc/intel_guc_slpc.o \
gt/uc/intel_guc_submission.o \
gt/uc/intel_huc.o \
gt/uc/intel_huc_debugfs.o \
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 979128e28372..39bc3c16057b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -7,6 +7,7 @@
#include "gt/intel_gt_irq.h"
#include "gt/intel_gt_pm_irq.h"
#include "intel_guc.h"
+#include "intel_guc_slpc.h"
#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -157,6 +158,7 @@ void intel_guc_init_early(struct intel_guc *guc)
intel_guc_ct_init_early(>ct);
intel_guc_log_init_early(>log);
intel_guc_submission_init_early(guc);
+ intel_guc_slpc_init_early(>slpc);
mutex_init(>send_mutex);
spin_lock_init(>irq_lock);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index a9547069ee7e..15ad2eaee473 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -15,6 +15,7 @@
#include "intel_guc_ct.h"
#include "intel_guc_log.h"
#include "intel_guc_reg.h"
+#include "intel_guc_slpc_types.h"
#include "intel_uc_fw.h"
#include "i915_utils.h"
#include "i915_vma.h"
@@ -30,6 +31,7 @@ struct intel_guc {
struct intel_uc_fw fw;
struct intel_guc_log log;
struct intel_guc_ct ct;
+ struct intel_guc_slpc slpc;
/* Global engine used to submit requests to GuC */
struct i915_sched_engine *sched_engine;
@@ -57,6 +59,8 @@ struct intel_guc {
bool submission_supported;
bool submission_selected;
+ bool slpc_supported;
+ bool slpc_selected;
(I know that you were following existing code, but we might do better
and since you have to resend it anyway without patch 1/15 ...)
as we have here:
+ struct intel_guc_slpc slpc;
then maybe both supported/selected shall be moved there as:
struct intel_guc_slpc {
+ bool supported;
+ bool selected;
};
so the struct wont be empty any more, with that fixed:
Reviewed-by: Michal Wajdeczko
Ok, done,
Thanks for the review,
Vinay.
struct i915_vma *ads_vma;
struct __guc_ads_blob *ads_blob;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
new file mode 100644
index ..7275100ef8f8
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_guc_slpc.h"
+#include "gt/intel_gt.h"
+
+static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
+{
+ return container_of(slpc, struct intel_guc, slpc);
+}
+
+static bool __detect_slpc_supported(struct intel_guc *guc)
+{
+ /* GuC SLPC is unavailable for pre-Gen12 */
+ return guc->submission_supported &&
+ GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
+}
+
+static bool __guc_slpc_selected(struct intel_guc *guc)
+{
+ if
Re: [Intel-gfx] [PATCH 0/2] Add support for querying hw info that UMDs need
On 7/27/2021 02:49, Daniel Vetter wrote: On Mon, Jul 26, 2021 at 07:21:43PM -0700, john.c.harri...@intel.com wrote: From: John Harrison Various UMDs require hardware configuration information about the current platform. A bunch of static information is available in a fixed table that can be retrieved from the GuC. Test-with: 20210727002812.43469-2-john.c.harri...@intel.com UMD: https://github.com/intel/compute-runtime/pull/432/files Signed-off-by: John Harrison Can you pls submit this with all the usual suspect from the umd side (so also media-driver and mesa) cced? Do you have a list of names that you would like included? Also do the mesa/media-driver patches exist somewhere? Afaiui this isn't very useful without those bits in place too. I don't know about mesa but the media team have the support in place in their internal tree and (as per compute) are waiting for us to push the kernel side. This also comes under the headings of both new platforms and platforms which are POR for GuC submission. So I believe a lot of the UMD side changes for the config table are wrapped up in their support for the new platforms/GuC as a whole and thus not yet ready for upstream. John. -Daniel John Harrison (1): drm/i915/guc: Add fetch of hwconfig table Rodrigo Vivi (1): drm/i915/uapi: Add query for hwconfig table drivers/gpu/drm/i915/Makefile | 1 + .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 1 + .../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 4 + drivers/gpu/drm/i915/gt/uc/intel_guc.c| 3 +- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 + .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 156 ++ .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.h | 19 +++ drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 + drivers/gpu/drm/i915/i915_query.c | 23 +++ include/uapi/drm/i915_drm.h | 1 + 10 files changed, 215 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h -- 2.25.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 01/30] drm/i915/xehpsdv: Correct parameters for IS_XEHPSDV_GT_STEP()
On Tue, Jul 27, 2021 at 11:34:28AM -0700, Yokoyama, Caz wrote:
> On Fri, 2021-07-23 at 10:42 -0700, Matt Roper wrote:
> > During a rebase the parameters were partially renamed, but not
> > completely. Since the subsequent patches that start using this macro
> > haven't landed on an upstream tree yet this didn't cause a build
> > failure.
> >
> > Fixes: 086df54e20be ("drm/i915/xehpsdv: add initial XeHP SDV
> > definitions")
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index d118834a4ed9..d44d0050beec 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1562,8 +1562,8 @@ IS_SUBPLATFORM(const struct drm_i915_private
> > *i915,
> > (IS_ALDERLAKE_P(__i915) && \
> >IS_GT_STEP(__i915, since, until))
> >
> > -#define IS_XEHPSDV_GT_STEP(p, since, until) \
> > - (IS_XEHPSDV(p) && IS_GT_STEP(__i915, since, until))
> > +#define IS_XEHPSDV_GT_STEP(__i915, since, until) \
> > + (IS_XEHPSDV(__i915) && IS_GT_STEP(__i915, since, until))
> Is your comment saying that the first parameter
> of IS_XEHPSDV_GT_STEP(), p or __i915 must be the first parameter of
> both IS_XEHPSDV() and IS_GT_STEP()? The older code is a bug, correct?
> -caz
We can name the parameter anything we want, it just has to be used
consistently throughout the macro. Defining the parameter as 'p' but
then passing a different undefined name '__i915' into IS_GT_STEP won't
work (but it will only start causing compile errors when we land
workarounds and such that start using the macro).
Matt
>
> >
> > /*
> > * DG2 hardware steppings are a bit unusual. The hardware design
> > was forked
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 01/30] drm/i915/xehpsdv: Correct parameters for IS_XEHPSDV_GT_STEP()
On Fri, 2021-07-23 at 10:42 -0700, Matt Roper wrote:
> During a rebase the parameters were partially renamed, but not
> completely. Since the subsequent patches that start using this macro
> haven't landed on an upstream tree yet this didn't cause a build
> failure.
>
> Fixes: 086df54e20be ("drm/i915/xehpsdv: add initial XeHP SDV
> definitions")
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index d118834a4ed9..d44d0050beec 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1562,8 +1562,8 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
> (IS_ALDERLAKE_P(__i915) && \
>IS_GT_STEP(__i915, since, until))
>
> -#define IS_XEHPSDV_GT_STEP(p, since, until) \
> - (IS_XEHPSDV(p) && IS_GT_STEP(__i915, since, until))
> +#define IS_XEHPSDV_GT_STEP(__i915, since, until) \
> + (IS_XEHPSDV(__i915) && IS_GT_STEP(__i915, since, until))
Is your comment saying that the first parameter
of IS_XEHPSDV_GT_STEP(), p or __i915 must be the first parameter of
both IS_XEHPSDV() and IS_GT_STEP()? The older code is a bug, correct?
-caz
>
> /*
> * DG2 hardware steppings are a bit unusual. The hardware design
> was forked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 31/47] drm/i915/guc: Reset implementation for new GuC interface
On Tue, Jul 27, 2021 at 09:56:06AM +0100, Tvrtko Ursulin wrote:
>
> On 26/07/2021 23:48, Matthew Brost wrote:
> > On Thu, Jul 15, 2021 at 10:36:51AM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 24/06/2021 08:05, Matthew Brost wrote:
> > > > Reset implementation for new GuC interface. This is the legacy reset
> > > > implementation which is called when the i915 owns the engine hang check.
> > > > Future patches will offload the engine hang check to GuC but we will
> > > > continue to maintain this legacy path as a fallback and this code path
> > > > is also required if the GuC dies.
> > > >
> > > > With the new GuC interface it is not possible to reset individual
> > > > engines - it is only possible to reset the GPU entirely. This patch
> > > > forces an entire chip reset if any engine hangs.
> > >
> > > No updates after my review comments on 6th of May.
> > >
> > > At least:
> > >
> > > 1. wmb documentation
> > >
> >
> > Yea, missed this. Checkpatch yelled at me too. Will be fixed in next
> > rev.
> >
> > > 2. Spin lock cycling I either didn't understand or didn't buy the
> > > explanation. I don't remember seeing that pattern elsewhere in the driver
> > > -
> > > cycle a spinlock to make sure what was updated inside it is visible you
> > > said?
> > >
> >
> > I did respond - not really my fault if you don't understand a fairly
> > simple concept but I'll explain again.
> >
> > Change a variable
> > Cycle a lock
> > At this point we know anyone that acquires above lock the variable
> > change is visible.
> >
> > I can't be the first person in the Linux kernel to do this nor in the
> > i915.
>
> Don't know, did not do an exhaustive search. I can understand it being used
> to make sure any lock taking sections would exit, if they happened to be
> running simultaneously to the lock cycling code, but you seem to be
> describing it being used as a memory barrier.
>
> So either a code comment or just use a memory barrier is my ask. There is a
> requirement to comment memory barriers anyway so if this is effectively one
> of them it's pretty clear cut.
>
This more than a memory barrier, not just ensuring that variable change
is visible but any actions before the change was visible are complete.
> > This basically allows to seal all the reset races without a BKL.
> >
> > Also I told you I explain in this a doc patch that will get reposted
> > after GuC submission lands:
> > https://patchwork.freedesktop.org/patch/432408/?series=89844=1
> >
> > > 3. Dropping the lock protecting the list in the middle of
> > > list_for_each_entry_safe and just continuing to iterate like nothing
> > > happened. (__unwind_incomplete_requests) Again, perhaps I did not
> > > understand
> > > your explanation properly but you did appear to write:
> > >
> >
> > To be honest looking at the code now we likely don't need to drop the
> > look but regardless I don't think we should change this for the
> > following reasons.
>
> Then don't?
>
Ok, let me write this down and do this in an immediate follow up after
some thorough testing.
Matt
> > 1. I assure you this is safe and works. I can add a better comment
> > explaining this though.
>
> Yes please for a comment. Assurances are all good until a new bug is found.
>
> > 2. This is thoroughly tested and resets are the hardest thing to get
> > stable and working.
>
> Well new bugs are found even after statements of things being well tested so
> I'd err on the side of caution. And I don't mean your code here but as a
> general principle.
>
> > 3. This code is literally going to get deleted when we move to the DRM
> > scheduler as all the tracking / unwinding / resubmission will be in the
> > DRM scheduler core.
>
> Yeah, but if that cannot be guaranteed to happen in the same kernel release
> then lets not put dodgy code in.
>
> > 4. A 2 second search of the driver found that we do the same thing in
> > intel_gt_retire_requests_timeout so this isn't unprecedented.
>
> The code there is bit different. It uses list_safe_reset_next after
> re-acquiring the lock and only then unlinks the current element from the
> list.
>
> It all boils down to whether something can modify the list in parallel in
> your case. If it can't, just don't take the lock but instead put a comment
> saying why the lock does not need to be taken would be my suggestion. That
> way you avoid having to explain why the iteration is not broken.
>
> Regards,
>
> Tvrtko
>
> >
> > Matt
> >
> > > """
> > > We only need the active lock for ce->guc_active.requests list. It is
> > > indeed safe to drop the lock.
> > > """
> > >
> > > + spin_lock(>guc_active.lock);
> > > + list_for_each_entry_safe(rq, rn,
> > > + >guc_active.requests,
> > > + sched.link) {
> > > + if (i915_request_completed(rq))
> > > + continue;
> > > +
> > > + list_del_init(>sched.link);
> > > + spin_unlock(>guc_active.lock);
> > > ...
> > >
Re: [Intel-gfx] [PATCH v2 11/11] drm/i915: Extract i915_module.c
On Tue, Jul 27, 2021 at 9:44 AM Tvrtko Ursulin
wrote:
>
>
> On 27/07/2021 13:10, Daniel Vetter wrote:
> > The module init code is somewhat misplaced in i915_pci.c, since it
> > needs to pull in init/exit functions from every part of the driver and
> > pollutes the include list a lot.
> >
> > Extract an i915_module.c file which pulls all the bits together, and
> > allows us to massively trim the include list of i915_pci.c.
> >
> > The downside is that have to drop the error path check Jason added to
> > catch when we set up the pci driver too early. I think that risk is
> > acceptable for this pretty nice include.
>
> i915_module.c is an improvement and the rest for me is not extremely
> objectionable by the end of this incarnation, but I also do not see it
> as an improvement really.
It's not a big improvement to be sure, but I think there are a few
ways this is nicer:
1. One less level of indirection to sort through.
2. The init/exit table is generally simpler than the i915_global interface.
3. It's easy to forget i915_global_register but forgetting to put an
_exit function in the module init table is a lot more obvious.
None of those are deal-breakers but they're kind-of nice. Anyway,
this one is also
Reviewed-by: Jason Ekstrand
--Jason
> There was a bug to fix relating to mock tests, but that is where the
> exercise should have stopped for now. After that it IMHO spiraled out of
> control, not least the unjustifiably expedited removal of cache
> shrinking. On balance for me it is too churny and boils down to two
> extremely capable people spending time on kind of really unimportant
> side fiddles. And I do not intend to prescribe you what to do, just
> expressing my bewilderment. FWIW... I can only say my opinion as it, not
> that it matters a lot.
>
> Regards,
>
> Tvrtko
>
> > Cc: Jason Ekstrand
> > Cc: Tvrtko Ursulin
> > Signed-off-by: Daniel Vetter
> > ---
> > drivers/gpu/drm/i915/Makefile | 1 +
> > drivers/gpu/drm/i915/i915_module.c | 113
> > drivers/gpu/drm/i915/i915_pci.c| 117 +
> > drivers/gpu/drm/i915/i915_pci.h| 8 ++
> > 4 files changed, 125 insertions(+), 114 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/i915_module.c
> > create mode 100644 drivers/gpu/drm/i915/i915_pci.h
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > index 9022dc638ed6..4ebd9f417ddb 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -38,6 +38,7 @@ i915-y += i915_drv.o \
> > i915_irq.o \
> > i915_getparam.o \
> > i915_mitigations.o \
> > + i915_module.o \
> > i915_params.o \
> > i915_pci.o \
> > i915_scatterlist.o \
> > diff --git a/drivers/gpu/drm/i915/i915_module.c
> > b/drivers/gpu/drm/i915/i915_module.c
> > new file mode 100644
> > index ..c578ea8f56a0
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/i915_module.c
> > @@ -0,0 +1,113 @@
> > +/*
> > + * SPDX-License-Identifier: MIT
> > + *
> > + * Copyright © 2021 Intel Corporation
> > + */
> > +
> > +#include
> > +
> > +#include "gem/i915_gem_context.h"
> > +#include "gem/i915_gem_object.h"
> > +#include "i915_active.h"
> > +#include "i915_buddy.h"
> > +#include "i915_params.h"
> > +#include "i915_pci.h"
> > +#include "i915_perf.h"
> > +#include "i915_request.h"
> > +#include "i915_scheduler.h"
> > +#include "i915_selftest.h"
> > +#include "i915_vma.h"
> > +
> > +static int i915_check_nomodeset(void)
> > +{
> > + bool use_kms = true;
> > +
> > + /*
> > + * Enable KMS by default, unless explicitly overriden by
> > + * either the i915.modeset prarameter or by the
> > + * vga_text_mode_force boot option.
> > + */
> > +
> > + if (i915_modparams.modeset == 0)
> > + use_kms = false;
> > +
> > + if (vgacon_text_force() && i915_modparams.modeset == -1)
> > + use_kms = false;
> > +
> > + if (!use_kms) {
> > + /* Silently fail loading to not upset userspace. */
> > + DRM_DEBUG_DRIVER("KMS disabled.\n");
> > + return 1;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static const struct {
> > + int (*init)(void);
> > + void (*exit)(void);
> > +} init_funcs[] = {
> > + { i915_check_nomodeset, NULL },
> > + { i915_active_module_init, i915_active_module_exit },
> > + { i915_buddy_module_init, i915_buddy_module_exit },
> > + { i915_context_module_init, i915_context_module_exit },
> > + { i915_gem_context_module_init, i915_gem_context_module_exit },
> > + { i915_objects_module_init, i915_objects_module_exit },
> > + { i915_request_module_init, i915_request_module_exit },
> > + { i915_scheduler_module_init, i915_scheduler_module_exit },
> > + { i915_vma_module_init, i915_vma_module_exit },
> > + { i915_mock_selftests, NULL },
> > + { i915_pmu_init, i915_pmu_exit },
> > + {
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,01/28] drm/i915/display: remove PORT_F workaround for CNL (rev2)
== Series Details ==
Series: series starting with [CI,01/28] drm/i915/display: remove PORT_F
workaround for CNL (rev2)
URL : https://patchwork.freedesktop.org/series/93056/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10405 -> Patchwork_20719
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/index.html
Known issues
Here are the changes found in Patchwork_20719 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +25 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: NOTRUN -> [WARN][2] ([i915#3718])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html
* igt@i915_pm_rpm@basic-rte:
- fi-bdw-5557u: NOTRUN -> [FAIL][3] ([i915#579])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/fi-bdw-5557u/igt@i915_pm_...@basic-rte.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][4] ([i915#1888]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@migrate:
- {fi-hsw-gt1}: [FAIL][6] -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/fi-hsw-gt1/igt@i915_selftest@l...@migrate.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/fi-hsw-gt1/igt@i915_selftest@l...@migrate.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][8] ([i915#1372]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20719/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Participating hosts (41 -> 35)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-bdw-samus
bat-jsl-1
Build changes
-
* Linux: CI_DRM_10405 -> Patchwork_20719
CI-20190529: 20190529
CI_DRM_10405: 6db19b5e1fac016d9dffa6ce54aa21f3200c5c8d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6153: a5dffe7499a2f7189718ddf1ccf49060b7c1529d @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20719: 780f9f17ba298db69780500fda0bdd7b38255a92 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
780f9f17ba29 drm/i915: switch num_scalers/num_sprites to consider DISPLAY_VER
0b043f4ac3d8 drm/i915: replace random CNL comments
cd928dae0d3e drm/i915: rename/remove CNL registers
4ba93d420a70 drm/i915: remove GRAPHICS_VER == 10
4e912a6452e0 drm/i915: finish removal of CNL
7aa7558721aa drm/i915/gt: rename CNL references in intel_engine.h
6de7ed1a59e6 drm/i915: rename CNL references in intel_dram.c
80d677c2345f drm/i915/gt: remove explicit CNL handling from intel_sseu.c
393456abc7be drm/i915: remove explicit CNL handling from intel_wopcm.c
f586bf32e6ff drm/i915: remove explicit CNL handling from intel_pch.c
e17f59582390 drm/i915: remove explicit CNL handling from intel_mocs.c
1a5d634b421c drm/i915: remove explicit CNL handling from intel_pm.c
a1a4e070f933 drm/i915: remove explicit CNL handling from i915_irq.c
a81e83af78c5 drm/i915/display: rename CNL references in skl_scaler.c
8ae2070a04a2 drm/i915/display: remove CNL ddi buf translation tables
b52e50d278b9 drm/i915/display: remove explicit CNL handling from
intel_display_power.c
302231afebdf drm/i915/display: remove explicit CNL handling from
skl_universal_plane.c
02aea789a348 drm/i915/display: remove explicit CNL handling from intel_vdsc.c
1552f5470753 drm/i915/display: remove explicit CNL handling from
intel_dpll_mgr.c
0933019dde76 drm/i915/display: remove explicit CNL handling from intel_dp.c
9edcd79df25c drm/i915/display: remove explicit CNL handling from intel_dmc.c
58f0263bf79d drm/i915/display: remove explicit CNL handling from
[Intel-gfx] [PATCH i-g-t 0/1] Fix gem_scheduler.manycontexts for GuC submission
Patch should explain it all. Will include in [1] when that series is respun. Signed-off-by: Matthew Brost [1] https://patchwork.freedesktop.org/series/93071/ Matthew Brost (1): i915/gem_scheduler: Ensure submission order in manycontexts tests/i915/gem_exec_schedule.c | 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) -- 2.28.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/1] i915/gem_scheduler: Ensure submission order in manycontexts
With GuC submission contexts can get reordered (compared to submission
order), if contexts get reordered the sequential nature of the batches
releasing the next batch's semaphore in function timesliceN() get broken
resulting in the test taking much longer than if should. e.g. Every
contexts needs to be timesliced to release the next batch. Corking the
first submission until all the batches have been submitted should ensure
submission order.
Signed-off-by: Matthew Brost
---
tests/i915/gem_exec_schedule.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index f03842478..41f2591a5 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -597,12 +597,13 @@ static void timesliceN(int i915, const intel_ctx_cfg_t
*cfg,
struct drm_i915_gem_execbuffer2 execbuf = {
.buffers_ptr = to_user_pointer(),
.buffer_count = 1,
- .flags = engine | I915_EXEC_FENCE_OUT,
+ .flags = engine | I915_EXEC_FENCE_OUT | I915_EXEC_FENCE_SUBMIT,
};
uint32_t *result =
gem_mmap__device_coherent(i915, obj.handle, 0, sz, PROT_READ);
const intel_ctx_t *ctx;
int fence[count];
+ IGT_CORK_FENCE(cork);
/*
* Create a pair of interlocking batches, that ping pong
@@ -614,6 +615,17 @@ static void timesliceN(int i915, const intel_ctx_cfg_t
*cfg,
igt_require(gem_scheduler_has_timeslicing(i915));
igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8);
+ /*
+* With GuC submission contexts can get reordered (compared to
+* submission order), if contexts get reordered the sequential
+* nature of the batches releasing the next batch's semaphore gets
+* broken resulting in the test taking much longer than it should (e.g.
+* every context needs to be timesliced to release the next batch).
+* Corking the first submission until all batches have been
+* submitted should ensure submission order.
+*/
+ execbuf.rsvd2 = igt_cork_plug(, i915);
+
/* No coupling between requests; free to timeslice */
for (int i = 0; i < count; i++) {
@@ -624,8 +636,10 @@ static void timesliceN(int i915, const intel_ctx_cfg_t
*cfg,
intel_ctx_destroy(i915, ctx);
fence[i] = execbuf.rsvd2 >> 32;
+ execbuf.rsvd2 >>= 32;
}
+ igt_cork_unplug();
gem_sync(i915, obj.handle);
gem_close(i915, obj.handle);
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,01/28] drm/i915/display: remove PORT_F workaround for CNL (rev2)
== Series Details == Series: series starting with [CI,01/28] drm/i915/display: remove PORT_F workaround for CNL (rev2) URL : https://patchwork.freedesktop.org/series/93056/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1900:21:expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1900:21:got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1900:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_context.c:1413:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1413:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1413:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:expected struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:got struct i915_address_space * +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1402:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1210:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/28] drm/i915/display: remove PORT_F workaround for CNL (rev2)
== Series Details == Series: series starting with [CI,01/28] drm/i915/display: remove PORT_F workaround for CNL (rev2) URL : https://patchwork.freedesktop.org/series/93056/ State : warning == Summary == $ dim checkpatch origin/drm-tip a5e4bffd6d6f drm/i915/display: remove PORT_F workaround for CNL 00ffd16fcca9 drm/i915/display: remove explicit CNL handling from intel_cdclk.c f0962a46c4db drm/i915/display: remove explicit CNL handling from intel_color.c 9cef952bf781 drm/i915/display: remove explicit CNL handling from intel_combo_phy.c b0b88d826064 drm/i915/display: remove explicit CNL handling from intel_crtc.c e2ad5114dd83 drm/i915/display: remove explicit CNL handling from intel_ddi.c 58f0263bf79d drm/i915/display: remove explicit CNL handling from intel_display_debugfs.c 9edcd79df25c drm/i915/display: remove explicit CNL handling from intel_dmc.c 0933019dde76 drm/i915/display: remove explicit CNL handling from intel_dp.c 1552f5470753 drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.c 02aea789a348 drm/i915/display: remove explicit CNL handling from intel_vdsc.c 302231afebdf drm/i915/display: remove explicit CNL handling from skl_universal_plane.c b52e50d278b9 drm/i915/display: remove explicit CNL handling from intel_display_power.c 8ae2070a04a2 drm/i915/display: remove CNL ddi buf translation tables a81e83af78c5 drm/i915/display: rename CNL references in skl_scaler.c -:63: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id' - possible side-effects? #63: FILE: drivers/gpu/drm/i915/i915_reg.h:7752: +#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe,\ _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) -:63: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'set' - possible side-effects? #63: FILE: drivers/gpu/drm/i915/i915_reg.h:7752: +#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe,\ _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) -:68: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id' - possible side-effects? #68: FILE: drivers/gpu/drm/i915/i915_reg.h:7756: +#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) -:68: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'set' - possible side-effects? #68: FILE: drivers/gpu/drm/i915/i915_reg.h:7756: +#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) total: 0 errors, 0 warnings, 4 checks, 48 lines checked a1a4e070f933 drm/i915: remove explicit CNL handling from i915_irq.c 1a5d634b421c drm/i915: remove explicit CNL handling from intel_pm.c e17f59582390 drm/i915: remove explicit CNL handling from intel_mocs.c f586bf32e6ff drm/i915: remove explicit CNL handling from intel_pch.c 393456abc7be drm/i915: remove explicit CNL handling from intel_wopcm.c 80d677c2345f drm/i915/gt: remove explicit CNL handling from intel_sseu.c 6de7ed1a59e6 drm/i915: rename CNL references in intel_dram.c 7aa7558721aa drm/i915/gt: rename CNL references in intel_engine.h 4e912a6452e0 drm/i915: finish removal of CNL 4ba93d420a70 drm/i915: remove GRAPHICS_VER == 10 -:348: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #348: FILE: drivers/gpu/drm/i915/i915_drv.h:1650: +#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \ IS_GEMINILAKE(dev_priv) || \ IS_KABYLAKE(dev_priv)) total: 0 errors, 0 warnings, 1 checks, 336 lines checked cd928dae0d3e drm/i915: rename/remove CNL registers 0b043f4ac3d8 drm/i915: replace random CNL comments 780f9f17ba29 drm/i915: switch num_scalers/num_sprites to consider DISPLAY_VER -:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #12: v3 (Lucas): Change check to DISPLAY_VER >= 9, to cover the GLK's num_scalers, total: 0 errors, 1 warnings, 0 checks, 32 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adl_p: Allow underrun recovery when possible (rev2)
== Series Details ==
Series: drm/i915/adl_p: Allow underrun recovery when possible (rev2)
URL : https://patchwork.freedesktop.org/series/93054/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10405 -> Patchwork_20717
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/index.html
Known issues
Here are the changes found in Patchwork_20717 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +25 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: NOTRUN -> [WARN][2] ([i915#3718])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html
* igt@i915_pm_rpm@basic-rte:
- fi-bdw-5557u: NOTRUN -> [FAIL][3] ([i915#579])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/fi-bdw-5557u/igt@i915_pm_...@basic-rte.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][4] ([i915#1888]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@migrate:
- {fi-hsw-gt1}: [FAIL][6] -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/fi-hsw-gt1/igt@i915_selftest@l...@migrate.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/fi-hsw-gt1/igt@i915_selftest@l...@migrate.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][8] ([i915#1372]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10405/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Participating hosts (41 -> 35)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-bdw-samus
bat-jsl-1
Build changes
-
* Linux: CI_DRM_10405 -> Patchwork_20717
CI-20190529: 20190529
CI_DRM_10405: 6db19b5e1fac016d9dffa6ce54aa21f3200c5c8d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6153: a5dffe7499a2f7189718ddf1ccf49060b7c1529d @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20717: ae83e93206ad984459bc6336d3f43fb06eab11b3 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ae83e93206ad drm/i915/adl_p: Allow underrun recovery when possible
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20717/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm, drm/vmwgfx: fixes and updates related to drm_master (rev2)
== Series Details ==
Series: drm, drm/vmwgfx: fixes and updates related to drm_master (rev2)
URL : https://patchwork.freedesktop.org/series/92894/
State : failure
== Summary ==
CC arch/x86/kernel/asm-offsets.s
In file included from ./arch/x86/include/asm/bug.h:84,
from ./include/linux/bug.h:5,
from ./include/linux/crypto.h:18,
from arch/x86/kernel/asm-offsets.c:9:
./include/linux/ww_mutex.h: In function ‘ww_acquire_done’:
./include/linux/lockdep.h:316:39: error: ‘LOCK_STAT_NOT_HELD’ undeclared (first
use in this function); did you mean ‘LOCK_STATE_NOT_HELD’?
lockdep_assert(lockdep_is_held(l) != LOCK_STAT_NOT_HELD)
^~
./include/asm-generic/bug.h:121:25: note: in definition of macro ‘WARN_ON’
int __ret_warn_on = !!(condition);\
^
./include/linux/lockdep.h:316:2: note: in expansion of macro ‘lockdep_assert’
lockdep_assert(lockdep_is_held(l) != LOCK_STAT_NOT_HELD)
^~
./include/linux/ww_mutex.h:147:2: note: in expansion of macro
‘lockdep_assert_held’
lockdep_assert_held(ctx);
^~~
./include/linux/lockdep.h:316:39: note: each undeclared identifier is reported
only once for each function it appears in
lockdep_assert(lockdep_is_held(l) != LOCK_STAT_NOT_HELD)
^~
./include/asm-generic/bug.h:121:25: note: in definition of macro ‘WARN_ON’
int __ret_warn_on = !!(condition);\
^
./include/linux/lockdep.h:316:2: note: in expansion of macro ‘lockdep_assert’
lockdep_assert(lockdep_is_held(l) != LOCK_STAT_NOT_HELD)
^~
./include/linux/ww_mutex.h:147:2: note: in expansion of macro
‘lockdep_assert_held’
lockdep_assert_held(ctx);
^~~
In file included from ./include/linux/mmzone.h:16,
from ./include/linux/gfp.h:6,
from ./include/linux/slab.h:15,
from ./include/linux/crypto.h:20,
from arch/x86/kernel/asm-offsets.c:9:
./include/linux/seqlock.h: In function ‘__seqprop_raw_spinlock_assert’:
./include/linux/lockdep.h:316:39: error: ‘LOCK_STAT_NOT_HELD’ undeclared (first
use in this function); did you mean ‘LOCK_STATE_NOT_HELD’?
lockdep_assert(lockdep_is_held(l) != LOCK_STAT_NOT_HELD)
^~
./include/linux/seqlock.h:152:26: note: in definition of macro ‘__SEQ_LOCK’
#define __SEQ_LOCK(expr) expr
^~~~
./include/linux/lockdep.h:310:7: note: in expansion of macro ‘WARN_ON’
do { WARN_ON(debug_locks && !(cond)); } while (0)
^~~
./include/linux/lockdep.h:316:2: note: in expansion of macro ‘lockdep_assert’
lockdep_assert(lockdep_is_held(l) != LOCK_STAT_NOT_HELD)
^~
./include/linux/seqlock.h:247:13: note: in expansion of macro
‘lockdep_assert_held’
__SEQ_LOCK(lockdep_assert_held(lockmember)); \
^~~
./include/linux/seqlock.h:276:1: note: in expansion of macro ‘SEQCOUNT_LOCKNAME’
SEQCOUNT_LOCKNAME(raw_spinlock, raw_spinlock_t, false,s->lock,
raw_spin, raw_spin_lock(s->lock))
^
./include/linux/seqlock.h: In function ‘__seqprop_spinlock_assert’:
./include/linux/lockdep.h:316:39: error: ‘LOCK_STAT_NOT_HELD’ undeclared (first
use in this function); did you mean ‘LOCK_STATE_NOT_HELD’?
lockdep_assert(lockdep_is_held(l) != LOCK_STAT_NOT_HELD)
^~
./include/linux/seqlock.h:152:26: note: in definition of macro ‘__SEQ_LOCK’
#define __SEQ_LOCK(expr) expr
^~~~
./include/linux/lockdep.h:310:7: note: in expansion of macro ‘WARN_ON’
do { WARN_ON(debug_locks && !(cond)); } while (0)
^~~
./include/linux/lockdep.h:316:2: note: in expansion of macro ‘lockdep_assert’
lockdep_assert(lockdep_is_held(l) != LOCK_STAT_NOT_HELD)
^~
./include/linux/seqlock.h:247:13: note: in expansion of macro
‘lockdep_assert_held’
__SEQ_LOCK(lockdep_assert_held(lockmember)); \
^~~
./include/linux/seqlock.h:277:1: note: in expansion of macro ‘SEQCOUNT_LOCKNAME’
SEQCOUNT_LOCKNAME(spinlock, spinlock_t, __SEQ_RT, s->lock,
spin, spin_lock(s->lock))
^
./include/linux/seqlock.h: In function ‘__seqprop_rwlock_assert’:
./include/linux/lockdep.h:316:39: error: ‘LOCK_STAT_NOT_HELD’ undeclared (first
use in this function); did you mean ‘LOCK_STATE_NOT_HELD’?
lockdep_assert(lockdep_is_held(l) != LOCK_STAT_NOT_HELD)
^~
./include/linux/seqlock.h:152:26: note: in definition of macro ‘__SEQ_LOCK’
#define __SEQ_LOCK(expr) expr
^~~~
./include/linux/lockdep.h:310:7: note: in expansion of macro ‘WARN_ON’
do { WARN_ON(debug_locks && !(cond)); } while (0)
^~~
[Intel-gfx] [PATCH 1/1] drm/i915: dgfx cards need to wait on pcode's uncore init done
From: Badal Nilawar
In discrete cards, the graphics driver shouldn't proceed with the probe
or resume unless PCODE indicated everything is done, including memory
training and gt bring up.
For this reason, the driver probe and resume paths needs to be blocked
until PCODE indicates it is done. Also, it needs to aborted if the
notification never arrives.
In general, the few miliseconds would be enough and the regular PCODE
recommendation for the timeout was 10 seconds. However there are some
rare cases where this initialization can take up to 1 minute. So,
PCODE has increased the recommendation to 3 minutes so we don't fully
block the device utilization when something just got delayed for
whatever reason. To be on the safest side, let's accept this
recommendation, since on the regular case it won't delay or block the
driver initialization and resume flows
Cc: Rodrigo Vivi
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/i915_drv.c | 8 +++-
drivers/gpu/drm/i915/intel_sideband.c | 13 +
drivers/gpu/drm/i915/intel_sideband.h | 2 +-
3 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c43b698bf0b97..59fb4c710c8ca 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -620,7 +620,9 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
intel_opregion_setup(dev_priv);
- intel_pcode_init(dev_priv);
+ ret = intel_pcode_init(dev_priv);
+ if (ret)
+ goto err_msi;
/*
* Fill the dram structure to get the system dram info. This will be
@@ -1231,6 +1233,10 @@ static int i915_drm_resume(struct drm_device *dev)
disable_rpm_wakeref_asserts(_priv->runtime_pm);
+ ret = intel_pcode_init(dev_priv);
+ if (ret)
+ return ret;
+
sanitize_gpu(dev_priv);
ret = i915_ggtt_enable_hw(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sideband.c
b/drivers/gpu/drm/i915/intel_sideband.c
index f0a82b37bd1ac..e304bf44e1ff8 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -556,17 +556,22 @@ int skl_pcode_request(struct drm_i915_private *i915, u32
mbox, u32 request,
#undef COND
}
-void intel_pcode_init(struct drm_i915_private *i915)
+int intel_pcode_init(struct drm_i915_private *i915)
{
- int ret;
+ int ret = 0;
if (!IS_DGFX(i915))
- return;
+ return ret;
ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
DG1_UNCORE_GET_INIT_STATUS,
DG1_UNCORE_INIT_STATUS_COMPLETE,
- DG1_UNCORE_INIT_STATUS_COMPLETE, 50);
+ DG1_UNCORE_INIT_STATUS_COMPLETE, 18);
+
+ drm_dbg(>drm, "PCODE init status %d\n", ret);
+
if (ret)
drm_err(>drm, "Pcode did not report uncore initialization
completion!\n");
+
+ return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_sideband.h
b/drivers/gpu/drm/i915/intel_sideband.h
index 094c7b19c5d42..d1d14bcb8f56e 100644
--- a/drivers/gpu/drm/i915/intel_sideband.h
+++ b/drivers/gpu/drm/i915/intel_sideband.h
@@ -138,6 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private
*i915, u32 mbox,
int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
-void intel_pcode_init(struct drm_i915_private *i915);
+int intel_pcode_init(struct drm_i915_private *i915);
#endif /* _INTEL_SIDEBAND_H */
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/adlp: Add workaround to disable CMTG clock gating
On Tue, 2021-07-27 at 16:44 +0300, Imre Deak wrote:
> The driver doesn't depend atm on the common mode timing generator
> functionality (it would be used for some power saving feature and panel
> timing synchronization), however DMC will corrupt the CMTG registers
> across DC5 entry/exit sequences unless the CMTG clock gating is
> disabled. This in turn can lead to at least the DPLL0/1 configuration
> getting stuck at their last state, which means we can't reprogram them
> to a new config.
>
> Add the corresponding Bspec workaround to prevent the above.
>
> Cc: Uma Shankar
> Cc: José Roberto de Souza
> Cc: Anshuman Gupta
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 18 ++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index bb0aebcc3ecd3..474d723a37454 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13198,6 +13198,24 @@ static void intel_early_display_was(struct
> drm_i915_private *dev_priv)
>KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
>KBL_ARB_FILL_SPARE_14);
> }
> +
> + if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> + uint32_t val;
Fixing style errors pointed by bot.
Reviewed-by: José Roberto de Souza
> +
> + /*
> + * Wa_16011069516:adl-p[a0]
> + *
> + * All CMTG regs are unreliable until CMTG clock gating is
> + * disabled, so we can only assume the default CMTG_CHICKEN
> + * reg value and sanity check this assumption with a double
> + * read, which presumably returns the correct value even with
> + * clock gating on.
> + */
> + val = intel_de_read(dev_priv, TRANS_CMTG_CHICKEN);
> + val = intel_de_read(dev_priv, TRANS_CMTG_CHICKEN);
> + intel_de_write(dev_priv, TRANS_CMTG_CHICKEN,
> DISABLE_DPT_CLK_GATING);
> + drm_WARN_ON(_priv->drm, val &~ DISABLE_DPT_CLK_GATING);
> + }
> }
>
> static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c41f9083e2338..e02bd75dd1064 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10208,6 +10208,9 @@ enum skl_power_gate {
> #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
> #define PORT_SYNC_MODE_MASTER_SELECT(x)
> REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
>
> +#define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
> +#define DISABLE_DPT_CLK_GATING REG_BIT(1)
> +
> /* DisplayPort Transport Control */
> #define _DP_TP_CTL_A 0x64040
> #define _DP_TP_CTL_B 0x64140
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/15] drm/i915/guc/slpc: Sysfs hooks for SLPC
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Update the get/set min/max freq hooks to work for
> SLPC case as well. Consolidate helpers for requested/min/max
> frequency get/set to intel_rps where the proper action can
> be taken depending on whether SLPC is enabled.
>
> v2: Add wrappers for getting rp0/1/n frequencies, update
> softlimits in set min/max SLPC functions. Also check for
> boundary conditions before setting them.
>
> v3: Address review comments (Michal W)
>
> Acked-by: Michal Wajdeczko
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Sujaritha Sundaresan
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 165
> drivers/gpu/drm/i915/gt/intel_rps.h | 11 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 14 ++
> drivers/gpu/drm/i915/i915_pmu.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/i915/i915_sysfs.c | 77 ++---
> 6 files changed, 207 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index e858eeb2c59d..48d4147165a9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps
> *rps)
> return rps_to_gt(rps)->uncore;
> }
>
> +static struct intel_guc_slpc *rps_to_slpc(struct intel_rps *rps)
> +{
> + struct intel_gt *gt = rps_to_gt(rps);
> +
> + return >uc.guc.slpc;
> +}
> +
> static bool rps_uses_slpc(struct intel_rps *rps)
> {
> struct intel_gt *gt = rps_to_gt(rps);
> @@ -1960,6 +1967,164 @@ u32 intel_rps_read_actual_frequency(struct intel_rps
> *rps)
> return freq;
> }
>
> +u32 intel_rps_read_punit_req(struct intel_rps *rps)
> +{
> + struct intel_uncore *uncore = rps_to_uncore(rps);
> +
> + return intel_uncore_read(uncore, GEN6_RPNSWREQ);
> +}
> +
> +u32 intel_rps_get_req(struct intel_rps *rps, u32 pureq)
hmm, "rps" looks to be not needed here
btw, shouldn't this function be static ?
> +{
> + u32 req = pureq >> GEN9_SW_REQ_UNSLICE_RATIO_SHIFT;
> +
> + return req;
> +}
> +
> +u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps)
> +{
> + u32 freq = intel_rps_get_req(rps, intel_rps_read_punit_req(rps));
> +
> + return intel_gpu_freq(rps, freq);
> +}
> +
> +u32 intel_rps_get_requested_frequency(struct intel_rps *rps)
> +{
> + if (rps_uses_slpc(rps))
> + return intel_rps_read_punit_req_frequency(rps);
> + else
> + return intel_gpu_freq(rps, rps->cur_freq);
> +}
> +
> +u32 intel_rps_get_max_frequency(struct intel_rps *rps)
> +{
> + struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> +
> + if (rps_uses_slpc(rps))
> + return slpc->max_freq_softlimit;
> + else
> + return intel_gpu_freq(rps, rps->max_freq_softlimit);
> +}
> +
> +u32 intel_rps_get_rp0_frequency(struct intel_rps *rps)
> +{
> + struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> +
> + if (rps_uses_slpc(rps))
> + return slpc->rp0_freq;
> + else
> + return intel_gpu_freq(rps, rps->rp0_freq);
> +}
> +
> +u32 intel_rps_get_rp1_frequency(struct intel_rps *rps)
> +{
> + struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> +
> + if (rps_uses_slpc(rps))
> + return slpc->rp1_freq;
> + else
> + return intel_gpu_freq(rps, rps->rp1_freq);
> +}
> +
> +u32 intel_rps_get_rpn_frequency(struct intel_rps *rps)
> +{
> + struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> +
> + if (rps_uses_slpc(rps))
> + return slpc->min_freq;
> + else
> + return intel_gpu_freq(rps, rps->min_freq);
> +}
> +
> +int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val)
> +{
> + struct drm_i915_private *i915 = rps_to_i915(rps);
> + struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> + int ret = 0;
> +
> + if (rps_uses_slpc(rps))
> + return intel_guc_slpc_set_max_freq(slpc, val);
few above functions are implemented as nice dispatcher
if (rps_uses_slpc(rps))
return ... slpc stuff;
else
return ... gpu stuff;
can we have something similar here ?
likely just putting below code into helper will do the trick
> +
> + mutex_lock(>lock);
> +
> + val = intel_freq_opcode(rps, val);
> + if (val < rps->min_freq ||
> + val > rps->max_freq ||
> + val < rps->min_freq_softlimit) {
> + ret = -EINVAL;
> + goto unlock;
> + }
> +
> + if (val > rps->rp0_freq)
> + drm_dbg(>drm, "User requested overclocking to %d\n",
> + intel_gpu_freq(rps, val));
> +
> + rps->max_freq_softlimit = val;
> +
> + val = clamp_t(int, rps->cur_freq,
> + rps->min_freq_softlimit,
> + rps->max_freq_softlimit);
> +
> + /*
> + * We
[Intel-gfx] [PATCH v2.1] drm/i915: switch num_scalers/num_sprites to consider DISPLAY_VER
The numbers of scalers and sprites depend on the display version, so use
it instead of GRAPHICS_VER. We were mixing both, which let me confused
while removing CNL and GRAPHICS_VER == 10.
v2 (Rodrigo): Switch IS_GEMINILAKE to DISPLAY_VER == 10
v3 (Lucas): Change check to DISPLAY_VER >= 9, to cover the GLK's num_scalers,
otherwise it remains set to 0.
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_device_info.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index ffe3b5d89a63..305facedd284 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -265,10 +265,10 @@ void intel_device_info_runtime_init(struct
drm_i915_private *dev_priv)
if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
for_each_pipe(dev_priv, pipe)
runtime->num_scalers[pipe] = 0;
- else if (GRAPHICS_VER(dev_priv) >= 11) {
+ else if (DISPLAY_VER(dev_priv) >= 11) {
for_each_pipe(dev_priv, pipe)
runtime->num_scalers[pipe] = 2;
- } else if (GRAPHICS_VER(dev_priv) == 9) {
+ } else if (DISPLAY_VER(dev_priv) >= 9) {
runtime->num_scalers[PIPE_A] = 2;
runtime->num_scalers[PIPE_B] = 2;
runtime->num_scalers[PIPE_C] = 1;
@@ -279,10 +279,10 @@ void intel_device_info_runtime_init(struct
drm_i915_private *dev_priv)
if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 4;
- else if (GRAPHICS_VER(dev_priv) >= 11)
+ else if (DISPLAY_VER(dev_priv) >= 11)
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 6;
- else if (IS_GEMINILAKE(dev_priv))
+ else if (DISPLAY_VER(dev_priv) == 10)
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 3;
else if (IS_BROXTON(dev_priv)) {
@@ -301,7 +301,7 @@ void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv)
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 2;
- } else if (GRAPHICS_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
+ } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 1;
}
--
2.31.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 15/15] drm/i915/guc/rc: Setup and enable GUCRC feature
On 7/27/2021 8:37 AM, Matt Roper wrote:
On Mon, Jul 26, 2021 at 12:08:00PM -0700, Vinay Belgaumkar wrote:
This feature hands over the control of HW RC6 to the GuC.
GuC decides when to put HW into RC6 based on it's internal
busyness algorithms.
GUCRC needs GuC submission to be enabled, and only
supported on Gen12+ for now.
When GUCRC is enabled, do not set HW RC6. Use a H2G message
to tell GuC to enable GUCRC. When disabling RC6, tell GuC to
revert RC6 control back to KMD.
v2: Address comments (Michal W)
Reviewed-by: Michal Wajdeczko
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_rc6.c | 22 +++--
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 6 ++
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 +
drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 80 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h | 31 +++
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 +
8 files changed, 140 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d8eac4468df9..3fc17f20d88e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \
gt/uc/intel_guc_fw.o \
gt/uc/intel_guc_log.o \
gt/uc/intel_guc_log_debugfs.o \
+ gt/uc/intel_guc_rc.o \
gt/uc/intel_guc_slpc.o \
gt/uc/intel_guc_submission.o \
gt/uc/intel_huc.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 259d7eb4e165..299fcf10b04b 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -98,11 +98,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
Do steps 2b and 2c above this still apply to gucrc? Are those still
controlling the behavior of gucrc or does the GuC firmware just
overwrite them with its own values? If they're still impacting the
behavior when gucrc is enabled, is there any updated guidance on how the
values should be set? It seems that there isn't any guidance in the
bspec for the last several platforms, so we've pretty much been re-using
old values without knowing if there's additional adjustment that should
be done for the newer platforms.
If the tuning values the driver sets get ignored/overwritten during GuC
operation, maybe we should add a new gucrc_rc6_enable() that gets used
instead of gen11_rc6_enable() and drops the unnecessary steps to help
clarify what's truly important?
Yeah, 2b does get overwritten by guc, but we still need 2c.
- /* 3a: Enable RC6 */
- rc6->ctl_enable =
- GEN6_RC_CTL_HW_ENABLE |
- GEN6_RC_CTL_RC6_ENABLE |
- GEN6_RC_CTL_EI_MODE(1);
+ /* 3a: Enable RC6
+*
+* With GUCRC, we do not enable bit 31 of RC_CTL,
+* thus allowing GuC to control RC6 entry/exit fully instead.
+* We will not set the HW ENABLE and EI bits
+*/
+ if (!intel_guc_rc_enable(>uc.guc))
+ rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE;
+ else
+ rc6->ctl_enable =
+ GEN6_RC_CTL_HW_ENABLE |
+ GEN6_RC_CTL_RC6_ENABLE |
+ GEN6_RC_CTL_EI_MODE(1);
pg_enable =
GEN9_RENDER_PG_ENABLE |
We should probably clarify in the commit message that gucrc doesn't
cover powergating and leaves that under driver control. Maybe we should
even pull this out into its own function rather than leaving it in the
"rc6 enable" function since it really is its own thing?
I have a note in the summary patch about this, will pull it into this
patch header as well.
There is already a separate effort underway from Suja to decouple RC6
and coarse power gate enabling. Might become more streamlined after that.
For now, I can have an if check around 2b so that there is more clarity?
Thanks,
Vinay.
Matt
@@ -513,6 +521,10 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
{
struct drm_i915_private *i915 = rc6_to_i915(rc6);
struct intel_uncore *uncore = rc6_to_uncore(rc6);
+ struct intel_gt *gt = rc6_to_gt(rc6);
+
+ /* Take control of RC6 back from GuC */
+ intel_guc_rc_disable(>uc.guc);
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
if (GRAPHICS_VER(i915) >= 9)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index ca538e5de940..8ff58aff 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++
Re: [Intel-gfx] refactor the i915 GVT support
On Thu, Jul 22, 2021 at 01:26:36PM +0200, Gerd Hoffmann wrote: > Hi, > > > https://github.com/intel/gvt-linux/blob/topic/gvt-xengt/drivers/gpu/drm/i915/gvt/xengt.c > > > But it's hard for some customers to contribute their own "hypervisor" > > module to the upstream Linux kernel. I am thinking what would be a > > better solution here? The MPT layer in the kernel helps a lot for > > customers, but only one open-source "hypervisor" module is there in > > the kernel. That can confuse people which don't know the story. One > > thing I was thinking is to put a document about the background and > > more description in the MPT headers. So it won't confuse more people. > > Getting the xengt module linked above merged into mainline > would also nicely explain why there are hypervisor modules. It would also be nice to explain why a GPU driver needs a hypervisor specific shim like this in the first place. enum hypervisor_type type; int (*host_init)(struct device *dev, void *gvt, const void *ops); void (*host_exit)(struct device *dev, void *gvt); int (*attach_vgpu)(void *vgpu, unsigned long *handle); void (*detach_vgpu)(void *vgpu); Doesn't vfio provide all this generically with notifiers? int (*inject_msi)(unsigned long handle, u32 addr, u16 data); Isn't this one just an eventfd? unsigned long (*from_virt_to_mfn)(void *p); int (*read_gpa)(unsigned long handle, unsigned long gpa, void *buf, unsigned long len); int (*write_gpa)(unsigned long handle, unsigned long gpa, void *buf, unsigned long len); unsigned long (*gfn_to_mfn)(unsigned long handle, unsigned long gfn); int (*dma_map_guest_page)(unsigned long handle, unsigned long gfn, unsigned long size, dma_addr_t *dma_addr); void (*dma_unmap_guest_page)(unsigned long handle, dma_addr_t dma_addr); int (*dma_pin_guest_page)(unsigned long handle, dma_addr_t dma_addr); int (*map_gfn_to_mfn)(unsigned long handle, unsigned long gfn, unsigned long mfn, unsigned int nr, bool map); bool (*is_valid_gfn)(unsigned long handle, unsigned long gfn); Shouldn't the vfio page SW IOMMU do all of this generically? int (*enable_page_track)(unsigned long handle, u64 gfn); int (*disable_page_track)(unsigned long handle, u64 gfn); int (*set_trap_area)(unsigned long handle, u64 start, u64 end, bool map); int (*set_opregion)(void *vgpu); int (*set_edid)(void *vgpu, int port_num); edid depends on hypervisor?? int (*get_vfio_device)(void *vgpu); void (*put_vfio_device)(void *vgpu); Jason ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 12/15] drm/i915/guc/slpc: Cache platform frequency limits
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Cache rp0, rp1 and rpn platform limits into SLPC structure
> for range checking while setting min/max frequencies.
>
> Also add "soft" limits which keep track of frequency changes
> made from userland. These are initially set to platform min
> and max.
>
> v2: Address review comments (Michal W)
> v3: Formatting (Michal W)
>
> Signed-off-by: Vinay Belgaumkar
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 97 +++
> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 11 +++
> drivers/gpu/drm/i915/i915_reg.h | 3 +
> 3 files changed, 111 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index c79dba60b2e6..a98cbf274862 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -94,6 +94,9 @@ static int slpc_shared_data_init(struct intel_guc_slpc
> *slpc)
> return err;
> }
>
> + slpc->max_freq_softlimit = 0;
> + slpc->min_freq_softlimit = 0;
> +
> return err;
> }
>
> @@ -124,6 +127,18 @@ static int guc_action_slpc_set_param(struct intel_guc
> *guc, u8 id, u32 value)
> return ret > 0 ? -EPROTO : ret;
> }
>
> +static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)
> +{
> + u32 request[] = {
> + INTEL_GUC_ACTION_SLPC_REQUEST,
> + SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 2),
> + id,
> + };
> +
> + return intel_guc_send(guc, request, ARRAY_SIZE(request));
> +}
> +
> +
> static bool slpc_is_running(struct intel_guc_slpc *slpc)
> {
> return (slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING);
> @@ -170,6 +185,16 @@ static int slpc_set_param(struct intel_guc_slpc *slpc,
> u8 id, u32 value)
> return guc_action_slpc_set_param(guc, id, value);
> }
>
> +static int slpc_unset_param(struct intel_guc_slpc *slpc,
> + u8 id)
> +{
> + struct intel_guc *guc = slpc_to_guc(slpc);
> +
> + GEM_BUG_ON(id >= SLPC_MAX_PARAM);
> +
> + return guc_action_slpc_unset_param(guc, id);
> +}
> +
> static const char *slpc_global_state_to_string(enum slpc_global_state state)
> {
> const char *str = NULL;
> @@ -406,6 +431,55 @@ void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
> GEN6_PMINTRMSK, pm_intrmsk_mbz, 0);
> }
>
> +static int intel_guc_slpc_set_softlimits(struct intel_guc_slpc *slpc)
nit: "intel_" prefix not needed for static function
> +{
> + int ret = 0;
> +
> + /* Softlimits are initially equivalent to platform limits
> + * unless they have deviated from defaults, in which case,
> + * we retain the values and set min/max accordingly.
> + */
fix style for multi-line comment
> + if (!slpc->max_freq_softlimit)
> + slpc->max_freq_softlimit = slpc->rp0_freq;
> + else if (slpc->max_freq_softlimit != slpc->rp0_freq)
> + ret = intel_guc_slpc_set_max_freq(slpc,
> + slpc->max_freq_softlimit);
> +
> + if (!slpc->min_freq_softlimit)
> + slpc->min_freq_softlimit = slpc->min_freq;
> + else if (slpc->min_freq_softlimit != slpc->min_freq)
> + ret = intel_guc_slpc_set_min_freq(slpc,
> + slpc->min_freq_softlimit);
> +
> + return ret;
> +}
> +
> +static void intel_guc_slpc_ignore_eff_freq(struct intel_guc_slpc *slpc, bool
> ignore)
> +{
> + if (ignore) {
> + /* A failure here does not affect the algorithm in a fatal way
> */
is this comment just for "ignore" case or whole function ? (as you don't
check for errors in "else" case anyway)
> + slpc_set_param(slpc,
> +SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
> +ignore);
> + slpc_set_param(slpc,
> +SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
> +slpc->min_freq);
> + } else {
> + slpc_unset_param(slpc,
> +SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY);
> + slpc_unset_param(slpc,
> +SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ);
> + }
> +}
> +
> +static void intel_guc_slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
> +{
> + /* Force slpc to used platform rp0 */
s/slpc/SLPC
> + slpc_set_param(slpc,
> +SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
> +slpc->rp0_freq);
hmm, likely indent is wrong, did you run checkpatch.pl ?
> +}
> +
> /*
> * intel_guc_slpc_enable() - Start SLPC
> * @slpc: pointer to intel_guc_slpc.
> @@ -423,6 +497,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
> {
> struct drm_i915_private *i915 = slpc_to_i915(slpc);
> struct slpc_shared_data *data;
> + u32 rp_state_cap;
> int ret;
>
> GEM_BUG_ON(!slpc->vma);
> @@ -460,6 +535,28 @@ int intel_guc_slpc_enable(struct intel_guc_slpc
Re: [Intel-gfx] [PATCH 11/15] drm/i915/guc/slpc: Enable ARAT timer interrupt
On Mon, Jul 26, 2021 at 12:07:56PM -0700, Vinay Belgaumkar wrote:
> This interrupt is enabled during RPS initialization, and
> now needs to be done by SLPC code. It allows ARAT timer
> expiry interrupts to get forwarded to GuC.
>
> Signed-off-by: Vinay Belgaumkar
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 16
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 ++
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8
> 3 files changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index 995d3d4807a3..c79dba60b2e6 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -392,6 +392,20 @@ int intel_guc_slpc_get_min_freq(struct intel_guc_slpc
> *slpc, u32 *val)
> return ret;
> }
>
> +void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
> +{
> + u32 pm_intrmsk_mbz = 0;
> +
> + /* Allow GuC to receive ARAT timer expiry event.
I've been berated for using comments like this this by other engineers.
I personally don't care at all (nor does checkpatch) but if you want to
avoid the wrath of others I'd change this to what I have below:
/*
* Allow GuC to receive ARAT timer expiry event.
* This interrupt register is setup by RPS code
* when host based Turbo is enabled.
*/
Same goes for comment below of same style.
Either way, patch looks good to me. With that:
Reviewed-by: Matthew Brost
> + * This interrupt register is setup by RPS code
> + * when host based Turbo is enabled.
> + */
> + pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
> +
> + intel_uncore_rmw(gt->uncore,
> +GEN6_PMINTRMSK, pm_intrmsk_mbz, 0);
> +}
> +
> /*
> * intel_guc_slpc_enable() - Start SLPC
> * @slpc: pointer to intel_guc_slpc.
> @@ -439,6 +453,8 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>
> slpc_query_task_state(slpc);
>
> + intel_guc_pm_intrmsk_enable(>gt);
> +
> /* min and max frequency limits being used by SLPC */
> drm_info(>drm, "SLPC min freq: %u Mhz, max is %u Mhz\n",
> slpc_decode_min_freq(slpc),
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> index d133c8020c16..f128143cc1d8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> @@ -9,6 +9,7 @@
> #include "intel_guc_submission.h"
> #include "intel_guc_slpc_types.h"
>
> +struct intel_gt;
> struct drm_printer;
>
> static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc)
> @@ -35,5 +36,6 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc
> *slpc, u32 val);
> int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val);
> int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val);
> int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p);
> +void intel_guc_pm_intrmsk_enable(struct intel_gt *gt);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index b98c14f8c229..9238bc076605 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -652,6 +652,7 @@ void intel_uc_suspend(struct intel_uc *uc)
> static int __uc_resume(struct intel_uc *uc, bool enable_communication)
> {
> struct intel_guc *guc = >guc;
> + struct intel_gt *gt = guc_to_gt(guc);
> int err;
>
> if (!intel_guc_is_fw_running(guc))
> @@ -663,6 +664,13 @@ static int __uc_resume(struct intel_uc *uc, bool
> enable_communication)
> if (enable_communication)
> guc_enable_communication(guc);
>
> + /* If we are only resuming GuC communication but not reloading
> + * GuC, we need to ensure the ARAT timer interrupt is enabled
> + * again. In case of GuC reload, it is enabled during SLPC enable.
> + */
> + if (enable_communication && intel_uc_uses_guc_slpc(uc))
> + intel_guc_pm_intrmsk_enable(gt);
> +
> err = intel_guc_resume(guc);
> if (err) {
> DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
> --
> 2.25.0
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/15] drm/i915/guc/slpc: Add debugfs for SLPC info
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> This prints out relevant SLPC info from the SLPC shared structure.
>
> We will send a h2g message which forces SLPC to update the
s/h2g/H2G
> shared data structure with latest information before reading it.
>
> v2: Address review comments (Michal W)
> v3: Remove unnecessary tasks from slpc_info (Michal W)
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
> ---
> .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c| 22 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 29 +++
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 4 ++-
> 3 files changed, 54 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
> index 72ddfff42f7d..3244e54b1337 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
> @@ -12,6 +12,7 @@
> #include "gt/uc/intel_guc_ct.h"
> #include "gt/uc/intel_guc_ads.h"
> #include "gt/uc/intel_guc_submission.h"
> +#include "gt/uc/intel_guc_slpc.h"
>
> static int guc_info_show(struct seq_file *m, void *data)
> {
> @@ -50,11 +51,32 @@ static int guc_registered_contexts_show(struct seq_file
> *m, void *data)
> }
> DEFINE_GT_DEBUGFS_ATTRIBUTE(guc_registered_contexts);
>
> +static int guc_slpc_info_show(struct seq_file *m, void *unused)
> +{
> + struct intel_guc *guc = m->private;
> + struct intel_guc_slpc *slpc = >slpc;
> + struct drm_printer p = drm_seq_file_printer(m);
> +
> + if (!intel_guc_slpc_is_used(guc))
> + return -ENODEV;
> +
> + return intel_guc_slpc_info(slpc, );
> +}
> +DEFINE_GT_DEBUGFS_ATTRIBUTE(guc_slpc_info);
> +
> +static bool intel_eval_slpc_support(void *data)
> +{
> + struct intel_guc *guc = (struct intel_guc *)data;
> +
> + return intel_guc_slpc_is_used(guc);
> +}
> +
> void intel_guc_debugfs_register(struct intel_guc *guc, struct dentry *root)
> {
> static const struct debugfs_gt_file files[] = {
> { "guc_info", _info_fops, NULL },
> { "guc_registered_contexts", _registered_contexts_fops,
> NULL },
> + { "guc_slpc_info", _slpc_info_fops,
> _eval_slpc_support},
> };
>
> if (!intel_guc_is_supported(guc))
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index c653bba3b5eb..995d3d4807a3 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -448,6 +448,35 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
> return 0;
> }
>
> +int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p)
nit: intel_guc_slpc_print_info ?
> +{
> + struct drm_i915_private *i915 = guc_to_gt(slpc_to_guc(slpc))->i915;
use slpc_to_i915()
> + struct slpc_shared_data *data = slpc->vaddr;
> + struct slpc_task_state_data *slpc_tasks;
> + intel_wakeref_t wakeref;
> + int ret = 0;
> +
> + GEM_BUG_ON(!slpc->vma);
> +
> + with_intel_runtime_pm(>runtime_pm, wakeref) {
> + ret = slpc_query_task_state(slpc);
> +
> + if (!ret) {
> + slpc_tasks = >task_state_data;
> +
> + drm_printf(p, "\tSLPC state: %s\n",
> slpc_get_state_string(slpc));
> + drm_printf(p, "\tGTPERF task active: %s\n",
> + yesno(slpc_tasks->status &
> SLPC_GTPERF_TASK_ENABLED));
> + drm_printf(p, "\tMax freq: %u MHz\n",
> + slpc_decode_max_freq(slpc));
> + drm_printf(p, "\tMin freq: %u MHz\n",
> + slpc_decode_min_freq(slpc));
> + }
> + }
> +
> + return ret;
> +}
> +
> void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
> {
> if (!slpc->vma)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> index 92d7afd44f07..d133c8020c16 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> @@ -9,6 +9,8 @@
> #include "intel_guc_submission.h"
> #include "intel_guc_slpc_types.h"
>
> +struct drm_printer;
> +
> static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc)
> {
> return guc->slpc_supported;
> @@ -25,7 +27,6 @@ static inline bool intel_guc_slpc_is_used(struct intel_guc
> *guc)
> }
>
> void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc);
> -
this should be fixed in earlier patch
with all that fixed,
Reviewed-by: Michal Wajdeczko
> int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
> int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
> void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
> @@ -33,5 +34,6 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc
> *slpc, u32 val);
> int
Re: [Intel-gfx] [PATCH 15/15] drm/i915/guc/rc: Setup and enable GUCRC feature
On Mon, Jul 26, 2021 at 12:08:00PM -0700, Vinay Belgaumkar wrote:
> This feature hands over the control of HW RC6 to the GuC.
> GuC decides when to put HW into RC6 based on it's internal
> busyness algorithms.
>
> GUCRC needs GuC submission to be enabled, and only
> supported on Gen12+ for now.
>
> When GUCRC is enabled, do not set HW RC6. Use a H2G message
> to tell GuC to enable GUCRC. When disabling RC6, tell GuC to
> revert RC6 control back to KMD.
>
> v2: Address comments (Michal W)
>
> Reviewed-by: Michal Wajdeczko
> Signed-off-by: Vinay Belgaumkar
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/intel_rc6.c | 22 +++--
> .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 6 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 1 +
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 80 +++
> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h | 31 +++
> drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 +
> 8 files changed, 140 insertions(+), 5 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index d8eac4468df9..3fc17f20d88e 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \
> gt/uc/intel_guc_fw.o \
> gt/uc/intel_guc_log.o \
> gt/uc/intel_guc_log_debugfs.o \
> + gt/uc/intel_guc_rc.o \
> gt/uc/intel_guc_slpc.o \
> gt/uc/intel_guc_submission.o \
> gt/uc/intel_huc.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
> b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 259d7eb4e165..299fcf10b04b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -98,11 +98,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
> set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
> set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
Do steps 2b and 2c above this still apply to gucrc? Are those still
controlling the behavior of gucrc or does the GuC firmware just
overwrite them with its own values? If they're still impacting the
behavior when gucrc is enabled, is there any updated guidance on how the
values should be set? It seems that there isn't any guidance in the
bspec for the last several platforms, so we've pretty much been re-using
old values without knowing if there's additional adjustment that should
be done for the newer platforms.
If the tuning values the driver sets get ignored/overwritten during GuC
operation, maybe we should add a new gucrc_rc6_enable() that gets used
instead of gen11_rc6_enable() and drops the unnecessary steps to help
clarify what's truly important?
>
> - /* 3a: Enable RC6 */
> - rc6->ctl_enable =
> - GEN6_RC_CTL_HW_ENABLE |
> - GEN6_RC_CTL_RC6_ENABLE |
> - GEN6_RC_CTL_EI_MODE(1);
> + /* 3a: Enable RC6
> + *
> + * With GUCRC, we do not enable bit 31 of RC_CTL,
> + * thus allowing GuC to control RC6 entry/exit fully instead.
> + * We will not set the HW ENABLE and EI bits
> + */
> + if (!intel_guc_rc_enable(>uc.guc))
> + rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE;
> + else
> + rc6->ctl_enable =
> + GEN6_RC_CTL_HW_ENABLE |
> + GEN6_RC_CTL_RC6_ENABLE |
> + GEN6_RC_CTL_EI_MODE(1);
>
> pg_enable =
> GEN9_RENDER_PG_ENABLE |
We should probably clarify in the commit message that gucrc doesn't
cover powergating and leaves that under driver control. Maybe we should
even pull this out into its own function rather than leaving it in the
"rc6 enable" function since it really is its own thing?
Matt
> @@ -513,6 +521,10 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
> {
> struct drm_i915_private *i915 = rc6_to_i915(rc6);
> struct intel_uncore *uncore = rc6_to_uncore(rc6);
> + struct intel_gt *gt = rc6_to_gt(rc6);
> +
> + /* Take control of RC6 back from GuC */
> + intel_guc_rc_disable(>uc.guc);
>
> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> if (GRAPHICS_VER(i915) >= 9)
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> index ca538e5de940..8ff58aff 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> @@ -135,6 +135,7 @@ enum intel_guc_action {
> INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007,
> INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,
> INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
> + INTEL_GUC_ACTION_SETUP_PC_GUCRC = 0x3004,
> INTEL_GUC_ACTION_AUTHENTICATE_HUC =
Re: [Intel-gfx] [PATCH 09/15] drm/i915/guc/slpc: Add get max/min freq hooks
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Add helpers to read the min/max frequency being used
> by SLPC. This is done by send a H2G command which forces
> SLPC to update the shared data struct which can then be
> read. These helpers will be used in a sysfs patch later
> on.
>
> v2: Address review comments (Michal W)
> v3: Return err in case of query failure (Michal W)
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 54 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 +
> 2 files changed, 56 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index 63656640189c..c653bba3b5eb 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -306,6 +306,33 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc
> *slpc, u32 val)
> return ret;
> }
>
> +/**
> + * intel_guc_slpc_get_max_freq() - Get max frequency limit for SLPC.
> + * @slpc: pointer to intel_guc_slpc.
> + * @val: pointer to val which will hold max frequency (MHz)
> + *
> + * This function will invoke GuC SLPC action to read the max frequency
> + * limit for unslice.
> + *
> + * Return: 0 on success, non-zero error code on failure.
> + */
> +int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val)
> +{
> + struct drm_i915_private *i915 = slpc_to_i915(slpc);
> + intel_wakeref_t wakeref;
> + int ret = 0;
> +
> + with_intel_runtime_pm(>runtime_pm, wakeref) {
> + /* Force GuC to update task data */
> + ret = slpc_query_task_state(slpc);
> +
> + if (!ret)
> + *val = slpc_decode_max_freq(slpc);
> + }
> +
> + return ret;
> +}
> +
> /**
> * intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
> * @slpc: pointer to intel_guc_slpc.
> @@ -338,6 +365,33 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc
> *slpc, u32 val)
> return ret;
> }
>
> +/**
> + * intel_guc_slpc_get_min_freq() - Get min frequency limit for SLPC.
> + * @slpc: pointer to intel_guc_slpc.
> + * @val: pointer to val which will hold min frequency (MHz)
> + *
> + * This function will invoke GuC SLPC action to read the min frequency
> + * limit for unslice.
> + *
> + * Return: 0 on success, non-zero error code on failure.
> + */
> +int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val)
> +{
> + intel_wakeref_t wakeref;
> + struct drm_i915_private *i915 = guc_to_gt(slpc_to_guc(slpc))->i915;
use slpc_to_i915() and in this order:
struct drm_i915_private *i915 = slpc_to_i915(slpc);
intel_wakeref_t wakeref;
int ret = 0;
with that fixed,
Reviewed-by: Michal Wajdeczko
> + int ret = 0;
> +
> + with_intel_runtime_pm(>runtime_pm, wakeref) {
> + /* Force GuC to update task data */
> + ret = slpc_query_task_state(slpc);
> +
> + if (!ret)
> + *val = slpc_decode_min_freq(slpc);
> + }
> +
> + return ret;
> +}
> +
> /*
> * intel_guc_slpc_enable() - Start SLPC
> * @slpc: pointer to intel_guc_slpc.
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> index e594510497ec..92d7afd44f07 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> @@ -31,5 +31,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
> void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
> int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val);
> int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val);
> +int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val);
> +int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val);
>
> #endif
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/15] drm/i915/guc/slpc: Add methods to set min/max frequency
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Add param set h2g helpers to set the min and max frequencies
s/h2g/H2G
> for use by SLPC.
>
> v2: Address review comments (Michal W)
> v3: Check for positive error code (Michal W)
>
> Signed-off-by: Sundaresan Sujaritha
> Signed-off-by: Vinay Belgaumkar
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 89 -
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 +
> 2 files changed, 90 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index f5808d2acbca..63656640189c 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -109,6 +109,21 @@ static u32 slpc_get_state(struct intel_guc_slpc *slpc)
> return data->header.global_state;
> }
>
> +static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
> +{
> + u32 request[] = {
> + INTEL_GUC_ACTION_SLPC_REQUEST,
> + SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),
> + id,
> + value,
> + };
> + int ret;
> +
> + ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
> +
> + return ret > 0 ? -EPROTO : ret;
> +}
> +
> static bool slpc_is_running(struct intel_guc_slpc *slpc)
> {
> return (slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING);
> @@ -118,7 +133,7 @@ static int guc_action_slpc_query(struct intel_guc *guc,
> u32 offset)
> {
> u32 request[] = {
> INTEL_GUC_ACTION_SLPC_REQUEST,
> - SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
> + SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
this should be fixed in original patch
> offset,
> 0,
> };
> @@ -146,6 +161,15 @@ static int slpc_query_task_state(struct intel_guc_slpc
> *slpc)
> return ret;
> }
>
> +static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
> +{
> + struct intel_guc *guc = slpc_to_guc(slpc);
> +
> + GEM_BUG_ON(id >= SLPC_MAX_PARAM);
> +
> + return guc_action_slpc_set_param(guc, id, value);
> +}
> +
> static const char *slpc_global_state_to_string(enum slpc_global_state state)
> {
> const char *str = NULL;
> @@ -251,6 +275,69 @@ static u32 slpc_decode_max_freq(struct intel_guc_slpc
> *slpc)
> GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
> }
>
> +/**
> + * intel_guc_slpc_set_max_freq() - Set max frequency limit for SLPC.
> + * @slpc: pointer to intel_guc_slpc.
> + * @val: frequency (MHz)
> + *
> + * This function will invoke GuC SLPC action to update the max frequency
> + * limit for unslice.
> + *
> + * Return: 0 on success, non-zero error code on failure.
> + */
> +int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
> +{
> + struct drm_i915_private *i915 = slpc_to_i915(slpc);
> + intel_wakeref_t wakeref;
> + int ret;
> +
> + with_intel_runtime_pm(>runtime_pm, wakeref) {
> + ret = slpc_set_param(slpc,
> +SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
> +val);
> + if (ret) {
> + drm_err(>drm,
> + "Set max frequency unslice returned (%pe)\n",
> ERR_PTR(ret));
maybe generic error reporting could be moved to slpc_set_param() ?
> + /* Return standardized err code for sysfs */
> + ret = -EIO;
at this point we don't know if this function is for sysfs only
I would sanitize error in "store" hook if really needed
ssize_t slpc_max_freq_store(... const char *buf, size_t count)
{
...
err = intel_guc_slpc_set_max_freq(slpc, val);
return err ? -EIO : count;
}
> + }
> + }
> +
> + return ret;
> +}
> +
> +/**
> + * intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
> + * @slpc: pointer to intel_guc_slpc.
> + * @val: frequency (MHz)
> + *
> + * This function will invoke GuC SLPC action to update the min unslice
> + * frequency.
> + *
> + * Return: 0 on success, non-zero error code on failure.
> + */
> +int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
> +{
> + int ret;
> + struct intel_guc *guc = slpc_to_guc(slpc);
> + struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> + intel_wakeref_t wakeref;
> +
> + with_intel_runtime_pm(>runtime_pm, wakeref) {
> + ret = slpc_set_param(slpc,
> +SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
> +val);
> + if (ret) {
> + drm_err(>drm,
> + "Set min frequency for unslice returned
> (%pe)\n", ERR_PTR(ret));
> + /* Return standardized err code for sysfs */
> + ret = -EIO;
> + }
> + }
same here
Michal
> +
> + return ret;
> +}
> +
> /*
> *
Re: [Intel-gfx] [PATCH 06/15] drm/i915/guc/slpc: Enable SLPC and add related H2G events
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Add methods for interacting with GuC for enabling SLPC. Enable
> SLPC after GuC submission has been established. GuC load will
> fail if SLPC cannot be successfully initialized. Add various
> helper methods to set/unset the parameters for SLPC. They can
> be set using H2G calls or directly setting bits in the shared
> data structure.
>
> v2: Address several review comments, add new helpers for
> decoding the SLPC min/max frequencies. Use masks instead of hardcoded
> constants. (Michal W)
>
> v3: Split global_state_to_string function, and check for positive
> non-zero return value from intel_guc_send() (Michal W)
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 237 ++
> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 2 +
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8 +
> 3 files changed, 247 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index bae4e33db0f8..f5808d2acbca 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -45,6 +45,40 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
> guc->slpc_selected = __guc_slpc_selected(guc);
> }
>
> +static void slpc_mem_set_param(struct slpc_shared_data *data,
> + u32 id, u32 value)
> +{
> + GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS);
> + /*
> + * When the flag bit is set, corresponding value will be read
> + * and applied by slpc.
s/slpc/SLPC
> + */
> + data->override_params.bits[id >> 5] |= (1 << (id % 32));
> + data->override_params.values[id] = value;
> +}
> +
> +static void slpc_mem_set_enabled(struct slpc_shared_data *data,
> + u8 enable_id, u8 disable_id)
> +{
> + /*
> + * Enabling a param involves setting the enable_id
> + * to 1 and disable_id to 0.
> + */
> + slpc_mem_set_param(data, enable_id, 1);
> + slpc_mem_set_param(data, disable_id, 0);
> +}
> +
> +static void slpc_mem_set_disabled(struct slpc_shared_data *data,
> + u8 enable_id, u8 disable_id)
> +{
> + /*
> + * Disabling a param involves setting the enable_id
> + * to 0 and disable_id to 1.
> + */
> + slpc_mem_set_param(data, disable_id, 1);
> + slpc_mem_set_param(data, enable_id, 0);
> +}
> +
> static int slpc_shared_data_init(struct intel_guc_slpc *slpc)
> {
> struct intel_guc *guc = slpc_to_guc(slpc);
> @@ -63,6 +97,129 @@ static int slpc_shared_data_init(struct intel_guc_slpc
> *slpc)
> return err;
> }
>
> +static u32 slpc_get_state(struct intel_guc_slpc *slpc)
> +{
> + struct slpc_shared_data *data;
> +
> + GEM_BUG_ON(!slpc->vma);
> +
> + drm_clflush_virt_range(slpc->vaddr, sizeof(u32));
> + data = slpc->vaddr;
> +
> + return data->header.global_state;
> +}
> +
> +static bool slpc_is_running(struct intel_guc_slpc *slpc)
> +{
> + return (slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING);
extra ( ) not needed
> +}
> +
> +static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
> +{
> + u32 request[] = {
> + INTEL_GUC_ACTION_SLPC_REQUEST,
> + SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
> + offset,
> + 0,
> + };
> + int ret;
> +
> + ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
> +
> + return ret > 0 ? -EPROTO : ret;
> +}
> +
> +static int slpc_query_task_state(struct intel_guc_slpc *slpc)
> +{
> + struct intel_guc *guc = slpc_to_guc(slpc);
> + struct drm_i915_private *i915 = slpc_to_i915(slpc);
> + u32 shared_data_gtt_offset = intel_guc_ggtt_offset(guc, slpc->vma);
just "offset" ? or maybe pass directly in call below ?
> + int ret;
> +
> + ret = guc_action_slpc_query(guc, shared_data_gtt_offset);
> + if (ret)
> + drm_err(>drm, "Query task state data returned (%pe)\n",
"Failed to query task state (%pe)\n" ?
> + ERR_PTR(ret));
> +
> + drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
> +
> + return ret;
> +}
> +
> +static const char *slpc_global_state_to_string(enum slpc_global_state state)
> +{
> + const char *str = NULL;
> +
> + switch (state) {
> + case SLPC_GLOBAL_STATE_NOT_RUNNING:
> + str = "not running";
> + break;
> + case SLPC_GLOBAL_STATE_INITIALIZING:
> + str = "initializing";
> + break;
> + case SLPC_GLOBAL_STATE_RESETTING:
> + str = "resetting";
> + break;
> + case SLPC_GLOBAL_STATE_RUNNING:
> + str = "running";
> + break;
> + case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
> + str = "shutting down";
> + break;
> + case
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adlp: Add workaround to disable CMTG clock gating
== Series Details == Series: drm/i915/adlp: Add workaround to disable CMTG clock gating URL : https://patchwork.freedesktop.org/series/93067/ State : success == Summary == CI Bug Log - changes from CI_DRM_10404 -> Patchwork_20716 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/index.html Known issues Here are the changes found in Patchwork_20716 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +29 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][2] ([i915#3718]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html * igt@gem_exec_suspend@basic-s0: - fi-tgl-1115g4: [PASS][3] -> [FAIL][4] ([i915#1888]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html * igt@i915_pm_rpm@basic-rte: - fi-bdw-5557u: NOTRUN -> [FAIL][5] ([i915#579]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/fi-bdw-5557u/igt@i915_pm_...@basic-rte.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 Participating hosts (40 -> 35) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-jsl-1 fi-bdw-samus Build changes - * Linux: CI_DRM_10404 -> Patchwork_20716 CI-20190529: 20190529 CI_DRM_10404: 371bd54db63fdd99356a1a3d0fdc9b76616eddcb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6153: a5dffe7499a2f7189718ddf1ccf49060b7c1529d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20716: 9cf8974d9e837f95ddbd9fef2411c699d619d24d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9cf8974d9e83 drm/i915/adlp: Add workaround to disable CMTG clock gating == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 0/7] Updates for GuC & parallel submission
IGT updates for GuC submission [1] and parallel submission (aka multi-bb execbuf) [2]. This entails adding tests for parallel submission and teaching IGTs to know of static priority mapping. More IGTs likely need to be updated gem_ctx_persistence and i915_hangman come to mind. Expect following series to address those tests. v2: (CI) - Fix off by 1 error in reserved fields of drm_i915_engine_info Signed-off-by: Matthew Brost [1] https://patchwork.freedesktop.org/series/91840/ [2] https://patchwork.freedesktop.org/series/92789/ Signed-off-by: Matthew Brost Matthew Brost (7): include/drm-uapi: Add parallel context configuration uAPI include/drm-uapi: Add logical mapping uAPI lib/intel_ctx: Add support for parallel contexts to intel_ctx library i915/gem_exec_balancer: Test parallel execbuf include/drm-uapi: Add static priority mapping UAPI i915/gem_scheduler: Make gem_scheduler understand static priority mapping i915/gem_ctx_shared: Make gem_ctx_shared understand static priority mapping include/drm-uapi/i915_drm.h| 145 +- lib/i915/gem_scheduler.c | 13 + lib/i915/gem_scheduler.h | 1 + lib/intel_ctx.c| 28 +- lib/intel_ctx.h| 2 + lib/intel_reg.h| 5 + tests/i915/gem_ctx_shared.c| 5 +- tests/i915/gem_exec_balancer.c | 487 + tests/i915/gem_exec_schedule.c | 47 ++-- 9 files changed, 709 insertions(+), 24 deletions(-) -- 2.28.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 5/7] include/drm-uapi: Add static priority mapping UAPI
Signed-off-by: Matthew Brost
---
include/drm-uapi/i915_drm.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 332c07e3d..0c023a52d 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -572,6 +572,15 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_PREEMPTION(1ul << 2)
#define I915_SCHEDULER_CAP_SEMAPHORES(1ul << 3)
#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
+/*
+ * Indicates the 2k user priority levels are statically mapped into 3 buckets
as
+ * follows:
+ *
+ * -1k to -1 Low priority
+ * 0 Normal priority
+ * 1 to 1k Highest priority
+ */
+#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
#define I915_PARAM_HUC_STATUS 42
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 7/7] i915/gem_ctx_shared: Make gem_ctx_shared understand static priority mapping
The i915 currently has 2k visible priority levels which are currently unique. This is changing to statically map these 2k levels into 3 buckets: low: < 0 mid: 0 high: > 0 Update gem_scheduler to understand this. This entails updating promotion test to use 3 levels that will map into different buckets and also delete a racey check. Signed-off-by: Matthew Brost --- tests/i915/gem_ctx_shared.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c index 4441e6eb7..0d95df8a5 100644 --- a/tests/i915/gem_ctx_shared.c +++ b/tests/i915/gem_ctx_shared.c @@ -771,10 +771,10 @@ static void promotion(int i915, const intel_ctx_cfg_t *cfg, unsigned ring) gem_context_set_priority(i915, ctx[LO]->id, MIN_PRIO); ctx[HI] = intel_ctx_create(i915, _cfg); - gem_context_set_priority(i915, ctx[HI]->id, 0); + gem_context_set_priority(i915, ctx[HI]->id, MAX_PRIO); ctx[NOISE] = intel_ctx_create(i915, _cfg); - gem_context_set_priority(i915, ctx[NOISE]->id, MIN_PRIO/2); + gem_context_set_priority(i915, ctx[NOISE]->id, 0); result = gem_create(i915, 4096); dep = gem_create(i915, 4096); @@ -811,7 +811,6 @@ static void promotion(int i915, const intel_ctx_cfg_t *cfg, unsigned ring) I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT); gem_close(i915, result); - igt_assert_eq_u32(ptr[0], ctx[NOISE]->id); munmap(ptr, 4096); intel_ctx_destroy(i915, ctx[NOISE]); -- 2.28.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 4/7] i915/gem_exec_balancer: Test parallel execbuf
Add basic parallel execbuf submission test which more or less just
submits the same BB in loop a which does an atomic increment to a memory
location. The memory location is checked at the end for the correct
value. Different sections use various IOCTL options (e.g. fences,
location of BBs, etc...).
In addition to above sections, an additional section ensure the ordering
of parallel submission by submitting a spinning batch to 1 individual
engine, submit a parallel execbuf to all engines instances within the
class, verify none on parallel execbuf make to hardware, release
spinner, and finally verify everything has completed.
Signed-off-by: Matthew Brost
---
lib/intel_reg.h| 5 +
tests/i915/gem_exec_balancer.c | 487 +
2 files changed, 492 insertions(+)
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index ac1fc6cbc..146ac76c9 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2593,6 +2593,11 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define STATE3D_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x01<<16))
+/* Atomics */
+#define MI_ATOMIC ((0x2f << 23) | 2)
+#define MI_ATOMIC_INLINE_DATA (1 << 18)
+#define MI_ATOMIC_ADD (0x7 << 8)
+
/* Batch */
#define MI_BATCH_BUFFER((0x30 << 23) | 1)
#define MI_BATCH_BUFFER_START (0x31 << 23)
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index 2f98950bb..053f1d1f7 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include "i915/gem.h"
#include "i915/gem_create.h"
@@ -56,6 +57,31 @@ static size_t sizeof_load_balance(int count)
#define alloca0(sz) ({ size_t sz__ = (sz); memset(alloca(sz__), 0, sz__); })
+static int
+__i915_query(int fd, struct drm_i915_query *q)
+{
+ if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+ return -errno;
+
+ return 0;
+}
+
+static int
+__i915_query_items(int fd, struct drm_i915_query_item *items, uint32_t n_items)
+{
+ struct drm_i915_query q = {
+ .num_items = n_items,
+ .items_ptr = to_user_pointer(items),
+ };
+
+ return __i915_query(fd, );
+}
+
+#define i915_query_items(fd, items, n_items) do { \
+ igt_assert_eq(__i915_query_items(fd, items, n_items), 0); \
+ errno = 0; \
+ } while (0)
+
static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
{
int fd;
@@ -2691,6 +2717,380 @@ static void nohangcheck(int i915)
close(params);
}
+static void check_bo(int i915, uint32_t handle, unsigned int count, bool wait)
+{
+ uint32_t *map;
+
+ map = gem_mmap__cpu(i915, handle, 0, 4096, PROT_READ);
+ if (wait)
+ gem_set_domain(i915, handle, I915_GEM_DOMAIN_CPU,
+ I915_GEM_DOMAIN_CPU);
+ igt_assert_eq(map[0], count);
+ munmap(map, 4096);
+}
+
+static struct drm_i915_query_engine_info *query_engine_info(int i915)
+{
+ struct drm_i915_query_engine_info *engines;
+ struct drm_i915_query_item item;
+
+#define QUERY_SIZE 0x4000
+ engines = malloc(QUERY_SIZE);
+ igt_assert(engines);
+
+ memset(engines, 0, QUERY_SIZE);
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.data_ptr = to_user_pointer(engines);
+ item.length = QUERY_SIZE;
+
+ i915_query_items(i915, , 1);
+ igt_assert(item.length >= 0);
+ igt_assert(item.length <= QUERY_SIZE);
+#undef QUERY_SIZE
+
+ return engines;
+}
+
+/* This function only works if siblings contains all instances of a class */
+static void logical_sort_siblings(int i915,
+ struct i915_engine_class_instance *siblings,
+ unsigned int count)
+{
+ struct i915_engine_class_instance *sorted;
+ struct drm_i915_query_engine_info *engines;
+ unsigned int i, j;
+
+ sorted = calloc(count, sizeof(*sorted));
+ igt_assert(sorted);
+
+ engines = query_engine_info(i915);
+
+ for (j = 0; j < count; ++j) {
+ for (i = 0; i < engines->num_engines; ++i) {
+ if (siblings[j].engine_class ==
+ engines->engines[i].engine.engine_class &&
+ siblings[j].engine_instance ==
+ engines->engines[i].engine.engine_instance) {
+ uint16_t logical_instance =
+ engines->engines[i].logical_instance;
+
+ igt_assert(logical_instance < count);
+
igt_assert(!sorted[logical_instance].engine_class);
+
igt_assert(!sorted[logical_instance].engine_instance);
+
+ sorted[logical_instance]
[Intel-gfx] [PATCH i-g-t 3/7] lib/intel_ctx: Add support for parallel contexts to intel_ctx library
Signed-off-by: Matthew Brost
---
lib/intel_ctx.c | 28 +++-
lib/intel_ctx.h | 2 ++
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/lib/intel_ctx.c b/lib/intel_ctx.c
index f28c15544..11ec6fca4 100644
--- a/lib/intel_ctx.c
+++ b/lib/intel_ctx.c
@@ -83,6 +83,7 @@ __context_create_cfg(int fd, const intel_ctx_cfg_t *cfg,
uint32_t *ctx_id)
{
uint64_t ext_root = 0;
I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(balance, GEM_MAX_ENGINES);
+ I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(parallel, GEM_MAX_ENGINES);
I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, GEM_MAX_ENGINES);
struct drm_i915_gem_context_create_ext_setparam engines_param, vm_param;
struct drm_i915_gem_context_create_ext_setparam persist_param;
@@ -117,7 +118,29 @@ __context_create_cfg(int fd, const intel_ctx_cfg_t *cfg,
uint32_t *ctx_id)
unsigned num_logical_engines;
memset(, 0, sizeof(engines));
- if (cfg->load_balance) {
+ if (cfg->parallel) {
+ memset(, 0, sizeof(parallel));
+
+ num_logical_engines = 1;
+
+ parallel.base.name =
+ I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT;
+
+ engines.engines[0].engine_class =
+ I915_ENGINE_CLASS_INVALID;
+ engines.engines[0].engine_instance =
+ I915_ENGINE_CLASS_INVALID_NONE;
+
+ parallel.num_siblings = cfg->num_engines;
+ parallel.width = cfg->width;
+ for (i = 0; i < cfg->num_engines * cfg->width; i++) {
+ igt_assert_eq(cfg->engines[0].engine_class,
+ cfg->engines[i].engine_class);
+ parallel.engines[i] = cfg->engines[i];
+ }
+
+ engines.extensions = to_user_pointer();
+ } else if (cfg->load_balance) {
memset(, 0, sizeof(balance));
/* In this case, the first engine is the virtual
@@ -127,6 +150,9 @@ __context_create_cfg(int fd, const intel_ctx_cfg_t *cfg,
uint32_t *ctx_id)
igt_assert(cfg->num_engines + 1 <= GEM_MAX_ENGINES);
num_logical_engines = cfg->num_engines + 1;
+ balance.base.name =
+ I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE;
+
engines.engines[0].engine_class =
I915_ENGINE_CLASS_INVALID;
engines.engines[0].engine_instance =
diff --git a/lib/intel_ctx.h b/lib/intel_ctx.h
index 9649f6d96..89c65fcd3 100644
--- a/lib/intel_ctx.h
+++ b/lib/intel_ctx.h
@@ -46,7 +46,9 @@ typedef struct intel_ctx_cfg {
uint32_t vm;
bool nopersist;
bool load_balance;
+ bool parallel;
unsigned int num_engines;
+ unsigned int width;
struct i915_engine_class_instance engines[GEM_MAX_ENGINES];
} intel_ctx_cfg_t;
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/7] include/drm-uapi: Add parallel context configuration uAPI
Signed-off-by: Matthew Brost
---
include/drm-uapi/i915_drm.h | 128
1 file changed, 128 insertions(+)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index a1c0030c3..3c1aac348 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -1705,6 +1705,7 @@ struct drm_i915_gem_context_param {
* Extensions:
* i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
* i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
+ * i915_context_engines_parallel_submit
(I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT)
*/
#define I915_CONTEXT_PARAM_ENGINES 0xa
@@ -1883,10 +1884,137 @@ struct i915_context_engines_bond {
struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
+/**
+ * struct i915_context_engines_parallel_submit - Configure engine for
+ * parallel submission.
+ *
+ * Setup a slot in the context engine map to allow multiple BBs to be submitted
+ * in a single execbuf IOCTL. Those BBs will then be scheduled to run on the
GPU
+ * in parallel. Multiple hardware contexts are created internally in the i915
+ * run these BBs. Once a slot is configured for N BBs only N BBs can be
+ * submitted in each execbuf IOCTL and this is implicit behavior e.g. The user
+ * doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how
+ * many BBs there are based on the slot's configuration. The N BBs are the last
+ * N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.
+ *
+ * The default placement behavior is to create implicit bonds between each
+ * context if each context maps to more than 1 physical engine (e.g. context is
+ * a virtual engine). Also we only allow contexts of same engine class and
these
+ * contexts must be in logically contiguous order. Examples of the placement
+ * behavior described below. Lastly, the default is to not allow BBs to
+ * preempted mid BB rather insert coordinated preemption on all hardware
+ * contexts between each set of BBs. Flags may be added in the future to change
+ * both of these default behaviors.
+ *
+ * Returns -EINVAL if hardware context placement configuration is invalid or if
+ * the placement configuration isn't supported on the platform / submission
+ * interface.
+ * Returns -ENODEV if extension isn't supported on the platform / submission
+ * interface.
+ *
+ * .. code-block:: none
+ *
+ * Example 1 pseudo code:
+ * CS[X] = generic engine of same class, logical instance X
+ * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=1,
+ * engines=CS[0],CS[1])
+ *
+ * Results in the following valid placement:
+ * CS[0], CS[1]
+ *
+ * Example 2 pseudo code:
+ * CS[X] = generic engine of same class, logical instance X
+ * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=2,
+ * engines=CS[0],CS[2],CS[1],CS[3])
+ *
+ * Results in the following valid placements:
+ * CS[0], CS[1]
+ * CS[2], CS[3]
+ *
+ * This can also be thought of as 2 virtual engines described by 2-D array
+ * in the engines the field with bonds placed between each index of the
+ * virtual engines. e.g. CS[0] is bonded to CS[1], CS[2] is bonded to
+ * CS[3].
+ * VE[0] = CS[0], CS[2]
+ * VE[1] = CS[1], CS[3]
+ *
+ * Example 3 pseudo code:
+ * CS[X] = generic engine of same class, logical instance X
+ * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=2,
+ * engines=CS[0],CS[1],CS[1],CS[3])
+ *
+ * Results in the following valid and invalid placements:
+ * CS[0], CS[1]
+ * CS[1], CS[3] - Not logical contiguous, return -EINVAL
+ */
+struct i915_context_engines_parallel_submit {
+ /**
+* @base: base user extension.
+*/
+ struct i915_user_extension base;
+
+ /**
+* @engine_index: slot for parallel engine
+*/
+ __u16 engine_index;
+
+ /**
+* @width: number of contexts per parallel engine
+*/
+ __u16 width;
+
+ /**
+* @num_siblings: number of siblings per context
+*/
+ __u16 num_siblings;
+
+ /**
+* @mbz16: reserved for future use; must be zero
+*/
+ __u16 mbz16;
+
+ /**
+* @flags: all undefined flags must be zero, currently not defined flags
+*/
+ __u64 flags;
+
+ /**
+* @mbz64: reserved for future use; must be zero
+*/
+ __u64 mbz64[3];
+
+ /**
+* @engines: 2-d array of engine instances to configure parallel engine
+*
+* length = width (i) * num_siblings (j)
+
[Intel-gfx] [PATCH i-g-t 6/7] i915/gem_scheduler: Make gem_scheduler understand static priority mapping
The i915 currently has 2k visible priority levels which are currently
unique. This is changing to statically map these 2k levels into 3
buckets:
low: < 0
mid: 0
high: > 0
Update gem_scheduler to understand this. This entails updating promotion
test to use 3 levels that will map into different buckets and also
delete a racey check. Also skip any tests that rely on having more than
3 priority levels.
Signed-off-by: Matthew Brost
---
lib/i915/gem_scheduler.c | 13 ++
lib/i915/gem_scheduler.h | 1 +
tests/i915/gem_exec_schedule.c | 47 --
3 files changed, 42 insertions(+), 19 deletions(-)
diff --git a/lib/i915/gem_scheduler.c b/lib/i915/gem_scheduler.c
index cdddf42ad..bec2e485a 100644
--- a/lib/i915/gem_scheduler.c
+++ b/lib/i915/gem_scheduler.c
@@ -90,6 +90,19 @@ bool gem_scheduler_has_ctx_priority(int fd)
I915_SCHEDULER_CAP_PRIORITY;
}
+/**
+ * gem_scheduler_has_ctx_priority:
+ * @fd: open i915 drm file descriptor
+ *
+ * Feature test macro to query whether the driver supports priority assigned
+ * from user space are statically mapping into 3 buckets.
+ */
+bool gem_scheduler_has_static_priority(int fd)
+{
+ return gem_scheduler_capability(fd) &
+ I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP;
+}
+
/**
* gem_scheduler_has_preemption:
* @fd: open i915 drm file descriptor
diff --git a/lib/i915/gem_scheduler.h b/lib/i915/gem_scheduler.h
index d43e84bd2..b00804f70 100644
--- a/lib/i915/gem_scheduler.h
+++ b/lib/i915/gem_scheduler.h
@@ -29,6 +29,7 @@
unsigned gem_scheduler_capability(int fd);
bool gem_scheduler_enabled(int fd);
bool gem_scheduler_has_ctx_priority(int fd);
+bool gem_scheduler_has_static_priority(int fd);
bool gem_scheduler_has_preemption(int fd);
bool gem_scheduler_has_semaphores(int fd);
bool gem_scheduler_has_engine_busy_stats(int fd);
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index e5fb45982..f03842478 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -1344,8 +1344,7 @@ static void reorder(int fd, const intel_ctx_cfg_t *cfg,
static void promotion(int fd, const intel_ctx_cfg_t *cfg, unsigned ring)
{
IGT_CORK_FENCE(cork);
- uint32_t result, dep;
- uint32_t result_read, dep_read;
+ uint32_t result, dep, dep_read;
const intel_ctx_t *ctx[3];
int fence;
@@ -1353,10 +1352,10 @@ static void promotion(int fd, const intel_ctx_cfg_t
*cfg, unsigned ring)
gem_context_set_priority(fd, ctx[LO]->id, MIN_PRIO);
ctx[HI] = intel_ctx_create(fd, cfg);
- gem_context_set_priority(fd, ctx[HI]->id, 0);
+ gem_context_set_priority(fd, ctx[HI]->id, MAX_PRIO);
ctx[NOISE] = intel_ctx_create(fd, cfg);
- gem_context_set_priority(fd, ctx[NOISE]->id, MIN_PRIO/2);
+ gem_context_set_priority(fd, ctx[NOISE]->id, 0);
result = gem_create(fd, 4096);
dep = gem_create(fd, 4096);
@@ -1383,11 +1382,9 @@ static void promotion(int fd, const intel_ctx_cfg_t
*cfg, unsigned ring)
dep_read = __sync_read_u32(fd, dep, 0);
gem_close(fd, dep);
- result_read = __sync_read_u32(fd, result, 0);
gem_close(fd, result);
igt_assert_eq_u32(dep_read, ctx[HI]->id);
- igt_assert_eq_u32(result_read, ctx[NOISE]->id);
intel_ctx_destroy(fd, ctx[NOISE]);
intel_ctx_destroy(fd, ctx[LO]);
@@ -2963,19 +2960,25 @@ igt_main
test_each_engine_store("preempt-other-chain", fd, ctx,
e)
preempt_other(fd, >cfg, e->flags, CHAIN);
- test_each_engine_store("preempt-queue", fd, ctx, e)
- preempt_queue(fd, >cfg, e->flags, 0);
+ test_each_engine_store("preempt-engines", fd, ctx, e)
+ preempt_engines(fd, e, 0);
- test_each_engine_store("preempt-queue-chain", fd, ctx,
e)
- preempt_queue(fd, >cfg, e->flags, CHAIN);
- test_each_engine_store("preempt-queue-contexts", fd,
ctx, e)
- preempt_queue(fd, >cfg, e->flags,
CONTEXTS);
+ igt_subtest_group {
+ igt_fixture {
+
igt_require(!gem_scheduler_has_static_priority(fd));
+ }
- test_each_engine_store("preempt-queue-contexts-chain",
fd, ctx, e)
- preempt_queue(fd, >cfg, e->flags, CONTEXTS
| CHAIN);
+ test_each_engine_store("preempt-queue", fd,
ctx, e)
+ preempt_queue(fd, >cfg, e->flags,
0);
- test_each_engine_store("preempt-engines", fd, ctx, e)
- preempt_engines(fd, e, 0);
+
[Intel-gfx] [PATCH i-g-t 2/7] include/drm-uapi: Add logical mapping uAPI
v2:
(CI)
- Fix off by 1 error in size of reserved fields
Signed-off-by: Matthew Brost
---
include/drm-uapi/i915_drm.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 3c1aac348..332c07e3d 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -2518,14 +2518,20 @@ struct drm_i915_engine_info {
/** @flags: Engine flags. */
__u64 flags;
+#define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0)
/** @capabilities: Capabilities of this engine. */
__u64 capabilities;
#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC(1 << 1)
+ /** @logical_instance: Logical instance of engine */
+ __u16 logical_instance;
+
/** @rsvd1: Reserved fields. */
- __u64 rsvd1[4];
+ __u16 rsvd1[3];
+ /** @rsvd2: Reserved fields. */
+ __u64 rsvd2[3];
};
/**
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm: use the lookup lock in drm_is_current_master
On Thu, Jul 22, 2021 at 12:38:10PM +0200, Daniel Vetter wrote:
> On Thu, Jul 22, 2021 at 05:29:27PM +0800, Desmond Cheong Zhi Xi wrote:
> > Inside drm_is_current_master, using the outer drm_device.master_mutex
> > to protect reads of drm_file.master makes the function prone to creating
> > lock hierarchy inversions. Instead, we can use the
> > drm_file.master_lookup_lock that sits at the bottom of the lock
> > hierarchy.
> >
> > Reported-by: Daniel Vetter
> > Signed-off-by: Desmond Cheong Zhi Xi
> > ---
> > drivers/gpu/drm/drm_auth.c | 9 +
> > 1 file changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c
> > index f00354bec3fb..9c24b8cc8e36 100644
> > --- a/drivers/gpu/drm/drm_auth.c
> > +++ b/drivers/gpu/drm/drm_auth.c
> > @@ -63,8 +63,9 @@
> >
> > static bool drm_is_current_master_locked(struct drm_file *fpriv)
> > {
> > - lockdep_assert_held_once(>minor->dev->master_mutex);
> > -
> > + /* Either drm_device.master_mutex or drm_file.master_lookup_lock
> > +* should be held here.
> > +*/
>
> Disappointing that lockdep can't check or conditions for us, a
> lockdep_assert_held_either would be really neat in some cases.
>
> Adding lockdep folks, maybe they have ideas.
#ifdef CONFIG_LOCKDEP
WARN_ON_ONCE(debug_locks && !(lockdep_is_held(_device.master_mutex)
||
lockdep_is_held(_file.master_lookup_lock)));
#endif
doesn't exactly roll off the tongue, but should do as you want I
suppose.
Would something like:
#define lockdep_assert(cond)WARN_ON_ONCE(debug_locks && !(cond))
Such that we can write:
lockdep_assert(lockdep_is_held(_device.master_mutex) ||
lockdep_is_held(_file.master_lookup_lock));
make it better ?
---
Subject: locking/lockdep: Provide lockdep_assert{,_once}() helpers
Extract lockdep_assert{,_once}() helpers to more easily write composite
assertions like, for example:
lockdep_assert(lockdep_is_held(_device.master_mutex) ||
lockdep_is_held(_file.master_lookup_lock));
Signed-off-by: Peter Zijlstra (Intel)
---
diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h
index 5cf387813754..0da67341c1fb 100644
--- a/include/linux/lockdep.h
+++ b/include/linux/lockdep.h
@@ -306,31 +306,29 @@ extern void lock_unpin_lock(struct lockdep_map *lock,
struct pin_cookie);
#define lockdep_depth(tsk) (debug_locks ? (tsk)->lockdep_depth : 0)
-#define lockdep_assert_held(l) do {\
- WARN_ON(debug_locks && \
- lockdep_is_held(l) == LOCK_STATE_NOT_HELD); \
- } while (0)
+#define lockdep_assert(cond) \
+ do { WARN_ON(debug_locks && !(cond)); } while (0)
-#define lockdep_assert_not_held(l) do {\
- WARN_ON(debug_locks && \
- lockdep_is_held(l) == LOCK_STATE_HELD); \
- } while (0)
+#define lockdep_assert_once(cond) \
+ do { WARN_ON_ONCE(debug_locks && !(cond)); } while (0)
-#define lockdep_assert_held_write(l) do {\
- WARN_ON(debug_locks && !lockdep_is_held_type(l, 0));\
- } while (0)
+#define lockdep_assert_held(l) \
+ lockdep_assert(lockdep_is_held(l) != LOCK_STAT_NOT_HELD)
-#define lockdep_assert_held_read(l)do {\
- WARN_ON(debug_locks && !lockdep_is_held_type(l, 1));\
- } while (0)
+#define lockdep_assert_not_held(l) \
+ lockdep_assert(lockdep_is_held(l) != LOCK_STATE_HELD)
-#define lockdep_assert_held_once(l)do {\
- WARN_ON_ONCE(debug_locks && !lockdep_is_held(l)); \
- } while (0)
+#define lockdep_assert_held_write(l) \
+ lockdep_assert(lockdep_is_held_type(l, 0))
-#define lockdep_assert_none_held_once()do {
\
- WARN_ON_ONCE(debug_locks && current->lockdep_depth);\
- } while (0)
+#define lockdep_assert_held_read(l)\
+ lockdep_assert(lockdep_is_held_type(l, 1))
+
+#define lockdep_assert_held_once(l)\
+ lockdep_assert_once(lockdep_is_held(l) != LOCK_STAT_NOT_HELD)
+
+#define lockdep_assert_none_held_once()\
+ lockdep_assert_once(!current->lockdep_depth)
#define lockdep_recursing(tsk) ((tsk)->lockdep_recursion)
@@ -407,6 +405,9 @@ extern int lock_is_held(const void *);
extern int lockdep_is_held(const void *);
#define lockdep_is_held_type(l, r) (1)
+#define lockdep_assert(c) do { } while (0)
+#define lockdep_assert_once(c) do { } while (0)
+
#define lockdep_assert_held(l) do { (void)(l); } while (0)
#define lockdep_assert_not_held(l) do { (void)(l);
[Intel-gfx] [PATCH v2] drm/i915/adl_p: Allow underrun recovery when possible
ADL_P requires that we disable underrun recovery when downscaling (or
using the scaler for YUV420 pipe output), using DSC, or using PSR2.
Otherwise we should be able to enable the underrun recovery.
On DG2 we need to keep underrun recovery disabled at all times, but the
chicken bit in PIPE_CHICKEN has an inverted meaning (it's an enable bit
instead of disable).
v2:
- Reverse the condition (clear the disable bit when supported, set
disable bit when not supported).
Bspec: 50351
Signed-off-by: Matt Roper
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 50 +---
drivers/gpu/drm/i915/i915_reg.h | 3 +-
2 files changed, 36 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index bd533813e5e2..83c918265835 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2211,8 +2211,26 @@ void intel_display_finish_reset(struct drm_i915_private
*dev_priv)
clear_bit_unlock(I915_RESET_MODESET, _priv->gt.reset.flags);
}
-static void icl_set_pipe_chicken(struct intel_crtc *crtc)
+static bool underrun_recovery_supported(const struct intel_crtc_state
*crtc_state)
{
+ if (crtc_state->pch_pfit.enabled &&
+ (crtc_state->pipe_src_w > drm_rect_width(_state->pch_pfit.dst)
||
+crtc_state->pipe_src_h >
drm_rect_height(_state->pch_pfit.dst) ||
+crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420))
+ return false;
+
+ if (crtc_state->dsc.compression_enable)
+ return false;
+
+ if (crtc_state->has_psr2)
+ return false;
+
+ return true;
+}
+
+static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
u32 tmp;
@@ -2233,19 +2251,19 @@ static void icl_set_pipe_chicken(struct intel_crtc
*crtc)
*/
tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
- /*
-* "The underrun recovery mechanism should be disabled
-* when the following is enabled for this pipe:
-* WiDi
-* Downscaling (this includes YUV420 fullblend)
-* COG
-* DSC
-* PSR2"
-*
-* FIXME: enable whenever possible...
-*/
- if (IS_ALDERLAKE_P(dev_priv))
- tmp |= UNDERRUN_RECOVERY_DISABLE;
+ if (IS_DG2(dev_priv)) {
+ /*
+* Underrun recovery must always be disabled on DG2. However
+* the chicken bit meaning is inverted compared to other
+* platforms.
+*/
+ tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
+ } else if (DISPLAY_VER(dev_priv) >= 13) {
+ if (underrun_recovery_supported(crtc_state))
+ tmp &= ~UNDERRUN_RECOVERY_DISABLE_ADLP;
+ else
+ tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
+ }
intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
}
@@ -3561,7 +3579,7 @@ static void hsw_crtc_enable(struct intel_atomic_state
*state,
hsw_set_linetime_wm(new_crtc_state);
if (DISPLAY_VER(dev_priv) >= 11)
- icl_set_pipe_chicken(crtc);
+ icl_set_pipe_chicken(new_crtc_state);
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
@@ -10193,7 +10211,7 @@ static void intel_pipe_fastset(const struct
intel_crtc_state *old_crtc_state,
hsw_set_linetime_wm(new_crtc_state);
if (DISPLAY_VER(dev_priv) >= 11)
- icl_set_pipe_chicken(crtc);
+ icl_set_pipe_chicken(new_crtc_state);
}
static void commit_pipe_pre_planes(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d5c67fd5dc7d..a10cdd1a3001 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8416,7 +8416,8 @@ enum {
#define _PIPEC_CHICKEN 0x72038
#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe,
_PIPEA_CHICKEN,\
_PIPEB_CHICKEN)
-#define UNDERRUN_RECOVERY_DISABLEREG_BIT(30)
+#define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
+#define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
#define PER_PIXEL_ALPHA_BYPASS_EN(1 << 7)
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 00/18] drm/sched dependency tracking and dma-resv fixes
On 07/12, Daniel Vetter wrote: > Hi all, > > Quick new version since the previous one was a bit too broken: > - dropped the bug-on patch to avoid breaking amdgpu's gpu reset failure > games > - another attempt at splitting job_init/arm, hopefully we're getting > there. > > Note that Christian has brought up a bikeshed on the new functions to add > dependencies to drm_sched_jobs. I'm happy to repaint, if there's some kind > of consensus on what it should be. > > Testing and review very much welcome, as usual. Hi, I've tested it some time ago; but now, for v3d, don't forget to rebase. Also, common parts lgtm, so for them: Acked-by: Melissa Wen > > Cheers, Daniel > > Daniel Vetter (18): > drm/sched: Split drm_sched_job_init > drm/sched: Barriers are needed for entity->last_scheduled > drm/sched: Add dependency tracking > drm/sched: drop entity parameter from drm_sched_push_job > drm/sched: improve docs around drm_sched_entity > drm/panfrost: use scheduler dependency tracking > drm/lima: use scheduler dependency tracking > drm/v3d: Move drm_sched_job_init to v3d_job_init > drm/v3d: Use scheduler dependency handling > drm/etnaviv: Use scheduler dependency handling > drm/gem: Delete gem array fencing helpers > drm/sched: Don't store self-dependencies > drm/sched: Check locking in drm_sched_job_await_implicit > drm/msm: Don't break exclusive fence ordering > drm/etnaviv: Don't break exclusive fence ordering > drm/i915: delete exclude argument from i915_sw_fence_await_reservation > drm/i915: Don't break exclusive fence ordering > dma-resv: Give the docs a do-over > > Documentation/gpu/drm-mm.rst | 3 + > drivers/dma-buf/dma-resv.c| 24 ++- > drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 4 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 4 +- > drivers/gpu/drm/drm_gem.c | 96 - > drivers/gpu/drm/etnaviv/etnaviv_gem.h | 5 +- > drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 64 +++--- > drivers/gpu/drm/etnaviv/etnaviv_sched.c | 65 +- > drivers/gpu/drm/etnaviv/etnaviv_sched.h | 3 +- > drivers/gpu/drm/i915/display/intel_display.c | 4 +- > drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 2 +- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 8 +- > drivers/gpu/drm/i915/i915_sw_fence.c | 6 +- > drivers/gpu/drm/i915/i915_sw_fence.h | 1 - > drivers/gpu/drm/lima/lima_gem.c | 7 +- > drivers/gpu/drm/lima/lima_sched.c | 28 +-- > drivers/gpu/drm/lima/lima_sched.h | 6 +- > drivers/gpu/drm/msm/msm_gem_submit.c | 3 +- > drivers/gpu/drm/panfrost/panfrost_drv.c | 16 +- > drivers/gpu/drm/panfrost/panfrost_job.c | 39 +--- > drivers/gpu/drm/panfrost/panfrost_job.h | 5 +- > drivers/gpu/drm/scheduler/sched_entity.c | 140 +++-- > drivers/gpu/drm/scheduler/sched_fence.c | 19 +- > drivers/gpu/drm/scheduler/sched_main.c| 181 +++-- > drivers/gpu/drm/v3d/v3d_drv.h | 6 +- > drivers/gpu/drm/v3d/v3d_gem.c | 115 +-- > drivers/gpu/drm/v3d/v3d_sched.c | 44 + > include/drm/drm_gem.h | 5 - > include/drm/gpu_scheduler.h | 186 ++ > include/linux/dma-buf.h | 7 + > include/linux/dma-resv.h | 104 +- > 31 files changed, 672 insertions(+), 528 deletions(-) > > -- > 2.32.0 > signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 11/11] drm/i915: Extract i915_module.c
On 27/07/2021 13:10, Daniel Vetter wrote:
The module init code is somewhat misplaced in i915_pci.c, since it
needs to pull in init/exit functions from every part of the driver and
pollutes the include list a lot.
Extract an i915_module.c file which pulls all the bits together, and
allows us to massively trim the include list of i915_pci.c.
The downside is that have to drop the error path check Jason added to
catch when we set up the pci driver too early. I think that risk is
acceptable for this pretty nice include.
i915_module.c is an improvement and the rest for me is not extremely
objectionable by the end of this incarnation, but I also do not see it
as an improvement really.
There was a bug to fix relating to mock tests, but that is where the
exercise should have stopped for now. After that it IMHO spiraled out of
control, not least the unjustifiably expedited removal of cache
shrinking. On balance for me it is too churny and boils down to two
extremely capable people spending time on kind of really unimportant
side fiddles. And I do not intend to prescribe you what to do, just
expressing my bewilderment. FWIW... I can only say my opinion as it, not
that it matters a lot.
Regards,
Tvrtko
Cc: Jason Ekstrand
Cc: Tvrtko Ursulin
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_module.c | 113
drivers/gpu/drm/i915/i915_pci.c| 117 +
drivers/gpu/drm/i915/i915_pci.h| 8 ++
4 files changed, 125 insertions(+), 114 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_module.c
create mode 100644 drivers/gpu/drm/i915/i915_pci.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9022dc638ed6..4ebd9f417ddb 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -38,6 +38,7 @@ i915-y += i915_drv.o \
i915_irq.o \
i915_getparam.o \
i915_mitigations.o \
+ i915_module.o \
i915_params.o \
i915_pci.o \
i915_scatterlist.o \
diff --git a/drivers/gpu/drm/i915/i915_module.c
b/drivers/gpu/drm/i915/i915_module.c
new file mode 100644
index ..c578ea8f56a0
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_module.c
@@ -0,0 +1,113 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include
+
+#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_object.h"
+#include "i915_active.h"
+#include "i915_buddy.h"
+#include "i915_params.h"
+#include "i915_pci.h"
+#include "i915_perf.h"
+#include "i915_request.h"
+#include "i915_scheduler.h"
+#include "i915_selftest.h"
+#include "i915_vma.h"
+
+static int i915_check_nomodeset(void)
+{
+ bool use_kms = true;
+
+ /*
+* Enable KMS by default, unless explicitly overriden by
+* either the i915.modeset prarameter or by the
+* vga_text_mode_force boot option.
+*/
+
+ if (i915_modparams.modeset == 0)
+ use_kms = false;
+
+ if (vgacon_text_force() && i915_modparams.modeset == -1)
+ use_kms = false;
+
+ if (!use_kms) {
+ /* Silently fail loading to not upset userspace. */
+ DRM_DEBUG_DRIVER("KMS disabled.\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+static const struct {
+ int (*init)(void);
+ void (*exit)(void);
+} init_funcs[] = {
+ { i915_check_nomodeset, NULL },
+ { i915_active_module_init, i915_active_module_exit },
+ { i915_buddy_module_init, i915_buddy_module_exit },
+ { i915_context_module_init, i915_context_module_exit },
+ { i915_gem_context_module_init, i915_gem_context_module_exit },
+ { i915_objects_module_init, i915_objects_module_exit },
+ { i915_request_module_init, i915_request_module_exit },
+ { i915_scheduler_module_init, i915_scheduler_module_exit },
+ { i915_vma_module_init, i915_vma_module_exit },
+ { i915_mock_selftests, NULL },
+ { i915_pmu_init, i915_pmu_exit },
+ { i915_register_pci_driver, i915_unregister_pci_driver },
+ { i915_perf_sysctl_register, i915_perf_sysctl_unregister },
+};
+static int init_progress;
+
+static int __init i915_init(void)
+{
+ int err, i;
+
+ for (i = 0; i < ARRAY_SIZE(init_funcs); i++) {
+ err = init_funcs[i].init();
+ if (err < 0) {
+ while (i--) {
+ if (init_funcs[i].exit)
+ init_funcs[i].exit();
+ }
+ return err;
+ } else if (err > 0) {
+ /*
+* Early-exit success is reserved for things which
+* don't have an exit() function because we have no
+* idea how far they got or how to partially tear
+*
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/adlp: Add workaround to disable CMTG clock gating
== Series Details == Series: drm/i915/adlp: Add workaround to disable CMTG clock gating URL : https://patchwork.freedesktop.org/series/93067/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9cf8974d9e83 drm/i915/adlp: Add workaround to disable CMTG clock gating -:34: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t' #34: FILE: drivers/gpu/drm/i915/display/intel_display.c:13203: + uint32_t val; -:48: CHECK:SPACING: spaces preferred around that '&' (ctx:WxO) #48: FILE: drivers/gpu/drm/i915/display/intel_display.c:13217: + drm_WARN_ON(_priv->drm, val &~ DISABLE_DPT_CLK_GATING); ^ -:48: ERROR:SPACING: space prohibited after that '~' (ctx:OxW) #48: FILE: drivers/gpu/drm/i915/display/intel_display.c:13217: + drm_WARN_ON(_priv->drm, val &~ DISABLE_DPT_CLK_GATING); ^ total: 1 errors, 0 warnings, 2 checks, 33 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,01/11] drm/i915: Check for nomodeset in i915_init() first
== Series Details ==
Series: series starting with [v2,01/11] drm/i915: Check for nomodeset in
i915_init() first
URL : https://patchwork.freedesktop.org/series/93066/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10404 -> Patchwork_20715
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/index.html
Known issues
Here are the changes found in Patchwork_20715 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +29 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: NOTRUN -> [WARN][2] ([i915#3718])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html
* igt@i915_pm_rpm@basic-rte:
- fi-bdw-5557u: NOTRUN -> [FAIL][3] ([i915#579])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/fi-bdw-5557u/igt@i915_pm_...@basic-rte.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][4] -> [FAIL][5] ([i915#1372])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
- fi-bdw-5557u: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Participating hosts (40 -> 35)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-jsl-1 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_10404 -> Patchwork_20715
CI-20190529: 20190529
CI_DRM_10404: 371bd54db63fdd99356a1a3d0fdc9b76616eddcb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6153: a5dffe7499a2f7189718ddf1ccf49060b7c1529d @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20715: e3aa4c53ca1e1c5676978e68a9f6d0125eec7ae9 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e3aa4c53ca1e drm/i915: Extract i915_module.c
0d4a676a47a4 drm/i915: Remove i915_globals
2567a687274b drm/i915: move vma slab to direct module init/exit
1eefc0331fde drm/i915: move scheduler slabs to direct module init/exit
9547d213ca53 drm/i915: move request slabs to direct module init/exit
d8736bba255c drm/i915: move gem_objects slab to direct module init/exit
591b60d8aad3 drm/i915: move gem_context slab to direct module init/exit
68a6ff81e0d6 drm/i915: move intel_context slab to direct module init/exit
d56d75be6b62 drm/i915: move i915_buddy slab to direct module init/exit
2f47345a0149 drm/i915: move i915_active slab to direct module init/exit
526b1246de6a drm/i915: Check for nomodeset in i915_init() first
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20715/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/display: Disable audio, DRRS and PSR before planes
Looks good to me.
Reviewed-by: Gwan-gyeong Mun
On 7/26/21 9:15 PM, José Roberto de Souza wrote:
HDMI and DisplayPort sequences states that audio and PSR should be
disabled before planes are disabled.
Not following it did not caused any problems up to Alderlake-P but
for this platform it causes underruns during the PSR2 disable
sequence.
Specification don't mention that DRRS should be disabled before planes
but it looks safer to switch back to the default refresh rate before
following with the rest of the pipe disable sequence.
BSpec: 49191
BSpec: 49190
Cc: Ville Syrjälä
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 30 ---
drivers/gpu/drm/i915/display/intel_display.c | 24 +++
.../drm/i915/display/intel_display_types.h| 4 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 14 +++--
4 files changed, 59 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 26a3aa73fcc43..061a663f43b84 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3204,12 +3204,6 @@ static void intel_disable_ddi_dp(struct
intel_atomic_state *state,
intel_dp->link_trained = false;
- if (old_crtc_state->has_audio)
- intel_audio_codec_disable(encoder,
- old_crtc_state, old_conn_state);
-
- intel_edp_drrs_disable(intel_dp, old_crtc_state);
- intel_psr_disable(intel_dp, old_crtc_state);
intel_edp_backlight_off(old_conn_state);
/* Disable the decompression in DP Sink */
intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
@@ -3227,10 +3221,6 @@ static void intel_disable_ddi_hdmi(struct
intel_atomic_state *state,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct drm_connector *connector = old_conn_state->connector;
- if (old_crtc_state->has_audio)
- intel_audio_codec_disable(encoder,
- old_crtc_state, old_conn_state);
-
if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
false, false))
drm_dbg_kms(>drm,
@@ -3238,6 +3228,25 @@ static void intel_disable_ddi_hdmi(struct
intel_atomic_state *state,
connector->base.id, connector->name);
}
+static void intel_pre_disable_ddi(struct intel_atomic_state *state,
+ struct intel_encoder *encoder,
+ const struct intel_crtc_state *old_crtc_state,
+ const struct drm_connector_state
*old_conn_state)
+{
+ struct intel_dp *intel_dp;
+
+ if (old_crtc_state->has_audio)
+ intel_audio_codec_disable(encoder, old_crtc_state,
+ old_conn_state);
+
+ if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
+ return;
+
+ intel_dp = enc_to_intel_dp(encoder);
+ intel_edp_drrs_disable(intel_dp, old_crtc_state);
+ intel_psr_disable(intel_dp, old_crtc_state);
+}
+
static void intel_disable_ddi(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -4590,6 +4599,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
encoder->enable = intel_enable_ddi;
encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
encoder->pre_enable = intel_ddi_pre_enable;
+ encoder->pre_disable = intel_pre_disable_ddi;
encoder->disable = intel_disable_ddi;
encoder->post_disable = intel_ddi_post_disable;
encoder->update_pipe = intel_ddi_update_pipe;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index bb0aebcc3ecd3..cf58df9132748 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3195,6 +3195,28 @@ static void intel_encoders_enable(struct
intel_atomic_state *state,
}
}
+static void intel_encoders_pre_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct drm_connector_state *old_conn_state;
+ struct drm_connector *conn;
+ int i;
+
+ for_each_old_connector_in_state(>base, conn, old_conn_state, i) {
+ struct intel_encoder *encoder =
+ to_intel_encoder(old_conn_state->best_encoder);
+
+ if (old_conn_state->crtc != >base)
+ continue;
+
+ if (encoder->pre_disable)
+
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,01/11] drm/i915: Check for nomodeset in i915_init() first
== Series Details == Series: series starting with [v2,01/11] drm/i915: Check for nomodeset in i915_init() first URL : https://patchwork.freedesktop.org/series/93066/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1900:21:expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1900:21:got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1900:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_context.c:1409:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1409:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1409:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:expected struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:got struct i915_address_space * +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1402:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1210:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_perf.c:1443:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1497:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,01/11] drm/i915: Check for nomodeset in i915_init() first
== Series Details == Series: series starting with [v2,01/11] drm/i915: Check for nomodeset in i915_init() first URL : https://patchwork.freedesktop.org/series/93066/ State : warning == Summary == $ dim checkpatch origin/drm-tip 526b1246de6a drm/i915: Check for nomodeset in i915_init() first -:32: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 10 lines checked 2f47345a0149 drm/i915: move i915_active slab to direct module init/exit -:177: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 126 lines checked d56d75be6b62 drm/i915: move i915_buddy slab to direct module init/exit -:135: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 92 lines checked 68a6ff81e0d6 drm/i915: move intel_context slab to direct module init/exit -:150: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 102 lines checked 591b60d8aad3 drm/i915: move gem_context slab to direct module init/exit -:84: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 0) #84: FILE: drivers/gpu/drm/i915/gem/i915_gem_context.h:224: for (i915_gem_engines_iter_init(&(it), (engines)); \ [...] +void i915_gem_context_module_exit(void); -:144: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 2 warnings, 0 checks, 98 lines checked d8736bba255c drm/i915: move gem_objects slab to direct module init/exit -:135: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 89 lines checked 9547d213ca53 drm/i915: move request slabs to direct module init/exit -:192: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #192: FILE: drivers/gpu/drm/i915/i915_request.c:2103: + slab_execute_cbs = KMEM_CACHE(execute_cb, SLAB_HWCACHE_ALIGN | -:218: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 1 warnings, 1 checks, 167 lines checked 1eefc0331fde drm/i915: move scheduler slabs to direct module init/exit -:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #10: noise with removing the static global.slab_dependencies|priorities to just a -:150: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #150: FILE: drivers/gpu/drm/i915/i915_scheduler.c:483: + slab_dependencies = KMEM_CACHE(i915_dependency, SLAB_HWCACHE_ALIGN | -:181: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 2 warnings, 1 checks, 132 lines checked 2567a687274b drm/i915: move vma slab to direct module init/exit -:145: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 96 lines checked 0d4a676a47a4 drm/i915: Remove i915_globals -:36: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #36: deleted file mode 100644 -:144: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 2 warnings, 0 checks, 28 lines checked e3aa4c53ca1e drm/i915: Extract i915_module.c -:34: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #34: new file mode 100644 -:39: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #39: FILE: drivers/gpu/drm/i915/i915_module.c:1: +/* -:40: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #40: FILE: drivers/gpu/drm/i915/i915_module.c:2: + * SPDX-License-Identifier: MIT -:64: WARNING:TYPO_SPELLING: 'overriden' may be misspelled - perhaps 'overridden'? #64: FILE: drivers/gpu/drm/i915/i915_module.c:26: +* Enable KMS by default, unless explicitly overriden by ^ -:85: WARNING:LEADING_SPACE: please, no spaces at the start of a line #85: FILE: drivers/gpu/drm/i915/i915_module.c:47: + int (*init)(void);$ -:86: WARNING:LEADING_SPACE: please, no spaces at the start of a line #86: FILE:
Re: [Intel-gfx] [PATCH 05/15] drm/i915/guc/slpc: Allocate, initialize and release SLPC
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Allocate data structures for SLPC and functions for
> initializing on host side.
>
> v2: Address review comments (Michal W)
> v3: Remove unnecessary header includes (Michal W)
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 11 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 36 ++-
> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 2 ++
> 3 files changed, 48 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 5b0f8c541b69..13d162353b1a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -336,6 +336,12 @@ int intel_guc_init(struct intel_guc *guc)
> goto err_ct;
> }
>
> + if (intel_guc_slpc_is_used(guc)) {
> + ret = intel_guc_slpc_init(>slpc);
> + if (ret)
> + goto err_submission;
> + }
> +
> /* now that everything is perma-pinned, initialize the parameters */
> guc_init_params(guc);
>
> @@ -346,6 +352,8 @@ int intel_guc_init(struct intel_guc *guc)
>
> return 0;
>
> +err_submission:
> + intel_guc_submission_fini(guc);
> err_ct:
> intel_guc_ct_fini(>ct);
> err_ads:
> @@ -368,6 +376,9 @@ void intel_guc_fini(struct intel_guc *guc)
>
> i915_ggtt_disable_guc(gt->ggtt);
>
> + if (intel_guc_slpc_is_used(guc))
> + intel_guc_slpc_fini(>slpc);
> +
> if (intel_guc_submission_is_used(guc))
> intel_guc_submission_fini(guc);
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index 7275100ef8f8..bae4e33db0f8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -12,6 +12,16 @@ static inline struct intel_guc *slpc_to_guc(struct
> intel_guc_slpc *slpc)
> return container_of(slpc, struct intel_guc, slpc);
> }
>
> +static inline struct intel_gt *slpc_to_gt(struct intel_guc_slpc *slpc)
> +{
> + return guc_to_gt(slpc_to_guc(slpc));
> +}
> +
> +static inline struct drm_i915_private *slpc_to_i915(struct intel_guc_slpc
> *slpc)
> +{
> + return slpc_to_gt(slpc)->i915;
> +}
> +
> static bool __detect_slpc_supported(struct intel_guc *guc)
> {
> /* GuC SLPC is unavailable for pre-Gen12 */
> @@ -35,11 +45,35 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc
> *slpc)
> guc->slpc_selected = __guc_slpc_selected(guc);
> }
>
> +static int slpc_shared_data_init(struct intel_guc_slpc *slpc)
> +{
> + struct intel_guc *guc = slpc_to_guc(slpc);
> + struct drm_i915_private *i915 = slpc_to_i915(slpc);
> + u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
> + int err;
> +
> + err = intel_guc_allocate_and_map_vma(guc, size, >vma, (void
> **)>vaddr);
> + if (unlikely(err)) {
> + drm_err(>drm,
> + "Failed to allocate SLPC struct (err=%pe)\n",
> + ERR_PTR(err));
> + return err;
> + }
> +
> + return err;
> +}
> +
> int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
> {
> - return 0;
> + GEM_BUG_ON(slpc->vma);
> +
> + return slpc_shared_data_init(slpc);
> }
>
> void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
> {
> + if (!slpc->vma)
> + return;
> +
> + i915_vma_unpin_and_release(>vma, I915_VMA_RELEASE_MAP);
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> index bfe4a7f9ce15..edcf4c05bd9f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> @@ -7,6 +7,8 @@
> #define _INTEL_GUC_SLPC_TYPES_H_
>
> struct intel_guc_slpc {
> + struct i915_vma *vma;
> + struct slpc_shared_data *vaddr;
> };
>
> #endif
>
Reviewed-by: Michal Wajdeczko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 3/5] drm/print: RFC add choice to use dynamic debug in drm-debug
On Thu, Jul 22, 2021 at 11:20 AM Sean Paul wrote:
>
Reply-all fail. Adding everyone else back to my response.
> On Tue, Jul 20, 2021 at 03:29:34PM +0200, Daniel Vetter wrote:
> > On Wed, Jul 14, 2021 at 11:51:36AM -0600, Jim Cromie wrote:
> > > drm's debug system uses distinct categories of debug messages, encoded
> > > in an enum (DRM_UT_), which are mapped to bits in drm.debug.
> > > drm_debug_enabled() does a lot of unlikely bit-mask checks on
> > > drm.debug; we can use dynamic debug instead, and get all that
> > > static_key/jump_label goodness.
>
> Hi Jim,
> Thanks for your patches! Daniel pointed me at them in response to my drm_trace
> patchset (https://patchwork.freedesktop.org/series/78133/). I'd love to get
> your
> input on it. I think the 2 sets are mostly compatible, we'd just need to keep
> drm_dev_dbg and do the CONFIG check in the function beside the trace_enabled
> checks.
>
> > >
> > > Dynamic debug has no concept of category, but we can map the DRM_UT_*
> > > to a set of distinct prefixes; "drm:core:", "drm:kms:" etc, and
> > > prepend them to the given formats.
> > >
> > > Then we can use:
> > > `echo module drm format ^drm:core: +p > control`
> > >
> > > to enable every such "prefixed" pr_debug with one query. This new
> > > prefix changes pr_debug's output, so is user visible, but it seems
> > > unlikely to cause trouble for log watchers; they're not relying on the
> > > absence of class prefix strings.
> > >
> > > This conversion yields ~2100 new callsites on my i7/i915 laptop:
> > >
> > > dyndbg: 195 debug prints in module drm_kms_helper
> > > dyndbg: 298 debug prints in module drm
> > > dyndbg: 1630 debug prints in module i915
> > >
> > > CONFIG_DRM_USE_DYNAMIC_DEBUG enables this, and is available if
> > > CONFIG_DYNAMIC_DEBUG or CONFIG_DYNAMIC_DEBUG_CORE is chosen, and if
> > > CONFIG_JUMP_LABEL is enabled; this because its required to get the
> > > promised optimizations.
> > >
> > > The indirection/switchover is layered into the macro scheme:
> > >
> > > 0. A new callback on drm.debug which calls dynamic_debug_exec_queries
> > >to map those bits to specific query/commands
> > >dynamic_debug_exec_queries("format ^drm:kms: +p", "drm*");
> > >here for POC, this should be in dynamic_debug.c
> > >with a MODULE_PARAM_DEBUG_BITMAP(__drm_debug, { "prefix-1", "desc-1"
> > > }+)
> >
> > This is really awesome.
>
>
> Agreed, this is a very clever way of merging the 2 worlds!
>
>
> > For merging I think we need to discuss with dyn
> > debug folks whether they're all ok with this, but it's exported already
> > should should be fine.
>
> I wonder if this is a good time to reconsider our drm categories. IMO they're
> overly broad and it's hard to get the right information without subscribing to
> the firehose. It seems like dyndbg might be a good opportunity to unlock
> subcategories of log messages.
>
> More concretely, on CrOS we can't subscribe to atomic or state categories
> since
> they're too noisy. However if there was a "fail" subcategory which dumped
> state/atomic logs on check failures, that would be really compelling.
> Something
> like:
>
> drm:atomic:fail vs. drm:atomic
>
> Both would be picked up if (drm.debug & DRM_DBG_ATOMIC), however it would
> allow
> dyndbg-aware clients to get better logs without having a huge table of
> individual log signatures.
>
> I'm not sure how tightly we'd want to control the subcategories. It could be
> strict like the categories spelled out in drm_print.h, or an open prefix arg
> to
> drm_dev_dbg. I suspect we'd want the former, but would want to be careful to
> provide enough flexibility to properly
>
> Of course, none of this needs to be decided to land this initial support, it
> can
> be bolted on later easily enough (I think).
>
>
> >
> > >
> > > 1. A "converted" or "classy" DRM_UT_* map
> > >
> > >based on: DRM_UT_* ( symbol => bit-mask )
> > >named it: cDRM_UT_* ( symbol => format-class-prefix-string )
> > >
> > >So cDRM_UT_* is either:
> > >legacy: cDRM_UT_* <-- DRM_UT_* ( !CONFIG_DRM_USE_DYNAMIC_DEBUG )
> > >enabled:
> > > #define cDRM_UT_KMS"drm:kms: "
> > > #define cDRM_UT_PRIME "drm:prime: "
> > > #define cDRM_UT_ATOMIC "drm:atomic: "
> >
> > the cDRM looks a bit funny, plus I don't eve have an idea what _UT_ means
> > (and git history isn't helpful either). What about just using
> > DRM_DBG_CLASS_ as the prefix here for these indirection macros, i.e.
> > DRM_DBG_CLASS_KMS.
> >
> > Also would be really nice if we could make these a table or something, but
> > I guess with the macro magic that's not possible.
> >
> > >
> > >DRM_UT_* are unchanged, since theyre used in drm_debug_enabled()
> > >and elsewhere.
> >
> > I think for the production version of these we need to retire/deprecate
> > them, at least for drm core. Otherwise you have an annoying mismatch
> > between drm.debug module option and dyn debug.
> >
> > >
> > > 2. drm_dev_dbg &
Re: [Intel-gfx] [PATCH 04/15] drm/i915/guc/slpc: Adding SLPC communication interfaces
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Add constants and params that are needed to configure SLPC.
>
> v2: Add a new abi header for SLPC. Replace bitfields with
> genmasks. Address other comments from Michal W.
>
> v3: Add slpc H2G format in abi, other review commments (Michal W)
>
> v4: Update status bits according to latest spec
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
> ---
> .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 1 -
> .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 235 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 3 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 7 +
> 4 files changed, 245 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> index d832c8f11c11..ca538e5de940 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> @@ -135,7 +135,6 @@ enum intel_guc_action {
> INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007,
> INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,
> INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
> - INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
> INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
> INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
> INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
> new file mode 100644
> index ..70b300d4a536
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
> @@ -0,0 +1,235 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#ifndef _GUC_ACTIONS_SLPC_ABI_H_
> +#define _GUC_ACTIONS_SLPC_ABI_H_
> +
> +#include
> +
> +/**
> + * DOC: SLPC SHARED DATA STRUCTURE
> + *
> + *
> ++--+--+
> + * | CL | Bytes| Description
> |
> + *
> ++==+==+
> + * | 1 | 0-3 | SHARED DATA SIZE
> |
> + * |
> +--+--+
> + * || 4-7 | GLOBAL STATE
> |
> + * |
> +--+--+
> + * || 8-11 | DISPLAY DATA ADDRESS
> |
> + * |
> +--+--+
> + * || 12:63| PADDING
> |
> + *
> ++--+--+
> + * || 0:63 | PADDING(PLATFORM INFO)
> |
> + *
> ++--+--+
> + * | 3 | 0-3 | TASK STATE DATA
> |
> + * +
> +--+--+
> + * || 4:63 | PADDING
> |
> + *
> ++--+--+
> + * |4-21|0:1087| OVERRIDE PARAMS AND BIT FIELDS
> |
> + *
> ++--+--+
> + * || | PADDING + EXTRA RESERVED PAGE
> |
> + *
> ++--+--+
> + */
> +
> +/*
> + * SLPC exposes certain parameters for global configuration by the host.
> + * These are referred to as override parameters, because in most cases
> + * the host will not need to modify the default values used by SLPC.
> + * SLPC remembers the default values which allows the host to easily restore
> + * them by simply unsetting the override. The host can set or unset override
> + * parameters during SLPC (re-)initialization using the SLPC Reset event.
> + * The host can also set or unset override parameters on the fly using the
> + * Parameter Set and Parameter Unset events
> + */
> +
> +#define SLPC_MAX_OVERRIDE_PARAMETERS 256
> +#define SLPC_OVERRIDE_BITFIELD_SIZE \
> + (SLPC_MAX_OVERRIDE_PARAMETERS / 32)
> +
> +#define SLPC_PAGE_SIZE_BYTES 4096
> +#define SLPC_CACHELINE_SIZE_BYTES64
> +#define SLPC_SHARED_DATA_SIZE_BYTE_HEADERSLPC_CACHELINE_SIZE_BYTES
> +#define SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO
> SLPC_CACHELINE_SIZE_BYTES
> +#define SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE
> SLPC_CACHELINE_SIZE_BYTES
> +#define
Re: [Intel-gfx] [PATCH v3 3/5] drm/print: RFC add choice to use dynamic debug in drm-debug
On Tue, Jul 20, 2021 at 03:29:34PM +0200, Daniel Vetter wrote:
> On Wed, Jul 14, 2021 at 11:51:36AM -0600, Jim Cromie wrote:
> > drm's debug system uses distinct categories of debug messages, encoded
> > in an enum (DRM_UT_), which are mapped to bits in drm.debug.
> > drm_debug_enabled() does a lot of unlikely bit-mask checks on
> > drm.debug; we can use dynamic debug instead, and get all that
> > static_key/jump_label goodness.
Hi Jim,
Thanks for your patches! Daniel pointed me at them in response to my drm_trace
patchset (https://patchwork.freedesktop.org/series/78133/). I'd love to get your
input on it. I think the 2 sets are mostly compatible, we'd just need to keep
drm_dev_dbg and do the CONFIG check in the function beside the trace_enabled
checks.
> >
> > Dynamic debug has no concept of category, but we can map the DRM_UT_*
> > to a set of distinct prefixes; "drm:core:", "drm:kms:" etc, and
> > prepend them to the given formats.
> >
> > Then we can use:
> > `echo module drm format ^drm:core: +p > control`
> >
> > to enable every such "prefixed" pr_debug with one query. This new
> > prefix changes pr_debug's output, so is user visible, but it seems
> > unlikely to cause trouble for log watchers; they're not relying on the
> > absence of class prefix strings.
> >
> > This conversion yields ~2100 new callsites on my i7/i915 laptop:
> >
> > dyndbg: 195 debug prints in module drm_kms_helper
> > dyndbg: 298 debug prints in module drm
> > dyndbg: 1630 debug prints in module i915
> >
> > CONFIG_DRM_USE_DYNAMIC_DEBUG enables this, and is available if
> > CONFIG_DYNAMIC_DEBUG or CONFIG_DYNAMIC_DEBUG_CORE is chosen, and if
> > CONFIG_JUMP_LABEL is enabled; this because its required to get the
> > promised optimizations.
> >
> > The indirection/switchover is layered into the macro scheme:
> >
> > 0. A new callback on drm.debug which calls dynamic_debug_exec_queries
> >to map those bits to specific query/commands
> >dynamic_debug_exec_queries("format ^drm:kms: +p", "drm*");
> >here for POC, this should be in dynamic_debug.c
> >with a MODULE_PARAM_DEBUG_BITMAP(__drm_debug, { "prefix-1", "desc-1" }+)
>
> This is really awesome.
Agreed, this is a very clever way of merging the 2 worlds!
> For merging I think we need to discuss with dyn
> debug folks whether they're all ok with this, but it's exported already
> should should be fine.
I wonder if this is a good time to reconsider our drm categories. IMO they're
overly broad and it's hard to get the right information without subscribing to
the firehose. It seems like dyndbg might be a good opportunity to unlock
subcategories of log messages.
More concretely, on CrOS we can't subscribe to atomic or state categories since
they're too noisy. However if there was a "fail" subcategory which dumped
state/atomic logs on check failures, that would be really compelling. Something
like:
drm:atomic:fail vs. drm:atomic
Both would be picked up if (drm.debug & DRM_DBG_ATOMIC), however it would allow
dyndbg-aware clients to get better logs without having a huge table of
individual log signatures.
I'm not sure how tightly we'd want to control the subcategories. It could be
strict like the categories spelled out in drm_print.h, or an open prefix arg to
drm_dev_dbg. I suspect we'd want the former, but would want to be careful to
provide enough flexibility to properly
Of course, none of this needs to be decided to land this initial support, it can
be bolted on later easily enough (I think).
>
> >
> > 1. A "converted" or "classy" DRM_UT_* map
> >
> >based on: DRM_UT_* ( symbol => bit-mask )
> >named it: cDRM_UT_* ( symbol => format-class-prefix-string )
> >
> >So cDRM_UT_* is either:
> >legacy: cDRM_UT_* <-- DRM_UT_* ( !CONFIG_DRM_USE_DYNAMIC_DEBUG )
> >enabled:
> > #define cDRM_UT_KMS"drm:kms: "
> > #define cDRM_UT_PRIME "drm:prime: "
> > #define cDRM_UT_ATOMIC "drm:atomic: "
>
> the cDRM looks a bit funny, plus I don't eve have an idea what _UT_ means
> (and git history isn't helpful either). What about just using
> DRM_DBG_CLASS_ as the prefix here for these indirection macros, i.e.
> DRM_DBG_CLASS_KMS.
>
> Also would be really nice if we could make these a table or something, but
> I guess with the macro magic that's not possible.
>
> >
> >DRM_UT_* are unchanged, since theyre used in drm_debug_enabled()
> >and elsewhere.
>
> I think for the production version of these we need to retire/deprecate
> them, at least for drm core. Otherwise you have an annoying mismatch
> between drm.debug module option and dyn debug.
>
> >
> > 2. drm_dev_dbg & drm_debug are renamed (prefixed with '_')
> >
> >old names are now macros, calling either:
> > legacy: -> to renamed fn
> > enabled: -> dev_dbg & pr_debug, with cDRM-prefix # format.
> >
> >these names are used in a fat layer of macros (3) which supply the
> >category; those macros are used throughout drm
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,01/28] drm/i915/display: remove PORT_F workaround for CNL
== Series Details ==
Series: series starting with [CI,01/28] drm/i915/display: remove PORT_F
workaround for CNL
URL : https://patchwork.freedesktop.org/series/93056/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10399_full -> Patchwork_20713_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20713_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20713_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20713_full:
### IGT changes ###
Possible regressions
* igt@kms_flip@flip-vs-suspend@a-vga1:
- shard-snb: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-snb7/igt@kms_flip@flip-vs-susp...@a-vga1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20713/shard-snb2/igt@kms_flip@flip-vs-susp...@a-vga1.html
* igt@kms_universal_plane@universal-plane-pipe-b-sanity:
- shard-glk: [PASS][3] -> [FAIL][4] +23 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-glk7/igt@kms_universal_pl...@universal-plane-pipe-b-sanity.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20713/shard-glk9/igt@kms_universal_pl...@universal-plane-pipe-b-sanity.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@dpms-non-lpsp:
- {shard-rkl}:NOTRUN -> [SKIP][5] +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20713/shard-rkl-2/igt@i915_pm_...@dpms-non-lpsp.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- {shard-rkl}:NOTRUN -> [DMESG-WARN][6]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20713/shard-rkl-6/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html
### Piglit changes ###
Possible regressions
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-double_dmat4x3-int_ivec3_array3-position
(NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][7] +7 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20713/pig-icl-1065g7/spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-double_dmat4x3-int_ivec3_array3-position.html
New tests
-
New tests have been introduced between CI_DRM_10399_full and
Patchwork_20713_full:
### New Piglit tests (8) ###
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-double_dmat4x3-int_ivec3_array3-position:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_vec3-position-double_dmat4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat3x4-float_mat3x2_array3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dvec4_array5-uint_uvec2_array3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-float_mat3x2-double_dmat3x4_array2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-ushort_uvec4-double_dmat4x2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-ubyte_uvec2-position-short_ivec4-double_dmat4x2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-uint_uint-double_dmat4x2-position:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_20713_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][8] -> [SKIP][9] ([i915#658])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-iclb2/igt@feature_discov...@psr2.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20713/shard-iclb5/igt@feature_discov...@psr2.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][10] -> [TIMEOUT][11] ([i915#2369] /
[i915#3063] / [i915#3648])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-tglb2/igt@gem_...@unwedge-stress.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20713/shard-tglb2/igt@gem_...@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#2846])
[12]:
[Intel-gfx] [PATCH] drm/i915/adlp: Add workaround to disable CMTG clock gating
The driver doesn't depend atm on the common mode timing generator
functionality (it would be used for some power saving feature and panel
timing synchronization), however DMC will corrupt the CMTG registers
across DC5 entry/exit sequences unless the CMTG clock gating is
disabled. This in turn can lead to at least the DPLL0/1 configuration
getting stuck at their last state, which means we can't reprogram them
to a new config.
Add the corresponding Bspec workaround to prevent the above.
Cc: Uma Shankar
Cc: José Roberto de Souza
Cc: Anshuman Gupta
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 18 ++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index bb0aebcc3ecd3..474d723a37454 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13198,6 +13198,24 @@ static void intel_early_display_was(struct
drm_i915_private *dev_priv)
KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
KBL_ARB_FILL_SPARE_14);
}
+
+ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+ uint32_t val;
+
+ /*
+* Wa_16011069516:adl-p[a0]
+*
+* All CMTG regs are unreliable until CMTG clock gating is
+* disabled, so we can only assume the default CMTG_CHICKEN
+* reg value and sanity check this assumption with a double
+* read, which presumably returns the correct value even with
+* clock gating on.
+*/
+ val = intel_de_read(dev_priv, TRANS_CMTG_CHICKEN);
+ val = intel_de_read(dev_priv, TRANS_CMTG_CHICKEN);
+ intel_de_write(dev_priv, TRANS_CMTG_CHICKEN,
DISABLE_DPT_CLK_GATING);
+ drm_WARN_ON(_priv->drm, val &~ DISABLE_DPT_CLK_GATING);
+ }
}
static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c41f9083e2338..e02bd75dd1064 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10208,6 +10208,9 @@ enum skl_power_gate {
#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
#define PORT_SYNC_MODE_MASTER_SELECT(x)
REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
+#define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
+#define DISABLE_DPT_CLK_GATINGREG_BIT(1)
+
/* DisplayPort Transport Control */
#define _DP_TP_CTL_A 0x64040
#define _DP_TP_CTL_B 0x64140
--
2.27.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/15] drm/i915/guc/slpc: Initial definitions for SLPC
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Add macros to check for SLPC support. This feature is currently supported
> for Gen12+ and enabled whenever GuC submission is enabled/selected.
>
> Include templates for SLPC init/fini and enable.
>
> v2: Move SLPC helper functions to intel_guc_slpc.c/.h. Define basic
> template for SLPC structure in intel_guc_slpc_types.h. Fix copyright (Michal
> W)
>
> v3: Review comments (Michal W)
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
> Signed-off-by: Daniele Ceraolo Spurio
>
> drm/i915/guc/slpc: Lay out slpc init/enable/fini
>
> Declare init/fini and enable function templates.
>
> v2: Rebase
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 45 +++
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 33 ++
> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 12 +
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 ++-
> drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 +
> 8 files changed, 103 insertions(+), 2 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index ab7679957623..d8eac4468df9 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \
> gt/uc/intel_guc_fw.o \
> gt/uc/intel_guc_log.o \
> gt/uc/intel_guc_log_debugfs.o \
> + gt/uc/intel_guc_slpc.o \
> gt/uc/intel_guc_submission.o \
> gt/uc/intel_huc.o \
> gt/uc/intel_huc_debugfs.o \
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 979128e28372..39bc3c16057b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -7,6 +7,7 @@
> #include "gt/intel_gt_irq.h"
> #include "gt/intel_gt_pm_irq.h"
> #include "intel_guc.h"
> +#include "intel_guc_slpc.h"
> #include "intel_guc_ads.h"
> #include "intel_guc_submission.h"
> #include "i915_drv.h"
> @@ -157,6 +158,7 @@ void intel_guc_init_early(struct intel_guc *guc)
> intel_guc_ct_init_early(>ct);
> intel_guc_log_init_early(>log);
> intel_guc_submission_init_early(guc);
> + intel_guc_slpc_init_early(>slpc);
>
> mutex_init(>send_mutex);
> spin_lock_init(>irq_lock);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index a9547069ee7e..15ad2eaee473 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -15,6 +15,7 @@
> #include "intel_guc_ct.h"
> #include "intel_guc_log.h"
> #include "intel_guc_reg.h"
> +#include "intel_guc_slpc_types.h"
> #include "intel_uc_fw.h"
> #include "i915_utils.h"
> #include "i915_vma.h"
> @@ -30,6 +31,7 @@ struct intel_guc {
> struct intel_uc_fw fw;
> struct intel_guc_log log;
> struct intel_guc_ct ct;
> + struct intel_guc_slpc slpc;
>
> /* Global engine used to submit requests to GuC */
> struct i915_sched_engine *sched_engine;
> @@ -57,6 +59,8 @@ struct intel_guc {
>
> bool submission_supported;
> bool submission_selected;
> + bool slpc_supported;
> + bool slpc_selected;
(I know that you were following existing code, but we might do better
and since you have to resend it anyway without patch 1/15 ...)
as we have here:
+ struct intel_guc_slpc slpc;
then maybe both supported/selected shall be moved there as:
struct intel_guc_slpc {
+ bool supported;
+ bool selected;
};
so the struct wont be empty any more, with that fixed:
Reviewed-by: Michal Wajdeczko
>
> struct i915_vma *ads_vma;
> struct __guc_ads_blob *ads_blob;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> new file mode 100644
> index ..7275100ef8f8
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -0,0 +1,45 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_guc_slpc.h"
> +#include "gt/intel_gt.h"
> +
> +static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
> +{
> + return container_of(slpc, struct intel_guc, slpc);
> +}
> +
> +static bool __detect_slpc_supported(struct intel_guc *guc)
> +{
> + /* GuC SLPC is unavailable for pre-Gen12 */
> + return guc->submission_supported &&
> + GRAPHICS_VER(guc_to_gt(guc)->i915) >=
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix the 12 BPC bits for PIPE_MISC reg (rev2)
== Series Details == Series: drm/i915: Fix the 12 BPC bits for PIPE_MISC reg (rev2) URL : https://patchwork.freedesktop.org/series/92690/ State : success == Summary == CI Bug Log - changes from CI_DRM_10403 -> Patchwork_20714 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/index.html Known issues Here are the changes found in Patchwork_20714 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +29 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@core_auth@basic-auth: - fi-kbl-soraka: [PASS][2] -> [DMESG-WARN][3] ([i915#1982]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10403/fi-kbl-soraka/igt@core_a...@basic-auth.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/fi-kbl-soraka/igt@core_a...@basic-auth.html * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][4] ([i915#3718]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html * igt@gem_exec_suspend@basic-s0: - fi-kbl-soraka: [PASS][5] -> [INCOMPLETE][6] ([i915#155]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10403/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html * igt@i915_pm_rpm@basic-rte: - fi-bdw-5557u: NOTRUN -> [FAIL][7] ([i915#579]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/fi-bdw-5557u/igt@i915_pm_...@basic-rte.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][8] -> [FAIL][9] ([i915#1372]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10403/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html - fi-bdw-5557u: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 Participating hosts (40 -> 35) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-jsl-1 fi-bdw-samus Build changes - * Linux: CI_DRM_10403 -> Patchwork_20714 CI-20190529: 20190529 CI_DRM_10403: 7f637979f31e7dc1d2cd422f63df18f307d477b3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6153: a5dffe7499a2f7189718ddf1ccf49060b7c1529d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20714: 921d552b1d0bcddbb6f6a690ea43fc89f30e3c7e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 921d552b1d0b drm/i915: Fix the 12 BPC bits for PIPE_MISC reg == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20714/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/3] drm: use the lookup lock in drm_is_current_master
On Sat, Jul 24, 2021 at 07:18:22PM +0800, Desmond Cheong Zhi Xi wrote:
> Inside drm_is_current_master, using the outer drm_device.master_mutex
> to protect reads of drm_file.master makes the function prone to creating
> lock hierarchy inversions. Instead, we can use the
> drm_file.master_lookup_lock that sits at the bottom of the lock
> hierarchy.
>
> Reported-by: Daniel Vetter
> Signed-off-by: Desmond Cheong Zhi Xi
> Reviewed-by: Daniel Vetter
Applied to drm-misc-next, thanks for your patch.
-Daniel
> ---
> drivers/gpu/drm/drm_auth.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c
> index f00354bec3fb..9c24b8cc8e36 100644
> --- a/drivers/gpu/drm/drm_auth.c
> +++ b/drivers/gpu/drm/drm_auth.c
> @@ -63,8 +63,9 @@
>
> static bool drm_is_current_master_locked(struct drm_file *fpriv)
> {
> - lockdep_assert_held_once(>minor->dev->master_mutex);
> -
> + /* Either drm_device.master_mutex or drm_file.master_lookup_lock
> + * should be held here.
> + */
> return fpriv->is_master && drm_lease_owner(fpriv->master) ==
> fpriv->minor->dev->master;
> }
>
> @@ -82,9 +83,9 @@ bool drm_is_current_master(struct drm_file *fpriv)
> {
> bool ret;
>
> - mutex_lock(>minor->dev->master_mutex);
> + spin_lock(>master_lookup_lock);
> ret = drm_is_current_master_locked(fpriv);
> - mutex_unlock(>minor->dev->master_mutex);
> + spin_unlock(>master_lookup_lock);
>
> return ret;
> }
> --
> 2.25.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/3] drm: clarify usage of drm leases
On Sat, Jul 24, 2021 at 07:18:23PM +0800, Desmond Cheong Zhi Xi wrote: > We make the following changes to the documentation of drm leases to > make it easier to reason about their usage. In particular, we clarify > the lifetime and locking rules of lease fields in drm_master: > > 1. Make it clear that _device.mode_config.idr_mutex protects the > lease idr and list structures for drm_master. The lessor field itself > doesn't need to be protected as it doesn't change after it's set in > drm_lease_create. > > 2. Add descriptions for the lifetime of lessors and leases. > > 3. Add an overview DOC: section in drm-uapi.rst that defines the > terminology for drm leasing, and explains how leases work and why > they're used. > > 4. Clean up function documentation in drm_lease.c to use kernel-doc > formatting. > > Signed-off-by: Desmond Cheong Zhi Xi > --- > > Hi, > > After I updated the formatting for comments in drm_lease.c, I noticed > that none of these were driver interfaces (i.e. no structs/inline > functions declared in headers, and no exported symbols in .c files). > > I left the kernel-doc links inside drm-uapi.rst so that if any such > interfaces are defined in the future, they'll go to the appropriate > place. But if these should be removed, or if the formatting changes for > function comments should be removed, please let me know. Hm indeed, so there's not really any need to either include the drm_lease.c or drm_lease.h kerneldoc. The DOC section itself is still useful. For the internal pieces usually what we do is remove the comment outright if it doesn't provide anything useful (like just repeats what the function name says already). If there's something interesting in the comment then we leave it that sentence in there as a normal comment, but without any of the structured comment stuff (so no /**, nor @arguments, or the function summary). > > Best wishes, > Desmond > > Documentation/gpu/drm-uapi.rst | 15 +++ > drivers/gpu/drm/drm_lease.c| 182 - > include/drm/drm_auth.h | 67 ++-- > 3 files changed, 180 insertions(+), 84 deletions(-) > > diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst > index 7e51dd40bf6e..6d7233a9fb14 100644 > --- a/Documentation/gpu/drm-uapi.rst > +++ b/Documentation/gpu/drm-uapi.rst > @@ -37,6 +37,21 @@ Primary Nodes, DRM Master and Authentication > .. kernel-doc:: include/drm/drm_auth.h > :internal: > > + > +.. _drm_leasing: > + > +DRM Display Resource Leasing > + > + > +.. kernel-doc:: drivers/gpu/drm/drm_lease.c > + :doc: drm leasing > + > +.. kernel-doc:: drivers/gpu/drm/drm_lease.c > + :export: > + > +.. kernel-doc:: include/drm/drm_lease.h > + :internal: > + > Open-Source Userspace Requirements > == > > diff --git a/drivers/gpu/drm/drm_lease.c b/drivers/gpu/drm/drm_lease.c > index 92eac73d9001..9b68617840ed 100644 > --- a/drivers/gpu/drm/drm_lease.c > +++ b/drivers/gpu/drm/drm_lease.c > @@ -15,18 +15,67 @@ > #include "drm_crtc_internal.h" > #include "drm_internal.h" > > +/** > + * DOC: drm leasing > + * > + * DRM leases provide information about whether a DRM master may control a > DRM > + * mode setting object. This enables the creation of multiple DRM masters > that > + * manage subsets of display resources. > + * > + * The original DRM master of a device 'owns' the available drm resources. It > + * may create additional DRM masters and 'lease' resources which it controls > + * to the new DRM master. This gives the new DRM master control over the > + * leased resources until the owner revokes the lease, or the new DRM master > + * is closed. Some helpful terminology: > + * > + * - An 'owner' is a drm_master that is not leasing objects from > + * another drm_master, and hence 'owns' the objects. The owner can > be > + * identified as the drm_master for which _master.lessor is > NULL. > + * > + * - A 'lessor' is a drm_master which is leasing objects to one or > more > + * other drm_master. Currently, lessees are not allowed to > + * create sub-leases, hence the lessor is the same as the owner. > + * > + * - A 'lessee' is a drm_master which is leasing objects from some > + * other drm_master. Each lessee only leases resources from a > single > + * lessor recorded in _master.lessor, and holds the set of objects that > + * it is leasing in _master.leases. > + * > + * - A 'lease' is a contract between the lessor and lessee that identifies > + * which resources may be controlled by the lessee. All of the resources > + * that are leased must be owned by or leased to the lessor, and lessors > are > + * not permitted to lease the same object to multiple lessees. > + * > + * The set of objects any drm_master 'controls' is limited to the set > + * of objects it leases (for lessees) or all objects (for owners). > + * > + * Objects not controlled by a drm_master cannot
[Intel-gfx] [PATCH v2 11/11] drm/i915: Extract i915_module.c
The module init code is somewhat misplaced in i915_pci.c, since it
needs to pull in init/exit functions from every part of the driver and
pollutes the include list a lot.
Extract an i915_module.c file which pulls all the bits together, and
allows us to massively trim the include list of i915_pci.c.
The downside is that have to drop the error path check Jason added to
catch when we set up the pci driver too early. I think that risk is
acceptable for this pretty nice include.
Cc: Jason Ekstrand
Cc: Tvrtko Ursulin
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_module.c | 113
drivers/gpu/drm/i915/i915_pci.c| 117 +
drivers/gpu/drm/i915/i915_pci.h| 8 ++
4 files changed, 125 insertions(+), 114 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_module.c
create mode 100644 drivers/gpu/drm/i915/i915_pci.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9022dc638ed6..4ebd9f417ddb 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -38,6 +38,7 @@ i915-y += i915_drv.o \
i915_irq.o \
i915_getparam.o \
i915_mitigations.o \
+ i915_module.o \
i915_params.o \
i915_pci.o \
i915_scatterlist.o \
diff --git a/drivers/gpu/drm/i915/i915_module.c
b/drivers/gpu/drm/i915/i915_module.c
new file mode 100644
index ..c578ea8f56a0
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_module.c
@@ -0,0 +1,113 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include
+
+#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_object.h"
+#include "i915_active.h"
+#include "i915_buddy.h"
+#include "i915_params.h"
+#include "i915_pci.h"
+#include "i915_perf.h"
+#include "i915_request.h"
+#include "i915_scheduler.h"
+#include "i915_selftest.h"
+#include "i915_vma.h"
+
+static int i915_check_nomodeset(void)
+{
+ bool use_kms = true;
+
+ /*
+* Enable KMS by default, unless explicitly overriden by
+* either the i915.modeset prarameter or by the
+* vga_text_mode_force boot option.
+*/
+
+ if (i915_modparams.modeset == 0)
+ use_kms = false;
+
+ if (vgacon_text_force() && i915_modparams.modeset == -1)
+ use_kms = false;
+
+ if (!use_kms) {
+ /* Silently fail loading to not upset userspace. */
+ DRM_DEBUG_DRIVER("KMS disabled.\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+static const struct {
+ int (*init)(void);
+ void (*exit)(void);
+} init_funcs[] = {
+ { i915_check_nomodeset, NULL },
+ { i915_active_module_init, i915_active_module_exit },
+ { i915_buddy_module_init, i915_buddy_module_exit },
+ { i915_context_module_init, i915_context_module_exit },
+ { i915_gem_context_module_init, i915_gem_context_module_exit },
+ { i915_objects_module_init, i915_objects_module_exit },
+ { i915_request_module_init, i915_request_module_exit },
+ { i915_scheduler_module_init, i915_scheduler_module_exit },
+ { i915_vma_module_init, i915_vma_module_exit },
+ { i915_mock_selftests, NULL },
+ { i915_pmu_init, i915_pmu_exit },
+ { i915_register_pci_driver, i915_unregister_pci_driver },
+ { i915_perf_sysctl_register, i915_perf_sysctl_unregister },
+};
+static int init_progress;
+
+static int __init i915_init(void)
+{
+ int err, i;
+
+ for (i = 0; i < ARRAY_SIZE(init_funcs); i++) {
+ err = init_funcs[i].init();
+ if (err < 0) {
+ while (i--) {
+ if (init_funcs[i].exit)
+ init_funcs[i].exit();
+ }
+ return err;
+ } else if (err > 0) {
+ /*
+* Early-exit success is reserved for things which
+* don't have an exit() function because we have no
+* idea how far they got or how to partially tear
+* them down.
+*/
+ WARN_ON(init_funcs[i].exit);
+ break;
+ }
+ }
+
+ init_progress = i;
+
+ return 0;
+}
+
+static void __exit i915_exit(void)
+{
+ int i;
+
+ for (i = init_progress - 1; i >= 0; i--) {
+ GEM_BUG_ON(i >= ARRAY_SIZE(init_funcs));
+ if (init_funcs[i].exit)
+ init_funcs[i].exit();
+ }
+}
+
+module_init(i915_init);
+module_exit(i915_exit);
+
+MODULE_AUTHOR("Tungsten Graphics, Inc.");
+MODULE_AUTHOR("Intel Corporation");
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/gpu/drm/i915/i915_pci.c
[Intel-gfx] [PATCH v2 10/11] drm/i915: Remove i915_globals
No longer used.
Cc: Jason Ekstrand
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/Makefile | 1 -
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 1 -
drivers/gpu/drm/i915/i915_globals.c | 53 ---
drivers/gpu/drm/i915/i915_globals.h | 25 -
drivers/gpu/drm/i915/i915_pci.c | 2 -
5 files changed, 82 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/i915_globals.c
delete mode 100644 drivers/gpu/drm/i915/i915_globals.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 10b3bb6207ba..9022dc638ed6 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -166,7 +166,6 @@ i915-y += \
i915_gem_gtt.o \
i915_gem_ww.o \
i915_gem.o \
- i915_globals.o \
i915_query.o \
i915_request.o \
i915_scheduler.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index d86825437516..943c1d416ec0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -6,7 +6,6 @@
#include
#include "i915_drv.h"
-#include "i915_globals.h"
#include "i915_params.h"
#include "intel_context.h"
#include "intel_engine_pm.h"
diff --git a/drivers/gpu/drm/i915/i915_globals.c
b/drivers/gpu/drm/i915/i915_globals.c
deleted file mode 100644
index 04979789e7be..
--- a/drivers/gpu/drm/i915/i915_globals.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * SPDX-License-Identifier: MIT
- *
- * Copyright © 2019 Intel Corporation
- */
-
-#include
-#include
-
-#include "i915_globals.h"
-#include "i915_drv.h"
-
-static LIST_HEAD(globals);
-
-void __init i915_global_register(struct i915_global *global)
-{
- GEM_BUG_ON(!global->exit);
-
- list_add_tail(>link, );
-}
-
-static void __i915_globals_cleanup(void)
-{
- struct i915_global *global, *next;
-
- list_for_each_entry_safe_reverse(global, next, , link)
- global->exit();
-}
-
-static __initconst int (* const initfn[])(void) = {
-};
-
-int __init i915_globals_init(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(initfn); i++) {
- int err;
-
- err = initfn[i]();
- if (err) {
- __i915_globals_cleanup();
- return err;
- }
- }
-
- return 0;
-}
-
-void i915_globals_exit(void)
-{
- __i915_globals_cleanup();
-}
diff --git a/drivers/gpu/drm/i915/i915_globals.h
b/drivers/gpu/drm/i915/i915_globals.h
deleted file mode 100644
index 57d2998bba45..
--- a/drivers/gpu/drm/i915/i915_globals.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * SPDX-License-Identifier: MIT
- *
- * Copyright © 2019 Intel Corporation
- */
-
-#ifndef _I915_GLOBALS_H_
-#define _I915_GLOBALS_H_
-
-#include
-
-typedef void (*i915_global_func_t)(void);
-
-struct i915_global {
- struct list_head link;
-
- i915_global_func_t exit;
-};
-
-void i915_global_register(struct i915_global *global);
-
-int i915_globals_init(void);
-void i915_globals_exit(void);
-
-#endif /* _I915_GLOBALS_H_ */
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 14785d88dafb..b4f5e88aaae6 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -37,7 +37,6 @@
#include "gem/i915_gem_object.h"
#include "i915_request.h"
#include "i915_perf.h"
-#include "i915_globals.h"
#include "i915_selftest.h"
#include "i915_scheduler.h"
#include "i915_vma.h"
@@ -1309,7 +1308,6 @@ static const struct {
{ i915_request_module_init, i915_request_module_exit },
{ i915_scheduler_module_init, i915_scheduler_module_exit },
{ i915_vma_module_init, i915_vma_module_exit },
- { i915_globals_init, i915_globals_exit },
{ i915_mock_selftests, NULL },
{ i915_pmu_init, i915_pmu_exit },
{ i915_register_pci_driver, i915_unregister_pci_driver },
--
2.32.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 09/11] drm/i915: move vma slab to direct module init/exit
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_vmas to just a
slab_vmas.
We have to keep i915_drv.h include in i915_globals otherwise there's
nothing anymore that pulls in GEM_BUG_ON.
v2: Make slab static (Jason, 0day)
Reviewed-by: Jason Ekstrand
Cc: Jason Ekstrand
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_globals.c | 3 +--
drivers/gpu/drm/i915/i915_globals.h | 3 ---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/i915_vma.c | 25 -
drivers/gpu/drm/i915/i915_vma.h | 3 +++
5 files changed, 14 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_globals.c
b/drivers/gpu/drm/i915/i915_globals.c
index 8923589057ab..04979789e7be 100644
--- a/drivers/gpu/drm/i915/i915_globals.c
+++ b/drivers/gpu/drm/i915/i915_globals.c
@@ -8,7 +8,7 @@
#include
#include "i915_globals.h"
-#include "i915_vma.h"
+#include "i915_drv.h"
static LIST_HEAD(globals);
@@ -28,7 +28,6 @@ static void __i915_globals_cleanup(void)
}
static __initconst int (* const initfn[])(void) = {
- i915_global_vma_init,
};
int __init i915_globals_init(void)
diff --git a/drivers/gpu/drm/i915/i915_globals.h
b/drivers/gpu/drm/i915/i915_globals.h
index 7a57bce1da05..57d2998bba45 100644
--- a/drivers/gpu/drm/i915/i915_globals.h
+++ b/drivers/gpu/drm/i915/i915_globals.h
@@ -22,7 +22,4 @@ void i915_global_register(struct i915_global *global);
int i915_globals_init(void);
void i915_globals_exit(void);
-/* constructors */
-int i915_global_vma_init(void);
-
#endif /* _I915_GLOBALS_H_ */
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 500897d0d4b5..14785d88dafb 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -40,6 +40,7 @@
#include "i915_globals.h"
#include "i915_selftest.h"
#include "i915_scheduler.h"
+#include "i915_vma.h"
#define PLATFORM(x) .platform = (x)
#define GEN(x) \
@@ -1307,6 +1308,7 @@ static const struct {
{ i915_objects_module_init, i915_objects_module_exit },
{ i915_request_module_init, i915_request_module_exit },
{ i915_scheduler_module_init, i915_scheduler_module_exit },
+ { i915_vma_module_init, i915_vma_module_exit },
{ i915_globals_init, i915_globals_exit },
{ i915_mock_selftests, NULL },
{ i915_pmu_init, i915_pmu_exit },
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 09a7c47926f7..4b7fc4647e46 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -34,24 +34,20 @@
#include "gt/intel_gt_requests.h"
#include "i915_drv.h"
-#include "i915_globals.h"
#include "i915_sw_fence_work.h"
#include "i915_trace.h"
#include "i915_vma.h"
-static struct i915_global_vma {
- struct i915_global base;
- struct kmem_cache *slab_vmas;
-} global;
+static struct kmem_cache *slab_vmas;
struct i915_vma *i915_vma_alloc(void)
{
- return kmem_cache_zalloc(global.slab_vmas, GFP_KERNEL);
+ return kmem_cache_zalloc(slab_vmas, GFP_KERNEL);
}
void i915_vma_free(struct i915_vma *vma)
{
- return kmem_cache_free(global.slab_vmas, vma);
+ return kmem_cache_free(slab_vmas, vma);
}
#if IS_ENABLED(CONFIG_DRM_I915_ERRLOG_GEM) && IS_ENABLED(CONFIG_DRM_DEBUG_MM)
@@ -1414,21 +1410,16 @@ void i915_vma_make_purgeable(struct i915_vma *vma)
#include "selftests/i915_vma.c"
#endif
-static void i915_global_vma_exit(void)
+void i915_vma_module_exit(void)
{
- kmem_cache_destroy(global.slab_vmas);
+ kmem_cache_destroy(slab_vmas);
}
-static struct i915_global_vma global = { {
- .exit = i915_global_vma_exit,
-} };
-
-int __init i915_global_vma_init(void)
+int __init i915_vma_module_init(void)
{
- global.slab_vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
- if (!global.slab_vmas)
+ slab_vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
+ if (!slab_vmas)
return -ENOMEM;
- i915_global_register();
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index eca452a9851f..ed69f66c7ab0 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -426,4 +426,7 @@ static inline int i915_vma_sync(struct i915_vma *vma)
return i915_active_wait(>active);
}
+void i915_vma_module_exit(void);
+int i915_vma_module_init(void);
+
#endif
--
2.32.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 07/11] drm/i915: move request slabs to direct module init/exit
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_requests|execute_cbs to just a
slab_requests|execute_cbs.
v2: Make slab static (Jason, 0day)
Reviewed-by: Jason Ekstrand
Cc: Jason Ekstrand
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_globals.c | 2 --
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/i915_request.c | 47 -
drivers/gpu/drm/i915/i915_request.h | 3 ++
4 files changed, 24 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_globals.c
b/drivers/gpu/drm/i915/i915_globals.c
index 40a592fbc3e0..8fffa8d93bc5 100644
--- a/drivers/gpu/drm/i915/i915_globals.c
+++ b/drivers/gpu/drm/i915/i915_globals.c
@@ -8,7 +8,6 @@
#include
#include "i915_globals.h"
-#include "i915_request.h"
#include "i915_scheduler.h"
#include "i915_vma.h"
@@ -30,7 +29,6 @@ static void __i915_globals_cleanup(void)
}
static __initconst int (* const initfn[])(void) = {
- i915_global_request_init,
i915_global_scheduler_init,
i915_global_vma_init,
};
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 7a13570c04a5..3f1716a3d74f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -35,6 +35,7 @@
#include "i915_drv.h"
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_object.h"
+#include "i915_request.h"
#include "i915_perf.h"
#include "i915_globals.h"
#include "i915_selftest.h"
@@ -1303,6 +1304,7 @@ static const struct {
{ i915_context_module_init, i915_context_module_exit },
{ i915_gem_context_module_init, i915_gem_context_module_exit },
{ i915_objects_module_init, i915_objects_module_exit },
+ { i915_request_module_init, i915_request_module_exit },
{ i915_globals_init, i915_globals_exit },
{ i915_mock_selftests, NULL },
{ i915_pmu_init, i915_pmu_exit },
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 6594cb2f8ebd..3dd759be3c28 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -42,7 +42,6 @@
#include "i915_active.h"
#include "i915_drv.h"
-#include "i915_globals.h"
#include "i915_trace.h"
#include "intel_pm.h"
@@ -52,11 +51,8 @@ struct execute_cb {
struct i915_request *signal;
};
-static struct i915_global_request {
- struct i915_global base;
- struct kmem_cache *slab_requests;
- struct kmem_cache *slab_execute_cbs;
-} global;
+static struct kmem_cache *slab_requests;
+static struct kmem_cache *slab_execute_cbs;
static const char *i915_fence_get_driver_name(struct dma_fence *fence)
{
@@ -107,7 +103,7 @@ static signed long i915_fence_wait(struct dma_fence *fence,
struct kmem_cache *i915_request_slab_cache(void)
{
- return global.slab_requests;
+ return slab_requests;
}
static void i915_fence_release(struct dma_fence *fence)
@@ -159,7 +155,7 @@ static void i915_fence_release(struct dma_fence *fence)
!cmpxchg(>engine->request_pool, NULL, rq))
return;
- kmem_cache_free(global.slab_requests, rq);
+ kmem_cache_free(slab_requests, rq);
}
const struct dma_fence_ops i915_fence_ops = {
@@ -176,7 +172,7 @@ static void irq_execute_cb(struct irq_work *wrk)
struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
i915_sw_fence_complete(cb->fence);
- kmem_cache_free(global.slab_execute_cbs, cb);
+ kmem_cache_free(slab_execute_cbs, cb);
}
static __always_inline void
@@ -514,7 +510,7 @@ __await_execution(struct i915_request *rq,
if (i915_request_is_active(signal))
return 0;
- cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
+ cb = kmem_cache_alloc(slab_execute_cbs, gfp);
if (!cb)
return -ENOMEM;
@@ -868,7 +864,7 @@ request_alloc_slow(struct intel_timeline *tl,
rq = list_first_entry(>requests, typeof(*rq), link);
i915_request_retire(rq);
- rq = kmem_cache_alloc(global.slab_requests,
+ rq = kmem_cache_alloc(slab_requests,
gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
if (rq)
return rq;
@@ -881,7 +877,7 @@ request_alloc_slow(struct intel_timeline *tl,
retire_requests(tl);
out:
- return kmem_cache_alloc(global.slab_requests, gfp);
+ return kmem_cache_alloc(slab_requests, gfp);
}
static void __i915_request_ctor(void *arg)
@@ -942,7 +938,7 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp)
*
* Do not use kmem_cache_zalloc() here!
*/
- rq = kmem_cache_alloc(global.slab_requests,
+ rq = kmem_cache_alloc(slab_requests,
gfp | __GFP_RETRY_MAYFAIL |
[Intel-gfx] [PATCH v2 06/11] drm/i915: move gem_objects slab to direct module init/exit
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_objects to just a
slab_objects.
v2: Make slab static (Jason, 0day)
Reviewed-by: Jason Ekstrand
Cc: Jason Ekstrand
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 26 +++---
drivers/gpu/drm/i915/gem/i915_gem_object.h | 3 +++
drivers/gpu/drm/i915/i915_globals.c| 1 -
drivers/gpu/drm/i915/i915_globals.h| 1 -
drivers/gpu/drm/i915/i915_pci.c| 1 +
5 files changed, 12 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 9d3497e1235a..6fb9afb65034 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -30,14 +30,10 @@
#include "i915_gem_context.h"
#include "i915_gem_mman.h"
#include "i915_gem_object.h"
-#include "i915_globals.h"
#include "i915_memcpy.h"
#include "i915_trace.h"
-static struct i915_global_object {
- struct i915_global base;
- struct kmem_cache *slab_objects;
-} global;
+static struct kmem_cache *slab_objects;
static const struct drm_gem_object_funcs i915_gem_object_funcs;
@@ -45,7 +41,7 @@ struct drm_i915_gem_object *i915_gem_object_alloc(void)
{
struct drm_i915_gem_object *obj;
- obj = kmem_cache_zalloc(global.slab_objects, GFP_KERNEL);
+ obj = kmem_cache_zalloc(slab_objects, GFP_KERNEL);
if (!obj)
return NULL;
obj->base.funcs = _gem_object_funcs;
@@ -55,7 +51,7 @@ struct drm_i915_gem_object *i915_gem_object_alloc(void)
void i915_gem_object_free(struct drm_i915_gem_object *obj)
{
- return kmem_cache_free(global.slab_objects, obj);
+ return kmem_cache_free(slab_objects, obj);
}
void i915_gem_object_init(struct drm_i915_gem_object *obj,
@@ -658,23 +654,17 @@ void i915_gem_init__objects(struct drm_i915_private *i915)
INIT_WORK(>mm.free_work, __i915_gem_free_work);
}
-static void i915_global_objects_exit(void)
+void i915_objects_module_exit(void)
{
- kmem_cache_destroy(global.slab_objects);
+ kmem_cache_destroy(slab_objects);
}
-static struct i915_global_object global = { {
- .exit = i915_global_objects_exit,
-} };
-
-int __init i915_global_objects_init(void)
+int __init i915_objects_module_init(void)
{
- global.slab_objects =
- KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
- if (!global.slab_objects)
+ slab_objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
+ if (!slab_objects)
return -ENOMEM;
- i915_global_register();
return 0;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 0896ac532f5e..48112b9d76df 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -48,6 +48,9 @@ static inline bool i915_gem_object_size_2big(u64 size)
void i915_gem_init__objects(struct drm_i915_private *i915);
+void i915_objects_module_exit(void);
+int i915_objects_module_init(void);
+
struct drm_i915_gem_object *i915_gem_object_alloc(void);
void i915_gem_object_free(struct drm_i915_gem_object *obj);
diff --git a/drivers/gpu/drm/i915/i915_globals.c
b/drivers/gpu/drm/i915/i915_globals.c
index dbb3d81eeea7..40a592fbc3e0 100644
--- a/drivers/gpu/drm/i915/i915_globals.c
+++ b/drivers/gpu/drm/i915/i915_globals.c
@@ -30,7 +30,6 @@ static void __i915_globals_cleanup(void)
}
static __initconst int (* const initfn[])(void) = {
- i915_global_objects_init,
i915_global_request_init,
i915_global_scheduler_init,
i915_global_vma_init,
diff --git a/drivers/gpu/drm/i915/i915_globals.h
b/drivers/gpu/drm/i915/i915_globals.h
index f16752dbbdbf..9734740708f4 100644
--- a/drivers/gpu/drm/i915/i915_globals.h
+++ b/drivers/gpu/drm/i915/i915_globals.h
@@ -23,7 +23,6 @@ int i915_globals_init(void);
void i915_globals_exit(void);
/* constructors */
-int i915_global_objects_init(void);
int i915_global_request_init(void);
int i915_global_scheduler_init(void);
int i915_global_vma_init(void);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 410a85a1cbab..7a13570c04a5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1302,6 +1302,7 @@ static const struct {
{ i915_buddy_module_init, i915_buddy_module_exit },
{ i915_context_module_init, i915_context_module_exit },
{ i915_gem_context_module_init, i915_gem_context_module_exit },
+ { i915_objects_module_init, i915_objects_module_exit },
{ i915_globals_init, i915_globals_exit },
{ i915_mock_selftests, NULL },
{ i915_pmu_init, i915_pmu_exit },
--
2.32.0
[Intel-gfx] [PATCH v2 08/11] drm/i915: move scheduler slabs to direct module init/exit
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_dependencies|priorities to just a
slab_dependencies|priorities.
v2: Make slab static (Jason, 0day)
Reviewed-by: Jason Ekstrand
Cc: Jason Ekstrand
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_globals.c | 2 --
drivers/gpu/drm/i915/i915_globals.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/i915_scheduler.c | 39 +++
drivers/gpu/drm/i915/i915_scheduler.h | 3 +++
5 files changed, 20 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_globals.c
b/drivers/gpu/drm/i915/i915_globals.c
index 8fffa8d93bc5..8923589057ab 100644
--- a/drivers/gpu/drm/i915/i915_globals.c
+++ b/drivers/gpu/drm/i915/i915_globals.c
@@ -8,7 +8,6 @@
#include
#include "i915_globals.h"
-#include "i915_scheduler.h"
#include "i915_vma.h"
static LIST_HEAD(globals);
@@ -29,7 +28,6 @@ static void __i915_globals_cleanup(void)
}
static __initconst int (* const initfn[])(void) = {
- i915_global_scheduler_init,
i915_global_vma_init,
};
diff --git a/drivers/gpu/drm/i915/i915_globals.h
b/drivers/gpu/drm/i915/i915_globals.h
index 9734740708f4..7a57bce1da05 100644
--- a/drivers/gpu/drm/i915/i915_globals.h
+++ b/drivers/gpu/drm/i915/i915_globals.h
@@ -23,8 +23,6 @@ int i915_globals_init(void);
void i915_globals_exit(void);
/* constructors */
-int i915_global_request_init(void);
-int i915_global_scheduler_init(void);
int i915_global_vma_init(void);
#endif /* _I915_GLOBALS_H_ */
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 3f1716a3d74f..500897d0d4b5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -39,6 +39,7 @@
#include "i915_perf.h"
#include "i915_globals.h"
#include "i915_selftest.h"
+#include "i915_scheduler.h"
#define PLATFORM(x) .platform = (x)
#define GEN(x) \
@@ -1305,6 +1306,7 @@ static const struct {
{ i915_gem_context_module_init, i915_gem_context_module_exit },
{ i915_objects_module_init, i915_objects_module_exit },
{ i915_request_module_init, i915_request_module_exit },
+ { i915_scheduler_module_init, i915_scheduler_module_exit },
{ i915_globals_init, i915_globals_exit },
{ i915_mock_selftests, NULL },
{ i915_pmu_init, i915_pmu_exit },
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 561c649e59f7..c7ea5a1f3b94 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -7,15 +7,11 @@
#include
#include "i915_drv.h"
-#include "i915_globals.h"
#include "i915_request.h"
#include "i915_scheduler.h"
-static struct i915_global_scheduler {
- struct i915_global base;
- struct kmem_cache *slab_dependencies;
- struct kmem_cache *slab_priorities;
-} global;
+static struct kmem_cache *slab_dependencies;
+static struct kmem_cache *slab_priorities;
static DEFINE_SPINLOCK(schedule_lock);
@@ -93,7 +89,7 @@ i915_sched_lookup_priolist(struct i915_sched_engine
*sched_engine, int prio)
if (prio == I915_PRIORITY_NORMAL) {
p = _engine->default_priolist;
} else {
- p = kmem_cache_alloc(global.slab_priorities, GFP_ATOMIC);
+ p = kmem_cache_alloc(slab_priorities, GFP_ATOMIC);
/* Convert an allocation failure to a priority bump */
if (unlikely(!p)) {
prio = I915_PRIORITY_NORMAL; /* recurses just once */
@@ -122,7 +118,7 @@ i915_sched_lookup_priolist(struct i915_sched_engine
*sched_engine, int prio)
void __i915_priolist_free(struct i915_priolist *p)
{
- kmem_cache_free(global.slab_priorities, p);
+ kmem_cache_free(slab_priorities, p);
}
struct sched_cache {
@@ -313,13 +309,13 @@ void i915_sched_node_reinit(struct i915_sched_node *node)
static struct i915_dependency *
i915_dependency_alloc(void)
{
- return kmem_cache_alloc(global.slab_dependencies, GFP_KERNEL);
+ return kmem_cache_alloc(slab_dependencies, GFP_KERNEL);
}
static void
i915_dependency_free(struct i915_dependency *dep)
{
- kmem_cache_free(global.slab_dependencies, dep);
+ kmem_cache_free(slab_dependencies, dep);
}
bool __i915_sched_node_add_dependency(struct i915_sched_node *node,
@@ -475,32 +471,27 @@ i915_sched_engine_create(unsigned int subclass)
return sched_engine;
}
-static void i915_global_scheduler_exit(void)
+void i915_scheduler_module_exit(void)
{
- kmem_cache_destroy(global.slab_dependencies);
- kmem_cache_destroy(global.slab_priorities);
+ kmem_cache_destroy(slab_dependencies);
+ kmem_cache_destroy(slab_priorities);
}
-static struct i915_global_scheduler global = { {
-
