Re: [Intel-gfx] [PATCH 50/53] drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable
Now, this change and changes from patch 51 of this series is taken care as part
of the below series
https://patchwork.freedesktop.org/series/92750/
and merged.
Thanks,
Vandita
> -Original Message-
> From: Jani Nikula
> Sent: Friday, July 2, 2021 1:50 PM
> To: Roper, Matthew D ; intel-
> g...@lists.freedesktop.org
> Cc: Patnana, Venkata Sai ; Srivatsa, Anusha
> ; dri-de...@lists.freedesktop.org; Navare,
> Manasi D ; Kulkarni, Vandita
>
> Subject: Re: [PATCH 50/53] drm/i915/display/dsc: Add Per connector debugfs
> node for DSC BPP enable
>
> On Thu, 01 Jul 2021, Matt Roper wrote:
> > From: Anusha Srivatsa
> >
> > DSC can be supported per DP connector. This patch creates a per
> > connector debugfs node to expose the Input and Compressed BPP.
> >
> > The same node can be used from userspace to force DSC to a certain
> > BPP.
> >
> > force_dsc_bpp is written through this debugfs node to force DSC BPP to
> > all accepted values
>
> I think this patch needs rework, and it's independent of the rest of the
> series. Please just drop this one and the next.
>
> BR,
> Jani.
>
> >
> > Cc: Vandita Kulkarni
> > Cc: Manasi Navare
> > Signed-off-by: Anusha Srivatsa
> > Signed-off-by: Patnana Venkata Sai
> > Signed-off-by: Matt Roper
> > ---
> > .../drm/i915/display/intel_display_debugfs.c | 103 +-
> > .../drm/i915/display/intel_display_types.h| 1 +
> > 2 files changed, 103 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index af9e58619667..1805d70ea817 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -2389,6 +2389,100 @@ static const struct file_operations
> i915_dsc_fec_support_fops = {
> > .write = i915_dsc_fec_support_write
> > };
> >
> > +static int i915_dsc_bpp_support_show(struct seq_file *m, void *data)
> > +{
> > + struct drm_connector *connector = m->private;
> > + struct drm_device *dev = connector->dev;
> > + struct drm_crtc *crtc;
> > + struct intel_dp *intel_dp;
> > + struct drm_modeset_acquire_ctx ctx;
> > + struct intel_crtc_state *crtc_state = NULL;
> > + int ret = 0;
> > + bool try_again = false;
> > +
> > + drm_modeset_acquire_init(,
> DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
> > +
> > + do {
> > + try_again = false;
> > + ret = drm_modeset_lock(
> >mode_config.connection_mutex,
> > + );
> > + if (ret) {
> > + ret = -EINTR;
> > + break;
> > + }
> > + crtc = connector->state->crtc;
> > + if (connector->status != connector_status_connected ||
> !crtc) {
> > + ret = -ENODEV;
> > + break;
> > + }
> > + ret = drm_modeset_lock(>mutex, );
> > + if (ret == -EDEADLK) {
> > + ret = drm_modeset_backoff();
> > + if (!ret) {
> > + try_again = true;
> > + continue;
> > + }
> > + break;
> > + } else if (ret) {
> > + break;
> > + }
> > + intel_dp =
> intel_attached_dp(to_intel_connector(connector));
> > + crtc_state = to_intel_crtc_state(crtc->state);
> > + seq_printf(m, "Input_BPP: %d\n", crtc_state->pipe_bpp);
> > + seq_printf(m, "Compressed_BPP: %d\n",
> > + crtc_state->dsc.compressed_bpp);
> > + } while (try_again);
> > +
> > + drm_modeset_drop_locks();
> > + drm_modeset_acquire_fini();
> > +
> > + return ret;
> > +}
> > +
> > +static ssize_t i915_dsc_bpp_support_write(struct file *file,
> > + const char __user *ubuf,
> > + size_t len, loff_t *offp)
> > +{
> > + int dsc_bpp = 0;
> > + int ret;
> > + struct drm_connector *connector =
> > + ((struct seq_file *)file->private_data)->private;
> > + struct intel_encoder *encoder =
> intel_attached_encoder(to_intel_connector(connector));
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +
> > + if (len == 0)
> > + return 0;
> > +
> > + drm_dbg(>drm,
> > + "Copied %zu bytes from user to force BPP\n", len);
> > +
> > + ret = kstrtoint_from_user(ubuf, len, 0, _bpp);
> > +
> > + intel_dp->force_dsc_bpp = dsc_bpp;
> > + if (ret < 0)
> > + return ret;
> > +
> > + *offp += len;
> > + return len;
> > +}
> > +
> > +static int i915_dsc_bpp_support_open(struct inode *inode,
> > + struct file *file)
> > +{
> > + return single_open(file, i915_dsc_bpp_support_show,
> > + inode->i_private);
> > +}
> > +
> >
[Intel-gfx] ✓ Fi.CI.BAT: success for Enable mipi dsi on XELPD (rev2)
== Series Details ==
Series: Enable mipi dsi on XELPD (rev2)
URL : https://patchwork.freedesktop.org/series/93917/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10506 -> Patchwork_20869
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20869/index.html
Known issues
Here are the changes found in Patchwork_20869 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +11 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20869/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20869/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][3] ([i915#1886] / [i915#2291])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20869/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_busy@basic@modeset:
- fi-tgl-1115g4: [PASS][4] -> [DMESG-WARN][5] ([i915#4002])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10506/fi-tgl-1115g4/igt@kms_busy@ba...@modeset.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20869/fi-tgl-1115g4/igt@kms_busy@ba...@modeset.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20869/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [PASS][7] -> [DMESG-FAIL][8] ([i915#165])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10506/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20869/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20869/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-1115g4: [DMESG-WARN][10] ([i915#4002]) -> [PASS][11] +1
similar issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10506/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20869/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
Warnings
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][12] ([i915#1888]) -> [DMESG-WARN][13]
([i915#4002])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10506/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20869/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-1115g4: [SKIP][14] ([fdo#111827] / [i915#1385]) -> [SKIP][15]
([fdo#111827])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10506/fi-tgl-1115g4/igt@kms_chamel...@dp-hpd-fast.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20869/fi-tgl-1115g4/igt@kms_chamel...@dp-hpd-fast.html
* igt@kms_psr@primary_page_flip:
- fi-tgl-1115g4: [SKIP][16] ([i915#1072]) -> [SKIP][17] ([i915#1072] /
[i915#1385])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10506/fi-tgl-1115g4/igt@kms_psr@primary_page_flip.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20869/fi-tgl-1115g4/igt@kms_psr@primary_page_flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1385]: https://gitlab.freedesktop.org/drm/intel/issues/1385
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4002]: https://gitlab.freedesktop.org/drm/intel/issues/4002
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (38 -> 34)
--
Additional (1): fi-kbl-soraka
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable mipi dsi on XELPD (rev2)
== Series Details == Series: Enable mipi dsi on XELPD (rev2) URL : https://patchwork.freedesktop.org/series/93917/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:expected struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:got struct i915_address_space * +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1268:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts
[Intel-gfx] [v2] drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband
Wa_16012360555 SW will have to program the "LP to HS Wakeup Guardband"
field to account for the repeaters on the HS Request/Ready PPI signaling
between the Display engine and the DPHY.
v2: Fix build issue.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/icl_dsi.c | 25 +
drivers/gpu/drm/i915/i915_reg.h| 8
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 43ec7fcd3f5d..b075defb88bb 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1270,6 +1270,28 @@ static void icl_apply_kvmr_pipe_a_wa(struct
intel_encoder *encoder,
IGNORE_KVMR_PIPE_A,
enable ? IGNORE_KVMR_PIPE_A : 0);
}
+
+/*
+ * Wa_16012360555:ADLP
+ * SW will have to program the "LP to HS Wakeup Guardband"
+ * field (bits 15:12) of register offset 0x6B0C0 (DSI0)
+ * and 0x6B8C0 (DSI1) to a value of 4 to account for the repeaters
+ * on the HS Request/Ready PPI signaling between
+ * the Display engine and the DPHY.
+ */
+static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+ enum port port;
+
+ if (DISPLAY_VER(dev_priv) == 13) {
+ for_each_dsi_port(port, intel_dsi->ports)
+ intel_de_rmw(dev_priv, TGL_DSI_CHKN_REG(port),
+TGL_DSI_CHKN_LSHS_GB, 0x4);
+ }
+}
+
static void gen11_dsi_enable(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
@@ -1283,6 +1305,9 @@ static void gen11_dsi_enable(struct intel_atomic_state
*state,
/* Wa_1409054076:icl,jsl,ehl */
icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);
+ /* Wa_16012360555: adlp */
+ adlp_set_lp_hs_wakeup_gb(encoder);
+
/* step6d: enable dsi transcoder */
gen11_dsi_enable_transcoder(encoder);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 72dd3a6d205d..4c90d45343d6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11614,6 +11614,14 @@ enum skl_power_gate {
_ICL_DSI_IO_MODECTL_1)
#define COMBO_PHY_MODE_DSI(1 << 0)
+/* TGL DSI Chicken register */
+#define _TGL_DSI_CHKN_REG_00x6B0C0
+#define _TGL_DSI_CHKN_REG_10x6B8C0
+#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port,\
+ _TGL_DSI_CHKN_REG_0, \
+ _TGL_DSI_CHKN_REG_1)
+#define TGL_DSI_CHKN_LSHS_GB (0xF << 12)
+
/* Display Stream Splitter Control */
#define DSS_CTL1 _MMIO(0x67400)
#define SPLITTER_ENABLE (1 << 31)
--
2.32.0
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable mipi dsi on XELPD
== Series Details ==
Series: Enable mipi dsi on XELPD
URL : https://patchwork.freedesktop.org/series/93917/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/display/icl_dsi.o
In file included from drivers/gpu/drm/i915/display/intel_ddi.h:10,
from drivers/gpu/drm/i915/display/icl_dsi.c:35:
drivers/gpu/drm/i915/display/icl_dsi.c: In function ‘adlp_set_lp_hs_wakeup_gb’:
./drivers/gpu/drm/i915/i915_reg.h:11623:11: error: ‘_TGL_DSI_CHKN_REG_0’
undeclared (first use in this function); did you mean ‘TGL_DSI_CHKN_REG_0’?
_TGL_DSI_CHKN_REG_0, \
^~~
./drivers/gpu/drm/i915/i915_reg.h:185:47: note: in definition of macro ‘_MMIO’
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
^
./drivers/gpu/drm/i915/i915_reg.h:231:28: note: in expansion of macro
‘_PICK_EVEN’
#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
^~
./drivers/gpu/drm/i915/i915_reg.h:238:39: note: in expansion of macro ‘_PORT’
#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
^
./drivers/gpu/drm/i915/i915_reg.h:11622:33: note: in expansion of macro
‘_MMIO_PORT’
#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \
^~
drivers/gpu/drm/i915/display/icl_dsi.c:1290:27: note: in expansion of macro
‘TGL_DSI_CHKN_REG’
intel_de_rmw(dev_priv, TGL_DSI_CHKN_REG(port),
^~~~
./drivers/gpu/drm/i915/i915_reg.h:11623:11: note: each undeclared identifier is
reported only once for each function it appears in
_TGL_DSI_CHKN_REG_0, \
^~~
./drivers/gpu/drm/i915/i915_reg.h:185:47: note: in definition of macro ‘_MMIO’
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
^
./drivers/gpu/drm/i915/i915_reg.h:231:28: note: in expansion of macro
‘_PICK_EVEN’
#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
^~
./drivers/gpu/drm/i915/i915_reg.h:238:39: note: in expansion of macro ‘_PORT’
#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
^
./drivers/gpu/drm/i915/i915_reg.h:11622:33: note: in expansion of macro
‘_MMIO_PORT’
#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \
^~
drivers/gpu/drm/i915/display/icl_dsi.c:1290:27: note: in expansion of macro
‘TGL_DSI_CHKN_REG’
intel_de_rmw(dev_priv, TGL_DSI_CHKN_REG(port),
^~~~
./drivers/gpu/drm/i915/i915_reg.h:11624:11: error: ‘_TGL_DSI_CHKN_REG_1’
undeclared (first use in this function); did you mean ‘TGL_DSI_CHKN_REG_1’?
_TGL_DSI_CHKN_REG_1)
^~~
./drivers/gpu/drm/i915/i915_reg.h:185:47: note: in definition of macro ‘_MMIO’
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
^
./drivers/gpu/drm/i915/i915_reg.h:231:28: note: in expansion of macro
‘_PICK_EVEN’
#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
^~
./drivers/gpu/drm/i915/i915_reg.h:238:39: note: in expansion of macro ‘_PORT’
#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
^
./drivers/gpu/drm/i915/i915_reg.h:11622:33: note: in expansion of macro
‘_MMIO_PORT’
#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \
^~
drivers/gpu/drm/i915/display/icl_dsi.c:1290:27: note: in expansion of macro
‘TGL_DSI_CHKN_REG’
intel_de_rmw(dev_priv, TGL_DSI_CHKN_REG(port),
^~~~
drivers/gpu/drm/i915/display/icl_dsi.c:1288:5: error: suggest explicit braces
to avoid ambiguous ‘else’ [-Werror=dangling-else]
if (DISPLAY_VER(dev_priv) == 13)
^
cc1: all warnings being treated as errors
scripts/Makefile.build:271: recipe for target
'drivers/gpu/drm/i915/display/icl_dsi.o' failed
make[4]: *** [drivers/gpu/drm/i915/display/icl_dsi.o] Error 1
scripts/Makefile.build:514: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:514: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:514: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1851: recipe for target 'drivers' failed
make: *** [drivers] Error 2
[Intel-gfx] [PATCH 2/2] drm/i915/dsi/xelpd: Enable mipi dsi support.
Enable MIPI DSI support on ADL-P platform.
The esc clock changes, WA changes are taken care
in the previous patches.
As per the Bspec the seq remains to be same as TGL.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a257e5dc381c..55142b9ec976 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11488,6 +11488,7 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_ddi_init(dev_priv, PORT_TC2);
intel_ddi_init(dev_priv, PORT_TC3);
intel_ddi_init(dev_priv, PORT_TC4);
+ icl_dsi_init(dev_priv);
} else if (IS_ALDERLAKE_S(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_TC1);
--
2.32.0
[Intel-gfx] [PATCH 1/2] drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband
Wa_16012360555 SW will have to program the "LP to HS Wakeup Guardband"
field to account for the repeaters on the HS Request/Ready PPI signaling
between the Display engine and the DPHY.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/icl_dsi.c | 24
drivers/gpu/drm/i915/i915_reg.h| 8
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 43ec7fcd3f5d..61aea695c565 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1270,6 +1270,27 @@ static void icl_apply_kvmr_pipe_a_wa(struct
intel_encoder *encoder,
IGNORE_KVMR_PIPE_A,
enable ? IGNORE_KVMR_PIPE_A : 0);
}
+
+/*
+ * Wa_16012360555:ADLP
+ * SW will have to program the "LP to HS Wakeup Guardband"
+ * field (bits 15:12) of register offset 0x6B0C0 (DSI0)
+ * and 0x6B8C0 (DSI1) to a value of 4 to account for the repeaters
+ * on the HS Request/Ready PPI signaling between
+ * the Display engine and the DPHY.
+ */
+static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+ enum port port;
+
+ if (DISPLAY_VER(dev_priv) == 13)
+ for_each_dsi_port(port, intel_dsi->ports)
+ intel_de_rmw(dev_priv, TGL_DSI_CHKN_REG(port),
+TGL_DSI_CHKN_LSHS_GB, 0x4);
+}
+
static void gen11_dsi_enable(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
@@ -1283,6 +1304,9 @@ static void gen11_dsi_enable(struct intel_atomic_state
*state,
/* Wa_1409054076:icl,jsl,ehl */
icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);
+ /* Wa_16012360555: adlp */
+ adlp_set_lp_hs_wakeup_gb(encoder);
+
/* step6d: enable dsi transcoder */
gen11_dsi_enable_transcoder(encoder);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 72dd3a6d205d..34ad288de748 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11614,6 +11614,14 @@ enum skl_power_gate {
_ICL_DSI_IO_MODECTL_1)
#define COMBO_PHY_MODE_DSI(1 << 0)
+/* TGL DSI Chicken register */
+#define TGL_DSI_CHKN_REG_0 0x6B0C0
+#define TGL_DSI_CHKN_REG_1 0x6B8C0
+#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port,\
+ _TGL_DSI_CHKN_REG_0, \
+ _TGL_DSI_CHKN_REG_1)
+#define TGL_DSI_CHKN_LSHS_GB (0xF << 12)
+
/* Display Stream Splitter Control */
#define DSS_CTL1 _MMIO(0x67400)
#define SPLITTER_ENABLE (1 << 31)
--
2.32.0
[Intel-gfx] [PATCH 0/2] Enable mipi dsi on XELPD
The delta from TGL is wrt the ESC clock, and an additional WA needed. With that support in place, extend the support for mipi dsi. Vandita Kulkarni (2): drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband drm/i915/dsi/xelpd: Enable mipi dsi support. drivers/gpu/drm/i915/display/icl_dsi.c | 24 drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 8 +++ 3 files changed, 33 insertions(+) -- 2.32.0
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: switch from 'pci_' to 'dma_' API
== Series Details == Series: drm/i915: switch from 'pci_' to 'dma_' API URL : https://patchwork.freedesktop.org/series/93911/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10505_full -> Patchwork_20866_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20866_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20866_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20866_full: ### IGT changes ### Possible regressions * igt@gem_softpin@allocator-evict-all-engines: - shard-glk: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-glk9/igt@gem_soft...@allocator-evict-all-engines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/shard-glk6/igt@gem_soft...@allocator-evict-all-engines.html Known issues Here are the changes found in Patchwork_20866_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@idempotent: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/shard-snb6/igt@gem_ctx_persiste...@idempotent.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: NOTRUN -> [FAIL][4] ([i915#2846]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/shard-kbl6/igt@gem_exec_f...@basic-deadline.html - shard-apl: NOTRUN -> [FAIL][5] ([i915#2846]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/shard-apl1/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/shard-kbl2/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-tglb2/igt@gem_exec_fair@basic-p...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/shard-tglb6/igt@gem_exec_fair@basic-p...@rcs0.html - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-glk9/igt@gem_exec_fair@basic-p...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/shard-glk6/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html - shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/shard-kbl2/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2849]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_flush@basic-wb-ro-before-default: - shard-glk: [PASS][16] -> [INCOMPLETE][17] ([i915#2944]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-glk7/igt@gem_exec_fl...@basic-wb-ro-before-default.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/shard-glk4/igt@gem_exec_fl...@basic-wb-ro-before-default.html * igt@gem_exec_schedule@semaphore-codependency: - shard-snb: NOTRUN -> [SKIP][18] ([fdo#109271]) +306 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/shard-snb2/igt@gem_exec_sched...@semaphore-codependency.html * igt@gem_mmap_gtt@cpuset-big-copy: - shard-iclb: [PASS][19] -> [FAIL][20] ([i915#307]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-iclb7/igt@gem_mmap_...@cpuset-big-copy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/shard-iclb3/igt@gem_mmap_...@cpuset-big-copy.html * igt@gem_mmap_gtt@cpuset-big-copy-xy: - shard-iclb: [PASS][21] -> [FAIL][22] ([i915#2428]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-iclb1/igt@gem_mmap_...@cpuset-big-copy-xy.html [22]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/amdgpu: switch from 'pci_' to 'dma_' API
== Series Details == Series: drm/amdgpu: switch from 'pci_' to 'dma_' API URL : https://patchwork.freedesktop.org/series/93906/ State : success == Summary == CI Bug Log - changes from CI_DRM_10505_full -> Patchwork_20865_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20865_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@idempotent: - shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-snb7/igt@gem_ctx_persiste...@idempotent.html * igt@gem_eio@in-flight-contexts-1us: - shard-iclb: [PASS][2] -> [TIMEOUT][3] ([i915#3070]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-iclb2/igt@gem_...@in-flight-contexts-1us.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-iclb7/igt@gem_...@in-flight-contexts-1us.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: NOTRUN -> [FAIL][4] ([i915#2846]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-kbl3/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][5] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-kbl7/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-apl: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-apl1/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-tglb2/igt@gem_exec_fair@basic-p...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-tglb3/igt@gem_exec_fair@basic-p...@rcs0.html - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-glk9/igt@gem_exec_fair@basic-p...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-glk6/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_schedule@semaphore-codependency: - shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271]) +306 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-snb2/igt@gem_exec_sched...@semaphore-codependency.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][12] -> [SKIP][13] ([i915#2190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-tglb2/igt@gem_huc_c...@huc-copy.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@gem_mmap_gtt@cpuset-big-copy-odd: - shard-iclb: [PASS][14] -> [FAIL][15] ([i915#307]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-iclb2/igt@gem_mmap_...@cpuset-big-copy-odd.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-iclb7/igt@gem_mmap_...@cpuset-big-copy-odd.html * igt@gem_pwrite@basic-exhaustion: - shard-kbl: NOTRUN -> [WARN][16] ([i915#2658]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-kbl7/igt@gem_pwr...@basic-exhaustion.html * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs: - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-skl2/igt@gem_render_c...@y-tiled-ccs-to-y-tiled-mc-ccs.html - shard-glk: NOTRUN -> [SKIP][18] ([fdo#109271]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-glk5/igt@gem_render_c...@y-tiled-ccs-to-y-tiled-mc-ccs.html * igt@gem_set_tiling_vs_blt@tiled-to-tiled: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-skl4/igt@gem_set_tiling_vs_...@tiled-to-tiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-skl2/igt@gem_set_tiling_vs_...@tiled-to-tiled.html * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-apl1/igt@gem_soft...@noreloc-s3.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-apl6/igt@gem_soft...@noreloc-s3.html * igt@gem_userptr_blits@vma-merge: - shard-apl: NOTRUN -> [FAIL][23] ([i915#3318]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/shard-apl2/igt@gem_userptr_bl...@vma-merge.html - shard-glk: NOTRUN -> [FAIL][24] ([i915#3318]) [24]:
[Intel-gfx] ✗ Fi.CI.BUILD: failure for use DYNAMIC_DEBUG to implement DRM.debug
== Series Details ==
Series: use DYNAMIC_DEBUG to implement DRM.debug
URL : https://patchwork.freedesktop.org/series/93914/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
AR lib/lib.a
GEN lib/crc32table.h
CC lib/crc32.o
CC lib/dynamic_debug.o
lib/dynamic_debug.c: In function ‘ddebug_exec_queries’:
lib/dynamic_debug.c:601:2: error: ‘query’ undeclared (first use in this
function); did you mean ‘query_in’?
query = kstrndup(query_in, PAGE_SIZE, GFP_KERNEL);
^
query_in
lib/dynamic_debug.c:601:2: note: each undeclared identifier is reported only
once for each function it appears in
lib/dynamic_debug.c: In function ‘dynamic_debug_exec_queries’:
lib/dynamic_debug.c:621:29: error: ‘qry’ undeclared (first use in this
function); did you mean ‘query’?
return ddebug_exec_queries(qry, modname, NULL);
^~~
query
lib/dynamic_debug.c: In function ‘ddebug_exec_queries’:
lib/dynamic_debug.c:619:1: warning: ISO C90 forbids mixed declarations and code
[-Wdeclaration-after-statement]
int dynamic_debug_exec_queries(const char *query, const char *modname)
^~~
In file included from ./include/linux/linkage.h:7,
from ./include/linux/kernel.h:8,
from lib/dynamic_debug.c:16:
lib/dynamic_debug.c:623:19: error: non-static declaration of
‘dynamic_debug_exec_queries’ follows static declaration
EXPORT_SYMBOL_GPL(dynamic_debug_exec_queries);
^~
./include/linux/export.h:98:21: note: in definition of macro ‘___EXPORT_SYMBOL’
extern typeof(sym) sym; \
^~~
./include/linux/export.h:160:34: note: in expansion of macro ‘__EXPORT_SYMBOL’
#define _EXPORT_SYMBOL(sym, sec) __EXPORT_SYMBOL(sym, sec, "")
^~~
./include/linux/export.h:164:33: note: in expansion of macro ‘_EXPORT_SYMBOL’
#define EXPORT_SYMBOL_GPL(sym) _EXPORT_SYMBOL(sym, "_gpl")
^~
lib/dynamic_debug.c:623:1: note: in expansion of macro ‘EXPORT_SYMBOL_GPL’
EXPORT_SYMBOL_GPL(dynamic_debug_exec_queries);
^
lib/dynamic_debug.c:619:5: note: previous definition of
‘dynamic_debug_exec_queries’ was here
int dynamic_debug_exec_queries(const char *query, const char *modname)
^~
In file included from ./include/linux/export.h:43,
from ./include/linux/linkage.h:7,
from ./include/linux/kernel.h:8,
from lib/dynamic_debug.c:16:
./include/linux/compiler.h:241:2: warning: ISO C90 forbids mixed declarations
and code [-Wdeclaration-after-statement]
static void * __section(".discard.addressable") __used \
^~
./include/linux/export.h:51:2: note: in expansion of macro ‘__ADDRESSABLE’
__ADDRESSABLE(sym) \
^
./include/linux/export.h:108:2: note: in expansion of macro ‘__KSYMTAB_ENTRY’
__KSYMTAB_ENTRY(sym, sec)
^~~
./include/linux/export.h:152:39: note: in expansion of macro ‘___EXPORT_SYMBOL’
#define __EXPORT_SYMBOL(sym, sec, ns) ___EXPORT_SYMBOL(sym, sec, ns)
^~~~
./include/linux/export.h:160:34: note: in expansion of macro ‘__EXPORT_SYMBOL’
#define _EXPORT_SYMBOL(sym, sec) __EXPORT_SYMBOL(sym, sec, "")
^~~
./include/linux/export.h:164:33: note: in expansion of macro ‘_EXPORT_SYMBOL’
#define EXPORT_SYMBOL_GPL(sym) _EXPORT_SYMBOL(sym, "_gpl")
^~
lib/dynamic_debug.c:623:1: note: in expansion of macro ‘EXPORT_SYMBOL_GPL’
EXPORT_SYMBOL_GPL(dynamic_debug_exec_queries);
^
lib/dynamic_debug.c:637:1: warning: ISO C90 forbids mixed declarations and code
[-Wdeclaration-after-statement]
int param_set_dyndbg(const char *instr, const struct kernel_param *kp)
^~~
In file included from ./include/linux/linkage.h:7,
from ./include/linux/kernel.h:8,
from lib/dynamic_debug.c:16:
lib/dynamic_debug.c:667:15: error: non-static declaration of ‘param_set_dyndbg’
follows static declaration
EXPORT_SYMBOL(param_set_dyndbg);
^~~~
./include/linux/export.h:98:21: note: in definition of macro ‘___EXPORT_SYMBOL’
extern typeof(sym) sym; \
^~~
./include/linux/export.h:160:34: note: in expansion of macro ‘__EXPORT_SYMBOL’
#define _EXPORT_SYMBOL(sym, sec) __EXPORT_SYMBOL(sym, sec, "")
^~~
./include/linux/export.h:163:29: note: in expansion of macro ‘_EXPORT_SYMBOL’
#define EXPORT_SYMBOL(sym) _EXPORT_SYMBOL(sym, "")
^~
lib/dynamic_debug.c:667:1: note: in expansion of macro ‘EXPORT_SYMBOL’
EXPORT_SYMBOL(param_set_dyndbg);
^
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: switch from 'pci_' to 'dma_' API
== Series Details ==
Series: drm/i915: switch from 'pci_' to 'dma_' API
URL : https://patchwork.freedesktop.org/series/93911/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10505 -> Patchwork_20866
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/index.html
Known issues
Here are the changes found in Patchwork_20866 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@amdgpu/amd_prime@amd-to-i915:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +1 similar issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/fi-kbl-soraka/igt@amdgpu/amd_pr...@amd-to-i915.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-8809g: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#533])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g: NOTRUN -> [SKIP][6] ([fdo#109271]) +35 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-kbl-8809g: [DMESG-WARN][7] ([i915#3848]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/fi-kbl-8809g/igt@gem_exec_susp...@basic-s3.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/fi-kbl-8809g/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@workarounds:
- fi-rkl-guc: [INCOMPLETE][9] ([i915#3920]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3848]: https://gitlab.freedesktop.org/drm/intel/issues/3848
[i915#3920]: https://gitlab.freedesktop.org/drm/intel/issues/3920
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (40 -> 33)
--
Missing(7): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-bsw-cyan fi-apl-guc
fi-bdw-samus bat-jsl-1
Build changes
-
* Linux: CI_DRM_10505 -> Patchwork_20866
CI-20190529: 20190529
CI_DRM_10505: 7c36ed237585ed2f645439e62dafccac070d5e33 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6181: e7a9ab2f21a67b1ab3f4093ec0bd775647308ba6 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20866: 1152eea97e17a03bbe9c4b844b64499321ef0d05 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1152eea97e17 drm/i915: switch from 'pci_' to 'dma_' API
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20866/index.html
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/amdgpu: switch from 'pci_' to 'dma_' API
== Series Details == Series: drm/amdgpu: switch from 'pci_' to 'dma_' API URL : https://patchwork.freedesktop.org/series/93906/ State : success == Summary == CI Bug Log - changes from CI_DRM_10505 -> Patchwork_20865 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/index.html Known issues Here are the changes found in Patchwork_20865 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_prime@amd-to-i915: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-kbl-soraka/igt@amdgpu/amd_pr...@amd-to-i915.html * igt@core_hotunplug@unbind-rebind: - fi-rkl-guc: [PASS][2] -> [DMESG-WARN][3] ([i915#3925]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/fi-rkl-guc/igt@core_hotunp...@unbind-rebind.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-rkl-guc/igt@core_hotunp...@unbind-rebind.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html - fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][6] ([i915#1155]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rpm@module-reload: - fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][7] ([i915#4006]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-tgl-1115g4/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@execlists: - fi-bsw-kefka: [PASS][8] -> [INCOMPLETE][9] ([i915#2940]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html * igt@kms_addfb_basic@too-wide: - fi-tgl-1115g4: NOTRUN -> [DMESG-WARN][10] ([i915#4002]) +90 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-tgl-1115g4/igt@kms_addfb_ba...@too-wide.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-edid-read: - fi-kbl-8809g: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([fdo#109285]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-8809g: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@cursor_plane_move: - fi-kbl-8809g: NOTRUN -> [SKIP][15] ([fdo#109271]) +35 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][16] ([i915#1072]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html * igt@kms_psr@primary_page_flip: - fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([i915#1072] / [i915#1385]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-tgl-1115g4/igt@kms_psr@primary_page_flip.html * igt@prime_vgem@basic-userptr: - fi-tgl-1115g4: NOTRUN -> [SKIP][18] ([i915#3301]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html * igt@runner@aborted: - fi-rkl-guc: NOTRUN -> [FAIL][19] ([i915#1602]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-rkl-guc/igt@run...@aborted.html - fi-tgl-1115g4: NOTRUN -> [FAIL][20] ([i915#2722] / [i915#3834]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20865/fi-tgl-1115g4/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-kbl-8809g: [DMESG-WARN][21] ([i915#3848]) -> [PASS][22] [21]:
[Intel-gfx] [PATCH v6 06/11] drm_print: add choice to use dynamic debug in drm-debug
drm's debug system writes 10 distinct categories of messages to syslog
using a small API[1]: drm_dbg*(10 names), DRM_DEBUG*(8 names),
DRM_DEV_DEBUG*(3 names). There are thousands of these callsites, each
categorized by their authors.
These callsites can be enabled at runtime by their category, each
controlled by a bit in drm.debug (/sys/modules/drm/parameter/debug).
In the current "basic" implementation, drm_debug_enabled() tests these
bits in __drm_debug each time an API[1] call is executed; while cheap
individually, the costs accumulate.
This patch uses dynamic-debug with jump-label to patch enabled calls
onto their respective NOOP slots, avoiding all runtime bit-checks of
__drm_debug.
Dynamic debug has no concept of category, but we can emulate one by
replacing enum categories with a set of prefix-strings; "drm:core:",
"drm:kms:" "drm:driver:" etc, and prepend them (at compile time) to
the given formats.
Then we can use:
`echo module drm format "^drm:core: " +p > control`
to enable the whole category with one query.
This conversion yields ~2100 new callsites on my i7/i915 laptop:
dyndbg: 195 debug prints in module drm_kms_helper
dyndbg: 298 debug prints in module drm
dyndbg: 1630 debug prints in module i915
CONFIG_DRM_USE_DYNAMIC_DEBUG enables this, and is available if
CONFIG_DYNAMIC_DEBUG or CONFIG_DYNAMIC_DEBUG_CORE is chosen, and if
CONFIG_JUMP_LABEL is enabled; this because its required to get the
promised optimizations.
The "basic" -> "dyndbg" switchover is layered into the macro scheme
A. use DEFINE_DYNAMIC_DEBUG_CATEGORIES(debug, __drm_debug,
"DRM debug category-per-bit control",
{ "drm:core:", "enable CORE debug messages" },
{ "drm:kms:", "enable KMS debug messages" }, ...);
B. A "classy" version of DRM_UT_ map, named DRM_DBG_CAT_
DRM_DBG_CLASS_ was proposed, I had agreed, but reconsidered;
CATEGORY is already DRM's term-of-art, and adding a near-synonym
'CLASS' only adds ambiguity.
"basic": DRM_DBG_CAT_ <=== DRM_UT_. Identity map.
"dyndbg":
#define DRM_DBG_CAT_KMS"drm:kms: "
#define DRM_DBG_CAT_PRIME "drm:prime: "
#define DRM_DBG_CAT_ATOMIC "drm:atomic: "
DRM_UT_* are preserved, since theyre used elsewhere.
We can probably reduce its use further, but thats a separate thing.
C. drm_dev_dbg() & drm_debug() are interposed with macros
basic: forward to renamed fn, with args preserved
enabled: redirect to pr_debug, dev_dbg, with CATEGORY # format
this is where drm_debug_enabled() is avoided.
prefix is prepended at compile-time, no category at runtime.
D. API[1] uses DRM_DBG_CAT_s
these already use (C), now they use (B) too,
to get the correct token type for "basic" and "dyndbg" configs.
NOTES:
Because the dyndbg callback is watching __drm_debug, it is coherent
with drm_debug_enabled(), the switchover should be transparent.
Code Review is expected to catch lack of correspondence between
bit=>prefix definitions (the selector) and the prefixes used in the
API[1] layer above pr_debug()
I've coded the search-prefixes/categories with a trailing space, which
excludes any sub-categories added later. This convention protects any
"drm:atomic:fail:" callsites from getting stomped on by `echo 0 > debug`.
Other categories could differ, but we need some default.
Dyndbg requires that the prefix be in the compiled-in format string;
run-time prefixing evades callsite selection by category.
pr_debug("%s: ...", __func__, ...) // not ideal
With "lineno X" in a query, its possible to enable single callsites,
but it is tedious, and useless in a category context.
Unfortunately __func__ is not a macro, and cannot be catenated at
preprocess/compile time.
Signed-off-by: Jim Cromie
---
v6:
. add kernel doc
. fix cpp paste, drop '#'
v5:
. use DEFINE_DYNAMIC_DEBUG_CATEGORIES in drm_print.c
. s/DRM_DBG_CLASS_/DRM_DBG_CAT_/ - dont need another term
. default=y in KBuild entry - per @DanVet
. move some commit-log prose to dyndbg commit
. add-prototyes to (param_get/set)_dyndbg
. more wrinkles found by
. relocate ratelimit chunk from elsewhere
---
drivers/gpu/drm/Kconfig | 13
drivers/gpu/drm/drm_print.c | 49 +
include/drm/drm_print.h | 142
3 files changed, 160 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 7ff89690a976..97e38d86fd27 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -57,6 +57,19 @@ config DRM_DEBUG_MM
If in doubt, say "N".
+config DRM_USE_DYNAMIC_DEBUG
+ bool "use dynamic debug to implement drm.debug"
+ default y
+ depends on DRM
+ depends on DYNAMIC_DEBUG || DYNAMIC_DEBUG_CORE
+ depends on JUMP_LABEL
+ help
+ The "basic" drm.debug facility does a lot of unlikely
+ bit-field tests at runtime; while cheap individually, the
+ cost
[Intel-gfx] [PATCH v6 11/11] dyndbg: RFC add print-once and print-ratelimited features. RFC.
Its tautological that having pr_debug()s with optional print-once and
rate-limiting features could be useful. Build it, they will come.
The advantages:
- dynamically configured with flags
- can use them on existing callsites
- printonce is easy, (almost) just new flags
no additional resources
- ratelimiting is pooled, expecting rare use
provisioned only for enabled & ratelimited callsites
- RFC ratelimit grouping
mostly to reduce resources
reduces to choice of hash key: module, function, file, line
Whats done here:
Expand ddebug.flags to 11 bits, and define new flags to support
print-once and ratelimited semantics:
echo file init/main.c +o > control# init/main runs just once anyway
echo module foo +r > control # turn on ratelimiting
echo module foo +g > control # turn on group flag
is_onced_or_ratelimited() tests these conditions, it is called from
__dynamic_pr_debug() and others (which are all behind the '+p'
enablement test).
NB: test_dynamic_debug.ko ratelimiting test triggers reports on
is_onced_or_ratelimited() as the limited source.
PRINT-ONCE: can be done with just +2 bits in flags;
.o _DPRINTK_FLAGS_ONCE enables state test and set
.P _DPRINTK_FLAGS_PRINTED state bit
Just adding the flags lets the existing code operate on them.
We will need new code to enforce constraints on flag combos;
'+ro' is nonsense, but this can wait, or can take a new meaning.
RATE-LIMITING:
.r _DPRINTK_FLAGS_RATELIMITED - track & limit prdbgs callrate
We wait until a prdebug is called, and if RATELIMITED is set, THEN
lookup a RateLimitState (RL) for it. If found, bump its state and
return true/false, otherwise create & initialize one and return false.
RFC: GROUP-FLAG:
.g _DPRINTK_FLAGS_GROUPED
Currently, the hash-key is just the prdebug descriptor, so is unique
per prdebug. With the 'g' flag, we could use a different key, for
example desc->site.function, to get a shared ratelimit for whole
functions.
This gets subtly different behavior at the ratelimit transition, but
it is predictable for a given function (except perhaps recursive, but
thats not done anyway).
Note also that any function can have a single group of prdebugs, plus
any number of prdbgs without 'g', either with or without 'r'. So
grouping should be flexible enough to use advantageously.
Signed-off-by: Jim Cromie
---
v6: new to patchset
---
include/linux/dynamic_debug.h | 19 --
lib/dynamic_debug.c | 125 +-
2 files changed, 137 insertions(+), 7 deletions(-)
diff --git a/include/linux/dynamic_debug.h b/include/linux/dynamic_debug.h
index 8807367c7903..e9871557cff1 100644
--- a/include/linux/dynamic_debug.h
+++ b/include/linux/dynamic_debug.h
@@ -28,26 +28,33 @@ struct _ddebug {
* writes commands to /dynamic_debug/control
*/
#define _DPRINTK_FLAGS_NONE0
-#define _DPRINTK_FLAGS_PRINT (1<<0) /* printk() a message */
+#define _DPRINTK_FLAGS_PRINT (1<<4) /* printk() a message */
#define _DPRINTK_FLAGS_PRINT_TRACE (1<<5) /* call (*tracer) */
#define _DPRINTK_ENABLED (_DPRINTK_FLAGS_PRINT | _DPRINTK_FLAGS_PRINT_TRACE)
-#define _DPRINTK_FLAGS_INCL_MODNAME(1<<1)
-#define _DPRINTK_FLAGS_INCL_FUNCNAME (1<<2)
-#define _DPRINTK_FLAGS_INCL_LINENO (1<<3)
-#define _DPRINTK_FLAGS_INCL_TID(1<<4)
+#define _DPRINTK_FLAGS_INCL_MODNAME(1<<0)
+#define _DPRINTK_FLAGS_INCL_FUNCNAME (1<<1)
+#define _DPRINTK_FLAGS_INCL_LINENO (1<<2)
+#define _DPRINTK_FLAGS_INCL_TID(1<<3)
#define _DPRINTK_FLAGS_INCL_ANY\
(_DPRINTK_FLAGS_INCL_MODNAME | _DPRINTK_FLAGS_INCL_FUNCNAME |\
_DPRINTK_FLAGS_INCL_LINENO | _DPRINTK_FLAGS_INCL_TID)
+#define _DPRINTK_FLAGS_ONCE(1<<6) /* print once flag */
+#define _DPRINTK_FLAGS_PRINTED (1<<7) /* print once state */
+#define _DPRINTK_FLAGS_RATELIMITED (1<<8)
+#define _DPRINTK_FLAGS_GROUPED (1<<9) /* manipulate as a group */
+#define _DPRINTK_FLAGS_DELETE_SITE (1<<10) /* drop site info to save ram */
+
#if defined DEBUG
#define _DPRINTK_FLAGS_DEFAULT _DPRINTK_FLAGS_PRINT
#else
#define _DPRINTK_FLAGS_DEFAULT 0
#endif
- unsigned int flags:8;
+ unsigned int flags:11;
+
#ifdef CONFIG_JUMP_LABEL
union {
struct static_key_true dd_key_true;
diff --git a/lib/dynamic_debug.c b/lib/dynamic_debug.c
index 60bf2c01db1a..16e4db04082b 100644
--- a/lib/dynamic_debug.c
+++ b/lib/dynamic_debug.c
@@ -83,13 +83,19 @@ static inline const char *trim_prefix(const char *path)
return path + skip;
}
-static struct { unsigned flag:8; char opt_char; } opt_array[] = {
+static struct { unsigned flag:12; char opt_char; } opt_array[] = {
{ _DPRINTK_FLAGS_PRINT, 'p' },
{ _DPRINTK_FLAGS_PRINT_TRACE, 'T' },
{ _DPRINTK_FLAGS_INCL_MODNAME, 'm' },
{ _DPRINTK_FLAGS_INCL_FUNCNAME, 'f' },
{ _DPRINTK_FLAGS_INCL_LINENO, 'l' },
[Intel-gfx] [PATCH v6 08/11] amdgpu_ucode: reduce number of pr_debug calls
There are blocks of DRM_DEBUG calls, consolidate their args into
single calls. With dynamic-debug in use, each callsite consumes 56
bytes of ro callsite data, and this patch removes about 65 calls, so
it saves ~3.5kb.
no functional changes.
RFC: this creates multi-line log messages, does that break any syslog
conventions ?
Signed-off-by: Jim Cromie
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 293 --
1 file changed, 158 insertions(+), 135 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 2834981f8c08..14a9fef1f4c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -30,17 +30,26 @@
static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header
*hdr)
{
- DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
- DRM_DEBUG("header_size_bytes: %u\n",
le32_to_cpu(hdr->header_size_bytes));
- DRM_DEBUG("header_version_major: %u\n",
le16_to_cpu(hdr->header_version_major));
- DRM_DEBUG("header_version_minor: %u\n",
le16_to_cpu(hdr->header_version_minor));
- DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
- DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
- DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
- DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
- DRM_DEBUG("ucode_array_offset_bytes: %u\n",
- le32_to_cpu(hdr->ucode_array_offset_bytes));
- DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
+ DRM_DEBUG("size_bytes: %u\n"
+ "header_size_bytes: %u\n"
+ "header_version_major: %u\n"
+ "header_version_minor: %u\n"
+ "ip_version_major: %u\n"
+ "ip_version_minor: %u\n"
+ "ucode_version: 0x%08x\n"
+ "ucode_size_bytes: %u\n"
+ "ucode_array_offset_bytes: %u\n"
+ "crc32: 0x%08x\n",
+ le32_to_cpu(hdr->size_bytes),
+ le32_to_cpu(hdr->header_size_bytes),
+ le16_to_cpu(hdr->header_version_major),
+ le16_to_cpu(hdr->header_version_minor),
+ le16_to_cpu(hdr->ip_version_major),
+ le16_to_cpu(hdr->ip_version_minor),
+ le32_to_cpu(hdr->ucode_version),
+ le32_to_cpu(hdr->ucode_size_bytes),
+ le32_to_cpu(hdr->ucode_array_offset_bytes),
+ le32_to_cpu(hdr->crc32));
}
void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
@@ -55,9 +64,9 @@ void amdgpu_ucode_print_mc_hdr(const struct
common_firmware_header *hdr)
const struct mc_firmware_header_v1_0 *mc_hdr =
container_of(hdr, struct mc_firmware_header_v1_0,
header);
- DRM_DEBUG("io_debug_size_bytes: %u\n",
- le32_to_cpu(mc_hdr->io_debug_size_bytes));
- DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
+ DRM_DEBUG("io_debug_size_bytes: %u\n"
+ "io_debug_array_offset_bytes: %u\n",
+ le32_to_cpu(mc_hdr->io_debug_size_bytes),
le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
} else {
DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major,
version_minor);
@@ -82,13 +91,17 @@ void amdgpu_ucode_print_smc_hdr(const struct
common_firmware_header *hdr)
switch (version_minor) {
case 0:
v2_0_hdr = container_of(hdr, struct
smc_firmware_header_v2_0, v1_0.header);
- DRM_DEBUG("ppt_offset_bytes: %u\n",
le32_to_cpu(v2_0_hdr->ppt_offset_bytes));
- DRM_DEBUG("ppt_size_bytes: %u\n",
le32_to_cpu(v2_0_hdr->ppt_size_bytes));
+ DRM_DEBUG("ppt_offset_bytes: %u\n"
+ "ppt_size_bytes: %u\n",
+ le32_to_cpu(v2_0_hdr->ppt_offset_bytes),
+ le32_to_cpu(v2_0_hdr->ppt_size_bytes));
break;
case 1:
v2_1_hdr = container_of(hdr, struct
smc_firmware_header_v2_1, v1_0.header);
- DRM_DEBUG("pptable_count: %u\n",
le32_to_cpu(v2_1_hdr->pptable_count));
- DRM_DEBUG("pptable_entry_offset: %u\n",
le32_to_cpu(v2_1_hdr->pptable_entry_offset));
+ DRM_DEBUG("pptable_count: %u\n"
+ "pptable_entry_offset: %u\n",
+ le32_to_cpu(v2_1_hdr->pptable_count),
+ le32_to_cpu(v2_1_hdr->pptable_entry_offset));
break;
default:
break;
@@ -111,10 +124,12 @@
[Intel-gfx] [PATCH v6 05/11] amdgpu: use DEFINE_DYNAMIC_DEBUG_CATEGORIES to control categorized pr_debugs
logger_types.h defines many DC_LOG_*() categorized debug wrappers.
Most of these use DRM debug API, so are controllable using drm.debug,
but others use bare pr_debug("$prefix: .."), each with a different
class-prefix matching "^\[\w+\]:"
Use DEFINE_DYNAMIC_DEBUG_CATEGORIES to create a /sys debug_dc
parameter, modinfos, and to specify a map from bits -> categorized
pr_debugs to be controlled.
Signed-off-by: Jim Cromie
---
.../gpu/drm/amd/display/dc/core/dc_debug.c| 44 ++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 21be2a684393..69e68d721512 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -36,8 +36,50 @@
#include "resource.h"
-#define DC_LOGGER_INIT(logger)
+#ifdef DRM_USE_DYNAMIC_DEBUG
+/* define a drm.debug style dyndbg pr-debug control point */
+#include
+
+unsigned long __debug_dc;
+EXPORT_SYMBOL(__debug_dc);
+
+#define _help_(key)"\t " key "\t- help for " key "\n"
+
+/* Id like to do these inside DEFINE_DYNAMIC_DEBUG_CATEGORIES, if possible */
+#define DC_DYNDBG_BITMAP_DESC(name)\
+ "Control pr_debugs via /sys/module/amdgpu/parameters/" #name\
+ ", where each bit controls a debug category.\n" \
+ _help_("[SURFACE]:")\
+ _help_("[CURSOR]:") \
+ _help_("[PFLIP]:") \
+ _help_("[VBLANK]:") \
+ _help_("[HW_LINK_TRAINING]:") \
+ _help_("[HW_AUDIO]:") \
+ _help_("[SCALER]:") \
+ _help_("[BIOS]:") \
+ _help_("[BANDWIDTH_CALCS]:")\
+ _help_("[DML]:")\
+ _help_("[IF_TRACE]:") \
+ _help_("[GAMMA]:") \
+ _help_("[SMU_MSG]:")
+
+DEFINE_DYNAMIC_DEBUG_CATEGORIES(debug_dc, __debug_dc,
+ DC_DYNDBG_BITMAP_DESC(debug_dc),
+ _DD_cat_("[CURSOR]:"),
+ _DD_cat_("[PFLIP]:"),
+ _DD_cat_("[VBLANK]:"),
+ _DD_cat_("[HW_LINK_TRAINING]:"),
+ _DD_cat_("[HW_AUDIO]:"),
+ _DD_cat_("[SCALER]:"),
+ _DD_cat_("[BIOS]:"),
+ _DD_cat_("[BANDWIDTH_CALCS]:"),
+ _DD_cat_("[DML]:"),
+ _DD_cat_("[IF_TRACE]:"),
+ _DD_cat_("[GAMMA]:"),
+ _DD_cat_("[SMU_MSG]:"));
+#endif
+#define DC_LOGGER_INIT(logger)
#define SURFACE_TRACE(...) do {\
if (dc->debug.surface_trace) \
--
2.31.1
[Intel-gfx] [PATCH v6 10/11] dyndbg: RFC add debug-trace callback, selftest with it. RFC
Sean Paul seanp...@chromium.org proposed, in https://patchwork.freedesktop.org/series/78133/ drm/trace: Mirror DRM debug logs to tracefs That patchset's objective is to be able to independently steer some of the debug stream to an alternate tracing destination, by splitting drm_debug_enabled() into syslog & trace flavors, and enabling them separately with a drm.debug_trace knob. 2 advantages are identified: - syslog is heavyweight, alternate stream is lighter - steering selected categories separately means less traffic Dynamic-Debug can do this better: 1- all work is behind jump-label's NOOP, Zero overhead when off. 2- perfect site selectivity, no unwanted traffic. drm's debug categories are a general classification system, not one tailored to pick out the exact pool of pr_debugs to watch/trace. With drm.debug built on dyndbg, the given "drm::" system can be used to select a base trace-set, which can then be adjusted +/-, and/or augmented with unrelated pr_debugs that just happen to be useful. And this tweaking can be done at the command-line, and reduced to a script. Then the string-prefix "drm::" system can be extended to suit. The basic elements: - add a new struct _ddebug member: (*tracer)(char *format, ...) - add a new T flag to enable tracer - adjust the static-key-enable/disable condition for (p|T) - if (p) before printk, since T enables too. - if (T) call tracer if its true = int dynamic_debug_register_tracer(query, modname, tracer); = int dynamic_debug_unregister_tracer(query, modname, cookie); This new interface lets clients set/unset a tracer function on each callsite matching the query, for example: "drm:atomic:fail:". Clients must unregister the same callsites they register, allowing protection of each client's dyndbg-state setup against overwrites by others, while allowing maximal sharing of 1 slot/callsite. The internal call-chain gets some rework: it gets new void* tracer param, which dynamic_debug_exec_queries() hides from public. And convert ddebug_exec_queries() to wrap __ddebug_exec_queries(), and move the query copy code to it. public: passing down: dynamic_debug_(un)register_tracer tracer dynamic_debug_exec_queriestracer=NULL calling: ddebug_exec_queries copies ro-query, tracer __ddebug_exec_queries modifies query, tracer ddebug_exec_query modifies query, tracer Then adjust most ddebug_exec_queries users to __ddebug_exec_queries Intended Behavior: (things are in flux, RFC) - register sets empty slot, doesn't overwrite the query selects callsites, and sets +T (grammar requires +-action) - register allows same-tracer over-set wo warn 2nd register can then enable superset, subset, disjoint set - unregister clears slot if it matches cookie/tracer query selects set, -T (as tested) tolerates over-clears - dd-exec-queries(+/-T) can modify the enablements not sure its needed, but it falls out.. The code is currently in-line in ddebug_change(), to be moved to separate fn, rc determines flow, may also veto/alter changes by altering flag-settings - tbd. TBD: Im not sure what happens when exec-queries(+T) hits a site wo a tracer (silence I think. maybe not ideal). SELFTEST: test_dynamic_debug.ko: Uses the tracer facility to implement a selftest: - DUT(x) calls a set of categorized pr_debugs x times - A custom tracer counts the number of calls (of T-enabled pr_debugs), - test registers the tracer on the function, then iteratively: manipulates dyndbg states via query-cmds calls DUT(x) counts enabled callsite executions reports mismatches - modprobe test_dynamic_debug broken_tracer=1 attaches a broken tracer: recursive on pr_debug Bad Things Happen. has thrown me interesting panics. This needs more work. RFC. waste of time due to use_bad_tracer properties ? NOTES: Next step: replace tracer member with a hashtable lookup, done only when T. Registration then becomes populating the hashtable; mod->name would make a good key, which would limit tracer mapping granularity to 1 registrant per module, but not enablement, which is still the per-callsite bit. ERRORS (or WARNINGS): It should be an error to +T a callsite which has no aux_print set (ie already registered with a query that selected that callsite). This tacitly enforces registration. Then +T,-T can toggle those aux_print callsites (or subsets of them) to tailor the debug-stream for the purpose. Controlling flow is the best work limiter. Signed-off-by: Jim Cromie --- v5: (this patch sent after (on top of) v4) . fix "too many arguments to function", and name the args: int (*aux_print)(const char *fmt, char *prefix, char *label, void *); prefix : is a slot for dynamic_emit_prefix, or for custom buffer insert label : for builtin-caller used by drm-trace-print void* : vaf, add type constraint later. . fix printk (to syslog) needs if (+p), since +T
[Intel-gfx] [PATCH v6 09/11] nouveau: fold multiple DRM_DEBUG_DRIVERs together
With DRM_USE_DYNAMIC_DEBUG, each callsite record requires 56 bytes.
We can combine 12 into one here and save ~620 bytes.
Signed-off-by: Jim Cromie
---
---
drivers/gpu/drm/nouveau/nouveau_drm.c | 36 +--
1 file changed, 23 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c
b/drivers/gpu/drm/nouveau/nouveau_drm.c
index a616cf4573b8..58693e40b447 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -1246,19 +1246,29 @@ nouveau_drm_pci_table[] = {
static void nouveau_display_options(void)
{
- DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
-
- DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
- DRM_DEBUG_DRIVER("... ignorelid: %d\n", nouveau_ignorelid);
- DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
- DRM_DEBUG_DRIVER("... nofbaccel: %d\n", nouveau_nofbaccel);
- DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
- DRM_DEBUG_DRIVER("... debug: %s\n", nouveau_debug);
- DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
- DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
- DRM_DEBUG_DRIVER("... runpm: %d\n", nouveau_runtime_pm);
- DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
- DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
+ DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n"
+"... tv_disable : %d\n"
+"... ignorelid: %d\n"
+"... duallink : %d\n"
+"... nofbaccel: %d\n"
+"... config : %s\n"
+"... debug: %s\n"
+"... noaccel : %d\n"
+"... modeset : %d\n"
+"... runpm: %d\n"
+"... vram_pushbuf : %d\n"
+"... hdmimhz : %d\n"
+, nouveau_tv_disable
+, nouveau_ignorelid
+, nouveau_duallink
+, nouveau_nofbaccel
+, nouveau_config
+, nouveau_debug
+, nouveau_noaccel
+, nouveau_modeset
+, nouveau_runtime_pm
+, nouveau_vram_pushbuf
+, nouveau_hdmimhz);
}
static const struct dev_pm_ops nouveau_pm_ops = {
--
2.31.1
[Intel-gfx] [PATCH v6 07/11] drm_print: instrument drm_debug_enabled
Duplicate drm_debug_enabled() code into both "basic" and "dyndbg"
ifdef branches. Then add a pr_debug("todo: ...") into the "dyndbg"
branch.
Then convert the "dyndbg" branch's code to a macro, so that its
pr_debug() get its callsite info from the invoking function, instead
of from drm_debug_enabled() itself.
This gives us unique callsite info for the 8 remaining users of
drm_debug_enabled(), and lets us enable them individually to see how
much logging traffic they generate. The oft-visited callsites can
then be reviewed for runtime cost and possible optimizations.
Heres what we get:
bash-5.1# modprobe drm
dyndbg: 384 debug prints in module drm
bash-5.1# grep todo: /proc/dynamic_debug/control
drivers/gpu/drm/drm_edid.c:1843 [drm]connector_bad_edid =_ "todo: maybe avoid
via dyndbg\012"
drivers/gpu/drm/drm_print.c:309 [drm]___drm_dbg =p "todo: maybe avoid via
dyndbg\012"
drivers/gpu/drm/drm_print.c:286 [drm]__drm_dev_dbg =p "todo: maybe avoid via
dyndbg\012"
drivers/gpu/drm/drm_vblank.c:1491 [drm]drm_vblank_restore =_ "todo: maybe avoid
via dyndbg\012"
drivers/gpu/drm/drm_vblank.c:787
[drm]drm_crtc_vblank_helper_get_vblank_timestamp_internal =_ "todo: maybe avoid
via dyndbg\012"
drivers/gpu/drm/drm_vblank.c:410 [drm]drm_crtc_accurate_vblank_count =_ "todo:
maybe avoid via dyndbg\012"
drivers/gpu/drm/drm_atomic_uapi.c:1457 [drm]drm_mode_atomic_ioctl =_ "todo:
maybe avoid via dyndbg\012"
drivers/gpu/drm/drm_edid_load.c:178 [drm]edid_load =_ "todo: maybe avoid via
dyndbg\012"
At quick glance, edid won't qualify, drm_print might, drm_vblank is
strongest chance, maybe atomic-ioctl too.
Signed-off-by: Jim Cromie
---
---
include/drm/drm_print.h | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index 8775b67ecb30..1f8a65eb5d9a 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -378,6 +378,11 @@ enum drm_debug_category {
#define DRM_DBG_CAT_DP DRM_UT_DP
#define DRM_DBG_CAT_DRMRES DRM_UT_DRMRES
+static inline bool drm_debug_enabled(enum drm_debug_category category)
+{
+ return unlikely(__drm_debug & category);
+}
+
#else /* CONFIG_DRM_USE_DYNAMIC_DEBUG */
/* join prefix+format in cpp so dyndbg can see it */
@@ -397,12 +402,13 @@ enum drm_debug_category {
#define DRM_DBG_CAT_DP "drm:dp: "
#define DRM_DBG_CAT_DRMRES "drm:res: " /* not in MODULE_PARM_DESC */
-#endif /* CONFIG_DRM_USE_DYNAMIC_DEBUG */
+#define drm_debug_enabled(category)\
+ ({ \
+ pr_debug("todo: maybe avoid via dyndbg\n"); \
+ unlikely(__drm_debug & category); \
+ })
-static inline bool drm_debug_enabled(enum drm_debug_category category)
-{
- return unlikely(__drm_debug & category);
-}
+#endif /* CONFIG_DRM_USE_DYNAMIC_DEBUG */
/*
* struct device based logging
--
2.31.1
[Intel-gfx] [PATCH v6 03/11] i915/gvt: remove spaces in pr_debug "gvt: core:" etc prefixes
Taking embedded spaces out of existing prefixes makes them better
class-prefixes; simplifying the nested quoting needed otherwise:
$> echo "format '^gvt: core:' +p" >control
Dropping the internal spaces means any trailing space in a query will
more clearly terminate the prefix being searched for.
Consider a generic drm-debug example:
# turn off ATOMIC reports
echo format "^drm:atomic: " -p > control
# turn off all ATOMIC:* reports, including any sub-categories
echo format "^drm:atomic:" -p > control
# turn on ATOMIC:FAIL: reports
echo format "^drm:atomic:fail: " +p > control
Removing embedded spaces in the class-prefixes simplifies the
corresponding match-prefix. This means that "quoted" match-prefixes
are only needed when the trailing space is desired, in order to
exclude explicitly sub-categorized pr-debugs; in this example,
"drm:atomic:fail:".
RFC: maybe the prefix catenation should paste in the " " class-prefix
terminator explicitly. A pr_debug_() flavor could exclude the " ",
allowing ad-hoc sub-categorization by appending for example, "fail:"
to "drm:atomic:".
Signed-off-by: Jim Cromie
---
drivers/gpu/drm/i915/gvt/debug.h | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/debug.h b/drivers/gpu/drm/i915/gvt/debug.h
index c6027125c1ec..b4021f41c546 100644
--- a/drivers/gpu/drm/i915/gvt/debug.h
+++ b/drivers/gpu/drm/i915/gvt/debug.h
@@ -36,30 +36,30 @@ do {
\
} while (0)
#define gvt_dbg_core(fmt, args...) \
- pr_debug("gvt: core: "fmt, ##args)
+ pr_debug("gvt:core: "fmt, ##args)
#define gvt_dbg_irq(fmt, args...) \
- pr_debug("gvt: irq: "fmt, ##args)
+ pr_debug("gvt:irq: "fmt, ##args)
#define gvt_dbg_mm(fmt, args...) \
- pr_debug("gvt: mm: "fmt, ##args)
+ pr_debug("gvt:mm: "fmt, ##args)
#define gvt_dbg_mmio(fmt, args...) \
- pr_debug("gvt: mmio: "fmt, ##args)
+ pr_debug("gvt:mmio: "fmt, ##args)
#define gvt_dbg_dpy(fmt, args...) \
- pr_debug("gvt: dpy: "fmt, ##args)
+ pr_debug("gvt:dpy: "fmt, ##args)
#define gvt_dbg_el(fmt, args...) \
- pr_debug("gvt: el: "fmt, ##args)
+ pr_debug("gvt:el: "fmt, ##args)
#define gvt_dbg_sched(fmt, args...) \
- pr_debug("gvt: sched: "fmt, ##args)
+ pr_debug("gvt:sched: "fmt, ##args)
#define gvt_dbg_render(fmt, args...) \
- pr_debug("gvt: render: "fmt, ##args)
+ pr_debug("gvt:render: "fmt, ##args)
#define gvt_dbg_cmd(fmt, args...) \
- pr_debug("gvt: cmd: "fmt, ##args)
+ pr_debug("gvt:cmd: "fmt, ##args)
#endif
--
2.31.1
[Intel-gfx] [PATCH v6 04/11] i915/gvt: use DEFINE_DYNAMIC_DEBUG_CATEGORIES to create "gvt:core:" etc categories
The gvt component of this driver has ~120 pr_debugs, in 9 categories
quite similar to those in DRM. Following the interface model of
drm.debug, add a parameter to map bits to these categorizations.
DEFINE_DYNAMIC_DEBUG_CATEGORIES(debug_gvt, __gvt_debug,
"dyndbg bitmap desc",
{ "gvt:cmd: ", "command processing" },
{ "gvt:core: ", "core help" },
{ "gvt:dpy: ", "display help" },
{ "gvt:el: ", "help" },
{ "gvt:irq: ", "help" },
{ "gvt:mm: ", "help" },
{ "gvt:mmio: ", "help" },
{ "gvt:render: ", "help" },
{ "gvt:sched: " "help" });
The actual patch has a few details different, cmd_help() macro emits
the initialization construct.
if CONFIG_DRM_USE_DYNAMIC_DEBUG, then -DDYNAMIC_DEBUG_MODULE is added
cflags, by gvt/Makefile.
Signed-off-by: Jim Cromie
---
v4+:
. static decl of vector of bit->class descriptors - Emil.V
. relocate gvt-makefile chunk from elsewhere
---
drivers/gpu/drm/i915/gvt/Makefile | 4
drivers/gpu/drm/i915/i915_params.c | 35 ++
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/gvt/Makefile
b/drivers/gpu/drm/i915/gvt/Makefile
index ea8324abc784..846ba73b8de6 100644
--- a/drivers/gpu/drm/i915/gvt/Makefile
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -7,3 +7,7 @@ GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o
trace_points.o firmware.o \
ccflags-y += -I $(srctree)/$(src) -I
$(srctree)/$(src)/$(GVT_DIR)/
i915-y += $(addprefix $(GVT_DIR)/,
$(GVT_SOURCE))
+
+#ifdef CONFIG_DRM_USE_DYNAMIC_DEBUG
+ccflags-y += -DDYNAMIC_DEBUG_MODULE
+#endif
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index e07f4cfea63a..683e942a074e 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -265,3 +265,38 @@ void i915_params_free(struct i915_params *params)
I915_PARAMS_FOR_EACH(FREE);
#undef FREE
}
+
+#ifdef DRM_USE_DYNAMIC_DEBUG
+/* todo: needs DYNAMIC_DEBUG_MODULE in some cases */
+
+unsigned long __gvt_debug;
+EXPORT_SYMBOL(__gvt_debug);
+
+#define _help(key) "\t\"" key "\"\t: help for " key "\n"
+
+#define I915_GVT_CATEGORIES(name) \
+ " Enable debug output via /sys/module/i915/parameters/" #name \
+ ", where each bit enables a debug category.\n" \
+ _help("gvt:cmd:") \
+ _help("gvt:core:") \
+ _help("gvt:dpy:") \
+ _help("gvt:el:")\
+ _help("gvt:irq:") \
+ _help("gvt:mm:")\
+ _help("gvt:mmio:") \
+ _help("gvt:render:")\
+ _help("gvt:sched:")
+
+DEFINE_DYNAMIC_DEBUG_CATEGORIES(debug_gvt, __gvt_debug,
+ I915_GVT_CATEGORIES(debug_gvt),
+ _DD_cat_("gvt:cmd:"),
+ _DD_cat_("gvt:core:"),
+ _DD_cat_("gvt:dpy:"),
+ _DD_cat_("gvt:el:"),
+ _DD_cat_("gvt:irq:"),
+ _DD_cat_("gvt:mm:"),
+ _DD_cat_("gvt:mmio:"),
+ _DD_cat_("gvt:render:"),
+ _DD_cat_("gvt:sched:"));
+
+#endif
--
2.31.1
[Intel-gfx] [PATCH v6 02/11] dyndbg: add DEFINE_DYNAMIC_DEBUG_CATEGORIES and callbacks
DEFINE_DYNAMIC_DEBUG_CATEGORIES(name, var, bitmap_desc, @bit_descs)
allows users to define a drm.debug style (bitmap) sysfs interface, and
to specify the desired mapping from bits[0-N] to the format-prefix'd
pr_debug()s to be controlled.
DEFINE_DYNAMIC_DEBUG_CATEGORIES(debug_gvt, __gvt_debug,
"i915/gvt bitmap desc",
/**
* search-prefixes, passed to dd-exec_queries
* defines bits 0-N in order.
* leading ^ is tacitly inserted (by callback currently)
* trailing space used here excludes subcats.
* helper macro needs more work
* macro to autogen ++$i, 0x%x$i ?
*/
_DD_cat_("gvt:cmd: "),
_DD_cat_("gvt:core: "),
_DD_cat_("gvt:dpy: "),
_DD_cat_("gvt:el: "),
_DD_cat_("gvt:irq: "),
_DD_cat_("gvt:mm: "),
_DD_cat_("gvt:mmio: "),
_DD_cat_("gvt:render: "),
_DD_cat_("gvt:sched: "));
dynamic_debug.c: add 3 new elements:
- int param_set_dyndbg()
- int param_get_dyndbg()
- struct kernel_param_ops param_ops_dyndbg
Following the model of kernel/params.c STANDARD_PARAM_DEFS, All 3 are
non-static and exported.
dynamic_debug.h:
Add DEFINE_DYNAMIC_DEBUG_CATEGORIES() described above, and a do-nothing stub.
Note that it also calls MODULE_PARM_DESC for the user, but expects the
user to catenate all the bit-descriptions together (as is done in
drm.debug), and in the following uses in amdgpu, i915.
This in the hope that someone can offer an auto-incrementing
label-generating macro, producing "\tbit-4 0x10\t" etc, and can show
how to apply it to __VA_ARGS__.
Also extern the struct kernel_param param_ops_dyndbg symbol, as is
done in moduleparams.h for all the STANDARD params.
USAGE NOTES:
Using dyndbg to query on "format ^$prefix" requires that the prefix be
present in the compiled-in format string; where run-time prefixing is
used, that format would be "%s...", which is not usefully selectable.
Adding structural query terms (func,file,lineno) could help (module is
already done), but DEFINE_DYNAMIC_DEBUG_CATEGORIES can't do that now,
adding it needs a better reason imo.
Dyndbg is completely agnostic wrt the categorization scheme used, to
play well with any prefix convention already in use. Ad-hoc
categories and sub-categories are implicitly allowed, author
discipline and review is expected.
Here are some examples:
"1","2","3" 2 doesn't imply 1.
otherwize, sorta like printk levels
"1:","2:","3:" are better, avoiding [1-9]\d+ ambiguity
"hi:","mid:","low:" are reasonable, and imply independence
"todo:","rfc:","fixme:" might be handy
"A:".."Z:" uhm, yeah
Hierarchical classes/categories are natural:
"drm::"is used in later commit
"drm:::" is a natural extension.
"drm:atomic:fail:" has been proposed, sounds directly useful
Some properties of a hierarchical category deserve explication:
Trailing spaces matter !
With 1..3-space ("drm: ", "drm:atomic: ", "drm:atomic:fail: "), the
":" doesn't terminate the search-space, the trailing space does. So a
"drm:" search spec will match all DRM categories & subcategories, and
will not be useful in an interface where all categories are already
controlled together. That said, "drm:atomic:" & "drm:atomic: " are
different, and both are useful in cases.
Ad-Hoc sub-categories:
These have a caveat wrt wrapper macros adding prefixes like
"drm:atomic: "; the trailing space in the prefix means that
drm_dbg_atomic("fail: ...") pastes as "drm:atomic: fail: ", which
obviously isn't ideal wrt clear and simple bitmaps.
A possible solution is to have a FOO_() version of every FOO() macro
which (anti-mnemonically) elides the trailing space, which is normally
inserted by a modified FOO(). Doing this would enforce a policy
decision that "debug categories will be space terminated", with an
pressure-relief valve.
Summarizing:
- "drm:kms: " & "drm:kms:" are different
- "drm:kms"also different - includes drm:kms2:
- "drm:kms:\t" also different
- "drm:kms:*" doesn't work, no wildcard on format atm.
Order matters in DEFINE_DYNAMIC_DEBUG_CATEGORIES(... @bit_descs)
@bit_descs (array) position determines the bit mapping to the prefix,
so to keep a stable map, new categories or 3rd level categories must
be added to the end.
Since bits are/will-stay applied 0-N, the later bits can countermand
the earlier ones, but its tricky - consider;
DD_CATs(... "drm:atomic:", "drm:atomic:fail:" ) // misleading
The 1st search-term is misleading, because it includes (modifies)
subcategories, but then 2nd overrides it. So don't do that.
For "drm:atomic:fail:" in particular, its best not to add it into an
existing bitmap, because the current setting would be lost at every
(unrelated) write, and a separate bitmap is much more stable.
There is still plenty of bikeshedding to do.
Signed-off-by: Jim Cromie
---
v5:
. rename to
[Intel-gfx] [PATCH v6 01/11] moduleparam: add data member to struct kernel_param
Add a const void* data member to the struct, to allow attaching
private data that will be used soon by a setter method (via kp->data)
to perform more elaborate actions.
To attach the data at compile time, add new macros:
module_param_cb_data() derives from module_param_cb(), adding data
param, and latter is redefined to use former.
It calls __module_param_call_with_data(), which accepts new data param
and inits .data with it. Re-define __module_param_call() to use it.
Use of this new data member will be rare, it might be worth redoing
this as a separate/sub-type to de-bloat the base case.
Signed-off-by: Jim Cromie
---
v6:
. const void* data -
. better macro names s/_cbd/_cb_data/, s/_wdata/_with_data/
. more const, no cast - Willy
---
include/linux/moduleparam.h | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/include/linux/moduleparam.h b/include/linux/moduleparam.h
index eed280fae433..b8871e514de5 100644
--- a/include/linux/moduleparam.h
+++ b/include/linux/moduleparam.h
@@ -78,6 +78,7 @@ struct kernel_param {
const struct kparam_string *str;
const struct kparam_array *arr;
};
+ const void *data;
};
extern const struct kernel_param __start___param[], __stop___param[];
@@ -175,6 +176,9 @@ struct kparam_array
#define module_param_cb(name, ops, arg, perm)\
__module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, -1, 0)
+#define module_param_cb_data(name, ops, arg, perm, data)
\
+ __module_param_call_with_data(MODULE_PARAM_PREFIX, name, ops, arg,
perm, -1, 0, data)
+
#define module_param_cb_unsafe(name, ops, arg, perm) \
__module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, -1,\
KERNEL_PARAM_FL_UNSAFE)
@@ -284,14 +288,17 @@ struct kparam_array
/* This is the fundamental function for registering boot/module
parameters. */
-#define __module_param_call(prefix, name, ops, arg, perm, level, flags)
\
+#define __module_param_call(prefix, name, ops, arg, perm, level, flags) \
+ __module_param_call_with_data(prefix, name, ops, arg, perm, level,
flags, NULL)
+
+#define __module_param_call_with_data(prefix, name, ops, arg, perm, level,
flags, data) \
/* Default value instead of permissions? */ \
static const char __param_str_##name[] = prefix #name; \
static struct kernel_param __moduleparam_const __param_##name \
__used __section("__param") \
__aligned(__alignof__(struct kernel_param)) \
= { __param_str_##name, THIS_MODULE, ops, \
- VERIFY_OCTAL_PERMISSIONS(perm), level, flags, { arg } }
+ VERIFY_OCTAL_PERMISSIONS(perm), level, flags, { arg }, data }
/* Obsolete - use module_param_cb() */
#define module_param_call(name, _set, _get, arg, perm) \
--
2.31.1
[Intel-gfx] [PATCH v6 00/11] use DYNAMIC_DEBUG to implement DRM.debug
This patchset does 3 main things. Adds DEFINE_DYNAMIC_DEBUG_CATEGORIES to define bitmap => category control of pr_debugs, and to create their sysfs entries. Uses it in amdgpu, i915 to control existing pr_debugs according to their ad-hoc categorizations. Plugs dyndbg into drm-debug framework, in a configurable manner. v6: cleans up per v5 feedback, and adds RFC stuff: - test_dynamic_debug.ko: uses tracer facility added in v5:8/9 - prototype print-once & rate-limiting Hopefully adding RFC stuff doesnt distract too much. Jim Cromie (11): moduleparam: add data member to struct kernel_param dyndbg: add DEFINE_DYNAMIC_DEBUG_CATEGORIES and callbacks i915/gvt: remove spaces in pr_debug "gvt: core:" etc prefixes i915/gvt: use DEFINE_DYNAMIC_DEBUG_CATEGORIES to create "gvt:core:" etc categories amdgpu: use DEFINE_DYNAMIC_DEBUG_CATEGORIES to control categorized pr_debugs drm_print: add choice to use dynamic debug in drm-debug drm_print: instrument drm_debug_enabled amdgpu_ucode: reduce number of pr_debug calls nouveau: fold multiple DRM_DEBUG_DRIVERs together dyndbg: RFC add debug-trace callback, selftest with it. RFC dyndbg: RFC add print-once and print-ratelimited features. RFC. drivers/gpu/drm/Kconfig | 13 + drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 293 --- .../gpu/drm/amd/display/dc/core/dc_debug.c| 44 ++- drivers/gpu/drm/drm_print.c | 49 ++- drivers/gpu/drm/i915/gvt/Makefile | 4 + drivers/gpu/drm/i915/gvt/debug.h | 18 +- drivers/gpu/drm/i915/i915_params.c| 35 ++ drivers/gpu/drm/nouveau/nouveau_drm.c | 36 +- include/drm/drm_print.h | 148 ++-- include/linux/dynamic_debug.h | 81 - include/linux/moduleparam.h | 11 +- lib/Kconfig.debug | 11 + lib/Makefile | 1 + lib/dynamic_debug.c | 336 -- lib/test_dynamic_debug.c | 279 +++ 15 files changed, 1117 insertions(+), 242 deletions(-) create mode 100644 lib/test_dynamic_debug.c -- 2.31.1
[Intel-gfx] [PATCH] drm/i915: switch from 'pci_' to 'dma_' API
The wrappers in include/linux/pci-dma-compat.h should go away.
The patch has been generated with the coccinelle script below.
It has been compile tested.
@@
@@
-PCI_DMA_BIDIRECTIONAL
+DMA_BIDIRECTIONAL
@@
@@
-PCI_DMA_TODEVICE
+DMA_TO_DEVICE
@@
@@
-PCI_DMA_FROMDEVICE
+DMA_FROM_DEVICE
@@
@@
-PCI_DMA_NONE
+DMA_NONE
@@
expression e1, e2, e3;
@@
-pci_alloc_consistent(e1, e2, e3)
+dma_alloc_coherent(>dev, e2, e3, GFP_)
@@
expression e1, e2, e3;
@@
-pci_zalloc_consistent(e1, e2, e3)
+dma_alloc_coherent(>dev, e2, e3, GFP_)
@@
expression e1, e2, e3, e4;
@@
-pci_free_consistent(e1, e2, e3, e4)
+dma_free_coherent(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_map_single(e1, e2, e3, e4)
+dma_map_single(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_unmap_single(e1, e2, e3, e4)
+dma_unmap_single(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4, e5;
@@
-pci_map_page(e1, e2, e3, e4, e5)
+dma_map_page(>dev, e2, e3, e4, e5)
@@
expression e1, e2, e3, e4;
@@
-pci_unmap_page(e1, e2, e3, e4)
+dma_unmap_page(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_map_sg(e1, e2, e3, e4)
+dma_map_sg(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_unmap_sg(e1, e2, e3, e4)
+dma_unmap_sg(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_dma_sync_single_for_cpu(e1, e2, e3, e4)
+dma_sync_single_for_cpu(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_dma_sync_single_for_device(e1, e2, e3, e4)
+dma_sync_single_for_device(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_dma_sync_sg_for_cpu(e1, e2, e3, e4)
+dma_sync_sg_for_cpu(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_dma_sync_sg_for_device(e1, e2, e3, e4)
+dma_sync_sg_for_device(>dev, e2, e3, e4)
@@
expression e1, e2;
@@
-pci_dma_mapping_error(e1, e2)
+dma_mapping_error(>dev, e2)
@@
expression e1, e2;
@@
-pci_set_dma_mask(e1, e2)
+dma_set_mask(>dev, e2)
@@
expression e1, e2;
@@
-pci_set_consistent_dma_mask(e1, e2)
+dma_set_coherent_mask(>dev, e2)
Signed-off-by: Christophe JAILLET
---
If needed, see post from Christoph Hellwig on the kernel-janitors ML:
https://marc.info/?l=kernel-janitors=158745678307186=4
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 ++--
drivers/gpu/drm/i915/gvt/gtt.c | 16
drivers/gpu/drm/i915/gvt/kvmgt.c| 4 ++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
4 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index a74b72f50cc9..afb35d2e5c73 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -32,7 +32,7 @@ static int init_fake_lmem_bar(struct intel_memory_region *mem)
mem->remap_addr = dma_map_resource(i915->drm.dev,
mem->region.start,
mem->fake_mappable.size,
- PCI_DMA_BIDIRECTIONAL,
+ DMA_BIDIRECTIONAL,
DMA_ATTR_FORCE_CONTIGUOUS);
if (dma_mapping_error(i915->drm.dev, mem->remap_addr)) {
drm_mm_remove_node(>fake_mappable);
@@ -62,7 +62,7 @@ static void release_fake_lmem_bar(struct intel_memory_region
*mem)
dma_unmap_resource(mem->i915->drm.dev,
mem->remap_addr,
mem->fake_mappable.size,
- PCI_DMA_BIDIRECTIONAL,
+ DMA_BIDIRECTIONAL,
DMA_ATTR_FORCE_CONTIGUOUS);
}
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index e5c2fdfc20e3..fb4e96a3e79e 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -745,7 +745,7 @@ static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt)
trace_spt_free(spt->vgpu->id, spt, spt->guest_page.type);
dma_unmap_page(kdev, spt->shadow_page.mfn << I915_GTT_PAGE_SHIFT, 4096,
- PCI_DMA_BIDIRECTIONAL);
+ DMA_BIDIRECTIONAL);
radix_tree_delete(>vgpu->gtt.spt_tree, spt->shadow_page.mfn);
@@ -849,7 +849,7 @@ static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
*/
spt->shadow_page.type = type;
daddr = dma_map_page(kdev, spt->shadow_page.page,
-0, 4096, PCI_DMA_BIDIRECTIONAL);
+0, 4096, DMA_BIDIRECTIONAL);
if (dma_mapping_error(kdev, daddr)) {
gvt_vgpu_err("fail to map dma addr\n");
ret = -EINVAL;
@@ -865,7 +865,7 @@ static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
return spt;
err_unmap_dma:
- dma_unmap_page(kdev, daddr, PAGE_SIZE,
[Intel-gfx] [PATCH] drm/amdgpu: switch from 'pci_' to 'dma_' API
The wrappers in include/linux/pci-dma-compat.h should go away.
The patch has been generated with the coccinelle script below.
It has been compile tested.
@@
@@
-PCI_DMA_BIDIRECTIONAL
+DMA_BIDIRECTIONAL
@@
@@
-PCI_DMA_TODEVICE
+DMA_TO_DEVICE
@@
@@
-PCI_DMA_FROMDEVICE
+DMA_FROM_DEVICE
@@
@@
-PCI_DMA_NONE
+DMA_NONE
@@
expression e1, e2, e3;
@@
-pci_alloc_consistent(e1, e2, e3)
+dma_alloc_coherent(>dev, e2, e3, GFP_)
@@
expression e1, e2, e3;
@@
-pci_zalloc_consistent(e1, e2, e3)
+dma_alloc_coherent(>dev, e2, e3, GFP_)
@@
expression e1, e2, e3, e4;
@@
-pci_free_consistent(e1, e2, e3, e4)
+dma_free_coherent(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_map_single(e1, e2, e3, e4)
+dma_map_single(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_unmap_single(e1, e2, e3, e4)
+dma_unmap_single(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4, e5;
@@
-pci_map_page(e1, e2, e3, e4, e5)
+dma_map_page(>dev, e2, e3, e4, e5)
@@
expression e1, e2, e3, e4;
@@
-pci_unmap_page(e1, e2, e3, e4)
+dma_unmap_page(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_map_sg(e1, e2, e3, e4)
+dma_map_sg(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_unmap_sg(e1, e2, e3, e4)
+dma_unmap_sg(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_dma_sync_single_for_cpu(e1, e2, e3, e4)
+dma_sync_single_for_cpu(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_dma_sync_single_for_device(e1, e2, e3, e4)
+dma_sync_single_for_device(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_dma_sync_sg_for_cpu(e1, e2, e3, e4)
+dma_sync_sg_for_cpu(>dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
-pci_dma_sync_sg_for_device(e1, e2, e3, e4)
+dma_sync_sg_for_device(>dev, e2, e3, e4)
@@
expression e1, e2;
@@
-pci_dma_mapping_error(e1, e2)
+dma_mapping_error(>dev, e2)
@@
expression e1, e2;
@@
-pci_set_dma_mask(e1, e2)
+dma_set_mask(>dev, e2)
@@
expression e1, e2;
@@
-pci_set_consistent_dma_mask(e1, e2)
+dma_set_coherent_mask(>dev, e2)
Signed-off-by: Christophe JAILLET
---
If needed, see post from Christoph Hellwig on the kernel-janitors ML:
https://marc.info/?l=kernel-janitors=158745678307186=4
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index b36405170ff3..76efd5f8950f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -76,7 +76,7 @@ static int amdgpu_gart_dummy_page_init(struct amdgpu_device
*adev)
if (adev->dummy_page_addr)
return 0;
adev->dummy_page_addr = dma_map_page(>pdev->dev, dummy_page, 0,
-PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+PAGE_SIZE, DMA_BIDIRECTIONAL);
if (dma_mapping_error(>pdev->dev, adev->dummy_page_addr)) {
dev_err(>pdev->dev, "Failed to DMA MAP the dummy page\n");
adev->dummy_page_addr = 0;
@@ -96,8 +96,8 @@ void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
{
if (!adev->dummy_page_addr)
return;
- pci_unmap_page(adev->pdev, adev->dummy_page_addr,
- PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+ dma_unmap_page(>pdev->dev, adev->dummy_page_addr, PAGE_SIZE,
+ DMA_BIDIRECTIONAL);
adev->dummy_page_addr = 0;
}
--
2.30.2
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/lmem: Enable device memory support for DG2
== Series Details == Series: drm/i915/lmem: Enable device memory support for DG2 URL : https://patchwork.freedesktop.org/series/93904/ State : success == Summary == CI Bug Log - changes from CI_DRM_10505_full -> Patchwork_20864_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20864_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-kbl1/igt@gem_ctx_isolation@preservation...@vecs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/shard-kbl4/igt@gem_ctx_isolation@preservation...@vecs0.html * igt@gem_ctx_persistence@process: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/shard-snb6/igt@gem_ctx_persiste...@process.html * igt@gem_eio@in-flight-1us: - shard-skl: [PASS][4] -> [TIMEOUT][5] ([i915#3063]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-skl4/igt@gem_...@in-flight-1us.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/shard-skl5/igt@gem_...@in-flight-1us.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: NOTRUN -> [FAIL][6] ([i915#2846]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/shard-kbl1/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/shard-tglb2/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][9] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/shard-kbl4/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-tglb: NOTRUN -> [FAIL][10] ([i915#2842]) +4 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/shard-tglb5/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-kbl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/shard-kbl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2849]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_suspend@basic-s3: - shard-apl: [PASS][18] -> [DMESG-WARN][19] ([i915#180]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-apl7/igt@gem_exec_susp...@basic-s3.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/shard-apl3/igt@gem_exec_susp...@basic-s3.html * igt@gem_mmap_gtt@cpuset-medium-copy-xy: - shard-iclb: [PASS][20] -> [FAIL][21] ([i915#307]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/shard-iclb3/igt@gem_mmap_...@cpuset-medium-copy-xy.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/shard-iclb8/igt@gem_mmap_...@cpuset-medium-copy-xy.html * igt@gem_pwrite@basic-exhaustion: - shard-kbl: NOTRUN -> [WARN][22] ([i915#2658]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/shard-kbl2/igt@gem_pwr...@basic-exhaustion.html * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs: - shard-glk: NOTRUN -> [SKIP][23] ([fdo#109271]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/shard-glk7/igt@gem_render_c...@y-tiled-ccs-to-y-tiled-mc-ccs.html * igt@gem_userptr_blits@vma-merge: -
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/lmem: Enable device memory support for DG2
== Series Details == Series: drm/i915/lmem: Enable device memory support for DG2 URL : https://patchwork.freedesktop.org/series/93904/ State : success == Summary == CI Bug Log - changes from CI_DRM_10505 -> Patchwork_20864 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/index.html Known issues Here are the changes found in Patchwork_20864 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_prime@i915-to-amd: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-kbl-soraka/igt@amdgpu/amd_pr...@i915-to-amd.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html - fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([i915#1155]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rpm@module-reload: - fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][5] ([i915#4006]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-tgl-1115g4/igt@i915_pm_...@module-reload.html * igt@kms_addfb_basic@too-wide: - fi-tgl-1115g4: NOTRUN -> [DMESG-WARN][6] ([i915#4002]) +91 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-tgl-1115g4/igt@kms_addfb_ba...@too-wide.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([fdo#111827]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-edid-read: - fi-kbl-8809g: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-rkl-11600: [PASS][9] -> [SKIP][10] ([fdo#111825]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/fi-rkl-11600/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-rkl-11600/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([fdo#109285]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-8809g: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@cursor_plane_move: - fi-kbl-8809g: NOTRUN -> [SKIP][13] ([fdo#109271]) +35 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#1072]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html * igt@prime_vgem@basic-userptr: - fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([i915#3301]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html * igt@runner@aborted: - fi-tgl-1115g4: NOTRUN -> [FAIL][16] ([i915#2722] / [i915#3834]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-tgl-1115g4/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-kbl-8809g: [DMESG-WARN][17] ([i915#3848]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10505/fi-kbl-8809g/igt@gem_exec_susp...@basic-s3.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20864/fi-kbl-8809g/igt@gem_exec_susp...@basic-s3.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#2190]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/lmem: Enable device memory support for DG2
== Series Details == Series: drm/i915/lmem: Enable device memory support for DG2 URL : https://patchwork.freedesktop.org/series/93904/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/display/intel_display.c:1902:21:expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1902:21:got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1902:21: warning: incorrect type in assignment (different address spaces) +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/lmem: Enable device memory support for DG2
== Series Details == Series: drm/i915/lmem: Enable device memory support for DG2 URL : https://patchwork.freedesktop.org/series/93904/ State : warning == Summary == $ dim checkpatch origin/drm-tip d96ba2006a6a drm/i915: Add has_64k_pages flag 6ba41b6b2c87 drm/i915/xehpsdv: set min page-size to 64K 00fb079092d9 drm/i915/xehpsdv: enforce min GTT alignment 1e386ec5b392 drm/i915/gem: Remove unused i915_gem_lmem_obj_ops e14c5791cf60 drm/i915: enforce min page size for scratch bb305eaba00b drm/i915/gtt/xehpsdv: move scratch page to system memory ef698973c78e drm/i915/xehpsdv: support 64K GTT pages 2593fa6f3554 drm/i915: Add vm min alignment support 75128fae26bb drm/i915/selftests: account for min_alignment in GTT selftests -:108: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #108: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:456: + if (offset < hole_start + aligned_size) -:120: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #120: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:480: + if (offset + aligned_size > hole_end) -:138: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #138: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:496: + if (offset < hole_start + aligned_size) -:150: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #150: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:519: + if (offset + aligned_size > hole_end) -:168: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #168: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:535: + if (offset < hole_start + aligned_size) -:180: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #180: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:559: + if (offset + aligned_size > hole_end) -:198: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #198: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:575: + if (offset < hole_start + aligned_size) -:210: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #210: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:598: + if (offset + aligned_size > hole_end) total: 0 errors, 8 warnings, 0 checks, 297 lines checked ad751b4ca2fb drm/i915/xehpsdv: implement memory coloring ef7a6211c866 drm/i915/xehpsdv: Add has_flat_ccs to device info ea82c71e78be drm/i915/lmem: Enable lmem for platforms with Flat CCS -:70: CHECK:LINE_SPACING: Please don't use multiple blank lines #70: FILE: drivers/gpu/drm/i915/gt/intel_region_lmem.c:205: + total: 0 errors, 0 warnings, 1 checks, 70 lines checked 136640c27dc2 drm/i915/gt: Clear compress metadata for Gen12.5 >= platforms
[Intel-gfx] [RFC 10/13] drm/i915/xehpsdv: implement memory coloring
From: Matthew Auld
The basic idea is that each 2M block(page-table) has a color, depending
on if the page-table is occupied by LMEM objects(64K) or SMEM
objects(4K), where our goal is to prevent mixing 64K and 4K GTT pages in
the page-table, which is not supported by the HW.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 16 ++
drivers/gpu/drm/i915/gt/intel_gtt.h | 6
drivers/gpu/drm/i915/i915_gem_evict.c | 17 ++
drivers/gpu/drm/i915/i915_vma.c | 46 +++
4 files changed, 71 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 8bf7c81064e1..67ac85e6a0b3 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -464,6 +464,19 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
return idx;
}
+static void xehpsdv_ppgtt_color_adjust(const struct drm_mm_node *node,
+ unsigned long color,
+ u64 *start,
+ u64 *end)
+{
+ if (i915_node_color_differs(node, color))
+ *start = round_up(*start, SZ_2M);
+
+ node = list_next_entry(node, node_list);
+ if (i915_node_color_differs(node, color))
+ *end = round_down(*end, SZ_2M);
+}
+
static void
xehpsdv_ppgtt_insert_huge(struct i915_vma *vma,
struct sgt_dma *iter,
@@ -898,6 +911,9 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
}
+ if (HAS_64K_PAGES(gt->i915))
+ ppgtt->vm.mm.color_adjust = xehpsdv_ppgtt_color_adjust;
+
err = gen8_init_scratch(>vm);
if (err)
goto err_free;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index a4388dd06177..2dc79fade83b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -394,6 +394,12 @@ i915_vm_has_cache_coloring(struct i915_address_space *vm)
return i915_is_ggtt(vm) && vm->mm.color_adjust;
}
+static inline bool
+i915_vm_has_memory_coloring(struct i915_address_space *vm)
+{
+ return !i915_is_ggtt(vm) && vm->mm.color_adjust;
+}
+
static inline struct i915_ggtt *
i915_vm_to_ggtt(struct i915_address_space *vm)
{
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index 2b73ddb11c66..006bf4924c24 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -292,6 +292,13 @@ int i915_gem_evict_for_node(struct i915_address_space *vm,
/* Always look at the page afterwards to avoid the end-of-GTT */
end += I915_GTT_PAGE_SIZE;
+ } else if (i915_vm_has_memory_coloring(vm)) {
+ /*
+* Expand the search the cover the page-table boundries, in
+* case we need to flip the color of the page-table(s).
+*/
+ start = round_down(start, SZ_2M);
+ end = round_up(end, SZ_2M);
}
GEM_BUG_ON(start >= end);
@@ -321,6 +328,16 @@ int i915_gem_evict_for_node(struct i915_address_space *vm,
if (node->color == target->color)
continue;
}
+ } else if (i915_vm_has_memory_coloring(vm)) {
+ if (node->start + node->size <= target->start) {
+ if (node->color == target->color)
+ continue;
+ }
+
+ if (node->start >= target->start + target->size) {
+ if (node->color == target->color)
+ continue;
+ }
}
if (i915_vma_is_pinned(vma)) {
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 1ea1fa08efdf..2664d3ab49b9 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -585,6 +585,10 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma,
unsigned long color)
struct drm_mm_node *node = >node;
struct drm_mm_node *other;
+ /* Only valid to be called on an already inserted vma */
+ GEM_BUG_ON(!drm_mm_node_allocated(node));
+ GEM_BUG_ON(list_empty(>node_list));
+
/*
* On some machines we have to be careful when putting differing types
* of snoopable memory together to avoid the prefetcher crossing memory
@@ -592,22 +596,34 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma,
unsigned long color)
* these constraints apply and set the drm_mm.color_adjust
* appropriately.
*/
-
[Intel-gfx] [RFC 13/13] drm/i915/gt: Clear compress metadata for Gen12.5 >= platforms
Gen12.5 >= devices support Flat CCS which reserved a portion of the device
memory to store compression metadata, during the clearing of device memory
buffer object we also need to clear the associated CCS buffer.
Flat CCS memory can not be directly accessed by S/W.
Address of CCS buffer associated main BO is automatically calculated
by device itself. KMD/UMD can only access this buffer indirectly using
XY_CTRL_SURF_COPY_BLT cmd via the address of device memory buffer.
Cc: CQ Tang
Signed-off-by: Ayaz A Siddiqui
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 14 +++
drivers/gpu/drm/i915/gt/intel_migrate.c | 121 ++-
drivers/gpu/drm/i915/gt/intel_migrate.h | 1 -
3 files changed, 132 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 1c3af0fc0456..62cc750d9990 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -198,6 +198,20 @@
#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
+#define XY_CTRL_SURF_INSTR_SIZE5
+#define MI_FLUSH_DW_SIZE 3
+#define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
+#define SRC_ACCESS_TYPE_SHIFT21
+#define DST_ACCESS_TYPE_SHIFT20
+#define CCS_SIZE_SHIFT 8
+#define XY_CTRL_SURF_MOCS_SHIFT 25
+#define NUM_CCS_BYTES_PER_BLOCK 256
+#define NUM_CCS_BLKS_PER_XFER1024
+#define INDIRECT_ACCESS 0
+#define DIRECT_ACCESS1
+#define MI_FLUSH_LLC BIT(9)
+#define MI_FLUSH_CCS BIT(16)
+
#define COLOR_BLT_CMD (2 << 29 | 0x40 << 22 | (5 - 2))
#define XY_COLOR_BLT_CMD (2 << 29 | 0x50 << 22)
#define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index d0a7c934fd3b..5d471655fe10 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -17,6 +17,8 @@ struct insert_pte_data {
};
#define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
+#define GET_CCS_SIZE(i915, size) (HAS_FLAT_CCS(i915) ? \
+(size) >> 8 : 0)
static bool engine_supports_migration(struct intel_engine_cs *engine)
{
@@ -490,15 +492,104 @@ intel_context_migrate_copy(struct intel_context *ce,
return err;
}
-static int emit_clear(struct i915_request *rq, int size, u32 value)
+static inline u32 *i915_flush_dw(u32 *cmd, u64 dst, u32 flags)
+{
+ /* Mask the 3 LSB to use the PPGTT address space */
+ *cmd++ = MI_FLUSH_DW | flags;
+ *cmd++ = lower_32_bits(dst);
+ *cmd++ = upper_32_bits(dst);
+
+ return cmd;
+}
+
+static u32 calc_ctrl_surf_instr_size(struct drm_i915_private *i915, int size)
+{
+ u32 num_cmds, num_blks, total_size;
+
+ if (!GET_CCS_SIZE(i915, size))
+ return 0;
+
+ /*
+* XY_CTRL_SURF_COPY_BLT transfers CCS in 256 byte
+* blocks. one XY_CTRL_SURF_COPY_BLT command can
+* trnasfer upto 1024 blocks.
+*/
+ num_blks = (GET_CCS_SIZE(i915, size) +
+ (NUM_CCS_BYTES_PER_BLOCK - 1)) >> 8;
+ num_cmds = (num_blks + (NUM_CCS_BLKS_PER_XFER - 1)) >> 10;
+ total_size = (XY_CTRL_SURF_INSTR_SIZE) * num_cmds;
+
+ /*
+* We need to add a flush before and after
+* XY_CTRL_SURF_COPY_BLT
+*/
+ total_size += 2 * MI_FLUSH_DW_SIZE;
+ return total_size;
+}
+
+static u32 *_i915_ctrl_surf_copy_blt(u32 *cmd, u64 src_addr, u64 dst_addr,
+u8 src_mem_access, u8 dst_mem_access,
+int src_mocs, int dst_mocs,
+u16 num_ccs_blocks)
+{
+ int i = num_ccs_blocks;
+
+ /*
+* The XY_CTRL_SURF_COPY_BLT instruction is used to copy the CCS
+* data in and out of the CCS region.
+*
+* We can copy at most 1024 blocks of 256 bytes using one
+* XY_CTRL_SURF_COPY_BLT instruction.
+*
+* In case we need to copy more than 1024 blocks, we need to add
+* another instruction to the same batch buffer.
+*
+* 1024 blocks of 256 bytes of CCS represent a total 256KB of CCS.
+*
+* 256 KB of CCS represents 256 * 256 KB = 64 MB of LMEM.
+*/
+ do {
+ /*
+* We use logical AND with 1023 since the size field
+* takes values which is in the range of 0 - 1023
+*/
+ *cmd++ = ((XY_CTRL_SURF_COPY_BLT) |
+ (src_mem_access << SRC_ACCESS_TYPE_SHIFT) |
+ (dst_mem_access << DST_ACCESS_TYPE_SHIFT) |
+
[Intel-gfx] [RFC 12/13] drm/i915/lmem: Enable lmem for platforms with Flat CCS
A portion of device memory is reserved for Flat CCS so usable
device memory will be reduced by size of Flat CCS. Size of
Flat CCS is specified in “XEHPSDV_FLAT_CCS_BASE_ADDR”.
So to get effective device memory we need to subtract
total device memory by Flat CCS memory size.
Cc: Matthew Auld
Signed-off-by: Ayaz A Siddiqui
---
drivers/gpu/drm/i915/gt/intel_gt.c | 19 +
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 23 +++--
drivers/gpu/drm/i915/i915_reg.h | 3 +++
4 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 62d40c986642..817107d42a44 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -888,6 +888,25 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt,
i915_reg_t reg)
return intel_uncore_read_fw(gt->uncore, reg);
}
+u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg)
+{
+ int type;
+ u8 sliceid, subsliceid;
+
+ for (type = 0; type < NUM_STEERING_TYPES; type++) {
+ if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
+ intel_gt_get_valid_steering(gt, type, ,
+ );
+ return intel_uncore_read_with_mcr_steering(gt->uncore,
+ reg,
+ sliceid,
+ subsliceid);
+ }
+ }
+
+ return intel_uncore_read(gt->uncore, reg);
+}
+
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 74e771871a9b..24b78398a587 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -84,6 +84,7 @@ static inline bool intel_gt_needs_read_steering(struct
intel_gt *gt,
}
u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);
+u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p);
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 4ea0ad9435df..876ee8cb21fc 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -202,8 +202,27 @@ static struct intel_memory_region *setup_lmem(struct
intel_gt *gt)
if (!IS_DGFX(i915))
return ERR_PTR(-ENODEV);
- /* Stolen starts from GSMBASE on DG1 */
- lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE);
+
+ if (HAS_FLAT_CCS(i915)) {
+ u64 tile_stolen, flat_ccs_base_addr_reg, flat_ccs_base;
+
+ lmem_size = pci_resource_len(pdev, 2);
+ flat_ccs_base_addr_reg = intel_gt_read_register(gt,
XEHPSDV_FLAT_CCS_BASE_ADDR);
+ flat_ccs_base = (flat_ccs_base_addr_reg >>
XEHPSDV_CCS_BASE_SHIFT) * SZ_64K;
+ tile_stolen = lmem_size - flat_ccs_base;
+
+ /* If the FLAT_CCS_BASE_ADDR register is not populated, flag an
error */
+ if (tile_stolen == lmem_size)
+ DRM_ERROR("CCS_BASE_ADDR register did not have expected
value\n");
+
+ lmem_size -= tile_stolen;
+ } else {
+ /* Stolen starts from GSMBASE without CCS */
+ lmem_size = intel_uncore_read64(>uncore, GEN12_GSMBASE);
+ if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2)))
+ return ERR_PTR(-ENODEV);
+ }
+
io_start = pci_resource_start(pdev, 2);
if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2)))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 167eaa87501b..4d310d31e9dd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12355,6 +12355,9 @@ enum skl_power_gate {
#define GEN12_GSMBASE _MMIO(0x108100)
#define GEN12_DSMBASE _MMIO(0x1080C0)
+#define XEHPSDV_FLAT_CCS_BASE_ADDR _MMIO(0x4910)
+#define XEHPSDV_CCS_BASE_SHIFT 8
+
/* gamt regs */
#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for
LRA1/2 */
--
2.26.2
[Intel-gfx] [RFC 11/13] drm/i915/xehpsdv: Add has_flat_ccs to device info
From: CQ Tang
Gen12>= devices support 3D surface (buffer) compression and various
compression formats. This is accomplished by an additional compression
control state (CCS) stored for each surface.
Gen 12 devices(TGL family and DG1) stores compression states in a separate
region of memory. It is managed by user-space and has an associated set of
user-space managed page tables used by hardware for address translation.
In Gen12.5 devices(XEHPSDV, DG2, etc), there is a new feature introduced
“Flat CCS”. It replaced AUX page tables with a flat indexed region of
device memory for storing compression states.
Cc: Joonas Lahtinen
Cc: Matthew Auld
Signed-off-by: CQ Tang
Signed-off-by: Ayaz A Siddiqui
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ac050e4599de..e07f4d8426f1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1700,6 +1700,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
+#define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs)
+
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
#define HAS_POOLED_EU(dev_priv)(INTEL_INFO(dev_priv)->has_pooled_eu)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 7b8bba60b899..72ca087974c3 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -990,6 +990,7 @@ static const struct intel_device_info adl_p_info = {
XE_HP_PAGE_SIZES, \
.dma_mask_size = 46, \
.has_64bit_reloc = 1, \
+ .has_flat_ccs = 1, \
.has_global_mocs = 1, \
.has_gt_uc = 1, \
.has_llc = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index bbeec52ea6dc..93bb0e65cea9 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -126,6 +126,7 @@ enum intel_ppgtt_type {
func(has_64k_pages); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
+ func(has_flat_ccs); \
func(has_global_mocs); \
func(has_gt_uc); \
func(has_l3_dpf); \
--
2.26.2
[Intel-gfx] [RFC 09/13] drm/i915/selftests: account for min_alignment in GTT selftests
From: Matthew Auld
We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.
Signed-off-by: Matthew Auld
Signed-off-by: Ayaz A Siddiqui
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 96 ---
1 file changed, 63 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index f843a5040706..bd0cd501e411 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -237,6 +237,8 @@ static int lowlevel_hole(struct i915_address_space *vm,
u64 hole_start, u64 hole_end,
unsigned long end_time)
{
+ const unsigned int min_alignment =
+ i915_vm_min_alignment(vm, INTEL_MEMORY_SYSTEM);
I915_RND_STATE(seed_prng);
struct i915_vma *mock_vma;
unsigned int size;
@@ -250,9 +252,10 @@ static int lowlevel_hole(struct i915_address_space *vm,
I915_RND_SUBSTATE(prng, seed_prng);
struct drm_i915_gem_object *obj;
unsigned int *order, count, n;
- u64 hole_size;
+ u64 hole_size, aligned_size;
- hole_size = (hole_end - hole_start) >> size;
+ aligned_size = max_t(u32, ilog2(min_alignment), size);
+ hole_size = (hole_end - hole_start) >> aligned_size;
if (hole_size > KMALLOC_MAX_SIZE / sizeof(u32))
hole_size = KMALLOC_MAX_SIZE / sizeof(u32);
count = hole_size >> 1;
@@ -273,8 +276,8 @@ static int lowlevel_hole(struct i915_address_space *vm,
}
GEM_BUG_ON(!order);
- GEM_BUG_ON(count * BIT_ULL(size) > vm->total);
- GEM_BUG_ON(hole_start + count * BIT_ULL(size) > hole_end);
+ GEM_BUG_ON(count * BIT_ULL(aligned_size) > vm->total);
+ GEM_BUG_ON(hole_start + count * BIT_ULL(aligned_size) >
hole_end);
/* Ignore allocation failures (i.e. don't report them as
* a test failure) as we are purposefully allocating very
@@ -297,10 +300,10 @@ static int lowlevel_hole(struct i915_address_space *vm,
}
for (n = 0; n < count; n++) {
- u64 addr = hole_start + order[n] * BIT_ULL(size);
+ u64 addr = hole_start + order[n] *
BIT_ULL(aligned_size);
intel_wakeref_t wakeref;
- GEM_BUG_ON(addr + BIT_ULL(size) > vm->total);
+ GEM_BUG_ON(addr + BIT_ULL(aligned_size) > vm->total);
if (igt_timeout(end_time,
"%s timed out before %d/%d\n",
@@ -343,7 +346,7 @@ static int lowlevel_hole(struct i915_address_space *vm,
}
mock_vma->pages = obj->mm.pages;
- mock_vma->node.size = BIT_ULL(size);
+ mock_vma->node.size = BIT_ULL(aligned_size);
mock_vma->node.start = addr;
with_intel_runtime_pm(vm->gt->uncore->rpm, wakeref)
@@ -354,7 +357,7 @@ static int lowlevel_hole(struct i915_address_space *vm,
i915_random_reorder(order, count, );
for (n = 0; n < count; n++) {
- u64 addr = hole_start + order[n] * BIT_ULL(size);
+ u64 addr = hole_start + order[n] *
BIT_ULL(aligned_size);
intel_wakeref_t wakeref;
GEM_BUG_ON(addr + BIT_ULL(size) > vm->total);
@@ -398,8 +401,10 @@ static int fill_hole(struct i915_address_space *vm,
{
const u64 hole_size = hole_end - hole_start;
struct drm_i915_gem_object *obj;
+ const unsigned int min_alignment =
+ i915_vm_min_alignment(vm, INTEL_MEMORY_SYSTEM);
const unsigned long max_pages =
- min_t(u64, ULONG_MAX - 1, hole_size/2 >> PAGE_SHIFT);
+ min_t(u64, ULONG_MAX - 1, (hole_size / 2) >>
ilog2(min_alignment));
const unsigned long max_step = max(int_sqrt(max_pages), 2UL);
unsigned long npages, prime, flags;
struct i915_vma *vma;
@@ -440,14 +445,17 @@ static int fill_hole(struct i915_address_space *vm,
offset = p->offset;
list_for_each_entry(obj, , st_link) {
+ u64 aligned_size =
round_up(obj->base.size,
+
min_alignment);
+
vma = i915_vma_instance(obj, vm, NULL);
if (IS_ERR(vma))
continue;
[Intel-gfx] [RFC 08/13] drm/i915: Add vm min alignment support
From: Bommu Krishnaiah
Replace the hard coded 4K alignment value with vm->min_alignment.
Cc: Wilson Chris P
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Ayaz A Siddiqui
---
.../i915/gem/selftests/i915_gem_client_blt.c | 23 ---
drivers/gpu/drm/i915/gt/intel_gtt.c | 9
drivers/gpu/drm/i915/gt/intel_gtt.h | 9
3 files changed, 33 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index ecbcbb86ae1e..30c8d64df3b8 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -32,6 +32,7 @@ struct tiled_blits {
struct blit_buffer scratch;
struct i915_vma *batch;
u64 hole;
+ u64 align;
u32 width;
u32 height;
};
@@ -403,14 +404,21 @@ tiled_blits_create(struct intel_engine_cs *engine, struct
rnd_state *prng)
goto err_free;
}
- hole_size = 2 * PAGE_ALIGN(WIDTH * HEIGHT * 4);
+ t->align = I915_GTT_PAGE_SIZE_2M; /* XXX worst case, derive from vm! */
+ t->align = max(t->align,
+ i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_LOCAL));
+ t->align = max(t->align,
+ i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_SYSTEM));
+
+ hole_size = 2 * round_up(WIDTH * HEIGHT * 4, t->align);
hole_size *= 2; /* room to maneuver */
- hole_size += 2 * I915_GTT_MIN_ALIGNMENT;
+ hole_size += 2 * t->align; /* padding on either side */
mutex_lock(>ce->vm->mutex);
memset(, 0, sizeof(hole));
err = drm_mm_insert_node_in_range(>ce->vm->mm, ,
- hole_size, 0, I915_COLOR_UNEVICTABLE,
+ hole_size, t->align,
+ I915_COLOR_UNEVICTABLE,
0, U64_MAX,
DRM_MM_INSERT_BEST);
if (!err)
@@ -421,7 +429,7 @@ tiled_blits_create(struct intel_engine_cs *engine, struct
rnd_state *prng)
goto err_put;
}
- t->hole = hole.start + I915_GTT_MIN_ALIGNMENT;
+ t->hole = hole.start + t->align;
pr_info("Using hole at %llx\n", t->hole);
err = tiled_blits_create_buffers(t, WIDTH, HEIGHT, prng);
@@ -448,7 +456,7 @@ static void tiled_blits_destroy(struct tiled_blits *t)
static int tiled_blits_prepare(struct tiled_blits *t,
struct rnd_state *prng)
{
- u64 offset = PAGE_ALIGN(t->width * t->height * 4);
+ u64 offset = round_up(t->width * t->height * 4, t->align);
u32 *map;
int err;
int i;
@@ -479,8 +487,7 @@ static int tiled_blits_prepare(struct tiled_blits *t,
static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng)
{
- u64 offset =
- round_up(t->width * t->height * 4, 2 * I915_GTT_MIN_ALIGNMENT);
+ u64 offset = round_up(t->width * t->height * 4, 2 * t->align);
int err;
/* We want to check position invariant tiling across GTT eviction */
@@ -493,7 +500,7 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct
rnd_state *prng)
/* Reposition so that we overlap the old addresses, and slightly off */
err = tiled_blit(t,
->buffers[2], t->hole + I915_GTT_MIN_ALIGNMENT,
+>buffers[2], t->hole + t->align,
>buffers[1], t->hole + 3 * offset / 2);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 71b25cd67c9f..1c64cebd446d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -215,6 +215,15 @@ void i915_address_space_init(struct i915_address_space
*vm, int subclass)
GEM_BUG_ON(!vm->total);
drm_mm_init(>mm, 0, vm->total);
+
+ memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,
+ARRAY_SIZE(vm->min_alignment));
+
+ if (HAS_64K_PAGES(vm->i915)) {
+ vm->min_alignment[INTEL_MEMORY_LOCAL] = I915_GTT_PAGE_SIZE_64K;
+ vm->min_alignment[INTEL_MEMORY_STOLEN_LOCAL] =
I915_GTT_PAGE_SIZE_64K;
+ }
+
vm->mm.head_node.color = I915_COLOR_UNEVICTABLE;
INIT_LIST_HEAD(>bound_list);
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 8348c360dc81..a4388dd06177 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -28,6 +28,8 @@
#include "gt/intel_reset.h"
#include "i915_selftest.h"
#include "i915_vma_types.h"
+#include "i915_params.h"
+#include "intel_memory_region.h"
#define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
@@ -224,6 +226,7 @@ struct
[Intel-gfx] [RFC 07/13] drm/i915/xehpsdv: support 64K GTT pages
From: Matthew Auld
XEHPSDV optimises 64K GTT pages for local-memory, since everything
should be allocated at 64K granularity. We say goodbye to sparse
entries, and instead get a compact 256B page-table for 64K pages,
which should be more cache friendly. 4K pages for local-memory
are no longer supported by the HW.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ayaz A Siddiqui
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 61 ++
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 106 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 1 +
4 files changed, 168 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index a094f3ce1a90..6f1319d266d5 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1451,6 +1451,66 @@ static int igt_ppgtt_sanity_check(void *arg)
return err;
}
+static int igt_ppgtt_compact(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ struct drm_i915_gem_object *obj;
+ int err;
+
+ /*
+* Simple test to catch issues with compact 64K pages -- since the pt is
+* compacted to 256B that gives us 32 entries per pt, however since the
+* backing page for the pt is 4K, any extra entries we might incorrectly
+* write out should be ignored by the HW. If ever hit such a case this
+* test should catch it since some of our writes would land in scratch.
+*/
+
+ if (!HAS_64K_PAGES(i915)) {
+ pr_info("device lacks compact 64K page support, skipping\n");
+ return 0;
+ }
+
+ if (!HAS_LMEM(i915)) {
+ pr_info("device lacks LMEM support, skipping\n");
+ return 0;
+ }
+
+ /* We want the range to cover multiple page-table boundaries. */
+ obj = i915_gem_object_create_lmem(i915, SZ_4M, 0);
+ if (IS_ERR(obj))
+ return err;
+
+ err = i915_gem_object_pin_pages_unlocked(obj);
+ if (err)
+ goto out_put;
+
+ if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
+ pr_info("LMEM compact unable to allocate huge-page(s)\n");
+ goto out_unpin;
+ }
+
+ /*
+* Disable 2M GTT pages by forcing the page-size to 64K for the GTT
+* insertion.
+*/
+ obj->mm.page_sizes.sg = I915_GTT_PAGE_SIZE_64K;
+
+ err = igt_write_huge(ctx, obj);
+ if (err)
+ pr_err("LMEM compact write-huge failed\n");
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_tmpfs_fallback(void *arg)
{
struct i915_gem_context *ctx = arg;
@@ -1664,6 +1724,7 @@ int i915_gem_huge_page_live_selftests(struct
drm_i915_private *i915)
SUBTEST(igt_tmpfs_fallback),
SUBTEST(igt_ppgtt_smoke_huge),
SUBTEST(igt_ppgtt_sanity_check),
+ SUBTEST(igt_ppgtt_compact),
};
struct i915_gem_context *ctx;
struct i915_address_space *vm;
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 8c948f3b8cd8..8bf7c81064e1 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -233,6 +233,8 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space *
const vm,
start, end, lvl);
} else {
unsigned int count;
+ unsigned int pte = gen8_pd_index(start, 0);
+ unsigned int num_ptes;
u64 *vaddr;
count = gen8_pt_count(start, end);
@@ -242,10 +244,18 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space *
const vm,
atomic_read(>used));
GEM_BUG_ON(!count || count >= atomic_read(>used));
+ num_ptes = count;
+ if (pt->is_compact) {
+ GEM_BUG_ON(num_ptes % 16);
+ GEM_BUG_ON(pte % 16);
+ num_ptes /= 16;
+ pte /= 16;
+ }
+
vaddr = px_vaddr(pt);
- memset64(vaddr + gen8_pd_index(start, 0),
+ memset64(vaddr + pte,
vm->scratch[0]->encode,
-count);
+num_ptes);
atomic_sub(count, >used);
start
[Intel-gfx] [RFC 06/13] drm/i915/gtt/xehpsdv: move scratch page to system memory
From: Matthew Auld
On some platforms the hw has dropped support for 4K GTT pages when
dealing with LMEM, and due to the design of 64K GTT pages in the hw, we
can only mark the *entire* page-table as operating in 64K GTT mode,
since the enable bit is still on the pde, and not the pte. And since we
we still need to allow 4K GTT pages for SMEM objects, we can't have a
"normal" 4K page-table with scratch pointing to LMEM, since that's
undefined from the hw pov. The simplest solution is to just move the 64K
scratch page to SMEM on such platforms and call it a day, since that
should work for all configurations.
Signed-off-by: Matthew Auld
Signed-off-by: Ayaz A Siddiqui
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 +
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 23 +--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 +++
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++
drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 ++
6 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 1aee5e6b1b23..74306a77a2be 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -440,6 +440,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
ppgtt->base.vm.alloc_pt_dma = alloc_pt_dma;
+ ppgtt->base.vm.alloc_scratch_dma = alloc_pt_dma;
ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
ppgtt->base.pd = __alloc_pd(I915_PDES);
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 6e0e52eeb87a..8c948f3b8cd8 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -774,10 +774,29 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
*/
ppgtt->vm.has_read_only = !IS_GRAPHICS_VER(gt->i915, 11, 12);
- if (HAS_LMEM(gt->i915))
+ if (HAS_LMEM(gt->i915)) {
ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;
- else
+
+ /*
+* On some platforms the hw has dropped support for 4K GTT pages
+* when dealing with LMEM, and due to the design of 64K GTT
+* pages in the hw, we can only mark the *entire* page-table as
+* operating in 64K GTT mode, since the enable bit is still on
+* the pde, and not the pte. And since we still need to allow
+* 4K GTT pages for SMEM objects, we can't have a "normal" 4K
+* page-table with scratch pointing to LMEM, since that's
+* undefined from the hw pov. The simplest solution is to just
+* move the 64K scratch page to SMEM on such platforms and call
+* it a day, since that should work for all configurations.
+*/
+ if (HAS_64K_PAGES(gt->i915))
+ ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
+ else
+ ppgtt->vm.alloc_scratch_dma = alloc_pt_lmem;
+ } else {
ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
+ }
err = gen8_init_scratch(>vm);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index de3ac58fceec..140439c8bdeb 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -910,6 +910,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
size = gen8_get_total_gtt_size(snb_gmch_ctl);
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
ggtt->vm.cleanup = gen6_gmch_remove;
@@ -1062,6 +1063,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
ggtt->vm.clear_range = nop_clear_range;
if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
@@ -1114,6 +1116,7 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
(struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
if (needs_idle_maps(i915)) {
drm_notice(>drm,
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index e9c01f72fc18..71b25cd67c9f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -297,7 +297,7 @@ int setup_scratch_page(struct i915_address_space *vm)
do {
struct drm_i915_gem_object *obj;
- obj =
[Intel-gfx] [RFC 04/13] drm/i915/gem: Remove unused i915_gem_lmem_obj_ops
Removing extern declaration of i915_gem_lmem_obj_ops from i915_gem_lmem.h. Signed-off-by: Ayaz A Siddiqui --- drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h index 4ee81fc66302..2b4beb94b8db 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h @@ -12,8 +12,6 @@ struct drm_i915_private; struct drm_i915_gem_object; struct intel_memory_region; -extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops; - void __iomem * i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj, unsigned long n, -- 2.26.2
[Intel-gfx] [RFC 05/13] drm/i915: enforce min page size for scratch
From: Matthew Auld If the device needs 64K minimum GTT pages for device local-memory, like on XEHPSDV, then we need to fail the allocation if we can't meet it, instead of falling back to 4K pages, otherwise we can't safely support the insertion of device local-memory pages for this vm, since the HW expects the correct physical alignment and size for every PTE, if we mark the page-table as 64K GTT mode. Signed-off-by: Matthew Auld Signed-off-by: Ayaz A Siddiqui --- drivers/gpu/drm/i915/gt/intel_gtt.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index e137dd32b5b8..e9c01f72fc18 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -333,6 +333,18 @@ int setup_scratch_page(struct i915_address_space *vm) if (size == I915_GTT_PAGE_SIZE_4K) return -ENOMEM; + /* +* If we need 64K minimum GTT pages for device local-memory, +* like on XEHPSDV, then we need to fail the allocation here, +* otherwise we can't safely support the insertion of +* local-memory pages for this vm, since the HW expects the +* correct physical alignment and size when the page-table is +* operating in 64K GTT mode, which includes any scratch PTEs, +* since userpsace can still touch them. +*/ + if (HAS_64K_PAGES(vm->i915)) + return -ENOMEM; + size = I915_GTT_PAGE_SIZE_4K; } while (1); } -- 2.26.2
[Intel-gfx] [RFC 03/13] drm/i915/xehpsdv: enforce min GTT alignment
From: Matthew Auld
For local-memory objects we need to align the GTT addresses to 64K, both
for the ppgtt and ggtt.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_vma.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 4b7fc4647e46..1ea1fa08efdf 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -670,8 +670,13 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64
alignment, u64 flags)
}
color = 0;
- if (vma->obj && i915_vm_has_cache_coloring(vma->vm))
- color = vma->obj->cache_level;
+ if (vma->obj) {
+ if (HAS_64K_PAGES(vma->vm->i915) &&
i915_gem_object_is_lmem(vma->obj))
+ alignment = max(alignment, I915_GTT_PAGE_SIZE_64K);
+
+ if (i915_vm_has_cache_coloring(vma->vm))
+ color = vma->obj->cache_level;
+ }
if (flags & PIN_OFFSET_FIXED) {
u64 offset = flags & PIN_OFFSET_MASK;
--
2.26.2
[Intel-gfx] [RFC 02/13] drm/i915/xehpsdv: set min page-size to 64K
From: Matthew Auld LMEM should be allocated at 64K granularity, since 4K page support will eventually be dropped for LMEM when using the PPGTT. Signed-off-by: Matthew Auld Signed-off-by: Stuart Summers Signed-off-by: Ayaz A Siddiqui Cc: Joonas Lahtinen Cc: Rodrigo Vivi --- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 4 +++- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c index ddd37ccb1362..291fc3ec98de 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c @@ -780,6 +780,8 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type, struct intel_memory_region *mem; resource_size_t io_start; resource_size_t lmem_size; + resource_size_t min_page_size = HAS_64K_PAGES(i915) ? + I915_GTT_PAGE_SIZE_64K : I915_GTT_PAGE_SIZE_4K; u64 lmem_base; lmem_base = intel_uncore_read64(uncore, GEN12_DSMBASE); @@ -790,7 +792,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type, io_start = pci_resource_start(pdev, 2) + lmem_base; mem = intel_memory_region_create(i915, lmem_base, lmem_size, -I915_GTT_PAGE_SIZE_4K, io_start, +min_page_size, io_start, type, instance, _region_stolen_lmem_ops); if (IS_ERR(mem)) diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index a74b72f50cc9..4ea0ad9435df 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -195,6 +195,8 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) struct intel_memory_region *mem; resource_size_t io_start; resource_size_t lmem_size; + resource_size_t min_page_size = HAS_64K_PAGES(i915) ? + I915_GTT_PAGE_SIZE_64K : I915_GTT_PAGE_SIZE_4K; int err; if (!IS_DGFX(i915)) @@ -210,7 +212,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) mem = intel_memory_region_create(i915, 0, lmem_size, -I915_GTT_PAGE_SIZE_4K, +min_page_size, io_start, INTEL_MEMORY_LOCAL, 0, -- 2.26.2
[Intel-gfx] [RFC 01/13] drm/i915: Add has_64k_pages flag
From: Stuart Summers
Add a new platform flag, has_64k_pages, for platforms supporting
base page sizes of 64k.
Signed-off-by: Stuart Summers
Signed-off-by: Ayaz A Siddiqui
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8c722ea88e80..ac050e4599de 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1693,6 +1693,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_MSLICES(dev_priv) \
(INTEL_INFO(dev_priv)->has_mslices)
+#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
+
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2c1cb9b6b556..7b8bba60b899 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1014,6 +1014,7 @@ static const struct intel_device_info xehpsdv_info = {
DGFX_FEATURES,
PLATFORM(INTEL_XEHPSDV),
.display = { },
+ .has_64k_pages = 1,
.pipe_mask = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
@@ -1032,6 +1033,7 @@ static const struct intel_device_info dg2_info = {
.graphics_rel = 55,
.media_rel = 55,
PLATFORM(INTEL_DG2),
+ .has_64k_pages = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) |
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index d328bb95c49b..bbeec52ea6dc 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -123,6 +123,7 @@ enum intel_ppgtt_type {
func(is_dgfx); \
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
+ func(has_64k_pages); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_global_mocs); \
--
2.26.2
[Intel-gfx] [RFC 00/13] drm/i915/lmem: Enable device memory support for DG2
There are few changes for device memory in Gen12.5+ platforms. 1. Minimum page size has been changed to 64KB. 2. Compression control state (CCS) moved from user-space manages AUX page tables to flat indexed region of memory. This Flat index memory is referred as Flat CCS. 3. Due to different page sizes of LMEM(64K) and SMEM(4K), a mix of LMEM and SMEM pages are not supported in a single page table. This series is containing patches to cover all the above changes. Todo: Handling of Flat CCS during migration buffers from System to device memory and vice versa. Ayaz A Siddiqui (3): drm/i915/gem: Remove unused i915_gem_lmem_obj_ops drm/i915/lmem: Enable lmem for platforms with Flat CCS drm/i915/gt: Clear compress metadata for Gen12.5 >= platforms Bommu Krishnaiah (1): drm/i915: Add vm min alignment support CQ Tang (1): drm/i915/xehpsdv: Add has_flat_ccs to device info Matthew Auld (7): drm/i915/xehpsdv: set min page-size to 64K drm/i915/xehpsdv: enforce min GTT alignment drm/i915: enforce min page size for scratch drm/i915/gtt/xehpsdv: move scratch page to system memory drm/i915/xehpsdv: support 64K GTT pages drm/i915/selftests: account for min_alignment in GTT selftests drm/i915/xehpsdv: implement memory coloring Stuart Summers (1): drm/i915: Add has_64k_pages flag drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 2 - drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 4 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 61 .../i915/gem/selftests/i915_gem_client_blt.c | 23 ++- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 + drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 145 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 + drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 14 ++ drivers/gpu/drm/i915/gt/intel_gt.c| 19 +++ drivers/gpu/drm/i915/gt/intel_gt.h| 1 + drivers/gpu/drm/i915/gt/intel_gtt.c | 23 ++- drivers/gpu/drm/i915/gt/intel_gtt.h | 20 +++ drivers/gpu/drm/i915/gt/intel_migrate.c | 121 ++- drivers/gpu/drm/i915/gt/intel_migrate.h | 1 - drivers/gpu/drm/i915/gt/intel_ppgtt.c | 1 + drivers/gpu/drm/i915/gt/intel_region_lmem.c | 27 +++- drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_gem_evict.c | 17 ++ drivers/gpu/drm/i915/i915_pci.c | 3 + drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/i915_vma.c | 55 +-- drivers/gpu/drm/i915/intel_device_info.h | 2 + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 96 drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 + 24 files changed, 575 insertions(+), 73 deletions(-) -- 2.26.2
