[Intel-gfx] ✓ Fi.CI.BAT: success for Enable mipi dsi on XELPD (rev3)
== Series Details == Series: Enable mipi dsi on XELPD (rev3) URL : https://patchwork.freedesktop.org/series/93917/ State : success == Summary == CI Bug Log - changes from CI_DRM_10522 -> Patchwork_20898 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20898/index.html Known issues Here are the changes found in Patchwork_20898 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20898/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +14 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20898/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([i915#1372]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10522/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20898/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html Possible fixes * igt@i915_module_load@reload: - fi-tgl-1115g4: [DMESG-WARN][5] ([i915#4002]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10522/fi-tgl-1115g4/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20898/fi-tgl-1115g4/igt@i915_module_l...@reload.html * igt@i915_selftest@live@workarounds: - fi-rkl-guc: [INCOMPLETE][7] ([i915#3920]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10522/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20898/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html Warnings * igt@kms_psr@primary_page_flip: - fi-tgl-1115g4: [SKIP][9] ([i915#1072]) -> [SKIP][10] ([i915#1072] / [i915#1385]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10522/fi-tgl-1115g4/igt@kms_psr@primary_page_flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20898/fi-tgl-1115g4/igt@kms_psr@primary_page_flip.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#1385]: https://gitlab.freedesktop.org/drm/intel/issues/1385 [i915#3920]: https://gitlab.freedesktop.org/drm/intel/issues/3920 [i915#4002]: https://gitlab.freedesktop.org/drm/intel/issues/4002 Participating hosts (40 -> 34) -- Missing(6): fi-ilk-m540 bat-adls-5 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus bat-jsl-1 Build changes - * Linux: CI_DRM_10522 -> Patchwork_20898 CI-20190529: 20190529 CI_DRM_10522: b9b50258869989a477e7c04ac6d21a6e3660048e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6186: 250081b306c6fa8f95405fab6a7604f1968dd4ec @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20898: b68c166da558fa7fb56f92588e7ffde8d0d851ff @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b68c166da558 drm/i915/dsi/xelpd: Enable mipi dsi support. e060d617f06f drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20898/index.html
[Intel-gfx] [PATCH] drm/i915/gt: Register the migrate contexts with their engines
Pinned contexts, like the migrate contexts need reset after resume
since their context image may have been lost. Also the GuC needs to
register pinned contexts.
Add a list to struct intel_engine_cs where we add all pinned contexts on
creation, and traverse that list at __engine_unpark() time to reset the
pinned contexts.
This fixes the kms_pipe_crc_basic@suspend-read-crc-pipe-a selftest for now,
but proper LMEM backup / restore is needed for full suspend functionality.
However, note that even with full LMEM backup / restore it may be
desirable to keep the reset since backing up the migrate context images
must happen using memcpy() after the migrate context has become inactive,
and for performance- and other reasons we want to avoid memcpy() from
LMEM.
Also traverse the list at guc_init_lrc_mapping() calling
guc_kernel_context_pin() for the pinned contexts, like is already done
for the kernel context.
Cc: Tvrtko Ursulin
Cc: Matthew Auld
Cc: Maarten Lankhorst
Cc: Brost Matthew
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 8
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 9 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 +++
drivers/gpu/drm/i915/gt/mock_engine.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +++---
6 files changed, 36 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index e54351a170e2..a63631ea0ec4 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -152,6 +152,14 @@ struct intel_context {
/** sseu: Control eu/slice partitioning */
struct intel_sseu sseu;
+ /**
+* pinned_contexts_link: List link for the engine's pinned contexts.
+* This is only used if this is a perma-pinned kernel context and
+* the list is assumed to only be manipulated during driver load
+* or unload time so no mutex protection currently.
+*/
+ struct list_head pinned_contexts_link;
+
u8 wa_bb_page; /* if set, page num reserved for context workarounds */
struct {
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 332efea696a5..c606a4714904 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -320,6 +320,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
+ INIT_LIST_HEAD(&engine->pinned_contexts_list);
engine->id = id;
engine->legacy_idx = INVALID_ENGINE;
engine->mask = BIT(id);
@@ -875,6 +876,8 @@ intel_engine_create_pinned_context(struct intel_engine_cs
*engine,
return ERR_PTR(err);
}
+ list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list);
+
/*
* Give our perma-pinned kernel timelines a separate lockdep class,
* so that we can use them from within the normal user timelines
@@ -897,6 +900,7 @@ void intel_engine_destroy_pinned_context(struct
intel_context *ce)
list_del(&ce->timeline->engine_link);
mutex_unlock(&hwsp->vm->mutex);
+ list_del(&ce->pinned_contexts_link);
intel_context_unpin(ce);
intel_context_put(ce);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 1f07ac4e0672..3a5cbbf3e3fe 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -72,6 +72,15 @@ static int __engine_unpark(struct intel_wakeref *wf)
READ_ONCE(*ce->timeline->hwsp_seqno));
}
+ list_for_each_entry(ce, &engine->pinned_contexts_list,
+ pinned_contexts_link) {
+ if (ce == engine->kernel_context)
+ continue;
+
+ dbg_poison_ce(ce);
+ ce->ops->reset(ce);
+ }
+
if (engine->unpark)
engine->unpark(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index bfbfe53c23dd..5ae1207c363b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -307,6 +307,13 @@ struct intel_engine_cs {
struct intel_context *kernel_context; /* pinned */
+ /**
+* pinned_contexts_list: List of pinned contexts. This list is only
+* assumed to be manipulated during driver load- or unload time and
+* does therefore not have any additional protection.
+*/
+ struct list_head pinned_contexts_list;
+
intel_engine_mask_t saturated; /* submitting semaphores too late? */
Re: [Intel-gfx] refactor the i915 GVT support
On 2021.08.20 12:56:34 -0700, Luis Chamberlain wrote:
> On Fri, Aug 20, 2021 at 04:17:24PM +0200, Christoph Hellwig wrote:
> > On Thu, Aug 19, 2021 at 04:29:29PM +0800, Zhenyu Wang wrote:
> > > I'm working on below patch to resolve this. But I met a weird issue in
> > > case when building i915 as module and also kvmgt module, it caused
> > > busy wait on request_module("kvmgt") when boot, it doesn't happen if
> > > building i915 into kernel. I'm not sure what could be the reason?
> >
> > Luis, do you know if there is a problem with a request_module from
> > a driver ->probe routine that is probably called by a module_init
> > function itself?
>
> Generally no, but you can easily foot yourself in the feet by creating
> cross dependencies and not dealing with them properly. I'd make sure
> to keep module initialization as simple as possible, and run whatever
> takes more time asynchronously, then use a state machine to allow
> you to verify where you are in the initialization phase or query it
> or wait for a completion with a timeout.
>
> It seems the code in question is getting some spring cleaning, and its
> unclear where the code is I can inspect. If there's a tree somewhere I
> can take a peak I'd be happy to review possible oddities that may stick
> out.
I tried to put current patches under test here:
https://github.com/intel/gvt-linux/tree/gvt-staging
The issue can be produced with CONFIG_DRM_I915=m and
CONFIG_DRM_I915_GVT_KVMGT=m.
>
> My goto model for these sorts of problems is to abstract the issue
> *outside* of the driver in question and implement new selftests to
> try to reproduce. This serves two purposes, 1) helps with testing
> 2) may allow you to see the problem more clearly.
>
I'll see if can abstract that.
Thanks, Luis.
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Re: [Intel-gfx] refactor the i915 GVT support
On 2021.08.20 16:17:24 +0200, Christoph Hellwig wrote:
> On Thu, Aug 19, 2021 at 04:29:29PM +0800, Zhenyu Wang wrote:
> > I'm working on below patch to resolve this. But I met a weird issue in
> > case when building i915 as module and also kvmgt module, it caused
> > busy wait on request_module("kvmgt") when boot, it doesn't happen if
> > building i915 into kernel. I'm not sure what could be the reason?
>
> Luis, do you know if there is a problem with a request_module from
> a driver ->probe routine that is probably called by a module_init
> function itself?
>
> In the meantime I'll try to reproduce it locally, but I always had a
> hard time getting useful results out of a modular i915, especially
> when combined with module paramters. (no blame on i915, just the problem
> with modules needed early on).
>
> >
> > > But the problem I see is that after moving gvt device model (gvt/*.c
> > > except kvmgt.c) into kvmgt module, we'll have issue with initial mmio
> > > state which current gvt relies on, that is in design supposed to get
> > > initial HW state before i915 driver has taken any operation. Before
> > > we can ensure that, I think we may only remove MPT part first but
> > > still keep gvt device model as part of i915 with config. I'll try to
> > > split that out.
> >
> > Sorry I misread the code that as we always request kvmgt module when
> > gvt init, so it should still apply original method that this isn't a
> > problem. Our current validation result has shown no regression as well.
>
> What does initial mmio state mean? This is something new to me. But
> as you said in this mail unless I missed something very big it should
> work the same as before.
>
It's gvt internal track for all gfx mmio state, and yes with your current
change it should still work as before.
> > -static inline void intel_context_unpin(struct intel_context *ce)
> > +static inline void _intel_context_unpin(struct intel_context *ce)
> > {
> > if (!ce->ops->sched_disable) {
> > __intel_context_do_unpin(ce, 1);
> > @@ -150,6 +150,7 @@ static inline void intel_context_unpin(struct
> > intel_context *ce)
> > }
> > }
> > }
> > +void intel_context_unpin(struct intel_context *ce);
>
> Looking at intel_context_unpin/_intel_context_unpin is there really
> a need to have this inline to start with? It don't see much the compiler
> could optimize by inlining it.
I'll send patch to i915 for this, and get more comments there.
thanks
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Re: [Intel-gfx] refactor the i915 GVT support
On 2021.08.19 17:43:43 +0300, Joonas Lahtinen wrote:
> Quoting Zhenyu Wang (2021-08-19 11:29:29)
> > On 2021.08.17 13:22:03 +0800, Zhenyu Wang wrote:
> > > > On 2021.08.16 19:34:58 +0200, Christoph Hellwig wrote:
> > > > > Any updates on this? I'd really hate to miss this merge window.
> > > >
> > > > I'm still waiting for our validation team's report on this. I'm afraid
> > > > it might be missing for next version as i915 merge window is mostly
> > > > till rc5...and for any change outside of gvt, it still needs to be
> > > > acked by i915 maintainers.
> > >
> > > Looks our validation team did have problem against recent i915 change.
> > > If you like to try, we have a gvt-staging branch on
> > > https://github.com/intel/gvt-linux which is generated against drm-tip
> > > with gvt changes for testing, currently it's broken.
> > >
> > > One issue is with i915 export that intel_context_unpin has been
> > > changed into static inline function. Another is that intel_gvt.c
> > > should be part of i915 for gvt interface instead of depending on KVMGT
> > > config.
> >
> > I'm working on below patch to resolve this. But I met a weird issue in
> > case when building i915 as module and also kvmgt module, it caused
> > busy wait on request_module("kvmgt") when boot, it doesn't happen if
> > building i915 into kernel. I'm not sure what could be the reason?
> >
> > > But the problem I see is that after moving gvt device model (gvt/*.c
> > > except kvmgt.c) into kvmgt module, we'll have issue with initial mmio
> > > state which current gvt relies on, that is in design supposed to get
> > > initial HW state before i915 driver has taken any operation.
>
> As mentioned in some past discussions, I think it would be best rely on
> golden MMIO located in /lib/firmware or elsewhere. This way we will better
> isolate the guest system from host system updates/changes.
>
> This should also hopefully allow enabling kvmgt module after i915 has
> already loaded, as the initialization would not be conditional to
> capture the MMIO.
>
I think the concern is that even for same GEN hw there could be many
variant platforms e.g APL with gen9, etc. To verify golden states for
them all might take too much effort...
>
> > > Before
> > > we can ensure that, I think we may only remove MPT part first but
> > > still keep gvt device model as part of i915 with config. I'll try to
> > > split that out.
> >
> > Sorry I misread the code that as we always request kvmgt module when
> > gvt init, so it should still apply original method that this isn't a
> > problem. Our current validation result has shown no regression as well.
> >
> > ---8<---
> > From 58ff84572f1a0f9d79ca1d7ec0cff5ecbe78d280 Mon Sep 17 00:00:00 2001
> > From: Zhenyu Wang
> > Date: Thu, 19 Aug 2021 16:36:33 +0800
> > Subject: [PATCH] TESTONLY:drm/i915/gvt: potential fix for refactor against
> > current tip
> >
> > ---
> > drivers/gpu/drm/i915/Makefile | 4 +++-
> > drivers/gpu/drm/i915/gt/intel_context.c | 5 +
> > drivers/gpu/drm/i915/gt/intel_context.h | 3 ++-
> > drivers/gpu/drm/i915/i915_trace.h | 1 +
> > 4 files changed, 11 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > index c4f953837f72..2248574428a1 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -296,7 +296,9 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
> >
> > # virtual gpu code
> > i915-y += i915_vgpu.o
> > -i915-$(CONFIG_DRM_I915_GVT_KVMGT) += intel_gvt.o
> > +ifneq ($(CONFIG_DRM_I915_GVT_KVMGT),)
> > +i915-y += intel_gvt.o
> > +endif
> >
> > kvmgt-y += gvt/kvmgt.o \
> > gvt/gvt.o \
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
> > b/drivers/gpu/drm/i915/gt/intel_context.c
> > index 745e84c72c90..20e7522fed84 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> > @@ -328,6 +328,11 @@ void __intel_context_do_unpin(struct intel_context
> > *ce, int sub)
> > intel_context_put(ce);
> > }
> >
> > +void intel_context_unpin(struct intel_context *ce)
> > +{
> > + _intel_context_unpin(ce);
> > +}
> > +
> > static void __intel_context_retire(struct i915_active *active)
> > {
> > struct intel_context *ce = container_of(active, typeof(*ce),
> > active);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
> > b/drivers/gpu/drm/i915/gt/intel_context.h
> > index c41098950746..f942cbf6300a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context.h
> > @@ -131,7 +131,7 @@ static inline void
> > intel_context_sched_disable_unpin(struct intel_context *ce)
> > __intel_context_do_unpin(ce, 2);
> > }
> >
> > -static inline void intel_context_unpin(struct intel_context *ce)
> > +static inline void _intel_context_unpin(struct intel_context *ce)
> > {
> > if (!ce->ops->sched_disable) {
> > __intel
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable mipi dsi on XELPD (rev3)
== Series Details == Series: Enable mipi dsi on XELPD (rev3) URL : https://patchwork.freedesktop.org/series/93917/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:expected struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:got struct i915_address_space * +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - differ
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Ensure wa_init_finish() is called for ctx workaround list
== Series Details == Series: drm/i915: Ensure wa_init_finish() is called for ctx workaround list URL : https://patchwork.freedesktop.org/series/94053/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10522 -> Patchwork_20897 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20897 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20897, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20897/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20897: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_heartbeat: - fi-rkl-11600: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10522/fi-rkl-11600/igt@i915_selftest@live@gt_heartbeat.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20897/fi-rkl-11600/igt@i915_selftest@live@gt_heartbeat.html Known issues Here are the changes found in Patchwork_20897 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-rkl-guc: NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20897/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html * igt@i915_selftest@live@gt_lrc: - fi-rkl-guc: NOTRUN -> [DMESG-WARN][4] ([i915#3958]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20897/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-rkl-11600: [PASS][5] -> [SKIP][6] ([fdo#111825]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10522/fi-rkl-11600/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20897/fi-rkl-11600/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html Possible fixes * igt@i915_selftest@live@workarounds: - fi-rkl-guc: [INCOMPLETE][7] ([i915#3920]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10522/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20897/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [i915#3920]: https://gitlab.freedesktop.org/drm/intel/issues/3920 [i915#3958]: https://gitlab.freedesktop.org/drm/intel/issues/3958 Participating hosts (40 -> 33) -- Missing(7): fi-ilk-m540 bat-adls-5 fi-hsw-4200u fi-tgl-1115g4 fi-bsw-cyan fi-bdw-samus bat-jsl-1 Build changes - * Linux: CI_DRM_10522 -> Patchwork_20897 CI-20190529: 20190529 CI_DRM_10522: b9b50258869989a477e7c04ac6d21a6e3660048e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6186: 250081b306c6fa8f95405fab6a7604f1968dd4ec @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20897: 62aa62c0a572e2f0d442321e5dc197c51e896e1c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 62aa62c0a572 drm/i915: Ensure wa_init_finish() is called for ctx workaround list == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20897/index.html
Re: [Intel-gfx] [v2] drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband
Thanks for the review. Have fixed in the latest version, will merge once CI is
green.
> -Original Message-
> From: Nikula, Jani
> Sent: Wednesday, August 25, 2021 7:38 PM
> To: Kulkarni, Vandita ; intel-
> g...@lists.freedesktop.org
> Cc: Kulkarni, Vandita
> Subject: Re: [v2] drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup
> guardband
>
> On Mon, 23 Aug 2021, Vandita Kulkarni wrote:
> > Wa_16012360555 SW will have to program the "LP to HS Wakeup
> Guardband"
> > field to account for the repeaters on the HS Request/Ready PPI
> > signaling between the Display engine and the DPHY.
> >
> > v2: Fix build issue.
> >
> > Signed-off-by: Vandita Kulkarni
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 25
> +
> > drivers/gpu/drm/i915/i915_reg.h| 8
> > 2 files changed, 33 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index 43ec7fcd3f5d..b075defb88bb 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -1270,6 +1270,28 @@ static void icl_apply_kvmr_pipe_a_wa(struct
> intel_encoder *encoder,
> > IGNORE_KVMR_PIPE_A,
> > enable ? IGNORE_KVMR_PIPE_A : 0); }
> > +
> > +/*
> > + * Wa_16012360555:ADLP
>
> It should be adl-p, i.e. lower case and with a hyphen.
>
> > + * SW will have to program the "LP to HS Wakeup Guardband"
> > + * field (bits 15:12) of register offset 0x6B0C0 (DSI0)
> > + * and 0x6B8C0 (DSI1) to a value of 4 to account for the repeaters
> > + * on the HS Request/Ready PPI signaling between
> > + * the Display engine and the DPHY.
> > + */
>
> I think that's a bit verbose for the comment. In particular the register
> addresses and bits and values are redundant with the code.
>
> > +static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) {
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> i915 variable name is preferred for all new code.
>
> > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> > + enum port port;
> > +
> > + if (DISPLAY_VER(dev_priv) == 13) {
> > + for_each_dsi_port(port, intel_dsi->ports)
> > + intel_de_rmw(dev_priv, TGL_DSI_CHKN_REG(port),
> > +TGL_DSI_CHKN_LSHS_GB, 0x4);
> > + }
> > +}
> > +
> > static void gen11_dsi_enable(struct intel_atomic_state *state,
> > struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state, @@ -
> 1283,6 +1305,9
> > @@ static void gen11_dsi_enable(struct intel_atomic_state *state,
> > /* Wa_1409054076:icl,jsl,ehl */
> > icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);
> >
> > + /* Wa_16012360555: adlp */
>
> No space after : and adl-p.
>
> > + adlp_set_lp_hs_wakeup_gb(encoder);
> > +
> > /* step6d: enable dsi transcoder */
> > gen11_dsi_enable_transcoder(encoder);
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 72dd3a6d205d..4c90d45343d6
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -11614,6 +11614,14 @@ enum skl_power_gate {
> > _ICL_DSI_IO_MODECTL_1)
> > #define COMBO_PHY_MODE_DSI(1 << 0)
> >
> > +/* TGL DSI Chicken register */
> > +#define _TGL_DSI_CHKN_REG_00x6B0C0
> > +#define _TGL_DSI_CHKN_REG_10x6B8C0
> > +#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port,\
> > + _TGL_DSI_CHKN_REG_0, \
> > + _TGL_DSI_CHKN_REG_1)
> > +#define TGL_DSI_CHKN_LSHS_GB (0xF << 12)
>
> Please use REG_GENMASK(15, 12)
>
> With the issues fixed,
>
> Reviewed-by: Jani Nikula
>
>
> > +
> > /* Display Stream Splitter Control */
> > #define DSS_CTL1 _MMIO(0x67400)
> > #define SPLITTER_ENABLE (1 << 31)
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [v4 3/7] drm/i915/dsi: wait for header and payload credit available
> -Original Message-
> From: Lee, Shawn C
> Sent: Thursday, August 12, 2021 9:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; ville.syrj...@linux.intel.com;
> Kulkarni, Vandita ; Chiou, Cooper
> ; Tseng, William ; Lee,
> Shawn C ; Jani Nikula
> Subject: [v4 3/7] drm/i915/dsi: wait for header and payload credit available
>
> Driver should wait for free header or payload buffer in FIFO.
> It would be good to wait a while for HW to release credit before give it up to
> write to HW. Without sending initailize command sets completely. It would
> caused MIPI display can't light up properly.
>
> Cc: Ville Syrjala
> Cc: Jani Nikula
> Cc: Vandita Kulkarni
> Cc: Cooper Chiou
> Cc: William Tseng
> Signed-off-by: Lee Shawn C
Looks good to me.
Reviewed-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 40 --
> 1 file changed, 19 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 43ec7fcd3f5d..1780830d9909 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -54,20 +54,28 @@ static int payload_credits_available(struct
> drm_i915_private *dev_priv,
> >> FREE_PLOAD_CREDIT_SHIFT;
> }
>
> -static void wait_for_header_credits(struct drm_i915_private *dev_priv,
> - enum transcoder dsi_trans)
> +static bool wait_for_header_credits(struct drm_i915_private *dev_priv,
> + enum transcoder dsi_trans, int hdr_credit)
> {
> if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
> - MAX_HEADER_CREDIT, 100))
> + hdr_credit, 100)) {
> drm_err(&dev_priv->drm, "DSI header credits not
> released\n");
> + return false;
> + }
> +
> + return true;
> }
>
> -static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
> - enum transcoder dsi_trans)
> +static bool wait_for_payload_credits(struct drm_i915_private *dev_priv,
> + enum transcoder dsi_trans, int
> payld_credit)
> {
> if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
> - MAX_PLOAD_CREDIT, 100))
> + payld_credit, 100)) {
> drm_err(&dev_priv->drm, "DSI payload credits not
> released\n");
> + return false;
> + }
> +
> + return true;
> }
>
> static enum transcoder dsi_port_to_transcoder(enum port port) @@ -90,8
> +98,8 @@ static void wait_for_cmds_dispatched_to_panel(struct
> intel_encoder *encoder)
> /* wait for header/payload credits to be released */
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - wait_for_header_credits(dev_priv, dsi_trans);
> - wait_for_payload_credits(dev_priv, dsi_trans);
> + wait_for_header_credits(dev_priv, dsi_trans,
> MAX_HEADER_CREDIT);
> + wait_for_payload_credits(dev_priv, dsi_trans,
> MAX_PLOAD_CREDIT);
> }
>
> /* send nop DCS command */
> @@ -108,7 +116,7 @@ static void
> wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
> /* wait for header credits to be released */
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - wait_for_header_credits(dev_priv, dsi_trans);
> + wait_for_header_credits(dev_priv, dsi_trans,
> MAX_HEADER_CREDIT);
> }
>
> /* wait for LP TX in progress bit to be cleared */ @@ -126,18 +134,13
> @@ static bool add_payld_to_queue(struct intel_dsi_host *host, const u8
> *data,
> struct intel_dsi *intel_dsi = host->intel_dsi;
> struct drm_i915_private *dev_priv = to_i915(intel_dsi-
> >base.base.dev);
> enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
> - int free_credits;
> int i, j;
>
> for (i = 0; i < len; i += 4) {
> u32 tmp = 0;
>
> - free_credits = payload_credits_available(dev_priv,
> dsi_trans);
> - if (free_credits < 1) {
> - drm_err(&dev_priv->drm,
> - "Payload credit not available\n");
> + if (!wait_for_payload_credits(dev_priv, dsi_trans, 1))
> return false;
> - }
>
> for (j = 0; j < min_t(u32, len - i, 4); j++)
> tmp |= *data++ << 8 * j;
> @@ -155,15 +158,10 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host
> *host,
> struct drm_i915_private *dev_priv = to_i915(intel_dsi-
> >base.base.dev);
> enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
> u32 tmp;
> - int free_credits;
>
> /* check if header credit available */
> - free_credits = header_credits_availa
[Intel-gfx] [v2 1/2] drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband
Wa_16012360555 SW will have to program the "LP to HS Wakeup Guardband"
field to account for the repeaters on the HS Request/Ready PPI signaling
between the Display engine and the DPHY.
v2: Fix build issue.
v3: Align to new naming (Jani)
Signed-off-by: Vandita Kulkarni
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 23 +++
drivers/gpu/drm/i915/i915_reg.h| 8
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 43ec7fcd3f5d..55645c456d9e 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1270,6 +1270,26 @@ static void icl_apply_kvmr_pipe_a_wa(struct
intel_encoder *encoder,
IGNORE_KVMR_PIPE_A,
enable ? IGNORE_KVMR_PIPE_A : 0);
}
+
+/*
+ * Wa_16012360555:adl-p
+ * SW will have to program the "LP to HS Wakeup Guardband"
+ * to account for the repeaters on the HS Request/Ready
+ * PPI signaling between the Display engine and the DPHY.
+ */
+static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+ enum port port;
+
+ if (DISPLAY_VER(i915) == 13) {
+ for_each_dsi_port(port, intel_dsi->ports)
+ intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
+TGL_DSI_CHKN_LSHS_GB, 0x4);
+ }
+}
+
static void gen11_dsi_enable(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
@@ -1283,6 +1303,9 @@ static void gen11_dsi_enable(struct intel_atomic_state
*state,
/* Wa_1409054076:icl,jsl,ehl */
icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);
+ /* Wa_16012360555:adl-p */
+ adlp_set_lp_hs_wakeup_gb(encoder);
+
/* step6d: enable dsi transcoder */
gen11_dsi_enable_transcoder(encoder);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8d4cf1e203ab..815fc73bd2f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11639,6 +11639,14 @@ enum skl_power_gate {
_ICL_DSI_IO_MODECTL_1)
#define COMBO_PHY_MODE_DSI(1 << 0)
+/* TGL DSI Chicken register */
+#define _TGL_DSI_CHKN_REG_00x6B0C0
+#define _TGL_DSI_CHKN_REG_10x6B8C0
+#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port,\
+ _TGL_DSI_CHKN_REG_0, \
+ _TGL_DSI_CHKN_REG_1)
+#define TGL_DSI_CHKN_LSHS_GB REG_GENMASK(15, 12)
+
/* Display Stream Splitter Control */
#define DSS_CTL1 _MMIO(0x67400)
#define SPLITTER_ENABLE (1 << 31)
--
2.32.0
[Intel-gfx] [v2 2/2] drm/i915/dsi/xelpd: Enable mipi dsi support.
Enable MIPI DSI support on ADL-P platform.
The esc clock changes, WA changes are taken care
in the previous patches.
As per the Bspec the seq remains to be same as TGL.
Signed-off-by: Vandita Kulkarni
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index fe5ad599c218..a7d002321bdc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11009,6 +11009,7 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_ddi_init(dev_priv, PORT_TC2);
intel_ddi_init(dev_priv, PORT_TC3);
intel_ddi_init(dev_priv, PORT_TC4);
+ icl_dsi_init(dev_priv);
} else if (IS_ALDERLAKE_S(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_TC1);
--
2.32.0
[Intel-gfx] [v2 0/2] Enable mipi dsi on XELPD
Vandita Kulkarni (2): drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband drm/i915/dsi/xelpd: Enable mipi dsi support. drivers/gpu/drm/i915/display/icl_dsi.c | 23 drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 8 +++ 3 files changed, 32 insertions(+) -- 2.32.0
[Intel-gfx] ✓ Fi.CI.BAT: success for Clean up GuC CI failures, simplify locking, and kernel DOC (rev5)
== Series Details == Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev5) URL : https://patchwork.freedesktop.org/series/93704/ State : success == Summary == CI Bug Log - changes from CI_DRM_10522 -> Patchwork_20896 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20896/index.html New tests - New tests have been introduced between CI_DRM_10522 and Patchwork_20896: ### New IGT tests (1) ### * igt@i915_selftest@live@guc: - Statuses : 29 pass(s) - Exec time: [0.40, 5.00] s Known issues Here are the changes found in Patchwork_20896 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20896/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html * igt@core_hotunplug@unbind-rebind: - fi-rkl-guc: [PASS][2] -> [DMESG-WARN][3] ([i915#3925]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10522/fi-rkl-guc/igt@core_hotunp...@unbind-rebind.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20896/fi-rkl-guc/igt@core_hotunp...@unbind-rebind.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-skl-6700k2: [PASS][4] -> [INCOMPLETE][5] ([i915#146]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10522/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20896/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html * igt@runner@aborted: - fi-rkl-guc: NOTRUN -> [FAIL][6] ([i915#1602]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20896/fi-rkl-guc/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602 [i915#3925]: https://gitlab.freedesktop.org/drm/intel/issues/3925 Participating hosts (40 -> 33) -- Missing(7): fi-ilk-m540 bat-adls-5 fi-hsw-4200u fi-tgl-1115g4 fi-bsw-cyan fi-bdw-samus bat-jsl-1 Build changes - * Linux: CI_DRM_10522 -> Patchwork_20896 CI-20190529: 20190529 CI_DRM_10522: b9b50258869989a477e7c04ac6d21a6e3660048e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6186: 250081b306c6fa8f95405fab6a7604f1968dd4ec @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20896: cf1ce58e8ab52b2d06bd0ed91d8fe1d2e62b646c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == cf1ce58e8ab5 drm/i915/guc: Drop static inline functions intel_guc_submission.c b9a4dd93511f drm/i915/guc: Add GuC kernel doc 818b96c726c3 drm/i915/guc: Drop guc_active move everything into guc_state 8a835e57e906 drm/i915/guc: Move fields protected by guc->contexts_lock into sub structure d463a3297412 drm/i915/guc: Move GuC priority fields in context under guc_active fa4e0e879240 drm/i915/guc: Drop pin count check trick between sched_disable and re-pin b7cbde64c3bf drm/i915/guc: Proper xarray usage for contexts_lookup ffc3720eacde drm/i915/guc: Rework and simplify locking e45d040e7d64 drm/i915/guc: Move guc_blocked fence to struct guc_state c26a137a1a98 drm/i915/guc: Release submit fence from an irq_work 1275c6c2a642 drm/i915/guc: Flush G2H work queue during reset 7ffd90c5f795 drm/i915: Allocate error capture in nowait context ec42c335cbc5 drm/i915/guc: Reset LRC descriptor if register returns -ENODEV 21b0b713c8ed drm/i915/guc: Don't touch guc_state.sched_state without a lock 294dd722f049 drm/i915/guc: Take context ref when cancelling request 10c9d7e6445c drm/i915/selftests: Add initial GuC selftest for scrubbing lost G2H 94e9e0579d73 drm/i915/guc: Copy whole golden context, set engine state size of subset c72bc8455075 drm/i915/guc: Don't enable scheduling on a banned context, guc_id invalid, not registered 8c57d70df62e drm/i915/guc: Kick tasklet after queuing a request 641110bbb3dd drm/i915/selftests: Add a cancel request selftest that triggers a reset 5db336e06b96 Revert "drm/i915/gt: Propagate change in error status to children on unhold" 0bd9a75d05d5 drm/i915/guc: Workaround reset G2H is received after schedule done G2H 917c35136667 drm/i915/guc: Process all G2H message at once in work queue 9d217dd094d4 drm/i915/guc: Don't drop ce->guc_active.lock when unwinding context 6d797176750f drm/i915/guc: Unwind context requests in reverse order e463d05638a5 drm/i915/guc: Fix outstanding G2H accounting 7dc01ebd7a94 drm/i915/guc: Fix blocked context accounting == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20896/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Clean up GuC CI failures, simplify locking, and kernel DOC (rev5)
== Series Details == Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev5) URL : https://patchwork.freedesktop.org/series/93704/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:expected struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:got struct i915_address_space * +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock co
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clean up GuC CI failures, simplify locking, and kernel DOC (rev5)
== Series Details ==
Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev5)
URL : https://patchwork.freedesktop.org/series/93704/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7dc01ebd7a94 drm/i915/guc: Fix blocked context accounting
e463d05638a5 drm/i915/guc: Fix outstanding G2H accounting
6d797176750f drm/i915/guc: Unwind context requests in reverse order
9d217dd094d4 drm/i915/guc: Don't drop ce->guc_active.lock when unwinding context
917c35136667 drm/i915/guc: Process all G2H message at once in work queue
0bd9a75d05d5 drm/i915/guc: Workaround reset G2H is received after schedule done
G2H
5db336e06b96 Revert "drm/i915/gt: Propagate change in error status to children
on unhold"
-:8: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 3761baae908a ("Revert "drm/i915:
Propagate errors on awaiting already signaled fences"")'
#8:
errors from one client ending up in another. In 3761baae908a (Revert
-:11: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 8e9f84cf5cac ("drm/i915/gt:
Propagate change in error status to children on unhold")'
#11:
added in 8e9f84cf5cac ("drm/i915/gt: Propagate change in error status
-:24: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#24:
References: '3761baae908a ("Revert "drm/i915: Propagate errors on awaiting
already signaled fences"")'
total: 2 errors, 1 warnings, 0 checks, 10 lines checked
641110bbb3dd drm/i915/selftests: Add a cancel request selftest that triggers a
reset
8c57d70df62e drm/i915/guc: Kick tasklet after queuing a request
-:8: WARNING:TYPO_SPELLING: 'inteface' may be misspelled - perhaps 'interface'?
#8:
Fixes: 3a4cdf1982f0 ("drm/i915/guc: Implement GuC context operations for new
inteface")
total: 0 errors, 1 warnings, 0 checks, 7 lines checked
c72bc8455075 drm/i915/guc: Don't enable scheduling on a banned context, guc_id
invalid, not registered
94e9e0579d73 drm/i915/guc: Copy whole golden context, set engine state size of
subset
10c9d7e6445c drm/i915/selftests: Add initial GuC selftest for scrubbing lost G2H
-:108: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#108:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 233 lines checked
294dd722f049 drm/i915/guc: Take context ref when cancelling request
21b0b713c8ed drm/i915/guc: Don't touch guc_state.sched_state without a lock
ec42c335cbc5 drm/i915/guc: Reset LRC descriptor if register returns -ENODEV
7ffd90c5f795 drm/i915: Allocate error capture in nowait context
1275c6c2a642 drm/i915/guc: Flush G2H work queue during reset
c26a137a1a98 drm/i915/guc: Release submit fence from an irq_work
e45d040e7d64 drm/i915/guc: Move guc_blocked fence to struct guc_state
ffc3720eacde drm/i915/guc: Rework and simplify locking
b7cbde64c3bf drm/i915/guc: Proper xarray usage for contexts_lookup
fa4e0e879240 drm/i915/guc: Drop pin count check trick between sched_disable and
re-pin
d463a3297412 drm/i915/guc: Move GuC priority fields in context under guc_active
8a835e57e906 drm/i915/guc: Move fields protected by guc->contexts_lock into sub
structure
818b96c726c3 drm/i915/guc: Drop guc_active move everything into guc_state
b9a4dd93511f drm/i915/guc: Add GuC kernel doc
cf1ce58e8ab5 drm/i915/guc: Drop static inline functions intel_guc_submission.c
Re: [Intel-gfx] [PATCH 24/33] drm/i915/guc: Implement banned contexts for GuC submission
On Wed, Aug 25, 2021 at 11:39:10AM +0100, Tvrtko Ursulin wrote:
>
> On 27/07/2021 01:23, Matthew Brost wrote:
> > When using GuC submission, if a context gets banned disable scheduling
> > and mark all inflight requests as complete.
> >
> > Cc: John Harrison
> > Signed-off-by: Matthew Brost
> > Reviewed-by: John Harrison
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_context.h | 13 ++
> > drivers/gpu/drm/i915/gt/intel_context_types.h | 2 +
> > drivers/gpu/drm/i915/gt/intel_reset.c | 32 +---
> > .../gpu/drm/i915/gt/intel_ring_submission.c | 20 +++
> > drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 +
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 151 --
> > drivers/gpu/drm/i915/i915_trace.h | 10 ++
> > 8 files changed, 195 insertions(+), 37 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index e3df01a201d7..05c3ee191710 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -1084,7 +1084,7 @@ static void kill_engines(struct i915_gem_engines
> > *engines, bool ban)
> > for_each_gem_engine(ce, engines, it) {
> > struct intel_engine_cs *engine;
> > - if (ban && intel_context_set_banned(ce))
> > + if (ban && intel_context_ban(ce, NULL))
> > continue;
> > /*
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
> > b/drivers/gpu/drm/i915/gt/intel_context.h
> > index 2ed9bf5f91a5..814d9277096a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context.h
> > @@ -16,6 +16,7 @@
> > #include "intel_engine_types.h"
> > #include "intel_ring_types.h"
> > #include "intel_timeline_types.h"
> > +#include "i915_trace.h"
> > #define CE_TRACE(ce, fmt, ...) do {
> > \
> > const struct intel_context *ce__ = (ce);\
> > @@ -243,6 +244,18 @@ static inline bool intel_context_set_banned(struct
> > intel_context *ce)
> > return test_and_set_bit(CONTEXT_BANNED, &ce->flags);
> > }
> > +static inline bool intel_context_ban(struct intel_context *ce,
> > +struct i915_request *rq)
> > +{
> > + bool ret = intel_context_set_banned(ce);
> > +
> > + trace_intel_context_ban(ce);
> > + if (ce->ops->ban)
> > + ce->ops->ban(ce, rq);
> > +
> > + return ret;
> > +}
> > +
> > static inline bool
> > intel_context_force_single_submission(const struct intel_context *ce)
> > {
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > index 035108c10b2c..57c19ee3e313 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > @@ -35,6 +35,8 @@ struct intel_context_ops {
> > int (*alloc)(struct intel_context *ce);
> > + void (*ban)(struct intel_context *ce, struct i915_request *rq);
> > +
> > int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww,
> > void **vaddr);
> > int (*pin)(struct intel_context *ce, void *vaddr);
> > void (*unpin)(struct intel_context *ce);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> > b/drivers/gpu/drm/i915/gt/intel_reset.c
> > index 4d281bc8a38c..91200c43951f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > @@ -22,7 +22,6 @@
> > #include "intel_reset.h"
> > #include "uc/intel_guc.h"
> > -#include "uc/intel_guc_submission.h"
> > #define RESET_MAX_RETRIES 3
> > @@ -39,21 +38,6 @@ static void rmw_clear_fw(struct intel_uncore *uncore,
> > i915_reg_t reg, u32 clr)
> > intel_uncore_rmw_fw(uncore, reg, clr, 0);
> > }
> > -static void skip_context(struct i915_request *rq)
> > -{
> > - struct intel_context *hung_ctx = rq->context;
> > -
> > - list_for_each_entry_from_rcu(rq, &hung_ctx->timeline->requests, link) {
> > - if (!i915_request_is_active(rq))
> > - return;
> > -
> > - if (rq->context == hung_ctx) {
> > - i915_request_set_error_once(rq, -EIO);
> > - __i915_request_skip(rq);
> > - }
> > - }
> > -}
> > -
> > static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
> > {
> > struct drm_i915_file_private *file_priv = ctx->file_priv;
> > @@ -88,10 +72,8 @@ static bool mark_guilty(struct i915_request *rq)
> > bool banned;
> > int i;
> > - if (intel_context_is_closed(rq->context)) {
> > - intel_context_set_banned(rq->context);
> > + if (intel_context_is_closed(rq->context))
> > return true;
> > - }
> > rcu_read_lock();
> > ctx = rcu_dereference(rq->context->gem_context);
> > @@ -123,11 +105,9 @@ static bool ma
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/fdi: refactor some fdi code out of intel_display.c
== Series Details == Series: drm/i915/fdi: refactor some fdi code out of intel_display.c URL : https://patchwork.freedesktop.org/series/94026/ State : success == Summary == CI Bug Log - changes from CI_DRM_10520_full -> Patchwork_20894_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20894_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@psr2: - shard-iclb: [PASS][1] -> [SKIP][2] ([i915#658]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-iclb2/igt@feature_discov...@psr2.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-iclb6/igt@feature_discov...@psr2.html * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-snb6/igt@gem_cre...@create-massive.html - shard-kbl: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-kbl3/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-apl: NOTRUN -> [DMESG-WARN][5] ([i915#180]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-apl7/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +6 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: NOTRUN -> [FAIL][7] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-kbl4/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-kbl6/igt@gem_exec_fair@basic-p...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-kbl2/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_mmap_gtt@cpuset-big-copy-odd: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#1888] / [i915#307]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-skl6/igt@gem_mmap_...@cpuset-big-copy-odd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-skl2/igt@gem_mmap_...@cpuset-big-copy-odd.html * igt@gem_mmap_gtt@cpuset-big-copy-xy: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2428]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-iclb4/igt@gem_mmap_...@cpuset-big-copy-xy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-iclb2/igt@gem_mmap_...@cpuset-big-copy-xy.html * igt@gem_render_copy@yf-tiled-to-vebox-linear: - shard-iclb: NOTRUN -> [SKIP][15] ([i915#768]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-iclb4/igt@gem_render_c...@yf-tiled-to-vebox-linear.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3323]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-apl1/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy@fixed: - shard-iclb: NOTRUN -> [SKIP][17] ([i915#3922]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-iclb4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-b...@fixed.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][18] ([i915#2724]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-snb2/igt@gem_userptr_bl...@vma-merge.html - shard-apl: NOTRUN -> [FAIL][19] ([i915#3318]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-apl2/igt@gem_userptr_bl...@vma-merge.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#1436] / [i915#716]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-skl9/igt@gen9_exec_pa...@allowed-single.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-skl9/igt@gen9_exec_pa...@allowed-single.html * igt@i915_query@query-topology-known-pci-ids: - shard-iclb: NOTRUN -> [SKIP][22] ([fdo#109303]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/shard-iclb4/igt@i915_qu...@query-topology-known-pci-ids.html * igt@kms_big_fb@x-tiled-max-hw-stride-64
[Intel-gfx] [PATCH] drm/i915: Ensure wa_init_finish() is called for ctx workaround list
A recent restructuring of our context workaround list initialization
added an early return for non-render engines; this caused us to
potentially miss the wa_init_finish() call at the end of the function.
The mistake is pretty harmless --- the only impact is that non-render
engines on graphics version 12.50+ platforms we don't trim down the
workaround list to reclaim some memory, and we don't print the usual
"Initialized 1 context workaround" message in dmesg. Let's change the
early return to a jump down to the wa_init_finish() call at the bottom
of the function.
Reported-by: Tvrtko Ursulin
Fixes: 9e9dfd080201 ("drm/i915/dg2: Maintain backward-compatible nested batch
behavior")
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 688ed04edbf6..94e1937f8d29 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -689,7 +689,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
fakewa_disable_nestedbb_mode(engine, wal);
if (engine->class != RENDER_CLASS)
- return;
+ goto done;
if (IS_DG1(i915))
dg1_ctx_workarounds_init(engine, wal);
@@ -720,6 +720,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
else
MISSING_CASE(GRAPHICS_VER(i915));
+done:
wa_init_finish(wal);
}
--
2.25.4
[Intel-gfx] [PATCH 23/27] drm/i915/guc: Move GuC priority fields in context under guc_active
Move GuC management fields in context under guc_active struct as this is
where the lock that protects theses fields lives. Also only set guc_prio
field once during context init.
v2:
(Daniele)
- set CONTEXT_SET_INIT
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 12 ++--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 69 +++
drivers/gpu/drm/i915/i915_trace.h | 2 +-
3 files changed, 46 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 3a5d98e908f4..b56960a781da 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -112,6 +112,7 @@ struct intel_context {
#define CONTEXT_FORCE_SINGLE_SUBMISSION7
#define CONTEXT_NOPREEMPT 8
#define CONTEXT_LRCA_DIRTY 9
+#define CONTEXT_GUC_INIT 10
struct {
u64 timeout_us;
@@ -178,6 +179,11 @@ struct intel_context {
spinlock_t lock;
/** requests: active requests on this context */
struct list_head requests;
+ /*
+* GuC priority management
+*/
+ u8 prio;
+ u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
} guc_active;
/* GuC LRC descriptor ID */
@@ -191,12 +197,6 @@ struct intel_context {
*/
struct list_head guc_id_link;
- /*
-* GuC priority management
-*/
- u8 guc_prio;
- u32 guc_prio_count[GUC_CLIENT_PRIORITY_NUM];
-
#ifdef CONFIG_DRM_I915_SELFTEST
/**
* @drop_schedule_enable: Force drop of schedule enable G2H for selftest
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 14a512533c39..bc68c0122be4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1367,8 +1367,6 @@ static void guc_context_policy_init(struct
intel_engine_cs *engine,
desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
}
-static inline u8 map_i915_prio_to_guc_prio(int prio);
-
static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
{
struct intel_engine_cs *engine = ce->engine;
@@ -1376,8 +1374,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
struct intel_guc *guc = &engine->gt->uc.guc;
u32 desc_idx = ce->guc_id;
struct guc_lrc_desc *desc;
- const struct i915_gem_context *ctx;
- int prio = I915_CONTEXT_DEFAULT_PRIORITY;
bool context_registered;
intel_wakeref_t wakeref;
int ret = 0;
@@ -1394,12 +1390,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
context_registered = lrc_desc_registered(guc, desc_idx);
- rcu_read_lock();
- ctx = rcu_dereference(ce->gem_context);
- if (ctx)
- prio = ctx->sched.priority;
- rcu_read_unlock();
-
reset_lrc_desc(guc, desc_idx);
set_lrc_desc_registered(guc, desc_idx, ce);
@@ -1408,8 +1398,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
desc->engine_submit_mask = adjust_engine_mask(engine->class,
engine->mask);
desc->hw_context_desc = ce->lrc.lrca;
- ce->guc_prio = map_i915_prio_to_guc_prio(prio);
- desc->priority = ce->guc_prio;
+ desc->priority = ce->guc_active.prio;
desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
guc_context_policy_init(engine, desc);
@@ -1805,10 +1794,10 @@ static inline void guc_lrc_desc_unpin(struct
intel_context *ce)
static void __guc_context_destroy(struct intel_context *ce)
{
- GEM_BUG_ON(ce->guc_prio_count[GUC_CLIENT_PRIORITY_KMD_HIGH] ||
- ce->guc_prio_count[GUC_CLIENT_PRIORITY_HIGH] ||
- ce->guc_prio_count[GUC_CLIENT_PRIORITY_KMD_NORMAL] ||
- ce->guc_prio_count[GUC_CLIENT_PRIORITY_NORMAL]);
+ GEM_BUG_ON(ce->guc_active.prio_count[GUC_CLIENT_PRIORITY_KMD_HIGH] ||
+ ce->guc_active.prio_count[GUC_CLIENT_PRIORITY_HIGH] ||
+ ce->guc_active.prio_count[GUC_CLIENT_PRIORITY_KMD_NORMAL] ||
+ ce->guc_active.prio_count[GUC_CLIENT_PRIORITY_NORMAL]);
GEM_BUG_ON(ce->guc_state.number_committed_requests);
lrc_fini(ce);
@@ -1918,14 +1907,17 @@ static void guc_context_set_prio(struct intel_guc *guc,
GEM_BUG_ON(prio < GUC_CLIENT_PRIORITY_KMD_HIGH ||
prio > GUC_CLIENT_PRIORITY_NORMAL);
+ lockdep_assert_held(&ce->guc_active.lock);
- if (ce->guc_prio == prio || submission_disabled(guc) ||
- !context_registered(ce))
+ if (ce->guc_active.prio == prio || submission_disabled(guc) ||
+ !context_regis
[Intel-gfx] [PATCH 26/27] drm/i915/guc: Add GuC kernel doc
Add GuC kernel doc for all structures added thus far for GuC submission
and update the main GuC submission section with the new interface
details.
v2:
- Drop guc_active.lock DOC
v3:
(Daniele)
- Fixup a few kernel doc comments
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 44 +---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 19 +++-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 101 ++
drivers/gpu/drm/i915/i915_request.h | 18 ++--
4 files changed, 132 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 5285d660eacf..920ed92f4382 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -156,40 +156,52 @@ struct intel_context {
u8 wa_bb_page; /* if set, page num reserved for context workarounds */
struct {
- /** lock: protects everything in guc_state */
+ /** @lock: protects everything in guc_state */
spinlock_t lock;
/**
-* sched_state: scheduling state of this context using GuC
+* @sched_state: scheduling state of this context using GuC
* submission
*/
u32 sched_state;
/*
-* fences: maintains of list of requests that have a submit
-* fence related to GuC submission
+* @fences: maintains a list of requests are currently being
+* fenced until a GuC operation completes
*/
struct list_head fences;
- /* GuC context blocked fence */
+ /**
+* @blocked: fence used to signal when the blocking of a
+* contexts submissions is complete.
+*/
struct i915_sw_fence blocked;
- /* GuC committed requests */
+ /** @number_committed_requests: number of committed requests */
int number_committed_requests;
- /** requests: active requests on this context */
+ /** @requests: list of active requests on this context */
struct list_head requests;
- /*
-* GuC priority management
-*/
+ /** @prio: the contexts current guc priority */
u8 prio;
+ /**
+* @prio_count: a counter of the number requests inflight in
+* each priority bucket
+*/
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
} guc_state;
struct {
- /* GuC LRC descriptor ID */
+ /**
+* @id: unique handle which is used to communicate information
+* with the GuC about this context, protected by
+* guc->contexts_lock
+*/
u16 id;
-
- /* GuC LRC descriptor reference count */
+ /**
+* @ref: the number of references to the guc_id, when
+* transitioning in and out of zero protected by
+* guc->contexts_lock
+*/
atomic_t ref;
-
- /*
-* GuC ID link - in list when unpinned but guc_id still valid
in GuC
+ /**
+* @link: in guc->guc_id_list when the guc_id has no refs but is
+* still valid, protected by guc->contexts_lock
*/
struct list_head link;
} guc_id;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 2e27fe59786b..112dd29a63fe 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -41,6 +41,10 @@ struct intel_guc {
spinlock_t irq_lock;
unsigned int msg_enabled_mask;
+ /**
+* @outstanding_submission_g2h: number of outstanding G2H related to GuC
+* submission, used to determine if the GT is idle
+*/
atomic_t outstanding_submission_g2h;
struct {
@@ -49,12 +53,16 @@ struct intel_guc {
void (*disable)(struct intel_guc *guc);
} interrupts;
- /*
-* contexts_lock protects the pool of free guc ids and a linked list of
-* guc ids available to be stolen
+ /**
+* @contexts_lock: protects guc_ids, guc_id_list, ce->guc_id.id, and
+* ce->guc_id.ref when transitioning in and out of zero
*/
spinlock_t contexts_lock;
+ /** @guc_ids: used to allocate new guc_ids */
struct ida guc_ids;
+ /**
+* @guc_id_list: list of intel_context with valid guc_ids but no refs
+*/
struct list_head guc_id_list;
bool submission_supported;
@@ -70,7 +78,10 @@ struct intel
[Intel-gfx] [PATCH 21/27] drm/i915/guc: Proper xarray usage for contexts_lookup
Lock the xarray and take ref to the context if needed.
v2:
(Checkpatch)
- Add new line after declaration
(Daniel Vetter)
- Correct put / get accounting in xa_for_loops
v3:
(Checkpatch)
- Extra new line
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 102 +++---
1 file changed, 87 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 2aa25cc4ac4b..2c6a6453d332 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -606,8 +606,18 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
intel_guc *guc)
unsigned long index, flags;
bool pending_disable, pending_enable, deregister, destroyed, banned;
+ xa_lock_irqsave(&guc->context_lookup, flags);
xa_for_each(&guc->context_lookup, index, ce) {
- spin_lock_irqsave(&ce->guc_state.lock, flags);
+ /*
+* Corner case where the ref count on the object is zero but and
+* deregister G2H was lost. In this case we don't touch the ref
+* count and finish the destroy of the context.
+*/
+ bool do_put = kref_get_unless_zero(&ce->ref);
+
+ xa_unlock(&guc->context_lookup);
+
+ spin_lock(&ce->guc_state.lock);
/*
* Once we are at this point submission_disabled() is guaranteed
@@ -623,7 +633,9 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
intel_guc *guc)
banned = context_banned(ce);
init_sched_state(ce);
- spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+ spin_unlock(&ce->guc_state.lock);
+
+ GEM_BUG_ON(!do_put && !destroyed);
if (pending_enable || destroyed || deregister) {
decr_outstanding_submission_g2h(guc);
@@ -646,13 +658,19 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
intel_guc *guc)
}
intel_context_sched_disable_unpin(ce);
decr_outstanding_submission_g2h(guc);
- spin_lock_irqsave(&ce->guc_state.lock, flags);
+
+ spin_lock(&ce->guc_state.lock);
guc_blocked_fence_complete(ce);
- spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+ spin_unlock(&ce->guc_state.lock);
intel_context_put(ce);
}
+
+ if (do_put)
+ intel_context_put(ce);
+ xa_lock(&guc->context_lookup);
}
+ xa_unlock_irqrestore(&guc->context_lookup, flags);
}
static inline bool
@@ -871,16 +889,29 @@ void intel_guc_submission_reset(struct intel_guc *guc,
bool stalled)
{
struct intel_context *ce;
unsigned long index;
+ unsigned long flags;
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
return;
}
- xa_for_each(&guc->context_lookup, index, ce)
+ xa_lock_irqsave(&guc->context_lookup, flags);
+ xa_for_each(&guc->context_lookup, index, ce) {
+ if (!kref_get_unless_zero(&ce->ref))
+ continue;
+
+ xa_unlock(&guc->context_lookup);
+
if (intel_context_is_pinned(ce))
__guc_reset_context(ce, stalled);
+ intel_context_put(ce);
+
+ xa_lock(&guc->context_lookup);
+ }
+ xa_unlock_irqrestore(&guc->context_lookup, flags);
+
/* GuC is blown away, drop all references to contexts */
xa_destroy(&guc->context_lookup);
}
@@ -955,11 +986,24 @@ void intel_guc_submission_cancel_requests(struct
intel_guc *guc)
{
struct intel_context *ce;
unsigned long index;
+ unsigned long flags;
+
+ xa_lock_irqsave(&guc->context_lookup, flags);
+ xa_for_each(&guc->context_lookup, index, ce) {
+ if (!kref_get_unless_zero(&ce->ref))
+ continue;
+
+ xa_unlock(&guc->context_lookup);
- xa_for_each(&guc->context_lookup, index, ce)
if (intel_context_is_pinned(ce))
guc_cancel_context_requests(ce);
+ intel_context_put(ce);
+
+ xa_lock(&guc->context_lookup);
+ }
+ xa_unlock_irqrestore(&guc->context_lookup, flags);
+
guc_cancel_sched_engine_requests(guc->sched_engine);
/* GuC is blown away, drop all references to contexts */
@@ -2849,21 +2893,28 @@ void intel_guc_find_hung_context(struct intel_engine_cs
*engine)
struct intel_context *ce;
struct i915_request *rq;
u
[Intel-gfx] [PATCH 20/27] drm/i915/guc: Rework and simplify locking
Rework and simplify the locking with GuC subission. Drop
sched_state_no_lock and move all fields under the guc_state.sched_state
and protect all these fields with guc_state.lock . This requires
changing the locking hierarchy from guc_state.lock -> sched_engine.lock
to sched_engine.lock -> guc_state.lock.
v2:
(Daniele)
- Don't check fields outside of lock during sched disable, check less
fields within lock as some of the outside are no longer needed
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 5 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 200 --
drivers/gpu/drm/i915/i915_trace.h | 6 +-
3 files changed, 89 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 5aecb9038b5b..d2f798ef678c 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -161,7 +161,7 @@ struct intel_context {
* sched_state: scheduling state of this context using GuC
* submission
*/
- u16 sched_state;
+ u32 sched_state;
/*
* fences: maintains of list of requests that have a submit
* fence related to GuC submission
@@ -178,9 +178,6 @@ struct intel_context {
struct list_head requests;
} guc_active;
- /* GuC scheduling state flags that do not require a lock. */
- atomic_t guc_sched_state_no_lock;
-
/* GuC LRC descriptor ID */
u16 guc_id;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 9d1eadd4b7c4..2aa25cc4ac4b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -72,87 +72,24 @@ guc_create_virtual(struct intel_engine_cs **siblings,
unsigned int count);
#define GUC_REQUEST_SIZE 64 /* bytes */
-/*
- * Below is a set of functions which control the GuC scheduling state which do
- * not require a lock as all state transitions are mutually exclusive. i.e. It
- * is not possible for the context pinning code and submission, for the same
- * context, to be executing simultaneously. We still need an atomic as it is
- * possible for some of the bits to changing at the same time though.
- */
-#define SCHED_STATE_NO_LOCK_ENABLEDBIT(0)
-#define SCHED_STATE_NO_LOCK_PENDING_ENABLE BIT(1)
-#define SCHED_STATE_NO_LOCK_REGISTERED BIT(2)
-static inline bool context_enabled(struct intel_context *ce)
-{
- return (atomic_read(&ce->guc_sched_state_no_lock) &
- SCHED_STATE_NO_LOCK_ENABLED);
-}
-
-static inline void set_context_enabled(struct intel_context *ce)
-{
- atomic_or(SCHED_STATE_NO_LOCK_ENABLED, &ce->guc_sched_state_no_lock);
-}
-
-static inline void clr_context_enabled(struct intel_context *ce)
-{
- atomic_and((u32)~SCHED_STATE_NO_LOCK_ENABLED,
- &ce->guc_sched_state_no_lock);
-}
-
-static inline bool context_pending_enable(struct intel_context *ce)
-{
- return (atomic_read(&ce->guc_sched_state_no_lock) &
- SCHED_STATE_NO_LOCK_PENDING_ENABLE);
-}
-
-static inline void set_context_pending_enable(struct intel_context *ce)
-{
- atomic_or(SCHED_STATE_NO_LOCK_PENDING_ENABLE,
- &ce->guc_sched_state_no_lock);
-}
-
-static inline void clr_context_pending_enable(struct intel_context *ce)
-{
- atomic_and((u32)~SCHED_STATE_NO_LOCK_PENDING_ENABLE,
- &ce->guc_sched_state_no_lock);
-}
-
-static inline bool context_registered(struct intel_context *ce)
-{
- return (atomic_read(&ce->guc_sched_state_no_lock) &
- SCHED_STATE_NO_LOCK_REGISTERED);
-}
-
-static inline void set_context_registered(struct intel_context *ce)
-{
- atomic_or(SCHED_STATE_NO_LOCK_REGISTERED,
- &ce->guc_sched_state_no_lock);
-}
-
-static inline void clr_context_registered(struct intel_context *ce)
-{
- atomic_and((u32)~SCHED_STATE_NO_LOCK_REGISTERED,
- &ce->guc_sched_state_no_lock);
-}
-
/*
* Below is a set of functions which control the GuC scheduling state which
- * require a lock, aside from the special case where the functions are called
- * from guc_lrc_desc_pin(). In that case it isn't possible for any other code
- * path to be executing on the context.
+ * require a lock.
*/
#define SCHED_STATE_WAIT_FOR_DEREGISTER_TO_REGISTERBIT(0)
#define SCHED_STATE_DESTROYED BIT(1)
#define SCHED_STATE_PENDING_DISABLEBIT(2)
#define SCHED_STATE_BANNED BIT(3)
-#define SCHED_STATE_BLOCKED_SHIFT 4
+#define SCHED_STATE_ENABLEDBIT(4)
+#define SCHED_STATE_PENDING_
[Intel-gfx] [PATCH 24/27] drm/i915/guc: Move fields protected by guc->contexts_lock into sub structure
To make ownership of locking clear move fields (guc_id, guc_id_ref,
guc_id_link) to sub structure guc_id in intel_context.
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
drivers/gpu/drm/i915/gt/intel_context_types.h | 18 +--
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 6 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 104 +-
drivers/gpu/drm/i915/i915_trace.h | 4 +-
5 files changed, 69 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 3048267ddc7e..485460a11331 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -398,8 +398,8 @@ intel_context_init(struct intel_context *ce, struct
intel_engine_cs *engine)
spin_lock_init(&ce->guc_active.lock);
INIT_LIST_HEAD(&ce->guc_active.requests);
- ce->guc_id = GUC_INVALID_LRC_ID;
- INIT_LIST_HEAD(&ce->guc_id_link);
+ ce->guc_id.id = GUC_INVALID_LRC_ID;
+ INIT_LIST_HEAD(&ce->guc_id.link);
/*
* Initialize fence to be complete as this is expected to be complete
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index b56960a781da..0b00d249c884 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -186,16 +186,18 @@ struct intel_context {
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
} guc_active;
- /* GuC LRC descriptor ID */
- u16 guc_id;
+ struct {
+ /* GuC LRC descriptor ID */
+ u16 id;
- /* GuC LRC descriptor reference count */
- atomic_t guc_id_ref;
+ /* GuC LRC descriptor reference count */
+ atomic_t ref;
- /*
-* GuC ID link - in list when unpinned but guc_id still valid in GuC
-*/
- struct list_head guc_id_link;
+ /*
+* GuC ID link - in list when unpinned but guc_id still valid
in GuC
+*/
+ struct list_head link;
+ } guc_id;
#ifdef CONFIG_DRM_I915_SELFTEST
/**
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 2c1ed32ca5ac..e9130fa39616 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -789,7 +789,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool
active)
if (err)
pr_err("[%s] Wait for request %lld:%lld
[0x%04X] failed: %d!\n",
engine->name, rq->fence.context,
- rq->fence.seqno,
rq->context->guc_id, err);
+ rq->fence.seqno,
rq->context->guc_id.id, err);
}
skip:
@@ -1098,7 +1098,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
if (err)
pr_err("[%s] Wait for request %lld:%lld
[0x%04X] failed: %d!\n",
engine->name, rq->fence.context,
- rq->fence.seqno,
rq->context->guc_id, err);
+ rq->fence.seqno,
rq->context->guc_id.id, err);
}
count++;
@@ -1108,7 +1108,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
pr_err("i915_reset_engine(%s:%s):
failed to reset request %lld:%lld [0x%04X]\n",
engine->name, test_name,
rq->fence.context,
- rq->fence.seqno,
rq->context->guc_id);
+ rq->fence.seqno,
rq->context->guc_id.id);
i915_request_put(rq);
GEM_TRACE_DUMP();
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index bc68c0122be4..044f9dda1397 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -270,12 +270,12 @@ static inline void decr_context_committed_requests(struct
intel_context *ce)
static inline bool context_guc_id_invalid(struct intel_context *ce)
{
- return ce->guc_id == GUC_INVALID_LRC_ID;
+ return ce->guc_id.id == GUC_INVALID_LRC_ID;
}
static inline void set_context_guc_id_invalid(struct intel_context *ce)
{
- ce->guc_id = GUC_INVALID_LRC_ID;
+ ce->guc_id.id = GUC_INVALID_LRC_ID;
}
static inline struct intel_guc *ce_t
[Intel-gfx] [PATCH 11/27] drm/i915/guc: Copy whole golden context, set engine state size of subset
When the GuC does a media reset, it copies a golden context state back
into the corrupted context's state. The address of the golden context
and the size of the engine state restore are passed in via the GuC ADS.
The i915 had a bug where it passed in the whole size of the golden
context, not the size of the engine state to restore resulting in a
memory corruption.
Also copy the entire golden context on init rather than just the engine
state that is restored.
Fixes: 481d458caede ("drm/i915/guc: Add golden context to GuC ADS")
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 28 +-
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 6926919bcac6..df2734bfe078 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -358,6 +358,11 @@ static int guc_prep_golden_context(struct intel_guc *guc,
u8 engine_class, guc_class;
struct guc_gt_system_info *info, local_info;
+ /* Skip execlist and PPGTT registers + HWSP */
+ const u32 lr_hw_context_size = 80 * sizeof(u32);
+ const u32 skip_size = LRC_PPHWSP_SZ * PAGE_SIZE +
+ lr_hw_context_size;
+
/*
* Reserve the memory for the golden contexts and point GuC at it but
* leave it empty for now. The context data will be filled in later
@@ -396,7 +401,18 @@ static int guc_prep_golden_context(struct intel_guc *guc,
if (!blob)
continue;
- blob->ads.eng_state_size[guc_class] = real_size;
+ /*
+* This interface is slightly confusing. We need to pass the
+* base address of the golden context and the engine state size
+* which is not the size of the whole golden context, it is a
+* subset that the GuC uses when doing a watchdog reset. The
+* engine state size must match the size of the golden context
+* minus the first part of the golden context that the GuC does
+* not retore during reset. Currently no real way to verify this
+* other than reading the GuC spec / code and ensuring the
+* 'skip_size' below matches the value used in the GuC code.
+*/
+ blob->ads.eng_state_size[guc_class] = real_size - skip_size;
blob->ads.golden_context_lrca[guc_class] = addr_ggtt;
addr_ggtt += alloc_size;
}
@@ -437,8 +453,8 @@ static void guc_init_golden_context(struct intel_guc *guc)
u8 *ptr;
/* Skip execlist and PPGTT registers + HWSP */
- const u32 lr_hw_context_size = 80 * sizeof(u32);
- const u32 skip_size = LRC_PPHWSP_SZ * PAGE_SIZE +
+ __maybe_unused const u32 lr_hw_context_size = 80 * sizeof(u32);
+ __maybe_unused const u32 skip_size = LRC_PPHWSP_SZ * PAGE_SIZE +
lr_hw_context_size;
if (!intel_uc_uses_guc_submission(>->uc))
@@ -476,12 +492,12 @@ static void guc_init_golden_context(struct intel_guc *guc)
continue;
}
- GEM_BUG_ON(blob->ads.eng_state_size[guc_class] != real_size);
+ GEM_BUG_ON(blob->ads.eng_state_size[guc_class] !=
+ real_size - skip_size);
GEM_BUG_ON(blob->ads.golden_context_lrca[guc_class] !=
addr_ggtt);
addr_ggtt += alloc_size;
- shmem_read(engine->default_state, skip_size, ptr + skip_size,
- real_size - skip_size);
+ shmem_read(engine->default_state, 0, ptr, real_size);
ptr += alloc_size;
}
--
2.32.0
[Intel-gfx] [PATCH 05/27] drm/i915/guc: Process all G2H message at once in work queue
Rather than processing 1 G2H at a time and re-queuing the work queue if
more messages exist, process all the G2H in a single pass of the work
queue.
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
Cc: Daniel Vetter
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 22b4733b55e2..20c710a74498 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -1042,9 +1042,9 @@ static void ct_incoming_request_worker_func(struct
work_struct *w)
container_of(w, struct intel_guc_ct, requests.worker);
bool done;
- done = ct_process_incoming_requests(ct);
- if (!done)
- queue_work(system_unbound_wq, &ct->requests.worker);
+ do {
+ done = ct_process_incoming_requests(ct);
+ } while (!done);
}
static int ct_handle_event(struct intel_guc_ct *ct, struct ct_incoming_msg
*request)
--
2.32.0
[Intel-gfx] [PATCH 22/27] drm/i915/guc: Drop pin count check trick between sched_disable and re-pin
Drop pin count check trick between a sched_disable and re-pin, now rely
on the lock and counter of the number of committed requests to determine
if scheduling should be disabled on the context.
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 2 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 53 +++
2 files changed, 34 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index d2f798ef678c..3a5d98e908f4 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -169,6 +169,8 @@ struct intel_context {
struct list_head fences;
/* GuC context blocked fence */
struct i915_sw_fence blocked;
+ /* GuC committed requests */
+ int number_committed_requests;
} guc_state;
struct {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 2c6a6453d332..14a512533c39 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -249,6 +249,25 @@ static inline void decr_context_blocked(struct
intel_context *ce)
ce->guc_state.sched_state -= SCHED_STATE_BLOCKED;
}
+static inline bool context_has_committed_requests(struct intel_context *ce)
+{
+ return !!ce->guc_state.number_committed_requests;
+}
+
+static inline void incr_context_committed_requests(struct intel_context *ce)
+{
+ lockdep_assert_held(&ce->guc_state.lock);
+ ++ce->guc_state.number_committed_requests;
+ GEM_BUG_ON(ce->guc_state.number_committed_requests < 0);
+}
+
+static inline void decr_context_committed_requests(struct intel_context *ce)
+{
+ lockdep_assert_held(&ce->guc_state.lock);
+ --ce->guc_state.number_committed_requests;
+ GEM_BUG_ON(ce->guc_state.number_committed_requests < 0);
+}
+
static inline bool context_guc_id_invalid(struct intel_context *ce)
{
return ce->guc_id == GUC_INVALID_LRC_ID;
@@ -1749,24 +1768,18 @@ static void guc_context_sched_disable(struct
intel_context *ce)
spin_lock_irqsave(&ce->guc_state.lock, flags);
/*
-* We have to check if the context has been disabled by another thread.
-* We also have to check if the context has been pinned again as another
-* pin operation is allowed to pass this function. Checking the pin
-* count, within ce->guc_state.lock, synchronizes this function with
-* guc_request_alloc ensuring a request doesn't slip through the
-* 'context_pending_disable' fence. Checking within the spin lock (can't
-* sleep) ensures another process doesn't pin this context and generate
-* a request before we set the 'context_pending_disable' flag here.
+* We have to check if the context has been disabled by another thread,
+* check if submssion has been disabled to seal a race with reset and
+* finally check if any more requests have been committed to the
+* context ensursing that a request doesn't slip through the
+* 'context_pending_disable' fence.
*/
- if (unlikely(!context_enabled(ce) || submission_disabled(guc))) {
+ if (unlikely(!context_enabled(ce) || submission_disabled(guc) ||
+context_has_committed_requests(ce))) {
clr_context_enabled(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
goto unpin;
}
- if (unlikely(atomic_add_unless(&ce->pin_count, -2, 2))) {
- spin_unlock_irqrestore(&ce->guc_state.lock, flags);
- return;
- }
guc_id = prep_context_pending_disable(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
@@ -1796,6 +1809,7 @@ static void __guc_context_destroy(struct intel_context
*ce)
ce->guc_prio_count[GUC_CLIENT_PRIORITY_HIGH] ||
ce->guc_prio_count[GUC_CLIENT_PRIORITY_KMD_NORMAL] ||
ce->guc_prio_count[GUC_CLIENT_PRIORITY_NORMAL]);
+ GEM_BUG_ON(ce->guc_state.number_committed_requests);
lrc_fini(ce);
intel_context_fini(ce);
@@ -2026,6 +2040,10 @@ static void remove_from_context(struct i915_request *rq)
spin_unlock_irq(&ce->guc_active.lock);
+ spin_lock_irq(&ce->guc_state.lock);
+ decr_context_committed_requests(ce);
+ spin_unlock_irq(&ce->guc_state.lock);
+
atomic_dec(&ce->guc_id_ref);
i915_request_notify_execute_cb_imm(rq);
}
@@ -2176,15 +2194,7 @@ static int guc_request_alloc(struct i915_request *rq)
* schedule enable or context registration if either G2H is pending
* respectfully. Once a G2H returns, the fence is released that is
* blocking these requests (see g
[Intel-gfx] [PATCH 10/27] drm/i915/guc: Don't enable scheduling on a banned context, guc_id invalid, not registered
When unblocking a context, do not enable scheduling if the context is
banned, guc_id invalid, or not registered.
v2:
(Daniele)
- Add helper for unblock
Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
Cc:
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 22 ---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b30fdccc71d4..56f11accd6cc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -148,6 +148,7 @@ static inline void clr_context_registered(struct
intel_context *ce)
#define SCHED_STATE_BLOCKED_SHIFT 4
#define SCHED_STATE_BLOCKEDBIT(SCHED_STATE_BLOCKED_SHIFT)
#define SCHED_STATE_BLOCKED_MASK (0xfff << SCHED_STATE_BLOCKED_SHIFT)
+
static inline void init_sched_state(struct intel_context *ce)
{
/* Only should be called from guc_lrc_desc_pin() */
@@ -1569,6 +1570,23 @@ static struct i915_sw_fence *guc_context_block(struct
intel_context *ce)
return &ce->guc_blocked;
}
+#define SCHED_STATE_MULTI_BLOCKED_MASK \
+ (SCHED_STATE_BLOCKED_MASK & ~SCHED_STATE_BLOCKED)
+#define SCHED_STATE_NO_UNBLOCK \
+ (SCHED_STATE_MULTI_BLOCKED_MASK | \
+SCHED_STATE_PENDING_DISABLE | \
+SCHED_STATE_BANNED)
+
+static bool context_cant_unblock(struct intel_context *ce)
+{
+ lockdep_assert_held(&ce->guc_state.lock);
+
+ return (ce->guc_state.sched_state & SCHED_STATE_NO_UNBLOCK) ||
+ context_guc_id_invalid(ce) ||
+ !lrc_desc_registered(ce_to_guc(ce), ce->guc_id) ||
+ !intel_context_is_pinned(ce);
+}
+
static void guc_context_unblock(struct intel_context *ce)
{
struct intel_guc *guc = ce_to_guc(ce);
@@ -1583,9 +1601,7 @@ static void guc_context_unblock(struct intel_context *ce)
spin_lock_irqsave(&ce->guc_state.lock, flags);
if (unlikely(submission_disabled(guc) ||
-!intel_context_is_pinned(ce) ||
-context_pending_disable(ce) ||
-context_blocked(ce) > 1)) {
+context_cant_unblock(ce))) {
enable = false;
} else {
enable = true;
--
2.32.0
[Intel-gfx] [PATCH 18/27] drm/i915/guc: Release submit fence from an irq_work
A subsequent patch will flip the locking hierarchy from
ce->guc_state.lock -> sched_engine->lock to sched_engine->lock ->
ce->guc_state.lock. As such we need to release the submit fence for a
request from an IRQ to break a lock inversion - i.e. the fence must be
release went holding ce->guc_state.lock and the releasing of the can
acquire sched_engine->lock.
v2:
(Daniele)
- Delete request from list before calling irq_work_queue
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 22 ---
drivers/gpu/drm/i915/i915_request.h | 5 +
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index baf789f37d42..c86aae0899e5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2035,17 +2035,32 @@ static const struct intel_context_ops guc_context_ops =
{
.create_virtual = guc_create_virtual,
};
+static void submit_work_cb(struct irq_work *wrk)
+{
+ struct i915_request *rq = container_of(wrk, typeof(*rq), submit_work);
+
+ might_lock(&rq->engine->sched_engine->lock);
+ i915_sw_fence_complete(&rq->submit);
+}
+
static void __guc_signal_context_fence(struct intel_context *ce)
{
- struct i915_request *rq;
+ struct i915_request *rq, *rn;
lockdep_assert_held(&ce->guc_state.lock);
if (!list_empty(&ce->guc_state.fences))
trace_intel_context_fence_release(ce);
- list_for_each_entry(rq, &ce->guc_state.fences, guc_fence_link)
- i915_sw_fence_complete(&rq->submit);
+ /*
+* Use an IRQ to ensure locking order of sched_engine->lock ->
+* ce->guc_state.lock is preserved.
+*/
+ list_for_each_entry_safe(rq, rn, &ce->guc_state.fences,
+guc_fence_link) {
+ list_del(&rq->guc_fence_link);
+ irq_work_queue(&rq->submit_work);
+ }
INIT_LIST_HEAD(&ce->guc_state.fences);
}
@@ -2155,6 +2170,7 @@ static int guc_request_alloc(struct i915_request *rq)
spin_lock_irqsave(&ce->guc_state.lock, flags);
if (context_wait_for_deregister_to_register(ce) ||
context_pending_disable(ce)) {
+ init_irq_work(&rq->submit_work, submit_work_cb);
i915_sw_fence_await(&rq->submit);
list_add_tail(&rq->guc_fence_link, &ce->guc_state.fences);
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index 1bc1349ba3c2..d818cfbfc41d 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -218,6 +218,11 @@ struct i915_request {
};
struct llist_head execute_cb;
struct i915_sw_fence semaphore;
+ /**
+* @submit_work: complete submit fence from an IRQ if needed for
+* locking hierarchy reasons.
+*/
+ struct irq_work submit_work;
/*
* A list of everyone we wait upon, and everyone who waits upon us.
--
2.32.0
[Intel-gfx] [PATCH 13/27] drm/i915/guc: Take context ref when cancelling request
A context can get destroyed after cancelling a request, if a context or
GT reset occurs, so take a reference to context when cancelling a
request.
Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 5844bb954922..1cb97e98871c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1630,8 +1630,10 @@ static void guc_context_cancel_request(struct
intel_context *ce,
struct i915_request *rq)
{
if (i915_sw_fence_signaled(&rq->submit)) {
- struct i915_sw_fence *fence = guc_context_block(ce);
+ struct i915_sw_fence *fence;
+ intel_context_get(ce);
+ fence = guc_context_block(ce);
i915_sw_fence_wait(fence);
if (!i915_request_completed(rq)) {
__i915_request_skip(rq);
@@ -1646,6 +1648,7 @@ static void guc_context_cancel_request(struct
intel_context *ce,
flush_work(&ce_to_guc(ce)->ct.requests.worker);
guc_context_unblock(ce);
+ intel_context_put(ce);
}
}
--
2.32.0
[Intel-gfx] [PATCH 17/27] drm/i915/guc: Flush G2H work queue during reset
It isn't safe to scrub for missing G2H or continue with the reset until
all G2H processing is complete. Flush the G2H work queue during reset to
ensure it is done running. No need to call the IRQ handler directly
either as the scrubbing code can deal with any missing G2H.
Fixes: eb5e7da736f3 ("drm/i915/guc: Reset implementation for new GuC interface")
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 2949dce57489..baf789f37d42 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -714,8 +714,6 @@ static void guc_flush_submissions(struct intel_guc *guc)
void intel_guc_submission_reset_prepare(struct intel_guc *guc)
{
- int i;
-
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
return;
@@ -731,20 +729,8 @@ void intel_guc_submission_reset_prepare(struct intel_guc
*guc)
guc_flush_submissions(guc);
- /*
-* Handle any outstanding G2Hs before reset. Call IRQ handler directly
-* each pass as interrupt have been disabled. We always scrub for
-* outstanding G2H as it is possible for outstanding_submission_g2h to
-* be incremented after the context state update.
-*/
- for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h);
++i) {
- intel_guc_to_host_event_handler(guc);
-#define wait_for_reset(guc, wait_var) \
- intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20))
- do {
- wait_for_reset(guc, &guc->outstanding_submission_g2h);
- } while (!list_empty(&guc->ct.requests.incoming));
- }
+ flush_work(&guc->ct.requests.worker);
+
scrub_guc_desc_for_outstanding_g2h(guc);
}
--
2.32.0
[Intel-gfx] [PATCH 07/27] Revert "drm/i915/gt: Propagate change in error status to children on unhold"
Propagating errors to dependent fences is broken and can lead to
errors from one client ending up in another. In 3761baae908a (Revert
"drm/i915: Propagate errors on awaiting already signaled fences"), we
attempted to get rid of fence error propagation but missed the case
added in 8e9f84cf5cac ("drm/i915/gt: Propagate change in error status
to children on unhold"). Revert that one too. This error was found
by an up-and-coming selftest which triggers a reset during request
cancellation and verifies that subsequent requests complete
successfully.
v2:
(Daniel Vetter)
- Use revert
v3:
(Jason)
- Update commit message
References: '3761baae908a ("Revert "drm/i915: Propagate errors on awaiting
already signaled fences"")'
Signed-off-by: Matthew Brost
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index de5f9c86b9a4..cafb0608ffb4 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2140,10 +2140,6 @@ static void __execlists_unhold(struct i915_request *rq)
if (p->flags & I915_DEPENDENCY_WEAK)
continue;
- /* Propagate any change in error status */
- if (rq->fence.error)
- i915_request_set_error_once(w, rq->fence.error);
-
if (w->engine != rq->engine)
continue;
--
2.32.0
[Intel-gfx] [PATCH 27/27] drm/i915/guc: Drop static inline functions intel_guc_submission.c
s/static inline/static/g + fix function argument alignment to make
checkpatch happy.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 116 +-
1 file changed, 57 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 3fe45eca95ff..f921763eb7a4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -144,7 +144,7 @@ guc_create_virtual(struct intel_engine_cs **siblings,
unsigned int count);
#define SCHED_STATE_BLOCKEDBIT(SCHED_STATE_BLOCKED_SHIFT)
#define SCHED_STATE_BLOCKED_MASK (0xfff << SCHED_STATE_BLOCKED_SHIFT)
-static inline void init_sched_state(struct intel_context *ce)
+static void init_sched_state(struct intel_context *ce)
{
lockdep_assert_held(&ce->guc_state.lock);
ce->guc_state.sched_state &= SCHED_STATE_BLOCKED_MASK;
@@ -161,14 +161,14 @@ static bool sched_state_is_init(struct intel_context *ce)
~(SCHED_STATE_BLOCKED_MASK | SCHED_STATE_REGISTERED));
}
-static inline bool
+static bool
context_wait_for_deregister_to_register(struct intel_context *ce)
{
return ce->guc_state.sched_state &
SCHED_STATE_WAIT_FOR_DEREGISTER_TO_REGISTER;
}
-static inline void
+static void
set_context_wait_for_deregister_to_register(struct intel_context *ce)
{
lockdep_assert_held(&ce->guc_state.lock);
@@ -176,7 +176,7 @@ set_context_wait_for_deregister_to_register(struct
intel_context *ce)
SCHED_STATE_WAIT_FOR_DEREGISTER_TO_REGISTER;
}
-static inline void
+static void
clr_context_wait_for_deregister_to_register(struct intel_context *ce)
{
lockdep_assert_held(&ce->guc_state.lock);
@@ -184,111 +184,111 @@ clr_context_wait_for_deregister_to_register(struct
intel_context *ce)
~SCHED_STATE_WAIT_FOR_DEREGISTER_TO_REGISTER;
}
-static inline bool
+static bool
context_destroyed(struct intel_context *ce)
{
return ce->guc_state.sched_state & SCHED_STATE_DESTROYED;
}
-static inline void
+static void
set_context_destroyed(struct intel_context *ce)
{
lockdep_assert_held(&ce->guc_state.lock);
ce->guc_state.sched_state |= SCHED_STATE_DESTROYED;
}
-static inline bool context_pending_disable(struct intel_context *ce)
+static bool context_pending_disable(struct intel_context *ce)
{
return ce->guc_state.sched_state & SCHED_STATE_PENDING_DISABLE;
}
-static inline void set_context_pending_disable(struct intel_context *ce)
+static void set_context_pending_disable(struct intel_context *ce)
{
lockdep_assert_held(&ce->guc_state.lock);
ce->guc_state.sched_state |= SCHED_STATE_PENDING_DISABLE;
}
-static inline void clr_context_pending_disable(struct intel_context *ce)
+static void clr_context_pending_disable(struct intel_context *ce)
{
lockdep_assert_held(&ce->guc_state.lock);
ce->guc_state.sched_state &= ~SCHED_STATE_PENDING_DISABLE;
}
-static inline bool context_banned(struct intel_context *ce)
+static bool context_banned(struct intel_context *ce)
{
return ce->guc_state.sched_state & SCHED_STATE_BANNED;
}
-static inline void set_context_banned(struct intel_context *ce)
+static void set_context_banned(struct intel_context *ce)
{
lockdep_assert_held(&ce->guc_state.lock);
ce->guc_state.sched_state |= SCHED_STATE_BANNED;
}
-static inline void clr_context_banned(struct intel_context *ce)
+static void clr_context_banned(struct intel_context *ce)
{
lockdep_assert_held(&ce->guc_state.lock);
ce->guc_state.sched_state &= ~SCHED_STATE_BANNED;
}
-static inline bool context_enabled(struct intel_context *ce)
+static bool context_enabled(struct intel_context *ce)
{
return ce->guc_state.sched_state & SCHED_STATE_ENABLED;
}
-static inline void set_context_enabled(struct intel_context *ce)
+static void set_context_enabled(struct intel_context *ce)
{
lockdep_assert_held(&ce->guc_state.lock);
ce->guc_state.sched_state |= SCHED_STATE_ENABLED;
}
-static inline void clr_context_enabled(struct intel_context *ce)
+static void clr_context_enabled(struct intel_context *ce)
{
lockdep_assert_held(&ce->guc_state.lock);
ce->guc_state.sched_state &= ~SCHED_STATE_ENABLED;
}
-static inline bool context_pending_enable(struct intel_context *ce)
+static bool context_pending_enable(struct intel_context *ce)
{
return ce->guc_state.sched_state & SCHED_STATE_PENDING_ENABLE;
}
-static inline void set_context_pending_enable(struct intel_context *ce)
+static void set_context_pending_enable(struct intel_context *ce)
{
lockdep_assert_held(&ce->guc_state.lock);
ce->guc_state.sched_state |= SCHED_STATE_PENDING_ENABLE;
}
-static inline void clr_context_pending_enable(struct intel_context *ce)
+static void clr_context_pen
[Intel-gfx] [PATCH 25/27] drm/i915/guc: Drop guc_active move everything into guc_state
Now that we have locking hierarchy of sched_engine->lock ->
ce->guc_state everything from guc_active can be moved into guc_state and
protected the guc_state.lock.
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_context.c | 10 +--
drivers/gpu/drm/i915/gt/intel_context_types.h | 7 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 88 +--
drivers/gpu/drm/i915/i915_trace.h | 2 +-
4 files changed, 49 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 485460a11331..ff637147b1a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -394,9 +394,7 @@ intel_context_init(struct intel_context *ce, struct
intel_engine_cs *engine)
spin_lock_init(&ce->guc_state.lock);
INIT_LIST_HEAD(&ce->guc_state.fences);
-
- spin_lock_init(&ce->guc_active.lock);
- INIT_LIST_HEAD(&ce->guc_active.requests);
+ INIT_LIST_HEAD(&ce->guc_state.requests);
ce->guc_id.id = GUC_INVALID_LRC_ID;
INIT_LIST_HEAD(&ce->guc_id.link);
@@ -521,15 +519,15 @@ struct i915_request
*intel_context_find_active_request(struct intel_context *ce)
GEM_BUG_ON(!intel_engine_uses_guc(ce->engine));
- spin_lock_irqsave(&ce->guc_active.lock, flags);
- list_for_each_entry_reverse(rq, &ce->guc_active.requests,
+ spin_lock_irqsave(&ce->guc_state.lock, flags);
+ list_for_each_entry_reverse(rq, &ce->guc_state.requests,
sched.link) {
if (i915_request_completed(rq))
break;
active = rq;
}
- spin_unlock_irqrestore(&ce->guc_active.lock, flags);
+ spin_unlock_irqrestore(&ce->guc_state.lock, flags);
return active;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 0b00d249c884..5285d660eacf 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -172,11 +172,6 @@ struct intel_context {
struct i915_sw_fence blocked;
/* GuC committed requests */
int number_committed_requests;
- } guc_state;
-
- struct {
- /** lock: protects everything in guc_active */
- spinlock_t lock;
/** requests: active requests on this context */
struct list_head requests;
/*
@@ -184,7 +179,7 @@ struct intel_context {
*/
u8 prio;
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
- } guc_active;
+ } guc_state;
struct {
/* GuC LRC descriptor ID */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 044f9dda1397..eb884b48f4b8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -827,9 +827,9 @@ __unwind_incomplete_requests(struct intel_context *ce)
unsigned long flags;
spin_lock_irqsave(&sched_engine->lock, flags);
- spin_lock(&ce->guc_active.lock);
+ spin_lock(&ce->guc_state.lock);
list_for_each_entry_safe_reverse(rq, rn,
-&ce->guc_active.requests,
+&ce->guc_state.requests,
sched.link) {
if (i915_request_completed(rq))
continue;
@@ -848,7 +848,7 @@ __unwind_incomplete_requests(struct intel_context *ce)
list_add(&rq->sched.link, pl);
set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
}
- spin_unlock(&ce->guc_active.lock);
+ spin_unlock(&ce->guc_state.lock);
spin_unlock_irqrestore(&sched_engine->lock, flags);
}
@@ -943,10 +943,10 @@ static void guc_cancel_context_requests(struct
intel_context *ce)
/* Mark all executing requests as skipped. */
spin_lock_irqsave(&sched_engine->lock, flags);
- spin_lock(&ce->guc_active.lock);
- list_for_each_entry(rq, &ce->guc_active.requests, sched.link)
+ spin_lock(&ce->guc_state.lock);
+ list_for_each_entry(rq, &ce->guc_state.requests, sched.link)
i915_request_put(i915_request_mark_eio(rq));
- spin_unlock(&ce->guc_active.lock);
+ spin_unlock(&ce->guc_state.lock);
spin_unlock_irqrestore(&sched_engine->lock, flags);
}
@@ -1398,7 +1398,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
desc->engine_submit_mask = adjust_engine_mask(engine->class,
engine->mask);
desc->hw_context_desc = ce->lrc.lrca;
- desc->priority = ce->guc_active.prio;
+ desc->prio
[Intel-gfx] [PATCH 19/27] drm/i915/guc: Move guc_blocked fence to struct guc_state
Move guc_blocked fence to struct guc_state as the lock which protects
the fence lives there.
s/ce->guc_blocked/ce->guc_state.blocked/g
v2:
(Daniele)
- s/blocked_fence/blocked/g
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.c| 5 +++--
drivers/gpu/drm/i915/gt/intel_context_types.h | 5 ++---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +-
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 745e84c72c90..3048267ddc7e 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -405,8 +405,9 @@ intel_context_init(struct intel_context *ce, struct
intel_engine_cs *engine)
* Initialize fence to be complete as this is expected to be complete
* unless there is a pending schedule disable outstanding.
*/
- i915_sw_fence_init(&ce->guc_blocked, sw_fence_dummy_notify);
- i915_sw_fence_commit(&ce->guc_blocked);
+ i915_sw_fence_init(&ce->guc_state.blocked,
+ sw_fence_dummy_notify);
+ i915_sw_fence_commit(&ce->guc_state.blocked);
i915_active_init(&ce->active,
__intel_context_active, __intel_context_retire, 0);
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 3a73f3117873..5aecb9038b5b 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -167,6 +167,8 @@ struct intel_context {
* fence related to GuC submission
*/
struct list_head fences;
+ /* GuC context blocked fence */
+ struct i915_sw_fence blocked;
} guc_state;
struct {
@@ -190,9 +192,6 @@ struct intel_context {
*/
struct list_head guc_id_link;
- /* GuC context blocked fence */
- struct i915_sw_fence guc_blocked;
-
/*
* GuC priority management
*/
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index c86aae0899e5..9d1eadd4b7c4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1488,24 +1488,24 @@ static void guc_blocked_fence_complete(struct
intel_context *ce)
{
lockdep_assert_held(&ce->guc_state.lock);
- if (!i915_sw_fence_done(&ce->guc_blocked))
- i915_sw_fence_complete(&ce->guc_blocked);
+ if (!i915_sw_fence_done(&ce->guc_state.blocked))
+ i915_sw_fence_complete(&ce->guc_state.blocked);
}
static void guc_blocked_fence_reinit(struct intel_context *ce)
{
lockdep_assert_held(&ce->guc_state.lock);
- GEM_BUG_ON(!i915_sw_fence_done(&ce->guc_blocked));
+ GEM_BUG_ON(!i915_sw_fence_done(&ce->guc_state.blocked));
/*
* This fence is always complete unless a pending schedule disable is
* outstanding. We arm the fence here and complete it when we receive
* the pending schedule disable complete message.
*/
- i915_sw_fence_fini(&ce->guc_blocked);
- i915_sw_fence_reinit(&ce->guc_blocked);
- i915_sw_fence_await(&ce->guc_blocked);
- i915_sw_fence_commit(&ce->guc_blocked);
+ i915_sw_fence_fini(&ce->guc_state.blocked);
+ i915_sw_fence_reinit(&ce->guc_state.blocked);
+ i915_sw_fence_await(&ce->guc_state.blocked);
+ i915_sw_fence_commit(&ce->guc_state.blocked);
}
static u16 prep_context_pending_disable(struct intel_context *ce)
@@ -1545,7 +1545,7 @@ static struct i915_sw_fence *guc_context_block(struct
intel_context *ce)
if (enabled)
clr_context_enabled(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
- return &ce->guc_blocked;
+ return &ce->guc_state.blocked;
}
/*
@@ -1561,7 +1561,7 @@ static struct i915_sw_fence *guc_context_block(struct
intel_context *ce)
with_intel_runtime_pm(runtime_pm, wakeref)
__guc_context_sched_disable(guc, ce, guc_id);
- return &ce->guc_blocked;
+ return &ce->guc_state.blocked;
}
#define SCHED_STATE_MULTI_BLOCKED_MASK \
--
2.32.0
[Intel-gfx] [PATCH 09/27] drm/i915/guc: Kick tasklet after queuing a request
Kick tasklet after queuing a request so it submitted in a timely manner.
Fixes: 3a4cdf1982f0 ("drm/i915/guc: Implement GuC context operations for new
inteface")
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 592b421e1429..b30fdccc71d4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1047,6 +1047,7 @@ static inline void queue_request(struct i915_sched_engine
*sched_engine,
list_add_tail(&rq->sched.link,
i915_sched_lookup_priolist(sched_engine, prio));
set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
+ tasklet_hi_schedule(&sched_engine->tasklet);
}
static int guc_bypass_tasklet_submit(struct intel_guc *guc,
--
2.32.0
[Intel-gfx] [PATCH 06/27] drm/i915/guc: Workaround reset G2H is received after schedule done G2H
If the context is reset as a result of the request cancellation the
context reset G2H is received after schedule disable done G2H which is
the wrong order. The schedule disable done G2H release the waiting
request cancellation code which resubmits the context. This races
with the context reset G2H which also wants to resubmit the context but
in this case it really should be a NOP as request cancellation code owns
the resubmit. Use some clever tricks of checking the context state to
seal this race until the GuC firmware is fixed.
v2:
(Checkpatch)
- Fix typos
v3:
(Daniele)
- State that is a bug in the GuC firmware
Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
Signed-off-by: Matthew Brost
Cc:
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 41 ---
1 file changed, 35 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index d94e7e1a876f..592b421e1429 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -831,17 +831,33 @@ __unwind_incomplete_requests(struct intel_context *ce)
static void __guc_reset_context(struct intel_context *ce, bool stalled)
{
struct i915_request *rq;
+ unsigned long flags;
u32 head;
+ bool skip = false;
intel_context_get(ce);
/*
-* GuC will implicitly mark the context as non-schedulable
-* when it sends the reset notification. Make sure our state
-* reflects this change. The context will be marked enabled
-* on resubmission.
+* GuC will implicitly mark the context as non-schedulable when it sends
+* the reset notification. Make sure our state reflects this change. The
+* context will be marked enabled on resubmission.
+*
+* XXX: If the context is reset as a result of the request cancellation
+* this G2H is received after the schedule disable complete G2H which is
+* wrong as this creates a race between the request cancellation code
+* re-submitting the context and this G2H handler. This is a bug in the
+* GuC but can be worked around in the meantime but converting this to a
+* NOP if a pending enable is in flight as this indicates that a request
+* cancellation has occurred.
*/
- clr_context_enabled(ce);
+ spin_lock_irqsave(&ce->guc_state.lock, flags);
+ if (likely(!context_pending_enable(ce)))
+ clr_context_enabled(ce);
+ else
+ skip = true;
+ spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+ if (unlikely(skip))
+ goto out_put;
rq = intel_context_find_active_request(ce);
if (!rq) {
@@ -860,6 +876,7 @@ static void __guc_reset_context(struct intel_context *ce,
bool stalled)
out_replay:
guc_reset_state(ce, head, stalled);
__unwind_incomplete_requests(ce);
+out_put:
intel_context_put(ce);
}
@@ -1604,6 +1621,13 @@ static void guc_context_cancel_request(struct
intel_context *ce,
guc_reset_state(ce, intel_ring_wrap(ce->ring, rq->head),
true);
}
+
+ /*
+* XXX: Racey if context is reset, see comment in
+* __guc_reset_context().
+*/
+ flush_work(&ce_to_guc(ce)->ct.requests.worker);
+
guc_context_unblock(ce);
}
}
@@ -2718,7 +2742,12 @@ static void guc_handle_context_reset(struct intel_guc
*guc,
{
trace_intel_context_reset(ce);
- if (likely(!intel_context_is_banned(ce))) {
+ /*
+* XXX: Racey if request cancellation has occurred, see comment in
+* __guc_reset_context().
+*/
+ if (likely(!intel_context_is_banned(ce) &&
+ !context_blocked(ce))) {
capture_error_state(guc, ce);
guc_context_replay(ce);
}
--
2.32.0
[Intel-gfx] [PATCH 08/27] drm/i915/selftests: Add a cancel request selftest that triggers a reset
Add a cancel request selftest that results in an engine reset to cancel
the request as it is non-preemptable. Also insert a NOP request after
the cancelled request and confirm that it completely successfully.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/selftests/i915_request.c | 100 ++
1 file changed, 100 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index d67710d10615..e2c5db77f087 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -772,6 +772,98 @@ static int __cancel_completed(struct intel_engine_cs
*engine)
return err;
}
+static int __cancel_reset(struct intel_engine_cs *engine)
+{
+ struct intel_context *ce;
+ struct igt_spinner spin;
+ struct i915_request *rq, *nop;
+ unsigned long preempt_timeout_ms;
+ int err = 0;
+
+ preempt_timeout_ms = engine->props.preempt_timeout_ms;
+ engine->props.preempt_timeout_ms = 100;
+
+ if (igt_spinner_init(&spin, engine->gt))
+ goto out_restore;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ goto out_spin;
+ }
+
+ rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_ce;
+ }
+
+ pr_debug("%s: Cancelling active request\n", engine->name);
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (!igt_wait_for_spinner(&spin, rq)) {
+ struct drm_printer p = drm_info_printer(engine->i915->drm.dev);
+
+ pr_err("Failed to start spinner on %s\n", engine->name);
+ intel_engine_dump(engine, &p, "%s\n", engine->name);
+ err = -ETIME;
+ goto out_rq;
+ }
+
+ nop = intel_context_create_request(ce);
+ if (IS_ERR(nop))
+ goto out_nop;
+ i915_request_get(nop);
+ i915_request_add(nop);
+
+ i915_request_cancel(rq, -EINTR);
+
+ if (i915_request_wait(rq, 0, HZ) < 0) {
+ struct drm_printer p = drm_info_printer(engine->i915->drm.dev);
+
+ pr_err("%s: Failed to cancel hung request\n", engine->name);
+ intel_engine_dump(engine, &p, "%s\n", engine->name);
+ err = -ETIME;
+ goto out_nop;
+ }
+
+ if (rq->fence.error != -EINTR) {
+ pr_err("%s: fence not cancelled (%u)\n",
+ engine->name, rq->fence.error);
+ err = -EINVAL;
+ goto out_nop;
+ }
+
+ if (i915_request_wait(nop, 0, HZ) < 0) {
+ struct drm_printer p = drm_info_printer(engine->i915->drm.dev);
+
+ pr_err("%s: Failed to complete nop request\n", engine->name);
+ intel_engine_dump(engine, &p, "%s\n", engine->name);
+ err = -ETIME;
+ goto out_nop;
+ }
+
+ if (nop->fence.error != 0) {
+ pr_err("%s: Nop request errored (%u)\n",
+ engine->name, nop->fence.error);
+ err = -EINVAL;
+ }
+
+out_nop:
+ i915_request_put(nop);
+out_rq:
+ i915_request_put(rq);
+out_ce:
+ intel_context_put(ce);
+out_spin:
+ igt_spinner_fini(&spin);
+out_restore:
+ engine->props.preempt_timeout_ms = preempt_timeout_ms;
+ if (err)
+ pr_err("%s: %s error %d\n", __func__, engine->name, err);
+ return err;
+}
+
static int live_cancel_request(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -804,6 +896,14 @@ static int live_cancel_request(void *arg)
return err;
if (err2)
return err2;
+
+ /* Expects reset so call outside of igt_live_test_* */
+ err = __cancel_reset(engine);
+ if (err)
+ return err;
+
+ if (igt_flush_test(i915))
+ return -EIO;
}
return 0;
--
2.32.0
[Intel-gfx] [PATCH 15/27] drm/i915/guc: Reset LRC descriptor if register returns -ENODEV
Reset LRC descriptor if a context register returns -ENODEV as this means
we are mid-reset.
Fixes: eb5e7da736f3 ("drm/i915/guc: Reset implementation for new GuC interface")
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 901d867a4d90..2949dce57489 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1405,10 +1405,12 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
} else {
with_intel_runtime_pm(runtime_pm, wakeref)
ret = register_context(ce, loop);
- if (unlikely(ret == -EBUSY))
+ if (unlikely(ret == -EBUSY)) {
+ reset_lrc_desc(guc, desc_idx);
+ } else if (unlikely(ret == -ENODEV)) {
reset_lrc_desc(guc, desc_idx);
- else if (unlikely(ret == -ENODEV))
ret = 0;/* Will get registered later */
+ }
}
return ret;
--
2.32.0
[Intel-gfx] [PATCH 16/27] drm/i915: Allocate error capture in nowait context
Error captures can now be done in a work queue processing G2H messages.
These messages need to be completely done being processed in the reset
path, to avoid races in the missing G2H cleanup, which create a
dependency on memory allocations and dma fences (i915_requests).
Requests depend on resets, thus now we have a circular dependency. To
work around this, allocate the error capture in a nowait context.
v2:
(Daniel Vetter)
- Use GFP_NOWAIT instead GFP_ATOMIC
Fixes: dc0dad365c5e ("Fix for error capture after full GPU reset with GuC")
Fixes: 573ba126aef3 ("Capture error state on context reset")
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/i915_gpu_error.c | 39 +--
1 file changed, 19 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index b9f66dbd46bb..8696ead02118 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -49,8 +49,7 @@
#include "i915_memcpy.h"
#include "i915_scatterlist.h"
-#define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
-#define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)
+#define ATOMIC_MAYFAIL (GFP_NOWAIT | __GFP_NOWARN)
static void __sg_set_buf(struct scatterlist *sg,
void *addr, unsigned int len, loff_t it)
@@ -79,7 +78,7 @@ static bool __i915_error_grow(struct drm_i915_error_state_buf
*e, size_t len)
if (e->cur == e->end) {
struct scatterlist *sgl;
- sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL);
+ sgl = (typeof(sgl))__get_free_page(ATOMIC_MAYFAIL);
if (!sgl) {
e->err = -ENOMEM;
return false;
@@ -99,10 +98,10 @@ static bool __i915_error_grow(struct
drm_i915_error_state_buf *e, size_t len)
}
e->size = ALIGN(len + 1, SZ_64K);
- e->buf = kmalloc(e->size, ALLOW_FAIL);
+ e->buf = kmalloc(e->size, ATOMIC_MAYFAIL);
if (!e->buf) {
e->size = PAGE_ALIGN(len + 1);
- e->buf = kmalloc(e->size, GFP_KERNEL);
+ e->buf = kmalloc(e->size, ATOMIC_MAYFAIL);
}
if (!e->buf) {
e->err = -ENOMEM;
@@ -243,12 +242,12 @@ static bool compress_init(struct i915_vma_compress *c)
{
struct z_stream_s *zstream = &c->zstream;
- if (pool_init(&c->pool, ALLOW_FAIL))
+ if (pool_init(&c->pool, ATOMIC_MAYFAIL))
return false;
zstream->workspace =
kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
- ALLOW_FAIL);
+ ATOMIC_MAYFAIL);
if (!zstream->workspace) {
pool_fini(&c->pool);
return false;
@@ -256,7 +255,7 @@ static bool compress_init(struct i915_vma_compress *c)
c->tmp = NULL;
if (i915_has_memcpy_from_wc())
- c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);
+ c->tmp = pool_alloc(&c->pool, ATOMIC_MAYFAIL);
return true;
}
@@ -280,7 +279,7 @@ static void *compress_next_page(struct i915_vma_compress *c,
if (dst->page_count >= dst->num_pages)
return ERR_PTR(-ENOSPC);
- page = pool_alloc(&c->pool, ALLOW_FAIL);
+ page = pool_alloc(&c->pool, ATOMIC_MAYFAIL);
if (!page)
return ERR_PTR(-ENOMEM);
@@ -376,7 +375,7 @@ struct i915_vma_compress {
static bool compress_init(struct i915_vma_compress *c)
{
- return pool_init(&c->pool, ALLOW_FAIL) == 0;
+ return pool_init(&c->pool, ATOMIC_MAYFAIL) == 0;
}
static bool compress_start(struct i915_vma_compress *c)
@@ -391,7 +390,7 @@ static int compress_page(struct i915_vma_compress *c,
{
void *ptr;
- ptr = pool_alloc(&c->pool, ALLOW_FAIL);
+ ptr = pool_alloc(&c->pool, ATOMIC_MAYFAIL);
if (!ptr)
return -ENOMEM;
@@ -1026,7 +1025,7 @@ i915_vma_coredump_create(const struct intel_gt *gt,
num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
- dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL);
+ dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ATOMIC_MAYFAIL);
if (!dst)
return NULL;
@@ -1462,7 +1461,7 @@ capture_engine(struct intel_engine_cs *engine,
struct i915_request *rq = NULL;
unsigned long flags;
- ee = intel_engine_coredump_alloc(engine, GFP_KERNEL);
+ ee = intel_engine_coredump_alloc(engine, ATOMIC_MAYFAIL);
if (!ee)
return NULL;
@@ -1510,7 +1509,7 @@ gt_record_engines(struct intel_gt_coredump *gt,
struct intel_engine_coredump *ee;
/* Refill our page pool before entering atomic section */
- pool_refill(&compress->pool, ALLOW_FAIL);
+ pool_re
[Intel-gfx] [PATCH 12/27] drm/i915/selftests: Add initial GuC selftest for scrubbing lost G2H
While debugging an issue with full GT resets I went down a rabbit hole
thinking the scrubbing of lost G2H wasn't working correctly. This proved
to be incorrect as this was working just fine but this chase inspired me
to write a selftest to prove that this works. This simple selftest
injects errors dropping various G2H and then issues a full GT reset
proving that the scrubbing of these G2H doesn't blow up.
v2:
(Daniel Vetter)
- Use ifdef instead of macros for selftests
v3:
(Checkpatch)
- A space after 'switch' statement
v4:
(Daniele)
- A comment saying GT won't idle if G2H are lost
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 18 +++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 25
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 127 ++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../i915/selftests/intel_scheduler_helpers.c | 12 ++
.../i915/selftests/intel_scheduler_helpers.h | 2 +
6 files changed, 185 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/uc/selftest_guc.c
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index e54351a170e2..3a73f3117873 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -198,6 +198,24 @@ struct intel_context {
*/
u8 guc_prio;
u32 guc_prio_count[GUC_CLIENT_PRIORITY_NUM];
+
+#ifdef CONFIG_DRM_I915_SELFTEST
+ /**
+* @drop_schedule_enable: Force drop of schedule enable G2H for selftest
+*/
+ bool drop_schedule_enable;
+
+ /**
+* @drop_schedule_disable: Force drop of schedule disable G2H for
+* selftest
+*/
+ bool drop_schedule_disable;
+
+ /**
+* @drop_deregister: Force drop of deregister G2H for selftest
+*/
+ bool drop_deregister;
+#endif
};
#endif /* __INTEL_CONTEXT_TYPES__ */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 56f11accd6cc..5844bb954922 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2645,6 +2645,13 @@ int intel_guc_deregister_done_process_msg(struct
intel_guc *guc,
trace_intel_context_deregister_done(ce);
+#ifdef CONFIG_DRM_I915_SELFTEST
+ if (unlikely(ce->drop_deregister)) {
+ ce->drop_deregister = false;
+ return 0;
+ }
+#endif
+
if (context_wait_for_deregister_to_register(ce)) {
struct intel_runtime_pm *runtime_pm =
&ce->engine->gt->i915->runtime_pm;
@@ -2699,10 +2706,24 @@ int intel_guc_sched_done_process_msg(struct intel_guc
*guc,
trace_intel_context_sched_done(ce);
if (context_pending_enable(ce)) {
+#ifdef CONFIG_DRM_I915_SELFTEST
+ if (unlikely(ce->drop_schedule_enable)) {
+ ce->drop_schedule_enable = false;
+ return 0;
+ }
+#endif
+
clr_context_pending_enable(ce);
} else if (context_pending_disable(ce)) {
bool banned;
+#ifdef CONFIG_DRM_I915_SELFTEST
+ if (unlikely(ce->drop_schedule_disable)) {
+ ce->drop_schedule_disable = false;
+ return 0;
+ }
+#endif
+
/*
* Unpin must be done before __guc_signal_context_fence,
* otherwise a race exists between the requests getting
@@ -3079,3 +3100,7 @@ bool intel_guc_virtual_engine_has_heartbeat(const struct
intel_engine_cs *ve)
return false;
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_guc.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
new file mode 100644
index ..fb0e4a7bd8ca
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright �� 2021 Intel Corporation
+ */
+
+#include "selftests/intel_scheduler_helpers.h"
+
+static struct i915_request *nop_user_request(struct intel_context *ce,
+struct i915_request *from)
+{
+ struct i915_request *rq;
+ int ret;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ return rq;
+
+ if (from) {
+ ret = i915_sw_fence_await_dma_fence(&rq->submit,
+ &from->fence, 0,
+ I915_FENCE_GFP);
+ if (ret < 0) {
+ i915_request_put(rq);
+ return ERR_PTR(ret);
+ }
+ }
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ return rq;
+}
+
+static i
[Intel-gfx] [PATCH 14/27] drm/i915/guc: Don't touch guc_state.sched_state without a lock
Before we did some clever tricks to not use the a lock when touching
guc_state.sched_state in certain cases. Don't do that, enforce the use
of the lock.
Part of this is removing a dead code path from guc_lrc_desc_pin where a
context could be deregistered when the aforementioned function was
called from the submission path. Remove this dead code and add a
GEM_BUG_ON if this path is ever attempted to be used.
v2:
(kernel test robo )
- Add __maybe_unused to sched_state_is_init()
Signed-off-by: Matthew Brost
Reported-by: kernel test robot
Reviewed-by: Daniele Ceraolo Spurio
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 58 ++-
1 file changed, 32 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 1cb97e98871c..901d867a4d90 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -151,11 +151,23 @@ static inline void clr_context_registered(struct
intel_context *ce)
static inline void init_sched_state(struct intel_context *ce)
{
- /* Only should be called from guc_lrc_desc_pin() */
+ lockdep_assert_held(&ce->guc_state.lock);
atomic_set(&ce->guc_sched_state_no_lock, 0);
ce->guc_state.sched_state &= SCHED_STATE_BLOCKED_MASK;
}
+__maybe_unused
+static bool sched_state_is_init(struct intel_context *ce)
+{
+ /*
+* XXX: Kernel contexts can have SCHED_STATE_NO_LOCK_REGISTERED after
+* suspend.
+*/
+ return !(atomic_read(&ce->guc_sched_state_no_lock) &
+~SCHED_STATE_NO_LOCK_REGISTERED) &&
+ !(ce->guc_state.sched_state &= ~SCHED_STATE_BLOCKED_MASK);
+}
+
static inline bool
context_wait_for_deregister_to_register(struct intel_context *ce)
{
@@ -166,7 +178,7 @@ context_wait_for_deregister_to_register(struct
intel_context *ce)
static inline void
set_context_wait_for_deregister_to_register(struct intel_context *ce)
{
- /* Only should be called from guc_lrc_desc_pin() without lock */
+ lockdep_assert_held(&ce->guc_state.lock);
ce->guc_state.sched_state |=
SCHED_STATE_WAIT_FOR_DEREGISTER_TO_REGISTER;
}
@@ -605,9 +617,7 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
intel_guc *guc)
bool pending_disable, pending_enable, deregister, destroyed, banned;
xa_for_each(&guc->context_lookup, index, ce) {
- /* Flush context */
spin_lock_irqsave(&ce->guc_state.lock, flags);
- spin_unlock_irqrestore(&ce->guc_state.lock, flags);
/*
* Once we are at this point submission_disabled() is guaranteed
@@ -623,6 +633,8 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
intel_guc *guc)
banned = context_banned(ce);
init_sched_state(ce);
+ spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+
if (pending_enable || destroyed || deregister) {
decr_outstanding_submission_g2h(guc);
if (deregister)
@@ -1323,6 +1335,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
int ret = 0;
GEM_BUG_ON(!engine->mask);
+ GEM_BUG_ON(!sched_state_is_init(ce));
/*
* Ensure LRC + CT vmas are is same region as write barrier is done
@@ -1351,7 +1364,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
desc->priority = ce->guc_prio;
desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
guc_context_policy_init(engine, desc);
- init_sched_state(ce);
/*
* The context_lookup xarray is used to determine if the hardware
@@ -1362,26 +1374,23 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
* registering this context.
*/
if (context_registered) {
+ bool disabled;
+ unsigned long flags;
+
trace_intel_context_steal_guc_id(ce);
- if (!loop) {
+ GEM_BUG_ON(!loop);
+
+ /* Seal race with Reset */
+ spin_lock_irqsave(&ce->guc_state.lock, flags);
+ disabled = submission_disabled(guc);
+ if (likely(!disabled)) {
set_context_wait_for_deregister_to_register(ce);
intel_context_get(ce);
- } else {
- bool disabled;
- unsigned long flags;
-
- /* Seal race with Reset */
- spin_lock_irqsave(&ce->guc_state.lock, flags);
- disabled = submission_disabled(guc);
- if (likely(!disabled)) {
- set_context_wait_for_deregister_to_register(ce);
- intel_context_get(ce);
- }
-
[Intel-gfx] [PATCH 04/27] drm/i915/guc: Don't drop ce->guc_active.lock when unwinding context
Don't drop ce->guc_active.lock when unwinding a context after reset.
At one point we had to drop this because of a lock inversion but that is
no longer the case. It is much safer to hold the lock so let's do that.
Fixes: eb5e7da736f3 ("drm/i915/guc: Reset implementation for new GuC interface")
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
Cc:
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 8b1a82cfb52d..d94e7e1a876f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -811,8 +811,6 @@ __unwind_incomplete_requests(struct intel_context *ce)
continue;
list_del_init(&rq->sched.link);
- spin_unlock(&ce->guc_active.lock);
-
__i915_request_unsubmit(rq);
/* Push the request back into the queue for later resubmission.
*/
@@ -825,8 +823,6 @@ __unwind_incomplete_requests(struct intel_context *ce)
list_add(&rq->sched.link, pl);
set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
-
- spin_lock(&ce->guc_active.lock);
}
spin_unlock(&ce->guc_active.lock);
spin_unlock_irqrestore(&sched_engine->lock, flags);
--
2.32.0
[Intel-gfx] [PATCH 03/27] drm/i915/guc: Unwind context requests in reverse order
When unwinding requests on a reset context, if other requests in the
context are in the priority list the requests could be resubmitted out
of seqno order. Traverse the list of active requests in reverse and
append to the head of the priority list to fix this.
Fixes: eb5e7da736f3 ("drm/i915/guc: Reset implementation for new GuC interface")
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
Cc:
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 03a86da6011e..8b1a82cfb52d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -804,9 +804,9 @@ __unwind_incomplete_requests(struct intel_context *ce)
spin_lock_irqsave(&sched_engine->lock, flags);
spin_lock(&ce->guc_active.lock);
- list_for_each_entry_safe(rq, rn,
-&ce->guc_active.requests,
-sched.link) {
+ list_for_each_entry_safe_reverse(rq, rn,
+&ce->guc_active.requests,
+sched.link) {
if (i915_request_completed(rq))
continue;
@@ -823,7 +823,7 @@ __unwind_incomplete_requests(struct intel_context *ce)
}
GEM_BUG_ON(i915_sched_engine_is_empty(sched_engine));
- list_add_tail(&rq->sched.link, pl);
+ list_add(&rq->sched.link, pl);
set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
spin_lock(&ce->guc_active.lock);
--
2.32.0
[Intel-gfx] [PATCH 02/27] drm/i915/guc: Fix outstanding G2H accounting
A small race that could result in incorrect accounting of the number
of outstanding G2H. Basically prior to this patch we did not increment
the number of outstanding G2H if we encoutered a GT reset while sending
a H2G. This was incorrect as the context state had already been updated
to anticipate a G2H response thus the counter should be incremented.
Also always use helper when decrementing this value.
Fixes: f4eb1f3fe946 ("drm/i915/guc: Ensure G2H response has space in buffer")
Signed-off-by: Matthew Brost
Cc:
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 23 ++-
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 69faa39da178..03a86da6011e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -352,6 +352,12 @@ static inline void set_lrc_desc_registered(struct
intel_guc *guc, u32 id,
xa_unlock_irqrestore(&guc->context_lookup, flags);
}
+static void decr_outstanding_submission_g2h(struct intel_guc *guc)
+{
+ if (atomic_dec_and_test(&guc->outstanding_submission_g2h))
+ wake_up_all(&guc->ct.wq);
+}
+
static int guc_submission_send_busy_loop(struct intel_guc *guc,
const u32 *action,
u32 len,
@@ -360,11 +366,12 @@ static int guc_submission_send_busy_loop(struct intel_guc
*guc,
{
int err;
- err = intel_guc_send_busy_loop(guc, action, len, g2h_len_dw, loop);
-
- if (!err && g2h_len_dw)
+ if (g2h_len_dw)
atomic_inc(&guc->outstanding_submission_g2h);
+ err = intel_guc_send_busy_loop(guc, action, len, g2h_len_dw, loop);
+ GEM_BUG_ON(g2h_len_dw && err == -EBUSY);
+
return err;
}
@@ -616,7 +623,7 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
intel_guc *guc)
init_sched_state(ce);
if (pending_enable || destroyed || deregister) {
- atomic_dec(&guc->outstanding_submission_g2h);
+ decr_outstanding_submission_g2h(guc);
if (deregister)
guc_signal_context_fence(ce);
if (destroyed) {
@@ -635,7 +642,7 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
intel_guc *guc)
intel_engine_signal_breadcrumbs(ce->engine);
}
intel_context_sched_disable_unpin(ce);
- atomic_dec(&guc->outstanding_submission_g2h);
+ decr_outstanding_submission_g2h(guc);
spin_lock_irqsave(&ce->guc_state.lock, flags);
guc_blocked_fence_complete(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
@@ -2583,12 +2590,6 @@ g2h_context_lookup(struct intel_guc *guc, u32 desc_idx)
return ce;
}
-static void decr_outstanding_submission_g2h(struct intel_guc *guc)
-{
- if (atomic_dec_and_test(&guc->outstanding_submission_g2h))
- wake_up_all(&guc->ct.wq);
-}
-
int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
const u32 *msg,
u32 len)
--
2.32.0
[Intel-gfx] [PATCH 00/27] Clean up GuC CI failures, simplify locking, and kernel DOC
Daniel Vetter pointed out that locking in the GuC submission code was overly complicated, let's clean this up a bit before introducing more features in the GuC submission backend. Also fix some CI failures, port fixes from our internal tree, and add a few more selftests for coverage. Lastly, add some kernel DOC explaining how the GuC submission backend works. v2: Fix logic error in 'Workaround reset G2H is received after schedule done G2H', don't propagate errors to dependent fences in execlists submissiom, resolve checkpatch issues, resend to correct lists v3: Fix issue kicking tasklet, drop guc_active, fix ref counting in xarray, add guc_id sub structure, drop inline fuctions, and various other cleanup suggested by Daniel v4: Address Daniele's feedback, rebase to tip, resend for CI Signed-off-by: Matthew Brost Matthew Brost (27): drm/i915/guc: Fix blocked context accounting drm/i915/guc: Fix outstanding G2H accounting drm/i915/guc: Unwind context requests in reverse order drm/i915/guc: Don't drop ce->guc_active.lock when unwinding context drm/i915/guc: Process all G2H message at once in work queue drm/i915/guc: Workaround reset G2H is received after schedule done G2H Revert "drm/i915/gt: Propagate change in error status to children on unhold" drm/i915/selftests: Add a cancel request selftest that triggers a reset drm/i915/guc: Kick tasklet after queuing a request drm/i915/guc: Don't enable scheduling on a banned context, guc_id invalid, not registered drm/i915/guc: Copy whole golden context, set engine state size of subset drm/i915/selftests: Add initial GuC selftest for scrubbing lost G2H drm/i915/guc: Take context ref when cancelling request drm/i915/guc: Don't touch guc_state.sched_state without a lock drm/i915/guc: Reset LRC descriptor if register returns -ENODEV drm/i915: Allocate error capture in nowait context drm/i915/guc: Flush G2H work queue during reset drm/i915/guc: Release submit fence from an irq_work drm/i915/guc: Move guc_blocked fence to struct guc_state drm/i915/guc: Rework and simplify locking drm/i915/guc: Proper xarray usage for contexts_lookup drm/i915/guc: Drop pin count check trick between sched_disable and re-pin drm/i915/guc: Move GuC priority fields in context under guc_active drm/i915/guc: Move fields protected by guc->contexts_lock into sub structure drm/i915/guc: Drop guc_active move everything into guc_state drm/i915/guc: Add GuC kernel doc drm/i915/guc: Drop static inline functions intel_guc_submission.c drivers/gpu/drm/i915/gt/intel_context.c | 19 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 81 +- .../drm/i915/gt/intel_execlists_submission.c | 4 - drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 6 +- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 19 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 28 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 996 +++--- drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 127 +++ drivers/gpu/drm/i915/i915_gpu_error.c | 39 +- drivers/gpu/drm/i915/i915_request.h | 23 +- drivers/gpu/drm/i915/i915_trace.h | 12 +- .../drm/i915/selftests/i915_live_selftests.h | 1 + drivers/gpu/drm/i915/selftests/i915_request.c | 100 ++ .../i915/selftests/intel_scheduler_helpers.c | 12 + .../i915/selftests/intel_scheduler_helpers.h | 2 + 16 files changed, 983 insertions(+), 492 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/uc/selftest_guc.c -- 2.32.0
[Intel-gfx] [PATCH 01/27] drm/i915/guc: Fix blocked context accounting
Prior to this patch the blocked context counter was cleared on
init_sched_state (used during registering a context & resets) which is
incorrect. This state needs to be persistent or the counter can read the
incorrect value resulting in scheduling never getting enabled again.
Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
Signed-off-by: Matthew Brost
Reviewed-by: Daniel Vetter
Cc:
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 87d8dc8f51b9..69faa39da178 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -152,7 +152,7 @@ static inline void init_sched_state(struct intel_context
*ce)
{
/* Only should be called from guc_lrc_desc_pin() */
atomic_set(&ce->guc_sched_state_no_lock, 0);
- ce->guc_state.sched_state = 0;
+ ce->guc_state.sched_state &= SCHED_STATE_BLOCKED_MASK;
}
static inline bool
--
2.32.0
Re: [Intel-gfx] [PATCH] drm/i915: Clean up disabled warnings
On Tue, Aug 24, 2021 at 4:23 PM Nathan Chancellor wrote:
>
> i915 enables a wider set of warnings with '-Wall -Wextra' then disables
> several with cc-disable-warning. If an unknown flag gets added to
> KBUILD_CFLAGS when building with clang, all subsequent calls to
> cc-{disable-warning,option} will fail, meaning that all of these
> warnings do not get disabled [1].
>
> A separate series will address the root cause of the issue by not adding
> these flags when building with clang [2]; however, the symptom of these
> extra warnings appearing can be addressed separately by just removing
> the calls to cc-disable-warning, which makes the build ever so slightly
> faster because the compiler does not need to be called as much before
> building.
>
> The following warnings are supported by GCC 4.9 and clang 10.0.1, which
> are the minimum supported versions of these compilers so the call to
> cc-disable-warning is not necessary. Masahiro cleaned this up for the
> reset of the kernel in commit 4c8dd95a723d ("kbuild: add some extra
> warning flags unconditionally").
>
> * -Wmissing-field-initializers
> * -Wsign-compare
> * -Wtype-limits
> * -Wunused-parameter
>
> -Wunused-but-set-variable was implemented in clang 13.0.0 and
> -Wframe-address was implemented in clang 12.0.0 so the
> cc-disable-warning calls are kept for these two warnings.
>
> Lastly, -Winitializer-overrides is clang's version of -Woverride-init,
> which is disabled for the specific files that are problematic. clang
> added a compatibility alias in clang 8.0.0 so -Winitializer-overrides
> can be removed.
>
> [1]: https://lore.kernel.org/r/202108210311.cbtcgoul-...@intel.com/
> [2]: https://lore.kernel.org/r/20210824022640.2170859-1-nat...@kernel.org/
>
> Signed-off-by: Nathan Chancellor
Thanks for the patch! Do you need to re-ping, rebase, or resend that
other series?
Reviewed-by: Nick Desaulniers
> ---
>
> NOTE: This is based on my series to enable -Wsometimes-initialized here:
>
> https://lore.kernel.org/r/20210824225427.2065517-1-nat...@kernel.org/
>
> I sent it separately as this can go into whatever release but I would
> like for that series to go into 5.15.
>
> drivers/gpu/drm/i915/Makefile | 10 --
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 335ba9f43d8f..6b38547543b1 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -13,13 +13,11 @@
> # will most likely get a sudden build breakage... Hopefully we will fix
> # new warnings before CI updates!
> subdir-ccflags-y := -Wall -Wextra
> -subdir-ccflags-y += $(call cc-disable-warning, unused-parameter)
> -subdir-ccflags-y += $(call cc-disable-warning, type-limits)
> -subdir-ccflags-y += $(call cc-disable-warning, missing-field-initializers)
> +subdir-ccflags-y += -Wno-unused-parameter
> +subdir-ccflags-y += -Wno-type-limits
> +subdir-ccflags-y += -Wno-missing-field-initializers
> +subdir-ccflags-y += -Wno-sign-compare
> subdir-ccflags-y += $(call cc-disable-warning, unused-but-set-variable)
> -# clang warnings
> -subdir-ccflags-y += $(call cc-disable-warning, sign-compare)
> -subdir-ccflags-y += $(call cc-disable-warning, initializer-overrides)
> subdir-ccflags-y += $(call cc-disable-warning, frame-address)
> subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
>
>
> base-commit: fb43ebc83e069625cfeeb2490efc3ffa0013bfa4
> prerequisite-patch-id: 31c28450ed7e8785dce967a16db6d52eff3d7d6d
> prerequisite-patch-id: 372dfa0e07249f207acc1942ab0e39b13ff229b2
> prerequisite-patch-id: 1a585fa6cda50c32ad1e3ac8235d3cff1b599978
> --
> 2.33.0
>
--
Thanks,
~Nick Desaulniers
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pci: rename functions to have i915_pci prefix
== Series Details == Series: drm/i915/pci: rename functions to have i915_pci prefix URL : https://patchwork.freedesktop.org/series/94022/ State : success == Summary == CI Bug Log - changes from CI_DRM_10520_full -> Patchwork_20892_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20892_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@psr2: - shard-iclb: [PASS][1] -> [SKIP][2] ([i915#658]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-iclb2/igt@feature_discov...@psr2.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-iclb8/igt@feature_discov...@psr2.html * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-snb5/igt@gem_cre...@create-massive.html - shard-kbl: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-kbl1/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +6 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_eio@in-flight-suspend: - shard-skl: [PASS][6] -> [INCOMPLETE][7] ([i915#198]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-skl9/igt@gem_...@in-flight-suspend.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-skl9/igt@gem_...@in-flight-suspend.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2846]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-kbl1/igt@gem_exec_f...@basic-deadline.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-kbl6/igt@gem_exec_f...@basic-deadline.html - shard-apl: NOTRUN -> [FAIL][10] ([i915#2846]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-apl3/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-tglb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-tglb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][13] -> [FAIL][14] ([i915#2842] / [i915#3468]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-apl7/igt@gem_exec_fair@basic-n...@vecs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-apl2/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html - shard-kbl: [PASS][16] -> [FAIL][17] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-kbl3/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][18] -> [SKIP][19] ([fdo#109271]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-kbl3/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_whisper@basic-fds-priority-all: - shard-glk: [PASS][20] -> [DMESG-WARN][21] ([i915#118] / [i915#95]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-glk4/igt@gem_exec_whis...@basic-fds-priority-all.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-glk7/igt@gem_exec_whis...@basic-fds-priority-all.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#3323]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-apl8/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy@fixed: - shard-iclb: NOTRUN -> [SKIP][23] ([i915#3922]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-iclb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-b...@fixed.html * igt@gem_userptr_blits@vma-merge: - shard-apl: NOTRUN -> [FAIL][24] ([i915#3318]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/shard-apl3/igt@gem_userptr_bl...@vma-merg
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm: update locking for modesetting (rev5)
== Series Details == Series: drm: update locking for modesetting (rev5) URL : https://patchwork.freedesktop.org/series/93864/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10521 -> Patchwork_20895 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20895 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20895, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20895: ### IGT changes ### Possible regressions * igt@kms_busy@basic@flip: - fi-bxt-dsi: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10521/fi-bxt-dsi/igt@kms_busy@ba...@flip.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/fi-bxt-dsi/igt@kms_busy@ba...@flip.html - fi-hsw-4770:[PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10521/fi-hsw-4770/igt@kms_busy@ba...@flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/fi-hsw-4770/igt@kms_busy@ba...@flip.html - fi-cfl-guc: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10521/fi-cfl-guc/igt@kms_busy@ba...@flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/fi-cfl-guc/igt@kms_busy@ba...@flip.html - fi-skl-guc: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10521/fi-skl-guc/igt@kms_busy@ba...@flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/fi-skl-guc/igt@kms_busy@ba...@flip.html - fi-ilk-650: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10521/fi-ilk-650/igt@kms_busy@ba...@flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/fi-ilk-650/igt@kms_busy@ba...@flip.html - fi-ivb-3770:[PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10521/fi-ivb-3770/igt@kms_busy@ba...@flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/fi-ivb-3770/igt@kms_busy@ba...@flip.html - fi-rkl-11600: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10521/fi-rkl-11600/igt@kms_busy@ba...@flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/fi-rkl-11600/igt@kms_busy@ba...@flip.html - fi-icl-y: [PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10521/fi-icl-y/igt@kms_busy@ba...@flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/fi-icl-y/igt@kms_busy@ba...@flip.html - fi-elk-e7500: [PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10521/fi-elk-e7500/igt@kms_busy@ba...@flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/fi-elk-e7500/igt@kms_busy@ba...@flip.html - fi-skl-6700k2: [PASS][19] -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10521/fi-skl-6700k2/igt@kms_busy@ba...@flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/fi-skl-6700k2/igt@kms_busy@ba...@flip.html - fi-icl-u2: [PASS][21] -> [DMESG-WARN][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10521/fi-icl-u2/igt@kms_busy@ba...@flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/fi-icl-u2/igt@kms_busy@ba...@flip.html - fi-cfl-8700k: [PASS][23] -> [DMESG-WARN][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10521/fi-cfl-8700k/igt@kms_busy@ba...@flip.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/fi-cfl-8700k/igt@kms_busy@ba...@flip.html - fi-snb-2520m: [PASS][25] -> [DMESG-WARN][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10521/fi-snb-2520m/igt@kms_busy@ba...@flip.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/fi-snb-2520m/igt@kms_busy@ba...@flip.html - fi-bsw-kefka: [PASS][27] -> [DMESG-WARN][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10521/fi-bsw-kefka/igt@kms_busy@ba...@flip.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/fi-bsw-kefka/igt@kms_busy@ba...@flip.html - fi-glk-dsi: [PASS][29] -> [DMESG-WARN][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10521/fi-glk-dsi/igt@kms_busy@ba...@flip.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20895/fi-glk-dsi/igt@kms_busy@ba...@flip.html - fi-pnv-d510:[PASS][31] -> [DMESG-WARN
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm: update locking for modesetting (rev5)
== Series Details == Series: drm: update locking for modesetting (rev5) URL : https://patchwork.freedesktop.org/series/93864/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:1365:16: warning: symbol 'configure_lttpr_mode_transparent' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:1376:16: warning: symbol 'configure_lttpr_mode_non_transparent' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:1627:16: warning: symbol 'dpcd_configure_channel_coding' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_resource.c:1741:16: warning: Using plain integer as NULL pointer +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:135:6: warning: symbol 'dcn10_log_hubbub_state' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1902:10: warning: symbol 'reduceSizeAndFraction' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1953:6: warning: symbol 'is_low_refresh_rate' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1962:9: warning: symbol 'get_clock_divider' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1982:5: warning: symbol 'dcn10_align_pixel_clocks' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2274:6: warning: symbol 'dcn10_program_pte_vm' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:80:6: warning: symbol 'print_microsec' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dsc.c:49:24: warning: symbol 'dcn20_dsc_funcs' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:1080:6: warning: symbol 'dcn20_enable_plane' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:1391:17: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:1391:17: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:678:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:678:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:679:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:679:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:680:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:680:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:681:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:681:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:682:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:682:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:683:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:683:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:687:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:687:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:692:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:692:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:776:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:776:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:777:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:777:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:778:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:778:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:779:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:779:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_
[Intel-gfx] [PATCH v8 7/7] drm: remove drm_file.master_lookup_lock
Previously, master_lookup_lock was introduced in
commit 0b0860a3cf5e ("drm: serialize drm_file.master with a new
spinlock") to serialize accesses to drm_file.master. This then allowed
us to write drm_file_get_master in commit 56f0729a510f ("drm: protect
drm_master pointers in drm_lease.c").
The rationale behind introducing a new spinlock at the time was that
the other lock that could have been used (drm_device.master_mutex) was
the outermost lock, so embedding calls to drm_file_get_master and
drm_is_current_master in various functions easily caused us to invert
the lock hierarchy.
Following the conversion of master_mutex into a rwsem, and its use to
plug races with modesetting rights, we've untangled some lock
hierarchies and removed the need for using drm_file_get_master and the
unlocked version of drm_is_current_master in multiple places.
Hence, we can take this opportunity to clean up the locking design by
replacing master_lookup_lock with drm_device.master_rwsem.
Signed-off-by: Desmond Cheong Zhi Xi
---
drivers/gpu/drm/drm_auth.c | 19 +++
drivers/gpu/drm/drm_file.c | 1 -
drivers/gpu/drm/drm_internal.h | 1 +
drivers/gpu/drm/drm_ioctl.c| 4 ++--
drivers/gpu/drm/drm_lease.c| 18 --
include/drm/drm_file.h | 9 +
6 files changed, 19 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c
index f2b2f197052a..232416119407 100644
--- a/drivers/gpu/drm/drm_auth.c
+++ b/drivers/gpu/drm/drm_auth.c
@@ -61,10 +61,9 @@
* trusted clients.
*/
-static bool drm_is_current_master_locked(struct drm_file *fpriv)
+bool drm_is_current_master_locked(struct drm_file *fpriv)
{
- lockdep_assert_once(lockdep_is_held(&fpriv->master_lookup_lock) ||
- lockdep_is_held(&fpriv->minor->dev->master_rwsem));
+ lockdep_assert_held_once(&fpriv->minor->dev->master_rwsem);
return fpriv->is_master && drm_lease_owner(fpriv->master) ==
fpriv->minor->dev->master;
}
@@ -83,9 +82,9 @@ bool drm_is_current_master(struct drm_file *fpriv)
{
bool ret;
- spin_lock(&fpriv->master_lookup_lock);
+ down_read(&fpriv->minor->dev->master_rwsem);
ret = drm_is_current_master_locked(fpriv);
- spin_unlock(&fpriv->master_lookup_lock);
+ up_read(&fpriv->minor->dev->master_rwsem);
return ret;
}
@@ -120,7 +119,7 @@ int drm_authmagic(struct drm_device *dev, void *data,
DRM_DEBUG("%u\n", auth->magic);
down_write(&dev->master_rwsem);
- if (unlikely(!drm_is_current_master(file_priv))) {
+ if (unlikely(!drm_is_current_master_locked(file_priv))) {
up_write(&dev->master_rwsem);
return -EACCES;
}
@@ -178,9 +177,7 @@ static int drm_new_set_master(struct drm_device *dev,
struct drm_file *fpriv)
new_master = drm_master_create(dev);
if (!new_master)
return -ENOMEM;
- spin_lock(&fpriv->master_lookup_lock);
fpriv->master = new_master;
- spin_unlock(&fpriv->master_lookup_lock);
fpriv->is_master = 1;
fpriv->authenticated = 1;
@@ -343,9 +340,7 @@ int drm_master_open(struct drm_file *file_priv)
if (!dev->master) {
ret = drm_new_set_master(dev, file_priv);
} else {
- spin_lock(&file_priv->master_lookup_lock);
file_priv->master = drm_master_get(dev->master);
- spin_unlock(&file_priv->master_lookup_lock);
}
up_write(&dev->master_rwsem);
@@ -413,13 +408,13 @@ struct drm_master *drm_file_get_master(struct drm_file
*file_priv)
if (!file_priv)
return NULL;
- spin_lock(&file_priv->master_lookup_lock);
+ down_read(&file_priv->minor->dev->master_rwsem);
if (!file_priv->master)
goto unlock;
master = drm_master_get(file_priv->master);
unlock:
- spin_unlock(&file_priv->master_lookup_lock);
+ up_read(&file_priv->minor->dev->master_rwsem);
return master;
}
EXPORT_SYMBOL(drm_file_get_master);
diff --git a/drivers/gpu/drm/drm_file.c b/drivers/gpu/drm/drm_file.c
index 90b62f360da1..8c846e0179d7 100644
--- a/drivers/gpu/drm/drm_file.c
+++ b/drivers/gpu/drm/drm_file.c
@@ -176,7 +176,6 @@ struct drm_file *drm_file_alloc(struct drm_minor *minor)
init_waitqueue_head(&file->event_wait);
file->event_space = 4096; /* set aside 4k for event buffer */
- spin_lock_init(&file->master_lookup_lock);
mutex_init(&file->event_read_lock);
if (drm_core_check_feature(dev, DRIVER_GEM))
diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
index 17f3548c8ed2..5d421f749a17 100644
--- a/drivers/gpu/drm/drm_internal.h
+++ b/drivers/gpu/drm/drm_internal.h
@@ -132,6 +132,7 @@ int drm_crtc_queue_sequence_ioctl(struct drm_device *dev,
void *data,
struct drm_file *filp);
/* drm_a
[Intel-gfx] [PATCH v8 6/7] drm: avoid circular locks in drm_lease_held
drm_lease_held calls drm_file_get_master. However, this function is
sometimes called while holding on to drm_device.master_rwsem or
modeset_mutex. Since master_rwsem will replace
drm_file.master_lookup_lock in drm_file_get_master in a future patch,
this results in both recursive locking, and an inversion of the
master_rwsem --> modeset_mutex lock hierarchy.
To fix this, we create a new drm_lease_held_master helper function
that enables us to avoid calling drm_file_get_master after locking
master_rwsem or modeset_mutex.
Signed-off-by: Desmond Cheong Zhi Xi
---
drivers/gpu/drm/drm_auth.c| 3 +++
drivers/gpu/drm/drm_crtc.c| 4 +++-
drivers/gpu/drm/drm_encoder.c | 7 ++-
drivers/gpu/drm/drm_lease.c | 30 +++---
drivers/gpu/drm/drm_plane.c | 18 ++
include/drm/drm_lease.h | 2 ++
6 files changed, 43 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c
index 65065f7e1499..f2b2f197052a 100644
--- a/drivers/gpu/drm/drm_auth.c
+++ b/drivers/gpu/drm/drm_auth.c
@@ -410,6 +410,9 @@ struct drm_master *drm_file_get_master(struct drm_file
*file_priv)
{
struct drm_master *master = NULL;
+ if (!file_priv)
+ return NULL;
+
spin_lock(&file_priv->master_lookup_lock);
if (!file_priv->master)
goto unlock;
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index b1279bb3fa61..0b1e76d2f9ff 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -665,8 +665,10 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
plane = crtc->primary;
+ lockdep_assert_held_once(&dev->master_rwsem);
/* allow disabling with the primary plane leased */
- if (crtc_req->mode_valid && !drm_lease_held(file_priv, plane->base.id))
+ if (crtc_req->mode_valid &&
+ !drm_lease_held_master(file_priv->master, plane->base.id))
return -EACCES;
DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx,
diff --git a/drivers/gpu/drm/drm_encoder.c b/drivers/gpu/drm/drm_encoder.c
index 72e982323a5e..bacb2f6a325c 100644
--- a/drivers/gpu/drm/drm_encoder.c
+++ b/drivers/gpu/drm/drm_encoder.c
@@ -22,6 +22,7 @@
#include
+#include
#include
#include
#include
@@ -281,6 +282,7 @@ int drm_mode_getencoder(struct drm_device *dev, void *data,
struct drm_mode_get_encoder *enc_resp = data;
struct drm_encoder *encoder;
struct drm_crtc *crtc;
+ struct drm_master *master;
if (!drm_core_check_feature(dev, DRIVER_MODESET))
return -EOPNOTSUPP;
@@ -289,13 +291,16 @@ int drm_mode_getencoder(struct drm_device *dev, void
*data,
if (!encoder)
return -ENOENT;
+ master = drm_file_get_master(file_priv);
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
crtc = drm_encoder_get_crtc(encoder);
- if (crtc && drm_lease_held(file_priv, crtc->base.id))
+ if (crtc && drm_lease_held_master(master, crtc->base.id))
enc_resp->crtc_id = crtc->base.id;
else
enc_resp->crtc_id = 0;
drm_modeset_unlock(&dev->mode_config.connection_mutex);
+ if (master)
+ drm_master_put(&master);
enc_resp->encoder_type = encoder->encoder_type;
enc_resp->encoder_id = encoder->base.id;
diff --git a/drivers/gpu/drm/drm_lease.c b/drivers/gpu/drm/drm_lease.c
index 1b156c85d1c8..15bf3a3c76d1 100644
--- a/drivers/gpu/drm/drm_lease.c
+++ b/drivers/gpu/drm/drm_lease.c
@@ -114,27 +114,30 @@ bool _drm_lease_held(struct drm_file *file_priv, int id)
return _drm_lease_held_master(file_priv->master, id);
}
-bool drm_lease_held(struct drm_file *file_priv, int id)
+bool drm_lease_held_master(struct drm_master *master, int id)
{
- struct drm_master *master;
bool ret;
- if (!file_priv)
+ if (!master || !master->lessor)
return true;
- master = drm_file_get_master(file_priv);
- if (!master)
- return true;
- if (!master->lessor) {
- ret = true;
- goto out;
- }
mutex_lock(&master->dev->mode_config.idr_mutex);
ret = _drm_lease_held_master(master, id);
mutex_unlock(&master->dev->mode_config.idr_mutex);
-out:
- drm_master_put(&master);
+ return ret;
+}
+
+bool drm_lease_held(struct drm_file *file_priv, int id)
+{
+ struct drm_master *master;
+ bool ret;
+
+ master = drm_file_get_master(file_priv);
+ ret = drm_lease_held_master(master, id);
+ if (master)
+ drm_master_put(&master);
+
return ret;
}
@@ -150,9 +153,6 @@ uint32_t drm_lease_filter_crtcs(struct drm_file *file_priv,
uint32_t crtcs_in)
int count_in, count_out;
uint32_t crtcs_out = 0;
- if (!file_priv)
- return crtcs_in;
-
master = drm_file_get_mas
[Intel-gfx] [PATCH v8 5/7] drm: avoid circular locks in drm_mode_object_find
__drm_mode_object_find checks if the given drm file holds the required
lease on a object by calling _drm_lease_held. _drm_lease_held in turn
uses drm_file_get_master to access drm_file.master.
However, in a future patch, the drm_file.master_lookup_lock in
drm_file_get_master will be replaced by drm_device.master_rwsem. This
is an issue for two reasons:
1. master_rwsem is sometimes already held when __drm_mode_object_find
is called, which leads to recursive locks on master_rwsem
2. drm_mode_object_find is sometimes called with the modeset_mutex
held, which leads to an inversion of the master_rwsem -->
modeset_mutex lock hierarchy
To fix this, we make __drm_mode_object_find the locked version of
drm_mode_object_find, and wrap calls to __drm_mode_object_find with
locks on master_rwsem. This allows us to safely access drm_file.master
in _drm_lease_held (__drm_mode_object_find is its only caller) without
the use of drm_file_get_master.
Functions that already lock master_rwsem are modified to call
__drm_mode_object_find, whereas functions that haven't locked
master_rwsem should call drm_mode_object_find. These two options
allow us to grab master_rwsem before modeset_mutex (such as in
drm_mode_get_obj_get_properties_ioctl).
This new rule requires more extensive changes to three functions:
drn_connector_lookup, drm_crtc_find, and drm_plane_find. These
functions are only sometimes called with master_rwsem held. Hence, we
have to further split them into locked and unlocked versions that call
__drm_mode_object_find and drm_mode_object_find respectively.
Signed-off-by: Desmond Cheong Zhi Xi
---
drivers/gpu/drm/drm_atomic_uapi.c| 7 ++---
drivers/gpu/drm/drm_color_mgmt.c | 2 +-
drivers/gpu/drm/drm_crtc.c | 5 ++--
drivers/gpu/drm/drm_framebuffer.c| 2 +-
drivers/gpu/drm/drm_lease.c | 21 +--
drivers/gpu/drm/drm_mode_object.c| 28 +---
drivers/gpu/drm/drm_plane.c | 8 +++---
drivers/gpu/drm/drm_property.c | 6 ++---
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 2 +-
include/drm/drm_connector.h | 23
include/drm/drm_crtc.h | 22 +++
include/drm/drm_mode_object.h| 3 +++
include/drm/drm_plane.h | 20 ++
15 files changed, 118 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 909f31833181..cda9a501cf74 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -557,7 +557,7 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
return -EINVAL;
} else if (property == config->prop_crtc_id) {
- struct drm_crtc *crtc = drm_crtc_find(dev, file_priv, val);
+ struct drm_crtc *crtc = __drm_crtc_find(dev, file_priv, val);
if (val && !crtc)
return -EACCES;
@@ -709,7 +709,7 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
int ret;
if (property == config->prop_crtc_id) {
- struct drm_crtc *crtc = drm_crtc_find(dev, file_priv, val);
+ struct drm_crtc *crtc = __drm_crtc_find(dev, file_priv, val);
if (val && !crtc)
return -EACCES;
@@ -1385,7 +1385,8 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
goto out;
}
- obj = drm_mode_object_find(dev, file_priv, obj_id,
DRM_MODE_OBJECT_ANY);
+ obj = __drm_mode_object_find(dev, file_priv, obj_id,
+DRM_MODE_OBJECT_ANY);
if (!obj) {
ret = -ENOENT;
goto out;
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index bb14f488c8f6..9dcb2ccca3ab 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -365,7 +365,7 @@ int drm_mode_gamma_set_ioctl(struct drm_device *dev,
if (!drm_core_check_feature(dev, DRIVER_MODESET))
return -EOPNOTSUPP;
- crtc = drm_crtc_find(dev, file_priv, crtc_lut->crtc_id);
+ crtc = __drm_crtc_find(dev, file_priv, crtc_lut->crtc_id);
if (!crtc)
return -ENOENT;
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 26a77a735905..b1279bb3fa61 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -656,7 +656,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
if (crtc_req->x & 0x || crtc_req->y & 0x)
return -ERANGE;
- crtc = drm_crtc_find(dev, file_priv, crtc_req->crtc_i
[Intel-gfx] [PATCH v8 4/7] drm: avoid races with modesetting rights
In drm_client_modeset.c and drm_fb_helper.c,
drm_master_internal_{acquire,release} are used to avoid races with DRM
userspace. These functions hold onto drm_device.master_rwsem while
committing, and bail if there's already a master.
However, there are other places where modesetting rights can race. A
time-of-check-to-time-of-use error can occur if an ioctl that changes
the modeset has its rights revoked after it validates its permissions,
but before it completes.
There are four places where modesetting permissions can change:
- DROP_MASTER ioctl removes rights for a master and its leases
- REVOKE_LEASE ioctl revokes rights for a specific lease
- SET_MASTER ioctl sets the device master if the master role hasn't
been acquired yet
- drm_open which can create a new master for a device if one does not
currently exist
These races can be avoided using drm_device.master_rwsem: users that
perform modesetting should hold a read lock on the new
drm_device.master_rwsem, and users that change these permissions
should hold a write lock.
To avoid deadlocks with master_rwsem, for ioctls that need to check
for modesetting permissions, but also need to hold a write lock on
master_rwsem to protect some other attribute (or recurses to some
function that holds a write lock, like drm_mode_create_lease_ioctl
which eventually calls drm_master_open), we remove the DRM_MASTER flag
and push the master_rwsem lock and permissions check into the ioctl.
Reported-by: Daniel Vetter
Signed-off-by: Desmond Cheong Zhi Xi
---
drivers/gpu/drm/drm_auth.c | 4
drivers/gpu/drm/drm_ioctl.c | 20 +++-
drivers/gpu/drm/drm_lease.c | 35 ---
include/drm/drm_device.h| 5 +
4 files changed, 48 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c
index 73ade0513ccb..65065f7e1499 100644
--- a/drivers/gpu/drm/drm_auth.c
+++ b/drivers/gpu/drm/drm_auth.c
@@ -120,6 +120,10 @@ int drm_authmagic(struct drm_device *dev, void *data,
DRM_DEBUG("%u\n", auth->magic);
down_write(&dev->master_rwsem);
+ if (unlikely(!drm_is_current_master(file_priv))) {
+ up_write(&dev->master_rwsem);
+ return -EACCES;
+ }
file = idr_find(&file_priv->master->magic_map, auth->magic);
if (file) {
file->authenticated = 1;
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 158629d88319..8bea39ffc5c0 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -386,6 +386,10 @@ static int drm_setversion(struct drm_device *dev, void
*data, struct drm_file *f
int if_version, retcode = 0;
down_write(&dev->master_rwsem);
+ if (unlikely(!drm_is_current_master(file_priv))) {
+ retcode = -EACCES;
+ goto unlock;
+ }
if (sv->drm_di_major != -1) {
if (sv->drm_di_major != DRM_IF_MAJOR ||
sv->drm_di_minor < 0 || sv->drm_di_minor > DRM_IF_MINOR) {
@@ -420,8 +424,9 @@ static int drm_setversion(struct drm_device *dev, void
*data, struct drm_file *f
sv->drm_di_minor = DRM_IF_MINOR;
sv->drm_dd_major = dev->driver->major;
sv->drm_dd_minor = dev->driver->minor;
- up_write(&dev->master_rwsem);
+unlock:
+ up_write(&dev->master_rwsem);
return retcode;
}
@@ -574,12 +579,12 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
DRM_IOCTL_DEF(DRM_IOCTL_GET_STATS, drm_getstats, 0),
DRM_IOCTL_DEF(DRM_IOCTL_GET_CAP, drm_getcap, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SET_CLIENT_CAP, drm_setclientcap, 0),
- DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER),
+ DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, 0),
DRM_IOCTL_DEF(DRM_IOCTL_SET_UNIQUE, drm_invalid_op,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_IOCTL_BLOCK, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_IOCTL_UNBLOCK, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_MASTER),
+ DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, 0),
DRM_LEGACY_IOCTL_DEF(DRM_IOCTL_ADD_MAP, drm_legacy_addmap_ioctl,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_LEGACY_IOCTL_DEF(DRM_IOCTL_RM_MAP, drm_legacy_rmmap_ioctl,
DRM_AUTH),
@@ -706,10 +711,10 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_CRTC_GET_SEQUENCE, drm_crtc_get_sequence_ioctl,
0),
DRM_IOCTL_DEF(DRM_IOCTL_CRTC_QUEUE_SEQUENCE,
drm_crtc_queue_sequence_ioctl, 0),
- DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_LEASE, drm_mode_create_lease_ioctl,
DRM_MASTER),
+ DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_LEASE, drm_mode_create_lease_ioctl,
0),
DRM_IOCTL_DEF(DRM_IOCTL_MODE_LIST_LESSEES, drm_mode_list_lessees_ioctl,
DRM_MASTER),
[Intel-gfx] [PATCH v8 3/7] drm: lock drm_global_mutex earlier in the ioctl handler
In a future patch, a read lock on drm_device.master_rwsem is
held in the ioctl handler before the check for ioctl
permissions. However, this inverts the lock hierarchy of
drm_global_mutex --> master_rwsem.
To avoid this, we do some prep work to grab the drm_global_mutex
before checking for ioctl permissions.
Signed-off-by: Desmond Cheong Zhi Xi
---
drivers/gpu/drm/drm_ioctl.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index d25713b09b80..158629d88319 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -772,19 +772,19 @@ long drm_ioctl_kernel(struct file *file, drm_ioctl_t
*func, void *kdata,
if (drm_dev_is_unplugged(dev))
return -ENODEV;
+ /* Enforce sane locking for modern driver ioctls. */
+ if (unlikely(drm_core_check_feature(dev, DRIVER_LEGACY)) && !(flags &
DRM_UNLOCKED))
+ mutex_lock(&drm_global_mutex);
+
retcode = drm_ioctl_permit(flags, file_priv);
if (unlikely(retcode))
- return retcode;
+ goto out;
- /* Enforce sane locking for modern driver ioctls. */
- if (likely(!drm_core_check_feature(dev, DRIVER_LEGACY)) ||
- (flags & DRM_UNLOCKED))
- retcode = func(dev, kdata, file_priv);
- else {
- mutex_lock(&drm_global_mutex);
- retcode = func(dev, kdata, file_priv);
+ retcode = func(dev, kdata, file_priv);
+
+out:
+ if (unlikely(drm_core_check_feature(dev, DRIVER_LEGACY)) && !(flags &
DRM_UNLOCKED))
mutex_unlock(&drm_global_mutex);
- }
return retcode;
}
EXPORT_SYMBOL(drm_ioctl_kernel);
--
2.25.1
[Intel-gfx] [PATCH v8 2/7] drm: convert drm_device.master_mutex into a rwsem
drm_device.master_mutex currently protects the following:
- drm_device.master
- drm_file.master
- drm_file.was_master
- drm_file.is_master
- drm_master.unique
- drm_master.unique_len
- drm_master.magic_map
There is a clear separation between functions that read or change
these attributes. Hence, convert master_mutex into a rwsem to enable
concurrent readers.
Signed-off-by: Desmond Cheong Zhi Xi
---
drivers/gpu/drm/drm_auth.c| 35 ++-
drivers/gpu/drm/drm_debugfs.c | 4 ++--
drivers/gpu/drm/drm_drv.c | 3 +--
drivers/gpu/drm/drm_ioctl.c | 10 +-
include/drm/drm_auth.h| 6 +++---
include/drm/drm_device.h | 10 ++
include/drm/drm_file.h| 12 ++--
7 files changed, 41 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c
index 60a6b21474b1..73ade0513ccb 100644
--- a/drivers/gpu/drm/drm_auth.c
+++ b/drivers/gpu/drm/drm_auth.c
@@ -64,7 +64,7 @@
static bool drm_is_current_master_locked(struct drm_file *fpriv)
{
lockdep_assert_once(lockdep_is_held(&fpriv->master_lookup_lock) ||
- lockdep_is_held(&fpriv->minor->dev->master_mutex));
+ lockdep_is_held(&fpriv->minor->dev->master_rwsem));
return fpriv->is_master && drm_lease_owner(fpriv->master) ==
fpriv->minor->dev->master;
}
@@ -96,7 +96,7 @@ int drm_getmagic(struct drm_device *dev, void *data, struct
drm_file *file_priv)
struct drm_auth *auth = data;
int ret = 0;
- mutex_lock(&dev->master_mutex);
+ down_write(&dev->master_rwsem);
if (!file_priv->magic) {
ret = idr_alloc(&file_priv->master->magic_map, file_priv,
1, 0, GFP_KERNEL);
@@ -104,7 +104,7 @@ int drm_getmagic(struct drm_device *dev, void *data, struct
drm_file *file_priv)
file_priv->magic = ret;
}
auth->magic = file_priv->magic;
- mutex_unlock(&dev->master_mutex);
+ up_write(&dev->master_rwsem);
DRM_DEBUG("%u\n", auth->magic);
@@ -119,13 +119,13 @@ int drm_authmagic(struct drm_device *dev, void *data,
DRM_DEBUG("%u\n", auth->magic);
- mutex_lock(&dev->master_mutex);
+ down_write(&dev->master_rwsem);
file = idr_find(&file_priv->master->magic_map, auth->magic);
if (file) {
file->authenticated = 1;
idr_replace(&file_priv->master->magic_map, NULL, auth->magic);
}
- mutex_unlock(&dev->master_mutex);
+ up_write(&dev->master_rwsem);
return file ? 0 : -EINVAL;
}
@@ -167,7 +167,7 @@ static int drm_new_set_master(struct drm_device *dev,
struct drm_file *fpriv)
struct drm_master *old_master;
struct drm_master *new_master;
- lockdep_assert_held_once(&dev->master_mutex);
+ lockdep_assert_held_once(&dev->master_rwsem);
WARN_ON(fpriv->is_master);
old_master = fpriv->master;
@@ -249,7 +249,7 @@ int drm_setmaster_ioctl(struct drm_device *dev, void *data,
{
int ret;
- mutex_lock(&dev->master_mutex);
+ down_write(&dev->master_rwsem);
ret = drm_master_check_perm(dev, file_priv);
if (ret)
@@ -281,7 +281,7 @@ int drm_setmaster_ioctl(struct drm_device *dev, void *data,
drm_set_master(dev, file_priv, false);
out_unlock:
- mutex_unlock(&dev->master_mutex);
+ up_write(&dev->master_rwsem);
return ret;
}
@@ -298,7 +298,7 @@ int drm_dropmaster_ioctl(struct drm_device *dev, void *data,
{
int ret;
- mutex_lock(&dev->master_mutex);
+ down_write(&dev->master_rwsem);
ret = drm_master_check_perm(dev, file_priv);
if (ret)
@@ -321,8 +321,9 @@ int drm_dropmaster_ioctl(struct drm_device *dev, void *data,
}
drm_drop_master(dev, file_priv);
+
out_unlock:
- mutex_unlock(&dev->master_mutex);
+ up_write(&dev->master_rwsem);
return ret;
}
@@ -334,7 +335,7 @@ int drm_master_open(struct drm_file *file_priv)
/* if there is no current master make this fd it, but do not create
* any master object for render clients
*/
- mutex_lock(&dev->master_mutex);
+ down_write(&dev->master_rwsem);
if (!dev->master) {
ret = drm_new_set_master(dev, file_priv);
} else {
@@ -342,7 +343,7 @@ int drm_master_open(struct drm_file *file_priv)
file_priv->master = drm_master_get(dev->master);
spin_unlock(&file_priv->master_lookup_lock);
}
- mutex_unlock(&dev->master_mutex);
+ up_write(&dev->master_rwsem);
return ret;
}
@@ -352,7 +353,7 @@ void drm_master_release(struct drm_file *file_priv)
struct drm_device *dev = file_priv->minor->dev;
struct drm_master *master;
- mutex_lock(&dev->master_mutex);
+ down_write(&dev->master_rwsem);
master = file_priv->ma
[Intel-gfx] [PATCH v8 1/7] drm: fix null ptr dereference in drm_master_release
drm_master_release can be called on a drm_file without a master, which results in a null ptr dereference of file_priv->master->magic_map. The three cases are: 1. Error path in drm_open_helper drm_open(): drm_open_helper(): drm_master_open(): drm_new_set_master(); <--- returns -ENOMEM, drm_file.master not set drm_file_free(): drm_master_release(); <--- NULL ptr dereference (file_priv->master->magic_map) 2. Error path in mock_drm_getfile mock_drm_getfile(): anon_inode_getfile(); <--- returns error, drm_file.master not set drm_file_free(): drm_master_release(); <--- NULL ptr dereference (file_priv->master->magic_map) 3. In drm_client_close, as drm_client_open doesn't set up a master drm_file.master is set up in drm_open_helper through the call to drm_master_open, so we mirror it with a call to drm_master_release in drm_close_helper, and remove drm_master_release from drm_file_free to avoid the null ptr dereference. Signed-off-by: Desmond Cheong Zhi Xi --- drivers/gpu/drm/drm_file.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_file.c b/drivers/gpu/drm/drm_file.c index ed25168619fc..90b62f360da1 100644 --- a/drivers/gpu/drm/drm_file.c +++ b/drivers/gpu/drm/drm_file.c @@ -282,9 +282,6 @@ void drm_file_free(struct drm_file *file) drm_legacy_ctxbitmap_flush(dev, file); - if (drm_is_primary_client(file)) - drm_master_release(file); - if (dev->driver->postclose) dev->driver->postclose(dev, file); @@ -305,6 +302,9 @@ static void drm_close_helper(struct file *filp) list_del(&file_priv->lhead); mutex_unlock(&dev->filelist_mutex); + if (drm_is_primary_client(file_priv)) + drm_master_release(file_priv); + drm_file_free(file_priv); } -- 2.25.1
[Intel-gfx] [PATCH v8 0/7] drm: update locking for modesetting
Hi,
Seems that Intel-gfx CI still doesn't like what's going on, so I updated
the series to remove more recursive locking again.
Note: patch 5 touches a number of files, including the Intel and VMware
drivers, but most changes are simply switching a function call to the
appropriate locked/unlocked version.
Overall, this series fixes races with modesetting rights, converts
drm_device.master_mutex into master_rwsem, and removes
drm_file.master_lookup_lock.
- Patch 1: Fix a potential null ptr dereference in drm_master_release
- Patch 2: Convert master_mutex into rwsem (avoids creating a new lock)
- Patch 3: Update global mutex locking in the ioctl handler (avoids
deadlock when grabbing read lock on master_rwsem in drm_ioctl_kernel)
- Patch 4: Plug races with drm modesetting rights
- Patch 5: Modify drm_mode_object_find to fix potential recursive
locking of master_rwsem and lock inversions between modeset_mutex and
master_rwsem
- Patch 6: Remove remaining potential recursive locking of master_rwsem
and lock inversions between modeset_mutex and master_rwsem from calling
drm_lease_held
- Patch 7: Replace master_lookup_lock with master_rwsem
v7 -> v8:
- Avoid calling drm_lease_held in drm_mode_setcrtc and
drm_wait_vblank_ioctl, caught by Intel-gfx CI (patch 6)
v6 -> v7:
- Export __drm_mode_object_find for loadable modules, caught by the
Intel-gfx CI (patch 5)
v5 -> v6:
- Fix recursive locking on master_rwsem, caught by the Intel-gfx CI
(patch 5 & 6)
v4 -> v5:
- Avoid calling drm_file_get_master while holding on to the modeset
mutex, caught by the Intel-gfx CI (patch 5 & 6)
v3 -> v4 (suggested by Daniel Vetter):
- Drop a patch that added an unnecessary master_lookup_lock in
drm_master_release
- Drop a patch that addressed a non-existent race in
drm_is_current_master_locked
- Remove fixes for non-existent null ptr dereferences
- Protect drm_master.magic_map,unique{_len} with master_rwsem instead of
master_lookup_lock
- Drop the patch that moved master_lookup_lock into struct drm_device
- Drop a patch to export task_work_add
- Revert the check for the global mutex in the ioctl handler to use
drm_core_check_feature instead of drm_dev_needs_global_mutex
- Push down master_rwsem locking for selected ioctls to avoid lock
hierarchy inversions, and to allow us to hold write locks on
master_rwsem instead of flushing readers
- Remove master_lookup_lock by replacing it with master_rwsem
v2 -> v3:
- Unexport drm_master_flush, as suggested by Daniel Vetter.
- Merge master_mutex and master_rwsem, as suggested by Daniel Vetter.
- Export task_work_add, reported by kernel test robot.
- Make master_flush static, reported by kernel test robot.
- Move master_lookup_lock into struct drm_device.
- Add a missing lock on master_lookup_lock in drm_master_release.
- Fix a potential race in drm_is_current_master_locked.
- Fix potential null ptr dereferences in drm_{auth, ioctl}.
- Protect magic_map,unique{_len} with master_lookup_lock.
- Convert master_mutex into a rwsem.
- Update global mutex locking in the ioctl handler.
v1 -> v2 (suggested by Daniel Vetter):
- Address an additional race when drm_open runs.
- Switch from SRCU to rwsem to synchronise readers and writers.
- Implement drm_master_flush with task_work so that flushes can be
queued to run before returning to userspace without creating a new
DRM_MASTER_FLUSH ioctl flag.
Best wishes,
Desmond
Desmond Cheong Zhi Xi (7):
drm: fix null ptr dereference in drm_master_release
drm: convert drm_device.master_mutex into a rwsem
drm: lock drm_global_mutex earlier in the ioctl handler
drm: avoid races with modesetting rights
drm: avoid circular locks in drm_mode_object_find
drm: avoid circular locks in drm_lease_held
drm: remove drm_file.master_lookup_lock
drivers/gpu/drm/drm_atomic_uapi.c| 7 +-
drivers/gpu/drm/drm_auth.c | 57 ++--
drivers/gpu/drm/drm_color_mgmt.c | 2 +-
drivers/gpu/drm/drm_crtc.c | 9 +-
drivers/gpu/drm/drm_debugfs.c| 4 +-
drivers/gpu/drm/drm_drv.c| 3 +-
drivers/gpu/drm/drm_encoder.c| 7 +-
drivers/gpu/drm/drm_file.c | 7 +-
drivers/gpu/drm/drm_framebuffer.c| 2 +-
drivers/gpu/drm/drm_internal.h | 1 +
drivers/gpu/drm/drm_ioctl.c | 48 ++
drivers/gpu/drm/drm_lease.c | 94 ++--
drivers/gpu/drm/drm_mode_object.c| 28 +-
drivers/gpu/drm/drm_plane.c | 26 --
drivers/gpu/drm/drm_property.c | 6 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 2 +-
include/drm/drm_auth.h | 6 +-
include/drm/drm_connector.h | 23 +
include/drm/drm_crtc.h | 22 +
include/drm/drm_device.h
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/snps: constify struct intel_mpllb_state arrays harder
== Series Details ==
Series: drm/i915/snps: constify struct intel_mpllb_state arrays harder
URL : https://patchwork.freedesktop.org/series/94021/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10520_full -> Patchwork_20891_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20891_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_create@create-valid-nonaligned:
- {shard-rkl}:[PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-rkl-5/igt@gem_cre...@create-valid-nonaligned.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/shard-rkl-5/igt@gem_cre...@create-valid-nonaligned.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-rapid-movement:
- {shard-rkl}:[SKIP][3] ([fdo#112022]) -> [TIMEOUT][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-rkl-5/igt@kms_cursor_...@pipe-c-cursor-256x85-rapid-movement.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/shard-rkl-5/igt@kms_cursor_...@pipe-c-cursor-256x85-rapid-movement.html
* igt@kms_fbcon_fbt@fbc:
- {shard-rkl}:[SKIP][5] ([i915#1849]) -> [TIMEOUT][6] +1 similar
issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-rkl-5/igt@kms_fbcon_...@fbc.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/shard-rkl-5/igt@kms_fbcon_...@fbc.html
Known issues
Here are the changes found in Patchwork_20891_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#658])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-iclb2/igt@feature_discov...@psr2.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/shard-iclb8/igt@feature_discov...@psr2.html
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][9] ([i915#3002]) +1 similar
issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/shard-kbl7/igt@gem_cre...@create-massive.html
* igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1099]) +2
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-mixed.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][11] -> [TIMEOUT][12] ([i915#2369] /
[i915#2481] / [i915#3070])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-iclb6/igt@gem_...@unwedge-stress.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/shard-iclb5/igt@gem_...@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][13] ([i915#2846])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/shard-apl8/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [PASS][16] -> [SKIP][17] ([fdo#109271])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [PASS][18] -> [FAIL][19] ([i915#2842])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs1.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-snb: NOTRUN -> [SKIP][20] ([fdo#109271]) +230 similar
issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/shard-snb2/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html
* igt@gem_mmap_gtt@cpuset-big-copy:
- shard-glk: [PASS][21] -> [FAIL][22] ([i915#1888] / [i915#307])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-glk4/igt@gem_mmap_...@cpuset-big-copy.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/shard-glk5/igt@gem_mmap_...@cpuset-big-copy.html
* igt@gem_mmap_gtt@cpuset-big-copy-xy:
- shard-iclb: [PASS][23] -> [FAIL][24] ([i915#307])
Re: [Intel-gfx] [PATCH 26/27] drm/i915/guc: Add GuC kernel doc
On 8/18/2021 11:16 PM, Matthew Brost wrote:
Add GuC kernel doc for all structures added thus far for GuC submission
and update the main GuC submission section with the new interface
details.
v2:
- Drop guc_active.lock DOC
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 44 ++---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 19 +++-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 97 ++-
drivers/gpu/drm/i915/i915_request.h | 18 ++--
4 files changed, 128 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 66286ce36c84..80bbdc7810f6 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -156,40 +156,52 @@ struct intel_context {
u8 wa_bb_page; /* if set, page num reserved for context workarounds */
struct {
- /** lock: protects everything in guc_state */
+ /** @lock: protects everything in guc_state */
spinlock_t lock;
/**
-* sched_state: scheduling state of this context using GuC
+* @sched_state: scheduling state of this context using GuC
* submission
*/
u32 sched_state;
/*
-* fences: maintains of list of requests that have a submit
-* fence related to GuC submission
+* @fences: maintains a list of requests are currently being
+* fenced until a GuC operation completes
*/
struct list_head fences;
- /* GuC context blocked fence */
+ /**
+* @blocked_fence: fence used to signal when the blocking of a
+* contexts submissions is complete.
+*/
struct i915_sw_fence blocked_fence;
- /* GuC committed requests */
+ /** @number_committed_requests: number of committed requests */
int number_committed_requests;
- /** requests: active requests on this context */
+ /** @requests: list of active requests on this context */
struct list_head requests;
- /*
-* GuC priority management
-*/
+ /** @prio: the contexts current guc priority */
u8 prio;
+ /**
+* @prio_count: a counter of the number requests inflight in
+* each priority bucket
+*/
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
} guc_state;
struct {
- /* GuC LRC descriptor ID */
+ /**
+* @id: unique handle which is used to communicate information
+* with the GuC about this context, protected by
+* guc->contexts_lock
+*/
u16 id;
-
- /* GuC LRC descriptor reference count */
+ /**
+* @ref: the number of references to the guc_id, when
+* transitioning in and out of zero protected by
+* guc->contexts_lock
+*/
atomic_t ref;
-
- /*
-* GuC ID link - in list when unpinned but guc_id still valid
in GuC
+ /**
+* @link: in guc->guc_id_list when the guc_id has no refs but is
+* still valid, protected by guc->contexts_lock
*/
struct list_head link;
} guc_id;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 2e27fe59786b..112dd29a63fe 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -41,6 +41,10 @@ struct intel_guc {
spinlock_t irq_lock;
unsigned int msg_enabled_mask;
+ /**
+* @outstanding_submission_g2h: number of outstanding G2H related to GuC
+* submission, used to determine if the GT is idle
+*/
atomic_t outstanding_submission_g2h;
struct {
@@ -49,12 +53,16 @@ struct intel_guc {
void (*disable)(struct intel_guc *guc);
} interrupts;
- /*
-* contexts_lock protects the pool of free guc ids and a linked list of
-* guc ids available to be stolen
+ /**
+* @contexts_lock: protects guc_ids, guc_id_list, ce->guc_id.id, and
+* ce->guc_id.ref when transitioning in and out of zero
*/
spinlock_t contexts_lock;
+ /** @guc_ids: used to allocate new guc_ids */
struct ida guc_ids;
+ /**
+* @guc_id_list: list of intel_context with valid guc_ids but no refs
+*/
struct list_head guc_id_list;
bool submission_supported;
@@ -70,7 +78,10 @@ struct intel_guc
Re: [Intel-gfx] [PATCH 25/27] drm/i915/guc: Drop guc_active move everything into guc_state
On 8/18/2021 11:16 PM, Matthew Brost wrote:
Now that we have locking hierarchy of sched_engine->lock ->
ce->guc_state everything from guc_active can be moved into guc_state and
protected the guc_state.lock.
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/intel_context.c | 10 +--
drivers/gpu/drm/i915/gt/intel_context_types.h | 7 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 88 +--
drivers/gpu/drm/i915/i915_trace.h | 2 +-
4 files changed, 49 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 87b84c1d5393..adfe49b53b1b 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -394,9 +394,7 @@ intel_context_init(struct intel_context *ce, struct
intel_engine_cs *engine)
spin_lock_init(&ce->guc_state.lock);
INIT_LIST_HEAD(&ce->guc_state.fences);
-
- spin_lock_init(&ce->guc_active.lock);
- INIT_LIST_HEAD(&ce->guc_active.requests);
+ INIT_LIST_HEAD(&ce->guc_state.requests);
ce->guc_id.id = GUC_INVALID_LRC_ID;
INIT_LIST_HEAD(&ce->guc_id.link);
@@ -521,15 +519,15 @@ struct i915_request
*intel_context_find_active_request(struct intel_context *ce)
GEM_BUG_ON(!intel_engine_uses_guc(ce->engine));
- spin_lock_irqsave(&ce->guc_active.lock, flags);
- list_for_each_entry_reverse(rq, &ce->guc_active.requests,
+ spin_lock_irqsave(&ce->guc_state.lock, flags);
+ list_for_each_entry_reverse(rq, &ce->guc_state.requests,
sched.link) {
if (i915_request_completed(rq))
break;
active = rq;
}
- spin_unlock_irqrestore(&ce->guc_active.lock, flags);
+ spin_unlock_irqrestore(&ce->guc_state.lock, flags);
return active;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 7a1d1537cf67..66286ce36c84 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -172,11 +172,6 @@ struct intel_context {
struct i915_sw_fence blocked_fence;
/* GuC committed requests */
int number_committed_requests;
- } guc_state;
-
- struct {
- /** lock: protects everything in guc_active */
- spinlock_t lock;
/** requests: active requests on this context */
struct list_head requests;
/*
@@ -184,7 +179,7 @@ struct intel_context {
*/
u8 prio;
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
- } guc_active;
+ } guc_state;
struct {
/* GuC LRC descriptor ID */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index c4c018348ac0..4b9a2f3774d5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -827,9 +827,9 @@ __unwind_incomplete_requests(struct intel_context *ce)
unsigned long flags;
spin_lock_irqsave(&sched_engine->lock, flags);
- spin_lock(&ce->guc_active.lock);
+ spin_lock(&ce->guc_state.lock);
list_for_each_entry_safe_reverse(rq, rn,
-&ce->guc_active.requests,
+&ce->guc_state.requests,
sched.link) {
if (i915_request_completed(rq))
continue;
@@ -848,7 +848,7 @@ __unwind_incomplete_requests(struct intel_context *ce)
list_add(&rq->sched.link, pl);
set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
}
- spin_unlock(&ce->guc_active.lock);
+ spin_unlock(&ce->guc_state.lock);
spin_unlock_irqrestore(&sched_engine->lock, flags);
}
@@ -945,10 +945,10 @@ static void guc_cancel_context_requests(struct intel_context *ce)
/* Mark all executing requests as skipped. */
spin_lock_irqsave(&sched_engine->lock, flags);
- spin_lock(&ce->guc_active.lock);
- list_for_each_entry(rq, &ce->guc_active.requests, sched.link)
+ spin_lock(&ce->guc_state.lock);
+ list_for_each_entry(rq, &ce->guc_state.requests, sched.link)
i915_request_put(i915_request_mark_eio(rq));
- spin_unlock(&ce->guc_active.lock);
+ spin_unlock(&ce->guc_state.lock);
spin_unlock_irqrestore(&sched_engine->lock, flags);
}
@@ -1400,7 +1400,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
desc->engine_submit_mask = adjust_engine_mask(engine->class,
engine->mask);
desc->hw_context_desc = ce->lrc.lrca;
- desc->priority
Re: [Intel-gfx] [PATCH 22/27] drm/i915/guc: Drop pin count check trick between sched_disable and re-pin
On 8/18/2021 11:16 PM, Matthew Brost wrote:
Drop pin count check trick between a sched_disable and re-pin, now rely
on the lock and counter of the number of committed requests to determine
if scheduling should be disabled on the context.
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 2 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 49 ---
2 files changed, 34 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index d5d643b04d54..524a35a78bf4 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -169,6 +169,8 @@ struct intel_context {
struct list_head fences;
/* GuC context blocked fence */
struct i915_sw_fence blocked_fence;
+ /* GuC committed requests */
+ int number_committed_requests;
} guc_state;
struct {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 5f77f25322ca..3e90985b0c1b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -248,6 +248,25 @@ static inline void decr_context_blocked(struct
intel_context *ce)
ce->guc_state.sched_state -= SCHED_STATE_BLOCKED;
}
+static inline bool context_has_committed_requests(struct intel_context *ce)
+{
+ return !!ce->guc_state.number_committed_requests;
+}
+
+static inline void incr_context_committed_requests(struct intel_context *ce)
+{
+ lockdep_assert_held(&ce->guc_state.lock);
+ ++ce->guc_state.number_committed_requests;
+ GEM_BUG_ON(ce->guc_state.number_committed_requests < 0);
+}
+
+static inline void decr_context_committed_requests(struct intel_context *ce)
+{
+ lockdep_assert_held(&ce->guc_state.lock);
+ --ce->guc_state.number_committed_requests;
+ GEM_BUG_ON(ce->guc_state.number_committed_requests < 0);
+}
+
static inline bool context_guc_id_invalid(struct intel_context *ce)
{
return ce->guc_id == GUC_INVALID_LRC_ID;
@@ -1751,14 +1770,11 @@ static void guc_context_sched_disable(struct
intel_context *ce)
spin_lock_irqsave(&ce->guc_state.lock, flags);
/*
-* We have to check if the context has been disabled by another thread.
-* We also have to check if the context has been pinned again as another
-* pin operation is allowed to pass this function. Checking the pin
-* count, within ce->guc_state.lock, synchronizes this function with
-* guc_request_alloc ensuring a request doesn't slip through the
-* 'context_pending_disable' fence. Checking within the spin lock (can't
-* sleep) ensures another process doesn't pin this context and generate
-* a request before we set the 'context_pending_disable' flag here.
+* We have to check if the context has been disabled by another thread,
+* check if submssion has been disabled to seal a race with reset and
+* finally check if any more requests have been committed to the
+* context ensursing that a request doesn't slip through the
+* 'context_pending_disable' fence.
*/
enabled = context_enabled(ce);
if (unlikely(!enabled || submission_disabled(guc))) {
@@ -1767,7 +1783,8 @@ static void guc_context_sched_disable(struct
intel_context *ce)
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
goto unpin;
}
- if (unlikely(atomic_add_unless(&ce->pin_count, -2, 2))) {
+ if (unlikely(context_has_committed_requests(ce))) {
+ intel_context_sched_disable_unpin(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
return;
}
@@ -1800,6 +1817,7 @@ static void __guc_context_destroy(struct intel_context
*ce)
ce->guc_prio_count[GUC_CLIENT_PRIORITY_HIGH] ||
ce->guc_prio_count[GUC_CLIENT_PRIORITY_KMD_NORMAL] ||
ce->guc_prio_count[GUC_CLIENT_PRIORITY_NORMAL]);
+ GEM_BUG_ON(ce->guc_state.number_committed_requests);
lrc_fini(ce);
intel_context_fini(ce);
@@ -2030,6 +2048,10 @@ static void remove_from_context(struct i915_request *rq)
spin_unlock_irq(&ce->guc_active.lock);
+ spin_lock_irq(&ce->guc_state.lock);
+ decr_context_committed_requests(ce);
+ spin_unlock_irq(&ce->guc_state.lock);
+
atomic_dec(&ce->guc_id_ref);
i915_request_notify_execute_cb_imm(rq);
}
@@ -2177,15 +2199,7 @@ static int guc_request_alloc(struct i915_request *rq)
* schedule enable or context registration if either G2H is pending
* respectfully. Once a G2H returns, the fence is released that is
* blocking these requests (see
Re: [Intel-gfx] [PATCH 21/27] drm/i915/guc: Proper xarray usage for contexts_lookup
On 8/25/2021 5:41 PM, Matthew Brost wrote:
On Wed, Aug 25, 2021 at 05:44:11PM -0700, Daniele Ceraolo Spurio wrote:
On 8/18/2021 11:16 PM, Matthew Brost wrote:
Lock the xarray and take ref to the context if needed.
v2:
(Checkpatch)
- Add new line after declaration
(Daniel Vetter)
- Correct put / get accounting in xa_for_loops
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 103 +++---
1 file changed, 88 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 509b298e7cf3..5f77f25322ca 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -606,8 +606,18 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
intel_guc *guc)
unsigned long index, flags;
bool pending_disable, pending_enable, deregister, destroyed, banned;
+ xa_lock_irqsave(&guc->context_lookup, flags);
xa_for_each(&guc->context_lookup, index, ce) {
- spin_lock_irqsave(&ce->guc_state.lock, flags);
+ /*
+* Corner case where the ref count on the object is zero but and
+* deregister G2H was lost. In this case we don't touch the ref
+* count and finish the destroy of the context.
+*/
+ bool do_put = kref_get_unless_zero(&ce->ref);
+
+ xa_unlock(&guc->context_lookup);
+
+ spin_lock(&ce->guc_state.lock);
/*
* Once we are at this point submission_disabled() is guaranteed
@@ -623,7 +633,9 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
intel_guc *guc)
banned = context_banned(ce);
init_sched_state(ce);
- spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+ spin_unlock(&ce->guc_state.lock);
+
+ GEM_BUG_ON(!do_put && !destroyed);
if (pending_enable || destroyed || deregister) {
decr_outstanding_submission_g2h(guc);
@@ -646,13 +658,19 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
intel_guc *guc)
}
intel_context_sched_disable_unpin(ce);
decr_outstanding_submission_g2h(guc);
- spin_lock_irqsave(&ce->guc_state.lock, flags);
+
+ spin_lock(&ce->guc_state.lock);
guc_blocked_fence_complete(ce);
- spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+ spin_unlock(&ce->guc_state.lock);
intel_context_put(ce);
}
+
+ if (do_put)
+ intel_context_put(ce);
is it safe to do the put outside the xa_lock, in case the refcount goes to
zero with this? I know it is unlikely because the refcount was > 0 if do_put
is true, but it might've gone down between us checking earlier and now.
It is safe as xa_for_each indicates it is safe to destroy / delete
objects from the array while traversing it.
ok.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
+ xa_lock(&guc->context_lookup);
}
+ xa_unlock_irqrestore(&guc->context_lookup, flags);
}
static inline bool
@@ -873,16 +891,29 @@ void intel_guc_submission_reset(struct intel_guc *guc,
bool stalled)
{
struct intel_context *ce;
unsigned long index;
+ unsigned long flags;
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
return;
}
- xa_for_each(&guc->context_lookup, index, ce)
+ xa_lock_irqsave(&guc->context_lookup, flags);
+ xa_for_each(&guc->context_lookup, index, ce) {
+ if (!kref_get_unless_zero(&ce->ref))
+ continue;
+
+ xa_unlock(&guc->context_lookup);
+
if (intel_context_is_pinned(ce))
__guc_reset_context(ce, stalled);
+ intel_context_put(ce);
+
+ xa_lock(&guc->context_lookup);
+ }
+ xa_unlock_irqrestore(&guc->context_lookup, flags);
+
/* GuC is blown away, drop all references to contexts */
xa_destroy(&guc->context_lookup);
}
@@ -957,11 +988,24 @@ void intel_guc_submission_cancel_requests(struct
intel_guc *guc)
{
struct intel_context *ce;
unsigned long index;
+ unsigned long flags;
+
+ xa_lock_irqsave(&guc->context_lookup, flags);
+ xa_for_each(&guc->context_lookup, index, ce) {
+ if (!kref_get_unless_zero(&ce->ref))
+ continue;
+
+ xa_unlock(&guc->context_lookup);
- xa_for_each(&guc->context_lookup, index, ce)
if (intel_context_is_pinned(ce))
Re: [Intel-gfx] [PATCH 21/27] drm/i915/guc: Proper xarray usage for contexts_lookup
On Wed, Aug 25, 2021 at 05:44:11PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 8/18/2021 11:16 PM, Matthew Brost wrote:
> > Lock the xarray and take ref to the context if needed.
> >
> > v2:
> > (Checkpatch)
> >- Add new line after declaration
> > (Daniel Vetter)
> >- Correct put / get accounting in xa_for_loops
> >
> > Signed-off-by: Matthew Brost
> > ---
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 103 +++---
> > 1 file changed, 88 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 509b298e7cf3..5f77f25322ca 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -606,8 +606,18 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
> > intel_guc *guc)
> > unsigned long index, flags;
> > bool pending_disable, pending_enable, deregister, destroyed, banned;
> > + xa_lock_irqsave(&guc->context_lookup, flags);
> > xa_for_each(&guc->context_lookup, index, ce) {
> > - spin_lock_irqsave(&ce->guc_state.lock, flags);
> > + /*
> > +* Corner case where the ref count on the object is zero but and
> > +* deregister G2H was lost. In this case we don't touch the ref
> > +* count and finish the destroy of the context.
> > +*/
> > + bool do_put = kref_get_unless_zero(&ce->ref);
> > +
> > + xa_unlock(&guc->context_lookup);
> > +
> > + spin_lock(&ce->guc_state.lock);
> > /*
> > * Once we are at this point submission_disabled() is guaranteed
> > @@ -623,7 +633,9 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
> > intel_guc *guc)
> > banned = context_banned(ce);
> > init_sched_state(ce);
> > - spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> > + spin_unlock(&ce->guc_state.lock);
> > +
> > + GEM_BUG_ON(!do_put && !destroyed);
> > if (pending_enable || destroyed || deregister) {
> > decr_outstanding_submission_g2h(guc);
> > @@ -646,13 +658,19 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
> > intel_guc *guc)
> > }
> > intel_context_sched_disable_unpin(ce);
> > decr_outstanding_submission_g2h(guc);
> > - spin_lock_irqsave(&ce->guc_state.lock, flags);
> > +
> > + spin_lock(&ce->guc_state.lock);
> > guc_blocked_fence_complete(ce);
> > - spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> > + spin_unlock(&ce->guc_state.lock);
> > intel_context_put(ce);
> > }
> > +
> > + if (do_put)
> > + intel_context_put(ce);
>
> is it safe to do the put outside the xa_lock, in case the refcount goes to
> zero with this? I know it is unlikely because the refcount was > 0 if do_put
> is true, but it might've gone down between us checking earlier and now.
>
It is safe as xa_for_each indicates it is safe to destroy / delete
objects from the array while traversing it.
> > + xa_lock(&guc->context_lookup);
> > }
> > + xa_unlock_irqrestore(&guc->context_lookup, flags);
> > }
> > static inline bool
> > @@ -873,16 +891,29 @@ void intel_guc_submission_reset(struct intel_guc
> > *guc, bool stalled)
> > {
> > struct intel_context *ce;
> > unsigned long index;
> > + unsigned long flags;
> > if (unlikely(!guc_submission_initialized(guc))) {
> > /* Reset called during driver load? GuC not yet initialised! */
> > return;
> > }
> > - xa_for_each(&guc->context_lookup, index, ce)
> > + xa_lock_irqsave(&guc->context_lookup, flags);
> > + xa_for_each(&guc->context_lookup, index, ce) {
> > + if (!kref_get_unless_zero(&ce->ref))
> > + continue;
> > +
> > + xa_unlock(&guc->context_lookup);
> > +
> > if (intel_context_is_pinned(ce))
> > __guc_reset_context(ce, stalled);
> > + intel_context_put(ce);
> > +
> > + xa_lock(&guc->context_lookup);
> > + }
> > + xa_unlock_irqrestore(&guc->context_lookup, flags);
> > +
> > /* GuC is blown away, drop all references to contexts */
> > xa_destroy(&guc->context_lookup);
> > }
> > @@ -957,11 +988,24 @@ void intel_guc_submission_cancel_requests(struct
> > intel_guc *guc)
> > {
> > struct intel_context *ce;
> > unsigned long index;
> > + unsigned long flags;
> > +
> > + xa_lock_irqsave(&guc->context_lookup, flags);
> > + xa_for_each(&guc->context_lookup, index, ce) {
> > + if (!kref_get_unless_zero(&ce->ref))
> > + continue;
> > +
> > + xa_unlock(&guc->context_lookup);
> > - xa_for_each(&guc->context_lookup, index
Re: [Intel-gfx] [PATCH 21/27] drm/i915/guc: Proper xarray usage for contexts_lookup
On 8/18/2021 11:16 PM, Matthew Brost wrote:
Lock the xarray and take ref to the context if needed.
v2:
(Checkpatch)
- Add new line after declaration
(Daniel Vetter)
- Correct put / get accounting in xa_for_loops
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 103 +++---
1 file changed, 88 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 509b298e7cf3..5f77f25322ca 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -606,8 +606,18 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
intel_guc *guc)
unsigned long index, flags;
bool pending_disable, pending_enable, deregister, destroyed, banned;
+ xa_lock_irqsave(&guc->context_lookup, flags);
xa_for_each(&guc->context_lookup, index, ce) {
- spin_lock_irqsave(&ce->guc_state.lock, flags);
+ /*
+* Corner case where the ref count on the object is zero but and
+* deregister G2H was lost. In this case we don't touch the ref
+* count and finish the destroy of the context.
+*/
+ bool do_put = kref_get_unless_zero(&ce->ref);
+
+ xa_unlock(&guc->context_lookup);
+
+ spin_lock(&ce->guc_state.lock);
/*
* Once we are at this point submission_disabled() is guaranteed
@@ -623,7 +633,9 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
intel_guc *guc)
banned = context_banned(ce);
init_sched_state(ce);
- spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+ spin_unlock(&ce->guc_state.lock);
+
+ GEM_BUG_ON(!do_put && !destroyed);
if (pending_enable || destroyed || deregister) {
decr_outstanding_submission_g2h(guc);
@@ -646,13 +658,19 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
intel_guc *guc)
}
intel_context_sched_disable_unpin(ce);
decr_outstanding_submission_g2h(guc);
- spin_lock_irqsave(&ce->guc_state.lock, flags);
+
+ spin_lock(&ce->guc_state.lock);
guc_blocked_fence_complete(ce);
- spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+ spin_unlock(&ce->guc_state.lock);
intel_context_put(ce);
}
+
+ if (do_put)
+ intel_context_put(ce);
is it safe to do the put outside the xa_lock, in case the refcount goes
to zero with this? I know it is unlikely because the refcount was > 0 if
do_put is true, but it might've gone down between us checking earlier
and now.
+ xa_lock(&guc->context_lookup);
}
+ xa_unlock_irqrestore(&guc->context_lookup, flags);
}
static inline bool
@@ -873,16 +891,29 @@ void intel_guc_submission_reset(struct intel_guc *guc,
bool stalled)
{
struct intel_context *ce;
unsigned long index;
+ unsigned long flags;
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
return;
}
- xa_for_each(&guc->context_lookup, index, ce)
+ xa_lock_irqsave(&guc->context_lookup, flags);
+ xa_for_each(&guc->context_lookup, index, ce) {
+ if (!kref_get_unless_zero(&ce->ref))
+ continue;
+
+ xa_unlock(&guc->context_lookup);
+
if (intel_context_is_pinned(ce))
__guc_reset_context(ce, stalled);
+ intel_context_put(ce);
+
+ xa_lock(&guc->context_lookup);
+ }
+ xa_unlock_irqrestore(&guc->context_lookup, flags);
+
/* GuC is blown away, drop all references to contexts */
xa_destroy(&guc->context_lookup);
}
@@ -957,11 +988,24 @@ void intel_guc_submission_cancel_requests(struct
intel_guc *guc)
{
struct intel_context *ce;
unsigned long index;
+ unsigned long flags;
+
+ xa_lock_irqsave(&guc->context_lookup, flags);
+ xa_for_each(&guc->context_lookup, index, ce) {
+ if (!kref_get_unless_zero(&ce->ref))
+ continue;
+
+ xa_unlock(&guc->context_lookup);
- xa_for_each(&guc->context_lookup, index, ce)
if (intel_context_is_pinned(ce))
guc_cancel_context_requests(ce);
+ intel_context_put(ce);
+
+ xa_lock(&guc->context_lookup);
+ }
+ xa_unlock_irqrestore(&guc->context_lookup, flags);
+
guc_cancel_sched_engine_requests(guc->sched_engine);
/* GuC is blown away, drop all references to contexts */
@@ -2850,21 +2894,28 @@ void intel
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable -Wsometimes-uninitialized
== Series Details == Series: drm/i915: Enable -Wsometimes-uninitialized URL : https://patchwork.freedesktop.org/series/94015/ State : success == Summary == CI Bug Log - changes from CI_DRM_10520_full -> Patchwork_20890_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20890_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@psr2: - shard-iclb: [PASS][1] -> [SKIP][2] ([i915#658]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-iclb2/igt@feature_discov...@psr2.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/shard-iclb1/igt@feature_discov...@psr2.html * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/shard-snb5/igt@gem_cre...@create-massive.html - shard-kbl: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/shard-kbl6/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2410]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-tglb6/igt@gem_ctx_persiste...@many-contexts.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/shard-tglb2/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_eio@in-flight-suspend: - shard-kbl: [PASS][8] -> [DMESG-WARN][9] ([i915#180]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-kbl7/igt@gem_...@in-flight-suspend.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/shard-kbl3/igt@gem_...@in-flight-suspend.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2846]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-kbl1/igt@gem_exec_f...@basic-deadline.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/shard-kbl4/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-tglb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/shard-tglb6/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: NOTRUN -> [FAIL][14] ([i915#2842]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][15] -> [SKIP][16] ([fdo#109271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][17] -> [FAIL][18] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/shard-kbl1/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#2842]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_whisper@basic-contexts-forked: - shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([i915#1895]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-iclb2/igt@gem_exec_whis...@basic-contexts-forked.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/shard-iclb1/igt@gem_exec_whis...@basic-contexts-forked.html * igt@gem_exec_whisper@basic-normal: - shard-glk: [PASS][23] -> [DMESG-WARN][24] ([i915#118] / [i915#95]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-glk3/igt@gem_exec_whis...@basic-normal.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/shard-glk4/igt@gem_exec_whis...@basic-normal.html * igt@gem_mmap_gtt@cpuset-big-copy-xy: - shard-iclb: [PASS][25] -> [FAIL][26] ([i915#307]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-icl
Re: [Intel-gfx] [PATCH] drm/i915: Clean up disabled warnings
On 8/25/2021 4:03 PM, Nick Desaulniers wrote:
On Tue, Aug 24, 2021 at 4:23 PM Nathan Chancellor wrote:
i915 enables a wider set of warnings with '-Wall -Wextra' then disables
several with cc-disable-warning. If an unknown flag gets added to
KBUILD_CFLAGS when building with clang, all subsequent calls to
cc-{disable-warning,option} will fail, meaning that all of these
warnings do not get disabled [1].
A separate series will address the root cause of the issue by not adding
these flags when building with clang [2]; however, the symptom of these
extra warnings appearing can be addressed separately by just removing
the calls to cc-disable-warning, which makes the build ever so slightly
faster because the compiler does not need to be called as much before
building.
The following warnings are supported by GCC 4.9 and clang 10.0.1, which
are the minimum supported versions of these compilers so the call to
cc-disable-warning is not necessary. Masahiro cleaned this up for the
reset of the kernel in commit 4c8dd95a723d ("kbuild: add some extra
warning flags unconditionally").
* -Wmissing-field-initializers
* -Wsign-compare
* -Wtype-limits
* -Wunused-parameter
-Wunused-but-set-variable was implemented in clang 13.0.0 and
-Wframe-address was implemented in clang 12.0.0 so the
cc-disable-warning calls are kept for these two warnings.
Lastly, -Winitializer-overrides is clang's version of -Woverride-init,
which is disabled for the specific files that are problematic. clang
added a compatibility alias in clang 8.0.0 so -Winitializer-overrides
can be removed.
[1]: https://lore.kernel.org/r/202108210311.cbtcgoul-...@intel.com/
[2]: https://lore.kernel.org/r/20210824022640.2170859-1-nat...@kernel.org/
Signed-off-by: Nathan Chancellor
Thanks for the patch! Do you need to re-ping, rebase, or resend that
other series?
Reviewed-by: Nick Desaulniers
I assume you mean the series below rather than above? I sent this patch
right after that series and it has one set of reviews so I am hoping the
i915 maintainers will pick them up soon so this one can be applied
afterwards or resent.
Thank you for the review!
Cheers,
Nathan
---
NOTE: This is based on my series to enable -Wsometimes-initialized here:
https://lore.kernel.org/r/20210824225427.2065517-1-nat...@kernel.org/
I sent it separately as this can go into whatever release but I would
like for that series to go into 5.15.
drivers/gpu/drm/i915/Makefile | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 335ba9f43d8f..6b38547543b1 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -13,13 +13,11 @@
# will most likely get a sudden build breakage... Hopefully we will fix
# new warnings before CI updates!
subdir-ccflags-y := -Wall -Wextra
-subdir-ccflags-y += $(call cc-disable-warning, unused-parameter)
-subdir-ccflags-y += $(call cc-disable-warning, type-limits)
-subdir-ccflags-y += $(call cc-disable-warning, missing-field-initializers)
+subdir-ccflags-y += -Wno-unused-parameter
+subdir-ccflags-y += -Wno-type-limits
+subdir-ccflags-y += -Wno-missing-field-initializers
+subdir-ccflags-y += -Wno-sign-compare
subdir-ccflags-y += $(call cc-disable-warning, unused-but-set-variable)
-# clang warnings
-subdir-ccflags-y += $(call cc-disable-warning, sign-compare)
-subdir-ccflags-y += $(call cc-disable-warning, initializer-overrides)
subdir-ccflags-y += $(call cc-disable-warning, frame-address)
subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
base-commit: fb43ebc83e069625cfeeb2490efc3ffa0013bfa4
prerequisite-patch-id: 31c28450ed7e8785dce967a16db6d52eff3d7d6d
prerequisite-patch-id: 372dfa0e07249f207acc1942ab0e39b13ff229b2
prerequisite-patch-id: 1a585fa6cda50c32ad1e3ac8235d3cff1b599978
--
2.33.0
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: remove duplicate include
== Series Details == Series: drm/i915: remove duplicate include URL : https://patchwork.freedesktop.org/series/94016/ State : success == Summary == CI Bug Log - changes from CI_DRM_10520_full -> Patchwork_20889_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20889_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@psr2: - shard-iclb: [PASS][1] -> [SKIP][2] ([i915#658]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-iclb2/igt@feature_discov...@psr2.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-iclb3/igt@feature_discov...@psr2.html * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-snb5/igt@gem_cre...@create-massive.html - shard-kbl: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-kbl2/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2410]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-tglb6/igt@gem_ctx_persiste...@many-contexts.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-tglb6/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_eio@reset-stress: - shard-skl: [PASS][8] -> [DMESG-WARN][9] ([i915#1982]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-skl6/igt@gem_...@reset-stress.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-skl7/igt@gem_...@reset-stress.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][10] ([i915#2846]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-apl2/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none@vcs1: - shard-kbl: NOTRUN -> [FAIL][11] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html - shard-kbl: [PASS][13] -> [SKIP][14] ([fdo#109271]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][15] -> [FAIL][16] ([i915#2842]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-kbl4/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_mmap_gtt@cpuset-basic-small-copy-odd: - shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2428]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-iclb6/igt@gem_mmap_...@cpuset-basic-small-copy-odd.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-iclb4/igt@gem_mmap_...@cpuset-basic-small-copy-odd.html * igt@gem_render_copy@yf-tiled-to-vebox-linear: - shard-iclb: NOTRUN -> [SKIP][19] ([i915#768]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-iclb4/igt@gem_render_c...@yf-tiled-to-vebox-linear.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3323]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-apl6/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy@fixed: - shard-iclb: NOTRUN -> [SKIP][21] ([i915#3922]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-iclb4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-b...@fixed.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][22] -> [DMESG-WARN][23] ([i915#1436] / [i915#716]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/shard-skl9/igt@gen9_exec_pa...@allowed-single.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/shard-skl5/igt@gen9_exec_pa...@allowed-single.html * igt@gen9_exec_parse@batch-invalid-length: -
Re: [Intel-gfx] [PATCH 23/27] drm/i915/guc: Move GuC priority fields in context under guc_active
On Wed, Aug 25, 2021 at 02:51:11PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 8/18/2021 11:16 PM, Matthew Brost wrote:
> > Move GuC management fields in context under guc_active struct as this is
> > where the lock that protects theses fields lives. Also only set guc_prio
> > field once during context init.
>
> Can you explain what we gain by setting that only on first pin? AFAICS
> re-setting it doesn't hurt and we would cover the case where a context
> priority gets updated while the context is idle. I know the request
> submission would eventually update the prio so there is no bug, but that
> then requires an extra H2G.
>
> >
> > Fixes: ee242ca704d3 ("drm/i915/guc: Implement GuC priority management")
> > Signed-off-by: Matthew Brost
> > Cc:
> > ---
> > drivers/gpu/drm/i915/gt/intel_context_types.h | 12 ++--
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 68 +++
> > drivers/gpu/drm/i915/i915_trace.h | 2 +-
> > 3 files changed, 45 insertions(+), 37 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > index 524a35a78bf4..9fb0480ccf3b 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > @@ -112,6 +112,7 @@ struct intel_context {
> > #define CONTEXT_FORCE_SINGLE_SUBMISSION 7
> > #define CONTEXT_NOPREEMPT 8
> > #define CONTEXT_LRCA_DIRTY9
> > +#define CONTEXT_GUC_INIT 10
> > struct {
> > u64 timeout_us;
> > @@ -178,6 +179,11 @@ struct intel_context {
> > spinlock_t lock;
> > /** requests: active requests on this context */
> > struct list_head requests;
> > + /*
> > +* GuC priority management
> > +*/
> > + u8 prio;
> > + u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
> > } guc_active;
> > /* GuC LRC descriptor ID */
> > @@ -191,12 +197,6 @@ struct intel_context {
> > */
> > struct list_head guc_id_link;
> > - /*
> > -* GuC priority management
> > -*/
> > - u8 guc_prio;
> > - u32 guc_prio_count[GUC_CLIENT_PRIORITY_NUM];
> > -
> > #ifdef CONFIG_DRM_I915_SELFTEST
> > /**
> > * @drop_schedule_enable: Force drop of schedule enable G2H for selftest
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 3e90985b0c1b..bb90bedb1305 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -1369,8 +1369,6 @@ static void guc_context_policy_init(struct
> > intel_engine_cs *engine,
> > desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
> > }
> > -static inline u8 map_i915_prio_to_guc_prio(int prio);
> > -
> > static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
> > {
> > struct intel_engine_cs *engine = ce->engine;
> > @@ -1378,8 +1376,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
> > bool loop)
> > struct intel_guc *guc = &engine->gt->uc.guc;
> > u32 desc_idx = ce->guc_id;
> > struct guc_lrc_desc *desc;
> > - const struct i915_gem_context *ctx;
> > - int prio = I915_CONTEXT_DEFAULT_PRIORITY;
> > bool context_registered;
> > intel_wakeref_t wakeref;
> > int ret = 0;
> > @@ -1396,12 +1392,6 @@ static int guc_lrc_desc_pin(struct intel_context
> > *ce, bool loop)
> > context_registered = lrc_desc_registered(guc, desc_idx);
> > - rcu_read_lock();
> > - ctx = rcu_dereference(ce->gem_context);
> > - if (ctx)
> > - prio = ctx->sched.priority;
> > - rcu_read_unlock();
> > -
> > reset_lrc_desc(guc, desc_idx);
> > set_lrc_desc_registered(guc, desc_idx, ce);
> > @@ -1410,8 +1400,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
> > bool loop)
> > desc->engine_submit_mask = adjust_engine_mask(engine->class,
> > engine->mask);
> > desc->hw_context_desc = ce->lrc.lrca;
> > - ce->guc_prio = map_i915_prio_to_guc_prio(prio);
> > - desc->priority = ce->guc_prio;
> > + desc->priority = ce->guc_active.prio;
> > desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
> > guc_context_policy_init(engine, desc);
> > @@ -1813,10 +1802,10 @@ static inline void guc_lrc_desc_unpin(struct
> > intel_context *ce)
> > static void __guc_context_destroy(struct intel_context *ce)
> > {
> > - GEM_BUG_ON(ce->guc_prio_count[GUC_CLIENT_PRIORITY_KMD_HIGH] ||
> > - ce->guc_prio_count[GUC_CLIENT_PRIORITY_HIGH] ||
> > - ce->guc_prio_count[GUC_CLIENT_PRIORITY_KMD_NORMAL] ||
> > - ce->guc_prio_count[GUC_CLIENT_PRIORITY_NORMAL]);
> > + GEM_BUG_ON(ce->guc_active.prio_count[GUC_CLIENT_PRIORITY_KMD_HIGH] ||
> > + ce->guc_active.prio_count[GUC_CLIENT_PRIORITY_HIGH] ||
> > +
Re: [Intel-gfx] [PATCH 23/27] drm/i915/guc: Move GuC priority fields in context under guc_active
On Wed, Aug 25, 2021 at 02:51:11PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 8/18/2021 11:16 PM, Matthew Brost wrote:
> > Move GuC management fields in context under guc_active struct as this is
> > where the lock that protects theses fields lives. Also only set guc_prio
> > field once during context init.
>
> Can you explain what we gain by setting that only on first pin? AFAICS
> re-setting it doesn't hurt and we would cover the case where a context
> priority gets updated while the context is idle. I know the request
> submission would eventually update the prio so there is no bug, but that
> then requires an extra H2G.
>
Contexts really shouldn't be getting registred and deregistered, so
real need to set this field on each register. Also the priority really
shouldn't be getting all the regularly. IMO this is the correct place,
so I moved it. Lastly, a subsequent patch will also use
guc_context_init() so the helper makes a bit more sense.
Matt
> >
> > Fixes: ee242ca704d3 ("drm/i915/guc: Implement GuC priority management")
> > Signed-off-by: Matthew Brost
> > Cc:
> > ---
> > drivers/gpu/drm/i915/gt/intel_context_types.h | 12 ++--
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 68 +++
> > drivers/gpu/drm/i915/i915_trace.h | 2 +-
> > 3 files changed, 45 insertions(+), 37 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > index 524a35a78bf4..9fb0480ccf3b 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > @@ -112,6 +112,7 @@ struct intel_context {
> > #define CONTEXT_FORCE_SINGLE_SUBMISSION 7
> > #define CONTEXT_NOPREEMPT 8
> > #define CONTEXT_LRCA_DIRTY9
> > +#define CONTEXT_GUC_INIT 10
> > struct {
> > u64 timeout_us;
> > @@ -178,6 +179,11 @@ struct intel_context {
> > spinlock_t lock;
> > /** requests: active requests on this context */
> > struct list_head requests;
> > + /*
> > +* GuC priority management
> > +*/
> > + u8 prio;
> > + u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
> > } guc_active;
> > /* GuC LRC descriptor ID */
> > @@ -191,12 +197,6 @@ struct intel_context {
> > */
> > struct list_head guc_id_link;
> > - /*
> > -* GuC priority management
> > -*/
> > - u8 guc_prio;
> > - u32 guc_prio_count[GUC_CLIENT_PRIORITY_NUM];
> > -
> > #ifdef CONFIG_DRM_I915_SELFTEST
> > /**
> > * @drop_schedule_enable: Force drop of schedule enable G2H for selftest
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 3e90985b0c1b..bb90bedb1305 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -1369,8 +1369,6 @@ static void guc_context_policy_init(struct
> > intel_engine_cs *engine,
> > desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
> > }
> > -static inline u8 map_i915_prio_to_guc_prio(int prio);
> > -
> > static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
> > {
> > struct intel_engine_cs *engine = ce->engine;
> > @@ -1378,8 +1376,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
> > bool loop)
> > struct intel_guc *guc = &engine->gt->uc.guc;
> > u32 desc_idx = ce->guc_id;
> > struct guc_lrc_desc *desc;
> > - const struct i915_gem_context *ctx;
> > - int prio = I915_CONTEXT_DEFAULT_PRIORITY;
> > bool context_registered;
> > intel_wakeref_t wakeref;
> > int ret = 0;
> > @@ -1396,12 +1392,6 @@ static int guc_lrc_desc_pin(struct intel_context
> > *ce, bool loop)
> > context_registered = lrc_desc_registered(guc, desc_idx);
> > - rcu_read_lock();
> > - ctx = rcu_dereference(ce->gem_context);
> > - if (ctx)
> > - prio = ctx->sched.priority;
> > - rcu_read_unlock();
> > -
> > reset_lrc_desc(guc, desc_idx);
> > set_lrc_desc_registered(guc, desc_idx, ce);
> > @@ -1410,8 +1400,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
> > bool loop)
> > desc->engine_submit_mask = adjust_engine_mask(engine->class,
> > engine->mask);
> > desc->hw_context_desc = ce->lrc.lrca;
> > - ce->guc_prio = map_i915_prio_to_guc_prio(prio);
> > - desc->priority = ce->guc_prio;
> > + desc->priority = ce->guc_active.prio;
> > desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
> > guc_context_policy_init(engine, desc);
> > @@ -1813,10 +1802,10 @@ static inline void guc_lrc_desc_unpin(struct
> > intel_context *ce)
> > static void __guc_context_destroy(struct intel_context *ce)
> > {
> > - GEM_BUG_ON(ce->guc_prio_count[GUC_CLIENT_PRIORITY_KMD_HIGH] ||
> > - ce->guc_prio_count[GUC_CL
Re: [Intel-gfx] [PATCH] drm/i915/dg2: Memory latency values from pcode must be doubled
On Fri, Aug 20, 2021 at 03:57:10PM -0700, Matt Roper wrote: > The memory latency values returned by pcode on DG2 are in units of "2 > usec" rather than 1 usec on all other platforms. I.e., we need to > double the value returned by pcode to obtain the true latency value. > > The bspec wording here was a bit ambiguous as to whether it wanted us to > multiply or divide the pcode value by two, but we confirmed offline with > the hardware team that we need to double the value the pcode gives us; > this change is intended to support a larger range of potential latency > values. > > Bspec: 49326 > Signed-off-by: Matt Roper Reviewed-by: Harish Chegondi > --- > drivers/gpu/drm/i915/intel_pm.c | 29 +++-- > 1 file changed, 15 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 65bc3709f54c..cfc41f8fa74a 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2859,6 +2859,7 @@ static void intel_read_wm_latency(struct > drm_i915_private *dev_priv, > u32 val; > int ret, i; > int level, max_level = ilk_wm_max_level(dev_priv); > + int mult = IS_DG2(dev_priv) ? 2 : 1; > > /* read the first set of memory latencies[0:3] */ > val = 0; /* data0 to be programmed to 0 for first set */ > @@ -2872,13 +2873,13 @@ static void intel_read_wm_latency(struct > drm_i915_private *dev_priv, > return; > } > > - wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; > - wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK; > - wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK; > - wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK; > + wm[0] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[1] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & > + GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[2] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & > + GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[3] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & > + GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > > /* read the second set of memory latencies[4:7] */ > val = 1; /* data0 to be programmed to 1 for second set */ > @@ -2891,13 +2892,13 @@ static void intel_read_wm_latency(struct > drm_i915_private *dev_priv, > return; > } > > - wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; > - wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK; > - wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK; > - wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK; > + wm[4] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[5] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & > + GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[6] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & > + GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & > + GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > > /* >* If a level n (n > 1) has a 0us latency, all levels m (m >= n) > -- > 2.25.4 >
Re: [Intel-gfx] [PATCH 23/27] drm/i915/guc: Move GuC priority fields in context under guc_active
On 8/18/2021 11:16 PM, Matthew Brost wrote:
Move GuC management fields in context under guc_active struct as this is
where the lock that protects theses fields lives. Also only set guc_prio
field once during context init.
Can you explain what we gain by setting that only on first pin? AFAICS
re-setting it doesn't hurt and we would cover the case where a context
priority gets updated while the context is idle. I know the request
submission would eventually update the prio so there is no bug, but that
then requires an extra H2G.
Fixes: ee242ca704d3 ("drm/i915/guc: Implement GuC priority management")
Signed-off-by: Matthew Brost
Cc:
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 12 ++--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 68 +++
drivers/gpu/drm/i915/i915_trace.h | 2 +-
3 files changed, 45 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 524a35a78bf4..9fb0480ccf3b 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -112,6 +112,7 @@ struct intel_context {
#define CONTEXT_FORCE_SINGLE_SUBMISSION 7
#define CONTEXT_NOPREEMPT 8
#define CONTEXT_LRCA_DIRTY9
+#define CONTEXT_GUC_INIT 10
struct {
u64 timeout_us;
@@ -178,6 +179,11 @@ struct intel_context {
spinlock_t lock;
/** requests: active requests on this context */
struct list_head requests;
+ /*
+* GuC priority management
+*/
+ u8 prio;
+ u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
} guc_active;
/* GuC LRC descriptor ID */
@@ -191,12 +197,6 @@ struct intel_context {
*/
struct list_head guc_id_link;
- /*
-* GuC priority management
-*/
- u8 guc_prio;
- u32 guc_prio_count[GUC_CLIENT_PRIORITY_NUM];
-
#ifdef CONFIG_DRM_I915_SELFTEST
/**
* @drop_schedule_enable: Force drop of schedule enable G2H for selftest
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 3e90985b0c1b..bb90bedb1305 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1369,8 +1369,6 @@ static void guc_context_policy_init(struct
intel_engine_cs *engine,
desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
}
-static inline u8 map_i915_prio_to_guc_prio(int prio);
-
static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
{
struct intel_engine_cs *engine = ce->engine;
@@ -1378,8 +1376,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
struct intel_guc *guc = &engine->gt->uc.guc;
u32 desc_idx = ce->guc_id;
struct guc_lrc_desc *desc;
- const struct i915_gem_context *ctx;
- int prio = I915_CONTEXT_DEFAULT_PRIORITY;
bool context_registered;
intel_wakeref_t wakeref;
int ret = 0;
@@ -1396,12 +1392,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
context_registered = lrc_desc_registered(guc, desc_idx);
- rcu_read_lock();
- ctx = rcu_dereference(ce->gem_context);
- if (ctx)
- prio = ctx->sched.priority;
- rcu_read_unlock();
-
reset_lrc_desc(guc, desc_idx);
set_lrc_desc_registered(guc, desc_idx, ce);
@@ -1410,8 +1400,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
desc->engine_submit_mask = adjust_engine_mask(engine->class,
engine->mask);
desc->hw_context_desc = ce->lrc.lrca;
- ce->guc_prio = map_i915_prio_to_guc_prio(prio);
- desc->priority = ce->guc_prio;
+ desc->priority = ce->guc_active.prio;
desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
guc_context_policy_init(engine, desc);
@@ -1813,10 +1802,10 @@ static inline void guc_lrc_desc_unpin(struct intel_context *ce)
static void __guc_context_destroy(struct intel_context *ce)
{
- GEM_BUG_ON(ce->guc_prio_count[GUC_CLIENT_PRIORITY_KMD_HIGH] ||
- ce->guc_prio_count[GUC_CLIENT_PRIORITY_HIGH] ||
- ce->guc_prio_count[GUC_CLIENT_PRIORITY_KMD_NORMAL] ||
- ce->guc_prio_count[GUC_CLIENT_PRIORITY_NORMAL]);
+ GEM_BUG_ON(ce->guc_active.prio_count[GUC_CLIENT_PRIORITY_KMD_HIGH] ||
+ ce->guc_active.prio_count[GUC_CLIENT_PRIORITY_HIGH] ||
+ ce->guc_active.prio_count[GUC_CLIENT_PRIORITY_KMD_NORMAL] ||
+ ce->guc_active.prio_count[GUC_CLIENT_PRIORITY_NORMAL]);
GEM_BUG_ON(ce->guc_state.number_committed_requests);
lrc_fini(ce);
@@ -1926,14 +1915,17 @@ static void guc_context
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fdi: refactor some fdi code out of intel_display.c
== Series Details ==
Series: drm/i915/fdi: refactor some fdi code out of intel_display.c
URL : https://patchwork.freedesktop.org/series/94026/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10520 -> Patchwork_20894
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/index.html
Known issues
Here are the changes found in Patchwork_20894 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +12 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][2] -> [FAIL][3] ([i915#1372])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
Participating hosts (40 -> 33)
--
Missing(7): fi-ilk-m540 bat-adls-5 fi-hsw-4200u fi-tgl-1115g4 fi-bsw-cyan
fi-bdw-samus bat-jsl-1
Build changes
-
* Linux: CI_DRM_10520 -> Patchwork_20894
CI-20190529: 20190529
CI_DRM_10520: df6d856ea920279c17e875a80fca47a428fd7fcd @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6185: 5dca04416f50576f464ebbd9aea96edccd7e4eab @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20894: 8e6bd97aa2be037c4bc36c05cf15025a98c5b745 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8e6bd97aa2be drm/i915/fdi: convert BUG()'s to MISSING_CASE()
dd2f514ed896 drm/i915/fdi: move fdi mphy reset and programming to intel_fdi.c
efc363bfa49e drm/i915/fdi: move more FDI stuff to FDI link train hooks
e2f0b2d220b7 drm/i915/fdi: move fdi bc bifurcation functions to intel_fdi.c
b573cd162507 drm/i915/fdi: move intel_update_fdi_pll_freq to intel_fdi.c
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20894/index.html
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fdi: refactor some fdi code out of intel_display.c
== Series Details == Series: drm/i915/fdi: refactor some fdi code out of intel_display.c URL : https://patchwork.freedesktop.org/series/94026/ State : warning == Summary == $ dim checkpatch origin/drm-tip b573cd162507 drm/i915/fdi: move intel_update_fdi_pll_freq to intel_fdi.c e2f0b2d220b7 drm/i915/fdi: move fdi bc bifurcation functions to intel_fdi.c -:125: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() #125: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:218: + BUG(); total: 0 errors, 1 warnings, 0 checks, 117 lines checked efc363bfa49e drm/i915/fdi: move more FDI stuff to FDI link train hooks dd2f514ed896 drm/i915/fdi: move fdi mphy reset and programming to intel_fdi.c 8e6bd97aa2be drm/i915/fdi: convert BUG()'s to MISSING_CASE()
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/runtime_pm: Consolidate runtime_pm functions
== Series Details ==
Series: series starting with [1/4] drm/i915/runtime_pm: Consolidate runtime_pm
functions
URL : https://patchwork.freedesktop.org/series/94023/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10520 -> Patchwork_20893
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20893 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20893, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20893/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20893:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@objects:
- fi-bsw-n3050: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-bsw-n3050/igt@i915_selftest@l...@objects.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20893/fi-bsw-n3050/igt@i915_selftest@l...@objects.html
- fi-bxt-dsi: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-bxt-dsi/igt@i915_selftest@l...@objects.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20893/fi-bxt-dsi/igt@i915_selftest@l...@objects.html
- fi-kbl-soraka: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-kbl-soraka/igt@i915_selftest@l...@objects.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20893/fi-kbl-soraka/igt@i915_selftest@l...@objects.html
- fi-bsw-nick:[PASS][7] -> [DMESG-FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-bsw-nick/igt@i915_selftest@l...@objects.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20893/fi-bsw-nick/igt@i915_selftest@l...@objects.html
- fi-glk-dsi: [PASS][9] -> [DMESG-FAIL][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-glk-dsi/igt@i915_selftest@l...@objects.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20893/fi-glk-dsi/igt@i915_selftest@l...@objects.html
* igt@kms_flip@basic-flip-vs-modeset:
- fi-rkl-11600: NOTRUN -> [SKIP][11]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20893/fi-rkl-11600/igt@kms_f...@basic-flip-vs-modeset.html
Known issues
Here are the changes found in Patchwork_20893 that come from known issues:
### IGT changes ###
Issues hit
* igt@runner@aborted:
- fi-glk-dsi: NOTRUN -> [FAIL][12] ([i915#3363] / [k.org#202321])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20893/fi-glk-dsi/igt@run...@aborted.html
- fi-bsw-nick:NOTRUN -> [FAIL][13] ([fdo#109271] / [i915#1436])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20893/fi-bsw-nick/igt@run...@aborted.html
- fi-kbl-soraka: NOTRUN -> [FAIL][14] ([i915#1436] / [i915#3363])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20893/fi-kbl-soraka/igt@run...@aborted.html
- fi-bxt-dsi: NOTRUN -> [FAIL][15] ([i915#3363])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20893/fi-bxt-dsi/igt@run...@aborted.html
- fi-bsw-n3050: NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#1436])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20893/fi-bsw-n3050/igt@run...@aborted.html
Warnings
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-1115g4: [DMESG-WARN][17] ([i915#1982] / [i915#4002]) ->
[DMESG-WARN][18] ([i915#4002])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20893/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
* igt@i915_pm_rpm@module-reload:
- fi-tgl-1115g4: [INCOMPLETE][19] ([i915#4006]) -> [INCOMPLETE][20]
([i915#1385] / [i915#4006])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-tgl-1115g4/igt@i915_pm_...@module-reload.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20893/fi-tgl-1115g4/igt@i915_pm_...@module-reload.html
* igt@kms_psr@primary_page_flip:
- fi-tgl-1115g4: [SKIP][21] ([i915#1072]) -> [SKIP][22] ([i915#1072] /
[i915#1385])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-tgl-1115g4/igt@kms_psr@primary_page_flip.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20893/fi-tgl-1115g4/igt@kms_psr@primary_page_flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i91
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/runtime_pm: Consolidate runtime_pm functions
== Series Details == Series: series starting with [1/4] drm/i915/runtime_pm: Consolidate runtime_pm functions URL : https://patchwork.freedesktop.org/series/94023/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:expected struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:got struct i915_address_space * +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: conte
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pci: rename functions to have i915_pci prefix
== Series Details == Series: drm/i915/pci: rename functions to have i915_pci prefix URL : https://patchwork.freedesktop.org/series/94022/ State : success == Summary == CI Bug Log - changes from CI_DRM_10520 -> Patchwork_20892 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/index.html Known issues Here are the changes found in Patchwork_20892 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +8 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html * igt@i915_selftest@live@workarounds: - fi-rkl-guc: [PASS][2] -> [DMESG-FAIL][3] ([i915#3928]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html * igt@runner@aborted: - fi-rkl-guc: NOTRUN -> [FAIL][4] ([i915#3928]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/fi-rkl-guc/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928 Participating hosts (40 -> 33) -- Missing(7): fi-ilk-m540 bat-adls-5 fi-hsw-4200u fi-tgl-1115g4 fi-bsw-cyan fi-bdw-samus bat-jsl-1 Build changes - * Linux: CI_DRM_10520 -> Patchwork_20892 CI-20190529: 20190529 CI_DRM_10520: df6d856ea920279c17e875a80fca47a428fd7fcd @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6185: 5dca04416f50576f464ebbd9aea96edccd7e4eab @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20892: 1977b4b9d0f6c6ed6cc56164df221109255d4d1b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1977b4b9d0f6 drm/i915/pci: rename functions to have i915_pci prefix == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20892/index.html
Re: [Intel-gfx] [PATCH 11/27] drm/i915/selftests: Fix memory corruption in live_lrc_isolation
On Tue, Aug 24, 2021 at 05:07:13PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 8/18/2021 11:16 PM, Matthew Brost wrote:
> > GuC submission has exposed an existing memory corruption in
> > live_lrc_isolation. We believe that some writes to the watchdog offsets
> > in the LRC (0x178 & 0x17c) can result in trashing of portions of the
> > address space. With GuC submission there are additional objects which
> > can move the context redzone into the space that is trashed. To
> > workaround this avoid poisoning the watchdog.
>
> This is kind of a worrying explanation, as it implies an HW issue. AFAICS we
> no longer increase the context size with GuC submission, so the redzone
> should be in the same place relative to the base address of the context;
> although it is true that we have more objects in memory due to support the
> GuC, hitting the redzone consistently feels too much like a coincidence.
> When we write the watchdog regs there is a risk we're triggering a watchdog
> interrupt, which will cause the GuC to handle that; on a media reset, the
> GuC overwrites the context with the golden context in the ADS, are we sure
> that's not what is causing this problem?
> Looking in the ADS we set the context memcpy size to:
>
> real_size = intel_engine_context_size(gt, engine_class);
>
> but then we only initialize real_size - SKIP_SIZE(gt->i915), which IMO could
> be the real cause of the bug as the GuC memcpy starts at SKIP_SIZE().
>
Good analysis Daniele. This definitely seems to be the issue as the
below patch appears to have fixed the failing selftest:
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 9f5f43a16182..c19ce71c9de9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -358,6 +358,11 @@ static int guc_prep_golden_context(struct intel_guc *guc,
u8 engine_class, guc_class;
struct guc_gt_system_info *info, local_info;
+ /* Skip execlist and PPGTT registers + HWSP */
+ const u32 lr_hw_context_size = 80 * sizeof(u32);
+ const u32 skip_size = LRC_PPHWSP_SZ * PAGE_SIZE +
+ lr_hw_context_size;
+
/*
* Reserve the memory for the golden contexts and point GuC at it but
* leave it empty for now. The context data will be filled in later
@@ -396,7 +401,7 @@ static int guc_prep_golden_context(struct intel_guc *guc,
if (!blob)
continue;
- blob->ads.eng_state_size[guc_class] = real_size;
+ blob->ads.eng_state_size[guc_class] = real_size - skip_size;
blob->ads.golden_context_lrca[guc_class] = addr_ggtt;
addr_ggtt += alloc_size;
}
@@ -476,7 +481,8 @@ static void guc_init_golden_context(struct intel_guc *guc)
continue;
}
- GEM_BUG_ON(blob->ads.eng_state_size[guc_class] != real_size);
+ GEM_BUG_ON(blob->ads.eng_state_size[guc_class] !=
+ real_size - skip_size);
GEM_BUG_ON(blob->ads.golden_context_lrca[guc_class] !=
addr_ggtt);
addr_ggtt += alloc_size;
This being said, IMO this actually a bug in the GuC firmware as it
basically is doing:
memcpy(some_guc_dest, blob->ads.golden_context_lrca +
guc_calculated_skip_size,
blob->ads.eng_state_size);
IMO if the GuC is applying an internally calculated offset to
blob->ads.golden_context_lrca it should substract that calculated size
from blob->ads.eng_state_size.
e.g. the GuC should be doing:
memcpy(some_guc_dest, blob->ads.golden_context_lrca +
guc_calculated_skip_size,
blob->ads.eng_state_size - guc_calculated_skip_size);
We can bring this up with the GuC firmware team today, but in the
meantime I'll include the above patch in the respin of this series as a
workaround.
Matt
> Daniele
>
> >
> > v2:
> > (Daniel Vetter)
> >- Add VLK ref in code to workaround
> >
> > Signed-off-by: Matthew Brost
> > ---
> > drivers/gpu/drm/i915/gt/selftest_lrc.c | 29 +-
> > 1 file changed, 28 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > index b0977a3b699b..cdc6ae48a1e1 100644
> > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > @@ -1074,6 +1074,32 @@ record_registers(struct intel_context *ce,
> > goto err_after;
> > }
> > +static u32 safe_offset(u32 offset, u32 reg)
> > +{
> > + /* XXX skip testing of watchdog - VLK-22772 */
> > + if (offset == 0x178 || offset == 0x17c)
> > + reg = 0;
> > +
> > + return reg;
> > +}
> > +
> > +static int get_offset_mask(struct intel_engine_cs *engine)
> > +{
> > + if (GRAPHICS_VER(engine->i915) < 12)
> > + return 0xfff;
> > +
> > + switch (engine->class) {
> > + default:
> > + case
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/snps: constify struct intel_mpllb_state arrays harder
== Series Details ==
Series: drm/i915/snps: constify struct intel_mpllb_state arrays harder
URL : https://patchwork.freedesktop.org/series/94021/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10520 -> Patchwork_20891
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/index.html
Known issues
Here are the changes found in Patchwork_20891 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +8 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][2] -> [INCOMPLETE][3] ([i915#2940])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@workarounds:
- fi-rkl-guc: [PASS][4] -> [DMESG-FAIL][5] ([i915#3928])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html
* igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][6] ([fdo#109271] / [i915#1436])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/fi-bsw-nick/igt@run...@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][7] ([i915#3928])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/fi-rkl-guc/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928
Participating hosts (40 -> 33)
--
Missing(7): fi-ilk-m540 bat-adls-5 fi-hsw-4200u fi-tgl-1115g4 fi-bsw-cyan
fi-bdw-samus bat-jsl-1
Build changes
-
* Linux: CI_DRM_10520 -> Patchwork_20891
CI-20190529: 20190529
CI_DRM_10520: df6d856ea920279c17e875a80fca47a428fd7fcd @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6185: 5dca04416f50576f464ebbd9aea96edccd7e4eab @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20891: 03fdae3123b661ea574ae46a8be274ee70266db7 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
03fdae3123b6 drm/i915/snps: constify struct intel_mpllb_state arrays harder
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20891/index.html
Re: [Intel-gfx] [PATCH 20/27] drm/i915/guc: Rework and simplify locking
On Wed, Aug 25, 2021 at 09:52:06AM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 8/18/2021 11:16 PM, Matthew Brost wrote:
> > Rework and simplify the locking with GuC subission. Drop
> > sched_state_no_lock and move all fields under the guc_state.sched_state
> > and protect all these fields with guc_state.lock . This requires
> > changing the locking hierarchy from guc_state.lock -> sched_engine.lock
> > to sched_engine.lock -> guc_state.lock.
> >
> > Signed-off-by: Matthew Brost
> > ---
> > drivers/gpu/drm/i915/gt/intel_context_types.h | 5 +-
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 186 --
> > drivers/gpu/drm/i915/i915_trace.h | 6 +-
> > 3 files changed, 89 insertions(+), 108 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > index c06171ee8792..d5d643b04d54 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > @@ -161,7 +161,7 @@ struct intel_context {
> > * sched_state: scheduling state of this context using GuC
> > * submission
> > */
> > - u16 sched_state;
> > + u32 sched_state;
> > /*
> > * fences: maintains of list of requests that have a submit
> > * fence related to GuC submission
> > @@ -178,9 +178,6 @@ struct intel_context {
> > struct list_head requests;
> > } guc_active;
> > - /* GuC scheduling state flags that do not require a lock. */
> > - atomic_t guc_sched_state_no_lock;
> > -
> > /* GuC LRC descriptor ID */
> > u16 guc_id;
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 053f4485d6e9..509b298e7cf3 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -72,86 +72,23 @@ guc_create_virtual(struct intel_engine_cs **siblings,
> > unsigned int count);
> > #define GUC_REQUEST_SIZE 64 /* bytes */
> > -/*
> > - * Below is a set of functions which control the GuC scheduling state
> > which do
> > - * not require a lock as all state transitions are mutually exclusive.
> > i.e. It
> > - * is not possible for the context pinning code and submission, for the
> > same
> > - * context, to be executing simultaneously. We still need an atomic as it
> > is
> > - * possible for some of the bits to changing at the same time though.
> > - */
> > -#define SCHED_STATE_NO_LOCK_ENABLEDBIT(0)
> > -#define SCHED_STATE_NO_LOCK_PENDING_ENABLE BIT(1)
> > -#define SCHED_STATE_NO_LOCK_REGISTERED BIT(2)
> > -static inline bool context_enabled(struct intel_context *ce)
> > -{
> > - return (atomic_read(&ce->guc_sched_state_no_lock) &
> > - SCHED_STATE_NO_LOCK_ENABLED);
> > -}
> > -
> > -static inline void set_context_enabled(struct intel_context *ce)
> > -{
> > - atomic_or(SCHED_STATE_NO_LOCK_ENABLED, &ce->guc_sched_state_no_lock);
> > -}
> > -
> > -static inline void clr_context_enabled(struct intel_context *ce)
> > -{
> > - atomic_and((u32)~SCHED_STATE_NO_LOCK_ENABLED,
> > - &ce->guc_sched_state_no_lock);
> > -}
> > -
> > -static inline bool context_pending_enable(struct intel_context *ce)
> > -{
> > - return (atomic_read(&ce->guc_sched_state_no_lock) &
> > - SCHED_STATE_NO_LOCK_PENDING_ENABLE);
> > -}
> > -
> > -static inline void set_context_pending_enable(struct intel_context *ce)
> > -{
> > - atomic_or(SCHED_STATE_NO_LOCK_PENDING_ENABLE,
> > - &ce->guc_sched_state_no_lock);
> > -}
> > -
> > -static inline void clr_context_pending_enable(struct intel_context *ce)
> > -{
> > - atomic_and((u32)~SCHED_STATE_NO_LOCK_PENDING_ENABLE,
> > - &ce->guc_sched_state_no_lock);
> > -}
> > -
> > -static inline bool context_registered(struct intel_context *ce)
> > -{
> > - return (atomic_read(&ce->guc_sched_state_no_lock) &
> > - SCHED_STATE_NO_LOCK_REGISTERED);
> > -}
> > -
> > -static inline void set_context_registered(struct intel_context *ce)
> > -{
> > - atomic_or(SCHED_STATE_NO_LOCK_REGISTERED,
> > - &ce->guc_sched_state_no_lock);
> > -}
> > -
> > -static inline void clr_context_registered(struct intel_context *ce)
> > -{
> > - atomic_and((u32)~SCHED_STATE_NO_LOCK_REGISTERED,
> > - &ce->guc_sched_state_no_lock);
> > -}
> > -
> > /*
> >* Below is a set of functions which control the GuC scheduling state
> > which
> > - * require a lock, aside from the special case where the functions are
> > called
> > - * from guc_lrc_desc_pin(). In that case it isn't possible for any other
> > code
> > - * path to be executing on the context.
> > + * require a lock.
> >*/
> > #define SCHED_STATE_WAIT_FOR_DEREGISTER_TO_REGISTER BIT(0)
> > #define SCHED_STATE_DESTRO
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable -Wsometimes-uninitialized
== Series Details ==
Series: drm/i915: Enable -Wsometimes-uninitialized
URL : https://patchwork.freedesktop.org/series/94015/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10520 -> Patchwork_20890
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20890:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_heartbeat:
- {fi-ehl-2}: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-ehl-2/igt@i915_selftest@live@gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/fi-ehl-2/igt@i915_selftest@live@gt_heartbeat.html
Known issues
Here are the changes found in Patchwork_20890 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +13 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@i915_module_load@reload:
- fi-tgl-1115g4: [PASS][4] -> [DMESG-WARN][5] ([i915#4002])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-tgl-1115g4/igt@i915_module_l...@reload.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/fi-tgl-1115g4/igt@i915_module_l...@reload.html
Warnings
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-1115g4: [DMESG-WARN][6] ([i915#1982] / [i915#4002]) ->
[DMESG-WARN][7] ([i915#4002])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4002]: https://gitlab.freedesktop.org/drm/intel/issues/4002
Participating hosts (40 -> 34)
--
Missing(6): fi-ilk-m540 bat-adls-5 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus
bat-jsl-1
Build changes
-
* Linux: CI_DRM_10520 -> Patchwork_20890
CI-20190529: 20190529
CI_DRM_10520: df6d856ea920279c17e875a80fca47a428fd7fcd @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6185: 5dca04416f50576f464ebbd9aea96edccd7e4eab @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20890: 7546facdfedf25a2bcb0ec01664ad1f6222e7527 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7546facdfedf drm/i915: Enable -Wsometimes-uninitialized
e66835a6c56a drm/i915/selftests: Always initialize err in
igt_dmabuf_import_same_driver_lmem()
c048385d19af drm/i915/selftests: Do not use import_obj uninitialized
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20890/index.html
Re: [Intel-gfx] [PATCH v2 2/8] drm/i915/display: Move DRRS code its own file
On Wed, Aug 25, 2021 at 05:23:35PM +, Souza, Jose wrote: > On Wed, 2021-08-25 at 11:55 -0400, Rodrigo Vivi wrote: > > On Tue, Aug 24, 2021 at 05:58:34PM -0700, José Roberto de Souza wrote: > > > intel_dp.c is a 5k lines monster, so moving DRRS out of it to reduce > > > some lines from it. > > > > > > Cc: Jani Nikula > > > Cc: Rodrigo Vivi > > > Signed-off-by: José Roberto de Souza > > > --- > > > Documentation/gpu/i915.rst| 14 +- > > > drivers/gpu/drm/i915/Makefile | 1 + > > > drivers/gpu/drm/i915/display/intel_ddi.c | 1 + > > > .../drm/i915/display/intel_display_debugfs.c | 1 + > > > drivers/gpu/drm/i915/display/intel_dp.c | 467 + > > > drivers/gpu/drm/i915/display/intel_dp.h | 11 - > > > drivers/gpu/drm/i915/display/intel_drrs.c | 477 ++ > > > drivers/gpu/drm/i915/display/intel_drrs.h | 32 ++ > > > .../gpu/drm/i915/display/intel_frontbuffer.c | 1 + > > > 9 files changed, 521 insertions(+), 484 deletions(-) > > > create mode 100644 drivers/gpu/drm/i915/display/intel_drrs.c > > > create mode 100644 drivers/gpu/drm/i915/display/intel_drrs.h > > > > > > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst > > > index 204ebdaadb45a..03021dfa0dd81 100644 > > > --- a/Documentation/gpu/i915.rst > > > +++ b/Documentation/gpu/i915.rst > > > @@ -183,25 +183,25 @@ Frame Buffer Compression (FBC) > > > Display Refresh Rate Switching (DRRS) > > > - > > > > > > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c > > > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c > > > :doc: Display Refresh Rate Switching (DRRS) > > > > > > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c > > > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c > > > :functions: intel_dp_set_drrs_state > > > > > > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c > > > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c > > > :functions: intel_edp_drrs_enable > > > > > > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c > > > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c > > > :functions: intel_edp_drrs_disable > > > > > > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c > > > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c > > > :functions: intel_edp_drrs_invalidate > > > > > > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c > > > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c > > > :functions: intel_edp_drrs_flush > > > > > > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c > > > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c > > > :functions: intel_dp_drrs_init > > > > > > DPIO > > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > > > index fd997dfa5e32c..ee502a2354c44 100644 > > > --- a/drivers/gpu/drm/i915/Makefile > > > +++ b/drivers/gpu/drm/i915/Makefile > > > @@ -213,6 +213,7 @@ i915-y += \ > > > display/intel_dpll.o \ > > > display/intel_dpll_mgr.o \ > > > display/intel_dpt.o \ > > > + display/intel_drrs.o \ > > > display/intel_dsb.o \ > > > display/intel_fb.o \ > > > display/intel_fbc.o \ > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > > index 1ef7a65feb660..828df570a4809 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -40,6 +40,7 @@ > > > #include "intel_dp_link_training.h" > > > #include "intel_dp_mst.h" > > > #include "intel_dpio_phy.h" > > > +#include "intel_drrs.h" > > > #include "intel_dsi.h" > > > #include "intel_fdi.h" > > > #include "intel_fifo_underrun.h" > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > index 8fdacb252bb19..b136a0fc0963b 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > @@ -13,6 +13,7 @@ > > > #include "intel_display_types.h" > > > #include "intel_dmc.h" > > > #include "intel_dp.h" > > > +#include "intel_drrs.h" > > > #include "intel_fbc.h" > > > #include "intel_hdcp.h" > > > #include "intel_hdmi.h" > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > index fd4f7e82e4205..965b888e0e771 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > @@ -55,6 +55,7 @@ > > > #include "intel_dp_mst.h" > > > #include "intel_dpio_phy.h" > > > #include "intel_dpll.h" > > > +#include "intel_drrs.h" > > > #include "intel_fifo_underrun.h" > > > #include "intel_hdcp.h" > > > #include "intel_hdmi.h" > > > @@ -1675,46 +1676,6 @@ intel_dp_compute_hdr_metadata_infoframe_sdp(struct > > > intel_dp
Re: [Intel-gfx] [PATCH rdma-next v4 2/3] lib/scatterlist: Fix wrong update of orig_nents
On Wed, Aug 25, 2021 at 07:59:27AM +0300, Maor Gottlieb wrote: > > On 8/24/2021 10:12 PM, Jason Gunthorpe wrote: > > On Tue, Aug 24, 2021 at 05:25:30PM +0300, Maor Gottlieb wrote: > > > @@ -514,11 +531,13 @@ struct scatterlist > > > *sg_alloc_append_table_from_pages(struct sg_table *sgt, > > > offset = 0; > > > cur_page = j; > > > } > > > - sgt->nents += added_nents; > > > + sgt_append->sgt.nents += added_nents; > > > + sgt_append->sgt.orig_nents = sgt_append->sgt.nents; > > > + sgt_append->prv = s; > > Why is nents being touched here? > > > > Shouldn't it just be > > > > sgt_append->sgt.orig_nents += added_nents; > > sgt_append->prv = s; > > > > ? > > In general yes, but all the sg_alloc_* functions update both > orig_nents and nents (to same value). May be drivers that pass nents > instead of orig_nents to dma_map_sg* (like umem did before this > patch set). So I prefer to set it here as well, also not to break > sg_alloc_table_from_pages_segment which use the same path. This kind > of change could be done very carefully next cycle for all > sg_alloc_*. Ok, interesting Jason
Re: [Intel-gfx] [PATCH v6 01/11] moduleparam: add data member to struct kernel_param
On 8/22/21 6:19 PM, Jim Cromie wrote:
> Add a const void* data member to the struct, to allow attaching
> private data that will be used soon by a setter method (via kp->data)
> to perform more elaborate actions.
>
> To attach the data at compile time, add new macros:
>
> module_param_cb_data() derives from module_param_cb(), adding data
> param, and latter is redefined to use former.
>
> It calls __module_param_call_with_data(), which accepts new data param
> and inits .data with it. Re-define __module_param_call() to use it.
>
> Use of this new data member will be rare, it might be worth redoing
> this as a separate/sub-type to de-bloat the base case.
>
> Signed-off-by: Jim Cromie
> ---
> v6:
> . const void* data -
> . better macro names s/_cbd/_cb_data/, s/_wdata/_with_data/
> . more const, no cast - Willy
> ---
> include/linux/moduleparam.h | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/include/linux/moduleparam.h b/include/linux/moduleparam.h
> index eed280fae433..b8871e514de5 100644
> --- a/include/linux/moduleparam.h
> +++ b/include/linux/moduleparam.h
> @@ -78,6 +78,7 @@ struct kernel_param {
> const struct kparam_string *str;
> const struct kparam_array *arr;
> };
> + const void *data;
> };
>
I wonder if kp->arg can just be used for all this and avoid this patch entirely?
define something like:
struct dd_bitmap_param {
int bitmap;
struct dyndbg_bitdesc *bitmap_arr;
};
and then just pass a pointer to it as 'arg' for module_param_cb? And then in
the get/set callbacks you can use kp->bitmap and kp->bitmap_arr.
Thanks,
-Jason
> extern const struct kernel_param __start___param[], __stop___param[];
> @@ -175,6 +176,9 @@ struct kparam_array
> #define module_param_cb(name, ops, arg, perm)
> \
> __module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, -1, 0)
>
> +#define module_param_cb_data(name, ops, arg, perm, data)
> \
> + __module_param_call_with_data(MODULE_PARAM_PREFIX, name, ops, arg,
> perm, -1, 0, data)
> +
> #define module_param_cb_unsafe(name, ops, arg, perm) \
> __module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, -1,\
> KERNEL_PARAM_FL_UNSAFE)
> @@ -284,14 +288,17 @@ struct kparam_array
>
> /* This is the fundamental function for registering boot/module
> parameters. */
> -#define __module_param_call(prefix, name, ops, arg, perm, level, flags)
> \
> +#define __module_param_call(prefix, name, ops, arg, perm, level, flags) \
> + __module_param_call_with_data(prefix, name, ops, arg, perm, level,
> flags, NULL)
> +
> +#define __module_param_call_with_data(prefix, name, ops, arg, perm, level,
> flags, data) \
> /* Default value instead of permissions? */ \
> static const char __param_str_##name[] = prefix #name; \
> static struct kernel_param __moduleparam_const __param_##name \
> __used __section("__param") \
> __aligned(__alignof__(struct kernel_param)) \
> = { __param_str_##name, THIS_MODULE, ops, \
> - VERIFY_OCTAL_PERMISSIONS(perm), level, flags, { arg } }
> + VERIFY_OCTAL_PERMISSIONS(perm), level, flags, { arg }, data }
>
> /* Obsolete - use module_param_cb() */
> #define module_param_call(name, _set, _get, arg, perm)
> \
>
Re: [Intel-gfx] [PATCH v6 02/11] dyndbg: add DEFINE_DYNAMIC_DEBUG_CATEGORIES and callbacks
On 8/22/21 6:20 PM, Jim Cromie wrote:
> DEFINE_DYNAMIC_DEBUG_CATEGORIES(name, var, bitmap_desc, @bit_descs)
> allows users to define a drm.debug style (bitmap) sysfs interface, and
> to specify the desired mapping from bits[0-N] to the format-prefix'd
> pr_debug()s to be controlled.
>
> DEFINE_DYNAMIC_DEBUG_CATEGORIES(debug_gvt, __gvt_debug,
> "i915/gvt bitmap desc",
> /**
>* search-prefixes, passed to dd-exec_queries
>* defines bits 0-N in order.
>* leading ^ is tacitly inserted (by callback currently)
>* trailing space used here excludes subcats.
>* helper macro needs more work
>* macro to autogen ++$i, 0x%x$i ?
>*/
> _DD_cat_("gvt:cmd: "),
> _DD_cat_("gvt:core: "),
> _DD_cat_("gvt:dpy: "),
> _DD_cat_("gvt:el: "),
> _DD_cat_("gvt:irq: "),
> _DD_cat_("gvt:mm: "),
> _DD_cat_("gvt:mmio: "),
> _DD_cat_("gvt:render: "),
> _DD_cat_("gvt:sched: "));
>
> dynamic_debug.c: add 3 new elements:
>
> - int param_set_dyndbg()
> - int param_get_dyndbg()
> - struct kernel_param_ops param_ops_dyndbg
>
> Following the model of kernel/params.c STANDARD_PARAM_DEFS, All 3 are
> non-static and exported.
>
> dynamic_debug.h:
>
> Add DEFINE_DYNAMIC_DEBUG_CATEGORIES() described above, and a do-nothing stub.
>
> Note that it also calls MODULE_PARM_DESC for the user, but expects the
> user to catenate all the bit-descriptions together (as is done in
> drm.debug), and in the following uses in amdgpu, i915.
>
> This in the hope that someone can offer an auto-incrementing
> label-generating macro, producing "\tbit-4 0x10\t" etc, and can show
> how to apply it to __VA_ARGS__.
>
> Also extern the struct kernel_param param_ops_dyndbg symbol, as is
> done in moduleparams.h for all the STANDARD params.
>
> USAGE NOTES:
>
> Using dyndbg to query on "format ^$prefix" requires that the prefix be
> present in the compiled-in format string; where run-time prefixing is
> used, that format would be "%s...", which is not usefully selectable.
>
> Adding structural query terms (func,file,lineno) could help (module is
> already done), but DEFINE_DYNAMIC_DEBUG_CATEGORIES can't do that now,
> adding it needs a better reason imo.
>
> Dyndbg is completely agnostic wrt the categorization scheme used, to
> play well with any prefix convention already in use. Ad-hoc
> categories and sub-categories are implicitly allowed, author
> discipline and review is expected.
>
> Here are some examples:
>
> "1","2","3" 2 doesn't imply 1.
> otherwize, sorta like printk levels
> "1:","2:","3:"are better, avoiding [1-9]\d+ ambiguity
> "hi:","mid:","low:" are reasonable, and imply independence
> "todo:","rfc:","fixme:" might be handy
> "A:".."Z:"uhm, yeah
>
> Hierarchical classes/categories are natural:
>
> "drm::" is used in later commit
> "drm:::"is a natural extension.
> "drm:atomic:fail:"has been proposed, sounds directly useful
>
> Some properties of a hierarchical category deserve explication:
>
> Trailing spaces matter !
>
> With 1..3-space ("drm: ", "drm:atomic: ", "drm:atomic:fail: "), the
> ":" doesn't terminate the search-space, the trailing space does. So a
> "drm:" search spec will match all DRM categories & subcategories, and
> will not be useful in an interface where all categories are already
> controlled together. That said, "drm:atomic:" & "drm:atomic: " are
> different, and both are useful in cases.
>
> Ad-Hoc sub-categories:
>
> These have a caveat wrt wrapper macros adding prefixes like
> "drm:atomic: "; the trailing space in the prefix means that
> drm_dbg_atomic("fail: ...") pastes as "drm:atomic: fail: ", which
> obviously isn't ideal wrt clear and simple bitmaps.
>
> A possible solution is to have a FOO_() version of every FOO() macro
> which (anti-mnemonically) elides the trailing space, which is normally
> inserted by a modified FOO(). Doing this would enforce a policy
> decision that "debug categories will be space terminated", with an
> pressure-relief valve.
>
> Summarizing:
>
> - "drm:kms: " & "drm:kms:" are different
> - "drm:kms" also different - includes drm:kms2:
> - "drm:kms:\t" also different
> - "drm:kms:*"doesn't work, no wildcard on format atm.
>
> Order matters in DEFINE_DYNAMIC_DEBUG_CATEGORIES(... @bit_descs)
>
> @bit_descs (array) position determines the bit mapping to the prefix,
> so to keep a stable map, new categories or 3rd level categories must
> be added to the end.
>
> Since bits are/will-stay applied 0-N, the later bits can countermand
> the earlier ones, but its tricky - consider;
>
> DD_CATs(... "drm:atomic:", "drm:atomic:fail:" ) // misleading
>
> The 1st search-term is misleading, because it includes (modifies)
> subcategories, but then 2nd overrides it. So don't do that.
>
> For "drm:atomic:fail:" in particular, its best not to add
Re: [Intel-gfx] [PATCH v6 00/11] use DYNAMIC_DEBUG to implement DRM.debug
On 8/22/21 6:19 PM, Jim Cromie wrote: > This patchset does 3 main things. > > Adds DEFINE_DYNAMIC_DEBUG_CATEGORIES to define bitmap => category > control of pr_debugs, and to create their sysfs entries. > > Uses it in amdgpu, i915 to control existing pr_debugs according to > their ad-hoc categorizations. > > Plugs dyndbg into drm-debug framework, in a configurable manner. > > v6: cleans up per v5 feedback, and adds RFC stuff: > > - test_dynamic_debug.ko: uses tracer facility added in v5:8/9 > - prototype print-once & rate-limiting > > Hopefully adding RFC stuff doesnt distract too much. Hi Jim, Yeah, I feel like the RFC patches should be in a separate series unless there is a drm dependency for them? Thanks, -Jason > > Jim Cromie (11): > moduleparam: add data member to struct kernel_param > dyndbg: add DEFINE_DYNAMIC_DEBUG_CATEGORIES and callbacks > i915/gvt: remove spaces in pr_debug "gvt: core:" etc prefixes > i915/gvt: use DEFINE_DYNAMIC_DEBUG_CATEGORIES to create "gvt:core:" > etc categories > amdgpu: use DEFINE_DYNAMIC_DEBUG_CATEGORIES to control categorized > pr_debugs > drm_print: add choice to use dynamic debug in drm-debug > drm_print: instrument drm_debug_enabled > amdgpu_ucode: reduce number of pr_debug calls > nouveau: fold multiple DRM_DEBUG_DRIVERs together > dyndbg: RFC add debug-trace callback, selftest with it. RFC > dyndbg: RFC add print-once and print-ratelimited features. RFC. > > drivers/gpu/drm/Kconfig | 13 + > drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 293 --- > .../gpu/drm/amd/display/dc/core/dc_debug.c| 44 ++- > drivers/gpu/drm/drm_print.c | 49 ++- > drivers/gpu/drm/i915/gvt/Makefile | 4 + > drivers/gpu/drm/i915/gvt/debug.h | 18 +- > drivers/gpu/drm/i915/i915_params.c| 35 ++ > drivers/gpu/drm/nouveau/nouveau_drm.c | 36 +- > include/drm/drm_print.h | 148 ++-- > include/linux/dynamic_debug.h | 81 - > include/linux/moduleparam.h | 11 +- > lib/Kconfig.debug | 11 + > lib/Makefile | 1 + > lib/dynamic_debug.c | 336 -- > lib/test_dynamic_debug.c | 279 +++ > 15 files changed, 1117 insertions(+), 242 deletions(-) > create mode 100644 lib/test_dynamic_debug.c >
Re: [Intel-gfx] [PATCH] drm/i915/guc: drop guc_communication_enabled
On Mon, Aug 23, 2021 at 09:31:37AM -0700, Daniele Ceraolo Spurio wrote:
> The function is only used from within GEM_BUG_ON(), which is causing
> warnings with Wunneeded-internal-declaration in some builds. Since the
> function is a simple wrapper around a CT function, we can just call the
> CT function directly instead.
>
> Fixes: 1fb12c587152 ("drm/i915/guc: skip disabling CTBs before sanitizing the
> GuC")
> Reported-by: kernel test robot
> Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Matthew Brost
> Cc: Matthew Brost
> Cc: John Harrison
> ---
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 11 +++
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index b104fb7607eb..86c318516e14 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -172,11 +172,6 @@ void intel_uc_driver_remove(struct intel_uc *uc)
> __uc_free_load_err_log(uc);
> }
>
> -static inline bool guc_communication_enabled(struct intel_guc *guc)
> -{
> - return intel_guc_ct_enabled(&guc->ct);
> -}
> -
> /*
> * Events triggered while CT buffers are disabled are logged in the
> SCRATCH_15
> * register using the same bits used in the CT message payload. Since our
> @@ -210,7 +205,7 @@ static void guc_get_mmio_msg(struct intel_guc *guc)
> static void guc_handle_mmio_msg(struct intel_guc *guc)
> {
> /* we need communication to be enabled to reply to GuC */
> - GEM_BUG_ON(!guc_communication_enabled(guc));
> + GEM_BUG_ON(!intel_guc_ct_enabled(&guc->ct));
>
> spin_lock_irq(&guc->irq_lock);
> if (guc->mmio_msg) {
> @@ -226,7 +221,7 @@ static int guc_enable_communication(struct intel_guc *guc)
> struct drm_i915_private *i915 = gt->i915;
> int ret;
>
> - GEM_BUG_ON(guc_communication_enabled(guc));
> + GEM_BUG_ON(intel_guc_ct_enabled(&guc->ct));
>
> ret = i915_inject_probe_error(i915, -ENXIO);
> if (ret)
> @@ -662,7 +657,7 @@ static int __uc_resume(struct intel_uc *uc, bool
> enable_communication)
> return 0;
>
> /* Make sure we enable communication if and only if it's disabled */
> - GEM_BUG_ON(enable_communication == guc_communication_enabled(guc));
> + GEM_BUG_ON(enable_communication == intel_guc_ct_enabled(&guc->ct));
>
> if (enable_communication)
> guc_enable_communication(guc);
> --
> 2.33.0
>
Re: [Intel-gfx] [PATCH rdma-next v4 2/3] lib/scatterlist: Fix wrong update of orig_nents
On 8/24/2021 10:12 PM, Jason Gunthorpe wrote: On Tue, Aug 24, 2021 at 05:25:30PM +0300, Maor Gottlieb wrote: @@ -514,11 +531,13 @@ struct scatterlist *sg_alloc_append_table_from_pages(struct sg_table *sgt, offset = 0; cur_page = j; } - sgt->nents += added_nents; + sgt_append->sgt.nents += added_nents; + sgt_append->sgt.orig_nents = sgt_append->sgt.nents; + sgt_append->prv = s; Why is nents being touched here? Shouldn't it just be sgt_append->sgt.orig_nents += added_nents; sgt_append->prv = s; ? In general yes, but all the sg_alloc_* functions update both orig_nents and nents (to same value). May be drivers that pass nents instead of orig_nents to dma_map_sg* (like umem did before this patch set). So I prefer to set it here as well, also not to break sg_alloc_table_from_pages_segment which use the same path. This kind of change could be done very carefully next cycle for all sg_alloc_*. Let me know I can fix it Jason
Re: [Intel-gfx] [PATCH 2/2] drm/amdgpu: Disable PCIE_DPM on Intel RKL Platform
On 8/25/2021 4:46 PM, Koba Ko wrote:
On Wed, Aug 25, 2021 at 6:24 PM Jani Nikula wrote:
On Wed, 25 Aug 2021, Koba Ko wrote:
On Wed, Aug 25, 2021 at 5:22 PM Jani Nikula wrote:
On Wed, 25 Aug 2021, Koba Ko wrote:
AMD polaris GPUs have an issue about audio noise on RKL platform,
they provide a commit to fix but for SMU7-based GPU still
need another module parameter,
For avoiding the module parameter, switch PCI_DPM by determining
intel platform in amd drm driver.
I'll just note that you could have a Tiger Lake PCH combined with a
number of platforms other than Rocket Lake, including not just the
obvious Tiger Lake but also Sky Lake, Kaby Lake, Coffee Lake, and Comet
Lake.
Again, I don't know what the root cause or fix should be, the workaround
presented here impacts a much larger number of platforms than where
you're claiming the issue is.
Hi Jani, thanks for your feedback.
Is there any way to identify the RKL PCH?
I trace the intel_pch.c and can't find the only pch id for RKL.
INTEL_PCH_TGP_DEVICE_ID_TYPE is used by both TGL and RKL.
so it seems that using IS_ROCKETLAKE() is the only way.
I don't think there is a Rocket Lake PCH. But is the problem related to
the PCH or not?
I thought its' not because the issue wouldn't be observed on the TGL platform.
I only tried RKL platform and it use
INTEL_PCH_TGP_DEVICE_ID_TYPE/INTEL_PCH_TGP2_DEVICE_ID_TYPE,
As per AMD guys, they said the issue is only triggered in RKL platform.
The GPU PCI IDs are in i915_pciids.h. See INTEL_RKL_IDS() for
RKL. There's a lot of indirection, but that's what IS_ROCKETLAKE() boils
down to. But again, I'm not sure if that's what you want or not.
Thanks for suggestions,
Just want a way to check if it's a RKL platform,
After tracing the kernel, can check by CPU VENDOR(lacks type), check
igpu(but there're cpus without igpu)
and check pch type(it seems one pch has multiple combinations with CPU).
for check igpu, as per my current understanding, only found RKL CPU with igpu.
Is there a RKL CPU without integrated gpu?
Just for RKL - you could do fetch the x86 info and check
#ifdef CONFIG_X86_64
struct cpuinfo_x86 *c = &cpu_data(0);
// Family/Model check, find the model
(c->x86 == 6 && c->x86_model == INTEL_FAM6_ROCKETLAKE)
#endif
I think we don't use anything like this so far. So Alex should give a
nod as well.
Thanks,
Lijo
BR,
Jani.
Thanks
BR,
Jani.
Fixes: 1a31474cdb48 ("drm/amd/pm: workaround for audio noise issue")
Ref:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Farchives%2Famd-gfx%2F2021-August%2F067413.html&data=04%7C01%7Clijo.lazar%40amd.com%7C888ab428f2bb4f32e4d408d967c4ae08%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637654916721463596%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Bgf14CmIx%2FTOD54LN6dccZL0U5gT9lv9yTw7MfKc2sQ%3D&reserved=0
Signed-off-by: Koba Ko
---
.../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 21 ++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 0541bfc81c1b..346110dd0f51 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -1733,6 +1733,25 @@ static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
return result;
}
+#include
+
+static bool intel_tgp_chk(void)
+{
+ struct pci_dev *pch = NULL;
+ unsigned short id;
+
+ while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
+ if (pch->vendor != PCI_VENDOR_ID_INTEL)
+ continue;
+
+ id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
+ if (id == INTEL_PCH_TGP_DEVICE_ID_TYPE ||
INTEL_PCH_TGP2_DEVICE_ID_TYPE)
PS. This is always true. ;)
got, thanks
+ return true;
+ }
+
+ return false;
+}
+
static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -1758,7 +1777,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ?
false : true;
data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ?
false : true;
- data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ?
false : true;
+ data->pcie_dpm_key_disabled = intel_tgp_chk() || !(hwmgr->feature_mask &
PP_PCIE_DPM_MASK);
/* need to set voltage control types before EVV patching */
data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
--
Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: remove duplicate include
== Series Details ==
Series: drm/i915: remove duplicate include
URL : https://patchwork.freedesktop.org/series/94016/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10520 -> Patchwork_20889
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/index.html
Known issues
Here are the changes found in Patchwork_20889 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +3 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@gem_exec_suspend@basic-s3:
- fi-kbl-8809g: [PASS][2] -> [DMESG-WARN][3] ([i915#3848])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-kbl-8809g/igt@gem_exec_susp...@basic-s3.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/fi-kbl-8809g/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [PASS][4] -> [DMESG-WARN][5] ([i915#3958])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
* igt@runner@aborted:
- fi-kbl-8809g: NOTRUN -> [FAIL][6] ([i915#180] / [i915#3363])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/fi-kbl-8809g/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3848]: https://gitlab.freedesktop.org/drm/intel/issues/3848
[i915#3958]: https://gitlab.freedesktop.org/drm/intel/issues/3958
Participating hosts (40 -> 33)
--
Missing(7): fi-ilk-m540 bat-adls-5 fi-hsw-4200u fi-tgl-1115g4 fi-bsw-cyan
fi-bdw-samus bat-jsl-1
Build changes
-
* Linux: CI_DRM_10520 -> Patchwork_20889
CI-20190529: 20190529
CI_DRM_10520: df6d856ea920279c17e875a80fca47a428fd7fcd @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6185: 5dca04416f50576f464ebbd9aea96edccd7e4eab @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20889: 9daad9c7fa22d0e342261b77e9d078ca8fbe6457 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9daad9c7fa22 drm/i915: remove duplicate include
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20889/index.html
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: better backlight & panel abstractions
== Series Details == Series: drm/i915: better backlight & panel abstractions URL : https://patchwork.freedesktop.org/series/94004/ State : success == Summary == CI Bug Log - changes from CI_DRM_10519_full -> Patchwork_20886_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20886_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-kbl1/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-apl: [PASS][2] -> [DMESG-WARN][3] ([i915#180]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10519/shard-apl1/igt@gem_ctx_isolation@preservation...@vecs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-apl3/igt@gem_ctx_isolation@preservation...@vecs0.html * igt@gem_ctx_persistence@file: - shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-snb6/igt@gem_ctx_persiste...@file.html * igt@gem_eio@in-flight-suspend: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#146] / [i915#198]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10519/shard-skl5/igt@gem_...@in-flight-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-skl6/igt@gem_...@in-flight-suspend.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][7] ([i915#3354]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-snb6/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10519/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_schedule@submit-golden-slice@vcs1: - shard-tglb: [PASS][11] -> [INCOMPLETE][12] ([i915#3797]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10519/shard-tglb6/igt@gem_exec_schedule@submit-golden-sl...@vcs1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-tglb6/igt@gem_exec_schedule@submit-golden-sl...@vcs1.html * igt@gem_pread@exhaustion: - shard-snb: NOTRUN -> [WARN][13] ([i915#2658]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-snb5/igt@gem_pr...@exhaustion.html * igt@gem_render_copy@yf-tiled-to-vebox-linear: - shard-iclb: NOTRUN -> [SKIP][14] ([i915#768]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-iclb2/igt@gem_render_c...@yf-tiled-to-vebox-linear.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3323]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-apl2/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@vma-merge: - shard-skl: NOTRUN -> [FAIL][16] ([i915#3318]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-skl6/igt@gem_userptr_bl...@vma-merge.html * igt@i915_module_load@reload-with-fault-injection: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10519/shard-skl10/igt@i915_module_l...@reload-with-fault-injection.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-skl5/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_pm_rpm@gem-mmap-type@fixed: - shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3976]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-apl1/igt@i915_pm_rpm@gem-mmap-t...@fixed.html * igt@kms_big_fb@linear-32bpp-rotate-0: - shard-iclb: [PASS][20] -> [DMESG-WARN][21] ([i915#3621]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10519/shard-iclb5/igt@kms_big...@linear-32bpp-rotate-0.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-iclb1/igt@kms_big...@linear-32bpp-rotate-0.html - shard-glk: [PASS][22] -> [DMESG-WARN][23] ([i915#118] / [i915#95]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10519/shard-glk8/igt@kms_big...@linear-32bpp-rotate-0.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20886/shard-glk5/igt@kms_big...@linear-32b
Re: [Intel-gfx] [PATCH 0/3] drm/i915: better backlight & panel abstractions
On Wed, 25 Aug 2021, Lyude Paul wrote: > Reviewed-by: Lyude Paul (assuming this still applies) > > As I mentioned on IRC pretty much all of the DPCD backlight helpers already > made it upstream. There are some changes I'm working on right now for VESA > backlights that use PWM for controlling the brightness level (so we can > hopefully fix https://gitlab.freedesktop.org/drm/intel/-/issues/3680 , > otherwise I've gotta do some more poking with the backlight folks from Intel I > got in touch with), but I have no problem with rebasing this when the time > comes. Thanks! BR, Jani. > > On Wed, 2021-08-25 at 14:06 +0300, Jani Nikula wrote: >> Extract the backlight code out of intel_panel.c, and rename the panel >> and backlight functions according to usual conventions. >> >> Lyude, I haven't seen follow-ups on the DPCD backlight stuff you've >> worked on. Is it okay to merge this (and inevitably cause you conflicts) >> or shall I wait more? >> >> BR, >> Jani. >> >> >> Cc: Lyude Paul >> >> Jani Nikula (3): >> drm/i915/backlight: extract backlight code to a separate file >> drm/i915/backlight: mass rename functions to have intel_backlight_ >> prefix >> drm/i915/panel: mass rename functions to have intel_panel_ prefix >> >> drivers/gpu/drm/i915/Makefile | 1 + >> drivers/gpu/drm/i915/display/g4x_dp.c | 4 +- >> drivers/gpu/drm/i915/display/icl_dsi.c | 13 +- >> .../gpu/drm/i915/display/intel_backlight.c | 1776 >> .../gpu/drm/i915/display/intel_backlight.h | 52 + >> .../gpu/drm/i915/display/intel_connector.c | 4 +- >> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +- >> drivers/gpu/drm/i915/display/intel_dp.c | 16 +- >> .../drm/i915/display/intel_dp_aux_backlight.c | 12 +- >> drivers/gpu/drm/i915/display/intel_dvo.c | 2 +- >> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- >> drivers/gpu/drm/i915/display/intel_lvds.c | 18 +- >> drivers/gpu/drm/i915/display/intel_opregion.c | 5 +- >> drivers/gpu/drm/i915/display/intel_panel.c | 1786 + >> drivers/gpu/drm/i915/display/intel_panel.h | 42 +- >> drivers/gpu/drm/i915/display/vlv_dsi.c | 16 +- >> 16 files changed, 1895 insertions(+), 1858 deletions(-) >> create mode 100644 drivers/gpu/drm/i915/display/intel_backlight.c >> create mode 100644 drivers/gpu/drm/i915/display/intel_backlight.h >> -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v2 2/8] drm/i915/display: Move DRRS code its own file
On Wed, 2021-08-25 at 11:55 -0400, Rodrigo Vivi wrote: > On Tue, Aug 24, 2021 at 05:58:34PM -0700, José Roberto de Souza wrote: > > intel_dp.c is a 5k lines monster, so moving DRRS out of it to reduce > > some lines from it. > > > > Cc: Jani Nikula > > Cc: Rodrigo Vivi > > Signed-off-by: José Roberto de Souza > > --- > > Documentation/gpu/i915.rst| 14 +- > > drivers/gpu/drm/i915/Makefile | 1 + > > drivers/gpu/drm/i915/display/intel_ddi.c | 1 + > > .../drm/i915/display/intel_display_debugfs.c | 1 + > > drivers/gpu/drm/i915/display/intel_dp.c | 467 + > > drivers/gpu/drm/i915/display/intel_dp.h | 11 - > > drivers/gpu/drm/i915/display/intel_drrs.c | 477 ++ > > drivers/gpu/drm/i915/display/intel_drrs.h | 32 ++ > > .../gpu/drm/i915/display/intel_frontbuffer.c | 1 + > > 9 files changed, 521 insertions(+), 484 deletions(-) > > create mode 100644 drivers/gpu/drm/i915/display/intel_drrs.c > > create mode 100644 drivers/gpu/drm/i915/display/intel_drrs.h > > > > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst > > index 204ebdaadb45a..03021dfa0dd81 100644 > > --- a/Documentation/gpu/i915.rst > > +++ b/Documentation/gpu/i915.rst > > @@ -183,25 +183,25 @@ Frame Buffer Compression (FBC) > > Display Refresh Rate Switching (DRRS) > > - > > > > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c > > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c > > :doc: Display Refresh Rate Switching (DRRS) > > > > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c > > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c > > :functions: intel_dp_set_drrs_state > > > > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c > > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c > > :functions: intel_edp_drrs_enable > > > > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c > > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c > > :functions: intel_edp_drrs_disable > > > > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c > > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c > > :functions: intel_edp_drrs_invalidate > > > > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c > > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c > > :functions: intel_edp_drrs_flush > > > > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c > > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c > > :functions: intel_dp_drrs_init > > > > DPIO > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > > index fd997dfa5e32c..ee502a2354c44 100644 > > --- a/drivers/gpu/drm/i915/Makefile > > +++ b/drivers/gpu/drm/i915/Makefile > > @@ -213,6 +213,7 @@ i915-y += \ > > display/intel_dpll.o \ > > display/intel_dpll_mgr.o \ > > display/intel_dpt.o \ > > + display/intel_drrs.o \ > > display/intel_dsb.o \ > > display/intel_fb.o \ > > display/intel_fbc.o \ > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 1ef7a65feb660..828df570a4809 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -40,6 +40,7 @@ > > #include "intel_dp_link_training.h" > > #include "intel_dp_mst.h" > > #include "intel_dpio_phy.h" > > +#include "intel_drrs.h" > > #include "intel_dsi.h" > > #include "intel_fdi.h" > > #include "intel_fifo_underrun.h" > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > index 8fdacb252bb19..b136a0fc0963b 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > @@ -13,6 +13,7 @@ > > #include "intel_display_types.h" > > #include "intel_dmc.h" > > #include "intel_dp.h" > > +#include "intel_drrs.h" > > #include "intel_fbc.h" > > #include "intel_hdcp.h" > > #include "intel_hdmi.h" > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index fd4f7e82e4205..965b888e0e771 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -55,6 +55,7 @@ > > #include "intel_dp_mst.h" > > #include "intel_dpio_phy.h" > > #include "intel_dpll.h" > > +#include "intel_drrs.h" > > #include "intel_fifo_underrun.h" > > #include "intel_hdcp.h" > > #include "intel_hdmi.h" > > @@ -1675,46 +1676,6 @@ intel_dp_compute_hdr_metadata_infoframe_sdp(struct > > intel_dp *intel_dp, > > intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); > > } > > > > -static void > > -intel_dp_drrs_compute_config(struct intel_dp *intel_dp, > > -struct intel_crtc_state *pipe_config, > > -
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm: update locking for modesetting (rev4)
== Series Details == Series: drm: update locking for modesetting (rev4) URL : https://patchwork.freedesktop.org/series/93864/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10520 -> Patchwork_20888 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20888 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20888, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20888: ### IGT changes ### Possible regressions * igt@kms_busy@basic@flip: - fi-bxt-dsi: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-bxt-dsi/igt@kms_busy@ba...@flip.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/fi-bxt-dsi/igt@kms_busy@ba...@flip.html - fi-hsw-4770:[PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-hsw-4770/igt@kms_busy@ba...@flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/fi-hsw-4770/igt@kms_busy@ba...@flip.html - fi-cfl-guc: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-cfl-guc/igt@kms_busy@ba...@flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/fi-cfl-guc/igt@kms_busy@ba...@flip.html - fi-skl-guc: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-skl-guc/igt@kms_busy@ba...@flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/fi-skl-guc/igt@kms_busy@ba...@flip.html - fi-ilk-650: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-ilk-650/igt@kms_busy@ba...@flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/fi-ilk-650/igt@kms_busy@ba...@flip.html - fi-ivb-3770:[PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-ivb-3770/igt@kms_busy@ba...@flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/fi-ivb-3770/igt@kms_busy@ba...@flip.html - fi-rkl-11600: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-rkl-11600/igt@kms_busy@ba...@flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/fi-rkl-11600/igt@kms_busy@ba...@flip.html - fi-icl-y: [PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-icl-y/igt@kms_busy@ba...@flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/fi-icl-y/igt@kms_busy@ba...@flip.html - fi-elk-e7500: [PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-elk-e7500/igt@kms_busy@ba...@flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/fi-elk-e7500/igt@kms_busy@ba...@flip.html - fi-skl-6700k2: [PASS][19] -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-skl-6700k2/igt@kms_busy@ba...@flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/fi-skl-6700k2/igt@kms_busy@ba...@flip.html - fi-icl-u2: [PASS][21] -> [DMESG-WARN][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-icl-u2/igt@kms_busy@ba...@flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/fi-icl-u2/igt@kms_busy@ba...@flip.html - fi-cfl-8700k: [PASS][23] -> [DMESG-WARN][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-cfl-8700k/igt@kms_busy@ba...@flip.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/fi-cfl-8700k/igt@kms_busy@ba...@flip.html - fi-snb-2520m: [PASS][25] -> [DMESG-WARN][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-snb-2520m/igt@kms_busy@ba...@flip.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/fi-snb-2520m/igt@kms_busy@ba...@flip.html - fi-bsw-kefka: [PASS][27] -> [DMESG-WARN][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-bsw-kefka/igt@kms_busy@ba...@flip.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/fi-bsw-kefka/igt@kms_busy@ba...@flip.html - fi-glk-dsi: [PASS][29] -> [DMESG-WARN][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10520/fi-glk-dsi/igt@kms_busy@ba...@flip.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20888/fi-glk-dsi/igt@kms_busy@ba...@flip.html - fi-pnv-d510:[PASS][31] -> [DMESG-WARN
Re: [Intel-gfx] [PATCH] drm/i915/snps: constify struct intel_mpllb_state arrays harder
On Wed, Aug 25, 2021 at 05:58:11PM +0300, Jani Nikula wrote:
> The tables should be const arrays of const pointers, not just arrays of
> const pointers.
>
> Cc: Matt Roper
> Signed-off-by: Jani Nikula
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index d81f71296297..58ec2467ad66 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -171,7 +171,7 @@ static const struct intel_mpllb_state dg2_dp_hbr3_100 = {
> REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> };
>
> -static const struct intel_mpllb_state *dg2_dp_100_tables[] = {
> +static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {
> &dg2_dp_rbr_100,
> &dg2_dp_hbr1_100,
> &dg2_dp_hbr2_100,
> @@ -284,7 +284,7 @@ static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = {
> REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 61440),
> };
>
> -static const struct intel_mpllb_state *dg2_dp_38_4_tables[] = {
> +static const struct intel_mpllb_state * const dg2_dp_38_4_tables[] = {
> &dg2_dp_rbr_38_4,
> &dg2_dp_hbr1_38_4,
> &dg2_dp_hbr2_38_4,
> @@ -421,7 +421,7 @@ static const struct intel_mpllb_state dg2_edp_r432 = {
> REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),
> };
>
> -static const struct intel_mpllb_state *dg2_edp_tables[] = {
> +static const struct intel_mpllb_state * const dg2_edp_tables[] = {
> &dg2_dp_rbr_100,
> &dg2_edp_r216,
> &dg2_edp_r243,
> @@ -584,7 +584,7 @@ static const struct intel_mpllb_state dg2_hdmi_594 = {
> REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
> };
>
> -static const struct intel_mpllb_state *dg2_hdmi_tables[] = {
> +static const struct intel_mpllb_state * const dg2_hdmi_tables[] = {
> &dg2_hdmi_25_175,
> &dg2_hdmi_27_0,
> &dg2_hdmi_74_25,
> @@ -593,7 +593,7 @@ static const struct intel_mpllb_state *dg2_hdmi_tables[]
> = {
> NULL,
> };
>
> -static const struct intel_mpllb_state **
> +static const struct intel_mpllb_state * const *
> intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder)
> {
> @@ -627,7 +627,7 @@ intel_mpllb_tables_get(struct intel_crtc_state
> *crtc_state,
> int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder)
> {
> - const struct intel_mpllb_state **tables;
> + const struct intel_mpllb_state * const *tables;
> int i;
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> @@ -823,7 +823,7 @@ void intel_mpllb_readout_hw_state(struct intel_encoder
> *encoder,
>
> int intel_snps_phy_check_hdmi_link_rate(int clock)
> {
> - const struct intel_mpllb_state **tables = dg2_hdmi_tables;
> + const struct intel_mpllb_state * const *tables = dg2_hdmi_tables;
> int i;
>
> for (i = 0; tables[i]; i++) {
> --
> 2.20.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm: update locking for modesetting (rev4)
== Series Details == Series: drm: update locking for modesetting (rev4) URL : https://patchwork.freedesktop.org/series/93864/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:1365:16: warning: symbol 'configure_lttpr_mode_transparent' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:1376:16: warning: symbol 'configure_lttpr_mode_non_transparent' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:1627:16: warning: symbol 'dpcd_configure_channel_coding' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_resource.c:1741:16: warning: Using plain integer as NULL pointer +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:135:6: warning: symbol 'dcn10_log_hubbub_state' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1902:10: warning: symbol 'reduceSizeAndFraction' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1953:6: warning: symbol 'is_low_refresh_rate' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1962:9: warning: symbol 'get_clock_divider' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1982:5: warning: symbol 'dcn10_align_pixel_clocks' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2274:6: warning: symbol 'dcn10_program_pte_vm' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:80:6: warning: symbol 'print_microsec' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dsc.c:49:24: warning: symbol 'dcn20_dsc_funcs' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:1080:6: warning: symbol 'dcn20_enable_plane' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:1391:17: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:1391:17: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:678:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:678:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:679:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:679:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:680:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:680:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:681:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:681:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:682:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:682:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:683:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:683:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:687:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:687:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:692:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:692:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:776:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:776:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:777:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:777:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:778:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:778:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:779:9: also defined here +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:779:9: warning: Initializer entry defined twice +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_
Re: [Intel-gfx] [PATCH 20/27] drm/i915/guc: Rework and simplify locking
On 8/18/2021 11:16 PM, Matthew Brost wrote:
Rework and simplify the locking with GuC subission. Drop
sched_state_no_lock and move all fields under the guc_state.sched_state
and protect all these fields with guc_state.lock . This requires
changing the locking hierarchy from guc_state.lock -> sched_engine.lock
to sched_engine.lock -> guc_state.lock.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 5 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 186 --
drivers/gpu/drm/i915/i915_trace.h | 6 +-
3 files changed, 89 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index c06171ee8792..d5d643b04d54 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -161,7 +161,7 @@ struct intel_context {
* sched_state: scheduling state of this context using GuC
* submission
*/
- u16 sched_state;
+ u32 sched_state;
/*
* fences: maintains of list of requests that have a submit
* fence related to GuC submission
@@ -178,9 +178,6 @@ struct intel_context {
struct list_head requests;
} guc_active;
- /* GuC scheduling state flags that do not require a lock. */
- atomic_t guc_sched_state_no_lock;
-
/* GuC LRC descriptor ID */
u16 guc_id;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 053f4485d6e9..509b298e7cf3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -72,86 +72,23 @@ guc_create_virtual(struct intel_engine_cs **siblings,
unsigned int count);
#define GUC_REQUEST_SIZE 64 /* bytes */
-/*
- * Below is a set of functions which control the GuC scheduling state which do
- * not require a lock as all state transitions are mutually exclusive. i.e. It
- * is not possible for the context pinning code and submission, for the same
- * context, to be executing simultaneously. We still need an atomic as it is
- * possible for some of the bits to changing at the same time though.
- */
-#define SCHED_STATE_NO_LOCK_ENABLEDBIT(0)
-#define SCHED_STATE_NO_LOCK_PENDING_ENABLE BIT(1)
-#define SCHED_STATE_NO_LOCK_REGISTERED BIT(2)
-static inline bool context_enabled(struct intel_context *ce)
-{
- return (atomic_read(&ce->guc_sched_state_no_lock) &
- SCHED_STATE_NO_LOCK_ENABLED);
-}
-
-static inline void set_context_enabled(struct intel_context *ce)
-{
- atomic_or(SCHED_STATE_NO_LOCK_ENABLED, &ce->guc_sched_state_no_lock);
-}
-
-static inline void clr_context_enabled(struct intel_context *ce)
-{
- atomic_and((u32)~SCHED_STATE_NO_LOCK_ENABLED,
- &ce->guc_sched_state_no_lock);
-}
-
-static inline bool context_pending_enable(struct intel_context *ce)
-{
- return (atomic_read(&ce->guc_sched_state_no_lock) &
- SCHED_STATE_NO_LOCK_PENDING_ENABLE);
-}
-
-static inline void set_context_pending_enable(struct intel_context *ce)
-{
- atomic_or(SCHED_STATE_NO_LOCK_PENDING_ENABLE,
- &ce->guc_sched_state_no_lock);
-}
-
-static inline void clr_context_pending_enable(struct intel_context *ce)
-{
- atomic_and((u32)~SCHED_STATE_NO_LOCK_PENDING_ENABLE,
- &ce->guc_sched_state_no_lock);
-}
-
-static inline bool context_registered(struct intel_context *ce)
-{
- return (atomic_read(&ce->guc_sched_state_no_lock) &
- SCHED_STATE_NO_LOCK_REGISTERED);
-}
-
-static inline void set_context_registered(struct intel_context *ce)
-{
- atomic_or(SCHED_STATE_NO_LOCK_REGISTERED,
- &ce->guc_sched_state_no_lock);
-}
-
-static inline void clr_context_registered(struct intel_context *ce)
-{
- atomic_and((u32)~SCHED_STATE_NO_LOCK_REGISTERED,
- &ce->guc_sched_state_no_lock);
-}
-
/*
* Below is a set of functions which control the GuC scheduling state which
- * require a lock, aside from the special case where the functions are called
- * from guc_lrc_desc_pin(). In that case it isn't possible for any other code
- * path to be executing on the context.
+ * require a lock.
*/
#define SCHED_STATE_WAIT_FOR_DEREGISTER_TO_REGISTER BIT(0)
#define SCHED_STATE_DESTROYED BIT(1)
#define SCHED_STATE_PENDING_DISABLE BIT(2)
#define SCHED_STATE_BANNEDBIT(3)
-#define SCHED_STATE_BLOCKED_SHIFT 4
+#define SCHED_STATE_ENABLEDBIT(4)
+#define SCHED_STATE_PENDING_ENABLE BIT(5)
+#define SCHED_STATE_REGISTERED BIT(6)
+#define SCHED_STATE_BLOCKED_SHIFT
Re: [Intel-gfx] [PATCH 0/3] drm/i915: better backlight & panel abstractions
Reviewed-by: Lyude Paul (assuming this still applies) As I mentioned on IRC pretty much all of the DPCD backlight helpers already made it upstream. There are some changes I'm working on right now for VESA backlights that use PWM for controlling the brightness level (so we can hopefully fix https://gitlab.freedesktop.org/drm/intel/-/issues/3680 , otherwise I've gotta do some more poking with the backlight folks from Intel I got in touch with), but I have no problem with rebasing this when the time comes. On Wed, 2021-08-25 at 14:06 +0300, Jani Nikula wrote: > Extract the backlight code out of intel_panel.c, and rename the panel > and backlight functions according to usual conventions. > > Lyude, I haven't seen follow-ups on the DPCD backlight stuff you've > worked on. Is it okay to merge this (and inevitably cause you conflicts) > or shall I wait more? > > BR, > Jani. > > > Cc: Lyude Paul > > Jani Nikula (3): > drm/i915/backlight: extract backlight code to a separate file > drm/i915/backlight: mass rename functions to have intel_backlight_ > prefix > drm/i915/panel: mass rename functions to have intel_panel_ prefix > > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/display/g4x_dp.c | 4 +- > drivers/gpu/drm/i915/display/icl_dsi.c | 13 +- > .../gpu/drm/i915/display/intel_backlight.c | 1776 > .../gpu/drm/i915/display/intel_backlight.h | 52 + > .../gpu/drm/i915/display/intel_connector.c | 4 +- > drivers/gpu/drm/i915/display/intel_ddi.c | 4 +- > drivers/gpu/drm/i915/display/intel_dp.c | 16 +- > .../drm/i915/display/intel_dp_aux_backlight.c | 12 +- > drivers/gpu/drm/i915/display/intel_dvo.c | 2 +- > drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- > drivers/gpu/drm/i915/display/intel_lvds.c | 18 +- > drivers/gpu/drm/i915/display/intel_opregion.c | 5 +- > drivers/gpu/drm/i915/display/intel_panel.c | 1786 + > drivers/gpu/drm/i915/display/intel_panel.h | 42 +- > drivers/gpu/drm/i915/display/vlv_dsi.c | 16 +- > 16 files changed, 1895 insertions(+), 1858 deletions(-) > create mode 100644 drivers/gpu/drm/i915/display/intel_backlight.c > create mode 100644 drivers/gpu/drm/i915/display/intel_backlight.h > -- Cheers, Lyude Paul (she/her) Software Engineer at Red Hat
Re: [Intel-gfx] [PATCH 2/2] drm/amdgpu: Disable PCIE_DPM on Intel RKL Platform
On Wed, Aug 25, 2021 at 10:33 PM Alex Deucher wrote:
>
> On Wed, Aug 25, 2021 at 10:22 AM Lazar, Lijo wrote:
> >
> >
> >
> > On 8/25/2021 4:46 PM, Koba Ko wrote:
> > > On Wed, Aug 25, 2021 at 6:24 PM Jani Nikula
> > > wrote:
> > >>
> > >> On Wed, 25 Aug 2021, Koba Ko wrote:
> > >>> On Wed, Aug 25, 2021 at 5:22 PM Jani Nikula
> > >>> wrote:
> >
> > On Wed, 25 Aug 2021, Koba Ko wrote:
> > > AMD polaris GPUs have an issue about audio noise on RKL platform,
> > > they provide a commit to fix but for SMU7-based GPU still
> > > need another module parameter,
> > >
> > > For avoiding the module parameter, switch PCI_DPM by determining
> > > intel platform in amd drm driver.
> >
> > I'll just note that you could have a Tiger Lake PCH combined with a
> > number of platforms other than Rocket Lake, including not just the
> > obvious Tiger Lake but also Sky Lake, Kaby Lake, Coffee Lake, and Comet
> > Lake.
> >
> > Again, I don't know what the root cause or fix should be, the
> > workaround
> > presented here impacts a much larger number of platforms than where
> > you're claiming the issue is.
> > >>>
> > >>> Hi Jani, thanks for your feedback.
> > >>> Is there any way to identify the RKL PCH?
> > >>> I trace the intel_pch.c and can't find the only pch id for RKL.
> > >>>
> > >>> INTEL_PCH_TGP_DEVICE_ID_TYPE is used by both TGL and RKL.
> > >>>
> > >>> so it seems that using IS_ROCKETLAKE() is the only way.
> > >>
> > >> I don't think there is a Rocket Lake PCH. But is the problem related to
> > >> the PCH or not?
> > >
> > > I thought its' not because the issue wouldn't be observed on the TGL
> > > platform.
> > > I only tried RKL platform and it use
> > > INTEL_PCH_TGP_DEVICE_ID_TYPE/INTEL_PCH_TGP2_DEVICE_ID_TYPE,
> > > As per AMD guys, they said the issue is only triggered in RKL platform.
> > >
> > >>
> > >> The GPU PCI IDs are in i915_pciids.h. See INTEL_RKL_IDS() for
> > >> RKL. There's a lot of indirection, but that's what IS_ROCKETLAKE() boils
> > >> down to. But again, I'm not sure if that's what you want or not.
> > > Thanks for suggestions,
> > >
> > > Just want a way to check if it's a RKL platform,
> > > After tracing the kernel, can check by CPU VENDOR(lacks type), check
> > > igpu(but there're cpus without igpu)
> > > and check pch type(it seems one pch has multiple combinations with CPU).
> > > for check igpu, as per my current understanding, only found RKL CPU with
> > > igpu.
> > > Is there a RKL CPU without integrated gpu?
> > >
> >
> > Just for RKL - you could do fetch the x86 info and check
> >
> > #ifdef CONFIG_X86_64
> > struct cpuinfo_x86 *c = &cpu_data(0);
> > // Family/Model check, find the model
> > (c->x86 == 6 && c->x86_model == INTEL_FAM6_ROCKETLAKE)
> > #endif
> >
> > I think we don't use anything like this so far. So Alex should give a
> > nod as well.
>
> I think that makes sense. For some background the issue that was
> observed with RKL was that the PCIE gen switching has a very high
> latency which can lead to audio problems during playback if PCIE DPM
> is enabled.
>
> Alex
Thanks, use Lazar's suggestion and don't need any information from i915.
I will send the next patch.
Thanks
Koba
>
> >
> > Thanks,
> > Lijo
> >
> > >>
> > >> BR,
> > >> Jani.
> > >>
> > >>
> > >>>
> > >>> Thanks
> >
> > BR,
> > Jani.
> >
> >
> > >
> > > Fixes: 1a31474cdb48 ("drm/amd/pm: workaround for audio noise issue")
> > > Ref:
> > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Farchives%2Famd-gfx%2F2021-August%2F067413.html&data=04%7C01%7Clijo.lazar%40amd.com%7C888ab428f2bb4f32e4d408d967c4ae08%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637654916721463596%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Bgf14CmIx%2FTOD54LN6dccZL0U5gT9lv9yTw7MfKc2sQ%3D&reserved=0
> > > Signed-off-by: Koba Ko
> > > ---
> > > .../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 21
> > > ++-
> > > 1 file changed, 20 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> > > b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> > > index 0541bfc81c1b..346110dd0f51 100644
> > > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> > > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> > > @@ -1733,6 +1733,25 @@ static int smu7_disable_dpm_tasks(struct
> > > pp_hwmgr *hwmgr)
> > >return result;
> > > }
> > >
> > > +#include
> > > +
> > > +static bool intel_tgp_chk(void)
> > > +{
> > > + struct pci_dev *pch = NULL;
> > > + unsigned short id;
> > > +
> > > + while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
> > > + if (pch->vendor != PCI
Re: [Intel-gfx] [GIT PULL] drm-misc + drm-intel: Add support for out-of-band hotplug notification
On Tue, 2021-08-24 at 18:48 +0200, Hans de Goede wrote: > Hi, > > On 8/24/21 10:45 AM, Jani Nikula wrote: > > On Fri, 20 Aug 2021, Hans de Goede wrote: > > > Hello drm-misc and drm-intel maintainers, > > > > > > My "Add support for out-of-band hotplug notification" patchset: > > > https://patchwork.freedesktop.org/series/93763/ > > > > > > Is ready for merging now, as discussed on IRC I based this series > > > on top drm-tip and when trying to apply the i915 parts on top > > > of drm-misc this fails due to conflict. > > > > > > So as Jani suggested here is a pull-req for a topic-branch with > > > the > > > entire set, minus the troublesome i915 bits. Once this has been > > > merged > > > into both drm-misc-next and drm-intel-next I can push the 2 i915 > > > patch do drm-intel-next on top of the merge. > > > > > > Note there are also 2 drivers/usb/typec patches in here these > > > have Greg KH's Reviewed-by for merging through the drm tree, > > > Since this USB code does not change all that much. I also checked > > > and the drm-misc-next-2021-08-12 base of this tree contains the > > > same last commit to the modified file as usb-next. > > > > > > Daniel Vetter mentioned on IRC that it might be better for you to > > > simply > > > pick-up the series directly from patchwork, that is fine too in > > > that > > > case don't forget to add: > > > > > > Reviewed-by: Lyude Paul > > > > > > To the entire series (given in a reply to the cover-letter) > > > > > > And: > > > > > > Reviewed-by: Greg Kroah-Hartman > > > > > > To the usb/typec patches (patch 7/8), this was given in reply > > > to a previous posting of the series and I forgot to add this > > > in the resend. > > > > Since this is mostly touching drm core, I think it should be merged > > to > > drm-misc-next first, and drm-intel-next after. Please let us know. > > I agree this should go to drm-misc-next first. > > (I was planning on pushing this to drm-misc-next myself, > but then ended up going with the topic branch because of the > conflict in the i915 bits.) Just to be clear and avoid confusion: This pull request does apply cleanly on drm-misc-next nd drm-intel-next right now. I'm just waiting for drm-misc-next maintainers to pull this to drm- misc-next so I can pull it to drm-intel-next. Maxime, is that your round now? or Thomas? Thanks, Rodrigo. > > Regards, > > Hans > > > > > > The following changes since commit > > > c7782443a88926a4f938f0193041616328cf2db2: > > > > > > drm/bridge: ti-sn65dsi86: Avoid creating multiple connectors > > > (2021-08-12 09:56:09 -0700) > > > > > > are available in the Git repository at: > > > > > > git://git.kernel.org/pub/scm/linux/kernel/git/hansg/linux.git > > > drm-misc-intel-oob-hotplug-v1 > > > > > > for you to fetch changes up to > > > 7f811394878535ed9a6849717de8c2959ae38899: > > > > > > usb: typec: altmodes/displayport: Notify drm subsys of hotplug > > > events (2021-08-20 12:35:59 +0200) > > > > > > > > > Topic branch for drm-misc / drm-intel for OOB hotplug support for > > > Type-C connectors > > > > > > > > > Hans de Goede (6): > > > drm/connector: Give connector sysfs devices there own > > > device_type > > > drm/connector: Add a fwnode pointer to drm_connector and > > > register with ACPI (v2) > > > drm/connector: Add drm_connector_find_by_fwnode() function > > > (v3) > > > drm/connector: Add support for out-of-band hotplug > > > notification (v3) > > > usb: typec: altmodes/displayport: Make dp_altmode_notify() > > > more generic > > > usb: typec: altmodes/displayport: Notify drm subsys of > > > hotplug events > > > > > > drivers/gpu/drm/drm_connector.c | 79 > > > + > > > drivers/gpu/drm/drm_crtc_internal.h | 2 + > > > drivers/gpu/drm/drm_sysfs.c | 87 > > > +++- > > > drivers/usb/typec/altmodes/Kconfig | 1 + > > > drivers/usb/typec/altmodes/displayport.c | 58 +- > > > --- > > > include/drm/drm_connector.h | 25 + > > > 6 files changed, 217 insertions(+), 35 deletions(-) > > > > > >
