[Intel-gfx] ✗ Fi.CI.BAT: failure for Assorted fixes/tweaks to GuC support (rev3)
== Series Details ==
Series: Assorted fixes/tweaks to GuC support (rev3)
URL : https://patchwork.freedesktop.org/series/97514/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10963 -> Patchwork_21757
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_21757 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21757, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21757/index.html
Participating hosts (45 -> 33)
--
Missing(12): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan
bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus bat-jsl-2 bat-jsl-1
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21757:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@mman:
- fi-ivb-3770:[PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-ivb-3770/igt@i915_selftest@l...@mman.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21757/fi-ivb-3770/igt@i915_selftest@l...@mman.html
* igt@i915_selftest@live@workarounds:
- fi-rkl-guc: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21757/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html
Known issues
Here are the changes found in Patchwork_21757 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][5] ([fdo#109271]) +31 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21757/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [PASS][6] -> [INCOMPLETE][7] ([i915#198] /
[i915#4547])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21757/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-bdw-5557u: NOTRUN -> [DMESG-FAIL][8] ([i915#541])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21757/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][9] -> [DMESG-FAIL][10] ([i915#4528])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21757/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21757/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][12] -> [DMESG-WARN][13] ([i915#4269])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21757/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][14] ([i915#2722] / [i915#3363] /
[i915#4312])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21757/fi-skl-6600u/igt@run...@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][15] ([i915#2426] / [i915#3928] /
[i915#4312])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21757/fi-rkl-guc/igt@run...@aborted.html
- fi-ivb-3770:NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#2426] /
[i915#4312])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21757/fi-ivb-3770/igt@run...@aborted.html
- fi-blb-e6850: NOTRUN -> [FAIL][17] ([fdo#109271] / [i915#2403] /
[i915#4312])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21757/fi-blb-e6850/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-bdw-5557u: [INCOMPLETE][18] ([i915#146]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21757/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_b
Re: [Intel-gfx] [PATCH i-g-t] intel-gpu-top: Add support for per client stats
On Fri, 03 Dec 2021 07:54:56 -0800, Tvrtko Ursulin wrote: > > From: Tvrtko Ursulin > > Use the i915 exported data in /proc//fdinfo to show GPU utilization > per DRM client. Didn't we just remove it? Adding it back now? Sorry for the probably dumb question :/
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Assorted fixes/tweaks to GuC support (rev3)
== Series Details == Series: Assorted fixes/tweaks to GuC support (rev3) URL : https://patchwork.freedesktop.org/series/97514/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Assorted fixes/tweaks to GuC support (rev3)
== Series Details == Series: Assorted fixes/tweaks to GuC support (rev3) URL : https://patchwork.freedesktop.org/series/97514/ State : warning == Summary == $ dim checkpatch origin/drm-tip 251e5012b67c drm/i915/uc: Allow platforms to have GuC but not HuC -:36: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #36: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:51: +#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \ + fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3)) \ + fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0)) \ + fw_def(DG1, 0, guc_def(dg1, 62, 0, 0)) \ + fw_def(ROCKETLAKE, 0, guc_def(tgl, 62, 0, 0)) \ + fw_def(TIGERLAKE,0, guc_def(tgl, 62, 0, 0)) \ + fw_def(JASPERLAKE, 0, guc_def(ehl, 62, 0, 0)) \ + fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0)) \ + fw_def(ICELAKE, 0, guc_def(icl, 62, 0, 0)) \ + fw_def(COMETLAKE,5, guc_def(cml, 62, 0, 0)) \ + fw_def(COMETLAKE,0, guc_def(kbl, 62, 0, 0)) \ + fw_def(COFFEELAKE, 0, guc_def(kbl, 62, 0, 0)) \ + fw_def(GEMINILAKE, 0, guc_def(glk, 62, 0, 0)) \ + fw_def(KABYLAKE, 0, guc_def(kbl, 62, 0, 0)) \ + fw_def(BROXTON, 0, guc_def(bxt, 62, 0, 0)) \ + fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0)) -:36: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fw_def' - possible side-effects? #36: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:51: +#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \ + fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3)) \ + fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0)) \ + fw_def(DG1, 0, guc_def(dg1, 62, 0, 0)) \ + fw_def(ROCKETLAKE, 0, guc_def(tgl, 62, 0, 0)) \ + fw_def(TIGERLAKE,0, guc_def(tgl, 62, 0, 0)) \ + fw_def(JASPERLAKE, 0, guc_def(ehl, 62, 0, 0)) \ + fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0)) \ + fw_def(ICELAKE, 0, guc_def(icl, 62, 0, 0)) \ + fw_def(COMETLAKE,5, guc_def(cml, 62, 0, 0)) \ + fw_def(COMETLAKE,0, guc_def(kbl, 62, 0, 0)) \ + fw_def(COFFEELAKE, 0, guc_def(kbl, 62, 0, 0)) \ + fw_def(GEMINILAKE, 0, guc_def(glk, 62, 0, 0)) \ + fw_def(KABYLAKE, 0, guc_def(kbl, 62, 0, 0)) \ + fw_def(BROXTON, 0, guc_def(bxt, 62, 0, 0)) \ + fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0)) -:36: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'guc_def' - possible side-effects? #36: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:51: +#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \ + fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3)) \ + fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0)) \ + fw_def(DG1, 0, guc_def(dg1, 62, 0, 0)) \ + fw_def(ROCKETLAKE, 0, guc_def(tgl, 62, 0, 0)) \ + fw_def(TIGERLAKE,0, guc_def(tgl, 62, 0, 0)) \ + fw_def(JASPERLAKE, 0, guc_def(ehl, 62, 0, 0)) \ + fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0)) \ + fw_def(ICELAKE, 0, guc_def(icl, 62, 0, 0)) \ + fw_def(COMETLAKE,5, guc_def(cml, 62, 0, 0)) \ + fw_def(COMETLAKE,0, guc_def(kbl, 62, 0, 0)) \ + fw_def(COFFEELAKE, 0, guc_def(kbl, 62, 0, 0)) \ + fw_def(GEMINILAKE, 0, guc_def(glk, 62, 0, 0)) \ + fw_def(KABYLAKE, 0, guc_def(kbl, 62, 0, 0)) \ + fw_def(BROXTON, 0, guc_def(bxt, 62, 0, 0)) \ + fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0)) -:53: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #53: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:68: +#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \ + fw_def(ALDERLAKE_P, 0, huc_def(tgl, 7, 9, 3)) \ + fw_def(ALDERLAKE_S, 0, huc_def(tgl, 7, 9, 3)) \ + fw_def(DG1, 0, huc_def(dg1, 7, 9, 3)) \ + fw_def(ROCKETLAKE, 0, huc_def(tgl, 7, 9, 3)) \ + fw_def(TIGERLAKE,0, huc_def(tgl, 7, 9, 3)) \ + fw_def(JASPERLAKE, 0, huc_def(ehl, 9, 0, 0)) \ + fw_def(ELKHARTLAKE, 0, huc_def(ehl, 9, 0, 0)) \ + fw_def(ICELAKE, 0, huc_def(icl, 9, 0, 0)) \ + fw_def(COMETLAKE,5, huc_def(cml, 4, 0, 0)) \ + fw_def(COMETLAKE,0, huc_def(kbl, 4, 0, 0)) \ + fw_def(COFFEELAKE, 0, huc_def(kbl, 4, 0, 0)) \ + fw_def(GEMINILAKE, 0, huc_def(glk, 4, 0, 0)) \ + fw_def(KABYLAKE, 0, huc_def(kbl, 4, 0, 0)) \ + fw_def(BROXTON, 0, huc_def(bxt, 2, 0, 0)) \ + fw_def(SKYLAKE, 0, huc_def(skl, 2, 0, 0)) -:53: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fw_def' - possible side-effects? #53: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:68: +#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \ + fw_def(ALDERLAKE_P, 0, huc_def(tgl, 7, 9, 3)) \ + fw_def(ALDERLAKE_S, 0, huc_def(tgl, 7, 9, 3)) \ + fw_def(DG1, 0, huc_def(dg1, 7, 9, 3)) \ + fw_def(ROCKETLAKE, 0, huc_def(tgl, 7, 9, 3)) \ + fw_d
[Intel-gfx] ✗ Fi.CI.IGT: failure for Per client GPU stats (rev5)
== Series Details == Series: Per client GPU stats (rev5) URL : https://patchwork.freedesktop.org/series/92574/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10961_full -> Patchwork_21748_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21748_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21748_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21748_full: ### IGT changes ### Possible regressions * igt@i915_suspend@sysfs-reader: - shard-kbl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/shard-kbl4/igt@i915_susp...@sysfs-reader.html Known issues Here are the changes found in Patchwork_21748_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@psr2: - shard-iclb: [PASS][2] -> [SKIP][3] ([i915#658]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-iclb2/igt@feature_discov...@psr2.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/shard-iclb5/igt@feature_discov...@psr2.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063] / [i915#3648]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-tglb1/igt@gem_...@unwedge-stress.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/shard-tglb5/igt@gem_...@unwedge-stress.html - shard-iclb: [PASS][6] -> [TIMEOUT][7] ([i915#2481] / [i915#3070]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-iclb2/igt@gem_...@unwedge-stress.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/shard-iclb8/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/shard-kbl2/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-tglb5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-iclb8/igt@gem_exec_fair@basic-pace-s...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/shard-iclb6/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-sync@rcs0: - shard-kbl: [PASS][14] -> [SKIP][15] ([fdo#109271]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-kbl7/igt@gem_exec_fair@basic-s...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/shard-kbl3/igt@gem_exec_fair@basic-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2849]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_params@secure-non-master: - shard-tglb: NOTRUN -> [SKIP][18] ([fdo#112283]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/shard-tglb8/igt@gem_exec_par...@secure-non-master.html * igt@gem_exec_whisper@basic-fds-all: - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#118]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-glk4/igt@gem_exec_whis...@basic-fds-all.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/shard-glk5/igt@gem_exec_whis...@basic-fds-all.html * igt@gem_lmem_swapping@parallel-random: - shard-kbl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/shard-kbl2/igt@gem_lmem_swapp...@parallel-random.html * igt@gem_lmem_swapping@random-engines: - shard-apl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4613]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/shard-apl4/igt@gem_
[Intel-gfx] [PATCH v2] drm/i915/adlp: Remove require_force_probe protection
From: Clint Taylor
Remove force probe protection from ADL_P platform. Did not obsevre
warnings, errors, flickering or any visual defects while doing ordinary
tasks like browsing and editing documents in a two monitor setup.
For more info drm-tip idle run results :
https://intel-gfx-ci.01.org/tree/drm-tip/drmtip.html?
Cc: Rodrigo Vivi
Acked-by: Jon Bloomfield
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_pci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f01cba4ec283..0ba516838b02 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -977,7 +977,6 @@ static const struct intel_device_info adl_p_info = {
GEN12_FEATURES,
XE_LPD_FEATURES,
PLATFORM(INTEL_ALDERLAKE_P),
- .require_force_probe = 1,
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
--
2.33.1
Re: [Intel-gfx] [PATCH] drm/i915: Rollback seqno when request creation fails
Hi Matthew,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next
drm/drm-next tegra-drm/drm/tegra/for-next v5.16-rc3 next-20211203]
[cannot apply to airlied/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Matthew-Brost/drm-i915-Rollback-seqno-when-request-creation-fails/20211204-020638
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-m021-20211203
(https://download.01.org/0day-ci/archive/20211204/202112040802.qqhqie5v-...@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/af590220a3160c7a680487eac25eb2dc24baf42d
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Matthew-Brost/drm-i915-Rollback-seqno-when-request-creation-fails/20211204-020638
git checkout af590220a3160c7a680487eac25eb2dc24baf42d
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/gt/intel_timeline.c: In function
'intel_timeline_rollback_seqno':
>> drivers/gpu/drm/i915/gt/intel_timeline.c:306:2: error: implicit declaration
>> of function 'timeline_rollback' [-Werror=implicit-function-declaration]
306 | timeline_rollback(tl);
| ^
cc1: some warnings being treated as errors
vim +/timeline_rollback +306 drivers/gpu/drm/i915/gt/intel_timeline.c
303
304 void intel_timeline_rollback_seqno(struct intel_timeline *tl)
305 {
> 306 timeline_rollback(tl);
307 }
308
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Rollback seqno when request creation fails (rev2)
== Series Details == Series: drm/i915: Rollback seqno when request creation fails (rev2) URL : https://patchwork.freedesktop.org/series/97562/ State : success == Summary == CI Bug Log - changes from CI_DRM_10963 -> Patchwork_21756 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/index.html Participating hosts (45 -> 33) -- Missing(12): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21756 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +31 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [PASS][2] -> [INCOMPLETE][3] ([i915#198]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-bdw-5557u: [INCOMPLETE][5] ([i915#146]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 Build changes - * Linux: CI_DRM_10963 -> Patchwork_21756 CI-20190529: 20190529 CI_DRM_10963: 2b63a468d3e3c264a3d1a4773edfe8785d45d4ec @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6300: f69bd65fa9f72b7d5e5a5a22981f16d034334761 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21756: 1cf3b54b7c910952dcd286013db37f0d7b927b21 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1cf3b54b7c91 drm/i915: Rollback seqno when request creation fails == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/index.html
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftests
== Series Details == Series: drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftests URL : https://patchwork.freedesktop.org/series/97577/ State : success == Summary == CI Bug Log - changes from CI_DRM_10963 -> Patchwork_21755 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/index.html Participating hosts (45 -> 33) -- Missing(12): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21755 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +31 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [PASS][2] -> [FAIL][3] ([i915#4547]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html * igt@i915_selftest@live@gt_engines: - fi-rkl-guc: [PASS][4] -> [INCOMPLETE][5] ([i915#4432]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#4269]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html * igt@runner@aborted: - fi-skl-6600u: NOTRUN -> [FAIL][9] ([i915#3363] / [i915#4312]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/fi-skl-6600u/igt@run...@aborted.html - fi-rkl-guc: NOTRUN -> [FAIL][10] ([i915#3928] / [i915#4312]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/fi-rkl-guc/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-bdw-5557u: [INCOMPLETE][11] ([i915#146]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 Build changes - * Linux: CI_DRM_10963 -> Patchwork_21755 CI-20190529: 20190529 CI_DRM_10963: 2b63a468d3e3c264a3d1a4773edfe8785d45d4ec @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6300: f69bd65fa9f72b7d5e5a5a22981f16d034334761 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21755: 06b07fd47af5e769f56fed3e5727ddb759d70f50 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 06b07fd47af5 drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftests == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/index.html
Re: [Intel-gfx] [PATCH v2] drm/dp: Actually read Adjust Request Post Cursor2 register
On Fri, Dec 03, 2021 at 04:28:56PM +0100, Thierry Reding wrote:
> On Fri, Dec 03, 2021 at 01:25:17AM -0800, Kees Cook wrote:
> > The link_status array was not large enough to read the Adjust Request
> > Post Cursor2 register. Adjust the size to include it. Found with a
> > -Warray-bounds build:
> >
> > drivers/gpu/drm/drm_dp_helper.c: In function
> > 'drm_dp_get_adjust_request_post_cursor':
> > drivers/gpu/drm/drm_dp_helper.c:59:27: error: array subscript 10 is outside
> > array bounds of 'const u8[6]' {aka 'const unsigned char[6]'}
> > [-Werror=array-bounds]
> >59 | return link_status[r - DP_LANE0_1_STATUS];
> > |~~~^~~
> > drivers/gpu/drm/drm_dp_helper.c:147:51: note: while referencing
> > 'link_status'
> > 147 | u8 drm_dp_get_adjust_request_post_cursor(const u8
> > link_status[DP_LINK_STATUS_SIZE],
> > |
> > ~^~~~
> >
> > Fixes: 79465e0ffeb9 ("drm/dp: Add helper to get post-cursor adjustments")
> > Signed-off-by: Kees Cook
> > ---
> > v2: Fix missed array size change in intel_dp_check_mst_status()
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 8
> > include/drm/drm_dp_helper.h | 10 +-
> > 2 files changed, 13 insertions(+), 5 deletions(-)
>
> This sounds very familiar and I vaguely recall typing up a patch like
> that a long time ago. But I obviously failed because that never seems
> to have made it upstream.
>
> Or perhaps I'm misremembering and was thinking about this instead:
>
>
> https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/338590/
Oh! Yeah, that's the same thing. Looks like that never made its way
upstream. :(
>
> Bonus points for adding that comment with background information on why
> we need this.
Thanks! Yeah, I needed to really convince myself everything added up and
made sense, and figured I should try to capture that research. ;)
> Reviewed-by: Thierry Reding
Thanks!
-Kees
--
Kees Cook
Re: [Intel-gfx] [PATCH] drm/i915/adlp: Remove require_force_probe protection
Assuming the whitespace cleanup requested below is completed:
Acked-by: Jon Bloomfield
> -Original Message-
> From: Intel-gfx On Behalf Of
> Rodrigo Vivi
> Sent: Tuesday, November 16, 2021 2:33 PM
> To: Taylor, Clinton A
> Cc: Intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/adlp: Remove
> require_force_probe protection
>
> On Mon, Nov 15, 2021 at 03:53:45PM -0800, clinton.a.tay...@intel.com
> wrote:
> > From: Clint Taylor
> >
> > drm/i915/adlp: Remove require_force_probe protection
> >
> > Removing force probe protection from ADL_P platform. Did
> > not observe warnings, errors, flickering or any visual
> > defects while doing ordinary tasks like browsing and
> > editing documents in a two monitor setup.
>
> some strange alignment here... please remove the extra
> tabs here.
>
> >
> > For more info drm-tip idle run results :
> > https://intel-gfx-ci.01.org/tree/drm-tip/drmtip.html?
>
> hmm... I could swear that I had seen the ADL-P green there a few
> days ago as well... But right now I couldn't see ADL-P there...
>
> So that fails on having a *reliable* green CI picture...
> Any idea why that is down at this moment?
>
> >
> > Cc: Rodrigo Vivi
> >
> > Signed-off-by: Clint Taylor
> > ---
> > drivers/gpu/drm/i915/i915_pci.c | 1 -
> > 1 file changed, 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> > index 4c7fcc5f9a97..af9f4988bd88 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -970,7 +970,6 @@ static const struct intel_device_info adl_p_info = {
> > GEN12_FEATURES,
> > XE_LPD_FEATURES,
> > PLATFORM(INTEL_ALDERLAKE_P),
> > - .require_force_probe = 1,
> > .cpu_transcoder_mask = BIT(TRANSCODER_A) |
> BIT(TRANSCODER_B) |
> >BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> >BIT(TRANSCODER_DSI_0) |
> BIT(TRANSCODER_DSI_1),
> > --
> > 2.33.1
> >
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Rollback seqno when request creation fails (rev2)
== Series Details == Series: drm/i915: Rollback seqno when request creation fails (rev2) URL : https://patchwork.freedesktop.org/series/97562/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftests
On Fri, Dec 03, 2021 at 03:53:56PM -0800, Matthew Brost wrote:
> On Fri, Dec 03, 2021 at 03:30:57PM -0800, Bruce Chang wrote:
> > Follow up on patch https://patchwork.freedesktop.org/patch/446832/
> >
> > Different platforms will take a bit longer while GuC is enabled, so
> > increase the timeout and also add some margin in i915_gem_context
> > selftest.
> >
> > Signed-off-by: Bruce Chang
> > Cc: Matthew Brost
> > Cc: John Harrison
> > ---
> > drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> > b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> > index b32f7fed2d9c..ae33e8c705da 100644
> > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> > @@ -88,7 +88,7 @@ static int live_nop_switch(void *arg)
> > rq = i915_request_get(this);
> > i915_request_add(this);
> > }
> > - if (i915_request_wait(rq, 0, HZ) < 0) {
> > + if (i915_request_wait(rq, 0, 10*HZ) < 0) {
>
> s/10*HZ/10 * HZ/
>
> With that and an agreed upon audit of selftests / IGTs:
> Reviewed-by: Matthew Brost
> s/10*HZ/10 * HZ/
>
> With that and an agreed upon audit of selftests / IGTs:
> Reviewed-by: Matthew Brost
> s/10*HZ/10 * HZ/
>
> With that and an agreed upon audit of selftests / IGTs:
> Reviewed-by: Matthew Brost
> s/10*HZ/10 * HZ/
>
> With that and an agreed upon audit of selftests / IGTs:
> Reviewed-by: Matthew Brost
> s/10*HZ/10 * HZ/
>
> With that and an agreed upon audit of selftests / IGTs:
> Reviewed-by: Matthew Brost
> s/10*HZ/10 * HZ/
>
> With that and an agreed upon audit of selftests / IGTs:
> Reviewed-by: Matthew Brost
> s/10*HZ/10 * HZ/
>
> With that and an agreed upon audit of selftests / IGTs:
> Reviewed-by: Matthew Brost
> s/10*HZ/10 * HZ/
>
> With that and an agreed upon audit of selftests / IGTs:
> Reviewed-by: Matthew Brost
> s/10*HZ/10 * HZ/
>
> With that and an agreed upon audit of selftests / IGTs:
> Reviewed-by: Matthew Brost
>
^^^ Copy paste malfunction
> > pr_err("Failed to populated %d contexts\n", nctx);
> > intel_gt_set_wedged(&i915->gt);
> > i915_request_put(rq);
> > --
> > 2.21.3
> >
Re: [Intel-gfx] [PATCH 4/5] drm/i915/guc: Update to GuC version 69.0.0
On Fri, Dec 03, 2021 at 11:28:00PM +0100, Michal Wajdeczko wrote: > > > On 03.12.2021 19:33, john.c.harri...@intel.com wrote: > > From: John Harrison > > > > Update to the latest GuC release. > > > > The latest GuC firmware introduces a number of interface changes: > > Why can't we review all these changes in smaller patches and squash them > in separate CI series *after* collecting all required r-b ? > > Michal > I reviewed this and it seems pretty straight forward to me. I'm giving a RB, but we can hold up merging if you have an objection. Likely targeting an early next week merge so please raise any concerns before then. With that: Reviewed-by: Matthew Brost > > > > GuC may return NO_RESPONSE_RETRY message for requests sent over CTB. > > Add support for this reply and try resending the request again as a > > new CTB message. > > > > A KLV (key-length-value) mechanism is now used for passing > > configuration data such as CTB management. > > > > With the new KLV scheme, the old CTB management actions are no longer > > used and are removed. > > > > Register capture on hang is now supported by GuC. Full i915 support > > for this will be added by a later patch. A minimum support of > > providing capture memory and register lists is required though, so add > > that in. > > > > The device id of the current platform needs to be provided at init time. > > > > The 'poll CS' w/a (Wa_22012773006) was blanket enabled by previous > > versions of GuC. It must now be explicitly requested by the KMD. So, > > add in the code to turn it on when relevant. > > > > The GuC log entry format has changed. This requires adding a new field > > to the log header structure to mark the wrap point at the end of the > > buffer (as the buffer size is no longer a multiple of the log entry > > size). > > > > New CTB notification messages are now sent for some things that were > > previously only sent via MMIO notifications. > > > > Of these, the crash dump notification was not really being handled by > > i915. It called the log flush code but that only flushed the regular > > debug log and then only if relay logging was enabled. So just report > > an error message instead. > > > > The 'exception' notification was just being ignored completely. So add > > an error message for that as well. > > > > Note that in either the crash dump or the exception case, the GuC is > > basically dead. The KMD will detect this via the heartbeat and trigger > > both an error log (which will include the crash dump as part of the > > GuC log) and a GT reset. So no other processing is really required. > > > > Signed-off-by: John Harrison > > Signed-off-by: Michal Wajdeczko > > --- > > Documentation/gpu/i915.rst| 1 + > > .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 80 +- > > drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 82 ++ > > drivers/gpu/drm/i915/gt/uc/intel_guc.c| 126 +--- > > drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 + > > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 45 +- > > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 141 ++ > > drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 37 - > > drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 31 ++-- > > drivers/gpu/drm/i915/gt/uc/intel_guc_log.h| 3 + > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +++ > > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 30 ++-- > > 12 files changed, 434 insertions(+), 164 deletions(-) > > create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h > > > > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst > > index b7d801993bfa..bcaefc952764 100644 > > --- a/Documentation/gpu/i915.rst > > +++ b/Documentation/gpu/i915.rst > > @@ -539,6 +539,7 @@ GuC ABI > > .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h > > .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h > > .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > > +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h > > > > HuC > > --- > > diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > > b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > > index fe5d7d261797..7afdadc7656f 100644 > > --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > > +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > > @@ -7,9 +7,9 @@ > > #define _ABI_GUC_ACTIONS_ABI_H > > > > /** > > - * DOC: HOST2GUC_REGISTER_CTB > > + * DOC: HOST2GUC_SELF_CFG > > * > > - * This message is used as part of the `CTB based communication`_ setup. > > + * This message is used by Host KMD to setup of the `GuC Self Config > > KLVs`_. > > * > > * This message must be sent as `MMIO HXG Message`_. > > * > > @@ -22,20 +22,18 @@ > > * | > > +---+--+ > > * | | 27:16 | DATA0 = MBZ
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftests
On Fri, Dec 03, 2021 at 03:30:57PM -0800, Bruce Chang wrote:
> Follow up on patch https://patchwork.freedesktop.org/patch/446832/
>
> Different platforms will take a bit longer while GuC is enabled, so
> increase the timeout and also add some margin in i915_gem_context
> selftest.
>
> Signed-off-by: Bruce Chang
> Cc: Matthew Brost
> Cc: John Harrison
> ---
> drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> index b32f7fed2d9c..ae33e8c705da 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> @@ -88,7 +88,7 @@ static int live_nop_switch(void *arg)
> rq = i915_request_get(this);
> i915_request_add(this);
> }
> - if (i915_request_wait(rq, 0, HZ) < 0) {
> + if (i915_request_wait(rq, 0, 10*HZ) < 0) {
s/10*HZ/10 * HZ/
With that and an agreed upon audit of selftests / IGTs:
Reviewed-by: Matthew Brost
> pr_err("Failed to populated %d contexts\n", nctx);
> intel_gt_set_wedged(&i915->gt);
> i915_request_put(rq);
> --
> 2.21.3
>
[Intel-gfx] [PATCH] drm/i915: Rollback seqno when request creation fails
gem_ctx_create.basic-files can slam on kernel contexts to the extent
where request creation fails because the ring is full. When this happens
seqno numbers are skipped which can result the below GEM_BUG_ON blowing
in gt/intel_engine_pm.c:__engine_unpark:
GEM_BUG_ON(ce->timeline->seqno !=
READ_ONCE(*ce->timeline->hwsp_seqno));
Fixup request creation code to roll back seqno when request creation
fails.
v2:
(CI)
- Fix build error
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_timeline.c | 8
drivers/gpu/drm/i915/gt/intel_timeline.h | 1 +
drivers/gpu/drm/i915/i915_request.c | 1 +
3 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 438bbc7b8147..3785e5605549 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -301,6 +301,14 @@ static u32 timeline_advance(struct intel_timeline *tl)
return tl->seqno += 1 + tl->has_initial_breadcrumb;
}
+void intel_timeline_rollback_seqno(struct intel_timeline *tl)
+{
+ GEM_BUG_ON(!atomic_read(&tl->pin_count));
+ GEM_BUG_ON(tl->seqno & tl->has_initial_breadcrumb);
+
+ tl->seqno -= 1 + tl->has_initial_breadcrumb;
+}
+
static noinline int
__intel_timeline_get_seqno(struct intel_timeline *tl,
u32 *seqno)
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h
b/drivers/gpu/drm/i915/gt/intel_timeline.h
index 57308c4d664a..a2f2e0ea186f 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
@@ -72,6 +72,7 @@ void intel_timeline_enter(struct intel_timeline *tl);
int intel_timeline_get_seqno(struct intel_timeline *tl,
struct i915_request *rq,
u32 *seqno);
+void intel_timeline_rollback_seqno(struct intel_timeline *tl);
void intel_timeline_exit(struct intel_timeline *tl);
void intel_timeline_unpin(struct intel_timeline *tl);
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index a72c8f0346a0..86f32ee082f7 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -966,6 +966,7 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp)
err_unwind:
ce->ring->emit = rq->head;
+ intel_timeline_rollback_seqno(tl);
/* Make sure we didn't add ourselves to external state before freeing */
GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
--
2.33.1
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftests
== Series Details ==
Series: drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts
selftests
URL : https://patchwork.freedesktop.org/series/97577/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
06b07fd47af5 drm/i915/selftests: Follow up on increase timeout in
i915_gem_contexts selftests
-:26: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#26: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c:91:
+ if (i915_request_wait(rq, 0, 10*HZ) < 0) {
^
total: 0 errors, 0 warnings, 1 checks, 8 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Use local pointer ttm for __i915_ttm_move
== Series Details == Series: drm/i915/gem: Use local pointer ttm for __i915_ttm_move URL : https://patchwork.freedesktop.org/series/97572/ State : success == Summary == CI Bug Log - changes from CI_DRM_10963 -> Patchwork_21754 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/index.html Participating hosts (45 -> 33) -- Missing(12): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21754 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +31 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_exec_suspend@basic-s0: - fi-tgl-1115g4: [PASS][2] -> [FAIL][3] ([i915#1888]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html * igt@i915_selftest@live: - fi-skl-6600u: NOTRUN -> [INCOMPLETE][4] ([i915#198] / [i915#4547]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/fi-skl-6600u/igt@i915_selft...@live.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [PASS][6] -> [DMESG-WARN][7] ([i915#4269]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html * igt@runner@aborted: - fi-skl-6600u: NOTRUN -> [FAIL][8] ([i915#1436] / [i915#3363] / [i915#4312]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/fi-skl-6600u/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-bdw-5557u: [INCOMPLETE][9] ([i915#146]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 Build changes - * Linux: CI_DRM_10963 -> Patchwork_21754 CI-20190529: 20190529 CI_DRM_10963: 2b63a468d3e3c264a3d1a4773edfe8785d45d4ec @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6300: f69bd65fa9f72b7d5e5a5a22981f16d034334761 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21754: 4f37b82c97ecf25350ea6b94a7cf28c752db347f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4f37b82c97ec drm/i915/gem: Use local pointer ttm for __i915_ttm_move == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/index.html
[Intel-gfx] [PATCH] drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftests
Follow up on patch https://patchwork.freedesktop.org/patch/446832/
Different platforms will take a bit longer while GuC is enabled, so
increase the timeout and also add some margin in i915_gem_context
selftest.
Signed-off-by: Bruce Chang
Cc: Matthew Brost
Cc: John Harrison
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index b32f7fed2d9c..ae33e8c705da 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -88,7 +88,7 @@ static int live_nop_switch(void *arg)
rq = i915_request_get(this);
i915_request_add(this);
}
- if (i915_request_wait(rq, 0, HZ) < 0) {
+ if (i915_request_wait(rq, 0, 10*HZ) < 0) {
pr_err("Failed to populated %d contexts\n", nctx);
intel_gt_set_wedged(&i915->gt);
i915_request_put(rq);
--
2.21.3
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Use local pointer for __i915_ttm_move
== Series Details == Series: drm/i915/gem: Use local pointer for __i915_ttm_move URL : https://patchwork.freedesktop.org/series/97571/ State : success == Summary == CI Bug Log - changes from CI_DRM_10963 -> Patchwork_21753 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/index.html Participating hosts (45 -> 34) -- Missing(11): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21753 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +31 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@amdgpu/amd_prime@amd-to-i915: - fi-pnv-d510:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/fi-pnv-d510/igt@amdgpu/amd_pr...@amd-to-i915.html * igt@i915_selftest@live@execlists: - fi-bsw-n3050: [PASS][3] -> [INCOMPLETE][4] ([i915#2940]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_engines: - fi-rkl-guc: [PASS][5] -> [INCOMPLETE][6] ([i915#4432]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html * igt@runner@aborted: - fi-rkl-guc: NOTRUN -> [FAIL][8] ([i915#3928] / [i915#4312]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/fi-rkl-guc/igt@run...@aborted.html - fi-bsw-n3050: NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/fi-bsw-n3050/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-bdw-5557u: [INCOMPLETE][10] ([i915#146]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live@requests: - fi-pnv-d510:[DMESG-FAIL][12] -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-pnv-d510/igt@i915_selftest@l...@requests.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/fi-pnv-d510/igt@i915_selftest@l...@requests.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432 Build changes - * Linux: CI_DRM_10963 -> Patchwork_21753 CI-20190529: 20190529 CI_DRM_10963: 2b63a468d3e3c264a3d1a4773edfe8785d45d4ec @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6300: f69bd65fa9f72b7d5e5a5a22981f16d034334761 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21753: c48a10e7ad67411f65b8c32858f3041275fdbfc0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c48a10e7ad67 drm/i915/gem: Use local pointer for __i915_ttm_move == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/index.html
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gem: Use local pointer ttm for __i915_ttm_move
== Series Details == Series: drm/i915/gem: Use local pointer ttm for __i915_ttm_move URL : https://patchwork.freedesktop.org/series/97572/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4f37b82c97ec drm/i915/gem: Use local pointer ttm for __i915_ttm_move -:22: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) total: 1 errors, 0 warnings, 0 checks, 8 lines checked
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gem: Use local pointer for __i915_ttm_move
== Series Details == Series: drm/i915/gem: Use local pointer for __i915_ttm_move URL : https://patchwork.freedesktop.org/series/97571/ State : warning == Summary == $ dim checkpatch origin/drm-tip c48a10e7ad67 drm/i915/gem: Use local pointer for __i915_ttm_move -:21: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) total: 1 errors, 0 warnings, 0 checks, 8 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for Update to GuC version 69.0.0
== Series Details == Series: Update to GuC version 69.0.0 URL : https://patchwork.freedesktop.org/series/97564/ State : success == Summary == CI Bug Log - changes from CI_DRM_10963 -> Patchwork_21752 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/index.html Participating hosts (45 -> 34) -- Missing(11): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21752 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_parallel@engines@userptr: - fi-pnv-d510:[PASS][1] -> [INCOMPLETE][2] ([i915#299]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-pnv-d510/igt@gem_exec_parallel@engi...@userptr.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/fi-pnv-d510/igt@gem_exec_parallel@engi...@userptr.html * igt@gem_exec_suspend@basic-s3: - fi-skl-6600u: [PASS][3] -> [INCOMPLETE][4] ([i915#4547]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live@gt_engines: - fi-rkl-guc: [PASS][5] -> [INCOMPLETE][6] ([i915#4432]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#4269]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][9] ([i915#2426] / [i915#4312]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/fi-bdw-5557u/igt@run...@aborted.html - fi-rkl-guc: NOTRUN -> [FAIL][10] ([i915#3928] / [i915#4312]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/fi-rkl-guc/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-bdw-5557u: [INCOMPLETE][11] ([i915#146]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html Warnings * igt@runner@aborted: - fi-pnv-d510:[FAIL][13] ([fdo#109271] / [i915#2403] / [i915#4312]) -> [FAIL][14] ([i915#2403] / [i915#2722] / [i915#4312]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-pnv-d510/igt@run...@aborted.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/fi-pnv-d510/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722 [i915#299]: https://gitlab.freedesktop.org/drm/intel/issues/299 [i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 Build changes - * Linux: CI_DRM_10963 -> Patchwork_21752 CI-20190529: 20190529 CI_DRM_10963: 2b63a468d3e3c264a3d1a4773edfe8785d45d4ec @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6300: f69bd65fa9f72b7d5e5a5a22981f16d034334761 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21752: 25e36b6914e27199304dfa603366e6bc78288206 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 25e36b6914e2 drm/i915/guc: Improve GuC loading status check/error reports b1173763d5c2 drm/i915/guc: Update to GuC version 69.0.0 dcbfeb6078aa drm/i915/guc: Don't go bang in GuC log if no GuC 0c27c3d306db drm/i915/guc: Increase GuC log size for CONFIG_DEBUG_GEM 1ba090939f4f drm/i915/uc: Allow platforms to have GuC but not HuC == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/index.html
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gen11: Moving WAs to icl_gt_workarounds_init() (rev4)
== Series Details == Series: drm/i915/gen11: Moving WAs to icl_gt_workarounds_init() (rev4) URL : https://patchwork.freedesktop.org/series/97208/ State : success == Summary == CI Bug Log - changes from CI_DRM_10961_full -> Patchwork_21747_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_21747_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-apl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [FAIL][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#4386]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl6/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl6/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl6/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl7/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl7/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl8/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl8/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl8/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl7/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl7/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl8/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl8/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl1/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl1/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl1/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl2/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl2/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl2/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl3/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl3/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl3/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl3/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl4/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/shard-apl4/boot.html [44]: https://intel-
Re: [Intel-gfx] [PATCH 4/5] drm/i915/guc: Update to GuC version 69.0.0
On 03.12.2021 19:33, john.c.harri...@intel.com wrote: > From: John Harrison > > Update to the latest GuC release. > > The latest GuC firmware introduces a number of interface changes: Why can't we review all these changes in smaller patches and squash them in separate CI series *after* collecting all required r-b ? Michal > > GuC may return NO_RESPONSE_RETRY message for requests sent over CTB. > Add support for this reply and try resending the request again as a > new CTB message. > > A KLV (key-length-value) mechanism is now used for passing > configuration data such as CTB management. > > With the new KLV scheme, the old CTB management actions are no longer > used and are removed. > > Register capture on hang is now supported by GuC. Full i915 support > for this will be added by a later patch. A minimum support of > providing capture memory and register lists is required though, so add > that in. > > The device id of the current platform needs to be provided at init time. > > The 'poll CS' w/a (Wa_22012773006) was blanket enabled by previous > versions of GuC. It must now be explicitly requested by the KMD. So, > add in the code to turn it on when relevant. > > The GuC log entry format has changed. This requires adding a new field > to the log header structure to mark the wrap point at the end of the > buffer (as the buffer size is no longer a multiple of the log entry > size). > > New CTB notification messages are now sent for some things that were > previously only sent via MMIO notifications. > > Of these, the crash dump notification was not really being handled by > i915. It called the log flush code but that only flushed the regular > debug log and then only if relay logging was enabled. So just report > an error message instead. > > The 'exception' notification was just being ignored completely. So add > an error message for that as well. > > Note that in either the crash dump or the exception case, the GuC is > basically dead. The KMD will detect this via the heartbeat and trigger > both an error log (which will include the crash dump as part of the > GuC log) and a GT reset. So no other processing is really required. > > Signed-off-by: John Harrison > Signed-off-by: Michal Wajdeczko > --- > Documentation/gpu/i915.rst| 1 + > .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 80 +- > drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 82 ++ > drivers/gpu/drm/i915/gt/uc/intel_guc.c| 126 +--- > drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 + > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 45 +- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 141 ++ > drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 37 - > drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 31 ++-- > drivers/gpu/drm/i915/gt/uc/intel_guc_log.h| 3 + > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +++ > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 30 ++-- > 12 files changed, 434 insertions(+), 164 deletions(-) > create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h > > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst > index b7d801993bfa..bcaefc952764 100644 > --- a/Documentation/gpu/i915.rst > +++ b/Documentation/gpu/i915.rst > @@ -539,6 +539,7 @@ GuC ABI > .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h > .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h > .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h > > HuC > --- > diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > index fe5d7d261797..7afdadc7656f 100644 > --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > @@ -7,9 +7,9 @@ > #define _ABI_GUC_ACTIONS_ABI_H > > /** > - * DOC: HOST2GUC_REGISTER_CTB > + * DOC: HOST2GUC_SELF_CFG > * > - * This message is used as part of the `CTB based communication`_ setup. > + * This message is used by Host KMD to setup of the `GuC Self Config KLVs`_. > * > * This message must be sent as `MMIO HXG Message`_. > * > @@ -22,20 +22,18 @@ > * | > +---+--+ > * | | 27:16 | DATA0 = MBZ > | > * | > +---+--+ > - * | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_REGISTER_CTB` = 0x4505 > | > + * | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_SELF_CFG` = 0x0508 > | > * > +---+---+--+ > - * | 1 | 31:12 | RESERVED = MBZ > | > + * | 1 | 31:16 | **KLV_KEY** - KLV key, see `GuC Self Config KLVs`_
[Intel-gfx] ✗ Fi.CI.DOCS: warning for Update to GuC version 69.0.0
== Series Details == Series: Update to GuC version 69.0.0 URL : https://patchwork.freedesktop.org/series/97564/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915:542: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h:44: WARNING: Inline target start-string without end-string. /home/cidrm/kernel/Documentation/gpu/i915:542: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h:48: WARNING: Inline target start-string without end-string. /home/cidrm/kernel/Documentation/gpu/i915:542: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h:52: WARNING: Inline target start-string without end-string.
[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce new i915 macros for checking PTEs (rev5)
== Series Details ==
Series: Introduce new i915 macros for checking PTEs (rev5)
URL : https://patchwork.freedesktop.org/series/96679/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10963 -> Patchwork_21750
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21750/index.html
Participating hosts (45 -> 33)
--
Missing(12): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan
bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus bat-jsl-2 bat-jsl-1
Known issues
Here are the changes found in Patchwork_21750 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [PASS][1] -> [FAIL][2] ([i915#1888])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21750/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@gt_engines:
- fi-rkl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#4432])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21750/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#4269])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21750/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
* igt@runner@aborted:
- fi-rkl-guc: NOTRUN -> [FAIL][7] ([i915#3928] / [i915#4312])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21750/fi-rkl-guc/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432
Build changes
-
* Linux: CI_DRM_10963 -> Patchwork_21750
CI-20190529: 20190529
CI_DRM_10963: 2b63a468d3e3c264a3d1a4773edfe8785d45d4ec @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6300: f69bd65fa9f72b7d5e5a5a22981f16d034334761 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21750: 998f668db4002df4c70816c84b1c5fc07530903e @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
998f668db400 drm/i915: Introduce new macros for i915 PTE
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21750/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Update to GuC version 69.0.0
== Series Details == Series: Update to GuC version 69.0.0 URL : https://patchwork.freedesktop.org/series/97564/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Update to GuC version 69.0.0
== Series Details == Series: Update to GuC version 69.0.0 URL : https://patchwork.freedesktop.org/series/97564/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1ba090939f4f drm/i915/uc: Allow platforms to have GuC but not HuC -:37: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #37: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:51: +#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \ + fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3)) \ + fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0)) \ + fw_def(DG1, 0, guc_def(dg1, 62, 0, 0)) \ + fw_def(ROCKETLAKE, 0, guc_def(tgl, 62, 0, 0)) \ + fw_def(TIGERLAKE,0, guc_def(tgl, 62, 0, 0)) \ + fw_def(JASPERLAKE, 0, guc_def(ehl, 62, 0, 0)) \ + fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0)) \ + fw_def(ICELAKE, 0, guc_def(icl, 62, 0, 0)) \ + fw_def(COMETLAKE,5, guc_def(cml, 62, 0, 0)) \ + fw_def(COMETLAKE,0, guc_def(kbl, 62, 0, 0)) \ + fw_def(COFFEELAKE, 0, guc_def(kbl, 62, 0, 0)) \ + fw_def(GEMINILAKE, 0, guc_def(glk, 62, 0, 0)) \ + fw_def(KABYLAKE, 0, guc_def(kbl, 62, 0, 0)) \ + fw_def(BROXTON, 0, guc_def(bxt, 62, 0, 0)) \ + fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0)) -:37: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fw_def' - possible side-effects? #37: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:51: +#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \ + fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3)) \ + fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0)) \ + fw_def(DG1, 0, guc_def(dg1, 62, 0, 0)) \ + fw_def(ROCKETLAKE, 0, guc_def(tgl, 62, 0, 0)) \ + fw_def(TIGERLAKE,0, guc_def(tgl, 62, 0, 0)) \ + fw_def(JASPERLAKE, 0, guc_def(ehl, 62, 0, 0)) \ + fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0)) \ + fw_def(ICELAKE, 0, guc_def(icl, 62, 0, 0)) \ + fw_def(COMETLAKE,5, guc_def(cml, 62, 0, 0)) \ + fw_def(COMETLAKE,0, guc_def(kbl, 62, 0, 0)) \ + fw_def(COFFEELAKE, 0, guc_def(kbl, 62, 0, 0)) \ + fw_def(GEMINILAKE, 0, guc_def(glk, 62, 0, 0)) \ + fw_def(KABYLAKE, 0, guc_def(kbl, 62, 0, 0)) \ + fw_def(BROXTON, 0, guc_def(bxt, 62, 0, 0)) \ + fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0)) -:37: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'guc_def' - possible side-effects? #37: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:51: +#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \ + fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3)) \ + fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0)) \ + fw_def(DG1, 0, guc_def(dg1, 62, 0, 0)) \ + fw_def(ROCKETLAKE, 0, guc_def(tgl, 62, 0, 0)) \ + fw_def(TIGERLAKE,0, guc_def(tgl, 62, 0, 0)) \ + fw_def(JASPERLAKE, 0, guc_def(ehl, 62, 0, 0)) \ + fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0)) \ + fw_def(ICELAKE, 0, guc_def(icl, 62, 0, 0)) \ + fw_def(COMETLAKE,5, guc_def(cml, 62, 0, 0)) \ + fw_def(COMETLAKE,0, guc_def(kbl, 62, 0, 0)) \ + fw_def(COFFEELAKE, 0, guc_def(kbl, 62, 0, 0)) \ + fw_def(GEMINILAKE, 0, guc_def(glk, 62, 0, 0)) \ + fw_def(KABYLAKE, 0, guc_def(kbl, 62, 0, 0)) \ + fw_def(BROXTON, 0, guc_def(bxt, 62, 0, 0)) \ + fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0)) -:54: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #54: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:68: +#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \ + fw_def(ALDERLAKE_P, 0, huc_def(tgl, 7, 9, 3)) \ + fw_def(ALDERLAKE_S, 0, huc_def(tgl, 7, 9, 3)) \ + fw_def(DG1, 0, huc_def(dg1, 7, 9, 3)) \ + fw_def(ROCKETLAKE, 0, huc_def(tgl, 7, 9, 3)) \ + fw_def(TIGERLAKE,0, huc_def(tgl, 7, 9, 3)) \ + fw_def(JASPERLAKE, 0, huc_def(ehl, 9, 0, 0)) \ + fw_def(ELKHARTLAKE, 0, huc_def(ehl, 9, 0, 0)) \ + fw_def(ICELAKE, 0, huc_def(icl, 9, 0, 0)) \ + fw_def(COMETLAKE,5, huc_def(cml, 4, 0, 0)) \ + fw_def(COMETLAKE,0, huc_def(kbl, 4, 0, 0)) \ + fw_def(COFFEELAKE, 0, huc_def(kbl, 4, 0, 0)) \ + fw_def(GEMINILAKE, 0, huc_def(glk, 4, 0, 0)) \ + fw_def(KABYLAKE, 0, huc_def(kbl, 4, 0, 0)) \ + fw_def(BROXTON, 0, huc_def(bxt, 2, 0, 0)) \ + fw_def(SKYLAKE, 0, huc_def(skl, 2, 0, 0)) -:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fw_def' - possible side-effects? #54: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:68: +#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \ + fw_def(ALDERLAKE_P, 0, huc_def(tgl, 7, 9, 3)) \ + fw_def(ALDERLAKE_S, 0, huc_def(tgl, 7, 9, 3)) \ + fw_def(DG1, 0, huc_def(dg1, 7, 9, 3)) \ + fw_def(ROCKETLAKE, 0, huc_def(tgl, 7, 9, 3)) \ + fw_def(TIGERLAKE,
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Rollback seqno when request creation fails
== Series Details == Series: drm/i915: Rollback seqno when request creation fails URL : https://patchwork.freedesktop.org/series/97562/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/gt/intel_timeline.o drivers/gpu/drm/i915/gt/intel_timeline.c: In function ‘intel_timeline_rollback_seqno’: drivers/gpu/drm/i915/gt/intel_timeline.c:306:2: error: implicit declaration of function ‘timeline_rollback’; did you mean ‘timeline_advance’? [-Werror=implicit-function-declaration] timeline_rollback(tl); ^ timeline_advance cc1: all warnings being treated as errors scripts/Makefile.build:287: recipe for target 'drivers/gpu/drm/i915/gt/intel_timeline.o' failed make[4]: *** [drivers/gpu/drm/i915/gt/intel_timeline.o] Error 1 scripts/Makefile.build:549: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:549: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:549: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1846: recipe for target 'drivers' failed make: *** [drivers] Error 2
[Intel-gfx] [PATCH] drm/i915/gem: Use local pointer ttm for __i915_ttm_move
To avoid confusion with deferencing possible null pointer bo->ttm, replace pointer bo->ttm with local pointer ttm in i915_ttm_move as ttm has checks for null before getting passed to __i915_ttm_move --- drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c index 80df9f592407..56b6573b5c93 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c @@ -763,7 +763,7 @@ int i915_ttm_move(struct ttm_buffer_object *bo, bool evict, return PTR_ERR(dep); } - migration_fence = __i915_ttm_move(bo, clear, dst_mem, bo->ttm, + migration_fence = __i915_ttm_move(bo, clear, dst_mem, ttm, dst_rsgt, true, dep); dma_fence_put(dep); } -- 2.25.1
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce new i915 macros for checking PTEs (rev5)
== Series Details == Series: Introduce new i915 macros for checking PTEs (rev5) URL : https://patchwork.freedesktop.org/series/96679/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v5,1/1] drm/i915: Introduce new macros for i915 PTE
== Series Details == Series: series starting with [v5,1/1] drm/i915: Introduce new macros for i915 PTE URL : https://patchwork.freedesktop.org/series/97559/ State : failure == Summary == Patch is empty. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/ddi: add use_edp_hobl() and use_edp_low_vswing() helpers
== Series Details == Series: drm/i915/ddi: add use_edp_hobl() and use_edp_low_vswing() helpers URL : https://patchwork.freedesktop.org/series/97547/ State : success == Summary == CI Bug Log - changes from CI_DRM_10961_full -> Patchwork_21745_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_21745_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-apl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [FAIL][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#4386]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl6/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl6/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl6/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl7/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl7/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl8/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl8/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl8/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl6/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl7/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl6/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl7/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl7/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl8/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl6/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl8/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl4/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl4/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl8/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl4/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl8/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl3/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl3/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl3/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl3/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/shard-apl2/boot.html [44]: https://int
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Use hw_engine_masks as reset_domains
== Series Details == Series: drm/i915/gt: Use hw_engine_masks as reset_domains URL : https://patchwork.freedesktop.org/series/97543/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10961_full -> Patchwork_21743_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21743_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21743_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21743_full: ### IGT changes ### Possible regressions * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-tglb1/igt@kms_flip_scaled_...@flip-64bpp-ytile-to-32bpp-ytile.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21743/shard-tglb8/igt@kms_flip_scaled_...@flip-64bpp-ytile-to-32bpp-ytile.html Known issues Here are the changes found in Patchwork_21743_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-apl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [FAIL][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) ([i915#4386]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl6/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl7/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl7/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl8/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl8/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl8/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21743/shard-apl1/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21743/shard-apl1/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21743/shard-apl1/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21743/shard-apl2/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21743/shard-apl2/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21743/shard-apl2/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21743/shard-apl2/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21743/shard-apl3/boot.html [36]: https://intel-g
Re: [Intel-gfx] [PATCH] drm/i915/gem: Use local pointer for __i915_ttm_move
On Fri, Dec 03, 2021 at 12:47:53PM -0800, Jasmine Newsome wrote: > Replace pointer bo->ttm with ttm in i915_ttm_move > when passed as argument to __i915_ttm_move Hi Jasmine, Can you please resend this patch with the commit description updated to describe why this patch is needed? Thanks, Sudeep Dutt > --- > drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c > b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c > index 80df9f592407..56b6573b5c93 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c > @@ -763,7 +763,7 @@ int i915_ttm_move(struct ttm_buffer_object *bo, bool > evict, > return PTR_ERR(dep); > } > > - migration_fence = __i915_ttm_move(bo, clear, dst_mem, bo->ttm, > + migration_fence = __i915_ttm_move(bo, clear, dst_mem, ttm, > dst_rsgt, true, dep); > dma_fence_put(dep); > } > -- > 2.25.1 >
[Intel-gfx] [PATCH] drm/i915/gem: Use local pointer for __i915_ttm_move
Replace pointer bo->ttm with ttm in i915_ttm_move when passed as argument to __i915_ttm_move --- drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c index 80df9f592407..56b6573b5c93 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c @@ -763,7 +763,7 @@ int i915_ttm_move(struct ttm_buffer_object *bo, bool evict, return PTR_ERR(dep); } - migration_fence = __i915_ttm_move(bo, clear, dst_mem, bo->ttm, + migration_fence = __i915_ttm_move(bo, clear, dst_mem, ttm, dst_rsgt, true, dep); dma_fence_put(dep); } -- 2.25.1
Re: [Intel-gfx] [PATCH bpf v2] treewide: add missing includes masked by cgroup -> bpf dependency
Hello: This patch was applied to bpf/bpf.git (master) by Alexei Starovoitov : On Thu, 2 Dec 2021 12:34:00 -0800 you wrote: > cgroup.h (therefore swap.h, therefore half of the universe) > includes bpf.h which in turn includes module.h and slab.h. > Since we're about to get rid of that dependency we need > to clean things up. > > v2: drop the cpu.h include from cacheinfo.h, it's not necessary > and it makes riscv sensitive to ordering of include files. > > [...] Here is the summary with links: - [bpf,v2] treewide: add missing includes masked by cgroup -> bpf dependency https://git.kernel.org/bpf/bpf/c/8581fd402a0c You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html
Re: [Intel-gfx] [PATCH 2/5] drm/i915/guc: Increase GuC log size for CONFIG_DEBUG_GEM
On Fri, Dec 03, 2021 at 10:33:36AM -0800, john.c.harri...@intel.com wrote: > From: John Harrison > > Lots of testing is done with the DEBUG_GEM config option enabled but > not the DEBUG_GUC option. That means we only get teeny-tiny GuC logs > which are not hugely useful. Enabling full DEBUG_GUC also spews lots > of other detailed output that is not generally desired. However, > bigger GuC logs are extremely useful for almost any regression debug. > So enable bigger logs for DEBUG_GEM builds as well. > > Signed-off-by: John Harrison Reviewed-by: Matthew Brost > --- > drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h > b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h > index ac1ee1d5ce10..fe6ab7550a14 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h > @@ -15,9 +15,12 @@ > > struct intel_guc; > > -#ifdef CONFIG_DRM_I915_DEBUG_GUC > +#if defined(CONFIG_DRM_I915_DEBUG_GUC) > #define CRASH_BUFFER_SIZESZ_2M > #define DEBUG_BUFFER_SIZESZ_16M > +#elif defined(CONFIG_DRM_I915_DEBUG_GEM) > +#define CRASH_BUFFER_SIZESZ_1M > +#define DEBUG_BUFFER_SIZESZ_2M > #else > #define CRASH_BUFFER_SIZESZ_8K > #define DEBUG_BUFFER_SIZESZ_64K > -- > 2.25.1 >
Re: [Intel-gfx] [PATCH 5/5] drm/i915/guc: Improve GuC loading status check/error reports
On Fri, Dec 03, 2021 at 10:33:39AM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> If the GuC fails to load, it is useful to know what firmware file /
> version was attempted. So move the version info report to before the
> load attempt rather than only after a successful load.
>
> If the GuC does fail to load, then make the error messages visible
> rather than being 'debug' prints that do not appears in dmesg output
> by default.
>
> When waiting for the GuC to load, it used to be necessary to check for
> two different states - READY and (LAPIC_DONE | MIA_CORE). Apparently
> the second signified init complete on RC6 exit. However, in more
> recent GuC versions the RC6 exit sequence now finishes with status
> READY as well. So the test can be simplified.
>
> Also, add an enum giving all the current status codes that GuC loading
> can report as a reference without having to pull and search through
> the GuC source files.
>
> Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
> ---
> .../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 23 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 17 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h| 4 ---
> drivers/gpu/drm/i915/gt/uc/intel_huc.c| 1 +
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 31 ++-
> 5 files changed, 48 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
> index 488b6061ee89..c20658ee85a5 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
> @@ -11,4 +11,27 @@ enum intel_guc_response_status {
> INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
> };
>
> +enum intel_guc_load_status {
> + INTEL_GUC_LOAD_STATUS_DEFAULT = 0x00,
> + INTEL_GUC_LOAD_STATUS_START= 0x01,
> + INTEL_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH = 0x02,
> + INTEL_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH = 0x03,
> + INTEL_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE = 0x04,
> + INTEL_GUC_LOAD_STATUS_GDT_DONE = 0x10,
> + INTEL_GUC_LOAD_STATUS_IDT_DONE = 0x20,
> + INTEL_GUC_LOAD_STATUS_LAPIC_DONE = 0x30,
> + INTEL_GUC_LOAD_STATUS_GUCINT_DONE = 0x40,
> + INTEL_GUC_LOAD_STATUS_DPC_READY= 0x50,
> + INTEL_GUC_LOAD_STATUS_DPC_ERROR= 0x60,
> + INTEL_GUC_LOAD_STATUS_EXCEPTION= 0x70,
> + INTEL_GUC_LOAD_STATUS_INIT_DATA_INVALID= 0x71,
> + INTEL_GUC_LOAD_STATUS_PXP_TEARDOWN_CTRL_ENABLED= 0x72,
> + INTEL_GUC_LOAD_STATUS_INVALID_INIT_DATA_RANGE_START,
> + INTEL_GUC_LOAD_STATUS_MPU_DATA_INVALID = 0x73,
> + INTEL_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID = 0x74,
> + INTEL_GUC_LOAD_STATUS_INVALID_INIT_DATA_RANGE_END,
> +
> + INTEL_GUC_LOAD_STATUS_READY= 0xF0,
> +};
> +
> #endif /* _ABI_GUC_ERRORS_ABI_H */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> index 196424be0998..d3cee01d07e0 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> @@ -70,11 +70,10 @@ static int guc_xfer_rsa(struct intel_uc_fw *guc_fw,
> static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
> {
> u32 val = intel_uncore_read(uncore, GUC_STATUS);
> - u32 uk_val = val & GS_UKERNEL_MASK;
> + u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val);
>
> *status = val;
> - return (uk_val == GS_UKERNEL_READY) ||
> - ((val & GS_MIA_CORE_STATE) && (uk_val ==
> GS_UKERNEL_LAPIC_DONE));
> + return uk_val == INTEL_GUC_LOAD_STATUS_READY;
> }
>
> static int guc_wait_ucode(struct intel_uncore *uncore)
> @@ -94,8 +93,8 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
> if (ret) {
> struct drm_device *drm = &uncore->i915->drm;
>
> - drm_dbg(drm, "GuC load failed: status = 0x%08X\n", status);
> - drm_dbg(drm, "GuC load failed: status: Reset = %d, "
> + drm_info(drm, "GuC load failed: status = 0x%08X\n", status);
> + drm_info(drm, "GuC load failed: status: Reset = %d, "
> "BootROM = 0x%02X, UKernel = 0x%02X, "
> "MIA = 0x%02X, Auth = 0x%02X\n",
> REG_FIELD_GET(GS_MIA_IN_RESET, status),
> @@ -105,13 +104,13 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
> REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
>
> if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
> - drm_dbg(drm, "GuC firmware signature verification
> failed\n");
>
Re: [Intel-gfx] [PATCH 4/4] drm/i915/guc: Don't go bang in GuC log if no GuC
On 12/2/2021 4:33 PM, Lucas De Marchi wrote:
On Thu, Dec 02, 2021 at 04:06:23PM -0800, john.c.harri...@intel.com
wrote:
From: John Harrison
If the GuC has failed to load for any reason and then the user pokes
the debugfs GuC log interface, a BUG and/or null pointer deref can
occur. Don't let that happen.
Signed-off-by: John Harrison
Reviewed-by: Lucas De Marchi
Lucas De Marchi
Do we need a fixes tag? or is it ok to not have it for debugfs bugs?
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
index 46026c2c1722..8fd068049376 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
@@ -31,7 +31,7 @@ static int guc_log_level_get(void *data, u64 *val)
{
struct intel_guc_log *log = data;
- if (!intel_guc_is_used(log_to_guc(log)))
+ if (!log->vma)
return -ENODEV;
*val = intel_guc_log_get_level(log);
@@ -43,7 +43,7 @@ static int guc_log_level_set(void *data, u64 val)
{
struct intel_guc_log *log = data;
- if (!intel_guc_is_used(log_to_guc(log)))
+ if (!log->vma)
return -ENODEV;
return intel_guc_log_set_level(log, val);
--
2.25.1
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Nuke {pipe, plane}_to_crtc_mapping[]
== Series Details ==
Series: series starting with [1/3] drm/i915: Nuke {pipe,
plane}_to_crtc_mapping[]
URL : https://patchwork.freedesktop.org/series/97541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10961_full -> Patchwork_21742_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (10 -> 10)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_21742_full that come from known
issues:
### CI changes ###
Possible fixes
* boot:
- shard-apl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4],
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11],
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17],
[PASS][18], [PASS][19], [PASS][20], [FAIL][21], [PASS][22], [PASS][23],
[PASS][24], [PASS][25]) ([i915#4386]) -> ([PASS][26], [PASS][27], [PASS][28],
[PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34],
[PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40],
[PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46],
[PASS][47], [PASS][48], [PASS][49], [PASS][50])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl4/boot.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl6/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl6/boot.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl6/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl7/boot.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl7/boot.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl8/boot.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl8/boot.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl8/boot.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl1/boot.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl2/boot.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/shard-apl3/boot.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl2/boot.html
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl2/boot.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl8/boot.html
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl8/boot.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl8/boot.html
[31]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl7/boot.html
[32]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl7/boot.html
[33]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl7/boot.html
[34]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl7/boot.html
[35]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl6/boot.html
[36]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl6/boot.html
[37]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl6/boot.html
[38]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl6/boot.html
[39]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl1/boot.html
[40]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl4/boot.html
[41]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl4/boot.html
[42]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl4/boot.html
[43]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/shard-apl1/boot.html
[44]:
ht
Re: [Intel-gfx] [PATCH] drm/i915: Fix error pointer dereference in i915_gem_do_execbuffer()
On Wed, Dec 01, 2021 at 08:48:31PM -0800, Matthew Brost wrote:
> From: Dan Carpenter
>
> Originally "out_fence" was set using out_fence = sync_file_create() but
> which returns NULL, but now it is set with out_fence = eb_requests_create()
> which returns error pointers. The error path needs to be modified to
> avoid an Oops in the "goto err_request;" path.
>
> Fixes: 544460c33821 ("drm/i915: Multi-BB execbuf")
> Signed-off-by: Dan Carpenter
> Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 9f7c6ecadb90..6db588b9a30e 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -3288,6 +3288,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
> out_fence = eb_requests_create(&eb, in_fence, out_fence_fd);
> if (IS_ERR(out_fence)) {
> err = PTR_ERR(out_fence);
> + out_fence = NULL;
> if (eb.requests[0])
> goto err_request;
> else
> --
> 2.33.1
>
Re: [Intel-gfx] [PATCH bpf v2] treewide: add missing includes masked by cgroup -> bpf dependency
On Thu, Dec 2, 2021 at 11:11 PM Greg KH wrote: > > On Thu, Dec 02, 2021 at 12:34:00PM -0800, Jakub Kicinski wrote: > > cgroup.h (therefore swap.h, therefore half of the universe) > > includes bpf.h which in turn includes module.h and slab.h. > > Since we're about to get rid of that dependency we need > > to clean things up. > > > > v2: drop the cpu.h include from cacheinfo.h, it's not necessary > > and it makes riscv sensitive to ordering of include files. > > > > Link: https://lore.kernel.org/all/20211120035253.72074-1-k...@kernel.org/ > > # v1 > > Link: https://lore.kernel.org/all/20211120165528.197359-1-k...@kernel.org/ > > # cacheinfo discussion > > Acked-by: Krzysztof Wilczyński > > Acked-by: Peter Chen > > Acked-by: SeongJae Park > > Acked-by: Jani Nikula > > Signed-off-by: Jakub Kicinski > > Acked-by: Greg Kroah-Hartman I'm not sure how to test that it helps to reduce build deps, but it builds and passes tests, so applied to bpf tree. Jakub, you'll soon get it back via bpf tree PR :)
Re: [Intel-gfx] [PATCH 1/5] drm/i915/uc: Allow platforms to have GuC but not HuC
On Fri, Dec 03, 2021 at 10:33:35AM -0800, john.c.harri...@intel.com wrote:
From: John Harrison
It is possible for platforms to require GuC but not HuC firmware.
Also, the firmware versions for GuC and HuC advance independently. So
split the macros up to allow the lists to be maintained separately.
Signed-off-by: John Harrison
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 93
1 file changed, 63 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 3aa87be4f2e4..a7788ce50736 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -48,22 +48,39 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
* Note that RKL and ADL-S have the same GuC/HuC device ID's and use the same
* firmware as TGL.
*/
-#define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
- fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3), huc_def(tgl, 7, 9, 3)) \
- fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
- fw_def(DG1, 0, guc_def(dg1, 62, 0, 0), huc_def(dg1, 7, 9, 3)) \
- fw_def(ROCKETLAKE, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
- fw_def(TIGERLAKE, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
- fw_def(JASPERLAKE, 0, guc_def(ehl, 62, 0, 0), huc_def(ehl, 9, 0, 0)) \
- fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0), huc_def(ehl, 9, 0, 0)) \
- fw_def(ICELAKE, 0, guc_def(icl, 62, 0, 0), huc_def(icl, 9, 0, 0)) \
- fw_def(COMETLAKE, 5, guc_def(cml, 62, 0, 0), huc_def(cml, 4, 0, 0)) \
- fw_def(COMETLAKE, 0, guc_def(kbl, 62, 0, 0), huc_def(kbl, 4, 0, 0)) \
- fw_def(COFFEELAKE, 0, guc_def(kbl, 62, 0, 0), huc_def(kbl, 4, 0, 0)) \
- fw_def(GEMINILAKE, 0, guc_def(glk, 62, 0, 0), huc_def(glk, 4, 0, 0)) \
- fw_def(KABYLAKE,0, guc_def(kbl, 62, 0, 0), huc_def(kbl, 4, 0, 0)) \
- fw_def(BROXTON, 0, guc_def(bxt, 62, 0, 0), huc_def(bxt, 2, 0, 0)) \
- fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0), huc_def(skl, 2, 0, 0))
+#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \
+ fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3)) \
+ fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0)) \
+ fw_def(DG1, 0, guc_def(dg1, 62, 0, 0)) \
+ fw_def(ROCKETLAKE, 0, guc_def(tgl, 62, 0, 0)) \
+ fw_def(TIGERLAKE,0, guc_def(tgl, 62, 0, 0)) \
+ fw_def(JASPERLAKE, 0, guc_def(ehl, 62, 0, 0)) \
+ fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0)) \
+ fw_def(ICELAKE, 0, guc_def(icl, 62, 0, 0)) \
+ fw_def(COMETLAKE,5, guc_def(cml, 62, 0, 0)) \
+ fw_def(COMETLAKE,0, guc_def(kbl, 62, 0, 0)) \
+ fw_def(COFFEELAKE, 0, guc_def(kbl, 62, 0, 0)) \
+ fw_def(GEMINILAKE, 0, guc_def(glk, 62, 0, 0)) \
+ fw_def(KABYLAKE, 0, guc_def(kbl, 62, 0, 0)) \
+ fw_def(BROXTON, 0, guc_def(bxt, 62, 0, 0)) \
+ fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0))
+
+#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \
+ fw_def(ALDERLAKE_P, 0, huc_def(tgl, 7, 9, 3)) \
+ fw_def(ALDERLAKE_S, 0, huc_def(tgl, 7, 9, 3)) \
+ fw_def(DG1, 0, huc_def(dg1, 7, 9, 3)) \
+ fw_def(ROCKETLAKE, 0, huc_def(tgl, 7, 9, 3)) \
+ fw_def(TIGERLAKE,0, huc_def(tgl, 7, 9, 3)) \
+ fw_def(JASPERLAKE, 0, huc_def(ehl, 9, 0, 0)) \
+ fw_def(ELKHARTLAKE, 0, huc_def(ehl, 9, 0, 0)) \
+ fw_def(ICELAKE, 0, huc_def(icl, 9, 0, 0)) \
+ fw_def(COMETLAKE,5, huc_def(cml, 4, 0, 0)) \
+ fw_def(COMETLAKE,0, huc_def(kbl, 4, 0, 0)) \
+ fw_def(COFFEELAKE, 0, huc_def(kbl, 4, 0, 0)) \
+ fw_def(GEMINILAKE, 0, huc_def(glk, 4, 0, 0)) \
+ fw_def(KABYLAKE, 0, huc_def(kbl, 4, 0, 0)) \
+ fw_def(BROXTON, 0, huc_def(bxt, 2, 0, 0)) \
+ fw_def(SKYLAKE, 0, huc_def(skl, 2, 0, 0))
#define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \
"i915/" \
@@ -79,11 +96,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
__MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_)
/* All blobs need to be declared via MODULE_FIRMWARE() */
-#define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \
- MODULE_FIRMWARE(guc_); \
- MODULE_FIRMWARE(huc_);
+#define INTEL_UC_MODULE_FW(platform_, revid_, uc_) \
+ MODULE_FIRMWARE(uc_);
-INTEL_UC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH, MAKE_HUC_FW_PATH)
+INTEL_GUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH)
+INTEL_HUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_HUC_FW_PATH)
/* The below structs and macros are used to iterate across the list of blobs */
struct __packed uc_fw_blob {
@@ -106,31 +123,47 @@ struct __packed uc_fw_blob {
struct __packed uc_fw_platform_requirement {
enum intel_platform p
[Intel-gfx] [PATCH 5/5] drm/i915/guc: Improve GuC loading status check/error reports
From: John Harrison
If the GuC fails to load, it is useful to know what firmware file /
version was attempted. So move the version info report to before the
load attempt rather than only after a successful load.
If the GuC does fail to load, then make the error messages visible
rather than being 'debug' prints that do not appears in dmesg output
by default.
When waiting for the GuC to load, it used to be necessary to check for
two different states - READY and (LAPIC_DONE | MIA_CORE). Apparently
the second signified init complete on RC6 exit. However, in more
recent GuC versions the RC6 exit sequence now finishes with status
READY as well. So the test can be simplified.
Also, add an enum giving all the current status codes that GuC loading
can report as a reference without having to pull and search through
the GuC source files.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 23 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 17 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h| 4 ---
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 1 +
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 31 ++-
5 files changed, 48 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
index 488b6061ee89..c20658ee85a5 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
@@ -11,4 +11,27 @@ enum intel_guc_response_status {
INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
};
+enum intel_guc_load_status {
+ INTEL_GUC_LOAD_STATUS_DEFAULT = 0x00,
+ INTEL_GUC_LOAD_STATUS_START= 0x01,
+ INTEL_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH = 0x02,
+ INTEL_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH = 0x03,
+ INTEL_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE = 0x04,
+ INTEL_GUC_LOAD_STATUS_GDT_DONE = 0x10,
+ INTEL_GUC_LOAD_STATUS_IDT_DONE = 0x20,
+ INTEL_GUC_LOAD_STATUS_LAPIC_DONE = 0x30,
+ INTEL_GUC_LOAD_STATUS_GUCINT_DONE = 0x40,
+ INTEL_GUC_LOAD_STATUS_DPC_READY= 0x50,
+ INTEL_GUC_LOAD_STATUS_DPC_ERROR= 0x60,
+ INTEL_GUC_LOAD_STATUS_EXCEPTION= 0x70,
+ INTEL_GUC_LOAD_STATUS_INIT_DATA_INVALID= 0x71,
+ INTEL_GUC_LOAD_STATUS_PXP_TEARDOWN_CTRL_ENABLED= 0x72,
+ INTEL_GUC_LOAD_STATUS_INVALID_INIT_DATA_RANGE_START,
+ INTEL_GUC_LOAD_STATUS_MPU_DATA_INVALID = 0x73,
+ INTEL_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID = 0x74,
+ INTEL_GUC_LOAD_STATUS_INVALID_INIT_DATA_RANGE_END,
+
+ INTEL_GUC_LOAD_STATUS_READY= 0xF0,
+};
+
#endif /* _ABI_GUC_ERRORS_ABI_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 196424be0998..d3cee01d07e0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -70,11 +70,10 @@ static int guc_xfer_rsa(struct intel_uc_fw *guc_fw,
static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
{
u32 val = intel_uncore_read(uncore, GUC_STATUS);
- u32 uk_val = val & GS_UKERNEL_MASK;
+ u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val);
*status = val;
- return (uk_val == GS_UKERNEL_READY) ||
- ((val & GS_MIA_CORE_STATE) && (uk_val ==
GS_UKERNEL_LAPIC_DONE));
+ return uk_val == INTEL_GUC_LOAD_STATUS_READY;
}
static int guc_wait_ucode(struct intel_uncore *uncore)
@@ -94,8 +93,8 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
if (ret) {
struct drm_device *drm = &uncore->i915->drm;
- drm_dbg(drm, "GuC load failed: status = 0x%08X\n", status);
- drm_dbg(drm, "GuC load failed: status: Reset = %d, "
+ drm_info(drm, "GuC load failed: status = 0x%08X\n", status);
+ drm_info(drm, "GuC load failed: status: Reset = %d, "
"BootROM = 0x%02X, UKernel = 0x%02X, "
"MIA = 0x%02X, Auth = 0x%02X\n",
REG_FIELD_GET(GS_MIA_IN_RESET, status),
@@ -105,13 +104,13 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
- drm_dbg(drm, "GuC firmware signature verification
failed\n");
+ drm_info(drm, "GuC firmware signature verification
failed\n");
ret = -ENOEXEC;
}
- if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) {
-
[Intel-gfx] [PATCH 3/5] drm/i915/guc: Don't go bang in GuC log if no GuC
From: John Harrison
If the GuC has failed to load for any reason and then the user pokes
the debugfs GuC log interface, a BUG and/or null pointer deref can
occur. Don't let that happen.
Signed-off-by: John Harrison
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
index 46026c2c1722..8fd068049376 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
@@ -31,7 +31,7 @@ static int guc_log_level_get(void *data, u64 *val)
{
struct intel_guc_log *log = data;
- if (!intel_guc_is_used(log_to_guc(log)))
+ if (!log->vma)
return -ENODEV;
*val = intel_guc_log_get_level(log);
@@ -43,7 +43,7 @@ static int guc_log_level_set(void *data, u64 val)
{
struct intel_guc_log *log = data;
- if (!intel_guc_is_used(log_to_guc(log)))
+ if (!log->vma)
return -ENODEV;
return intel_guc_log_set_level(log, val);
--
2.25.1
[Intel-gfx] [PATCH 1/5] drm/i915/uc: Allow platforms to have GuC but not HuC
From: John Harrison
It is possible for platforms to require GuC but not HuC firmware.
Also, the firmware versions for GuC and HuC advance independently. So
split the macros up to allow the lists to be maintained separately.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 93
1 file changed, 63 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 3aa87be4f2e4..a7788ce50736 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -48,22 +48,39 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
* Note that RKL and ADL-S have the same GuC/HuC device ID's and use the same
* firmware as TGL.
*/
-#define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
- fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3), huc_def(tgl, 7, 9, 3)) \
- fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
- fw_def(DG1, 0, guc_def(dg1, 62, 0, 0), huc_def(dg1, 7, 9, 3)) \
- fw_def(ROCKETLAKE, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
- fw_def(TIGERLAKE, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
- fw_def(JASPERLAKE, 0, guc_def(ehl, 62, 0, 0), huc_def(ehl, 9, 0, 0)) \
- fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0), huc_def(ehl, 9, 0, 0)) \
- fw_def(ICELAKE, 0, guc_def(icl, 62, 0, 0), huc_def(icl, 9, 0, 0)) \
- fw_def(COMETLAKE, 5, guc_def(cml, 62, 0, 0), huc_def(cml, 4, 0, 0)) \
- fw_def(COMETLAKE, 0, guc_def(kbl, 62, 0, 0), huc_def(kbl, 4, 0, 0)) \
- fw_def(COFFEELAKE, 0, guc_def(kbl, 62, 0, 0), huc_def(kbl, 4, 0, 0)) \
- fw_def(GEMINILAKE, 0, guc_def(glk, 62, 0, 0), huc_def(glk, 4, 0, 0)) \
- fw_def(KABYLAKE,0, guc_def(kbl, 62, 0, 0), huc_def(kbl, 4, 0, 0)) \
- fw_def(BROXTON, 0, guc_def(bxt, 62, 0, 0), huc_def(bxt, 2, 0, 0)) \
- fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0), huc_def(skl, 2, 0, 0))
+#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \
+ fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3)) \
+ fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0)) \
+ fw_def(DG1, 0, guc_def(dg1, 62, 0, 0)) \
+ fw_def(ROCKETLAKE, 0, guc_def(tgl, 62, 0, 0)) \
+ fw_def(TIGERLAKE,0, guc_def(tgl, 62, 0, 0)) \
+ fw_def(JASPERLAKE, 0, guc_def(ehl, 62, 0, 0)) \
+ fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0)) \
+ fw_def(ICELAKE, 0, guc_def(icl, 62, 0, 0)) \
+ fw_def(COMETLAKE,5, guc_def(cml, 62, 0, 0)) \
+ fw_def(COMETLAKE,0, guc_def(kbl, 62, 0, 0)) \
+ fw_def(COFFEELAKE, 0, guc_def(kbl, 62, 0, 0)) \
+ fw_def(GEMINILAKE, 0, guc_def(glk, 62, 0, 0)) \
+ fw_def(KABYLAKE, 0, guc_def(kbl, 62, 0, 0)) \
+ fw_def(BROXTON, 0, guc_def(bxt, 62, 0, 0)) \
+ fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0))
+
+#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \
+ fw_def(ALDERLAKE_P, 0, huc_def(tgl, 7, 9, 3)) \
+ fw_def(ALDERLAKE_S, 0, huc_def(tgl, 7, 9, 3)) \
+ fw_def(DG1, 0, huc_def(dg1, 7, 9, 3)) \
+ fw_def(ROCKETLAKE, 0, huc_def(tgl, 7, 9, 3)) \
+ fw_def(TIGERLAKE,0, huc_def(tgl, 7, 9, 3)) \
+ fw_def(JASPERLAKE, 0, huc_def(ehl, 9, 0, 0)) \
+ fw_def(ELKHARTLAKE, 0, huc_def(ehl, 9, 0, 0)) \
+ fw_def(ICELAKE, 0, huc_def(icl, 9, 0, 0)) \
+ fw_def(COMETLAKE,5, huc_def(cml, 4, 0, 0)) \
+ fw_def(COMETLAKE,0, huc_def(kbl, 4, 0, 0)) \
+ fw_def(COFFEELAKE, 0, huc_def(kbl, 4, 0, 0)) \
+ fw_def(GEMINILAKE, 0, huc_def(glk, 4, 0, 0)) \
+ fw_def(KABYLAKE, 0, huc_def(kbl, 4, 0, 0)) \
+ fw_def(BROXTON, 0, huc_def(bxt, 2, 0, 0)) \
+ fw_def(SKYLAKE, 0, huc_def(skl, 2, 0, 0))
#define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \
"i915/" \
@@ -79,11 +96,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
__MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_)
/* All blobs need to be declared via MODULE_FIRMWARE() */
-#define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \
- MODULE_FIRMWARE(guc_); \
- MODULE_FIRMWARE(huc_);
+#define INTEL_UC_MODULE_FW(platform_, revid_, uc_) \
+ MODULE_FIRMWARE(uc_);
-INTEL_UC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH, MAKE_HUC_FW_PATH)
+INTEL_GUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH)
+INTEL_HUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_HUC_FW_PATH)
/* The below structs and macros are used to iterate across the list of blobs */
struct __packed uc_fw_blob {
@@ -106,31 +123,47 @@ struct __packed uc_fw_blob {
struct __packed uc_fw_platform_requirement {
enum intel_platform p;
u8 rev; /* first platform rev using this FW */
- const struct uc_fw_blob blobs[INTEL_UC_FW_NUM_TYPE
[Intel-gfx] [PATCH 4/5] drm/i915/guc: Update to GuC version 69.0.0
From: John Harrison Update to the latest GuC release. The latest GuC firmware introduces a number of interface changes: GuC may return NO_RESPONSE_RETRY message for requests sent over CTB. Add support for this reply and try resending the request again as a new CTB message. A KLV (key-length-value) mechanism is now used for passing configuration data such as CTB management. With the new KLV scheme, the old CTB management actions are no longer used and are removed. Register capture on hang is now supported by GuC. Full i915 support for this will be added by a later patch. A minimum support of providing capture memory and register lists is required though, so add that in. The device id of the current platform needs to be provided at init time. The 'poll CS' w/a (Wa_22012773006) was blanket enabled by previous versions of GuC. It must now be explicitly requested by the KMD. So, add in the code to turn it on when relevant. The GuC log entry format has changed. This requires adding a new field to the log header structure to mark the wrap point at the end of the buffer (as the buffer size is no longer a multiple of the log entry size). New CTB notification messages are now sent for some things that were previously only sent via MMIO notifications. Of these, the crash dump notification was not really being handled by i915. It called the log flush code but that only flushed the regular debug log and then only if relay logging was enabled. So just report an error message instead. The 'exception' notification was just being ignored completely. So add an error message for that as well. Note that in either the crash dump or the exception case, the GuC is basically dead. The KMD will detect this via the heartbeat and trigger both an error log (which will include the crash dump as part of the GuC log) and a GT reset. So no other processing is really required. Signed-off-by: John Harrison Signed-off-by: Michal Wajdeczko --- Documentation/gpu/i915.rst| 1 + .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 80 +- drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 82 ++ drivers/gpu/drm/i915/gt/uc/intel_guc.c| 126 +--- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 + drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 45 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 141 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 37 - drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 31 ++-- drivers/gpu/drm/i915/gt/uc/intel_guc_log.h| 3 + .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +++ drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 30 ++-- 12 files changed, 434 insertions(+), 164 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index b7d801993bfa..bcaefc952764 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -539,6 +539,7 @@ GuC ABI .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h HuC --- diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h index fe5d7d261797..7afdadc7656f 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h @@ -7,9 +7,9 @@ #define _ABI_GUC_ACTIONS_ABI_H /** - * DOC: HOST2GUC_REGISTER_CTB + * DOC: HOST2GUC_SELF_CFG * - * This message is used as part of the `CTB based communication`_ setup. + * This message is used by Host KMD to setup of the `GuC Self Config KLVs`_. * * This message must be sent as `MMIO HXG Message`_. * @@ -22,20 +22,18 @@ * | +---+--+ * | | 27:16 | DATA0 = MBZ | * | +---+--+ - * | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_REGISTER_CTB` = 0x4505 | + * | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_SELF_CFG` = 0x0508 | * +---+---+--+ - * | 1 | 31:12 | RESERVED = MBZ | + * | 1 | 31:16 | **KLV_KEY** - KLV key, see `GuC Self Config KLVs`_ | * | +---+--+ - * | | 11:8 | **TYPE** - type for the `CT Buffer`_ | + * | | 15:0 | **KLV_LEN** - KLV length | * | | | | - * | | | - _`GUC_CTB_TYPE_HOST2GUC` = 0 |
[Intel-gfx] [PATCH 2/5] drm/i915/guc: Increase GuC log size for CONFIG_DEBUG_GEM
From: John Harrison Lots of testing is done with the DEBUG_GEM config option enabled but not the DEBUG_GUC option. That means we only get teeny-tiny GuC logs which are not hugely useful. Enabling full DEBUG_GUC also spews lots of other detailed output that is not generally desired. However, bigger GuC logs are extremely useful for almost any regression debug. So enable bigger logs for DEBUG_GEM builds as well. Signed-off-by: John Harrison --- drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h index ac1ee1d5ce10..fe6ab7550a14 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h @@ -15,9 +15,12 @@ struct intel_guc; -#ifdef CONFIG_DRM_I915_DEBUG_GUC +#if defined(CONFIG_DRM_I915_DEBUG_GUC) #define CRASH_BUFFER_SIZE SZ_2M #define DEBUG_BUFFER_SIZE SZ_16M +#elif defined(CONFIG_DRM_I915_DEBUG_GEM) +#define CRASH_BUFFER_SIZE SZ_1M +#define DEBUG_BUFFER_SIZE SZ_2M #else #define CRASH_BUFFER_SIZE SZ_8K #define DEBUG_BUFFER_SIZE SZ_64K -- 2.25.1
[Intel-gfx] [PATCH 0/5] Update to GuC version 69.0.0
From: John Harrison Update to the latest GuC version. This includes a suite of interface changes and new features with corresponding i915 side changes. Also, fix/improve a bunch of other things while at it. Signed-off-by: John Harrison John Harrison (5): drm/i915/uc: Allow platforms to have GuC but not HuC drm/i915/guc: Increase GuC log size for CONFIG_DEBUG_GEM drm/i915/guc: Don't go bang in GuC log if no GuC drm/i915/guc: Update to GuC version 69.0.0 drm/i915/guc: Improve GuC loading status check/error reports Documentation/gpu/i915.rst| 1 + .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 80 +- .../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 23 +++ drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 82 ++ drivers/gpu/drm/i915/gt/uc/intel_guc.c| 126 +--- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 + drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 45 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 141 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 17 +-- drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 37 - drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 31 ++-- drivers/gpu/drm/i915/gt/uc/intel_guc_log.h| 8 +- .../drm/i915/gt/uc/intel_guc_log_debugfs.c| 4 +- drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h| 4 - .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +++ drivers/gpu/drm/i915/gt/uc/intel_huc.c| 1 + drivers/gpu/drm/i915/gt/uc/intel_uc.c | 31 ++-- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 93 18 files changed, 536 insertions(+), 210 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h -- 2.25.1
[Intel-gfx] [PATCH] drm/i915: Rollback seqno when request creation fails
gem_ctx_create.basic-files can slam on kernel contexts to the extent
where request creation fails because the ring is full. When this happens
seqno numbers are skipped which can result the below GEM_BUG_ON blowing
in gt/intel_engine_pm.c:__engine_unpark:
GEM_BUG_ON(ce->timeline->seqno !=
READ_ONCE(*ce->timeline->hwsp_seqno));
Fixup request creation code to roll back seqno when request creation
fails.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_timeline.c | 5 +
drivers/gpu/drm/i915/gt/intel_timeline.h | 1 +
drivers/gpu/drm/i915/i915_request.c | 1 +
3 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 438bbc7b8147..64ea9a90c7a0 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -301,6 +301,11 @@ static u32 timeline_advance(struct intel_timeline *tl)
return tl->seqno += 1 + tl->has_initial_breadcrumb;
}
+void intel_timeline_rollback_seqno(struct intel_timeline *tl)
+{
+ timeline_rollback(tl);
+}
+
static noinline int
__intel_timeline_get_seqno(struct intel_timeline *tl,
u32 *seqno)
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h
b/drivers/gpu/drm/i915/gt/intel_timeline.h
index 57308c4d664a..a2f2e0ea186f 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
@@ -72,6 +72,7 @@ void intel_timeline_enter(struct intel_timeline *tl);
int intel_timeline_get_seqno(struct intel_timeline *tl,
struct i915_request *rq,
u32 *seqno);
+void intel_timeline_rollback_seqno(struct intel_timeline *tl);
void intel_timeline_exit(struct intel_timeline *tl);
void intel_timeline_unpin(struct intel_timeline *tl);
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index a72c8f0346a0..86f32ee082f7 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -966,6 +966,7 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp)
err_unwind:
ce->ring->emit = rq->head;
+ intel_timeline_rollback_seqno(tl);
/* Make sure we didn't add ourselves to external state before freeing */
GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
--
2.33.1
[Intel-gfx] [PATCH v5 1/1] drm/i915: Introduce new macros for i915 PTE
Certain functions within i915 uses macros that are defined for
specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT
(Some architectures don't even have these macros defined, like ARM64).
Instead of re-using bits defined for the CPU, we should use bits
defined for i915. This patch introduces two new 64 bit macros,
I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to
replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++
drivers/gpu/drm/i915/gvt/gtt.c | 12 ++--
4 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 9966e9dc5218..f89b50ffc286 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -18,7 +18,7 @@
static u64 gen8_pde_encode(const dma_addr_t addr,
const enum i915_cache_level level)
{
- u64 pde = addr | _PAGE_PRESENT | _PAGE_RW;
+ u64 pde = addr | I915_PAGE_PRESENT | I915_PAGE_RW;
if (level != I915_CACHE_NONE)
pde |= PPAT_CACHED_PDE;
@@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags)
{
- gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
+ gen8_pte_t pte = addr | I915_PAGE_PRESENT | I915_PAGE_RW;
if (unlikely(flags & PTE_READ_ONLY))
- pte &= ~_PAGE_RW;
+ pte &= ~I915_PAGE_RW;
if (flags & PTE_LM)
pte |= GEN12_PPGTT_PTE_LM;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 110d3944f9a2..43cbfdb60412 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -209,7 +209,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags)
{
- gen8_pte_t pte = addr | _PAGE_PRESENT;
+ gen8_pte_t pte = addr | I915_PAGE_PRESENT;
if (flags & PTE_LM)
pte |= GEN12_GGTT_PTE_LM;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index dfeaef680aac..fba9c0c18f4a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -39,6 +39,9 @@
#define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */
+#define I915_PAGE_PRESENT BIT_ULL(0)
+#define I915_PAGE_RW BIT_ULL(1)
+
#define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
#define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
#define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 53d0cb327539..8f6a055854f7 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -446,17 +446,17 @@ static bool gen8_gtt_test_present(struct
intel_gvt_gtt_entry *e)
|| e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
return (e->val64 != 0);
else
- return (e->val64 & _PAGE_PRESENT);
+ return (e->val64 & I915_PAGE_PRESENT);
}
static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
{
- e->val64 &= ~_PAGE_PRESENT;
+ e->val64 &= ~I915_PAGE_PRESENT;
}
static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
{
- e->val64 |= _PAGE_PRESENT;
+ e->val64 |= I915_PAGE_PRESENT;
}
static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
@@ -2439,7 +2439,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
/* The entry parameters like present/writeable/cache type
* set to the same as i915's scratch page tree.
*/
- se.val64 |= _PAGE_PRESENT | _PAGE_RW;
+ se.val64 |= I915_PAGE_PRESENT | I915_PAGE_RW;
if (type == GTT_TYPE_PPGTT_PDE_PT)
se.val64 |= PPAT_CACHED;
@@ -2896,7 +2896,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt)
offset = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
for (idx = 0; idx < num_low; idx++) {
pte = mm->ggtt_mm.host_ggtt_aperture[idx];
- if (pte & _PAGE_PRESENT)
+ if (pte & I915_PAGE_PRESENT)
write_pte64(vgpu->gvt->gt->ggtt, offset + idx,
pte);
}
@@ -2904,7 +2904,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt)
offset = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
for (idx = 0; idx < num_hi; idx++) {
pte = mm->ggtt_mm.host_ggtt_hidden[idx];
- if (pte & _PAGE_PRESENT)
+ if (pte & I915_PAGE_PRES
[Intel-gfx] [PATCH v5 0/1] Introduce new i915 macros for checking PTEs
This series is to introduce new macros generic to i915 for checking 0 and 1 bits, instead on relying on whats defined by the mmu, since it could be different or non-exisitent between different platforms. v2: Corrected sender's email. v3: Corrected spelling error. v4: Clean up a few other macros that are checking 0 and 1 bits. Thanks to Lucas De Marchi for suggesting these cleanups. v5: Remove changes to GEN6_PTE_VALID/GEN6_PDE_VALID and BYT_PTE_WRITEABLE. Those macros checks for 32bit PTEs, and our new macro is checking for 64bit. Michael Cheng (1): drm/i915: Introduce new macros for i915 PTE drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++--- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++ drivers/gpu/drm/i915/gvt/gtt.c | 12 ++-- 4 files changed, 13 insertions(+), 10 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH v5 1/1] drm/i915: Introduce new macros for i915 PTE
Certain functions within i915 uses macros that are defined for
specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT
(Some architectures don't even have these macros defined, like ARM64).
Instead of re-using bits defined for the CPU, we should use bits
defined for i915. This patch introduces two new 64 bit macros,
I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to
replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++
drivers/gpu/drm/i915/gvt/gtt.c | 12 ++--
4 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 9966e9dc5218..f89b50ffc286 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -18,7 +18,7 @@
static u64 gen8_pde_encode(const dma_addr_t addr,
const enum i915_cache_level level)
{
- u64 pde = addr | _PAGE_PRESENT | _PAGE_RW;
+ u64 pde = addr | I915_PAGE_PRESENT | I915_PAGE_RW;
if (level != I915_CACHE_NONE)
pde |= PPAT_CACHED_PDE;
@@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags)
{
- gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
+ gen8_pte_t pte = addr | I915_PAGE_PRESENT | I915_PAGE_RW;
if (unlikely(flags & PTE_READ_ONLY))
- pte &= ~_PAGE_RW;
+ pte &= ~I915_PAGE_RW;
if (flags & PTE_LM)
pte |= GEN12_PPGTT_PTE_LM;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 110d3944f9a2..43cbfdb60412 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -209,7 +209,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags)
{
- gen8_pte_t pte = addr | _PAGE_PRESENT;
+ gen8_pte_t pte = addr | I915_PAGE_PRESENT;
if (flags & PTE_LM)
pte |= GEN12_GGTT_PTE_LM;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index dfeaef680aac..fba9c0c18f4a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -39,6 +39,9 @@
#define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */
+#define I915_PAGE_PRESENT BIT_ULL(0)
+#define I915_PAGE_RW BIT_ULL(1)
+
#define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
#define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
#define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 53d0cb327539..8f6a055854f7 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -446,17 +446,17 @@ static bool gen8_gtt_test_present(struct
intel_gvt_gtt_entry *e)
|| e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
return (e->val64 != 0);
else
- return (e->val64 & _PAGE_PRESENT);
+ return (e->val64 & I915_PAGE_PRESENT);
}
static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
{
- e->val64 &= ~_PAGE_PRESENT;
+ e->val64 &= ~I915_PAGE_PRESENT;
}
static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
{
- e->val64 |= _PAGE_PRESENT;
+ e->val64 |= I915_PAGE_PRESENT;
}
static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
@@ -2439,7 +2439,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
/* The entry parameters like present/writeable/cache type
* set to the same as i915's scratch page tree.
*/
- se.val64 |= _PAGE_PRESENT | _PAGE_RW;
+ se.val64 |= I915_PAGE_PRESENT | I915_PAGE_RW;
if (type == GTT_TYPE_PPGTT_PDE_PT)
se.val64 |= PPAT_CACHED;
@@ -2896,7 +2896,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt)
offset = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
for (idx = 0; idx < num_low; idx++) {
pte = mm->ggtt_mm.host_ggtt_aperture[idx];
- if (pte & _PAGE_PRESENT)
+ if (pte & I915_PAGE_PRESENT)
write_pte64(vgpu->gvt->gt->ggtt, offset + idx,
pte);
}
@@ -2904,7 +2904,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt)
offset = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
for (idx = 0; idx < num_hi; idx++) {
pte = mm->ggtt_mm.host_ggtt_hidden[idx];
- if (pte & _PAGE_PRESENT)
+ if (pte & I915_PAGE_PRES
Re: [Intel-gfx] [PATCH v2 2/8] drm/i915/gtt: add xehpsdv_ppgtt_insert_entry
On 2021-12-03 at 17:31:11 +, Matthew Auld wrote:
> On 03/12/2021 16:59, Ramalingam C wrote:
> > On 2021-12-03 at 12:24:20 +, Matthew Auld wrote:
> > > If this is LMEM then we get a 32 entry PT, with each PTE pointing to
> > > some 64K block of memory, otherwise it's just the usual 512 entry PT.
> > > This very much assumes the caller knows what they are doing.
> > >
> > > Signed-off-by: Matthew Auld
> > > Cc: Thomas Hellström
> > > Cc: Ramalingam C
> > > ---
> > > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 50 ++--
> > > 1 file changed, 48 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > > b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > > index bd3ca0996a23..312b2267bf87 100644
> > > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > > @@ -728,13 +728,56 @@ static void gen8_ppgtt_insert_entry(struct
> > > i915_address_space *vm,
> > > gen8_pdp_for_page_index(vm, idx);
> > > struct i915_page_directory *pd =
> > > i915_pd_entry(pdp, gen8_pd_index(idx, 2));
> > > + struct i915_page_table *pt = i915_pt_entry(pd, gen8_pd_index(idx, 1));
> > > gen8_pte_t *vaddr;
> > > - vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
> > > + GEM_BUG_ON(pt->is_compact);
> >
> > Do we have compact PT for smem with 64k pages?
>
> It's technically possible but we don't bother trying to support it in the
> driver.
Ok.
Reviewed-by: Ramalingam C
>
> >
> > > +
> > > + vaddr = px_vaddr(pt);
> > > vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level,
> > > flags);
> > > clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)],
> > > sizeof(*vaddr));
> > > }
> > > +static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space
> > > *vm,
> > > + dma_addr_t addr,
> > > + u64 offset,
> > > + enum i915_cache_level level,
> > > + u32 flags)
> > > +{
> > > + u64 idx = offset >> GEN8_PTE_SHIFT;
> > > + struct i915_page_directory * const pdp =
> > > + gen8_pdp_for_page_index(vm, idx);
> > > + struct i915_page_directory *pd =
> > > + i915_pd_entry(pdp, gen8_pd_index(idx, 2));
> > > + struct i915_page_table *pt = i915_pt_entry(pd, gen8_pd_index(idx, 1));
> > > + gen8_pte_t *vaddr;
> > > +
> > > + GEM_BUG_ON(!IS_ALIGNED(addr, SZ_64K));
> > > + GEM_BUG_ON(!IS_ALIGNED(offset, SZ_64K));
> > > +
> > > + if (!pt->is_compact) {
> > > + vaddr = px_vaddr(pd);
> > > + vaddr[gen8_pd_index(idx, 1)] |= GEN12_PDE_64K;
> > > + pt->is_compact = true;
> > > + }
> > > +
> > > + vaddr = px_vaddr(pt);
> > > + vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level, flags);
> > > +}
> > > +
> > > +static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
> > > +dma_addr_t addr,
> > > +u64 offset,
> > > +enum i915_cache_level level,
> > > +u32 flags)
> > > +{
> > > + if (flags & PTE_LM)
> > > + return __xehpsdv_ppgtt_insert_entry_lm(vm, addr, offset,
> > > +level, flags);
> > > +
> > > + return gen8_ppgtt_insert_entry(vm, addr, offset, level, flags);
> > Matt,
> >
> > Is this call for gen8_*** is for insertion of smem PTE entries on the
> > 64K capable platforms like DG2?
>
> Yeah, this just falls back to the generic 512 entry layout for the PT.
>
> >
> > Ram
> >
> > > +}
> > > +
> > > static int gen8_init_scratch(struct i915_address_space *vm)
> > > {
> > > u32 pte_flags;
> > > @@ -937,7 +980,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt
> > > *gt,
> > > ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
> > > ppgtt->vm.insert_entries = gen8_ppgtt_insert;
> > > - ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
> > > + if (HAS_64K_PAGES(gt->i915))
> > > + ppgtt->vm.insert_page = xehpsdv_ppgtt_insert_entry;
> > > + else
> > > + ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
> > > ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
> > > ppgtt->vm.clear_range = gen8_ppgtt_clear;
> > > ppgtt->vm.foreach = gen8_ppgtt_foreach;
> > > --
> > > 2.31.1
> > >
[Intel-gfx] [PATCH v5 0/1]
This series is to introduce new macros generic to i915 for checking 0 and 1 bits, instead on relying on whats defined by the mmu, since it could be different or non-exisitent between different platforms. v2: Corrected sender's email. v3: Corrected spelling error. v4: Clean up a few other macros that are checking 0 and 1 bits. Thanks to Lucas De Marchi for suggesting these cleanups. v5: Remove changes to GEN6_PTE_VALID/GEN6_PDE_VALID and BYT_PTE_WRITEABLE. Those macros checks for 32bit PTEs, and our new macro is checking for 64bit. Michael Cheng (1): drm/i915: Introduce new macros for i915 PTE drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++--- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++ drivers/gpu/drm/i915/gvt/gtt.c | 12 ++-- 4 files changed, 13 insertions(+), 10 deletions(-) -- 2.25.1
Re: [Intel-gfx] [PATCH v2 4/8] drm/i915/migrate: fix offset calculation
On 03/12/2021 17:30, Ramalingam C wrote: On 2021-12-03 at 12:24:22 +, Matthew Auld wrote: Ensure we add the engine base only after we calculate the qword offset into the PTE window. So we didn't hit this issue because we were always using the engine->instance 0!? Yes, AFAIK. Looks good to me Reviewed-by: Ramalingam C Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Ramalingam C --- drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c index d553b76b1168..cb0bb3b94644 100644 --- a/drivers/gpu/drm/i915/gt/intel_migrate.c +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c @@ -284,10 +284,10 @@ static int emit_pte(struct i915_request *rq, GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8); /* Compute the page directory offset for the target address range */ - offset += (u64)rq->engine->instance << 32; offset >>= 12; offset *= sizeof(u64); offset += 2 * CHUNK_SZ; + offset += (u64)rq->engine->instance << 32; cs = intel_ring_begin(rq, 6); if (IS_ERR(cs)) -- 2.31.1
Re: [Intel-gfx] [PATCH v2 3/8] drm/i915/gtt: add gtt mappable plumbing
On 03/12/2021 17:25, Ramalingam C wrote:
On 2021-12-03 at 12:24:21 +, Matthew Auld wrote:
With object clearing/copying we need to be able to modify the PTEs on
the fly via some batch buffer, which means we need to be able to map the
paging structures(or at the very least the PT, but being able to also
map the PD might also be useful at some point) into the GTT. And since
the paging structures must reside in LMEM on discrete, we need to ensure
that these objects have correct physical alignment, as per any min page
restrictions, like on DG2. This is potentially costly, but this should
be limited to the special migrate_vm, which only needs to a few fixed
sized windows.
Matt,
Just a thought. instead of classifying whole ppgtt as VM_GTT_MAPPABLE
and rounding up the pt size to min_page_size,
could we just add size of pt as parameter into i915_vm_alloc_pt_stash
and alloc_pt, which can be used for vm->alloc_pt_dma() instead of
I915_GTT_PAGE_SIZE_4K.
But PT for a smem entries also needs to be 64k aligned to be mapped into
the GTT right? So no advantage of having the pt_stash level physical
alignment..
Any thoughts on this line?
Yes, this sounds like a good idea. Initially I was worried about stuff
like gen8_alloc_top_pd() which would skip this, but it looks like we
only really care about the PT and maybe also the PD having correct
alignment. Will change.
Ram
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++--
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
drivers/gpu/drm/i915/gt/gen6_ppgtt.c| 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c| 3 ++-
drivers/gpu/drm/i915/gt/gen8_ppgtt.h| 1 +
drivers/gpu/drm/i915/gt/intel_ggtt.c| 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 7 +++
drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +
drivers/gpu/drm/i915/gt/intel_migrate.c | 4 +++-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 17 -
drivers/gpu/drm/i915/gt/selftest_hangcheck.c| 2 +-
drivers/gpu/drm/i915/gvt/scheduler.c| 2 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 ++--
14 files changed, 44 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ebd775cb1661..b394954726b0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1559,7 +1559,7 @@ i915_gem_create_context(struct drm_i915_private *i915,
} else if (HAS_FULL_PPGTT(i915)) {
struct i915_ppgtt *ppgtt;
- ppgtt = i915_ppgtt_create(&i915->gt, 0);
+ ppgtt = i915_ppgtt_create(&i915->gt, 0, 0);
if (IS_ERR(ppgtt)) {
drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
PTR_ERR(ppgtt));
@@ -1742,7 +1742,7 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void
*data,
if (args->flags)
return -EINVAL;
- ppgtt = i915_ppgtt_create(&i915->gt, 0);
+ ppgtt = i915_ppgtt_create(&i915->gt, 0, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index bd8dc1a28022..c1b86c7a4754 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1764,7 +1764,7 @@ int i915_gem_huge_page_mock_selftests(void)
mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
mkwrite_device_info(dev_priv)->ppgtt_size = 48;
- ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
+ ppgtt = i915_ppgtt_create(&dev_priv->gt, 0, 0);
if (IS_ERR(ppgtt)) {
err = PTR_ERR(ppgtt);
goto out_unlock;
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index c0d149f04949..778472e563aa 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -443,7 +443,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
mutex_init(&ppgtt->flush);
- ppgtt_init(&ppgtt->base, gt, 0);
+ ppgtt_init(&ppgtt->base, gt, 0, 0);
ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen6_pte_t));
ppgtt->base.vm.top = 1;
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 312b2267bf87..dfca803b4ff1 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -912,6 +912,7 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
*
*/
struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
+unsigned long vm_flags,
unsigned
Re: [Intel-gfx] [PATCH v2 6/8] drm/i915/selftests: handle object rounding
On 2021-12-03 at 12:24:24 +, Matthew Auld wrote: > Ensure we account for any object rounding due to min_page_size > restrictions. > > Signed-off-by: Matthew Auld Reviewed-by: Ramalingam C > Cc: Thomas Hellström > Cc: Ramalingam C > --- > drivers/gpu/drm/i915/gt/selftest_migrate.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c > b/drivers/gpu/drm/i915/gt/selftest_migrate.c > index 12ef2837c89b..e21787301bbd 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_migrate.c > +++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c > @@ -49,6 +49,7 @@ static int copy(struct intel_migrate *migrate, > if (IS_ERR(src)) > return 0; > > + sz = src->base.size; > dst = i915_gem_object_create_internal(i915, sz); > if (IS_ERR(dst)) > goto err_free_src; > -- > 2.31.1 >
Re: [Intel-gfx] [PATCH v2 5/8] drm/i915/migrate: fix length calculation
On 2021-12-03 at 12:24:23 +, Matthew Auld wrote: > No need to insert PTEs for the PTE window itself, also foreach expects a > length not an end offset, which could be gigantic here with a second > engine. > Looks good to me Reviewed-by: Ramalingam C > Signed-off-by: Matthew Auld > Cc: Thomas Hellström > Cc: Ramalingam C > --- > drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c > b/drivers/gpu/drm/i915/gt/intel_migrate.c > index cb0bb3b94644..2076e24e0489 100644 > --- a/drivers/gpu/drm/i915/gt/intel_migrate.c > +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c > @@ -136,7 +136,7 @@ static struct i915_address_space *migrate_vm(struct > intel_gt *gt) > goto err_vm; > > /* Now allow the GPU to rewrite the PTE via its own ppGTT */ > - vm->vm.foreach(&vm->vm, base, base + sz, insert_pte, &d); > + vm->vm.foreach(&vm->vm, base, d.offset - base, insert_pte, &d); > } > > return &vm->vm; > -- > 2.31.1 >
Re: [Intel-gfx] [PATCH v2 2/8] drm/i915/gtt: add xehpsdv_ppgtt_insert_entry
On 03/12/2021 16:59, Ramalingam C wrote:
On 2021-12-03 at 12:24:20 +, Matthew Auld wrote:
If this is LMEM then we get a 32 entry PT, with each PTE pointing to
some 64K block of memory, otherwise it's just the usual 512 entry PT.
This very much assumes the caller knows what they are doing.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 50 ++--
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index bd3ca0996a23..312b2267bf87 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -728,13 +728,56 @@ static void gen8_ppgtt_insert_entry(struct
i915_address_space *vm,
gen8_pdp_for_page_index(vm, idx);
struct i915_page_directory *pd =
i915_pd_entry(pdp, gen8_pd_index(idx, 2));
+ struct i915_page_table *pt = i915_pt_entry(pd, gen8_pd_index(idx, 1));
gen8_pte_t *vaddr;
- vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
+ GEM_BUG_ON(pt->is_compact);
Do we have compact PT for smem with 64k pages?
It's technically possible but we don't bother trying to support it in
the driver.
+
+ vaddr = px_vaddr(pt);
vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
}
+static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ u64 idx = offset >> GEN8_PTE_SHIFT;
+ struct i915_page_directory * const pdp =
+ gen8_pdp_for_page_index(vm, idx);
+ struct i915_page_directory *pd =
+ i915_pd_entry(pdp, gen8_pd_index(idx, 2));
+ struct i915_page_table *pt = i915_pt_entry(pd, gen8_pd_index(idx, 1));
+ gen8_pte_t *vaddr;
+
+ GEM_BUG_ON(!IS_ALIGNED(addr, SZ_64K));
+ GEM_BUG_ON(!IS_ALIGNED(offset, SZ_64K));
+
+ if (!pt->is_compact) {
+ vaddr = px_vaddr(pd);
+ vaddr[gen8_pd_index(idx, 1)] |= GEN12_PDE_64K;
+ pt->is_compact = true;
+ }
+
+ vaddr = px_vaddr(pt);
+ vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level, flags);
+}
+
+static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ if (flags & PTE_LM)
+ return __xehpsdv_ppgtt_insert_entry_lm(vm, addr, offset,
+ level, flags);
+
+ return gen8_ppgtt_insert_entry(vm, addr, offset, level, flags);
Matt,
Is this call for gen8_*** is for insertion of smem PTE entries on the
64K capable platforms like DG2?
Yeah, this just falls back to the generic 512 entry layout for the PT.
Ram
+}
+
static int gen8_init_scratch(struct i915_address_space *vm)
{
u32 pte_flags;
@@ -937,7 +980,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
ppgtt->vm.insert_entries = gen8_ppgtt_insert;
- ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
+ if (HAS_64K_PAGES(gt->i915))
+ ppgtt->vm.insert_page = xehpsdv_ppgtt_insert_entry;
+ else
+ ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
ppgtt->vm.clear_range = gen8_ppgtt_clear;
ppgtt->vm.foreach = gen8_ppgtt_foreach;
--
2.31.1
Re: [Intel-gfx] [PATCH v2 4/8] drm/i915/migrate: fix offset calculation
On 2021-12-03 at 12:24:22 +, Matthew Auld wrote: > Ensure we add the engine base only after we calculate the qword offset > into the PTE window. So we didn't hit this issue because we were always using the engine->instance 0!? Looks good to me Reviewed-by: Ramalingam C > > Signed-off-by: Matthew Auld > Cc: Thomas Hellström > Cc: Ramalingam C > --- > drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c > b/drivers/gpu/drm/i915/gt/intel_migrate.c > index d553b76b1168..cb0bb3b94644 100644 > --- a/drivers/gpu/drm/i915/gt/intel_migrate.c > +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c > @@ -284,10 +284,10 @@ static int emit_pte(struct i915_request *rq, > GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8); > > /* Compute the page directory offset for the target address range */ > - offset += (u64)rq->engine->instance << 32; > offset >>= 12; > offset *= sizeof(u64); > offset += 2 * CHUNK_SZ; > + offset += (u64)rq->engine->instance << 32; > > cs = intel_ring_begin(rq, 6); > if (IS_ERR(cs)) > -- > 2.31.1 >
[Intel-gfx] ✓ Fi.CI.BAT: success for Per client GPU stats (rev5)
== Series Details == Series: Per client GPU stats (rev5) URL : https://patchwork.freedesktop.org/series/92574/ State : success == Summary == CI Bug Log - changes from CI_DRM_10961 -> Patchwork_21748 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/index.html Participating hosts (42 -> 33) -- Missing(9): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21748 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [PASS][3] -> [INCOMPLETE][4] ([i915#198]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html Possible fixes * igt@i915_selftest@live@gt_engines: - fi-rkl-guc: [INCOMPLETE][5] ([i915#4432]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick:[DMESG-FAIL][7] ([i915#2927] / [i915#3428]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432 Build changes - * Linux: CI_DRM_10961 -> Patchwork_21748 CI-20190529: 20190529 CI_DRM_10961: e7bbdc541b4748718cd6ce8b839f3db335f3a0fc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6299: 0933b7ccdb2bb054b6a8154171e35315d84299b7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21748: ad834d8654cb1b0f9acade04909f17430cf3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ad834d8654cb drm/i915: Expose client engine utilisation via fdinfo 652aa6036d85 drm: Document fdinfo format specification 3cf647c7e74e drm/i915: Track context current active time e5ae4129e699 drm/i915: Track all user contexts per client 3ccc766dae95 drm/i915: Track runtime spent in closed and unreachable GEM contexts 9e794520713e drm/i915: Make GEM contexts track DRM clients 5b365ef06833 drm/i915: Explicitly track DRM clients == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21748/index.html
Re: [Intel-gfx] [PATCH v2 3/8] drm/i915/gtt: add gtt mappable plumbing
On 2021-12-03 at 12:24:21 +, Matthew Auld wrote:
> With object clearing/copying we need to be able to modify the PTEs on
> the fly via some batch buffer, which means we need to be able to map the
> paging structures(or at the very least the PT, but being able to also
> map the PD might also be useful at some point) into the GTT. And since
> the paging structures must reside in LMEM on discrete, we need to ensure
> that these objects have correct physical alignment, as per any min page
> restrictions, like on DG2. This is potentially costly, but this should
> be limited to the special migrate_vm, which only needs to a few fixed
> sized windows.
Matt,
Just a thought. instead of classifying whole ppgtt as VM_GTT_MAPPABLE
and rounding up the pt size to min_page_size,
could we just add size of pt as parameter into i915_vm_alloc_pt_stash
and alloc_pt, which can be used for vm->alloc_pt_dma() instead of
I915_GTT_PAGE_SIZE_4K.
But PT for a smem entries also needs to be 64k aligned to be mapped into
the GTT right? So no advantage of having the pt_stash level physical
alignment..
Any thoughts on this line?
Ram
>
> Signed-off-by: Matthew Auld
> Cc: Thomas Hellström
> Cc: Ramalingam C
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++--
> drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
> drivers/gpu/drm/i915/gt/gen6_ppgtt.c| 2 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c| 3 ++-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.h| 1 +
> drivers/gpu/drm/i915/gt/intel_ggtt.c| 2 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gtt.c | 7 +++
> drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +
> drivers/gpu/drm/i915/gt/intel_migrate.c | 4 +++-
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 17 -
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c| 2 +-
> drivers/gpu/drm/i915/gvt/scheduler.c| 2 +-
> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 ++--
> 14 files changed, 44 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index ebd775cb1661..b394954726b0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1559,7 +1559,7 @@ i915_gem_create_context(struct drm_i915_private *i915,
> } else if (HAS_FULL_PPGTT(i915)) {
> struct i915_ppgtt *ppgtt;
>
> - ppgtt = i915_ppgtt_create(&i915->gt, 0);
> + ppgtt = i915_ppgtt_create(&i915->gt, 0, 0);
> if (IS_ERR(ppgtt)) {
> drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
> PTR_ERR(ppgtt));
> @@ -1742,7 +1742,7 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev,
> void *data,
> if (args->flags)
> return -EINVAL;
>
> - ppgtt = i915_ppgtt_create(&i915->gt, 0);
> + ppgtt = i915_ppgtt_create(&i915->gt, 0, 0);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> index bd8dc1a28022..c1b86c7a4754 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> @@ -1764,7 +1764,7 @@ int i915_gem_huge_page_mock_selftests(void)
> mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
> mkwrite_device_info(dev_priv)->ppgtt_size = 48;
>
> - ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
> + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0, 0);
> if (IS_ERR(ppgtt)) {
> err = PTR_ERR(ppgtt);
> goto out_unlock;
> diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> index c0d149f04949..778472e563aa 100644
> --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> @@ -443,7 +443,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
>
> mutex_init(&ppgtt->flush);
>
> - ppgtt_init(&ppgtt->base, gt, 0);
> + ppgtt_init(&ppgtt->base, gt, 0, 0);
> ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen6_pte_t));
> ppgtt->base.vm.top = 1;
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index 312b2267bf87..dfca803b4ff1 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -912,6 +912,7 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
> *
> */
> struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> + unsigned long vm_flags,
>unsigned long lmem_pt_obj_flags)
> {
> struct i915_ppgtt *ppgtt;
> @@ -921,7 +922,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
>
[Intel-gfx] ✗ Fi.CI.DOCS: warning for Per client GPU stats (rev5)
== Series Details == Series: Per client GPU stats (rev5) URL : https://patchwork.freedesktop.org/series/92574/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_context_types.h:417: warning: Function parameter or member 'client_link' not described in 'i915_gem_context'
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Per client GPU stats (rev5)
== Series Details == Series: Per client GPU stats (rev5) URL : https://patchwork.freedesktop.org/series/92574/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Per client GPU stats (rev5)
== Series Details == Series: Per client GPU stats (rev5) URL : https://patchwork.freedesktop.org/series/92574/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5b365ef06833 drm/i915: Explicitly track DRM clients -:129: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #129: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 227 lines checked 9e794520713e drm/i915: Make GEM contexts track DRM clients 3ccc766dae95 drm/i915: Track runtime spent in closed and unreachable GEM contexts e5ae4129e699 drm/i915: Track all user contexts per client 3cf647c7e74e drm/i915: Track context current active time -:139: WARNING:LINE_SPACING: Missing a blank line after declarations #139: FILE: drivers/gpu/drm/i915/gt/intel_context_types.h:148: + u32 last; + I915_SELFTEST_DECLARE(u32 num_underflow); total: 0 errors, 1 warnings, 0 checks, 296 lines checked 652aa6036d85 drm: Document fdinfo format specification -:40: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #40: new file mode 100644 -:45: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #45: FILE: Documentation/gpu/drm-usage-stats.rst:1: +.. _drm-client-usage-stats: total: 0 errors, 2 warnings, 0 checks, 104 lines checked ad834d8654cb drm/i915: Expose client engine utilisation via fdinfo
Re: [Intel-gfx] [PATCH v2 2/8] drm/i915/gtt: add xehpsdv_ppgtt_insert_entry
On 2021-12-03 at 12:24:20 +, Matthew Auld wrote:
> If this is LMEM then we get a 32 entry PT, with each PTE pointing to
> some 64K block of memory, otherwise it's just the usual 512 entry PT.
> This very much assumes the caller knows what they are doing.
>
> Signed-off-by: Matthew Auld
> Cc: Thomas Hellström
> Cc: Ramalingam C
> ---
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 50 ++--
> 1 file changed, 48 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index bd3ca0996a23..312b2267bf87 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -728,13 +728,56 @@ static void gen8_ppgtt_insert_entry(struct
> i915_address_space *vm,
> gen8_pdp_for_page_index(vm, idx);
> struct i915_page_directory *pd =
> i915_pd_entry(pdp, gen8_pd_index(idx, 2));
> + struct i915_page_table *pt = i915_pt_entry(pd, gen8_pd_index(idx, 1));
> gen8_pte_t *vaddr;
>
> - vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
> + GEM_BUG_ON(pt->is_compact);
Do we have compact PT for smem with 64k pages?
> +
> + vaddr = px_vaddr(pt);
> vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
> clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
> }
>
> +static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
> + dma_addr_t addr,
> + u64 offset,
> + enum i915_cache_level level,
> + u32 flags)
> +{
> + u64 idx = offset >> GEN8_PTE_SHIFT;
> + struct i915_page_directory * const pdp =
> + gen8_pdp_for_page_index(vm, idx);
> + struct i915_page_directory *pd =
> + i915_pd_entry(pdp, gen8_pd_index(idx, 2));
> + struct i915_page_table *pt = i915_pt_entry(pd, gen8_pd_index(idx, 1));
> + gen8_pte_t *vaddr;
> +
> + GEM_BUG_ON(!IS_ALIGNED(addr, SZ_64K));
> + GEM_BUG_ON(!IS_ALIGNED(offset, SZ_64K));
> +
> + if (!pt->is_compact) {
> + vaddr = px_vaddr(pd);
> + vaddr[gen8_pd_index(idx, 1)] |= GEN12_PDE_64K;
> + pt->is_compact = true;
> + }
> +
> + vaddr = px_vaddr(pt);
> + vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level, flags);
> +}
> +
> +static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
> +dma_addr_t addr,
> +u64 offset,
> +enum i915_cache_level level,
> +u32 flags)
> +{
> + if (flags & PTE_LM)
> + return __xehpsdv_ppgtt_insert_entry_lm(vm, addr, offset,
> +level, flags);
> +
> + return gen8_ppgtt_insert_entry(vm, addr, offset, level, flags);
Matt,
Is this call for gen8_*** is for insertion of smem PTE entries on the
64K capable platforms like DG2?
Ram
> +}
> +
> static int gen8_init_scratch(struct i915_address_space *vm)
> {
> u32 pte_flags;
> @@ -937,7 +980,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
>
> ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
> ppgtt->vm.insert_entries = gen8_ppgtt_insert;
> - ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
> + if (HAS_64K_PAGES(gt->i915))
> + ppgtt->vm.insert_page = xehpsdv_ppgtt_insert_entry;
> + else
> + ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
> ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
> ppgtt->vm.clear_range = gen8_ppgtt_clear;
> ppgtt->vm.foreach = gen8_ppgtt_foreach;
> --
> 2.31.1
>
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftest: Disable IRQ for timestamp calculation (rev3)
We have a bug https://gitlab.freedesktop.org/drm/intel/-/issues/4384 for the regression failure. Re-reported. Thanks, Lakshmi. -Original Message- From: Gupta, Anshuman Sent: Friday, December 3, 2021 12:40 AM To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana Cc: Dixit, Ashutosh ; Nilawar, Badal Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/selftest: Disable IRQ for timestamp calculation (rev3) On 2021-11-30 at 18:29:54 +, Patchwork wrote: > == Series Details == > > Series: drm/i915/selftest: Disable IRQ for timestamp calculation (rev3) > URL : https://patchwork.freedesktop.org/series/96853/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_10943_full -> Patchwork_21701_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_21701_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_21701_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Participating hosts (11 -> 11) > -- > > No changes in participating hosts > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_21701_full: > > ### IGT changes ### > > Possible regressions > > * igt@gem_fenced_exec_thrash@too-many-fences: > - shard-snb: [PASS][1] -> [INCOMPLETE][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10943/shard-snb4/igt@gem_fenced_exec_thr...@too-many-fences.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-snb5/ig > t@gem_fenced_exec_thr...@too-many-fences.html Above failure is unrelated to this patch. Pushed to drm-intel-next, thanks for review. Br, Anshuman. > > > Known issues > > > Here are the changes found in Patchwork_21701_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_exec_balancer@parallel-out-fence: > - shard-iclb: NOTRUN -> [SKIP][3] ([i915#4525]) >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-iclb6/i > gt@gem_exec_balan...@parallel-out-fence.html > > * igt@gem_exec_fair@basic-deadline: > - shard-glk: [PASS][4] -> [FAIL][5] ([i915#2846]) >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10943/shard-glk2/igt@gem_exec_f...@basic-deadline.html >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-glk5/ig > t@gem_exec_f...@basic-deadline.html > > * igt@gem_exec_fair@basic-none-rrul@rcs0: > - shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842]) >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10943/shard-kbl7/igt@gem_exec_fair@basic-none-r...@rcs0.html >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-kbl7/ig > t@gem_exec_fair@basic-none-r...@rcs0.html > > * igt@gem_exec_fair@basic-none@vcs1: > - shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-iclb4/i > gt@gem_exec_fair@basic-n...@vcs1.html > > * igt@gem_exec_fair@basic-pace-share@rcs0: > - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar > issue >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10943/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-glk6/ig > t@gem_exec_fair@basic-pace-sh...@rcs0.html > > * igt@gem_lmem_swapping@heavy-verify-random: > - shard-kbl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-kbl3/ig > t@gem_lmem_swapp...@heavy-verify-random.html > > * igt@gem_userptr_blits@input-checking: > - shard-skl: NOTRUN -> [DMESG-WARN][12] ([i915#3002]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-skl4/ig > t@gem_userptr_bl...@input-checking.html > > * igt@gem_userptr_blits@vma-merge: > - shard-skl: NOTRUN -> [FAIL][13] ([i915#3318]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-skl4/ig > t@gem_userptr_bl...@vma-merge.html > > * igt@i915_suspend@debugfs-reader: > - shard-kbl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) +4 > similar issues >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10943/shard-kbl2/igt@i915_susp...@debugfs-reader.html >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-kbl4/ig > t@i915_susp...@debugfs-reader.html > > * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip: > - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3777]) > +1
Re: [Intel-gfx] [PATCH v2 1/8] drm/i915/migrate: don't check the scratch page
On 2021-12-03 at 12:24:19 +, Matthew Auld wrote:
> The scratch page might not be allocated in LMEM(like on DG2), so instead
> of using that as the deciding factor for where the paging structures
> live, let's just query the pt before mapping it.
>
Looks good to me.
Reviewed-by: Ramalingam C
> Signed-off-by: Matthew Auld
> Cc: Thomas Hellström
> Cc: Ramalingam C
> ---
> drivers/gpu/drm/i915/gt/intel_migrate.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
> b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 765c6d48fe52..2d3188a398dd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -13,7 +13,6 @@
>
> struct insert_pte_data {
> u64 offset;
> - bool is_lmem;
> };
>
> #define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
> @@ -41,7 +40,7 @@ static void insert_pte(struct i915_address_space *vm,
> struct insert_pte_data *d = data;
>
> vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE,
> - d->is_lmem ? PTE_LM : 0);
> + i915_gem_object_is_lmem(pt->base) ? PTE_LM : 0);
> d->offset += PAGE_SIZE;
> }
>
> @@ -135,7 +134,6 @@ static struct i915_address_space *migrate_vm(struct
> intel_gt *gt)
> goto err_vm;
>
> /* Now allow the GPU to rewrite the PTE via its own ppGTT */
> - d.is_lmem = i915_gem_object_is_lmem(vm->vm.scratch[0]);
> vm->vm.foreach(&vm->vm, base, base + sz, insert_pte, &d);
> }
>
> --
> 2.31.1
>
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftest: Disable IRQ for timestamp calculation (rev3)
== Series Details == Series: drm/i915/selftest: Disable IRQ for timestamp calculation (rev3) URL : https://patchwork.freedesktop.org/series/96853/ State : success == Summary == CI Bug Log - changes from CI_DRM_10943_full -> Patchwork_21701_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_21701_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@parallel-out-fence: - shard-iclb: NOTRUN -> [SKIP][1] ([i915#4525]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-iclb6/igt@gem_exec_balan...@parallel-out-fence.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][2] -> [FAIL][3] ([i915#2846]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10943/shard-glk2/igt@gem_exec_f...@basic-deadline.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-glk5/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-kbl: [PASS][4] -> [FAIL][5] ([i915#2842]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10943/shard-kbl7/igt@gem_exec_fair@basic-none-r...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-kbl7/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10943/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_fenced_exec_thrash@too-many-fences: - shard-snb: [PASS][9] -> [INCOMPLETE][10] ([i915#4384]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10943/shard-snb4/igt@gem_fenced_exec_thr...@too-many-fences.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-snb5/igt@gem_fenced_exec_thr...@too-many-fences.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-kbl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-kbl3/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_userptr_blits@input-checking: - shard-skl: NOTRUN -> [DMESG-WARN][12] ([i915#3002]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-skl4/igt@gem_userptr_bl...@input-checking.html * igt@gem_userptr_blits@vma-merge: - shard-skl: NOTRUN -> [FAIL][13] ([i915#3318]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-skl4/igt@gem_userptr_bl...@vma-merge.html * igt@i915_suspend@debugfs-reader: - shard-kbl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) +4 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10943/shard-kbl2/igt@i915_susp...@debugfs-reader.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-kbl4/igt@i915_susp...@debugfs-reader.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3777]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-kbl3/igt@kms_big...@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_big_fb@y-tiled-32bpp-rotate-0: - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#118]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10943/shard-glk4/igt@kms_big...@y-tiled-32bpp-rotate-0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-glk2/igt@kms_big...@y-tiled-32bpp-rotate-0.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][19] ([i915#3743]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-skl9/igt@kms_big...@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc: - shard-skl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3886]) +7 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21701/shard-skl9/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs: - shard-kbl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3886]) +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/P
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp: Actually read Adjust Request Post Cursor2 register
== Series Details == Series: drm/dp: Actually read Adjust Request Post Cursor2 register URL : https://patchwork.freedesktop.org/series/97533/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10959_full -> Patchwork_21740_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21740_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21740_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21740_full: ### IGT changes ### Possible regressions * igt@i915_suspend@sysfs-reader: - shard-kbl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21740/shard-kbl4/igt@i915_susp...@sysfs-reader.html * igt@kms_atomic_transition@modeset-transition-fencing@1x-outputs: - shard-tglb: [PASS][2] -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10959/shard-tglb3/igt@kms_atomic_transition@modeset-transition-fenc...@1x-outputs.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21740/shard-tglb8/igt@kms_atomic_transition@modeset-transition-fenc...@1x-outputs.html Known issues Here are the changes found in Patchwork_21740_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-contexts-immediate: - shard-iclb: [PASS][4] -> [TIMEOUT][5] ([i915#3070]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10959/shard-iclb2/igt@gem_...@in-flight-contexts-immediate.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21740/shard-iclb8/igt@gem_...@in-flight-contexts-immediate.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][6] -> [TIMEOUT][7] ([i915#3063] / [i915#3648]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10959/shard-tglb8/igt@gem_...@unwedge-stress.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21740/shard-tglb6/igt@gem_...@unwedge-stress.html * igt@gem_exec_capture@pi@bcs0: - shard-skl: NOTRUN -> [INCOMPLETE][8] ([i915#4547]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21740/shard-skl8/igt@gem_exec_capture@p...@bcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10959/shard-glk5/igt@gem_exec_fair@basic-n...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21740/shard-glk9/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21740/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html - shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10959/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21740/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_params@secure-non-master: - shard-tglb: NOTRUN -> [SKIP][14] ([fdo#112283]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21740/shard-tglb2/igt@gem_exec_par...@secure-non-master.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][15] -> [SKIP][16] ([i915#2190]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10959/shard-tglb5/igt@gem_huc_c...@huc-copy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21740/shard-tglb6/igt@gem_huc_c...@huc-copy.html - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21740/shard-skl1/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@random: - shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21740/shard-kbl7/igt@gem_lmem_swapp...@random.html * igt@gem_lmem_swapping@verify-random: - shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21740/shard-skl9/igt@gem_lmem_swapp...@verify-random.html * igt@gem_pwrite@basic-exhaustion: - shard-apl: NOTRUN -> [WARN][20] ([i915#2658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21740/shard-apl4/igt@gem_pwr...@basic-exhaustion.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][21
Re: [Intel-gfx] [PATCH 20/20] drm/i915/fbc: Pimp the FBC debugfs output
On Fri, 03 Dec 2021, Ville Syrjälä wrote: > On Wed, Nov 24, 2021 at 01:36:52PM +0200, Ville Syrjala wrote: >> From: Ville Syrjälä >> >> Now that each plane tracks its own no_fbc_reason we can print that >> out in debugfs, and we can also show which plane is currently >> selected for FBC duty. >> >> Signed-off-by: Ville Syrjälä > > This one is still missing review. > > I've pushed everything else, thans for the reviews so far. Seems fine. Reviewed-by: Jani Nikula -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH i-g-t] intel-gpu-top: Add support for per client stats
From: Tvrtko Ursulin
Use the i915 exported data in /proc//fdinfo to show GPU utilization
per DRM client.
Example of the output:
intel-gpu-top: Intel Tigerlake (Gen12) @ /dev/dri/card0 - 220/ 221 MHz
70% RC6; 0.62/ 7.08 W; 760 irqs/s
ENGINES BUSY MI_SEMA MI_WAIT
Render/3D 23.06% |██▊ | 0% 0%
Blitter0.00% | | 0% 0%
Video5.40% |█▋ | 0% 0%
VideoEnhance 20.67% |██ | 0% 0%
PID NAME Render/3DBlitter VideoVideoEnhance
3082 mpv | || ||▌ ||██|
3117 neverball |█▉|| || || |
1 systemd |▍ || || || |
2338 gnome-shell | || || || |
Signed-off-by: Tvrtko Ursulin
---
man/intel_gpu_top.rst | 4 +
tools/intel_gpu_top.c | 866 +-
2 files changed, 868 insertions(+), 2 deletions(-)
diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rst
index b3b765b05feb..f4dbfc5b44d9 100644
--- a/man/intel_gpu_top.rst
+++ b/man/intel_gpu_top.rst
@@ -56,6 +56,10 @@ Supported keys:
'q'Exit from the tool.
'h'Show interactive help.
'1'Toggle between aggregated engine class and physical engine mode.
+'n'Toggle display of numeric client busyness overlay.
+'s'Toggle between sort modes (runtime, total runtime, pid, client id).
+'i'Toggle display of clients which used no GPU time.
+'H'Toggle between per PID aggregation and individual clients.
DEVICE SELECTION
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 81c724d1fe1c..5c9a195ea275 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -43,6 +43,7 @@
#include
#include
#include
+#include
#include "igt_perf.h"
@@ -309,7 +310,8 @@ static int engine_cmp(const void *__a, const void *__b)
return a->instance - b->instance;
}
-#define is_igpu_pci(x) (strcmp(x, ":00:02.0") == 0)
+#define IGPU_PCI ":00:02.0"
+#define is_igpu_pci(x) (strcmp(x, IGPU_PCI) == 0)
#define is_igpu(x) (strcmp(x, "i915") == 0)
static struct engines *discover_engines(char *device)
@@ -633,6 +635,613 @@ static void pmu_sample(struct engines *engines)
}
}
+enum client_status {
+ FREE = 0, /* mbz */
+ ALIVE,
+ PROBE
+};
+
+struct clients;
+
+struct client {
+ struct clients *clients;
+
+ enum client_status status;
+ unsigned int id;
+ unsigned int pid;
+ char name[24];
+ char print_name[24];
+ unsigned int samples;
+ unsigned long total_runtime;
+ unsigned long last_runtime;
+ struct engines *engines;
+ unsigned long *val;
+ uint64_t *last;
+};
+
+struct clients {
+ unsigned int num_clients;
+ unsigned int active_clients;
+
+ unsigned int num_classes;
+ struct engine_class *class;
+
+ char pci_slot[64];
+
+ struct client *client;
+};
+
+#define for_each_client(clients, c, tmp) \
+ for ((tmp) = (clients)->num_clients, c = (clients)->client; \
+(tmp > 0); (tmp)--, (c)++)
+
+static struct clients *init_clients(const char *pci_slot)
+{
+ struct clients *clients;
+
+ clients = malloc(sizeof(*clients));
+ if (!clients)
+ return NULL;
+
+ memset(clients, 0, sizeof(*clients));
+
+ strncpy(clients->pci_slot, pci_slot, sizeof(clients->pci_slot));
+
+ return clients;
+}
+
+static struct client *
+find_client(struct clients *clients, enum client_status status, unsigned int
id)
+{
+ unsigned int start, num;
+ struct client *c;
+
+ start = status == FREE ? clients->active_clients : 0; /* Free block at
the end. */
+ num = clients->num_clients - start;
+
+ for (c = &clients->client[start]; num; c++, num--) {
+ if (status != c->status)
+ continue;
+
+ if (status == FREE || c->id == id)
+ return c;
+ }
+
+ return NULL;
+}
+
+static void
+update_client(struct client *c, unsigned int pid, char *name, uint64_t val[16])
+{
+ unsigned int i;
+
+ if (c->pid != pid)
+ c->pid = pid;
+
+ if (strcmp(c->name, name)) {
+ char *p;
+
+ strncpy(c->name, name, sizeof(c->name) - 1);
+ strncpy(c->print_name, name, sizeof(c->print_name) - 1);
+
+ p = c->print_name;
+ while (*p) {
+ if (!isprint(*p))
+ *p = '*';
+ p++;
+ }
+ }
+
+ c->last_runtime = 0;
+ c->total_runtime = 0;
+
+ for (i = 0; i < c->
[Intel-gfx] [PATCH 6/7] drm: Document fdinfo format specification
From: Tvrtko Ursulin Proposal to standardise the fdinfo text format as optionally output by DRM drivers. Idea is that a simple but, well defined, spec will enable generic userspace tools to be written while at the same time avoiding a more heavy handed approach of adding a mid-layer to DRM. i915 implements a subset of the spec, everything apart from the memory stats currently, and a matching intel_gpu_top tool exists. Open is to see if AMD can migrate to using the proposed GPU utilisation key-value pairs, or if they are not workable to see whether to go vendor specific, or if a standardised alternative can be found which is workable for both drivers. Same for the memory utilisation key-value pairs proposal. v2: * Update for removal of name and pid. v3: * 'Drm-driver' tag will be obtained from struct drm_driver.name. (Daniel) Signed-off-by: Tvrtko Ursulin Cc: David M Nieto Cc: Christian König Cc: Daniel Vetter Cc: Daniel Stone Acked-by: Christian König --- Documentation/gpu/drm-usage-stats.rst | 97 +++ Documentation/gpu/index.rst | 1 + 2 files changed, 98 insertions(+) create mode 100644 Documentation/gpu/drm-usage-stats.rst diff --git a/Documentation/gpu/drm-usage-stats.rst b/Documentation/gpu/drm-usage-stats.rst new file mode 100644 index ..c669026be244 --- /dev/null +++ b/Documentation/gpu/drm-usage-stats.rst @@ -0,0 +1,97 @@ +.. _drm-client-usage-stats: + +== +DRM client usage stats +== + +DRM drivers can choose to export partly standardised text output via the +`fops->show_fdinfo()` as part of the driver specific file operations registered +in the `struct drm_driver` object registered with the DRM core. + +One purpose of this output is to enable writing as generic as practicaly +feasible `top(1)` like userspace monitoring tools. + +Given the differences between various DRM drivers the specification of the +output is split between common and driver specific parts. Having said that, +wherever possible effort should still be made to standardise as much as +possible. + +File format specification += + +- File shall contain one key value pair per one line of text. +- Colon character (`:`) must be used to delimit keys and values. +- All keys shall be prefixed with `drm-`. +- Whitespace between the delimiter and first non-whitespace character shall be + ignored when parsing. +- Neither keys or values are allowed to contain whitespace characters. +- Numerical key value pairs can end with optional unit string. +- Data type of the value is fixed as defined in the specification. + +Key types +- + +1. Mandatory, fully standardised. +2. Optional, fully standardised. +3. Driver specific. + +Data types +-- + +- - Unsigned integer without defining the maximum value. +- - String excluding any above defined reserved characters or whitespace. + +Mandatory fully standardised keys +- + +- drm-driver: + +String shall contain the name this driver registered as via the respective +`struct drm_driver` data structure. + +Optional fully standardised keys + + +- drm-pdev: + +For PCI devices this should contain the PCI slot address of the device in +question. + +- drm-client-id: + +Unique value relating to the open DRM file descriptor used to distinguish +duplicated and shared file descriptors. Conceptually the value should map 1:1 +to the in kernel representation of `struct drm_file` instances. + +Uniqueness of the value shall be either globally unique, or unique within the +scope of each device, in which case `drm-pdev` shall be present as well. + +Userspace should make sure to not double account any usage statistics by using +the above described criteria in order to associate data to individual clients. + +- drm-engine-: ns + +GPUs usually contain multiple execution engines. Each shall be given a stable +and unique name (str), with possible values documented in the driver specific +documentation. + +Value shall be in specified time units which the respective GPU engine spent +busy executing workloads belonging to this client. + +Values are not required to be constantly monotonic if it makes the driver +implementation easier, but are required to catch up with the previously reported +larger value within a reasonable period. Upon observing a value lower than what +was previously read, userspace is expected to stay with that larger previous +value until a monotonic update is seen. + +- drm-memory-: [KiB|MiB] + +Each possible memory type which can be used to store buffer objects by the +GPU in question shall be given a stable and unique name to be returned as the +string here. + +Value shall reflect the amount of storage currently consumed by the buffer +object belong to this client, in the respective memory region. + +Default unit shall be bytes with optional unit specifiers of 'KiB' or 'MiB' +indicating kibi- o
[Intel-gfx] [PATCH 4/7] drm/i915: Track all user contexts per client
From: Tvrtko Ursulin
We soon want to start answering questions like how much GPU time is the
context belonging to a client which exited still using.
To enable this we start tracking all context belonging to a client on a
separate list.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind Iddamsetty
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 12
drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 3 +++
drivers/gpu/drm/i915/i915_drm_client.c| 2 ++
drivers/gpu/drm/i915/i915_drm_client.h| 5 +
4 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ae9de81b0e6b..b37b0b45ea68 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1461,6 +1461,7 @@ static void set_closed_name(struct i915_gem_context *ctx)
static void context_close(struct i915_gem_context *ctx)
{
+ struct i915_drm_client *client;
struct i915_address_space *vm;
/* Flush any concurrent set_engines() */
@@ -1498,6 +1499,13 @@ static void context_close(struct i915_gem_context *ctx)
list_del(&ctx->link);
spin_unlock(&ctx->i915->gem.contexts.lock);
+ client = ctx->client;
+ if (client) {
+ spin_lock(&client->ctx_lock);
+ list_del_rcu(&ctx->client_link);
+ spin_unlock(&client->ctx_lock);
+ }
+
mutex_unlock(&ctx->mutex);
/*
@@ -1683,6 +1691,10 @@ static void gem_context_register(struct i915_gem_context
*ctx,
old = xa_store(&fpriv->context_xa, id, ctx, GFP_KERNEL);
WARN_ON(old);
+ spin_lock(&ctx->client->ctx_lock);
+ list_add_tail_rcu(&ctx->client_link, &ctx->client->ctx_list);
+ spin_unlock(&ctx->client->ctx_lock);
+
spin_lock(&i915->gem.contexts.lock);
list_add_tail(&ctx->link, &i915->gem.contexts.list);
spin_unlock(&i915->gem.contexts.lock);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 93d24f189ba9..5946dcb11cf5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -296,6 +296,9 @@ struct i915_gem_context {
/** @client: struct i915_drm_client */
struct i915_drm_client *client;
+ /** link: &drm_client.context_list */
+ struct list_head client_link;
+
/**
* @ref: reference count
*
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c
b/drivers/gpu/drm/i915/i915_drm_client.c
index e61e9ba15256..91a8559bebf7 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -38,6 +38,8 @@ struct i915_drm_client *i915_drm_client_add(struct
i915_drm_clients *clients)
goto err;
kref_init(&client->kref);
+ spin_lock_init(&client->ctx_lock);
+ INIT_LIST_HEAD(&client->ctx_list);
client->clients = clients;
return client;
diff --git a/drivers/gpu/drm/i915/i915_drm_client.h
b/drivers/gpu/drm/i915/i915_drm_client.h
index 9d80d9f715ee..7416e18aa33c 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.h
+++ b/drivers/gpu/drm/i915/i915_drm_client.h
@@ -7,6 +7,8 @@
#define __I915_DRM_CLIENT_H__
#include
+#include
+#include
#include
#include "gt/intel_engine_types.h"
@@ -25,6 +27,9 @@ struct i915_drm_client {
unsigned int id;
+ spinlock_t ctx_lock; /* For add/remove from ctx_list. */
+ struct list_head ctx_list; /* List of contexts belonging to client. */
+
struct i915_drm_clients *clients;
/**
--
2.32.0
[Intel-gfx] [PATCH 7/7] drm/i915: Expose client engine utilisation via fdinfo
From: Tvrtko Ursulin
Similar to AMD commit
874442541133 ("drm/amdgpu: Add show_fdinfo() interface"), using the
infrastructure added in previous patches, we add basic client info
and GPU engine utilisation for i915.
Example of the output:
pos:0
flags: 012
mnt_id: 21
drm-driver: i915
drm-pdev: :00:02.0
drm-client-id: 7
drm-engine-render: 9288864723 ns
drm-engine-copy:2035071108 ns
drm-engine-video: 0 ns
drm-engine-video-enhance: 0 ns
v2:
* Update for removal of name and pid.
v3:
* Use drm_driver.name.
Signed-off-by: Tvrtko Ursulin
Cc: David M Nieto
Cc: Christian König
Cc: Daniel Vetter
Acked-by: Christian König
---
Documentation/gpu/drm-usage-stats.rst | 6 +++
Documentation/gpu/i915.rst | 27 ++
drivers/gpu/drm/i915/i915_driver.c | 3 ++
drivers/gpu/drm/i915/i915_drm_client.c | 73 ++
drivers/gpu/drm/i915/i915_drm_client.h | 4 ++
5 files changed, 113 insertions(+)
diff --git a/Documentation/gpu/drm-usage-stats.rst
b/Documentation/gpu/drm-usage-stats.rst
index c669026be244..6952f8389d07 100644
--- a/Documentation/gpu/drm-usage-stats.rst
+++ b/Documentation/gpu/drm-usage-stats.rst
@@ -95,3 +95,9 @@ object belong to this client, in the respective memory region.
Default unit shall be bytes with optional unit specifiers of 'KiB' or 'MiB'
indicating kibi- or mebi-bytes.
+
+===
+Driver specific implementations
+===
+
+:ref:`i915-usage-stats`
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index b7d801993bfa..29f412a0c3dc 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -708,3 +708,30 @@ The style guide for ``i915_reg.h``.
.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
:doc: The i915 register macro definition style guide
+
+.. _i915-usage-stats:
+
+i915 DRM client usage stats implementation
+==
+
+The drm/i915 driver implements the DRM client usage stats specification as
+documented in :ref:`drm-client-usage-stats`.
+
+Example of the output showing the implemented key value pairs and entirety of
+the currenly possible format options:
+
+::
+
+ pos:0
+ flags: 012
+ mnt_id: 21
+ drm-driver: i915
+ drm-pdev: :00:02.0
+ drm-client-id: 7
+ drm-engine-render: 9288864723 ns
+ drm-engine-copy:2035071108 ns
+ drm-engine-video: 0 ns
+ drm-engine-video-enhance: 0 ns
+
+Possible `drm-engine-` key names are: `render`, `copy`, `video` and
+`video-enhance`.
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index a4f8031602b3..3b75e88de1b8 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1753,6 +1753,9 @@ static const struct file_operations i915_driver_fops = {
.read = drm_read,
.compat_ioctl = i915_ioc32_compat_ioctl,
.llseek = noop_llseek,
+#ifdef CONFIG_PROC_FS
+ .show_fdinfo = i915_drm_client_fdinfo,
+#endif
};
static int
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c
b/drivers/gpu/drm/i915/i915_drm_client.c
index 91a8559bebf7..06dbd20ce763 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -7,6 +7,11 @@
#include
#include
+#include
+
+#include
+
+#include "gem/i915_gem_context.h"
#include "i915_drm_client.h"
#include "i915_gem.h"
#include "i915_utils.h"
@@ -68,3 +73,71 @@ void i915_drm_clients_fini(struct i915_drm_clients *clients)
GEM_BUG_ON(!xa_empty(&clients->xarray));
xa_destroy(&clients->xarray);
}
+
+#ifdef CONFIG_PROC_FS
+static const char * const uabi_class_names[] = {
+ [I915_ENGINE_CLASS_RENDER] = "render",
+ [I915_ENGINE_CLASS_COPY] = "copy",
+ [I915_ENGINE_CLASS_VIDEO] = "video",
+ [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
+};
+
+static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
+{
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+ u64 total = 0;
+
+ for_each_gem_engine(ce, rcu_dereference(ctx->engines), it) {
+ if (ce->engine->uabi_class != class)
+ continue;
+
+ total += intel_context_get_total_runtime_ns(ce);
+ }
+
+ return total;
+}
+
+static void
+show_client_class(struct seq_file *m,
+ struct i915_drm_client *client,
+ unsigned int class)
+{
+ const struct list_head *list = &client->ctx_list;
+ u64 total = atomic64_read(&client->past_runtime[class]);
+ struct i915_gem_context *ctx;
+
+ rcu_read_lock();
+ list_for_each_entry_rcu(ctx, list, client_link)
+ total += busy_add(ctx, class);
+ rcu_read_unlock();
+
+ return seq_printf(m, "drm-engine-%s:\t%llu ns\n",
+ uabi_class_names[class], total);
+}
+
+void i915
[Intel-gfx] [PATCH 5/7] drm/i915: Track context current active time
From: Tvrtko Ursulin
Track context active (on hardware) status together with the start
timestamp.
This will be used to provide better granularity of context
runtime reporting in conjunction with already tracked pphwsp accumulated
runtime.
The latter is only updated on context save so does not give us visibility
to any currently executing work.
As part of the patch the existing runtime tracking data is moved under the
new ce->stats member and updated under the seqlock. This provides the
ability to atomically read out accumulated plus active runtime.
v2:
* Rename and make __intel_context_get_active_time unlocked.
v3:
* Use GRAPHICS_VER.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind Iddamsetty # v1
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_context.c | 27 ++-
drivers/gpu/drm/i915/gt/intel_context.h | 15 ---
drivers/gpu/drm/i915/gt/intel_context_types.h | 24 +++--
.../drm/i915/gt/intel_execlists_submission.c | 23
.../gpu/drm/i915/gt/intel_gt_clock_utils.c| 4 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 27 ++-
drivers/gpu/drm/i915/gt/intel_lrc.h | 24 +
drivers/gpu/drm/i915/gt/selftest_lrc.c| 10 +++
drivers/gpu/drm/i915/i915_gpu_error.c | 9 +++
drivers/gpu/drm/i915/i915_gpu_error.h | 2 +-
10 files changed, 116 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index ba083d800a08..2cabba7c1fc0 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -385,7 +385,7 @@ intel_context_init(struct intel_context *ce, struct
intel_engine_cs *engine)
ce->ring = NULL;
ce->ring_size = SZ_4K;
- ewma_runtime_init(&ce->runtime.avg);
+ ewma_runtime_init(&ce->stats.runtime.avg);
ce->vm = i915_vm_get(engine->gt->vm);
@@ -576,6 +576,31 @@ void intel_context_bind_parent_child(struct intel_context
*parent,
child->parallel.parent = parent;
}
+u64 intel_context_get_total_runtime_ns(const struct intel_context *ce)
+{
+ u64 total, active;
+
+ total = ce->stats.runtime.total;
+ if (ce->ops->flags & COPS_RUNTIME_CYCLES)
+ total *= ce->engine->gt->clock_period_ns;
+
+ active = READ_ONCE(ce->stats.active);
+ if (active)
+ active = intel_context_clock() - active;
+
+ return total + active;
+}
+
+u64 intel_context_get_avg_runtime_ns(struct intel_context *ce)
+{
+ u64 avg = ewma_runtime_read(&ce->stats.runtime.avg);
+
+ if (ce->ops->flags & COPS_RUNTIME_CYCLES)
+ avg *= ce->engine->gt->clock_period_ns;
+
+ return avg;
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_context.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index 246c37d72cd7..1a60193fa58e 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -350,18 +350,13 @@ intel_context_clear_nopreempt(struct intel_context *ce)
clear_bit(CONTEXT_NOPREEMPT, &ce->flags);
}
-static inline u64 intel_context_get_total_runtime_ns(struct intel_context *ce)
-{
- const u32 period = ce->engine->gt->clock_period_ns;
-
- return READ_ONCE(ce->runtime.total) * period;
-}
+u64 intel_context_get_total_runtime_ns(const struct intel_context *ce);
+u64 intel_context_get_avg_runtime_ns(struct intel_context *ce);
-static inline u64 intel_context_get_avg_runtime_ns(struct intel_context *ce)
+static inline u64 intel_context_clock(void)
{
- const u32 period = ce->engine->gt->clock_period_ns;
-
- return mul_u32_u32(ewma_runtime_read(&ce->runtime.avg), period);
+ /* As we mix CS cycles with CPU clocks, use the raw monotonic clock. */
+ return ktime_get_raw_fast_ns();
}
#endif /* __INTEL_CONTEXT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 9e0177dc5484..bf26349358f2 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -35,6 +35,9 @@ struct intel_context_ops {
#define COPS_HAS_INFLIGHT_BIT 0
#define COPS_HAS_INFLIGHT BIT(COPS_HAS_INFLIGHT_BIT)
+#define COPS_RUNTIME_CYCLES_BIT 1
+#define COPS_RUNTIME_CYCLES BIT(COPS_RUNTIME_CYCLES_BIT)
+
int (*alloc)(struct intel_context *ce);
void (*ban)(struct intel_context *ce, struct i915_request *rq);
@@ -133,14 +136,19 @@ struct intel_context {
} lrc;
u32 tag; /* cookie passed to HW to track this context on submission */
- /* Time on GPU as tracked by the hw. */
- struct {
- struct ewma_runtime avg;
- u64 total;
- u32 last;
- I915_SELFTEST_DECLARE(u32 num_underflow);
-
[Intel-gfx] [PATCH 3/7] drm/i915: Track runtime spent in closed and unreachable GEM contexts
From: Tvrtko Ursulin
As contexts are abandoned we want to remember how much GPU time they used
(per class) so later we can used it for smarter purposes.
As GEM contexts are closed we want to have the DRM client remember how
much GPU time they used (per class) so later we can used it for smarter
purposes.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind Iddamsetty
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 25 +++--
drivers/gpu/drm/i915/i915_drm_client.h | 7 ++
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 78c357baa65d..ae9de81b0e6b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1001,23 +1001,44 @@ static void free_engines_rcu(struct rcu_head *rcu)
free_engines(engines);
}
+static void accumulate_runtime(struct i915_drm_client *client,
+ struct i915_gem_engines *engines)
+{
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+
+ if (!client)
+ return;
+
+ /* Transfer accumulated runtime to the parent GEM context. */
+ for_each_gem_engine(ce, engines, it) {
+ unsigned int class = ce->engine->uabi_class;
+
+ GEM_BUG_ON(class >= ARRAY_SIZE(client->past_runtime));
+ atomic64_add(intel_context_get_total_runtime_ns(ce),
+&client->past_runtime[class]);
+ }
+}
+
static int
engines_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
{
struct i915_gem_engines *engines =
container_of(fence, typeof(*engines), fence);
+ struct i915_gem_context *ctx = engines->ctx;
switch (state) {
case FENCE_COMPLETE:
if (!list_empty(&engines->link)) {
- struct i915_gem_context *ctx = engines->ctx;
unsigned long flags;
spin_lock_irqsave(&ctx->stale.lock, flags);
list_del(&engines->link);
spin_unlock_irqrestore(&ctx->stale.lock, flags);
}
- i915_gem_context_put(engines->ctx);
+ accumulate_runtime(ctx->client, engines);
+ i915_gem_context_put(ctx);
+
break;
case FENCE_FREE:
diff --git a/drivers/gpu/drm/i915/i915_drm_client.h
b/drivers/gpu/drm/i915/i915_drm_client.h
index e8986ad51176..9d80d9f715ee 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.h
+++ b/drivers/gpu/drm/i915/i915_drm_client.h
@@ -9,6 +9,8 @@
#include
#include
+#include "gt/intel_engine_types.h"
+
struct drm_i915_private;
struct i915_drm_clients {
@@ -24,6 +26,11 @@ struct i915_drm_client {
unsigned int id;
struct i915_drm_clients *clients;
+
+ /**
+* @past_runtime: Accumulation of pphwsp runtimes from closed contexts.
+*/
+ atomic64_t past_runtime[MAX_ENGINE_CLASS + 1];
};
void i915_drm_clients_init(struct i915_drm_clients *clients,
--
2.32.0
[Intel-gfx] [PATCH 2/7] drm/i915: Make GEM contexts track DRM clients
From: Tvrtko Ursulin
Make GEM contexts keep a reference to i915_drm_client for the whole of
of their lifetime which will come handy in following patches.
v2: Don't bother supporting selftests contexts from debugfs. (Chris)
v3 (Lucas): Finish constructing ctx before adding it to the list
v4 (Ram): Rebase.
v5: Trivial rebase for proto ctx changes.
v6: Rebase after clients no longer track name and pid.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson # v5
Reviewed-by: Aravind Iddamsetty # v5
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +
drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 347dab952e90..78c357baa65d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1227,6 +1227,9 @@ static void i915_gem_context_release_work(struct
work_struct *work)
if (ctx->pxp_wakeref)
intel_runtime_pm_put(&ctx->i915->runtime_pm, ctx->pxp_wakeref);
+ if (ctx->client)
+ i915_drm_client_put(ctx->client);
+
mutex_destroy(&ctx->engines_mutex);
mutex_destroy(&ctx->lut_mutex);
@@ -1650,6 +1653,8 @@ static void gem_context_register(struct i915_gem_context
*ctx,
ctx->file_priv = fpriv;
ctx->pid = get_task_pid(current, PIDTYPE_PID);
+ ctx->client = i915_drm_client_get(fpriv->client);
+
snprintf(ctx->name, sizeof(ctx->name), "%s[%d]",
current->comm, pid_nr(ctx->pid));
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 282cdb8a5c5a..93d24f189ba9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -293,6 +293,9 @@ struct i915_gem_context {
/** @link: place with &drm_i915_private.context_list */
struct list_head link;
+ /** @client: struct i915_drm_client */
+ struct i915_drm_client *client;
+
/**
* @ref: reference count
*
--
2.32.0
[Intel-gfx] [PATCH 1/7] drm/i915: Explicitly track DRM clients
From: Tvrtko Ursulin
Tracking DRM clients more explicitly will allow later patches to
accumulate past and current GPU usage in a centralised place and also
consolidate access to owning task pid/name.
Unique client id is also assigned for the purpose of distinguishing/
consolidating between multiple file descriptors owned by the same process.
v2:
Chris Wilson:
* Enclose new members into dedicated structs.
* Protect against failed sysfs registration.
v3:
* sysfs_attr_init.
v4:
* Fix for internal clients.
v5:
* Use cyclic ida for client id. (Chris)
* Do not leak pid reference. (Chris)
* Tidy code with some locals.
v6:
* Use xa_alloc_cyclic to simplify locking. (Chris)
* No need to unregister individial sysfs files. (Chris)
* Rebase on top of fpriv kref.
* Track client closed status and reflect in sysfs.
v7:
* Make drm_client more standalone concept.
v8:
* Simplify sysfs show. (Chris)
* Always track name and pid.
v9:
* Fix cyclic id assignment.
v10:
* No need for a mutex around xa_alloc_cyclic.
* Refactor sysfs into own function.
* Unregister sysfs before freeing pid and name.
* Move clients setup into own function.
v11:
* Call clients init directly from driver init. (Chris)
v12:
* Do not fail client add on id wrap. (Maciej)
v13 (Lucas): Rebase.
v14:
* Dropped sysfs bits.
v15:
* Dropped tracking of pid/ and name.
* Dropped RCU freeing of the client object.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson # v11
Reviewed-by: Aravind Iddamsetty # v11
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_driver.c | 6 +++
drivers/gpu/drm/i915/i915_drm_client.c | 68 ++
drivers/gpu/drm/i915/i915_drm_client.h | 50 +++
drivers/gpu/drm/i915/i915_drv.h| 5 ++
drivers/gpu/drm/i915/i915_gem.c| 21 ++--
6 files changed, 148 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_drm_client.c
create mode 100644 drivers/gpu/drm/i915/i915_drm_client.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3b5857da4123..2a94e7c441a0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -31,6 +31,7 @@ subdir-ccflags-y += -I$(srctree)/$(src)
# core driver code
i915-y += i915_driver.o \
+ i915_drm_client.o \
i915_config.o \
i915_irq.o \
i915_getparam.o \
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index bbc99fc5888f..a4f8031602b3 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -73,6 +73,7 @@
#include "i915_debugfs.h"
#include "i915_driver.h"
+#include "i915_drm_client.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
#include "i915_irq.h"
@@ -349,6 +350,8 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
intel_gt_init_early(&dev_priv->gt, dev_priv);
+ i915_drm_clients_init(&dev_priv->clients, dev_priv);
+
i915_gem_init_early(dev_priv);
/* This must be called before any calls to HAS_PCH_* */
@@ -368,6 +371,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
err_gem:
i915_gem_cleanup_early(dev_priv);
+ i915_drm_clients_fini(&dev_priv->clients);
intel_gt_driver_late_release(&dev_priv->gt);
intel_region_ttm_device_fini(dev_priv);
err_ttm:
@@ -387,6 +391,7 @@ static void i915_driver_late_release(struct
drm_i915_private *dev_priv)
intel_irq_fini(dev_priv);
intel_power_domains_cleanup(dev_priv);
i915_gem_cleanup_early(dev_priv);
+ i915_drm_clients_fini(&dev_priv->clients);
intel_gt_driver_late_release(&dev_priv->gt);
intel_region_ttm_device_fini(dev_priv);
vlv_suspend_cleanup(dev_priv);
@@ -1017,6 +1022,7 @@ static void i915_driver_postclose(struct drm_device *dev,
struct drm_file *file)
struct drm_i915_file_private *file_priv = file->driver_priv;
i915_gem_context_close(file);
+ i915_drm_client_put(file_priv->client);
kfree_rcu(file_priv, rcu);
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c
b/drivers/gpu/drm/i915/i915_drm_client.c
new file mode 100644
index ..e61e9ba15256
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include
+#include
+#include
+
+#include "i915_drm_client.h"
+#include "i915_gem.h"
+#include "i915_utils.h"
+
+void i915_drm_clients_init(struct i915_drm_clients *clients,
+ struct drm_i915_private *i915)
+{
+ clients->i915 = i915;
+ clients->next_id = 0;
+
+ xa_init_flags(&clients->xarray, XA_FLAGS_ALLOC | XA_FLAGS_LOCK_IRQ);
+}
+
+struct i915_drm_client *i915_drm_client_add(struct i915_drm_clients *clients)
+{
+ struct i915_drm_client *client;
+ struct
[Intel-gfx] [PATCH 0/7] Per client GPU stats
From: Tvrtko Ursulin Same old work but now rebased and series ending with some DRM docs proposing the common specification which should enable nice common userspace tools to be written. For the moment I only have intel_gpu_top converted to use this and that seems to work okay. v2: * Added prototype of possible amdgpu changes and spec updates to align with the common spec. v3: * Documented that 'drm-driver' tag shall correspond with struct drm_driver.name. v4: * Dropped amdgpu conversion from the series for now until AMD folks can find some time to finish that patch. Tvrtko Ursulin (7): drm/i915: Explicitly track DRM clients drm/i915: Make GEM contexts track DRM clients drm/i915: Track runtime spent in closed and unreachable GEM contexts drm/i915: Track all user contexts per client drm/i915: Track context current active time drm: Document fdinfo format specification drm/i915: Expose client engine utilisation via fdinfo Documentation/gpu/drm-usage-stats.rst | 103 + Documentation/gpu/i915.rst| 27 Documentation/gpu/index.rst | 1 + drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gem/i915_gem_context.c | 42 - .../gpu/drm/i915/gem/i915_gem_context_types.h | 6 + drivers/gpu/drm/i915/gt/intel_context.c | 27 +++- drivers/gpu/drm/i915/gt/intel_context.h | 15 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 24 ++- .../drm/i915/gt/intel_execlists_submission.c | 23 ++- .../gpu/drm/i915/gt/intel_gt_clock_utils.c| 4 + drivers/gpu/drm/i915/gt/intel_lrc.c | 27 ++-- drivers/gpu/drm/i915/gt/intel_lrc.h | 24 +++ drivers/gpu/drm/i915/gt/selftest_lrc.c| 10 +- drivers/gpu/drm/i915/i915_driver.c| 9 ++ drivers/gpu/drm/i915/i915_drm_client.c| 143 ++ drivers/gpu/drm/i915/i915_drm_client.h| 66 drivers/gpu/drm/i915/i915_drv.h | 5 + drivers/gpu/drm/i915/i915_gem.c | 21 ++- drivers/gpu/drm/i915/i915_gpu_error.c | 9 +- drivers/gpu/drm/i915/i915_gpu_error.h | 2 +- 21 files changed, 535 insertions(+), 54 deletions(-) create mode 100644 Documentation/gpu/drm-usage-stats.rst create mode 100644 drivers/gpu/drm/i915/i915_drm_client.c create mode 100644 drivers/gpu/drm/i915/i915_drm_client.h -- 2.32.0
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen11: Moving WAs to icl_gt_workarounds_init() (rev4)
== Series Details == Series: drm/i915/gen11: Moving WAs to icl_gt_workarounds_init() (rev4) URL : https://patchwork.freedesktop.org/series/97208/ State : success == Summary == CI Bug Log - changes from CI_DRM_10961 -> Patchwork_21747 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/index.html Participating hosts (42 -> 34) -- Additional (1): fi-icl-u2 Missing(9): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21747 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@gem_huc_copy@huc-copy: - fi-icl-u2: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-icl-u2: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][6] ([fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: NOTRUN -> [SKIP][7] ([fdo#109278]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - fi-icl-u2: NOTRUN -> [SKIP][8] ([fdo#109285]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#295]) +12 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html * igt@prime_vgem@basic-userptr: - fi-icl-u2: NOTRUN -> [SKIP][11] ([i915#3301]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/fi-icl-u2/igt@prime_v...@basic-userptr.html Possible fixes * igt@i915_selftest@live@gt_engines: - fi-rkl-guc: [INCOMPLETE][12] ([i915#4432]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick:[DMESG-FAIL][14] ([i915#2927] / [i915#3428]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][16] ([i915#4269]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html Warnings * igt@kms_psr@primary_page_flip: - fi-skl-6600u: [INCOMPLETE][18] ([i915#198] / [i915#4547]) -> [FAIL][19] ([i915#4547]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-skl-6600u/igt@kms_psr@primary_page_flip.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21747/fi-skl-6600u/igt@kms_psr@primary_page_flip.html * igt@runner@aborted: - fi-skl-6600u: [FAIL][20] ([i915#2722] / [i915#3363] / [i915#4312]) -> [FAIL][21] ([i915#3363] / [i915#4312]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/f
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/adl_p: Fix ddc pin mapping
== Series Details == Series: drm/i915/adl_p: Fix ddc pin mapping URL : https://patchwork.freedesktop.org/series/97527/ State : success == Summary == CI Bug Log - changes from CI_DRM_10959_full -> Patchwork_21739_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_21739_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-skl: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-skl1/igt@gem_cre...@create-massive.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][2] -> [TIMEOUT][3] ([i915#3063] / [i915#3648]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10959/shard-tglb8/igt@gem_...@unwedge-stress.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-tglb6/igt@gem_...@unwedge-stress.html * igt@gem_exec_capture@pi@bcs0: - shard-skl: NOTRUN -> [INCOMPLETE][4] ([i915#4547]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-skl4/igt@gem_exec_capture@p...@bcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10959/shard-iclb2/igt@gem_exec_fair@basic-none-sh...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-iclb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10959/shard-glk5/igt@gem_exec_fair@basic-n...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-glk8/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10959/shard-kbl2/igt@gem_exec_fair@basic-pace-s...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10959/shard-tglb3/igt@gem_exec_fair@basic-p...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-tglb3/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_gttfill@engines@rcs0: - shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#118]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10959/shard-glk8/igt@gem_exec_gttfill@engi...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-glk3/igt@gem_exec_gttfill@engi...@rcs0.html * igt@gem_exec_params@secure-non-master: - shard-tglb: NOTRUN -> [SKIP][15] ([fdo#112283]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-tglb1/igt@gem_exec_par...@secure-non-master.html * igt@gem_huc_copy@huc-copy: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#2190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-skl6/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@random: - shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-kbl4/igt@gem_lmem_swapp...@random.html * igt@gem_lmem_swapping@verify-random: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +4 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-skl10/igt@gem_lmem_swapp...@verify-random.html * igt@gem_pwrite@basic-exhaustion: - shard-apl: NOTRUN -> [WARN][19] ([i915#2658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-apl1/igt@gem_pwr...@basic-exhaustion.html * igt@gem_render_copy@y-tiled-to-vebox-x-tiled: - shard-iclb: NOTRUN -> [SKIP][20] ([i915#768]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-iclb1/igt@gem_render_c...@y-tiled-to-vebox-x-tiled.html * igt@gem_userptr_blits@input-checking: - shard-iclb: NOTRUN -> [DMESG-WARN][21] ([i915#3002]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-iclb5/igt@gem_userptr_bl...@input-checking.html * igt@i915_pm_dc@dc9-dpms: - shard-iclb: [PASS][22] -> [SKIP][23] ([i915#4281]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10959/shard-iclb2/igt@i915_pm...@dc9-dpms.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21739/shard-iclb3/igt@i915_pm..
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ddi: add use_edp_hobl() and use_edp_low_vswing() helpers
== Series Details == Series: drm/i915/ddi: add use_edp_hobl() and use_edp_low_vswing() helpers URL : https://patchwork.freedesktop.org/series/97547/ State : success == Summary == CI Bug Log - changes from CI_DRM_10961 -> Patchwork_21745 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/index.html Participating hosts (42 -> 33) -- Missing(9): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21745 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html Possible fixes * igt@i915_selftest@live@gt_engines: - fi-rkl-guc: [INCOMPLETE][3] ([i915#4432]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick:[DMESG-FAIL][5] ([i915#2927] / [i915#3428]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][7] ([i915#4269]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html Warnings * igt@kms_psr@primary_page_flip: - fi-skl-6600u: [INCOMPLETE][9] ([i915#198] / [i915#4547]) -> [INCOMPLETE][10] ([i915#198]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-skl-6600u/igt@kms_psr@primary_page_flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/fi-skl-6600u/igt@kms_psr@primary_page_flip.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 [i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 Build changes - * Linux: CI_DRM_10961 -> Patchwork_21745 CI-20190529: 20190529 CI_DRM_10961: e7bbdc541b4748718cd6ce8b839f3db335f3a0fc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6299: 0933b7ccdb2bb054b6a8154171e35315d84299b7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21745: 914a84c9e0dd1dcc52d4d9107a02dc9e83e43d00 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 914a84c9e0dd drm/i915/ddi: add use_edp_hobl() and use_edp_low_vswing() helpers == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21745/index.html
Re: [Intel-gfx] [Linaro-mm-sig] [RFC PATCH 1/2] dma-fence: Avoid establishing a locking order between fence classes
On 12/3/21 16:00, Christian König wrote: Am 03.12.21 um 15:50 schrieb Thomas Hellström: On 12/3/21 15:26, Christian König wrote: [Adding Daniel here as well] Am 03.12.21 um 15:18 schrieb Thomas Hellström: [SNIP] Well that's ok as well. My question is why does this single dma_fence then shows up in the dma_fence_chain representing the whole migration? What we'd like to happen during eviction is that we 1) await any exclusive- or moving fences, then schedule the migration blit. The blit manages its own GPU ptes. Results in a single fence. 2) Schedule unbind of any gpu vmas, resulting possibly in multiple fences. 3) Most but not all of the remaining resv shared fences will have been finished in 2) We can't easily tell which so we have a couple of shared fences left. Stop, wait a second here. We are going a bit in circles. Before you migrate a buffer, you *MUST* wait for all shared fences to complete. This is documented mandatory DMA-buf behavior. Daniel and I have discussed that quite extensively in the last few month. So how does it come that you do the blit before all shared fences are completed? Well we don't currently but wanted to... (I haven't consulted Daniel in the matter, tbh). I was under the impression that all writes would add an exclusive fence to the dma_resv. Yes that's correct. I'm working on to have more than one write fence, but that is currently under review. If that's not the case or this is otherwise against the mandatory DMA-buf bevhavior, we can certainly keep that part as is and that would eliminate 3). Ah, now that somewhat starts to make sense. So your blit only waits for the writes to finish before starting the blit. Yes that's legal as long as you don't change the original content with the blit. But don't you then need to wait for both reads and writes before you unmap the VMAs? Yes, but that's planned to be done all async, and those unbind jobs are scheduled simultaneosly with the blit, and the blit itself manages its own page-table-entries, so no need to unbind any blit vmas. Anyway the good news is your problem totally goes away with the DMA-resv rework I've already send out. Basically it is now possible to have more than one fence in the DMA-resv object for migrations and all existing fences are kept around until they are finished. Sounds good. Thanks, Thomas
[Intel-gfx] ✗ Fi.CI.BUILD: failure for treewide: add missing includes masked by cgroup -> bpf dependency (rev2)
== Series Details == Series: treewide: add missing includes masked by cgroup -> bpf dependency (rev2) URL : https://patchwork.freedesktop.org/series/97159/ State : failure == Summary == Applying: treewide: add missing includes masked by cgroup -> bpf dependency error: sha1 information is lacking or useless (include/linux/filter.h). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 treewide: add missing includes masked by cgroup -> bpf dependency When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Use hw_engine_masks as reset_domains
== Series Details == Series: drm/i915/gt: Use hw_engine_masks as reset_domains URL : https://patchwork.freedesktop.org/series/97543/ State : success == Summary == CI Bug Log - changes from CI_DRM_10961 -> Patchwork_21743 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21743/index.html Participating hosts (42 -> 33) -- Missing(9): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21743 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21743/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@amdgpu/amd_cs_nop@sync-fork-gfx0: - fi-skl-6600u: NOTRUN -> [SKIP][2] ([fdo#109271]) +18 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21743/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html Possible fixes * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick:[DMESG-FAIL][3] ([i915#2927] / [i915#3428]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21743/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html * igt@kms_psr@primary_page_flip: - fi-skl-6600u: [INCOMPLETE][5] ([i915#198] / [i915#4547]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-skl-6600u/igt@kms_psr@primary_page_flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21743/fi-skl-6600u/igt@kms_psr@primary_page_flip.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 Build changes - * Linux: CI_DRM_10961 -> Patchwork_21743 CI-20190529: 20190529 CI_DRM_10961: e7bbdc541b4748718cd6ce8b839f3db335f3a0fc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6299: 0933b7ccdb2bb054b6a8154171e35315d84299b7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21743: bb714b5063e84b555fd42832b80ea3af0c6bab6f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == bb714b5063e8 drm/i915/gt: Use hw_engine_masks as reset_domains == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21743/index.html
[Intel-gfx] [v2] drm/i915/gen11: Moving WAs to icl_gt_workarounds_init()
From: Raviteja Goud Talla Bspec page says "Reset: BUS", Accordingly moving w/a's: Wa_1407352427,Wa_1406680159 to proper function icl_gt_workarounds_init() Which will resolve guc enabling error v2: - Previous patch rev2 was created by email client which caused the Build failure, This v2 is to resolve the previous broken series Reviewed-by: John Harrison Signed-off-by: Raviteja Goud Talla --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index c3211325c2d3..3113266c286e 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1224,6 +1224,15 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) GAMT_CHKN_BIT_REG, GAMT_CHKN_DISABLE_L3_COH_PIPE); + /* Wa_1407352427:icl,ehl */ + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, + PSDUNIT_CLKGATE_DIS); + + /* Wa_1406680159:icl,ehl */ + wa_write_or(wal, + SUBSLICE_UNIT_LEVEL_CLKGATE, + GWUNIT_CLKGATE_DIS); + /* Wa_1607087056:icl,ehl,jsl */ if (IS_ICELAKE(i915) || IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) @@ -2269,15 +2278,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); - /* Wa_1407352427:icl,ehl */ - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, - PSDUNIT_CLKGATE_DIS); - - /* Wa_1406680159:icl,ehl */ - wa_write_or(wal, - SUBSLICE_UNIT_LEVEL_CLKGATE, - GWUNIT_CLKGATE_DIS); - /* * Wa_1408767742:icl[a2..forever],ehl[all] * Wa_1605460711:icl[a0..c0] -- 2.34.1
Re: [Intel-gfx] [Linaro-mm-sig] [RFC PATCH 1/2] dma-fence: Avoid establishing a locking order between fence classes
On 12/3/21 15:26, Christian König wrote: [Adding Daniel here as well] Am 03.12.21 um 15:18 schrieb Thomas Hellström: [SNIP] Well that's ok as well. My question is why does this single dma_fence then shows up in the dma_fence_chain representing the whole migration? What we'd like to happen during eviction is that we 1) await any exclusive- or moving fences, then schedule the migration blit. The blit manages its own GPU ptes. Results in a single fence. 2) Schedule unbind of any gpu vmas, resulting possibly in multiple fences. 3) Most but not all of the remaining resv shared fences will have been finished in 2) We can't easily tell which so we have a couple of shared fences left. Stop, wait a second here. We are going a bit in circles. Before you migrate a buffer, you *MUST* wait for all shared fences to complete. This is documented mandatory DMA-buf behavior. Daniel and I have discussed that quite extensively in the last few month. So how does it come that you do the blit before all shared fences are completed? Well we don't currently but wanted to... (I haven't consulted Daniel in the matter, tbh). I was under the impression that all writes would add an exclusive fence to the dma_resv. If that's not the case or this is otherwise against the mandatory DMA-buf bevhavior, we can certainly keep that part as is and that would eliminate 3). /Thomas
[Intel-gfx] ✗ Fi.CI.BUILD: failure for DG2 accelerated migration/clearing support
== Series Details == Series: DG2 accelerated migration/clearing support URL : https://patchwork.freedesktop.org/series/97544/ State : failure == Summary == Applying: drm/i915/migrate: don't check the scratch page Applying: drm/i915/gtt: add xehpsdv_ppgtt_insert_entry Applying: drm/i915/gtt: add gtt mappable plumbing Applying: drm/i915/migrate: fix offset calculation Applying: drm/i915/migrate: fix length calculation Applying: drm/i915/selftests: handle object rounding Applying: drm/i915/migrate: add acceleration support for DG2 error: sha1 information is lacking or useless (drivers/gpu/drm/i915/gt/intel_migrate.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0007 drm/i915/migrate: add acceleration support for DG2 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gt: Use hw_engine_masks as reset_domains
== Series Details == Series: drm/i915/gt: Use hw_engine_masks as reset_domains URL : https://patchwork.freedesktop.org/series/97543/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [Linaro-mm-sig] [RFC PATCH 1/2] dma-fence: Avoid establishing a locking order between fence classes
On Fri, 2021-12-03 at 14:08 +0100, Christian König wrote: > Am 01.12.21 um 13:16 schrieb Thomas Hellström (Intel): > > > > On 12/1/21 12:25, Christian König wrote: > > > Am 01.12.21 um 12:04 schrieb Thomas Hellström (Intel): > > > > > > > > On 12/1/21 11:32, Christian König wrote: > > > > > Am 01.12.21 um 11:15 schrieb Thomas Hellström (Intel): > > > > > > [SNIP] > > > > > > > > > > > > > > What we could do is to avoid all this by not calling the > > > > > > > callback > > > > > > > with the lock held in the first place. > > > > > > > > > > > > If that's possible that might be a good idea, pls also see > > > > > > below. > > > > > > > > > > The problem with that is > > > > > dma_fence_signal_locked()/dma_fence_signal_timestamp_locked() > > > > > . If > > > > > we could avoid using that or at least allow it to drop the > > > > > lock > > > > > then we could call the callback without holding it. > > > > > > > > > > Somebody would need to audit the drivers and see if holding > > > > > the > > > > > lock is really necessary anywhere. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > /Thomas > > > > > > > > > > > > > > > > > > > > Oh, and a follow up question: > > > > > > > > > > > > > > > > > > > > If there was a way to break the recursion on final > > > > > > > > > > put() > > > > > > > > > > (using the same basic approach as patch 2 in this > > > > > > > > > > series uses > > > > > > > > > > to break recursion in enable_signaling()), so that > > > > > > > > > > none of > > > > > > > > > > these containers did require any special treatment, > > > > > > > > > > would it > > > > > > > > > > be worth pursuing? I guess it might be possible by > > > > > > > > > > having the > > > > > > > > > > callbacks drop the references rather than the loop > > > > > > > > > > in the > > > > > > > > > > final put. + a couple of changes in code iterating > > > > > > > > > > over the > > > > > > > > > > fence pointers. > > > > > > > > > > > > > > > > > > That won't really help, you just move the recursion > > > > > > > > > from the > > > > > > > > > final put into the callback. > > > > > > > > > > > > > > > > How do we recurse from the callback? The introduced > > > > > > > > fence_put() > > > > > > > > of individual fence pointers > > > > > > > > doesn't recurse anymore (at most 1 level), and any > > > > > > > > callback > > > > > > > > recursion is broken by the irq_work? > > > > > > > > > > > > > > Yeah, but then you would need to take another lock to > > > > > > > avoid > > > > > > > racing with dma_fence_array_signaled(). > > > > > > > > > > > > > > > > > > > > > > > I figure the big amount of work would be to adjust code > > > > > > > > that > > > > > > > > iterates over the individual fence pointers to > > > > > > > > recognize that > > > > > > > > they are rcu protected. > > > > > > > > > > > > > > Could be that we could solve this with RCU, but that > > > > > > > sounds like > > > > > > > a lot of churn for no gain at all. > > > > > > > > > > > > > > In other words even with the problems solved I think it > > > > > > > would be > > > > > > > a really bad idea to allow chaining of dma_fence_array > > > > > > > objects. > > > > > > > > > > > > Yes, that was really the question, Is it worth pursuing > > > > > > this? I'm > > > > > > not really suggesting we should allow this as an > > > > > > intentional > > > > > > feature. I'm worried, however, that if we allow these > > > > > > containers > > > > > > to start floating around cross-driver (or even internally) > > > > > > disguised as ordinary dma_fences, they would require a lot > > > > > > of > > > > > > driver special casing, or else completely unexpeced > > > > > > WARN_ON()s and > > > > > > lockdep splats would start to turn up, scaring people off > > > > > > from > > > > > > using them. And that would be a breeding ground for hairy > > > > > > driver-private constructs. > > > > > > > > > > Well the question is why we would want to do it? > > > > > > > > > > If it's to avoid inter driver lock dependencies by avoiding > > > > > to call > > > > > the callback with the spinlock held, then yes please. We had > > > > > tons > > > > > of problems with that, resulting in irq_work and work_item > > > > > delegation all over the place. > > > > > > > > Yes, that sounds like something desirable, but in these > > > > containers, > > > > what's causing the lock dependencies is the enable_signaling() > > > > callback that is typically called locked. > > > > > > > > > > > > > > > > > > If it's to allow nesting of dma_fence_array instances, then > > > > > it's > > > > > most likely a really bad idea even if we fix all the locking > > > > > order > > > > > problems. > > > > > > > > Well I think my use-case where I hit a dead end may illustrate > > > > what > > > > worries me here: > > > > > > > > 1) We use a dma-fence-array to coalesce all dependencies for > > > > ttm > > > > object mi
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Nuke {pipe, plane}_to_crtc_mapping[]
== Series Details ==
Series: series starting with [1/3] drm/i915: Nuke {pipe,
plane}_to_crtc_mapping[]
URL : https://patchwork.freedesktop.org/series/97541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10961 -> Patchwork_21742
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/index.html
Participating hosts (42 -> 34)
--
Additional (2): fi-icl-u2 fi-pnv-d510
Missing(10): fi-ilk-m540 fi-rkl-guc bat-dg1-6 bat-dg1-5 fi-hsw-4200u
fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus bat-jsl-2 bat-jsl-1
Known issues
Here are the changes found in Patchwork_21742 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-bsw-nick:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [PASS][3] -> [FAIL][4] ([i915#4547])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][5] ([i915#2190])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][7] ([fdo#111827]) +8 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: NOTRUN -> [SKIP][8] ([fdo#109278]) +2 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][9] ([fdo#109285])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][10] ([fdo#109271]) +57 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/fi-pnv-d510/igt@prime_v...@basic-userptr.html
- fi-icl-u2: NOTRUN -> [SKIP][11] ([i915#3301])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/fi-icl-u2/igt@prime_v...@basic-userptr.html
Possible fixes
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick:[DMESG-FAIL][12] ([i915#2927] / [i915#3428]) ->
[PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][14] ([i915#4269]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][16] ([i915#2722] / [i915#3363] / [i915#4312])
-> [FAIL][17] ([i915#3363] / [i915#4312])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10961/fi-skl-6600u/igt@run...@aborted.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21742/fi-skl-6600u/igt@run...@aborted.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3363]: https://gitlab.freedesktop
[Intel-gfx] [PATCH bpf v2] treewide: add missing includes masked by cgroup -> bpf dependency
cgroup.h (therefore swap.h, therefore half of the universe) includes bpf.h which in turn includes module.h and slab.h. Since we're about to get rid of that dependency we need to clean things up. v2: drop the cpu.h include from cacheinfo.h, it's not necessary and it makes riscv sensitive to ordering of include files. Link: https://lore.kernel.org/all/20211120035253.72074-1-k...@kernel.org/ # v1 Link: https://lore.kernel.org/all/20211120165528.197359-1-k...@kernel.org/ # cacheinfo discussion Acked-by: Krzysztof Wilczyński Acked-by: Peter Chen Acked-by: SeongJae Park Acked-by: Jani Nikula Signed-off-by: Jakub Kicinski --- CC: ax...@kernel.dk CC: maarten.lankho...@linux.intel.com CC: mrip...@kernel.org CC: tzimmerm...@suse.de CC: airl...@linux.ie CC: dan...@ffwll.ch CC: jani.nik...@linux.intel.com CC: joonas.lahti...@linux.intel.com CC: rodrigo.v...@intel.com CC: yuq...@gmail.com CC: robdcl...@gmail.com CC: s...@poorly.run CC: christian.koe...@amd.com CC: ray.hu...@amd.com CC: sgout...@marvell.com CC: gak...@marvell.com CC: sbha...@marvell.com CC: hke...@marvell.com CC: jingooh...@gmail.com CC: lorenzo.pieral...@arm.com CC: r...@kernel.org CC: k...@linux.com CC: bhelg...@google.com CC: krzysztof.kozlow...@canonical.com CC: m...@kernel.org CC: paw...@cadence.com CC: peter.c...@kernel.org CC: rog...@kernel.org CC: a-govindr...@ti.com CC: gre...@linuxfoundation.org CC: a...@kernel.org CC: dan...@iogearbox.net CC: and...@kernel.org CC: ka...@fb.com CC: songliubrav...@fb.com CC: y...@fb.com CC: john.fastab...@gmail.com CC: kpsi...@kernel.org CC: s...@kernel.org CC: a...@linux-foundation.org CC: thomas.hellst...@linux.intel.com CC: matthew.a...@intel.com CC: colin.k...@intel.com CC: ge...@linux-m68k.org CC: linux-bl...@vger.kernel.org CC: dri-de...@lists.freedesktop.org CC: intel-gfx@lists.freedesktop.org CC: l...@lists.freedesktop.org CC: linux-arm-...@vger.kernel.org CC: freedr...@lists.freedesktop.org CC: linux-...@vger.kernel.org CC: linux-arm-ker...@lists.infradead.org CC: linux-samsung-...@vger.kernel.org CC: linux-...@vger.kernel.org CC: b...@vger.kernel.org CC: linux...@kvack.org --- block/fops.c | 1 + drivers/gpu/drm/drm_gem_shmem_helper.c| 1 + drivers/gpu/drm/i915/gt/intel_gtt.c | 1 + drivers/gpu/drm/i915/i915_request.c | 1 + drivers/gpu/drm/lima/lima_device.c| 1 + drivers/gpu/drm/msm/msm_gem_shrinker.c| 1 + drivers/gpu/drm/ttm/ttm_tt.c | 1 + drivers/net/ethernet/huawei/hinic/hinic_sriov.c | 1 + drivers/net/ethernet/marvell/octeontx2/nic/otx2_ptp.c | 2 ++ drivers/pci/controller/dwc/pci-exynos.c | 1 + drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + drivers/usb/cdns3/host.c | 1 + include/linux/cacheinfo.h | 1 - include/linux/device/driver.h | 1 + include/linux/filter.h| 2 +- mm/damon/vaddr.c | 1 + mm/memory_hotplug.c | 1 + mm/swap_slots.c | 1 + 18 files changed, 18 insertions(+), 2 deletions(-) diff --git a/block/fops.c b/block/fops.c index ad732a36f9b3..3cb1e81929bc 100644 --- a/block/fops.c +++ b/block/fops.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "blk.h" static inline struct inode *bdev_file_inode(struct file *file) diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c index 7b9f69f21f1e..bca0de92802e 100644 --- a/drivers/gpu/drm/drm_gem_shmem_helper.c +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c @@ -9,6 +9,7 @@ #include #include #include +#include #ifdef CONFIG_X86 #include diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index 67d14afa6623..b67f620c3d93 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -6,6 +6,7 @@ #include /* fault-inject.h is not standalone! */ #include +#include #include "gem/i915_gem_lmem.h" #include "i915_trace.h" diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 820a1f38b271..89cccefeea63 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "gem/i915_gem_context.h" #include "gt/intel_breadcrumbs.h" diff --git a/drivers/gpu/drm/lima/lima_device.c b/drivers/gpu/drm/lima/lima_device.c index 65fdca366e41..f74f8048af8f 100644 --- a/drivers/gpu/drm/lima/lima_device.c +++ b/drivers/gpu/drm/lima/lima_device.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include diff --git a/drivers/gpu/drm/msm/msm_gem_shrinker.c b/drivers/gpu/drm/msm/msm_gem_shrinker.c index 4a1420b05e97..086dacf2f26a 100644 ---
Re: [Intel-gfx] [PATCH 0/2] Backport upstream commit e49a8b2cc852
Quoting Janusz Krzysztofik (2021-12-03 13:21:06) > diff --git a/0001-drm-i915-gt-Cleanup-partial-engine-discovery-failure.patch > b/0001-drm-i915-gt-Cleanup-partial-engine-discovery-failure.patch > index efadd30d8cad..62b0a41d4aa4 100644 > --- a/0001-drm-i915-gt-Cleanup-partial-engine-discovery-failure.patch > +++ b/0001-drm-i915-gt-Cleanup-partial-engine-discovery-failure.patch > @@ -8,20 +8,20 @@ some engines will be fully setup and some not. Those > incompletely setup > engines only have 'engine->release == NULL' and so will leak any of the > common objects allocated. > > -Incorporates some suggestions from Janusz for handling pinned context > -cleanup. > +v2: no longer incorporates suggestions from Janusz for handling pinned > +context cleanup since upstream version has been backported Noting the absence of something not explained just adds confusion. You've handled this appropriately as a standalone patch, no more needs to be said here (and the chunk doesn't even appear in the patch anymore). The covernote explained why this chunk disappears, so we have a story for the pile, which is a different story as that told by the series of individual patches. Reviewed-by: Chris Wilson -Chris
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915: Nuke {pipe, plane}_to_crtc_mapping[]
== Series Details ==
Series: series starting with [1/3] drm/i915: Nuke {pipe,
plane}_to_crtc_mapping[]
URL : https://patchwork.freedesktop.org/series/97541/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH 03/14] drm/i915: Get rid of the "sizes are 0 based" stuff
On Thu, 2021-12-02 at 13:56 +0200, Ville Syrjälä wrote:
> On Wed, Dec 01, 2021 at 05:18:54PM +, Souza, Jose wrote:
> > On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Replace the "sizes are 0 based" stuff with just straight
> > > up -1 where needed. Less confusing all around.
> > >
> > > Signed-off-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/i915/display/intel_sprite.c | 26 ---
> > > .../drm/i915/display/skl_universal_plane.c| 6 +
> > > 2 files changed, 6 insertions(+), 26 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > index 1b99a9501a45..2067a7bca4a8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > @@ -431,10 +431,6 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> > > u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
> > > unsigned long irqflags;
> > >
> > > - /* Sizes are 0 based */
> >
> > In my opinion at least this comment should stay, helps understand why the
> > -1.
>
> It's just normal practice for almost all such registers.
> We don't have similar comments elsewhere either. Also if
> the code already says "foo-1" then I don't see what extra
> the comment gets you.
Reviewed-by: José Roberto de Souza
>
> >
> > > - crtc_w--;
> > > - crtc_h--;
> > > -
> > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > >
> > > intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
> > > @@ -442,7 +438,7 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> > > intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
> > > (crtc_y << 16) | crtc_x);
> > > intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
> > > - (crtc_h << 16) | crtc_w);
> > > + ((crtc_h - 1) << 16) | (crtc_w - 1));
> > >
> > > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > > }
> > > @@ -866,21 +862,15 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
> > > u32 sprscale = 0;
> > > unsigned long irqflags;
> > >
> > > - /* Sizes are 0 based */
> > > - src_w--;
> > > - src_h--;
> > > - crtc_w--;
> > > - crtc_h--;
> > > -
> > > if (crtc_w != src_w || crtc_h != src_h)
> > > - sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
> > > + sprscale = SPRITE_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h -
> > > 1);
> > >
> > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > >
> > > intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
> > > plane_state->view.color_plane[0].mapping_stride);
> > > intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);
> > > - intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
> > > + intel_de_write_fw(dev_priv, SPRSIZE(pipe), ((crtc_h - 1) << 16) |
> > > (crtc_w - 1));
> > > if (IS_IVYBRIDGE(dev_priv))
> > > intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
> > >
> > > @@ -1208,21 +1198,15 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
> > > u32 dvsscale = 0;
> > > unsigned long irqflags;
> > >
> > > - /* Sizes are 0 based */
> > > - src_w--;
> > > - src_h--;
> > > - crtc_w--;
> > > - crtc_h--;
> > > -
> > > if (crtc_w != src_w || crtc_h != src_h)
> > > - dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
> > > + dvsscale = DVS_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
> > >
> > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > >
> > > intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
> > > plane_state->view.color_plane[0].mapping_stride);
> > > intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);
> > > - intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
> > > + intel_de_write_fw(dev_priv, DVSSIZE(pipe), ((crtc_h - 1) << 16) |
> > > (crtc_w - 1));
> > > intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
> > >
> > > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 9ff24a0e79b4..09948922016b 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -1022,10 +1022,6 @@ skl_program_plane_noarm(struct intel_plane *plane,
> > > u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> > > unsigned long irqflags;
> > >
> > > - /* Sizes are 0 based */
> > > - src_w--;
> > > - src_h--;
> > > -
> > > /* The scaler will handle the output position */
> > > if (plane_state->scaler_id >= 0) {
> > > crtc_x = 0;
> > > @@ -1045,7 +1041,7 @@ skl_program_plane_noarm(struct intel_plane *plane,
> > > intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
> > > (crtc_y << 16) |
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/4] drm/i915: Pass plane id to watermark calculation functions
== Series Details == Series: series starting with [1/4] drm/i915: Pass plane id to watermark calculation functions URL : https://patchwork.freedesktop.org/series/97536/ State : failure == Summary == Applying: drm/i915: Pass plane id to watermark calculation functions Applying: drm/i915: Introduce do_async_flip flag to intel_plane_state error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_atomic_plane.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0002 drm/i915: Introduce do_async_flip flag to intel_plane_state When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
