Re: [Intel-gfx] [v3 0/3] Enable pipe color support on D13 platform
> -Original Message- > From: Shankar, Uma > Sent: Tuesday, December 7, 2021 12:42 PM > To: intel-gfx@lists.freedesktop.org > Cc: ville.syrj...@linux.intel.com; Modem, Bhanuprakash > ; Shankar, Uma > Subject: [v3 0/3] Enable pipe color support on D13 platform > > Enable pipe color support for Display 13 platform. This series enables just > the 10bit > gamma mode. More advanced logarithmic gamma mode will be enable with the new > enhanced UAPI. It will be extended once the UAPI is agreed in community. This > series > just adds the basic support in the interim. > > v2: Addressed Ville's review comments. > > v3: Dropped gamma lut tests field (Ville) Pushed the changes to drm-intel-next. Thanks for the reviews. Regards, Uma Shankar > Uma Shankar (3): > drm/i915/xelpd: Enable Pipe color support for D13 platform > drm/i915/xelpd: Enable Pipe Degamma > drm/i915/xelpd: Add Pipe Color Lut caps to platform config > > drivers/gpu/drm/i915/display/intel_color.c | 23 +++--- > drivers/gpu/drm/i915/i915_pci.c| 5 - > 2 files changed, 24 insertions(+), 4 deletions(-) > > -- > 2.25.1
[Intel-gfx] [v3 3/3] drm/i915/xelpd: Add Pipe Color Lut caps to platform config
XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for
extended range. It has 511 entries for gamma with additional 2 entries
for extended range.
v2: Updated lut size for 10bit gamma, added lut_tests (Ville)
v3: Dropped the gamma lut tests fields (Ville)
Signed-off-by: Uma Shankar
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_pci.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0ba516838b02..6aaa7c644c9b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -938,7 +938,10 @@ static const struct intel_device_info adl_s_info = {
#define XE_LPD_FEATURES \
.abox_mask = GENMASK(1, 0),
\
- .color = { .degamma_lut_size = 0, .gamma_lut_size = 0 },
\
+ .color = { .degamma_lut_size = 128, .gamma_lut_size = 1024,
\
+ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |
\
+ DRM_COLOR_LUT_EQUAL_CHANNELS,
\
+ },
\
.dbuf.size = 4096,
\
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
\
BIT(DBUF_S4),
\
--
2.25.1
[Intel-gfx] [v3 2/3] drm/i915/xelpd: Enable Pipe Degamma
Enable Pipe Degamma for XE_LPD. Extend the legacy implementation
to incorparate the extended lut size for XE_LPD.
v2: Added a helper for degamma lut size (Ville)
Signed-off-by: Uma Shankar
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 42fe549ef6fe..de3ded1e327a 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -808,6 +808,14 @@ static void bdw_load_luts(const struct intel_crtc_state
*crtc_state)
}
}
+static int glk_degamma_lut_size(struct drm_i915_private *i915)
+{
+ if (DISPLAY_VER(i915) >= 13)
+ return 131;
+ else
+ return 35;
+}
+
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -827,8 +835,8 @@ static void glk_load_degamma_lut(const struct
intel_crtc_state *crtc_state)
for (i = 0; i < lut_size; i++) {
/*
-* First 33 entries represent range from 0 to 1.0
-* 34th and 35th entry will represent extended range
+* First lut_size entries represent range from 0 to 1.0
+* 3 additional lut entries will represent extended range
* inputs 3.0 and 7.0 respectively, currently clamped
* at 1.0. Since the precision is 16bit, the user
* value can be directly filled to register.
@@ -844,7 +852,7 @@ static void glk_load_degamma_lut(const struct
intel_crtc_state *crtc_state)
}
/* Clamp values > 1.0. */
- while (i++ < 35)
+ while (i++ < glk_degamma_lut_size(dev_priv))
intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
--
2.25.1
[Intel-gfx] [v3 1/3] drm/i915/xelpd: Enable Pipe color support for D13 platform
Enable pipe color support for Display 13 platforms. Currently
limit to just 10bit gamma and later extend it for logarithmic
gamma, once the new UAPI is agreed by community and implemented
by a userspace consumer.
v2: Updated dev_priv to i915 (Ville)
Signed-off-by: Uma Shankar
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 840f13b75492..42fe549ef6fe 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1574,6 +1574,8 @@ static int glk_color_check(struct intel_crtc_state
*crtc_state)
static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
u32 gamma_mode = 0;
if (crtc_state->hw.degamma_lut)
@@ -1586,6 +1588,13 @@ static u32 icl_gamma_mode(const struct intel_crtc_state
*crtc_state)
if (!crtc_state->hw.gamma_lut ||
crtc_state_is_legacy_gamma(crtc_state))
gamma_mode |= GAMMA_MODE_MODE_8BIT;
+ /*
+* Enable 10bit gamma for D13
+* ToDo: Extend to Logarithmic Gamma once the new UAPI
+* is acccepted and implemented by a userspace consumer
+*/
+ else if (DISPLAY_VER(i915) >= 13)
+ gamma_mode |= GAMMA_MODE_MODE_10BIT;
else
gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
--
2.25.1
[Intel-gfx] [v3 0/3] Enable pipe color support on D13 platform
Enable pipe color support for Display 13 platform. This series enables just the 10bit gamma mode. More advanced logarithmic gamma mode will be enable with the new enhanced UAPI. It will be extended once the UAPI is agreed in community. This series just adds the basic support in the interim. v2: Addressed Ville's review comments. v3: Dropped gamma lut tests field (Ville) Uma Shankar (3): drm/i915/xelpd: Enable Pipe color support for D13 platform drm/i915/xelpd: Enable Pipe Degamma drm/i915/xelpd: Add Pipe Color Lut caps to platform config drivers/gpu/drm/i915/display/intel_color.c | 23 +++--- drivers/gpu/drm/i915/i915_pci.c| 5 - 2 files changed, 24 insertions(+), 4 deletions(-) -- 2.25.1
Re: [Intel-gfx] [PATCH 4/4] drm/i915/guc: Don't go bang in GuC log if no GuC
On Fri, Dec 03, 2021 at 12:00:59PM -0800, Daniele Ceraolo Spurio wrote:
On 12/2/2021 4:33 PM, Lucas De Marchi wrote:
On Thu, Dec 02, 2021 at 04:06:23PM -0800, john.c.harri...@intel.com
wrote:
From: John Harrison
If the GuC has failed to load for any reason and then the user pokes
the debugfs GuC log interface, a BUG and/or null pointer deref can
occur. Don't let that happen.
Signed-off-by: John Harrison
Reviewed-by: Lucas De Marchi
Lucas De Marchi
Do we need a fixes tag? or is it ok to not have it for debugfs bugs?
for this file in debugfs, I don't think so, but I will let the
maintainers to chime in.
Lucas De Marchi
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
index 46026c2c1722..8fd068049376 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
@@ -31,7 +31,7 @@ static int guc_log_level_get(void *data, u64 *val)
{
struct intel_guc_log *log = data;
- if (!intel_guc_is_used(log_to_guc(log)))
+ if (!log->vma)
return -ENODEV;
*val = intel_guc_log_get_level(log);
@@ -43,7 +43,7 @@ static int guc_log_level_set(void *data, u64 val)
{
struct intel_guc_log *log = data;
- if (!intel_guc_is_used(log_to_guc(log)))
+ if (!log->vma)
return -ENODEV;
return intel_guc_log_set_level(log, val);
--
2.25.1
Re: [Intel-gfx] [PATCH v6 1/1] drm/i915: Introduce new macros for i915 PTE
On Mon, Dec 06, 2021 at 07:36:39PM -0800, Lucas De Marchi wrote:
On Mon, Dec 06, 2021 at 01:52:45PM -0800, Michael Cheng wrote:
Certain functions within i915 uses macros that are defined for
specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT
(Some architectures don't even have these macros defined, like ARM64).
Instead of re-using bits defined for the CPU, we should use bits
defined for i915. This patch introduces two new 64 bit macros,
GEN8_PAGE_PRESENT and GEN8_PAGE_RW, to check for bits 0 and 1 and, to
replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.
v2(Michael Cheng): Use GEN8_ instead of I915_
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++
drivers/gpu/drm/i915/gvt/gtt.c | 12 ++--
4 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 9966e9dc5218..95c02096a61b 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -18,7 +18,7 @@
static u64 gen8_pde_encode(const dma_addr_t addr,
const enum i915_cache_level level)
{
- u64 pde = addr | _PAGE_PRESENT | _PAGE_RW;
+ u64 pde = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
if (level != I915_CACHE_NONE)
pde |= PPAT_CACHED_PDE;
@@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags)
{
- gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
+ gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
if (unlikely(flags & PTE_READ_ONLY))
- pte &= ~_PAGE_RW;
+ pte &= ~GEN8_PAGE_RW;
if (flags & PTE_LM)
pte |= GEN12_PPGTT_PTE_LM;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 110d3944f9a2..cbc6d2b1fd9e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -209,7 +209,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags)
{
- gen8_pte_t pte = addr | _PAGE_PRESENT;
+ gen8_pte_t pte = addr | GEN8_PAGE_PRESENT;
if (flags & PTE_LM)
pte |= GEN12_GGTT_PTE_LM;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index dfeaef680aac..228fbfe33cb7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -39,6 +39,9 @@
#define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */
+#define GEN8_PAGE_PRESENT BIT_ULL(0)
+#define GEN8_PAGE_RW BIT_ULL(1)
ideally this would be together with other GEN8 defines, but this is
minor.
Reviewed-by: Lucas De Marchi
and pushed, thanks
Lucas De Marchi
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/xelpd: Add Pipe Color Lut caps to platform config
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, November 30, 2021 3:33 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org; Modem, Bhanuprakash
>
> Subject: Re: [PATCH v2 3/3] drm/i915/xelpd: Add Pipe Color Lut caps to
> platform
> config
>
> On Fri, Nov 26, 2021 at 01:57:50AM +0530, Uma Shankar wrote:
> > XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for
> > extended range. It has 511 entries for gamma with additional 2 entries
> > for extended range.
> >
> > v2: Updated lut size for 10bit gamma, added lut_tests (Ville)
> >
> > Signed-off-by: Uma Shankar
> > ---
> > drivers/gpu/drm/i915/i915_pci.c | 6 +-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c index f01cba4ec283..22eae330f075
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -938,7 +938,11 @@ static const struct intel_device_info adl_s_info
> > = {
> >
> > #define XE_LPD_FEATURES \
> > .abox_mask = GENMASK(1, 0),
> > \
> > - .color = { .degamma_lut_size = 0, .gamma_lut_size = 0 },
> > \
> > + .color = { .degamma_lut_size = 128, .gamma_lut_size = 1024,
> > \
> > + .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |
> \
> > + DRM_COLOR_LUT_EQUAL_CHANNELS,
> \
> > + .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING,
> \
>
> The 10bit mode doesn't interpolate so it can handle non-decreasing values
> just fine.
>
> With the gamma_lut_tests part dropped this is
Will drop this, refloat and merge.
Thanks Ville for the review and all the inputs.
Regards,
Uma Shankar
> Reviewed-by: Ville Syrjälä
>
> > + },
> > \
> > .dbuf.size = 4096,
> > \
> > .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
> \
> > BIT(DBUF_S4),
> > \
> > --
> > 2.25.1
>
> --
> Ville Syrjälä
> Intel
Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/xelpd: Enable Pipe Degamma
> -Original Message-
> From: Jani Nikula
> Sent: Tuesday, November 30, 2021 3:36 PM
> To: Ville Syrjälä
> Cc: Shankar, Uma ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/xelpd: Enable Pipe Degamma
>
> On Tue, 30 Nov 2021, Ville Syrjälä wrote:
> > On Mon, Nov 29, 2021 at 06:19:52PM +0200, Jani Nikula wrote:
> >> On Fri, 26 Nov 2021, Uma Shankar wrote:
> >> > Enable Pipe Degamma for XE_LPD. Extend the legacy implementation to
> >> > incorparate the extended lut size for XE_LPD.
> >> >
> >> > v2: Added a helper for degamma lut size (Ville)
> >> >
> >> > Signed-off-by: Uma Shankar
> >> > ---
> >> > drivers/gpu/drm/i915/display/intel_color.c | 14 +++---
> >> > 1 file changed, 11 insertions(+), 3 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> >> > b/drivers/gpu/drm/i915/display/intel_color.c
> >> > index 42fe549ef6fe..de3ded1e327a 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> >> > @@ -808,6 +808,14 @@ static void bdw_load_luts(const struct
> >> > intel_crtc_state
> *crtc_state)
> >> > }
> >> > }
> >> >
> >> > +static int glk_degamma_lut_size(struct drm_i915_private *i915) {
> >> > +if (DISPLAY_VER(i915) >= 13)
> >> > +return 131;
> >> > +else
> >> > +return 35;
> >> > +}
> >> > +
> >>
> >> Why do we have both a function with hardcoded values and device info
> >> members for this?
> >
> > The device info stuff just needs to get nuked. The size of the LUTs
> > depends on the gamma mode which we already select dynamically (and
> > if/when we get thre new uapi ironed out it'll become even more
> > dynamic), so trying to represent it with a single number in device
> > info is futile.
>
> Works for me, I just like to have the single point of truth instead of split
> all over the
> place. Not against adding this now, but let's not forget to follow up with the
> cleanup.
Yeah, device info may not be needed once we have the new UAPI's. Will clean it
up,
once we get that closed.
Thanks Jani and Ville for the review and feedbacks.
Regards,
Uma Shankar
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915/dmc: Change DMC FW size on ADL-P
On Mon, Dec 06, 2021 at 06:37:18PM -0800, Madhumitha Tolakanahalli Pradeep wrote: Increase the size of DMC on ADL-P to account for support of new features in the current/upcoming DMC versions. I was trying to find anything related on Bspec 49193 and 49194, but didn't find anything related to size. However I see adl-p 2.12 firmware is already above the previous 24kB. How did we ever loaded DMC? Yes, this is not the file size, but rather the payload size, but AFAICS the rest should account for less than 1k, so it doesn't make a real difference. For this specific change: Reviewed-by: Lucas De Marchi thanks Lucas De Marchi
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dmc: Change DMC FW size on ADL-P
== Series Details == Series: drm/i915/dmc: Change DMC FW size on ADL-P URL : https://patchwork.freedesktop.org/series/97638/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21770_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21770_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21770_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21770_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@mman: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/shard-skl8/igt@i915_selftest@l...@mman.html * igt@kms_async_flips@async-flip-with-page-flip-events: - shard-skl: [PASS][2] -> [FAIL][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-skl7/igt@kms_async_fl...@async-flip-with-page-flip-events.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/shard-skl4/igt@kms_async_fl...@async-flip-with-page-flip-events.html Known issues Here are the changes found in Patchwork_21770_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_capture@pi@vcs0: - shard-skl: NOTRUN -> [INCOMPLETE][4] ([i915#4547]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/shard-skl1/igt@gem_exec_capture@p...@vcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-kbl2/igt@gem_exec_fair@basic-pace-s...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-iclb7/igt@gem_exec_fair@basic-p...@bcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/shard-iclb1/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html - shard-kbl: [PASS][12] -> [SKIP][13] ([fdo#109271]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-kbl2/igt@gem_exec_fair@basic-p...@vcs1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-tglb1/igt@gem_exec_fair@basic-p...@vecs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/shard-tglb3/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/shard-kbl6/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/shard-apl3/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_lmem_swapping@smem-oom: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/shard-skl8/igt@gem_lmem_swapp...@smem-oom.html * igt@gem_mmap_gtt@coherency: - shard-tglb: NOTRUN -> [SKIP][19] ([fdo#111656]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/shard-tglb2/igt@gem_mmap_...@coherency.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][20] -> [DMESG-WARN][21] ([i915#180]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl2/igt@gem_workarou...@suspend-resume-context.html [21]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/pmu: Fix wakeref leak in PMU busyness during reset (rev2)
== Series Details == Series: drm/i915/pmu: Fix wakeref leak in PMU busyness during reset (rev2) URL : https://patchwork.freedesktop.org/series/97635/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21769_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21769_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21769_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21769_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@mman: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/shard-skl6/igt@i915_selftest@l...@mman.html Known issues Here are the changes found in Patchwork_21769_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_capture@pi@vcs0: - shard-skl: NOTRUN -> [INCOMPLETE][2] ([i915#4547]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/shard-skl1/igt@gem_exec_capture@p...@vcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][3] -> [FAIL][4] ([i915#2842]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-iclb2/igt@gem_exec_fair@basic-none-sh...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/shard-iclb4/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][5] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/shard-iclb1/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-kbl2/igt@gem_exec_fair@basic-p...@vecs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-tglb1/igt@gem_exec_fair@basic-p...@vecs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/shard-tglb2/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_whisper@basic-fds-forked: - shard-glk: [PASS][10] -> [DMESG-WARN][11] ([i915#118]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk7/igt@gem_exec_whis...@basic-fds-forked.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/shard-glk9/igt@gem_exec_whis...@basic-fds-forked.html * igt@gem_lmem_swapping@parallel-multi: - shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/shard-apl1/igt@gem_lmem_swapp...@parallel-multi.html * igt@gem_lmem_swapping@smem-oom: - shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/shard-skl6/igt@gem_lmem_swapp...@smem-oom.html * igt@gem_mmap_gtt@coherency: - shard-tglb: NOTRUN -> [SKIP][14] ([fdo#111656]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/shard-tglb1/igt@gem_mmap_...@coherency.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3323]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/shard-apl4/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gen7_exec_parse@cmd-crossing-page: - shard-tglb: NOTRUN -> [SKIP][16] ([fdo#109289]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/shard-tglb1/igt@gen7_exec_pa...@cmd-crossing-page.html - shard-iclb: NOTRUN -> [SKIP][17] ([fdo#109289]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/shard-iclb5/igt@gen7_exec_pa...@cmd-crossing-page.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][18] -> [FAIL][19] ([i915#454]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-iclb2/igt@i915_pm...@dc6-psr.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/shard-iclb4/igt@i915_pm...@dc6-psr.html * igt@i915_pm_sseu@full-enable: - shard-tglb: NOTRUN -> [SKIP][20] ([i915#4387]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/shard-tglb1/igt@i915_pm_s...@full-enable.html * igt@i915_selftest@live@gt_pm:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/pmu: Fix wakeref leak in PMU busyness during reset
== Series Details == Series: drm/i915/pmu: Fix wakeref leak in PMU busyness during reset URL : https://patchwork.freedesktop.org/series/97635/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21768_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21768_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21768_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21768_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@vma: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/shard-skl4/igt@i915_selftest@l...@vma.html Known issues Here are the changes found in Patchwork_21768_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_capture@pi@vcs0: - shard-skl: NOTRUN -> [INCOMPLETE][2] ([i915#4547]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/shard-skl8/igt@gem_exec_capture@p...@vcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-apl: [PASS][3] -> [FAIL][4] ([i915#2842]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl3/igt@gem_exec_fair@basic-n...@vcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/shard-apl6/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-iclb7/igt@gem_exec_fair@basic-p...@bcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/shard-iclb1/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-kbl2/igt@gem_exec_fair@basic-p...@vcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html - shard-kbl: [PASS][12] -> [SKIP][13] ([fdo#109271]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-kbl2/igt@gem_exec_fair@basic-p...@vcs1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-tglb1/igt@gem_exec_fair@basic-p...@vecs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/shard-tglb1/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_lmem_swapping@parallel-multi: - shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/shard-apl7/igt@gem_lmem_swapp...@parallel-multi.html * igt@gem_lmem_swapping@smem-oom: - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/shard-skl8/igt@gem_lmem_swapp...@smem-oom.html * igt@gem_mmap_gtt@coherency: - shard-tglb: NOTRUN -> [SKIP][18] ([fdo#111656]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/shard-tglb8/igt@gem_mmap_...@coherency.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3323]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/shard-apl1/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gen7_exec_parse@cmd-crossing-page: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#109289]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/shard-tglb8/igt@gen7_exec_pa...@cmd-crossing-page.html - shard-iclb: NOTRUN -> [SKIP][21] ([fdo#109289]) [21]:
Re: [Intel-gfx] [PATCH v6 1/1] drm/i915: Introduce new macros for i915 PTE
On Mon, Dec 06, 2021 at 01:52:45PM -0800, Michael Cheng wrote:
Certain functions within i915 uses macros that are defined for
specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT
(Some architectures don't even have these macros defined, like ARM64).
Instead of re-using bits defined for the CPU, we should use bits
defined for i915. This patch introduces two new 64 bit macros,
GEN8_PAGE_PRESENT and GEN8_PAGE_RW, to check for bits 0 and 1 and, to
replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.
v2(Michael Cheng): Use GEN8_ instead of I915_
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++
drivers/gpu/drm/i915/gvt/gtt.c | 12 ++--
4 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 9966e9dc5218..95c02096a61b 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -18,7 +18,7 @@
static u64 gen8_pde_encode(const dma_addr_t addr,
const enum i915_cache_level level)
{
- u64 pde = addr | _PAGE_PRESENT | _PAGE_RW;
+ u64 pde = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
if (level != I915_CACHE_NONE)
pde |= PPAT_CACHED_PDE;
@@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags)
{
- gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
+ gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
if (unlikely(flags & PTE_READ_ONLY))
- pte &= ~_PAGE_RW;
+ pte &= ~GEN8_PAGE_RW;
if (flags & PTE_LM)
pte |= GEN12_PPGTT_PTE_LM;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 110d3944f9a2..cbc6d2b1fd9e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -209,7 +209,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags)
{
- gen8_pte_t pte = addr | _PAGE_PRESENT;
+ gen8_pte_t pte = addr | GEN8_PAGE_PRESENT;
if (flags & PTE_LM)
pte |= GEN12_GGTT_PTE_LM;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index dfeaef680aac..228fbfe33cb7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -39,6 +39,9 @@
#define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */
+#define GEN8_PAGE_PRESENT BIT_ULL(0)
+#define GEN8_PAGE_RW BIT_ULL(1)
ideally this would be together with other GEN8 defines, but this is
minor.
Reviewed-by: Lucas De Marchi
Lucas De Marchi
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dmc: Change DMC FW size on ADL-P
== Series Details == Series: drm/i915/dmc: Change DMC FW size on ADL-P URL : https://patchwork.freedesktop.org/series/97638/ State : success == Summary == CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21770 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/index.html Participating hosts (43 -> 31) -- Missing(12): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-kbl-x1275 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21770 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@i915_selftest@live@gt_engines: - fi-rkl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#4432]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html * igt@kms_chamelium@hdmi-edid-read: - fi-bsw-kefka: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/fi-bsw-kefka/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [PASS][6] -> [DMESG-WARN][7] ([i915#295]) +12 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html * igt@runner@aborted: - fi-rkl-guc: NOTRUN -> [FAIL][8] ([i915#3928] / [i915#4312]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/fi-rkl-guc/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s0: - fi-bsw-kefka: [INCOMPLETE][9] ([i915#2539]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-1115g4: [FAIL][11] ([i915#1888]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick:[DMESG-FAIL][13] ([i915#2927] / [i915#3428]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][15] ([i915#4269]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21770/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539 [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927 [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432 Build changes - * Linux: CI_DRM_10965 -> Patchwork_21770 CI-20190529: 20190529 CI_DRM_10965: e9dedc5d0907d96371774cacca10160a167c5cd2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6300: f69bd65fa9f72b7d5e5a5a22981f16d034334761 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21770: 4fc1192bcc63db5f3beab609667a7b40ae176e54 @
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftests (rev2)
== Series Details == Series: drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftests (rev2) URL : https://patchwork.freedesktop.org/series/97577/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21767_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21767_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21767_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21767_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@coherency: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/shard-skl8/igt@i915_selftest@l...@coherency.html Known issues Here are the changes found in Patchwork_21767_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-apl: ([PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [FAIL][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51]) ([i915#4386]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl1/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl1/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl2/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl2/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl2/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl2/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl3/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl3/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl3/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl4/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl6/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl6/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl6/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl7/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl7/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl7/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl7/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl8/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl8/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl8/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl8/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/shard-apl7/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/shard-apl8/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/shard-apl8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/shard-apl8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/shard-apl8/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/shard-apl1/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/shard-apl1/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/shard-apl1/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/shard-apl1/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/shard-apl2/boot.html
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Fix wakeref leak in PMU busyness during reset (rev2)
== Series Details ==
Series: drm/i915/pmu: Fix wakeref leak in PMU busyness during reset (rev2)
URL : https://patchwork.freedesktop.org/series/97635/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21769
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/index.html
Participating hosts (43 -> 31)
--
Missing(12): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan
bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-kbl-x1275 fi-bdw-samus bat-jsl-2
bat-jsl-1
Known issues
Here are the changes found in Patchwork_21769 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html
* igt@amdgpu/amd_basic@semaphore:
- fi-bsw-nick:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html
* igt@i915_selftest@live@gt_engines:
- fi-rkl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#4432])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-bsw-kefka: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/fi-bsw-kefka/igt@kms_chamel...@hdmi-edid-read.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][6] ([i915#2426] / [i915#4312])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/fi-bdw-5557u/igt@run...@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][7] ([i915#3928] / [i915#4312])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/fi-rkl-guc/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s0:
- fi-bsw-kefka: [INCOMPLETE][8] ([i915#2539]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][10] ([i915#1888]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick:[DMESG-FAIL][12] ([i915#2927] / [i915#3428]) ->
[PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432
[i915#4449]: https://gitlab.freedesktop.org/drm/intel/issues/4449
Build changes
-
* Linux: CI_DRM_10965 -> Patchwork_21769
CI-20190529: 20190529
CI_DRM_10965: e9dedc5d0907d96371774cacca10160a167c5cd2 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6300: f69bd65fa9f72b7d5e5a5a22981f16d034334761 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21769: a71e851181bdcf625d70c498d9374f39e4f0df06 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a71e851181bd drm/i915/pmu: Fix wakeref leak in PMU busyness during reset
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21769/index.html
[Intel-gfx] [PATCH] drm/i915/dmc: Change DMC FW size on ADL-P
Increase the size of DMC on ADL-P to account for support of
new features in the current/upcoming DMC versions.
Signed-off-by: Madhumitha Tolakanahalli Pradeep
---
drivers/gpu/drm/i915/display/intel_dmc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 2dc9d632969d..0cab18f972d1 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -45,6 +45,8 @@
#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define GEN13_DMC_MAX_FW_SIZE 0x2
+
#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 12)
#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 12)
MODULE_FIRMWARE(ADLP_DMC_PATH);
@@ -682,7 +684,7 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
if (IS_ALDERLAKE_P(dev_priv)) {
dmc->fw_path = ADLP_DMC_PATH;
dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
- dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+ dmc->max_fw_size = GEN13_DMC_MAX_FW_SIZE;
} else if (IS_ALDERLAKE_S(dev_priv)) {
dmc->fw_path = ADLS_DMC_PATH;
dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
--
2.33.1
Re: [Intel-gfx] [PATCH] drm/i915/pmu: Fix wakeref leak in PMU busyness during reset
On Mon, Dec 06, 2021 at 05:30:43PM -0800, Dixit, Ashutosh wrote:
On Mon, 06 Dec 2021 16:45:42 -0800, Umesh Nerlige Ramappa wrote:
GuC PMU busyness gets gt wakeref if awake, but fails to release the
wakeref if a reset is in progress. Release the wakeref if it was
acquried successfully.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 1f9d4fde421f..a243304a2db1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1181,6 +1181,7 @@ static ktime_t guc_engine_busyness(struct intel_engine_cs
*engine, ktime_t *now)
struct intel_gt *gt = engine->gt;
struct intel_guc *guc = >uc.guc;
u64 total, gt_stamp_saved;
+ intel_wakeref_t wakeref;
Should be bool.
unsigned long flags;
u32 reset_count;
bool in_reset;
@@ -1206,18 +1207,21 @@ static ktime_t guc_engine_busyness(struct
intel_engine_cs *engine, ktime_t *now)
* start_gt_clk is derived from GuC state. To get a consistent
* view of activity, we query the GuC state only if gt is awake.
*/
- if (intel_gt_pm_get_if_awake(gt) && !in_reset) {
Also how about just switch them around:
if (!in_reset && intel_gt_pm_get_if_awake(gt))
Then you don't need any other changes I think.
:) that looks much simpler, I posted this in v2.
Thanks
Umesh
+ wakeref = intel_gt_pm_get_if_awake(gt);
+ if (wakeref && !in_reset) {
stats_saved = *stats;
gt_stamp_saved = guc->timestamp.gt_stamp;
guc_update_engine_gt_clks(engine);
guc_update_pm_timestamp(guc, engine, now);
- intel_gt_pm_put_async(gt);
if (i915_reset_count(gpu_error) != reset_count) {
*stats = stats_saved;
guc->timestamp.gt_stamp = gt_stamp_saved;
}
}
+ if (wakeref)
+ intel_gt_pm_put_async(gt);
+
total = intel_gt_clock_interval_to_ns(gt, stats->total_gt_clks);
if (stats->running) {
u64 clk = guc->timestamp.gt_stamp - stats->start_gt_clk;
--
2.20.1
[Intel-gfx] [PATCH] drm/i915/pmu: Fix wakeref leak in PMU busyness during reset
GuC PMU busyness gets gt wakeref if awake, but fails to release the
wakeref if a reset is in progress. Release the wakeref if it was
acquried successfully.
v2: Simplify the fix (Ashutosh)
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 1f9d4fde421f..9739da6f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1206,7 +1206,7 @@ static ktime_t guc_engine_busyness(struct intel_engine_cs
*engine, ktime_t *now)
* start_gt_clk is derived from GuC state. To get a consistent
* view of activity, we query the GuC state only if gt is awake.
*/
- if (intel_gt_pm_get_if_awake(gt) && !in_reset) {
+ if (!in_reset && intel_gt_pm_get_if_awake(gt)) {
stats_saved = *stats;
gt_stamp_saved = guc->timestamp.gt_stamp;
guc_update_engine_gt_clks(engine);
--
2.20.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Fix wakeref leak in PMU busyness during reset
== Series Details ==
Series: drm/i915/pmu: Fix wakeref leak in PMU busyness during reset
URL : https://patchwork.freedesktop.org/series/97635/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21768
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/index.html
Participating hosts (43 -> 31)
--
Missing(12): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan
bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-kbl-x1275 fi-bdw-samus bat-jsl-2
bat-jsl-1
Known issues
Here are the changes found in Patchwork_21768 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html
* igt@amdgpu/amd_basic@semaphore:
- fi-bsw-nick:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html
* igt@gem_exec_suspend@basic-s3:
- fi-bdw-5557u: [PASS][3] -> [INCOMPLETE][4] ([i915#146])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@gt_engines:
- fi-rkl-guc: [PASS][5] -> [INCOMPLETE][6] ([i915#4432])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-bsw-kefka: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/fi-bsw-kefka/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][8] -> [DMESG-WARN][9] ([i915#295]) +12 similar
issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: [PASS][10] -> [INCOMPLETE][11] ([i915#198])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
* igt@runner@aborted:
- fi-rkl-guc: NOTRUN -> [FAIL][12] ([i915#3928] / [i915#4312])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/fi-rkl-guc/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s0:
- fi-bsw-kefka: [INCOMPLETE][13] ([i915#2539]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][15] ([i915#1888]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick:[DMESG-FAIL][17] ([i915#2927] / [i915#3428]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21768/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3428]:
Re: [Intel-gfx] [PATCH] drm/i915/pmu: Fix wakeref leak in PMU busyness during reset
On Mon, 06 Dec 2021 16:45:42 -0800, Umesh Nerlige Ramappa wrote:
>
> GuC PMU busyness gets gt wakeref if awake, but fails to release the
> wakeref if a reset is in progress. Release the wakeref if it was
> acquried successfully.
>
> Signed-off-by: Umesh Nerlige Ramappa
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 1f9d4fde421f..a243304a2db1 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1181,6 +1181,7 @@ static ktime_t guc_engine_busyness(struct
> intel_engine_cs *engine, ktime_t *now)
> struct intel_gt *gt = engine->gt;
> struct intel_guc *guc = >uc.guc;
> u64 total, gt_stamp_saved;
> + intel_wakeref_t wakeref;
Should be bool.
> unsigned long flags;
> u32 reset_count;
> bool in_reset;
> @@ -1206,18 +1207,21 @@ static ktime_t guc_engine_busyness(struct
> intel_engine_cs *engine, ktime_t *now)
>* start_gt_clk is derived from GuC state. To get a consistent
>* view of activity, we query the GuC state only if gt is awake.
>*/
> - if (intel_gt_pm_get_if_awake(gt) && !in_reset) {
Also how about just switch them around:
if (!in_reset && intel_gt_pm_get_if_awake(gt))
Then you don't need any other changes I think.
> + wakeref = intel_gt_pm_get_if_awake(gt);
> + if (wakeref && !in_reset) {
> stats_saved = *stats;
> gt_stamp_saved = guc->timestamp.gt_stamp;
> guc_update_engine_gt_clks(engine);
> guc_update_pm_timestamp(guc, engine, now);
> - intel_gt_pm_put_async(gt);
> if (i915_reset_count(gpu_error) != reset_count) {
> *stats = stats_saved;
> guc->timestamp.gt_stamp = gt_stamp_saved;
> }
> }
>
> + if (wakeref)
> + intel_gt_pm_put_async(gt);
> +
> total = intel_gt_clock_interval_to_ns(gt, stats->total_gt_clks);
> if (stats->running) {
> u64 clk = guc->timestamp.gt_stamp - stats->start_gt_clk;
> --
> 2.20.1
>
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftests (rev2)
== Series Details == Series: drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftests (rev2) URL : https://patchwork.freedesktop.org/series/97577/ State : success == Summary == CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21767 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/index.html Participating hosts (43 -> 31) -- Missing(12): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-kbl-x1275 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21767 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_exec_suspend@basic-s0: - fi-ilk-650: [PASS][3] -> [DMESG-WARN][4] ([i915#164]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-ilk-650/igt@gem_exec_susp...@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/fi-ilk-650/igt@gem_exec_susp...@basic-s0.html * igt@kms_chamelium@hdmi-edid-read: - fi-bsw-kefka: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/fi-bsw-kefka/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-bdw-5557u: [PASS][6] -> [INCOMPLETE][7] ([i915#146]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bdw-5557u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/fi-bdw-5557u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html * igt@kms_psr@primary_page_flip: - fi-skl-6600u: [PASS][8] -> [FAIL][9] ([i915#4547]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-skl-6600u/igt@kms_psr@primary_page_flip.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/fi-skl-6600u/igt@kms_psr@primary_page_flip.html * igt@runner@aborted: - fi-skl-6600u: NOTRUN -> [FAIL][10] ([i915#3363] / [i915#4312]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/fi-skl-6600u/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s0: - fi-bsw-kefka: [INCOMPLETE][11] ([i915#2539]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-1115g4: [FAIL][13] ([i915#1888]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick:[DMESG-FAIL][15] ([i915#2927] / [i915#3428]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21767/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#164]: https://gitlab.freedesktop.org/drm/intel/issues/164 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539 [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 Build changes - * Linux: CI_DRM_10965 -> Patchwork_21767 CI-20190529: 20190529 CI_DRM_10965: e9dedc5d0907d96371774cacca10160a167c5cd2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6300: f69bd65fa9f72b7d5e5a5a22981f16d034334761 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21767: 9bb7b34ac5164caf62638ac6e62ccb50ffbf4d9b @ git://anongit.freedesktop.org/gfx-ci/linux
[Intel-gfx] [PATCH] drm/i915/pmu: Fix wakeref leak in PMU busyness during reset
GuC PMU busyness gets gt wakeref if awake, but fails to release the
wakeref if a reset is in progress. Release the wakeref if it was
acquried successfully.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 1f9d4fde421f..a243304a2db1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1181,6 +1181,7 @@ static ktime_t guc_engine_busyness(struct intel_engine_cs
*engine, ktime_t *now)
struct intel_gt *gt = engine->gt;
struct intel_guc *guc = >uc.guc;
u64 total, gt_stamp_saved;
+ intel_wakeref_t wakeref;
unsigned long flags;
u32 reset_count;
bool in_reset;
@@ -1206,18 +1207,21 @@ static ktime_t guc_engine_busyness(struct
intel_engine_cs *engine, ktime_t *now)
* start_gt_clk is derived from GuC state. To get a consistent
* view of activity, we query the GuC state only if gt is awake.
*/
- if (intel_gt_pm_get_if_awake(gt) && !in_reset) {
+ wakeref = intel_gt_pm_get_if_awake(gt);
+ if (wakeref && !in_reset) {
stats_saved = *stats;
gt_stamp_saved = guc->timestamp.gt_stamp;
guc_update_engine_gt_clks(engine);
guc_update_pm_timestamp(guc, engine, now);
- intel_gt_pm_put_async(gt);
if (i915_reset_count(gpu_error) != reset_count) {
*stats = stats_saved;
guc->timestamp.gt_stamp = gt_stamp_saved;
}
}
+ if (wakeref)
+ intel_gt_pm_put_async(gt);
+
total = intel_gt_clock_interval_to_ns(gt, stats->total_gt_clks);
if (stats->running) {
u64 clk = guc->timestamp.gt_stamp - stats->start_gt_clk;
--
2.20.1
[Intel-gfx] [PATCH] drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftests
Follow up on commit 5e076529e265 ("drm/i915/selftests: Increase timeout in
i915_gem_contexts selftests")
So we went from 200 msec to 1sec in that commit, and now we are going to
10sec as timeout.
Signed-off-by: Bruce Chang
Reviewed-by: Matthew Brost
Cc: John Harrison
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index b32f7fed2d9c..21b71568cd5f 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -88,7 +88,7 @@ static int live_nop_switch(void *arg)
rq = i915_request_get(this);
i915_request_add(this);
}
- if (i915_request_wait(rq, 0, HZ) < 0) {
+ if (i915_request_wait(rq, 0, 10 * HZ) < 0) {
pr_err("Failed to populated %d contexts\n", nctx);
intel_gt_set_wedged(>gt);
i915_request_put(rq);
--
2.21.3
[Intel-gfx] ✓ Fi.CI.IGT: success for Introduce new i915 macros for checking PTEs (rev7)
== Series Details == Series: Introduce new i915 macros for checking PTEs (rev7) URL : https://patchwork.freedesktop.org/series/96679/ State : success == Summary == CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21766_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_21766_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-snb: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [FAIL][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#4338]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb7/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb7/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb7/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb7/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb7/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb6/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb6/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb6/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb6/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb5/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb5/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb5/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb4/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb4/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb4/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb4/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb2/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb2/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-snb2/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb7/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb7/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb7/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb7/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb6/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb6/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb6/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb6/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb5/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb5/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb5/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb5/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb5/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb4/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb4/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/shard-snb4/boot.html [44]:
[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce new i915 macros for checking PTEs (rev7)
== Series Details == Series: Introduce new i915 macros for checking PTEs (rev7) URL : https://patchwork.freedesktop.org/series/96679/ State : success == Summary == CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21766 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/index.html Participating hosts (43 -> 31) -- Missing(12): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-kbl-x1275 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21766 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [PASS][3] -> [INCOMPLETE][4] ([i915#198]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html * igt@kms_chamelium@hdmi-edid-read: - fi-bsw-kefka: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/fi-bsw-kefka/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_frontbuffer_tracking@basic: - fi-cfl-8109u: [PASS][6] -> [DMESG-FAIL][7] ([i915#295]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [PASS][8] -> [DMESG-WARN][9] ([i915#295]) +10 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][10] ([i915#2426] / [i915#4312]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/fi-bdw-5557u/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s0: - fi-bsw-kefka: [INCOMPLETE][11] ([i915#2539]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-1115g4: [FAIL][13] ([i915#1888]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick:[DMESG-FAIL][15] ([i915#2927] / [i915#3428]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21766/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539 [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927 [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 Build changes - * Linux: CI_DRM_10965 -> Patchwork_21766 CI-20190529: 20190529 CI_DRM_10965: e9dedc5d0907d96371774cacca10160a167c5cd2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6300: f69bd65fa9f72b7d5e5a5a22981f16d034334761 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21766: fd5845562313775ef6f6ffacced3f330f04ea6bf @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == fd5845562313
Re: [Intel-gfx] ✗ Fi.CI.DOCS: warning for Update to GuC version 69.0.0
On 06.12.2021 20:29, John Harrison wrote: > Michal, do you know what this is complaining about? broken links definitions, fix below Michal diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h index d09d6a5bb63b..6aa3cf7172f7 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h @@ -40,23 +40,23 @@ * Refers to 64 bit Global Gfx address of H2G `CT Buffer`_. * Should be above WOPCM address but below APIC base address for native mode. * - * _`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR : 0x0903 + * _`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR` : 0x0903 * Refers to 64 bit Global Gfx address of H2G `CTB Descriptor`_. * Should be above WOPCM address but below APIC base address for native mode. * - * _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE : 0x0904 + * _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE` : 0x0904 * Refers to size of H2G `CT Buffer`_ in bytes. * Should be a multiple of 4K. * - * _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR : 0x0905 + * _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR` : 0x0905 * Refers to 64 bit Global Gfx address of G2H `CT Buffer`_. * Should be above WOPCM address but below APIC base address for native mode. * - * _GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR : 0x0906 + * _`GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR` : 0x0906 * Refers to 64 bit Global Gfx address of G2H `CTB Descriptor`_. * Should be above WOPCM address but below APIC base address for native mode. * - * _GUC_KLV_SELF_CFG_G2H_CTB_SIZE : 0x0907 + * _`GUC_KLV_SELF_CFG_G2H_CTB_SIZE` : 0x0907 * Refers to size of G2H `CT Buffer`_ in bytes. * Should be a multiple of 4K. */ > > John. > > On 12/3/2021 14:27, Patchwork wrote: >> == Series Details == >> >> Series: Update to GuC version 69.0.0 >> URL : https://patchwork.freedesktop.org/series/97564/ >> State : warning >> >> == Summary == >> >> $ make htmldocs 2>&1 > /dev/null | grep i915 >> /home/cidrm/kernel/Documentation/gpu/i915:542: >> ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h:44: WARNING: Inline >> target start-string without end-string. >> /home/cidrm/kernel/Documentation/gpu/i915:542: >> ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h:48: WARNING: Inline >> target start-string without end-string. >> /home/cidrm/kernel/Documentation/gpu/i915:542: >> ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h:52: WARNING: Inline >> target start-string without end-string. >> >> >
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce new i915 macros for checking PTEs (rev7)
== Series Details == Series: Introduce new i915 macros for checking PTEs (rev7) URL : https://patchwork.freedesktop.org/series/96679/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH 1/5] drm/i915/uc: Allow platforms to have GuC but not HuC
On 12/3/2021 10:33 AM, john.c.harri...@intel.com wrote:
From: John Harrison
It is possible for platforms to require GuC but not HuC firmware.
Also, the firmware versions for GuC and HuC advance independently. So
split the macros up to allow the lists to be maintained separately.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 93
1 file changed, 63 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 3aa87be4f2e4..a7788ce50736 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -48,22 +48,39 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
* Note that RKL and ADL-S have the same GuC/HuC device ID's and use the same
* firmware as TGL.
*/
-#define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
- fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3), huc_def(tgl, 7, 9, 3)) \
- fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
- fw_def(DG1, 0, guc_def(dg1, 62, 0, 0), huc_def(dg1, 7, 9, 3)) \
- fw_def(ROCKETLAKE, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
- fw_def(TIGERLAKE, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
- fw_def(JASPERLAKE, 0, guc_def(ehl, 62, 0, 0), huc_def(ehl, 9, 0, 0)) \
- fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0), huc_def(ehl, 9, 0, 0)) \
- fw_def(ICELAKE, 0, guc_def(icl, 62, 0, 0), huc_def(icl, 9, 0, 0)) \
- fw_def(COMETLAKE, 5, guc_def(cml, 62, 0, 0), huc_def(cml, 4, 0, 0)) \
- fw_def(COMETLAKE, 0, guc_def(kbl, 62, 0, 0), huc_def(kbl, 4, 0, 0)) \
- fw_def(COFFEELAKE, 0, guc_def(kbl, 62, 0, 0), huc_def(kbl, 4, 0, 0)) \
- fw_def(GEMINILAKE, 0, guc_def(glk, 62, 0, 0), huc_def(glk, 4, 0, 0)) \
- fw_def(KABYLAKE,0, guc_def(kbl, 62, 0, 0), huc_def(kbl, 4, 0, 0)) \
- fw_def(BROXTON, 0, guc_def(bxt, 62, 0, 0), huc_def(bxt, 2, 0, 0)) \
- fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0), huc_def(skl, 2, 0, 0))
+#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \
+ fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3)) \
+ fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0)) \
+ fw_def(DG1, 0, guc_def(dg1, 62, 0, 0)) \
+ fw_def(ROCKETLAKE, 0, guc_def(tgl, 62, 0, 0)) \
+ fw_def(TIGERLAKE,0, guc_def(tgl, 62, 0, 0)) \
+ fw_def(JASPERLAKE, 0, guc_def(ehl, 62, 0, 0)) \
+ fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0)) \
+ fw_def(ICELAKE, 0, guc_def(icl, 62, 0, 0)) \
+ fw_def(COMETLAKE,5, guc_def(cml, 62, 0, 0)) \
+ fw_def(COMETLAKE,0, guc_def(kbl, 62, 0, 0)) \
+ fw_def(COFFEELAKE, 0, guc_def(kbl, 62, 0, 0)) \
+ fw_def(GEMINILAKE, 0, guc_def(glk, 62, 0, 0)) \
+ fw_def(KABYLAKE, 0, guc_def(kbl, 62, 0, 0)) \
+ fw_def(BROXTON, 0, guc_def(bxt, 62, 0, 0)) \
+ fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0))
+
+#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \
+ fw_def(ALDERLAKE_P, 0, huc_def(tgl, 7, 9, 3)) \
+ fw_def(ALDERLAKE_S, 0, huc_def(tgl, 7, 9, 3)) \
+ fw_def(DG1, 0, huc_def(dg1, 7, 9, 3)) \
+ fw_def(ROCKETLAKE, 0, huc_def(tgl, 7, 9, 3)) \
+ fw_def(TIGERLAKE,0, huc_def(tgl, 7, 9, 3)) \
+ fw_def(JASPERLAKE, 0, huc_def(ehl, 9, 0, 0)) \
+ fw_def(ELKHARTLAKE, 0, huc_def(ehl, 9, 0, 0)) \
+ fw_def(ICELAKE, 0, huc_def(icl, 9, 0, 0)) \
+ fw_def(COMETLAKE,5, huc_def(cml, 4, 0, 0)) \
+ fw_def(COMETLAKE,0, huc_def(kbl, 4, 0, 0)) \
+ fw_def(COFFEELAKE, 0, huc_def(kbl, 4, 0, 0)) \
+ fw_def(GEMINILAKE, 0, huc_def(glk, 4, 0, 0)) \
+ fw_def(KABYLAKE, 0, huc_def(kbl, 4, 0, 0)) \
+ fw_def(BROXTON, 0, huc_def(bxt, 2, 0, 0)) \
+ fw_def(SKYLAKE, 0, huc_def(skl, 2, 0, 0))
#define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \
"i915/" \
@@ -79,11 +96,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
__MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_)
/* All blobs need to be declared via MODULE_FIRMWARE() */
-#define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \
- MODULE_FIRMWARE(guc_); \
- MODULE_FIRMWARE(huc_);
+#define INTEL_UC_MODULE_FW(platform_, revid_, uc_) \
+ MODULE_FIRMWARE(uc_);
-INTEL_UC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH, MAKE_HUC_FW_PATH)
+INTEL_GUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH)
+INTEL_HUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_HUC_FW_PATH)
/* The below structs and macros are used to iterate across the list of blobs */
struct __packed uc_fw_blob {
@@ -106,31 +123,47 @@ struct __packed uc_fw_blob {
struct __packed uc_fw_platform_requirement {
enum
[Intel-gfx] [PATCH v6 0/1] Introduce new i915 macros for checking PTEs
This series is to introduce new macros generic to i915 for checking 0 and 1 bits, instead on relying on whats defined by the mmu, since it could be different or non-exisitent between different platforms. v2: Corrected sender's email. v3: Corrected spelling error. v4: Clean up a few other macros that are checking 0 and 1 bits. Thanks to Lucas De Marchi for suggesting these cleanups. v5: Remove changes to GEN6_PTE_VALID/GEN6_PDE_VALID and BYT_PTE_WRITEABLE. Those macros checks for 32bit PTEs, and our new macro is checking for 64bit. v6: Use GEN8_* instead of I915_* Michael Cheng (1): drm/i915: Introduce new macros for i915 PTE drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++--- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++ drivers/gpu/drm/i915/gvt/gtt.c | 12 ++-- 4 files changed, 13 insertions(+), 10 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH v6 1/1] drm/i915: Introduce new macros for i915 PTE
Certain functions within i915 uses macros that are defined for
specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT
(Some architectures don't even have these macros defined, like ARM64).
Instead of re-using bits defined for the CPU, we should use bits
defined for i915. This patch introduces two new 64 bit macros,
GEN8_PAGE_PRESENT and GEN8_PAGE_RW, to check for bits 0 and 1 and, to
replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.
v2(Michael Cheng): Use GEN8_ instead of I915_
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++
drivers/gpu/drm/i915/gvt/gtt.c | 12 ++--
4 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 9966e9dc5218..95c02096a61b 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -18,7 +18,7 @@
static u64 gen8_pde_encode(const dma_addr_t addr,
const enum i915_cache_level level)
{
- u64 pde = addr | _PAGE_PRESENT | _PAGE_RW;
+ u64 pde = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
if (level != I915_CACHE_NONE)
pde |= PPAT_CACHED_PDE;
@@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags)
{
- gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
+ gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
if (unlikely(flags & PTE_READ_ONLY))
- pte &= ~_PAGE_RW;
+ pte &= ~GEN8_PAGE_RW;
if (flags & PTE_LM)
pte |= GEN12_PPGTT_PTE_LM;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 110d3944f9a2..cbc6d2b1fd9e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -209,7 +209,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags)
{
- gen8_pte_t pte = addr | _PAGE_PRESENT;
+ gen8_pte_t pte = addr | GEN8_PAGE_PRESENT;
if (flags & PTE_LM)
pte |= GEN12_GGTT_PTE_LM;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index dfeaef680aac..228fbfe33cb7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -39,6 +39,9 @@
#define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */
+#define GEN8_PAGE_PRESENT BIT_ULL(0)
+#define GEN8_PAGE_RW BIT_ULL(1)
+
#define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
#define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
#define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 53d0cb327539..99d1781fa5f0 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -446,17 +446,17 @@ static bool gen8_gtt_test_present(struct
intel_gvt_gtt_entry *e)
|| e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
return (e->val64 != 0);
else
- return (e->val64 & _PAGE_PRESENT);
+ return (e->val64 & GEN8_PAGE_PRESENT);
}
static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
{
- e->val64 &= ~_PAGE_PRESENT;
+ e->val64 &= ~GEN8_PAGE_PRESENT;
}
static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
{
- e->val64 |= _PAGE_PRESENT;
+ e->val64 |= GEN8_PAGE_PRESENT;
}
static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
@@ -2439,7 +2439,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
/* The entry parameters like present/writeable/cache type
* set to the same as i915's scratch page tree.
*/
- se.val64 |= _PAGE_PRESENT | _PAGE_RW;
+ se.val64 |= GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
if (type == GTT_TYPE_PPGTT_PDE_PT)
se.val64 |= PPAT_CACHED;
@@ -2896,7 +2896,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt)
offset = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
for (idx = 0; idx < num_low; idx++) {
pte = mm->ggtt_mm.host_ggtt_aperture[idx];
- if (pte & _PAGE_PRESENT)
+ if (pte & GEN8_PAGE_PRESENT)
write_pte64(vgpu->gvt->gt->ggtt, offset + idx,
pte);
}
@@ -2904,7 +2904,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt)
offset = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
for (idx = 0; idx < num_hi; idx++) {
pte = mm->ggtt_mm.host_ggtt_hidden[idx];
- if (pte & _PAGE_PRESENT)
[Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce new i915 macros for checking PTEs (rev6)
== Series Details == Series: Introduce new i915 macros for checking PTEs (rev6) URL : https://patchwork.freedesktop.org/series/96679/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21765_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21765_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21765_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21765_full: ### IGT changes ### Possible regressions * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-apl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl4/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/shard-apl1/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html Known issues Here are the changes found in Patchwork_21765_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_capture@pi@bcs0: - shard-skl: NOTRUN -> [INCOMPLETE][3] ([i915#4547]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/shard-skl8/igt@gem_exec_capture@p...@bcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][4] -> [FAIL][5] ([i915#2842]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-iclb2/igt@gem_exec_fair@basic-none-sh...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/shard-iclb2/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-kbl6/igt@gem_exec_fair@basic-n...@vecs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/shard-kbl3/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-tglb1/igt@gem_exec_fair@basic-p...@vecs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/shard-tglb5/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_whisper@basic-fds-forked: - shard-glk: [PASS][12] -> [DMESG-WARN][13] ([i915#118]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk7/igt@gem_exec_whis...@basic-fds-forked.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/shard-glk4/igt@gem_exec_whis...@basic-fds-forked.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/shard-kbl6/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-multi: - shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/shard-apl4/igt@gem_lmem_swapp...@parallel-multi.html * igt@gem_lmem_swapping@smem-oom: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/shard-skl10/igt@gem_lmem_swapp...@smem-oom.html * igt@gem_mmap_gtt@coherency: - shard-tglb: NOTRUN -> [SKIP][17] ([fdo#111656]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/shard-tglb1/igt@gem_mmap_...@coherency.html * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][18] -> [DMESG-WARN][19] ([i915#180]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl6/igt@gem_soft...@noreloc-s3.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/shard-apl3/igt@gem_soft...@noreloc-s3.html * igt@gen7_exec_parse@cmd-crossing-page: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#109289]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/shard-tglb1/igt@gen7_exec_pa...@cmd-crossing-page.html - shard-iclb: NOTRUN -> [SKIP][21] ([fdo#109289]) [21]:
Re: [Intel-gfx] [PATCH] drm/i915/execlists: Weak parallel submission support for execlists
On 11/11/2021 13:20, Matthew Brost wrote:
A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
execlists. Doing as little as possible to support this interface for
execlists - basically just passing submit fences between each request
generated and virtual engines are not allowed. This is on par with what
is there for the existing (hopefully soon deprecated) bonding interface.
We perma-pin these execlists contexts to align with GuC implementation.
v2:
(John Harrison)
- Drop siblings array as num_siblings must be 1
v3:
(John Harrison)
- Drop single submission
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +++--
drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
.../drm/i915/gt/intel_execlists_submission.c | 40 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -
5 files changed, 50 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ebd775cb1661c..d7bf6c8f70b7b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -570,10 +570,6 @@ set_proto_ctx_engines_parallel_submit(struct
i915_user_extension __user *base,
struct intel_engine_cs **siblings = NULL;
intel_engine_mask_t prev_mask;
- /* FIXME: This is NIY for execlists */
- if (!(intel_uc_uses_guc_submission(>gt.uc)))
- return -ENODEV;
-
if (get_user(slot, >engine_index))
return -EFAULT;
@@ -583,6 +579,12 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
if (get_user(num_siblings, >num_siblings))
return -EFAULT;
+ if (!intel_uc_uses_guc_submission(>gt.uc) && num_siblings != 1) {
+ drm_dbg(>drm, "Only 1 sibling (%d) supported in non-GuC
mode\n",
+ num_siblings);
+ return -EINVAL;
+ }
+
if (slot >= set->num_engines) {
drm_dbg(>drm, "Invalid placement value, %d >= %d\n",
slot, set->num_engines);
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 5634d14052bc9..1bec92e1d8e63 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -79,7 +79,8 @@ static int intel_context_active_acquire(struct intel_context
*ce)
__i915_active_acquire(>active);
- if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine))
+ if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine) ||
+ intel_context_is_parallel(ce))
return 0;
/* Preallocate tracking nodes */
@@ -563,7 +564,6 @@ void intel_context_bind_parent_child(struct intel_context
*parent,
* Callers responsibility to validate that this function is used
* correctly but we use GEM_BUG_ON here ensure that they do.
*/
- GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
GEM_BUG_ON(intel_context_is_pinned(parent));
GEM_BUG_ON(intel_context_is_child(parent));
GEM_BUG_ON(intel_context_is_pinned(child));
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index ca03880fa7e49..5fd49ee47096d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2598,6 +2598,45 @@ static void execlists_context_cancel_request(struct
intel_context *ce,
current->comm);
}
+static struct intel_context *
+execlists_create_parallel(struct intel_engine_cs **engines,
+ unsigned int num_siblings,
+ unsigned int width)
+{
+ struct intel_context *parent = NULL, *ce, *err;
+ int i;
+
+ GEM_BUG_ON(num_siblings != 1);
+
+ for (i = 0; i < width; ++i) {
+ ce = intel_context_create(engines[i]);
+ if (!ce) {
+ err = ERR_PTR(-ENOMEM);
intel_context_create already checks for null and returns -ENOMEM. This
needs to check for IS_ERR(ce).
+ goto unwind;
+ }
+
+ if (i == 0)
+ parent = ce;
+ else
+ intel_context_bind_parent_child(parent, ce);
+ }
+
+ parent->parallel.fence_context = dma_fence_context_alloc(1);
+
+ intel_context_set_nopreempt(parent);
+ for_each_child(parent, ce) {
+ intel_context_set_nopreempt(ce);
+ intel_context_set_single_submission(ce);
I thought the single submission thing wasn't wanted anymore?
+ }
+
+ return parent;
+
+unwind:
+ if (parent)
+ intel_context_put(parent);
+ return err;
+}
+
Re: [Intel-gfx] ✗ Fi.CI.DOCS: warning for Update to GuC version 69.0.0
Michal, do you know what this is complaining about? John. On 12/3/2021 14:27, Patchwork wrote: == Series Details == Series: Update to GuC version 69.0.0 URL : https://patchwork.freedesktop.org/series/97564/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915:542: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h:44: WARNING: Inline target start-string without end-string. /home/cidrm/kernel/Documentation/gpu/i915:542: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h:48: WARNING: Inline target start-string without end-string. /home/cidrm/kernel/Documentation/gpu/i915:542: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h:52: WARNING: Inline target start-string without end-string.
Re: [Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to drm-tip/drm-tip v5.16-rc4 next-20211206]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a012-20211130
(https://download.01.org/0day-ci/archive/20211207/202112070356.mqaltrgq-...@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project
4b553297ef3ee4dc2119d5429adf3072e90fac38)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
#
https://github.com/0day-ci/linux/commit/ec767426b169205cc023d38ea477e9bd38b93284
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
git checkout ec767426b169205cc023d38ea477e9bd38b93284
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1
O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gvt/display.c:188:41: error: use of undeclared
>> identifier 'DISPLAY_PLANE_ENABLE'
vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &=
~DISPLAY_PLANE_ENABLE;
^
drivers/gpu/drm/i915/gvt/display.c:499:40: error: use of undeclared
identifier 'DISPLAY_PLANE_ENABLE'
vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
^
2 errors generated.
--
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:86:7: error: use of undeclared
>> identifier 'DISPPLANE_8BPP'
case DISPPLANE_8BPP:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:89:7: error: use of undeclared
>> identifier 'DISPPLANE_BGRX565'
case DISPPLANE_BGRX565:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:92:7: error: use of undeclared
>> identifier 'DISPPLANE_BGRX888'
case DISPPLANE_BGRX888:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:95:7: error: use of undeclared
>> identifier 'DISPPLANE_RGBX101010'
case DISPPLANE_RGBX101010:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:98:7: error: use of undeclared
>> identifier 'DISPPLANE_BGRX101010'
case DISPPLANE_BGRX101010:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:101:7: error: use of undeclared
>> identifier 'DISPPLANE_RGBX888'
case DISPPLANE_RGBX888:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:214:28: error: use of undeclared
>> identifier 'DISPLAY_PLANE_ENABLE'
plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
^
drivers/gpu/drm/i915/gvt/fb_decoder.c:221:10: error: use of undeclared
identifier 'PLANE_CTL_FORMAT_MASK'
val & PLANE_CTL_FORMAT_MASK,
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:234:24: error: use of undeclared
>> identifier 'DISPPLANE_TILED'
plane->tiled = val & DISPPLANE_TILED;
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:235:33: error: use of undeclared
>> identifier 'DISPPLANE_PIXFORMAT_MASK'
fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
^
drivers/gpu/drm/i915/gvt/fb_decoder.c:430:21: error: use of undeclared
identifier 'SPRITE_YUV_BYTE_ORDER_MASK'
yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
^
11 errors generated.
vim +/DISPLAY_PLANE_ENABLE +188 drivers/gpu/drm/i915/gvt/display.c
04d348ae3f0aea Zhi Wang 2016-04-25 169
04d348ae3f0aea Zhi Wang 2016-04-25 170 static void
emulate_monitor_status_change(struct intel_vgpu *vgpu)
04d348ae3f0aea Zhi Wang 2016-04-25 171 {
a61ac1e75105a0 Chris Wilson 2020-03-06 172struct drm_i915_private
*dev_priv = vgpu->gvt->gt->i915;
65eff272330c72 Xiong Zhang 2018-03-28 173int pipe;
65eff272330c72 Xiong Zhang 2018-03-28 174
72bad997287693 Colin Xu 2018-06-11 175if (IS_BROXTON(dev_priv)) {
a5a8ef937cfa79 Colin Xu 2020-11-09 176
[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce new i915 macros for checking PTEs (rev6)
== Series Details ==
Series: Introduce new i915 macros for checking PTEs (rev6)
URL : https://patchwork.freedesktop.org/series/96679/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21765
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/index.html
Participating hosts (43 -> 31)
--
Missing(12): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan
bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-kbl-x1275 fi-bdw-samus bat-jsl-2
bat-jsl-1
Known issues
Here are the changes found in Patchwork_21765 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html
* igt@amdgpu/amd_basic@semaphore:
- fi-bsw-nick:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html
* igt@gem_exec_suspend@basic-s3:
- fi-bdw-5557u: [PASS][3] -> [INCOMPLETE][4] ([i915#146])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-bsw-kefka: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/fi-bsw-kefka/igt@kms_chamel...@hdmi-edid-read.html
Possible fixes
* igt@gem_exec_suspend@basic-s0:
- fi-bsw-kefka: [INCOMPLETE][6] ([i915#2539]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][8] ([i915#1888]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick:[DMESG-FAIL][10] ([i915#2927] / [i915#3428]) ->
[PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][12] ([i915#4269]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
Build changes
-
* Linux: CI_DRM_10965 -> Patchwork_21765
CI-20190529: 20190529
CI_DRM_10965: e9dedc5d0907d96371774cacca10160a167c5cd2 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6300: f69bd65fa9f72b7d5e5a5a22981f16d034334761 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21765: 77858b6bdbfdee96c6ddbfa75b065e71acfbc743 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
77858b6bdbfd drm/i915: Introduce new macros for i915 PTE
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21765/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce new i915 macros for checking PTEs (rev6)
== Series Details == Series: Introduce new i915 macros for checking PTEs (rev6) URL : https://patchwork.freedesktop.org/series/96679/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH v2 03/16] drm/i915: Remove pages_mutex and intel_gtt->vma_ops.set/clear_pages members, v2.
On Mon, 29 Nov 2021 at 13:57, Maarten Lankhorst
wrote:
>
> Big delta, but boils down to moving set_pages to i915_vma.c, and removing
> the special handling, all callers use the defaults anyway. We only remap
> in ggtt, so default case will fall through.
>
> Because we still don't require locking in i915_vma_unpin(), handle this by
> using xchg in get_pages(), as it's locked with obj->mutex, and cmpxchg in
> unpin, which only fails if we race a against a new pin.
>
> Changes since v1:
> - aliasing gtt sets ZERO_SIZE_PTR, not -ENODEV, remove special case
> from __i915_vma_get_pages(). (Matt)
>
> Signed-off-by: Maarten Lankhorst
> +static int
> +__i915_vma_get_pages(struct i915_vma *vma)
> +{
> + struct sg_table *pages;
> + int ret;
> +
> + /*
> +* The vma->pages are only valid within the lifespan of the borrowed
> +* obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so
> +* must be the vma->pages. A simple rule is that vma->pages must only
> +* be accessed when the obj->mm.pages are pinned.
> +*/
> + GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj));
> +
> + switch (vma->ggtt_view.type) {
> + default:
> + GEM_BUG_ON(vma->ggtt_view.type);
> + fallthrough;
> + case I915_GGTT_VIEW_NORMAL:
> + pages = vma->obj->mm.pages;
> + break;
> +
> + case I915_GGTT_VIEW_ROTATED:
> + pages =
> + intel_rotate_pages(>ggtt_view.rotated, vma->obj);
> + break;
> +
> + case I915_GGTT_VIEW_REMAPPED:
> + pages =
> + intel_remap_pages(>ggtt_view.remapped, vma->obj);
> + break;
> +
> + case I915_GGTT_VIEW_PARTIAL:
> + pages = intel_partial_pages(>ggtt_view, vma->obj);
> + break;
> + }
> +
> + ret = 0;
> + if (IS_ERR(pages)) {
> + ret = PTR_ERR(pages);
> + pages = NULL;
> + drm_err(>vm->i915->drm,
> + "Failed to get pages for VMA view type %u (%d)!\n",
> + vma->ggtt_view.type, ret);
> + }
> +
> + pages = xchg(>pages, pages);
> +
> + /* did we race against a put_pages? */
> + if (pages && pages != vma->obj->mm.pages) {
> + sg_free_table(vma->pages);
> + kfree(vma->pages);
So should this one rather be:
sg_free_table(pages);
kfree(pages);
Or am I missing something?
Re: [Intel-gfx] [PATCH v2 03/16] drm/i915: Remove pages_mutex and intel_gtt->vma_ops.set/clear_pages members, v2.
On Mon, 6 Dec 2021 at 15:18, Maarten Lankhorst
wrote:
>
> On 06-12-2021 14:13, Matthew Auld wrote:
> > On Mon, 29 Nov 2021 at 13:57, Maarten Lankhorst
> > wrote:
> >> Big delta, but boils down to moving set_pages to i915_vma.c, and removing
> >> the special handling, all callers use the defaults anyway. We only remap
> >> in ggtt, so default case will fall through.
> >>
> >> Because we still don't require locking in i915_vma_unpin(), handle this by
> >> using xchg in get_pages(), as it's locked with obj->mutex, and cmpxchg in
> >> unpin, which only fails if we race a against a new pin.
> >>
> >> Changes since v1:
> >> - aliasing gtt sets ZERO_SIZE_PTR, not -ENODEV, remove special case
> >> from __i915_vma_get_pages(). (Matt)
> >>
> >> Signed-off-by: Maarten Lankhorst
> >> ---
> >> drivers/gpu/drm/i915/display/intel_dpt.c | 2 -
> >> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 15 -
> >> drivers/gpu/drm/i915/gt/intel_ggtt.c | 403
> >> drivers/gpu/drm/i915/gt/intel_gtt.c | 13 -
> >> drivers/gpu/drm/i915/gt/intel_gtt.h | 7 -
> >> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 12 -
> >> drivers/gpu/drm/i915/i915_vma.c | 444 --
> >> drivers/gpu/drm/i915/i915_vma.h | 3 +
> >> drivers/gpu/drm/i915/i915_vma_types.h | 1 -
> >> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 +-
> >> drivers/gpu/drm/i915/selftests/mock_gtt.c | 4 -
> >> 11 files changed, 424 insertions(+), 492 deletions(-)
> >>
> >
> >
> >> }
> >> @@ -854,18 +1233,22 @@ static int vma_get_pages(struct i915_vma *vma)
> >> static void __vma_put_pages(struct i915_vma *vma, unsigned int count)
> >> {
> >> /* We allocate under vma_get_pages, so beware the shrinker */
> >> - mutex_lock_nested(>pages_mutex, SINGLE_DEPTH_NESTING);
> >> + struct sg_table *pages = READ_ONCE(vma->pages);
> >> +
> >> GEM_BUG_ON(atomic_read(>pages_count) < count);
> >> +
> >> if (atomic_sub_return(count, >pages_count) == 0) {
> > Does this emit a barrier? Or can the READ_ONCE(vma->pages) be moved
> > past this, and does that matter?
>
> It's not that tricky, and only there because we still have to support
> unlocked until patch 13, patch 15 removes it.
>
> From the kernel doc:
>
> - RMW operations that have a return value are fully ordered;
>
> - RMW operations that are conditional are unordered on FAILURE,
>otherwise the above rules apply.
>
> so READ_ONCE followed by a bunch of stuff that only happens when cmpxchg is
> succesful, is ok.
>
> At the beginning of vma_put_pages(), we hold at least 1 reference to
> vma->pages, and we assume vma->pages is set to something sane.
>
> We use READ_ONCE to read vma->pages before decreasing refcount on
> vma->pages_count, after which we attempt to clear vma->pages.
>
> HOWEVER, as we are not guaranteed to hold the lock, we are careful. New pages
> may have been set by __i915_vma_get_pages(), using xchg.
>
> In that case, we fail, and _get_pages() cleans up instead.
>
> After that, we drop the reference to the object's page pin, which we needed
> for the pages != vma->obj->mm.pages comparison.
Ok, I can buy that.
>
> >> - vma->ops->clear_pages(vma);
> >> - GEM_BUG_ON(vma->pages);
> >> + if (pages == cmpxchg(>pages, pages, NULL) &&
> > try_cmpxchg? Also can pages be NULL here?
>
> cmpxchg is correct here. We don't need to loop, and only need to try once.
> The only time we can fail, will happen after at least one get_pages() call,
> and that would have otherwise freed it for us.
>
> > As an aside, is it somehow possible to re-order the series or
> > something to avoid introducing the transient lockless trickery here? I
> > know by the end of the series this all gets removed, but still just
> > slightly worried here.
>
> The locked version would actually be identical in this case.
>
> I removed the locking because it didn't add anything. The same ops would be
> required, only with additional locking for something that is using atomic ops
> for a refcount anyway..
>
>
> >> + pages != vma->obj->mm.pages) {
> >> + sg_free_table(pages);
> >> + kfree(pages);
> >> + }
> >>
> >> i915_gem_object_unpin_pages(vma->obj);
> >> }
> >> - mutex_unlock(>pages_mutex);
> >> }
>
>
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/4] drm/i915/migrate: don't check the scratch page
== Series Details == Series: series starting with [1/4] drm/i915/migrate: don't check the scratch page URL : https://patchwork.freedesktop.org/series/97610/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21762_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21762_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21762_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21762_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@vma: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/shard-skl1/igt@i915_selftest@l...@vma.html Known issues Here are the changes found in Patchwork_21762_full that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@read_all_entries: - shard-kbl: [PASS][2] -> [DMESG-WARN][3] ([i915#203] / [i915#262] / [i915#62] / [i915#92]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-kbl7/igt@debugfs_test@read_all_entries.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/shard-kbl3/igt@debugfs_test@read_all_entries.html * igt@gem_eio@in-flight-contexts-10ms: - shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-tglb3/igt@gem_...@in-flight-contexts-10ms.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/shard-tglb8/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_exec_capture@pi@bcs0: - shard-skl: NOTRUN -> [INCOMPLETE][6] ([i915#4547]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/shard-skl10/igt@gem_exec_capture@p...@bcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-iclb7/igt@gem_exec_fair@basic-p...@bcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/shard-iclb2/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-kbl2/igt@gem_exec_fair@basic-p...@vcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-tglb1/igt@gem_exec_fair@basic-p...@vecs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/shard-tglb2/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/shard-kbl3/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/shard-apl6/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_lmem_swapping@smem-oom: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/shard-skl1/igt@gem_lmem_swapp...@smem-oom.html * igt@gem_mmap_gtt@coherency: - shard-tglb: NOTRUN -> [SKIP][19] ([fdo#111656]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/shard-tglb1/igt@gem_mmap_...@coherency.html * igt@gen7_exec_parse@cmd-crossing-page: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#109289]) [20]:
Re: [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal plane bits
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to drm-tip/drm-tip v5.16-rc4 next-20211206]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a012-20211130
(https://download.01.org/0day-ci/archive/20211206/202112062346.pub0kczk-...@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project
4b553297ef3ee4dc2119d5429adf3072e90fac38)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
#
https://github.com/0day-ci/linux/commit/50180d495a061c64528e2348a684037f5dc26e2e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
git checkout 50180d495a061c64528e2348a684037f5dc26e2e
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1
O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:221:10: error: use of undeclared
>> identifier 'PLANE_CTL_FORMAT_MASK'
val & PLANE_CTL_FORMAT_MASK,
^
drivers/gpu/drm/i915/gvt/fb_decoder.c:430:21: error: use of undeclared
identifier 'SPRITE_YUV_BYTE_ORDER_MASK'
yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
^
2 errors generated.
vim +/PLANE_CTL_FORMAT_MASK +221 drivers/gpu/drm/i915/gvt/fb_decoder.c
9f31d1063b434c Tina Zhang 2017-11-23 192
9f31d1063b434c Tina Zhang 2017-11-23 193 /**
9f31d1063b434c Tina Zhang 2017-11-23 194 *
intel_vgpu_decode_primary_plane - Decode primary plane
9f31d1063b434c Tina Zhang 2017-11-23 195 * @vgpu: input vgpu
9f31d1063b434c Tina Zhang 2017-11-23 196 * @plane: primary plane to
save decoded info
9f31d1063b434c Tina Zhang 2017-11-23 197 * This function is called
for decoding plane
9f31d1063b434c Tina Zhang 2017-11-23 198 *
9f31d1063b434c Tina Zhang 2017-11-23 199 * Returns:
9f31d1063b434c Tina Zhang 2017-11-23 200 * 0 on success, non-zero
if failed.
9f31d1063b434c Tina Zhang 2017-11-23 201 */
9f31d1063b434c Tina Zhang 2017-11-23 202 int
intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
9f31d1063b434c Tina Zhang 2017-11-23 203 struct
intel_vgpu_primary_plane_format *plane)
9f31d1063b434c Tina Zhang 2017-11-23 204 {
a61ac1e75105a0 Chris Wilson2020-03-06 205 struct drm_i915_private
*dev_priv = vgpu->gvt->gt->i915;
9f31d1063b434c Tina Zhang 2017-11-23 206 u32 val, fmt;
9f31d1063b434c Tina Zhang 2017-11-23 207 int pipe;
9f31d1063b434c Tina Zhang 2017-11-23 208
9f31d1063b434c Tina Zhang 2017-11-23 209 pipe =
get_active_pipe(vgpu);
9f31d1063b434c Tina Zhang 2017-11-23 210 if (pipe >=
I915_MAX_PIPES)
9f31d1063b434c Tina Zhang 2017-11-23 211 return -ENODEV;
9f31d1063b434c Tina Zhang 2017-11-23 212
90551a1296d4db Zhenyu Wang 2017-12-19 213 val = vgpu_vreg_t(vgpu,
DSPCNTR(pipe));
9f31d1063b434c Tina Zhang 2017-11-23 214 plane->enabled = !!(val
& DISPLAY_PLANE_ENABLE);
9f31d1063b434c Tina Zhang 2017-11-23 215 if (!plane->enabled)
9f31d1063b434c Tina Zhang 2017-11-23 216 return -ENODEV;
9f31d1063b434c Tina Zhang 2017-11-23 217
d8d123128c4872 Lucas De Marchi 2021-06-03 218 if
(GRAPHICS_VER(dev_priv) >= 9) {
b244ffa15c8b1a Zhenyu Wang 2018-08-30 219 plane->tiled =
val & PLANE_CTL_TILED_MASK;
9f31d1063b434c Tina Zhang 2017-11-23 220 fmt =
skl_format_to_drm(
9f31d1063b434c Tina Zhang 2017-11-23 @221 val &
PLANE_CTL_FORMAT_MASK,
9f31d1063b434c Tina Zhang 2017-11-23 222 val &
PLANE_CTL_ORDER_RGBX,
9f31d1063b434c Tina Zhang 2017-11-23 223 val &
PLANE_CTL_ALPHA_MASK,
9f31d1063b434c Tina Zhang 2017-11-23 224 val &
PLANE_CTL_YUV422_ORDER_MASK);
461bd6227ede27 Gustavo
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Use hw_engine_masks as reset_domains (rev2)
== Series Details == Series: drm/i915/gt: Use hw_engine_masks as reset_domains (rev2) URL : https://patchwork.freedesktop.org/series/97543/ State : success == Summary == CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21761_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_21761_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_capture@pi@bcs0: - shard-skl: NOTRUN -> [INCOMPLETE][1] ([i915#4547]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-skl10/igt@gem_exec_capture@p...@bcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][2] -> [FAIL][3] ([i915#2842]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-iclb2/igt@gem_exec_fair@basic-none-sh...@rcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][4] -> [FAIL][5] ([i915#2842]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-tglb1/igt@gem_exec_fair@basic-p...@vecs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-tglb1/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_whisper@basic-fds-forked: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#118]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk7/igt@gem_exec_whis...@basic-fds-forked.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-glk4/igt@gem_exec_whis...@basic-fds-forked.html * igt@gem_lmem_swapping@parallel-multi: - shard-kbl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-kbl4/igt@gem_lmem_swapp...@parallel-multi.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-apl4/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_mmap_gtt@coherency: - shard-tglb: NOTRUN -> [SKIP][13] ([fdo#111656]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-tglb5/igt@gem_mmap_...@coherency.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#3323]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-apl7/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-apl2/igt@gem_workarou...@suspend-resume-context.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-apl1/igt@gem_workarou...@suspend-resume-context.html * igt@gen7_exec_parse@cmd-crossing-page: - shard-tglb: NOTRUN -> [SKIP][17] ([fdo#109289]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-tglb5/igt@gen7_exec_pa...@cmd-crossing-page.html - shard-iclb: NOTRUN -> [SKIP][18] ([fdo#109289]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-iclb3/igt@gen7_exec_pa...@cmd-crossing-page.html * igt@i915_pm_sseu@full-enable: - shard-tglb: NOTRUN -> [SKIP][19] ([i915#4387]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-tglb5/igt@i915_pm_s...@full-enable.html * igt@kms_big_fb@yf-tiled-32bpp-rotate-180: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#111615]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-tglb5/igt@kms_big...@yf-tiled-32bpp-rotate-180.html * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs: - shard-iclb: NOTRUN -> [SKIP][21] ([fdo#109278] / [i915#3886]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/shard-iclb3/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc: -
Re: [Intel-gfx] [PATCH v2 03/16] drm/i915: Remove pages_mutex and intel_gtt->vma_ops.set/clear_pages members, v2.
On 06-12-2021 14:13, Matthew Auld wrote:
> On Mon, 29 Nov 2021 at 13:57, Maarten Lankhorst
> wrote:
>> Big delta, but boils down to moving set_pages to i915_vma.c, and removing
>> the special handling, all callers use the defaults anyway. We only remap
>> in ggtt, so default case will fall through.
>>
>> Because we still don't require locking in i915_vma_unpin(), handle this by
>> using xchg in get_pages(), as it's locked with obj->mutex, and cmpxchg in
>> unpin, which only fails if we race a against a new pin.
>>
>> Changes since v1:
>> - aliasing gtt sets ZERO_SIZE_PTR, not -ENODEV, remove special case
>> from __i915_vma_get_pages(). (Matt)
>>
>> Signed-off-by: Maarten Lankhorst
>> ---
>> drivers/gpu/drm/i915/display/intel_dpt.c | 2 -
>> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 15 -
>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 403
>> drivers/gpu/drm/i915/gt/intel_gtt.c | 13 -
>> drivers/gpu/drm/i915/gt/intel_gtt.h | 7 -
>> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 12 -
>> drivers/gpu/drm/i915/i915_vma.c | 444 --
>> drivers/gpu/drm/i915/i915_vma.h | 3 +
>> drivers/gpu/drm/i915/i915_vma_types.h | 1 -
>> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 +-
>> drivers/gpu/drm/i915/selftests/mock_gtt.c | 4 -
>> 11 files changed, 424 insertions(+), 492 deletions(-)
>>
>
>
>> }
>> @@ -854,18 +1233,22 @@ static int vma_get_pages(struct i915_vma *vma)
>> static void __vma_put_pages(struct i915_vma *vma, unsigned int count)
>> {
>> /* We allocate under vma_get_pages, so beware the shrinker */
>> - mutex_lock_nested(>pages_mutex, SINGLE_DEPTH_NESTING);
>> + struct sg_table *pages = READ_ONCE(vma->pages);
>> +
>> GEM_BUG_ON(atomic_read(>pages_count) < count);
>> +
>> if (atomic_sub_return(count, >pages_count) == 0) {
> Does this emit a barrier? Or can the READ_ONCE(vma->pages) be moved
> past this, and does that matter?
It's not that tricky, and only there because we still have to support unlocked
until patch 13, patch 15 removes it.
>From the kernel doc:
- RMW operations that have a return value are fully ordered;
- RMW operations that are conditional are unordered on FAILURE,
otherwise the above rules apply.
so READ_ONCE followed by a bunch of stuff that only happens when cmpxchg is
succesful, is ok.
At the beginning of vma_put_pages(), we hold at least 1 reference to
vma->pages, and we assume vma->pages is set to something sane.
We use READ_ONCE to read vma->pages before decreasing refcount on
vma->pages_count, after which we attempt to clear vma->pages.
HOWEVER, as we are not guaranteed to hold the lock, we are careful. New pages
may have been set by __i915_vma_get_pages(), using xchg.
In that case, we fail, and _get_pages() cleans up instead.
After that, we drop the reference to the object's page pin, which we needed for
the pages != vma->obj->mm.pages comparison.
>> - vma->ops->clear_pages(vma);
>> - GEM_BUG_ON(vma->pages);
>> + if (pages == cmpxchg(>pages, pages, NULL) &&
> try_cmpxchg? Also can pages be NULL here?
cmpxchg is correct here. We don't need to loop, and only need to try once. The
only time we can fail, will happen after at least one get_pages() call, and
that would have otherwise freed it for us.
> As an aside, is it somehow possible to re-order the series or
> something to avoid introducing the transient lockless trickery here? I
> know by the end of the series this all gets removed, but still just
> slightly worried here.
The locked version would actually be identical in this case.
I removed the locking because it didn't add anything. The same ops would be
required, only with additional locking for something that is using atomic ops
for a refcount anyway..
>> + pages != vma->obj->mm.pages) {
>> + sg_free_table(pages);
>> + kfree(pages);
>> + }
>>
>> i915_gem_object_unpin_pages(vma->obj);
>> }
>> - mutex_unlock(>pages_mutex);
>> }
Re: [Intel-gfx] [PATCH v3 0/8] DG2 accelerated migration/clearing support
On 06/12/2021 14:49, Daniel Stone wrote: Hi Matthew, On Mon, 6 Dec 2021 at 13:32, Matthew Auld wrote: Enable accelerated moves and clearing on DG2. On such HW we have minimum page size restrictions when accessing LMEM from the GTT, where we now have to use 64K GTT pages or larger. With the ppGTT the page-table also has a slightly different layout from past generations when using the 64K GTT mode(which is still enabled on via some PDE bit), where it is now compacted down to 32 qword entries. Note that on discrete the paging structures must also be placed in LMEM, and we need to able to modify them via the GTT itself(see patch 7), which is one of the complications here. The series needs to be applied on top of the DG2 enabling branch: https://cgit.freedesktop.org/~ramaling/linux/log/?h=dg2_enabling_ww49.3 What are the changes to the v1/v2? Yeah, I should have added that somewhere. Sorry. v2: Add missing cover letter v3: - Add some r-b tags - Drop the GTT_MAPPABLE approach. We can instead simply pass along the required size/alignment using alloc_pt(). Cheers, Daniel
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Use GEM_BUG_ON for obj ptr NULL check
== Series Details == Series: drm/i915: Use GEM_BUG_ON for obj ptr NULL check URL : https://patchwork.freedesktop.org/series/97605/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21760_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21760_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21760_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21760_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@vma: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21760/shard-skl1/igt@i915_selftest@l...@vma.html * igt@kms_cursor_legacy@pipe-a-single-move: - shard-tglb: [PASS][2] -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-tglb1/igt@kms_cursor_leg...@pipe-a-single-move.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21760/shard-tglb6/igt@kms_cursor_leg...@pipe-a-single-move.html Warnings * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp: - shard-iclb: [SKIP][4] ([fdo#110892]) -> [INCOMPLETE][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-iclb8/igt@i915_pm_...@dpms-mode-unset-non-lpsp.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21760/shard-iclb4/igt@i915_pm_...@dpms-mode-unset-non-lpsp.html Known issues Here are the changes found in Patchwork_21760_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-glk: ([PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30]) -> ([PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [FAIL][53], [PASS][54], [PASS][55]) ([i915#4392]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk1/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk1/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk2/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk2/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk2/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk3/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk3/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk3/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk5/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk5/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk6/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk6/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk6/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk7/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk7/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk7/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk7/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk8/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk8/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk8/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk9/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/shard-glk9/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21760/shard-glk9/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21760/shard-glk9/boot.html [33]:
Re: [Intel-gfx] [PATCH v3 0/8] DG2 accelerated migration/clearing support
Hi Matthew, On Mon, 6 Dec 2021 at 13:32, Matthew Auld wrote: > Enable accelerated moves and clearing on DG2. On such HW we have minimum page > size restrictions when accessing LMEM from the GTT, where we now have to use > 64K > GTT pages or larger. With the ppGTT the page-table also has a slightly > different > layout from past generations when using the 64K GTT mode(which is still > enabled > on via some PDE bit), where it is now compacted down to 32 qword entries. Note > that on discrete the paging structures must also be placed in LMEM, and we > need > to able to modify them via the GTT itself(see patch 7), which is one of the > complications here. > > The series needs to be applied on top of the DG2 enabling branch: > https://cgit.freedesktop.org/~ramaling/linux/log/?h=dg2_enabling_ww49.3 What are the changes to the v1/v2? Cheers, Daniel
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gvt: Constify static structs
== Series Details == Series: drm/i915/gvt: Constify static structs URL : https://patchwork.freedesktop.org/series/97616/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21763 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21763 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21763, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21763/index.html Participating hosts (43 -> 31) -- Missing(12): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-kbl-x1275 fi-bdw-samus bat-jsl-2 bat-jsl-1 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21763: ### CI changes ### Possible regressions * boot: - fi-ivb-3770:[PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-ivb-3770/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21763/fi-ivb-3770/boot.html Known issues Here are the changes found in Patchwork_21763 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> [SKIP][3] ([fdo#109271]) +35 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21763/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21763/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_exec_parallel@engines: - fi-skl-6600u: NOTRUN -> [FAIL][5] ([i915#4547]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21763/fi-skl-6600u/igt@gem_exec_paral...@engines.html * igt@i915_selftest@live@gt_engines: - fi-rkl-guc: [PASS][6] -> [INCOMPLETE][7] ([i915#4432]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21763/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html * igt@kms_chamelium@hdmi-edid-read: - fi-bsw-kefka: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21763/fi-bsw-kefka/igt@kms_chamel...@hdmi-edid-read.html * igt@runner@aborted: - fi-skl-6600u: NOTRUN -> [FAIL][9] ([i915#3363] / [i915#4312]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21763/fi-skl-6600u/igt@run...@aborted.html - fi-rkl-guc: NOTRUN -> [FAIL][10] ([i915#3928] / [i915#4312]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21763/fi-rkl-guc/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s0: - fi-bsw-kefka: [INCOMPLETE][11] ([i915#2539]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21763/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-1115g4: [FAIL][13] ([i915#1888]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21763/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick:[DMESG-FAIL][15] ([i915#2927] / [i915#3428]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21763/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539 [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 Build changes - * Linux: CI_DRM_10965 ->
[Intel-gfx] ✗ Fi.CI.BUILD: failure for DG2 accelerated migration/clearing support (rev2)
== Series Details == Series: DG2 accelerated migration/clearing support (rev2) URL : https://patchwork.freedesktop.org/series/97544/ State : failure == Summary == Applying: drm/i915/migrate: don't check the scratch page Applying: drm/i915/migrate: fix offset calculation Applying: drm/i915/migrate: fix length calculation Applying: drm/i915/selftests: handle object rounding Applying: drm/i915/gtt: allow overriding the pt alignment Applying: drm/i915/gtt: add xehpsdv_ppgtt_insert_entry Applying: drm/i915/migrate: add acceleration support for DG2 error: sha1 information is lacking or useless (drivers/gpu/drm/i915/gt/intel_migrate.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0007 drm/i915/migrate: add acceleration support for DG2 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/migrate: don't check the scratch page
== Series Details == Series: series starting with [1/4] drm/i915/migrate: don't check the scratch page URL : https://patchwork.freedesktop.org/series/97610/ State : success == Summary == CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21762 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/index.html Participating hosts (43 -> 31) -- Missing(12): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-kbl-x1275 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21762 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@i915_selftest@live@gt_engines: - fi-rkl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#4432]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html * igt@kms_chamelium@hdmi-edid-read: - fi-bsw-kefka: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/fi-bsw-kefka/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_psr@primary_page_flip: - fi-skl-6600u: [PASS][6] -> [FAIL][7] ([i915#4547]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-skl-6600u/igt@kms_psr@primary_page_flip.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/fi-skl-6600u/igt@kms_psr@primary_page_flip.html * igt@runner@aborted: - fi-skl-6600u: NOTRUN -> [FAIL][8] ([i915#3363] / [i915#4312]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/fi-skl-6600u/igt@run...@aborted.html - fi-rkl-guc: NOTRUN -> [FAIL][9] ([i915#3928] / [i915#4312]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/fi-rkl-guc/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s0: - fi-bsw-kefka: [INCOMPLETE][10] ([i915#2539]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick:[DMESG-FAIL][12] ([i915#2927] / [i915#3428]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][14] ([i915#4269]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21762/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539 [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 Build changes - * Linux: CI_DRM_10965 -> Patchwork_21762 CI-20190529: 20190529 CI_DRM_10965: e9dedc5d0907d96371774cacca10160a167c5cd2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6300: f69bd65fa9f72b7d5e5a5a22981f16d034334761 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21762: c48601e77009b4305782f5a673cfb90deedbde4c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c48601e77009 drm/i915/selftests: handle object rounding ed9715d59a3a drm/i915/migrate: fix length calculation 611d287b1898 drm/i915/migrate: fix offset calculation
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gvt: Constify static structs
== Series Details == Series: drm/i915/gvt: Constify static structs URL : https://patchwork.freedesktop.org/series/97616/ State : warning == Summary == $ dim checkpatch origin/drm-tip ad6d0d2d2854 drm/i915/gvt: Constify intel_gvt_gtt_pte_ops 9f75a74af3af drm/i915/gvt: Constify intel_gvt_gtt_pte_ops -:30: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #30: FILE: drivers/gpu/drm/i915/gvt/gtt.c:530: +static void update_entry_type_for_real(const struct intel_gvt_gtt_pte_ops *pte_ops, struct intel_gvt_gtt_entry *entry, bool ips) total: 0 errors, 0 warnings, 1 checks, 256 lines checked b150cdd67e79 drm/i915/gvt: Constify intel_gvt_irq_ops e41696ad17dc drm/i915/gvt: Constify intel_gvt_sched_policy_ops 431473d1ea36 drm/i915/gvt: Constify gvt_mmio_block 6b20e5f39324 drm/i915/gvt: Constify cmd_interrupt_events d11cda723a89 drm/i915/gvt: Constify formats f75eaccd8a90 drm/i915/gvt: Constify gtt_type_table_entry 1b4f726b33b2 drm/i915/gvt: Constify vgpu_types
[Intel-gfx] [PATCH v3 8/8] drm/i915/migrate: turn on acceleration for DG2
Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Ramalingam C --- drivers/gpu/drm/i915/gt/intel_migrate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c index fb658ae70a8d..0fb83d0bec91 100644 --- a/drivers/gpu/drm/i915/gt/intel_migrate.c +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c @@ -243,8 +243,6 @@ int intel_migrate_init(struct intel_migrate *m, struct intel_gt *gt) memset(m, 0, sizeof(*m)); - return 0; - ce = pinned_context(gt); if (IS_ERR(ce)) return PTR_ERR(ce); -- 2.31.1
[Intel-gfx] [PATCH v3 6/8] drm/i915/gtt: add xehpsdv_ppgtt_insert_entry
If this is LMEM then we get a 32 entry PT, with each PTE pointing to
some 64K block of memory, otherwise it's just the usual 512 entry PT.
This very much assumes the caller knows what they are doing.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
Reviewed-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 50 ++--
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index bd3ca0996a23..312b2267bf87 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -728,13 +728,56 @@ static void gen8_ppgtt_insert_entry(struct
i915_address_space *vm,
gen8_pdp_for_page_index(vm, idx);
struct i915_page_directory *pd =
i915_pd_entry(pdp, gen8_pd_index(idx, 2));
+ struct i915_page_table *pt = i915_pt_entry(pd, gen8_pd_index(idx, 1));
gen8_pte_t *vaddr;
- vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
+ GEM_BUG_ON(pt->is_compact);
+
+ vaddr = px_vaddr(pt);
vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
clflush_cache_range([gen8_pd_index(idx, 0)], sizeof(*vaddr));
}
+static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ u64 idx = offset >> GEN8_PTE_SHIFT;
+ struct i915_page_directory * const pdp =
+ gen8_pdp_for_page_index(vm, idx);
+ struct i915_page_directory *pd =
+ i915_pd_entry(pdp, gen8_pd_index(idx, 2));
+ struct i915_page_table *pt = i915_pt_entry(pd, gen8_pd_index(idx, 1));
+ gen8_pte_t *vaddr;
+
+ GEM_BUG_ON(!IS_ALIGNED(addr, SZ_64K));
+ GEM_BUG_ON(!IS_ALIGNED(offset, SZ_64K));
+
+ if (!pt->is_compact) {
+ vaddr = px_vaddr(pd);
+ vaddr[gen8_pd_index(idx, 1)] |= GEN12_PDE_64K;
+ pt->is_compact = true;
+ }
+
+ vaddr = px_vaddr(pt);
+ vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level, flags);
+}
+
+static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ if (flags & PTE_LM)
+ return __xehpsdv_ppgtt_insert_entry_lm(vm, addr, offset,
+ level, flags);
+
+ return gen8_ppgtt_insert_entry(vm, addr, offset, level, flags);
+}
+
static int gen8_init_scratch(struct i915_address_space *vm)
{
u32 pte_flags;
@@ -937,7 +980,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
ppgtt->vm.insert_entries = gen8_ppgtt_insert;
- ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
+ if (HAS_64K_PAGES(gt->i915))
+ ppgtt->vm.insert_page = xehpsdv_ppgtt_insert_entry;
+ else
+ ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
ppgtt->vm.clear_range = gen8_ppgtt_clear;
ppgtt->vm.foreach = gen8_ppgtt_foreach;
--
2.31.1
[Intel-gfx] [PATCH v3 7/8] drm/i915/migrate: add acceleration support for DG2
This is all kinds of awkward since we now have to contend with using 64K
GTT pages when mapping anything in LMEM(including the page-tables
themselves).
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 189 +++-
1 file changed, 150 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 0192b61ab541..fb658ae70a8d 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -33,6 +33,38 @@ static bool engine_supports_migration(struct intel_engine_cs
*engine)
return true;
}
+static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data)
+{
+ struct insert_pte_data *d = data;
+
+ /*
+* Insert a dummy PTE into every PT that will map to LMEM to ensure
+* we have a correctly setup PDE structure for later use.
+*/
+ vm->insert_page(vm, 0, d->offset, I915_CACHE_NONE, PTE_LM);
+ GEM_BUG_ON(!pt->is_compact);
+ d->offset += SZ_2M;
+}
+
+static void xehpsdv_insert_pte(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data)
+{
+ struct insert_pte_data *d = data;
+
+ /*
+* We are playing tricks here, since the actual pt, from the hw
+* pov, is only 256bytes with 32 entries, or 4096bytes with 512
+* entries, but we are still guaranteed that the physical
+* alignment is 64K underneath for the pt, and we are careful
+* not to access the space in the void.
+*/
+ vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE, PTE_LM);
+ d->offset += SZ_64K;
+}
+
static void insert_pte(struct i915_address_space *vm,
struct i915_page_table *pt,
void *data)
@@ -75,7 +107,12 @@ static struct i915_address_space *migrate_vm(struct
intel_gt *gt)
* i.e. within the same non-preemptible window so that we do not switch
* to another migration context that overwrites the PTE.
*
-* TODO: Add support for huge LMEM PTEs
+* On platforms with HAS_64K_PAGES support we have three windows, and
+* dedicate two windows just for mapping lmem pages(smem <-> smem is not
+* a thing), since we are forced to use 64K GTT pages underneath which
+* requires also modifying the PDE. An alternative might be to instead
+* map the PD into the GTT, and then on the fly toggle the 4K/64K mode
+* in the PDE from the same batch that also modifies the PTEs.
*/
vm = i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY);
@@ -87,6 +124,9 @@ static struct i915_address_space *migrate_vm(struct intel_gt
*gt)
goto err_vm;
}
+ if (HAS_64K_PAGES(gt->i915))
+ stash.pt_sz = I915_GTT_PAGE_SIZE_64K;
+
/*
* Each engine instance is assigned its own chunk in the VM, so
* that we can run multiple instances concurrently
@@ -106,14 +146,20 @@ static struct i915_address_space *migrate_vm(struct
intel_gt *gt)
* We copy in 8MiB chunks. Each PDE covers 2MiB, so we need
* 4x2 page directories for source/destination.
*/
- sz = 2 * CHUNK_SZ;
+ if (HAS_64K_PAGES(gt->i915))
+ sz = 3 * CHUNK_SZ;
+ else
+ sz = 2 * CHUNK_SZ;
d.offset = base + sz;
/*
* We need another page directory setup so that we can write
* the 8x512 PTE in each chunk.
*/
- sz += (sz >> 12) * sizeof(u64);
+ if (HAS_64K_PAGES(gt->i915))
+ sz += (sz / SZ_2M) * SZ_64K;
+ else
+ sz += (sz >> 12) * sizeof(u64);
err = i915_vm_alloc_pt_stash(>vm, , sz);
if (err)
@@ -134,7 +180,18 @@ static struct i915_address_space *migrate_vm(struct
intel_gt *gt)
goto err_vm;
/* Now allow the GPU to rewrite the PTE via its own ppGTT */
- vm->vm.foreach(>vm, base, d.offset - base, insert_pte, );
+ if (HAS_64K_PAGES(gt->i915)) {
+ vm->vm.foreach(>vm, base, d.offset - base,
+ xehpsdv_insert_pte, );
+ d.offset = base + CHUNK_SZ;
+ vm->vm.foreach(>vm,
+ d.offset,
+ 2 * CHUNK_SZ,
+ xehpsdv_toggle_pdes, );
+ } else {
+ vm->vm.foreach(>vm, base, d.offset - base,
+
[Intel-gfx] [PATCH v3 5/8] drm/i915/gtt: allow overriding the pt alignment
On some platforms we have alignment restrictions when accessing LMEM
from the GTT. In the next patch few patches we need to be able to modify
the page-tables directly via the GTT itself.
Suggested-by: Ramalingam C
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_gtt.h | 10 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 16
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index cbc0b5266cb4..a00d278d8175 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -196,6 +196,14 @@ void *__px_vaddr(struct drm_i915_gem_object *p);
struct i915_vm_pt_stash {
/* preallocated chains of page tables/directories */
struct i915_page_table *pt[2];
+ /*
+* Optionally override the alignment/size of the physical page that
+* contains each PT. If not set defaults back to the usual
+* I915_GTT_PAGE_SIZE_4K. This does not influence the other paging
+* structures. MUST be a power-of-two. ONLY applicable on discrete
+* platforms.
+*/
+ int pt_sz;
};
struct i915_vma_ops {
@@ -583,7 +591,7 @@ void free_scratch(struct i915_address_space *vm);
struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int
sz);
struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int
sz);
-struct i915_page_table *alloc_pt(struct i915_address_space *vm);
+struct i915_page_table *alloc_pt(struct i915_address_space *vm, int sz);
struct i915_page_directory *alloc_pd(struct i915_address_space *vm);
struct i915_page_directory *__alloc_pd(int npde);
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index b8238f5bc8b1..3c90aea25072 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -12,7 +12,7 @@
#include "gen6_ppgtt.h"
#include "gen8_ppgtt.h"
-struct i915_page_table *alloc_pt(struct i915_address_space *vm)
+struct i915_page_table *alloc_pt(struct i915_address_space *vm, int sz)
{
struct i915_page_table *pt;
@@ -20,7 +20,7 @@ struct i915_page_table *alloc_pt(struct i915_address_space
*vm)
if (unlikely(!pt))
return ERR_PTR(-ENOMEM);
- pt->base = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K);
+ pt->base = vm->alloc_pt_dma(vm, sz);
if (IS_ERR(pt->base)) {
kfree(pt);
return ERR_PTR(-ENOMEM);
@@ -219,17 +219,25 @@ int i915_vm_alloc_pt_stash(struct i915_address_space *vm,
u64 size)
{
unsigned long count;
- int shift, n;
+ int shift, n, pt_sz;
shift = vm->pd_shift;
if (!shift)
return 0;
+ pt_sz = stash->pt_sz;
+ if (!pt_sz)
+ pt_sz = I915_GTT_PAGE_SIZE_4K;
+ else
+ GEM_BUG_ON(!IS_DGFX(vm->i915));
+
+ GEM_BUG_ON(!is_power_of_2(pt_sz));
+
count = pd_count(size, shift);
while (count--) {
struct i915_page_table *pt;
- pt = alloc_pt(vm);
+ pt = alloc_pt(vm, pt_sz);
if (IS_ERR(pt)) {
i915_vm_free_pt_stash(vm, stash);
return PTR_ERR(pt);
--
2.31.1
[Intel-gfx] [PATCH v3 4/8] drm/i915/selftests: handle object rounding
Ensure we account for any object rounding due to min_page_size restrictions. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Ramalingam C Reviewed-by: Ramalingam C --- drivers/gpu/drm/i915/gt/selftest_migrate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c b/drivers/gpu/drm/i915/gt/selftest_migrate.c index 12ef2837c89b..e21787301bbd 100644 --- a/drivers/gpu/drm/i915/gt/selftest_migrate.c +++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c @@ -49,6 +49,7 @@ static int copy(struct intel_migrate *migrate, if (IS_ERR(src)) return 0; + sz = src->base.size; dst = i915_gem_object_create_internal(i915, sz); if (IS_ERR(dst)) goto err_free_src; -- 2.31.1
[Intel-gfx] [PATCH v3 3/8] drm/i915/migrate: fix length calculation
No need to insert PTEs for the PTE window itself, also foreach expects a length not an end offset, which could be gigantic here with a second engine. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Ramalingam C Reviewed-by: Ramalingam C --- drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c index 6f2c4388ebb4..0192b61ab541 100644 --- a/drivers/gpu/drm/i915/gt/intel_migrate.c +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c @@ -134,7 +134,7 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt) goto err_vm; /* Now allow the GPU to rewrite the PTE via its own ppGTT */ - vm->vm.foreach(>vm, base, base + sz, insert_pte, ); + vm->vm.foreach(>vm, base, d.offset - base, insert_pte, ); } return >vm; -- 2.31.1
[Intel-gfx] [PATCH v3 2/8] drm/i915/migrate: fix offset calculation
Ensure we add the engine base only after we calculate the qword offset into the PTE window. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Ramalingam C Reviewed-by: Ramalingam C --- drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c index 2d3188a398dd..6f2c4388ebb4 100644 --- a/drivers/gpu/drm/i915/gt/intel_migrate.c +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c @@ -282,10 +282,10 @@ static int emit_pte(struct i915_request *rq, GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8); /* Compute the page directory offset for the target address range */ - offset += (u64)rq->engine->instance << 32; offset >>= 12; offset *= sizeof(u64); offset += 2 * CHUNK_SZ; + offset += (u64)rq->engine->instance << 32; cs = intel_ring_begin(rq, 6); if (IS_ERR(cs)) -- 2.31.1
[Intel-gfx] [PATCH v3 1/8] drm/i915/migrate: don't check the scratch page
The scratch page might not be allocated in LMEM(like on DG2), so instead
of using that as the deciding factor for where the paging structures
live, let's just query the pt before mapping it.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
Reviewed-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 765c6d48fe52..2d3188a398dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -13,7 +13,6 @@
struct insert_pte_data {
u64 offset;
- bool is_lmem;
};
#define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
@@ -41,7 +40,7 @@ static void insert_pte(struct i915_address_space *vm,
struct insert_pte_data *d = data;
vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE,
- d->is_lmem ? PTE_LM : 0);
+ i915_gem_object_is_lmem(pt->base) ? PTE_LM : 0);
d->offset += PAGE_SIZE;
}
@@ -135,7 +134,6 @@ static struct i915_address_space *migrate_vm(struct
intel_gt *gt)
goto err_vm;
/* Now allow the GPU to rewrite the PTE via its own ppGTT */
- d.is_lmem = i915_gem_object_is_lmem(vm->vm.scratch[0]);
vm->vm.foreach(>vm, base, base + sz, insert_pte, );
}
--
2.31.1
[Intel-gfx] [PATCH v3 0/8] DG2 accelerated migration/clearing support
Enable accelerated moves and clearing on DG2. On such HW we have minimum page size restrictions when accessing LMEM from the GTT, where we now have to use 64K GTT pages or larger. With the ppGTT the page-table also has a slightly different layout from past generations when using the 64K GTT mode(which is still enabled on via some PDE bit), where it is now compacted down to 32 qword entries. Note that on discrete the paging structures must also be placed in LMEM, and we need to able to modify them via the GTT itself(see patch 7), which is one of the complications here. The series needs to be applied on top of the DG2 enabling branch: https://cgit.freedesktop.org/~ramaling/linux/log/?h=dg2_enabling_ww49.3 Matthew Auld (8): drm/i915/migrate: don't check the scratch page drm/i915/migrate: fix offset calculation drm/i915/migrate: fix length calculation drm/i915/selftests: handle object rounding drm/i915/gtt: allow overriding the pt alignment drm/i915/gtt: add xehpsdv_ppgtt_insert_entry drm/i915/migrate: add acceleration support for DG2 drm/i915/migrate: turn on acceleration for DG2 drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 50 +- drivers/gpu/drm/i915/gt/intel_gtt.h| 10 +- drivers/gpu/drm/i915/gt/intel_migrate.c| 195 - drivers/gpu/drm/i915/gt/intel_ppgtt.c | 16 +- drivers/gpu/drm/i915/gt/selftest_migrate.c | 1 + 5 files changed, 221 insertions(+), 51 deletions(-) -- 2.31.1
[Intel-gfx] [PATCH 7/9] drm/i915/gvt: Constify formats
These are never modified, so make them const to allow the compiler to
put them in read-only memory. WHile at it, make the description const
char* since it is never modified.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/fb_decoder.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c
b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 11a8baba6822..3c8736ae8fed 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -40,12 +40,12 @@
#define PRIMARY_FORMAT_NUM 16
struct pixel_format {
- int drm_format; /* Pixel format in DRM definition */
- int bpp;/* Bits per pixel, 0 indicates invalid */
- char*desc; /* The description */
+ int drm_format; /* Pixel format in DRM definition */
+ int bpp;/* Bits per pixel, 0 indicates invalid
*/
+ const char *desc; /* The description */
};
-static struct pixel_format bdw_pixel_formats[] = {
+static const struct pixel_format bdw_pixel_formats[] = {
{DRM_FORMAT_C8, 8, "8-bit Indexed"},
{DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
{DRM_FORMAT_XRGB, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
@@ -58,7 +58,7 @@ static struct pixel_format bdw_pixel_formats[] = {
{0, 0, NULL},
};
-static struct pixel_format skl_pixel_formats[] = {
+static const struct pixel_format skl_pixel_formats[] = {
{DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
{DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
{DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
@@ -278,14 +278,14 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu
*vgpu,
#define CURSOR_FORMAT_NUM (1 << 6)
struct cursor_mode_format {
- int drm_format; /* Pixel format in DRM definition */
- u8 bpp;/* Bits per pixel; 0 indicates invalid */
- u32 width; /* In pixel */
- u32 height; /* In lines */
- char*desc; /* The description */
+ int drm_format; /* Pixel format in DRM definition */
+ u8 bpp;/* Bits per pixel; 0 indicates invalid
*/
+ u32 width; /* In pixel */
+ u32 height; /* In lines */
+ const char *desc; /* The description */
};
-static struct cursor_mode_format cursor_pixel_formats[] = {
+static const struct cursor_mode_format cursor_pixel_formats[] = {
{DRM_FORMAT_ARGB, 32, 128, 128, "128x128 32bpp ARGB"},
{DRM_FORMAT_ARGB, 32, 256, 256, "256x256 32bpp ARGB"},
{DRM_FORMAT_ARGB, 32, 64, 64, "64x64 32bpp ARGB"},
@@ -391,7 +391,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
#define SPRITE_FORMAT_NUM (1 << 3)
-static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
+static const struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
[0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
[0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
[0x2] = {DRM_FORMAT_XRGB, 32, "RGB 32-bit 8:8:8:8"},
--
2.34.1
[Intel-gfx] [PATCH 2/9] drm/i915/gvt: Constify intel_gvt_gtt_pte_ops
These are never modified, so make them const to allow the compiler to
put them in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/gtt.c | 62 +-
drivers/gpu/drm/i915/gvt/gtt.h | 2 +-
2 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 6efa48727052..c8cd6bf28ea8 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -499,7 +499,7 @@ DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
-static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
+static const struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
.get_entry = gtt_get_entry64,
.set_entry = gtt_set_entry64,
.clear_present = gtt_entry_clear_present,
@@ -526,7 +526,7 @@ static const struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops
= {
};
/* Update entry type per pse and ips bit. */
-static void update_entry_type_for_real(struct intel_gvt_gtt_pte_ops *pte_ops,
+static void update_entry_type_for_real(const struct intel_gvt_gtt_pte_ops
*pte_ops,
struct intel_gvt_gtt_entry *entry, bool ips)
{
switch (entry->type) {
@@ -553,7 +553,7 @@ static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index,
bool guest)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops =
mm->vgpu->gvt->gtt.pte_ops;
GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
@@ -580,7 +580,7 @@ static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index,
bool guest)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops =
mm->vgpu->gvt->gtt.pte_ops;
pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
mm->ppgtt_mm.shadow_pdps,
@@ -596,7 +596,7 @@ static inline void ppgtt_set_shadow_root_entry(struct
intel_vgpu_mm *mm,
static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops =
mm->vgpu->gvt->gtt.pte_ops;
GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
@@ -608,7 +608,7 @@ static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops =
mm->vgpu->gvt->gtt.pte_ops;
GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
@@ -619,7 +619,7 @@ static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops =
mm->vgpu->gvt->gtt.pte_ops;
GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
@@ -629,7 +629,7 @@ static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops =
mm->vgpu->gvt->gtt.pte_ops;
unsigned long offset = index;
GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
@@ -655,7 +655,7 @@ static inline int ppgtt_spt_get_entry(
bool guest)
{
struct intel_gvt *gvt = spt->vgpu->gvt;
- struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
int ret;
e->type = get_entry_type(type);
@@ -684,7 +684,7 @@ static inline int ppgtt_spt_set_entry(
bool guest)
{
struct intel_gvt *gvt = spt->vgpu->gvt;
- struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
return -EINVAL;
@@ -947,7 +947,7 @@ static int ppgtt_invalidate_spt_by_shadow_entry(struct
intel_vgpu *vgpu,
struct intel_gvt_gtt_entry *e)
{
struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
[Intel-gfx] [PATCH 5/9] drm/i915/gvt: Constify gvt_mmio_block
These are never modified, so make them const to allow the compiler to
put it in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/gvt.h | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 12 ++--
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 0c0615602343..0ebffc327528 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -272,7 +272,7 @@ struct intel_gvt_mmio {
/* Value of command write of this reg needs to be patched */
#define F_CMD_WRITE_PATCH (1 << 8)
- struct gvt_mmio_block *mmio_block;
+ const struct gvt_mmio_block *mmio_block;
unsigned int num_mmio_block;
DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index cde0a477fb49..5e85a77da257 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -3627,11 +3627,11 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
return 0;
}
-static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
- unsigned int offset)
+static const struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
+ unsigned int offset)
{
unsigned long device = intel_gvt_get_device_type(gvt);
- struct gvt_mmio_block *block = gvt->mmio.mmio_block;
+ const struct gvt_mmio_block *block = gvt->mmio.mmio_block;
int num = gvt->mmio.num_mmio_block;
int i;
@@ -3670,7 +3670,7 @@ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
* accessible (should have no F_CMD_ACCESS flag).
* otherwise, need to update cmd_reg_handler in cmd_parser.c
*/
-static struct gvt_mmio_block mmio_blocks[] = {
+static const struct gvt_mmio_block mmio_blocks[] = {
{D_SKL_PLUS, _MMIO(DMC_MMIO_START_RANGE), 0x3000, NULL, NULL},
{D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x4, NULL, NULL},
{D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
@@ -3753,7 +3753,7 @@ int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
void *data)
{
- struct gvt_mmio_block *block = gvt->mmio.mmio_block;
+ const struct gvt_mmio_block *block = gvt->mmio.mmio_block;
struct intel_gvt_mmio_info *e;
int i, j, ret;
@@ -3871,7 +3871,7 @@ int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu,
unsigned int offset,
struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_mmio_info *mmio_info;
- struct gvt_mmio_block *mmio_block;
+ const struct gvt_mmio_block *mmio_block;
gvt_mmio_func func;
int ret;
--
2.34.1
[Intel-gfx] [PATCH 9/9] drm/i915/gvt: Constify vgpu_types
It is never modified, so make it const to allow the compiler to put it
in read-only memory. While at it, make name a const char*.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/vgpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index fa6b92615799..80a940a1 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -77,7 +77,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
#define VGPU_WEIGHT(vgpu_num) \
(VGPU_MAX_WEIGHT / (vgpu_num))
-static struct {
+static const struct {
unsigned int low_mm;
unsigned int high_mm;
unsigned int fence;
@@ -88,7 +88,7 @@ static struct {
*/
unsigned int weight;
enum intel_vgpu_edid edid;
- char *name;
+ const char *name;
} vgpu_types[] = {
/* Fixed vGPU type table */
{ MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8),
GVT_EDID_1024_768, "8" },
--
2.34.1
[Intel-gfx] [PATCH 4/9] drm/i915/gvt: Constify intel_gvt_sched_policy_ops
These are never modified, so make them const to allow the compiler to
put them in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/sched_policy.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.h| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/sched_policy.c
b/drivers/gpu/drm/i915/gvt/sched_policy.c
index 036b74fe9298..c077fb4674f0 100644
--- a/drivers/gpu/drm/i915/gvt/sched_policy.c
+++ b/drivers/gpu/drm/i915/gvt/sched_policy.c
@@ -368,7 +368,7 @@ static void tbs_sched_stop_schedule(struct intel_vgpu *vgpu)
vgpu_data->active = false;
}
-static struct intel_gvt_sched_policy_ops tbs_schedule_ops = {
+static const struct intel_gvt_sched_policy_ops tbs_schedule_ops = {
.init = tbs_sched_init,
.clean = tbs_sched_clean,
.init_vgpu = tbs_sched_init_vgpu,
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h
b/drivers/gpu/drm/i915/gvt/scheduler.h
index 7c86984a842f..1f391b3da2cc 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.h
+++ b/drivers/gpu/drm/i915/gvt/scheduler.h
@@ -56,7 +56,7 @@ struct intel_gvt_workload_scheduler {
wait_queue_head_t waitq[I915_NUM_ENGINES];
void *sched_data;
- struct intel_gvt_sched_policy_ops *sched_ops;
+ const struct intel_gvt_sched_policy_ops *sched_ops;
};
#define INDIRECT_CTX_ADDR_MASK 0xffc0
--
2.34.1
[Intel-gfx] [PATCH 6/9] drm/i915/gvt: Constify cmd_interrupt_events
It is never modified, so make it const to allow the compiler to put it
in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index c4118b808268..ce9307546e7f 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1144,7 +1144,7 @@ struct cmd_interrupt_event {
int mi_user_interrupt;
};
-static struct cmd_interrupt_event cmd_interrupt_events[] = {
+static const struct cmd_interrupt_event cmd_interrupt_events[] = {
[RCS0] = {
.pipe_control_notify = RCS_PIPE_CONTROL,
.mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
--
2.34.1
[Intel-gfx] [PATCH 1/9] drm/i915/gvt: Constify intel_gvt_gtt_pte_ops
These are never modified, so make them const to allow the compiler to
put them in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/gtt.c | 4 ++--
drivers/gpu/drm/i915/gvt/gtt.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 53d0cb327539..6efa48727052 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -516,7 +516,7 @@ static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
.set_pfn = gen8_gtt_set_pfn,
};
-static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
+static const struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
.gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
.gma_to_pte_index = gen8_gma_to_pte_index,
.gma_to_pde_index = gen8_gma_to_pde_index,
@@ -2097,7 +2097,7 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm
*mm, unsigned long gma)
struct intel_vgpu *vgpu = mm->vgpu;
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
- struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
+ const struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
unsigned long gpa = INTEL_GVT_INVALID_ADDR;
unsigned long gma_index[4];
struct intel_gvt_gtt_entry e;
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index 3bf45672ef98..d0d598322404 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -92,7 +92,7 @@ struct intel_gvt_gtt_gma_ops {
struct intel_gvt_gtt {
struct intel_gvt_gtt_pte_ops *pte_ops;
- struct intel_gvt_gtt_gma_ops *gma_ops;
+ const struct intel_gvt_gtt_gma_ops *gma_ops;
int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm);
void (*mm_free_page_table)(struct intel_vgpu_mm *mm);
struct list_head oos_page_use_list_head;
--
2.34.1
[Intel-gfx] [PATCH 0/9] drm/i915/gvt: Constify static structs
Constify a number of static structs that are never modified to allow the compiler to put them in read-only memory. In order to do this, constify a number of local variables and pointers in structs. This is most important for structs that contain function pointers, and the patches for those structs are placed first in the series. Rikard Falkeborn (9): drm/i915/gvt: Constify intel_gvt_gtt_pte_ops drm/i915/gvt: Constify intel_gvt_gtt_pte_ops drm/i915/gvt: Constify intel_gvt_irq_ops drm/i915/gvt: Constify intel_gvt_sched_policy_ops drm/i915/gvt: Constify gvt_mmio_block drm/i915/gvt: Constify cmd_interrupt_events drm/i915/gvt: Constify formats drm/i915/gvt: Constify gtt_type_table_entry drm/i915/gvt: Constify vgpu_types drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- drivers/gpu/drm/i915/gvt/fb_decoder.c | 24 - drivers/gpu/drm/i915/gvt/gtt.c | 68 - drivers/gpu/drm/i915/gvt/gtt.h | 4 +- drivers/gpu/drm/i915/gvt/gvt.h | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 12 ++--- drivers/gpu/drm/i915/gvt/interrupt.c| 10 ++-- drivers/gpu/drm/i915/gvt/interrupt.h| 2 +- drivers/gpu/drm/i915/gvt/sched_policy.c | 2 +- drivers/gpu/drm/i915/gvt/scheduler.h| 2 +- drivers/gpu/drm/i915/gvt/vgpu.c | 4 +- 11 files changed, 66 insertions(+), 66 deletions(-) -- 2.34.1
[Intel-gfx] [PATCH 8/9] drm/i915/gvt: Constify gtt_type_table_entry
It is never modified, so make it const to allow the compiler to put it
in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index c8cd6bf28ea8..614156856f16 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -185,7 +185,7 @@ struct gtt_type_table_entry {
.pse_entry_type = pse_type, \
}
-static struct gtt_type_table_entry gtt_type_table[] = {
+static const struct gtt_type_table_entry gtt_type_table[] = {
GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
GTT_TYPE_INVALID,
--
2.34.1
Re: [Intel-gfx] [PATCH v2 04/16] drm/i915: Take object lock in i915_ggtt_pin if ww is not set
On Mon, 29 Nov 2021 at 13:58, Maarten Lankhorst wrote: > > i915_vma_wait_for_bind needs the vma lock held, fix the caller. > > Signed-off-by: Maarten Lankhorst Reviewed-by: Matthew Auld
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Use hw_engine_masks as reset_domains (rev2)
== Series Details == Series: drm/i915/gt: Use hw_engine_masks as reset_domains (rev2) URL : https://patchwork.freedesktop.org/series/97543/ State : success == Summary == CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21761 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/index.html Participating hosts (43 -> 31) -- Missing(12): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-kbl-x1275 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21761 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@kms_chamelium@hdmi-edid-read: - fi-bsw-kefka: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/fi-bsw-kefka/igt@kms_chamel...@hdmi-edid-read.html Possible fixes * igt@gem_exec_suspend@basic-s0: - fi-bsw-kefka: [INCOMPLETE][4] ([i915#2539]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-1115g4: [FAIL][6] ([i915#1888]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick:[DMESG-FAIL][8] ([i915#2927] / [i915#3428]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][10] ([i915#4269]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539 [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 Build changes - * Linux: CI_DRM_10965 -> Patchwork_21761 CI-20190529: 20190529 CI_DRM_10965: e9dedc5d0907d96371774cacca10160a167c5cd2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6300: f69bd65fa9f72b7d5e5a5a22981f16d034334761 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21761: c86b41e0f693324dd3bdc0048ca8a3af63a5ddbf @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c86b41e0f693 drm/i915/gt: Use hw_engine_masks as reset_domains == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21761/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gt: Use hw_engine_masks as reset_domains (rev2)
== Series Details == Series: drm/i915/gt: Use hw_engine_masks as reset_domains (rev2) URL : https://patchwork.freedesktop.org/series/97543/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use GEM_BUG_ON for obj ptr NULL check
== Series Details == Series: drm/i915: Use GEM_BUG_ON for obj ptr NULL check URL : https://patchwork.freedesktop.org/series/97605/ State : success == Summary == CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21760 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21760/index.html Participating hosts (43 -> 32) -- Additional (1): fi-pnv-d510 Missing(12): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-kbl-x1275 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21760 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21760/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21760/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@kms_chamelium@hdmi-edid-read: - fi-bsw-kefka: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21760/fi-bsw-kefka/igt@kms_chamel...@hdmi-edid-read.html * igt@prime_vgem@basic-userptr: - fi-pnv-d510:NOTRUN -> [SKIP][4] ([fdo#109271]) +57 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21760/fi-pnv-d510/igt@prime_v...@basic-userptr.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][5] ([i915#2426] / [i915#4312]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21760/fi-bdw-5557u/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s0: - fi-bsw-kefka: [INCOMPLETE][6] ([i915#2539]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21760/fi-bsw-kefka/igt@gem_exec_susp...@basic-s0.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick:[DMESG-FAIL][8] ([i915#2927] / [i915#3428]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21760/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][10] ([i915#4269]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10965/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21760/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539 [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 Build changes - * Linux: CI_DRM_10965 -> Patchwork_21760 CI-20190529: 20190529 CI_DRM_10965: e9dedc5d0907d96371774cacca10160a167c5cd2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6300: f69bd65fa9f72b7d5e5a5a22981f16d034334761 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21760: 75f5a106eec54de2e7dca888ea3e20168f09de52 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 75f5a106eec5 drm/i915: Use GEM_BUG_ON for obj ptr NULL check == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21760/index.html
[Intel-gfx] ✗ Fi.CI.BAT: failure for More preparation for multi gt patches (rev5)
== Series Details ==
Series: More preparation for multi gt patches (rev5)
URL : https://patchwork.freedesktop.org/series/97020/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21759
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_21759 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21759, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/index.html
Participating hosts (43 -> 32)
--
Missing(11): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan
bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-2 bat-jsl-1
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21759:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- fi-rkl-11600: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-rkl-11600/igt@run...@aborted.html
- fi-hsw-4770:NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-hsw-4770/igt@run...@aborted.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-jsl-1}: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-jsl-1/igt@run...@aborted.html
- {fi-ehl-2}: NOTRUN -> [FAIL][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-ehl-2/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_21759 that come from known issues:
### IGT changes ###
Issues hit
* igt@runner@aborted:
- fi-ilk-650: NOTRUN -> [FAIL][5] ([i915#2426])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-ilk-650/igt@run...@aborted.html
- fi-kbl-x1275: NOTRUN -> [FAIL][6] ([i915#2426] / [i915#3363])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-kbl-x1275/igt@run...@aborted.html
- fi-bsw-kefka: NOTRUN -> [FAIL][7] ([i915#3690])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-bsw-kefka/igt@run...@aborted.html
- fi-bdw-gvtdvm: NOTRUN -> [FAIL][8] ([i915#2426])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-bdw-gvtdvm/igt@run...@aborted.html
- fi-cfl-8700k: NOTRUN -> [FAIL][9] ([i915#2426] / [i915#3363])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-cfl-8700k/igt@run...@aborted.html
- fi-skl-6600u: NOTRUN -> [FAIL][10] ([i915#2426] / [i915#3363])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-skl-6600u/igt@run...@aborted.html
- fi-cfl-8109u: NOTRUN -> [FAIL][11] ([i915#2426] / [i915#3363])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-cfl-8109u/igt@run...@aborted.html
- fi-glk-dsi: NOTRUN -> [FAIL][12] ([i915#2426] / [i915#3363] /
[k.org#202321])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-8809g: NOTRUN -> [FAIL][13] ([i915#2426] / [i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-kbl-8809g/igt@run...@aborted.html
- fi-snb-2520m: NOTRUN -> [FAIL][14] ([i915#2426])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-snb-2520m/igt@run...@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][15] ([i915#2426])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-bdw-5557u/igt@run...@aborted.html
- fi-bwr-2160:NOTRUN -> [FAIL][16] ([i915#4529])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-bwr-2160/igt@run...@aborted.html
- fi-kbl-7500u: NOTRUN -> [FAIL][17] ([i915#2426] / [i915#3363])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-kbl-7500u/igt@run...@aborted.html
- fi-kbl-guc: NOTRUN -> [FAIL][18] ([i915#2426] / [i915#3363])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-kbl-guc/igt@run...@aborted.html
- fi-cml-u2: NOTRUN -> [FAIL][19] ([i915#2426] / [i915#3363])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-cml-u2/igt@run...@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][20] ([i915#2426])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-rkl-guc/igt@run...@aborted.html
- fi-ivb-3770:NOTRUN -> [FAIL][21] ([i915#2426])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21759/fi-ivb-3770/igt@run...@aborted.html
-
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for More preparation for multi gt patches (rev5)
== Series Details == Series: More preparation for multi gt patches (rev5) URL : https://patchwork.freedesktop.org/series/97020/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More preparation for multi gt patches (rev5)
== Series Details == Series: More preparation for multi gt patches (rev5) URL : https://patchwork.freedesktop.org/series/97020/ State : warning == Summary == $ dim checkpatch origin/drm-tip 664bf127629d drm/i915: Store backpointer to GT in uncore 6126245f7f9b drm/i915: Introduce to_gt() helper 85a64d5e3941 drm/i915/display: Use to_gt() helper 285ede8ab554 drm/i915/gt: Use to_gt() helper -:13: WARNING:BAD_SIGN_OFF: Non-standard signature: 'Singed-off-by:' - perhaps 'Signed-off-by:'? #13: Singed-off-by: Andi Shyti total: 0 errors, 1 warnings, 0 checks, 306 lines checked 5d66c381c586 drm/i915/gem: Use to_gt() helper 1bce3ff140dd drm/i915/gvt: Use to_gt() helper 0ec5ef1f0da2 drm/i915/selftests: Use to_gt() helper fe75e5f64d63 drm/i915/pxp: Use to_gt() helper 7922c316658f drm/i915: Use to_gt() helper f8c0e8ff2a32 drm/i915: Use to_gt() helper for GGTT accesses -:226: WARNING:LONG_LINE: line length of 112 exceeds 100 columns #226: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:323: + (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT); -:257: WARNING:LONG_LINE: line length of 112 exceeds 100 columns #257: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:460: + (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT); total: 0 errors, 2 warnings, 0 checks, 494 lines checked fb8677e8f722 drm/i915: Rename i915->gt to i915->gt0
[Intel-gfx] [PATCH 1/4] drm/i915/migrate: don't check the scratch page
The scratch page might not be allocated in LMEM(like on DG2), so instead
of using that as the deciding factor for where the paging structures
live, let's just query the pt before mapping it.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
Reviewed-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index afb1cce9a352..0f94dedc1599 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -13,7 +13,6 @@
struct insert_pte_data {
u64 offset;
- bool is_lmem;
};
#define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
@@ -40,7 +39,7 @@ static void insert_pte(struct i915_address_space *vm,
struct insert_pte_data *d = data;
vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE,
- d->is_lmem ? PTE_LM : 0);
+ i915_gem_object_is_lmem(pt->base) ? PTE_LM : 0);
d->offset += PAGE_SIZE;
}
@@ -134,7 +133,6 @@ static struct i915_address_space *migrate_vm(struct
intel_gt *gt)
goto err_vm;
/* Now allow the GPU to rewrite the PTE via its own ppGTT */
- d.is_lmem = i915_gem_object_is_lmem(vm->vm.scratch[0]);
vm->vm.foreach(>vm, base, base + sz, insert_pte, );
}
--
2.31.1
[Intel-gfx] [PATCH 4/4] drm/i915/selftests: handle object rounding
Ensure we account for any object rounding due to min_page_size restrictions. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Ramalingam C Reviewed-by: Ramalingam C --- drivers/gpu/drm/i915/gt/selftest_migrate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c b/drivers/gpu/drm/i915/gt/selftest_migrate.c index 12ef2837c89b..e21787301bbd 100644 --- a/drivers/gpu/drm/i915/gt/selftest_migrate.c +++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c @@ -49,6 +49,7 @@ static int copy(struct intel_migrate *migrate, if (IS_ERR(src)) return 0; + sz = src->base.size; dst = i915_gem_object_create_internal(i915, sz); if (IS_ERR(dst)) goto err_free_src; -- 2.31.1
[Intel-gfx] [PATCH 2/4] drm/i915/migrate: fix offset calculation
Ensure we add the engine base only after we calculate the qword offset into the PTE window. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Ramalingam C Reviewed-by: Ramalingam C --- drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c index 0f94dedc1599..64afb9a52013 100644 --- a/drivers/gpu/drm/i915/gt/intel_migrate.c +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c @@ -279,10 +279,10 @@ static int emit_pte(struct i915_request *rq, GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8); /* Compute the page directory offset for the target address range */ - offset += (u64)rq->engine->instance << 32; offset >>= 12; offset *= sizeof(u64); offset += 2 * CHUNK_SZ; + offset += (u64)rq->engine->instance << 32; cs = intel_ring_begin(rq, 6); if (IS_ERR(cs)) -- 2.31.1
[Intel-gfx] [PATCH 3/4] drm/i915/migrate: fix length calculation
No need to insert PTEs for the PTE window itself, also foreach expects a length not an end offset, which could be gigantic here with a second engine. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Ramalingam C Reviewed-by: Ramalingam C --- drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c index 64afb9a52013..19a01878fee3 100644 --- a/drivers/gpu/drm/i915/gt/intel_migrate.c +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c @@ -133,7 +133,7 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt) goto err_vm; /* Now allow the GPU to rewrite the PTE via its own ppGTT */ - vm->vm.foreach(>vm, base, base + sz, insert_pte, ); + vm->vm.foreach(>vm, base, d.offset - base, insert_pte, ); } return >vm; -- 2.31.1
[Intel-gfx] [PATCH V2] drm/i915/gt: Use hw_engine_masks as reset_domains
We need a way to reset engines by their reset domains.
This change sets up way to fetch reset domains of each
engine globally.
Changes since V1:
- Use static reset domain array - Ville and Tvrtko
- Use BUG_ON at appropriate place - Tvrtko
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 32
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_reset.c| 29 ++
3 files changed, 35 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f2ccd5b53d42..352254e001b4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -325,6 +325,38 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id,
engine->id = id;
engine->legacy_idx = INVALID_ENGINE;
engine->mask = BIT(id);
+ if (GRAPHICS_VER(gt->i915) >= 11) {
+ static const u32 engine_reset_domains[] = {
+ [RCS0] = GEN11_GRDOM_RENDER,
+ [BCS0] = GEN11_GRDOM_BLT,
+ [VCS0] = GEN11_GRDOM_MEDIA,
+ [VCS1] = GEN11_GRDOM_MEDIA2,
+ [VCS2] = GEN11_GRDOM_MEDIA3,
+ [VCS3] = GEN11_GRDOM_MEDIA4,
+ [VCS4] = GEN11_GRDOM_MEDIA5,
+ [VCS5] = GEN11_GRDOM_MEDIA6,
+ [VCS6] = GEN11_GRDOM_MEDIA7,
+ [VCS7] = GEN11_GRDOM_MEDIA8,
+ [VECS0] = GEN11_GRDOM_VECS,
+ [VECS1] = GEN11_GRDOM_VECS2,
+ [VECS2] = GEN11_GRDOM_VECS3,
+ [VECS3] = GEN11_GRDOM_VECS4,
+ };
+ GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
+ !engine_reset_domains[id]);
+ engine->reset_domain = engine_reset_domains[id];
+ } else {
+ static const u32 engine_reset_domains[] = {
+ [RCS0] = GEN6_GRDOM_RENDER,
+ [BCS0] = GEN6_GRDOM_BLT,
+ [VCS0] = GEN6_GRDOM_MEDIA,
+ [VCS1] = GEN8_GRDOM_MEDIA2,
+ [VECS0] = GEN6_GRDOM_VECS,
+ };
+ GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
+ !engine_reset_domains[id]);
+ engine->reset_domain = engine_reset_domains[id];
+ }
engine->i915 = i915;
engine->gt = gt;
engine->uncore = gt->uncore;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 5732e0d71513..36365bdbe1ee 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -318,6 +318,7 @@ struct intel_engine_cs {
unsigned int guc_id;
intel_engine_mask_t mask;
+ u32 reset_domain;
/**
* @logical_mask: logical mask of engine, reported to user space via
* query IOCTL and used to communicate with the GuC in logical space.
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 0fbd6dbadce7..63199f0550e6 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -297,13 +297,6 @@ static int gen6_reset_engines(struct intel_gt *gt,
intel_engine_mask_t engine_mask,
unsigned int retry)
{
- static const u32 hw_engine_mask[] = {
- [RCS0] = GEN6_GRDOM_RENDER,
- [BCS0] = GEN6_GRDOM_BLT,
- [VCS0] = GEN6_GRDOM_MEDIA,
- [VCS1] = GEN8_GRDOM_MEDIA2,
- [VECS0] = GEN6_GRDOM_VECS,
- };
struct intel_engine_cs *engine;
u32 hw_mask;
@@ -314,8 +307,7 @@ static int gen6_reset_engines(struct intel_gt *gt,
hw_mask = 0;
for_each_engine_masked(engine, gt, engine_mask, tmp) {
- GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
- hw_mask |= hw_engine_mask[engine->id];
+ hw_mask |= engine->reset_domain;
}
}
@@ -492,22 +484,6 @@ static int gen11_reset_engines(struct intel_gt *gt,
intel_engine_mask_t engine_mask,
unsigned int retry)
{
- static const u32 hw_engine_mask[] = {
- [RCS0] = GEN11_GRDOM_RENDER,
- [BCS0] = GEN11_GRDOM_BLT,
- [VCS0] = GEN11_GRDOM_MEDIA,
- [VCS1] = GEN11_GRDOM_MEDIA2,
- [VCS2] = GEN11_GRDOM_MEDIA3,
- [VCS3] = GEN11_GRDOM_MEDIA4,
- [VCS4] = GEN11_GRDOM_MEDIA5,
- [VCS5] = GEN11_GRDOM_MEDIA6,
-
[Intel-gfx] [PATCH v2] drm/i915: Use GEM_BUG_ON for obj ptr NULL check
add GEM_BUG_ON to check for NULL ptr dereferences with
obj ptr, this will help catch exceptions in CI tests.
v2 change commit text
Signed-off-by: Pallavi Mishra
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 3 +++
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 218a9b3037c7..997fe73c205b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -906,6 +906,8 @@ vm_access_ttm(struct vm_area_struct *area, unsigned long
addr,
struct drm_i915_gem_object *obj =
i915_ttm_to_gem(area->vm_private_data);
+ GEM_BUG_ON(!obj);
+
if (i915_gem_object_is_readonly(obj) && write)
return -EACCES;
@@ -966,6 +968,7 @@ static const struct drm_i915_gem_object_ops
i915_gem_ttm_obj_ops = {
void i915_ttm_bo_destroy(struct ttm_buffer_object *bo)
{
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+ GEM_BUG_ON(!obj);
i915_gem_object_release_memory_region(obj);
mutex_destroy(>ttm.get_io_page.lock);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 80df9f592407..2b684903a9f5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -371,6 +371,7 @@ int i915_ttm_move_notify(struct ttm_buffer_object *bo)
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
int ret;
+ GEM_BUG_ON(!obj);
ret = i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE);
if (ret)
return ret;
@@ -506,7 +507,7 @@ static void i915_ttm_memcpy_init(struct i915_ttm_memcpy_arg
*arg,
dst_reg = i915_ttm_region(bo->bdev, dst_mem->mem_type);
src_reg = i915_ttm_region(bo->bdev, bo->resource->mem_type);
- GEM_BUG_ON(!dst_reg || !src_reg);
+ GEM_BUG_ON(!dst_reg || !src_reg || !obj);
arg->dst_iter = !i915_ttm_cpu_maps_iomem(dst_mem) ?
ttm_kmap_iter_tt_init(>_dst_iter.tt, dst_ttm) :
--
2.25.1
[Intel-gfx] [PATCH v5 10/11] drm/i915: Use to_gt() helper for GGTT accesses
From: Michał Winiarski
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
Signed-off-by: Michał Winiarski
Cc: Michal Wajdeczko
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
.../gpu/drm/i915/display/intel_plane_initial.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 16
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 6 +++---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +-
.../drm/i915/gem/selftests/i915_gem_client_blt.c | 2 +-
.../drm/i915/gem/selftests/i915_gem_context.c| 2 +-
.../gpu/drm/i915/gem/selftests/i915_gem_mman.c | 16
.../gpu/drm/i915/gem/selftests/i915_gem_object.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 +++---
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 ++--
drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 16
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++---
drivers/gpu/drm/i915/i915_getparam.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 4 ++--
drivers/gpu/drm/i915/selftests/i915_gem.c| 8
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c| 6 +++---
drivers/gpu/drm/i915/selftests/i915_request.c| 2 +-
drivers/gpu/drm/i915/selftests/i915_vma.c| 2 +-
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 6 +++---
26 files changed, 68 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 6efbef7a1fc0..128d62130768 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -595,7 +595,7 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
else if (DISPLAY_VER(i915) == 9)
skl_fbc_program_cfb_stride(fbc);
- if (i915->ggtt.num_fences)
+ if (to_gt(i915)->ggtt->num_fences)
snb_fbc_program_fence(fbc);
intel_de_write(i915, ILK_DPFC_CONTROL,
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index 01ce1d72297f..e4186a0b8edb 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -94,7 +94,7 @@ initial_plane_vma(struct drm_i915_private *i915,
goto err_obj;
}
- vma = i915_vma_instance(obj, >ggtt.vm, NULL);
+ vma = i915_vma_instance(obj, _gt(i915)->ggtt->vm, NULL);
if (IS_ERR(vma))
goto err_obj;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index babfecb17ad1..e5b0f66ea1fe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -174,7 +174,7 @@ i915_gem_context_get_eb_vm(struct i915_gem_context *ctx)
vm = ctx->vm;
if (!vm)
- vm = >i915->ggtt.vm;
+ vm = _gt(ctx->i915)->ggtt->vm;
vm = i915_vm_get(vm);
return vm;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index ec7c4a29a720..3078611d5bfe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1106,7 +1106,7 @@ static inline struct i915_ggtt *cache_to_ggtt(struct
reloc_cache *cache)
{
struct drm_i915_private *i915 =
container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
- return >ggtt;
+ return to_gt(i915)->ggtt;
}
static void reloc_cache_reset(struct reloc_cache *cache, struct
i915_execbuffer *eb)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 581553f688fd..feff49d169a6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -294,7 +294,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *i915 = to_i915(dev);
struct intel_runtime_pm *rpm = >runtime_pm;
- struct i915_ggtt *ggtt = >ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
bool write = area->vm_flags & VM_WRITE;
struct i915_gem_ww_ctx ww;
intel_wakeref_t wakeref;
@@ -387,16 +387,16 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
assert_rpm_wakelock_held(rpm);
/*
Re: [Intel-gfx] [PATCH i-g-t] intel-gpu-top: Add support for per client stats
On 04/12/2021 01:38, Dixit, Ashutosh wrote: On Fri, 03 Dec 2021 07:54:56 -0800, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Use the i915 exported data in /proc//fdinfo to show GPU utilization per DRM client. Didn't we just remove it? Adding it back now? Sorry for the probably dumb question :/ Same feature two implementation flavours. :) Removed the version using API removed from i915 back in April (or so), proposing to add a version using different API (https://patchwork.freedesktop.org/series/92574/). Regards, Tvrtko
[Intel-gfx] [PATCH v5 11/11] drm/i915: Rename i915->gt to i915->gt0
In preparation of the multitile support, highlight the root GT by
calling it gt0 inside the drm i915 private data.
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Lucas De Marchi
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 39a1b5ef64e8..4ab50a04e1fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1008,7 +1008,7 @@ struct drm_i915_private {
struct i915_perf perf;
/* Abstract the submission mechanism (legacy ringbuffer or execlists)
away */
- struct intel_gt gt;
+ struct intel_gt gt0;
struct {
struct i915_gem_contexts {
@@ -1082,7 +1082,7 @@ static inline struct drm_i915_private
*pdev_to_i915(struct pci_dev *pdev)
static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
{
- return >gt;
+ return >gt0;
}
/* Simple iterator over all initialised engines */
--
2.34.1
[Intel-gfx] [PATCH v5 08/11] drm/i915/pxp: Use to_gt() helper
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 5d169624ad60..726c2b5a3fa3 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -14,9 +14,11 @@
#include "intel_pxp_tee.h"
#include "intel_pxp_tee_interface.h"
-static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
+static struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
{
- return _to_i915(i915_kdev)->gt.pxp;
+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+
+ return _gt(i915)->pxp;
}
static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
--
2.34.1
[Intel-gfx] [PATCH v5 00/11] More preparation for multi gt patches
Hi, the first patch concludes the first stage of refactoring which makes the use of intel_gt on the different subsystem. It's taken from Matt's series and it has alread been reviewed. The patch has just been replaced before any multitile patches and I think it can be already pushed. Patch 2-10 are a simple abstraction of the i915->gt which now is under the to_gt() wrapper. This part is mostly taken from Michał. Patch 11 changes i915->gt to i915->gt0. Andi Changelog: == Patchwork: https://patchwork.freedesktop.org/series/97020/ v4 -> v5: - use to_gt() instead of to_root_gt() and use Michał work done previously. - split the /i915->gt/to_gt()/ patch in smaller chunks in order to make review easier. (Thanks Lucas) v3 -> v4: - the intel_gt_init_early() has been split as it was causing some headaches for the order of the early initialization. The split has been done keeping in mind the coming next patch in the series that wil make this a static function. v2 -> v3: - sed -i ... took too much freedom and changed more than it was supposed to. - fix a compile error which did not appear in my local build v1 -> v2: - patch 2: do not use anymore the reference i915->gt but use to_root_gt(), coming from Matt Roper's patch. - fix some comments from Chris. Andi Shyti (3): drm/i915/selftests: Use to_gt() helper drm/i915/pxp: Use to_gt() helper drm/i915: Rename i915->gt to i915->gt0 Michał Winiarski (8): drm/i915: Store backpointer to GT in uncore drm/i915: Introduce to_gt() helper drm/i915/display: Use to_gt() helper drm/i915/gt: Use to_gt() helper drm/i915/gem: Use to_gt() helper drm/i915/gvt: Use to_gt() helper drm/i915: Use to_gt() helper drm/i915: Use to_gt() helper for GGTT accesses .../gpu/drm/i915/display/intel_atomic_plane.c | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 18 +++--- drivers/gpu/drm/i915/display/intel_dpt.c | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- drivers/gpu/drm/i915/display/intel_overlay.c | 2 +- .../drm/i915/display/intel_plane_initial.c| 2 +- .../drm/i915/display/skl_universal_plane.c| 2 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 22 drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +- drivers/gpu/drm/i915/gem/i915_gem_create.c| 2 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 6 +- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 18 +++--- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 6 +- drivers/gpu/drm/i915/gem/i915_gem_pm.c| 8 +-- drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 8 +-- drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 2 +- drivers/gpu/drm/i915/gem/i915_gem_throttle.c | 3 +- drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 12 ++-- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 2 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 4 +- .../i915/gem/selftests/i915_gem_client_blt.c | 4 +- .../drm/i915/gem/selftests/i915_gem_context.c | 12 ++-- .../drm/i915/gem/selftests/i915_gem_migrate.c | 2 +- .../drm/i915/gem/selftests/i915_gem_mman.c| 42 +++--- .../drm/i915/gem/selftests/i915_gem_object.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 ++--- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 6 +- drivers/gpu/drm/i915/gt/intel_gt.c| 11 ++-- drivers/gpu/drm/i915/gt/intel_gt.h| 1 + .../gpu/drm/i915/gt/intel_gt_buffer_pool.c| 7 +-- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 +- drivers/gpu/drm/i915/gt/intel_rps.c | 12 ++-- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/gt/mock_engine.c | 10 ++-- drivers/gpu/drm/i915/gt/selftest_context.c| 2 +- drivers/gpu/drm/i915/gt/selftest_engine.c | 2 +- drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 4 +- .../drm/i915/gt/selftest_engine_heartbeat.c | 4 +- drivers/gpu/drm/i915/gt/selftest_execlists.c | 6 +- drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +-- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +- drivers/gpu/drm/i915/gt/selftest_lrc.c| 2 +- drivers/gpu/drm/i915/gt/selftest_migrate.c| 4 +- drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +- drivers/gpu/drm/i915/gt/selftest_reset.c | 4 +- .../drm/i915/gt/selftest_ring_submission.c| 4 +- drivers/gpu/drm/i915/gt/selftest_slpc.c | 6 +- drivers/gpu/drm/i915/gt/selftest_timeline.c | 6 +- .../gpu/drm/i915/gt/selftest_workarounds.c| 4 +- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 2 +- drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 2 +- .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 2 +- drivers/gpu/drm/i915/gvt/gvt.c| 2 +- drivers/gpu/drm/i915/gvt/scheduler.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 38 ++--- drivers/gpu/drm/i915/i915_debugfs_params.c| 4 +- drivers/gpu/drm/i915/i915_driver.c
[Intel-gfx] [PATCH v5 04/11] drm/i915/gt: Use to_gt() helper
From: Michał Winiarski
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
Signed-off-by: Michał Winiarski
Singed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c| 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 10 +-
drivers/gpu/drm/i915/gt/selftest_context.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_engine.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_engine_cs.c| 4 ++--
drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c | 4 ++--
drivers/gpu/drm/i915/gt/selftest_execlists.c| 6 +++---
drivers/gpu/drm/i915/gt/selftest_gt_pm.c| 8
drivers/gpu/drm/i915/gt/selftest_hangcheck.c| 2 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_migrate.c | 4 ++--
drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_reset.c| 2 +-
drivers/gpu/drm/i915/gt/selftest_ring_submission.c | 4 ++--
drivers/gpu/drm/i915/gt/selftest_slpc.c | 6 +++---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 6 +++---
drivers/gpu/drm/i915/gt/selftest_workarounds.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c | 2 +-
23 files changed, 46 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 8f8bea08e734..9ce85a845105 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -116,7 +116,7 @@ static void set_scheduler_caps(struct drm_i915_private
*i915)
disabled |= (I915_SCHEDULER_CAP_ENABLED |
I915_SCHEDULER_CAP_PRIORITY);
- if (intel_uc_uses_guc_submission(>gt.uc))
+ if (intel_uc_uses_guc_submission(_gt(i915)->uc))
enabled |= I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP;
for (i = 0; i < ARRAY_SIZE(map); i++) {
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 110d3944f9a2..80f78d58aa2e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -1229,7 +1229,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
{
int ret;
- ret = ggtt_probe_hw(>ggtt, >gt);
+ ret = ggtt_probe_hw(>ggtt, to_gt(i915));
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 07ff7ba7b2b7..36eb980d757e 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2302,7 +2302,7 @@ unsigned long i915_read_mch_val(void)
return 0;
with_intel_runtime_pm(>runtime_pm, wakeref) {
- struct intel_ips *ips = >gt.rps.ips;
+ struct intel_ips *ips = _gt(i915)->rps.ips;
spin_lock_irq(_lock);
chipset_val = __ips_chipset_val(ips);
@@ -2329,7 +2329,7 @@ bool i915_gpu_raise(void)
if (!i915)
return false;
- rps = >gt.rps;
+ rps = _gt(i915)->rps;
spin_lock_irq(_lock);
if (rps->max_freq_softlimit < rps->max_freq)
@@ -2356,7 +2356,7 @@ bool i915_gpu_lower(void)
if (!i915)
return false;
- rps = >gt.rps;
+ rps = _gt(i915)->rps;
spin_lock_irq(_lock);
if (rps->max_freq_softlimit > rps->min_freq)
@@ -2382,7 +2382,7 @@ bool i915_gpu_busy(void)
if (!i915)
return false;
- ret = i915->gt.awake;
+ ret = to_gt(i915)->awake;
drm_dev_put(>drm);
return ret;
@@ -2405,11 +2405,11 @@ bool i915_gpu_turbo_disable(void)
if (!i915)
return false;
- rps = >gt.rps;
+ rps = _gt(i915)->rps;
spin_lock_irq(_lock);
rps->max_freq_softlimit = rps->min_freq;
- ret = !__gen5_rps_set(>gt.rps, rps->min_freq);
+ ret = !__gen5_rps_set(_gt(i915)->rps, rps->min_freq);
spin_unlock_irq(_lock);
drm_dev_put(>drm);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3113266c286e..ab3277a3d593 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -929,7 +929,7 @@ hsw_gt_workarounds_init(struct intel_gt *gt, struct
i915_wa_list *wal)
static void
gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- const struct
[Intel-gfx] [PATCH v5 01/11] drm/i915: Store backpointer to GT in uncore
From: Michał Winiarski
We now support a per-gt uncore, yet we're not able to infer which GT
we're operating upon. Let's store a backpointer for now.
Signed-off-by: Michał Winiarski
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
drivers/gpu/drm/i915/i915_driver.c | 5 +++--
drivers/gpu/drm/i915/intel_uncore.c | 9 +
drivers/gpu/drm/i915/intel_uncore.h | 3 ++-
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 4 ++--
drivers/gpu/drm/i915/selftests/mock_uncore.c | 2 +-
7 files changed, 21 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f2422d48be32..f98f0fb21efb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -25,11 +25,8 @@
#include "shmem_utils.h"
#include "pxp/intel_pxp.h"
-void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
+void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
{
- gt->i915 = i915;
- gt->uncore = >uncore;
-
spin_lock_init(>irq_lock);
INIT_LIST_HEAD(>closed_vma);
@@ -48,6 +45,12 @@ void intel_gt_init_early(struct intel_gt *gt, struct
drm_i915_private *i915)
intel_rps_init_early(>rps);
}
+void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
+{
+ gt->i915 = i915;
+ gt->uncore = >uncore;
+}
+
int intel_gt_probe_lmem(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 74e771871a9b..3ace129eb2af 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -35,6 +35,7 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc
*huc)
}
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
+void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt);
int intel_gt_probe_lmem(struct intel_gt *gt);
int intel_gt_init_mmio(struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index bbc99fc5888f..fb828ef25a03 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -315,8 +315,9 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
intel_device_info_subplatform_init(dev_priv);
intel_step_init(dev_priv);
+ intel_gt_init_early(_priv->gt, dev_priv);
intel_uncore_mmio_debug_init_early(_priv->mmio_debug);
- intel_uncore_init_early(_priv->uncore, dev_priv);
+ intel_uncore_init_early(_priv->uncore, _priv->gt);
spin_lock_init(_priv->irq_lock);
spin_lock_init(_priv->gpu_error.lock);
@@ -347,7 +348,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
intel_wopcm_init_early(_priv->wopcm);
- intel_gt_init_early(_priv->gt, dev_priv);
+ __intel_gt_init_early(_priv->gt, dev_priv);
i915_gem_init_early(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index abdac78d3976..fc25ebf1a593 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2061,12 +2061,13 @@ void intel_uncore_cleanup_mmio(struct intel_uncore
*uncore)
}
void intel_uncore_init_early(struct intel_uncore *uncore,
-struct drm_i915_private *i915)
+struct intel_gt *gt)
{
spin_lock_init(>lock);
- uncore->i915 = i915;
- uncore->rpm = >runtime_pm;
- uncore->debug = >mmio_debug;
+ uncore->i915 = gt->i915;
+ uncore->gt = gt;
+ uncore->rpm = >i915->runtime_pm;
+ uncore->debug = >i915->mmio_debug;
}
static void uncore_raw_init(struct intel_uncore *uncore)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index d1d17b04e29f..210fe2a71612 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -129,6 +129,7 @@ struct intel_uncore {
void __iomem *regs;
struct drm_i915_private *i915;
+ struct intel_gt *gt;
struct intel_runtime_pm *rpm;
spinlock_t lock; /** lock is also taken in irq contexts. */
@@ -217,7 +218,7 @@ u32 intel_uncore_read_with_mcr_steering(struct intel_uncore
*uncore,
void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
void intel_uncore_init_early(struct intel_uncore *uncore,
-struct drm_i915_private *i915);
+struct intel_gt *gt);
int intel_uncore_setup_mmio(struct intel_uncore
[Intel-gfx] [PATCH v5 05/11] drm/i915/gem: Use to_gt() helper
From: Michał Winiarski
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
Signed-off-by: Michał Winiarski
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 22
drivers/gpu/drm/i915/gem/i915_gem_create.c| 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 4 +--
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 6 +++--
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 6 ++---
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_throttle.c | 3 ++-
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 12 -
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 2 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 4 +--
.../i915/gem/selftests/i915_gem_client_blt.c | 2 +-
.../drm/i915/gem/selftests/i915_gem_context.c | 10 +++
.../drm/i915/gem/selftests/i915_gem_migrate.c | 2 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 26 ++-
15 files changed, 55 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 347dab952e90..cad3f0b2be9e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -237,7 +237,7 @@ static int proto_context_set_persistence(struct
drm_i915_private *i915,
* colateral damage, and we should not pretend we can by
* exposing the interface.
*/
- if (!intel_has_reset_engine(>gt))
+ if (!intel_has_reset_engine(to_gt(i915)))
return -ENODEV;
pc->user_flags &= ~BIT(UCONTEXT_PERSISTENCE);
@@ -254,7 +254,7 @@ static int proto_context_set_protected(struct
drm_i915_private *i915,
if (!protected) {
pc->uses_protected_content = false;
- } else if (!intel_pxp_is_enabled(>gt.pxp)) {
+ } else if (!intel_pxp_is_enabled(_gt(i915)->pxp)) {
ret = -ENODEV;
} else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) ||
!(pc->user_flags & BIT(UCONTEXT_BANNABLE))) {
@@ -268,8 +268,8 @@ static int proto_context_set_protected(struct
drm_i915_private *i915,
*/
pc->pxp_wakeref = intel_runtime_pm_get(>runtime_pm);
- if (!intel_pxp_is_active(>gt.pxp))
- ret = intel_pxp_start(>gt.pxp);
+ if (!intel_pxp_is_active(_gt(i915)->pxp))
+ ret = intel_pxp_start(_gt(i915)->pxp);
}
return ret;
@@ -571,7 +571,7 @@ set_proto_ctx_engines_parallel_submit(struct
i915_user_extension __user *base,
intel_engine_mask_t prev_mask;
/* FIXME: This is NIY for execlists */
- if (!(intel_uc_uses_guc_submission(>gt.uc)))
+ if (!(intel_uc_uses_guc_submission(_gt(i915)->uc)))
return -ENODEV;
if (get_user(slot, >engine_index))
@@ -833,7 +833,7 @@ static int set_proto_ctx_sseu(struct drm_i915_file_private
*fpriv,
sseu = >legacy_rcs_sseu;
}
- ret = i915_gem_user_to_context_sseu(>gt, _sseu, sseu);
+ ret = i915_gem_user_to_context_sseu(to_gt(i915), _sseu, sseu);
if (ret)
return ret;
@@ -1044,7 +1044,7 @@ static struct i915_gem_engines *alloc_engines(unsigned
int count)
static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx,
struct intel_sseu rcs_sseu)
{
- const struct intel_gt *gt = >i915->gt;
+ const struct intel_gt *gt = to_gt(ctx->i915);
struct intel_engine_cs *engine;
struct i915_gem_engines *e, *err;
enum intel_engine_id id;
@@ -1521,7 +1521,7 @@ static int __context_set_persistence(struct
i915_gem_context *ctx, bool state)
* colateral damage, and we should not pretend we can by
* exposing the interface.
*/
- if (!intel_has_reset_engine(>i915->gt))
+ if (!intel_has_reset_engine(to_gt(ctx->i915)))
return -ENODEV;
i915_gem_context_clear_persistence(ctx);
@@ -1559,7 +1559,7 @@ i915_gem_create_context(struct drm_i915_private *i915,
} else if (HAS_FULL_PPGTT(i915)) {
struct i915_ppgtt *ppgtt;
- ppgtt = i915_ppgtt_create(>gt, 0);
+ ppgtt = i915_ppgtt_create(to_gt(i915), 0);
if (IS_ERR(ppgtt)) {
drm_dbg(>drm, "PPGTT setup failed (%ld)\n",
PTR_ERR(ppgtt));
@@ -1742,7 +1742,7 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void
*data,
if (args->flags)
return -EINVAL;
- ppgtt = i915_ppgtt_create(>gt, 0);
+ ppgtt = i915_ppgtt_create(to_gt(i915),
[Intel-gfx] [PATCH v5 07/11] drm/i915/selftests: Use to_gt() helper
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
Signed-off-by: Andi Shyti
Cc: Michał Winiarski
---
drivers/gpu/drm/i915/selftests/i915_active.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem.c | 2 +-
.../gpu/drm/i915/selftests/i915_gem_evict.c | 6 ++--
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 +--
drivers/gpu/drm/i915/selftests/i915_perf.c| 2 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 10 +++
.../gpu/drm/i915/selftests/i915_selftest.c| 4 +--
.../gpu/drm/i915/selftests/igt_flush_test.c | 2 +-
.../gpu/drm/i915/selftests/igt_live_test.c| 4 +--
.../drm/i915/selftests/intel_memory_region.c | 4 +--
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 30 +--
drivers/gpu/drm/i915/selftests/mock_gtt.c | 6 ++--
drivers/gpu/drm/i915/selftests/mock_uncore.c | 2 +-
14 files changed, 40 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_active.c
b/drivers/gpu/drm/i915/selftests/i915_active.c
index 61bf4560d8af..2dac9be1de58 100644
--- a/drivers/gpu/drm/i915/selftests/i915_active.c
+++ b/drivers/gpu/drm/i915/selftests/i915_active.c
@@ -254,7 +254,7 @@ int i915_active_live_selftests(struct drm_i915_private
*i915)
SUBTEST(live_active_barrier),
};
- if (intel_gt_is_wedged(>gt))
+ if (intel_gt_is_wedged(to_gt(i915)))
return 0;
return i915_subtests(tests, i915);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c
b/drivers/gpu/drm/i915/selftests/i915_gem.c
index 152d9ab135b1..b5576888cd78 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -248,7 +248,7 @@ int i915_gem_live_selftests(struct drm_i915_private *i915)
SUBTEST(igt_gem_ww_ctx),
};
- if (intel_gt_is_wedged(>gt))
+ if (intel_gt_is_wedged(to_gt(i915)))
return 0;
return i915_live_subtests(tests, i915);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 7e0658a77659..75b709c26dd3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -545,7 +545,7 @@ int i915_gem_evict_mock_selftests(void)
return -ENOMEM;
with_intel_runtime_pm(>runtime_pm, wakeref)
- err = i915_subtests(tests, >gt);
+ err = i915_subtests(tests, to_gt(i915));
mock_destroy_device(i915);
return err;
@@ -557,8 +557,8 @@ int i915_gem_evict_live_selftests(struct drm_i915_private
*i915)
SUBTEST(igt_evict_contexts),
};
- if (intel_gt_is_wedged(>gt))
+ if (intel_gt_is_wedged(to_gt(i915)))
return 0;
- return intel_gt_live_subtests(tests, >gt);
+ return intel_gt_live_subtests(tests, to_gt(i915));
}
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 46f4236039a9..48123c3e1ff0 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -155,7 +155,7 @@ static int igt_ppgtt_alloc(void *arg)
if (!HAS_PPGTT(dev_priv))
return 0;
- ppgtt = i915_ppgtt_create(_priv->gt, 0);
+ ppgtt = i915_ppgtt_create(to_gt(dev_priv), 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
@@ -1053,7 +1053,7 @@ static int exercise_ppgtt(struct drm_i915_private
*dev_priv,
if (IS_ERR(file))
return PTR_ERR(file);
- ppgtt = i915_ppgtt_create(_priv->gt, 0);
+ ppgtt = i915_ppgtt_create(to_gt(dev_priv), 0);
if (IS_ERR(ppgtt)) {
err = PTR_ERR(ppgtt);
goto out_free;
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c
b/drivers/gpu/drm/i915/selftests/i915_perf.c
index 9e9a6cb1d9e5..88db2e3d81d0 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf.c
+++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
@@ -424,7 +424,7 @@ int i915_perf_live_selftests(struct drm_i915_private *i915)
if (!perf->metrics_kobj || !perf->ops.enable_metric_set)
return 0;
- if (intel_gt_is_wedged(>gt))
+ if (intel_gt_is_wedged(to_gt(i915)))
return 0;
err = alloc_empty_config(>perf);
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 9979ef9197cd..92a859b34190 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -841,7 +841,7 @@ static struct i915_vma *empty_batch(struct drm_i915_private
*i915)
__i915_gem_object_flush_map(obj, 0, 64);
i915_gem_object_unpin_map(obj);
- intel_gt_chipset_flush(>gt);
+
[Intel-gfx] [PATCH v5 02/11] drm/i915: Introduce to_gt() helper
From: Michał Winiarski
To allow further refactoring and abstract away the fact that GT is
stored inside i915 private.
No functional changes.
Signed-off-by: Michał Winiarski
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c | 7 +--
drivers/gpu/drm/i915/i915_drv.h| 5 +
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
index acc49c56a9f3..9db3dcbd917f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
@@ -9,11 +9,6 @@
#include "intel_engine_pm.h"
#include "intel_gt_buffer_pool.h"
-static struct intel_gt *to_gt(struct intel_gt_buffer_pool *pool)
-{
- return container_of(pool, struct intel_gt, buffer_pool);
-}
-
static struct list_head *
bucket_for_size(struct intel_gt_buffer_pool *pool, size_t sz)
{
@@ -141,7 +136,7 @@ static struct intel_gt_buffer_pool_node *
node_create(struct intel_gt_buffer_pool *pool, size_t sz,
enum i915_map_type type)
{
- struct intel_gt *gt = to_gt(pool);
+ struct intel_gt *gt = container_of(pool, struct intel_gt, buffer_pool);
struct intel_gt_buffer_pool_node *node;
struct drm_i915_gem_object *obj;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 85bb8d3107f0..d43b08b80b0d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1080,6 +1080,11 @@ static inline struct drm_i915_private
*pdev_to_i915(struct pci_dev *pdev)
return pci_get_drvdata(pdev);
}
+static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
+{
+ return >gt;
+}
+
/* Simple iterator over all initialised engines */
#define for_each_engine(engine__, dev_priv__, id__) \
for ((id__) = 0; \
--
2.34.1
[Intel-gfx] [PATCH v5 06/11] drm/i915/gvt: Use to_gt() helper
From: Michał Winiarski Use to_gt() helper consistently throughout the codebase. Pure mechanical s/i915->gt/to_gt(i915). No functional changes. Signed-off-by: Michał Winiarski Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gvt/gvt.c | 2 +- drivers/gpu/drm/i915/gvt/scheduler.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c index cbac409f6c8a..f0b69e4dcb52 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.c +++ b/drivers/gpu/drm/i915/gvt/gvt.c @@ -205,7 +205,7 @@ int intel_gvt_init_device(struct drm_i915_private *i915) spin_lock_init(>scheduler.mmio_context_lock); mutex_init(>lock); mutex_init(>sched_lock); - gvt->gt = >gt; + gvt->gt = to_gt(i915); i915->gvt = gvt; init_device_info(gvt); diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 6c804102528b..42a0c9ae0a73 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -1386,7 +1386,7 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu) enum intel_engine_id i; int ret; - ppgtt = i915_ppgtt_create(>gt, I915_BO_ALLOC_PM_EARLY); + ppgtt = i915_ppgtt_create(to_gt(i915), I915_BO_ALLOC_PM_EARLY); if (IS_ERR(ppgtt)) return PTR_ERR(ppgtt); -- 2.34.1
[Intel-gfx] [PATCH v5 09/11] drm/i915: Use to_gt() helper
From: Michał Winiarski
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
Signed-off-by: Michał Winiarski
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/i915_debugfs.c| 38 +++
drivers/gpu/drm/i915/i915_debugfs_params.c | 4 +-
drivers/gpu/drm/i915/i915_driver.c | 32 ++---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
drivers/gpu/drm/i915/i915_gem.c| 16 +++
drivers/gpu/drm/i915/i915_getparam.c | 10 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
drivers/gpu/drm/i915/i915_irq.c| 56 +++---
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/i915_pmu.c| 14 +++---
drivers/gpu/drm/i915/i915_query.c | 2 +-
drivers/gpu/drm/i915/i915_sysfs.c | 22 -
drivers/gpu/drm/i915/intel_gvt.c | 2 +-
drivers/gpu/drm/i915/intel_wopcm.c | 2 +-
14 files changed, 103 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 390d541f64ea..0783baf5514f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -66,7 +66,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
intel_device_info_print_static(INTEL_INFO(i915), );
intel_device_info_print_runtime(RUNTIME_INFO(i915), );
i915_print_iommu_status(i915, );
- intel_gt_info_print(>gt.info, );
+ intel_gt_info_print(_gt(i915)->info, );
intel_driver_caps_print(>caps, );
kernel_param_lock(THIS_MODULE);
@@ -294,7 +294,7 @@ static int i915_gpu_info_open(struct inode *inode, struct
file *file)
gpu = NULL;
with_intel_runtime_pm(>runtime_pm, wakeref)
- gpu = i915_gpu_coredump(>gt, ALL_ENGINES);
+ gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES);
if (IS_ERR(gpu))
return PTR_ERR(gpu);
@@ -352,7 +352,7 @@ static const struct file_operations i915_error_state_fops =
{
static int i915_frequency_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *i915 = node_to_i915(m->private);
- struct intel_gt *gt = >gt;
+ struct intel_gt *gt = to_gt(i915);
struct drm_printer p = drm_seq_file_printer(m);
intel_gt_pm_frequency_dump(gt, );
@@ -440,11 +440,11 @@ static int i915_swizzle_info(struct seq_file *m, void
*data)
static int i915_rps_boost_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct intel_rps *rps = _priv->gt.rps;
+ struct intel_rps *rps = _gt(dev_priv)->rps;
seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));
seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps)));
- seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake));
+ seq_printf(m, "GPU busy? %s\n", yesno(to_gt(dev_priv)->awake));
seq_printf(m, "Boosts outstanding? %d\n",
atomic_read(>num_waiters));
seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
@@ -477,7 +477,7 @@ static int i915_runtime_pm_status(struct seq_file *m, void
*unused)
seq_printf(m, "Runtime power status: %s\n",
enableddisabled(!dev_priv->power_domains.init_wakeref));
- seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
+ seq_printf(m, "GPU idle: %s\n", yesno(!to_gt(dev_priv)->awake));
seq_printf(m, "IRQs disabled: %s\n",
yesno(!intel_irqs_enabled(dev_priv)));
#ifdef CONFIG_PM
@@ -509,18 +509,18 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
wakeref = intel_runtime_pm_get(>runtime_pm);
seq_printf(m, "GT awake? %s [%d], %llums\n",
- yesno(i915->gt.awake),
- atomic_read(>gt.wakeref.count),
- ktime_to_ms(intel_gt_get_awake_time(>gt)));
+ yesno(to_gt(i915)->awake),
+ atomic_read(_gt(i915)->wakeref.count),
+ ktime_to_ms(intel_gt_get_awake_time(to_gt(i915;
seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
- i915->gt.clock_frequency,
- i915->gt.clock_period_ns);
+ to_gt(i915)->clock_frequency,
+ to_gt(i915)->clock_period_ns);
p = drm_seq_file_printer(m);
for_each_uabi_engine(engine, i915)
intel_engine_dump(engine, , "%s\n", engine->name);
- intel_gt_show_timelines(>gt, , i915_request_show_with_schedule);
+ intel_gt_show_timelines(to_gt(i915), ,
i915_request_show_with_schedule);
intel_runtime_pm_put(>runtime_pm, wakeref);
@@ -559,14 +559,14 @@ static int i915_wedged_get(void *data, u64 *val)
{
struct drm_i915_private *i915 = data;
- return
[Intel-gfx] [PATCH v5 03/11] drm/i915/display: Use to_gt() helper
From: Michał Winiarski
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
Signed-off-by: Michał Winiarski
Signed-off-by: Andi Shyti
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display.c | 18 +-
drivers/gpu/drm/i915/display/intel_dpt.c | 2 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
.../gpu/drm/i915/display/skl_universal_plane.c | 2 +-
5 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 27b8f99dd099..39f5c77c63f6 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -818,7 +818,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
* maximum clocks following a vblank miss (see do_rps_boost()).
*/
if (!state->rps_interactive) {
- intel_rps_mark_interactive(_priv->gt.rps, true);
+ intel_rps_mark_interactive(_gt(dev_priv)->rps, true);
state->rps_interactive = true;
}
@@ -852,7 +852,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
return;
if (state->rps_interactive) {
- intel_rps_mark_interactive(_priv->gt.rps, false);
+ intel_rps_mark_interactive(_gt(dev_priv)->rps, false);
state->rps_interactive = false;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 128d4943a43b..b5cab57a26a6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -841,7 +841,7 @@ __intel_display_resume(struct drm_device *dev,
static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
{
return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
- intel_has_gpu_reset(_priv->gt));
+ intel_has_gpu_reset(to_gt(dev_priv)));
}
void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
@@ -860,14 +860,14 @@ void intel_display_prepare_reset(struct drm_i915_private
*dev_priv)
return;
/* We have a modeset vs reset deadlock, defensively unbreak it. */
- set_bit(I915_RESET_MODESET, _priv->gt.reset.flags);
+ set_bit(I915_RESET_MODESET, _gt(dev_priv)->reset.flags);
smp_mb__after_atomic();
- wake_up_bit(_priv->gt.reset.flags, I915_RESET_MODESET);
+ wake_up_bit(_gt(dev_priv)->reset.flags, I915_RESET_MODESET);
if (atomic_read(_priv->gpu_error.pending_fb_pin)) {
drm_dbg_kms(_priv->drm,
"Modeset potentially stuck, unbreaking through
wedging\n");
- intel_gt_set_wedged(_priv->gt);
+ intel_gt_set_wedged(to_gt(dev_priv));
}
/*
@@ -918,7 +918,7 @@ void intel_display_finish_reset(struct drm_i915_private
*dev_priv)
return;
/* reset doesn't touch the display */
- if (!test_bit(I915_RESET_MODESET, _priv->gt.reset.flags))
+ if (!test_bit(I915_RESET_MODESET, _gt(dev_priv)->reset.flags))
return;
state = fetch_and_zero(_priv->modeset_restore_state);
@@ -956,7 +956,7 @@ void intel_display_finish_reset(struct drm_i915_private
*dev_priv)
drm_modeset_acquire_fini(ctx);
mutex_unlock(>mode_config.mutex);
- clear_bit_unlock(I915_RESET_MODESET, _priv->gt.reset.flags);
+ clear_bit_unlock(I915_RESET_MODESET, _gt(dev_priv)->reset.flags);
}
static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
@@ -8564,19 +8564,19 @@ static void intel_atomic_commit_fence_wait(struct
intel_atomic_state *intel_stat
for (;;) {
prepare_to_wait(_state->commit_ready.wait,
_fence, TASK_UNINTERRUPTIBLE);
- prepare_to_wait(bit_waitqueue(_priv->gt.reset.flags,
+ prepare_to_wait(bit_waitqueue(_gt(dev_priv)->reset.flags,
I915_RESET_MODESET),
_reset, TASK_UNINTERRUPTIBLE);
if (i915_sw_fence_done(_state->commit_ready) ||
- test_bit(I915_RESET_MODESET, _priv->gt.reset.flags))
+ test_bit(I915_RESET_MODESET, _gt(dev_priv)->reset.flags))
break;
schedule();
}
finish_wait(_state->commit_ready.wait, _fence);
- finish_wait(bit_waitqueue(_priv->gt.reset.flags,
+ finish_wait(bit_waitqueue(_gt(dev_priv)->reset.flags,
I915_RESET_MODESET),
_reset);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index 963ca7155b06..ce760402a89a 100644
---
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Rollback seqno when request creation fails (rev2)
== Series Details == Series: drm/i915: Rollback seqno when request creation fails (rev2) URL : https://patchwork.freedesktop.org/series/97562/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10963_full -> Patchwork_21756_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21756_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21756_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21756_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@dmabuf: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/shard-skl1/igt@i915_selftest@l...@dmabuf.html Known issues Here are the changes found in Patchwork_21756_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-kbl: [PASS][2] -> [DMESG-WARN][3] ([i915#180]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-kbl2/igt@gem_ctx_isolation@preservation...@bcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/shard-kbl4/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_eio@in-flight-contexts-10ms: - shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-tglb2/igt@gem_...@in-flight-contexts-10ms.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/shard-tglb6/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_exec_capture@pi@bcs0: - shard-skl: [PASS][6] -> [INCOMPLETE][7] ([i915#4547]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-skl4/igt@gem_exec_capture@p...@bcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/shard-skl10/igt@gem_exec_capture@p...@bcs0.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2846]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk3/igt@gem_exec_f...@basic-deadline.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/shard-glk7/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share: - shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271]) +7 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/shard-snb4/igt@gem_exec_f...@basic-none-share.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/shard-kbl6/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-iclb2/igt@gem_exec_fair@basic-p...@bcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/shard-iclb1/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][17] -> [SKIP][18] ([fdo#109271]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_huc_copy@huc-copy: - shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/shard-skl9/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-multi: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21756/shard-apl7/igt@gem_lmem_swapp...@parallel-multi.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-kbl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613]) +2 similar issues [21]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Use local pointer ttm for __i915_ttm_move
== Series Details == Series: drm/i915/gem: Use local pointer ttm for __i915_ttm_move URL : https://patchwork.freedesktop.org/series/97572/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10963_full -> Patchwork_21754_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21754_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21754_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21754_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gtt: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/shard-skl8/igt@i915_selftest@l...@gtt.html Known issues Here are the changes found in Patchwork_21754_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fair@basic-none-share: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271]) +7 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/shard-snb5/igt@gem_exec_f...@basic-none-share.html * igt@gem_exec_fair@basic-none@rcs0: - shard-kbl: [PASS][3] -> [FAIL][4] ([i915#2842]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-kbl4/igt@gem_exec_fair@basic-n...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/shard-kbl7/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-iclb2/igt@gem_exec_fair@basic-p...@bcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/shard-iclb7/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_huc_copy@huc-copy: - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/shard-skl9/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-verify-multi: - shard-kbl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/shard-kbl7/igt@gem_lmem_swapp...@heavy-verify-multi.html * igt@gem_pwrite@basic-exhaustion: - shard-kbl: NOTRUN -> [WARN][11] ([i915#2658]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/shard-kbl1/igt@gem_pwr...@basic-exhaustion.html * igt@gem_softpin@noreloc-s3: - shard-kbl: NOTRUN -> [DMESG-WARN][12] ([i915#180]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/shard-kbl7/igt@gem_soft...@noreloc-s3.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#3323]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/shard-apl6/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gen7_exec_parse@cmd-crossing-page: - shard-tglb: NOTRUN -> [SKIP][14] ([fdo#109289]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/shard-tglb6/igt@gen7_exec_pa...@cmd-crossing-page.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1436] / [i915#716]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-skl1/igt@gen9_exec_pa...@allowed-single.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/shard-skl8/igt@gen9_exec_pa...@allowed-single.html * igt@i915_selftest@live@gt_pm: - shard-skl: NOTRUN -> [DMESG-FAIL][17] ([i915#1886] / [i915#2291]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/shard-skl8/igt@i915_selftest@live@gt_pm.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3777]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21754/shard-kbl7/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][19] ([i915#3743]) [19]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftests
== Series Details == Series: drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftests URL : https://patchwork.freedesktop.org/series/97577/ State : success == Summary == CI Bug Log - changes from CI_DRM_10963_full -> Patchwork_21755_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_21755_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-kbl2/igt@gem_ctx_isolation@preservation...@vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#2846]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk3/igt@gem_exec_f...@basic-deadline.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/shard-glk1/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-tglb2/igt@gem_exec_fair@basic-f...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/shard-tglb5/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/shard-kbl2/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_parallel@engines@basic: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#118]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk8/igt@gem_exec_parallel@engi...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/shard-glk6/igt@gem_exec_parallel@engi...@basic.html * igt@gem_huc_copy@huc-copy: - shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/shard-skl6/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-verify-multi: - shard-kbl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/shard-kbl7/igt@gem_lmem_swapp...@heavy-verify-multi.html * igt@gem_softpin@noreloc-s3: - shard-kbl: NOTRUN -> [DMESG-WARN][13] ([i915#180]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/shard-kbl7/igt@gem_soft...@noreloc-s3.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#3323]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/shard-apl8/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gen7_exec_parse@cmd-crossing-page: - shard-tglb: NOTRUN -> [SKIP][15] ([fdo#109289]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/shard-tglb6/igt@gen7_exec_pa...@cmd-crossing-page.html * igt@i915_selftest@live@gt_pm: - shard-skl: NOTRUN -> [DMESG-FAIL][16] ([i915#1886] / [i915#2291]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/shard-skl4/igt@i915_selftest@live@gt_pm.html * igt@i915_suspend@debugfs-reader: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-apl7/igt@i915_susp...@debugfs-reader.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/shard-apl8/igt@i915_susp...@debugfs-reader.html * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind@edp-1-pipe-a: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-skl9/igt@kms_atomic_transition@plane-use-after-nonblocking-unb...@edp-1-pipe-a.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/shard-skl10/igt@kms_atomic_transition@plane-use-after-nonblocking-unb...@edp-1-pipe-a.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-kbl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3777]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21755/shard-kbl7/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-skl: NOTRUN ->
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Use local pointer for __i915_ttm_move
== Series Details == Series: drm/i915/gem: Use local pointer for __i915_ttm_move URL : https://patchwork.freedesktop.org/series/97571/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10963_full -> Patchwork_21753_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21753_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21753_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21753_full: ### IGT changes ### Possible regressions * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html Warnings * igt@kms_psr2_su@page_flip-p010: - shard-iclb: [SKIP][3] ([i915#658]) -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-iclb5/igt@kms_psr2_su@page_flip-p010.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html Known issues Here are the changes found in Patchwork_21753_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-glk: ([PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29]) -> ([PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [FAIL][51], [PASS][52], [PASS][53], [PASS][54]) ([i915#4392]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk1/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk9/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk9/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk9/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk8/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk8/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk8/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk7/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk7/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk6/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk5/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk5/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk5/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk5/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk4/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk4/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk1/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk4/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk3/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk3/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk3/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk2/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk2/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk2/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/shard-glk4/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/shard-glk5/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/shard-glk5/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21753/shard-glk6/boot.html [34]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for Update to GuC version 69.0.0
== Series Details == Series: Update to GuC version 69.0.0 URL : https://patchwork.freedesktop.org/series/97564/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10963_full -> Patchwork_21752_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21752_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21752_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21752_full: ### IGT changes ### Possible regressions * igt@kms_psr@cursor_mmap_gtt: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-tglb8/igt@kms_psr@cursor_mmap_gtt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/shard-tglb8/igt@kms_psr@cursor_mmap_gtt.html Known issues Here are the changes found in Patchwork_21752_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#2846]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk3/igt@gem_exec_f...@basic-deadline.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/shard-glk5/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-tglb2/igt@gem_exec_fair@basic-f...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/shard-tglb2/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none-share: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271]) +7 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/shard-snb7/igt@gem_exec_f...@basic-none-share.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-iclb2/igt@gem_exec_fair@basic-p...@bcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/shard-iclb8/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_huc_copy@huc-copy: - shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#2190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/shard-skl10/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-multi: - shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/shard-apl7/igt@gem_lmem_swapp...@parallel-multi.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/shard-kbl4/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_pwrite@basic-exhaustion: - shard-kbl: NOTRUN -> [WARN][15] ([i915#2658]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/shard-kbl3/igt@gem_pwr...@basic-exhaustion.html * igt@gem_softpin@noreloc-s3: - shard-kbl: NOTRUN -> [DMESG-WARN][16] ([i915#180]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/shard-kbl7/igt@gem_soft...@noreloc-s3.html * igt@gem_spin_batch@engines@rcs0: - shard-apl: [PASS][17] -> [FAIL][18] ([i915#2898]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10963/shard-apl8/igt@gem_spin_batch@engi...@rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/shard-apl2/igt@gem_spin_batch@engi...@rcs0.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3323]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/shard-apl2/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gen7_exec_parse@cmd-crossing-page: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#109289]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21752/shard-tglb1/igt@gen7_exec_pa...@cmd-crossing-page.html * igt@i915_pm_dc@dc6-dpms: - shard-kbl: NOTRUN -> [FAIL][21]
