[Intel-gfx] ✗ Fi.CI.IGT: failure for More preparation for multi gt patches

[Patchwork]

== Series Details ==

Series: More preparation for multi gt patches
URL   : https://patchwork.freedesktop.org/series/98032/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11002_full -> Patchwork_21849_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_21849_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21849_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_21849_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@i915_suspend@sysfs-reader:
- shard-skl:  [PASS][2] -> [INCOMPLETE][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-skl8/igt@i915_susp...@sysfs-reader.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/shard-skl10/igt@i915_susp...@sysfs-reader.html

  
Known issues


  Here are the changes found in Patchwork_21849_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-snb:  ([PASS][4], [PASS][5], [PASS][6], [PASS][7], 
[PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], 
[PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], 
[PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], 
[PASS][26], [PASS][27], [PASS][28]) -> ([PASS][29], [PASS][30], [PASS][31], 
[PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], 
[PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [FAIL][43], 
[PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], 
[PASS][50], [PASS][51], [PASS][52], [PASS][53]) ([i915#4338])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb7/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb7/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb7/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb7/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb6/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb6/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb6/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb6/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb5/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb5/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb5/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb5/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb4/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb4/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb4/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb4/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb4/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb2/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb2/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb2/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb2/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb2/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-snb2/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/shard-snb7/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/shard-snb7/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/shard-snb7/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/shard-snb7/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/shard-snb7/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/shard-snb7/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/shard-snb6/boot.html
   

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: remove writeback hook

[Patchwork]

== Series Details ==

Series: drm/i915: remove writeback hook
URL   : https://patchwork.freedesktop.org/series/98029/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11002_full -> Patchwork_21848_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_21848_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_atomic@atomic_plane_damage:
- {shard-rkl}:NOTRUN -> [SKIP][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/shard-rkl-2/igt@kms_atomic@atomic_plane_damage.html

  
Known issues


  Here are the changes found in Patchwork_21848_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@display-4x:
- shard-iclb: NOTRUN -> [SKIP][2] ([i915#1839])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/shard-iclb5/igt@feature_discov...@display-4x.html

  * igt@feature_discovery@psr2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#658])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-iclb2/igt@feature_discov...@psr2.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/shard-iclb4/igt@feature_discov...@psr2.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][5] -> [TIMEOUT][6] ([i915#3063] / [i915#3648])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-tglb5/igt@gem_...@unwedge-stress.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/shard-tglb8/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  [PASS][7] -> [INCOMPLETE][8] ([i915#4547])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-skl4/igt@gem_exec_capture@p...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/shard-skl7/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-glk5/igt@gem_exec_fair@basic-none-r...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/shard-glk3/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-none@vecs0:
- shard-apl:  [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-apl7/igt@gem_exec_fair@basic-n...@vecs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842]) +2 similar 
issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-tglb8/igt@gem_exec_fair@basic-p...@bcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/shard-tglb7/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/shard-kbl6/igt@gem_lmem_swapp...@heavy-verify-multi.html

  * igt@gem_lmem_swapping@parallel-multi:
- shard-apl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/shard-apl3/igt@gem_lmem_swapp...@parallel-multi.html
- shard-skl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/shard-skl10/igt@gem_lmem_swapp...@parallel-multi.html
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#4613]) +1 similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/shard-tglb5/igt@gem_lmem_swapp...@parallel-multi.html

  * igt@gem_lmem_swapping@smem-oom:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#4613])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/shard-iclb7/igt@gem_lmem_swapp...@smem-oom.html

  * igt@gem_mmap_gtt@coherency:
- shard-iclb: NOTRUN -> [SKIP][21] ([fdo#109292])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/shard-iclb5/igt@gem_mmap_...@coherency.html

  * igt@gem_pxp@fail-invalid-protected-context:
- shard-iclb: NOTRUN -> [SKIP][22] ([i915#4270])
   

[Intel-gfx] ✗ Fi.CI.IGT: failure for Fix stealing guc_ids + test (rev3)

[Patchwork]

== Series Details ==

Series: Fix stealing guc_ids + test (rev3)
URL   : https://patchwork.freedesktop.org/series/97896/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11002_full -> Patchwork_21847_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_21847_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21847_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_21847_full:

### IGT changes ###

 Possible regressions 

  * igt@perf@invalid-oa-metric-set-id:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-iclb5/igt@p...@invalid-oa-metric-set-id.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/shard-iclb4/igt@p...@invalid-oa-metric-set-id.html

  
Known issues


  Here are the changes found in Patchwork_21847_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@display-4x:
- shard-iclb: NOTRUN -> [SKIP][3] ([i915#1839])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/shard-iclb7/igt@feature_discov...@display-4x.html

  * igt@feature_discovery@psr2:
- shard-iclb: [PASS][4] -> [SKIP][5] ([i915#658])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-iclb2/igt@feature_discov...@psr2.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/shard-iclb6/igt@feature_discov...@psr2.html

  * igt@gem_exec_capture@pi@bcs0:
- shard-skl:  [PASS][6] -> [INCOMPLETE][7] ([i915#4547])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-skl4/igt@gem_exec_capture@p...@bcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/shard-skl4/igt@gem_exec_capture@p...@bcs0.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk:  [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-glk5/igt@gem_exec_fair@basic-none-r...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/shard-glk4/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar 
issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-tglb8/igt@gem_exec_fair@basic-p...@bcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/shard-tglb6/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl:  [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/shard-kbl1/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_whisper@basic-contexts-forked-all:
- shard-glk:  [PASS][14] -> [DMESG-WARN][15] ([i915#118])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/shard-glk5/igt@gem_exec_whis...@basic-contexts-forked-all.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/shard-glk4/igt@gem_exec_whis...@basic-contexts-forked-all.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/shard-kbl6/igt@gem_lmem_swapp...@heavy-verify-multi.html

  * igt@gem_lmem_swapping@parallel-multi:
- shard-apl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/shard-apl3/igt@gem_lmem_swapp...@parallel-multi.html
- shard-skl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/shard-skl10/igt@gem_lmem_swapp...@parallel-multi.html
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#4613]) +1 similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/shard-tglb8/igt@gem_lmem_swapp...@parallel-multi.html

  * igt@gem_lmem_swapping@smem-oom:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#4613])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/shard-iclb4/igt@gem_lmem_swapp...@smem-oom.html

  * igt@gem_mmap_gtt@coherency:
- shard-iclb: NOTRUN -> [SKIP][21] ([fdo#109292])
   [21]: 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Log engine resets

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Log engine resets
URL   : https://patchwork.freedesktop.org/series/98020/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11001_full -> Patchwork_21846_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_21846_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl:  NOTRUN -> [FAIL][1] ([i915#2842])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-kbl3/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  [PASS][2] -> [FAIL][3] ([i915#2842]) +2 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11001/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-kbl2/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2842]) +1 similar issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11001/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-iclb: [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11001/shard-iclb7/igt@gem_exec_fair@basic-p...@bcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-iclb8/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl:  [PASS][8] -> [SKIP][9] ([fdo#109271])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11001/shard-kbl2/igt@gem_exec_fair@basic-p...@vcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_lmem_swapping@parallel-multi:
- shard-skl:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-skl1/igt@gem_lmem_swapp...@parallel-multi.html

  * igt@gem_lmem_swapping@random:
- shard-apl:  NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-apl2/igt@gem_lmem_swapp...@random.html
- shard-kbl:  NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-kbl3/igt@gem_lmem_swapp...@random.html

  * igt@gem_lmem_swapping@smem-oom:
- shard-glk:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-glk5/igt@gem_lmem_swapp...@smem-oom.html
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#4613])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-tglb1/igt@gem_lmem_swapp...@smem-oom.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-kbl:  NOTRUN -> [WARN][15] ([i915#2658])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-kbl3/igt@gem_pwr...@basic-exhaustion.html
- shard-apl:  NOTRUN -> [WARN][16] ([i915#2658])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-apl2/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_pxp@fail-invalid-protected-context:
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#4270])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-tglb1/igt@gem_...@fail-invalid-protected-context.html
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#4270])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-iclb3/igt@gem_...@fail-invalid-protected-context.html

  * igt@gen3_mixed_blits:
- shard-tglb: NOTRUN -> [SKIP][19] ([fdo#109289])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-tglb3/igt@gen3_mixed_blits.html

  * igt@gen9_exec_parse@batch-zero-length:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#2856]) +1 similar issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-tglb3/igt@gen9_exec_pa...@batch-zero-length.html

  * igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][21] -> [FAIL][22] ([i915#454])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11001/shard-iclb6/igt@i915_pm...@dc6-psr.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/shard-iclb3/igt@i915_pm...@dc6-psr.html

  * igt@i915_pm_dc@dc9-dpms:
- shard-tglb: NOTRUN -> [SKIP][23] ([i915#4281])
   [23]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Increment composite fence seqno

[Patchwork]

== Series Details ==

Series: drm/i915: Increment composite fence seqno
URL   : https://patchwork.freedesktop.org/series/98034/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11003 -> Patchwork_21850


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/index.html

Participating hosts (44 -> 36)
--

  Additional (1): fi-kbl-7500u 
  Missing(9): bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 
bat-adlp-4 fi-ctg-p8600 bat-jsl-2 bat-jsl-1 

Known issues


  Here are the changes found in Patchwork_21850 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-sdma:
- fi-kbl-7500u:   NOTRUN -> [SKIP][1] ([fdo#109271]) +28 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/fi-kbl-7500u/igt@amdgpu/amd_ba...@cs-sdma.html

  * igt@amdgpu/amd_prime@amd-to-i915:
- fi-pnv-d510:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/fi-pnv-d510/igt@amdgpu/amd_pr...@amd-to-i915.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-7500u:   NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/fi-kbl-7500u/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-7500u:   NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/fi-kbl-7500u/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-n3050:   [PASS][5] -> [INCOMPLETE][6] ([i915#2940])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][7] -> [INCOMPLETE][8] ([i915#3921])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u:   NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-7500u:   NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#533])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/fi-kbl-7500u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
- fi-bsw-n3050:   NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#1436] / 
[i915#3428] / [i915#4312])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/fi-bsw-n3050/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][12] ([i915#2927]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2:  [DMESG-WARN][14] ([i915#4269]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
- fi-cfl-8109u:   [DMESG-FAIL][16] ([i915#295]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u:   [DMESG-WARN][18] ([i915#295]) -> [PASS][19] +10 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#295]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for More preparation for multi gt patches

[Patchwork]

== Series Details ==

Series: More preparation for multi gt patches
URL   : https://patchwork.freedesktop.org/series/98032/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11002 -> Patchwork_21849


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/index.html

Participating hosts (46 -> 36)
--

  Additional (1): fi-kbl-soraka 
  Missing(11): bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-icl-u2 fi-bsw-cyan 
bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-2 bat-jsl-1 

Known issues


  Here are the changes found in Patchwork_21849 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka:   NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271]) +8 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-skl-6600u:   NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u:   NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][7] ([i915#1886] / [i915#2291])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][8] -> [INCOMPLETE][9] ([i915#3303])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka:  NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u:   NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u:   NOTRUN -> [SKIP][12] ([fdo#109271]) +2 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u:   NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_page_flip:
- fi-skl-6600u:   NOTRUN -> [FAIL][15] ([i915#4547])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-skl-6600u/igt@kms_psr@primary_page_flip.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#1436] / 
[i915#4312])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-hsw-4770/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_flink_basic@bad-flink:
- fi-skl-6600u:   [INCOMPLETE][17] ([i915#4547]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21849/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-kefka:   [INCOMPLETE][19] ([i915#2940]) -> [PASS][20]
   [19]: 

Re: [Intel-gfx] [PATCH] drm/i915: Increment composite fence seqno

[Matthew Brost]

On Tue, Dec 14, 2021 at 10:17:48PM +0200, Jani Nikula wrote:
> On Tue, 14 Dec 2021, Matthew Brost  wrote:
> > Increment composite fence seqno on each fence creation.
> >
> > Fixes: 544460c33821 ("drm/i915: Multi-BB execbuf")
> > Signed-off-by: Matthew Brost 
> > ---
> >  drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
> > b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > index 2213f7b613da..96cf8361b017 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > @@ -3113,7 +3113,7 @@ eb_composite_fence_create(struct i915_execbuffer *eb, 
> > int out_fence_fd)
> > fence_array = dma_fence_array_create(eb->num_batches,
> >  fences,
> >  
> > eb->context->parallel.fence_context,
> > -eb->context->parallel.seqno,
> > +eb->context->parallel.seqno++,
> >  false);
> > if (!fence_array) {
> > kfree(fences);
> 
> I have no idea what's going on, but the feeling I get from "code smells"
> just in this small snippet is that the seqno++ does not take the error
> path here into account.
> 

It does not take the error path into account, but it completely fine to
skip seqno numbers. As long as next valid seqno is greater than the last
valid seqno we should be fine.

Matt 

> 
> BR,
> Jani.
> 
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH] drm/i915: Increment composite fence seqno

[Jani Nikula]

On Tue, 14 Dec 2021, Matthew Brost  wrote:
> Increment composite fence seqno on each fence creation.
>
> Fixes: 544460c33821 ("drm/i915: Multi-BB execbuf")
> Signed-off-by: Matthew Brost 
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 2213f7b613da..96cf8361b017 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -3113,7 +3113,7 @@ eb_composite_fence_create(struct i915_execbuffer *eb, 
> int out_fence_fd)
>   fence_array = dma_fence_array_create(eb->num_batches,
>fences,
>
> eb->context->parallel.fence_context,
> -  eb->context->parallel.seqno,
> +  eb->context->parallel.seqno++,
>false);
>   if (!fence_array) {
>   kfree(fences);

I have no idea what's going on, but the feeling I get from "code smells"
just in this small snippet is that the seqno++ does not take the error
path here into account.


BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH] drm/i915: Increment composite fence seqno

[Matthew Brost]

Increment composite fence seqno on each fence creation.

Fixes: 544460c33821 ("drm/i915: Multi-BB execbuf")
Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 2213f7b613da..96cf8361b017 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -3113,7 +3113,7 @@ eb_composite_fence_create(struct i915_execbuffer *eb, int 
out_fence_fd)
fence_array = dma_fence_array_create(eb->num_batches,
 fences,
 
eb->context->parallel.fence_context,
-eb->context->parallel.seqno,
+eb->context->parallel.seqno++,
 false);
if (!fence_array) {
kfree(fences);
-- 
2.33.1

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/cdclk: move struct intel_cdclk_funcs to intel_cdclk.c

[Jani Nikula]

On Mon, 13 Dec 2021, Ville Syrjälä  wrote:
> On Mon, Dec 13, 2021 at 01:41:06PM +0200, Jani Nikula wrote:
>> The funcs struct can be opaque, make it internal to intel_cdclk.c.
>> 
>> Suggested-by: Ville Syrjälä 
>> Signed-off-by: Jani Nikula 
>
> Reviewed-by: Ville Syrjälä 

Thanks, pushed both to din.

BR,
Jani.

>
>> ---
>>  drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++
>>  drivers/gpu/drm/i915/i915_drv.h| 12 +---
>>  2 files changed, 12 insertions(+), 11 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
>> b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index c30cf8d2b835..249f81a80eb7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -63,6 +63,17 @@
>>   * dividers can be programmed correctly.
>>   */
>>  
>> +struct intel_cdclk_funcs {
>> +void (*get_cdclk)(struct drm_i915_private *i915,
>> +  struct intel_cdclk_config *cdclk_config);
>> +void (*set_cdclk)(struct drm_i915_private *i915,
>> +  const struct intel_cdclk_config *cdclk_config,
>> +  enum pipe pipe);
>> +int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
>> +int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
>> +u8 (*calc_voltage_level)(int cdclk);
>> +};
>> +
>>  void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
>> struct intel_cdclk_config *cdclk_config)
>>  {
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index e2c0d69753b1..0112ae942664 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -291,6 +291,7 @@ struct intel_connector;
>>  struct intel_encoder;
>>  struct intel_atomic_state;
>>  struct intel_cdclk_config;
>> +struct intel_cdclk_funcs;
>>  struct intel_cdclk_state;
>>  struct intel_cdclk_vals;
>>  struct intel_initial_plane_config;
>> @@ -339,17 +340,6 @@ struct intel_color_funcs {
>>  void (*read_luts)(struct intel_crtc_state *crtc_state);
>>  };
>>  
>> -struct intel_cdclk_funcs {
>> -void (*get_cdclk)(struct drm_i915_private *dev_priv,
>> -  struct intel_cdclk_config *cdclk_config);
>> -void (*set_cdclk)(struct drm_i915_private *dev_priv,
>> -  const struct intel_cdclk_config *cdclk_config,
>> -  enum pipe pipe);
>> -int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
>> -int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
>> -u8 (*calc_voltage_level)(int cdclk);
>> -};
>> -
>>  struct intel_hotplug_funcs {
>>  void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
>>  };
>> -- 
>> 2.30.2

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for More preparation for multi gt patches

[Patchwork]

== Series Details ==

Series: More preparation for multi gt patches
URL   : https://patchwork.freedesktop.org/series/98032/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More preparation for multi gt patches

[Patchwork]

== Series Details ==

Series: More preparation for multi gt patches
URL   : https://patchwork.freedesktop.org/series/98032/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
9213cee2d3f1 drm/i915: Store backpointer to GT in uncore
03c38fe5890e drm/i915: Introduce to_gt() helper
3396a9399332 drm/i915/display: Use to_gt() helper
c55e7cf11a96 drm/i915/gt: Use to_gt() helper
c76f51bbcc77 drm/i915/gem: Use to_gt() helper
8080a5ab6c26 drm/i915/gvt: Use to_gt() helper
15c86f199591 drm/i915/selftests: Use to_gt() helper
157bd8ae7fcb drm/i915/pxp: Use to_gt() helper
5208b9d94f5e drm/i915: Use to_gt() helper
3168444a49c9 drm/i915: Rename i915->gt to i915->gt0
816cc046ac41 drm/i915/gem: Use to_gt() helper for GGTT accesses
-:302: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#302: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:323:
+ (1 + 
next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);

-:333: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#333: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:460:
+ (1 + 
next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);

total: 0 errors, 2 warnings, 0 checks, 287 lines checked
0391dffccd54 drm/i915/display: Use to_gt() helper for GGTT accesses
3ee8899bc707 drm/i915/gt: Use to_gt() helper for GGTT accesses
5f031aaa1681 drm/i915/selftests: Use to_gt() helper for GGTT accesses
b78e5bf18426 drm/i915: Use to_gt() helper for GGTT accesses
9fbfb3c53e54 drm/i915: Remove unused i915->ggtt

Re: [Intel-gfx] [PATCH 7/7] drm/i915/guc: Selftest for stealing of guc ids

[John Harrison]

On 12/14/2021 09:05, Matthew Brost wrote:

Testing the stealing of guc ids is hard from user space as we have 64k
guc_ids. Add a selftest, which artificially reduces the number of guc
ids, and forces a steal.

The test creates a spinner which is used to block all subsequent
submissions until it completes. Next, a loop creates a context and a NOP
request each iteration until the guc_ids are exhausted (request creation
returns -EAGAIN). The spinner is ended, unblocking all requests created
in the loop. At this point all guc_ids are exhausted but are available
to steal. Try to create another request which should successfully steal
a guc_id. Wait on last request to complete, idle GPU, verify a guc_id
was stolen via a counter, and exit the test. Test also artificially
reduces the number of guc_ids so the test runs in a timely manner.

v2:
  (John Harrison)
   - s/stole/stolen
   - Fix some wording in test description
   - Rework indexing into context array
   - Add test description to commit message
   - Fix typo in commit message
  (Checkpatch)
   - s/guc/(guc) in NUMBER_MULTI_LRC_GUC_ID
v3:
  (John Harrison)
   - Set array value to NULL after extracting error
   - Fix a few typos in comments / error messages
   - Delete redundant comment in commit message

Signed-off-by: Matthew Brost 

Reviewed-by: John Harrison 


---
  drivers/gpu/drm/i915/gt/uc/intel_guc.h|  12 ++
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  16 +-
  drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 173 ++
  3 files changed, 196 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 1cb46098030d..f9240d4baa69 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -94,6 +94,11 @@ struct intel_guc {
 * @guc_ids: used to allocate new guc_ids, single-lrc
 */
struct ida guc_ids;
+   /**
+* @num_guc_ids: Number of guc_ids, selftest feature to be able
+* to reduce this number while testing.
+*/
+   int num_guc_ids;
/**
 * @guc_ids_bitmap: used to allocate new guc_ids, multi-lrc
 */
@@ -202,6 +207,13 @@ struct intel_guc {
 */
struct delayed_work work;
} timestamp;
+
+#ifdef CONFIG_DRM_I915_SELFTEST
+   /**
+* @number_guc_id_stolen: The number of guc_ids that have been stolen
+*/
+   int number_guc_id_stolen;
+#endif
  };
  
  static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 96fcf869e3ff..99414b49ca6d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -145,7 +145,8 @@ guc_create_parallel(struct intel_engine_cs **engines,
   * use should be low and 1/16 should be sufficient. Minimum of 32 guc_ids for
   * multi-lrc.
   */
-#define NUMBER_MULTI_LRC_GUC_ID(GUC_MAX_LRC_DESCRIPTORS / 16)
+#define NUMBER_MULTI_LRC_GUC_ID(guc)   \
+   ((guc)->submission_state.num_guc_ids / 16)
  
  /*

   * Below is a set of functions which control the GuC scheduling state which
@@ -1775,7 +1776,7 @@ int intel_guc_submission_init(struct intel_guc *guc)
  destroyed_worker_func);
  
  	guc->submission_state.guc_ids_bitmap =

-   bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID, GFP_KERNEL);
+   bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
if (!guc->submission_state.guc_ids_bitmap)
return -ENOMEM;
  
@@ -1869,13 +1870,13 @@ static int new_guc_id(struct intel_guc *guc, struct intel_context *ce)
  
  	if (intel_context_is_parent(ce))

ret = 
bitmap_find_free_region(guc->submission_state.guc_ids_bitmap,
- NUMBER_MULTI_LRC_GUC_ID,
+ NUMBER_MULTI_LRC_GUC_ID(guc),
  
order_base_2(ce->parallel.number_children
   + 1));
else
ret = ida_simple_get(>submission_state.guc_ids,
-NUMBER_MULTI_LRC_GUC_ID,
-GUC_MAX_LRC_DESCRIPTORS,
+NUMBER_MULTI_LRC_GUC_ID(guc),
+guc->submission_state.num_guc_ids,
 GFP_KERNEL | __GFP_RETRY_MAYFAIL |
 __GFP_NOWARN);
if (unlikely(ret < 0))
@@ -1941,6 +1942,10 @@ static int steal_guc_id(struct intel_guc *guc, struct 
intel_context *ce)
  
  		set_context_guc_id_invalid(cn);
  
+#ifdef CONFIG_DRM_I915_SELFTEST

+   

[Intel-gfx] [PATCH v8 16/16] drm/i915: Remove unused i915->ggtt

[Andi Shyti]

The reference to the GGTT from the private date is not used
anymore. Remove it.

Suggested-by: Matt Roper 
Signed-off-by: Andi Shyti 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/gt/intel_gt.c|  7 +--
 drivers/gpu/drm/i915/gt/intel_gt.h|  2 +-
 drivers/gpu/drm/i915/i915_driver.c|  4 +++-
 drivers/gpu/drm/i915/i915_drv.h   |  2 --
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 20 ++-
 drivers/gpu/drm/i915/selftests/i915_vma.c | 20 ++-
 .../gpu/drm/i915/selftests/mock_gem_device.c  |  9 +++--
 drivers/gpu/drm/i915/selftests/mock_gtt.c |  9 -
 drivers/gpu/drm/i915/selftests/mock_gtt.h |  3 ++-
 9 files changed, 44 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f98f0fb21efb..298ff32c8d0c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -3,6 +3,7 @@
  * Copyright © 2019 Intel Corporation
  */
 
+#include 
 #include 
 
 #include "intel_gt_debugfs.h"
@@ -85,9 +86,11 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
return 0;
 }
 
-void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
+int intel_gt_assign_ggtt(struct intel_gt *gt)
 {
-   gt->ggtt = ggtt;
+   gt->ggtt = drmm_kzalloc(>i915->drm, sizeof(*gt->ggtt), GFP_KERNEL);
+
+   return gt->ggtt ? 0 : -ENOMEM;
 }
 
 static const struct intel_mmio_range icl_l3bank_steering_table[] = {
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h 
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 3ace129eb2af..94e1bac8c0cc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -36,7 +36,7 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc 
*huc)
 
 void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
 void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
-void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt);
+int intel_gt_assign_ggtt(struct intel_gt *gt);
 int intel_gt_probe_lmem(struct intel_gt *gt);
 int intel_gt_init_mmio(struct intel_gt *gt);
 int __must_check intel_gt_init_hw(struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index 3c984553d86f..5f2343389b5e 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -571,7 +571,9 @@ static int i915_driver_hw_probe(struct drm_i915_private 
*dev_priv)
 
i915_perf_init(dev_priv);
 
-   intel_gt_init_hw_early(to_gt(dev_priv), _priv->ggtt);
+   ret = intel_gt_assign_ggtt(to_gt(dev_priv));
+   if (ret)
+   goto err_perf;
 
ret = i915_ggtt_probe_hw(dev_priv);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 65724e4df3bd..8266df3e11ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -838,8 +838,6 @@ struct drm_i915_private {
struct drm_atomic_state *modeset_restore_state;
struct drm_modeset_acquire_ctx reset_ctx;
 
-   struct i915_ggtt ggtt; /* VM representing the global address space */
-
struct i915_gem_mm mm;
 
/* Kernel Modesetting */
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 9afe7cf9d068..f62f7dac57f2 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1737,26 +1737,28 @@ int i915_gem_gtt_mock_selftests(void)
SUBTEST(igt_gtt_insert),
};
struct drm_i915_private *i915;
-   struct i915_ggtt *ggtt;
+   struct intel_gt *gt;
int err;
 
i915 = mock_gem_device();
if (!i915)
return -ENOMEM;
 
-   ggtt = kmalloc(sizeof(*ggtt), GFP_KERNEL);
-   if (!ggtt) {
-   err = -ENOMEM;
+   /* allocate the ggtt */
+   err = intel_gt_assign_ggtt(to_gt(i915));
+   if (err)
goto out_put;
-   }
-   mock_init_ggtt(i915, ggtt);
 
-   err = i915_subtests(tests, ggtt);
+   gt = to_gt(i915);
+
+   mock_init_ggtt(gt);
+
+   err = i915_subtests(tests, gt->ggtt);
 
mock_device_flush(i915);
i915_gem_drain_freed_objects(i915);
-   mock_fini_ggtt(ggtt);
-   kfree(ggtt);
+   mock_fini_ggtt(gt->ggtt);
+
 out_put:
mock_destroy_device(i915);
return err;
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c 
b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 6ac15d3bc5bc..a87cba4eb92f 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -907,26 +907,28 @@ int i915_vma_mock_selftests(void)
SUBTEST(igt_vma_partial),
};
struct drm_i915_private *i915;
-   struct i915_ggtt *ggtt;
+   struct intel_gt *gt;
int err;
 

[Intel-gfx] [PATCH v8 15/16] drm/i915: Use to_gt() helper for GGTT accesses

[Andi Shyti]

From: Michał Winiarski 

GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.

Signed-off-by: Michał Winiarski 
Cc: Michal Wajdeczko 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gvt/dmabuf.c|  2 +-
 drivers/gpu/drm/i915/i915_debugfs.c  |  4 ++--
 drivers/gpu/drm/i915/i915_driver.c   |  8 
 drivers/gpu/drm/i915/i915_drv.h  |  2 +-
 drivers/gpu/drm/i915/i915_gem.c  | 23 ---
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  6 +++---
 drivers/gpu/drm/i915/i915_getparam.c |  2 +-
 drivers/gpu/drm/i915/i915_perf.c |  4 ++--
 8 files changed, 26 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c 
b/drivers/gpu/drm/i915/gvt/dmabuf.c
index 8e65cd8258b9..94c3eb1586b0 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.c
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -84,7 +84,7 @@ static int vgpu_gem_get_pages(
kfree(st);
return ret;
}
-   gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
+   gtt_entries = (gen8_pte_t __iomem *)to_gt(dev_priv)->ggtt->gsm +
(fb_info->start >> PAGE_SHIFT);
for_each_sg(st->sgl, sg, page_num, i) {
dma_addr_t dma_addr =
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 93c3d154885b..0913daff62d7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -390,9 +390,9 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
intel_wakeref_t wakeref;
 
seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
-  swizzle_string(dev_priv->ggtt.bit_6_swizzle_x));
+  swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));
seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
-  swizzle_string(dev_priv->ggtt.bit_6_swizzle_y));
+  swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
 
if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
seq_puts(m, "L-shaped memory detected\n");
diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index 95174938b160..3c984553d86f 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -571,6 +571,8 @@ static int i915_driver_hw_probe(struct drm_i915_private 
*dev_priv)
 
i915_perf_init(dev_priv);
 
+   intel_gt_init_hw_early(to_gt(dev_priv), _priv->ggtt);
+
ret = i915_ggtt_probe_hw(dev_priv);
if (ret)
goto err_perf;
@@ -587,8 +589,6 @@ static int i915_driver_hw_probe(struct drm_i915_private 
*dev_priv)
if (ret)
goto err_ggtt;
 
-   intel_gt_init_hw_early(to_gt(dev_priv), _priv->ggtt);
-
ret = intel_gt_probe_lmem(to_gt(dev_priv));
if (ret)
goto err_mem_regions;
@@ -1146,7 +1146,7 @@ static int i915_drm_suspend(struct drm_device *dev)
 
/* Must be called before GGTT is suspended. */
intel_dpt_suspend(dev_priv);
-   i915_ggtt_suspend(_priv->ggtt);
+   i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
 
i915_save_display(dev_priv);
 
@@ -1270,7 +1270,7 @@ static int i915_drm_resume(struct drm_device *dev)
if (ret)
drm_err(_priv->drm, "failed to re-enable GGTT\n");
 
-   i915_ggtt_resume(_priv->ggtt);
+   i915_ggtt_resume(to_gt(dev_priv)->ggtt);
/* Must be called after GGTT is resumed. */
intel_dpt_resume(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 28c1524e2e3b..65724e4df3bd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1762,7 +1762,7 @@ static inline bool 
i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec
 {
struct drm_i915_private *i915 = to_i915(obj->base.dev);
 
-   return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
+   return to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 
&&
i915_gem_object_is_tiled(obj);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8ba2119092f2..45e3b4c540a1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -88,7 +88,8 @@ int
 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
 {
-   struct i915_ggtt *ggtt = _i915(dev)->ggtt;
+   struct drm_i915_private *i915 = to_i915(dev);
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct drm_i915_gem_get_aperture *args = data;
struct i915_vma *vma;
u64 pinned;
@@ -289,7 +290,7 @@ static struct i915_vma *i915_gem_gtt_prepare(struct 
drm_i915_gem_object *obj,
 bool write)
 {
struct 

[Intel-gfx] [PATCH v8 14/16] drm/i915/selftests: Use to_gt() helper for GGTT accesses

[Andi Shyti]

From: Michał Winiarski 

GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.

Signed-off-by: Michał Winiarski 
Cc: Michal Wajdeczko 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/selftests/i915_gem.c| 8 
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c| 6 +++---
 drivers/gpu/drm/i915/selftests/i915_request.c| 2 +-
 drivers/gpu/drm/i915/selftests/i915_vma.c| 2 +-
 drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c 
b/drivers/gpu/drm/i915/selftests/i915_gem.c
index b5576888cd78..1628b81d0a35 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -41,7 +41,7 @@ static int switch_to_context(struct i915_gem_context *ctx)
 
 static void trash_stolen(struct drm_i915_private *i915)
 {
-   struct i915_ggtt *ggtt = >ggtt;
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
const u64 slot = ggtt->error_capture.start;
const resource_size_t size = resource_size(>dsm);
unsigned long page;
@@ -99,7 +99,7 @@ static void igt_pm_suspend(struct drm_i915_private *i915)
intel_wakeref_t wakeref;
 
with_intel_runtime_pm(>runtime_pm, wakeref) {
-   i915_ggtt_suspend(>ggtt);
+   i915_ggtt_suspend(to_gt(i915)->ggtt);
i915_gem_suspend_late(i915);
}
 }
@@ -109,7 +109,7 @@ static void igt_pm_hibernate(struct drm_i915_private *i915)
intel_wakeref_t wakeref;
 
with_intel_runtime_pm(>runtime_pm, wakeref) {
-   i915_ggtt_suspend(>ggtt);
+   i915_ggtt_suspend(to_gt(i915)->ggtt);
 
i915_gem_freeze(i915);
i915_gem_freeze_late(i915);
@@ -125,7 +125,7 @@ static void igt_pm_resume(struct drm_i915_private *i915)
 * that runtime-pm just works.
 */
with_intel_runtime_pm(>runtime_pm, wakeref) {
-   i915_ggtt_resume(>ggtt);
+   i915_ggtt_resume(to_gt(i915)->ggtt);
i915_gem_resume(i915);
}
 }
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 48123c3e1ff0..9afe7cf9d068 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1122,7 +1122,7 @@ static int exercise_ggtt(struct drm_i915_private *i915,
 u64 hole_start, u64 hole_end,
 unsigned long end_time))
 {
-   struct i915_ggtt *ggtt = >ggtt;
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
u64 hole_start, hole_end, last = 0;
struct drm_mm_node *node;
IGT_TIMEOUT(end_time);
@@ -1182,7 +1182,7 @@ static int igt_ggtt_page(void *arg)
const unsigned int count = PAGE_SIZE/sizeof(u32);
I915_RND_STATE(prng);
struct drm_i915_private *i915 = arg;
-   struct i915_ggtt *ggtt = >ggtt;
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct drm_i915_gem_object *obj;
intel_wakeref_t wakeref;
struct drm_mm_node tmp;
@@ -2110,7 +2110,7 @@ int i915_gem_gtt_live_selftests(struct drm_i915_private 
*i915)
SUBTEST(igt_cs_tlb),
};
 
-   GEM_BUG_ON(offset_in_page(i915->ggtt.vm.total));
+   GEM_BUG_ON(offset_in_page(to_gt(i915)->ggtt->vm.total));
 
return i915_subtests(tests, i915);
 }
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c 
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 92a859b34190..7f66f6d299b2 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -843,7 +843,7 @@ static struct i915_vma *empty_batch(struct drm_i915_private 
*i915)
 
intel_gt_chipset_flush(to_gt(i915));
 
-   vma = i915_vma_instance(obj, >ggtt.vm, NULL);
+   vma = i915_vma_instance(obj, _gt(i915)->ggtt->vm, NULL);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
goto err;
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c 
b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 1f10fe36619b..6ac15d3bc5bc 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -967,7 +967,7 @@ static int igt_vma_remapped_gtt(void *arg)
intel_wakeref_t wakeref;
int err = 0;
 
-   if (!i915_ggtt_has_aperture(>ggtt))
+   if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return 0;
 
obj = i915_gem_object_create_internal(i915, 10 * 10 * PAGE_SIZE);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c 
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 8aa7b1d33865..0b469ae0f474 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ 

[Intel-gfx] [PATCH v8 13/16] drm/i915/gt: Use to_gt() helper for GGTT accesses

[Andi Shyti]

From: Michał Winiarski 

GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.

Signed-off-by: Michał Winiarski 
Cc: Michal Wajdeczko 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 +++---
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c |  6 +++---
 drivers/gpu/drm/i915/gt/intel_region_lmem.c  |  4 ++--
 drivers/gpu/drm/i915/gt/selftest_reset.c |  2 +-
 4 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 971e737b37b2..ec3b998392ff 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -89,7 +89,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
 * beyond the end of the batch buffer, across the page boundary,
 * and beyond the end of the GTT if we do not provide a guard.
 */
-   ret = ggtt_init_hw(>ggtt);
+   ret = ggtt_init_hw(to_gt(i915)->ggtt);
if (ret)
return ret;
 
@@ -725,14 +725,14 @@ int i915_init_ggtt(struct drm_i915_private *i915)
 {
int ret;
 
-   ret = init_ggtt(>ggtt);
+   ret = init_ggtt(to_gt(i915)->ggtt);
if (ret)
return ret;
 
if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
-   ret = init_aliasing_ppgtt(>ggtt);
+   ret = init_aliasing_ppgtt(to_gt(i915)->ggtt);
if (ret)
-   cleanup_init_ggtt(>ggtt);
+   cleanup_init_ggtt(to_gt(i915)->ggtt);
}
 
return 0;
@@ -775,7 +775,7 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
  */
 void i915_ggtt_driver_release(struct drm_i915_private *i915)
 {
-   struct i915_ggtt *ggtt = >ggtt;
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
 
fini_aliasing_ppgtt(ggtt);
 
@@ -790,7 +790,7 @@ void i915_ggtt_driver_release(struct drm_i915_private *i915)
  */
 void i915_ggtt_driver_late_release(struct drm_i915_private *i915)
 {
-   struct i915_ggtt *ggtt = >ggtt;
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
 
GEM_WARN_ON(kref_read(>vm.resv_ref) != 1);
dma_resv_fini(>vm._resv);
@@ -1232,7 +1232,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
 {
int ret;
 
-   ret = ggtt_probe_hw(>ggtt, to_gt(i915));
+   ret = ggtt_probe_hw(to_gt(i915)->ggtt, to_gt(i915));
if (ret)
return ret;
 
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index f8948de72036..beabf3bc9b75 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -728,8 +728,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
}
 
-   i915->ggtt.bit_6_swizzle_x = swizzle_x;
-   i915->ggtt.bit_6_swizzle_y = swizzle_y;
+   to_gt(i915)->ggtt->bit_6_swizzle_x = swizzle_x;
+   to_gt(i915)->ggtt->bit_6_swizzle_y = swizzle_y;
 }
 
 /*
@@ -896,7 +896,7 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
 
if (GRAPHICS_VER(i915) < 5 ||
-   i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
+   to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
return;
 
intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c 
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index fde2dcb59809..21215a080088 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -15,7 +15,7 @@
 static int init_fake_lmem_bar(struct intel_memory_region *mem)
 {
struct drm_i915_private *i915 = mem->i915;
-   struct i915_ggtt *ggtt = >ggtt;
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
unsigned long n;
int ret;
 
@@ -131,7 +131,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
if (!i915->params.fake_lmem_start)
return ERR_PTR(-ENODEV);
 
-   GEM_BUG_ON(i915_ggtt_has_aperture(>ggtt));
+   GEM_BUG_ON(i915_ggtt_has_aperture(to_gt(i915)->ggtt));
 
/* Your mappable aperture belongs to me now! */
mappable_end = pci_resource_len(pdev, 2);
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c 
b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 8a873f6bda7f..37c38bdd5f47 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -19,7 +19,7 @@ __igt_reset_stolen(struct intel_gt *gt,
   intel_engine_mask_t mask,
   const char *msg)
 {
-   struct i915_ggtt *ggtt = >i915->ggtt;
+   struct i915_ggtt *ggtt = gt->ggtt;
const struct resource *dsm = 

[Intel-gfx] [PATCH v8 12/16] drm/i915/display: Use to_gt() helper for GGTT accesses

[Andi Shyti]

From: Michał Winiarski 

GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.

Signed-off-by: Michał Winiarski 
Cc: Michal Wajdeczko 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/display/intel_fbc.c   | 2 +-
 drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +-
 drivers/gpu/drm/i915/display/intel_plane_initial.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 8be01b93015f..98319c0322d7 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -595,7 +595,7 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
else if (DISPLAY_VER(i915) == 9)
skl_fbc_program_cfb_stride(fbc);
 
-   if (i915->ggtt.num_fences)
+   if (to_gt(i915)->ggtt->num_fences)
snb_fbc_program_fence(fbc);
 
intel_de_write(i915, ILK_DPFC_CONTROL,
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c 
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index adc3a81be9f7..41d279db2be6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -180,7 +180,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
struct drm_device *dev = helper->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
-   struct i915_ggtt *ggtt = _priv->ggtt;
+   struct i915_ggtt *ggtt = to_gt(dev_priv)->ggtt;
const struct i915_ggtt_view view = {
.type = I915_GGTT_VIEW_NORMAL,
};
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c 
b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index 01ce1d72297f..e4186a0b8edb 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -94,7 +94,7 @@ initial_plane_vma(struct drm_i915_private *i915,
goto err_obj;
}
 
-   vma = i915_vma_instance(obj, >ggtt.vm, NULL);
+   vma = i915_vma_instance(obj, _gt(i915)->ggtt->vm, NULL);
if (IS_ERR(vma))
goto err_obj;
 
-- 
2.34.1

[Intel-gfx] [PATCH v8 11/16] drm/i915/gem: Use to_gt() helper for GGTT accesses

[Andi Shyti]

From: Michał Winiarski 

GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.

Signed-off-by: Michał Winiarski 
Cc: Michal Wajdeczko 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.h   |  2 +-
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c|  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_mman.c  | 19 ++-
 drivers/gpu/drm/i915/gem/i915_gem_pm.c|  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c  |  6 +++---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c|  8 +---
 drivers/gpu/drm/i915/gem/i915_gem_tiling.c| 15 ---
 .../i915/gem/selftests/i915_gem_client_blt.c  |  2 +-
 .../drm/i915/gem/selftests/i915_gem_context.c |  2 +-
 .../drm/i915/gem/selftests/i915_gem_mman.c| 19 ++-
 .../drm/i915/gem/selftests/i915_gem_object.c  |  2 +-
 11 files changed, 42 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h 
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index babfecb17ad1..e5b0f66ea1fe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -174,7 +174,7 @@ i915_gem_context_get_eb_vm(struct i915_gem_context *ctx)
 
vm = ctx->vm;
if (!vm)
-   vm = >i915->ggtt.vm;
+   vm = _gt(ctx->i915)->ggtt->vm;
vm = i915_vm_get(vm);
 
return vm;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index ec7c4a29a720..3078611d5bfe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1106,7 +1106,7 @@ static inline struct i915_ggtt *cache_to_ggtt(struct 
reloc_cache *cache)
 {
struct drm_i915_private *i915 =
container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
-   return >ggtt;
+   return to_gt(i915)->ggtt;
 }
 
 static void reloc_cache_reset(struct reloc_cache *cache, struct 
i915_execbuffer *eb)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c 
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 1ca5c062974e..a9effb34d7ed 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -295,7 +295,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *i915 = to_i915(dev);
struct intel_runtime_pm *rpm = >runtime_pm;
-   struct i915_ggtt *ggtt = >ggtt;
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
bool write = area->vm_flags & VM_WRITE;
struct i915_gem_ww_ctx ww;
intel_wakeref_t wakeref;
@@ -388,16 +388,16 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
assert_rpm_wakelock_held(rpm);
 
/* Mark as being mmapped into userspace for later revocation */
-   mutex_lock(>ggtt.vm.mutex);
+   mutex_lock(_gt(i915)->ggtt->vm.mutex);
if (!i915_vma_set_userfault(vma) && !obj->userfault_count++)
-   list_add(>userfault_link, >ggtt.userfault_list);
-   mutex_unlock(>ggtt.vm.mutex);
+   list_add(>userfault_link, 
_gt(i915)->ggtt->userfault_list);
+   mutex_unlock(_gt(i915)->ggtt->vm.mutex);
 
/* Track the mmo associated with the fenced vma */
vma->mmo = mmo;
 
if (CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND)
-   intel_wakeref_auto(>ggtt.userfault_wakeref,
+   intel_wakeref_auto(_gt(i915)->ggtt->userfault_wakeref,
   
msecs_to_jiffies_timeout(CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND));
 
if (write) {
@@ -512,7 +512,7 @@ void i915_gem_object_release_mmap_gtt(struct 
drm_i915_gem_object *obj)
 * wakeref.
 */
wakeref = intel_runtime_pm_get(>runtime_pm);
-   mutex_lock(>ggtt.vm.mutex);
+   mutex_lock(_gt(i915)->ggtt->vm.mutex);
 
if (!obj->userfault_count)
goto out;
@@ -530,7 +530,7 @@ void i915_gem_object_release_mmap_gtt(struct 
drm_i915_gem_object *obj)
wmb();
 
 out:
-   mutex_unlock(>ggtt.vm.mutex);
+   mutex_unlock(_gt(i915)->ggtt->vm.mutex);
intel_runtime_pm_put(>runtime_pm, wakeref);
 }
 
@@ -733,13 +733,14 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
  u32 handle,
  u64 *offset)
 {
+   struct drm_i915_private *i915 = to_i915(dev);
enum i915_mmap_type mmap_type;
 
if (HAS_LMEM(to_i915(dev)))
mmap_type = I915_MMAP_TYPE_FIXED;
else if (boot_cpu_has(X86_FEATURE_PAT))
mmap_type = I915_MMAP_TYPE_WC;
-   else if (!i915_ggtt_has_aperture(_i915(dev)->ggtt))
+   else if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return -ENODEV;
else
mmap_type = 

[Intel-gfx] [PATCH v8 10/16] drm/i915: Rename i915->gt to i915->gt0

[Andi Shyti]

In preparation of the multitile support, highlight the root GT by
calling it gt0 inside the drm i915 private data.

Signed-off-by: Andi Shyti 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Lucas De Marchi 
Cc: Rodrigo Vivi 
Cc: Tvrtko Ursulin 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/i915_drv.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3be29931feb0..28c1524e2e3b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1005,7 +1005,7 @@ struct drm_i915_private {
struct i915_perf perf;
 
/* Abstract the submission mechanism (legacy ringbuffer or execlists) 
away */
-   struct intel_gt gt;
+   struct intel_gt gt0;
 
struct {
struct i915_gem_contexts {
@@ -1079,7 +1079,7 @@ static inline struct drm_i915_private 
*pdev_to_i915(struct pci_dev *pdev)
 
 static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 {
-   return >gt;
+   return >gt0;
 }
 
 /* Simple iterator over all initialised engines */
-- 
2.34.1

[Intel-gfx] [PATCH v8 09/16] drm/i915: Use to_gt() helper

[Andi Shyti]

From: Michał Winiarski 

Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.

Signed-off-by: Michał Winiarski 
Signed-off-by: Andi Shyti 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/i915_debugfs.c| 38 +++
 drivers/gpu/drm/i915/i915_debugfs_params.c |  4 +-
 drivers/gpu/drm/i915/i915_driver.c | 32 ++---
 drivers/gpu/drm/i915/i915_drv.h|  2 +-
 drivers/gpu/drm/i915/i915_gem.c| 16 +++
 drivers/gpu/drm/i915/i915_getparam.c   | 10 ++--
 drivers/gpu/drm/i915/i915_gpu_error.c  |  4 +-
 drivers/gpu/drm/i915/i915_irq.c| 56 +++---
 drivers/gpu/drm/i915/i915_perf.c   |  2 +-
 drivers/gpu/drm/i915/i915_pmu.c| 14 +++---
 drivers/gpu/drm/i915/i915_query.c  |  2 +-
 drivers/gpu/drm/i915/i915_sysfs.c  | 22 -
 drivers/gpu/drm/i915/intel_gvt.c   |  2 +-
 drivers/gpu/drm/i915/intel_wopcm.c |  2 +-
 14 files changed, 103 insertions(+), 103 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index bafb902269de..93c3d154885b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -65,7 +65,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
intel_device_info_print_static(INTEL_INFO(i915), );
intel_device_info_print_runtime(RUNTIME_INFO(i915), );
i915_print_iommu_status(i915, );
-   intel_gt_info_print(>gt.info, );
+   intel_gt_info_print(_gt(i915)->info, );
intel_driver_caps_print(>caps, );
 
kernel_param_lock(THIS_MODULE);
@@ -293,7 +293,7 @@ static int i915_gpu_info_open(struct inode *inode, struct 
file *file)
 
gpu = NULL;
with_intel_runtime_pm(>runtime_pm, wakeref)
-   gpu = i915_gpu_coredump(>gt, ALL_ENGINES);
+   gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES);
if (IS_ERR(gpu))
return PTR_ERR(gpu);
 
@@ -351,7 +351,7 @@ static const struct file_operations i915_error_state_fops = 
{
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *i915 = node_to_i915(m->private);
-   struct intel_gt *gt = >gt;
+   struct intel_gt *gt = to_gt(i915);
struct drm_printer p = drm_seq_file_printer(m);
 
intel_gt_pm_frequency_dump(gt, );
@@ -439,11 +439,11 @@ static int i915_swizzle_info(struct seq_file *m, void 
*data)
 static int i915_rps_boost_info(struct seq_file *m, void *data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct intel_rps *rps = _priv->gt.rps;
+   struct intel_rps *rps = _gt(dev_priv)->rps;
 
seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));
seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps)));
-   seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake));
+   seq_printf(m, "GPU busy? %s\n", yesno(to_gt(dev_priv)->awake));
seq_printf(m, "Boosts outstanding? %d\n",
   atomic_read(>num_waiters));
seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
@@ -476,7 +476,7 @@ static int i915_runtime_pm_status(struct seq_file *m, void 
*unused)
seq_printf(m, "Runtime power status: %s\n",
   enableddisabled(!dev_priv->power_domains.init_wakeref));
 
-   seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
+   seq_printf(m, "GPU idle: %s\n", yesno(!to_gt(dev_priv)->awake));
seq_printf(m, "IRQs disabled: %s\n",
   yesno(!intel_irqs_enabled(dev_priv)));
 #ifdef CONFIG_PM
@@ -508,18 +508,18 @@ static int i915_engine_info(struct seq_file *m, void 
*unused)
wakeref = intel_runtime_pm_get(>runtime_pm);
 
seq_printf(m, "GT awake? %s [%d], %llums\n",
-  yesno(i915->gt.awake),
-  atomic_read(>gt.wakeref.count),
-  ktime_to_ms(intel_gt_get_awake_time(>gt)));
+  yesno(to_gt(i915)->awake),
+  atomic_read(_gt(i915)->wakeref.count),
+  ktime_to_ms(intel_gt_get_awake_time(to_gt(i915;
seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
-  i915->gt.clock_frequency,
-  i915->gt.clock_period_ns);
+  to_gt(i915)->clock_frequency,
+  to_gt(i915)->clock_period_ns);
 
p = drm_seq_file_printer(m);
for_each_uabi_engine(engine, i915)
intel_engine_dump(engine, , "%s\n", engine->name);
 
-   intel_gt_show_timelines(>gt, , i915_request_show_with_schedule);
+   intel_gt_show_timelines(to_gt(i915), , 
i915_request_show_with_schedule);
 
intel_runtime_pm_put(>runtime_pm, wakeref);
 
@@ -558,14 +558,14 @@ static int i915_wedged_get(void *data, u64 *val)
 {
struct drm_i915_private *i915 = data;
 
-  

[Intel-gfx] [PATCH v8 08/16] drm/i915/pxp: Use to_gt() helper

[Andi Shyti]

Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.

Signed-off-by: Andi Shyti 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c 
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 5d169624ad60..195b2323ec00 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -16,7 +16,9 @@
 
 static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
 {
-   return _to_i915(i915_kdev)->gt.pxp;
+   struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+
+   return _gt(i915)->pxp;
 }
 
 static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
-- 
2.34.1

[Intel-gfx] [PATCH v8 07/16] drm/i915/selftests: Use to_gt() helper

[Andi Shyti]

Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.

Signed-off-by: Andi Shyti 
Cc: Michał Winiarski 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/selftests/i915_active.c  |  2 +-
 drivers/gpu/drm/i915/selftests/i915_gem.c |  2 +-
 .../gpu/drm/i915/selftests/i915_gem_evict.c   |  6 ++--
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +--
 drivers/gpu/drm/i915/selftests/i915_perf.c|  2 +-
 drivers/gpu/drm/i915/selftests/i915_request.c | 10 +++
 .../gpu/drm/i915/selftests/i915_selftest.c|  4 +--
 .../gpu/drm/i915/selftests/igt_flush_test.c   |  2 +-
 .../gpu/drm/i915/selftests/igt_live_test.c|  4 +--
 .../drm/i915/selftests/intel_memory_region.c  |  4 +--
 drivers/gpu/drm/i915/selftests/intel_uncore.c |  2 +-
 .../gpu/drm/i915/selftests/mock_gem_device.c  | 30 +--
 drivers/gpu/drm/i915/selftests/mock_gtt.c |  6 ++--
 drivers/gpu/drm/i915/selftests/mock_uncore.c  |  2 +-
 14 files changed, 40 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/selftests/i915_active.c 
b/drivers/gpu/drm/i915/selftests/i915_active.c
index 61bf4560d8af..2dac9be1de58 100644
--- a/drivers/gpu/drm/i915/selftests/i915_active.c
+++ b/drivers/gpu/drm/i915/selftests/i915_active.c
@@ -254,7 +254,7 @@ int i915_active_live_selftests(struct drm_i915_private 
*i915)
SUBTEST(live_active_barrier),
};
 
-   if (intel_gt_is_wedged(>gt))
+   if (intel_gt_is_wedged(to_gt(i915)))
return 0;
 
return i915_subtests(tests, i915);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c 
b/drivers/gpu/drm/i915/selftests/i915_gem.c
index 152d9ab135b1..b5576888cd78 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -248,7 +248,7 @@ int i915_gem_live_selftests(struct drm_i915_private *i915)
SUBTEST(igt_gem_ww_ctx),
};
 
-   if (intel_gt_is_wedged(>gt))
+   if (intel_gt_is_wedged(to_gt(i915)))
return 0;
 
return i915_live_subtests(tests, i915);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 7e0658a77659..75b709c26dd3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -545,7 +545,7 @@ int i915_gem_evict_mock_selftests(void)
return -ENOMEM;
 
with_intel_runtime_pm(>runtime_pm, wakeref)
-   err = i915_subtests(tests, >gt);
+   err = i915_subtests(tests, to_gt(i915));
 
mock_destroy_device(i915);
return err;
@@ -557,8 +557,8 @@ int i915_gem_evict_live_selftests(struct drm_i915_private 
*i915)
SUBTEST(igt_evict_contexts),
};
 
-   if (intel_gt_is_wedged(>gt))
+   if (intel_gt_is_wedged(to_gt(i915)))
return 0;
 
-   return intel_gt_live_subtests(tests, >gt);
+   return intel_gt_live_subtests(tests, to_gt(i915));
 }
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 46f4236039a9..48123c3e1ff0 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -155,7 +155,7 @@ static int igt_ppgtt_alloc(void *arg)
if (!HAS_PPGTT(dev_priv))
return 0;
 
-   ppgtt = i915_ppgtt_create(_priv->gt, 0);
+   ppgtt = i915_ppgtt_create(to_gt(dev_priv), 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
 
@@ -1053,7 +1053,7 @@ static int exercise_ppgtt(struct drm_i915_private 
*dev_priv,
if (IS_ERR(file))
return PTR_ERR(file);
 
-   ppgtt = i915_ppgtt_create(_priv->gt, 0);
+   ppgtt = i915_ppgtt_create(to_gt(dev_priv), 0);
if (IS_ERR(ppgtt)) {
err = PTR_ERR(ppgtt);
goto out_free;
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c 
b/drivers/gpu/drm/i915/selftests/i915_perf.c
index 9e9a6cb1d9e5..88db2e3d81d0 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf.c
+++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
@@ -424,7 +424,7 @@ int i915_perf_live_selftests(struct drm_i915_private *i915)
if (!perf->metrics_kobj || !perf->ops.enable_metric_set)
return 0;
 
-   if (intel_gt_is_wedged(>gt))
+   if (intel_gt_is_wedged(to_gt(i915)))
return 0;
 
err = alloc_empty_config(>perf);
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c 
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 9979ef9197cd..92a859b34190 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -841,7 +841,7 @@ static struct i915_vma *empty_batch(struct drm_i915_private 
*i915)
__i915_gem_object_flush_map(obj, 0, 64);
i915_gem_object_unpin_map(obj);
 
-   intel_gt_chipset_flush(>gt);
+   

[Intel-gfx] [PATCH v8 06/16] drm/i915/gvt: Use to_gt() helper

[Andi Shyti]

From: Michał Winiarski 

Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.

Signed-off-by: Michał Winiarski 
Signed-off-by: Andi Shyti 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/gvt/gvt.c   | 2 +-
 drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
index cbac409f6c8a..f0b69e4dcb52 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.c
+++ b/drivers/gpu/drm/i915/gvt/gvt.c
@@ -205,7 +205,7 @@ int intel_gvt_init_device(struct drm_i915_private *i915)
spin_lock_init(>scheduler.mmio_context_lock);
mutex_init(>lock);
mutex_init(>sched_lock);
-   gvt->gt = >gt;
+   gvt->gt = to_gt(i915);
i915->gvt = gvt;
 
init_device_info(gvt);
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c 
b/drivers/gpu/drm/i915/gvt/scheduler.c
index 6c804102528b..42a0c9ae0a73 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1386,7 +1386,7 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
enum intel_engine_id i;
int ret;
 
-   ppgtt = i915_ppgtt_create(>gt, I915_BO_ALLOC_PM_EARLY);
+   ppgtt = i915_ppgtt_create(to_gt(i915), I915_BO_ALLOC_PM_EARLY);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
 
-- 
2.34.1

[Intel-gfx] [PATCH v8 05/16] drm/i915/gem: Use to_gt() helper

[Andi Shyti]

From: Michał Winiarski 

Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.

Signed-off-by: Michał Winiarski 
Signed-off-by: Andi Shyti 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c   | 22 
 drivers/gpu/drm/i915/gem/i915_gem_create.c|  2 +-
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c|  4 +--
 drivers/gpu/drm/i915/gem/i915_gem_mman.c  |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_phys.c  |  6 +++--
 drivers/gpu/drm/i915/gem/i915_gem_pm.c|  6 ++---
 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c  |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_throttle.c  |  3 ++-
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c  | 12 -
 drivers/gpu/drm/i915/gem/i915_gem_userptr.c   |  2 +-
 .../gpu/drm/i915/gem/selftests/huge_pages.c   |  4 +--
 .../i915/gem/selftests/i915_gem_client_blt.c  |  2 +-
 .../drm/i915/gem/selftests/i915_gem_context.c | 10 +++
 .../drm/i915/gem/selftests/i915_gem_migrate.c |  2 +-
 .../drm/i915/gem/selftests/i915_gem_mman.c| 26 ++-
 15 files changed, 55 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 347dab952e90..cad3f0b2be9e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -237,7 +237,7 @@ static int proto_context_set_persistence(struct 
drm_i915_private *i915,
 * colateral damage, and we should not pretend we can by
 * exposing the interface.
 */
-   if (!intel_has_reset_engine(>gt))
+   if (!intel_has_reset_engine(to_gt(i915)))
return -ENODEV;
 
pc->user_flags &= ~BIT(UCONTEXT_PERSISTENCE);
@@ -254,7 +254,7 @@ static int proto_context_set_protected(struct 
drm_i915_private *i915,
 
if (!protected) {
pc->uses_protected_content = false;
-   } else if (!intel_pxp_is_enabled(>gt.pxp)) {
+   } else if (!intel_pxp_is_enabled(_gt(i915)->pxp)) {
ret = -ENODEV;
} else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) ||
   !(pc->user_flags & BIT(UCONTEXT_BANNABLE))) {
@@ -268,8 +268,8 @@ static int proto_context_set_protected(struct 
drm_i915_private *i915,
 */
pc->pxp_wakeref = intel_runtime_pm_get(>runtime_pm);
 
-   if (!intel_pxp_is_active(>gt.pxp))
-   ret = intel_pxp_start(>gt.pxp);
+   if (!intel_pxp_is_active(_gt(i915)->pxp))
+   ret = intel_pxp_start(_gt(i915)->pxp);
}
 
return ret;
@@ -571,7 +571,7 @@ set_proto_ctx_engines_parallel_submit(struct 
i915_user_extension __user *base,
intel_engine_mask_t prev_mask;
 
/* FIXME: This is NIY for execlists */
-   if (!(intel_uc_uses_guc_submission(>gt.uc)))
+   if (!(intel_uc_uses_guc_submission(_gt(i915)->uc)))
return -ENODEV;
 
if (get_user(slot, >engine_index))
@@ -833,7 +833,7 @@ static int set_proto_ctx_sseu(struct drm_i915_file_private 
*fpriv,
sseu = >legacy_rcs_sseu;
}
 
-   ret = i915_gem_user_to_context_sseu(>gt, _sseu, sseu);
+   ret = i915_gem_user_to_context_sseu(to_gt(i915), _sseu, sseu);
if (ret)
return ret;
 
@@ -1044,7 +1044,7 @@ static struct i915_gem_engines *alloc_engines(unsigned 
int count)
 static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx,
struct intel_sseu rcs_sseu)
 {
-   const struct intel_gt *gt = >i915->gt;
+   const struct intel_gt *gt = to_gt(ctx->i915);
struct intel_engine_cs *engine;
struct i915_gem_engines *e, *err;
enum intel_engine_id id;
@@ -1521,7 +1521,7 @@ static int __context_set_persistence(struct 
i915_gem_context *ctx, bool state)
 * colateral damage, and we should not pretend we can by
 * exposing the interface.
 */
-   if (!intel_has_reset_engine(>i915->gt))
+   if (!intel_has_reset_engine(to_gt(ctx->i915)))
return -ENODEV;
 
i915_gem_context_clear_persistence(ctx);
@@ -1559,7 +1559,7 @@ i915_gem_create_context(struct drm_i915_private *i915,
} else if (HAS_FULL_PPGTT(i915)) {
struct i915_ppgtt *ppgtt;
 
-   ppgtt = i915_ppgtt_create(>gt, 0);
+   ppgtt = i915_ppgtt_create(to_gt(i915), 0);
if (IS_ERR(ppgtt)) {
drm_dbg(>drm, "PPGTT setup failed (%ld)\n",
PTR_ERR(ppgtt));
@@ -1742,7 +1742,7 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void 
*data,
if (args->flags)
return -EINVAL;
 
-   ppgtt = i915_ppgtt_create(>gt, 0);
+   ppgtt = 

[Intel-gfx] [PATCH v8 04/16] drm/i915/gt: Use to_gt() helper

[Andi Shyti]

From: Michał Winiarski 

Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.

Signed-off-by: Michał Winiarski 
Signed-off-by: Andi Shyti 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_engine_user.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_ggtt.c|  2 +-
 drivers/gpu/drm/i915/gt/intel_rps.c | 12 ++--
 drivers/gpu/drm/i915/gt/intel_workarounds.c |  2 +-
 drivers/gpu/drm/i915/gt/mock_engine.c   | 10 +-
 drivers/gpu/drm/i915/gt/selftest_context.c  |  2 +-
 drivers/gpu/drm/i915/gt/selftest_engine.c   |  2 +-
 drivers/gpu/drm/i915/gt/selftest_engine_cs.c|  4 ++--
 drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c |  4 ++--
 drivers/gpu/drm/i915/gt/selftest_execlists.c|  6 +++---
 drivers/gpu/drm/i915/gt/selftest_gt_pm.c|  8 
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c|  2 +-
 drivers/gpu/drm/i915/gt/selftest_lrc.c  |  2 +-
 drivers/gpu/drm/i915/gt/selftest_migrate.c  |  4 ++--
 drivers/gpu/drm/i915/gt/selftest_mocs.c |  2 +-
 drivers/gpu/drm/i915/gt/selftest_reset.c|  2 +-
 drivers/gpu/drm/i915/gt/selftest_ring_submission.c  |  4 ++--
 drivers/gpu/drm/i915/gt/selftest_slpc.c |  6 +++---
 drivers/gpu/drm/i915/gt/selftest_timeline.c |  6 +++---
 drivers/gpu/drm/i915/gt/selftest_workarounds.c  |  4 ++--
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c |  2 +-
 drivers/gpu/drm/i915/gt/uc/selftest_guc.c   |  2 +-
 drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c |  2 +-
 23 files changed, 46 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c 
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 8f8bea08e734..9ce85a845105 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -116,7 +116,7 @@ static void set_scheduler_caps(struct drm_i915_private 
*i915)
disabled |= (I915_SCHEDULER_CAP_ENABLED |
 I915_SCHEDULER_CAP_PRIORITY);
 
-   if (intel_uc_uses_guc_submission(>gt.uc))
+   if (intel_uc_uses_guc_submission(_gt(i915)->uc))
enabled |= I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP;
 
for (i = 0; i < ARRAY_SIZE(map); i++) {
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index d85a1050f4a8..971e737b37b2 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -1232,7 +1232,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
 {
int ret;
 
-   ret = ggtt_probe_hw(>ggtt, >gt);
+   ret = ggtt_probe_hw(>ggtt, to_gt(i915));
if (ret)
return ret;
 
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 07ff7ba7b2b7..36eb980d757e 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2302,7 +2302,7 @@ unsigned long i915_read_mch_val(void)
return 0;
 
with_intel_runtime_pm(>runtime_pm, wakeref) {
-   struct intel_ips *ips = >gt.rps.ips;
+   struct intel_ips *ips = _gt(i915)->rps.ips;
 
spin_lock_irq(_lock);
chipset_val = __ips_chipset_val(ips);
@@ -2329,7 +2329,7 @@ bool i915_gpu_raise(void)
if (!i915)
return false;
 
-   rps = >gt.rps;
+   rps = _gt(i915)->rps;
 
spin_lock_irq(_lock);
if (rps->max_freq_softlimit < rps->max_freq)
@@ -2356,7 +2356,7 @@ bool i915_gpu_lower(void)
if (!i915)
return false;
 
-   rps = >gt.rps;
+   rps = _gt(i915)->rps;
 
spin_lock_irq(_lock);
if (rps->max_freq_softlimit > rps->min_freq)
@@ -2382,7 +2382,7 @@ bool i915_gpu_busy(void)
if (!i915)
return false;
 
-   ret = i915->gt.awake;
+   ret = to_gt(i915)->awake;
 
drm_dev_put(>drm);
return ret;
@@ -2405,11 +2405,11 @@ bool i915_gpu_turbo_disable(void)
if (!i915)
return false;
 
-   rps = >gt.rps;
+   rps = _gt(i915)->rps;
 
spin_lock_irq(_lock);
rps->max_freq_softlimit = rps->min_freq;
-   ret = !__gen5_rps_set(>gt.rps, rps->min_freq);
+   ret = !__gen5_rps_set(_gt(i915)->rps, rps->min_freq);
spin_unlock_irq(_lock);
 
drm_dev_put(>drm);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3113266c286e..ab3277a3d593 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -929,7 +929,7 @@ hsw_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
 static void
 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 

[Intel-gfx] [PATCH v8 03/16] drm/i915/display: Use to_gt() helper

[Andi Shyti]

From: Michał Winiarski 

Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.

Signed-off-by: Michał Winiarski 
Signed-off-by: Andi Shyti 
Reviewed-by: Matt Roper 
---
 .../gpu/drm/i915/display/intel_atomic_plane.c  |  4 ++--
 drivers/gpu/drm/i915/display/intel_display.c   | 18 +-
 drivers/gpu/drm/i915/display/intel_dpt.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_overlay.c   |  2 +-
 .../gpu/drm/i915/display/skl_universal_plane.c |  2 +-
 5 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 89005628cc3a..c2c512cd8ec0 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -819,7 +819,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
 * maximum clocks following a vblank miss (see do_rps_boost()).
 */
if (!state->rps_interactive) {
-   intel_rps_mark_interactive(_priv->gt.rps, true);
+   intel_rps_mark_interactive(_gt(dev_priv)->rps, true);
state->rps_interactive = true;
}
 
@@ -853,7 +853,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
return;
 
if (state->rps_interactive) {
-   intel_rps_mark_interactive(_priv->gt.rps, false);
+   intel_rps_mark_interactive(_gt(dev_priv)->rps, false);
state->rps_interactive = false;
}
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 6fbad5c6cc71..bf7ce684dd8e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -843,7 +843,7 @@ __intel_display_resume(struct drm_device *dev,
 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
 {
return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
-   intel_has_gpu_reset(_priv->gt));
+   intel_has_gpu_reset(to_gt(dev_priv)));
 }
 
 void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
@@ -862,14 +862,14 @@ void intel_display_prepare_reset(struct drm_i915_private 
*dev_priv)
return;
 
/* We have a modeset vs reset deadlock, defensively unbreak it. */
-   set_bit(I915_RESET_MODESET, _priv->gt.reset.flags);
+   set_bit(I915_RESET_MODESET, _gt(dev_priv)->reset.flags);
smp_mb__after_atomic();
-   wake_up_bit(_priv->gt.reset.flags, I915_RESET_MODESET);
+   wake_up_bit(_gt(dev_priv)->reset.flags, I915_RESET_MODESET);
 
if (atomic_read(_priv->gpu_error.pending_fb_pin)) {
drm_dbg_kms(_priv->drm,
"Modeset potentially stuck, unbreaking through 
wedging\n");
-   intel_gt_set_wedged(_priv->gt);
+   intel_gt_set_wedged(to_gt(dev_priv));
}
 
/*
@@ -920,7 +920,7 @@ void intel_display_finish_reset(struct drm_i915_private 
*dev_priv)
return;
 
/* reset doesn't touch the display */
-   if (!test_bit(I915_RESET_MODESET, _priv->gt.reset.flags))
+   if (!test_bit(I915_RESET_MODESET, _gt(dev_priv)->reset.flags))
return;
 
state = fetch_and_zero(_priv->modeset_restore_state);
@@ -958,7 +958,7 @@ void intel_display_finish_reset(struct drm_i915_private 
*dev_priv)
drm_modeset_acquire_fini(ctx);
mutex_unlock(>mode_config.mutex);
 
-   clear_bit_unlock(I915_RESET_MODESET, _priv->gt.reset.flags);
+   clear_bit_unlock(I915_RESET_MODESET, _gt(dev_priv)->reset.flags);
 }
 
 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
@@ -8513,19 +8513,19 @@ static void intel_atomic_commit_fence_wait(struct 
intel_atomic_state *intel_stat
for (;;) {
prepare_to_wait(_state->commit_ready.wait,
_fence, TASK_UNINTERRUPTIBLE);
-   prepare_to_wait(bit_waitqueue(_priv->gt.reset.flags,
+   prepare_to_wait(bit_waitqueue(_gt(dev_priv)->reset.flags,
  I915_RESET_MODESET),
_reset, TASK_UNINTERRUPTIBLE);
 
 
if (i915_sw_fence_done(_state->commit_ready) ||
-   test_bit(I915_RESET_MODESET, _priv->gt.reset.flags))
+   test_bit(I915_RESET_MODESET, _gt(dev_priv)->reset.flags))
break;
 
schedule();
}
finish_wait(_state->commit_ready.wait, _fence);
-   finish_wait(bit_waitqueue(_priv->gt.reset.flags,
+   finish_wait(bit_waitqueue(_gt(dev_priv)->reset.flags,
  I915_RESET_MODESET),
_reset);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c 
b/drivers/gpu/drm/i915/display/intel_dpt.c
index 963ca7155b06..ce760402a89a 100644

[Intel-gfx] [PATCH v8 02/16] drm/i915: Introduce to_gt() helper

[Andi Shyti]

From: Michał Winiarski 

To allow further refactoring and abstract away the fact that GT is
stored inside i915 private.
No functional changes.

Signed-off-by: Michał Winiarski 
Signed-off-by: Andi Shyti 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c | 7 +--
 drivers/gpu/drm/i915/i915_drv.h| 5 +
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c 
b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
index acc49c56a9f3..9db3dcbd917f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
@@ -9,11 +9,6 @@
 #include "intel_engine_pm.h"
 #include "intel_gt_buffer_pool.h"
 
-static struct intel_gt *to_gt(struct intel_gt_buffer_pool *pool)
-{
-   return container_of(pool, struct intel_gt, buffer_pool);
-}
-
 static struct list_head *
 bucket_for_size(struct intel_gt_buffer_pool *pool, size_t sz)
 {
@@ -141,7 +136,7 @@ static struct intel_gt_buffer_pool_node *
 node_create(struct intel_gt_buffer_pool *pool, size_t sz,
enum i915_map_type type)
 {
-   struct intel_gt *gt = to_gt(pool);
+   struct intel_gt *gt = container_of(pool, struct intel_gt, buffer_pool);
struct intel_gt_buffer_pool_node *node;
struct drm_i915_gem_object *obj;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 47a9b1cb8eab..373455f2aa6e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1077,6 +1077,11 @@ static inline struct drm_i915_private 
*pdev_to_i915(struct pci_dev *pdev)
return pci_get_drvdata(pdev);
 }
 
+static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
+{
+   return >gt;
+}
+
 /* Simple iterator over all initialised engines */
 #define for_each_engine(engine__, dev_priv__, id__) \
for ((id__) = 0; \
-- 
2.34.1

[Intel-gfx] [PATCH v8 01/16] drm/i915: Store backpointer to GT in uncore

[Andi Shyti]

From: Michał Winiarski 

We now support a per-gt uncore, yet we're not able to infer which GT
we're operating upon.  Let's store a backpointer for now.

At this point the early initialization of the gt needs to be
broken in two parts where the first is needed to assign to the gt
the i915 private data pointer and the uncore. A temporary
function has been made and the two parts are
__intel_gt_init_early() and intel_gt_init_early(). This split
will be fixed in the future with the multitile patch.

Signed-off-by: Michał Winiarski 
Signed-off-by: Matt Roper 
Reviewed-by: Andi Shyti 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gt/intel_gt.c   | 11 +++
 drivers/gpu/drm/i915/gt/intel_gt.h   |  1 +
 drivers/gpu/drm/i915/i915_driver.c   |  5 +++--
 drivers/gpu/drm/i915/intel_uncore.c  |  9 +
 drivers/gpu/drm/i915/intel_uncore.h  |  3 ++-
 drivers/gpu/drm/i915/selftests/mock_gem_device.c |  4 ++--
 drivers/gpu/drm/i915/selftests/mock_uncore.c |  2 +-
 7 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f2422d48be32..f98f0fb21efb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -25,11 +25,8 @@
 #include "shmem_utils.h"
 #include "pxp/intel_pxp.h"
 
-void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
+void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
 {
-   gt->i915 = i915;
-   gt->uncore = >uncore;
-
spin_lock_init(>irq_lock);
 
INIT_LIST_HEAD(>closed_vma);
@@ -48,6 +45,12 @@ void intel_gt_init_early(struct intel_gt *gt, struct 
drm_i915_private *i915)
intel_rps_init_early(>rps);
 }
 
+void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
+{
+   gt->i915 = i915;
+   gt->uncore = >uncore;
+}
+
 int intel_gt_probe_lmem(struct intel_gt *gt)
 {
struct drm_i915_private *i915 = gt->i915;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h 
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 74e771871a9b..3ace129eb2af 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -35,6 +35,7 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc 
*huc)
 }
 
 void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
+void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
 void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt);
 int intel_gt_probe_lmem(struct intel_gt *gt);
 int intel_gt_init_mmio(struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index e9125f14b3d1..42ae5a12040d 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -314,8 +314,9 @@ static int i915_driver_early_probe(struct drm_i915_private 
*dev_priv)
intel_device_info_subplatform_init(dev_priv);
intel_step_init(dev_priv);
 
+   intel_gt_init_early(_priv->gt, dev_priv);
intel_uncore_mmio_debug_init_early(_priv->mmio_debug);
-   intel_uncore_init_early(_priv->uncore, dev_priv);
+   intel_uncore_init_early(_priv->uncore, _priv->gt);
 
spin_lock_init(_priv->irq_lock);
spin_lock_init(_priv->gpu_error.lock);
@@ -346,7 +347,7 @@ static int i915_driver_early_probe(struct drm_i915_private 
*dev_priv)
 
intel_wopcm_init_early(_priv->wopcm);
 
-   intel_gt_init_early(_priv->gt, dev_priv);
+   __intel_gt_init_early(_priv->gt, dev_priv);
 
i915_gem_init_early(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index abdac78d3976..fc25ebf1a593 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2061,12 +2061,13 @@ void intel_uncore_cleanup_mmio(struct intel_uncore 
*uncore)
 }
 
 void intel_uncore_init_early(struct intel_uncore *uncore,
-struct drm_i915_private *i915)
+struct intel_gt *gt)
 {
spin_lock_init(>lock);
-   uncore->i915 = i915;
-   uncore->rpm = >runtime_pm;
-   uncore->debug = >mmio_debug;
+   uncore->i915 = gt->i915;
+   uncore->gt = gt;
+   uncore->rpm = >i915->runtime_pm;
+   uncore->debug = >i915->mmio_debug;
 }
 
 static void uncore_raw_init(struct intel_uncore *uncore)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h 
b/drivers/gpu/drm/i915/intel_uncore.h
index d1d17b04e29f..210fe2a71612 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -129,6 +129,7 @@ struct intel_uncore {
void __iomem *regs;
 
struct drm_i915_private *i915;
+   struct intel_gt *gt;
struct intel_runtime_pm *rpm;
 
spinlock_t lock; /** lock is also taken in irq contexts. */
@@ -217,7 +218,7 @@ u32 

[Intel-gfx] [PATCH v8 00/16] More preparation for multi gt patches

[Andi Shyti]

Hi,

the first patch concludes the first stage of refactoring which
makes the use of intel_gt on the different subsystem. It's taken
from Matt's series and it has alread been reviewed. The patch has
just been replaced before any multitile patches and I think it
can be already pushed.

Patch 2-10 hides i915->gt behind the to_gt() wrapper proposed by
Michał. Finally i915->gt changes to i915->gt0.

The last six patches abstract the ggtt reference forcing the use
of the ggtt in the gt structure rather than in the i915.

Thanks a lot Matt for the reviews.

Andi

Changelog:
==
Patchwork: https://patchwork.freedesktop.org/series/97020/

v7 -> v8:
 - Removed patch 11 from v7 that was allocating statically the
   ggtt in the gt structure instead of a dynamic allocation. As
   Matt pointed out, we can have GT's sharing the same GGTT.
 - The whole i915->ggtt to gt->ggtt patch is split in 5 patches
   instead of one single to make it easier to review.
 - The last patch removes i915->ggtt and allocates the gt->ggtt
   with drmm_kzalloc in the early probe and mock device.

v6 -> v7:
 - Patch 1: add a note about the double presence of
   __intel_gt_init_early() and intel_gt_init_early().
 - Added all Matt's r-b's for patches 2-10.
 - Added a patch 12 that moves the i915->ggtt into gt->ggtt.

v5 -> v6:
 - fixed the assignement of i915->gt->ggtt = ggtt in the mock gem
   device that was making use of it before.

v4 -> v5:
 - use to_gt() instead of to_root_gt() and use Michał work done
   previously.
 - split the /i915->gt/to_gt()/ patch in smaller chunks in order
   to make review easier. (Thanks Lucas)

v3 -> v4:
 - the intel_gt_init_early() has been split as it was causing
   some headaches for the order of the early initialization. The
   split has been done keeping in mind the coming next patch in
   the series that wil make this a static function.

v2 -> v3:
 - sed -i ... took too much freedom and changed more than it was
   supposed to.
 - fix a compile error which did not appear in my local build

v1 -> v2:
 - patch 2: do not use anymore the reference i915->gt but use
   to_root_gt(), coming from Matt Roper's patch.
 - fix some comments from Chris.

Andi Shyti (4):
  drm/i915/selftests: Use to_gt() helper
  drm/i915/pxp: Use to_gt() helper
  drm/i915: Rename i915->gt to i915->gt0
  drm/i915: Move the GGTT from i915 private data to the GT

Michał Winiarski (8):
  drm/i915: Store backpointer to GT in uncore
  drm/i915: Introduce to_gt() helper
  drm/i915/display: Use to_gt() helper
  drm/i915/gt: Use to_gt() helper
  drm/i915/gem: Use to_gt() helper
  drm/i915/gvt: Use to_gt() helper
  drm/i915: Use to_gt() helper
  drm/i915: Use to_gt() helper for GGTT accesses

Andi Shyti (4):
  drm/i915/selftests: Use to_gt() helper
  drm/i915/pxp: Use to_gt() helper
  drm/i915: Rename i915->gt to i915->gt0
  drm/i915: Remove unused i915->ggtt

Michał Winiarski (12):
  drm/i915: Store backpointer to GT in uncore
  drm/i915: Introduce to_gt() helper
  drm/i915/display: Use to_gt() helper
  drm/i915/gt: Use to_gt() helper
  drm/i915/gem: Use to_gt() helper
  drm/i915/gvt: Use to_gt() helper
  drm/i915: Use to_gt() helper
  drm/i915/gem: Use to_gt() helper for GGTT accesses
  drm/i915/display: Use to_gt() helper for GGTT accesses
  drm/i915/gt: Use to_gt() helper for GGTT accesses
  drm/i915/selftests: Use to_gt() helper for GGTT accesses
  drm/i915: Use to_gt() helper for GGTT accesses

 .../gpu/drm/i915/display/intel_atomic_plane.c |  4 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 18 +++---
 drivers/gpu/drm/i915/display/intel_dpt.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_fbc.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_fbdev.c|  2 +-
 drivers/gpu/drm/i915/display/intel_overlay.c  |  2 +-
 .../drm/i915/display/intel_plane_initial.c|  2 +-
 .../drm/i915/display/skl_universal_plane.c|  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_context.c   | 22 
 drivers/gpu/drm/i915/gem/i915_gem_context.h   |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_create.c|  2 +-
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c|  6 +-
 drivers/gpu/drm/i915/gem/i915_gem_mman.c  | 21 +++
 drivers/gpu/drm/i915/gem/i915_gem_phys.c  |  6 +-
 drivers/gpu/drm/i915/gem/i915_gem_pm.c|  8 +--
 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c  |  8 +--
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c|  8 ++-
 drivers/gpu/drm/i915/gem/i915_gem_throttle.c  |  3 +-
 drivers/gpu/drm/i915/gem/i915_gem_tiling.c| 15 ++---
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c  | 12 ++--
 drivers/gpu/drm/i915/gem/i915_gem_userptr.c   |  2 +-
 .../gpu/drm/i915/gem/selftests/huge_pages.c   |  4 +-
 .../i915/gem/selftests/i915_gem_client_blt.c  |  4 +-
 .../drm/i915/gem/selftests/i915_gem_context.c | 12 ++--
 .../drm/i915/gem/selftests/i915_gem_migrate.c |  2 +-
 .../drm/i915/gem/selftests/i915_gem_mman.c| 45 ---
 .../drm/i915/gem/selftests/i915_gem_object.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_engine_user.c  

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: remove writeback hook

[Patchwork]

== Series Details ==

Series: drm/i915: remove writeback hook
URL   : https://patchwork.freedesktop.org/series/98029/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11002 -> Patchwork_21848


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/index.html

Participating hosts (46 -> 35)
--

  Missing(11): bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 
bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus bat-jsl-2 bat-jsl-1 

Known issues


  Here are the changes found in Patchwork_21848 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka:   NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4:  [PASS][2] -> [FAIL][3] ([i915#1888])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html

  
 Possible fixes 

  * igt@i915_selftest@live@execlists:
- fi-bsw-kefka:   [INCOMPLETE][4] ([i915#2940]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2:  [DMESG-WARN][6] ([i915#4269]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html

  
 Warnings 

  * igt@gem_flink_basic@bad-flink:
- fi-skl-6600u:   [INCOMPLETE][8] ([i915#4547]) -> [FAIL][9] 
([i915#4547])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html

  * igt@runner@aborted:
- fi-skl-6600u:   [FAIL][10] ([i915#2722] / [i915#4312]) -> [FAIL][11] 
([i915#4312])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/fi-skl-6600u/igt@run...@aborted.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/fi-skl-6600u/igt@run...@aborted.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547


Build changes
-

  * Linux: CI_DRM_11002 -> Patchwork_21848

  CI-20190529: 20190529
  CI_DRM_11002: 8dabbcc22a6b77b358ff35d31adbaa653ab45857 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6307: be84fe4f151bc092e068cab5cd0cd19c34948b40 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21848: 9e49009ab0fa8a63f7641eccbe5e8a1ed80f1f78 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

9e49009ab0fa drm/i915: remove writeback hook

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21848/index.html

[Intel-gfx] [PATCH v3 1/5] drm/i915/fbc: Parametrize FBC register offsets

[Ville Syrjala]

From: Ville Syrjälä 

Parametrize ilk+ FBC register offsets based on the FBC instance.

v2: More intel_ namespace (Jani)
v3: Don't break gvt (Jani)

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 34 +---
 drivers/gpu/drm/i915/display/intel_fbc.h |  6 +
 drivers/gpu/drm/i915/gvt/handlers.c  | 13 -
 drivers/gpu/drm/i915/i915_reg.h  | 34 
 drivers/gpu/drm/i915/intel_pm.c  | 31 -
 5 files changed, 67 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 8be01b93015f..112aafa72253 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -85,6 +85,8 @@ struct intel_fbc {
struct drm_mm_node compressed_fb;
struct drm_mm_node compressed_llb;
 
+   enum intel_fbc_id id;
+
u8 limit;
 
bool false_color;
@@ -454,10 +456,10 @@ static void ilk_fbc_activate(struct intel_fbc *fbc)
struct intel_fbc_state *fbc_state = >state;
struct drm_i915_private *i915 = fbc->i915;
 
-   intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
+   intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
   fbc_state->fence_y_offset);
 
-   intel_de_write(i915, ILK_DPFC_CONTROL,
+   intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
   DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
 }
 
@@ -467,28 +469,28 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
u32 dpfc_ctl;
 
/* Disable compression */
-   dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL);
+   dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
if (dpfc_ctl & DPFC_CTL_EN) {
dpfc_ctl &= ~DPFC_CTL_EN;
-   intel_de_write(i915, ILK_DPFC_CONTROL, dpfc_ctl);
+   intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
}
 }
 
 static bool ilk_fbc_is_active(struct intel_fbc *fbc)
 {
-   return intel_de_read(fbc->i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
+   return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & 
DPFC_CTL_EN;
 }
 
 static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
 {
-   return intel_de_read(fbc->i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK;
+   return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & 
DPFC_COMP_SEG_MASK;
 }
 
 static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
 {
struct drm_i915_private *i915 = fbc->i915;
 
-   intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
+   intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), 
fbc->compressed_fb.start);
 }
 
 static const struct intel_fbc_funcs ilk_fbc_funcs = {
@@ -524,8 +526,8 @@ static void snb_fbc_nuke(struct intel_fbc *fbc)
 {
struct drm_i915_private *i915 = fbc->i915;
 
-   intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE);
-   intel_de_posting_read(i915, MSG_FBC_REND_STATE);
+   intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
+   intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
 }
 
 static const struct intel_fbc_funcs snb_fbc_funcs = {
@@ -547,7 +549,7 @@ static void glk_fbc_program_cfb_stride(struct intel_fbc 
*fbc)
val |= FBC_STRIDE_OVERRIDE |
FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
 
-   intel_de_write(i915, GLK_FBC_STRIDE, val);
+   intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
 }
 
 static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
@@ -598,19 +600,19 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
if (i915->ggtt.num_fences)
snb_fbc_program_fence(fbc);
 
-   intel_de_write(i915, ILK_DPFC_CONTROL,
+   intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
   DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
 }
 
 static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
 {
-   return intel_de_read(fbc->i915, ILK_DPFC_STATUS2) & 
DPFC_COMP_SEG_MASK_IVB;
+   return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & 
DPFC_COMP_SEG_MASK_IVB;
 }
 
 static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
bool enable)
 {
-   intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL,
+   intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
 DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
 }
 
@@ -1620,7 +1622,8 @@ void intel_fbc_add_plane(struct intel_fbc *fbc, struct 
intel_plane *plane)
fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
 }
 
-static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915)
+static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
+ enum intel_fbc_id fbc_id)
 {
struct intel_fbc *fbc;
 
@@ -1628,6 +1631,7 @@ static struct intel_fbc 

Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/fbc: Register per-crtc debugfs files

[Ville Syrjälä]

On Mon, Dec 13, 2021 at 09:09:40PM +0200, Jani Nikula wrote:
> On Mon, 13 Dec 2021, Ville Syrjala  wrote:
> > From: Ville Syrjälä 
> >
> > Expose FBC debugfs files for each crtc. These may or may not point
> > to the same FBC instance depending on the platform.
> >
> > We leave the old global debugfs files in place until
> > igt catches up to the new per-crtc approach.
> >
> > v2: Take a trip via intel_crtc_debugfs_add() (Jani)
> >
> > Cc: Jani Nikula 
> > Signed-off-by: Ville Syrjälä 
> 
> Reviewed-by: Jani Nikula 
> 
> > ---
> >  .../drm/i915/display/intel_display_debugfs.c  |  7 +++--
> >  drivers/gpu/drm/i915/display/intel_fbc.c  | 31 ---
> >  drivers/gpu/drm/i915/display/intel_fbc.h  |  1 +
> >  3 files changed, 25 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index 572445299b04..f4de004d470f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -2402,6 +2402,9 @@ void intel_connector_debugfs_add(struct 
> > intel_connector *intel_connector)
> >   */
> >  void intel_crtc_debugfs_add(struct drm_crtc *crtc)
> >  {
> > -   if (crtc->debugfs_entry)
> > -   crtc_updates_add(crtc);
> > +   if (!crtc->debugfs_entry)
> > +   return;
> 
> I think this is probably unnecessary, but that's for another patch.

I guess. Seems unlikely at best that we'd have failed to allocate
that.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets

[Jani Nikula]

On Tue, 14 Dec 2021, Ville Syrjälä  wrote:
> On Mon, Dec 13, 2021 at 09:54:04PM +0200, Jani Nikula wrote:
>> On Mon, 13 Dec 2021, Ville Syrjala  wrote:
>> > From: Ville Syrjälä 
>> >
>> > Parametrize ilk+ FBC register offsets based on the FBC instance.
>> >
>> > v2: More intel_ namespace (Jani)
>> >
>> > Cc: Jani Nikula 
>> > Signed-off-by: Ville Syrjälä 
>> 
>> Some questions below, apart from that,
>> 
>> Reviewed-by: Jani Nikula 
>> 
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_fbc.c | 34 +---
>> >  drivers/gpu/drm/i915/display/intel_fbc.h |  6 +
>> >  drivers/gpu/drm/i915/i915_reg.h  | 34 
>> >  drivers/gpu/drm/i915/intel_pm.c  | 31 -
>> >  4 files changed, 60 insertions(+), 45 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
>> > b/drivers/gpu/drm/i915/display/intel_fbc.c
>> > index 8be01b93015f..112aafa72253 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> > @@ -85,6 +85,8 @@ struct intel_fbc {
>> >struct drm_mm_node compressed_fb;
>> >struct drm_mm_node compressed_llb;
>> >  
>> > +  enum intel_fbc_id id;
>> > +
>> >u8 limit;
>> >  
>> >bool false_color;
>> > @@ -454,10 +456,10 @@ static void ilk_fbc_activate(struct intel_fbc *fbc)
>> >struct intel_fbc_state *fbc_state = >state;
>> >struct drm_i915_private *i915 = fbc->i915;
>> >  
>> > -  intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
>> > +  intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
>> >   fbc_state->fence_y_offset);
>> >  
>> > -  intel_de_write(i915, ILK_DPFC_CONTROL,
>> > +  intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
>> >   DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
>> >  }
>> >  
>> > @@ -467,28 +469,28 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
>> >u32 dpfc_ctl;
>> >  
>> >/* Disable compression */
>> > -  dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL);
>> > +  dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
>> >if (dpfc_ctl & DPFC_CTL_EN) {
>> >dpfc_ctl &= ~DPFC_CTL_EN;
>> > -  intel_de_write(i915, ILK_DPFC_CONTROL, dpfc_ctl);
>> > +  intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
>> >}
>> >  }
>> >  
>> >  static bool ilk_fbc_is_active(struct intel_fbc *fbc)
>> >  {
>> > -  return intel_de_read(fbc->i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
>> > +  return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & 
>> > DPFC_CTL_EN;
>> >  }
>> >  
>> >  static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
>> >  {
>> > -  return intel_de_read(fbc->i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK;
>> > +  return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & 
>> > DPFC_COMP_SEG_MASK;
>> >  }
>> >  
>> >  static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
>> >  {
>> >struct drm_i915_private *i915 = fbc->i915;
>> >  
>> > -  intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
>> > +  intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), 
>> > fbc->compressed_fb.start);
>> >  }
>> >  
>> >  static const struct intel_fbc_funcs ilk_fbc_funcs = {
>> > @@ -524,8 +526,8 @@ static void snb_fbc_nuke(struct intel_fbc *fbc)
>> >  {
>> >struct drm_i915_private *i915 = fbc->i915;
>> >  
>> > -  intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE);
>> > -  intel_de_posting_read(i915, MSG_FBC_REND_STATE);
>> > +  intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
>> > +  intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
>> >  }
>> >  
>> >  static const struct intel_fbc_funcs snb_fbc_funcs = {
>> > @@ -547,7 +549,7 @@ static void glk_fbc_program_cfb_stride(struct 
>> > intel_fbc *fbc)
>> >val |= FBC_STRIDE_OVERRIDE |
>> >FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
>> >  
>> > -  intel_de_write(i915, GLK_FBC_STRIDE, val);
>> > +  intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
>> >  }
>> >  
>> >  static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
>> > @@ -598,19 +600,19 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
>> >if (i915->ggtt.num_fences)
>> >snb_fbc_program_fence(fbc);
>> >  
>> > -  intel_de_write(i915, ILK_DPFC_CONTROL,
>> > +  intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
>> >   DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
>> >  }
>> >  
>> >  static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
>> >  {
>> > -  return intel_de_read(fbc->i915, ILK_DPFC_STATUS2) & 
>> > DPFC_COMP_SEG_MASK_IVB;
>> > +  return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & 
>> > DPFC_COMP_SEG_MASK_IVB;
>> >  }
>> >  
>> >  static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
>> >bool enable)
>> >  {
>> > -  intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL,
>> > +  intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
>> > DPFC_CTL_FALSE_COLOR, enable ? 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: remove writeback hook

[Patchwork]

== Series Details ==

Series: drm/i915: remove writeback hook
URL   : https://patchwork.freedesktop.org/series/98029/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Fix stealing guc_ids + test (rev3)

[Patchwork]

== Series Details ==

Series: Fix stealing guc_ids + test (rev3)
URL   : https://patchwork.freedesktop.org/series/97896/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11002 -> Patchwork_21847


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/index.html

Participating hosts (46 -> 34)
--

  Missing(12): bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bdw-gvtdvm fi-bsw-cyan 
bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus bat-jsl-2 bat-jsl-1 

Known issues


  Here are the changes found in Patchwork_21847 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka:   NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u:   NOTRUN -> [SKIP][2] ([fdo#109271]) +21 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html

  * igt@gem_huc_copy@huc-copy:
- fi-skl-6600u:   NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u:   NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html

  * igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u:   NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u:   NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#533])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  
 Possible fixes 

  * igt@gem_flink_basic@bad-flink:
- fi-skl-6600u:   [INCOMPLETE][7] ([i915#4547]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-kefka:   [INCOMPLETE][9] ([i915#2940]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2:  [DMESG-WARN][11] ([i915#4269]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11002/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-

  * Linux: CI_DRM_11002 -> Patchwork_21847

  CI-20190529: 20190529
  CI_DRM_11002: 8dabbcc22a6b77b358ff35d31adbaa653ab45857 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6307: be84fe4f151bc092e068cab5cd0cd19c34948b40 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21847: c07631e2c9dfcef2599ea8f76bd23049eee201e5 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c07631e2c9df drm/i915/guc: Selftest for stealing of guc ids
344e5cf583e1 drm/i915/guc: Kick G2H tasklet if no credits
cbcb8fe154c3 drm/i915/guc: Add extra debug on CT deadlock
4d46938487d5 drm/i915/guc: Don't hog IRQs when destroying contexts
16e7a94892d5 drm/i915/guc: Remove racey GEM_BUG_ON
b2c8358f28bf drm/i915/guc: Only assign guc_id.id when stealing guc_id
b855be58ca75 drm/i915/guc: Use correct context lock when callig 
clr_context_registered

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21847/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Fix stealing guc_ids + test (rev3)

[Patchwork]

== Series Details ==

Series: Fix stealing guc_ids + test (rev3)
URL   : https://patchwork.freedesktop.org/series/97896/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix stealing guc_ids + test (rev3)

[Patchwork]

== Series Details ==

Series: Fix stealing guc_ids + test (rev3)
URL   : https://patchwork.freedesktop.org/series/97896/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b855be58ca75 drm/i915/guc: Use correct context lock when callig 
clr_context_registered
b2c8358f28bf drm/i915/guc: Only assign guc_id.id when stealing guc_id
16e7a94892d5 drm/i915/guc: Remove racey GEM_BUG_ON
4d46938487d5 drm/i915/guc: Don't hog IRQs when destroying contexts
cbcb8fe154c3 drm/i915/guc: Add extra debug on CT deadlock
344e5cf583e1 drm/i915/guc: Kick G2H tasklet if no credits
c07631e2c9df drm/i915/guc: Selftest for stealing of guc ids
-:183: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#183: FILE: drivers/gpu/drm/i915/gt/uc/selftest_guc.c:153:
+   if (!ce) {
+   pr_err("Context array allocation failed\n");

total: 0 errors, 1 warnings, 0 checks, 265 lines checked

[Intel-gfx] [PATCH] drm/i915: remove writeback hook

[Matthew Auld]

Ditch the writeback hook and drop i915_gem_object_writeback(). We
already support the shrinker_release_pages hook which can just call
shmem_writeback directly.

Suggested-by: Tvrtko Ursulin 
Signed-off-by: Matthew Auld 
---
 drivers/gpu/drm/i915/gem/i915_gem_object.h|  1 -
 .../gpu/drm/i915/gem/i915_gem_object_types.h  |  1 -
 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 10 --
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 19 ++-
 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c  | 12 
 5 files changed, 18 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 66f20b803b01..aaf9183e601b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -455,7 +455,6 @@ i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
 
 int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
 int i915_gem_object_truncate(struct drm_i915_gem_object *obj);
-void i915_gem_object_writeback(struct drm_i915_gem_object *obj);
 
 /**
  * i915_gem_object_pin_map - return a contiguous mapping of the entire object
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index f9f7e44099fe..00c844caeabd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -57,7 +57,6 @@ struct drm_i915_gem_object_ops {
void (*put_pages)(struct drm_i915_gem_object *obj,
  struct sg_table *pages);
int (*truncate)(struct drm_i915_gem_object *obj);
-   void (*writeback)(struct drm_i915_gem_object *obj);
int (*shrinker_release_pages)(struct drm_i915_gem_object *obj,
  bool no_gpu_wait,
  bool should_writeback);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c 
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 49c6e55c68ce..52e975f57956 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -168,16 +168,6 @@ int i915_gem_object_truncate(struct drm_i915_gem_object 
*obj)
return 0;
 }
 
-/* Try to discard unwanted pages */
-void i915_gem_object_writeback(struct drm_i915_gem_object *obj)
-{
-   assert_object_held_shared(obj);
-   GEM_BUG_ON(i915_gem_object_has_pages(obj));
-
-   if (obj->ops->writeback)
-   obj->ops->writeback(obj);
-}
-
 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
 {
struct radix_tree_iter iter;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c 
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index cc9fe258fba7..7fdf4fa10b0e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -331,6 +331,23 @@ shmem_writeback(struct drm_i915_gem_object *obj)
__shmem_writeback(obj->base.size, obj->base.filp->f_mapping);
 }
 
+static int shmem_shrinker_release_pages(struct drm_i915_gem_object *obj,
+   bool no_gpu_wait,
+   bool writeback)
+{
+   switch (obj->mm.madv) {
+   case I915_MADV_DONTNEED:
+   return i915_gem_object_truncate(obj);
+   case __I915_MADV_PURGED:
+   return 0;
+   }
+
+   if (writeback)
+   shmem_writeback(obj);
+
+   return 0;
+}
+
 void
 __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
struct sg_table *pages,
@@ -503,7 +520,7 @@ const struct drm_i915_gem_object_ops i915_gem_shmem_ops = {
.get_pages = shmem_get_pages,
.put_pages = shmem_put_pages,
.truncate = shmem_truncate,
-   .writeback = shmem_writeback,
+   .shrinker_release_pages = shmem_shrinker_release_pages,
 
.pwrite = shmem_pwrite,
.pread = shmem_pread,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c 
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index 157a9765f483..fd54e05521f6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -61,18 +61,6 @@ static int try_to_writeback(struct drm_i915_gem_object *obj, 
unsigned int flags)
return obj->ops->shrinker_release_pages(obj,
!(flags & 
I915_SHRINK_ACTIVE),
flags & 
I915_SHRINK_WRITEBACK);
-
-   switch (obj->mm.madv) {
-   case I915_MADV_DONTNEED:
-   i915_gem_object_truncate(obj);
-   return 0;
-   case __I915_MADV_PURGED:
-   return 0;
-   }
-
-   if (flags & I915_SHRINK_WRITEBACK)
-   i915_gem_object_writeback(obj);
-
return 0;
 }
 
-- 
2.31.1

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets

[Ville Syrjälä]

On Tue, Dec 14, 2021 at 06:25:43PM +0200, Ville Syrjälä wrote:
> On Mon, Dec 13, 2021 at 09:54:04PM +0200, Jani Nikula wrote:
> > On Mon, 13 Dec 2021, Ville Syrjala  wrote:
> > 
> > This one is only used in gvt, anyway. And that actually makes me wonder
> > if this should be breaking the build. Does CI not have gvt enabled?
> 
> Hmm. I thought it was enabled in CI, but maybe not. I've often broken
> gvt with register define changes but I've always caught it before
> pushing. I think I have gvt enabled in my "make sure all commits build
> before I push" test config, so maybe that's where I caught most of them.
> 
> Tomi, can we enable gvt in ci builds to make sure it at least still
> builds?

Actually cc Tomi..

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/debugfs: add noreclaim annotations (rev2)

[Vudum, Lakshminarayana]

All are known issues. Re-reported the results.

-Original Message-
From: Auld, Matthew  
Sent: Tuesday, December 14, 2021 1:26 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/debugfs: add noreclaim 
annotations (rev2)

On 14/12/2021 04:55, Patchwork wrote:
> *Patch Details*
> *Series:* drm/i915/debugfs: add noreclaim annotations (rev2)
> *URL:*https://patchwork.freedesktop.org/series/97966/ 
> 
> *State:*  failure
> *Details:*
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/index.html
> 
> 
> 
>   CI Bug Log - changes from CI_DRM_10996_full -> Patchwork_21842_full
> 
> 
> Summary
> 
> *FAILURE*
> 
> Serious unknown changes coming with Patchwork_21842_full absolutely 
> need to be verified manually.
> 
> If you think the reported changes have nothing to do with the changes 
> introduced in Patchwork_21842_full, please notify your bug team to 
> allow them to document this new failure mode, which will reduce false 
> positives in CI.
> 
> 
> Participating hosts (10 -> 10)
> 
> No changes in participating hosts
> 
> 
> Possible new issues
> 
> Here are the unknown changes that may have been introduced in
> Patchwork_21842_full:
> 
> 
>   IGT changes
> 
> 
> Possible regressions
> 
>   *
> 
> igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
> 
>   o
> 
> shard-iclb: NOTRUN -> SKIP
> 
>  igt@kms_psr2...@overlay-primary-update-sf-dmg-area.html>
> 
>   o
> 
> shard-tglb: NOTRUN -> SKIP
> 
>  igt@kms_psr2...@overlay-primary-update-sf-dmg-area.html>
> 
>   *
> 
> igt@perf@enable-disable:
> 
>   o shard-glk: PASS
> 
> 
> -> FAIL
> 
>  gt@p...@enable-disable.html>
> 
> 
> Suppressed
> 
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
> 
>   * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
>   o {shard-rkl}: NOTRUN -> SKIP
> 
>  igt@kms_psr2...@primary-plane-update-sf-dmg-area.html>
> 

These all look to be unrelated.

> 
> Known issues
> 
> Here are the changes found in Patchwork_21842_full that come from 
> known
> issues:
> 
> 
>   IGT changes
> 
> 
> Issues hit
> 
>   *
> 
> igt@gem_ctx_isolation@preservation-s3@rcs0:
> 
>   o shard-apl: PASS
> 
> 
> -> DMESG-WARN
> 
> 
> ([i915#180]) +2 similar issues
>   *
> 
> igt@gem_ctx_isolation@preservation-s3@vcs0:
> 
>   o shard-kbl: PASS
> 
> 
> -> DMESG-WARN
> 
> 
> ([i915#180]) +5 similar issues
>   *
> 
> igt@gem_exec_fair@basic-deadline:
> 
>   o shard-kbl: PASS
> 
> 
> -> FAIL
> 
> 
> ([i915#2846])
>   *
> 
> igt@gem_exec_fair@basic-none-share@rcs0:
> 
>   o shard-glk: PASS
> 
> 
> -> FAIL
> 
> 
> ([i915#2842])
>   *
> 
> igt@gem_exec_fair@basic-none-solo@rcs0:
> 
>   o shard-kbl: NOTRUN -> FAIL
> 
> 
> ([i915#2842])
>   *
> 
> igt@gem_exec_fair@basic-pace@vcs1:
> 
>   o shard-kbl: PASS
> 
> 
> -> FAIL
> 
> 
> ([i915#2842]) +1 similar issue
>   *
> 
>   

[Intel-gfx] [PATCH 3/7] drm/i915/guc: Remove racey GEM_BUG_ON

[Matthew Brost]

A full GT reset can race with the last context put resulting in the
context ref count being zero but the destroyed bit not yet being set.
Remove GEM_BUG_ON in scrub_guc_desc_for_outstanding_g2h that asserts the
destroyed bit must be set in ref count is zero.

Reviewed-by: Daniele Ceraolo Spurio 
Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0fb2eeff0262..36c2965db49b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1040,8 +1040,6 @@ static void scrub_guc_desc_for_outstanding_g2h(struct 
intel_guc *guc)
 
spin_unlock(>guc_state.lock);
 
-   GEM_BUG_ON(!do_put && !destroyed);
-
if (pending_enable || destroyed || deregister) {
decr_outstanding_submission_g2h(guc);
if (deregister)
-- 
2.33.1

[Intel-gfx] [PATCH 4/7] drm/i915/guc: Don't hog IRQs when destroying contexts

[Matthew Brost]

From: John Harrison 

While attempting to debug a CT deadlock issue in various CI failures
(most easily reproduced with gem_ctx_create/basic-files), I was seeing
CPU deadlock errors being reported. This were because the context
destroy loop was blocking waiting on H2G space from inside an IRQ
spinlock. There no was deadlock as such, it's just that the H2G queue
was full of context destroy commands and GuC was taking a long time to
process them. However, the kernel was seeing the large amount of time
spent inside the IRQ lock as a dead CPU. Various Bad Things(tm) would
then happen (heartbeat failures, CT deadlock errors, outstanding H2G
WARNs, etc.).

Re-working the loop to only acquire the spinlock around the list
management (which is all it is meant to protect) rather than the
entire destroy operation seems to fix all the above issues.

v2:
 (John Harrison)
  - Fix typo in comment message

Signed-off-by: John Harrison 
Signed-off-by: Matthew Brost 
Reviewed-by: Matthew Brost 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 45 ---
 1 file changed, 28 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 36c2965db49b..96fcf869e3ff 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2644,7 +2644,6 @@ static inline void guc_lrc_desc_unpin(struct 
intel_context *ce)
unsigned long flags;
bool disabled;
 
-   lockdep_assert_held(>submission_state.lock);
GEM_BUG_ON(!intel_gt_pm_is_awake(gt));
GEM_BUG_ON(!lrc_desc_registered(guc, ce->guc_id.id));
GEM_BUG_ON(ce != __get_context(guc, ce->guc_id.id));
@@ -2660,7 +2659,7 @@ static inline void guc_lrc_desc_unpin(struct 
intel_context *ce)
}
spin_unlock_irqrestore(>guc_state.lock, flags);
if (unlikely(disabled)) {
-   __release_guc_id(guc, ce);
+   release_guc_id(guc, ce);
__guc_context_destroy(ce);
return;
}
@@ -2694,36 +2693,48 @@ static void __guc_context_destroy(struct intel_context 
*ce)
 
 static void guc_flush_destroyed_contexts(struct intel_guc *guc)
 {
-   struct intel_context *ce, *cn;
+   struct intel_context *ce;
unsigned long flags;
 
GEM_BUG_ON(!submission_disabled(guc) &&
   guc_submission_initialized(guc));
 
-   spin_lock_irqsave(>submission_state.lock, flags);
-   list_for_each_entry_safe(ce, cn,
->submission_state.destroyed_contexts,
-destroyed_link) {
-   list_del_init(>destroyed_link);
-   __release_guc_id(guc, ce);
+   while (!list_empty(>submission_state.destroyed_contexts)) {
+   spin_lock_irqsave(>submission_state.lock, flags);
+   ce = 
list_first_entry_or_null(>submission_state.destroyed_contexts,
+ struct intel_context,
+ destroyed_link);
+   if (ce)
+   list_del_init(>destroyed_link);
+   spin_unlock_irqrestore(>submission_state.lock, flags);
+
+   if (!ce)
+   break;
+
+   release_guc_id(guc, ce);
__guc_context_destroy(ce);
}
-   spin_unlock_irqrestore(>submission_state.lock, flags);
 }
 
 static void deregister_destroyed_contexts(struct intel_guc *guc)
 {
-   struct intel_context *ce, *cn;
+   struct intel_context *ce;
unsigned long flags;
 
-   spin_lock_irqsave(>submission_state.lock, flags);
-   list_for_each_entry_safe(ce, cn,
->submission_state.destroyed_contexts,
-destroyed_link) {
-   list_del_init(>destroyed_link);
+   while (!list_empty(>submission_state.destroyed_contexts)) {
+   spin_lock_irqsave(>submission_state.lock, flags);
+   ce = 
list_first_entry_or_null(>submission_state.destroyed_contexts,
+ struct intel_context,
+ destroyed_link);
+   if (ce)
+   list_del_init(>destroyed_link);
+   spin_unlock_irqrestore(>submission_state.lock, flags);
+
+   if (!ce)
+   break;
+
guc_lrc_desc_unpin(ce);
}
-   spin_unlock_irqrestore(>submission_state.lock, flags);
 }
 
 static void destroyed_worker_func(struct work_struct *w)
-- 
2.33.1

[Intel-gfx] [PATCH 5/7] drm/i915/guc: Add extra debug on CT deadlock

[Matthew Brost]

Print CT state (H2G + G2H head / tail pointers, credits) on CT
deadlock.

v2:
 (John Harrison)
  - Add units to debug messages

Reviewed-by: John Harrison 
Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index a0cc34be7b56..741be9abab68 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -523,6 +523,15 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
CT_ERROR(ct, "Communication stalled for %lld ms, desc 
status=%#x,%#x\n",
 ktime_ms_delta(ktime_get(), ct->stall_time),
 send->status, recv->status);
+   CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
+atomic_read(>ctbs.send.space) * 4);
+   CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
+   CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
+   CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
+atomic_read(>ctbs.recv.space) * 4);
+   CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
+   CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
+
ct->ctbs.send.broken = true;
}
 
-- 
2.33.1

[Intel-gfx] [PATCH 2/7] drm/i915/guc: Only assign guc_id.id when stealing guc_id

[Matthew Brost]

Previously assigned whole guc_id structure (list, spin lock) which is
incorrect, only assign the guc_id.id.

Fixes: 0f7976506de61 ("drm/i915/guc: Rework and simplify locking")
Signed-off-by: Matthew Brost 
Reviewed-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 9b7b4f4e0d91..0fb2eeff0262 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1935,7 +1935,7 @@ static int steal_guc_id(struct intel_guc *guc, struct 
intel_context *ce)
GEM_BUG_ON(intel_context_is_parent(cn));
 
list_del_init(>guc_id.link);
-   ce->guc_id = cn->guc_id;
+   ce->guc_id.id = cn->guc_id.id;
 
spin_lock(>guc_state.lock);
clr_context_registered(cn);
-- 
2.33.1

[Intel-gfx] [PATCH 6/7] drm/i915/guc: Kick G2H tasklet if no credits

[Matthew Brost]

Let's be paranoid and kick the G2H tasklet, which dequeues messages, if
G2H credits are exhausted.

Signed-off-by: Matthew Brost 
Reviewed-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 741be9abab68..aa6dd6415202 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -591,12 +591,19 @@ static inline bool h2g_has_room(struct intel_guc_ct *ct, 
u32 len_dw)
 
 static int has_room_nb(struct intel_guc_ct *ct, u32 h2g_dw, u32 g2h_dw)
 {
+   bool h2g = h2g_has_room(ct, h2g_dw);
+   bool g2h = g2h_has_room(ct, g2h_dw);
+
lockdep_assert_held(>ctbs.send.lock);
 
-   if (unlikely(!h2g_has_room(ct, h2g_dw) || !g2h_has_room(ct, g2h_dw))) {
+   if (unlikely(!h2g || !g2h)) {
if (ct->stall_time == KTIME_MAX)
ct->stall_time = ktime_get();
 
+   /* Be paranoid and kick G2H tasklet to free credits */
+   if (!g2h)
+   tasklet_hi_schedule(>receive_tasklet);
+
if (unlikely(ct_deadlocked(ct)))
return -EPIPE;
else
-- 
2.33.1

[Intel-gfx] [PATCH 7/7] drm/i915/guc: Selftest for stealing of guc ids

[Matthew Brost]

Testing the stealing of guc ids is hard from user space as we have 64k
guc_ids. Add a selftest, which artificially reduces the number of guc
ids, and forces a steal.

The test creates a spinner which is used to block all subsequent
submissions until it completes. Next, a loop creates a context and a NOP
request each iteration until the guc_ids are exhausted (request creation
returns -EAGAIN). The spinner is ended, unblocking all requests created
in the loop. At this point all guc_ids are exhausted but are available
to steal. Try to create another request which should successfully steal
a guc_id. Wait on last request to complete, idle GPU, verify a guc_id
was stolen via a counter, and exit the test. Test also artificially
reduces the number of guc_ids so the test runs in a timely manner.

v2:
 (John Harrison)
  - s/stole/stolen
  - Fix some wording in test description
  - Rework indexing into context array
  - Add test description to commit message
  - Fix typo in commit message
 (Checkpatch)
  - s/guc/(guc) in NUMBER_MULTI_LRC_GUC_ID
v3:
 (John Harrison)
  - Set array value to NULL after extracting error
  - Fix a few typos in comments / error messages
  - Delete redundant comment in commit message

Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  12 ++
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  16 +-
 drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 173 ++
 3 files changed, 196 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 1cb46098030d..f9240d4baa69 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -94,6 +94,11 @@ struct intel_guc {
 * @guc_ids: used to allocate new guc_ids, single-lrc
 */
struct ida guc_ids;
+   /**
+* @num_guc_ids: Number of guc_ids, selftest feature to be able
+* to reduce this number while testing.
+*/
+   int num_guc_ids;
/**
 * @guc_ids_bitmap: used to allocate new guc_ids, multi-lrc
 */
@@ -202,6 +207,13 @@ struct intel_guc {
 */
struct delayed_work work;
} timestamp;
+
+#ifdef CONFIG_DRM_I915_SELFTEST
+   /**
+* @number_guc_id_stolen: The number of guc_ids that have been stolen
+*/
+   int number_guc_id_stolen;
+#endif
 };
 
 static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 96fcf869e3ff..99414b49ca6d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -145,7 +145,8 @@ guc_create_parallel(struct intel_engine_cs **engines,
  * use should be low and 1/16 should be sufficient. Minimum of 32 guc_ids for
  * multi-lrc.
  */
-#define NUMBER_MULTI_LRC_GUC_ID(GUC_MAX_LRC_DESCRIPTORS / 16)
+#define NUMBER_MULTI_LRC_GUC_ID(guc)   \
+   ((guc)->submission_state.num_guc_ids / 16)
 
 /*
  * Below is a set of functions which control the GuC scheduling state which
@@ -1775,7 +1776,7 @@ int intel_guc_submission_init(struct intel_guc *guc)
  destroyed_worker_func);
 
guc->submission_state.guc_ids_bitmap =
-   bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID, GFP_KERNEL);
+   bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
if (!guc->submission_state.guc_ids_bitmap)
return -ENOMEM;
 
@@ -1869,13 +1870,13 @@ static int new_guc_id(struct intel_guc *guc, struct 
intel_context *ce)
 
if (intel_context_is_parent(ce))
ret = 
bitmap_find_free_region(guc->submission_state.guc_ids_bitmap,
- NUMBER_MULTI_LRC_GUC_ID,
+ NUMBER_MULTI_LRC_GUC_ID(guc),
  
order_base_2(ce->parallel.number_children
   + 1));
else
ret = ida_simple_get(>submission_state.guc_ids,
-NUMBER_MULTI_LRC_GUC_ID,
-GUC_MAX_LRC_DESCRIPTORS,
+NUMBER_MULTI_LRC_GUC_ID(guc),
+guc->submission_state.num_guc_ids,
 GFP_KERNEL | __GFP_RETRY_MAYFAIL |
 __GFP_NOWARN);
if (unlikely(ret < 0))
@@ -1941,6 +1942,10 @@ static int steal_guc_id(struct intel_guc *guc, struct 
intel_context *ce)
 
set_context_guc_id_invalid(cn);
 
+#ifdef CONFIG_DRM_I915_SELFTEST
+   guc->number_guc_id_stolen++;
+#endif
+
return 0;
} else {
return 

[Intel-gfx] [PATCH 1/7] drm/i915/guc: Use correct context lock when callig clr_context_registered

[Matthew Brost]

s/ce/cn/ when grabbing guc_state.lock before calling
clr_context_registered.

Fixes: 0f7976506de61 ("drm/i915/guc: Rework and simplify locking")
Signed-off-by: Matthew Brost 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 1f9d4fde421f..9b7b4f4e0d91 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1937,9 +1937,9 @@ static int steal_guc_id(struct intel_guc *guc, struct 
intel_context *ce)
list_del_init(>guc_id.link);
ce->guc_id = cn->guc_id;
 
-   spin_lock(>guc_state.lock);
+   spin_lock(>guc_state.lock);
clr_context_registered(cn);
-   spin_unlock(>guc_state.lock);
+   spin_unlock(>guc_state.lock);
 
set_context_guc_id_invalid(cn);
 
-- 
2.33.1

[Intel-gfx] [PATCH 0/7] Fix stealing guc_ids + test

[Matthew Brost]

Patches 1 & 2 address bugs in stealing of guc_ids and patch 7 tests this
path.

Patches 4-6 address some issues with the CTs exposed by the selftest in
patch 7. Basically if a lot of contexts were all deregistered all at
once, the CT channel could deadlock.

Patch 3 is a small fix that is already review but just included for CI.

v2: Address comments, resend for CI
v3: Address comments in patch #7

Signed-off-by: Matthew Brost 

John Harrison (1):
  drm/i915/guc: Don't hog IRQs when destroying contexts

Matthew Brost (6):
  drm/i915/guc: Use correct context lock when callig
clr_context_registered
  drm/i915/guc: Only assign guc_id.id when stealing guc_id
  drm/i915/guc: Remove racey GEM_BUG_ON
  drm/i915/guc: Add extra debug on CT deadlock
  drm/i915/guc: Kick G2H tasklet if no credits
  drm/i915/guc: Selftest for stealing of guc ids

 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  12 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |  18 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  69 ---
 drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 173 ++
 4 files changed, 244 insertions(+), 28 deletions(-)

-- 
2.33.1

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/debugfs: add noreclaim annotations (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/debugfs: add noreclaim annotations (rev2)
URL   : https://patchwork.freedesktop.org/series/97966/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10996_full -> Patchwork_21842_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_21842_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl:  [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +2 similar 
issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10996/shard-apl4/igt@gem_ctx_isolation@preservation...@rcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-apl2/igt@gem_ctx_isolation@preservation...@rcs0.html

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl:  [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +5 similar 
issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10996/shard-kbl6/igt@gem_ctx_isolation@preservation...@vcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-kbl7/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-kbl:  [PASS][5] -> [FAIL][6] ([i915#2846])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10996/shard-kbl7/igt@gem_exec_f...@basic-deadline.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-kbl1/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk:  [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10996/shard-glk8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-glk3/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl:  NOTRUN -> [FAIL][9] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-kbl1/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl:  [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar 
issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10996/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-kbl3/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_lmem_swapping@parallel-multi:
- shard-tglb: NOTRUN -> [SKIP][12] ([i915#4613]) +2 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-tglb2/igt@gem_lmem_swapp...@parallel-multi.html

  * igt@gem_lmem_swapping@random:
- shard-apl:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-apl6/igt@gem_lmem_swapp...@random.html
- shard-kbl:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-kbl1/igt@gem_lmem_swapp...@random.html
- shard-skl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-skl1/igt@gem_lmem_swapp...@random.html

  * igt@gem_lmem_swapping@smem-oom:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#4613])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-iclb8/igt@gem_lmem_swapp...@smem-oom.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-skl:  NOTRUN -> [WARN][17] ([i915#2658])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-skl1/igt@gem_pwr...@basic-exhaustion.html
- shard-kbl:  NOTRUN -> [WARN][18] ([i915#2658])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-kbl1/igt@gem_pwr...@basic-exhaustion.html
- shard-apl:  NOTRUN -> [WARN][19] ([i915#2658])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-apl6/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_pxp@fail-invalid-protected-context:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#4270])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-iclb8/igt@gem_...@fail-invalid-protected-context.html

  * igt@gem_pxp@reject-modify-context-protection-on:
- shard-tglb: NOTRUN -> [SKIP][21] ([i915#4270])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/shard-tglb6/igt@gem_...@reject-modify-context-protection-on.html

  * igt@gem_userptr_blits@coherency-unsync:
- shard-tglb: NOTRUN -> [SKIP][22] ([i915#3297])
   [22]: 

Re: [Intel-gfx] [PATCH 7/7] drm/i915/guc: Selftest for stealing of guc ids

[Matthew Brost]

On Mon, Dec 13, 2021 at 04:26:07PM -0800, John Harrison wrote:
> On 12/11/2021 09:35, Matthew Brost wrote:
> > Testing the stealing of guc ids is hard from user space as we have 64k
> > guc_ids. Add a selftest, which artificially reduces the number of guc
> > ids, and forces a steal. Description of test below.
> Last sentence seems redundant.
> 

Will delete.

> > 
> > The test creates a spinner which is used to block all subsequent
> > submissions until it completes. Next, a loop creates a context and a NOP
> > request each iteration until the guc_ids are exhausted (request creation
> > returns -EAGAIN). The spinner is ended, unblocking all requests created
> > in the loop. At this point all guc_ids are exhausted but are available
> > to steal. Try to create another request which should successfully steal
> > a guc_id. Wait on last request to complete, idle GPU, verify a guc_id
> > was stolen via a counter, and exit the test. Test also artificially
> > reduces the number of guc_ids so the test runs in a timely manner.
> > 
> > v2:
> >   (John Harrison)
> >- s/stole/stolen
> >- Fix some wording in test description
> >- Rework indexing into context array
> >- Add test description to commit message
> >- Fix typo in commit message
> >   (Checkpatch)
> >- s/guc/(guc) in NUMBER_MULTI_LRC_GUC_ID
> > 
> > Signed-off-by: Matthew Brost 
> > ---
> >   drivers/gpu/drm/i915/gt/uc/intel_guc.h|  12 ++
> >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  16 +-
> >   drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 173 ++
> >   3 files changed, 196 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > index 1cb46098030d..f9240d4baa69 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > @@ -94,6 +94,11 @@ struct intel_guc {
> >  * @guc_ids: used to allocate new guc_ids, single-lrc
> >  */
> > struct ida guc_ids;
> > +   /**
> > +* @num_guc_ids: Number of guc_ids, selftest feature to be able
> > +* to reduce this number while testing.
> > +*/
> > +   int num_guc_ids;
> > /**
> >  * @guc_ids_bitmap: used to allocate new guc_ids, multi-lrc
> >  */
> > @@ -202,6 +207,13 @@ struct intel_guc {
> >  */
> > struct delayed_work work;
> > } timestamp;
> > +
> > +#ifdef CONFIG_DRM_I915_SELFTEST
> > +   /**
> > +* @number_guc_id_stolen: The number of guc_ids that have been stolen
> > +*/
> > +   int number_guc_id_stolen;
> > +#endif
> >   };
> >   static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 96fcf869e3ff..99414b49ca6d 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -145,7 +145,8 @@ guc_create_parallel(struct intel_engine_cs **engines,
> >* use should be low and 1/16 should be sufficient. Minimum of 32 guc_ids 
> > for
> >* multi-lrc.
> >*/
> > -#define NUMBER_MULTI_LRC_GUC_ID(GUC_MAX_LRC_DESCRIPTORS / 16)
> > +#define NUMBER_MULTI_LRC_GUC_ID(guc)   \
> > +   ((guc)->submission_state.num_guc_ids / 16)
> >   /*
> >* Below is a set of functions which control the GuC scheduling state 
> > which
> > @@ -1775,7 +1776,7 @@ int intel_guc_submission_init(struct intel_guc *guc)
> >   destroyed_worker_func);
> > guc->submission_state.guc_ids_bitmap =
> > -   bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID, GFP_KERNEL);
> > +   bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
> > if (!guc->submission_state.guc_ids_bitmap)
> > return -ENOMEM;
> > @@ -1869,13 +1870,13 @@ static int new_guc_id(struct intel_guc *guc, struct 
> > intel_context *ce)
> > if (intel_context_is_parent(ce))
> > ret = 
> > bitmap_find_free_region(guc->submission_state.guc_ids_bitmap,
> > - NUMBER_MULTI_LRC_GUC_ID,
> > + NUMBER_MULTI_LRC_GUC_ID(guc),
> >   
> > order_base_2(ce->parallel.number_children
> >+ 1));
> > else
> > ret = ida_simple_get(>submission_state.guc_ids,
> > -NUMBER_MULTI_LRC_GUC_ID,
> > -GUC_MAX_LRC_DESCRIPTORS,
> > +NUMBER_MULTI_LRC_GUC_ID(guc),
> > +guc->submission_state.num_guc_ids,
> >  GFP_KERNEL | __GFP_RETRY_MAYFAIL |
> >  __GFP_NOWARN);
> > if (unlikely(ret < 0))
> > @@ -1941,6 +1942,10 @@ 

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Disable tracing points on PREEMPT_RT

[Steven Rostedt]

On Tue, 14 Dec 2021 18:34:50 +0200
Ville Syrjälä  wrote:

> Looks lightly tedious. Can't we have "slow" (or whatever) versions of
> the trace macros so we could just declare these the same was as before
> without having to manually write that wrapper for every event?

That would be quite tedious as well ;-)

There's a couple of problems with doing it as a macro. One is that the data
would need to be saved on stack. There's no guarantee that there will be
enough stack available. We could probably add a way to limit the size. That
is, adding something like:

#define MAX_SLOW_TRACE_ENTRY_SIZE   256

BUILD_BUG_ON(sizeof(trace_event_raw_##call) > 
MAX_SLOW_TRACE_ENTRY_SIZE);

and then have the entry done outside the trace event. But even with that,
this is specific to the perf and ftrace code, and not to the trace point
that is called. We would need to figure out a way to make the macro work
for all the users.

It may be possible to do, but it will be far from trivial, and I'm not sure
I want this to be an easy option. Locks should not be taken from trace
events in general, as they are not tested with lockdep when the trace
points are not enabled, and could hide deadlocks that may not appear until
running on production.

-- Steve

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Disable tracing points on PREEMPT_RT

[Ville Syrjälä]

On Tue, Dec 14, 2021 at 09:36:52AM -0500, Steven Rostedt wrote:
> On Tue, 14 Dec 2021 15:03:00 +0100
> Sebastian Andrzej Siewior  wrote:
> 
> > Luca Abeni reported this:
> > | BUG: scheduling while atomic: kworker/u8:2/15203/0x0003
> > | CPU: 1 PID: 15203 Comm: kworker/u8:2 Not tainted 4.19.1-rt3 #10
> > | Call Trace:
> > |  rt_spin_lock+0x3f/0x50
> > |  gen6_read32+0x45/0x1d0 [i915]
> > |  g4x_get_vblank_counter+0x36/0x40 [i915]
> > |  trace_event_raw_event_i915_pipe_update_start+0x7d/0xf0 [i915]
> > 
> > The tracing events use trace_i915_pipe_update_start() among other events
> > use functions acquire spinlock_t locks which are transformed into
> > sleeping locks on PREEMPT_RT. A few trace points use
> > intel_get_crtc_scanline(), others use ->get_vblank_counter() wich also
> > might acquire a sleeping locks on PREEMPT_RT.
> > At the time the arguments are evaluated within trace point, preemption
> > is disabled and so the locks must not be acquired on PREEMPT_RT.
> > 
> > Based on this I don't see any other way than disable trace points on
> > PREMPT_RT.
> 
> Another way around this that I can see is if the data for the tracepoints
> can fit on the stack and add wrappers around the tracepoints. For example,
> looking at the first tracepoint in i915_trace.h:
> 
> TRACE_EVENT(intel_pipe_enable,
>   TP_PROTO(struct intel_crtc *crtc),
>   TP_ARGS(crtc),
> 
>   TP_STRUCT__entry(
>__array(u32, frame, 3)
>__array(u32, scanline, 3)
>__field(enum pipe, pipe)
>),
>   TP_fast_assign(
>  struct drm_i915_private *dev_priv = 
> to_i915(crtc->base.dev);
>  struct intel_crtc *it__;
>  for_each_intel_crtc(_priv->drm, it__) {
>  __entry->frame[it__->pipe] = 
> intel_crtc_get_vblank_counter(it__);
>  __entry->scanline[it__->pipe] = 
> intel_get_crtc_scanline(it__);
>  }
>  __entry->pipe = crtc->pipe;
>  ),
> 
>   TP_printk("pipe %c enable, pipe A: frame=%u, scanline=%u, pipe B: 
> frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
> pipe_name(__entry->pipe),
> __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
> __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
> __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
> );
> 
> We could modify this to be:
> 
> TRACE_EVENT(intel_pipe_enable,
>   TP_PROTO(u32 *frame, u32 *scanline, enum pipe),
>   TP_ARGS(frame, scanline, pipe),
> 
>   TP_STRUCT__entry(
>__array(u32, frame, 3)
>__array(u32, scanline, 3)
>__field(enum pipe, pipe)
>),
>   TP_fast_assign(
>  int i;
>  for (i = 0; i < 3; i++) {
> __entry->frame[i] = frame[i];
> __entry->scanline[i] = scanline[i];
>  }
>  __entry->pipe = pipe;
>  ),
> 
>   TP_printk("pipe %c enable, pipe A: frame=%u, scanline=%u, pipe B: 
> frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
> pipe_name(__entry->pipe),
> __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
> __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
> __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
> );
> 
> 
> static inline void do_trace_intel_pipe(struct intel_crtc *crtc)
> {
>   u32 frame[3];
>   u32 scanline[3];
>   enum pipe pipe;
> 
>   if (!trace_intel_pipe_enable_enabled())
>   return;
> 
>   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   struct intel_crtc *it__;
>   for_each_intel_crtc(_priv->drm, it__) {
>   frame[it__->pipe] = intel_crtc_get_vblank_counter(it__);
>   scanline[it__->pipe] = intel_get_crtc_scanline(it__);
>   }
> 
>   trace_intel_pipe(frame, scanline, crtc->pipe);
> }

Looks lightly tedious. Can't we have "slow" (or whatever) versions of
the trace macros so we could just declare these the same was as before
without having to manually write that wrapper for every event?

-- 
Ville Syrjälä
Intel

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Log engine resets

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Log engine resets
URL   : https://patchwork.freedesktop.org/series/98020/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11001 -> Patchwork_21846


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/index.html

Participating hosts (46 -> 35)
--

  Additional (1): fi-kbl-soraka 
  Missing(12): bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-icl-u2 fi-bsw-cyan 
bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus bat-jsl-2 bat-jsl-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_21846:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@hangcheck:
- {fi-jsl-1}: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11001/fi-jsl-1/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/fi-jsl-1/igt@i915_selftest@l...@hangcheck.html

  
Known issues


  Here are the changes found in Patchwork_21846 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271]) +2 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_exec_suspend@basic-s0:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][4] ([i915#4782])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-kefka:   [PASS][5] -> [INCOMPLETE][6] ([i915#2940])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11001/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
- fi-bsw-n3050:   [PASS][7] -> [INCOMPLETE][8] ([i915#2940])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11001/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][9] -> [INCOMPLETE][10] ([i915#3921])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11001/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u:   [PASS][11] -> [DMESG-WARN][12] ([i915#295]) +12 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11001/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html

  * igt@runner@aborted:
- fi-bsw-kefka:   NOTRUN -> [FAIL][13] ([fdo#109271] / [i915#1436] / 
[i915#3428] / [i915#4312])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/fi-bsw-kefka/igt@run...@aborted.html
- fi-bsw-n3050:   NOTRUN -> [FAIL][14] ([fdo#109271] / [i915#1436] / 
[i915#3428] / [i915#4312])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/fi-bsw-n3050/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_lrc:
- fi-rkl-11600:   [DMESG-FAIL][15] ([i915#2373]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11001/fi-rkl-11600/igt@i915_selftest@live@gt_lrc.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21846/fi-rkl-11600/igt@i915_selftest@live@gt_lrc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#3970]: https://gitlab.freedesktop.org/drm/intel/issues/3970
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4782]: https://gitlab.freedesktop.org/drm/intel/issues/4782


Build changes
-

  * Linux: CI_DRM_11001 -> Patchwork_21846

  CI-20190529: 

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915/cdclk: turn around i915_drv.h and intel_cdclk.h dependency (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/cdclk: turn around i915_drv.h 
and intel_cdclk.h dependency (rev3)
URL   : https://patchwork.freedesktop.org/series/97964/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11000_full -> Patchwork_21844_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_21844_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-skl:  NOTRUN -> [DMESG-WARN][1] ([i915#3002])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-skl10/igt@gem_cre...@create-massive.html

  * igt@gem_exec_capture@pi@vcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][2] ([i915#4547])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-skl10/igt@gem_exec_capture@p...@vcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl:  NOTRUN -> [FAIL][3] ([i915#2842])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-kbl7/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl:  [PASS][4] -> [FAIL][5] ([i915#2842])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11000/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs1.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_huc_copy@huc-copy:
- shard-skl:  NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-skl4/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-multi:
- shard-skl:  NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-skl6/igt@gem_lmem_swapp...@parallel-multi.html
- shard-tglb: NOTRUN -> [SKIP][8] ([i915#4613]) +1 similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-tglb3/igt@gem_lmem_swapp...@parallel-multi.html

  * igt@gem_lmem_swapping@random:
- shard-kbl:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-kbl7/igt@gem_lmem_swapp...@random.html

  * igt@gem_lmem_swapping@smem-oom:
- shard-iclb: NOTRUN -> [SKIP][10] ([i915#4613])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-iclb8/igt@gem_lmem_swapp...@smem-oom.html

  * igt@gem_pread@exhaustion:
- shard-skl:  NOTRUN -> [WARN][11] ([i915#2658])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-skl10/igt@gem_pr...@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-kbl:  NOTRUN -> [WARN][12] ([i915#2658])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-kbl7/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_pxp@fail-invalid-protected-context:
- shard-iclb: NOTRUN -> [SKIP][13] ([i915#4270])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-iclb8/igt@gem_...@fail-invalid-protected-context.html

  * igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-kbl:  NOTRUN -> [SKIP][14] ([fdo#109271]) +139 similar 
issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-kbl7/igt@gem_...@regular-baseline-src-copy-readible.html

  * igt@gen3_mixed_blits:
- shard-tglb: NOTRUN -> [SKIP][15] ([fdo#109289])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-tglb2/igt@gen3_mixed_blits.html

  * igt@gen9_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#2856])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-iclb8/igt@gen9_exec_pa...@batch-without-end.html

  * igt@gen9_exec_parse@batch-zero-length:
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#2856]) +1 similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-tglb2/igt@gen9_exec_pa...@batch-zero-length.html

  * igt@i915_pm_dc@dc9-dpms:
- shard-tglb: NOTRUN -> [SKIP][18] ([i915#4281])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-tglb7/igt@i915_pm...@dc9-dpms.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-skl:  NOTRUN -> [FAIL][19] ([i915#3743]) +2 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/shard-skl10/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-kbl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3777])
   [20]: 

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets

[Ville Syrjälä]

On Mon, Dec 13, 2021 at 09:54:04PM +0200, Jani Nikula wrote:
> On Mon, 13 Dec 2021, Ville Syrjala  wrote:
> > From: Ville Syrjälä 
> >
> > Parametrize ilk+ FBC register offsets based on the FBC instance.
> >
> > v2: More intel_ namespace (Jani)
> >
> > Cc: Jani Nikula 
> > Signed-off-by: Ville Syrjälä 
> 
> Some questions below, apart from that,
> 
> Reviewed-by: Jani Nikula 
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_fbc.c | 34 +---
> >  drivers/gpu/drm/i915/display/intel_fbc.h |  6 +
> >  drivers/gpu/drm/i915/i915_reg.h  | 34 
> >  drivers/gpu/drm/i915/intel_pm.c  | 31 -
> >  4 files changed, 60 insertions(+), 45 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 8be01b93015f..112aafa72253 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -85,6 +85,8 @@ struct intel_fbc {
> > struct drm_mm_node compressed_fb;
> > struct drm_mm_node compressed_llb;
> >  
> > +   enum intel_fbc_id id;
> > +
> > u8 limit;
> >  
> > bool false_color;
> > @@ -454,10 +456,10 @@ static void ilk_fbc_activate(struct intel_fbc *fbc)
> > struct intel_fbc_state *fbc_state = >state;
> > struct drm_i915_private *i915 = fbc->i915;
> >  
> > -   intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
> > +   intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
> >fbc_state->fence_y_offset);
> >  
> > -   intel_de_write(i915, ILK_DPFC_CONTROL,
> > +   intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
> >DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
> >  }
> >  
> > @@ -467,28 +469,28 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
> > u32 dpfc_ctl;
> >  
> > /* Disable compression */
> > -   dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL);
> > +   dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
> > if (dpfc_ctl & DPFC_CTL_EN) {
> > dpfc_ctl &= ~DPFC_CTL_EN;
> > -   intel_de_write(i915, ILK_DPFC_CONTROL, dpfc_ctl);
> > +   intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
> > }
> >  }
> >  
> >  static bool ilk_fbc_is_active(struct intel_fbc *fbc)
> >  {
> > -   return intel_de_read(fbc->i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
> > +   return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & 
> > DPFC_CTL_EN;
> >  }
> >  
> >  static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
> >  {
> > -   return intel_de_read(fbc->i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK;
> > +   return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & 
> > DPFC_COMP_SEG_MASK;
> >  }
> >  
> >  static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
> >  {
> > struct drm_i915_private *i915 = fbc->i915;
> >  
> > -   intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
> > +   intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), 
> > fbc->compressed_fb.start);
> >  }
> >  
> >  static const struct intel_fbc_funcs ilk_fbc_funcs = {
> > @@ -524,8 +526,8 @@ static void snb_fbc_nuke(struct intel_fbc *fbc)
> >  {
> > struct drm_i915_private *i915 = fbc->i915;
> >  
> > -   intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE);
> > -   intel_de_posting_read(i915, MSG_FBC_REND_STATE);
> > +   intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
> > +   intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
> >  }
> >  
> >  static const struct intel_fbc_funcs snb_fbc_funcs = {
> > @@ -547,7 +549,7 @@ static void glk_fbc_program_cfb_stride(struct intel_fbc 
> > *fbc)
> > val |= FBC_STRIDE_OVERRIDE |
> > FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
> >  
> > -   intel_de_write(i915, GLK_FBC_STRIDE, val);
> > +   intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
> >  }
> >  
> >  static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
> > @@ -598,19 +600,19 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
> > if (i915->ggtt.num_fences)
> > snb_fbc_program_fence(fbc);
> >  
> > -   intel_de_write(i915, ILK_DPFC_CONTROL,
> > +   intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
> >DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
> >  }
> >  
> >  static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
> >  {
> > -   return intel_de_read(fbc->i915, ILK_DPFC_STATUS2) & 
> > DPFC_COMP_SEG_MASK_IVB;
> > +   return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & 
> > DPFC_COMP_SEG_MASK_IVB;
> >  }
> >  
> >  static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
> > bool enable)
> >  {
> > -   intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL,
> > +   intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
> >  DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
> >  }
> >  
> > @@ -1620,7 +1622,8 @@ void intel_fbc_add_plane(struct intel_fbc *fbc, 
> > struct intel_plane 

Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: PREEMPT_RT related fixups. (rev4)

[Sebastian Andrzej Siewior]

On 2021-12-14 15:58:45 [-], Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: PREEMPT_RT related fixups. (rev4)
> URL   : https://patchwork.freedesktop.org/series/95463/
> State : failure
> 
> == Summary ==
> 
> Applying: drm/i915: Drop the irqs_disabled() check
> Applying: drm/i915/gt: Queue and wait for the irq_work item.
> Applying: drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() + 
> spin_lock()
> Applying: drm/i915: Use preempt_disable/enable_rt() where recommended
> Applying: drm/i915: Don't disable interrupts on PREEMPT_RT during atomic 
> updates
> Using index info to reconstruct a base tree...
> M drivers/gpu/drm/i915/display/intel_crtc.c
> Falling back to patching base and 3-way merge...
> Auto-merging drivers/gpu/drm/i915/display/intel_crtc.c
> CONFLICT (content): Merge conflict in 
> drivers/gpu/drm/i915/display/intel_crtc.c
> error: Failed to merge in the changes.
> hint: Use 'git am --show-current-patch=diff' to see the failed patch
> Patch failed at 0005 drm/i915: Don't disable interrupts on PREEMPT_RT during 
> atomic updates
> When you have resolved this problem, run "git am --continue".
> If you prefer to skip this patch, run "git am --skip" instead.
> To restore the original branch and stop patching, run "git am --abort".

I used the drm-intel-gt-next branch. Which one would be preferred?

Sebastian

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: PREEMPT_RT related fixups. (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: PREEMPT_RT related fixups. (rev4)
URL   : https://patchwork.freedesktop.org/series/95463/
State : failure

== Summary ==

Applying: drm/i915: Drop the irqs_disabled() check
Applying: drm/i915/gt: Queue and wait for the irq_work item.
Applying: drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() + 
spin_lock()
Applying: drm/i915: Use preempt_disable/enable_rt() where recommended
Applying: drm/i915: Don't disable interrupts on PREEMPT_RT during atomic updates
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/display/intel_crtc.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/intel_crtc.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_crtc.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0005 drm/i915: Don't disable interrupts on PREEMPT_RT during 
atomic updates
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Disable tracing points on PREEMPT_RT

[Sebastian Andrzej Siewior]

On 2021-12-14 09:36:52 [-0500], Steven Rostedt wrote:
> Another way around this that I can see is if the data for the tracepoints
> can fit on the stack and add wrappers around the tracepoints. For example,
> looking at the first tracepoint in i915_trace.h:
…

Nice.

> We could modify this to be:
…
> static inline void do_trace_intel_pipe(struct intel_crtc *crtc)
> {
>   u32 frame[3];
>   u32 scanline[3];
>   enum pipe pipe;
> 
>   if (!trace_intel_pipe_enable_enabled())
>   return;
> 
>   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   struct intel_crtc *it__;
>   for_each_intel_crtc(_priv->drm, it__) {
>   frame[it__->pipe] = intel_crtc_get_vblank_counter(it__);
>   scanline[it__->pipe] = intel_get_crtc_scanline(it__);
>   }
> 
>   trace_intel_pipe(frame, scanline, crtc->pipe);
> }
…

> Then have the code call do_trace_intel_pipe() instead of trace_intel_pipe()
> and this should fix the issue with preempt rt.

Is this is something, that the i915 devs would accept?

> -- Steve

Sebastian

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Disable tracing points on PREEMPT_RT

[Jani Nikula]

On Tue, 14 Dec 2021, Steven Rostedt  wrote:
> On Tue, 14 Dec 2021 15:03:00 +0100
> Sebastian Andrzej Siewior  wrote:
>
>> Luca Abeni reported this:
>> | BUG: scheduling while atomic: kworker/u8:2/15203/0x0003
>> | CPU: 1 PID: 15203 Comm: kworker/u8:2 Not tainted 4.19.1-rt3 #10
>> | Call Trace:
>> |  rt_spin_lock+0x3f/0x50
>> |  gen6_read32+0x45/0x1d0 [i915]
>> |  g4x_get_vblank_counter+0x36/0x40 [i915]
>> |  trace_event_raw_event_i915_pipe_update_start+0x7d/0xf0 [i915]
>> 
>> The tracing events use trace_i915_pipe_update_start() among other events
>> use functions acquire spinlock_t locks which are transformed into
>> sleeping locks on PREEMPT_RT. A few trace points use
>> intel_get_crtc_scanline(), others use ->get_vblank_counter() wich also
>> might acquire a sleeping locks on PREEMPT_RT.
>> At the time the arguments are evaluated within trace point, preemption
>> is disabled and so the locks must not be acquired on PREEMPT_RT.
>> 
>> Based on this I don't see any other way than disable trace points on
>> PREMPT_RT.
>
> Another way around this that I can see is if the data for the tracepoints
> can fit on the stack and add wrappers around the tracepoints. For example,
> looking at the first tracepoint in i915_trace.h:

FYI display portions of the file have been split to
display/intel_display_trace.[ch] in current drm-intel-next, headed for
v5.17 merge window.

BR,
Jani.


>
> TRACE_EVENT(intel_pipe_enable,
>   TP_PROTO(struct intel_crtc *crtc),
>   TP_ARGS(crtc),
>
>   TP_STRUCT__entry(
>__array(u32, frame, 3)
>__array(u32, scanline, 3)
>__field(enum pipe, pipe)
>),
>   TP_fast_assign(
>  struct drm_i915_private *dev_priv = 
> to_i915(crtc->base.dev);
>  struct intel_crtc *it__;
>  for_each_intel_crtc(_priv->drm, it__) {
>  __entry->frame[it__->pipe] = 
> intel_crtc_get_vblank_counter(it__);
>  __entry->scanline[it__->pipe] = 
> intel_get_crtc_scanline(it__);
>  }
>  __entry->pipe = crtc->pipe;
>  ),
>
>   TP_printk("pipe %c enable, pipe A: frame=%u, scanline=%u, pipe B: 
> frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
> pipe_name(__entry->pipe),
> __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
> __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
> __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
> );
>
> We could modify this to be:
>
> TRACE_EVENT(intel_pipe_enable,
>   TP_PROTO(u32 *frame, u32 *scanline, enum pipe),
>   TP_ARGS(frame, scanline, pipe),
>
>   TP_STRUCT__entry(
>__array(u32, frame, 3)
>__array(u32, scanline, 3)
>__field(enum pipe, pipe)
>),
>   TP_fast_assign(
>  int i;
>  for (i = 0; i < 3; i++) {
> __entry->frame[i] = frame[i];
> __entry->scanline[i] = scanline[i];
>  }
>  __entry->pipe = pipe;
>  ),
>
>   TP_printk("pipe %c enable, pipe A: frame=%u, scanline=%u, pipe B: 
> frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
> pipe_name(__entry->pipe),
> __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
> __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
> __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
> );
>
>
> static inline void do_trace_intel_pipe(struct intel_crtc *crtc)
> {
>   u32 frame[3];
>   u32 scanline[3];
>   enum pipe pipe;
>
>   if (!trace_intel_pipe_enable_enabled())
>   return;
>
>   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   struct intel_crtc *it__;
>   for_each_intel_crtc(_priv->drm, it__) {
>   frame[it__->pipe] = intel_crtc_get_vblank_counter(it__);
>   scanline[it__->pipe] = intel_get_crtc_scanline(it__);
>   }
>
>   trace_intel_pipe(frame, scanline, crtc->pipe);
> }
>
>
> The trace_intel_pipe_enable_enabled() is a static_branch that will act the
> same as the nop of a trace event, so this will still not add overhead when
> not enabled.
>
> All the processing will be done outside the trace event allowing it to be
> preempted, and then when the trace event is executed, it will run quickly
> without taking any locks.
>
> Then have the code call do_trace_intel_pipe() instead of trace_intel_pipe()
> and this should fix the issue with preempt rt.
>
> -- Steve

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH] drm/i915/gt: Do not add same i915_request to intel_context twice

[Tvrtko Ursulin]

On 14/12/2021 05:58, Yang, Dong wrote:

Thanks Tvrtko, I will try the patch you mentioned.

BTW, how do you think we use this patch in our project, any side-effect it may 
have?  If no side-effect we can take it as WA for temporally fix till we got 
the final root fixed.


For side effects I can't be sure. Best to try backporting and see if it 
fixes your issue, but note backporting may be tricky and you may end up 
pulling other patches as well.


Regards,

Tvrtko

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 01/11] tests/i915/i915_hangman: Add descriptions

[John Harrison]

On 12/14/2021 01:47, Petri Latvala wrote:

On Mon, Dec 13, 2021 at 03:29:04PM -0800, john.c.harri...@intel.com wrote:

From: John Harrison 

Added descriptions of the various sub-tests and the test as a whole.

Signed-off-by: John Harrison 
---
  tests/i915/i915_hangman.c | 11 +--
  1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 4c18c22db..025bb8713 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -46,6 +46,8 @@
  static int device = -1;
  static int sysfs = -1;
  
+IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");

+
  static bool has_error_state(int dir)
  {
bool result;
@@ -315,9 +317,9 @@ static void hangcheck_unterminated(void)
  
  	gem_execbuf(device, );

if (gem_wait(device, handle, _ns) != 0) {
-   /* need to manually trigger an hang to clean before failing */
+   /* need to manually trigger a hang to clean before failing */
igt_force_gpu_reset(device);
-   igt_assert_f(0, "unterminated batch did not trigger an hang!");
+   igt_assert_f(0, "unterminated batch did not trigger a hang!");

Ouch, this is a bug that could use a drive-by fix in this same commit:
Add a newline after that text.

With that,
Reviewed-by: Petri Latvala 

Well spotted. Will add that in.

Thanks,
John.




}
  }
  
@@ -341,9 +343,11 @@ igt_main

igt_require(has_error_state(sysfs));
}
  
+	igt_describe("Basic error capture");

igt_subtest("error-state-basic")
test_error_state_basic();
  
+	igt_describe("Per engine error capture");

igt_subtest_with_dynamic("error-state-capture") {
for_each_ctx_engine(device, ctx, e) {
igt_dynamic_f("%s", e->name)
@@ -351,6 +355,7 @@ igt_main
}
}
  
+	igt_describe("Per engine hang recovery (spin)");

igt_subtest_with_dynamic("engine-hang") {
  int has_gpu_reset = 0;
struct drm_i915_getparam gp = {
@@ -369,6 +374,7 @@ igt_main
}
}
  
+	igt_describe("Per engine hang recovery (invalid CS)");

igt_subtest_with_dynamic("engine-error") {
int has_gpu_reset = 0;
struct drm_i915_getparam gp = {
@@ -386,6 +392,7 @@ igt_main
}
}
  
+	igt_describe("Check that executing unintialised memory causes a hang");

igt_subtest("hangcheck-unterminated")
hangcheck_unterminated();
  
--

2.25.1

[Intel-gfx] [PULL] drm-intel-next

[Jani Nikula]

Hi Dave & Daniel -

drm-intel-next-2021-12-14:
drm/i915 feature pull #2 for v5.17:

Features and functionality:
- Add eDP privacy screen support (Hans)
- Add Raptor Lake S (RPL-S) support (Anusha)
- Add CD clock squashing support (Mika)
- Properly support ADL-P without force probe (Clint)
- Enable pipe color support (10 bit gamma) for display 13 platforms (Uma)
- Update ADL-P DMC firmware to v2.14 (Madhumitha)

Refactoring and cleanups:
- More FBC refactoring preparing for multiple FBC instances (Ville)
- Plane register cleanups (Ville)
- Header refactoring and include cleanups (Jani)
- Crtc helper and vblank wait function cleanups (Jani, Ville)
- Move pipe/transcoder/abox masks under intel_device_info.display (Ville)

Fixes:
- Add a delay to let eDP source OUI write take effect (Lyude)
- Use div32 version of MPLLB word clock for UHBR on SNPS PHY (Jani)
- Fix DMC firmware loader overflow check (Harshit Mogalapalli)
- Fully disable FBC on FIFO underruns (Ville)
- Disable FBC with double wide pipe as mutually exclusive (Ville)
- DG2 workarounds (Matt)
- Non-x86 build fixes (Siva)
- Fix HDR plane max width for NV12 (Vidya)
- Disable IRQ for selftest timestamp calculation (Anshuman)
- ADL-P VBT DDC pin mapping fix (Tejas)

Merges:
- Backmerge drm-next for privacy screen plumbing (Jani)

BR,
Jani.

The following changes since commit c8a04cbeedbc9f71c475141baa656f14f4879792:

  Merge tag 'drm-misc-next-2021-11-29' of 
git://anongit.freedesktop.org/drm/drm-misc into drm-next (2021-12-09 09:31:45 
+0100)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2021-12-14

for you to fetch changes up to 96db14432d979532be4cb6d5d52a127317e68b3f:

  drm/i915: Fix implicit use of struct pci_dev (2021-12-14 10:38:29 +0200)


drm/i915 feature pull #2 for v5.17:

Features and functionality:
- Add eDP privacy screen support (Hans)
- Add Raptor Lake S (RPL-S) support (Anusha)
- Add CD clock squashing support (Mika)
- Properly support ADL-P without force probe (Clint)
- Enable pipe color support (10 bit gamma) for display 13 platforms (Uma)
- Update ADL-P DMC firmware to v2.14 (Madhumitha)

Refactoring and cleanups:
- More FBC refactoring preparing for multiple FBC instances (Ville)
- Plane register cleanups (Ville)
- Header refactoring and include cleanups (Jani)
- Crtc helper and vblank wait function cleanups (Jani, Ville)
- Move pipe/transcoder/abox masks under intel_device_info.display (Ville)

Fixes:
- Add a delay to let eDP source OUI write take effect (Lyude)
- Use div32 version of MPLLB word clock for UHBR on SNPS PHY (Jani)
- Fix DMC firmware loader overflow check (Harshit Mogalapalli)
- Fully disable FBC on FIFO underruns (Ville)
- Disable FBC with double wide pipe as mutually exclusive (Ville)
- DG2 workarounds (Matt)
- Non-x86 build fixes (Siva)
- Fix HDR plane max width for NV12 (Vidya)
- Disable IRQ for selftest timestamp calculation (Anshuman)
- ADL-P VBT DDC pin mapping fix (Tejas)

Merges:
- Backmerge drm-next for privacy screen plumbing (Jani)


Anshuman Gupta (1):
  drm/i915/selftest: Disable IRQ for timestamp calculation

Anusha Srivatsa (3):
  drm/i915/rpl-s: Add PCI IDS for Raptor Lake S
  drm/i915/rpl-s: Add PCH Support for Raptor Lake S
  drm/i915/rpl-s: Enable guc submission by default

Clint Taylor (1):
  drm/i915/adlp: Remove require_force_probe protection

Hans de Goede (2):
  drm/i915: Add intel_modeset_probe_defer() helper
  drm/i915: Add privacy-screen support (v3)

Harshit Mogalapalli (1):
  drm/i915/display: Fix an unsigned subtraction which can never be negative.

Jani Nikula (24):
  drm/i915/display: add intel_crtc_wait_for_next_vblank() and use it
  drm/i915/crtc: rename intel_get_crtc_for_pipe() to intel_crtc_for_pipe()
  drm/i915/crtc: rename intel_get_crtc_for_plane() to intel_crtc_for_plane()
  drm/i915/display: remove intel_wait_for_vblank()
  drm/i915/crtc: un-inline some crtc functions and move to intel_crtc.[ch]
  drm/i915/fb: move intel_fb_uses_dpt to intel_fb.c and un-inline
  drm/i915: split out intel_pm_types.h
  drm/i915: move enum hpd_pin to intel_display.h
  drm/i915/display: convert dp_to_i915() to a macro
  drm/i915/display: stop including i915_drv.h from intel_display_types.h
  drm/i915/snps: use div32 version of MPLLB word clock for UHBR
  drm/i915/ddi: add use_edp_hobl() and use_edp_low_vswing() helpers
  drm/i915/trace: clean up boilerplate organization
  drm/i915/trace: split out display trace to a separate file
  Merge drm/drm-next into drm-intel-next
  drm/i915/reset: include intel_display.h instead of intel_display_types.h
  drm/i915/active: remove useless i915_utils.h include
  drm/i915/psr: avoid intel_frontbuffer.h include with declaration
  drm/i915/fbc: avoid 

[Intel-gfx] [PATCH] drm/i915/guc: Log engine resets

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Log engine resets done by the GuC firmware in the similar way it is done
by the execlists backend.

This way we have notion of where the hangs are before the GuC gains
support for proper error capture.

Signed-off-by: Tvrtko Ursulin 
Cc: Matthew Brost 
Cc: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 9739da6f..51512123dc1a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -11,6 +11,7 @@
 #include "gt/intel_context.h"
 #include "gt/intel_engine_pm.h"
 #include "gt/intel_engine_heartbeat.h"
+#include "gt/intel_engine_user.h"
 #include "gt/intel_gpu_commands.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_clock_utils.h"
@@ -3934,9 +3935,18 @@ static void capture_error_state(struct intel_guc *guc,
 {
struct intel_gt *gt = guc_to_gt(guc);
struct drm_i915_private *i915 = gt->i915;
-   struct intel_engine_cs *engine = __context_to_physical_engine(ce);
+   struct intel_engine_cs *engine = ce->engine;
intel_wakeref_t wakeref;
 
+   if (intel_engine_is_virtual(engine)) {
+   drm_notice(>drm, "%s class, engines 0x%x; GuC engine 
reset\n",
+  intel_engine_class_repr(engine->class),
+  engine->mask);
+   engine = guc_virtual_get_sibling(engine, 0);
+   } else {
+   drm_notice(>drm, "%s GuC engine reset\n", engine->name);
+   }
+
intel_engine_set_hung_context(engine, ce);
with_intel_runtime_pm(>runtime_pm, wakeref)
i915_capture_error_state(gt, engine->mask);
-- 
2.32.0

Re: [Intel-gfx] [PATCH] drm/i915/ttm: fix large buffer population trucation

[Matthew Auld]

On Mon, 13 Dec 2021 at 13:03, Matthew Auld  wrote:
>
> On 10/12/2021 19:50, Robert Beckett wrote:
> > ttm->num_pages is uint32_t which was causing very large buffers to
> > only populate a truncated size.
> >
> > This fixes gem_create@create-clear igt test on large memory systems.
> >
> > Fixes: 7ae034590cea ("drm/i915/ttm: add tt shmem backend")
> > Signed-off-by: Robert Beckett 
>
> Nice catch,
> Reviewed-by: Matthew Auld 

Pushed to drm-intel-gt-next. Thanks again for the fix.

>
> > ---
> >   drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
> > b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> > index 218a9b3037c7..923cc7ad8d70 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> > @@ -166,7 +166,7 @@ static int i915_ttm_tt_shmem_populate(struct ttm_device 
> > *bdev,
> >   struct intel_memory_region *mr = 
> > i915->mm.regions[INTEL_MEMORY_SYSTEM];
> >   struct i915_ttm_tt *i915_tt = container_of(ttm, typeof(*i915_tt), 
> > ttm);
> >   const unsigned int max_segment = i915_sg_segment_size();
> > - const size_t size = ttm->num_pages << PAGE_SHIFT;
> > + const size_t size = (size_t)ttm->num_pages << PAGE_SHIFT;
> >   struct file *filp = i915_tt->filp;
> >   struct sgt_iter sgt_iter;
> >   struct sg_table *st;
> >

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Disable tracing points on PREEMPT_RT

[Steven Rostedt]

On Tue, 14 Dec 2021 15:03:00 +0100
Sebastian Andrzej Siewior  wrote:

> Luca Abeni reported this:
> | BUG: scheduling while atomic: kworker/u8:2/15203/0x0003
> | CPU: 1 PID: 15203 Comm: kworker/u8:2 Not tainted 4.19.1-rt3 #10
> | Call Trace:
> |  rt_spin_lock+0x3f/0x50
> |  gen6_read32+0x45/0x1d0 [i915]
> |  g4x_get_vblank_counter+0x36/0x40 [i915]
> |  trace_event_raw_event_i915_pipe_update_start+0x7d/0xf0 [i915]
> 
> The tracing events use trace_i915_pipe_update_start() among other events
> use functions acquire spinlock_t locks which are transformed into
> sleeping locks on PREEMPT_RT. A few trace points use
> intel_get_crtc_scanline(), others use ->get_vblank_counter() wich also
> might acquire a sleeping locks on PREEMPT_RT.
> At the time the arguments are evaluated within trace point, preemption
> is disabled and so the locks must not be acquired on PREEMPT_RT.
> 
> Based on this I don't see any other way than disable trace points on
> PREMPT_RT.

Another way around this that I can see is if the data for the tracepoints
can fit on the stack and add wrappers around the tracepoints. For example,
looking at the first tracepoint in i915_trace.h:

TRACE_EVENT(intel_pipe_enable,
TP_PROTO(struct intel_crtc *crtc),
TP_ARGS(crtc),

TP_STRUCT__entry(
 __array(u32, frame, 3)
 __array(u32, scanline, 3)
 __field(enum pipe, pipe)
 ),
TP_fast_assign(
   struct drm_i915_private *dev_priv = 
to_i915(crtc->base.dev);
   struct intel_crtc *it__;
   for_each_intel_crtc(_priv->drm, it__) {
   __entry->frame[it__->pipe] = 
intel_crtc_get_vblank_counter(it__);
   __entry->scanline[it__->pipe] = 
intel_get_crtc_scanline(it__);
   }
   __entry->pipe = crtc->pipe;
   ),

TP_printk("pipe %c enable, pipe A: frame=%u, scanline=%u, pipe B: 
frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
  pipe_name(__entry->pipe),
  __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
  __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
  __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
);

We could modify this to be:

TRACE_EVENT(intel_pipe_enable,
TP_PROTO(u32 *frame, u32 *scanline, enum pipe),
TP_ARGS(frame, scanline, pipe),

TP_STRUCT__entry(
 __array(u32, frame, 3)
 __array(u32, scanline, 3)
 __field(enum pipe, pipe)
 ),
TP_fast_assign(
   int i;
   for (i = 0; i < 3; i++) {
  __entry->frame[i] = frame[i];
  __entry->scanline[i] = scanline[i];
   }
   __entry->pipe = pipe;
   ),

TP_printk("pipe %c enable, pipe A: frame=%u, scanline=%u, pipe B: 
frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
  pipe_name(__entry->pipe),
  __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
  __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
  __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
);


static inline void do_trace_intel_pipe(struct intel_crtc *crtc)
{
u32 frame[3];
u32 scanline[3];
enum pipe pipe;

if (!trace_intel_pipe_enable_enabled())
return;

struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc *it__;
for_each_intel_crtc(_priv->drm, it__) {
frame[it__->pipe] = intel_crtc_get_vblank_counter(it__);
scanline[it__->pipe] = intel_get_crtc_scanline(it__);
}

trace_intel_pipe(frame, scanline, crtc->pipe);
}


The trace_intel_pipe_enable_enabled() is a static_branch that will act the
same as the nop of a trace event, so this will still not add overhead when
not enabled.

All the processing will be done outside the trace event allowing it to be
preempted, and then when the trace event is executed, it will run quickly
without taking any locks.

Then have the code call do_trace_intel_pipe() instead of trace_intel_pipe()
and this should fix the issue with preempt rt.

-- Steve

[Intel-gfx] [PATCH 5/8] drm/i915: Don't disable interrupts on PREEMPT_RT during atomic updates

[Sebastian Andrzej Siewior]

From: Mike Galbraith 

Commit
   8d7849db3eab7 ("drm/i915: Make sprite updates atomic")

started disabling interrupts across atomic updates. This breaks on PREEMPT_RT
because within this section the code attempt to acquire spinlock_t locks which
are sleeping locks on PREEMPT_RT.

According to the comment the interrupts are disabled to avoid random delays and
not required for protection or synchronisation.
If this needs to happen with disabled interrupts on PREEMPT_RT, and the
whole section is restricted to register access then all sleeping locks
need to be acquired before interrupts are disabled and some function
maybe moved after enabling interrupts again.
This includes:
- prepare_to_wait() + finish_wait() due its wake queue.
- drm_crtc_vblank_put() -> vblank_disable_fn() drm_device::vbl_lock.
- skl_pfit_enable(), intel_update_plane(), vlv_atomic_update_fifo() and
  maybe others due to intel_uncore::lock
- drm_crtc_arm_vblank_event() due to drm_device::event_lock and
  drm_device::vblank_time_lock.

Don't disable interrupts on PREEMPT_RT during atomic updates.

[bigeasy: drop local locks, commit message]

Signed-off-by: Mike Galbraith 
Signed-off-by: Sebastian Andrzej Siewior 
---
 drivers/gpu/drm/i915/display/intel_crtc.c | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c 
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 254e67141a776..7a39029b083f4 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -425,7 +425,8 @@ void intel_pipe_update_start(const struct intel_crtc_state 
*new_crtc_state)
 */
intel_psr_wait_for_idle(new_crtc_state);
 
-   local_irq_disable();
+   if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+   local_irq_disable();
 
crtc->debug.min_vbl = min;
crtc->debug.max_vbl = max;
@@ -450,11 +451,13 @@ void intel_pipe_update_start(const struct 
intel_crtc_state *new_crtc_state)
break;
}
 
-   local_irq_enable();
+   if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+   local_irq_enable();
 
timeout = schedule_timeout(timeout);
 
-   local_irq_disable();
+   if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+   local_irq_disable();
}
 
finish_wait(wq, );
@@ -487,7 +490,8 @@ void intel_pipe_update_start(const struct intel_crtc_state 
*new_crtc_state)
return;
 
 irq_disable:
-   local_irq_disable();
+   if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+   local_irq_disable();
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
@@ -566,7 +570,8 @@ void intel_pipe_update_end(struct intel_crtc_state 
*new_crtc_state)
new_crtc_state->uapi.event = NULL;
}
 
-   local_irq_enable();
+   if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+   local_irq_enable();
 
/* Send VRR Push to terminate Vblank */
intel_vrr_send_push(new_crtc_state);
-- 
2.34.1

[Intel-gfx] [PATCH 6/8] drm/i915: Don't check for atomic context on PREEMPT_RT

[Sebastian Andrzej Siewior]

The !in_atomic() check in _wait_for_atomic() triggers on PREEMPT_RT
because the uncore::lock is a spinlock_t and does not disable
preemption or interrupts.

Changing the uncore:lock to a raw_spinlock_t doubles the worst case
latency on an otherwise idle testbox during testing. Therefore I'm
currently unsure about changing this.

Link: https://lore.kernel.org/all/20211006164628.s2mtsdd2jdbfy...@linutronix.de/
Signed-off-by: Sebastian Andrzej Siewior 
---
 drivers/gpu/drm/i915/i915_utils.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_utils.h 
b/drivers/gpu/drm/i915/i915_utils.h
index 7a5925072466a..b7b56fb1e2fc7 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -344,7 +344,7 @@ wait_remaining_ms_from_jiffies(unsigned long 
timestamp_jiffies, int to_wait_ms)
 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
 
 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
-#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
+#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT) && 
!defined(CONFIG_PREEMPT_RT)
 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
 #else
 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
-- 
2.34.1

[Intel-gfx] [PATCH 8/8] drm/i915: skip DRM_I915_LOW_LEVEL_TRACEPOINTS with NOTRACE

[Sebastian Andrzej Siewior]

The order of the header files is important. If this header file is
included after tracepoint.h was included then the NOTRACE here becomes a
nop. Currently this happens for two .c files which use the tracepoitns
behind DRM_I915_LOW_LEVEL_TRACEPOINTS.

Cc: Steven Rostedt 
Signed-off-by: Sebastian Andrzej Siewior 
Signed-off-by: Thomas Gleixner 
---
 drivers/gpu/drm/i915/i915_trace.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_trace.h 
b/drivers/gpu/drm/i915/i915_trace.h
index 64c3fa7cc05df..89a4089bc4baf 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -823,7 +823,7 @@ DEFINE_EVENT(i915_request, i915_request_add,
 TP_ARGS(rq)
 );
 
-#if defined(CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS)
+#if defined(CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS) && !defined(NOTRACE)
 DEFINE_EVENT(i915_request, i915_request_guc_submit,
 TP_PROTO(struct i915_request *rq),
 TP_ARGS(rq)
-- 
2.34.1

[Intel-gfx] [PATCH 2/8] drm/i915/gt: Queue and wait for the irq_work item.

[Sebastian Andrzej Siewior]

Disabling interrupts and invoking the irq_work function directly breaks
on PREEMPT_RT.
PREEMPT_RT does not invoke all irq_work from hardirq context because
some of the user have spinlock_t locking in the callback function.
These locks are then turned into a sleeping locks which can not be
acquired with disabled interrupts.

Using irq_work_queue() has the benefit that the irqwork will be invoked
in the regular context. In general there is "no" delay between enqueuing
the callback and its invocation because the interrupt is raised right
away on architectures which support it (which includes x86).

Use irq_work_queue() + irq_work_sync() instead invoking the callback
directly.

Reported-by: Clark Williams 
Signed-off-by: Sebastian Andrzej Siewior 
Reviewed-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index 209cf265bf746..6e1b9068d944c 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -311,10 +311,9 @@ void __intel_breadcrumbs_park(struct intel_breadcrumbs *b)
/* Kick the work once more to drain the signalers, and disarm the irq */
irq_work_sync(>irq_work);
while (READ_ONCE(b->irq_armed) && !atomic_read(>active)) {
-   local_irq_disable();
-   signal_irq_work(>irq_work);
-   local_irq_enable();
+   irq_work_queue(>irq_work);
cond_resched();
+   irq_work_sync(>irq_work);
}
 }
 
-- 
2.34.1

[Intel-gfx] [PATCH 7/8] drm/i915: Disable tracing points on PREEMPT_RT

[Sebastian Andrzej Siewior]

Luca Abeni reported this:
| BUG: scheduling while atomic: kworker/u8:2/15203/0x0003
| CPU: 1 PID: 15203 Comm: kworker/u8:2 Not tainted 4.19.1-rt3 #10
| Call Trace:
|  rt_spin_lock+0x3f/0x50
|  gen6_read32+0x45/0x1d0 [i915]
|  g4x_get_vblank_counter+0x36/0x40 [i915]
|  trace_event_raw_event_i915_pipe_update_start+0x7d/0xf0 [i915]

The tracing events use trace_i915_pipe_update_start() among other events
use functions acquire spinlock_t locks which are transformed into
sleeping locks on PREEMPT_RT. A few trace points use
intel_get_crtc_scanline(), others use ->get_vblank_counter() wich also
might acquire a sleeping locks on PREEMPT_RT.
At the time the arguments are evaluated within trace point, preemption
is disabled and so the locks must not be acquired on PREEMPT_RT.

Based on this I don't see any other way than disable trace points on
PREMPT_RT.

Reported-by: Luca Abeni 
Cc: Steven Rostedt 
Signed-off-by: Sebastian Andrzej Siewior 
---
 drivers/gpu/drm/i915/i915_trace.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_trace.h 
b/drivers/gpu/drm/i915/i915_trace.h
index 8104981a66044..64c3fa7cc05df 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -2,6 +2,10 @@
 #if !defined(_I915_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
 #define _I915_TRACE_H_
 
+#ifdef CONFIG_PREEMPT_RT
+#define NOTRACE
+#endif
+
 #include 
 #include 
 #include 
-- 
2.34.1

[Intel-gfx] [PATCH 0/8] drm/i915: PREEMPT_RT related fixups.

[Sebastian Andrzej Siewior]

Hi,

The following patches are from the PREEMPT_RT queue. One patch was
applied, one added so here are eight again. I can post them in smaller
batches if that is preferred.
It is mostly about disabling interrupts/preemption which leads to
problems.  Unfortunately DRM_I915_LOW_LEVEL_TRACEPOINTS had to be
disabled because it acquires locks from within trace points. Making the
lock a raw_spinlock_t led to higher latencies during video playback
  https://lore.kernel.org/all/20211006164628.s2mtsdd2jdbfy...@linutronix.de/

and I'm not sure if I hit the worse case here.
I tested it on a SandyBridge with built-in i915 by using X, OpenGL and
playing videos without noticing any warnings. However, some code paths
were not entered.

Sebastian

[Intel-gfx] [PATCH 4/8] drm/i915: Use preempt_disable/enable_rt() where recommended

[Sebastian Andrzej Siewior]

From: Mike Galbraith 

Mario Kleiner suggest in commit
  ad3543ede630f ("drm/intel: Push get_scanout_position() timestamping into kms 
driver.")

a spots where preemption should be disabled on PREEMPT_RT. The
difference is that on PREEMPT_RT the intel_uncore::lock disables neither
preemption nor interrupts and so region remains preemptible.

The area covers only register reads and writes. The part that worries me
is:
- __intel_get_crtc_scanline() the worst case is 100us if no match is
  found.

- intel_crtc_scanlines_since_frame_timestamp() not sure how long this
  may take in the worst case.

It was in the RT queue for a while and nobody complained.
Disable preemption on PREEPMPT_RT during timestamping.

[bigeasy: patch description.]

Cc: Mario Kleiner 
Signed-off-by: Mike Galbraith 
Signed-off-by: Thomas Gleixner 
Signed-off-by: Sebastian Andrzej Siewior 
---
 drivers/gpu/drm/i915/i915_irq.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 038a9ec563c10..8e9ff0bcbc7e4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -916,7 +916,8 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
 */
spin_lock_irqsave(_priv->uncore.lock, irqflags);
 
-   /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
+   if (IS_ENABLED(CONFIG_PREEMPT_RT))
+   preempt_disable();
 
/* Get optional system timestamp before query. */
if (stime)
@@ -980,7 +981,8 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
if (etime)
*etime = ktime_get();
 
-   /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
+   if (IS_ENABLED(CONFIG_PREEMPT_RT))
+   preempt_enable();
 
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
 
-- 
2.34.1

[Intel-gfx] [PATCH 3/8] drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() + spin_lock()

[Sebastian Andrzej Siewior]

execlists_dequeue() is invoked from a function which uses
local_irq_disable() to disable interrupts so the spin_lock() behaves
like spin_lock_irq().
This breaks PREEMPT_RT because local_irq_disable() + spin_lock() is not
the same as spin_lock_irq().

execlists_dequeue_irq() and execlists_dequeue() has each one caller
only. If intel_engine_cs::active::lock is acquired and released with the
_irq suffix then it behaves almost as if execlists_dequeue() would be
invoked with disabled interrupts. The difference is the last part of the
function which is then invoked with enabled interrupts.
I can't tell if this makes a difference. From looking at it, it might
work to move the last unlock at the end of the function as I didn't find
anything that would acquire the lock again.

Reported-by: Clark Williams 
Signed-off-by: Sebastian Andrzej Siewior 
Reviewed-by: Maarten Lankhorst 
---
 .../drm/i915/gt/intel_execlists_submission.c| 17 +
 1 file changed, 5 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index a69df5e9e77af..2d5f0c226ad66 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1284,7 +1284,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * and context switches) submission.
 */
 
-   spin_lock(_engine->lock);
+   spin_lock_irq(_engine->lock);
 
/*
 * If the queue is higher priority than the last
@@ -1384,7 +1384,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * Even if ELSP[1] is occupied and not worthy
 * of timeslices, our queue might be.
 */
-   spin_unlock(_engine->lock);
+   spin_unlock_irq(_engine->lock);
return;
}
}
@@ -1410,7 +1410,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 
if (last && !can_merge_rq(last, rq)) {
spin_unlock(>base.sched_engine->lock);
-   spin_unlock(>sched_engine->lock);
+   spin_unlock_irq(>sched_engine->lock);
return; /* leave this for another sibling */
}
 
@@ -1572,7 +1572,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 */
sched_engine->queue_priority_hint = queue_prio(sched_engine);
i915_sched_engine_reset_on_empty(sched_engine);
-   spin_unlock(_engine->lock);
+   spin_unlock_irq(_engine->lock);
 
/*
 * We can skip poking the HW if we ended up with exactly the same set
@@ -1598,13 +1598,6 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
}
 }
 
-static void execlists_dequeue_irq(struct intel_engine_cs *engine)
-{
-   local_irq_disable(); /* Suspend interrupts across request submission */
-   execlists_dequeue(engine);
-   local_irq_enable(); /* flush irq_work (e.g. breadcrumb enabling) */
-}
-
 static void clear_ports(struct i915_request **ports, int count)
 {
memset_p((void **)ports, NULL, count);
@@ -2425,7 +2418,7 @@ static void execlists_submission_tasklet(struct 
tasklet_struct *t)
}
 
if (!engine->execlists.pending[0]) {
-   execlists_dequeue_irq(engine);
+   execlists_dequeue(engine);
start_timeslice(engine);
}
 
-- 
2.34.1

[Intel-gfx] linux-next: manual merge of the drm-intel-gt tree with the drm-intel tree

[broonie]

Hi all,

Today's linux-next merge of the drm-intel-gt tree got a conflict in:

  drivers/gpu/drm/i915/i915_pci.c

between commit:

  6678916dfa012 ("drm/i915: Move pipe/transcoder/abox masks under 
intel_device_info.display")

from the drm-intel tree and commit:

  c83125bb2199b ("drm/i915: Add has_64k_pages flag")

from the drm-intel-gt tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --cc drivers/gpu/drm/i915/i915_pci.c
index ae36dfd77dcfa,332cb8b25e494..0
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@@ -1027,6 -1015,8 +1027,7 @@@ static const struct intel_device_info x
DGFX_FEATURES,
PLATFORM(INTEL_XEHPSDV),
.display = { },
+   .has_64k_pages = 1,
 -  .pipe_mask = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/cdclk: turn around i915_drv.h and intel_cdclk.h dependency (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/cdclk: turn around i915_drv.h 
and intel_cdclk.h dependency (rev3)
URL   : https://patchwork.freedesktop.org/series/97964/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11000 -> Patchwork_21844


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/index.html

Participating hosts (41 -> 35)
--

  Additional (3): fi-kbl-soraka fi-kbl-x1275 fi-rkl-11600 
  Missing(9): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan 
bat-adlp-6 fi-ctg-p8600 bat-jsl-2 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_21844 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u:   NOTRUN -> [SKIP][1] ([fdo#109271]) +21 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html

  * igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-rkl-11600:   NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-rkl-11600/igt@amdgpu/amd_cs_...@sync-gfx0.html

  * igt@amdgpu/amd_prime@amd-to-i915:
- fi-kbl-x1275:   NOTRUN -> [SKIP][3] ([fdo#109271]) +28 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-kbl-x1275/igt@amdgpu/amd_pr...@amd-to-i915.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271]) +8 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-skl-6600u:   NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
- fi-kbl-x1275:   NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-kbl-x1275/igt@gem_huc_c...@huc-copy.html
- fi-rkl-11600:   NOTRUN -> [SKIP][8] ([i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-rkl-11600/igt@gem_lmem_swapp...@basic.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- fi-kbl-x1275:   NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-kbl-x1275/igt@gem_lmem_swapp...@verify-random.html
- fi-skl-6600u:   NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_tiled_pread_basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][13] ([i915#3282])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600:   NOTRUN -> [SKIP][14] ([i915#3012])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-kefka:   [PASS][15] -> [INCOMPLETE][16] ([i915#2940])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11000/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][17] ([i915#1886] / [i915#2291])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka:  NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21844/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-rkl-11600:   NOTRUN -> [SKIP][19] ([fdo#111827]) +8 similar issues
   [19]: 

Re: [Intel-gfx] [PATCH v3 7/8] drm/i915/migrate: add acceleration support for DG2

[Matthew Auld]

On 14/12/2021 10:56, Ramalingam C wrote:

On 2021-12-06 at 13:31:39 +, Matthew Auld wrote:

This is all kinds of awkward since we now have to contend with using 64K
GTT pages when mapping anything in LMEM(including the page-tables
themselves).

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Ramalingam C 
---
  drivers/gpu/drm/i915/gt/intel_migrate.c | 189 +++-
  1 file changed, 150 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c 
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 0192b61ab541..fb658ae70a8d 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -33,6 +33,38 @@ static bool engine_supports_migration(struct intel_engine_cs 
*engine)
return true;
  }
  
+static void xehpsdv_toggle_pdes(struct i915_address_space *vm,

+   struct i915_page_table *pt,
+   void *data)
+{
+   struct insert_pte_data *d = data;
+
+   /*
+* Insert a dummy PTE into every PT that will map to LMEM to ensure
+* we have a correctly setup PDE structure for later use.
+*/
+   vm->insert_page(vm, 0, d->offset, I915_CACHE_NONE, PTE_LM);

This part i am not understanding. Why do we need to insert the dummy
PTE here.?


We have three windows, each CHUNK_SIZE in size. The first is reserved 
for mapping system-memory, and that just uses the 512 entry layout using 
4K GTT pages. The other two windows just map lmem pages and must use the 
new compact 32 entry layout using 64K GTT pages, which ensures we can 
address any lmem object that the user throws at us. The above is 
basically just toggling the PDE bit(GEN12_PDE_64K) for us, to enable the 
compact layout for each of these page-tables, that fall within the 2 * 
CHUNK_SIZE range starting at CHUNK_SIZE.




+   GEM_BUG_ON(!pt->is_compact);
+   d->offset += SZ_2M;
+}
+
+static void xehpsdv_insert_pte(struct i915_address_space *vm,
+  struct i915_page_table *pt,
+  void *data)
+{
+   struct insert_pte_data *d = data;
+
+   /*
+* We are playing tricks here, since the actual pt, from the hw
+* pov, is only 256bytes with 32 entries, or 4096bytes with 512
+* entries, but we are still guaranteed that the physical
+* alignment is 64K underneath for the pt, and we are careful
+* not to access the space in the void.
+*/
+   vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE, PTE_LM);
+   d->offset += SZ_64K;
+}
+
  static void insert_pte(struct i915_address_space *vm,
   struct i915_page_table *pt,
   void *data)
@@ -75,7 +107,12 @@ static struct i915_address_space *migrate_vm(struct 
intel_gt *gt)
 * i.e. within the same non-preemptible window so that we do not switch
 * to another migration context that overwrites the PTE.
 *
-* TODO: Add support for huge LMEM PTEs
+* On platforms with HAS_64K_PAGES support we have three windows, and
+* dedicate two windows just for mapping lmem pages(smem <-> smem is not
+* a thing), since we are forced to use 64K GTT pages underneath which
+* requires also modifying the PDE. An alternative might be to instead
+* map the PD into the GTT, and then on the fly toggle the 4K/64K mode
+* in the PDE from the same batch that also modifies the PTEs.

Could we also add a layout of the ppGTT, incase of HAS_64K_PAGES?


[0, CHUNK_SZ) -> first window, maps smem
[CHUNK_SZ, 2 * CHUNK_SZ) -> second window, maps lmem src
[2 * CHUNK_SZ, 3 * CHUNK_SZ) -> third window, maps lmem dst

It starts to get strange here, since each PTE must point to some 64K 
page, one for each PT(since it's in lmem), and yet each is only <= 
4096bytes, but since the unused space within that PTE range is never 
touched, this should be fine.


So basically each PT now needs 64K of virtual memory, instead of 4K. So 
something like:


[3 * CHUNK_SZ, 3 * CHUNK_SZ + ((3 * CHUNK_SZ / SZ_2M) * SZ_64K)] -> PTE

And then later when writing out the PTEs we know if the layout within a 
particular PT is 512 vs 32 depending on if we are mapping lmem or not.



 */
  
  	vm = i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY);

@@ -87,6 +124,9 @@ static struct i915_address_space *migrate_vm(struct intel_gt 
*gt)
goto err_vm;
}
  
+	if (HAS_64K_PAGES(gt->i915))

+   stash.pt_sz = I915_GTT_PAGE_SIZE_64K;
+
/*
 * Each engine instance is assigned its own chunk in the VM, so
 * that we can run multiple instances concurrently
@@ -106,14 +146,20 @@ static struct i915_address_space *migrate_vm(struct 
intel_gt *gt)
 * We copy in 8MiB chunks. Each PDE covers 2MiB, so we need
 * 4x2 page directories for source/destination.
 */
-   sz = 2 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/2] drm/i915/cdclk: turn around i915_drv.h and intel_cdclk.h dependency (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/cdclk: turn around i915_drv.h 
and intel_cdclk.h dependency (rev3)
URL   : https://patchwork.freedesktop.org/series/97964/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH v3 7/8] drm/i915/migrate: add acceleration support for DG2

[Ramalingam C]

On 2021-12-06 at 13:31:39 +, Matthew Auld wrote:
> This is all kinds of awkward since we now have to contend with using 64K
> GTT pages when mapping anything in LMEM(including the page-tables
> themselves).
> 
> Signed-off-by: Matthew Auld 
> Cc: Thomas Hellström 
> Cc: Ramalingam C 
> ---
>  drivers/gpu/drm/i915/gt/intel_migrate.c | 189 +++-
>  1 file changed, 150 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c 
> b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 0192b61ab541..fb658ae70a8d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -33,6 +33,38 @@ static bool engine_supports_migration(struct 
> intel_engine_cs *engine)
>   return true;
>  }
>  
> +static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
> + struct i915_page_table *pt,
> + void *data)
> +{
> + struct insert_pte_data *d = data;
> +
> + /*
> +  * Insert a dummy PTE into every PT that will map to LMEM to ensure
> +  * we have a correctly setup PDE structure for later use.
> +  */
> + vm->insert_page(vm, 0, d->offset, I915_CACHE_NONE, PTE_LM);
This part i am not understanding. Why do we need to insert the dummy
PTE here.?
> + GEM_BUG_ON(!pt->is_compact);
> + d->offset += SZ_2M;
> +}
> +
> +static void xehpsdv_insert_pte(struct i915_address_space *vm,
> +struct i915_page_table *pt,
> +void *data)
> +{
> + struct insert_pte_data *d = data;
> +
> + /*
> +  * We are playing tricks here, since the actual pt, from the hw
> +  * pov, is only 256bytes with 32 entries, or 4096bytes with 512
> +  * entries, but we are still guaranteed that the physical
> +  * alignment is 64K underneath for the pt, and we are careful
> +  * not to access the space in the void.
> +  */
> + vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE, PTE_LM);
> + d->offset += SZ_64K;
> +}
> +
>  static void insert_pte(struct i915_address_space *vm,
>  struct i915_page_table *pt,
>  void *data)
> @@ -75,7 +107,12 @@ static struct i915_address_space *migrate_vm(struct 
> intel_gt *gt)
>* i.e. within the same non-preemptible window so that we do not switch
>* to another migration context that overwrites the PTE.
>*
> -  * TODO: Add support for huge LMEM PTEs
> +  * On platforms with HAS_64K_PAGES support we have three windows, and
> +  * dedicate two windows just for mapping lmem pages(smem <-> smem is not
> +  * a thing), since we are forced to use 64K GTT pages underneath which
> +  * requires also modifying the PDE. An alternative might be to instead
> +  * map the PD into the GTT, and then on the fly toggle the 4K/64K mode
> +  * in the PDE from the same batch that also modifies the PTEs.
Could we also add a layout of the ppGTT, incase of HAS_64K_PAGES?
>*/
>  
>   vm = i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY);
> @@ -87,6 +124,9 @@ static struct i915_address_space *migrate_vm(struct 
> intel_gt *gt)
>   goto err_vm;
>   }
>  
> + if (HAS_64K_PAGES(gt->i915))
> + stash.pt_sz = I915_GTT_PAGE_SIZE_64K;
> +
>   /*
>* Each engine instance is assigned its own chunk in the VM, so
>* that we can run multiple instances concurrently
> @@ -106,14 +146,20 @@ static struct i915_address_space *migrate_vm(struct 
> intel_gt *gt)
>* We copy in 8MiB chunks. Each PDE covers 2MiB, so we need
>* 4x2 page directories for source/destination.
>*/
> - sz = 2 * CHUNK_SZ;
> + if (HAS_64K_PAGES(gt->i915))
> + sz = 3 * CHUNK_SZ;
> + else
> + sz = 2 * CHUNK_SZ;
>   d.offset = base + sz;
>  
>   /*
>* We need another page directory setup so that we can write
>* the 8x512 PTE in each chunk.
>*/
> - sz += (sz >> 12) * sizeof(u64);
> + if (HAS_64K_PAGES(gt->i915))
> + sz += (sz / SZ_2M) * SZ_64K;
> + else
> + sz += (sz >> 12) * sizeof(u64);
Here for 4K page support, per page we assume the u64 as the length required. But
for 64k page support we calculate the no of PDE and per PDE we allocate
the 64k page so that we can map it for edit right?

In this case i assume we have the unused space at the end. say after
32*sizeof(u64)

Ram
>  
>   err = i915_vm_alloc_pt_stash(>vm, , sz);
>   if (err)
> @@ -134,7 +180,18 @@ static struct i915_address_space *migrate_vm(struct 
> intel_gt *gt)
>   goto err_vm;
>  
>   /* Now allow the GPU to rewrite the PTE via its own ppGTT */
> - vm->vm.foreach(>vm, base, 

Re: [Intel-gfx] [PATCH v4 05/16] drm/i915/lmem: Enable lmem for platforms with Flat CCS

[Matthew Auld]

On 09/12/2021 15:45, Ramalingam C wrote:

From: Abdiel Janulgue 

A portion of device memory is reserved for Flat CCS so usable
device memory will be reduced by size of Flat CCS. Size of
Flat CCS is specified in “XEHPSDV_FLAT_CCS_BASE_ADDR”.
So to get effective device memory we need to subtract
total device memory by Flat CCS memory size.

Cc: Matthew Auld 
Signed-off-by: Abdiel Janulgue 
Signed-off-by: Ramalingam C 
---
  drivers/gpu/drm/i915/gt/intel_gt.c  | 19 ++
  drivers/gpu/drm/i915/gt/intel_gt.h  |  1 +
  drivers/gpu/drm/i915/gt/intel_region_lmem.c | 22 +++--
  drivers/gpu/drm/i915/i915_reg.h |  3 +++
  4 files changed, 43 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f2422d48be32..510cda6a163f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -902,6 +902,25 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt, 
i915_reg_t reg)
return intel_uncore_read_fw(gt->uncore, reg);
  }
  
+u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg)

+{
+   int type;
+   u8 sliceid, subsliceid;
+
+   for (type = 0; type < NUM_STEERING_TYPES; type++) {
+   if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
+   intel_gt_get_valid_steering(gt, type, ,
+   );
+   return intel_uncore_read_with_mcr_steering(gt->uncore,
+  reg,
+  sliceid,
+  subsliceid);
+   }
+   }
+
+   return intel_uncore_read(gt->uncore, reg);
+}
+
  void intel_gt_info_print(const struct intel_gt_info *info,
 struct drm_printer *p)
  {
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h 
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 74e771871a9b..24b78398a587 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -84,6 +84,7 @@ static inline bool intel_gt_needs_read_steering(struct 
intel_gt *gt,
  }
  
  u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);

+u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
  
  void intel_gt_info_print(const struct intel_gt_info *info,

 struct drm_printer *p);
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c 
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index fde2dcb59809..a358fa14372b 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -205,8 +205,26 @@ static struct intel_memory_region *setup_lmem(struct 
intel_gt *gt)
if (!IS_DGFX(i915))
return ERR_PTR(-ENODEV);
  
-	/* Stolen starts from GSMBASE on DG1 */

-   lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE);
+   if (HAS_FLAT_CCS(i915)) {
+   u64 tile_stolen, flat_ccs_base_addr_reg, flat_ccs_base;
+
+   lmem_size = pci_resource_len(pdev, 2);


Should we check if lmem_size < tile_stolen somewhere? I think I have 
seen that with 256M BAR. Maybe just return -ENODEV, for now?



+   flat_ccs_base_addr_reg = intel_gt_read_register(gt, 
XEHPSDV_FLAT_CCS_BASE_ADDR);
+   flat_ccs_base = (flat_ccs_base_addr_reg >> 
XEHPSDV_CCS_BASE_SHIFT) * SZ_64K;
+   tile_stolen = lmem_size - flat_ccs_base;
+
+   /* If the FLAT_CCS_BASE_ADDR register is not populated, flag an 
error */
+   if (tile_stolen == lmem_size)
+   DRM_ERROR("CCS_BASE_ADDR register did not have expected 
value\n");
+
+   lmem_size -= tile_stolen;
+   } else {
+   /* Stolen starts from GSMBASE without CCS */
+   lmem_size = intel_uncore_read64(>uncore, GEN12_GSMBASE);
+   if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2)))
+   return ERR_PTR(-ENODEV);


We also have this check below. I guess just set the lmem_size here?


+   }
+
  
  	io_start = pci_resource_start(pdev, 2);

if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2)))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d27ba273cc68..29f1cafb0f4b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12620,6 +12620,9 @@ enum skl_power_gate {
  #define   SGGI_DISREG_BIT(15)
  #define   SGR_DIS REG_BIT(13)
  
+#define XEHPSDV_FLAT_CCS_BASE_ADDR _MMIO(0x4910)

+#define   XEHPSDV_CCS_BASE_SHIFT   8
+
  /* gamt regs */
  #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
  #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for 
LRA1/2 */

Re: [Intel-gfx] [PATCH v4 04/16] drm/i915/xehpsdv: Add has_flat_ccs to device info

[Matthew Auld]

On 09/12/2021 15:45, Ramalingam C wrote:

From: CQ Tang 

Platforms of XeHP and beyond support 3D surface (buffer) compression and
various compression formats. This is accomplished by an additional
compression control state (CCS) stored for each surface.

Gen 12 devices(TGL family and DG1) stores compression states in a separate
region of memory. It is managed by user-space and has an associated set of
user-space managed page tables used by hardware for address translation.

In Xe HP and beyond (XEHPSDV, DG2, etc), there is a new feature introduced
i.e Flat CCS. It replaced AUX page tables with a flat indexed region of
device memory for storing compression states.

Cc: Joonas Lahtinen 
Cc: Matthew Auld 
Signed-off-by: CQ Tang 
Signed-off-by: Ramalingam C 
---
  drivers/gpu/drm/i915/i915_drv.h  | 2 ++
  drivers/gpu/drm/i915/i915_pci.c  | 1 +
  drivers/gpu/drm/i915/intel_device_info.h | 1 +
  3 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index aeafce112dcd..ad2dd18f7622 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1543,6 +1543,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
  #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
  #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
  
+#define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)


Could maybe add a comment here to give brief description of the feature?

Anyway,
Reviewed-by: Matthew Auld 


+
  #define HAS_GT_UC(dev_priv)   (INTEL_INFO(dev_priv)->has_gt_uc)
  
  #define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b523eb1ece5d..382e7278058a 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1005,6 +1005,7 @@ static const struct intel_device_info adl_p_info = {
XE_HP_PAGE_SIZES, \
.dma_mask_size = 46, \
.has_64bit_reloc = 1, \
+   .has_flat_ccs = 1, \
.has_global_mocs = 1, \
.has_gt_uc = 1, \
.has_llc = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 213ae2c07126..cbbb40e8451f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -129,6 +129,7 @@ enum intel_ppgtt_type {
func(has_64k_pages); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
+   func(has_flat_ccs); \
func(has_global_mocs); \
func(has_gt_uc); \
func(has_l3_dpf); \

Re: [Intel-gfx] [PATCH] drm/i915/dg1: Read OPROM via SPI controller

[Lucas De Marchi]

On Tue, Dec 14, 2021 at 11:42:41AM +0200, Jani Nikula wrote:

On Fri, 17 Sep 2021, Lucas De Marchi  wrote:

From: Clint Taylor 

Read OPROM SPI through MMIO and find VBT entry since we can't use
OpRegion and PCI mapping may not work on some systems due to most BIOSes
not leaving the Option ROM mapped.


What happened here, still not merged? :o


I don't understand neither. I got nacks, because of the other approach
to get the VBT from opregion. In that case reading via spi
controller directly would not be needed. However the other approach is
still not applied and meanwhile DG1 and DG2 have to fallback to our fake
vbt.

So I actually think we should go ahead and just merge this.

Lucas De Marchi



BR,
Jani.





Cc: Ville Syrjälä 
Cc: Tomas Winkler 
Signed-off-by: Clint Taylor 
Signed-off-by: Lucas De Marchi 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 80 +--
 drivers/gpu/drm/i915/i915_reg.h   |  8 +++
 2 files changed, 82 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index 3c25926092de..7f179dbdec1b 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2280,6 +2280,66 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t 
size)
return vbt;
 }

+static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915)
+{
+   u32 count, data, found, store = 0;
+   u32 static_region, oprom_offset;
+   u32 oprom_size = 0x20;
+   u16 vbt_size;
+   u32 *vbt;
+
+   static_region = intel_uncore_read(>uncore, SPI_STATIC_REGIONS);
+   static_region &= OPTIONROM_SPI_REGIONID_MASK;
+   intel_uncore_write(>uncore, PRIMARY_SPI_REGIONID, static_region);
+
+   oprom_offset = intel_uncore_read(>uncore, OROM_OFFSET);
+   oprom_offset &= OROM_OFFSET_MASK;
+
+   for (count = 0; count < oprom_size; count += 4) {
+   intel_uncore_write(>uncore, PRIMARY_SPI_ADDRESS, 
oprom_offset + count);
+   data = intel_uncore_read(>uncore, PRIMARY_SPI_TRIGGER);
+
+   if (data == *((const u32 *)"$VBT")) {
+   found = oprom_offset + count;
+   break;
+   }
+   }
+
+   if (count >= oprom_size)
+   goto err_not_found;
+
+   /* Get VBT size and allocate space for the VBT */
+   intel_uncore_write(>uncore, PRIMARY_SPI_ADDRESS, found +
+  offsetof(struct vbt_header, vbt_size));
+   vbt_size = intel_uncore_read(>uncore, PRIMARY_SPI_TRIGGER);
+   vbt_size &= 0x;
+
+   vbt = kzalloc(vbt_size, GFP_KERNEL);
+   if (!vbt) {
+   drm_err(>drm, "Unable to allocate %u bytes for VBT 
storage\n",
+   vbt_size);
+   goto err_not_found;
+   }
+
+   for (count = 0; count < vbt_size; count += 4) {
+   intel_uncore_write(>uncore, PRIMARY_SPI_ADDRESS, found + 
count);
+   data = intel_uncore_read(>uncore, PRIMARY_SPI_TRIGGER);
+   *(vbt + store++) = data;
+   }
+
+   if (!intel_bios_is_valid_vbt(vbt, vbt_size))
+   goto err_free_vbt;
+
+   drm_dbg_kms(>drm, "Found valid VBT in SPI flash\n");
+
+   return (struct vbt_header *)vbt;
+
+err_free_vbt:
+   kfree(vbt);
+err_not_found:
+   return NULL;
+}
+
 static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915)
 {
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
@@ -2329,6 +2389,8 @@ static struct vbt_header *oprom_get_vbt(struct 
drm_i915_private *i915)

pci_unmap_rom(pdev, oprom);

+   drm_dbg_kms(>drm, "Found valid VBT in PCI ROM\n");
+
return vbt;

 err_free_vbt:
@@ -2363,17 +2425,23 @@ void intel_bios_init(struct drm_i915_private *i915)

init_vbt_defaults(i915);

-   /* If the OpRegion does not have VBT, look in PCI ROM. */
+   /*
+* If the OpRegion does not have VBT, look in SPI flash through MMIO or
+* PCI mapping
+*/
+   if (!vbt && IS_DGFX(i915)) {
+   oprom_vbt = spi_oprom_get_vbt(i915);
+   vbt = oprom_vbt;
+   }
+
if (!vbt) {
oprom_vbt = oprom_get_vbt(i915);
-   if (!oprom_vbt)
-   goto out;
-
vbt = oprom_vbt;
-
-   drm_dbg_kms(>drm, "Found valid VBT in PCI ROM\n");
}

+   if (!vbt)
+   goto out;
+
bdb = get_bdb_header(vbt);
i915->vbt.version = bdb->version;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3a21f7c003d..fd3fee090412 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12771,6 +12771,14 @@ enum skl_power_gate {
 #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT   REG_BIT(1)
 #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT   REG_BIT(0)

+#define PRIMARY_SPI_TRIGGER   

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 01/11] tests/i915/i915_hangman: Add descriptions

[Petri Latvala]

On Mon, Dec 13, 2021 at 03:29:04PM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison 
> 
> Added descriptions of the various sub-tests and the test as a whole.
> 
> Signed-off-by: John Harrison 
> ---
>  tests/i915/i915_hangman.c | 11 +--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> index 4c18c22db..025bb8713 100644
> --- a/tests/i915/i915_hangman.c
> +++ b/tests/i915/i915_hangman.c
> @@ -46,6 +46,8 @@
>  static int device = -1;
>  static int sysfs = -1;
>  
> +IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
> +
>  static bool has_error_state(int dir)
>  {
>   bool result;
> @@ -315,9 +317,9 @@ static void hangcheck_unterminated(void)
>  
>   gem_execbuf(device, );
>   if (gem_wait(device, handle, _ns) != 0) {
> - /* need to manually trigger an hang to clean before failing */
> + /* need to manually trigger a hang to clean before failing */
>   igt_force_gpu_reset(device);
> - igt_assert_f(0, "unterminated batch did not trigger an hang!");
> + igt_assert_f(0, "unterminated batch did not trigger a hang!");

Ouch, this is a bug that could use a drive-by fix in this same commit:
Add a newline after that text.

With that,
Reviewed-by: Petri Latvala 

>   }
>  }
>  
> @@ -341,9 +343,11 @@ igt_main
>   igt_require(has_error_state(sysfs));
>   }
>  
> + igt_describe("Basic error capture");
>   igt_subtest("error-state-basic")
>   test_error_state_basic();
>  
> + igt_describe("Per engine error capture");
>   igt_subtest_with_dynamic("error-state-capture") {
>   for_each_ctx_engine(device, ctx, e) {
>   igt_dynamic_f("%s", e->name)
> @@ -351,6 +355,7 @@ igt_main
>   }
>   }
>  
> + igt_describe("Per engine hang recovery (spin)");
>   igt_subtest_with_dynamic("engine-hang") {
>  int has_gpu_reset = 0;
>   struct drm_i915_getparam gp = {
> @@ -369,6 +374,7 @@ igt_main
>   }
>   }
>  
> + igt_describe("Per engine hang recovery (invalid CS)");
>   igt_subtest_with_dynamic("engine-error") {
>   int has_gpu_reset = 0;
>   struct drm_i915_getparam gp = {
> @@ -386,6 +392,7 @@ igt_main
>   }
>   }
>  
> + igt_describe("Check that executing unintialised memory causes a hang");
>   igt_subtest("hangcheck-unterminated")
>   hangcheck_unterminated();
>  
> -- 
> 2.25.1
> 

Re: [Intel-gfx] [PATCH 0/3] drm/i915: Sanity Check for device memory region

[Ramalingam C]

On 2021-12-08 at 21:04:01 +0530, Ramalingam C wrote:
> Changes for introducing the quick test on the device memory range and
> also a test of detailed validation for each addr of the range with read
> and write.
> 
> Detailed testing is optionally enabled with a modparam i915.memtest=1
> 
> And third patch fixes the driver accessible stolen memory.
> 
> v2: Adding a wrapper for the memtest [Chris]
> v3: Handling a bisecting issue.

Thanks for the review. The changes are merged.

Ram.
> 
> Chris Wilson (3):
>   drm/i915: Exclude reserved stolen from driver use
>   drm/i915: Sanitycheck device iomem on probe
>   drm/i915: Test all device memory on probing
> 
>  drivers/gpu/drm/i915/gem/i915_gem_stolen.c |   3 +
>  drivers/gpu/drm/i915/i915_params.c |   3 +
>  drivers/gpu/drm/i915/i915_params.h |   1 +
>  drivers/gpu/drm/i915/intel_memory_region.c | 128 +
>  4 files changed, 135 insertions(+)
> 
> -- 
> 2.20.1
> 

Re: [Intel-gfx] [PATCH] drm/i915/dg1: Read OPROM via SPI controller

[Jani Nikula]

On Fri, 17 Sep 2021, Lucas De Marchi  wrote:
> From: Clint Taylor 
>
> Read OPROM SPI through MMIO and find VBT entry since we can't use
> OpRegion and PCI mapping may not work on some systems due to most BIOSes
> not leaving the Option ROM mapped.

What happened here, still not merged? :o

BR,
Jani.



>
> Cc: Ville Syrjälä 
> Cc: Tomas Winkler 
> Signed-off-by: Clint Taylor 
> Signed-off-by: Lucas De Marchi 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 80 +--
>  drivers/gpu/drm/i915/i915_reg.h   |  8 +++
>  2 files changed, 82 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 3c25926092de..7f179dbdec1b 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2280,6 +2280,66 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t 
> size)
>   return vbt;
>  }
>  
> +static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915)
> +{
> + u32 count, data, found, store = 0;
> + u32 static_region, oprom_offset;
> + u32 oprom_size = 0x20;
> + u16 vbt_size;
> + u32 *vbt;
> +
> + static_region = intel_uncore_read(>uncore, SPI_STATIC_REGIONS);
> + static_region &= OPTIONROM_SPI_REGIONID_MASK;
> + intel_uncore_write(>uncore, PRIMARY_SPI_REGIONID, static_region);
> +
> + oprom_offset = intel_uncore_read(>uncore, OROM_OFFSET);
> + oprom_offset &= OROM_OFFSET_MASK;
> +
> + for (count = 0; count < oprom_size; count += 4) {
> + intel_uncore_write(>uncore, PRIMARY_SPI_ADDRESS, 
> oprom_offset + count);
> + data = intel_uncore_read(>uncore, PRIMARY_SPI_TRIGGER);
> +
> + if (data == *((const u32 *)"$VBT")) {
> + found = oprom_offset + count;
> + break;
> + }
> + }
> +
> + if (count >= oprom_size)
> + goto err_not_found;
> +
> + /* Get VBT size and allocate space for the VBT */
> + intel_uncore_write(>uncore, PRIMARY_SPI_ADDRESS, found +
> +offsetof(struct vbt_header, vbt_size));
> + vbt_size = intel_uncore_read(>uncore, PRIMARY_SPI_TRIGGER);
> + vbt_size &= 0x;
> +
> + vbt = kzalloc(vbt_size, GFP_KERNEL);
> + if (!vbt) {
> + drm_err(>drm, "Unable to allocate %u bytes for VBT 
> storage\n",
> + vbt_size);
> + goto err_not_found;
> + }
> +
> + for (count = 0; count < vbt_size; count += 4) {
> + intel_uncore_write(>uncore, PRIMARY_SPI_ADDRESS, found + 
> count);
> + data = intel_uncore_read(>uncore, PRIMARY_SPI_TRIGGER);
> + *(vbt + store++) = data;
> + }
> +
> + if (!intel_bios_is_valid_vbt(vbt, vbt_size))
> + goto err_free_vbt;
> +
> + drm_dbg_kms(>drm, "Found valid VBT in SPI flash\n");
> +
> + return (struct vbt_header *)vbt;
> +
> +err_free_vbt:
> + kfree(vbt);
> +err_not_found:
> + return NULL;
> +}
> +
>  static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915)
>  {
>   struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> @@ -2329,6 +2389,8 @@ static struct vbt_header *oprom_get_vbt(struct 
> drm_i915_private *i915)
>  
>   pci_unmap_rom(pdev, oprom);
>  
> + drm_dbg_kms(>drm, "Found valid VBT in PCI ROM\n");
> +
>   return vbt;
>  
>  err_free_vbt:
> @@ -2363,17 +2425,23 @@ void intel_bios_init(struct drm_i915_private *i915)
>  
>   init_vbt_defaults(i915);
>  
> - /* If the OpRegion does not have VBT, look in PCI ROM. */
> + /*
> +  * If the OpRegion does not have VBT, look in SPI flash through MMIO or
> +  * PCI mapping
> +  */
> + if (!vbt && IS_DGFX(i915)) {
> + oprom_vbt = spi_oprom_get_vbt(i915);
> + vbt = oprom_vbt;
> + }
> +
>   if (!vbt) {
>   oprom_vbt = oprom_get_vbt(i915);
> - if (!oprom_vbt)
> - goto out;
> -
>   vbt = oprom_vbt;
> -
> - drm_dbg_kms(>drm, "Found valid VBT in PCI ROM\n");
>   }
>  
> + if (!vbt)
> + goto out;
> +
>   bdb = get_bdb_header(vbt);
>   i915->vbt.version = bdb->version;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c3a21f7c003d..fd3fee090412 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -12771,6 +12771,14 @@ enum skl_power_gate {
>  #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
>  #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
>  
> +#define PRIMARY_SPI_TRIGGER  _MMIO(0x102040)
> +#define PRIMARY_SPI_ADDRESS  _MMIO(0x102080)
> +#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
> +#define SPI_STATIC_REGIONS   _MMIO(0x102090)
> +#define   OPTIONROM_SPI_REGIONID_MASK

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/debugfs: add noreclaim annotations (rev2)

[Matthew Auld]

On 14/12/2021 04:55, Patchwork wrote:

*Patch Details*
*Series:*   drm/i915/debugfs: add noreclaim annotations (rev2)
*URL:*	https://patchwork.freedesktop.org/series/97966/ 


*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21842/index.html 




  CI Bug Log - changes from CI_DRM_10996_full -> Patchwork_21842_full


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_21842_full absolutely need 
to be

verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21842_full, please notify your bug team to allow 
them

to document this new failure mode, which will reduce false positives in CI.


Participating hosts (10 -> 10)

No changes in participating hosts


Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_21842_full:



  IGT changes


Possible regressions

  *

igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:

  o

shard-iclb: NOTRUN -> SKIP



  o

shard-tglb: NOTRUN -> SKIP



  *

igt@perf@enable-disable:

  o shard-glk: PASS


-> FAIL




Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
  o {shard-rkl}: NOTRUN -> SKIP





These all look to be unrelated.



Known issues

Here are the changes found in Patchwork_21842_full that come from known 
issues:



  IGT changes


Issues hit

  *

igt@gem_ctx_isolation@preservation-s3@rcs0:

  o shard-apl: PASS


-> DMESG-WARN


([i915#180]) +2 similar issues
  *

igt@gem_ctx_isolation@preservation-s3@vcs0:

  o shard-kbl: PASS


-> DMESG-WARN


([i915#180]) +5 similar issues
  *

igt@gem_exec_fair@basic-deadline:

  o shard-kbl: PASS


-> FAIL


([i915#2846])
  *

igt@gem_exec_fair@basic-none-share@rcs0:

  o shard-glk: PASS


-> FAIL


([i915#2842])
  *

igt@gem_exec_fair@basic-none-solo@rcs0:

  o shard-kbl: NOTRUN -> FAIL


([i915#2842])
  *

igt@gem_exec_fair@basic-pace@vcs1:

  o shard-kbl: PASS


-> FAIL


([i915#2842]) +1 similar issue
  *

igt@gem_lmem_swapping@parallel-multi:

  o shard-tglb: NOTRUN -> SKIP


([i915#4613]) +2 similar issues
  *

igt@gem_lmem_swapping@random:

  o

shard-apl: NOTRUN -> SKIP


([fdo#109271] / [i915#4613])

  o

shard-kbl: NOTRUN -> SKIP

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/debugfs: add noreclaim annotations

[Matthew Auld]

On 13/12/2021 18:15, Patchwork wrote:

*Patch Details*
*Series:*   drm/i915/debugfs: add noreclaim annotations
*URL:*	https://patchwork.freedesktop.org/series/97966/ 


*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21838/index.html 




  CI Bug Log - changes from CI_DRM_10995 -> Patchwork_21838


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_21838 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21838, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21838/index.html



Participating hosts (40 -> 33)

Missing (7): bat-dg1-6 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 
fi-pnv-d510 fi-bdw-samus



Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_21838:



  IGT changes


Possible regressions

  * igt@i915_selftest@live@gem:
  o fi-blb-e6850: PASS


-> DMESG-FAIL





Unrelated, looks like an object leaked.




Known issues

Here are the changes found in Patchwork_21838 that come from known issues:


  IGT changes


Issues hit

  *

igt@amdgpu/amd_basic@cs-gfx:

  o fi-rkl-guc: NOTRUN -> SKIP


(fdo#109315
) +17
similar issues
  *

igt@amdgpu/amd_basic@semaphore:

  o fi-bdw-5557u: NOTRUN -> SKIP


(fdo#109271
) +31
similar issues
  *

igt@amdgpu/amd_cs_nop@sync-fork-gfx0:

  o fi-skl-6600u: NOTRUN -> SKIP


(fdo#109271
) +21
similar issues
  *

igt@gem_huc_copy@huc-copy:

  o fi-skl-6600u: NOTRUN -> SKIP


(fdo#109271
 /
i915#2190 )
  *

igt@gem_lmem_swapping@verify-random:

  o fi-skl-6600u: NOTRUN -> SKIP


(fdo#109271
 /
i915#4613
) +3
similar issues
  *

igt@kms_chamelium@dp-crc-fast:

  o fi-bdw-5557u: NOTRUN -> SKIP


(fdo#109271
 /
fdo#111827
) +8
similar issues
  *

igt@kms_chamelium@vga-edid-read:

  o fi-skl-6600u: NOTRUN -> SKIP


(fdo#109271
 /
fdo#111827
) +8
similar issues
  *

igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:

  o fi-skl-6600u: NOTRUN -> SKIP


(fdo#109271
 / i915#533
)
  *

igt@runner@aborted:

  o fi-blb-e6850: NOTRUN -> FAIL


(fdo#109271
 /
i915#2403 
/ i915#4312 )


Possible fixes

  *

igt@gem_exec_suspend@basic-s3:

  o fi-bdw-5557u: 

Re: [Intel-gfx] [PULL] drm-misc-next

[Daniel Vetter]

On Mon, Nov 29, 2021 at 09:56:47AM +0100, Thomas Zimmermann wrote:
> Hi Dave and Daniel,
> 
> here's the second PR for drm-misc-next for what will become Linux 5.17.
> It's a bit late, as I was on vacation last week. The most significant
> change moves the nomodeset parameter entirely into the DRM subsystem.
> 
> Best regards
> Thomas
> 
> drm-misc-next-2021-11-29:
> drm-misc-next for 5.17:
> 
> UAPI Changes:
> 
> Cross-subsystem Changes:
> 
>  * Move 'nomodeset' kernel boot option into DRM subsystem
> 
> Core Changes:
> 
>  * Replace several DRM_*() logging macros with drm_*() equivalents
>  * panel: Add quirk for Lenovo Yoga Book X91F/L
>  * ttm: Documentation fixes
> 
> Driver Changes:
> 
>  * Cleanup nomodeset handling in drivers
>  * Fixes
>  * bridge/anx7625: Fix reading EDID; Fix error code
>  * bridge/megachips: Probe both bridges before registering
>  * vboxvideo: Fix ERR_PTR usage
> The following changes since commit a713ca234ea9d946235ac7248995c5fddfd9e523:
> 
>   Merge drm/drm-next into drm-misc-next (2021-11-18 09:36:39 +0100)
> 
> are available in the Git repository at:
> 
>   git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2021-11-29

Pulled, thanks.
-Daniel

> 
> for you to fetch changes up to 69d846126e1653ca9043c3766c66684132586941:
> 
>   drm: Fix build error caused by missing drm_nomodeset.o (2021-11-27 21:05:58 
> +0100)
> 
> 
> drm-misc-next for 5.17:
> 
> UAPI Changes:
> 
> Cross-subsystem Changes:
> 
>  * Move 'nomodeset' kernel boot option into DRM subsystem
> 
> Core Changes:
> 
>  * Replace several DRM_*() logging macros with drm_*() equivalents
>  * panel: Add quirk for Lenovo Yoga Book X91F/L
>  * ttm: Documentation fixes
> 
> Driver Changes:
> 
>  * Cleanup nomodeset handling in drivers
>  * Fixes
>  * bridge/anx7625: Fix reading EDID; Fix error code
>  * bridge/megachips: Probe both bridges before registering
>  * vboxvideo: Fix ERR_PTR usage
> 
> 
> Christian König (1):
>   drm/amdgpu: partially revert "svm bo enable_signal call condition"
> 
> Claudio Suarez (1):
>   drm: get rid of DRM_DEBUG_* log calls in drm core, files drm_a*.c
> 
> Dan Carpenter (2):
>   drm/vboxvideo: fix a NULL vs IS_ERR() check
>   drm/bridge: anx7625: fix an error code in anx7625_register_audio()
> 
> Hans de Goede (1):
>   drm: panel-orientation-quirks: Add quirk for the Lenovo Yoga Book X91F/L
> 
> Hsin-Yi Wang (1):
>   drm/bridge: anx7625: Fix edid_read break case in sp_tx_edid_read()
> 
> Javier Martinez Canillas (7):
>   drm: Don't print messages if drivers are disabled due nomodeset
>   drm/vboxvideo: Drop CONFIG_VGA_CONSOLE guard to call vgacon_text_force()
>   drm: Move nomodeset kernel parameter to the DRM subsystem
>   drm: Decouple nomodeset from CONFIG_VGA_CONSOLE
>   Documentation/admin-guide: Document nomodeset kernel parameter
>   drm: Make the nomodeset message less sensational
>   drm: Fix build error caused by missing drm_nomodeset.o
> 
> Martyn Welch (1):
>   drm/bridge: megachips: Ensure both bridges are probed before 
> registration
> 
> Randy Dunlap (1):
>   drm: ttm: correct ttm_range_manager kernel-doc notation
> 
>  Documentation/admin-guide/kernel-parameters.txt|   7 +
>  drivers/gpu/drm/Kconfig|   6 +
>  drivers/gpu/drm/Makefile   |   2 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|   5 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|   9 -
>  drivers/gpu/drm/ast/ast_drv.c  |   3 +-
>  drivers/gpu/drm/bridge/analogix/anx7625.c  |   6 +-
>  .../drm/bridge/megachips-stdp-ge-b850v3-fw.c   |  40 +++-
>  drivers/gpu/drm/drm_atomic.c   | 180 ---
>  drivers/gpu/drm/drm_atomic_helper.c| 243 
> -
>  drivers/gpu/drm/drm_atomic_uapi.c  |   2 +-
>  drivers/gpu/drm/drm_auth.c |  12 +-
>  drivers/gpu/drm/drm_nomodeset.c|  24 ++
>  drivers/gpu/drm/drm_panel_orientation_quirks.c |   6 +
>  drivers/gpu/drm/i915/i915_module.c |   4 +-
>  drivers/gpu/drm/mgag200/mgag200_drv.c  |   3 +-
>  drivers/gpu/drm/nouveau/nouveau_drm.c  |   4 +-
>  drivers/gpu/drm/qxl/qxl_drv.c  |   3 +-
>  drivers/gpu/drm/radeon/radeon_drv.c|   9 +-
>  drivers/gpu/drm/tiny/bochs.c   |   3 +-
>  drivers/gpu/drm/tiny/cirrus.c  |   4 +-
>  drivers/gpu/drm/ttm/ttm_range_manager.c|  11 +-
>  drivers/gpu/drm/vboxvideo/vbox_drv.c   |   5 +-
>  drivers/gpu/drm/vboxvideo/vbox_main.c  |   4 +-
>  drivers/gpu/drm/virtio/virtgpu_drv.c   |   3 +-
>  drivers/gpu/drm/vmwgfx/vmwgfx_drv.c|   3 +-
>  

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix implicit use of struct pci_dev

[Jani Nikula]

On Tue, 14 Dec 2021, Mark Brown  wrote:
> On Tue, Dec 14, 2021 at 01:36:33AM -, Patchwork wrote:
>> == Series Details ==
>> 
>> Series: drm/i915: Fix implicit use of struct pci_dev
>> URL   : https://patchwork.freedesktop.org/series/97975/
>> State : failure
>> 
>> == Summary ==
>> 
>> CI Bug Log - changes from CI_DRM_10995_full -> Patchwork_21841_full
>> 
>> 
>> Summary
>> ---
>> 
>>   **FAILURE**
>> 
>>   Serious unknown changes coming with Patchwork_21841_full absolutely need 
>> to be
>>   verified manually.
>>   
>>   If you think the reported changes have nothing to do with the changes
>>   introduced in Patchwork_21841_full, please notify your bug team to allow 
>> them
>>   to document this new failure mode, which will reduce false positives in CI.
>
> This report appears to be a false positive - it is difficult to see how
> the change could have triggered anything in the tests and the reported
> change looks like an administrative change with the infra.

Yeah, don't worry about it. Pushed to drm-intel-next, thanks for the
patch.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center