[Intel-gfx] [CI] PR for new GuC v69.0.3
The following changes since commit b0e898fbaf377c99a36aac6fdeb7250003648ca4: linux-firmware: Update firmware file for Intel Bluetooth 9462 (2021-11-23 12:31:45 -0500) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware guc_v69.0.3 for you to fetch changes up to 548b304a35b77cd43c1242e0eae68f775bd0df2a: i915: Add GuC v69.0.3 for all platforms (2021-12-15 13:28:54 -0800) John Harrison (1): i915: Add GuC v69.0.3 for all platforms WHENCE | 30 ++ i915/adlp_guc_69.0.3.bin | Bin 0 -> 356416 bytes i915/bxt_guc_69.0.3.bin | Bin 0 -> 216768 bytes i915/cml_guc_69.0.3.bin | Bin 0 -> 217664 bytes i915/dg1_guc_69.0.3.bin | Bin 0 -> 323968 bytes i915/ehl_guc_69.0.3.bin | Bin 0 -> 343360 bytes i915/glk_guc_69.0.3.bin | Bin 0 -> 217216 bytes i915/icl_guc_69.0.3.bin | Bin 0 -> 343360 bytes i915/kbl_guc_69.0.3.bin | Bin 0 -> 217664 bytes i915/skl_guc_69.0.3.bin | Bin 0 -> 216704 bytes i915/tgl_guc_69.0.3.bin | Bin 0 -> 343296 bytes 11 files changed, 30 insertions(+) create mode 100644 i915/adlp_guc_69.0.3.bin create mode 100644 i915/bxt_guc_69.0.3.bin create mode 100644 i915/cml_guc_69.0.3.bin create mode 100644 i915/dg1_guc_69.0.3.bin create mode 100644 i915/ehl_guc_69.0.3.bin create mode 100644 i915/glk_guc_69.0.3.bin create mode 100644 i915/icl_guc_69.0.3.bin create mode 100644 i915/kbl_guc_69.0.3.bin create mode 100644 i915/skl_guc_69.0.3.bin create mode 100644 i915/tgl_guc_69.0.3.bin
Re: [Intel-gfx] [PATCH] drm/i915/dg2: add Wa_14015023722
On Fri, Jan 14, 2022 at 11:41:31AM -0800, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> BSPEC: 46123
> Cc: Matt Roper
> Signed-off-by: Clint Taylor
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
> drivers/gpu/drm/i915/i915_reg.h | 4
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 6a4372c3a3c5..5cdacfa8aefc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -688,6 +688,11 @@ static void dg2_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0))
> wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
>DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
> +
> + /* wa_14015023722: DG2 G11 [B0..NONE] */
We generally want to refer to workarounds by their lineage number rather
than by their per-platform bug IDs. In this case the lineage number of
the workaround is Wa_14014947963.
> + if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_B0, STEP_FOREVER))
It looks like this workaround applies to DG2-G10 for B0 and beyond, so
the condition above should say "G10" rather than G11. It also applies
to G11 and G12 for _all_ steppings. I haven't sent the patch that adds
the G12 subplatform yet, but I'll do that soon. In the meantime, you'll
want an "|| IS_DG2_G11(engine->i915)" added to the condition since it
applies to all steppings of that subplatform.
> + wa_masked_en(wal, VF_PREEMPTION, PREEMPTION_VERTEX_4000);
wa_masked_en() will turn on any bits in PREEMPTION_VERTEX_4000 (i.e.,
bit 14 in this case), but won't clear any of the other bits that might
already be set in hardware. I think you want to use
wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000)
so that the bits 15:0 become exactly 0x4000 rather than just having bit
14 turned on. I also think it's fine to just pass a literal 0x4000 for
the final parameter rather than PREEMPTION_VERTEX_4000 in this case
since it is just a count and not representing a special enum value or
anything.
Matt
> +
> }
>
> static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ef6bc8180073..5805a45920b3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11934,4 +11934,8 @@ enum skl_power_gate {
> #define SLICE_COMMON_ECO_CHICKEN1_MMIO(0x731C)
> #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
>
> +#define VF_PREEMPTION_MMIO(0x83a4)
> +#define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
> +#define PREEMPTION_VERTEX_4000
> REG_FIELD_PREP(PREEMPTION_VERTEX_COUNT, 0x4000)
> +
> #endif /* _I915_REG_H_ */
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: add Wa_14015023722
== Series Details == Series: drm/i915/dg2: add Wa_14015023722 URL : https://patchwork.freedesktop.org/series/98911/ State : success == Summary == CI Bug Log - changes from CI_DRM_11088 -> Patchwork_22005 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/index.html Participating hosts (50 -> 42) -- Additional (1): fi-kbl-soraka Missing(9): fi-ilk-m540 shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 shard-rkl shard-dg1 bat-jsl-2 fi-bdw-samus Known issues Here are the changes found in Patchwork_22005 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-blb-e6850: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-blb-e6850/igt@amdgpu/amd_cs_...@fork-compute0.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +8 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_suspend@basic-s0@smem: - fi-skl-6700k2: [PASS][3] -> [DMESG-WARN][4] ([i915#4751]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11088/fi-skl-6700k2/igt@gem_exec_suspend@basic...@smem.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-skl-6700k2/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#2291]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[PASS][10] -> [INCOMPLETE][11] ([i915#3921]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11088/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@dp-edid-read: - fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html * igt@kms_chamelium@vga-edid-read: - fi-skl-6600u: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-skl-6600u: NOTRUN -> [SKIP][14] ([fdo#109271]) +21 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6600u: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#533]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html - fi-kbl-soraka: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@runner@aborted: - fi-skl-6700k2: NOTRUN -> [FAIL][17] ([i915#4312]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-skl-6700k2/igt@run...@aborted.html - fi-bdw-5557u: NOTRUN -> [FAIL][18] ([i915#2426] / [i915#4312]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22005/fi-bdw-5557u/igt@run...@aborted.html Possible fixes * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [INCOMPLETE][19] ([i915#4547]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11088/fi-skl-6600u/igt@gem_flink_ba...@bad-fli
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg2: add Wa_14015023722
== Series Details == Series: drm/i915/dg2: add Wa_14015023722 URL : https://patchwork.freedesktop.org/series/98911/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/wopcm: Handle pre-programmed WOPCM registers
== Series Details == Series: drm/i915/wopcm: Handle pre-programmed WOPCM registers URL : https://patchwork.freedesktop.org/series/98910/ State : success == Summary == CI Bug Log - changes from CI_DRM_11088 -> Patchwork_22004 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22004/index.html Participating hosts (50 -> 41) -- Additional (1): fi-icl-u2 Missing(10): fi-ilk-m540 shard-tglu fi-bsw-n3050 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 shard-rkl shard-dg1 fi-bdw-samus Known issues Here are the changes found in Patchwork_22004 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-blb-e6850: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22004/fi-blb-e6850/igt@amdgpu/amd_cs_...@fork-compute0.html * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22004/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [PASS][3] -> [INCOMPLETE][4] ([i915#146]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11088/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22004/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-icl-u2: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22004/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-icl-u2: NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22004/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_pm_rpm@module-reload: - fi-kbl-guc: [PASS][7] -> [SKIP][8] ([fdo#109271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11088/fi-kbl-guc/igt@i915_pm_...@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22004/fi-kbl-guc/igt@i915_pm_...@module-reload.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22004/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: NOTRUN -> [SKIP][10] ([fdo#109278]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22004/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_force_connector_basic@force-load-detect: - fi-icl-u2: NOTRUN -> [SKIP][11] ([fdo#109285]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22004/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html * igt@prime_vgem@basic-userptr: - fi-icl-u2: NOTRUN -> [SKIP][12] ([i915#3301]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22004/fi-icl-u2/igt@prime_v...@basic-userptr.html Possible fixes * igt@i915_selftest@live@hangcheck: - bat-dg1-6: [DMESG-FAIL][13] ([i915#4494]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11088/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22004/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html - bat-dg1-5: [DMESG-FAIL][15] ([i915#4494]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11088/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22004/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@requests: - fi-blb-e6850: [DMESG-FAIL][17] ([i915#4528]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11088/fi-blb-e6850/igt@i915_selftest@l...@requests.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22004/fi-blb-e6850/igt@i915_selftest@l...@requests.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][19] ([i915#4269]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11088/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22004/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html Warnings * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [INCOMPLETE][21] ([i915#4547]) -> [FAIL][22] ([i915#4547]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11088/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html [22]: https://intel-g
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/wopcm: Handle pre-programmed WOPCM registers
== Series Details == Series: drm/i915/wopcm: Handle pre-programmed WOPCM registers URL : https://patchwork.freedesktop.org/series/98910/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/wopcm: Handle pre-programmed WOPCM registers
== Series Details == Series: drm/i915/wopcm: Handle pre-programmed WOPCM registers URL : https://patchwork.freedesktop.org/series/98910/ State : warning == Summary == $ dim checkpatch origin/drm-tip 03db6d6cfb02 drm/i915/wopcm: Handle pre-programmed WOPCM registers -:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #14: sometimes using a smaller WOPCM size that the actual HW support (which isn't -:36: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #36: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h:98: +#define GUC_IS_PRIVILEGED(1<<29) ^ total: 0 errors, 1 warnings, 1 checks, 134 lines checked
[Intel-gfx] [PATCH] drm/i915/dg2: add Wa_14015023722
From: Clint Taylor
BSPEC: 46123
Cc: Matt Roper
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6a4372c3a3c5..5cdacfa8aefc 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -688,6 +688,11 @@ static void dg2_ctx_workarounds_init(struct
intel_engine_cs *engine,
IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0))
wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
+
+ /* wa_14015023722: DG2 G11 [B0..NONE] */
+ if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_B0, STEP_FOREVER))
+ wa_masked_en(wal, VF_PREEMPTION, PREEMPTION_VERTEX_4000);
+
}
static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ef6bc8180073..5805a45920b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11934,4 +11934,8 @@ enum skl_power_gate {
#define SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731C)
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
+#define VF_PREEMPTION _MMIO(0x83a4)
+#define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
+#define PREEMPTION_VERTEX_4000
REG_FIELD_PREP(PREEMPTION_VERTEX_COUNT, 0x4000)
+
#endif /* _I915_REG_H_ */
--
2.34.1
[Intel-gfx] [PATCH] drm/i915/wopcm: Handle pre-programmed WOPCM registers
Starting from DG2, some of the programming previously done by i915 and
the GuC has been moved to the GSC and the relevant registers are no
longer writable by either CPU or GuC. This is also referred to as GuC
deprivilege.
On the i915 side, this affects the WOPCM registers: these are no longer
programmed by the driver and we do instead expect to find them already
set. This can lead to verification failures because in i915 we cheat a bit
with the WOPCM size defines, to keep the code common across platforms, by
sometimes using a smaller WOPCM size that the actual HW support (which isn't
a problem because the extra size is not needed if the FW fits in the smaller
chunk), while the pre-programmed values can use the actual size.
Given tha the new programming entity is trusted, relax the amount of the
checks done on the pre-programmed values by not limiting the max
programmed size. In the extremely unlikely scenario that the registers
have been misprogrammed, we will still fail later at DMA time.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Stuart Summers
Cc: John Harrison
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 3 ++
drivers/gpu/drm/i915/i915_drv.h| 3 ++
drivers/gpu/drm/i915/i915_pci.c| 1 +
drivers/gpu/drm/i915/intel_device_info.c | 8 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_wopcm.c | 42 ++
6 files changed, 51 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index e6bd66d6ce5a..cdb47c2291c8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -94,6 +94,9 @@
#define GUC_ENABLE_MIA_CLOCK_GATING (1<<15)
#define GUC_GEN10_SHIM_WC_ENABLE (1<<21)
+#define GUC_SHIM_CONTROL2 _MMIO(0xc068)
+#define GUC_IS_PRIVILEGED(1<<29)
+
#define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
#define GUC_SEND_TRIGGER (1<<0)
#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6caec2eca8cd..4fe6e1444f17 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1565,6 +1565,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define INTEL_DISPLAY_ENABLED(dev_priv) \
(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),
!(dev_priv)->params.disable_display)
+#define HAS_GUC_DEPRIVILEGE(dev_priv) \
+ (INTEL_INFO(dev_priv)->has_guc_deprivilege)
+
static inline bool run_as_guest(void)
{
return !hypervisor_is_type(X86_HYPER_NATIVE);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8261b6455747..983546d5f415 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1045,6 +1045,7 @@ static const struct intel_device_info dg2_info = {
.graphics.rel = 55,
.media.rel = 55,
PLATFORM(INTEL_DG2),
+ .has_guc_deprivilege = 1,
.has_64k_pages = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 93b251b25aba..88aad892a0fc 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -394,6 +394,14 @@ void intel_device_info_runtime_init(struct
drm_i915_private *dev_priv)
memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
}
+
+ /*
+* Early DG2 steppings don't have the GuC depriv feature. We can't
+* rely on the fuse on those platforms because the meaning of the fuse
+* bit is inverted on platforms that do have the feature.
+*/
+ if (IS_DG2_GRAPHICS_STEP(dev_priv, G10, STEP_A0, STEP_A1))
+ info->has_guc_deprivilege = 0;
}
void intel_driver_caps_print(const struct intel_driver_caps *caps,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 3699b1c539ea..abf1e103c558 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -134,6 +134,7 @@ enum intel_ppgtt_type {
func(has_reset_engine); \
func(has_global_mocs); \
func(has_gt_uc); \
+ func(has_guc_deprivilege); \
func(has_l3_dpf); \
func(has_llc); \
func(has_logical_ring_contexts); \
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index f06d21005106..322fb9eeb880 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -43,6 +43,7 @@
/* Default WOPCM size is 2MB from Gen11, 1MB on previous platforms */
#define GEN11_WOPCM_SIZE SZ_2M
#define GEN
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: make a gt sysfs group and move power management files
Hi Matt, > > The GT has its own properties and in sysfs they should be grouped > > in the 'gt/' directory. > > > > Create a 'gt/' directory in sysfs which will contain gt0...gtN > > directories related to each tile configured in the GPU. Move the > > power management files inside those directories. > > > > The previous power management files are kept in their original > > root directory to avoid breaking the ABI. They point to the tile > > '0' and a warning message is printed whenever accessed to. The > > deprecated interface needs for the CONFIG_SYSFS_DEPRECATED_V2 > > flag in order to be generated. > > > > The new sysfs structure will have a similar layout for the 4 tile > > case: > > > > /sys/.../card0 > > ├── gt > > │ ├── gt0 > > │ │ ├── id > > │ │ ├── rc6_enable > > │ │ ├── rc6_residency_ms > > │ │ ├── rps_act_freq_mhz > > │ │ ├── rps_boost_freq_mhz > > │ │ ├── rps_cur_freq_mhz > > │ │ ├── rps_max_freq_mhz > > │ │ ├── rps_min_freq_mhz > > │ │ ├── rps_RP0_freq_mhz > > │ │ ├── rps_RP1_freq_mhz > > │ │ └── rps_RPn_freq_mhz > > . . > > . . > > . . > > │ └── gt3 > > │ ├── id > > │ ├── rc6_enable > > │ ├── rc6_residency_ms > > │ ├── rps_act_freq_mhz > > │ ├── rps_boost_freq_mhz > > │ ├── rps_cur_freq_mhz > > │ ├── rps_max_freq_mhz > > │ ├── rps_min_freq_mhz > > │ ├── rps_RP0_freq_mhz > > │ ├── rps_RP1_freq_mhz > > │ └── rps_RPn_freq_mhz > > ├── gt_act_freq_mhz -+ > > ├── gt_boost_freq_mhz | > > ├── gt_cur_freq_mhz|Original interface > > ├── gt_max_freq_mhz+─-> kept as existing ABI; > > ├── gt_min_freq_mhz|it points to gt0/ > > ├── gt_RP0_freq_mhz| > > └── gt_RP1_freq_mhz| > > └── gt_RPn_freq_mhz -+ > > > > Signed-off-by: Andi Shyti > > Signed-off-by: Lucas De Marchi > > Cc: Matt Roper > > Cc: Sujaritha Sundaresan > > Cc: Tvrtko Ursulin > > Even though this is a pretty natural extension of sysfs entries we > already have in the driver today, it's still technically "new ABI" so I > think we need a link to the IGT changes that exercise it to make sure > it's working as expected. this patch should unblock the level0 sysman for DG1 and DG2, currently being upstreamed, and this will be handled by Sujaritha in the next days. Besides there a patch that is adding an hwmon interface to i915 that depends on this one. > Likewise we need a link to the real userspace consumer that is expecting > to use this (does some of the Level0 stuff use these knobs?). If this > is one of those really rare cases where we never expect any specific > userspace software to use the ABI, but the intent is instead to let > sysadmins turn the knobs manually with custom shell scripts or whatever, > that would need to be justified in the commit message too. I think with the first multitile platform coming (next series) this will be essential to control the power of multitile devices, either manually or with tools, otherwise we will be able only to access tile 0. I can add a note in the commit message. Andi
[Intel-gfx] [PATCH v5 i-g-t 13/15] lib/i915: Add helper for non-destructive engine property updates
From: John Harrison
Various tests want to configure engine properties such as pre-emption
timeout and heartbeat interval. Some don't bother to restore the
original values again afterwards. So, add a helper to make it easier
to do this.
v2: Fix for platforms with no pre-emption capability.
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
lib/i915/gem_engine_topology.c | 46 ++
lib/i915/gem_engine_topology.h | 9 +++
2 files changed, 55 insertions(+)
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index 729f42b0a..bd12d0bc9 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -488,6 +488,52 @@ int gem_engine_property_printf(int i915, const char
*engine, const char *attr,
return ret;
}
+/* Ensure fast hang detection */
+void gem_engine_properties_configure(int fd, struct gem_engine_properties
*params)
+{
+ int ret;
+ struct gem_engine_properties write = *params;
+
+ ret = gem_engine_property_scanf(fd, write.engine->name,
+ "heartbeat_interval_ms",
+ "%d", ¶ms->heartbeat_interval);
+ igt_assert_eq(ret, 1);
+
+ ret = gem_engine_property_printf(fd, write.engine->name,
+"heartbeat_interval_ms", "%d",
+write.heartbeat_interval);
+ igt_assert_lt(0, ret);
+
+ if (gem_scheduler_has_preemption(fd)) {
+ ret = gem_engine_property_scanf(fd, write.engine->name,
+ "preempt_timeout_ms",
+ "%d", ¶ms->preempt_timeout);
+ igt_assert_eq(ret, 1);
+
+ ret = gem_engine_property_printf(fd, write.engine->name,
+"preempt_timeout_ms", "%d",
+write.preempt_timeout);
+ igt_assert_lt(0, ret);
+ }
+}
+
+void gem_engine_properties_restore(int fd, const struct gem_engine_properties
*saved)
+{
+ int ret;
+
+ ret = gem_engine_property_printf(fd, saved->engine->name,
+"heartbeat_interval_ms", "%d",
+saved->heartbeat_interval);
+ igt_assert_lt(0, ret);
+
+ if (gem_scheduler_has_preemption(fd)) {
+ ret = gem_engine_property_printf(fd, saved->engine->name,
+"preempt_timeout_ms", "%d",
+saved->preempt_timeout);
+ igt_assert_lt(0, ret);
+ }
+}
+
uint32_t gem_engine_mmio_base(int i915, const char *engine)
{
unsigned int mmio = 0;
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index 4cfab560b..b413aa8ab 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -115,6 +115,15 @@ struct intel_execution_engine2
gem_eb_flags_to_engine(unsigned int flags);
((e__) = intel_get_current_physical_engine(&i__##e__)); \
intel_next_engine(&i__##e__))
+struct gem_engine_properties {
+ const struct intel_execution_engine2 *engine;
+ int preempt_timeout;
+ int heartbeat_interval;
+};
+
+void gem_engine_properties_configure(int fd, struct gem_engine_properties
*params);
+void gem_engine_properties_restore(int fd, const struct gem_engine_properties
*saved);
+
__attribute__((format(scanf, 4, 5)))
int gem_engine_property_scanf(int i915, const char *engine, const char *attr,
const char *fmt, ...);
--
2.25.1
[Intel-gfx] [PATCH v5 i-g-t 08/15] tests/i915/i915_hangman: Add alive-ness test after error capture
From: John Harrison
Added a an extra step to the i915_hangman tests to check that the
system is still alive after the hang and recovery. This submits a
simple batch to each engine which does a write to memory and checks
that the write occurred.
v2: Use _device_coherent instead of _wc for mapping memory to support
discrete boards.
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
tests/i915/i915_hangman.c | 59 +++
1 file changed, 59 insertions(+)
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 5a0c9497c..73a86ec9e 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -48,8 +48,57 @@
static int device = -1;
static int sysfs = -1;
+#define OFFSET_ALIVE 10
+
IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
+static void check_alive(void)
+{
+ const struct intel_execution_engine2 *engine;
+ const intel_ctx_t *ctx;
+ uint32_t scratch, *out;
+ int fd, i = 0;
+ uint64_t ahnd, scratch_addr;
+
+ fd = drm_open_driver(DRIVER_INTEL);
+ igt_require(gem_class_can_store_dword(fd, 0));
+
+ ctx = intel_ctx_create_all_physical(fd);
+ ahnd = get_reloc_ahnd(fd, ctx->id);
+ scratch = gem_create(fd, 4096);
+ scratch_addr = get_offset(ahnd, scratch, 4096, 0);
+ out = gem_mmap__device_coherent(fd, scratch, 0, 4096, PROT_WRITE |
PROT_READ);
+ gem_set_domain(fd, scratch,
+ I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+
+ for_each_physical_engine(fd, engine) {
+ igt_assert_eq_u32(out[i + OFFSET_ALIVE], 0);
+ i++;
+ }
+
+ i = 0;
+ for_each_ctx_engine(fd, ctx, engine) {
+ if (!gem_class_can_store_dword(fd, engine->class))
+ continue;
+
+ /* +OFFSET_ALIVE to ensure engine zero doesn't get a false
negative */
+ igt_store_word(fd, ahnd, ctx, engine, -1, scratch, scratch_addr,
+ i + OFFSET_ALIVE, i + OFFSET_ALIVE);
+ i++;
+ }
+
+ gem_set_domain(fd, scratch, I915_GEM_DOMAIN_GTT, 0);
+
+ while (i--)
+ igt_assert_eq_u32(out[i + OFFSET_ALIVE], i + OFFSET_ALIVE);
+
+ munmap(out, 4096);
+ gem_close(fd, scratch);
+ put_ahnd(ahnd);
+ intel_ctx_destroy(fd, ctx);
+ close(fd);
+}
+
static bool has_error_state(int dir)
{
bool result;
@@ -231,6 +280,8 @@ static void test_error_state_capture(const intel_ctx_t *ctx,
check_error_state(e->name, offset, batch);
munmap(batch, 4096);
put_ahnd(ahnd);
+
+ check_alive();
}
static void
@@ -289,6 +340,8 @@ test_engine_hang(const intel_ctx_t *ctx,
put_ahnd(ahndN);
}
put_ahnd(ahnd);
+
+ check_alive();
}
static int hang_count;
@@ -321,6 +374,8 @@ static void test_hang_detector(const intel_ctx_t *ctx,
/* Did it work? */
igt_assert(hang_count == 1);
+
+ check_alive();
}
/* This test covers the case where we end up in an uninitialised area of the
@@ -356,6 +411,8 @@ static void hangcheck_unterminated(const intel_ctx_t *ctx)
igt_force_gpu_reset(device);
igt_assert_f(0, "unterminated batch did not trigger a hang!\n");
}
+
+ check_alive();
}
static void do_tests(const char *name, const char *prefix,
@@ -433,6 +490,8 @@ igt_main
igt_assert(sysfs != -1);
igt_require(has_error_state(sysfs));
+
+ gem_require_mmap_device_coherent(device);
}
igt_describe("Basic error capture");
--
2.25.1
[Intel-gfx] [PATCH v5 i-g-t 10/15] tests/i915/i915_hangman: Run background task on all engines
From: John Harrison
As opposed to only on the non-target engines. This means that there is
some other workload present for the scheduler to switch between and so
detet the hang immediately.
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
tests/i915/i915_hangman.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 24087931c..a1aeeba6d 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -298,12 +298,14 @@ test_engine_hang(const intel_ctx_t *ctx,
igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
- /* Fill all the other engines with background load */
+ /*
+* Fill all engines with background load.
+* This verifies that independent engines are unaffected and gives
+* the target engine something to switch between so it notices the
+* hang.
+*/
num_ctx = 0;
for_each_ctx_engine(device, ctx, other) {
- if (other->flags == e->flags)
- continue;
-
local_ctx[num_ctx] = intel_ctx_create(device, &ctx->cfg);
ahndN = get_reloc_ahnd(device, local_ctx[num_ctx]->id);
spin = __igt_spin_new(device,
--
2.25.1
[Intel-gfx] [PATCH v5 i-g-t 07/15] lib/store: Refactor common store code into helper function
From: John Harrison
A lot of tests use almost identical code for creating a batch buffer
which does a single write to memory and another is about to be added.
Instead, move the most generic version into a common helper function.
Unfortunately, the other instances are all subtly different enough to
make it not so trivial to try to use the helper. It could be done but
it is unclear if it is worth the effort at this point. This patch
proves the concept, if people like it enough then it can be extended.
v2: Fix up object address vs store offset confusion (with help from
Zbigniew K).
v3: Cope with >32bit store_offset (review feedback from Matthew Brost).
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
lib/igt_store.c | 100
lib/igt_store.h | 12 +
lib/meson.build | 1 +
tests/i915/gem_exec_fence.c | 77 ++-
tests/i915/i915_hangman.c | 1 +
5 files changed, 119 insertions(+), 72 deletions(-)
create mode 100644 lib/igt_store.c
create mode 100644 lib/igt_store.h
diff --git a/lib/igt_store.c b/lib/igt_store.c
new file mode 100644
index 0..98c6c4fbd
--- /dev/null
+++ b/lib/igt_store.c
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "i915/gem_create.h"
+#include "igt_core.h"
+#include "drmtest.h"
+#include "igt_store.h"
+#include "intel_chipset.h"
+#include "intel_reg.h"
+#include "ioctl_wrappers.h"
+#include "lib/intel_allocator.h"
+
+/**
+ * SECTION:igt_store_word
+ * @short_description: Library for writing a value to memory
+ * @title: StoreWord
+ * @include: igt.h
+ *
+ * A lot of igt testcases need some mechanism for writing a value to memory
+ * as a test that a batch buffer has executed.
+ *
+ * NB: Requires master for STORE_DWORD on gen4/5.
+ */
+void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e,
+ int fence, uint32_t target_handle,
+ uint64_t target_gpu_addr,
+ uint64_t store_offset, uint32_t store_value)
+{
+ const int SCRATCH = 0;
+ const int BATCH = 1;
+ const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
+ struct drm_i915_gem_exec_object2 obj[2];
+ struct drm_i915_gem_relocation_entry reloc;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ uint32_t batch[16];
+ uint64_t bb_offset, delta;
+ int i;
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.buffer_count = ARRAY_SIZE(obj);
+ execbuf.flags = e->flags;
+ execbuf.rsvd1 = ctx->id;
+ if (fence != -1) {
+ execbuf.flags |= I915_EXEC_FENCE_IN;
+ execbuf.rsvd2 = fence;
+ }
+ if (gen < 6)
+ execbuf.flags |= I915_EXEC_SECURE;
+
+ memset(obj, 0, sizeof(obj));
+ obj[SCRATCH].handle = target_handle;
+
+ obj[BATCH].handle = gem_create(fd, 4096);
+ obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
+ obj[BATCH].relocation_count = !ahnd ? 1 : 0;
+ bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
+ memset(&reloc, 0, sizeof(reloc));
+
+ i = 0;
+ delta = sizeof(uint32_t) * store_offset;
+ if (!ahnd) {
+ reloc.target_handle = obj[SCRATCH].handle;
+ reloc.presumed_offset = -1;
+ reloc.offset = sizeof(uint32_t) * (i + 1);
+ reloc.delta = lower_32_bits(delta);
+ igt_assert_eq(upper_32_bits(delta), 0);
+ reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+ reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+ } else {
+ obj[SCRATCH].offset = target_gpu_addr;
+ obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
+ obj[BATCH].offset = bb_offset;
+ obj[BATCH].flags |= EXEC_OBJECT_PINNED;
+ }
+ batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+ if (gen >= 8) {
+ uint64_t addr = target_gpu_addr + delta;
+ batch[++i] = lower_32_bits(addr);
+ batch[++i] = upper_32_bits(addr);
+ } else if (gen >= 4) {
+ batch[++i] = 0;
+ batch[++i] = lower_32_bits(delta);
+ igt_assert_eq(upper_32_bits(delta), 0);
+ reloc.offset += sizeof(uint32_t);
+ } else {
+ batch[i]--;
+ batch[++i] = lower_32_bits(delta);
+ igt_assert_eq(upper_32_bits(delta), 0);
+ }
+ batch[++i] = store_value;
+ batch[++i] = MI_BATCH_BUFFER_END;
+ gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
+ gem_execbuf(fd, &execbuf);
+ gem_close(fd, obj[BATCH].handle);
+ put_offset(ahnd, obj[BATCH].handle);
+}
diff --git a/lib/igt_store.h b/lib/igt_store.h
new
[Intel-gfx] [PATCH v5 i-g-t 12/15] tests/i915/gem_exec_fence: Configure correct context
From: John Harrison
The update to use intel_ctx_t missed a line that configures the
context to allow hanging. Fix that.
Fixes: 09c36188b ("tests/i915/gem_exec_fence: Convert to intel_ctx_t (v2)")
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
tests/i915/gem_exec_fence.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index 196236b27..5e45d0518 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -3139,7 +3139,7 @@ igt_main
igt_hang_t hang;
igt_fixture {
- hang = igt_allow_hang(i915, 0, 0);
+ hang = igt_allow_hang(i915, ctx->id, 0);
intel_allocator_multiprocess_start();
}
--
2.25.1
[Intel-gfx] [PATCH v5 i-g-t 04/15] tests/i915/i915_hangman: Explicitly test per engine reset vs full GPU reset
From: John Harrison
Although the hangman test was ensuring that *some* reset functionality
was enabled, it did not differentiate what kind. The infrastructure
required to choose between per engine reset or full GT reset was
recently added. So update this test to use it as well.
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
tests/i915/i915_hangman.c | 76 +--
1 file changed, 49 insertions(+), 27 deletions(-)
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 280eac197..7b8390a6c 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -323,40 +323,26 @@ static void hangcheck_unterminated(const intel_ctx_t *ctx)
}
}
-igt_main
+static void do_tests(const char *name, const char *prefix,
+const intel_ctx_t *ctx)
{
const struct intel_execution_engine2 *e;
- const intel_ctx_t *ctx;
- igt_hang_t hang = {};
-
- igt_fixture {
- device = drm_open_driver(DRIVER_INTEL);
- igt_require_gem(device);
-
- ctx = intel_ctx_create_all_physical(device);
-
- hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE);
-
- sysfs = igt_sysfs_open(device);
- igt_assert(sysfs != -1);
-
- igt_require(has_error_state(sysfs));
- }
+ char buff[256];
- igt_describe("Basic error capture");
- igt_subtest("error-state-basic")
- test_error_state_basic();
-
- igt_describe("Per engine error capture");
- igt_subtest_with_dynamic("error-state-capture") {
+ snprintf(buff, sizeof(buff), "Per engine error capture (%s reset)",
name);
+ igt_describe(buff);
+ snprintf(buff, sizeof(buff), "%s-error-state-capture", prefix);
+ igt_subtest_with_dynamic(buff) {
for_each_ctx_engine(device, ctx, e) {
igt_dynamic_f("%s", e->name)
test_error_state_capture(ctx, e);
}
}
- igt_describe("Per engine hang recovery (spin)");
- igt_subtest_with_dynamic("engine-hang") {
+ snprintf(buff, sizeof(buff), "Per engine hang recovery (spin, %s
reset)", name);
+ igt_describe(buff);
+ snprintf(buff, sizeof(buff), "%s-engine-hang", prefix);
+ igt_subtest_with_dynamic(buff) {
int has_gpu_reset = 0;
struct drm_i915_getparam gp = {
.param = I915_PARAM_HAS_GPU_RESET,
@@ -374,8 +360,10 @@ igt_main
}
}
- igt_describe("Per engine hang recovery (invalid CS)");
- igt_subtest_with_dynamic("engine-error") {
+ snprintf(buff, sizeof(buff), "Per engine hang recovery (invalid CS, %s
reset)", name);
+ igt_describe(buff);
+ snprintf(buff, sizeof(buff), "%s-engine-error", prefix);
+ igt_subtest_with_dynamic(buff) {
int has_gpu_reset = 0;
struct drm_i915_getparam gp = {
.param = I915_PARAM_HAS_GPU_RESET,
@@ -391,11 +379,45 @@ igt_main
test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
}
}
+}
+
+igt_main
+{
+ const intel_ctx_t *ctx;
+ igt_hang_t hang = {};
+
+ igt_fixture {
+ device = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(device);
+
+ ctx = intel_ctx_create_all_physical(device);
+
+ hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE);
+
+ sysfs = igt_sysfs_open(device);
+ igt_assert(sysfs != -1);
+
+ igt_require(has_error_state(sysfs));
+ }
+
+ igt_describe("Basic error capture");
+ igt_subtest("error-state-basic")
+ test_error_state_basic();
igt_describe("Check that executing unintialised memory causes a hang");
igt_subtest("hangcheck-unterminated")
hangcheck_unterminated(ctx);
+ do_tests("GT", "gt", ctx);
+
+ igt_fixture {
+ igt_disallow_hang(device, hang);
+
+ hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE |
HANG_WANT_ENGINE_RESET);
+ }
+
+ do_tests("engine", "engine", ctx);
+
igt_fixture {
igt_disallow_hang(device, hang);
intel_ctx_destroy(device, ctx);
--
2.25.1
[Intel-gfx] [PATCH v5 i-g-t 03/15] tests/i915/i915_hangman: Update capture test to use engine structure
From: John Harrison
The capture test was still using old style ring_id and ring_name
(derived from the engine structure at the higher level). Update it to
just take the engine structure directly.
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
tests/i915/i915_hangman.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index f64b8819d..280eac197 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -207,8 +207,8 @@ static void check_error_state(const char
*expected_ring_name,
igt_assert(found);
}
-static void test_error_state_capture(const intel_ctx_t *ctx, unsigned ring_id,
-const char *ring_name)
+static void test_error_state_capture(const intel_ctx_t *ctx,
+const struct intel_execution_engine2 *e)
{
uint32_t *batch;
igt_hang_t hang;
@@ -217,7 +217,7 @@ static void test_error_state_capture(const intel_ctx_t
*ctx, unsigned ring_id,
clear_error_state();
- hang = igt_hang_ctx_with_ahnd(device, ahnd, ctx->id, ring_id,
+ hang = igt_hang_ctx_with_ahnd(device, ahnd, ctx->id, e->flags,
HANG_ALLOW_CAPTURE);
offset = hang.spin->obj[IGT_SPIN_BATCH].offset;
@@ -226,7 +226,7 @@ static void test_error_state_capture(const intel_ctx_t
*ctx, unsigned ring_id,
igt_post_hang_ring(device, hang);
- check_error_state(ring_name, offset, batch);
+ check_error_state(e->name, offset, batch);
munmap(batch, 4096);
put_ahnd(ahnd);
}
@@ -351,7 +351,7 @@ igt_main
igt_subtest_with_dynamic("error-state-capture") {
for_each_ctx_engine(device, ctx, e) {
igt_dynamic_f("%s", e->name)
- test_error_state_capture(ctx, e->flags,
e->name);
+ test_error_state_capture(ctx, e);
}
}
--
2.25.1
[Intel-gfx] [PATCH v5 i-g-t 15/15] tests/i915/gem_exec_capture: Restore engines
From: John Harrison
The test was updated some engine properties but not restoring them
afterwards. That would leave the system in a non-default state which
could potentially affect subsequent tests. Fix it by using the new
save/restore engine properties helper functions.
v2: Don't restore too soon in the 'pi' test.
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
tests/i915/gem_exec_capture.c | 42 +++
1 file changed, 33 insertions(+), 9 deletions(-)
diff --git a/tests/i915/gem_exec_capture.c b/tests/i915/gem_exec_capture.c
index 9beb36fc7..5b2482518 100644
--- a/tests/i915/gem_exec_capture.c
+++ b/tests/i915/gem_exec_capture.c
@@ -209,14 +209,21 @@ static int check_error_state(int dir, struct offset
*obj_offsets, int obj_count,
return blobs;
}
-static void configure_hangs(int fd, const struct intel_execution_engine2 *e,
int ctxt_id)
+static struct gem_engine_properties
+configure_hangs(int fd, const struct intel_execution_engine2 *e, int ctxt_id)
{
+ struct gem_engine_properties props;
+
/* Ensure fast hang detection */
- gem_engine_property_printf(fd, e->name, "preempt_timeout_ms", "%d",
250);
- gem_engine_property_printf(fd, e->name, "heartbeat_interval_ms", "%d",
500);
+ props.engine = e;
+ props.preempt_timeout = 250;
+ props.heartbeat_interval = 500;
+ gem_engine_properties_configure(fd, &props);
/* Allow engine based resets and disable banning */
igt_allow_hang(fd, ctxt_id, HANG_ALLOW_CAPTURE |
HANG_WANT_ENGINE_RESET);
+
+ return props;
}
static bool fence_busy(int fence)
@@ -256,8 +263,9 @@ static void __capture1(int fd, int dir, uint64_t ahnd,
const intel_ctx_t *ctx,
uint32_t *batch, *seqno;
struct offset offset;
int i, fence_out;
+ struct gem_engine_properties saved_engine;
- configure_hangs(fd, e, ctx->id);
+ saved_engine = configure_hangs(fd, e, ctx->id);
memset(obj, 0, sizeof(obj));
obj[SCRATCH].handle = gem_create_in_memory_regions(fd, 4096, region);
@@ -371,6 +379,8 @@ static void __capture1(int fd, int dir, uint64_t ahnd,
const intel_ctx_t *ctx,
gem_close(fd, obj[BATCH].handle);
gem_close(fd, obj[NOCAPTURE].handle);
gem_close(fd, obj[SCRATCH].handle);
+
+ gem_engine_properties_restore(fd, &saved_engine);
}
static void capture(int fd, int dir, const intel_ctx_t *ctx,
@@ -417,8 +427,9 @@ __captureN(int fd, int dir, uint64_t ahnd, const
intel_ctx_t *ctx,
uint32_t *batch, *seqno;
struct offset *offsets;
int i, fence_out;
+ struct gem_engine_properties saved_engine;
- configure_hangs(fd, e, ctx->id);
+ saved_engine = configure_hangs(fd, e, ctx->id);
offsets = calloc(count, sizeof(*offsets));
igt_assert(offsets);
@@ -559,10 +570,12 @@ __captureN(int fd, int dir, uint64_t ahnd, const
intel_ctx_t *ctx,
qsort(offsets, count, sizeof(*offsets), cmp);
igt_assert(offsets[0].addr <= offsets[count-1].addr);
+
+ gem_engine_properties_restore(fd, &saved_engine);
return offsets;
}
-#define find_first_available_engine(fd, ctx, e) \
+#define find_first_available_engine(fd, ctx, e, saved) \
do { \
ctx = intel_ctx_create_all_physical(fd); \
igt_assert(ctx); \
@@ -570,7 +583,7 @@ __captureN(int fd, int dir, uint64_t ahnd, const
intel_ctx_t *ctx,
for_each_if(gem_class_can_store_dword(fd, e->class)) \
break; \
igt_assert(e); \
- configure_hangs(fd, e, ctx->id); \
+ saved = configure_hangs(fd, e, ctx->id); \
} while(0)
static void many(int fd, int dir, uint64_t size, unsigned int flags)
@@ -580,8 +593,9 @@ static void many(int fd, int dir, uint64_t size, unsigned
int flags)
uint64_t ram, gtt, ahnd;
unsigned long count, blobs;
struct offset *offsets;
+ struct gem_engine_properties saved_engine;
- find_first_available_engine(fd, ctx, e);
+ find_first_available_engine(fd, ctx, e, saved_engine);
gtt = gem_aperture_size(fd) / size;
ram = (intel_get_avail_ram_mb() << 20) / size;
@@ -602,6 +616,8 @@ static void many(int fd, int dir, uint64_t size, unsigned
int flags)
free(offsets);
put_ahnd(ahnd);
+
+ gem_engine_properties_restore(fd, &saved_engine);
}
static void prioinv(int fd, int dir, const intel_ctx_t *ctx,
@@ -617,6 +633,7 @@ static void prioinv(int fd, int dir, const intel_ctx_t *ctx,
.flags = e->flags,
.rsvd1 = ctx->id,
};
+ struct gem_engine_properties saved_engine;
int64_t timeout = NSEC_PER_SEC; /* 1s, feeling generous, blame debug */
uint64_t ram, gtt, ahnd, size = 4 << 20;
unsigned long count;
@@ -640,6 +657,8 @@ static void prioinv(int fd, int dir, const intel_ctx_
[Intel-gfx] [PATCH v5 i-g-t 14/15] tests/i915/i915_hangman: Configure engine properties for quicker hangs
From: John Harrison
Some platforms have very long timeouts configured for some engines.
Some have them disabled completely. That makes for a very slow (or
broken) hangman test. So explicitly configure the engines to have
reasonable settings first.
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
tests/i915/i915_hangman.c | 16
1 file changed, 16 insertions(+)
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index e661b8ad0..23055c271 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -496,8 +496,12 @@ igt_main
{
const intel_ctx_t *ctx;
igt_hang_t hang = {};
+ struct gem_engine_properties saved_params[GEM_MAX_ENGINES];
+ int num_engines = 0;
igt_fixture {
+ const struct intel_execution_engine2 *e;
+
device = drm_open_driver(DRIVER_INTEL);
igt_require_gem(device);
@@ -511,6 +515,13 @@ igt_main
igt_require(has_error_state(sysfs));
gem_require_mmap_device_coherent(device);
+
+ for_each_physical_engine(device, e) {
+ saved_params[num_engines].engine = e;
+ saved_params[num_engines].preempt_timeout = 500;
+ saved_params[num_engines].heartbeat_interval = 1000;
+ gem_engine_properties_configure(device, saved_params +
num_engines++);
+ }
}
igt_describe("Basic error capture");
@@ -542,6 +553,11 @@ igt_main
do_tests("engine", "engine", ctx);
igt_fixture {
+ int i;
+
+ for (i = 0; i < num_engines; i++)
+ gem_engine_properties_restore(device, saved_params + i);
+
igt_disallow_hang(device, hang);
intel_ctx_destroy(device, ctx);
close(device);
--
2.25.1
[Intel-gfx] [PATCH v5 i-g-t 01/15] tests/i915/i915_hangman: Add descriptions
From: John Harrison
Added descriptions of the various sub-tests and the test as a whole.
v2: Added missing linefeed (spotted by Petri)
Signed-off-by: John Harrison
Reviewed-by: Petri Latvala
---
tests/i915/i915_hangman.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 4c18c22db..b9c4d9983 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -46,6 +46,8 @@
static int device = -1;
static int sysfs = -1;
+IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
+
static bool has_error_state(int dir)
{
bool result;
@@ -315,9 +317,9 @@ static void hangcheck_unterminated(void)
gem_execbuf(device, &execbuf);
if (gem_wait(device, handle, &timeout_ns) != 0) {
- /* need to manually trigger an hang to clean before failing */
+ /* need to manually trigger a hang to clean before failing */
igt_force_gpu_reset(device);
- igt_assert_f(0, "unterminated batch did not trigger an hang!");
+ igt_assert_f(0, "unterminated batch did not trigger a hang!\n");
}
}
@@ -341,9 +343,11 @@ igt_main
igt_require(has_error_state(sysfs));
}
+ igt_describe("Basic error capture");
igt_subtest("error-state-basic")
test_error_state_basic();
+ igt_describe("Per engine error capture");
igt_subtest_with_dynamic("error-state-capture") {
for_each_ctx_engine(device, ctx, e) {
igt_dynamic_f("%s", e->name)
@@ -351,6 +355,7 @@ igt_main
}
}
+ igt_describe("Per engine hang recovery (spin)");
igt_subtest_with_dynamic("engine-hang") {
int has_gpu_reset = 0;
struct drm_i915_getparam gp = {
@@ -369,6 +374,7 @@ igt_main
}
}
+ igt_describe("Per engine hang recovery (invalid CS)");
igt_subtest_with_dynamic("engine-error") {
int has_gpu_reset = 0;
struct drm_i915_getparam gp = {
@@ -386,6 +392,7 @@ igt_main
}
}
+ igt_describe("Check that executing unintialised memory causes a hang");
igt_subtest("hangcheck-unterminated")
hangcheck_unterminated();
--
2.25.1
[Intel-gfx] [PATCH v5 i-g-t 11/15] tests/i915/i915_hangman: Don't let background contexts cause a ban
From: John Harrison
The global context used by all the subtests for causing hangs is
marked as unbannable. However, some of the subtests set background
spinners running on all engines using a freshly created context. If
there is a test failure for any reason, all of those spinners can be
killed off as hanging contexts. On systems with lots of engines, that
can result in the test being banned from creating any new contexts.
So make the spinner contexts unbannable as well. That way if one
subtest fails it won't necessarily bring down all subsequent subtests.
v2: Simplify anti-banning code (review feedback from Matthew Brost).
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
tests/i915/i915_hangman.c | 12
1 file changed, 12 insertions(+)
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index a1aeeba6d..e661b8ad0 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -284,6 +284,17 @@ static void test_error_state_capture(const intel_ctx_t
*ctx,
check_alive();
}
+static void context_unban(int fd, unsigned ctx)
+{
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = ctx,
+ .param = I915_CONTEXT_PARAM_BANNABLE,
+ .value = 0,
+ };
+
+ gem_context_set_param(fd, ¶m);
+}
+
static void
test_engine_hang(const intel_ctx_t *ctx,
const struct intel_execution_engine2 *e, unsigned int flags)
@@ -307,6 +318,7 @@ test_engine_hang(const intel_ctx_t *ctx,
num_ctx = 0;
for_each_ctx_engine(device, ctx, other) {
local_ctx[num_ctx] = intel_ctx_create(device, &ctx->cfg);
+ context_unban(device, local_ctx[num_ctx]->id);
ahndN = get_reloc_ahnd(device, local_ctx[num_ctx]->id);
spin = __igt_spin_new(device,
.ahnd = ahndN,
--
2.25.1
[Intel-gfx] [PATCH v5 i-g-t 06/15] tests/i915/i915_hangman: Use the correct context in hangcheck_unterminated
From: John Harrison
The hangman framework sets up a context that is valid for all engines
and has things like banning disabled. The 'unterminated' test then
ignores it and uses the default context. Fix that.
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
tests/i915/i915_hangman.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 354769f39..6656b3fcd 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -347,6 +347,7 @@ static void hangcheck_unterminated(const intel_ctx_t *ctx)
memset(&execbuf, 0, sizeof(execbuf));
execbuf.buffers_ptr = (uintptr_t)&gem_exec;
execbuf.buffer_count = 1;
+ execbuf.rsvd1 = ctx->id;
gem_execbuf(device, &execbuf);
if (gem_wait(device, handle, &timeout_ns) != 0) {
--
2.25.1
[Intel-gfx] [PATCH v5 i-g-t 05/15] tests/i915/i915_hangman: Add uevent test & fix detector
From: John Harrison
Some of the IGT framework relies on receving a uevent when a hang
occurs. So add a test that this actually works.
While testing this, noticed that hangs could sometimes be missed
because the uevent was (presumably) still in flight by the time the
handler was de-registered. So add an extra delay during cleanup to
give the uevent chance to arrive.
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
lib/igt_aux.c | 7 +++
tests/i915/i915_hangman.c | 43 +++
2 files changed, 50 insertions(+)
diff --git a/lib/igt_aux.c b/lib/igt_aux.c
index c247a1aa4..03cc38c93 100644
--- a/lib/igt_aux.c
+++ b/lib/igt_aux.c
@@ -523,6 +523,13 @@ void igt_fork_hang_detector(int fd)
void igt_stop_hang_detector(void)
{
+ /*
+* Give the uevent time to arrive. No sleep at all misses about 20% of
+* hangs (at least, in the i915_hangman/detector test). A sleep of 1ms
+* seems to miss about 2%, 10ms loses <1%, so 100ms should be safe.
+*/
+ usleep(100 * 1000);
+
igt_stop_helper(&hang_detector);
}
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 7b8390a6c..354769f39 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -31,6 +31,7 @@
#include
#include
#include
+#include
#include "i915/gem.h"
#include "i915/gem_create.h"
@@ -289,6 +290,38 @@ test_engine_hang(const intel_ctx_t *ctx,
put_ahnd(ahnd);
}
+static int hang_count;
+
+static void sig_io(int sig)
+{
+ hang_count++;
+}
+
+static void test_hang_detector(const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e)
+{
+ igt_hang_t hang;
+ uint64_t ahnd = get_reloc_ahnd(device, ctx->id);
+
+ hang_count = 0;
+
+ igt_fork_hang_detector(device);
+
+ /* Steal the signal handler */
+ signal(SIGIO, sig_io);
+
+ /* Make a hang... */
+ hang = igt_hang_ctx_with_ahnd(device, ahnd, ctx->id, e->flags, 0);
+
+ igt_post_hang_ring(device, hang);
+ put_ahnd(ahnd);
+
+ igt_stop_hang_detector();
+
+ /* Did it work? */
+ igt_assert(hang_count == 1);
+}
+
/* This test covers the case where we end up in an uninitialised area of the
* ppgtt and keep executing through it. This is particularly relevant if 48b
* ppgtt is enabled because the ppgtt is massively bigger compared to the 32b
@@ -408,6 +441,16 @@ igt_main
igt_subtest("hangcheck-unterminated")
hangcheck_unterminated(ctx);
+ igt_describe("Check that hang detector works");
+ igt_subtest_with_dynamic("detector") {
+ const struct intel_execution_engine2 *e;
+
+ for_each_ctx_engine(device, ctx, e) {
+ igt_dynamic_f("%s", e->name)
+ test_hang_detector(ctx, e);
+ }
+ }
+
do_tests("GT", "gt", ctx);
igt_fixture {
--
2.25.1
[Intel-gfx] [PATCH v5 i-g-t 09/15] tests/i915/i915_hangman: Remove reliance on context persistance
From: John Harrison
The hang test was relying on context persitence for no particular
reason. That is, it would set a bunch of background spinners running
then immediately destroy the active contexts but expect the spinners
to keep spinning. With the current implementation of context
persistence in i915, that means that super high priority pings are
sent to each engine at the start of the test. Depending upon the
timing and platform, one of those unexpected pings could cause test
failures.
There is no need to require context persitence in this test. So change
to managing the contexts cleanly and only destroying them when they
are no longer in use.
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
tests/i915/i915_hangman.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 73a86ec9e..24087931c 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -289,27 +289,29 @@ test_engine_hang(const intel_ctx_t *ctx,
const struct intel_execution_engine2 *e, unsigned int flags)
{
const struct intel_execution_engine2 *other;
- const intel_ctx_t *tmp_ctx;
+ const intel_ctx_t *local_ctx[GEM_MAX_ENGINES];
igt_spin_t *spin, *next;
IGT_LIST_HEAD(list);
uint64_t ahnd = get_reloc_ahnd(device, ctx->id), ahndN;
+ int num_ctx;
igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
/* Fill all the other engines with background load */
+ num_ctx = 0;
for_each_ctx_engine(device, ctx, other) {
if (other->flags == e->flags)
continue;
- tmp_ctx = intel_ctx_create(device, &ctx->cfg);
- ahndN = get_reloc_ahnd(device, tmp_ctx->id);
+ local_ctx[num_ctx] = intel_ctx_create(device, &ctx->cfg);
+ ahndN = get_reloc_ahnd(device, local_ctx[num_ctx]->id);
spin = __igt_spin_new(device,
.ahnd = ahndN,
- .ctx = tmp_ctx,
+ .ctx = local_ctx[num_ctx],
.engine = other->flags,
.flags = IGT_SPIN_FENCE_OUT);
- intel_ctx_destroy(device, tmp_ctx);
+ num_ctx++;
igt_list_move(&spin->link, &list);
}
@@ -339,7 +341,10 @@ test_engine_hang(const intel_ctx_t *ctx,
igt_spin_free(device, spin);
put_ahnd(ahndN);
}
+
put_ahnd(ahnd);
+ while (num_ctx)
+ intel_ctx_destroy(device, local_ctx[--num_ctx]);
check_alive();
}
--
2.25.1
[Intel-gfx] [PATCH v5 i-g-t 00/15] Fixes for i915_hangman, gem_exec_capture and gem_exec_fence
From: John Harrison Fix a bunch of issues with i915_hangman and gem_exec_capture with the ultimate aim of making them pass on GuC enabled platforms. v2: Fixes to the store code. Add engine properties management. v3: Fix for platforms without pre-emption. v4: Simplify anti-ban code, support >32bit store offsets and fix memory mapping on discrete platforms. v5: Fix for failure on 'pi' test. Update patch set subject. Signed-off-by: John Harrison John Harrison (15): tests/i915/i915_hangman: Add descriptions lib/hang: Fix igt_require_hang_ring to work with all engines tests/i915/i915_hangman: Update capture test to use engine structure tests/i915/i915_hangman: Explicitly test per engine reset vs full GPU reset tests/i915/i915_hangman: Add uevent test & fix detector tests/i915/i915_hangman: Use the correct context in hangcheck_unterminated lib/store: Refactor common store code into helper function tests/i915/i915_hangman: Add alive-ness test after error capture tests/i915/i915_hangman: Remove reliance on context persistance tests/i915/i915_hangman: Run background task on all engines tests/i915/i915_hangman: Don't let background contexts cause a ban tests/i915/gem_exec_fence: Configure correct context lib/i915: Add helper for non-destructive engine property updates tests/i915/i915_hangman: Configure engine properties for quicker hangs tests/i915/gem_exec_capture: Restore engines lib/i915/gem_engine_topology.c | 46 ++ lib/i915/gem_engine_topology.h | 9 ++ lib/igt_aux.c | 7 + lib/igt_gt.c | 6 +- lib/igt_gt.h | 2 +- lib/igt_store.c| 100 + lib/igt_store.h| 12 ++ lib/meson.build| 1 + tests/i915/gem_exec_capture.c | 42 -- tests/i915/gem_exec_fence.c| 79 +-- tests/i915/i915_hangman.c | 252 +++-- 11 files changed, 428 insertions(+), 128 deletions(-) create mode 100644 lib/igt_store.c create mode 100644 lib/igt_store.h -- 2.25.1
[Intel-gfx] [PATCH v5 i-g-t 02/15] lib/hang: Fix igt_require_hang_ring to work with all engines
From: John Harrison
The above function was checking for valid rings via the old interface.
The new scheme is to check for engines on contexts as there are now
more engines than could be supported.
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
lib/igt_gt.c | 6 +++---
lib/igt_gt.h | 2 +-
tests/i915/i915_hangman.c | 6 +++---
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index 7c7df95ee..50da512f2 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -122,12 +122,12 @@ static void eat_error_state(int dev)
* to be done under hang injection.
* Default: false
*/
-void igt_require_hang_ring(int fd, int ring)
+void igt_require_hang_ring(int fd, uint32_t ctx, int ring)
{
if (!igt_check_boolean_env_var("IGT_HANG", true))
igt_skip("hang injection disabled by user [IGT_HANG=0]\n");
- gem_require_ring(fd, ring);
+igt_require(gem_context_has_engine(fd, ctx, ring));
gem_context_require_bannable(fd);
if (!igt_check_boolean_env_var("IGT_HANG_WITHOUT_RESET", false))
igt_require(has_gpu_reset(fd));
@@ -290,7 +290,7 @@ static igt_hang_t __igt_hang_ctx(int fd, uint64_t ahnd,
uint32_t ctx, int ring,
igt_spin_t *spin;
unsigned ban;
- igt_require_hang_ring(fd, ring);
+ igt_require_hang_ring(fd, ctx, ring);
/* check if non-default ctx submission is allowed */
igt_require(ctx == 0 || has_ctx_exec(fd, ring, ctx));
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index c5059817b..3d10349e4 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -31,7 +31,7 @@
#include "i915/i915_drm_local.h"
#include "i915_drm.h"
-void igt_require_hang_ring(int fd, int ring);
+void igt_require_hang_ring(int fd, uint32_t ctx, int ring);
typedef struct igt_hang {
igt_spin_t *spin;
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index b9c4d9983..f64b8819d 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -295,7 +295,7 @@ test_engine_hang(const intel_ctx_t *ctx,
* case and it takes a lot more time to wrap, so the acthd can potentially keep
* increasing for a long time
*/
-static void hangcheck_unterminated(void)
+static void hangcheck_unterminated(const intel_ctx_t *ctx)
{
/* timeout needs to be greater than ~5*hangcheck */
int64_t timeout_ns = 100ull * NSEC_PER_SEC; /* 100 seconds */
@@ -304,7 +304,7 @@ static void hangcheck_unterminated(void)
uint32_t handle;
igt_require(gem_uses_full_ppgtt(device));
- igt_require_hang_ring(device, 0);
+ igt_require_hang_ring(device, ctx->id, 0);
handle = gem_create(device, 4096);
@@ -394,7 +394,7 @@ igt_main
igt_describe("Check that executing unintialised memory causes a hang");
igt_subtest("hangcheck-unterminated")
- hangcheck_unterminated();
+ hangcheck_unterminated(ctx);
igt_fixture {
igt_disallow_hang(device, hang);
--
2.25.1
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Prepare for multiple GTs
Hi Matt,
[...]
> > -int intel_uncore_setup_mmio(struct intel_uncore *uncore)
> > +int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t
> > phys_addr)
> > {
> > struct drm_i915_private *i915 = uncore->i915;
> > - struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > - int mmio_bar;
> > int mmio_size;
> >
> > - mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
> > /*
> > * Before gen4, the registers and the GTT are behind different BARs.
> > * However, from gen4 onwards, the registers and the GTT are shared
> > @@ -2044,7 +2041,7 @@ int intel_uncore_setup_mmio(struct intel_uncore
> > *uncore)
> > else
> > mmio_size = 2 * 1024 * 1024;
> >
> > - uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
> > + uncore->regs = ioremap(phys_addr, mmio_size);
>
> Is there a specific reason we switch to ioremap() instead of
> pci_iomap_range()? I.e., we could pass 'phys_offset' rather than
> 'phys_addr' and call
>
> pci_iomap_range(pdev, mmio_bar, phys_offset, mmio_size);
>
> Not that it really matters too much either way as far as I can see;
> ioremap()/iounmap() should work fine too.
this was originally changed by Abdiel (I think) and I left as it
is as I tried to change as less as I could from the original
work.
> Reviewed-by: Matt Roper
Thank you!
Andi
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: make a gt sysfs group and move power management files
On Thu, Jan 13, 2022 at 12:20:31AM +0200, Andi Shyti wrote: > The GT has its own properties and in sysfs they should be grouped > in the 'gt/' directory. > > Create a 'gt/' directory in sysfs which will contain gt0...gtN > directories related to each tile configured in the GPU. Move the > power management files inside those directories. > > The previous power management files are kept in their original > root directory to avoid breaking the ABI. They point to the tile > '0' and a warning message is printed whenever accessed to. The > deprecated interface needs for the CONFIG_SYSFS_DEPRECATED_V2 > flag in order to be generated. > > The new sysfs structure will have a similar layout for the 4 tile > case: > > /sys/.../card0 > ├── gt > │ ├── gt0 > │ │ ├── id > │ │ ├── rc6_enable > │ │ ├── rc6_residency_ms > │ │ ├── rps_act_freq_mhz > │ │ ├── rps_boost_freq_mhz > │ │ ├── rps_cur_freq_mhz > │ │ ├── rps_max_freq_mhz > │ │ ├── rps_min_freq_mhz > │ │ ├── rps_RP0_freq_mhz > │ │ ├── rps_RP1_freq_mhz > │ │ └── rps_RPn_freq_mhz >. . >. . >. . > │ └── gt3 > │ ├── id > │ ├── rc6_enable > │ ├── rc6_residency_ms > │ ├── rps_act_freq_mhz > │ ├── rps_boost_freq_mhz > │ ├── rps_cur_freq_mhz > │ ├── rps_max_freq_mhz > │ ├── rps_min_freq_mhz > │ ├── rps_RP0_freq_mhz > │ ├── rps_RP1_freq_mhz > │ └── rps_RPn_freq_mhz > ├── gt_act_freq_mhz -+ > ├── gt_boost_freq_mhz | > ├── gt_cur_freq_mhz|Original interface > ├── gt_max_freq_mhz+─-> kept as existing ABI; > ├── gt_min_freq_mhz|it points to gt0/ > ├── gt_RP0_freq_mhz| > └── gt_RP1_freq_mhz| > └── gt_RPn_freq_mhz -+ > > Signed-off-by: Andi Shyti > Signed-off-by: Lucas De Marchi > Cc: Matt Roper > Cc: Sujaritha Sundaresan > Cc: Tvrtko Ursulin Even though this is a pretty natural extension of sysfs entries we already have in the driver today, it's still technically "new ABI" so I think we need a link to the IGT changes that exercise it to make sure it's working as expected. Likewise we need a link to the real userspace consumer that is expecting to use this (does some of the Level0 stuff use these knobs?). If this is one of those really rare cases where we never expect any specific userspace software to use the ABI, but the intent is instead to let sysadmins turn the knobs manually with custom shell scripts or whatever, that would need to be justified in the commit message too. Matt > --- > drivers/gpu/drm/i915/Makefile | 4 +- > drivers/gpu/drm/i915/gt/intel_gt.c| 2 + > drivers/gpu/drm/i915/gt/sysfs_gt.c| 126 + > drivers/gpu/drm/i915/gt/sysfs_gt.h| 44 +++ > drivers/gpu/drm/i915/gt/sysfs_gt_pm.c | 393 ++ > drivers/gpu/drm/i915/gt/sysfs_gt_pm.h | 16 ++ > drivers/gpu/drm/i915/i915_drv.h | 2 + > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/i915_sysfs.c | 315 + > drivers/gpu/drm/i915/i915_sysfs.h | 3 + > 10 files changed, 600 insertions(+), 306 deletions(-) > create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt.c > create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt.h > create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt_pm.c > create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt_pm.h > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index aa86ac33effc..5fd203c626fc 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -121,7 +121,9 @@ gt-y += \ > gt/intel_timeline.o \ > gt/intel_workarounds.o \ > gt/shmem_utils.o \ > - gt/sysfs_engines.o > + gt/sysfs_engines.o \ > + gt/sysfs_gt.o \ > + gt/sysfs_gt_pm.o > # autogenerated null render state > gt-y += \ > gt/gen6_renderstate.o \ > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c > b/drivers/gpu/drm/i915/gt/intel_gt.c > index 17927da9e23e..2584c51c1c14 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -25,6 +25,7 @@ > #include "intel_rps.h" > #include "intel_uncore.h" > #include "shmem_utils.h" > +#include "sysfs_gt.h" > #include "pxp/intel_pxp.h" > > static void > @@ -453,6 +454,7 @@ void intel_gt_driver_register(struct intel_gt *gt) > intel_rps_driver_register(>->rps); > > intel_gt_debugfs_register(gt); > + intel_gt_sysfs_register(gt); > } > > static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size) > diff --git a/drivers/gpu/drm/i915/gt/sysfs_gt.c > b/drivers/gpu/drm/i915/gt/sysfs_gt.c > new file mode 100644 > index ..
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Prepare for multiple GTs
On Thu, Jan 13, 2022 at 12:20:30AM +0200, Andi Shyti wrote:
> From: Tvrtko Ursulin
>
> On a multi-tile platform, each tile has its own registers + GGTT
> space, and BAR 0 is extended to cover all of them.
>
> Up to four gts are supported in i915->gt[], with slot zero
> shadowing the existing i915->gt0 to enable source compatibility
> with legacy driver paths. A for_each_gt macro is added to iterate
> over the GTs and will be used by upcoming patches that convert
> various parts of the driver to be multi-gt aware.
>
> Only the primary/root tile is initialized for now; the other
> tiles will be detected and plugged in by future patches once the
> necessary infrastructure is in place to handle them.
>
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Matt Roper
> Signed-off-by: Andi Shyti
> Cc: Daniele Ceraolo Spurio
> Cc: Joonas Lahtinen
> Cc: Matthew Auld
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c| 139 --
> drivers/gpu/drm/i915/gt/intel_gt.h| 14 +-
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +
> drivers/gpu/drm/i915/i915_driver.c| 29 ++--
> drivers/gpu/drm/i915/i915_drv.h | 6 +
> drivers/gpu/drm/i915/intel_memory_region.h| 3 +
> drivers/gpu/drm/i915/intel_uncore.c | 12 +-
> drivers/gpu/drm/i915/intel_uncore.h | 3 +-
> .../gpu/drm/i915/selftests/mock_gem_device.c | 5 +-
> 10 files changed, 185 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 622cdfed8a8b..17927da9e23e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -27,7 +27,8 @@
> #include "shmem_utils.h"
> #include "pxp/intel_pxp.h"
>
> -void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private
> *i915)
> +static void
> +__intel_gt_init_early(struct intel_gt *gt)
> {
> spin_lock_init(>->irq_lock);
>
> @@ -47,19 +48,27 @@ void __intel_gt_init_early(struct intel_gt *gt, struct
> drm_i915_private *i915)
> intel_rps_init_early(>->rps);
> }
>
> +/* Preliminary initialization of Tile 0 */
> void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> {
> gt->i915 = i915;
> gt->uncore = &i915->uncore;
> +
> + __intel_gt_init_early(gt);
> }
>
> -int intel_gt_probe_lmem(struct intel_gt *gt)
> +static int intel_gt_probe_lmem(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> + unsigned int instance = gt->info.id;
> struct intel_memory_region *mem;
> int id;
> int err;
>
> + id = INTEL_REGION_LMEM + instance;
> + if (drm_WARN_ON(&i915->drm, id >= INTEL_REGION_STOLEN_SMEM))
> + return -ENODEV;
> +
> mem = intel_gt_setup_lmem(gt);
> if (mem == ERR_PTR(-ENODEV))
> mem = intel_gt_setup_fake_lmem(gt);
> @@ -74,9 +83,8 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
> return err;
> }
>
> - id = INTEL_REGION_LMEM;
> -
> mem->id = id;
> + mem->instance = instance;
>
> intel_memory_region_set_name(mem, "local%u", mem->instance);
>
> @@ -791,16 +799,21 @@ void intel_gt_driver_release(struct intel_gt *gt)
> intel_gt_fini_buffer_pool(gt);
> }
>
> -void intel_gt_driver_late_release(struct intel_gt *gt)
> +void intel_gt_driver_late_release(struct drm_i915_private *i915)
> {
> + struct intel_gt *gt;
> + unsigned int id;
> +
> /* We need to wait for inflight RCU frees to release their grip */
> rcu_barrier();
>
> - intel_uc_driver_late_release(>->uc);
> - intel_gt_fini_requests(gt);
> - intel_gt_fini_reset(gt);
> - intel_gt_fini_timelines(gt);
> - intel_engines_free(gt);
> + for_each_gt(gt, i915, id) {
> + intel_uc_driver_late_release(>->uc);
> + intel_gt_fini_requests(gt);
> + intel_gt_fini_reset(gt);
> + intel_gt_fini_timelines(gt);
> + intel_engines_free(gt);
> + }
> }
>
> /**
> @@ -909,6 +922,112 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt,
> i915_reg_t reg)
> return intel_uncore_read_fw(gt->uncore, reg);
> }
>
> +static int
> +intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
> +{
> + struct drm_i915_private *i915 = gt->i915;
> + unsigned int id = gt->info.id;
> + int ret;
> +
> + if (id) {
> + struct intel_uncore_mmio_debug *mmio_debug;
> + struct intel_uncore *uncore;
> +
> + /* For multi-tile platforms BAR0 must have at least 16MB per
> tile */
> + if (GEM_WARN_ON(pci_resource_len(to_pci_dev(i915->drm.dev), 0) <
> + (id + 1) * SZ_16M))
> + return -EINVAL;
> +
> + uncore = kzalloc(sizeof(*unco
Re: [Intel-gfx] [igt-dev] [PATCH v4 i-g-t 04/15] tests/i915/i915_hangman: Explicitly test per engine reset vs full GPU reset
On Thu, Jan 13, 2022 at 03:51:07PM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Although the hangman test was ensuring that *some* reset functionality
> was enabled, it did not differentiate what kind. The infrastructure
> required to choose between per engine reset or full GT reset was
> recently added. So update this test to use it as well.
>
> Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
> ---
> tests/i915/i915_hangman.c | 76 +--
> 1 file changed, 49 insertions(+), 27 deletions(-)
>
> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> index 280eac197..7b8390a6c 100644
> --- a/tests/i915/i915_hangman.c
> +++ b/tests/i915/i915_hangman.c
> @@ -323,40 +323,26 @@ static void hangcheck_unterminated(const intel_ctx_t
> *ctx)
> }
> }
>
> -igt_main
> +static void do_tests(const char *name, const char *prefix,
> + const intel_ctx_t *ctx)
> {
> const struct intel_execution_engine2 *e;
> - const intel_ctx_t *ctx;
> - igt_hang_t hang = {};
> -
> - igt_fixture {
> - device = drm_open_driver(DRIVER_INTEL);
> - igt_require_gem(device);
> -
> - ctx = intel_ctx_create_all_physical(device);
> -
> - hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE);
> -
> - sysfs = igt_sysfs_open(device);
> - igt_assert(sysfs != -1);
> -
> - igt_require(has_error_state(sysfs));
> - }
> + char buff[256];
>
> - igt_describe("Basic error capture");
> - igt_subtest("error-state-basic")
> - test_error_state_basic();
> -
> - igt_describe("Per engine error capture");
> - igt_subtest_with_dynamic("error-state-capture") {
> + snprintf(buff, sizeof(buff), "Per engine error capture (%s reset)",
> name);
> + igt_describe(buff);
> + snprintf(buff, sizeof(buff), "%s-error-state-capture", prefix);
> + igt_subtest_with_dynamic(buff) {
> for_each_ctx_engine(device, ctx, e) {
> igt_dynamic_f("%s", e->name)
> test_error_state_capture(ctx, e);
> }
> }
>
> - igt_describe("Per engine hang recovery (spin)");
> - igt_subtest_with_dynamic("engine-hang") {
> + snprintf(buff, sizeof(buff), "Per engine hang recovery (spin, %s
> reset)", name);
> + igt_describe(buff);
> + snprintf(buff, sizeof(buff), "%s-engine-hang", prefix);
> + igt_subtest_with_dynamic(buff) {
> int has_gpu_reset = 0;
> struct drm_i915_getparam gp = {
> .param = I915_PARAM_HAS_GPU_RESET,
> @@ -374,8 +360,10 @@ igt_main
> }
> }
>
> - igt_describe("Per engine hang recovery (invalid CS)");
> - igt_subtest_with_dynamic("engine-error") {
> + snprintf(buff, sizeof(buff), "Per engine hang recovery (invalid CS, %s
> reset)", name);
> + igt_describe(buff);
> + snprintf(buff, sizeof(buff), "%s-engine-error", prefix);
> + igt_subtest_with_dynamic(buff) {
> int has_gpu_reset = 0;
> struct drm_i915_getparam gp = {
> .param = I915_PARAM_HAS_GPU_RESET,
> @@ -391,11 +379,45 @@ igt_main
> test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
> }
> }
> +}
> +
> +igt_main
> +{
> + const intel_ctx_t *ctx;
> + igt_hang_t hang = {};
> +
> + igt_fixture {
> + device = drm_open_driver(DRIVER_INTEL);
> + igt_require_gem(device);
> +
> + ctx = intel_ctx_create_all_physical(device);
> +
> + hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE);
> +
> + sysfs = igt_sysfs_open(device);
> + igt_assert(sysfs != -1);
> +
> + igt_require(has_error_state(sysfs));
> + }
> +
> + igt_describe("Basic error capture");
> + igt_subtest("error-state-basic")
> + test_error_state_basic();
>
> igt_describe("Check that executing unintialised memory causes a hang");
> igt_subtest("hangcheck-unterminated")
> hangcheck_unterminated(ctx);
>
> + do_tests("GT", "gt", ctx);
> +
> + igt_fixture {
> + igt_disallow_hang(device, hang);
> +
> + hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE |
> HANG_WANT_ENGINE_RESET);
> + }
> +
> + do_tests("engine", "engine", ctx);
> +
> igt_fixture {
> igt_disallow_hang(device, hang);
> intel_ctx_destroy(device, ctx);
> --
> 2.25.1
>
Re: [Intel-gfx] [PATCH 11/14] drm/i915: Clean up cursor registers
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. to polish the cursor plane registers.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 25 ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 +-
> drivers/gpu/drm/i915/i915_reg.h | 71 +++-
> 3 files changed, 53 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
> b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 16d34685d83f..2ade8fdd9bdd 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -51,16 +51,16 @@ static u32 intel_cursor_position(const struct
> intel_plane_state *plane_state)
> u32 pos = 0;
>
> if (x < 0) {
> - pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
> + pos |= CURSOR_POS_X_SIGN;
> x = -x;
> }
> - pos |= x << CURSOR_X_SHIFT;
> + pos |= CURSOR_POS_X(x);
>
> if (y < 0) {
> - pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
> + pos |= CURSOR_POS_Y_SIGN;
> y = -y;
> }
> - pos |= y << CURSOR_Y_SHIFT;
> + pos |= CURSOR_POS_Y(y);
>
> return pos;
> }
> @@ -180,7 +180,7 @@ static u32 i845_cursor_ctl_crtc(const struct
> intel_crtc_state *crtc_state)
> u32 cntl = 0;
>
> if (crtc_state->gamma_enable)
> - cntl |= CURSOR_GAMMA_ENABLE;
> + cntl |= CURSOR_PIPE_GAMMA_ENABLE;
>
> return cntl;
> }
> @@ -264,7 +264,7 @@ static void i845_cursor_update_arm(struct intel_plane
> *plane,
> cntl = plane_state->ctl |
> i845_cursor_ctl_crtc(crtc_state);
>
> - size = (height << 12) | width;
> + size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
>
> base = intel_cursor_base(plane_state);
> pos = intel_cursor_position(plane_state);
> @@ -280,7 +280,7 @@ static void i845_cursor_update_arm(struct intel_plane
> *plane,
> plane->cursor.cntl != cntl) {
> intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
> intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
> - intel_de_write_fw(dev_priv, CURSIZE, size);
> + intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
> intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
> intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
>
> @@ -340,13 +340,13 @@ static u32 i9xx_cursor_ctl_crtc(const struct
> intel_crtc_state *crtc_state)
> return cntl;
>
> if (crtc_state->gamma_enable)
> - cntl = MCURSOR_GAMMA_ENABLE;
> + cntl = MCURSOR_PIPE_GAMMA_ENABLE;
>
> if (crtc_state->csc_enable)
> cntl |= MCURSOR_PIPE_CSC_ENABLE;
>
> if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
> - cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
> + cntl |= MCURSOR_PIPE_SEL(crtc->pipe);
>
> return cntl;
> }
> @@ -502,7 +502,7 @@ static void i9xx_cursor_update_arm(struct intel_plane
> *plane,
> i9xx_cursor_ctl_crtc(crtc_state);
>
> if (width != height)
> - fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
> + fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
>
> base = intel_cursor_base(plane_state);
> pos = intel_cursor_position(plane_state);
> @@ -586,13 +586,12 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane
> *plane,
>
> val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
>
> - ret = val & MCURSOR_MODE;
> + ret = val & MCURSOR_MODE_MASK;
>
> if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
> *pipe = plane->pipe;
> else
> - *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
> - MCURSOR_PIPE_SELECT_SHIFT;
> + *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
>
> intel_display_power_put(dev_priv, power_domain, wakeref);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 00a2c9915780..34c1463e2ef9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10041,9 +10041,9 @@ void i830_disable_pipe(struct drm_i915_private
> *dev_priv, enum pipe pipe)
> drm_WARN_ON(&dev_priv->drm,
> intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DSP_ENABLE);
> drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
> + intel_de_read(dev_priv, CURCNTR(PIPE_A)) &
> MCURSOR_MODE_MASK);
> drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
> + intel_de_read(dev
Re: [Intel-gfx] [PATCH 10/14] drm/i915: Clean up g4x+ sprite plane registers
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. to polish the g4x+ sprite plane registers.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 12 ++--
> drivers/gpu/drm/i915/i915_reg.h | 73 +
> 2 files changed, 53 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index eb9ce96c030f..6f2a560700ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -1054,7 +1054,7 @@ static u32 g4x_sprite_ctl_crtc(const struct
> intel_crtc_state *crtc_state)
> u32 dvscntr = 0;
>
> if (crtc_state->gamma_enable)
> - dvscntr |= DVS_GAMMA_ENABLE;
> + dvscntr |= DVS_PIPE_GAMMA_ENABLE;
>
> if (crtc_state->csc_enable)
> dvscntr |= DVS_PIPE_CSC_ENABLE;
> @@ -1206,14 +1206,18 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
> unsigned long irqflags;
>
> if (crtc_w != src_w || crtc_h != src_h)
> - dvsscale = DVS_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
> + dvsscale = DVS_SCALE_ENABLE |
> + DVS_SRC_WIDTH(src_w - 1) |
> + DVS_SRC_HEIGHT(src_h - 1);
>
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
> plane_state->view.color_plane[0].mapping_stride);
> - intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);
> - intel_de_write_fw(dev_priv, DVSSIZE(pipe), ((crtc_h - 1) << 16) |
> (crtc_w - 1));
> + intel_de_write_fw(dev_priv, DVSPOS(pipe),
> + DVS_POS_Y(crtc_y) | DVS_POS_X(crtc_x));
> + intel_de_write_fw(dev_priv, DVSSIZE(pipe),
> + DVS_HEIGHT(crtc_h - 1) | DVS_WIDTH(crtc_w - 1));
> intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4d61e7f2ee7c..d215cad95fe8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6970,46 +6970,63 @@ enum {
>
> /* Sprite A control */
> #define _DVSACNTR0x72180
> -#define DVS_ENABLE (1 << 31)
> -#define DVS_GAMMA_ENABLE (1 << 30)
> -#define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27)
> -#define DVS_PIXFORMAT_MASK (3 << 25)
> -#define DVS_FORMAT_YUV422 (0 << 25)
> -#define DVS_FORMAT_RGBX101010 (1 << 25)
> -#define DVS_FORMAT_RGBX888 (2 << 25)
> -#define DVS_FORMAT_RGBX161616 (3 << 25)
> -#define DVS_PIPE_CSC_ENABLE (1 << 24)
> -#define DVS_SOURCE_KEY (1 << 22)
> -#define DVS_RGB_ORDER_XBGR (1 << 20)
> -#define DVS_YUV_FORMAT_BT709 (1 << 18)
> -#define DVS_YUV_ORDER_MASK (3 << 16)
> -#define DVS_YUV_ORDER_YUYV (0 << 16)
> -#define DVS_YUV_ORDER_UYVY (1 << 16)
> -#define DVS_YUV_ORDER_YVYU (2 << 16)
> -#define DVS_YUV_ORDER_VYUY (3 << 16)
> -#define DVS_ROTATE_180 (1 << 15)
> -#define DVS_DEST_KEY (1 << 2)
> -#define DVS_TRICKLE_FEED_DISABLE (1 << 14)
> -#define DVS_TILED (1 << 10)
> +#define DVS_ENABLE REG_BIT(31)
> +#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
> +#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
> +#define DVS_FORMAT_MASKREG_GENMASK(26, 25)
> +#define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
> +#define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK,
> 1)
> +#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
> +#define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK,
> 3)
> +#define DVS_PIPE_CSC_ENABLEREG_BIT(24)
> +#define DVS_SOURCE_KEY REG_BIT(22)
> +#define DVS_RGB_ORDER_XBGR REG_BIT(20)
> +#define DVS_YUV_FORMAT_BT709 REG_BIT(18)
> +#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
> +#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
> +#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
> +#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
> +#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
> +#define DVS_ROTATE_180 REG_BIT(15)
> +#define DVS_DEST_KEY REG_BIT(2)
> +#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
> +#define DVS_TILED REG_BIT(10)
> #define _DVSALINOFF 0x72184
> #define _DVSASTRIDE 0x72188
> #define _DVSAPOS 0x7218c
> +#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
> +#define DVS_POS_Y(y) REG_FIELD_PR
Re: [Intel-gfx] [PATCH 09/14] drm/i915: Clean up vlv/chv sprite plane registers
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. to polish the vlv/chv sprite plane registers.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 9 +-
> drivers/gpu/drm/i915/i915_reg.h | 103
> 2 files changed, 70 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 70083d04a9fd..eb9ce96c030f 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -313,7 +313,7 @@ static u32 vlv_sprite_ctl_crtc(const struct
> intel_crtc_state *crtc_state)
> u32 sprctl = 0;
>
> if (crtc_state->gamma_enable)
> - sprctl |= SP_GAMMA_ENABLE;
> + sprctl |= SP_PIPE_GAMMA_ENABLE;
>
> return sprctl;
> }
> @@ -436,9 +436,9 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
> plane_state->view.color_plane[0].mapping_stride);
> intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
> - (crtc_y << 16) | crtc_x);
> + SP_POS_Y(crtc_y) | SP_POS_X(crtc_x));
> intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
> - ((crtc_h - 1) << 16) | (crtc_w - 1));
> + SP_HEIGHT(crtc_h - 1) | SP_WIDTH(crtc_w - 1));
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
> @@ -479,7 +479,8 @@ vlv_sprite_update_arm(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
>
> intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset);
> - intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), (y << 16) | x);
> + intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id),
> + SP_OFFSET_Y(y) | SP_OFFSET_X(x));
>
> /*
>* The control register self-arms if the plane was previously
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0bd47a929f5d..4d61e7f2ee7c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7146,48 +7146,67 @@ enum {
> #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
>
> #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
> -#define SP_ENABLE (1 << 31)
> -#define SP_GAMMA_ENABLE(1 << 30)
> -#define SP_PIXFORMAT_MASK (0xf << 26)
> -#define SP_FORMAT_YUV422 (0x0 << 26)
> -#define SP_FORMAT_8BPP (0x2 << 26)
> -#define SP_FORMAT_BGR565 (0x5 << 26)
> -#define SP_FORMAT_BGRX (0x6 << 26)
> -#define SP_FORMAT_BGRA (0x7 << 26)
> -#define SP_FORMAT_RGBX1010102 (0x8 << 26)
> -#define SP_FORMAT_RGBA1010102 (0x9 << 26)
> -#define SP_FORMAT_BGRX1010102 (0xa << 26) /* CHV pipe B */
> -#define SP_FORMAT_BGRA1010102 (0xb << 26) /* CHV pipe B */
> -#define SP_FORMAT_RGBX (0xe << 26)
> -#define SP_FORMAT_RGBA (0xf << 26)
> -#define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
> -#define SP_SOURCE_KEY (1 << 22)
> -#define SP_YUV_FORMAT_BT709(1 << 18)
> -#define SP_YUV_ORDER_MASK (3 << 16)
> -#define SP_YUV_ORDER_YUYV (0 << 16)
> -#define SP_YUV_ORDER_UYVY (1 << 16)
> -#define SP_YUV_ORDER_YVYU (2 << 16)
> -#define SP_YUV_ORDER_VYUY (3 << 16)
> -#define SP_ROTATE_180 (1 << 15)
> -#define SP_TILED (1 << 10)
> -#define SP_MIRROR (1 << 8) /* CHV pipe B */
> +#define SP_ENABLE REG_BIT(31)
> +#define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
> +#define SP_FORMAT_MASK REG_GENMASK(29, 26)
> +#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
> +#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
> +#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
> +#define SP_FORMAT_BGRX REG_FIELD_PREP(SP_FORMAT_MASK, 6)
> +#define SP_FORMAT_BGRA REG_FIELD_PREP(SP_FORMAT_MASK, 7)
> +#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK,
> 8)
> +#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK,
> 9)
> +#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK,
> 10) /* CHV pipe B */
> +#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK,
> 11) /* CHV pipe B */
> +#define SP_FORMAT_RGBX REG_FIELD_PREP(SP_FORMAT_MASK, 14)
> +#define SP_FORMAT_RGBA REG_FIELD_PREP(SP_FORMAT_MASK, 15)
> +#define SP_ALPHA_PREMULTIPLY REG_BIT(23)
Re: [Intel-gfx] [PATCH 08/14] drm/i915: Clean up ivb+ sprite plane registers
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. to polish the ivb+ sprite plane registers.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 20 +++--
> drivers/gpu/drm/i915/i915_reg.h | 81 +
> 2 files changed, 62 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 2067a7bca4a8..70083d04a9fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -700,7 +700,7 @@ static u32 ivb_sprite_ctl_crtc(const struct
> intel_crtc_state *crtc_state)
> u32 sprctl = 0;
>
> if (crtc_state->gamma_enable)
> - sprctl |= SPRITE_GAMMA_ENABLE;
> + sprctl |= SPRITE_PIPE_GAMMA_ENABLE;
>
> if (crtc_state->csc_enable)
> sprctl |= SPRITE_PIPE_CSC_ENABLE;
> @@ -770,7 +770,7 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state
> *crtc_state,
> }
>
> if (!ivb_need_sprite_gamma(plane_state))
> - sprctl |= SPRITE_INT_GAMMA_DISABLE;
> + sprctl |= SPRITE_PLANE_GAMMA_DISABLE;
>
> if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
> sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
> @@ -863,14 +863,18 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
> unsigned long irqflags;
>
> if (crtc_w != src_w || crtc_h != src_h)
> - sprscale = SPRITE_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h -
> 1);
> + sprscale = SPRITE_SCALE_ENABLE |
> + SPRITE_SRC_WIDTH(src_w - 1) |
> + SPRITE_SRC_HEIGHT(src_h - 1);
>
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
> plane_state->view.color_plane[0].mapping_stride);
> - intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);
> - intel_de_write_fw(dev_priv, SPRSIZE(pipe), ((crtc_h - 1) << 16) |
> (crtc_w - 1));
> + intel_de_write_fw(dev_priv, SPRPOS(pipe),
> + SPRITE_POS_Y(crtc_y) | SPRITE_POS_X(crtc_x));
> + intel_de_write_fw(dev_priv, SPRSIZE(pipe),
> + SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1));
> if (IS_IVYBRIDGE(dev_priv))
> intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
>
> @@ -907,10 +911,12 @@ ivb_sprite_update_arm(struct intel_plane *plane,
> /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
>* register */
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> - intel_de_write_fw(dev_priv, SPROFFSET(pipe), (y << 16) | x);
> + intel_de_write_fw(dev_priv, SPROFFSET(pipe),
> + SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
> } else {
> intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset);
> - intel_de_write_fw(dev_priv, SPRTILEOFF(pipe), (y << 16) | x);
> + intel_de_write_fw(dev_priv, SPRTILEOFF(pipe),
> + SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8678cbab1d33..0bd47a929f5d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7046,50 +7046,67 @@ enum {
> #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK,
> _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
>
> #define _SPRA_CTL0x70280
> -#define SPRITE_ENABLE (1 << 31)
> -#define SPRITE_GAMMA_ENABLE(1 << 30)
> -#define SPRITE_YUV_RANGE_CORRECTION_DISABLE(1 << 28)
> -#define SPRITE_PIXFORMAT_MASK (7 << 25)
> -#define SPRITE_FORMAT_YUV422 (0 << 25)
> -#define SPRITE_FORMAT_RGBX101010 (1 << 25)
> -#define SPRITE_FORMAT_RGBX888 (2 << 25)
> -#define SPRITE_FORMAT_RGBX161616 (3 << 25)
> -#define SPRITE_FORMAT_YUV444 (4 << 25)
> -#define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */
> -#define SPRITE_PIPE_CSC_ENABLE (1 << 24)
> -#define SPRITE_SOURCE_KEY (1 << 22)
> -#define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and
> 161616 */
> -#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
> -#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
> -#define SPRITE_YUV_ORDER_MASK (3 << 16)
> -#define SPRITE_YUV_ORDER_YUYV (0 << 16)
> -#define SPRITE_YUV_ORDER_UYVY (1 << 16)
> -#define SPRITE_YUV_ORDER_YVYU (2 << 16)
> -#define SPRITE_YUV_ORDER_VYUY (3 << 16)
> -#define SPRITE_ROTATE_180 (1 << 15)
> -#define
Re: [Intel-gfx] [igt-dev] [PATCH v4 i-g-t 02/15] lib/hang: Fix igt_require_hang_ring to work with all engines
On Thu, Jan 13, 2022 at 03:51:05PM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> The above function was checking for valid rings via the old interface.
> The new scheme is to check for engines on contexts as there are now
> more engines than could be supported.
>
> Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
> ---
> lib/igt_gt.c | 6 +++---
> lib/igt_gt.h | 2 +-
> tests/i915/i915_hangman.c | 6 +++---
> 3 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/lib/igt_gt.c b/lib/igt_gt.c
> index 7c7df95ee..50da512f2 100644
> --- a/lib/igt_gt.c
> +++ b/lib/igt_gt.c
> @@ -122,12 +122,12 @@ static void eat_error_state(int dev)
> * to be done under hang injection.
> * Default: false
> */
> -void igt_require_hang_ring(int fd, int ring)
> +void igt_require_hang_ring(int fd, uint32_t ctx, int ring)
> {
> if (!igt_check_boolean_env_var("IGT_HANG", true))
> igt_skip("hang injection disabled by user [IGT_HANG=0]\n");
>
> - gem_require_ring(fd, ring);
> +igt_require(gem_context_has_engine(fd, ctx, ring));
> gem_context_require_bannable(fd);
> if (!igt_check_boolean_env_var("IGT_HANG_WITHOUT_RESET", false))
> igt_require(has_gpu_reset(fd));
> @@ -290,7 +290,7 @@ static igt_hang_t __igt_hang_ctx(int fd, uint64_t ahnd,
> uint32_t ctx, int ring,
> igt_spin_t *spin;
> unsigned ban;
>
> - igt_require_hang_ring(fd, ring);
> + igt_require_hang_ring(fd, ctx, ring);
>
> /* check if non-default ctx submission is allowed */
> igt_require(ctx == 0 || has_ctx_exec(fd, ring, ctx));
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index c5059817b..3d10349e4 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -31,7 +31,7 @@
> #include "i915/i915_drm_local.h"
> #include "i915_drm.h"
>
> -void igt_require_hang_ring(int fd, int ring);
> +void igt_require_hang_ring(int fd, uint32_t ctx, int ring);
>
> typedef struct igt_hang {
> igt_spin_t *spin;
> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> index b9c4d9983..f64b8819d 100644
> --- a/tests/i915/i915_hangman.c
> +++ b/tests/i915/i915_hangman.c
> @@ -295,7 +295,7 @@ test_engine_hang(const intel_ctx_t *ctx,
> * case and it takes a lot more time to wrap, so the acthd can potentially
> keep
> * increasing for a long time
> */
> -static void hangcheck_unterminated(void)
> +static void hangcheck_unterminated(const intel_ctx_t *ctx)
> {
> /* timeout needs to be greater than ~5*hangcheck */
> int64_t timeout_ns = 100ull * NSEC_PER_SEC; /* 100 seconds */
> @@ -304,7 +304,7 @@ static void hangcheck_unterminated(void)
> uint32_t handle;
>
> igt_require(gem_uses_full_ppgtt(device));
> - igt_require_hang_ring(device, 0);
> + igt_require_hang_ring(device, ctx->id, 0);
>
> handle = gem_create(device, 4096);
>
> @@ -394,7 +394,7 @@ igt_main
>
> igt_describe("Check that executing unintialised memory causes a hang");
> igt_subtest("hangcheck-unterminated")
> - hangcheck_unterminated();
> + hangcheck_unterminated(ctx);
>
> igt_fixture {
> igt_disallow_hang(device, hang);
> --
> 2.25.1
>
Re: [Intel-gfx] [PATCH v4 i-g-t 05/15] tests/i915/i915_hangman: Add uevent test & fix detector
On Thu, Jan 13, 2022 at 03:51:08PM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Some of the IGT framework relies on receving a uevent when a hang
> occurs. So add a test that this actually works.
>
> While testing this, noticed that hangs could sometimes be missed
> because the uevent was (presumably) still in flight by the time the
> handler was de-registered. So add an extra delay during cleanup to
> give the uevent chance to arrive.
>
> Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
> ---
> lib/igt_aux.c | 7 +++
> tests/i915/i915_hangman.c | 43 +++
> 2 files changed, 50 insertions(+)
>
> diff --git a/lib/igt_aux.c b/lib/igt_aux.c
> index c247a1aa4..03cc38c93 100644
> --- a/lib/igt_aux.c
> +++ b/lib/igt_aux.c
> @@ -523,6 +523,13 @@ void igt_fork_hang_detector(int fd)
>
> void igt_stop_hang_detector(void)
> {
> + /*
> + * Give the uevent time to arrive. No sleep at all misses about 20% of
> + * hangs (at least, in the i915_hangman/detector test). A sleep of 1ms
> + * seems to miss about 2%, 10ms loses <1%, so 100ms should be safe.
> + */
> + usleep(100 * 1000);
> +
> igt_stop_helper(&hang_detector);
> }
>
> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> index 7b8390a6c..354769f39 100644
> --- a/tests/i915/i915_hangman.c
> +++ b/tests/i915/i915_hangman.c
> @@ -31,6 +31,7 @@
> #include
> #include
> #include
> +#include
>
> #include "i915/gem.h"
> #include "i915/gem_create.h"
> @@ -289,6 +290,38 @@ test_engine_hang(const intel_ctx_t *ctx,
> put_ahnd(ahnd);
> }
>
> +static int hang_count;
> +
> +static void sig_io(int sig)
> +{
> + hang_count++;
> +}
> +
> +static void test_hang_detector(const intel_ctx_t *ctx,
> +const struct intel_execution_engine2 *e)
> +{
> + igt_hang_t hang;
> + uint64_t ahnd = get_reloc_ahnd(device, ctx->id);
> +
> + hang_count = 0;
> +
> + igt_fork_hang_detector(device);
> +
> + /* Steal the signal handler */
> + signal(SIGIO, sig_io);
> +
> + /* Make a hang... */
> + hang = igt_hang_ctx_with_ahnd(device, ahnd, ctx->id, e->flags, 0);
> +
> + igt_post_hang_ring(device, hang);
> + put_ahnd(ahnd);
> +
> + igt_stop_hang_detector();
> +
> + /* Did it work? */
> + igt_assert(hang_count == 1);
> +}
> +
> /* This test covers the case where we end up in an uninitialised area of the
> * ppgtt and keep executing through it. This is particularly relevant if 48b
> * ppgtt is enabled because the ppgtt is massively bigger compared to the 32b
> @@ -408,6 +441,16 @@ igt_main
> igt_subtest("hangcheck-unterminated")
> hangcheck_unterminated(ctx);
>
> + igt_describe("Check that hang detector works");
> + igt_subtest_with_dynamic("detector") {
> + const struct intel_execution_engine2 *e;
> +
> + for_each_ctx_engine(device, ctx, e) {
> + igt_dynamic_f("%s", e->name)
> + test_hang_detector(ctx, e);
> + }
> + }
> +
> do_tests("GT", "gt", ctx);
>
> igt_fixture {
> --
> 2.25.1
>
Re: [Intel-gfx] [PATCH][RESEND] i915: make array flex_regs static const
On 13/01/2022 09:21, Jani Nikula wrote: On Wed, 12 Jan 2022, Colin Ian King wrote: Don't populate the read-only array flex_regs on the stack but instead it static const. Also makes the object code a little smaller. Signed-off-by: Colin Ian King --- RESEND: Use correct e-mail address for sign-off and From: in e-mail. There are a number of things at play here: - Our tooling checks for certain things, such as author/signed-off-by match, after applying the patch. - You have an entry in the kernel git .mailmap. - The git log.mailmap config default has changed from false to true. We apply the patch, and, with the default options, git show will display a different author than the signed-off-by. We should use --no-use-mailmap when examining a commit to ensure the commit is internally consistent, regardless of .mailmap. Yes that sounds like the right thing to do. In the meantime I have pushed this patch. Regards, Tvrtko
Re: [Intel-gfx] [PULL] drm-misc-next-fixes
On Fri, Jan 14, 2022 at 03:24:59PM +0100, Thomas Zimmermann wrote: > Hi Dave and Daniel, > > here are two more fixes for this week. I cherry-picked both from > drm-misc-next. > > Best regards > Thomas > > drm-misc-next-fixes-2022-01-14: > * atomic helpers: Fix error messages > * mipi-dbi: Fix buffer mapping > The following changes since commit 5da8b49de472c1da8658466d4f63ef8d9251a819: > > dt-bindings: display: bridge: lvds-codec: Fix duplicate key (2021-12-22 > 14:02:04 -0400) > > are available in the Git repository at: > > git://anongit.freedesktop.org/drm/drm-misc > tags/drm-misc-next-fixes-2022-01-14 Thanks, pulled to drm-next. -Daniel > > for you to fetch changes up to 5d474cc501b90b82c182b5d00439eb6790a82e21: > > drm/mipi-dbi: Fix source-buffer address in mipi_dbi_buf_copy (2022-01-14 > 14:43:02 +0100) > > > * atomic helpers: Fix error messages > * mipi-dbi: Fix buffer mapping > > > Claudio Suarez (1): > drm: fix error found in some cases after the patch d1af5cd86997 > > Liu Ying (1): > drm/atomic: Check new_crtc_state->active to determine if CRTC needs > disable in self refresh mode > > Thomas Zimmermann (1): > drm/mipi-dbi: Fix source-buffer address in mipi_dbi_buf_copy > > drivers/gpu/drm/drm_atomic_helper.c | 14 +++--- > drivers/gpu/drm/drm_mipi_dbi.c | 2 +- > 2 files changed, 8 insertions(+), 8 deletions(-) > > -- > Thomas Zimmermann > Graphics Driver Developer > SUSE Software Solutions Germany GmbH > Maxfeldstr. 5, 90409 Nürnberg, Germany > (HRB 36809, AG Nürnberg) > Geschäftsführer: Felix Imendörffer -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove short term pins from execbuf by requiring lock to unbind.
== Series Details ==
Series: drm/i915: Remove short term pins from execbuf by requiring lock to
unbind.
URL : https://patchwork.freedesktop.org/series/98895/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11086 -> Patchwork_22003
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22003/index.html
Participating hosts (48 -> 43)
--
Additional (1): fi-pnv-d510
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-icl-u2 fi-ctg-p8600
fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22003:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- {bat-adlp-6}: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11086/bat-adlp-6/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22003/bat-adlp-6/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html
Known issues
Here are the changes found in Patchwork_22003 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-bsw-n3050: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22003/fi-bsw-n3050/igt@amdgpu/amd_cs_...@fork-gfx0.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22003/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22003/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-pnv-d510:NOTRUN -> [SKIP][6] ([fdo#109271]) +57 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22003/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22003/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [PASS][8] -> [INCOMPLETE][9] ([i915#2940])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11086/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22003/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22003/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][11] ([fdo#109271]) +21 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22003/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][12] -> [DMESG-WARN][13] ([i915#4269])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11086/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22003/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22003/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> [FAIL][15] ([fdo#109271] / [i915#1436] /
[i915#3428] / [i915#4312])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22003/fi-bsw-kefka/igt@run...@aborted.html
Possible fixes
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [FAIL][16] ([i915#4547]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11086/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22003/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][18] ([i915#4494]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11086/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22003/bat-dg1-6/igt@i915_sel
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Remove short term pins from execbuf by requiring lock to unbind.
== Series Details == Series: drm/i915: Remove short term pins from execbuf by requiring lock to unbind. URL : https://patchwork.freedesktop.org/series/98895/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/i915_gem_evict.c:144: warning: Function parameter or member 'ww' not described in 'i915_gem_evict_something' ./drivers/gpu/drm/i915/i915_gem_evict.c:313: warning: Function parameter or member 'ww' not described in 'i915_gem_evict_for_node' ./drivers/gpu/drm/i915/i915_gem_evict.c:425: warning: Function parameter or member 'ww' not described in 'i915_gem_evict_vm' ./drivers/gpu/drm/i915/i915_gem_gtt.c:101: warning: Function parameter or member 'ww' not described in 'i915_gem_gtt_reserve' ./drivers/gpu/drm/i915/i915_gem_gtt.c:193: warning: Function parameter or member 'ww' not described in 'i915_gem_gtt_insert'
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Remove short term pins from execbuf by requiring lock to unbind.
== Series Details == Series: drm/i915: Remove short term pins from execbuf by requiring lock to unbind. URL : https://patchwork.freedesktop.org/series/98895/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Remove short term pins from execbuf by requiring lock to unbind.
== Series Details ==
Series: drm/i915: Remove short term pins from execbuf by requiring lock to
unbind.
URL : https://patchwork.freedesktop.org/series/98895/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
db8c9a3db0b3 drm/i915: Call i915_gem_evict_vm in vm_fault_gtt to prevent new
ENOSPC errors, v2.
d2192b26e81d drm/i915: Add locking to i915_gem_evict_vm(), v2.
ceef6899f6ef drm/i915: Add object locking to i915_gem_evict_for_node and
i915_gem_evict_something, v2.
-:228: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#228: FILE: drivers/gpu/drm/i915/i915_gem_evict.c:457:
+ if (dying_vma(vma) || (ww &&
+(dma_resv_locking_ctx(vma->obj->base.resv) ==
&ww->ctx))) {
total: 0 errors, 0 warnings, 1 checks, 376 lines checked
933249276580 drm/i915: Add i915_vma_unbind_unlocked, and take obj lock for
i915_vma_unbind, v2.
72fcac47dca9 drm/i915: Remove support for unlocked i915_vma unbind
842cd8d49f5e drm/i915: Remove short-term pins from execbuf, v6.
[Intel-gfx] [PULL] drm-misc-next-fixes
Hi Dave and Daniel, here are two more fixes for this week. I cherry-picked both from drm-misc-next. Best regards Thomas drm-misc-next-fixes-2022-01-14: * atomic helpers: Fix error messages * mipi-dbi: Fix buffer mapping The following changes since commit 5da8b49de472c1da8658466d4f63ef8d9251a819: dt-bindings: display: bridge: lvds-codec: Fix duplicate key (2021-12-22 14:02:04 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-fixes-2022-01-14 for you to fetch changes up to 5d474cc501b90b82c182b5d00439eb6790a82e21: drm/mipi-dbi: Fix source-buffer address in mipi_dbi_buf_copy (2022-01-14 14:43:02 +0100) * atomic helpers: Fix error messages * mipi-dbi: Fix buffer mapping Claudio Suarez (1): drm: fix error found in some cases after the patch d1af5cd86997 Liu Ying (1): drm/atomic: Check new_crtc_state->active to determine if CRTC needs disable in self refresh mode Thomas Zimmermann (1): drm/mipi-dbi: Fix source-buffer address in mipi_dbi_buf_copy drivers/gpu/drm/drm_atomic_helper.c | 14 +++--- drivers/gpu/drm/drm_mipi_dbi.c | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer
Re: [Intel-gfx] [PATCH v6 2/6] drm/i915: Add locking to i915_gem_evict_vm(), v2.
On 1/14/22 14:23, Maarten Lankhorst wrote:
i915_gem_evict_vm will need to be able to evict objects that are
locked by the current ctx. By testing if the current context already
locked the object, we can do this correctly. This allows us to
evict the entire vm even if we already hold some objects' locks.
Previously, this was spread over several commits, but it makes
more sense to commit the changes to i915_gem_evict_vm separately
from the changes to i915_gem_evict_something() and
i915_gem_evict_for_node().
Changes since v1:
- Handle evicting dead objects better.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/i915_gem_evict.c | 32 +--
drivers/gpu/drm/i915/i915_gem_evict.h | 4 ++-
drivers/gpu/drm/i915/i915_vma.c | 7 +++-
.../gpu/drm/i915/selftests/i915_gem_evict.c | 10 --
6 files changed, 49 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index cf283b5f6ffe..4d832d6696b5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -767,7 +767,7 @@ static int eb_reserve(struct i915_execbuffer *eb)
case 1:
/* Too fragmented, unbind everything and retry */
mutex_lock(&eb->context->vm->mutex);
- err = i915_gem_evict_vm(eb->context->vm);
+ err = i915_gem_evict_vm(eb->context->vm, &eb->ww);
mutex_unlock(&eb->context->vm->mutex);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index fafd158e5313..a69787999d09 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -367,7 +367,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
if (vma == ERR_PTR(-ENOSPC)) {
ret = mutex_lock_interruptible(&ggtt->vm.mutex);
if (!ret) {
- ret = i915_gem_evict_vm(&ggtt->vm);
+ ret = i915_gem_evict_vm(&ggtt->vm, &ww);
mutex_unlock(&ggtt->vm.mutex);
}
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index 24eee0c2055f..91f82ecb9ef4 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -368,7 +368,7 @@ int i915_gem_evict_for_node(struct i915_address_space *vm,
* To clarify: This is for freeing up virtual address space, not for freeing
* memory in e.g. the shrinker.
*/
-int i915_gem_evict_vm(struct i915_address_space *vm)
+int i915_gem_evict_vm(struct i915_address_space *vm, struct i915_gem_ww_ctx
*ww)
{
int ret = 0;
@@ -389,24 +389,52 @@ int i915_gem_evict_vm(struct i915_address_space *vm)
do {
struct i915_vma *vma, *vn;
LIST_HEAD(eviction_list);
+ LIST_HEAD(locked_eviction_list);
list_for_each_entry(vma, &vm->bound_list, vm_link) {
if (i915_vma_is_pinned(vma))
continue;
+ /*
+* If we already own the lock, trylock fails. In case
+* the resv is shared among multiple objects, we still
+* need the object ref.
+*/
Should we handle dying vmas like for the other eviction utilities and
also evict pinned dying vmas?
+ if (!kref_read(&vma->obj->base.refcount) ||
+ (ww && (dma_resv_locking_ctx(vma->obj->base.resv) ==
&ww->ctx))) {
+ __i915_vma_pin(vma);
+ list_add(&vma->evict_link,
&locked_eviction_list);
+ continue;
+ }
+
+ if (!i915_gem_object_trylock(vma->obj, ww))
+ continue;
+
__i915_vma_pin(vma);
list_add(&vma->evict_link, &eviction_list);
}
- if (list_empty(&eviction_list))
+ if (list_empty(&eviction_list) &&
list_empty(&locked_eviction_list))
break;
ret = 0;
+ /* Unbind locked objects first, before unlocking the
eviction_list */
+ list_for_each_entry_safe(vma, vn, &locked_eviction_list,
evict_link) {
+ __i915_vma_unpin(vma);
+
+ if (ret == 0)
+ ret = __i915_vma_unbind(vma);
+ if (ret != -EINTR) /* "Get
Re: [Intel-gfx] [PULL] drm-misc-next-fixes
On Thu, Jan 13, 2022 at 09:29:51AM +0100, Thomas Zimmermann wrote: > Hi Dave and Daniel, > > here's this week's PR for drm-misc-next-fixes. > > Best regards > Thomas > > drm-misc-next-fixes-2022-01-13: > * Fix use of CRTC state's active vs enable in atomic helper > The following changes since commit 5da8b49de472c1da8658466d4f63ef8d9251a819: > > dt-bindings: display: bridge: lvds-codec: Fix duplicate key (2021-12-22 > 14:02:04 -0400) > > are available in the Git repository at: > > git://anongit.freedesktop.org/drm/drm-misc > tags/drm-misc-next-fixes-2022-01-13 > > for you to fetch changes up to 69e630016ef4e4a1745310c446f204dc6243e907: Thanks, pulled to drm-next. -Daniel > > drm/atomic: Check new_crtc_state->active to determine if CRTC needs disable > in self refresh mode (2022-01-11 10:37:15 -0500) > > > * Fix use of CRTC state's active vs enable in atomic helper > > > Liu Ying (1): > drm/atomic: Check new_crtc_state->active to determine if CRTC needs > disable in self refresh mode > > drivers/gpu/drm/drm_atomic_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > -- > Thomas Zimmermann > Graphics Driver Developer > SUSE Software Solutions Germany GmbH > Maxfeldstr. 5, 90409 Nürnberg, Germany > (HRB 36809, AG Nürnberg) > Geschäftsführer: Felix Imendörffer -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
[Intel-gfx] [PATCH v6 6/6] drm/i915: Remove short-term pins from execbuf, v6.
Add a flag PIN_VALIDATE, to indicate we don't need to pin and only
protected by the object lock.
This removes the need to unpin, which is done by just releasing the
lock.
eb_reserve is slightly reworked for readability, but the same steps
are still done:
- First pass pins with NONBLOCK.
- Second pass unbinds all objects first, then pins.
- Third pass is only called when not all objects are softpinned, and
unbinds all objects, then calls i915_gem_evict_vm(), then pins.
Changes since v1:
- Split out eb_reserve() into separate functions for readability.
Changes since v2:
- Make batch buffer mappable on platforms where only GGTT is available,
to prevent moving the batch buffer during relocations.
Changes since v3:
- Preserve current behavior for batch buffer, instead be cautious when
calling i915_gem_object_ggtt_pin_ww, and re-use the current batch vma
if it's inside ggtt and map-and-fenceable.
- Remove impossible condition check from eb_reserve. (Matt)
Changes since v5:
- Do not even temporarily pin, just call i915_gem_evict_vm() and mark
all vma's as unpinned.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Matthew Auld
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 220 +-
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 1 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
drivers/gpu/drm/i915/i915_vma.c | 24 +-
4 files changed, 128 insertions(+), 118 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 4d832d6696b5..6e833bcd0012 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -442,7 +442,7 @@ eb_pin_vma(struct i915_execbuffer *eb,
else
pin_flags = entry->offset & PIN_OFFSET_MASK;
- pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED;
+ pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED | PIN_VALIDATE;
if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_GTT))
pin_flags |= PIN_GLOBAL;
@@ -460,17 +460,15 @@ eb_pin_vma(struct i915_execbuffer *eb,
entry->pad_to_size,
entry->alignment,
eb_pin_flags(entry, ev->flags) |
-PIN_USER | PIN_NOEVICT);
+PIN_USER | PIN_NOEVICT |
PIN_VALIDATE);
if (unlikely(err))
return err;
}
if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
err = i915_vma_pin_fence(vma);
- if (unlikely(err)) {
- i915_vma_unpin(vma);
+ if (unlikely(err))
return err;
- }
if (vma->fence)
ev->flags |= __EXEC_OBJECT_HAS_FENCE;
@@ -486,13 +484,9 @@ eb_pin_vma(struct i915_execbuffer *eb,
static inline void
eb_unreserve_vma(struct eb_vma *ev)
{
- if (!(ev->flags & __EXEC_OBJECT_HAS_PIN))
- return;
-
if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE))
__i915_vma_unpin_fence(ev->vma);
- __i915_vma_unpin(ev->vma);
ev->flags &= ~__EXEC_OBJECT_RESERVED;
}
@@ -685,10 +679,8 @@ static int eb_reserve_vma(struct i915_execbuffer *eb,
if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
err = i915_vma_pin_fence(vma);
- if (unlikely(err)) {
- i915_vma_unpin(vma);
+ if (unlikely(err))
return err;
- }
if (vma->fence)
ev->flags |= __EXEC_OBJECT_HAS_FENCE;
@@ -700,85 +692,95 @@ static int eb_reserve_vma(struct i915_execbuffer *eb,
return 0;
}
-static int eb_reserve(struct i915_execbuffer *eb)
+static bool eb_unbind(struct i915_execbuffer *eb, bool force)
{
const unsigned int count = eb->buffer_count;
- unsigned int pin_flags = PIN_USER | PIN_NONBLOCK;
+ unsigned int i;
struct list_head last;
+ bool unpinned = false;
+
+ /* Resort *all* the objects into priority order */
+ INIT_LIST_HEAD(&eb->unbound);
+ INIT_LIST_HEAD(&last);
+
+ for (i = 0; i < count; i++) {
+ struct eb_vma *ev = &eb->vma[i];
+ unsigned int flags = ev->flags;
+
+ if (!force && flags & EXEC_OBJECT_PINNED &&
+ flags & __EXEC_OBJECT_HAS_PIN)
+ continue;
+
+ unpinned = true;
+ eb_unreserve_vma(ev);
+
+ if (flags & EXEC_OBJECT_PINNED)
+ /* Pinned must have their slot */
+ list_add(&ev->bind_link, &eb->unbound);
+ else if (flags & __EXEC_OBJECT_NEEDS_MAP)
+ /* Map require the lowest 256MiB (apert
[Intel-gfx] [PATCH v6 5/6] drm/i915: Remove support for unlocked i915_vma unbind
Now that we require the object lock for all ops, some code handling
race conditions can be removed.
This is required to not take short-term pins inside execbuf.
Signed-off-by: Maarten Lankhorst
Acked-by: Niranjana Vishwanathapura
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/i915_vma.c | 55 +
1 file changed, 8 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 1213888b82d1..7b30a4ae11d1 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -839,7 +839,6 @@ i915_vma_detach(struct i915_vma *vma)
static bool try_qad_pin(struct i915_vma *vma, unsigned int flags)
{
unsigned int bound;
- bool pinned = true;
bound = atomic_read(&vma->flags);
do {
@@ -849,34 +848,10 @@ static bool try_qad_pin(struct i915_vma *vma, unsigned
int flags)
if (unlikely(bound & (I915_VMA_OVERFLOW | I915_VMA_ERROR)))
return false;
- if (!(bound & I915_VMA_PIN_MASK))
- goto unpinned;
-
GEM_BUG_ON(((bound + 1) & I915_VMA_PIN_MASK) == 0);
} while (!atomic_try_cmpxchg(&vma->flags, &bound, bound + 1));
return true;
-
-unpinned:
- /*
-* If pin_count==0, but we are bound, check under the lock to avoid
-* racing with a concurrent i915_vma_unbind().
-*/
- mutex_lock(&vma->vm->mutex);
- do {
- if (unlikely(bound & (I915_VMA_OVERFLOW | I915_VMA_ERROR))) {
- pinned = false;
- break;
- }
-
- if (unlikely(flags & ~bound)) {
- pinned = false;
- break;
- }
- } while (!atomic_try_cmpxchg(&vma->flags, &bound, bound + 1));
- mutex_unlock(&vma->vm->mutex);
-
- return pinned;
}
static struct scatterlist *
@@ -1215,7 +1190,6 @@ static int
__i915_vma_get_pages(struct i915_vma *vma)
{
struct sg_table *pages;
- int ret;
/*
* The vma->pages are only valid within the lifespan of the borrowed
@@ -1248,18 +1222,16 @@ __i915_vma_get_pages(struct i915_vma *vma)
break;
}
- ret = 0;
if (IS_ERR(pages)) {
- ret = PTR_ERR(pages);
- pages = NULL;
drm_err(&vma->vm->i915->drm,
- "Failed to get pages for VMA view type %u (%d)!\n",
- vma->ggtt_view.type, ret);
+ "Failed to get pages for VMA view type %u (%ld)!\n",
+ vma->ggtt_view.type, PTR_ERR(pages));
+ return PTR_ERR(pages);
}
vma->pages = pages;
- return ret;
+ return 0;
}
I915_SELFTEST_EXPORT int i915_vma_get_pages(struct i915_vma *vma)
@@ -1291,25 +1263,14 @@ I915_SELFTEST_EXPORT int i915_vma_get_pages(struct
i915_vma *vma)
static void __vma_put_pages(struct i915_vma *vma, unsigned int count)
{
/* We allocate under vma_get_pages, so beware the shrinker */
- struct sg_table *pages = READ_ONCE(vma->pages);
-
GEM_BUG_ON(atomic_read(&vma->pages_count) < count);
if (atomic_sub_return(count, &vma->pages_count) == 0) {
- /*
-* The atomic_sub_return is a read barrier for the READ_ONCE of
-* vma->pages above.
-*
-* READ_ONCE is safe because this is either called from the same
-* function (i915_vma_pin_ww), or guarded by vma->vm->mutex.
-*
-* TODO: We're leaving vma->pages dangling, until vma->obj->resv
-* lock is required.
-*/
- if (pages != vma->obj->mm.pages) {
- sg_free_table(pages);
- kfree(pages);
+ if (vma->pages != vma->obj->mm.pages) {
+ sg_free_table(vma->pages);
+ kfree(vma->pages);
}
+ vma->pages = NULL;
i915_gem_object_unpin_pages(vma->obj);
}
--
2.34.1
[Intel-gfx] [PATCH v6 3/6] drm/i915: Add object locking to i915_gem_evict_for_node and i915_gem_evict_something, v2.
Because we will start to require the obj->resv lock for unbinding,
ensure these vma eviction utility functions also take the lock.
This requires some function signature changes, to ensure that the
ww context is passed around, but is mostly straightforward.
Previously this was split up into several patches, but reworking
should allow for easier bisection.
Changes since v1:
- Handle evicting dead objects better.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
drivers/gpu/drm/i915/gvt/aperture_gm.c| 2 +-
drivers/gpu/drm/i915/i915_gem_evict.c | 69 ---
drivers/gpu/drm/i915/i915_gem_evict.h | 2 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++-
drivers/gpu/drm/i915/i915_gem_gtt.h | 3 +
drivers/gpu/drm/i915/i915_vgpu.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 9 +--
.../gpu/drm/i915/selftests/i915_gem_evict.c | 16 ++---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 6 +-
11 files changed, 91 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index a1b2761bc16e..da7f54b6fa38 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -506,7 +506,7 @@ static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP);
size = ggtt->vm.total - GUC_GGTT_TOP;
- ret = i915_gem_gtt_reserve(&ggtt->vm, &ggtt->uc_fw, size,
+ ret = i915_gem_gtt_reserve(&ggtt->vm, NULL, &ggtt->uc_fw, size,
GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,
PIN_NOEVICT);
if (ret)
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 4a20ba63446c..c078d3f55815 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1383,7 +1383,7 @@ static int evict_vma(void *data)
complete(&arg->completion);
mutex_lock(&vm->mutex);
- err = i915_gem_evict_for_node(vm, &evict, 0);
+ err = i915_gem_evict_for_node(vm, NULL, &evict, 0);
mutex_unlock(&vm->mutex);
return err;
diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c
b/drivers/gpu/drm/i915/gvt/aperture_gm.c
index 0d6d59871308..c08098a167e9 100644
--- a/drivers/gpu/drm/i915/gvt/aperture_gm.c
+++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c
@@ -63,7 +63,7 @@ static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
mutex_lock(>->ggtt->vm.mutex);
mmio_hw_access_pre(gt);
- ret = i915_gem_gtt_insert(>->ggtt->vm, node,
+ ret = i915_gem_gtt_insert(>->ggtt->vm, NULL, node,
size, I915_GTT_PAGE_SIZE,
I915_COLOR_UNEVICTABLE,
start, end, flags);
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index 91f82ecb9ef4..e93fe26930fb 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -38,6 +38,11 @@ I915_SELFTEST_DECLARE(static struct igt_evict_ctl {
bool fail_if_busy:1;
} igt_evict_ctl;)
+static bool dying_vma(struct i915_vma *vma)
+{
+ return !kref_read(&vma->obj->base.refcount);
+}
+
static int ggtt_flush(struct intel_gt *gt)
{
/*
@@ -50,8 +55,37 @@ static int ggtt_flush(struct intel_gt *gt)
return intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
}
+static bool grab_vma(struct i915_vma *vma, struct i915_gem_ww_ctx *ww)
+{
+ /*
+* We add the extra refcount so the object doesn't drop to zero until
+* after ungrab_vma(), this way trylock is always paired with unlock.
+*/
+ if (i915_gem_object_get_rcu(vma->obj)) {
+ if (!i915_gem_object_trylock(vma->obj, ww)) {
+ i915_gem_object_put(vma->obj);
+ return false;
+ }
+ } else {
+ /* Dead objects don't need pins */
+ atomic_and(~I915_VMA_PIN_MASK, &vma->flags);
+ }
+
+ return true;
+}
+
+static void ungrab_vma(struct i915_vma *vma)
+{
+ if (dying_vma(vma))
+ return;
+
+ i915_gem_object_unlock(vma->obj);
+ i915_gem_object_put(vma->obj);
+}
+
static bool
mark_free(struct drm_mm_scan *scan,
+ struct i915_gem_ww_ctx *ww,
struct i915_vma *vma,
unsigned int flags,
struct list_head *unwind)
@@ -59,6 +93,9 @@ mark_free(struct drm_mm_scan *scan,
if (i915_vma_is_pinned(vma))
return false;
+ if (!grab_vma(vma, ww))
+ return false;
+
list_add(&vma->evict_link, unwind);
return drm_mm_scan_add_block(scan, &vma->node);
}
@@ -99,6 +136,7 @@
[Intel-gfx] [PATCH v6 1/6] drm/i915: Call i915_gem_evict_vm in vm_fault_gtt to prevent new ENOSPC errors, v2.
Now that we cannot unbind kill the currently locked object directly
because we're removing short term pinning, we may have to unbind the
object from gtt manually, using a i915_gem_evict_vm() call.
Changes since v1:
- Remove -ENOSPC warning, can still happen with concurrent mmaps
where we can't unbind the other mmap because of the lock held.
This fixes the gem_mmap_gtt@cpuset tests.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 5ac2506f4ee8..fafd158e5313 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -21,6 +21,7 @@
#include "i915_trace.h"
#include "i915_user_extensions.h"
#include "i915_gem_ttm.h"
+#include "i915_gem_evict.h"
#include "i915_vma.h"
static inline bool
@@ -358,8 +359,21 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
vma = i915_gem_object_ggtt_pin_ww(obj, &ww, &view, 0,
0, flags);
}
- /* The entire mappable GGTT is pinned? Unexpected! */
- GEM_BUG_ON(vma == ERR_PTR(-ENOSPC));
+ /*
+* The entire mappable GGTT is pinned? Unexpected!
+* Try to evict the object we locked too, as normally we skip it
+* due to lack of short term pinning inside execbuf.
+*/
+ if (vma == ERR_PTR(-ENOSPC)) {
+ ret = mutex_lock_interruptible(&ggtt->vm.mutex);
+ if (!ret) {
+ ret = i915_gem_evict_vm(&ggtt->vm);
+ mutex_unlock(&ggtt->vm.mutex);
+ }
+ if (ret)
+ goto err_reset;
+ vma = i915_gem_object_ggtt_pin_ww(obj, &ww, &view, 0,
0, flags);
+ }
}
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
--
2.34.1
[Intel-gfx] [PATCH v6 0/6] drm/i915: Remove short term pins from execbuf by requiring lock to unbind.
Previously, short term pinning in execbuf was required because i915_vma was effectively independent from objects, and has its own refcount, locking, lifetime rules and pinning. This series removes the separate locking, by requiring vma->obj->resv to be held when pinning and unbinding. This will also be required for VM_BIND work. Some patches have already been merged, but this contains the mremainder of the conversion. With pinning required for pinning and unbinding, the lock is enough to prevent unbinding when trying to pin with the lock held, for example in execbuf. This makes binding/unbinding similar to ttm_bo_validate()'s use, which just cares that an object is in a certain place, without pinning it in place. Having the VMA part of gem bo removes a lot of the vma refcounting, and makes i915_vma more a part of the bo, instead of its own floating object that just happens to be part of a bo. This is also required to make it more compatible with TTM, and migration in general. For future work, it makes things a lot simpler and clear. We want to end up with i915_vma just being a specific mapping of the BO, just like is the case in other drivers. i915_vma->active removal is the next step there, and makes it when object is destroyed, the bindings are destroyed (after idle), instead of object being destroyed when bindings are idle. Changes since last version: - Fix list corruption in i915_gem_evict_vm() - Small fixes and assorted canges. Maarten Lankhorst (6): drm/i915: Call i915_gem_evict_vm in vm_fault_gtt to prevent new ENOSPC errors, v2. drm/i915: Add locking to i915_gem_evict_vm(), v2. drm/i915: Add object locking to i915_gem_evict_for_node and i915_gem_evict_something, v2. drm/i915: Add i915_vma_unbind_unlocked, and take obj lock for i915_vma_unbind, v2. drm/i915: Remove support for unlocked i915_vma unbind drm/i915: Remove short-term pins from execbuf, v6. drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 220 +- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 18 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +- .../i915/gem/selftests/i915_gem_client_blt.c | 2 +- .../drm/i915/gem/selftests/i915_gem_mman.c| 6 + drivers/gpu/drm/i915/gt/intel_ggtt.c | 47 +++- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 1 - drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +- drivers/gpu/drm/i915/gvt/aperture_gm.c| 2 +- drivers/gpu/drm/i915/i915_gem.c | 2 + drivers/gpu/drm/i915/i915_gem_evict.c | 97 +++- drivers/gpu/drm/i915/i915_gem_evict.h | 6 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 8 +- drivers/gpu/drm/i915/i915_gem_gtt.h | 4 + drivers/gpu/drm/i915/i915_vgpu.c | 2 +- drivers/gpu/drm/i915/i915_vma.c | 122 +- drivers/gpu/drm/i915/i915_vma.h | 1 + .../gpu/drm/i915/selftests/i915_gem_evict.c | 26 ++- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 28 +-- drivers/gpu/drm/i915/selftests/i915_vma.c | 8 +- 21 files changed, 382 insertions(+), 224 deletions(-) -- 2.34.1
[Intel-gfx] [PATCH v6 4/6] drm/i915: Add i915_vma_unbind_unlocked, and take obj lock for i915_vma_unbind, v2.
We want to remove more members of i915_vma, which requires the locking to
be held more often.
Start requiring gem object lock for i915_vma_unbind, as it's one of the
callers that may unpin pages.
Some special care is needed when evicting, because the last reference to
the object may be held by the VMA, so after __i915_vma_unbind, vma may be
garbage, and we need to cache vma->obj before unlocking.
Changes since v1:
- Make trylock failing a WARN. (Matt)
- Remove double i915_vma_wait_for_bind() (Matt)
- Move atomic_set to right before mutex_unlock(), to make it more clear
they belong together. (Matt)
Signed-off-by: Maarten Lankhorst
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 2 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 6 +++
drivers/gpu/drm/i915/gt/intel_ggtt.c | 45 +--
drivers/gpu/drm/i915/i915_gem.c | 2 +
drivers/gpu/drm/i915/i915_vma.c | 27 ++-
drivers/gpu/drm/i915/i915_vma.h | 1 +
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 22 -
drivers/gpu/drm/i915/selftests/i915_vma.c | 8 ++--
10 files changed, 94 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 31c15e5fca95..9c555f6d1958 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -47,7 +47,7 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
goto err;
if (i915_vma_misplaced(vma, 0, alignment, 0)) {
- ret = i915_vma_unbind(vma);
+ ret = i915_vma_unbind_unlocked(vma);
if (ret) {
vma = ERR_PTR(ret);
goto err;
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 26f997c376a2..f36191ebf964 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -641,7 +641,7 @@ static int igt_mock_ppgtt_misaligned_dma(void *arg)
* pages.
*/
for (offset = 4096; offset < page_size; offset += 4096) {
- err = i915_vma_unbind(vma);
+ err = i915_vma_unbind_unlocked(vma);
if (err)
goto out_unpin;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index c08f766e6e15..c8ff8bf0986d 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -318,7 +318,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
int err;
if (drm_mm_node_allocated(&vma->node) && vma->node.start != addr) {
- err = i915_vma_unbind(vma);
+ err = i915_vma_unbind_unlocked(vma);
if (err)
return err;
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index f61356b72b1c..ba29767348be 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -166,7 +166,9 @@ static int check_partial_mapping(struct drm_i915_gem_object
*obj,
kunmap(p);
out:
+ i915_gem_object_lock(obj, NULL);
__i915_vma_put(vma);
+ i915_gem_object_unlock(obj);
return err;
}
@@ -261,7 +263,9 @@ static int check_partial_mappings(struct
drm_i915_gem_object *obj,
if (err)
return err;
+ i915_gem_object_lock(obj, NULL);
__i915_vma_put(vma);
+ i915_gem_object_unlock(obj);
if (igt_timeout(end_time,
"%s: timed out after tiling=%d stride=%d\n",
@@ -1352,7 +1356,9 @@ static int __igt_mmap_revoke(struct drm_i915_private
*i915,
* for other objects. Ergo we have to revoke the previous mmap PTE
* access as it no longer points to the same object.
*/
+ i915_gem_object_lock(obj, NULL);
err = i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE);
+ i915_gem_object_unlock(obj);
if (err) {
pr_err("Failed to unbind object!\n");
goto out_unmap;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index da7f54b6fa38..536b0995b595 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -129,22 +129,51 @@ void i915_ggtt_suspend_vm(struct i915_address_space *vm)
drm_WARN_ON(&vm->i915->drm, !vm->is_ggtt && !vm->is_dpt);
+retry:
+ i915_gem_drain_fr
[Intel-gfx] [PATCH v6 2/6] drm/i915: Add locking to i915_gem_evict_vm(), v2.
i915_gem_evict_vm will need to be able to evict objects that are
locked by the current ctx. By testing if the current context already
locked the object, we can do this correctly. This allows us to
evict the entire vm even if we already hold some objects' locks.
Previously, this was spread over several commits, but it makes
more sense to commit the changes to i915_gem_evict_vm separately
from the changes to i915_gem_evict_something() and
i915_gem_evict_for_node().
Changes since v1:
- Handle evicting dead objects better.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/i915_gem_evict.c | 32 +--
drivers/gpu/drm/i915/i915_gem_evict.h | 4 ++-
drivers/gpu/drm/i915/i915_vma.c | 7 +++-
.../gpu/drm/i915/selftests/i915_gem_evict.c | 10 --
6 files changed, 49 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index cf283b5f6ffe..4d832d6696b5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -767,7 +767,7 @@ static int eb_reserve(struct i915_execbuffer *eb)
case 1:
/* Too fragmented, unbind everything and retry */
mutex_lock(&eb->context->vm->mutex);
- err = i915_gem_evict_vm(eb->context->vm);
+ err = i915_gem_evict_vm(eb->context->vm, &eb->ww);
mutex_unlock(&eb->context->vm->mutex);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index fafd158e5313..a69787999d09 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -367,7 +367,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
if (vma == ERR_PTR(-ENOSPC)) {
ret = mutex_lock_interruptible(&ggtt->vm.mutex);
if (!ret) {
- ret = i915_gem_evict_vm(&ggtt->vm);
+ ret = i915_gem_evict_vm(&ggtt->vm, &ww);
mutex_unlock(&ggtt->vm.mutex);
}
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index 24eee0c2055f..91f82ecb9ef4 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -368,7 +368,7 @@ int i915_gem_evict_for_node(struct i915_address_space *vm,
* To clarify: This is for freeing up virtual address space, not for freeing
* memory in e.g. the shrinker.
*/
-int i915_gem_evict_vm(struct i915_address_space *vm)
+int i915_gem_evict_vm(struct i915_address_space *vm, struct i915_gem_ww_ctx
*ww)
{
int ret = 0;
@@ -389,24 +389,52 @@ int i915_gem_evict_vm(struct i915_address_space *vm)
do {
struct i915_vma *vma, *vn;
LIST_HEAD(eviction_list);
+ LIST_HEAD(locked_eviction_list);
list_for_each_entry(vma, &vm->bound_list, vm_link) {
if (i915_vma_is_pinned(vma))
continue;
+ /*
+* If we already own the lock, trylock fails. In case
+* the resv is shared among multiple objects, we still
+* need the object ref.
+*/
+ if (!kref_read(&vma->obj->base.refcount) ||
+ (ww && (dma_resv_locking_ctx(vma->obj->base.resv)
== &ww->ctx))) {
+ __i915_vma_pin(vma);
+ list_add(&vma->evict_link,
&locked_eviction_list);
+ continue;
+ }
+
+ if (!i915_gem_object_trylock(vma->obj, ww))
+ continue;
+
__i915_vma_pin(vma);
list_add(&vma->evict_link, &eviction_list);
}
- if (list_empty(&eviction_list))
+ if (list_empty(&eviction_list) &&
list_empty(&locked_eviction_list))
break;
ret = 0;
+ /* Unbind locked objects first, before unlocking the
eviction_list */
+ list_for_each_entry_safe(vma, vn, &locked_eviction_list,
evict_link) {
+ __i915_vma_unpin(vma);
+
+ if (ret == 0)
+ ret = __i915_vma_unbind(vma);
+ if (ret != -EINTR) /* "Get me out of here!" */
+ ret = 0;
+ }
+
list_for_each_entry_safe(vma, v
Re: [Intel-gfx] [PULL] drm-intel-next-fixes
On Thu, Jan 13, 2022 at 09:33:03AM +, Tvrtko Ursulin wrote: > > Hi Dave and Daniel, > > A few fixes for the merge window. > > One dealing with runtime PM handling on the PXP unbind path and a few > regarding the newly added TTM backend support. > > Regards, > > Tvrtko > > --- > > drm-intel-next-fixes-2022-01-13: > - Hold runtime PM wakelock during PXP unbind (Juston Li) > - Three fixes for the TTM backend fault handling (Matthew Auld) > - Make sure to unmap when purging in the TTM backend (Matthew Auld) > The following changes since commit c65fe9cbbfd61dbc12868f9ed4940c80fcb249e8: > > drm/i915/fbc: Remember to update FBC state even when not reallocating CFB > (2021-12-27 11:46:48 +0200) > > are available in the Git repository at: > > git://anongit.freedesktop.org/drm/drm-intel > tags/drm-intel-next-fixes-2022-01-13 Pulled, thanks. -Daniel > > for you to fetch changes up to 6ef295e34297433c78ea02dfcf1c649a769050bb: > > drm/i915/ttm: ensure we unmap when purging (2022-01-10 14:00:47 +) > > > - Hold runtime PM wakelock during PXP unbind (Juston Li) > - Three fixes for the TTM backend fault handling (Matthew Auld) > - Make sure to unmap when purging in the TTM backend (Matthew Auld) > > > Juston Li (1): > drm/i915/pxp: Hold RPM wakelock during PXP unbind > > Matthew Auld (4): > drm/i915: don't call free_mmap_offset when purging > drm/i915/ttm: only fault WILLNEED objects > drm/i915/ttm: add unmap_virtual callback > drm/i915/ttm: ensure we unmap when purging > > drivers/gpu/drm/i915/gem/i915_gem_mman.c | 3 +++ > drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 1 + > drivers/gpu/drm/i915/gem/i915_gem_pages.c | 1 - > drivers/gpu/drm/i915/gem/i915_gem_ttm.c| 27 > +- > drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 18 --- > drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +++- > 6 files changed, 38 insertions(+), 17 deletions(-) -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
[Intel-gfx] [PULL] drm-misc-fixes
Hi Dave, Daniel, Here's a few patches stuck in drm-misc-fixes for some time. Maxime drm-misc-fixes-2022-01-14: Two DT bindings fixes for meson, a device refcounting fix for sun4i, a probe fix for vga16fb, a locking fix for the CMA dma-buf heap and a compilation fix for ttm. The following changes since commit 67f74302f45d5d862f22ced3297624e50ac352f0: drm/nouveau: wait for the exclusive fence after the shared ones v2 (2021-12-21 09:24:31 +0100) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2022-01-14 for you to fetch changes up to 016017a195b86d9761e91cb052438bf71207a12f: drm/ttm: fix compilation on ARCH=um (2022-01-14 13:30:56 +0100) Two DT bindings fixes for meson, a device refcounting fix for sun4i, a probe fix for vga16fb, a locking fix for the CMA dma-buf heap and a compilation fix for ttm. Alexander Stein (2): dt-bindings: display: meson-vpu: Add missing amlogic,canvas property dt-bindings: display: meson-dw-hdmi: add missing sound-name-prefix property Javier Martinez Canillas (1): video: vga16fb: Only probe for EGA and VGA 16 color graphic cards Johannes Berg (1): drm/ttm: fix compilation on ARCH=um Miaoqian Lin (1): drm/sun4i: dw-hdmi: Fix missing put_device() call in sun8i_hdmi_phy_get Weizhao Ouyang (1): dma-buf: cma_heap: Fix mutex locking section .../bindings/display/amlogic,meson-dw-hdmi.yaml| 5 + .../bindings/display/amlogic,meson-vpu.yaml| 6 ++ drivers/dma-buf/heaps/cma_heap.c | 6 -- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 4 +++- drivers/gpu/drm/ttm/ttm_module.c | 4 +++- drivers/video/fbdev/vga16fb.c | 24 ++ 6 files changed, 45 insertions(+), 4 deletions(-) signature.asc Description: PGP signature
Re: [Intel-gfx] [PATCH v11 03/19] dyndbg: add write-to-tracefs code
On Fri, Jan 07, 2022 at 06:29:26AM +0100, Jim Cromie wrote:
> adds: dynamic_trace()
> uses trace_console() temporarily to issue printk:console event
> uses internal-ish __ftrace_trace_stack code:
> 4-context buffer stack, barriers per Steve
>
> call it from new funcs:
> dynamic_printk() - print to both syslog/tracefs
> dynamic_dev_printk() - dev-print to both syslog/tracefs
>
> These handle both _DPRINTK_FLAGS_PRINTK and _DPRINTK_FLAGS_TRACE
> cases, allowing to vsnprintf the message once and use it for both,
> skipping past the KERN_DEBUG character for tracing.
>
> Finally, adjust the callers: __dynamic_{pr_debug,{,net,ib}dev_dbg},
> replacing printk and dev_printk with the new funcs above.
>
> The _DPRINTK_FLAGS_TRACE flag character s 'T', so the following finds
> all callsites enabled for tracing:
>
> grep -P =p?T /proc/dynamic_debug/control
>
> Enabling debug-to-tracefs is 2 steps:
>
> # event enable
> echo 1 > /sys/kernel/tracing/events/dyndbg/enable
> # callsite enable
> echo module foo +T > /proc/dynamic_debug/control
>
> This patch,~1,~2 are based upon:
>
> https://lore.kernel.org/lkml/20200825153338.17061-1-vincent.whitchu...@axis.com/
>
> .. with simplification of temporarily reusing trace_console() rather
> than adding a new printk:dyndbg event. Soon, add 2 new events
> capturing the pr_debug & dev_dbg() args.
The example above does not match the code in this patch since the
dyndbg:* events are only added in a later patch. Perhaps you could
reorder this patch stack so that you don't use trace_console() in this
patch just to replace it with the new events in the next patch?
>
> CC: vincent.whitchu...@axis.com
> Signed-off-by: Jim Cromie
> ---
> .../admin-guide/dynamic-debug-howto.rst | 1 +
> lib/dynamic_debug.c | 155 +++---
> 2 files changed, 130 insertions(+), 26 deletions(-)
>
> diff --git a/Documentation/admin-guide/dynamic-debug-howto.rst
> b/Documentation/admin-guide/dynamic-debug-howto.rst
[...]
> @@ -723,29 +822,33 @@ void __dynamic_ibdev_dbg(struct _ddebug *descriptor,
> {
> struct va_format vaf;
> va_list args;
> + unsigned int flags;
>
> va_start(args, fmt);
>
> vaf.fmt = fmt;
> vaf.va = &args;
> + flags = descriptor->flags;
>
> if (ibdev && ibdev->dev.parent) {
> char buf[PREFIX_SIZE] = "";
>
> - dev_printk_emit(LOGLEVEL_DEBUG, ibdev->dev.parent,
> - "%s%s %s %s: %pV",
> - dynamic_emit_prefix(descriptor, buf),
> - dev_driver_string(ibdev->dev.parent),
> - dev_name(ibdev->dev.parent),
> - dev_name(&ibdev->dev),
> - &vaf);
> + dynamic_dev_printk(flags, ibdev->dev.parent,
> +"%s%s %s %s: %pV",
> +dynamic_emit_prefix(descriptor, buf),
> +dev_driver_string(ibdev->dev.parent),
> +dev_name(ibdev->dev.parent),
> +dev_name(&ibdev->dev),
> +&vaf);
> } else if (ibdev) {
> - printk(KERN_DEBUG "%s: %pV", dev_name(&ibdev->dev), &vaf);
> + dynamic_printk(flags, KERN_DEBUG "%s%s: %pV",
> +dev_name(&ibdev->dev), &vaf);
> } else {
> - printk(KERN_DEBUG "(NULL ib_device): %pV", &vaf);
> + dynamic_printk(flags, KERN_DEBUG "(NULL ip_device): %pV",
> +&vaf);
> }
>
> - va_end(args);
> +va_end(args);
This looks like an unintentional whitespace change?
Re: [Intel-gfx] [PATCH v11 01/19] dyndbg: add _DPRINTK_FLAGS_ENABLED
On Fri, Jan 07, 2022 at 06:29:24AM +0100, Jim Cromie wrote:
> #ifdef CONFIG_JUMP_LABEL
> - if (dp->flags & _DPRINTK_FLAGS_PRINT) {
> - if (!(modifiers->flags & _DPRINTK_FLAGS_PRINT))
> + if (dp->flags & _DPRINTK_FLAGS_ENABLED) {
> + if (!(modifiers->flags &
> _DPRINTK_FLAGS_ENABLED))
>
> static_branch_disable(&dp->key.dd_key_true);
> - } else if (modifiers->flags & _DPRINTK_FLAGS_PRINT)
> + } else if (modifiers->flags & _DPRINTK_FLAGS_ENABLED)
> static_branch_enable(&dp->key.dd_key_true);
> #endif
> dp->flags = newflags;
> --
> 2.33.1
>
I haven't tested it so I could be mistaken, but when
_DPRINTK_FLAGS_ENABLED gets two flags in the next patch, it looks like
this code still has the problem which I mentioned in
https://lore.kernel.org/lkml/20211209150910.ga23...@axis.com/?
| I noticed a bug inside the CONFIG_JUMP_LABEL handling (also present
| in the last version I posted) which should be fixed as part of the
| diff below (I've added a comment).
| [...]
| #ifdef CONFIG_JUMP_LABEL
| - if (dp->flags & _DPRINTK_FLAGS_PRINT) {
| - if (!(modifiers->flags & _DPRINTK_FLAGS_PRINT))
| + if (dp->flags & _DPRINTK_FLAGS_ENABLE) {
| + /*
| + * The newflags check is to ensure that the
| + * static branch doesn't get disabled in step
| + * 3:
| + *
| + * (1) +pf
| + * (2) +x
| + * (3) -pf
| + */
| + if (!(modifiers->flags & _DPRINTK_FLAGS_ENABLE)
&&
| + !(newflags & _DPRINTK_FLAGS_ENABLE)) {
|
static_branch_disable(&dp->key.dd_key_true);
| - } else if (modifiers->flags & _DPRINTK_FLAGS_PRINT)
| + }
| + } else if (modifiers->flags & _DPRINTK_FLAGS_ENABLE) {
| static_branch_enable(&dp->key.dd_key_true);
| + }
| #endif
Re: [Intel-gfx] [PATCH] drm/i915/display/vrr: Reset VRR capable property on a long hpd
On Wed, 12 Jan 2022, Manasi Navare wrote:
> With some VRR panels, user can turn VRR ON/OFF on the fly from the panel
> settings.
> When VRR is turned OFF ,sends a long HPD to the driver clearing the Ignore
> MSA bit
> in the DPCD. Currently the driver parses that onevery HPD but fails to reset
> the corresponding VRR Capable Connector property.
> Hence the userspace still sees this as VRR Capable panel which is incorrect.
>
> Fix this by explicitly resetting the connector property.
>
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index df2a7d86aef0..4f1418f02b76 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4539,15 +4539,24 @@ static int intel_dp_get_modes(struct drm_connector
> *connector)
> {
> struct intel_connector *intel_connector = to_intel_connector(connector);
> struct edid *edid;
> + struct drm_i915_private *dev_priv = to_i915(connector->dev);
Please call it "i915" for new stuff.
> int num_modes = 0;
>
> edid = intel_connector->detect_edid;
> if (edid) {
> num_modes = intel_connector_update_modes(connector, edid);
>
> - if (intel_vrr_is_capable(connector))
> + if (intel_vrr_is_capable(connector)) {
> + drm_dbg_kms(&dev_priv->drm, "VRR capable = TRUE for
> [CONNECTOR:%d:%s]\n",
> + connector->base.id, connector->name);
> drm_connector_set_vrr_capable_property(connector,
> true);
> + } else {
> + drm_dbg_kms(&dev_priv->drm, "VRR capable = false for
> [CONNECTOR:%d:%s]\n",
> + connector->base.id, connector->name);
> + drm_connector_set_vrr_capable_property(connector,
> +false);
> + }
Please don't repeat yourself! Also, prefer having [CONNECTOR:%d:%s] at
the beginning.
bool capable = intel_vrr_is_capable(connector);
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
connector->base.id, connector->name,
yesno(capable));
drm_connector_set_vrr_capable_property(connector, capable);
BR,
Jani.
> }
>
> /* Also add fixed mode, which may or may not be present in EDID */
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [RE]: [PATCH v3 10/10] vfio/ccw: Move the lifecycle of the struct vfio_ccw_private to the mdev
Hi Eric,
Hope you are back from new year holiday.:-) Have you got chane to consider
this patch?
Regards,
Yi Liu
On 2021/11/30 19:32, Liu, Yi L wrote:
From: Eric Farman
Sent: Tuesday, November 30, 2021 1:18 AM
On Wed, 2021-11-24 at 12:25 +, Liu, Yi L wrote:
From: Jason Gunthorpe
Sent: Fri, 1 Oct 2021 14:52:51 -0300
The css_driver's main purpose is to create/destroy the mdev and
relay the
shutdown, irq, sch_event, and chp_event css_driver ops to the
single
created vfio_device, if it exists.
Reframe the boundary where the css_driver domain switches to the
vfio
domain by using rcu to read and refcount the vfio_device out of the
sch's
drvdata. The mdev probe/remove will manage the drvdata of the
parent.
The vfio core code refcounting thus guarantees that when a
css_driver
callback is running the vfio_device is registered, simplifying the
understanding of the whole lifecycle.
Finally the vfio_ccw_private is allocated/freed during probe/remove
of the
mdev like any other vfio_device struct.
Hi Eric,
how about the status of this patch?
Hi YiLiu,
To be honest I never got this far in the series, as the middle of the
series got into some more involved rework than I had the bandwidth to
consider. Not sure I'll be able to do anything with it before the year
end holiday, but I've noted your interest in getting this in line with
the rest of vfio_device so I don't drop it too far down the list.
thanks. look forward to your further thoughts on it. e.g. the rework
things and gaps in this cleanup.
Regards,
Yi Liu
Thanks,
Eric
I found it is a good clean up to make
vfio ccw behave same with other vfio_device users. Also, I'd like to
do a clean up to consolidate the vfio_device allocation which needs the
vfio ccw private allocation happen in the mdev probe. So it would be nice
to build the cleanup based on this patch.
Regards,
Yi Liu
Signed-off-by: Jason Gunthorpe
---
drivers/s390/cio/vfio_ccw_drv.c | 67 ++---
drivers/s390/cio/vfio_ccw_ops.c | 40 +++--
drivers/s390/cio/vfio_ccw_private.h | 23 +-
3 files changed, 69 insertions(+), 61 deletions(-)
diff --git a/drivers/s390/cio/vfio_ccw_drv.c
b/drivers/s390/cio/vfio_ccw_drv.c
index 18ad047811d111..c5582fc9c46c9e 100644
--- a/drivers/s390/cio/vfio_ccw_drv.c
+++ b/drivers/s390/cio/vfio_ccw_drv.c
@@ -86,13 +86,19 @@ static void vfio_ccw_crw_todo(struct
work_struct *work)
*/
static void vfio_ccw_sch_irq(struct subchannel *sch)
{
- struct vfio_ccw_private *private = dev_get_drvdata(&sch->dev);
+ struct vfio_ccw_private *private = vfio_ccw_get_priv(sch);
+
+ /* IRQ should not be delivered after the mdev is destroyed */
+ if (WARN_ON(!private))
+ return;
inc_irq_stat(IRQIO_CIO);
vfio_ccw_fsm_event(private, VFIO_CCW_EVENT_INTERRUPT);
+ vfio_device_put(&private->vdev);
}
-static struct vfio_ccw_private *vfio_ccw_alloc_private(struct
subchannel *sch)
+struct vfio_ccw_private *vfio_ccw_alloc_private(struct mdev_device
*mdev,
+ struct subchannel *sch)
{
struct vfio_ccw_private *private;
@@ -100,6 +106,8 @@ static struct vfio_ccw_private
*vfio_ccw_alloc_private(struct subchannel *sch)
if (!private)
return ERR_PTR(-ENOMEM);
+ vfio_init_group_dev(&private->vdev, &mdev->dev,
+ &vfio_ccw_dev_ops);
private->sch = sch;
mutex_init(&private->io_mutex);
private->state = VFIO_CCW_STATE_CLOSED;
@@ -145,11 +153,12 @@ static struct vfio_ccw_private
*vfio_ccw_alloc_private(struct subchannel *sch)
kfree(private->cp.guest_cp);
out_free_private:
mutex_destroy(&private->io_mutex);
+ vfio_uninit_group_dev(&private->vdev);
kfree(private);
return ERR_PTR(-ENOMEM);
}
-static void vfio_ccw_free_private(struct vfio_ccw_private
*private)
+void vfio_ccw_free_private(struct vfio_ccw_private *private)
{
struct vfio_ccw_crw *crw, *temp;
@@ -164,14 +173,14 @@ static void vfio_ccw_free_private(struct
vfio_ccw_private *private)
kmem_cache_free(vfio_ccw_io_region, private->io_region);
kfree(private->cp.guest_cp);
mutex_destroy(&private->io_mutex);
- kfree(private);
+ vfio_uninit_group_dev(&private->vdev);
+ kfree_rcu(private, rcu);
}
static int vfio_ccw_sch_probe(struct subchannel *sch)
{
struct pmcw *pmcw = &sch->schib.pmcw;
- struct vfio_ccw_private *private;
- int ret = -ENOMEM;
+ int ret;
if (pmcw->qf) {
dev_warn(&sch->dev, "vfio: ccw: does not support QDIO:
%s\n",
@@ -179,15 +188,9 @@ static int vfio_ccw_sch_probe(struct
subchannel *sch)
return -ENODEV;
}
- private = vfio_ccw_alloc_private(sch);
- if (IS_ERR(private))
- return PTR_ERR(private);
-
- dev_set_drvdata(&sch->dev, private);
-
- ret = vfio_ccw_mdev_r
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Use i915_gem_object_pin_map_unlocked function for lmem allocation
== Series Details ==
Series: drm/i915: Use i915_gem_object_pin_map_unlocked function for lmem
allocation
URL : https://patchwork.freedesktop.org/series/98878/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11081_full -> Patchwork_22002_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (10 -> 13)
--
Additional (3): shard-rkl shard-dg1 shard-tglu
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22002_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_create@forked@smem:
- {shard-tglu}: NOTRUN -> [DMESG-FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-tglu-7/igt@gem_exec_create@for...@smem.html
* igt@i915_pm_dc@dc5-psr:
- {shard-tglu}: NOTRUN -> [SKIP][2] +2 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-tglu-1/igt@i915_pm...@dc5-psr.html
* igt@kms_cursor_legacy@pipe-a-torture-move:
- {shard-rkl}:NOTRUN -> [INCOMPLETE][3] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-rkl-5/igt@kms_cursor_leg...@pipe-a-torture-move.html
* igt@runner@aborted:
- {shard-tglu}: NOTRUN -> ([FAIL][4], [FAIL][5], [FAIL][6],
[FAIL][7]) ([i915#2722] / [i915#3002] / [i915#4312])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-tglu-6/igt@run...@aborted.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-tglu-6/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-tglu-7/igt@run...@aborted.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-tglu-4/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_22002_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_create@create-massive:
- shard-skl: NOTRUN -> [DMESG-WARN][8] ([i915#3002])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-skl6/igt@gem_cre...@create-massive.html
- shard-apl: NOTRUN -> [DMESG-WARN][9] ([i915#3002])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-apl1/igt@gem_cre...@create-massive.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [PASS][10] -> [TIMEOUT][11] ([i915#3063])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11081/shard-tglb2/igt@gem_...@in-flight-contexts-10ms.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-tglb2/igt@gem_...@in-flight-contexts-10ms.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-skl: NOTRUN -> [TIMEOUT][12] ([i915#3063])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-skl7/igt@gem_...@in-flight-contexts-immediate.html
* igt@gem_eio@kms:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#232])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11081/shard-tglb7/igt@gem_...@kms.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-tglb2/igt@gem_...@kms.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][15] -> [SKIP][16] ([i915#4525])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11081/shard-iclb4/igt@gem_exec_balan...@parallel-keep-in-fence.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-iclb3/igt@gem_exec_balan...@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-deadline:
- shard-skl: NOTRUN -> [FAIL][17] ([i915#2846])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-skl3/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][18] -> [FAIL][19] ([i915#2842])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11081/shard-tglb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-tglb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-kbl: NOTRUN -> [FAIL][20] ([i915#2842])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs1.html
- shard-iclb: NOTRUN -> [FAIL][21] ([i915#2842])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [PASS][22] -> [FAIL][23] ([i915#2842])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11081/shard-glk1/igt@gem_exec_fair@basic-p...@rcs0.html
[23]:
https://intel-gfx-ci.01.org/
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use i915_gem_object_pin_map_unlocked function for lmem allocation
== Series Details == Series: drm/i915: Use i915_gem_object_pin_map_unlocked function for lmem allocation URL : https://patchwork.freedesktop.org/series/98878/ State : success == Summary == CI Bug Log - changes from CI_DRM_11081 -> Patchwork_22002 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/index.html Participating hosts (46 -> 42) -- Additional (2): fi-kbl-x1275 bat-dg1-5 Missing(6): shard-tglu fi-bsw-cyan fi-kbl-guc fi-pnv-d510 shard-rkl shard-dg1 Known issues Here are the changes found in Patchwork_22002 that come from known issues: ### CI changes ### Possible fixes * boot: - fi-bxt-dsi: [FAIL][1] ([i915#4912]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11081/fi-bxt-dsi/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/fi-bxt-dsi/boot.html ### IGT changes ### Issues hit * igt@amdgpu/amd_prime@amd-to-i915: - fi-kbl-x1275: NOTRUN -> [SKIP][3] ([fdo#109271]) +28 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/fi-kbl-x1275/igt@amdgpu/amd_pr...@amd-to-i915.html * igt@gem_exec_gttfill@basic: - bat-dg1-5: NOTRUN -> [SKIP][4] ([i915#4086]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/bat-dg1-5/igt@gem_exec_gttf...@basic.html * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [PASS][5] -> [INCOMPLETE][6] ([i915#146]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11081/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [PASS][7] -> [FAIL][8] ([i915#4547]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11081/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html * igt@gem_huc_copy@huc-copy: - fi-kbl-x1275: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/fi-kbl-x1275/igt@gem_huc_c...@huc-copy.html - fi-bxt-dsi: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#2190]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/fi-bxt-dsi/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-bxt-dsi: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/fi-bxt-dsi/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - fi-kbl-x1275: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/fi-kbl-x1275/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg1-5: NOTRUN -> [SKIP][13] ([i915#4083]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/bat-dg1-5/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#4077]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/bat-dg1-5/igt@gem_mmap_...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#4079]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/bat-dg1-5/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-5: NOTRUN -> [SKIP][16] ([i915#1155]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-5: NOTRUN -> [SKIP][17] ([i915#4215]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/bat-dg1-5/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@tile-pitch-mismatch: - bat-dg1-5: NOTRUN -> [SKIP][18] ([i915#4212]) +7 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/bat-dg1-5/igt@kms_addfb_ba...@tile-pitch-mismatch.html * igt@kms_chamelium@dp-hpd-fast: - fi-bxt-dsi: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +8 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/fi-bxt-dsi/igt@kms_chamel...@dp-hpd-fast.html - bat-dg1-5: NOTRUN -> [SKIP][20] ([fdo#111827]) +8 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22002/bat-dg1-5/igt@kms_chamel...@dp-hpd-fast.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-x1275: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827])
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Use i915_gem_object_pin_map_unlocked function for lmem allocation
== Series Details == Series: drm/i915: Use i915_gem_object_pin_map_unlocked function for lmem allocation URL : https://patchwork.freedesktop.org/series/98878/ State : warning == Summary == $ dim checkpatch origin/drm-tip 578053b3b809 drm/i915: Use i915_gem_object_pin_map_unlocked function for lmem allocation -:36: CHECK:BRACES: Unbalanced braces around else statement #36: FILE: drivers/gpu/drm/i915/i915_vma.c:559: + } else total: 0 errors, 0 warnings, 1 checks, 51 lines checked
[Intel-gfx] [PATCH] drm/i915: Use i915_gem_object_pin_map_unlocked function for lmem allocation
Using i915_gem_object_pin_map_unlocked instead of
i915_gem_object_lmem_io_map, would eliminate the need
of using I915_BO_ALLOC_CONTIGUOUS, when calling
i915_vma_pin_iomap, because it supports non-contiguous
allocation as well.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/i915_vma.c | 27 ---
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 1f15c3298112..194ad92013f6 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -547,10 +547,16 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
* of pages, that way we can also drop the
* I915_BO_ALLOC_CONTIGUOUS when allocating the object.
*/
- if (i915_gem_object_is_lmem(vma->obj))
- ptr = i915_gem_object_lmem_io_map(vma->obj, 0,
- vma->obj->base.size);
- else
+ if (i915_gem_object_is_lmem(vma->obj)) {
+ ptr = (void __iomem *)
+ i915_gem_object_pin_map_unlocked(vma->obj,
+ I915_MAP_WC);
+ if (IS_ERR(ptr)) {
+ err = PTR_ERR(ptr);
+ goto err;
+ }
+ ptr = page_pack_bits(ptr, 1);
+ } else
ptr =
io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap,
vma->node.start,
vma->node.size);
@@ -560,7 +566,10 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
}
if (unlikely(cmpxchg(&vma->iomap, NULL, ptr))) {
- io_mapping_unmap(ptr);
+ if (page_unmask_bits(ptr))
+ __i915_gem_object_release_map(vma->obj);
+ else
+ io_mapping_unmap(ptr);
ptr = vma->iomap;
}
}
@@ -574,7 +583,7 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
i915_vma_set_ggtt_write(vma);
/* NB Access through the GTT requires the device to be awake. */
- return ptr;
+ return page_mask_bits(ptr);
err_unpin:
__i915_vma_unpin(vma);
@@ -1687,7 +1696,11 @@ static void __i915_vma_iounmap(struct i915_vma *vma)
if (vma->iomap == NULL)
return;
- io_mapping_unmap(vma->iomap);
+ if (page_unmask_bits(vma->iomap))
+ __i915_gem_object_release_map(vma->obj);
+ else
+ io_mapping_unmap(vma->iomap);
+
vma->iomap = NULL;
}
--
2.24.1.485.gad05a3d8e5
