[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Use drm_clflush* instead of clflush

[Patchwork]

== Series Details ==

Series: Use drm_clflush* instead of clflush
URL   : https://patchwork.freedesktop.org/series/100717/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush

[Patchwork]

== Series Details ==

Series: Use drm_clflush* instead of clflush
URL   : https://patchwork.freedesktop.org/series/100717/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
86596975e130 drm: Add arch arm64 for drm_clflush_virt_range
-:35: WARNING:LINE_SPACING: Missing a blank line after declarations
#35: FILE: drivers/gpu/drm/drm_cache.c:180:
+   void *end = addr + length;
+   caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);

total: 0 errors, 1 warnings, 0 checks, 11 lines checked
74d1a9bccc41 drm/i915/gt: Re-work intel_write_status_page
08cf76981869 drm/i915/gt: Drop invalidate_csb_entries
5568b6fef0f6 drm/i915/gt: Re-work reset_csb
78a5efb9813c drm/i915/: Re-work clflush_write32
43b085a28892 drm/i915/gt: replace cache_clflush_range

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Do not complain about stale reset notifications (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Do not complain about stale reset notifications (rev3)
URL   : https://patchwork.freedesktop.org/series/2/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11285 -> Patchwork_22406


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22406/index.html

Participating hosts (39 -> 39)
--

  Additional (1): fi-kbl-soraka 
  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22406 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271]) +8 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22406/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u:   NOTRUN -> [INCOMPLETE][2] ([i915#4547])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22406/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22406/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22406/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#2291])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22406/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][6] -> [INCOMPLETE][7] ([i915#3921])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22406/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22406/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22406/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-

  * Linux: CI_DRM_11285 -> Patchwork_22406

  CI-20190529: 20190529
  CI_DRM_11285: 937927c7022766ecf991e0071ae055412fb3805f @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6357: 6546304ecf053b9c5ec278ee3c210d2c6d50a3a6 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22406: b98ef7c5447cd12bfea91aa6f579a13404f62530 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

b98ef7c5447c drm/i915/guc: Do not complain about stale reset notifications

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22406/index.html

Re: [Intel-gfx] [PATCH v5 07/10] drm/i915/guc: Extract GuC error capture lists on G2H notification.

[Teres Alexis, Alan Previn]

Folks, a brief update: over the last few weeks of internal reviews,
testing and debug, another redesign has been implemented for this
patch (the extraction of error capture information). When
experiencing back to back error capture notifications (as part of
multiple dependent engine resets), if a forced full GT reset comes
in at the same time (from either the heartbeat or the user forced
reset debugfs or the igt_core cleanup) GT reset code takes the reset
lock and later calls guc_submission_reset_prepare. This function
flushes the ct processing worker queue for handling G2H events.
intel_guc_capture gets called to extract new error capture data from
the guc-log buffer but is actually in the midst of a reset ..
this causes lockdep issues (the memory shrinker vs reset locks).
Checking for uc->reset_in_progress is racy. That said, the
extraction code (this patch) needs to be modified to never allocate
memory for the output 'engine-instance-capture' node. Redesign is
complete where a pool of blank nodes are allocated up front and
re-used through the life of the driver. That will be part of the
next rev.

..alan

On 2/17/2022 11:21 AM, Umesh Nerlige Ramappa wrote:
On Sun, Feb 13, 2022 at 11:47:00AM -0800, Teres Alexis, Alan Previn 
wrote:

Thanks Umesh for reviewing the patch.
Am fixing all the rest but a couple of comments.
Responses to the latter and other questions below:

...alan


> +enum intel_guc_state_capture_event_status {
> +   INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_SUCCESS = 0x0,
> +   INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE = 0x1,
> +};
> +
> +#define INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_MASK 0x1

MASK is not needed. See below


Alan: Oh wait, actually the mask for the capture status is 0x00FF
(above is a typo). I'll fix above  mask and shall not change the
code below because the upper 24 bits of the first dword of this msg
is not defined.

...



> +static int guc_capture_buf_cnt(struct __guc_capture_bufstate *buf)
> +{
> +   if (buf->rd == buf->wr)
> +   return 0;
> +   if (buf->wr > buf->rd)
> +   return (buf->wr - buf->rd);
> +   return (buf->size - buf->rd) + buf->wr;
> +}

Is this a circular buffer shared between GuC and kmd? Since the size is
a power of 2, the above function is simply:


Alan: not this is not a circular buffer, so I'll keep the above
version.

static u32 guc_capture_buf_count(struct __guc_capture_bufstate *buf)
{
  return (buf->wr - buf->rd) & (buf->size - 1);
}



...


> +static int
> +guc_capture_log_remove_dw(struct intel_guc *guc, struct 
__guc_capture_bufstate *buf,

> + u32 *dw)
> +{
> +   struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> +   int tries = 2;
> +   int avail = 0;
> +   u32 *src_data;
> +
> +   if (!guc_capture_buf_cnt(buf))
> +   return 0;
> +
> +   while (tries--) {
> +   avail = guc_capture_buf_cnt_to_end(buf);

Shouldn't this be avail = guc_capture_buf_cnt(buf)?



Alan : The "guc_capture_log_get_[foo]" functions only call above
guc_capture_log_remove_dw when there isnt sufficient space to
copy out an entire structure from the space between the read pointer
and the end of the subregion (before the wrap-around). Those function
would populate the structure dword by dword by calling above func.
(NOTE the buffer and all error capture output structs are dword
aligned). Thats why above function tries twice and resets buf->rd = 0
if we find no space left at the end of the subregion (i.e. need to
wrap around) - which can only be done by calling
"guc_capture_buf_cnt_to_end".

...


> +
> +   /* Bookkeeping stuff */
> +   guc->log_state[GUC_CAPTURE_LOG_BUFFER].flush += 
log_buf_state_local.flush_to_file;

> +   new_overflow = intel_guc_check_log_buf_overflow(guc,
> + >log_state[GUC_CAPTURE_LOG_BUFFER],
> + full_count);

I am not sure how the overflow logic works here and whether it is
applicable to the error capture buffer. Is the guc log buffer one big
buffer where the error capture is just a portion of that buffer? If so,
is the wrap around applicable to just the errorcapture buffer or to the
whole buffer?

Alan: Yes, the guc log buffer is one big log buffer but there are 3 
independent

subregions within that are populated with different content and are used
in different ways and timings. Each guc-log subregion (general-logs,
crash-dump and error-capture) has it's own read and write pointers.


got it. I would also put this one detail in the commit message since 
it's not quickly inferred.






Also what is the wrap_offset field in struct guc_log_buffer_state?


Alan: This is the byte offset of a location in the subregion that is 
the 1st byte
after the last valid guc entry written by Guc firmware before a 
wraparound
was done. This would generate a tiny hole at the end of the subregion 
for better

cacheline alignment when flushing entries into the subregion. However,
the error-capture subregion is dword aligned and all of the output 
structures
used for error-capture are also dword 

[Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC HWCONFIG with documentation (rev6)

[Patchwork]

== Series Details ==

Series: GuC HWCONFIG with documentation (rev6)
URL   : https://patchwork.freedesktop.org/series/99787/
State : failure

== Summary ==

Applying: drm/i915/guc: Add fetch of hwconfig table
Applying: drm/i915/uapi: Add query for hwconfig blob
Applying: drm/i915/uapi: Add struct drm_i915_query_hwconfig_blob_item
Applying: drm/i915/guc: Verify hwconfig blob matches supported format
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
CONFLICT (content): Merge conflict in 
drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0004 drm/i915/guc: Verify hwconfig blob matches supported format
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Set "SF Partial Frame Enable" also on full update

[Hogander, Jouni]

Addressed comments from Jose and Paul in version 3.

On Thu, 2022-02-24 at 15:02 -0500, Lyude Paul wrote:
> Also - I realized this is missing an appropriate Fixes: tag for the
> commit
> that enabled PSR2 selective fetch on tigerlake in the first place
> 
> On Wed, 2022-02-23 at 17:32 +, Souza, Jose wrote:
> > On Wed, 2022-02-23 at 14:48 +0200, Jouni Högander wrote:
> > > Currently we are observing occasional screen flickering when
> > > PSR2 selective fetch is enabled. More specifically glitch seems
> > > to happen on full frame update when cursor moves to coords
> > > x = -1 or y = -1.
> > > 
> > > According to Bspec SF Single full frame should not be set if
> > > SF Partial Frame Enable is not set. This happened to be true for
> > > ADLP as PSR2_MAN_TRK_CTL_ENABLE is always set and for ADLP it's
> > > actually "SF Partial Frame Enable" (Bit 31).
> > > 
> > > Setting "SF Partial Frame Enable" bit also on full update seems
> > > to
> > > fix screen flickering.
> > > 
> > > Also make code more clear by setting PSR2_MAN_TRK_CTL_ENABLE
> > > only if not on ADLP as this bit doesn't exist in ADLP.
> > 
> > Bit exist but has another name.
> > 
> > > Bspec: 49274
> > > 
> > > v2: Fix Mihai Harpau email address
> > > 
> > > Reported-by: Lyude Paul 
> > > Cc: Mihai Harpau 
> > > Cc: José Roberto de Souza 
> > > Cc: Ville Syrjälä 
> > > Bugzilla: https://gitlab.freedesktop.org/drm/intel/-/issues/5077
> > > Signed-off-by: Jouni Högander 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_psr.c | 20
> > > ++--
> > >  drivers/gpu/drm/i915/i915_reg.h  |  1 +
> > >  2 files changed, 19 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 2e0b092f4b6b..90aca75e05e0 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -1439,6 +1439,13 @@ static inline u32
> > > man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private
> > >PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > >  }
> > >  
> > > +static inline u32 man_trk_ctl_partial_frame_bit_get(struct
> > > drm_i915_private *dev_priv)
> > > +{
> > > +   return IS_ALDERLAKE_P(dev_priv) ?
> > > +  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE :
> > > +  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > > +}
> > > +
> > >  static void psr_force_hw_tracking_exit(struct intel_dp
> > > *intel_dp)
> > >  {
> > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > @@ -1543,7 +1550,17 @@ static void psr2_man_trk_ctl_calc(struct
> > > intel_crtc_state *crtc_state,
> > >  {
> > > struct intel_crtc *crtc = to_intel_crtc(crtc_state-
> > > >uapi.crtc);
> > > struct drm_i915_private *dev_priv = to_i915(crtc-
> > > >base.dev);
> > > -   u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> > > +   u32 val = 0;
> > > +
> > > +   /*
> > > +* ADL_P doesn't have HW tracking nor manual tracking
> > > enable
> > > +* bit
> > > +*/
> > 
> > Nit: Unnecessary comment.
> > 
> > Reviewed-by: José Roberto de Souza 
> > 
> > > +   if (!IS_ALDERLAKE_P(dev_priv))
> > > +   val = PSR2_MAN_TRK_CTL_ENABLE;
> > > +
> > > +   /* SF partial frame enable has to be set even on full
> > > update */
> > > +   val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
> > >  
> > > if (full_update) {
> > > /*
> > > @@ -1563,7 +1580,6 @@ static void psr2_man_trk_ctl_calc(struct
> > > intel_crtc_state *crtc_state,
> > > } else {
> > > drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1
> > > % 4 ||
> > > clip->y2 % 4);
> > >  
> > > -   val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > > val |=
> > > PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4
> > > + 1);
> > > val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip-
> > > >y2 / 4 +
> > > 1);
> > > }
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 2b8a3086ed35..89bbb64e520d 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -2316,6 +2316,7 @@
> > >  #define 
> > > ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)   REG_FIELD_P
> > > REP(ADLP_
> > > PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> > >  #define 
> > > ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK
> > > (12, 0)
> > >  #define 
> > > ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_P
> > > REP(ADLP_
> > > PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> > > +#define 
> > > ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
> > >  #define 
> > > ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAMEREG_BIT(14)
> > >  #define 
> > > ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
> > >  

BR,

Jouni Högander

[Intel-gfx] [PATCH v3] drm/i915/psr: Set "SF Partial Frame Enable" also on full update

[Jouni Högander]

Currently we are observing occasional screen flickering when
PSR2 selective fetch is enabled. More specifically glitch seems
to happen on full frame update when cursor moves to coords
x = -1 or y = -1.

According to Bspec SF Single full frame should not be set if
SF Partial Frame Enable is not set. This happened to be true for
ADLP as PSR2_MAN_TRK_CTL_ENABLE is always set and for ADL_P it's
actually "SF Partial Frame Enable" (Bit 31).

Setting "SF Partial Frame Enable" bit also on full update seems to
fix screen flickering.

Also make code more clear by setting PSR2_MAN_TRK_CTL_ENABLE
only if not on ADL_P. Bit 31 has different meaning in ADL_P.

Bspec: 49274

v2: Fix Mihai Harpau email address
v3: Modify commit message and remove unnecessary comment

Fixes: 7f6002e58025 ("drm/i915/display: Enable PSR2 selective fetch by default")
Reported-by: Lyude Paul 
Cc: Mihai Harpau 
Cc: José Roberto de Souza 
Cc: Ville Syrjälä 
Bugzilla: https://gitlab.freedesktop.org/drm/intel/-/issues/5077
Signed-off-by: Jouni Högander 
Reviewed-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/display/intel_psr.c | 16 ++--
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 2e0b092f4b6b..b6b7bb5be5ae 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1439,6 +1439,13 @@ static inline u32 
man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private
   PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
 }
 
+static inline u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private 
*dev_priv)
+{
+   return IS_ALDERLAKE_P(dev_priv) ?
+  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE :
+  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
+}
+
 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
 {
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1543,7 +1550,13 @@ static void psr2_man_trk_ctl_calc(struct 
intel_crtc_state *crtc_state,
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   u32 val = PSR2_MAN_TRK_CTL_ENABLE;
+   u32 val = 0;
+
+   if (!IS_ALDERLAKE_P(dev_priv))
+   val = PSR2_MAN_TRK_CTL_ENABLE;
+
+   /* SF partial frame enable has to be set even on full update */
+   val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
 
if (full_update) {
/*
@@ -1563,7 +1576,6 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state 
*crtc_state,
} else {
drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || 
clip->y2 % 4);
 
-   val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a2f36ef91cec..b347a8921178 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2316,6 +2316,7 @@
 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)   
REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 
0)
 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) 
REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
+#define  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
 #define  ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAMEREG_BIT(14)
 #define  ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
 
-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v6,1/2] drm/vrr: Set VRR capable prop only if it is attached to connector

[Patchwork]

== Series Details ==

Series: series starting with [v6,1/2] drm/vrr: Set VRR capable prop only if it 
is attached to connector
URL   : https://patchwork.freedesktop.org/series/100712/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11285 -> Patchwork_22405


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/index.html

Participating hosts (39 -> 39)
--

  Additional (1): fi-kbl-soraka 
  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22405 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271]) +8 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_exec_suspend@basic-s0@smem:
- fi-glk-dsi: [PASS][2] -> [DMESG-WARN][3] ([i915#2943])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-glk-dsi/igt@gem_exec_suspend@basic...@smem.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/fi-glk-dsi/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-skl-6600u:   NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u:   NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live:
- fi-skl-6600u:   NOTRUN -> [FAIL][8] ([i915#4547])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/fi-skl-6600u/igt@i915_selft...@live.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#2291])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][10] -> [INCOMPLETE][11] ([i915#3921])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka:  NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u:   NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u:   NOTRUN -> [SKIP][14] ([fdo#109271]) +3 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u:   [PASS][15] -> [DMESG-FAIL][16] ([i915#295])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u:   [PASS][17] -> [DMESG-WARN][18] ([i915#295]) +10 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u:   NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#533])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22405/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#533])
   [20]: 

Re: [Intel-gfx] [PATCH v5 1/4] drm/i915/guc: Add fetch of hwconfig table

[Jordan Justen]

John Harrison  writes:

> On 2/22/2022 02:36, Jordan Justen wrote:
>> From: John Harrison 
>>
>> Implement support for fetching the hardware description table from the
>> GuC. The call is made twice - once without a destination buffer to
>> query the size and then a second time to fill in the buffer.
>>
>> Note that the table is only available on ADL-P and later platforms.
>>
>> v5 (of Jordan's posting):
>>   * Various changes made by Jordan and recommended by Michal
>> - Makefile ordering
>> - Adjust "struct intel_guc_hwconfig hwconfig" comment
>> - Set Copyright year to 2022 in intel_guc_hwconfig.c/.h
>> - Drop inline from hwconfig_to_guc()
>> - Replace hwconfig param with guc in __guc_action_get_hwconfig()
>> - Move zero size check into guc_hwconfig_discover_size()
>> - Change comment to say zero size offset/size is needed to get size
>> - Add has_guc_hwconfig to devinfo and drop has_table()
>> - Change drm_err to notice in __uc_init_hw() and use %pe
>>
>> Cc: Michal Wajdeczko 
>> Signed-off-by: Rodrigo Vivi 
>> Signed-off-by: John Harrison 
>> Reviewed-by: Matthew Brost 
>> Acked-by: Jon Bloomfield 
>> Signed-off-by: Jordan Justen 
>> ---
>>   
>> +ret = intel_guc_hwconfig_init(>hwconfig);
>> +if (ret)
>> +drm_notice(>drm, "Failed to retrieve hwconfig table: 
>> %pe\n",
> Why only drm_notice? As you are keen to point out, the UMDs won't work 
> if the table is not available. All the failure paths in your own 
> verification function are 'drm_err'. So why is it only a 'notice' if 
> there is no table at all?

This was requested by Michal in my v3 posting:

https://patchwork.freedesktop.org/patch/472936/?series=99787=3

I don't think that it should be a failure for i915 if it is unable to
read the table, or if the table read is invalid. I think it should be up
to the UMD to react to the missing hwconfig however they think is
appropriate, but I would like the i915 to guarantee & document the
format returned to userspace to whatever extent is feasible.

As you point out there is a discrepancy, and I think I should be
consistent with whatever is used here in my "drm/i915/guc: Verify
hwconfig blob matches supported format" patch.

I guess I'd tend to agree with Michal that "maybe drm_notice since we
continue probe", but I would go along with either if you two want to
discuss further.

> Note that this function is called as part of the reset path. The reset 
> path is not allowed to allocate memory. The table is stored in a 
> dynamically allocated object. Hence the IGT test failure. The table 
> query has to be done elsewhere at driver init time only.

Thanks for clearing this up. I did notice on dg2 that gpu resets were
causing a re-read of the hwconfig from GuC, but it definitely was not
clear to me that there would be a connection to the IGT failure that you
pointed out.

>
>> +   ERR_PTR(ret));
>> +
>>  ret = guc_enable_communication(guc);
>>  if (ret)
>>  goto err_log_capture;
>> @@ -562,6 +567,8 @@ static void __uc_fini_hw(struct intel_uc *uc)
>>  if (intel_uc_uses_guc_submission(uc))
>>  intel_guc_submission_disable(guc);
>>   
>> +intel_guc_hwconfig_fini(>hwconfig);
>> +
>>  __uc_sanitize(uc);
>>   }
>>   
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c 
>> b/drivers/gpu/drm/i915/i915_pci.c
>> index 76e590fcb903..1d31e35a5154 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -990,6 +990,7 @@ static const struct intel_device_info adl_p_info = {
>>  BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>>  .ppgtt_size = 48,
>>  .dma_mask_size = 39,
>> +.has_guc_hwconfig = 1,
> Who requested this change? It was previously done this way but the 
> instruction was that i915_pci.c is for hardware features only but that 
> this, as you seem extremely keen about pointing out at every 
> opportunity, is a software feature.

This was requested by Michal as well. I definitely agree it is a
software feature, but I was not aware that "i915_pci.c is for hardware
features only".

Michal, do you agree with this and returning to the previous method for
enabling the feature?

-Jordan

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v6,1/2] drm/vrr: Set VRR capable prop only if it is attached to connector

[Patchwork]

== Series Details ==

Series: series starting with [v6,1/2] drm/vrr: Set VRR capable prop only if it 
is attached to connector
URL   : https://patchwork.freedesktop.org/series/100712/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
783e65f81a2e drm/vrr: Set VRR capable prop only if it is attached to connector
b22db1344f58 drm/i915/display/vrr: Reset VRR capable property on a long hpd
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#10: 
With some VRR panels, user can turn VRR ON/OFF on the fly from the panel 
settings.

-:22: WARNING:TYPO_SPELLING: 'reseting' may be misspelled - perhaps 'resetting'?
#22: 
v5: Fixes the regression on older platforms by reseting the VRR
   

total: 0 errors, 2 warnings, 0 checks, 32 lines checked

[Intel-gfx] ✓ Fi.CI.BAT: success for Prep work for next GuC release (rev3)

[Patchwork]

== Series Details ==

Series: Prep work for next GuC release (rev3)
URL   : https://patchwork.freedesktop.org/series/99805/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11285 -> Patchwork_22404


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/index.html

Participating hosts (39 -> 41)
--

  Additional (3): fi-kbl-soraka fi-cml-u2 fi-pnv-d510 
  Missing(1): fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22404:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@workarounds:
- {bat-adlp-6}:   [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/bat-adlp-6/igt@i915_selftest@l...@workarounds.html

  
Known issues


  Here are the changes found in Patchwork_22404 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@memory-alloc:
- fi-cml-u2:  NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271]) +8 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
- fi-cml-u2:  NOTRUN -> [SKIP][5] ([i915#1208]) +1 similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-skl-6600u:   NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-cml-u2:  NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/fi-cml-u2/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-cml-u2:  NOTRUN -> [SKIP][10] ([i915#4613]) +3 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/fi-cml-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u:   NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live:
- fi-skl-6600u:   NOTRUN -> [FAIL][12] ([i915#4547])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/fi-skl-6600u/igt@i915_selft...@live.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-bsw-nick:[PASS][13] -> [DMESG-FAIL][14] ([i915#541])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-bsw-nick/igt@i915_selftest@live@gt_heartbeat.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/fi-bsw-nick/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][15] ([i915#1886] / [i915#2291])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][16] -> [INCOMPLETE][17] ([i915#3921])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka:  NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-cml-u2:  NOTRUN -> [SKIP][19] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22404/fi-cml-u2/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_chamelium@vga-edid-read:
- 

[Intel-gfx] ✓ Fi.CI.IGT: success for hda/i915: split wait for component binding

[Patchwork]

== Series Details ==

Series: hda/i915: split wait for component binding
URL   : https://patchwork.freedesktop.org/series/100661/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11277_full -> Patchwork_22391_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_22391_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-apl:  NOTRUN -> [DMESG-WARN][1] ([i915#4991])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/shard-apl8/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-kbl:  [PASS][2] -> [DMESG-WARN][3] ([i915#180]) +2 similar 
issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-kbl1/igt@gem_ctx_isolation@preservation...@rcs0.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/shard-kbl1/igt@gem_ctx_isolation@preservation...@rcs0.html

  * igt@gem_eio@kms:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#232])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-tglb6/igt@gem_...@kms.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/shard-tglb1/igt@gem_...@kms.html

  * igt@gem_exec_balancer@parallel-contexts:
- shard-kbl:  NOTRUN -> [DMESG-WARN][6] ([i915#5076])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/shard-kbl6/igt@gem_exec_balan...@parallel-contexts.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][7] -> [FAIL][8] ([i915#2846])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-glk2/igt@gem_exec_f...@basic-deadline.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/shard-glk8/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-glk8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/shard-glk1/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  [PASS][11] -> [FAIL][12] ([i915#2842]) +3 similar 
issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs0.html
- shard-apl:  [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl4/igt@gem_exec_fair@basic-n...@vcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/shard-apl3/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-apl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/shard-apl7/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@heavy-verify-random:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/shard-kbl3/igt@gem_lmem_swapp...@heavy-verify-random.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +5 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/shard-skl5/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-verify:
- shard-glk:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/shard-glk8/igt@gem_lmem_swapp...@parallel-random-verify.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][19] ([i915#2658])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/shard-apl4/igt@gem_pr...@exhaustion.html

  * igt@gen9_exec_parse@allowed-all:
- shard-apl:  [PASS][20] -> [DMESG-WARN][21] ([i915#1436] / 
[i915#716])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl8/igt@gen9_exec_pa...@allowed-all.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/shard-apl7/igt@gen9_exec_pa...@allowed-all.html

  * igt@gen9_exec_parse@basic-rejected:
- shard-iclb: NOTRUN -> [SKIP][22] ([i915#2856])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/shard-iclb7/igt@gen9_exec_pa...@basic-rejected.html

  * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind@edp-1-pipe-a:
- shard-skl:  [PASS][23] -> [DMESG-WARN][24] ([i915#1982])
   [23]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Prep work for next GuC release (rev3)

[Patchwork]

== Series Details ==

Series: Prep work for next GuC release (rev3)
URL   : https://patchwork.freedesktop.org/series/99805/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Allow users to disable PSR2 (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Allow users to disable PSR2 (rev2)
URL   : https://patchwork.freedesktop.org/series/100658/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11285 -> Patchwork_22403


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/index.html

Participating hosts (39 -> 40)
--

  Additional (2): fi-kbl-soraka fi-cml-u2 
  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22403 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@memory-alloc:
- fi-cml-u2:  NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271]) +8 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
- fi-cml-u2:  NOTRUN -> [SKIP][3] ([i915#1208]) +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_flink_basic@bad-flink:
- fi-skl-6600u:   NOTRUN -> [FAIL][4] ([i915#4547])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html

  * igt@gem_huc_copy@huc-copy:
- fi-cml-u2:  NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-cml-u2/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-cml-u2:  NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-cml-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#2291])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][10] -> [INCOMPLETE][11] ([i915#3921])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka:  NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-cml-u2:  NOTRUN -> [SKIP][13] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-cml-u2/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-cml-u2:  NOTRUN -> [SKIP][14] ([fdo#109278]) +1 similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-cml-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2:  NOTRUN -> [SKIP][15] ([fdo#109285])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-cml-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2:  NOTRUN -> [SKIP][16] ([fdo#109278] / [i915#533])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-cml-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
- fi-cml-u2:  NOTRUN -> [SKIP][18] ([i915#3301])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22403/fi-cml-u2/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}:   [DMESG-WARN][19] ([i915#3576]) -> [PASS][20]
   [19]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Optimize CSC updates for ilk+

[Patchwork]

== Series Details ==

Series: drm/i915: Optimize CSC updates for ilk+
URL   : https://patchwork.freedesktop.org/series/100693/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11285 -> Patchwork_22402


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/index.html

Participating hosts (39 -> 38)
--

  Additional (2): fi-kbl-soraka fi-pnv-d510 
  Missing(3): fi-bdw-samus fi-kbl-x1275 fi-kbl-guc 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22402:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@core_auth@basic-auth:
- {bat-jsl-2}:[PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/bat-jsl-2/igt@core_a...@basic-auth.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/bat-jsl-2/igt@core_a...@basic-auth.html

  * igt@i915_selftest@live@hangcheck:
- {bat-jsl-2}:[PASS][3] -> [DMESG-FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/bat-jsl-2/igt@i915_selftest@l...@hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/bat-jsl-2/igt@i915_selftest@l...@hangcheck.html

  
Known issues


  Here are the changes found in Patchwork_22402 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-bxt-dsi: [PASS][5] -> [FAIL][6] ([i915#4912])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-bxt-dsi/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-bxt-dsi/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][7] ([fdo#109271]) +8 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-skl-6600u:   NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u:   NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@gem:
- fi-blb-e6850:   [PASS][12] -> [DMESG-FAIL][13] ([i915#5026])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-blb-e6850/igt@i915_selftest@l...@gem.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-blb-e6850/igt@i915_selftest@l...@gem.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][14] ([i915#1886] / [i915#2291])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][15] -> [INCOMPLETE][16] ([i915#3921])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka:  NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u:   NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u:   NOTRUN -> [SKIP][19] ([fdo#109271]) +2 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-connector-state:
- fi-cfl-8109u:   [PASS][20] -> [DMESG-WARN][21] ([i915#165]) +1 
similar issue
   [20]: 

[Intel-gfx] [PATCH v12 0/6] Use drm_clflush* instead of clflush

[Michael Cheng]

This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.

v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
more patches to convert additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)

v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran

v4: Remove extra memory barriers

v5: s/cache_clflush_range/drm_clflush_virt_range

v6: Fix up "Drop invalidate_csb_entries" to use correct parameters. Also
added in arm64 support for drm_clflush_virt_range.

v7: Re-order patches, and use correct macro for dcache flush for arm64.

v8: Remove ifdef for asm/cacheflush.

v9: Rebased

v10: Replaced asm/cacheflush with linux/cacheflush

v11: Correctly get the sizeof certian addresses. Also rebased to the latest.

v12: Drop include of cacheflush.h and use caches_clean_inval_pou instead of
dcache_clean_inval_poc, since it is not exported for other modules to use.

Michael Cheng (6):
  drm: Add arch arm64 for drm_clflush_virt_range
  drm/i915/gt: Re-work intel_write_status_page
  drm/i915/gt: Drop invalidate_csb_entries
  drm/i915/gt: Re-work reset_csb
  drm/i915/: Re-work clflush_write32
  drm/i915/gt: replace cache_clflush_range

 drivers/gpu/drm/drm_cache.c   |  5 +
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c|  8 +++-
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c  | 12 +--
 drivers/gpu/drm/i915/gt/intel_engine.h| 13 
 .../drm/i915/gt/intel_execlists_submission.c  | 20 +++
 drivers/gpu/drm/i915/gt/intel_gtt.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c |  2 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  2 +-
 8 files changed, 28 insertions(+), 36 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH v12 6/6] drm/i915/gt: replace cache_clflush_range

[Michael Cheng]

Replace all occurrence of cache_clflush_range with drm_clflush_virt_range.
This will prevent compile errors on non-x86 platforms.

Signed-off-by: Michael Cheng 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++--
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_gtt.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c|  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c|  2 +-
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c 
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index f574da00eff1..c7bd5d71b03e 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -454,11 +454,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
pd = pdp->entry[gen8_pd_index(idx, 2)];
}
 
-   clflush_cache_range(vaddr, PAGE_SIZE);
+   drm_clflush_virt_range(vaddr, PAGE_SIZE);
vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 
1)));
}
} while (1);
-   clflush_cache_range(vaddr, PAGE_SIZE);
+   drm_clflush_virt_range(vaddr, PAGE_SIZE);
 
return idx;
 }
@@ -631,7 +631,7 @@ static void gen8_ppgtt_insert_huge(struct 
i915_address_space *vm,
}
} while (rem >= page_size && index < I915_PDES);
 
-   clflush_cache_range(vaddr, PAGE_SIZE);
+   drm_clflush_virt_range(vaddr, PAGE_SIZE);
 
/*
 * Is it safe to mark the 2M block as 64K? -- Either we have
@@ -647,7 +647,7 @@ static void gen8_ppgtt_insert_huge(struct 
i915_address_space *vm,
  I915_GTT_PAGE_SIZE_2M {
vaddr = px_vaddr(pd);
vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
-   clflush_cache_range(vaddr, PAGE_SIZE);
+   drm_clflush_virt_range(vaddr, PAGE_SIZE);
page_size = I915_GTT_PAGE_SIZE_64K;
 
/*
@@ -668,7 +668,7 @@ static void gen8_ppgtt_insert_huge(struct 
i915_address_space *vm,
for (i = 1; i < index; i += 16)
memset64(vaddr + i, encode, 15);
 
-   clflush_cache_range(vaddr, PAGE_SIZE);
+   drm_clflush_virt_range(vaddr, PAGE_SIZE);
}
}
 
@@ -722,7 +722,7 @@ static void gen8_ppgtt_insert_entry(struct 
i915_address_space *vm,
 
vaddr = px_vaddr(pt);
vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
-   clflush_cache_range([gen8_pd_index(idx, 0)], sizeof(*vaddr));
+   drm_clflush_virt_range([gen8_pd_index(idx, 0)], sizeof(*vaddr));
 }
 
 static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 89aef3ce53f0..d6f02dce45a0 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2823,7 +2823,7 @@ static void execlists_sanitize(struct intel_engine_cs 
*engine)
sanitize_hwsp(engine);
 
/* And scrub the dirty cachelines for the HWSP */
-   clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+   drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
 
intel_engine_reset_pinned_contexts(engine);
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index c548c193cd35..fc314946d426 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -268,7 +268,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, 
unsigned int count)
void *vaddr = __px_vaddr(p);
 
memset64(vaddr, val, count);
-   clflush_cache_range(vaddr, PAGE_SIZE);
+   drm_clflush_virt_range(vaddr, PAGE_SIZE);
 }
 
 static void poison_scratch_page(struct drm_i915_gem_object *scratch)
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c 
b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index d91e2beb7517..d8b94d638559 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -91,7 +91,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma,
u64 * const vaddr = __px_vaddr(pdma);
 
vaddr[idx] = encoded_entry;
-   clflush_cache_range([idx], sizeof(u64));
+   drm_clflush_virt_range([idx], sizeof(u64));
 }
 
 void
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b3a429a92c0d..89020706adc4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ 

[Intel-gfx] [PATCH v12 5/6] drm/i915/: Re-work clflush_write32

[Michael Cheng]

Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.

v2(Michael Cheng): Use sizeof(*addr) instead of sizeof(addr) to get the
   actual size of the page. Thanks to Matt Roper for
   pointing this out.

Signed-off-by: Michael Cheng 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 89aa0557ade1..0ca6c3d810da 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1333,10 +1333,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
 {
if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
-   if (flushes & CLFLUSH_BEFORE) {
-   clflushopt(addr);
-   mb();
-   }
+   if (flushes & CLFLUSH_BEFORE)
+   drm_clflush_virt_range(addr, sizeof(*addr));
 
*addr = value;
 
@@ -1348,7 +1346,7 @@ static void clflush_write32(u32 *addr, u32 value, 
unsigned int flushes)
 * to ensure ordering of clflush wrt to the system.
 */
if (flushes & CLFLUSH_AFTER)
-   clflushopt(addr);
+   drm_clflush_virt_range(addr, sizeof(*addr));
} else
*addr = value;
 }
-- 
2.25.1

[Intel-gfx] [PATCH v12 1/6] drm: Add arch arm64 for drm_clflush_virt_range

[Michael Cheng]

Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou
performs a flush by first performing a clean, follow by an invalidation
operation.

v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
dcache. Thanks Tvrtko for the suggestion.

v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h

v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a
symbol that could be use by other modules, thus use
caches_clean_inval_pou instead. Also this version
removes include for cacheflush, since its already
included base on architecture type.

Signed-off-by: Michael Cheng 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/drm_cache.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index c3e6e615bf09..81c28714f930 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length)
 
if (wbinvd_on_all_cpus())
pr_err("Timed out waiting for cache flush\n");
+
+#elif defined(CONFIG_ARM64)
+   void *end = addr + length;
+   caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
+
 #else
WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
 #endif
-- 
2.25.1

[Intel-gfx] [PATCH v12 3/6] drm/i915/gt: Drop invalidate_csb_entries

[Michael Cheng]

Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.

v2(Michael Cheng): Drop invalidate_csb_entries function and directly
   invoke drm_clflush_virt_range. Thanks to Tvrtko for the
   sugguestion.

v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range.
   Thanks to Tvrtko for pointing this out.

v4(Michael Cheng): Simplify >csb_status[0] to
   execlists->csb_status. Thanks to Matt Roper for the
   suggestion.

Signed-off-by: Michael Cheng 
Reviewed-by: Matt Roper 
---
 .../gpu/drm/i915/gt/intel_execlists_submission.c| 13 -
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 961d795220a3..e5e73a1b2e4e 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * 
const execlists,
return inactive;
 }
 
-static void invalidate_csb_entries(const u64 *first, const u64 *last)
-{
-   clflush((void *)first);
-   clflush((void *)last);
-}
-
 /*
  * Starting with Gen12, the status has a new format:
  *
@@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct 
i915_request **inactive)
 * the wash as hardware, working or not, will need to do the
 * invalidation before.
 */
-   invalidate_csb_entries([0], [num_entries - 1]);
+   drm_clflush_virt_range([0], num_entries * sizeof(buf[0]));
 
/*
 * We assume that any event reflects a change in context flow
@@ -2783,8 +2777,9 @@ static void reset_csb_pointers(struct intel_engine_cs 
*engine)
 
/* Check that the GPU does indeed update the CSB entries! */
memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
-   invalidate_csb_entries(>csb_status[0],
-  >csb_status[reset_value]);
+   drm_clflush_virt_range(execlists->csb_status,
+  execlists->csb_size *
+  sizeof(execlists->csb_status));
 
/* Once more for luck and our trusty paranoia */
ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
-- 
2.25.1

[Intel-gfx] [PATCH v12 4/6] drm/i915/gt: Re-work reset_csb

[Michael Cheng]

Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.

v2(Michael Cheng): Remove extra clflush

v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
   takes care of it.

v4(Michael Cheng): Get the size of value and not the size of the pointer
   when passing in execlists->csb_write. Thanks to Matt
   Roper for pointing this out.

Signed-off-by: Michael Cheng 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index e5e73a1b2e4e..89aef3ce53f0 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2945,9 +2945,8 @@ reset_csb(struct intel_engine_cs *engine, struct 
i915_request **inactive)
 {
struct intel_engine_execlists * const execlists = >execlists;
 
-   mb(); /* paranoia: read the CSB pointers from after the reset */
-   clflush(execlists->csb_write);
-   mb();
+   drm_clflush_virt_range(execlists->csb_write,
+  sizeof(execlists->csb_write[0]));
 
inactive = process_csb(engine, inactive); /* drain preemption events */
 
-- 
2.25.1

[Intel-gfx] [PATCH v12 2/6] drm/i915/gt: Re-work intel_write_status_page

[Michael Cheng]

Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.

Signed-off-by: Michael Cheng 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h 
b/drivers/gpu/drm/i915/gt/intel_engine.h
index be4b1e65442f..818468e0a02e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -4,6 +4,7 @@
 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, 
int reg, u32 value)
 * of extra paranoia to try and ensure that the HWS takes the value
 * we give and that it doesn't end up trapped inside the CPU!
 */
-   if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
-   mb();
-   clflush(>status_page.addr[reg]);
-   engine->status_page.addr[reg] = value;
-   clflush(>status_page.addr[reg]);
-   mb();
-   } else {
-   WRITE_ONCE(engine->status_page.addr[reg], value);
-   }
+   drm_clflush_virt_range(>status_page.addr[reg], sizeof(value));
+   WRITE_ONCE(engine->status_page.addr[reg], value);
+   drm_clflush_virt_range(>status_page.addr[reg], sizeof(value));
 }
 
 /*
-- 
2.25.1

[Intel-gfx] [PATCH] drm/i915/guc: Add fetch of hwconfig table

[John . C . Harrison]

From: John Harrison 

Implement support for fetching the hardware description table from the
GuC. The call is made twice - once without a destination buffer to
query the size and then a second time to fill in the buffer.

The table is stored in the GT structure so that it can be fetched once
at driver load time. Keeping inside a GuC structure would mean it
would be release and reloaded on a GuC reset (part of a full GT
reset). However, the table does not change just because the GT has been
reset and the GuC reloaded. Also, dynamic memory allocations inside
the reset path are a problem.

Note that the table is only available on ADL-P and later platforms.

v2: Move to GT level to avoid memory allocation during reset path (and
unnecessary re-read of the table on a reset).

Cc: Michal Wajdeczko 
Signed-off-by: Rodrigo Vivi 
Signed-off-by: John Harrison 
Reviewed-by: Matthew Brost  (v1)

Mush: hwconf
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/gt/intel_gt.c|   6 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h  |   4 +
 drivers/gpu/drm/i915/gt/intel_hwconfig.h  |  21 +++
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |   1 +
 .../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h   |   4 +
 .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c   | 160 ++
 7 files changed, 197 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_hwconfig.h
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 713f59a88312..8da4a1fe8b36 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -193,6 +193,7 @@ i915-y += gt/uc/intel_uc.o \
  gt/uc/intel_guc_rc.o \
  gt/uc/intel_guc_slpc.o \
  gt/uc/intel_guc_submission.o \
+ gt/uc/intel_guc_hwconfig.o \
  gt/uc/intel_huc.o \
  gt/uc/intel_huc_debugfs.o \
  gt/uc/intel_huc_fw.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index e6f6bf7c3926..2ad55d7ffe53 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -711,6 +711,11 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_uc_init;
 
+   /* Table failure is bad but not currently fatal */
+   err = intel_gt_init_hwconfig(gt);
+   if (err)
+   drm_err(>i915->drm, "Failed to retrieve hwconfig table: 
%d\n", err);
+
err = __engines_record_defaults(gt);
if (err)
goto err_gt;
@@ -792,6 +797,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
intel_gt_pm_fini(gt);
intel_gt_fini_scratch(gt);
intel_gt_fini_buffer_pool(gt);
+   intel_gt_fini_hwconfig(gt);
 }
 
 void intel_gt_driver_late_release(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index f20687796490..514b92cff9b0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -20,6 +20,7 @@
 #include "i915_vma.h"
 #include "intel_engine_types.h"
 #include "intel_gt_buffer_pool_types.h"
+#include "intel_hwconfig.h"
 #include "intel_llc_types.h"
 #include "intel_reset_types.h"
 #include "intel_rc6_types.h"
@@ -199,6 +200,9 @@ struct intel_gt {
struct sseu_dev_info sseu;
 
unsigned long mslice_mask;
+
+   /** @hwconfig: hardware configuration data */
+   struct intel_hwconfig hwconfig;
} info;
 
struct {
diff --git a/drivers/gpu/drm/i915/gt/intel_hwconfig.h 
b/drivers/gpu/drm/i915/gt/intel_hwconfig.h
new file mode 100644
index ..322290780b67
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_hwconfig.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef _INTEL_HWCONFIG_H_
+#define _INTEL_HWCONFIG_H_
+
+#include 
+
+struct intel_gt;
+
+struct intel_hwconfig {
+   u32 size;
+   void *ptr;
+};
+
+int intel_gt_init_hwconfig(struct intel_gt *gt);
+void intel_gt_fini_hwconfig(struct intel_gt *gt);
+
+#endif /* _INTEL_HWCONFIG_H_ */
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 7afdadc7656f..a9a329e53c35 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -129,6 +129,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
INTEL_GUC_ACTION_SETUP_PC_GUCRC = 0x3004,
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
+   INTEL_GUC_ACTION_GET_HWCONFIG = 0x4100,
INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h 

Re: [Intel-gfx] [PATCH v5 1/4] drm/i915/guc: Add fetch of hwconfig table

[John Harrison]

On 2/22/2022 02:36, Jordan Justen wrote:

From: John Harrison 

Implement support for fetching the hardware description table from the
GuC. The call is made twice - once without a destination buffer to
query the size and then a second time to fill in the buffer.

Note that the table is only available on ADL-P and later platforms.

v5 (of Jordan's posting):
  * Various changes made by Jordan and recommended by Michal
- Makefile ordering
- Adjust "struct intel_guc_hwconfig hwconfig" comment
- Set Copyright year to 2022 in intel_guc_hwconfig.c/.h
- Drop inline from hwconfig_to_guc()
- Replace hwconfig param with guc in __guc_action_get_hwconfig()
- Move zero size check into guc_hwconfig_discover_size()
- Change comment to say zero size offset/size is needed to get size
- Add has_guc_hwconfig to devinfo and drop has_table()
- Change drm_err to notice in __uc_init_hw() and use %pe

Cc: Michal Wajdeczko 
Signed-off-by: Rodrigo Vivi 
Signed-off-by: John Harrison 
Reviewed-by: Matthew Brost 
Acked-by: Jon Bloomfield 
Signed-off-by: Jordan Justen 
---
  drivers/gpu/drm/i915/Makefile |   1 +
  .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |   1 +
  .../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h   |   4 +
  drivers/gpu/drm/i915/gt/uc/intel_guc.h|   3 +
  .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c   | 145 ++
  .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.h   |  19 +++
  drivers/gpu/drm/i915/gt/uc/intel_uc.c |   7 +
  drivers/gpu/drm/i915/i915_pci.c   |   1 +
  drivers/gpu/drm/i915/intel_device_info.h  |   1 +
  9 files changed, 182 insertions(+)
  create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
  create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e9ce09620eb5..661f1afb51d7 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -188,6 +188,7 @@ i915-y += gt/uc/intel_uc.o \
  gt/uc/intel_guc_ct.o \
  gt/uc/intel_guc_debugfs.o \
  gt/uc/intel_guc_fw.o \
+ gt/uc/intel_guc_hwconfig.o \
  gt/uc/intel_guc_log.o \
  gt/uc/intel_guc_log_debugfs.o \
  gt/uc/intel_guc_rc.o \
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index fe5d7d261797..4a61c819f32b 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -137,6 +137,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
INTEL_GUC_ACTION_SETUP_PC_GUCRC = 0x3004,
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
+   INTEL_GUC_ACTION_GET_HWCONFIG = 0x4100,
INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
index 488b6061ee89..f9e2a6aaef4a 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
@@ -8,6 +8,10 @@
  
  enum intel_guc_response_status {

INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
+   INTEL_GUC_RESPONSE_NOT_SUPPORTED = 0x20,
+   INTEL_GUC_RESPONSE_NO_ATTRIBUTE_TABLE = 0x201,
+   INTEL_GUC_RESPONSE_NO_DECRYPTION_KEY = 0x202,
+   INTEL_GUC_RESPONSE_DECRYPTION_FAILED = 0x204,
INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
  };
  
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h

index f9240d4baa69..2058eb8c3d0c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -13,6 +13,7 @@
  #include "intel_guc_fw.h"
  #include "intel_guc_fwif.h"
  #include "intel_guc_ct.h"
+#include "intel_guc_hwconfig.h"
  #include "intel_guc_log.h"
  #include "intel_guc_reg.h"
  #include "intel_guc_slpc_types.h"
@@ -37,6 +38,8 @@ struct intel_guc {
struct intel_guc_ct ct;
/** @slpc: sub-structure containing SLPC related data and objects */
struct intel_guc_slpc slpc;
+   /** @hwconfig: data related to hardware configuration KLV blob */
+   struct intel_guc_hwconfig hwconfig;
  
  	/** @sched_engine: Global engine used to submit requests to GuC */

struct i915_sched_engine *sched_engine;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
new file mode 100644
index ..ad289603460c
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "gt/intel_gt.h"
+#include "i915_drv.h"
+#include "i915_memcpy.h"
+#include "intel_guc_hwconfig.h"
+
+static struct intel_guc *hwconfig_to_guc(struct 

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for GuC HWCONFIG with documentation (rev5)

[John Harrison]

On 2/22/2022 04:03, Patchwork wrote:

Project List - Patchwork *Patch Details*
*Series:*   GuC HWCONFIG with documentation (rev5)
*URL:*  https://patchwork.freedesktop.org/series/99787/
*State:*success
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22348/index.html



  CI Bug Log - changes from CI_DRM_11264 -> Patchwork_22348


Summary

*SUCCESS*

No regressions found.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22348/index.html



Participating hosts (44 -> 43)

Additional (4): bat-dg2-8 fi-icl-u2 fi-bdw-5557u fi-pnv-d510
Missing (5): fi-kbl-soraka shard-tglu fi-bsw-cyan shard-rkl shard-dg1


Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_22348:



  IGT changes


Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

 *

igt@i915_hangman@error-state-basic:

  o {bat-adlp-6}: PASS


-> DMESG-WARN



Despite the 'success' subject line, this is a failure caused by this 
patch set and it must be fixed before it can be merged.


John.


 *
 *

igt@i915_selftest@live:

  o {fi-tgl-dsi}: NOTRUN -> FAIL




Known issues

Here are the changes found in Patchwork_22348 that come from known issues:


  IGT changes


Issues hit

 *

igt@amdgpu/amd_cs_nop@fork-gfx0:

  o fi-icl-u2: NOTRUN -> SKIP


(fdo#109315
) +17
similar issues
 *

igt@gem_exec_suspend@basic-s3@smem:

  o fi-bdw-5557u: NOTRUN -> INCOMPLETE


(i915#146 )
 *

igt@gem_huc_copy@huc-copy:

 o

fi-skl-6600u: NOTRUN -> SKIP


(fdo#109271
 /
i915#2190 )

 o

fi-pnv-d510: NOTRUN -> SKIP


(fdo#109271
) +39
similar issues

 o

fi-icl-u2: NOTRUN -> SKIP


(i915#2190 )

 *

igt@gem_lmem_swapping@parallel-random-engines:

  o fi-icl-u2: NOTRUN -> SKIP


(i915#4613
) +3
similar issues
 *

igt@gem_lmem_swapping@verify-random:

  o fi-skl-6600u: NOTRUN -> SKIP


(fdo#109271
 /
i915#4613
) +3
similar issues
 *

igt@i915_selftest@live@requests:

 o

fi-blb-e6850: PASS


-> DMESG-FAIL


(i915#5026 )

 o

fi-pnv-d510: NOTRUN -> DMESG-FAIL


(i915#2927 )

 *

igt@kms_chamelium@hdmi-hpd-fast:

  o fi-icl-u2: NOTRUN -> SKIP


(fdo#111827
) +8
similar issues
 *

igt@kms_chamelium@vga-edid-read:

  o fi-skl-6600u: NOTRUN -> SKIP

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Check stolen memory size before calling drm_mm_init (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Check stolen memory size before calling drm_mm_init (rev4)
URL   : https://patchwork.freedesktop.org/series/99917/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11277_full -> Patchwork_22390_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_22390_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-apl:  NOTRUN -> [DMESG-WARN][1] ([i915#4991])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-apl7/igt@gem_cre...@create-massive.html

  * igt@gem_eio@kms:
- shard-tglb: [PASS][2] -> [FAIL][3] ([i915#232])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-tglb6/igt@gem_...@kms.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-tglb2/igt@gem_...@kms.html

  * igt@gem_exec_balancer@parallel-contexts:
- shard-kbl:  NOTRUN -> [DMESG-WARN][4] ([i915#5076])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-kbl3/igt@gem_exec_balan...@parallel-contexts.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][5] -> [FAIL][6] ([i915#2846])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-glk2/igt@gem_exec_f...@basic-deadline.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-glk2/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk:  [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-glk8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-glk7/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-kbl3/igt@gem_exec_fair@basic-n...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-kbl6/igt@gem_exec_fair@basic-n...@rcs0.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-apl:  NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-apl8/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@heavy-verify-random:
- shard-kbl:  NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-kbl3/igt@gem_lmem_swapp...@heavy-verify-random.html
- shard-skl:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +4 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-skl9/igt@gem_lmem_swapp...@heavy-verify-random.html

  * igt@gem_lmem_swapping@parallel-random-verify:
- shard-glk:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-glk2/igt@gem_lmem_swapp...@parallel-random-verify.html

  * igt@gem_pread@exhaustion:
- shard-iclb: NOTRUN -> [WARN][15] ([i915#2658])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-iclb3/igt@gem_pr...@exhaustion.html

  * igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#4270])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-iclb3/igt@gem_...@protected-encrypted-src-copy-not-readible.html

  * igt@gem_workarounds@suspend-resume-context:
- shard-apl:  [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +1 
similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl8/igt@gem_workarou...@suspend-resume-context.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-apl2/igt@gem_workarou...@suspend-resume-context.html

  * igt@gen7_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109289])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-iclb3/igt@gen7_exec_pa...@batch-without-end.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl:  NOTRUN -> [FAIL][20] ([i915#3763])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-skl6/igt@kms_big...@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-apl:  NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3777])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22390/shard-apl3/igt@kms_big...@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * 

[Intel-gfx] [PATCH v3] drm/i915/guc: Do not complain about stale reset notifications

[John . C . Harrison]

From: John Harrison 

It is possible for reset notifications to arrive for a context that is
in the process of being banned. So don't flag these as an error, just
report it as informational (because it is still useful to know that
resets are happening even if they are being ignored).

v2: Better wording for the message (review feedback from Tvrtko).
v3: Fix rebase issue (review feedback from Daniele).

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b3a429a92c0d..d39d74d39794 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4022,10 +4022,9 @@ static void guc_handle_context_reset(struct intel_guc 
*guc,
capture_error_state(guc, ce);
guc_context_replay(ce);
} else {
-   drm_err(_to_gt(guc)->i915->drm,
-   "Invalid GuC engine reset notificaion for 0x%04X on %s: 
banned = %d, blocked = %d",
-   ce->guc_id.id, ce->engine->name, 
intel_context_is_banned(ce),
-   context_blocked(ce));
+   drm_info(_to_gt(guc)->i915->drm,
+"Ignoring context reset notification of banned context 
0x%04X on %s",
+ce->guc_id.id, ce->engine->name);
}
 }
 
-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev3)
URL   : https://patchwork.freedesktop.org/series/100633/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11284 -> Patchwork_22401


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22401/index.html

Participating hosts (42 -> 36)
--

  Missing(6): fi-kbl-soraka fi-bsw-cyan fi-snb-2520m fi-pnv-d510 bat-jsl-2 
fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22401 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][1] -> [INCOMPLETE][2] ([i915#3921])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11284/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22401/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u:   [PASS][3] -> [DMESG-WARN][4] ([i915#295]) +12 similar 
issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11284/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22401/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- {bat-adlp-6}:   [DMESG-WARN][5] ([i915#3576]) -> [PASS][6] +2 similar 
issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11284/bat-adlp-6/igt@i915_pm_...@module-reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22401/bat-adlp-6/igt@i915_pm_...@module-reload.html

  
 Warnings 

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-6:  [DMESG-FAIL][7] ([i915#4957]) -> [DMESG-FAIL][8] 
([i915#4494] / [i915#4957])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11284/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22401/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068


Build changes
-

  * Linux: CI_DRM_11284 -> Patchwork_22401

  CI-20190529: 20190529
  CI_DRM_11284: 22ba895f56529e4d9c0533f71b1f8eb8a1b6f86e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6357: 6546304ecf053b9c5ec278ee3c210d2c6d50a3a6 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22401: f759cb0833e1f477bd4f1c7fe435865f6bc69009 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f759cb0833e1 drm/i915/psr: Set "SF Partial Frame Enable" also on full update

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22401/index.html

[Intel-gfx] [PATCH v6 1/2] drm/vrr: Set VRR capable prop only if it is attached to connector

[Manasi Navare]

VRR capable property is not attached by default to the connector
It is attached only if VRR is supported.
So if the driver tries to call drm core set prop function without
it being attached that causes NULL dereference.

Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/drm_connector.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index a50c82bc2b2f..76a8c707c34b 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -2330,6 +2330,9 @@ EXPORT_SYMBOL(drm_connector_atomic_hdr_metadata_equal);
 void drm_connector_set_vrr_capable_property(
struct drm_connector *connector, bool capable)
 {
+   if (!connector->vrr_capable_property)
+   return;
+
drm_object_property_set_value(>base,
  connector->vrr_capable_property,
  capable);
-- 
2.19.1

[Intel-gfx] [PATCH v6 2/2] drm/i915/display/vrr: Reset VRR capable property on a long hpd

[Manasi Navare]

With some VRR panels, user can turn VRR ON/OFF on the fly from the panel 
settings.
When VRR is turned OFF ,sends a long HPD to the driver clearing the Ignore MSA 
bit
in the DPCD. Currently the driver parses that onevery HPD but fails to reset
the corresponding VRR Capable Connector property.
Hence the userspace still sees this as VRR Capable panel which is incorrect.

Fix this by explicitly resetting the connector property.

v2: Reset vrr capable if status == connector_disconnected
v3: Use i915 and use bool vrr_capable (Jani Nikula)
v4: Move vrr_capable to after update modes call (Jani N)
Remove the redundant comment (Jan N)
v5: Fixes the regression on older platforms by reseting the VRR
only if HAS_VRR
v6: Remove the checks from driver, add in drm core before
setting VRR prop (Ville)

Cc: Jani Nikula 
Cc: Ville Syrjälä 
Fixes: 390a1f8beb87 ("Revert "drm/i915/display/vrr: Reset VRR capable property 
on a long hpd")
Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 15 +++
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1046e7fe310a..f96123b56935 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4455,6 +4455,10 @@ intel_dp_detect(struct drm_connector *connector,
memset(_dp->compliance, 0, sizeof(intel_dp->compliance));
memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
 
+   /* Reset VRR Capable property on disconnect */
+   drm_connector_set_vrr_capable_property(connector,
+  false);
+
if (intel_dp->is_mst) {
drm_dbg_kms(_priv->drm,
"MST device may have disappeared %d vs 
%d\n",
@@ -4569,15 +4573,18 @@ static int intel_dp_get_modes(struct drm_connector 
*connector)
 {
struct intel_connector *intel_connector = to_intel_connector(connector);
struct edid *edid;
+   struct drm_i915_private *i915 = to_i915(connector->dev);
int num_modes = 0;
 
edid = intel_connector->detect_edid;
if (edid) {
-   num_modes = intel_connector_update_modes(connector, edid);
+   bool vrr_capable;
 
-   if (intel_vrr_is_capable(connector))
-   drm_connector_set_vrr_capable_property(connector,
-  true);
+   num_modes = intel_connector_update_modes(connector, edid);
+   vrr_capable = intel_vrr_is_capable(connector);
+   drm_dbg_kms(>drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
+   connector->base.id, connector->name, 
yesno(vrr_capable));
+   drm_connector_set_vrr_capable_property(connector, vrr_capable);
}
 
/* Also add fixed mode, which may or may not be present in EDID */
-- 
2.19.1

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev3)
URL   : https://patchwork.freedesktop.org/series/100633/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: Skip output init on PHY calibration failure

[Patchwork]

== Series Details ==

Series: drm/i915/dg2: Skip output init on PHY calibration failure
URL   : https://patchwork.freedesktop.org/series/100650/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11277_full -> Patchwork_22388_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 10)
--

  Missing(1): shard-tglu 

Known issues


  Here are the changes found in Patchwork_22388_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-apl:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [FAIL][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], 
[PASS][48], [PASS][49], [PASS][50]) ([i915#4386])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl1/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl1/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl1/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl2/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl2/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl2/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl3/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl3/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl3/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl3/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl4/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl4/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl4/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl4/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl6/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl6/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl6/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl6/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl6/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl7/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl7/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl7/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl7/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl8/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl8/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl4/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl8/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl8/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl8/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl1/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl8/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl1/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl1/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl2/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl2/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl7/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl7/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl7/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl6/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl2/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl2/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl6/boot.html
   [43]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22388/shard-apl6/boot.html
   [44]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: s/JSP2/ICP2/ PCH

[Patchwork]

== Series Details ==

Series: drm/i915: s/JSP2/ICP2/ PCH
URL   : https://patchwork.freedesktop.org/series/100689/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11283 -> Patchwork_22400


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22400/index.html

Participating hosts (42 -> 39)
--

  Additional (1): fi-cml-u2 
  Missing(4): fi-kbl-soraka fi-bsw-cyan fi-bdw-samus bat-dg1-5 

Known issues


  Here are the changes found in Patchwork_22400 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@memory-alloc:
- fi-cml-u2:  NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22400/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html

  * igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u:   NOTRUN -> [SKIP][2] ([fdo#109271]) +18 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22400/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][3] ([i915#1208]) +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22400/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-cml-u2:  NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22400/fi-cml-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-cml-u2:  NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22400/fi-cml-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][6] -> [INCOMPLETE][7] ([i915#3921])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11283/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22400/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-cml-u2:  NOTRUN -> [SKIP][8] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22400/fi-cml-u2/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-cml-u2:  NOTRUN -> [SKIP][9] ([fdo#109278]) +1 similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22400/fi-cml-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2:  NOTRUN -> [SKIP][10] ([fdo#109285])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22400/fi-cml-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2:  NOTRUN -> [DMESG-WARN][11] ([i915#4269])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22400/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2:  NOTRUN -> [SKIP][12] ([fdo#109278] / [i915#533])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22400/fi-cml-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
- fi-cml-u2:  NOTRUN -> [SKIP][13] ([i915#3301])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22400/fi-cml-u2/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}:   [DMESG-WARN][14] ([i915#3576]) -> [PASS][15] +1 
similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11283/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22400/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  * igt@kms_psr@primary_page_flip:
- fi-skl-6600u:   [INCOMPLETE][16] ([i915#4838]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11283/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22400/fi-skl-6600u/igt@kms_psr@primary_page_flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: s/JSP2/ICP2/ PCH

[Patchwork]

== Series Details ==

Series: drm/i915: s/JSP2/ICP2/ PCH
URL   : https://patchwork.freedesktop.org/series/100689/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: s/JSP2/ICP2/ PCH

[Patchwork]

== Series Details ==

Series: drm/i915: s/JSP2/ICP2/ PCH
URL   : https://patchwork.freedesktop.org/series/100689/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
0862321e317b drm/i915: s/JSP2/ICP2/ PCH
-:9: WARNING:REPEATED_WORD: Possible repeated word: 'to'
#9: 
This JSP2 PCH actually seems to to be some special Apple

total: 0 errors, 1 warnings, 0 checks, 26 lines checked

[Intel-gfx] [PATCH v2 7/8] drm/i915/guc: Drop obsolete H2G definitions

[John . C . Harrison]

From: John Harrison 

The CTB registration process changed significantly a while back using
a single KLV based H2G. So drop the original and now obsolete H2G
definitions.

Signed-off-by: John Harrison 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 7afdadc7656f..e77f955435ce 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -131,8 +131,6 @@ enum intel_guc_action {
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
-   INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
-   INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
INTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,
INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
INTEL_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
-- 
2.25.1

[Intel-gfx] [PATCH v2 3/8] drm/i915/guc: Better name for context id limit

[John . C . Harrison]

From: John Harrison 

The LRC descriptor pool is going away. So, stop using it as the limit
for how many context ids are available. Instead, size the pool
according to the number of contexts allowed. Note that this is just a
naming change, the actual limit is identical in value.

While at it, also update a kzalloc(sizeof()*count) to be a
kcalloc(count,size).

Signed-off-by: John Harrison 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/intel_context.c  |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h  |  4 ++--
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c| 16 
 drivers/gpu/drm/i915/gt/uc/selftest_guc.c|  2 +-
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_context.c 
b/drivers/gpu/drm/i915/gt/intel_context.c
index 5d0ec7c49b6a..d87145b8fca0 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -400,7 +400,7 @@ intel_context_init(struct intel_context *ce, struct 
intel_engine_cs *engine)
INIT_LIST_HEAD(>guc_state.fences);
INIT_LIST_HEAD(>guc_state.requests);
 
-   ce->guc_id.id = GUC_INVALID_LRC_ID;
+   ce->guc_id.id = GUC_INVALID_CONTEXT_ID;
INIT_LIST_HEAD(>guc_id.link);
 
INIT_LIST_HEAD(>destroyed_link);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 6a4612a852e2..11099f0320ce 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -32,8 +32,8 @@
 #define GUC_CLIENT_PRIORITY_NORMAL 3
 #define GUC_CLIENT_PRIORITY_NUM4
 
-#define GUC_MAX_LRC_DESCRIPTORS65535
-#defineGUC_INVALID_LRC_ID  GUC_MAX_LRC_DESCRIPTORS
+#define GUC_MAX_CONTEXT_ID 65535
+#defineGUC_INVALID_CONTEXT_ID  GUC_MAX_CONTEXT_ID
 
 #define GUC_RENDER_ENGINE  0
 #define GUC_VIDEO_ENGINE   1
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 11bf56b5a266..ad784e8068c7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -354,12 +354,12 @@ request_to_scheduling_context(struct i915_request *rq)
 
 static inline bool context_guc_id_invalid(struct intel_context *ce)
 {
-   return ce->guc_id.id == GUC_INVALID_LRC_ID;
+   return ce->guc_id.id == GUC_INVALID_CONTEXT_ID;
 }
 
 static inline void set_context_guc_id_invalid(struct intel_context *ce)
 {
-   ce->guc_id.id = GUC_INVALID_LRC_ID;
+   ce->guc_id.id = GUC_INVALID_CONTEXT_ID;
 }
 
 static inline struct intel_guc *ce_to_guc(struct intel_context *ce)
@@ -474,7 +474,7 @@ static struct guc_lrc_desc *__get_lrc_desc(struct intel_guc 
*guc, u32 index)
 {
struct guc_lrc_desc *base = guc->lrc_desc_pool_vaddr;
 
-   GEM_BUG_ON(index >= GUC_MAX_LRC_DESCRIPTORS);
+   GEM_BUG_ON(index >= GUC_MAX_CONTEXT_ID);
 
return [index];
 }
@@ -483,7 +483,7 @@ static inline struct intel_context *__get_context(struct 
intel_guc *guc, u32 id)
 {
struct intel_context *ce = xa_load(>context_lookup, id);
 
-   GEM_BUG_ON(id >= GUC_MAX_LRC_DESCRIPTORS);
+   GEM_BUG_ON(id >= GUC_MAX_CONTEXT_ID);
 
return ce;
 }
@@ -494,7 +494,7 @@ static int guc_lrc_desc_pool_create(struct intel_guc *guc)
int ret;
 
size = PAGE_ALIGN(sizeof(struct guc_lrc_desc) *
- GUC_MAX_LRC_DESCRIPTORS);
+ GUC_MAX_CONTEXT_ID);
ret = intel_guc_allocate_and_map_vma(guc, size, >lrc_desc_pool,
 (void 
**)>lrc_desc_pool_vaddr);
if (ret)
@@ -2441,7 +2441,7 @@ static void __guc_context_sched_disable(struct intel_guc 
*guc,
GUC_CONTEXT_DISABLE
};
 
-   GEM_BUG_ON(guc_id == GUC_INVALID_LRC_ID);
+   GEM_BUG_ON(guc_id == GUC_INVALID_CONTEXT_ID);
 
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_sched_disable(ce);
@@ -3840,7 +3840,7 @@ static bool __guc_submission_selected(struct intel_guc 
*guc)
 
 void intel_guc_submission_init_early(struct intel_guc *guc)
 {
-   guc->submission_state.num_guc_ids = GUC_MAX_LRC_DESCRIPTORS;
+   guc->submission_state.num_guc_ids = GUC_MAX_CONTEXT_ID;
guc->submission_supported = __guc_submission_supported(guc);
guc->submission_selected = __guc_submission_selected(guc);
 }
@@ -3850,7 +3850,7 @@ g2h_context_lookup(struct intel_guc *guc, u32 desc_idx)
 {
struct intel_context *ce;
 
-   if (unlikely(desc_idx >= GUC_MAX_LRC_DESCRIPTORS)) {
+   if (unlikely(desc_idx >= GUC_MAX_CONTEXT_ID)) {
drm_err(_to_gt(guc)->i915->drm,
"Invalid desc_idx %u", desc_idx);
return NULL;
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c 

[Intel-gfx] [PATCH v2 4/8] drm/i915/guc: Split guc_lrc_desc_pin apart

[John . C . Harrison]

From: John Harrison 

The LRC descriptor pool is going away. Further, the function that was
populating it was also doing a bunch of logic about the context
registration sequence. So, split that code apart into separate state
setup and try to register functions. Note that some of those 'try to
register' code paths actually undo the state setup and leave it to be
redone again later (with potentially different values). This is
inefficient. The next patch will correct this.

Also, move a comment about ignoring return values to the place where
the return values are actually ignored.

v2: Move some more splitting from a later patch (and do it correctly).

Signed-off-by: John Harrison 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 54 +++
 1 file changed, 33 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index ad784e8068c7..e41e309b9e7e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -634,7 +634,7 @@ int intel_guc_wait_for_idle(struct intel_guc *guc, long 
timeout)
  true, timeout);
 }
 
-static int guc_lrc_desc_pin(struct intel_context *ce, bool loop);
+static int try_context_registration(struct intel_context *ce, bool loop);
 
 static int __guc_add_request(struct intel_guc *guc, struct i915_request *rq)
 {
@@ -932,7 +932,7 @@ static int guc_dequeue_one_context(struct intel_guc *guc)
 
if (unlikely(!ctx_id_mapped(guc, ce->guc_id.id) &&
 !intel_context_is_banned(ce))) {
-   ret = guc_lrc_desc_pin(ce, false);
+   ret = try_context_registration(ce, false);
if (unlikely(ret == -EPIPE)) {
goto deadlk;
} else if (ret == -EBUSY) {
@@ -2237,20 +2237,15 @@ static void guc_context_policy_init(struct 
intel_engine_cs *engine,
desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
 }
 
-static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
+static void prepare_context_registration_info(struct intel_context *ce)
 {
struct intel_engine_cs *engine = ce->engine;
-   struct intel_runtime_pm *runtime_pm = engine->uncore->rpm;
struct intel_guc *guc = >gt->uc.guc;
u32 desc_idx = ce->guc_id.id;
struct guc_lrc_desc *desc;
-   bool context_registered;
-   intel_wakeref_t wakeref;
struct intel_context *child;
-   int ret = 0;
 
GEM_BUG_ON(!engine->mask);
-   GEM_BUG_ON(!sched_state_is_init(ce));
 
/*
 * Ensure LRC + CT vmas are is same region as write barrier is done
@@ -2259,11 +2254,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce, 
bool loop)
GEM_BUG_ON(i915_gem_object_is_lmem(guc->ct.vma->obj) !=
   i915_gem_object_is_lmem(ce->ring->vma->obj));
 
-   context_registered = ctx_id_mapped(guc, desc_idx);
-
-   clr_ctx_id_mapping(guc, desc_idx);
-   set_ctx_id_mapping(guc, desc_idx, ce);
-
desc = __get_lrc_desc(guc, desc_idx);
desc->engine_class = engine_class_to_guc_class(engine->class);
desc->engine_submit_mask = engine->logical_mask;
@@ -2308,6 +2298,26 @@ static int guc_lrc_desc_pin(struct intel_context *ce, 
bool loop)
 
clear_children_join_go_memory(ce);
}
+}
+
+static int try_context_registration(struct intel_context *ce, bool loop)
+{
+   struct intel_engine_cs *engine = ce->engine;
+   struct intel_runtime_pm *runtime_pm = engine->uncore->rpm;
+   struct intel_guc *guc = >gt->uc.guc;
+   intel_wakeref_t wakeref;
+   u32 desc_idx = ce->guc_id.id;
+   bool context_registered;
+   int ret = 0;
+
+   GEM_BUG_ON(!sched_state_is_init(ce));
+
+   context_registered = ctx_id_mapped(guc, desc_idx);
+
+   clr_ctx_id_mapping(guc, desc_idx);
+   set_ctx_id_mapping(guc, desc_idx, ce);
+
+   prepare_context_registration_info(ce);
 
/*
 * The context_lookup xarray is used to determine if the hardware
@@ -3145,7 +3155,7 @@ static int guc_request_alloc(struct i915_request *rq)
if (unlikely(ret < 0))
return ret;
if (context_needs_register(ce, !!ret)) {
-   ret = guc_lrc_desc_pin(ce, true);
+   ret = try_context_registration(ce, true);
if (unlikely(ret)) {/* unwind */
if (ret == -EPIPE) {
disable_submission(guc);
@@ -3633,9 +3643,17 @@ static void guc_set_default_submission(struct 
intel_engine_cs *engine)
 static inline void guc_kernel_context_pin(struct intel_guc *guc,
  struct intel_context *ce)
 {
+   /*
+* Note: we purposefully do not check the returns below because
+* the registration 

[Intel-gfx] [PATCH v2 1/8] drm/i915/guc: Do not conflate lrc_desc with GuC id for registration

[John . C . Harrison]

From: John Harrison 

The LRC descriptor pool is going away. So, stop using it as a check for
context registration, use the GuC id instead (being the thing that
actually gets registered with the GuC).

Also, rename the set/clear/query helper functions for context id
mappings to better reflect their purpose and to differentiate from
other registration related helper functions.

Signed-off-by: John Harrison 
Reviewed-by: Daniele Ceraolo Spurio 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 69 ++-
 1 file changed, 38 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b3a429a92c0d..7fb889e14995 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -514,31 +514,20 @@ static inline bool guc_submission_initialized(struct 
intel_guc *guc)
return !!guc->lrc_desc_pool_vaddr;
 }
 
-static inline void reset_lrc_desc(struct intel_guc *guc, u32 id)
+static inline void _reset_lrc_desc(struct intel_guc *guc, u32 id)
 {
-   if (likely(guc_submission_initialized(guc))) {
-   struct guc_lrc_desc *desc = __get_lrc_desc(guc, id);
-   unsigned long flags;
-
-   memset(desc, 0, sizeof(*desc));
+   struct guc_lrc_desc *desc = __get_lrc_desc(guc, id);
 
-   /*
-* xarray API doesn't have xa_erase_irqsave wrapper, so calling
-* the lower level functions directly.
-*/
-   xa_lock_irqsave(>context_lookup, flags);
-   __xa_erase(>context_lookup, id);
-   xa_unlock_irqrestore(>context_lookup, flags);
-   }
+   memset(desc, 0, sizeof(*desc));
 }
 
-static inline bool lrc_desc_registered(struct intel_guc *guc, u32 id)
+static inline bool ctx_id_mapped(struct intel_guc *guc, u32 id)
 {
return __get_context(guc, id);
 }
 
-static inline void set_lrc_desc_registered(struct intel_guc *guc, u32 id,
-  struct intel_context *ce)
+static inline void set_ctx_id_mapping(struct intel_guc *guc, u32 id,
+ struct intel_context *ce)
 {
unsigned long flags;
 
@@ -551,6 +540,24 @@ static inline void set_lrc_desc_registered(struct 
intel_guc *guc, u32 id,
xa_unlock_irqrestore(>context_lookup, flags);
 }
 
+static inline void clr_ctx_id_mapping(struct intel_guc *guc, u32 id)
+{
+   unsigned long flags;
+
+   if (unlikely(!guc_submission_initialized(guc)))
+   return;
+
+   _reset_lrc_desc(guc, id);
+
+   /*
+* xarray API doesn't have xa_erase_irqsave wrapper, so calling
+* the lower level functions directly.
+*/
+   xa_lock_irqsave(>context_lookup, flags);
+   __xa_erase(>context_lookup, id);
+   xa_unlock_irqrestore(>context_lookup, flags);
+}
+
 static void decr_outstanding_submission_g2h(struct intel_guc *guc)
 {
if (atomic_dec_and_test(>outstanding_submission_g2h))
@@ -795,7 +802,7 @@ static int __guc_wq_item_append(struct i915_request *rq)
GEM_BUG_ON(!atomic_read(>guc_id.ref));
GEM_BUG_ON(context_guc_id_invalid(ce));
GEM_BUG_ON(context_wait_for_deregister_to_register(ce));
-   GEM_BUG_ON(!lrc_desc_registered(ce_to_guc(ce), ce->guc_id.id));
+   GEM_BUG_ON(!ctx_id_mapped(ce_to_guc(ce), ce->guc_id.id));
 
/* Insert NOOP if this work queue item will wrap the tail pointer. */
if (wqi_size > wq_space_until_wrap(ce)) {
@@ -923,7 +930,7 @@ static int guc_dequeue_one_context(struct intel_guc *guc)
if (submit) {
struct intel_context *ce = request_to_scheduling_context(last);
 
-   if (unlikely(!lrc_desc_registered(guc, ce->guc_id.id) &&
+   if (unlikely(!ctx_id_mapped(guc, ce->guc_id.id) &&
 !intel_context_is_banned(ce))) {
ret = guc_lrc_desc_pin(ce, false);
if (unlikely(ret == -EPIPE)) {
@@ -1897,7 +1904,7 @@ static bool need_tasklet(struct intel_guc *guc, struct 
i915_request *rq)
 
return submission_disabled(guc) || guc->stalled_request ||
!i915_sched_engine_is_empty(sched_engine) ||
-   !lrc_desc_registered(guc, ce->guc_id.id);
+   !ctx_id_mapped(guc, ce->guc_id.id);
 }
 
 static void guc_submit_request(struct i915_request *rq)
@@ -1954,7 +1961,7 @@ static void __release_guc_id(struct intel_guc *guc, 
struct intel_context *ce)
else
ida_simple_remove(>submission_state.guc_ids,
  ce->guc_id.id);
-   reset_lrc_desc(guc, ce->guc_id.id);
+   clr_ctx_id_mapping(guc, ce->guc_id.id);
set_context_guc_id_invalid(ce);
}
if (!list_empty(>guc_id.link))
@@ -2250,10 +2257,10 @@ static int 

[Intel-gfx] [PATCH v2 2/8] drm/i915/guc: Add an explicit 'submission_initialized' flag

[John . C . Harrison]

From: John Harrison 

The LRC descriptor pool is going away. So, stop using it as a check
for whether submission has been initialised or not.

Signed-off-by: John Harrison 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +---
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 9d779de16613..568eb6352ef0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -137,6 +137,8 @@ struct intel_guc {
bool submission_supported;
/** @submission_selected: tracks whether the user enabled GuC 
submission */
bool submission_selected;
+   /** @submission_initialized: tracks whether GuC submission has been 
initialised */
+   bool submission_initialized;
/**
 * @rc_supported: tracks whether we support GuC rc on the current 
platform
 */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 7fb889e14995..11bf56b5a266 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -511,7 +511,7 @@ static void guc_lrc_desc_pool_destroy(struct intel_guc *guc)
 
 static inline bool guc_submission_initialized(struct intel_guc *guc)
 {
-   return !!guc->lrc_desc_pool_vaddr;
+   return guc->submission_initialized;
 }
 
 static inline void _reset_lrc_desc(struct intel_guc *guc, u32 id)
@@ -1813,7 +1813,7 @@ int intel_guc_submission_init(struct intel_guc *guc)
struct intel_gt *gt = guc_to_gt(guc);
int ret;
 
-   if (guc->lrc_desc_pool)
+   if (guc->submission_initialized)
return 0;
 
ret = guc_lrc_desc_pool_create(guc);
@@ -1845,19 +1845,21 @@ int intel_guc_submission_init(struct intel_guc *guc)
INIT_DELAYED_WORK(>timestamp.work, guc_timestamp_ping);
guc->timestamp.ping_delay = (POLL_TIME_CLKS / gt->clock_frequency + 1) 
* HZ;
guc->timestamp.shift = gpm_timestamp_shift(gt);
+   guc->submission_initialized = true;
 
return 0;
 }
 
 void intel_guc_submission_fini(struct intel_guc *guc)
 {
-   if (!guc->lrc_desc_pool)
+   if (!guc->submission_initialized)
return;
 
guc_flush_destroyed_contexts(guc);
guc_lrc_desc_pool_destroy(guc);
i915_sched_engine_put(guc->sched_engine);
bitmap_free(guc->submission_state.guc_ids_bitmap);
+   guc->submission_initialized = false;
 }
 
 static inline void queue_request(struct i915_sched_engine *sched_engine,
-- 
2.25.1

[Intel-gfx] [PATCH v2 6/8] drm/i915/guc: Rename desc_idx to ctx_id

[John . C . Harrison]

From: John Harrison 

The LRC descriptor pool is going away. So, stop naming context ids as
descriptor pool indecies.

While at it, add a bunch of missing line feeds to some error messages.

Signed-off-by: John Harrison 
Reviewed-by: Daniele Ceraolo Spurio 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 52 +--
 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index d9e1cd3e1db2..53114097a5b9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2245,7 +2245,7 @@ static void prepare_context_registration_info(struct 
intel_context *ce)
 {
struct intel_engine_cs *engine = ce->engine;
struct intel_guc *guc = >gt->uc.guc;
-   u32 desc_idx = ce->guc_id.id;
+   u32 ctx_id = ce->guc_id.id;
struct guc_lrc_desc *desc;
struct intel_context *child;
 
@@ -2258,7 +2258,7 @@ static void prepare_context_registration_info(struct 
intel_context *ce)
GEM_BUG_ON(i915_gem_object_is_lmem(guc->ct.vma->obj) !=
   i915_gem_object_is_lmem(ce->ring->vma->obj));
 
-   desc = __get_lrc_desc(guc, desc_idx);
+   desc = __get_lrc_desc(guc, ctx_id);
desc->engine_class = engine_class_to_guc_class(engine->class);
desc->engine_submit_mask = engine->logical_mask;
desc->hw_context_desc = ce->lrc.lrca;
@@ -2310,16 +2310,16 @@ static int try_context_registration(struct 
intel_context *ce, bool loop)
struct intel_runtime_pm *runtime_pm = engine->uncore->rpm;
struct intel_guc *guc = >gt->uc.guc;
intel_wakeref_t wakeref;
-   u32 desc_idx = ce->guc_id.id;
+   u32 ctx_id = ce->guc_id.id;
bool context_registered;
int ret = 0;
 
GEM_BUG_ON(!sched_state_is_init(ce));
 
-   context_registered = ctx_id_mapped(guc, desc_idx);
+   context_registered = ctx_id_mapped(guc, ctx_id);
 
-   clr_ctx_id_mapping(guc, desc_idx);
-   set_ctx_id_mapping(guc, desc_idx, ce);
+   clr_ctx_id_mapping(guc, ctx_id);
+   set_ctx_id_mapping(guc, ctx_id, ce);
 
/*
 * The context_lookup xarray is used to determine if the hardware
@@ -2345,7 +2345,7 @@ static int try_context_registration(struct intel_context 
*ce, bool loop)
}
spin_unlock_irqrestore(>guc_state.lock, flags);
if (unlikely(disabled)) {
-   clr_ctx_id_mapping(guc, desc_idx);
+   clr_ctx_id_mapping(guc, ctx_id);
return 0;   /* Will get registered later */
}
 
@@ -2361,9 +2361,9 @@ static int try_context_registration(struct intel_context 
*ce, bool loop)
with_intel_runtime_pm(runtime_pm, wakeref)
ret = register_context(ce, loop);
if (unlikely(ret == -EBUSY)) {
-   clr_ctx_id_mapping(guc, desc_idx);
+   clr_ctx_id_mapping(guc, ctx_id);
} else if (unlikely(ret == -ENODEV)) {
-   clr_ctx_id_mapping(guc, desc_idx);
+   clr_ctx_id_mapping(guc, ctx_id);
ret = 0;/* Will get registered later */
}
}
@@ -3860,26 +3860,26 @@ void intel_guc_submission_init_early(struct intel_guc 
*guc)
 }
 
 static inline struct intel_context *
-g2h_context_lookup(struct intel_guc *guc, u32 desc_idx)
+g2h_context_lookup(struct intel_guc *guc, u32 ctx_id)
 {
struct intel_context *ce;
 
-   if (unlikely(desc_idx >= GUC_MAX_CONTEXT_ID)) {
+   if (unlikely(ctx_id >= GUC_MAX_CONTEXT_ID)) {
drm_err(_to_gt(guc)->i915->drm,
-   "Invalid desc_idx %u", desc_idx);
+   "Invalid ctx_id %u\n", ctx_id);
return NULL;
}
 
-   ce = __get_context(guc, desc_idx);
+   ce = __get_context(guc, ctx_id);
if (unlikely(!ce)) {
drm_err(_to_gt(guc)->i915->drm,
-   "Context is NULL, desc_idx %u", desc_idx);
+   "Context is NULL, ctx_id %u\n", ctx_id);
return NULL;
}
 
if (unlikely(intel_context_is_child(ce))) {
drm_err(_to_gt(guc)->i915->drm,
-   "Context is child, desc_idx %u", desc_idx);
+   "Context is child, ctx_id %u\n", ctx_id);
return NULL;
}
 
@@ -3891,14 +3891,14 @@ int intel_guc_deregister_done_process_msg(struct 
intel_guc *guc,
  u32 len)
 {
struct intel_context *ce;
-   u32 desc_idx = msg[0];
+   u32 ctx_id = msg[0];
 
if (unlikely(len < 1)) {
-   drm_err(_to_gt(guc)->i915->drm, "Invalid length %u", len);
+   drm_err(_to_gt(guc)->i915->drm, "Invalid length %u\n", len);

[Intel-gfx] [PATCH v2 5/8] drm/i915/guc: Move lrc desc setup to where it is needed

[John . C . Harrison]

From: John Harrison 

The LRC descriptor was being initialised early on in the context
registration sequence. It could then be determined that the actual
registration needs to be delayed and the descriptor would be wiped
out. This is inefficient, so move the setup to later in the process
after the point of no return.

v2: Move some split changes into the split patch (and do them
correctly).

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e41e309b9e7e..d9e1cd3e1db2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2153,6 +2153,8 @@ static int __guc_action_register_context(struct intel_guc 
*guc,
 0, loop);
 }
 
+static void prepare_context_registration_info(struct intel_context *ce);
+
 static int register_context(struct intel_context *ce, bool loop)
 {
struct intel_guc *guc = ce_to_guc(ce);
@@ -2163,6 +2165,8 @@ static int register_context(struct intel_context *ce, 
bool loop)
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_register(ce);
 
+   prepare_context_registration_info(ce);
+
if (intel_context_is_parent(ce))
ret = __guc_action_register_multi_lrc(guc, ce, ce->guc_id.id,
  offset, loop);
@@ -2317,8 +2321,6 @@ static int try_context_registration(struct intel_context 
*ce, bool loop)
clr_ctx_id_mapping(guc, desc_idx);
set_ctx_id_mapping(guc, desc_idx, ce);
 
-   prepare_context_registration_info(ce);
-
/*
 * The context_lookup xarray is used to determine if the hardware
 * context is currently registered. There are two cases in which it
-- 
2.25.1

[Intel-gfx] [PATCH v2 8/8] drm/i915/guc: Fix potential invalid pointer dereferences when decoding G2Hs

[John . C . Harrison]

From: John Harrison 

Some G2H handlers were reading the context id field from the payload
before checking the payload met the minimum length required.

Signed-off-by: John Harrison 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 53114097a5b9..820f6e870505 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3891,12 +3891,13 @@ int intel_guc_deregister_done_process_msg(struct 
intel_guc *guc,
  u32 len)
 {
struct intel_context *ce;
-   u32 ctx_id = msg[0];
+   u32 ctx_id;
 
if (unlikely(len < 1)) {
drm_err(_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
return -EPROTO;
}
+   ctx_id = msg[0];
 
ce = g2h_context_lookup(guc, ctx_id);
if (unlikely(!ce))
@@ -3942,12 +3943,13 @@ int intel_guc_sched_done_process_msg(struct intel_guc 
*guc,
 {
struct intel_context *ce;
unsigned long flags;
-   u32 ctx_id = msg[0];
+   u32 ctx_id;
 
if (unlikely(len < 2)) {
drm_err(_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
return -EPROTO;
}
+   ctx_id = msg[0];
 
ce = g2h_context_lookup(guc, ctx_id);
if (unlikely(!ce))
-- 
2.25.1

[Intel-gfx] [PATCH v2 0/8] Prep work for next GuC release

[John . C . Harrison]

From: John Harrison 

The next GuC firmware release includes some significant backwards
breaking API changes. One such is that there is no longer an LRC
descriptor pool. A bunch of prep work for that change can be done in
advance - the descriptor pool was being used for things it shouldn't
really have been used for anyway.

v2: Extend commit message on 'better name' patch. Improve 'split
apart' patch to include some necessary re-arrangement that was in a
later patch and which introduced an unnecessary conditional in said
patch too. (review feedback from Daniele)

Signed-off-by: John Harrison 


John Harrison (8):
  drm/i915/guc: Do not conflate lrc_desc with GuC id for registration
  drm/i915/guc: Add an explicit 'submission_initialized' flag
  drm/i915/guc: Better name for context id limit
  drm/i915/guc: Split guc_lrc_desc_pin apart
  drm/i915/guc: Move lrc desc setup to where it is needed
  drm/i915/guc: Rename desc_idx to ctx_id
  drm/i915/guc: Drop obsolete H2G definitions
  drm/i915/guc: Fix potential invalid pointer dereferences when decoding
G2Hs

 drivers/gpu/drm/i915/gt/intel_context.c   |   2 +-
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |   2 -
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|   2 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   4 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 181 ++
 drivers/gpu/drm/i915/gt/uc/selftest_guc.c |   2 +-
 6 files changed, 109 insertions(+), 84 deletions(-)

-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Be more gentle when exiting non-persistent contexts (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Be more gentle when exiting non-persistent contexts (rev3)
URL   : https://patchwork.freedesktop.org/series/93420/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11283 -> Patchwork_22399


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22399/index.html

Participating hosts (42 -> 39)
--

  Additional (2): fi-cml-u2 fi-pnv-d510 
  Missing(5): fi-kbl-soraka fi-bxt-dsi bat-dg1-5 fi-bsw-cyan fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22399 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@memory-alloc:
- fi-cml-u2:  NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22399/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][2] ([i915#1208]) +1 similar issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22399/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-cml-u2:  NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22399/fi-cml-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-cml-u2:  NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22399/fi-cml-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-cml-u2:  NOTRUN -> [SKIP][5] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22399/fi-cml-u2/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-cml-u2:  NOTRUN -> [SKIP][6] ([fdo#109278]) +1 similar issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22399/fi-cml-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2:  NOTRUN -> [SKIP][7] ([fdo#109285])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22399/fi-cml-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2:  NOTRUN -> [SKIP][8] ([fdo#109278] / [i915#533])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22399/fi-cml-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@cursor_plane_move:
- fi-skl-6600u:   NOTRUN -> [INCOMPLETE][9] ([i915#636])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22399/fi-skl-6600u/igt@kms_psr@cursor_plane_move.html

  * igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][10] ([fdo#109271]) +57 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22399/fi-pnv-d510/igt@prime_v...@basic-userptr.html
- fi-cml-u2:  NOTRUN -> [SKIP][11] ([i915#3301])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22399/fi-cml-u2/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@kms_busy@basic@modeset:
- {bat-adlp-6}:   [DMESG-WARN][12] ([i915#3576]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11283/bat-adlp-6/igt@kms_busy@ba...@modeset.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22399/bat-adlp-6/igt@kms_busy@ba...@modeset.html

  * igt@kms_psr@primary_page_flip:
- fi-skl-6600u:   [INCOMPLETE][14] ([i915#4838]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11283/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22399/fi-skl-6600u/igt@kms_psr@primary_page_flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1208]: https://gitlab.freedesktop.org/drm/intel/issues/1208
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4613]: 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: make a handful of read-only arrays static const (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: make a handful of read-only arrays static const (rev2)
URL   : https://patchwork.freedesktop.org/series/100570/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11277_full -> Patchwork_22386_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_22386_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-apl:  NOTRUN -> [DMESG-WARN][1] ([i915#4991])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22386/shard-apl1/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-apl:  [PASS][2] -> [DMESG-WARN][3] ([i915#180]) +1 similar 
issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl6/igt@gem_ctx_isolation@preservation...@bcs0.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22386/shard-apl8/igt@gem_ctx_isolation@preservation...@bcs0.html

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl:  [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +2 similar 
issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-kbl1/igt@gem_ctx_isolation@preservation...@vcs0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22386/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@gem_exec_balancer@parallel-contexts:
- shard-kbl:  NOTRUN -> [DMESG-WARN][6] ([i915#5076])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22386/shard-kbl3/igt@gem_exec_balan...@parallel-contexts.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][7] ([i915#4547])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22386/shard-skl7/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][8] -> [FAIL][9] ([i915#2846])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-glk2/igt@gem_exec_f...@basic-deadline.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22386/shard-glk5/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22386/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-kbl:  [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs1.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22386/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22386/shard-tglb6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-apl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22386/shard-apl2/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@heavy-verify-random:
- shard-kbl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22386/shard-kbl7/igt@gem_lmem_swapp...@heavy-verify-random.html
- shard-skl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +4 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22386/shard-skl8/igt@gem_lmem_swapp...@heavy-verify-random.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#4613])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22386/shard-iclb7/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-verify:
- shard-glk:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22386/shard-glk5/igt@gem_lmem_swapp...@parallel-random-verify.html

  * igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#4270]) +1 similar issue
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22386/shard-iclb7/igt@gem_...@verify-pxp-stale-ctx-execution.html

  * igt@i915_pm_dc@dc6-psr:
- shard-skl:  NOTRUN -> [FAIL][22] ([i915#454])
   [22]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Be more gentle when exiting non-persistent contexts (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Be more gentle when exiting non-persistent contexts (rev3)
URL   : https://patchwork.freedesktop.org/series/93420/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for Replace VT-d workaround with guard pages (rev3)

[Patchwork]

== Series Details ==

Series: Replace VT-d workaround with guard pages (rev3)
URL   : https://patchwork.freedesktop.org/series/97492/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11283 -> Patchwork_22398


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22398 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22398, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/index.html

Participating hosts (42 -> 38)
--

  Additional (2): fi-cml-u2 bat-adls-5 
  Missing(6): fi-bsw-n3050 fi-bsw-cyan fi-apl-guc fi-bsw-kefka fi-bsw-nick 
fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22398:

### IGT changes ###

 Possible regressions 

  * igt@runner@aborted:
- bat-dg1-5:  NOTRUN -> [FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/bat-dg1-5/igt@run...@aborted.html
- fi-bwr-2160:NOTRUN -> [FAIL][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-bwr-2160/igt@run...@aborted.html
- bat-dg1-6:  NOTRUN -> [FAIL][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/bat-dg1-6/igt@run...@aborted.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@runner@aborted:
- {fi-rkl-11600}: NOTRUN -> [FAIL][4]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-rkl-11600/igt@run...@aborted.html
- {bat-adlp-6}:   NOTRUN -> [FAIL][5]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/bat-adlp-6/igt@run...@aborted.html
- {bat-jsl-2}:[FAIL][6] ([i915#4312]) -> [FAIL][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11283/bat-jsl-2/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/bat-jsl-2/igt@run...@aborted.html
- {fi-jsl-1}: NOTRUN -> [FAIL][8]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-jsl-1/igt@run...@aborted.html
- {bat-jsl-1}:NOTRUN -> [FAIL][9]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/bat-jsl-1/igt@run...@aborted.html
- {fi-ehl-2}: NOTRUN -> [FAIL][10]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-ehl-2/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_22398 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@runner@aborted:
- fi-snb-2600:NOTRUN -> [FAIL][11] ([i915#2426])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-snb-2600/igt@run...@aborted.html
- fi-ilk-650: NOTRUN -> [FAIL][12] ([i915#2426])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-ilk-650/igt@run...@aborted.html
- fi-kbl-x1275:   NOTRUN -> [FAIL][13] ([i915#2426])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-kbl-x1275/igt@run...@aborted.html
- fi-bdw-gvtdvm:  NOTRUN -> [FAIL][14] ([i915#2426])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-bdw-gvtdvm/igt@run...@aborted.html
- fi-cfl-8700k:   NOTRUN -> [FAIL][15] ([i915#2426])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-cfl-8700k/igt@run...@aborted.html
- fi-skl-6600u:   NOTRUN -> [FAIL][16] ([i915#2426])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-skl-6600u/igt@run...@aborted.html
- fi-cfl-8109u:   NOTRUN -> [FAIL][17] ([i915#2426])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-cfl-8109u/igt@run...@aborted.html
- fi-glk-dsi: NOTRUN -> [FAIL][18] ([i915#2426] / [k.org#202321])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-8809g:   NOTRUN -> [FAIL][19] ([i915#2426])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-kbl-8809g/igt@run...@aborted.html
- fi-snb-2520m:   NOTRUN -> [FAIL][20] ([i915#2426])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-snb-2520m/igt@run...@aborted.html
- fi-kbl-soraka:  NOTRUN -> [FAIL][21] ([i915#2426])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-kbl-soraka/igt@run...@aborted.html
- fi-kbl-7500u:   NOTRUN -> [FAIL][22] ([i915#2426])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22398/fi-kbl-7500u/igt@run...@aborted.html
- fi-kbl-guc: NOTRUN -> [FAIL][23] ([i915#2426])
   [23]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Replace VT-d workaround with guard pages (rev3)

[Patchwork]

== Series Details ==

Series: Replace VT-d workaround with guard pages (rev3)
URL   : https://patchwork.freedesktop.org/series/97492/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/cdclk: Add cdclk check to atomic check

[Patchwork]

== Series Details ==

Series: drm/i915/cdclk: Add cdclk check to atomic check
URL   : https://patchwork.freedesktop.org/series/100671/
State : failure

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  DESCEND objtool
  CHK include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/display/intel_cdclk.o
drivers/gpu/drm/i915/display/intel_cdclk.c: In function ‘bxt_set_cdclk’:
drivers/gpu/drm/i915/display/intel_cdclk.c:1706:36: error: initialization 
discards ‘const’ qualifier from pointer target type 
[-Werror=discarded-qualifiers]
  struct cdclk_steps *cdclk_steps = new_cdclk_state->steps;
^~~
drivers/gpu/drm/i915/display/intel_cdclk.c: In function 
‘intel_cdclk_needs_modeset’:
drivers/gpu/drm/i915/display/intel_cdclk.c:2034:41: error: initialization 
discards ‘const’ qualifier from pointer target type 
[-Werror=discarded-qualifiers]
  struct cdclk_steps *cdclk_transition = new_cdclk_state->steps;
 ^~~
cc1: all warnings being treated as errors
scripts/Makefile.build:288: recipe for target 
'drivers/gpu/drm/i915/display/intel_cdclk.o' failed
make[4]: *** [drivers/gpu/drm/i915/display/intel_cdclk.o] Error 1
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1831: recipe for target 'drivers' failed
make: *** [drivers] Error 2

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev4)

[Patchwork]

== Series Details ==

Series: drm/mm: Add an iterator to optimally walk over holes suitable for an 
allocation (rev4)
URL   : https://patchwork.freedesktop.org/series/100136/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11282 -> Patchwork_22396


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/index.html

Participating hosts (41 -> 42)
--

  Additional (3): fi-cml-u2 fi-kbl-8809g fi-pnv-d510 
  Missing(2): fi-bsw-cyan fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22396 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@memory-alloc:
- fi-cml-u2:  NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][3] ([i915#1208]) +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_exec_suspend@basic-s0@smem:
- fi-kbl-8809g:   NOTRUN -> [DMESG-WARN][4] ([i915#4962]) +1 similar 
issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-kbl-8809g/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-skl-6600u:   NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-cml-u2:  NOTRUN -> [SKIP][6] ([i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-cml-u2/igt@gem_huc_c...@huc-copy.html
- fi-kbl-8809g:   NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-cml-u2:  NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-cml-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
- fi-kbl-8809g:   NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-kbl-8809g/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u:   NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live:
- fi-skl-6600u:   NOTRUN -> [FAIL][11] ([i915#4547])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-skl-6600u/igt@i915_selft...@live.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][12] ([i915#2927])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-cml-u2:  NOTRUN -> [SKIP][13] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-cml-u2/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-8809g:   NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u:   NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-cml-u2:  NOTRUN -> [SKIP][16] ([fdo#109278]) +1 similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-cml-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u:   NOTRUN -> [SKIP][17] ([fdo#109271]) +3 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22396/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-connector-state:
- fi-cfl-8109u:   [PASS][18] -> [DMESG-WARN][19] ([i915#165]) +1 
similar issue
   [18]: 

Re: [Intel-gfx] [PATCH 5/8] drm/i915/guc: Move lrc desc setup to where it is needed

[John Harrison]

On 2/23/2022 18:03, Ceraolo Spurio, Daniele wrote:

On 2/23/2022 12:23 PM, John Harrison wrote:

On 2/22/2022 17:12, Ceraolo Spurio, Daniele wrote:

On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote:

From: John Harrison 

The LRC descriptor was being initialised early on in the context
registration sequence. It could then be determined that the actual
registration needs to be delayed and the descriptor would be wiped
out. This is inefficient, so move the setup to later in the process
after the point of no return.

Signed-off-by: John Harrison 
---
  drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 +--
  1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

index 0ab2d1a24bf6..aa74ec74194a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2153,6 +2153,8 @@ static int 
__guc_action_register_context(struct intel_guc *guc,

   0, loop);
  }
  +static void prepare_context_registration_info(struct 
intel_context *ce);

+
  static int register_context(struct intel_context *ce, bool loop)
  {
  struct intel_guc *guc = ce_to_guc(ce);
@@ -2163,6 +2165,8 @@ static int register_context(struct 
intel_context *ce, bool loop)

  GEM_BUG_ON(intel_context_is_child(ce));
  trace_intel_context_register(ce);
  +    prepare_context_registration_info(ce);
+
  if (intel_context_is_parent(ce))
  ret = __guc_action_register_multi_lrc(guc, ce, 
ce->guc_id.id,

    offset, loop);
@@ -2246,7 +2250,6 @@ static void 
prepare_context_registration_info(struct intel_context *ce)

  struct intel_context *child;
    GEM_BUG_ON(!engine->mask);
-    GEM_BUG_ON(!sched_state_is_init(ce));
    /*
   * Ensure LRC + CT vmas are is same region as write barrier 
is done
@@ -2314,9 +2317,13 @@ static int try_context_registration(struct 
intel_context *ce, bool loop)

  bool context_registered;
  int ret = 0;
  +    GEM_BUG_ON(!sched_state_is_init(ce));
+
  context_registered = ctx_id_mapped(guc, desc_idx);
  -    prepare_context_registration_info(ce);
+    if (context_registered)
+    clr_ctx_id_mapping(guc, desc_idx);
+    set_ctx_id_mapping(guc, desc_idx, ce);


I think we can do the clr unconditionally. Also, should we drop the 
clr/set pair in prepare_context_registration_info? it shouldn't be 
needed, unless I'm missing a path where we don;t pass through here.


Daniele

I don't believe so.

The point is that the context id might have changed (it got stolen, 
re-used, etc. - all the state machine code below can cause aborts and 
retries and such like if something is pending and the register needs 
to be delayed). So we need to clear out the old mapping and add a new 
one to be safe. Also, I'm not sure if it is safe to do a xa_store to 
an already used entry as an update or if you are supposed to clear it 
first? But that's what the code did before and I'm trying to not 
change any actual behaviour here.


I was comparing with previous behavior. before this patch, we only do 
the setting of the ctx_id here (inside 
prepare_context_registration_info) and you're not changing any of the 
abort/retry behavior, so if it was enough before it should be enough now.
Hmm, I think I must have confused myself with the intermediate steps 
along the way. Yes, it looks like the clr/set in prepare is redundant by 
the end.




Regarding the xa ops, we did an unconditional clear before, so it 
should be ok to just do the same and have the clear and set back to 
back without checking if the context ID was already in use or not.
Actually, I was thinking you meant to drop the clr completely rather 
than just drop the condition. Yeah, that sounds fine.


Will post an update.

John.



Daniele



John.




    /*
   * The context_lookup xarray is used to determine if the 
hardware

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev4)

[Patchwork]

== Series Details ==

Series: drm/mm: Add an iterator to optimally walk over holes suitable for an 
allocation (rev4)
URL   : https://patchwork.freedesktop.org/series/100136/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev4)

[Patchwork]

== Series Details ==

Series: drm/mm: Add an iterator to optimally walk over holes suitable for an 
allocation (rev4)
URL   : https://patchwork.freedesktop.org/series/100136/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
1a82dfc67642 drm/mm: Add an iterator to optimally walk over holes for an 
allocation (v4)
-:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pos' - possible 
side-effects?
#153: FILE: include/drm/drm_mm.h:430:
+#define drm_mm_for_each_suitable_hole(pos, mm, range_start, range_end, \
+ size, mode) \
+   for (pos = __drm_mm_first_hole(mm, range_start, range_end, size, \
+  mode & ~DRM_MM_INSERT_ONCE); \
+pos; \
+pos = mode & DRM_MM_INSERT_ONCE ? \
+NULL : __drm_mm_next_hole(mm, pos, size, \
+  mode & ~DRM_MM_INSERT_ONCE))

-:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mm' - possible side-effects?
#153: FILE: include/drm/drm_mm.h:430:
+#define drm_mm_for_each_suitable_hole(pos, mm, range_start, range_end, \
+ size, mode) \
+   for (pos = __drm_mm_first_hole(mm, range_start, range_end, size, \
+  mode & ~DRM_MM_INSERT_ONCE); \
+pos; \
+pos = mode & DRM_MM_INSERT_ONCE ? \
+NULL : __drm_mm_next_hole(mm, pos, size, \
+  mode & ~DRM_MM_INSERT_ONCE))

-:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'size' - possible 
side-effects?
#153: FILE: include/drm/drm_mm.h:430:
+#define drm_mm_for_each_suitable_hole(pos, mm, range_start, range_end, \
+ size, mode) \
+   for (pos = __drm_mm_first_hole(mm, range_start, range_end, size, \
+  mode & ~DRM_MM_INSERT_ONCE); \
+pos; \
+pos = mode & DRM_MM_INSERT_ONCE ? \
+NULL : __drm_mm_next_hole(mm, pos, size, \
+  mode & ~DRM_MM_INSERT_ONCE))

-:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mode' - possible 
side-effects?
#153: FILE: include/drm/drm_mm.h:430:
+#define drm_mm_for_each_suitable_hole(pos, mm, range_start, range_end, \
+ size, mode) \
+   for (pos = __drm_mm_first_hole(mm, range_start, range_end, size, \
+  mode & ~DRM_MM_INSERT_ONCE); \
+pos; \
+pos = mode & DRM_MM_INSERT_ONCE ? \
+NULL : __drm_mm_next_hole(mm, pos, size, \
+  mode & ~DRM_MM_INSERT_ONCE))

-:153: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'mode' may be better as 
'(mode)' to avoid precedence issues
#153: FILE: include/drm/drm_mm.h:430:
+#define drm_mm_for_each_suitable_hole(pos, mm, range_start, range_end, \
+ size, mode) \
+   for (pos = __drm_mm_first_hole(mm, range_start, range_end, size, \
+  mode & ~DRM_MM_INSERT_ONCE); \
+pos; \
+pos = mode & DRM_MM_INSERT_ONCE ? \
+NULL : __drm_mm_next_hole(mm, pos, size, \
+  mode & ~DRM_MM_INSERT_ONCE))

total: 0 errors, 0 warnings, 5 checks, 114 lines checked
0a3739e5ef01 drm/i915/gem: Don't try to map and fence large scanout buffers (v9)

Re: [Intel-gfx] [PATCH 0/3] drm/helpers: Make the suballocation manager drm generic.

[Maarten Lankhorst]

Op 23-02-2022 om 16:11 schreef Christian König:
> Am 23.02.22 um 14:51 schrieb Maarten Lankhorst:
>> Second version of the patch. I didn't fix the copyright (which ame up
>> in the previous version), as I feel the original author should send a
>> patch for that.
>>
>> I've made the suballocator into its own module, and did a cleanup pass on it.
>> The suballocator is generic enough to be useful for any resource that can be
>> subdivided and is guarded by a completion fence.
>
> Well the main issue is still that you removed the per allocation alignment.
>
> For amdgpu that is not much of a problem, but for radeon that could cause 
> massive issues with UVD semaphore synchronization. 

Hey,

Is this really a problem? I made the per allocation alignment fixed and set it 
to the higher of the 2 places it's used in by radeon. This just means that 
slightly more memory might be allocated to each suballocation. This shouldn't 
cause any problem. It would reserve 256 bytes for a semaphore allocation, 
instead of 8.

~Maarten

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/helpers: Make the suballocation manager drm generic. (rev2)

[Patchwork]

== Series Details ==

Series: drm/helpers: Make the suballocation manager drm generic. (rev2)
URL   : https://patchwork.freedesktop.org/series/99713/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11277_full -> Patchwork_22385_full


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/index.html

Participating hosts (11 -> 8)
--

  Missing(3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 

Known issues


  Here are the changes found in Patchwork_22385_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-apl:  NOTRUN -> [DMESG-WARN][1] ([i915#4991])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/shard-apl8/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl:  [PASS][2] -> [DMESG-WARN][3] ([i915#180]) +4 similar 
issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-kbl1/igt@gem_ctx_isolation@preservation...@vcs0.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/shard-kbl1/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@gem_eio@kms:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#232])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-tglb6/igt@gem_...@kms.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/shard-tglb2/igt@gem_...@kms.html

  * igt@gem_eio@unwedge-stress:
- shard-skl:  [PASS][6] -> [TIMEOUT][7] ([i915#3063])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-skl9/igt@gem_...@unwedge-stress.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/shard-skl9/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_capture@pi@bcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][8] ([i915#4547])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/shard-skl10/igt@gem_exec_capture@p...@bcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/shard-apl3/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  [PASS][11] -> [FAIL][12] ([i915#2842]) +3 similar 
issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2849])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_whisper@basic-contexts-all:
- shard-glk:  [PASS][15] -> [DMESG-WARN][16] ([i915#118])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-glk8/igt@gem_exec_whis...@basic-contexts-all.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/shard-glk3/igt@gem_exec_whis...@basic-contexts-all.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-apl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/shard-apl6/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@heavy-verify-random:
- shard-kbl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/shard-kbl6/igt@gem_lmem_swapp...@heavy-verify-random.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +5 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/shard-skl1/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-verify:
- shard-glk:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/shard-glk4/igt@gem_lmem_swapp...@parallel-random-verify.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][21] ([i915#2658])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/shard-apl3/igt@gem_pr...@exhaustion.html
- shard-iclb: NOTRUN -> [WARN][22] ([i915#2658])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22385/shard-iclb5/igt@gem_pr...@exhaustion.html

  * igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-iclb: 

[Intel-gfx] [PATCH v2] drm/i915/display: Allow users to disable PSR2

[José Roberto de Souza]

Some users are suffering with PSR2 issues that are under debug or
issues that were root caused to panel firmware bugs, to make life of
those users easier here adding a option to disable PSR2 with kernel
parameters so they can still benefit from PSR1 power savings.

Using the same enable_psr that is current used to turn the whole
feature on or off and allowing user to select up to what PSR version
it should enable.
Right now users only set this parameter to 0 when they want to disable
PSR1 and PSR2 or don't add it at all leaving it to per-chip behavior
so it should not cause a bad impact on users.

v2:
- changing enable_psr values (Ville and Rodrigo)

Link: https://gitlab.freedesktop.org/drm/intel/-/issues/4951
Cc: Jouni Högander 
Cc: Rodrigo Vivi 
Cc: Ville Syrjälä 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/display/intel_psr.c | 4 
 drivers/gpu/drm/i915/i915_params.c   | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 2e0b092f4b6be..9817ebd4c839e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -100,11 +100,15 @@ static bool psr_global_enabled(struct intel_dp *intel_dp)
 
 static bool psr2_global_enabled(struct intel_dp *intel_dp)
 {
+   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_DISABLE:
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
default:
+   if (i915->params.enable_psr == 1)
+   return false;
return true;
}
 }
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index eea355c2fc28a..207b54a4e6ce7 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -94,7 +94,7 @@ i915_param_named_unsafe(enable_hangcheck, bool, 0400,
 
 i915_param_named_unsafe(enable_psr, int, 0400,
"Enable PSR "
-   "(0=disabled, 1=enabled) "
+   "(0=disabled, 1=enable up to PSR1, 2=enable up to PSR2) "
"Default: -1 (use per-chip default)");
 
 i915_param_named(psr_safest_params, bool, 0400,
-- 
2.35.1

Re: [Intel-gfx] [PATCH 0/3] Improve anti-pre-emption w/a for compute workloads

[John Harrison]

On 2/23/2022 04:00, Tvrtko Ursulin wrote:

On 23/02/2022 02:22, John Harrison wrote:

On 2/22/2022 01:53, Tvrtko Ursulin wrote:

On 18/02/2022 21:33, john.c.harri...@intel.com wrote:

From: John Harrison 

Compute workloads are inherently not pre-emptible on current hardware.
Thus the pre-emption timeout was disabled as a workaround to prevent
unwanted resets. Instead, the hang detection was left to the heartbeat
and its (longer) timeout. This is undesirable with GuC submission as
the heartbeat is a full GT reset rather than a per engine reset and so
is much more destructive. Instead, just bump the pre-emption timeout


Can we have a feature request to allow asking GuC for an engine reset?

For what purpose?


To allow "stopped heartbeat" to reset the engine, however..

GuC manages the scheduling of contexts across engines. With virtual 
engines, the KMD has no knowledge of which engine a context might be 
executing on. Even without virtual engines, the KMD still has no 
knowledge of which context is currently executing on any given engine 
at any given time.


There is a reason why hang detection should be left to the entity 
that is doing the scheduling. Any other entity is second guessing at 
best.


The reason for keeping the heartbeat around even when GuC submission 
is enabled is for the case where the KMD/GuC have got out of sync 
with either other somehow or GuC itself has just crashed. I.e. when 
no submission at all is working and we need to reset the GuC itself 
and start over.


.. I wasn't really up to speed to know/remember heartbeats are nerfed 
already in GuC mode.
Not sure what you mean by that claim. Engine resets are handled by GuC 
because GuC handles the scheduling. You can't do the former if you 
aren't doing the latter. However, the heartbeat is still present and is 
still the watchdog by which engine resets are triggered. As per the rest 
of the submission process, the hang detection and recovery is split 
between i915 and GuC.





I am not sure it was the best way since full reset penalizes everyone 
for one hanging engine. Better question would be why leave heartbeats 
around to start with with GuC? If you want to use it to health check 
GuC, as you say, maybe just send a CT message and expect replies? Then 
full reset would make sense. It also achieves the goal of not 
seconding guessing the submission backend you raise.
Adding yet another hang detection mechanism is yet more complication and 
is unnecessary when we already have one that works well enough. As 
above, the heartbeat is still required for sending the pulses that cause 
pre-emptions and so let GuC detect hangs. It also provides a fallback 
against a dead GuC by default. So why invent yet another wheel?




Like it is now, and the need for this series demonstrates it, the 
whole thing has a pretty poor "impedance" match. Not even sure what 
intel_guc_find_hung_context is doing in intel_engine_hearbeat.c - why 
is that not in intel_gt_handle_error at least? Why is hearbeat code 
special and other callers of intel_gt_handle_error don't need it?
There is no guilty context if the reset was triggered via debugfs or 
similar. And as stated ad nauseam, i915 is no longer handling the 
scheduling and so cannot make assumptions about what is or is not 
running on the hardware at any given time. And obviously, if the reset 
initiated by GuC itself then i915 should not be second guessing the 
guilty context as the GuC notification has already told us who was 
responsible.


And to be clear, the 'poor impedance match' is purely because we don't 
have mid-thread pre-emption and so need a stupidly huge timeout on 
compute capable engines. Whereas, we don't want a total heatbeat timeout 
of a minute or more. That is the impedance mis-match. If the 640ms was 
acceptable for RCS then none of this hacky timeout algorithm mush would 
be needed.


John.




Regards,

Tvrtko

Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Set "SF Partial Frame Enable" also on full update

[Lyude Paul]

Also - I realized this is missing an appropriate Fixes: tag for the commit
that enabled PSR2 selective fetch on tigerlake in the first place

On Wed, 2022-02-23 at 17:32 +, Souza, Jose wrote:
> On Wed, 2022-02-23 at 14:48 +0200, Jouni Högander wrote:
> > Currently we are observing occasional screen flickering when
> > PSR2 selective fetch is enabled. More specifically glitch seems
> > to happen on full frame update when cursor moves to coords
> > x = -1 or y = -1.
> > 
> > According to Bspec SF Single full frame should not be set if
> > SF Partial Frame Enable is not set. This happened to be true for
> > ADLP as PSR2_MAN_TRK_CTL_ENABLE is always set and for ADLP it's
> > actually "SF Partial Frame Enable" (Bit 31).
> > 
> > Setting "SF Partial Frame Enable" bit also on full update seems to
> > fix screen flickering.
> > 
> > Also make code more clear by setting PSR2_MAN_TRK_CTL_ENABLE
> > only if not on ADLP as this bit doesn't exist in ADLP.
> 
> Bit exist but has another name.
> 
> > 
> > Bspec: 49274
> > 
> > v2: Fix Mihai Harpau email address
> > 
> > Reported-by: Lyude Paul 
> > Cc: Mihai Harpau 
> > Cc: José Roberto de Souza 
> > Cc: Ville Syrjälä 
> > Bugzilla: https://gitlab.freedesktop.org/drm/intel/-/issues/5077
> > Signed-off-by: Jouni Högander 
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 20 ++--
> >  drivers/gpu/drm/i915/i915_reg.h  |  1 +
> >  2 files changed, 19 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 2e0b092f4b6b..90aca75e05e0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1439,6 +1439,13 @@ static inline u32
> > man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private
> >    PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> >  }
> >  
> > +static inline u32 man_trk_ctl_partial_frame_bit_get(struct
> > drm_i915_private *dev_priv)
> > +{
> > +   return IS_ALDERLAKE_P(dev_priv) ?
> > +  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE :
> > +  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > +}
> > +
> >  static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
> >  {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > @@ -1543,7 +1550,17 @@ static void psr2_man_trk_ctl_calc(struct
> > intel_crtc_state *crtc_state,
> >  {
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > -   u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> > +   u32 val = 0;
> > +
> > +   /*
> > +    * ADL_P doesn't have HW tracking nor manual tracking enable
> > +    * bit
> > +    */
> 
> Nit: Unnecessary comment.
> 
> Reviewed-by: José Roberto de Souza 
> 
> > +   if (!IS_ALDERLAKE_P(dev_priv))
> > +   val = PSR2_MAN_TRK_CTL_ENABLE;
> > +
> > +   /* SF partial frame enable has to be set even on full update */
> > +   val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
> >  
> > if (full_update) {
> > /*
> > @@ -1563,7 +1580,6 @@ static void psr2_man_trk_ctl_calc(struct
> > intel_crtc_state *crtc_state,
> > } else {
> > drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 ||
> > clip->y2 % 4);
> >  
> > -   val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4
> > + 1);
> > val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 +
> > 1);
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 2b8a3086ed35..89bbb64e520d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2316,6 +2316,7 @@
> >  #define 
> > ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)   REG_FIELD_PREP(ADLP_
> > PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> >  #define 
> > ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
> >  #define 
> > ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_
> > PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> > +#define 
> > ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
> >  #define 
> > ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAMEREG_BIT(14)
> >  #define 
> > ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
> >  
> 

-- 
Cheers,
 Lyude Paul (she/her)
 Software Engineer at Red Hat

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4)

[Saarinen, Jani]

Hi, 
> -Original Message-
> From: Navare, Manasi D 
> Sent: torstai 24. helmikuuta 2022 21.00
> To: intel-gfx@lists.freedesktop.org
> Cc: Sarvela, Tomi P ; Syrjala, Ville
> ; Saarinen, Jani ; Nikula, 
> Jani
> 
> Subject: RE: ✗ Fi.CI.BAT: failure for drm/i915/display/vrr: Reset VRR capable
> property on a long hpd (rev4)
> 
> Hi,
> 
> 
> 
> I fixed the regression in this patch and resent it, it still has BAT 
> failures, I wanted
> to understand if it failed to boot some of the machines again or the errors 
> flagged
> here are the known errors.
> 
> 
> 
> Regards
> 
> Manasi
> 
> 
> 
> From: Patchwork 
> Sent: Thursday, February 24, 2022 10:45 AM
> To: Navare, Manasi D 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: ✗ Fi.CI.BAT: failure for drm/i915/display/vrr: Reset VRR capable 
> property
> on a long hpd (rev4)
> 
> 
> 
> Patch Details
> 
> Series:
> 
> drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4)
> 
> URL:
> 
> https://patchwork.freedesktop.org/series/98801/
> 
> State:
> 
> failure
> 
> Details:
> 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/index.html
> 
> 
> CI Bug Log - changes from CI_DRM_11279 -> Patchwork_22394
> 
> 
> Summary
> 
> 
> FAILURE
> 
> Serious unknown changes coming with Patchwork_22394 absolutely need to be
> verified manually.
> 
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_22394, please notify your bug team to allow them to
> document this new failure mode, which will reduce false positives in CI.
> 
> External URL: https://intel-gfx-ci.01.org/tree/drm-
> tip/Patchwork_22394/index.html
> 
> 
> Participating hosts (43 -> 32)
> 
> 
> Missing (11): fi-kbl-soraka fi-cml-u2 fi-bsw-cyan fi-ilk-650 fi-apl-guc 
> fi-kbl-7500u fi-
> kbl-x1275 fi-cfl-8109u fi-bsw-kefka fi-bdw-samus fi-skl-6600u
Would be good to understand why there is this many systems down still. Also are 
these same than on previous series...
Previous was missing:
--
Missing (29): fi-kbl-soraka fi-bdw-gvtdvm fi-apl-guc fi-snb-2520m fi-skl-6600u 
fi-snb-2600 fi-cml-u2 fi-bxt-dsi fi-bdw-5557u shard-tglu fi-bsw-n3050 
fi-glk-dsi fi-ilk-650 fi-kbl-7500u fi-hsw-4770 fi-ivb-3770 fi-elk-e7500 
fi-bsw-nick fi-skl-6700k2 fi-kbl-7567u fi-skl-guc fi-cfl-8700k fi-bsw-cyan 
fi-cfl-guc fi-kbl-guc fi-kbl-x1275 fi-cfl-8109u fi-kbl-8809g fi-bsw-kefka
--
So there are same systems. Tomi, what is threshold how many systems need to 
have boot issues and having 
Just looking some same systems on both...:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/filelist.html 
eg. 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/fi-kbl-soraka/run0.txt 
and 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/fi-kbl-7500u/run0.txt 
, there is also oops 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/fi-kbl-7500u/pstore0-1645726566_Oops_1.txt
 
I would say not clean really yet


> 
> 
> Possible new issues
> 
> 
> Here are the unknown changes that may have been introduced in
> Patchwork_22394:
> 
> 
> IGT changes
> 
> 
> Possible regressions
> 
> 
> * igt@gem_exec_suspend@basic-s0@smem:
> 
>   *   fi-skl-6700k2: PASS  tip/CI_DRM_11279/fi-skl-6700k2/igt@gem_exec_suspend@basic-
> s...@smem.html>  -> DMESG-WARN  tip/Patchwork_22394/fi-skl-6700k2/igt@gem_exec_suspend@basic-
> s...@smem.html>
> 
> 
> Known issues
> 
> 
> Here are the changes found in Patchwork_22394 that come from known issues:
> 
> 
> IGT changes
> 
> 
> Issues hit
> 
> 
> * igt@amdgpu/amd_basic@cs-multi-fence:
> 
>   *   fi-blb-e6850: NOTRUN -> SKIP  ci.01.org/tree/drm-tip/Patchwork_22394/fi-blb-
> e6850/igt@amdgpu/amd_ba...@cs-multi-fence.html>  (fdo#109271
>  ) +17 similar issues
> 
> * igt@runner@aborted:
> 
>   *   fi-skl-6700k2: NOTRUN -> FAIL  ci.01.org/tree/drm-tip/Patchwork_22394/fi-skl-
> 6700k2/igt@run...@aborted.html>  (i915#4312
>  )
> 
> 
> Possible fixes
> 
> 
> * igt@i915_selftest@live@hangcheck:
> 
>   *   bat-dg1-6: DMESG-FAIL  tip/CI_DRM_11279/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html>
> (i915#4494   / i915#4957
>  ) -> PASS 
>  gfx-ci.01.org/tree/drm-tip/Patchwork_22394/bat-dg1-
> 6/igt@i915_selftest@l...@hangcheck.html>
> 
> * igt@i915_selftest@live@requests:
> 
>   *   fi-blb-e6850: DMESG-FAIL  tip/CI_DRM_11279/fi-blb-e6850/igt@i915_selftest@l...@requests.html>
> (i915#5026  ) -> PASS
>  

Re: [Intel-gfx] [PATCH 1/3] drm/i915/guc: Limit scheduling properties to avoid overflow

[John Harrison]

On 2/24/2022 11:19, John Harrison wrote:

[snip]

I'll change it to _uses_ and repost, then.


[    7.683149] kernel BUG at drivers/gpu/drm/i915/gt/uc/intel_guc.h:367!

Told you that one went bang.

John.

Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Set "SF Partial Frame Enable" also on full update

[Lyude Paul]

I'm back so I will try this patch on my machine and see if it helps, thank
you!

On Wed, 2022-02-23 at 14:48 +0200, Jouni Högander wrote:
> Currently we are observing occasional screen flickering when
> PSR2 selective fetch is enabled. More specifically glitch seems
> to happen on full frame update when cursor moves to coords
> x = -1 or y = -1.
> 
> According to Bspec SF Single full frame should not be set if
> SF Partial Frame Enable is not set. This happened to be true for
> ADLP as PSR2_MAN_TRK_CTL_ENABLE is always set and for ADLP it's
> actually "SF Partial Frame Enable" (Bit 31).
> 
> Setting "SF Partial Frame Enable" bit also on full update seems to
> fix screen flickering.
> 
> Also make code more clear by setting PSR2_MAN_TRK_CTL_ENABLE
> only if not on ADLP as this bit doesn't exist in ADLP.
> 
> Bspec: 49274
> 
> v2: Fix Mihai Harpau email address
> 
> Reported-by: Lyude Paul 
> Cc: Mihai Harpau 
> Cc: José Roberto de Souza 
> Cc: Ville Syrjälä 
> Bugzilla: https://gitlab.freedesktop.org/drm/intel/-/issues/5077
> Signed-off-by: Jouni Högander 
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 20 ++--
>  drivers/gpu/drm/i915/i915_reg.h  |  1 +
>  2 files changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2e0b092f4b6b..90aca75e05e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1439,6 +1439,13 @@ static inline u32
> man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private
>    PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
>  }
>  
> +static inline u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private
> *dev_priv)
> +{
> +   return IS_ALDERLAKE_P(dev_priv) ?
> +  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE :
> +  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> +}
> +
>  static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
>  {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -1543,7 +1550,17 @@ static void psr2_man_trk_ctl_calc(struct
> intel_crtc_state *crtc_state,
>  {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -   u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> +   u32 val = 0;
> +
> +   /*
> +    * ADL_P doesn't have HW tracking nor manual tracking enable
> +    * bit
> +    */
> +   if (!IS_ALDERLAKE_P(dev_priv))
> +   val = PSR2_MAN_TRK_CTL_ENABLE;
> +
> +   /* SF partial frame enable has to be set even on full update */
> +   val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
>  
> if (full_update) {
> /*
> @@ -1563,7 +1580,6 @@ static void psr2_man_trk_ctl_calc(struct
> intel_crtc_state *crtc_state,
> } else {
> drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 ||
> clip->y2 % 4);
>  
> -   val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 +
> 1);
> val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 +
> 1);
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 2b8a3086ed35..89bbb64e520d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2316,6 +2316,7 @@
>  #define 
> ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)   REG_FIELD_PREP(ADLP_PS
> R2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
>  #define 
> ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
>  #define 
> ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PS
> R2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> +#define  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
>  #define  ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAMEREG_BIT(14)
>  #define  ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
>  

-- 
Cheers,
 Lyude Paul (she/her)
 Software Engineer at Red Hat

Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Make the heartbeat play nice with long pre-emption timeouts

[John Harrison]

On 2/24/2022 03:41, Tvrtko Ursulin wrote:

On 23/02/2022 20:00, John Harrison wrote:

On 2/23/2022 05:58, Tvrtko Ursulin wrote:

On 23/02/2022 02:45, John Harrison wrote:

On 2/22/2022 03:19, Tvrtko Ursulin wrote:

On 18/02/2022 21:33, john.c.harri...@intel.com wrote:

From: John Harrison 

Compute workloads are inherantly not pre-emptible for long 
periods on

current hardware. As a workaround for this, the pre-emption timeout
for compute capable engines was disabled. This is undesirable 
with GuC
submission as it prevents per engine reset of hung contexts. 
Hence the

next patch will re-enable the timeout but bumped up by an order of
magnititude.


(Some typos above.)

I'm spotting 'inherently' but not anything else.


Magnititude! O;)

Doh!

[snip]

Whereas, bumping all heartbeat periods to be greater than the 
pre-emption timeout is wasteful and unnecessary. That leads to a 
total heartbeat time of about a minute. Which is a very long time 
to wait for a hang to be detected and recovered. Especially when 
the official limit on a context responding to an 'are you dead' 
query is only 7.5 seconds.


Not sure how did you get one minute?
7.5 * 2 (to be safe) = 15. 15 * 5 (number of heartbeat periods) = 75 
=> 1 minute 15 seconds


Even ignoring any safety factor and just going with 7.5 * 5 still 
gets you to 37.5 seconds which is over a half a minute and likely to 
race.


Ah because my starting point is there should be no preempt timeout = 
heartbeat * 3, I just think that's too ugly.
Then complain at the hardware designers to give us mid-thread 
pre-emption back. The heartbeat is only one source of pre-emption 
events. For example, a user can be running multiple contexts in parallel 
and expecting them to time slice on a single engine. Or maybe a user is 
just running one compute task in the background but is doing render work 
in the foreground. Etc.


There was a reason the original hack was to disable pre-emption rather 
than increase the heartbeat. This is simply a slightly less ugly version 
of the same hack. And unfortunately, the basic idea of the hack is 
non-negotiable.


As per other comments, 'tP(RCS) = tH *3' or 'tP(RCS) = tP(default) * 12' 
or 'tP(RCS) = 7500' are the available options. Given that the heartbeat 
is the ever present hard limit, it seems most plausible to base the hack 
on that. Any of the others works, though. Although I think a explicit 
hardcoded value is the most ugly. I guess the other option is to add 
CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE and default that to 7500.


Take your pick. But 640ms is not allowed.



Regardless, crux of argument was to avoid GuC engine reset and 
heartbeat reset racing with each other, and to do that by 
considering the preempt timeout with the heartbeat interval. I was 
thinking about this scenario in this series:


[Please use fixed width font and no line wrap to view.]

A)

tP = preempt timeout
tH = hearbeat interval

tP = 3 * tH

1) Background load = I915_PRIORITY_DISPLAY

<-- [tH] --> Pulse1 <-- [tH] --> Pulse2 <-- [tH] --> Pulse3 < [2 
* tH] > FULL RESET

   |
   \- preemption 
triggered, tP = 3 * tH --\

\-> preempt timeout would hit here

Here we have collateral damage due full reset, since we can't tell 
GuC to reset just one engine and we fudged tP just to "account" for 
heartbeats.
You are missing the whole point of the patch series which is that the 
last heartbeat period is '2 * tP' not '2 * tH'.

+        longer = READ_ONCE(engine->props.preempt_timeout_ms) * 2;

By making the last period double the pre-emption timeout, it is 
guaranteed that the FULL RESET stage cannot be hit before the 
hardware has attempted and timed-out on at least one pre-emption.


Oh well :) that probably means the overall scheme is too odd for me. 
tp = 3tH and last pulse after 2tP I mean.
To be accurate, it is 'tP(RCS) = 3 * tH(default); tH(final) = 
tP(current) * 2;'. Seems fairly straight forward to me. It's not a 
recursive definition or anything like that. It gives us a total 
heartbeat timeout that is close to the original version but still allows 
at least one pre-emption event.





[snip]


<-- [tH] --> Pulse1 <-- [tH] --> Pulse2 <-- [tH] --> Pulse3 < [2 
* tH] > full reset would be here

   |
   \- preemption triggered, tP = 3 * tH \
\-> Preempt timeout reset

Here is is kind of least worse, but question is why we fudged tP 
when it gives us nothing good in this case.


The point of fudging tP(RCS) is to give compute workloads longer to 
reach a pre-emptible point (given that EU walkers are basically not 
pre-emptible). The reason for doing the fudge is not connected to the 
heartbeat at all. The fact that it causes problems for the heartbeat 
is an undesired side effect.


Note that the use of 'tP(RCS) = tH * 3' was just an arbitrary 
calculation that gave us something that all 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix cursor coordinates on bigjoiner slave (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix cursor coordinates on bigjoiner slave (rev3)
URL   : https://patchwork.freedesktop.org/series/100154/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11277_full -> Patchwork_22384_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_22384_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-apl:  NOTRUN -> [DMESG-WARN][1] ([i915#4991])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-apl7/igt@gem_cre...@create-massive.html

  * igt@gem_eio@kms:
- shard-tglb: [PASS][2] -> [FAIL][3] ([i915#232])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-tglb6/igt@gem_...@kms.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-tglb5/igt@gem_...@kms.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][4] ([i915#4547])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-skl6/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][5] -> [FAIL][6] ([i915#2846])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-glk2/igt@gem_exec_f...@basic-deadline.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-glk8/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk:  [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-glk8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-glk3/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl:  [PASS][9] -> [FAIL][10] ([i915#2842]) +2 similar 
issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-kbl3/igt@gem_exec_fair@basic-n...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-kbl1/igt@gem_exec_fair@basic-n...@rcs0.html

  * igt@gem_exec_fair@basic-none@vecs0:
- shard-apl:  [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-apl4/igt@gem_exec_fair@basic-n...@vecs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-apl3/igt@gem_exec_fair@basic-n...@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2849])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_whisper@basic-contexts-all:
- shard-glk:  [PASS][15] -> [DMESG-WARN][16] ([i915#118])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/shard-glk8/igt@gem_exec_whis...@basic-contexts-all.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-glk3/igt@gem_exec_whis...@basic-contexts-all.html

  * igt@gem_lmem_swapping@heavy-multi:
- shard-kbl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-kbl3/igt@gem_lmem_swapp...@heavy-multi.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-apl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-apl3/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-skl10/igt@gem_lmem_swapp...@parallel-random.html
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#4613])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-iclb3/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-verify:
- shard-glk:  NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-glk8/igt@gem_lmem_swapp...@parallel-random-verify.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][22] ([i915#2658])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-apl2/igt@gem_pr...@exhaustion.html
- shard-iclb: NOTRUN -> [WARN][23] ([i915#2658])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22384/shard-iclb8/igt@gem_pr...@exhaustion.html

  * 

Re: [Intel-gfx] [PATCH 1/3] drm/i915/guc: Limit scheduling properties to avoid overflow

[John Harrison]

On 2/24/2022 01:59, Tvrtko Ursulin wrote:

On 23/02/2022 19:03, John Harrison wrote:

On 2/23/2022 04:13, Tvrtko Ursulin wrote:

On 23/02/2022 02:11, John Harrison wrote:

On 2/22/2022 01:52, Tvrtko Ursulin wrote:

On 18/02/2022 21:33, john.c.harri...@intel.com wrote:

From: John Harrison 

GuC converts the pre-emption timeout and timeslice quantum values 
into
clock ticks internally. That significantly reduces the point of 
32bit

overflow. On current platforms, worst case scenario is approximately


Where does 32-bit come from, the GuC side? We already use 64-bits 
so that something to fix to start with. Yep...
Yes, the GuC API is defined as 32bits only and then does a straight 
multiply by the clock speed with no range checking. We have 
requested 64bit support but there was push back on the grounds that 
it is not something the GuC timer hardware supports and such long 
timeouts are not real world usable anyway.


As long as compute are happy with 100 seconds, then it "should be 
enough for everbody". :D

Compute disable all forms of reset and rely on manual kill. So yes.

But even if they aren't. That's all we can do at the moment. If there 
is a genuine customer requirement for more then we can push for full 
64bit software implemented timers in the GuC but until that happens, 
we don't have much choice.


Yeah.







./gt/uc/intel_guc_fwif.h:   u32 execution_quantum;

./gt/uc/intel_guc_submission.c: desc->execution_quantum = 
engine->props.timeslice_duration_ms * 1000;


./gt/intel_engine_types.h:  unsigned long 
timeslice_duration_ms;


timeslice_store/preempt_timeout_store:
err = kstrtoull(buf, 0, );

So both kconfig and sysfs can already overflow GuC, not only 
because of tick conversion internally but because at backend level 
nothing was done for assigning 64-bit into 32-bit. Or I failed to 
find where it is handled.
That's why I'm adding this range check to make sure we don't allow 
overflows.


Yes and no, this fixes it, but the first bug was not only due GuC 
internal tick conversion. It was present ever since the u64 from 
i915 was shoved into u32 sent to GuC. So even if GuC used the value 
without additional multiplication, bug was be there. My point being 
when GuC backend was added timeout_ms values should have been 
limited/clamped to U32_MAX. The tick discovery is additional limit 
on top.
I'm not disagreeing. I'm just saying that the truncation wasn't 
noticed until I actually tried using very long timeouts to debug a 
particular problem. Now that it is noticed, we need some method of 
range checking and this simple clamp solves all the truncation problems.


Agreed in principle, just please mention in the commit message all 
aspects of the problem.


I think we can get away without a Fixes: tag since it requires user 
fiddling to break things in unexpected ways.


I would though put in a code a clamping which expresses both, 
something like min(u32, ..GUC LIMIT..). So the full story is 
documented forever. Or "if > u32 || > ..GUC LIMIT..) return -EINVAL". 
Just in case GuC limit one day changes but u32 stays. Perhaps internal 
ticks go away or anything and we are left with plain 1:1 millisecond 
relationship.
Can certainly add a comment along the lines of "GuC API only takes a 
32bit field but that is further reduced to GUC_LIMIT due to internal 
calculations which would otherwise overflow".


But if the GuC limit is > u32 then, by definition, that means the GuC 
API has changed to take a u64 instead of a u32. So there will no u32 
truncation any more. So I'm not seeing a need to explicitly test the 
integer size when the value check covers that.





110 seconds. Rather than allowing the user to set higher values and
then get confused by early timeouts, add limits when setting these
values.


Btw who is reviewing GuC patches these days - things have somehow 
gotten pretty quiet in activity and I don't think that's due 
absence of stuff to improve or fix? Asking since I think I noticed 
a few already which you posted and then crickets on the mailing list.

Too much work to do and not enough engineers to do it all :(.





Signed-off-by: John Harrison 
---
  drivers/gpu/drm/i915/gt/intel_engine_cs.c   | 15 +++
  drivers/gpu/drm/i915/gt/sysfs_engines.c | 14 ++
  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h |  9 +
  3 files changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c

index e53008b4dd05..2a1e9f36e6f5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -389,6 +389,21 @@ static int intel_engine_setup(struct 
intel_gt *gt, enum intel_engine_id id,

  if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
  engine->props.preempt_timeout_ms = 0;
  +    /* Cap timeouts to prevent overflow inside GuC */
+    if (intel_guc_submission_is_wanted(>uc.guc)) {
+    if 

[Intel-gfx] ✗ Fi.CI.BAT: failure for Bump DMC to v2.16 on ADL-P

[Patchwork]

== Series Details ==

Series: Bump DMC to v2.16 on ADL-P
URL   : https://patchwork.freedesktop.org/series/100666/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11279 -> Patchwork_22395


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22395 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22395, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22395/index.html

Participating hosts (43 -> 39)
--

  Additional (1): fi-pnv-d510 
  Missing(5): fi-kbl-soraka fi-bsw-cyan fi-apl-guc fi-bsw-kefka 
fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22395:

### IGT changes ###

 Possible regressions 

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-cml-u2:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/fi-cml-u2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22395/fi-cml-u2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  
Known issues


  Here are the changes found in Patchwork_22395 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-multi-fence:
- fi-blb-e6850:   NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22395/fi-blb-e6850/igt@amdgpu/amd_ba...@cs-multi-fence.html

  * igt@gem_huc_copy@huc-copy:
- fi-skl-6600u:   NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22395/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u:   NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22395/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html

  * igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u:   NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22395/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u:   NOTRUN -> [SKIP][7] ([fdo#109271]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22395/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-connector-state:
- fi-cfl-8109u:   [PASS][8] -> [DMESG-WARN][9] ([i915#165]) +1 similar 
issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/fi-cfl-8109u/igt@kms_force_connector_ba...@force-connector-state.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22395/fi-cfl-8109u/igt@kms_force_connector_ba...@force-connector-state.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u:   NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#533])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22395/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_page_flip:
- fi-skl-6600u:   NOTRUN -> [FAIL][11] ([i915#4547])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22395/fi-skl-6600u/igt@kms_psr@primary_page_flip.html

  * igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][12] ([fdo#109271]) +57 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22395/fi-pnv-d510/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@debugfs_test@read_all_entries:
- fi-cfl-8109u:   [DMESG-WARN][13] ([i915#203] / [i915#262] / 
[i915#295]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22395/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html

  * igt@gem_exec_suspend@basic-s0@smem:
- fi-cfl-8109u:   [DMESG-WARN][15] ([i915#203] / [i915#295]) -> 
[PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/fi-cfl-8109u/igt@gem_exec_suspend@basic...@smem.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22395/fi-cfl-8109u/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_flink_basic@bad-flink:
- fi-skl-6600u:   [INCOMPLETE][17] ([i915#4547]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
   [18]: 

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4)

[Navare, Manasi D]

Hi,

I fixed the regression in this patch and resent it, it still has BAT failures, 
I wanted to understand if it failed to boot some of the machines again or the 
errors flagged here are the known errors.

Regards
Manasi

From: Patchwork 
Sent: Thursday, February 24, 2022 10:45 AM
To: Navare, Manasi D 
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failure for drm/i915/display/vrr: Reset VRR capable 
property on a long hpd (rev4)

Patch Details
Series:

drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4)

URL:

https://patchwork.freedesktop.org/series/98801/

State:

failure

Details:

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/index.html

CI Bug Log - changes from CI_DRM_11279 -> Patchwork_22394
Summary

FAILURE

Serious unknown changes coming with Patchwork_22394 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22394, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/index.html

Participating hosts (43 -> 32)

Missing (11): fi-kbl-soraka fi-cml-u2 fi-bsw-cyan fi-ilk-650 fi-apl-guc 
fi-kbl-7500u fi-kbl-x1275 fi-cfl-8109u fi-bsw-kefka fi-bdw-samus fi-skl-6600u

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_22394:

IGT changes
Possible regressions

  *   igt@gem_exec_suspend@basic-s0@smem:
 *   fi-skl-6700k2: 
PASS
 -> 
DMESG-WARN

Known issues

Here are the changes found in Patchwork_22394 that come from known issues:

IGT changes
Issues hit

  *   igt@amdgpu/amd_basic@cs-multi-fence:
 *   fi-blb-e6850: NOTRUN -> 
SKIP
 (fdo#109271) +17 similar 
issues
  *   igt@runner@aborted:
 *   fi-skl-6700k2: NOTRUN -> 
FAIL
 (i915#4312)

Possible fixes

  *   igt@i915_selftest@live@hangcheck:
 *   bat-dg1-6: 
DMESG-FAIL
 (i915#4494 / 
i915#4957) -> 
PASS
  *   igt@i915_selftest@live@requests:
 *   fi-blb-e6850: 
DMESG-FAIL
 (i915#5026) -> 
PASS
  *   igt@i915_selftest@live@workarounds:
 *   {bat-adlp-6}: 
DMESG-WARN
 (i915#5068) -> 
PASS
  *   igt@kms_flip@basic-flip-vs-modeset@a-edp1:
 *   {bat-adlp-6}: 
DMESG-WARN
 (i915#3576) -> 
PASS

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Build changes

  *   Linux: CI_DRM_11279 -> Patchwork_22394

CI-20190529: 20190529
CI_DRM_11279: 5301cc85b3cc0eaa37405a117c77a35db7f4a76d @ 
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6356: b403d8e73c6888561eaec97835688313b0763ce9 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22394: 244f36e5190c176be3ec2fbc9fc18c63b8383621 @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

244f36e5190c drm/i915/display/vrr: Reset VRR capable property on a long hpd

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4)
URL   : https://patchwork.freedesktop.org/series/98801/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11279 -> Patchwork_22394


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22394 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22394, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/index.html

Participating hosts (43 -> 32)
--

  Missing(11): fi-kbl-soraka fi-cml-u2 fi-bsw-cyan fi-ilk-650 fi-apl-guc 
fi-kbl-7500u fi-kbl-x1275 fi-cfl-8109u fi-bsw-kefka fi-bdw-samus fi-skl-6600u 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22394:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_suspend@basic-s0@smem:
- fi-skl-6700k2:  [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/fi-skl-6700k2/igt@gem_exec_suspend@basic...@smem.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/fi-skl-6700k2/igt@gem_exec_suspend@basic...@smem.html

  
Known issues


  Here are the changes found in Patchwork_22394 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-multi-fence:
- fi-blb-e6850:   NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/fi-blb-e6850/igt@amdgpu/amd_ba...@cs-multi-fence.html

  * igt@runner@aborted:
- fi-skl-6700k2:  NOTRUN -> [FAIL][4] ([i915#4312])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/fi-skl-6700k2/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-6:  [DMESG-FAIL][5] ([i915#4494] / [i915#4957]) -> 
[PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [DMESG-FAIL][7] ([i915#5026]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@workarounds:
- {bat-adlp-6}:   [DMESG-WARN][9] ([i915#5068]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/bat-adlp-6/igt@i915_selftest@l...@workarounds.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}:   [DMESG-WARN][11] ([i915#3576]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026
  [i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068


Build changes
-

  * Linux: CI_DRM_11279 -> Patchwork_22394

  CI-20190529: 20190529
  CI_DRM_11279: 5301cc85b3cc0eaa37405a117c77a35db7f4a76d @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6356: b403d8e73c6888561eaec97835688313b0763ce9 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22394: 244f36e5190c176be3ec2fbc9fc18c63b8383621 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

244f36e5190c drm/i915/display/vrr: Reset VRR capable property on a long hpd

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22394/index.html

Re: [Intel-gfx] [PATCH] drm/i915: s/JSP2/ICP2/ PCH

[Kasireddy, Vivek]

Acked-by: Vivek Kasireddy 

> -Original Message-
> From: Ville Syrjala 
> Sent: Thursday, February 24, 2022 5:22 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D ; Kasireddy, Vivek
> 
> Subject: [PATCH] drm/i915: s/JSP2/ICP2/ PCH
> 
> From: Ville Syrjälä 
> 
> This JSP2 PCH actually seems to to be some special Apple
> specific ICP variant rather than a JSP. Make it so. Or at
> least all the references to it seem to be some Apple ICL
> machines. Didn't manage to find these PCI IDs in any
> public chipset docs unfortunately.
> 
> The only thing we're losing here with this JSP->ICP change
> is Wa_14011294188, but based on the HSD that isn't actually
> needed on any ICP based design (including JSP), only TGP
> based stuff (including MCC) really need it. The documented
> w/a just never made that distinction because Windows didn't
> want to differentiate between JSP and MCC (not sure how
> they handle hpd/ddc/etc. then though...).
> 
> Cc: Matt Roper 
> Cc: Vivek Kasireddy 
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4226
> Fixes: 943682e3bd19 ("drm/i915: Introduce Jasper Lake PCH")
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_pch.c | 2 +-
>  drivers/gpu/drm/i915/intel_pch.h | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pch.c 
> b/drivers/gpu/drm/i915/intel_pch.c
> index 4f7a61d5502e..4cce044efde2 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -108,6 +108,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
> unsigned short id)
>   /* Comet Lake V PCH is based on KBP, which is SPT compatible */
>   return PCH_SPT;
>   case INTEL_PCH_ICP_DEVICE_ID_TYPE:
> + case INTEL_PCH_ICP2_DEVICE_ID_TYPE:
>   drm_dbg_kms(_priv->drm, "Found Ice Lake PCH\n");
>   drm_WARN_ON(_priv->drm, !IS_ICELAKE(dev_priv));
>   return PCH_ICP;
> @@ -123,7 +124,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
> unsigned short id)
>   !IS_GEN9_BC(dev_priv));
>   return PCH_TGP;
>   case INTEL_PCH_JSP_DEVICE_ID_TYPE:
> - case INTEL_PCH_JSP2_DEVICE_ID_TYPE:
>   drm_dbg_kms(_priv->drm, "Found Jasper Lake PCH\n");
>   drm_WARN_ON(_priv->drm, !IS_JSL_EHL(dev_priv));
>   return PCH_JSP;
> diff --git a/drivers/gpu/drm/i915/intel_pch.h 
> b/drivers/gpu/drm/i915/intel_pch.h
> index 6fd20408f7bf..b7a8cf409d48 100644
> --- a/drivers/gpu/drm/i915/intel_pch.h
> +++ b/drivers/gpu/drm/i915/intel_pch.h
> @@ -50,11 +50,11 @@ enum intel_pch {
>  #define INTEL_PCH_CMP2_DEVICE_ID_TYPE0x0680
>  #define INTEL_PCH_CMP_V_DEVICE_ID_TYPE   0xA380
>  #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
> +#define INTEL_PCH_ICP2_DEVICE_ID_TYPE0x3880
>  #define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
>  #define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080
>  #define INTEL_PCH_TGP2_DEVICE_ID_TYPE0x4380
>  #define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
> -#define INTEL_PCH_JSP2_DEVICE_ID_TYPE0x3880
>  #define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
>  #define INTEL_PCH_ADP2_DEVICE_ID_TYPE0x5180
>  #define INTEL_PCH_ADP3_DEVICE_ID_TYPE0x7A00
> --
> 2.34.1

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev2)
URL   : https://patchwork.freedesktop.org/series/100633/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11276 -> Patchwork_22382


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22382 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22382, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22382/index.html

Participating hosts (49 -> 45)
--

  Additional (3): fi-kbl-soraka fi-icl-u2 fi-pnv-d510 
  Missing(7): fi-bdw-5557u fi-hsw-4200u fi-ctg-p8600 fi-hsw-4770 shard-rkl 
bat-jsl-2 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22382:

### CI changes ###

 Possible regressions 

  * boot:
- fi-ivb-3770:[PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/fi-ivb-3770/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22382/fi-ivb-3770/boot.html

  

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * 
{igt@kms_plane_scaling@upscale-with-rotation-factor-4@pipe-c-upscale-with-rotation}:
- {shard-dg1}:NOTRUN -> [SKIP][3] +3 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22382/shard-dg1-18/igt@kms_plane_scaling@upscale-with-rotation-facto...@pipe-c-upscale-with-rotation.html

  
Known issues


  Here are the changes found in Patchwork_22382 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-blb-e6850:   NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22382/fi-blb-e6850/igt@amdgpu/amd_cs_...@fork-compute0.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][5] ([fdo#109271]) +8 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22382/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u:   NOTRUN -> [INCOMPLETE][6] ([i915#4547])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22382/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][7] ([fdo#109271]) +57 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22382/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22382/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
- fi-icl-u2:  NOTRUN -> [SKIP][9] ([i915#2190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22382/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([i915#4613]) +3 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22382/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22382/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][12] ([i915#1886] / [i915#2291])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22382/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@dp-edid-read:
- fi-kbl-soraka:  NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22382/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][14] ([fdo#111827]) +8 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22382/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([fdo#109278]) +1 similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22382/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_flip@basic-plain-flip@b-dp2:
- fi-icl-u2:  NOTRUN -> [DMESG-WARN][16] ([i915#4890])
   [16]: 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4)
URL   : https://patchwork.freedesktop.org/series/98801/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
244f36e5190c drm/i915/display/vrr: Reset VRR capable property on a long hpd
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#10: 
With some VRR panels, user can turn VRR ON/OFF on the fly from the panel 
settings.

-:22: WARNING:TYPO_SPELLING: 'reseting' may be misspelled - perhaps 'resetting'?
#22: 
v5: Fixes the regression on older platforms by reseting the VRR
   

total: 0 errors, 2 warnings, 0 checks, 36 lines checked

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dmc: Do not try loading wrong DMC version

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Do not try loading wrong DMC version
URL   : https://patchwork.freedesktop.org/series/100664/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11279 -> Patchwork_22393


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22393/index.html

Participating hosts (43 -> 42)
--

  Additional (1): fi-pnv-d510 
  Missing(2): fi-bsw-cyan fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22393 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-multi-fence:
- fi-blb-e6850:   NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22393/fi-blb-e6850/igt@amdgpu/amd_ba...@cs-multi-fence.html

  * igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][2] ([fdo#109271]) +57 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22393/fi-pnv-d510/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@debugfs_test@read_all_entries:
- fi-cfl-8109u:   [DMESG-WARN][3] ([i915#203] / [i915#262] / 
[i915#295]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22393/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html

  * igt@gem_exec_suspend@basic-s0@smem:
- fi-cfl-8109u:   [DMESG-WARN][5] ([i915#203] / [i915#295]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/fi-cfl-8109u/igt@gem_exec_suspend@basic...@smem.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22393/fi-cfl-8109u/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [DMESG-FAIL][7] ([i915#5026]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22393/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@workarounds:
- {bat-adlp-6}:   [DMESG-WARN][9] ([i915#5068]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22393/bat-adlp-6/igt@i915_selftest@l...@workarounds.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2:  [DMESG-WARN][11] ([i915#4269]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22393/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u:   [DMESG-WARN][13] ([i915#295]) -> [PASS][14] +13 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22393/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html

  
 Warnings 

  * igt@gem_flink_basic@bad-flink:
- fi-skl-6600u:   [INCOMPLETE][15] ([i915#4547]) -> [FAIL][16] 
([i915#4547])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22393/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html

  * igt@runner@aborted:
- fi-skl-6600u:   [FAIL][17] ([i915#2722] / [i915#4312]) -> [FAIL][18] 
([i915#4312])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11279/fi-skl-6600u/igt@run...@aborted.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22393/fi-skl-6600u/igt@run...@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
  [i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026
  [i915#5068]: 

Re: [Intel-gfx] [PATCH v2] drm/i915/display: Use unions per platform in intel_dpll_hw_state

[Imre Deak]

On Thu, Feb 24, 2022 at 07:48:10PM +0200, Souza, Jose wrote:
> On Thu, 2022-02-24 at 17:39 +0200, Ville Syrjälä wrote:
> > On Thu, Feb 24, 2022 at 01:49:36PM +, Souza, Jose wrote:
> > > On Thu, 2022-02-24 at 15:25 +0200, Ville Syrjälä wrote:
> > > > On Thu, Feb 24, 2022 at 01:17:35PM +, Souza, Jose wrote:
> > > > > On Thu, 2022-02-24 at 12:20 +0200, Ville Syrjälä wrote:
> > > > > > On Wed, Feb 23, 2022 at 12:55:51PM -0800, José Roberto de Souza 
> > > > > > wrote:
> > > > > > 
> > > > > > > + union {
> > > > > > > + /* icl+ TC */
> > > > > > > + struct {
> > > > > > > + u32 mg_refclkin_ctl;
> > > > > > > + u32 mg_clktop2_coreclkctl1;
> > > > > > > + u32 mg_clktop2_hsclkctl;
> > > > > > > + u32 mg_pll_div0;
> > > > > > > + u32 mg_pll_div1;
> > > > > > > + u32 mg_pll_lf;
> > > > > > > + u32 mg_pll_frac_lock;
> > > > > > > + u32 mg_pll_ssc;
> > > > > > > + u32 mg_pll_bias;
> > > > > > > + u32 mg_pll_tdc_coldst_bias;
> > > > > > > + u32 mg_pll_bias_mask;
> > > > > > > + u32 mg_pll_tdc_coldst_bias_mask;
> > > > > > > + };
> > > > > > > +
> > > > > > > + /* bxt */
> > > > > > > + struct {
> > > > > > > + /* bxt */
> > > > > > > + u32 ebb0;
> > > > > > > + u32 ebb4;
> > > > > > > + u32 pll0;
> > > > > > > + u32 pll1;
> > > > > > > + u32 pll2;
> > > > > > > + u32 pll3;
> > > > > > > + u32 pll6;
> > > > > > > + u32 pll8;
> > > > > > > + u32 pll9;
> > > > > > > + u32 pll10;
> > > > > > > + u32 pcsdw12;
> > > > > > > + };
> > > > > > 
> > > > > > Wasn't there some funny compiler bug around anonymous unions?
> > > > > > git log --grep='anon.*union' seems to agree. Please double check
> > > > > > that stuff to make sure this is actually safe.
> > > > > 
> > > > > I don't see any patch referring to compiler issues with 'git log 
> > > > > --grep='anon.*union', what I see is other subsystems making use of it 
> > > > > too.
> > > > > Can you share the commit hash that you are referring to?
> > > > 
> > > > $ git log --format=oneline --grep='anon.*union' -- drivers/gpu/drm/i915
> > > > 
> > > 
> > > I see issues with initialization of anonymous union but we don't 
> > > initialize intel_dpll_hw_state.
> > > Also it was fixed on GCC 4.6 that is older than current GCC requirement 
> > > to build kernel(GCC 5.1).
> > > 
> > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=10676
> > 
> > OK. However, after pondering this a bit I think naming things wpild
> > probably be better here. You have a bunch of if ladders now where each
> > branch only operates on one of the structs inside the union. IMO the
> > anonymity is making it rather hard to see if the code is even correct.
> 
> Just to mare sure we are in the same page, you want to have this?
> 
> 
> struct icl_tc {
>   u32 mg_refclkin_ctl;
>   u32 mg_clktop2_coreclkctl1;
>   u32 mg_clktop2_hsclkctl;
>   u32 mg_pll_div0;
>   u32 mg_pll_div1;
>   u32 mg_pll_lf;
>   u32 mg_pll_frac_lock;
>   u32 mg_pll_ssc;
>   u32 mg_pll_bias;
>   u32 mg_pll_tdc_coldst_bias;
>   u32 mg_pll_bias_mask;
>   u32 mg_pll_tdc_coldst_bias_mask;
> };
> 
> So we would need to access members with icl_tc.mg_refclkin_ctl?
> 
> I can do that but the diff will be huge.
> Are you okay with that too Imre?

Yes, makes sense to clarify the type of PLL params at each place they
are used.

Re: [Intel-gfx] [PATCH v2] drm/i915/display: Use unions per platform in intel_dpll_hw_state

[Ville Syrjälä]

On Thu, Feb 24, 2022 at 05:48:10PM +, Souza, Jose wrote:
> On Thu, 2022-02-24 at 17:39 +0200, Ville Syrjälä wrote:
> > On Thu, Feb 24, 2022 at 01:49:36PM +, Souza, Jose wrote:
> > > On Thu, 2022-02-24 at 15:25 +0200, Ville Syrjälä wrote:
> > > > On Thu, Feb 24, 2022 at 01:17:35PM +, Souza, Jose wrote:
> > > > > On Thu, 2022-02-24 at 12:20 +0200, Ville Syrjälä wrote:
> > > > > > On Wed, Feb 23, 2022 at 12:55:51PM -0800, José Roberto de Souza 
> > > > > > wrote:
> > > > > > 
> > > > > > > + union {
> > > > > > > + /* icl+ TC */
> > > > > > > + struct {
> > > > > > > + u32 mg_refclkin_ctl;
> > > > > > > + u32 mg_clktop2_coreclkctl1;
> > > > > > > + u32 mg_clktop2_hsclkctl;
> > > > > > > + u32 mg_pll_div0;
> > > > > > > + u32 mg_pll_div1;
> > > > > > > + u32 mg_pll_lf;
> > > > > > > + u32 mg_pll_frac_lock;
> > > > > > > + u32 mg_pll_ssc;
> > > > > > > + u32 mg_pll_bias;
> > > > > > > + u32 mg_pll_tdc_coldst_bias;
> > > > > > > + u32 mg_pll_bias_mask;
> > > > > > > + u32 mg_pll_tdc_coldst_bias_mask;
> > > > > > > + };
> > > > > > > +
> > > > > > > + /* bxt */
> > > > > > > + struct {
> > > > > > > + /* bxt */
> > > > > > > + u32 ebb0;
> > > > > > > + u32 ebb4;
> > > > > > > + u32 pll0;
> > > > > > > + u32 pll1;
> > > > > > > + u32 pll2;
> > > > > > > + u32 pll3;
> > > > > > > + u32 pll6;
> > > > > > > + u32 pll8;
> > > > > > > + u32 pll9;
> > > > > > > + u32 pll10;
> > > > > > > + u32 pcsdw12;
> > > > > > > + };
> > > > > > 
> > > > > > Wasn't there some funny compiler bug around anonymous unions?
> > > > > > git log --grep='anon.*union' seems to agree. Please double check
> > > > > > that stuff to make sure this is actually safe.
> > > > > 
> > > > > I don't see any patch referring to compiler issues with 'git log 
> > > > > --grep='anon.*union', what I see is other subsystems making use of it 
> > > > > too.
> > > > > Can you share the commit hash that you are referring to?
> > > > 
> > > > $ git log --format=oneline --grep='anon.*union' -- drivers/gpu/drm/i915
> > > > 
> > > 
> > > I see issues with initialization of anonymous union but we don't 
> > > initialize intel_dpll_hw_state.
> > > Also it was fixed on GCC 4.6 that is older than current GCC requirement 
> > > to build kernel(GCC 5.1).
> > > 
> > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=10676
> > 
> > OK. However, after pondering this a bit I think naming things wpild
> > probably be better here. You have a bunch of if ladders now where each
> > branch only operates on one of the structs inside the union. IMO the
> > anonymity is making it rather hard to see if the code is even correct.
> 
> Just to mare sure we are in the same page, you want to have this?
> 
> 
> struct icl_tc {
>   u32 mg_refclkin_ctl;
>   u32 mg_clktop2_coreclkctl1;
>   u32 mg_clktop2_hsclkctl;
>   u32 mg_pll_div0;
>   u32 mg_pll_div1;
>   u32 mg_pll_lf;
>   u32 mg_pll_frac_lock;
>   u32 mg_pll_ssc;
>   u32 mg_pll_bias;
>   u32 mg_pll_tdc_coldst_bias;
>   u32 mg_pll_bias_mask;
>   u32 mg_pll_tdc_coldst_bias_mask;
> };

struct {

} whatever;

In this case the name that immediately came to mind was just "mg"
(+ then drop the extra mg_ namespace in the members).

We could name the types too I guess if we wanted to use those
somewhere. Eg. instead of passing in the whole union to some
function we could just pass in the specific substruct.

> 
> So we would need to access members with icl_tc.mg_refclkin_ctl?
> 
> I can do that but the diff will be huge.
> Are you okay with that too Imre?
> 
> 
> > 
> 

-- 
Ville Syrjälä
Intel

[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm-intel-gt tree

[broonie]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

between commit:

  721fd84ea1fe9 ("drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for 
reference")

from the drm-intel-gt tree and commit:

  b3f74938d6566 ("drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for 
reference")

from the drm-intel tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 04b8321fc7587,b3a429a92c0da..0
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

[Used drm-next version]

Re: [Intel-gfx] [PATCH v2] drm/i915/display: Use unions per platform in intel_dpll_hw_state

[Souza, Jose]

On Thu, 2022-02-24 at 17:39 +0200, Ville Syrjälä wrote:
> On Thu, Feb 24, 2022 at 01:49:36PM +, Souza, Jose wrote:
> > On Thu, 2022-02-24 at 15:25 +0200, Ville Syrjälä wrote:
> > > On Thu, Feb 24, 2022 at 01:17:35PM +, Souza, Jose wrote:
> > > > On Thu, 2022-02-24 at 12:20 +0200, Ville Syrjälä wrote:
> > > > > On Wed, Feb 23, 2022 at 12:55:51PM -0800, José Roberto de Souza wrote:
> > > > > 
> > > > > > +   union {
> > > > > > +   /* icl+ TC */
> > > > > > +   struct {
> > > > > > +   u32 mg_refclkin_ctl;
> > > > > > +   u32 mg_clktop2_coreclkctl1;
> > > > > > +   u32 mg_clktop2_hsclkctl;
> > > > > > +   u32 mg_pll_div0;
> > > > > > +   u32 mg_pll_div1;
> > > > > > +   u32 mg_pll_lf;
> > > > > > +   u32 mg_pll_frac_lock;
> > > > > > +   u32 mg_pll_ssc;
> > > > > > +   u32 mg_pll_bias;
> > > > > > +   u32 mg_pll_tdc_coldst_bias;
> > > > > > +   u32 mg_pll_bias_mask;
> > > > > > +   u32 mg_pll_tdc_coldst_bias_mask;
> > > > > > +   };
> > > > > > +
> > > > > > +   /* bxt */
> > > > > > +   struct {
> > > > > > +   /* bxt */
> > > > > > +   u32 ebb0;
> > > > > > +   u32 ebb4;
> > > > > > +   u32 pll0;
> > > > > > +   u32 pll1;
> > > > > > +   u32 pll2;
> > > > > > +   u32 pll3;
> > > > > > +   u32 pll6;
> > > > > > +   u32 pll8;
> > > > > > +   u32 pll9;
> > > > > > +   u32 pll10;
> > > > > > +   u32 pcsdw12;
> > > > > > +   };
> > > > > 
> > > > > Wasn't there some funny compiler bug around anonymous unions?
> > > > > git log --grep='anon.*union' seems to agree. Please double check
> > > > > that stuff to make sure this is actually safe.
> > > > 
> > > > I don't see any patch referring to compiler issues with 'git log 
> > > > --grep='anon.*union', what I see is other subsystems making use of it 
> > > > too.
> > > > Can you share the commit hash that you are referring to?
> > > 
> > > $ git log --format=oneline --grep='anon.*union' -- drivers/gpu/drm/i915
> > > 
> > 
> > I see issues with initialization of anonymous union but we don't initialize 
> > intel_dpll_hw_state.
> > Also it was fixed on GCC 4.6 that is older than current GCC requirement to 
> > build kernel(GCC 5.1).
> > 
> > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=10676
> 
> OK. However, after pondering this a bit I think naming things wpild
> probably be better here. You have a bunch of if ladders now where each
> branch only operates on one of the structs inside the union. IMO the
> anonymity is making it rather hard to see if the code is even correct.

Just to mare sure we are in the same page, you want to have this?


struct icl_tc {
u32 mg_refclkin_ctl;
u32 mg_clktop2_coreclkctl1;
u32 mg_clktop2_hsclkctl;
u32 mg_pll_div0;
u32 mg_pll_div1;
u32 mg_pll_lf;
u32 mg_pll_frac_lock;
u32 mg_pll_ssc;
u32 mg_pll_bias;
u32 mg_pll_tdc_coldst_bias;
u32 mg_pll_bias_mask;
u32 mg_pll_tdc_coldst_bias_mask;
};

So we would need to access members with icl_tc.mg_refclkin_ctl?

I can do that but the diff will be huge.
Are you okay with that too Imre?


> 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc: Do not try loading wrong DMC version

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Do not try loading wrong DMC version
URL   : https://patchwork.freedesktop.org/series/100664/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
1548d273add7 drm/i915/dmc: Do not try loading wrong DMC version
-:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#14: 
<6>[0.00] DMI: Intel Corporation CoffeeLake Client 
Platform/CoffeeLake S UDIMM RVP, BIOS CNLSFWR1.R00.X220.B00.2103302221 
03/30/2021

total: 0 errors, 1 warnings, 0 checks, 8 lines checked

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Move bigjoiner refactoring (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Move bigjoiner refactoring (rev2)
URL   : https://patchwork.freedesktop.org/series/100195/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11276_full -> Patchwork_22383_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 11)
--

  Missing(1): shard-dg1 

Known issues


  Here are the changes found in Patchwork_22383_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_capture@pi@vcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][1] ([i915#4547])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22383/shard-skl6/igt@gem_exec_capture@p...@vcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][2] -> [FAIL][3] ([i915#2842])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-glk5/igt@gem_exec_fair@basic-throt...@rcs0.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22383/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22383/shard-skl2/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-verify:
- shard-glk:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22383/shard-glk2/igt@gem_lmem_swapp...@parallel-random-verify.html
- shard-apl:  NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22383/shard-apl6/igt@gem_lmem_swapp...@parallel-random-verify.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-skl:  NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#3323])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22383/shard-skl7/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gem_userptr_blits@input-checking:
- shard-apl:  NOTRUN -> [DMESG-WARN][8] ([i915#4991])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22383/shard-apl7/igt@gem_userptr_bl...@input-checking.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy@uc:
- shard-skl:  NOTRUN -> [DMESG-WARN][9] ([i915#1982])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22383/shard-skl7/igt@gem_userptr_blits@map-fixed-invalidate-b...@uc.html

  * igt@gem_workarounds@suspend-resume-fd:
- shard-kbl:  [PASS][10] -> [DMESG-WARN][11] ([i915#180]) +5 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-kbl4/igt@gem_workarou...@suspend-resume-fd.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22383/shard-kbl4/igt@gem_workarou...@suspend-resume-fd.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-glk:  [PASS][12] -> [DMESG-WARN][13] ([i915#118])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-glk5/igt@kms_big...@x-tiled-32bpp-rotate-180.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22383/shard-glk6/igt@kms_big...@x-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl:  NOTRUN -> [FAIL][14] ([i915#3763])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22383/shard-skl10/igt@kms_big...@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-apl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3777]) +4 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22383/shard-apl7/igt@kms_big...@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-skl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3777]) +2 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22383/shard-skl8/igt@kms_big...@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-apl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#3886]) +4 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22383/shard-apl6/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][18] ([fdo#109278] / [i915#3886])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22383/shard-iclb6/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-kbl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3886]) +4 
similar issues
   [19]: 

Re: [Intel-gfx] [PATCH 2/2] hda/i915: split the wait for the component binding

[Lucas De Marchi]

On Thu, Feb 24, 2022 at 01:22:03AM +0530, Ramalingam C wrote:

Split the wait for component binding from i915 in multiples of
sysctl_hung_task_timeout_secs. This helps to avoid the possible kworker
thread hung detection given below.

<3>[   60.946316] INFO: task kworker/11:1:104 blocked for more than 30
seconds.
<3>[   60.946479]   Tainted: GW
5.17.0-rc5-CI-CI_DRM_11265+ #1
<3>[   60.946580] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs"
disables this message.
<6>[   60.946688] task:kworker/11:1state:D stack:14192 pid:  104
ppid: 2 flags:0x4000
<6>[   60.946713] Workqueue: events azx_probe_work [snd_hda_intel]
<6>[   60.946740] Call Trace:
<6>[   60.946745]  
<6>[   60.946763]  __schedule+0x42c/0xa80
<6>[   60.946797]  schedule+0x3f/0xc0
<6>[   60.946811]  schedule_timeout+0x1be/0x2e0
<6>[   60.946829]  ? del_timer_sync+0xb0/0xb0
<6>[   60.946849]  ? 0x8100
<6>[   60.946864]  ? wait_for_completion_timeout+0x79/0x120
<6>[   60.946879]  wait_for_completion_timeout+0xab/0x120
<6>[   60.946906]  snd_hdac_i915_init+0xa5/0xb0 [snd_hda_core]
<6>[   60.946943]  azx_probe_work+0x71/0x84c [snd_hda_intel]
<6>[   60.946974]  process_one_work+0x275/0x5c0
<6>[   60.947010]  worker_thread+0x37/0x370
<6>[   60.947028]  ? process_one_work+0x5c0/0x5c0
<6>[   60.947038]  kthread+0xef/0x120
<6>[   60.947047]  ? kthread_complete_and_exit+0x20/0x20
<6>[   60.947065]  ret_from_fork+0x22/0x30
<6>[   60.947110]  

Signed-off-by: Ramalingam C 
cc: Kai Vehmanen 
cc: Lucas De Marchi 


some more Cc needed?

$ ./scripts/get_maintainer.pl sound/hda/hdac_i915.c
Jaroslav Kysela  (maintainer:SOUND)
Takashi Iwai  (maintainer:SOUND)
Lucas De Marchi  (commit_signer:2/2=100%)
Rodrigo Vivi  (commit_signer:1/2=50%)
Ramalingam C  
(commit_signer:1/2=50%,authored:1/2=50%,removed_lines:1/1=100%)
Chris Wilson  (authored:1/2=50%,added_lines:23/24=96%)
alsa-de...@alsa-project.org (moderated list:SOUND)
linux-ker...@vger.kernel.org (open list)



---
sound/hda/hdac_i915.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/sound/hda/hdac_i915.c b/sound/hda/hdac_i915.c
index d20a450a9a15..daaeebc5099e 100644
--- a/sound/hda/hdac_i915.c
+++ b/sound/hda/hdac_i915.c
@@ -6,6 +6,7 @@
#include 
#include 
#include 
+#include 
#include 
#include 
#include 
@@ -163,7 +164,8 @@ static bool dg1_gfx_present(void)
int snd_hdac_i915_init(struct hdac_bus *bus)
{
struct drm_audio_component *acomp;
-   int err;
+   unsigned long timeout, ret = 0;
+   int err, i, itr_cnt;

if (!i915_gfx_present())
return -ENODEV;
@@ -182,9 +184,18 @@ int snd_hdac_i915_init(struct hdac_bus *bus)
if (!acomp->ops) {
if (!IS_ENABLED(CONFIG_MODULES) ||
!request_module("i915")) {
+   if (!sysctl_hung_task_timeout_secs) {
+   itr_cnt = 1;
+   timeout = msecs_to_jiffies(60 * 1000);
+   } else {
+   itr_cnt = DIV_ROUND_UP(60, 
sysctl_hung_task_timeout_secs);
+   timeout = 
msecs_to_jiffies(sysctl_hung_task_timeout_secs * 1000);
+   }
+
/* 60s timeout */
-   
wait_for_completion_timeout(>master_bind_complete,
-   msecs_to_jiffies(30 * 
1000));
+   for (i = 0; i < itr_cnt || !ret; i++)


it will return 0 if a timeout occurs so it's trapped forever here? Did
you mean &&?

Also maybe:

itr_cnt = DIV_ROUND_UP(60, sysctl_hung_task_timeout_secs ?: 60);

Lucas De Marchi

} while ();


+   ret = 
wait_for_completion_timeout(>master_bind_complete,
+ timeout);
}
}
if (!acomp->ops) {
--
2.20.1

Re: [Intel-gfx] [PATCH v3 3/5] drm/i915: Make cursor plane registers unlocked

[Ville Syrjälä]

On Thu, Feb 24, 2022 at 04:37:03PM +0200, Lisovskiy, Stanislav wrote:
> On Fri, Feb 11, 2022 at 11:26:04AM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > Drop the locks around cursor plane register writes. The
> > lock isn't needed since each plane's register are neatly
> > contained on their own cachelines.
> > 
> > The locking did have a secondary effect of disabling
> > interrupts around the cursor registers writes though.
> > If we drop that then we open outselves up for sceduling
> > delays and whatnot while on the middle of the register
> > writes. That increases the chance of not all the register
> > writes land during the same frame. For normal atomic
> > commits this is not a concern as the vblank evade mechanism
> > anyway disables interrupts around the update, but the legacy
> > cursor codepath does not. Technically we should do a vblank
> > evade there as well, but so far no one has bothered to hook
> > that up. So in the meantime let's put an explicit local irq
> > disable/enable around the legacy cursor update to keep the
> > race window minimal.
> > 
> > v2: local_irq_{disable,enable}() for legacy cursor ioctl
> 
> Guess, this will help our infamous atomic update evasion time exceeeded.
> I think I've even checked with similar patch.
> Good that its finally will make its way into kernel.

Yeah. I also sent a new series that split color management
to noarm+arm and drops some more usless locks.

After those I think the TODO list is down to:
- cursor noarm+arm split
- scaler/pfit noarm+arm split
- random locked register accesses during fastsea,
  and maybe a few are still left in pure plane commits as well

> Reviewed-by: Stanislav Lisovskiy 

Thanks.

-- 
Ville Syrjälä
Intel

[Intel-gfx] [PATCH 0/4] drm/i915: Optimize CSC updates for ilk+

[Ville Syrjala]

From: Ville Syrjälä 

As we did with plane updates we can split the color management
updates to noarm+arm pair. The CSC matrix coefficients can all
be written in the noarm hook, with just the PIPE_CSC_mode (the
arming register) left behind in the arm hook.

Also make the scaler/pfit completely lockless as that too
adds overhead into the vblank evasion critical section.

Ville Syrjälä (4):
  drm/i915: Remove locks around skl+ scaler programming
  drm/i915: Make ilk+ pfit regiser unlocked
  drm/i915: Split color_commit() into noarm+arm pair
  drm/i915: Split pipe+output CSC programming to noarm+arm pair

 drivers/gpu/drm/i915/display/intel_color.c   | 95 +---
 drivers/gpu/drm/i915/display/intel_color.h   |  3 +-
 drivers/gpu/drm/i915/display/intel_display.c | 40 +
 drivers/gpu/drm/i915/display/skl_scaler.c| 10 ---
 4 files changed, 88 insertions(+), 60 deletions(-)

-- 
2.34.1

[Intel-gfx] [PATCH 4/4] drm/i915: Split pipe+output CSC programming to noarm+arm pair

[Ville Syrjala]

From: Ville Syrjälä 

Move most of the pipe+output CSC programming to the
.color_commit_noarm() hook which runs before vblank evasion.
Only PIPE_CSC_MODE (the arming register) needs to remain in
inside the critical section.

A test case that just updates the CTM in a loop produces
the following i915_update_info numbers on ilk (w/o lockdep):
old new
Updates: 10012  Updates: 10008
   |   |
   1us |** 1us |**
   |*  |*
   4us |*  4us |*
   |*  |**
  16us |  16us |
   |   |
  66us |  66us |
   |   |
 262us | 262us |
   |   |
   1ms |   1ms |
   |   |
   4ms |   4ms |
   |   |
  17ms |  17ms |
   |   |
Min update: 1345ns  Min update: 1268ns
Max update: 16672ns Max update: 15656ns
Average update: 3914ns  Average update: 2185ns
Overruns > 100us: 0 Overruns > 100us: 0

And here is tgl (forced to update both pipe CSC and
output CSC, and with lockdep enabled):
old new
Updates: 10012  Updates: 10012
   |   |
   1us |   1us |
   |   |
   4us |*  4us |**
   |** |**
  16us |* 16us |*
   |*  |
  66us |  66us |
   |   |
 262us | 262us |
   |   |
   1ms |   1ms |
   |   |
   4ms |   4ms |
   |   |
  17ms |  17ms |
   |   |
Min update: 5204ns  Min update: 5176ns
Max update: 176038nsMax update: 186685ns
Average update: 23931ns Average update: 16654ns
Overruns > 250us: 0 Overruns > 250us: 0

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_color.c | 36 ++
 1 file changed, 23 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c 
b/drivers/gpu/drm/i915/display/intel_color.c
index df775c6179b2..34128c9c635c 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -346,15 +346,11 @@ static void ilk_load_csc_matrix(const struct 
intel_crtc_state *crtc_state)
ilk_csc_coeff_identity,
ilk_csc_off_zero);
}
-
-   intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
- crtc_state->csc_mode);
 }
 
 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
if (crtc_state->hw.ctm) {
u16 coeff[9];
@@ -373,9 +369,6 @@ static void icl_load_csc_matrix(const struct 
intel_crtc_state *crtc_state)
  ilk_csc_coeff_limited_range,
  ilk_csc_postoff_limited_range);
}
-
-   intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
- crtc_state->csc_mode);
 }
 
 static void chv_load_cgm_csc(struct intel_crtc *crtc,
@@ -500,6 +493,16 @@ static void icl_lut_multi_seg_pack(struct drm_color_lut 
*entry, u32 ldw, u32 udw

REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
 }
 
+static void icl_color_commit_noarm(const struct intel_crtc_state *crtc_state)
+{
+   icl_load_csc_matrix(crtc_state);
+}
+
+static void ilk_color_commit_noarm(const struct intel_crtc_state *crtc_state)
+{
+   ilk_load_csc_matrix(crtc_state);
+}
+
 static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -525,7 +528,8 @@ static void ilk_color_commit_arm(const struct 
intel_crtc_state *crtc_state)
val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
intel_de_write(dev_priv, PIPECONF(pipe), val);
 
-   ilk_load_csc_matrix(crtc_state);
+   intel_de_write_fw(dev_priv, 

[Intel-gfx] [PATCH 3/4] drm/i915: Split color_commit() into noarm+arm pair

[Ville Syrjala]

From: Ville Syrjälä 

To reduce the amount of registers written during the vblank evade
critical section let's also split the .color_commit() hook to
noarm+arm pair. The noarm hook runs before the vblank evasion
with the arm hook staying inside the critical section.

Just the framework here, actually moving stuff out into the noarm
hook will follow.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_color.c   | 59 +---
 drivers/gpu/drm/i915/display/intel_color.h   |  3 +-
 drivers/gpu/drm/i915/display/intel_display.c | 22 ++--
 3 files changed, 56 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c 
b/drivers/gpu/drm/i915/display/intel_color.c
index e94ec57260f1..df775c6179b2 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -31,12 +31,21 @@
 struct intel_color_funcs {
int (*color_check)(struct intel_crtc_state *crtc_state);
/*
-* Program double buffered color management registers during
-* vblank evasion. The registers should then latch during the
-* next vblank start, alongside any other double buffered registers
-* involved with the same commit.
+* Program non-arming double buffered color management registers
+* before vblank evasion. The registers should then latch after
+* the arming register is written (by color_commit_arm()) during
+* the next vblank start, alongside any other double buffered
+* registers involved with the same commit. This hook is optional.
 */
-   void (*color_commit)(const struct intel_crtc_state *crtc_state);
+   void (*color_commit_noarm)(const struct intel_crtc_state *crtc_state);
+   /*
+* Program arming double buffered color management registers
+* during vblank evasion. The registers (and whatever other registers
+* they arm that were written by color_commit_noarm) should then latch
+* during the next vblank start, alongside any other double buffered
+* registers involved with the same commit.
+*/
+   void (*color_commit_arm)(const struct intel_crtc_state *crtc_state);
/*
 * Load LUTs (and other single buffered color management
 * registers). Will (hopefully) be called during the vblank
@@ -491,7 +500,7 @@ static void icl_lut_multi_seg_pack(struct drm_color_lut 
*entry, u32 ldw, u32 udw

REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
 }
 
-static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
+static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -504,7 +513,7 @@ static void i9xx_color_commit(const struct intel_crtc_state 
*crtc_state)
intel_de_write(dev_priv, PIPECONF(pipe), val);
 }
 
-static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
+static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -519,7 +528,7 @@ static void ilk_color_commit(const struct intel_crtc_state 
*crtc_state)
ilk_load_csc_matrix(crtc_state);
 }
 
-static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
+static void hsw_color_commit_arm(const struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -530,7 +539,7 @@ static void hsw_color_commit(const struct intel_crtc_state 
*crtc_state)
ilk_load_csc_matrix(crtc_state);
 }
 
-static void skl_color_commit(const struct intel_crtc_state *crtc_state)
+static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1169,11 +1178,19 @@ void intel_color_load_luts(const struct 
intel_crtc_state *crtc_state)
dev_priv->color_funcs->load_luts(crtc_state);
 }
 
-void intel_color_commit(const struct intel_crtc_state *crtc_state)
+void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-   dev_priv->color_funcs->color_commit(crtc_state);
+   if (dev_priv->color_funcs->color_commit_noarm)
+   dev_priv->color_funcs->color_commit_noarm(crtc_state);
+}
+
+void intel_color_commit_arm(const struct intel_crtc_state *crtc_state)
+{
+   struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+
+   dev_priv->color_funcs->color_commit_arm(crtc_state);
 }
 
 static bool 

[Intel-gfx] [PATCH 2/4] drm/i915: Make ilk+ pfit regiser unlocked

[Ville Syrjala]

From: Ville Syrjälä 

The ilk+ panel fitter register are sitting nicely on their own
cacheline, so no need for global serialization via uncore.lock.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 7bf24df20b14..705f23be409c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1114,13 +1114,13 @@ static void ilk_pfit_enable(const struct 
intel_crtc_state *crtc_state)
 * e.g. x201.
 */
if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
-   intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
-  PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
+   intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
+ PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
else
-   intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
-  PF_FILTER_MED_3x3);
-   intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
-   intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
+   intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
+ PF_FILTER_MED_3x3);
+   intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
+   intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
 }
 
 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
@@ -2022,9 +2022,9 @@ void ilk_pfit_disable(const struct intel_crtc_state 
*old_crtc_state)
if (!old_crtc_state->pch_pfit.enabled)
return;
 
-   intel_de_write(dev_priv, PF_CTL(pipe), 0);
-   intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
-   intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
+   intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
+   intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
+   intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
 }
 
 static void ilk_crtc_disable(struct intel_atomic_state *state,
-- 
2.34.1

[Intel-gfx] [PATCH 1/4] drm/i915: Remove locks around skl+ scaler programming

[Ville Syrjala]

From: Ville Syrjälä 

All the skl+ scaler registers are suitably confined to their own
cachelines so we don't need the uncore.lock to globally serialize
access to these registers. We actually already dropped some of this
in commit 14ad15296d1f ("drm/i915: Make skl+ universal plane
registers unlocked") as the plane scaler enabling/reconfiguration
became lockless. So let's complete that and remove the rest of
the locks from the scaler programming as well.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/skl_scaler.c | 10 --
 1 file changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c 
b/drivers/gpu/drm/i915/display/skl_scaler.c
index c2e94118566b..ac67e9fbb713 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -412,7 +412,6 @@ void skl_pfit_enable(const struct intel_crtc_state 
*crtc_state)
int x = dst->x1;
int y = dst->y1;
int hscale, vscale;
-   unsigned long irqflags;
int id;
u32 ps_ctrl;
 
@@ -434,8 +433,6 @@ void skl_pfit_enable(const struct intel_crtc_state 
*crtc_state)
ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 
0);
ps_ctrl |=  PS_SCALER_EN | scaler_state->scalers[id].mode;
 
-   spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
skl_scaler_setup_filter(dev_priv, pipe, id, 0,
crtc_state->hw.scaling_filter);
 
@@ -449,8 +446,6 @@ void skl_pfit_enable(const struct intel_crtc_state 
*crtc_state)
  x << 16 | y);
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
  width << 16 | height);
-
-   spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
 }
 
 void
@@ -519,15 +514,10 @@ static void skl_detach_scaler(struct intel_crtc *crtc, 
int id)
 {
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
-   unsigned long irqflags;
-
-   spin_lock_irqsave(_priv->uncore.lock, irqflags);
 
intel_de_write_fw(dev_priv, SKL_PS_CTRL(crtc->pipe, id), 0);
intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(crtc->pipe, id), 0);
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, id), 0);
-
-   spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
 }
 
 /*
-- 
2.34.1

Re: [Intel-gfx] [PATCH 2/2] hda/i915: split the wait for the component binding

[Kai Vehmanen]

Hi,

On Thu, 24 Feb 2022, Ramalingam C wrote:

> Split the wait for component binding from i915 in multiples of
> sysctl_hung_task_timeout_secs. This helps to avoid the possible kworker
> thread hung detection given below.

while I understand the problem, I'm not sure whether a simpler option
should be chosen. Maybe just split the wait_for_completion_timeout()
into small 5sec iterations, without consulting value of hung_task_timeout.
This would seem unligned with more mainstream use of 
wait_for_completion_timeout() in kernel and still do the job.

I'll loop in Takashi here as well. Basicly the 60 sec timeout in 
hda/hdac_i915.c is getting caught by hung_task_detection logic in builds
where the hung_task_timeout is below 60secs.

I have a patch that tries to avoid hitting the timeout in some of the more 
common cases:
"ALSA: hda/i915 - skip acomp init if no matching display"
https://lists.freedesktop.org/archives/intel-gfx-trybot/2022-February/128278.html
... but we'll still be stuck with some configurations where the timeout 
will be hit. And above needs careful testing.

One logic comment below as well, but I'll quote the whole patch to give
context to Takashi.
 
> <3>[   60.946316] INFO: task kworker/11:1:104 blocked for more than 30
> seconds.
> <3>[   60.946479]   Tainted: GW
> 5.17.0-rc5-CI-CI_DRM_11265+ #1
> <3>[   60.946580] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs"
> disables this message.
> <6>[   60.946688] task:kworker/11:1state:D stack:14192 pid:  104
> ppid: 2 flags:0x4000
> <6>[   60.946713] Workqueue: events azx_probe_work [snd_hda_intel]
> <6>[   60.946740] Call Trace:
> <6>[   60.946745]  
> <6>[   60.946763]  __schedule+0x42c/0xa80
> <6>[   60.946797]  schedule+0x3f/0xc0
> <6>[   60.946811]  schedule_timeout+0x1be/0x2e0
> <6>[   60.946829]  ? del_timer_sync+0xb0/0xb0
> <6>[   60.946849]  ? 0x8100
> <6>[   60.946864]  ? wait_for_completion_timeout+0x79/0x120
> <6>[   60.946879]  wait_for_completion_timeout+0xab/0x120
> <6>[   60.946906]  snd_hdac_i915_init+0xa5/0xb0 [snd_hda_core]
> <6>[   60.946943]  azx_probe_work+0x71/0x84c [snd_hda_intel]
> <6>[   60.946974]  process_one_work+0x275/0x5c0
> <6>[   60.947010]  worker_thread+0x37/0x370
> <6>[   60.947028]  ? process_one_work+0x5c0/0x5c0
> <6>[   60.947038]  kthread+0xef/0x120
> <6>[   60.947047]  ? kthread_complete_and_exit+0x20/0x20
> <6>[   60.947065]  ret_from_fork+0x22/0x30
> <6>[   60.947110]  
> 
> Signed-off-by: Ramalingam C 
> cc: Kai Vehmanen 
> cc: Lucas De Marchi 
> ---
>  sound/hda/hdac_i915.c | 17 ++---
>  1 file changed, 14 insertions(+), 3 deletions(-)
> 
> diff --git a/sound/hda/hdac_i915.c b/sound/hda/hdac_i915.c
> index d20a450a9a15..daaeebc5099e 100644
> --- a/sound/hda/hdac_i915.c
> +++ b/sound/hda/hdac_i915.c
> @@ -6,6 +6,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -163,7 +164,8 @@ static bool dg1_gfx_present(void)
>  int snd_hdac_i915_init(struct hdac_bus *bus)
>  {
>   struct drm_audio_component *acomp;
> - int err;
> + unsigned long timeout, ret = 0;
> + int err, i, itr_cnt;
>  
>   if (!i915_gfx_present())
>   return -ENODEV;
> @@ -182,9 +184,18 @@ int snd_hdac_i915_init(struct hdac_bus *bus)
>   if (!acomp->ops) {
>   if (!IS_ENABLED(CONFIG_MODULES) ||
>   !request_module("i915")) {
5~> +   if (!sysctl_hung_task_timeout_secs) {
> + itr_cnt = 1;
> + timeout = msecs_to_jiffies(60 * 1000);
> + } else {
> + itr_cnt = DIV_ROUND_UP(60, 
> sysctl_hung_task_timeout_secs);
> + timeout = 
> msecs_to_jiffies(sysctl_hung_task_timeout_secs * 1000);
> + }
> +
>   /* 60s timeout */
> - 
> wait_for_completion_timeout(>master_bind_complete,
> - msecs_to_jiffies(30 * 
> 1000));
> + for (i = 0; i < itr_cnt || !ret; i++)
> + ret = 
> wait_for_completion_timeout(>master_bind_complete,
> +   timeout);

I think that should be 'i < itr_cnt && !ret'. If wait_for_completion
returns with a positive value, we should stop waiting as the completion
has been signalled.

>   }
>   }
>   if (!acomp->ops) {
> -- 

Br, Kai

[Intel-gfx] ✗ Fi.CI.IGT: failure for Use drm_clflush* instead of clflush (rev11)

[Patchwork]

== Series Details ==

Series: Use drm_clflush* instead of clflush (rev11)
URL   : https://patchwork.freedesktop.org/series/99450/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11276_full -> Patchwork_22381_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22381_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22381_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 11)
--

  Missing(1): shard-tglu 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22381_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@mock@requests:
- shard-skl:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-skl2/igt@i915_selftest@m...@requests.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22381/shard-skl2/igt@i915_selftest@m...@requests.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_display_modes@extended-mode-basic}:
- {shard-dg1}:NOTRUN -> [SKIP][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22381/shard-dg1-18/igt@kms_display_mo...@extended-mode-basic.html

  * 
{igt@kms_plane_scaling@downscale-with-rotation-factor-2@pipe-d-downscale-with-rotation}:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][4]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22381/shard-dg1-15/igt@kms_plane_scaling@downscale-with-rotation-facto...@pipe-d-downscale-with-rotation.html

  
Known issues


  Here are the changes found in Patchwork_22381_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl:  [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +9 similar 
issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-kbl7/igt@gem_ctx_isolation@preservation...@vcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22381/shard-kbl7/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#232])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-tglb7/igt@gem_...@unwedge-stress.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22381/shard-tglb2/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_capture@pi@vcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][9] ([i915#4547])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22381/shard-skl5/igt@gem_exec_capture@p...@vcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22381/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html
- shard-kbl:  [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs1.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22381/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-glk5/igt@gem_exec_fair@basic-throt...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22381/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_schedule@smoketest-all:
- shard-glk:  [PASS][15] -> [DMESG-WARN][16] ([i915#118]) +2 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-glk9/igt@gem_exec_sched...@smoketest-all.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22381/shard-glk1/igt@gem_exec_sched...@smoketest-all.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22381/shard-skl8/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-verify:
- shard-glk:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22381/shard-glk4/igt@gem_lmem_swapp...@parallel-random-verify.html
- shard-apl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22381/shard-apl6/igt@gem_lmem_swapp...@parallel-random-verify.html

  * igt@gem_pxp@create-regular-context-1:
- 

Re: [Intel-gfx] [PATCH 1/2] kernel/hung_task: Exporting sysctl_hung_task_timeout_secs

[Lucas De Marchi]

On Thu, Feb 24, 2022 at 01:22:02AM +0530, Ramalingam C wrote:

Exporting sysctl_hung_task_timeout_secs, to make it available for other
kernel modules.


I guess this should only be done if second patch is accepted by sound
subsystem maintainers. If it is, then I'd do some changes in the commit
message.

Please use imperative style in commit messages. Here we also need to
give more details on why we are exporting this and Cc the maintainers.
Proposed new message:

Subject: kernel/hung_task: Export sysctl_hung_task_timeout_secs

Kernel modules may want to read sysctl_hung_task_timeout_secs so they
can do long waits by multiples of that value, avoiding the hung task
detector to trigger. This is already done in other places in the kernel
that are builtin-only, like:

block/bio.c:submit_bio_wait()
block/blk-mq.c:blk_execute_rq()
mm/kfence/core.c:toggle_allocation_gate()

Export it so it can also be used by modules.

Cc: Andrew Morton 
Cc: Luis Chamberlain 
Cc: Kai Vehmanen 
Cc: Jaroslav Kysela  
Cc: Takashi Iwai 




Signed-off-by: Ramalingam C 
cc: Lucas De Marchi 


Acked-by: Lucas De Marchi 

Lucas De Marchi


---
kernel/hung_task.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/kernel/hung_task.c b/kernel/hung_task.c
index db59b6d4f0e7..01120265395d 100644
--- a/kernel/hung_task.c
+++ b/kernel/hung_task.c
@@ -43,6 +43,7 @@ int __read_mostly sysctl_hung_task_check_count = 
PID_MAX_LIMIT;
 * Zero means infinite timeout - no checking done:
 */
unsigned long __read_mostly sysctl_hung_task_timeout_secs = 
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT;
+EXPORT_SYMBOL(sysctl_hung_task_timeout_secs);

/*
 * Zero (default value) means use sysctl_hung_task_timeout_secs:
--
2.20.1

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Use unions per platform in intel_dpll_hw_state (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Use unions per platform in intel_dpll_hw_state (rev3)
URL   : https://patchwork.freedesktop.org/series/100577/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11278 -> Patchwork_22392


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22392 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22392, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/index.html

Participating hosts (42 -> 41)
--

  Additional (1): fi-kbl-8809g 
  Missing(2): fi-bdw-samus fi-pnv-d510 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22392:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-skl-6600u:   NOTRUN -> [FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html

  
Known issues


  Here are the changes found in Patchwork_22392 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s0@smem:
- fi-kbl-8809g:   NOTRUN -> [DMESG-WARN][2] ([i915#4962]) +1 similar 
issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/fi-kbl-8809g/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-skl-6600u:   NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-kbl-8809g:   NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
- fi-kbl-8809g:   NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/fi-kbl-8809g/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u:   NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live:
- fi-skl-6600u:   NOTRUN -> [FAIL][7] ([i915#4547])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/fi-skl-6600u/igt@i915_selft...@live.html

  * igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-8809g:   NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u:   NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u:   NOTRUN -> [SKIP][10] ([fdo#109271]) +3 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u:   NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-8809g:   NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g:   NOTRUN -> [SKIP][13] ([fdo#109271]) +54 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {fi-rkl-11600}: [INCOMPLETE][14] ([i915#5127]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11278/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_flink_basic@bad-flink:
- fi-skl-6600u:   [FAIL][16] ([i915#4547]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11278/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22392/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html

  * 

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] HAX: drm/i915: Clarify vma lifetime (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] HAX: drm/i915: Clarify vma lifetime (rev3)
URL   : https://patchwork.freedesktop.org/series/100593/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11276_full -> Patchwork_22380_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22380_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22380_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 12)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22380_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_suspend@basic-s3@smem:
- shard-snb:  [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-snb4/igt@gem_exec_suspend@basic...@smem.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22380/shard-snb2/igt@gem_exec_suspend@basic...@smem.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_display_modes@extended-mode-basic}:
- {shard-dg1}:NOTRUN -> [SKIP][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22380/shard-dg1-18/igt@kms_display_mo...@extended-mode-basic.html

  * 
{igt@kms_plane_scaling@downscale-with-rotation-factor-2@pipe-d-downscale-with-rotation}:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][4]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22380/shard-dg1-19/igt@kms_plane_scaling@downscale-with-rotation-facto...@pipe-d-downscale-with-rotation.html

  
Known issues


  Here are the changes found in Patchwork_22380_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl:  [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +7 similar 
issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-kbl7/igt@gem_ctx_isolation@preservation...@vcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22380/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#232])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-tglb7/igt@gem_...@unwedge-stress.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22380/shard-tglb5/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-iclb: NOTRUN -> [INCOMPLETE][9] ([i915#3371])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22380/shard-iclb6/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-kbl1/igt@gem_exec_fair@basic-n...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22380/shard-kbl3/igt@gem_exec_fair@basic-n...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl:  [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-apl1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22380/shard-apl8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: NOTRUN -> [FAIL][14] ([i915#2842]) +2 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22380/shard-iclb7/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-glk5/igt@gem_exec_fair@basic-throt...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22380/shard-glk1/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22380/shard-skl10/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-verify:
- shard-glk:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22380/shard-glk7/igt@gem_lmem_swapp...@parallel-random-verify.html
- shard-apl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613])
   [19]: 

Re: [Intel-gfx] [PATCH v2] drm/i915/display: Use unions per platform in intel_dpll_hw_state

[Ville Syrjälä]

On Thu, Feb 24, 2022 at 01:49:36PM +, Souza, Jose wrote:
> On Thu, 2022-02-24 at 15:25 +0200, Ville Syrjälä wrote:
> > On Thu, Feb 24, 2022 at 01:17:35PM +, Souza, Jose wrote:
> > > On Thu, 2022-02-24 at 12:20 +0200, Ville Syrjälä wrote:
> > > > On Wed, Feb 23, 2022 at 12:55:51PM -0800, José Roberto de Souza wrote:
> > > > 
> > > > > + union {
> > > > > + /* icl+ TC */
> > > > > + struct {
> > > > > + u32 mg_refclkin_ctl;
> > > > > + u32 mg_clktop2_coreclkctl1;
> > > > > + u32 mg_clktop2_hsclkctl;
> > > > > + u32 mg_pll_div0;
> > > > > + u32 mg_pll_div1;
> > > > > + u32 mg_pll_lf;
> > > > > + u32 mg_pll_frac_lock;
> > > > > + u32 mg_pll_ssc;
> > > > > + u32 mg_pll_bias;
> > > > > + u32 mg_pll_tdc_coldst_bias;
> > > > > + u32 mg_pll_bias_mask;
> > > > > + u32 mg_pll_tdc_coldst_bias_mask;
> > > > > + };
> > > > > +
> > > > > + /* bxt */
> > > > > + struct {
> > > > > + /* bxt */
> > > > > + u32 ebb0;
> > > > > + u32 ebb4;
> > > > > + u32 pll0;
> > > > > + u32 pll1;
> > > > > + u32 pll2;
> > > > > + u32 pll3;
> > > > > + u32 pll6;
> > > > > + u32 pll8;
> > > > > + u32 pll9;
> > > > > + u32 pll10;
> > > > > + u32 pcsdw12;
> > > > > + };
> > > > 
> > > > Wasn't there some funny compiler bug around anonymous unions?
> > > > git log --grep='anon.*union' seems to agree. Please double check
> > > > that stuff to make sure this is actually safe.
> > > 
> > > I don't see any patch referring to compiler issues with 'git log 
> > > --grep='anon.*union', what I see is other subsystems making use of it too.
> > > Can you share the commit hash that you are referring to?
> > 
> > $ git log --format=oneline --grep='anon.*union' -- drivers/gpu/drm/i915
> > 
> 
> I see issues with initialization of anonymous union but we don't initialize 
> intel_dpll_hw_state.
> Also it was fixed on GCC 4.6 that is older than current GCC requirement to 
> build kernel(GCC 5.1).
> 
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=10676

OK. However, after pondering this a bit I think naming things wpild
probably be better here. You have a bunch of if ladders now where each
branch only operates on one of the structs inside the union. IMO the
anonymity is making it rather hard to see if the code is even correct.

-- 
Ville Syrjälä
Intel

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: Use unions per platform in intel_dpll_hw_state (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Use unions per platform in intel_dpll_hw_state (rev3)
URL   : https://patchwork.freedesktop.org/series/100577/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: fix one mem leak in mmap_offset_attach() (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev3)
URL   : https://patchwork.freedesktop.org/series/100532/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11276_full -> Patchwork_22378_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_22378_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22378_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 12)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22378_full:

### IGT changes ###

 Warnings 

  * igt@i915_pm_dc@dc9-dpms:
- shard-skl:  [SKIP][1] ([fdo#109271]) -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-skl1/igt@i915_pm...@dc9-dpms.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22378/shard-skl8/igt@i915_pm...@dc9-dpms.html

  
Known issues


  Here are the changes found in Patchwork_22378_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#232])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-tglb7/igt@gem_...@unwedge-stress.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22378/shard-tglb5/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_balancer@parallel:
- shard-kbl:  NOTRUN -> [DMESG-WARN][5] ([i915#5076])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22378/shard-kbl3/igt@gem_exec_balan...@parallel.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-kbl:  [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-kbl7/igt@gem_exec_fair@basic-none-r...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22378/shard-kbl6/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842]) +4 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22378/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-apl1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22378/shard-apl3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar 
issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-glk5/igt@gem_exec_fair@basic-throt...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22378/shard-glk9/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_lmem_swapping@parallel-random-verify:
- shard-glk:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22378/shard-glk3/igt@gem_lmem_swapp...@parallel-random-verify.html
- shard-skl:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22378/shard-skl7/igt@gem_lmem_swapp...@parallel-random-verify.html
- shard-apl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22378/shard-apl4/igt@gem_lmem_swapp...@parallel-random-verify.html

  * igt@gem_lmem_swapping@verify-random:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22378/shard-kbl1/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_pxp@create-regular-context-1:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#4270])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22378/shard-iclb7/igt@gem_...@create-regular-context-1.html

  * igt@gem_userptr_blits@input-checking:
- shard-apl:  NOTRUN -> [DMESG-WARN][18] ([i915#4991])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22378/shard-apl7/igt@gem_userptr_bl...@input-checking.html
- shard-kbl:  NOTRUN -> [DMESG-WARN][19] ([i915#4991])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22378/shard-kbl6/igt@gem_userptr_bl...@input-checking.html

  * igt@gen9_exec_parse@allowed-single:
- shard-skl:  NOTRUN -> [DMESG-WARN][20] ([i915#1436] / [i915#716])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22378/shard-skl10/igt@gen9_exec_pa...@allowed-single.html

 

[Intel-gfx] ✓ Fi.CI.BAT: success for hda/i915: split wait for component binding

[Patchwork]

== Series Details ==

Series: hda/i915: split wait for component binding
URL   : https://patchwork.freedesktop.org/series/100661/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11277 -> Patchwork_22391


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/index.html

Participating hosts (46 -> 40)
--

  Missing(6): fi-cml-u2 shard-tglu fi-bsw-cyan fi-icl-u2 fi-pnv-d510 
fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22391:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_module_load@reload:
- {bat-dg2-8}:[DMESG-FAIL][1] ([i915#5172]) -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/bat-dg2-8/igt@i915_module_l...@reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/bat-dg2-8/igt@i915_module_l...@reload.html

  
Known issues


  Here are the changes found in Patchwork_22391 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_prime@amd-to-i915:
- fi-ivb-3770:NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/fi-ivb-3770/igt@amdgpu/amd_pr...@amd-to-i915.html

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u:   [PASS][4] -> [INCOMPLETE][5] ([i915#4547])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][6] -> [INCOMPLETE][7] ([i915#3921])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-ivb-3770:[INCOMPLETE][8] ([i915#3303]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html
- bat-dg1-5:  [DMESG-FAIL][10] ([i915#4494] / [i915#4957]) -> 
[PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_busy@basic@modeset:
- {bat-adlp-6}:   [DMESG-WARN][12] ([i915#3576]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11277/bat-adlp-6/igt@kms_busy@ba...@modeset.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/bat-adlp-6/igt@kms_busy@ba...@modeset.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#5172]: https://gitlab.freedesktop.org/drm/intel/issues/5172


Build changes
-

  * Linux: CI_DRM_11277 -> Patchwork_22391

  CI-20190529: 20190529
  CI_DRM_11277: a9d1ffee8dbe2c5506cccf9077eab8fe439eea46 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6355: 83ec34916bd8268bc331105cf77c4d3d3cd352be @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22391: 25f3faec26be3820943854a42f7cbba3cb334c9d @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

25f3faec26be hda/i915: split the wait for the component binding
9fff1bdb8db0 kernel/hung_task: Exporting sysctl_hung_task_timeout_secs

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22391/index.html

Re: [Intel-gfx] [PATCH v2 2/5] drm/i915: Make skl+ universal plane registers unlocked

[Lisovskiy, Stanislav]

On Thu, Feb 10, 2022 at 08:24:00AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Drop the locks around most universal plane register writes.
> The lock isn't needed since each plane's register are neatly
> contained on their own cachelines.
> 
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Stanislav Lisovskiy 

> ---
>  .../drm/i915/display/skl_universal_plane.c| 35 ---
>  1 file changed, 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 5b1b089e045d..db9e31c12169 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -615,16 +615,11 @@ skl_plane_disable_arm(struct intel_plane *plane,
>   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>   enum plane_id plane_id = plane->id;
>   enum pipe pipe = plane->pipe;
> - unsigned long irqflags;
> -
> - spin_lock_irqsave(_priv->uncore.lock, irqflags);
>  
>   skl_write_plane_wm(plane, crtc_state);
>  
>   intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
>   intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
> -
> - spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
>  }
>  
>  static void
> @@ -634,9 +629,6 @@ icl_plane_disable_arm(struct intel_plane *plane,
>   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>   enum plane_id plane_id = plane->id;
>   enum pipe pipe = plane->pipe;
> - unsigned long irqflags;
> -
> - spin_lock_irqsave(_priv->uncore.lock, irqflags);
>  
>   if (icl_is_hdr_plane(dev_priv, plane_id))
>   intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0);
> @@ -646,8 +638,6 @@ icl_plane_disable_arm(struct intel_plane *plane,
>   intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
>   intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
>   intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
> -
> - spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
>  }
>  
>  static bool
> @@ -1106,7 +1096,6 @@ skl_plane_update_noarm(struct intel_plane *plane,
>   int crtc_y = plane_state->uapi.dst.y1;
>   u32 src_w = drm_rect_width(_state->uapi.src) >> 16;
>   u32 src_h = drm_rect_height(_state->uapi.src) >> 16;
> - unsigned long irqflags;
>  
>   /* The scaler will handle the output position */
>   if (plane_state->scaler_id >= 0) {
> @@ -1114,8 +1103,6 @@ skl_plane_update_noarm(struct intel_plane *plane,
>   crtc_y = 0;
>   }
>  
> - spin_lock_irqsave(_priv->uncore.lock, irqflags);
> -
>   intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
> PLANE_STRIDE_(stride));
>   intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
> @@ -1124,8 +,6 @@ skl_plane_update_noarm(struct intel_plane *plane,
> PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
>  
>   skl_write_plane_wm(plane, crtc_state);
> -
> - spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
>  }
>  
>  static void
> @@ -1139,7 +1124,6 @@ skl_plane_update_arm(struct intel_plane *plane,
>   u32 x = plane_state->view.color_plane[0].x;
>   u32 y = plane_state->view.color_plane[0].y;
>   u32 plane_ctl, plane_color_ctl = 0;
> - unsigned long irqflags;
>  
>   plane_ctl = plane_state->ctl |
>   skl_plane_ctl_crtc(crtc_state);
> @@ -1148,8 +1132,6 @@ skl_plane_update_arm(struct intel_plane *plane,
>   plane_color_ctl = plane_state->color_ctl |
>   glk_plane_color_ctl_crtc(crtc_state);
>  
> - spin_lock_irqsave(_priv->uncore.lock, irqflags);
> -
>   intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), 
> skl_plane_keyval(plane_state));
>   intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), 
> skl_plane_keymsk(plane_state));
>   intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), 
> skl_plane_keymax(plane_state));
> @@ -1185,8 +1167,6 @@ skl_plane_update_arm(struct intel_plane *plane,
>   intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
>   intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> skl_plane_surf(plane_state, 0));
> -
> - spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
>  }
>  
>  static void
> @@ -1207,7 +1187,6 @@ icl_plane_update_noarm(struct intel_plane *plane,
>   int src_w = drm_rect_width(_state->uapi.src) >> 16;
>   int src_h = drm_rect_height(_state->uapi.src) >> 16;
>   u32 plane_color_ctl;
> - unsigned long irqflags;
>  
>   plane_color_ctl = plane_state->color_ctl |
>   glk_plane_color_ctl_crtc(crtc_state);
> @@ -1218,8 +1197,6 @@ icl_plane_update_noarm(struct intel_plane *plane,
>   crtc_y = 0;
>   }
>  
> - spin_lock_irqsave(_priv->uncore.lock, irqflags);
> -
>   intel_de_write_fw(dev_priv, 

Re: [Intel-gfx] [PATCH v3 3/5] drm/i915: Make cursor plane registers unlocked

[Lisovskiy, Stanislav]

On Fri, Feb 11, 2022 at 11:26:04AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Drop the locks around cursor plane register writes. The
> lock isn't needed since each plane's register are neatly
> contained on their own cachelines.
> 
> The locking did have a secondary effect of disabling
> interrupts around the cursor registers writes though.
> If we drop that then we open outselves up for sceduling
> delays and whatnot while on the middle of the register
> writes. That increases the chance of not all the register
> writes land during the same frame. For normal atomic
> commits this is not a concern as the vblank evade mechanism
> anyway disables interrupts around the update, but the legacy
> cursor codepath does not. Technically we should do a vblank
> evade there as well, but so far no one has bothered to hook
> that up. So in the meantime let's put an explicit local irq
> disable/enable around the legacy cursor update to keep the
> race window minimal.
> 
> v2: local_irq_{disable,enable}() for legacy cursor ioctl

Guess, this will help our infamous atomic update evasion time exceeeded.
I think I've even checked with similar patch.
Good that its finally will make its way into kernel.

Reviewed-by: Stanislav Lisovskiy 

> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_cursor.c | 20 ++--
>  1 file changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c 
> b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 2ade8fdd9bdd..b648be744cf2 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -255,7 +255,6 @@ static void i845_cursor_update_arm(struct intel_plane 
> *plane,
>  {
>   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>   u32 cntl = 0, base = 0, pos = 0, size = 0;
> - unsigned long irqflags;
>  
>   if (plane_state && plane_state->uapi.visible) {
>   unsigned int width = drm_rect_width(_state->uapi.dst);
> @@ -270,8 +269,6 @@ static void i845_cursor_update_arm(struct intel_plane 
> *plane,
>   pos = intel_cursor_position(plane_state);
>   }
>  
> - spin_lock_irqsave(_priv->uncore.lock, irqflags);
> -
>   /* On these chipsets we can only modify the base/size/stride
>* whilst the cursor is disabled.
>*/
> @@ -290,8 +287,6 @@ static void i845_cursor_update_arm(struct intel_plane 
> *plane,
>   } else {
>   intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
>   }
> -
> - spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
>  }
>  
>  static void i845_cursor_disable_arm(struct intel_plane *plane,
> @@ -492,7 +487,6 @@ static void i9xx_cursor_update_arm(struct intel_plane 
> *plane,
>   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>   enum pipe pipe = plane->pipe;
>   u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
> - unsigned long irqflags;
>  
>   if (plane_state && plane_state->uapi.visible) {
>   int width = drm_rect_width(_state->uapi.dst);
> @@ -508,8 +502,6 @@ static void i9xx_cursor_update_arm(struct intel_plane 
> *plane,
>   pos = intel_cursor_position(plane_state);
>   }
>  
> - spin_lock_irqsave(_priv->uncore.lock, irqflags);
> -
>   /*
>* On some platforms writing CURCNTR first will also
>* cause CURPOS to be armed by the CURBASE write.
> @@ -555,8 +547,6 @@ static void i9xx_cursor_update_arm(struct intel_plane 
> *plane,
>   intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
>   intel_de_write_fw(dev_priv, CURBASE(pipe), base);
>   }
> -
> - spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
>  }
>  
>  static void i9xx_cursor_disable_arm(struct intel_plane *plane,
> @@ -715,6 +705,14 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
>*/
>   crtc_state->active_planes = new_crtc_state->active_planes;
>  
> + /*
> +  * Technically we should do a vblank evasion here to make
> +  * sure all the cursor registers update on the same frame.
> +  * For now just make sure the register writes happen as
> +  * quickly as possible to minimize the race window.
> +  */
> + local_irq_disable();
> +
>   if (new_plane_state->uapi.visible) {
>   intel_plane_update_noarm(plane, crtc_state, new_plane_state);
>   intel_plane_update_arm(plane, crtc_state, new_plane_state);
> @@ -722,6 +720,8 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
>   intel_plane_disable_arm(plane, crtc_state);
>   }
>  
> + local_irq_enable();
> +
>   intel_plane_unpin_fb(old_plane_state);
>  
>  out_free:
> -- 
> 2.34.1
> 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg1: Remove require_force_probe protection (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dg1: Remove require_force_probe protection (rev2)
URL   : https://patchwork.freedesktop.org/series/100601/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11276_full -> Patchwork_22377_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22377_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * 
{igt@kms_plane_scaling@downscale-with-rotation-factor-2@pipe-d-downscale-with-rotation}:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22377/shard-dg1-12/igt@kms_plane_scaling@downscale-with-rotation-facto...@pipe-d-downscale-with-rotation.html

  
Known issues


  Here are the changes found in Patchwork_22377_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-kbl:  NOTRUN -> [DMESG-WARN][2] ([i915#4991]) +1 similar 
issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22377/shard-kbl4/igt@gem_cre...@create-massive.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#232])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-tglb7/igt@gem_...@unwedge-stress.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22377/shard-tglb5/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_balancer@parallel:
- shard-kbl:  NOTRUN -> [DMESG-WARN][5] ([i915#5076])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22377/shard-kbl7/igt@gem_exec_balan...@parallel.html

  * igt@gem_exec_capture@pi@vecs0:
- shard-iclb: NOTRUN -> [INCOMPLETE][6] ([i915#3371])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22377/shard-iclb5/igt@gem_exec_capture@p...@vecs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][7] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22377/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html
- shard-kbl:  [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs1.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22377/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-apl1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22377/shard-apl4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar 
issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-glk5/igt@gem_exec_fair@basic-throt...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22377/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22377/shard-skl3/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-verify:
- shard-glk:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22377/shard-glk5/igt@gem_lmem_swapp...@parallel-random-verify.html
- shard-apl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22377/shard-apl3/igt@gem_lmem_swapp...@parallel-random-verify.html

  * igt@gem_lmem_swapping@verify-random:
- shard-kbl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22377/shard-kbl6/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_userptr_blits@input-checking:
- shard-apl:  NOTRUN -> [DMESG-WARN][18] ([i915#4991])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22377/shard-apl3/igt@gem_userptr_bl...@input-checking.html

  * igt@gem_workarounds@suspend-resume-fd:
- shard-kbl:  [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +3 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11276/shard-kbl4/igt@gem_workarou...@suspend-resume-fd.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22377/shard-kbl6/igt@gem_workarou...@suspend-resume-fd.html

  * 

Re: [Intel-gfx] [PATCH] drm/i915/display: Allow users to disable PSR2

[Ville Syrjälä]

On Thu, Feb 24, 2022 at 02:15:44PM +, Souza, Jose wrote:
> + Rodrigo
> 
> On Thu, 2022-02-24 at 15:11 +0200, Ville Syrjälä wrote:
> > On Thu, Feb 24, 2022 at 03:06:30PM +0200, Ville Syrjälä wrote:
> > > On Thu, Feb 24, 2022 at 01:01:24PM +, Souza, Jose wrote:
> > > > On Thu, 2022-02-24 at 12:12 +0200, Ville Syrjälä wrote:
> > > > > On Wed, Feb 23, 2022 at 11:41:03AM -0800, José Roberto de Souza wrote:
> > > > > > Some users are suffering with PSR2 issues that are under debug or
> > > > > > issues that were root caused to panel firmware, to make life of 
> > > > > > those
> > > > > > users easier here adding a option to disable PSR1 with kernel
> > > > > > parameter.
> > > > > > 
> > > > > > Using the same enable_psr that is current used to turn PSR1 and PSR2
> > > > > > off or on and adding a new value to only disable PSR2.
> > > > > > The previous valid values did not had their behavior changed.
> > > > > > 
> > > > > > Link: https://gitlab.freedesktop.org/drm/intel/-/issues/4951
> > > > > > Cc: Jouni Högander 
> > > > > > Signed-off-by: José Roberto de Souza 
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/display/intel_psr.c | 4 
> > > > > >  drivers/gpu/drm/i915/i915_params.c   | 2 +-
> > > > > >  2 files changed, 5 insertions(+), 1 deletion(-)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> > > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > index 2e0b092f4b6be..fc6b684bb7bec 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > @@ -100,11 +100,15 @@ static bool psr_global_enabled(struct 
> > > > > > intel_dp *intel_dp)
> > > > > >  
> > > > > >  static bool psr2_global_enabled(struct intel_dp *intel_dp)
> > > > > >  {
> > > > > > +   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > > > > +
> > > > > > switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> > > > > > case I915_PSR_DEBUG_DISABLE:
> > > > > > case I915_PSR_DEBUG_FORCE_PSR1:
> > > > > > return false;
> > > > > > default:
> > > > > > +   if (i915->params.enable_psr == 2)
> > > > > > +   return false;
> > > > > > return true;
> > > > > > }
> > > > > >  }
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_params.c 
> > > > > > b/drivers/gpu/drm/i915/i915_params.c
> > > > > > index eea355c2fc28a..a9b97e6eb3df0 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_params.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_params.c
> > > > > > @@ -94,7 +94,7 @@ i915_param_named_unsafe(enable_hangcheck, bool, 
> > > > > > 0400,
> > > > > >  
> > > > > >  i915_param_named_unsafe(enable_psr, int, 0400,
> > > > > > "Enable PSR "
> > > > > > -   "(0=disabled, 1=enabled) "
> > > > > > +   "(0=disabled, 1=enable up to PSR2 if supported, 2=enable up to 
> > > > > > PSR1) "
> > > > > 
> > > > > That seems very unintuitive. I would just make it 1==PSR1 and 2==PSR2.
> > > > 
> > > > This will break current behavior.
> > > 
> > > It's a modparam. We routinely break those since they are not meant
> > > to used by normal users as any kind of permanent "make my machine
> > > work" knob.
> > 
> > But I guess if we want to make it a bit less painful your idea of a new
> > modparam might work. + deprecate the old param and remove after one or
> > two kernel releases.
> 
> Was thinking about a new one to limit the version of PSR:
> 
> enable_psr_version
> default = 0(per-chip default), 1 = up to PSR1, 2 = PSR2

I would use the standard -1==default, 0==disable convention here.
Then we can drop the old param after a short transition period.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH] drm/i915/display: Allow users to disable PSR2

[Rodrigo Vivi]

On Thu, Feb 24, 2022 at 02:15:44PM +, Souza, Jose wrote:
> + Rodrigo
> 
> On Thu, 2022-02-24 at 15:11 +0200, Ville Syrjälä wrote:
> > On Thu, Feb 24, 2022 at 03:06:30PM +0200, Ville Syrjälä wrote:
> > > On Thu, Feb 24, 2022 at 01:01:24PM +, Souza, Jose wrote:
> > > > On Thu, 2022-02-24 at 12:12 +0200, Ville Syrjälä wrote:
> > > > > On Wed, Feb 23, 2022 at 11:41:03AM -0800, José Roberto de Souza wrote:
> > > > > > Some users are suffering with PSR2 issues that are under debug or
> > > > > > issues that were root caused to panel firmware, to make life of 
> > > > > > those
> > > > > > users easier here adding a option to disable PSR1 with kernel
> > > > > > parameter.
> > > > > > 
> > > > > > Using the same enable_psr that is current used to turn PSR1 and PSR2
> > > > > > off or on and adding a new value to only disable PSR2.
> > > > > > The previous valid values did not had their behavior changed.
> > > > > > 
> > > > > > Link: https://gitlab.freedesktop.org/drm/intel/-/issues/4951
> > > > > > Cc: Jouni Högander 
> > > > > > Signed-off-by: José Roberto de Souza 
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/display/intel_psr.c | 4 
> > > > > >  drivers/gpu/drm/i915/i915_params.c   | 2 +-
> > > > > >  2 files changed, 5 insertions(+), 1 deletion(-)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> > > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > index 2e0b092f4b6be..fc6b684bb7bec 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > @@ -100,11 +100,15 @@ static bool psr_global_enabled(struct 
> > > > > > intel_dp *intel_dp)
> > > > > >  
> > > > > >  static bool psr2_global_enabled(struct intel_dp *intel_dp)
> > > > > >  {
> > > > > > +   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > > > > +
> > > > > > switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> > > > > > case I915_PSR_DEBUG_DISABLE:
> > > > > > case I915_PSR_DEBUG_FORCE_PSR1:
> > > > > > return false;
> > > > > > default:
> > > > > > +   if (i915->params.enable_psr == 2)
> > > > > > +   return false;
> > > > > > return true;
> > > > > > }
> > > > > >  }
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_params.c 
> > > > > > b/drivers/gpu/drm/i915/i915_params.c
> > > > > > index eea355c2fc28a..a9b97e6eb3df0 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_params.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_params.c
> > > > > > @@ -94,7 +94,7 @@ i915_param_named_unsafe(enable_hangcheck, bool, 
> > > > > > 0400,
> > > > > >  
> > > > > >  i915_param_named_unsafe(enable_psr, int, 0400,
> > > > > > "Enable PSR "
> > > > > > -   "(0=disabled, 1=enabled) "
> > > > > > +   "(0=disabled, 1=enable up to PSR2 if supported, 2=enable up to 
> > > > > > PSR1) "
> > > > > 
> > > > > That seems very unintuitive. I would just make it 1==PSR1 and 2==PSR2.
> > > > 
> > > > This will break current behavior.
> > > 
> > > It's a modparam. We routinely break those since they are not meant
> > > to used by normal users as any kind of permanent "make my machine
> > > work" knob.
> > 
> > But I guess if we want to make it a bit less painful your idea of a new
> > modparam might work. + deprecate the old param and remove after one or
> > two kernel releases.
> 
> Was thinking about a new one to limit the version of PSR:
> 
> enable_psr_version
> default = 0(per-chip default), 1 = up to PSR1, 2 = PSR2
> 
> > 
> 

My trauma with PSR makes me to ask if we really wants this option.
Is PSR1 really more stable at this point? Shouldn't we just disable everything
while we fix the PSR2 and avoid touching the parameter?

If we are confident that PSR1 is better than simply disabling, then
I like the idea of a new parameter that overrides the previous one so
we can delete in a couple months and keep only one.

i915.psr
default=-1 (per-chip default), 0=disabled, 1=psr1, 2=psr2

but I also would be okay breaking a parameter that is marked as unstable
and which main use externally is to disable the psr (i915.enable_psr=0).

Thanks,
Rodrigo.

Re: [Intel-gfx] [PATCH] drm/i915/display: Allow users to disable PSR2

[Souza, Jose]

+ Rodrigo

On Thu, 2022-02-24 at 15:11 +0200, Ville Syrjälä wrote:
> On Thu, Feb 24, 2022 at 03:06:30PM +0200, Ville Syrjälä wrote:
> > On Thu, Feb 24, 2022 at 01:01:24PM +, Souza, Jose wrote:
> > > On Thu, 2022-02-24 at 12:12 +0200, Ville Syrjälä wrote:
> > > > On Wed, Feb 23, 2022 at 11:41:03AM -0800, José Roberto de Souza wrote:
> > > > > Some users are suffering with PSR2 issues that are under debug or
> > > > > issues that were root caused to panel firmware, to make life of those
> > > > > users easier here adding a option to disable PSR1 with kernel
> > > > > parameter.
> > > > > 
> > > > > Using the same enable_psr that is current used to turn PSR1 and PSR2
> > > > > off or on and adding a new value to only disable PSR2.
> > > > > The previous valid values did not had their behavior changed.
> > > > > 
> > > > > Link: https://gitlab.freedesktop.org/drm/intel/-/issues/4951
> > > > > Cc: Jouni Högander 
> > > > > Signed-off-by: José Roberto de Souza 
> > > > > ---
> > > > >  drivers/gpu/drm/i915/display/intel_psr.c | 4 
> > > > >  drivers/gpu/drm/i915/i915_params.c   | 2 +-
> > > > >  2 files changed, 5 insertions(+), 1 deletion(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > index 2e0b092f4b6be..fc6b684bb7bec 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > @@ -100,11 +100,15 @@ static bool psr_global_enabled(struct intel_dp 
> > > > > *intel_dp)
> > > > >  
> > > > >  static bool psr2_global_enabled(struct intel_dp *intel_dp)
> > > > >  {
> > > > > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > > > +
> > > > >   switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> > > > >   case I915_PSR_DEBUG_DISABLE:
> > > > >   case I915_PSR_DEBUG_FORCE_PSR1:
> > > > >   return false;
> > > > >   default:
> > > > > + if (i915->params.enable_psr == 2)
> > > > > + return false;
> > > > >   return true;
> > > > >   }
> > > > >  }
> > > > > diff --git a/drivers/gpu/drm/i915/i915_params.c 
> > > > > b/drivers/gpu/drm/i915/i915_params.c
> > > > > index eea355c2fc28a..a9b97e6eb3df0 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_params.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_params.c
> > > > > @@ -94,7 +94,7 @@ i915_param_named_unsafe(enable_hangcheck, bool, 
> > > > > 0400,
> > > > >  
> > > > >  i915_param_named_unsafe(enable_psr, int, 0400,
> > > > >   "Enable PSR "
> > > > > - "(0=disabled, 1=enabled) "
> > > > > + "(0=disabled, 1=enable up to PSR2 if supported, 2=enable up to 
> > > > > PSR1) "
> > > > 
> > > > That seems very unintuitive. I would just make it 1==PSR1 and 2==PSR2.
> > > 
> > > This will break current behavior.
> > 
> > It's a modparam. We routinely break those since they are not meant
> > to used by normal users as any kind of permanent "make my machine
> > work" knob.
> 
> But I guess if we want to make it a bit less painful your idea of a new
> modparam might work. + deprecate the old param and remove after one or
> two kernel releases.

Was thinking about a new one to limit the version of PSR:

enable_psr_version
default = 0(per-chip default), 1 = up to PSR1, 2 = PSR2

>