[Intel-gfx] ✓ Fi.CI.IGT: success for i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi
== Series Details == Series: i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi URL : https://patchwork.freedesktop.org/series/102553/ State : success == Summary == CI Bug Log - changes from CI_DRM_11484_full -> Patchwork_102553v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (13 -> 10) -- Missing(3): shard-rkl shard-dg1 shard-tglu Known issues Here are the changes found in Patchwork_102553v1_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-skl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [FAIL][12], [PASS][13], [PASS][14], [FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#5032]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl9/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl9/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl8/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl8/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl7/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl6/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl5/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl1/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl1/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl10/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl10/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl10/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl1/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl9/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl8/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl8/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl7/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl7/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl6/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl6/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl5/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl5/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl4/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl4/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard-skl4/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/shard
Re: [Intel-gfx] [PATCH v9 1/3] i915/gvt: Separate the MMIO tracking table from GVT-g
Ping. :)
On 4/8/22 2:07 PM, Zhi Wang wrote:
> Hi Jani:
>
> Thanks so much for the help. Can you generate a new tag on drm-intel-next? I
> noticed that there was one patch moving the DMC related registers into
> display/intel_dmc_regs.h, which is not included in the latest tag on
> drm-intel-next.
>
> Guess it would be better that I can change this patch according to it when
> checking in. This would prevent a conflict in future.
>
> Thanks,
> Zhi.
>
> On 4/7/22 3:03 PM, Jani Nikula wrote:
>> On Thu, 07 Apr 2022, Zhi Wang wrote:
>>> diff --git a/drivers/gpu/drm/i915/intel_gvt.h
>>> b/drivers/gpu/drm/i915/intel_gvt.h
>>> index d7d3fb6186fd..7665d7cf0bdd 100644
>>> --- a/drivers/gpu/drm/i915/intel_gvt.h
>>> +++ b/drivers/gpu/drm/i915/intel_gvt.h
>>> @@ -26,7 +26,17 @@
>>>
>>> struct drm_i915_private;
>>>
>>> +#include
>>
>> You only need . Please add it before the forward
>> declaration above.
>>
>>> +
>>> #ifdef CONFIG_DRM_I915_GVT
>>> +
>>> +struct intel_gvt_mmio_table_iter {
>>> + struct drm_i915_private *i915;
>>> + void *data;
>>> + int (*handle_mmio_cb)(struct intel_gvt_mmio_table_iter *iter,
>>> + u32 offset, u32 size);
>>> +};
>>> +
>>> int intel_gvt_init(struct drm_i915_private *dev_priv);
>>> void intel_gvt_driver_remove(struct drm_i915_private *dev_priv);
>>> int intel_gvt_init_device(struct drm_i915_private *dev_priv);
>>> @@ -34,6 +44,7 @@ void intel_gvt_clean_device(struct drm_i915_private
>>> *dev_priv);
>>> int intel_gvt_init_host(void);
>>> void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv);
>>> void intel_gvt_resume(struct drm_i915_private *dev_priv);
>>> +int intel_gvt_iterate_mmio_table(struct intel_gvt_mmio_table_iter *iter);
>>> #else
>>> static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
>>> {
>>> @@ -51,6 +62,16 @@ static inline void intel_gvt_sanitize_options(struct
>>> drm_i915_private *dev_priv)
>>> static inline void intel_gvt_resume(struct drm_i915_private *dev_priv)
>>> {
>>> }
>>> +
>>> +unsigned long intel_gvt_get_device_type(struct drm_i915_private *i915)
>>> +{
>>> + return 0;
>>> +}
>>
>> The CONFIG_DRM_I915_GVT=y counterpart for this is in mmio.h. Should be
>> both in the same header.
>>
>>> +
>>> +int intel_gvt_iterate_mmio_table(struct intel_gvt_mmio_table_iter *iter)
>>> +{
>>> + return 0;
>>> +}
>>> #endif
>>>
>>> #endif /* _INTEL_GVT_H_ */
>>> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
>>> b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
>>> new file mode 100644
>>> index ..d29491a6d209
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
>>> @@ -0,0 +1,1290 @@
>>> +// SPDX-License-Identifier: MIT
>>> +/*
>>> + * Copyright © 2020 Intel Corporation
>>> + */
>>> +
>>> +#include "i915_drv.h"
>>> +#include "i915_reg.h"
>>> +#include "display/vlv_dsi_pll_regs.h"
>>> +#include "gt/intel_gt_regs.h"
>>> +#include "intel_mchbar_regs.h"
>>> +#include "i915_pvinfo.h"
>>> +#include "intel_gvt.h"
>>> +#include "gvt/gvt.h"
>>
>> Generally we have the include lists sorted.
>>
>> Other than the nitpicks above, the series is
>>
>> Acked-by: Jani Nikula
>>
>>
>> BR,
>> Jani.
>>
>>
>
[Intel-gfx] [PATCH] drm/i915: Check EDID before dpcd for possible HDR aux bl support
We have now seen panel (XMG Core 15 e21 laptop) avertizing support
for Intel proprietary eDP backlight control via DPCD registers, but
actually working only with legacy pwm control.
This patch adds panel EDID check for possible HDR static metadata and
does detection from DPCD registers only if this data block exists.
Fixes: 4a8d79901d5b ("drm/i915/dp: Enable Intel's HDR backlight interface (only
SDR for now)")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5284
Cc: Lyude Paul
Cc: Mika Kahola
Cc: Jani Nikula
Tested-by: Filippo Falezza
Signed-off-by: Jouni Högander
---
.../gpu/drm/i915/display/intel_dp_aux_backlight.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 97cf3cac0105..f69e185b58c1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -108,6 +108,19 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector
*connector)
int ret;
u8 tcon_cap[4];
+ /*
+* If we don't have HDR static metadata there is no way to
+* runtime detect used range for nits based control. For now
+* do not use Intel proprietary eDP backlight control if we
+* don't have this data in panel EDID. In case we find panel
+* which supports only nits based control, but doesn't provide
+* HDR static metadata we need to start maintaining table of
+* ranges for such panels.
+*/
+ if (!(connector->base.hdr_sink_metadata.hdmi_type1.metadata_type &
+ BIT(HDMI_STATIC_METADATA_TYPE1)))
+ return false;
+
intel_dp_wait_source_oui(intel_dp);
ret = drm_dp_dpcd_read(aux, INTEL_EDP_HDR_TCON_CAP0, tcon_cap,
sizeof(tcon_cap));
--
2.25.1
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi
Yeah that something new https://gitlab.freedesktop.org/drm/intel/-/issues/5631 igt@i915_selftest@live@gt_engines - fail - rcs0 Mismatch between ring timestamp and walltime! i915/live_engine_pm_selftests: live_engine_timestamps failed with error -22 Thanks, Lakshmi. -Original Message- From: Roper, Matthew D Sent: Monday, April 11, 2022 8:11 PM To: intel-gfx@lists.freedesktop.org Cc: Vudum, Lakshminarayana Subject: Re: ✗ Fi.CI.BAT: failure for i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi On Tue, Apr 12, 2022 at 12:43:28AM +, Patchwork wrote: > == Series Details == > > Series: i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi > URL : https://patchwork.freedesktop.org/series/102553/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_11484 -> Patchwork_102553v1 > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_102553v1 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_102553v1, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/index.html > > Participating hosts (49 -> 36) > -- > > Additional (1): fi-hsw-4770 > Missing(14): shard-tglu bat-dg1-6 bat-dg2-8 shard-rkl bat-dg2-9 > fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-kbl-x1275 bat-rpls-1 bat-rpls-2 > shard-dg1 bat-jsl-2 bat-jsl-1 > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_102553v1: > > ### IGT changes ### > > Possible regressions > > * igt@i915_selftest@live@gt_engines: > - fi-glk-j4005: [PASS][1] -> [FAIL][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-glk-j4005/igt@i915_selftest@live@gt_engines.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-glk-j40 > 05/igt@i915_selftest@live@gt_engines.html (i915_selftest:5830) igt_kmod-WARNING: rcs0 elapsed:100430ns, CTX_TIMESTAMP:145261ns, RING_TIMESTAMP:145261ns (i915_selftest:5830) igt_kmod-WARNING: rcs0 Mismatch between ring timestamp and walltime! (i915_selftest:5830) igt_kmod-WARNING: i915/live_engine_pm_selftests: live_engine_timestamps failed with error -22 Doesn't appear to be related to this series since the query interface isn't being used by the test. I don't see any similar failures from a quick fdo search though. Matt > > > Known issues > > > Here are the changes found in Patchwork_102553v1 that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_softpin@allocator-basic-reserve: > - fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271]) +9 similar issues >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-477 > 0/igt@gem_soft...@allocator-basic-reserve.html > > * igt@i915_pm_backlight@basic-brightness: > - fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#3012]) >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-477 > 0/igt@i915_pm_backli...@basic-brightness.html > > * igt@kms_chamelium@dp-crc-fast: > - fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) > +8 similar issues >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-477 > 0/igt@kms_chamel...@dp-crc-fast.html > > * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: > - fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#533]) >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-477 > 0/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html > > * igt@kms_psr@primary_mmap_gtt: > - fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1072]) +3 > similar issues >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-477 > 0/igt@kms_psr@primary_mmap_gtt.html > > * igt@runner@aborted: > - fi-bdw-5557u: NOTRUN -> [FAIL][8] ([i915#4312]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-bdw-555 > 7u/igt@run...@aborted.html > > > Possible fixes > > * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c: > - fi-cfl-8109u: [DMESG-WARN][9] ([i915#5341] / [i915#62]) -> > [PASS][10] >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-cfl-810 > 9u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html > > * igt@kms_pipe_crc_basic@read-crc-pipe-b: > - fi-cfl-8109u: [DMESG-WARN][11] ([i915#62]) -> [PASS][12] +11 > similar i
[Intel-gfx] ✓ Fi.CI.BAT: success for i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi
== Series Details == Series: i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi URL : https://patchwork.freedesktop.org/series/102553/ State : success == Summary == CI Bug Log - changes from CI_DRM_11484 -> Patchwork_102553v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/index.html Participating hosts (49 -> 37) -- Additional (2): fi-kbl-soraka fi-hsw-4770 Missing(14): shard-tglu bat-dg1-6 bat-dg2-8 shard-rkl bat-dg2-9 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-kbl-x1275 bat-rpls-1 bat-rpls-2 shard-dg1 bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_102553v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +9 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_softpin@allocator-basic-reserve: - fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html * igt@i915_pm_backlight@basic-brightness: - fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#3012]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@gt_engines: - fi-glk-j4005: [PASS][6] -> [FAIL][7] ([i915#5631]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-glk-j4005/igt@i915_selftest@live@gt_engines.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-glk-j4005/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][8] ([i915#1886]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@guc_multi_lrc: - fi-kbl-soraka: NOTRUN -> [INCOMPLETE][9] ([i915#5633]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-kbl-soraka/igt@i915_selftest@live@guc_multi_lrc.html * igt@kms_chamelium@dp-crc-fast: - fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@dp-edid-read: - fi-kbl-soraka: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html - fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_mmap_gtt: - fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1072]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][15] ([i915#4312]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-bdw-5557u/igt@run...@aborted.html Possible fixes * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c: - fi-cfl-8109u: [DMESG-WARN][16] ([i915#5341] / [i915#62]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html * igt@kms_pipe_crc_basic@read-crc-pipe-b: - fi-cfl-8109u: [DMESG-WARN][18] ([i915#62]) -> [PASS][19] +11 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-cfl-8109u/igt@kms_pip
[Intel-gfx] ✗ Fi.CI.BAT: failure for i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi
== Series Details == Series: i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi URL : https://patchwork.freedesktop.org/series/102553/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11484 -> Patchwork_102553v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_102553v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_102553v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/index.html Participating hosts (49 -> 37) -- Additional (2): fi-kbl-soraka fi-hsw-4770 Missing(14): shard-tglu bat-dg1-6 bat-dg2-8 shard-rkl bat-dg2-9 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-kbl-x1275 bat-rpls-1 bat-rpls-2 shard-dg1 bat-jsl-2 bat-jsl-1 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_102553v1: ### IGT changes ### Possible regressions * igt@i915_selftest@live@guc_multi_lrc: - fi-kbl-soraka: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-kbl-soraka/igt@i915_selftest@live@guc_multi_lrc.html Known issues Here are the changes found in Patchwork_102553v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +9 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_softpin@allocator-basic-reserve: - fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html * igt@i915_pm_backlight@basic-brightness: - fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3012]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@gt_engines: - fi-glk-j4005: [PASS][7] -> [FAIL][8] ([i915#5631]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-glk-j4005/igt@i915_selftest@live@gt_engines.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-glk-j4005/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@dp-crc-fast: - fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@dp-edid-read: - fi-kbl-soraka: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html - fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_mmap_gtt: - fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1072]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][15] ([i915#4312]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-bdw-5557u/igt@run...@aborted.html Possible fixes * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c: - fi-cfl-8109u: [DMESG-WARN][16] ([i915#5341] / [i915#62]) -> [PASS][17] [16]: https://intel-
Re: [Intel-gfx] [V2 1/3] drm/debug: Expose connector's max supported bpc via debugfs
On Tue-12-04-2022 08:37 am, Murthy, Arun R wrote:
+static int output_bpc_show(struct seq_file *m, void *data) {
Would it be better to have this function name as drm_output_bpc_show()
As we are using DEFINE_SHOW_ATTRIBUTE() to define file_operations, this
function name must be _show(). Otherwise, either we need
to define new file_operations to use the suggested name or rename the
debugfs name to "drm_output_bpc"
Also, to align/maintain uniform with other debugfs, I think it's ok to
use output_bpc_show().
- Bhanu
Thanks and Regards,
Arun R Murthy
Re: [Intel-gfx] [V2 2/3] drm/i915/display/debug: Expose crtc current bpc via debugfs
> -Original Message- > From: Intel-gfx On Behalf Of > Bhanuprakash Modem > Sent: Monday, April 11, 2022 3:21 PM > To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; amd- > g...@lists.freedesktop.org; jani.nik...@linux.intel.com; > ville.syrj...@linux.intel.com; harry.wentl...@amd.com; Sharma, Swati2 > > Subject: [Intel-gfx] [V2 2/3] drm/i915/display/debug: Expose crtc current bpc > via debugfs > > This new debugfs will expose the currently using bpc by crtc. > It is very useful for verifying whether we enter the correct output color > depth > from IGT. > > This patch will also add the connector's max supported bpc to > "i915_display_info" debugfs. > > Example: > cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc > Current: 8 > > Cc: Jani Nikula > Cc: Ville Syrjälä > Cc: Uma Shankar > Signed-off-by: Bhanuprakash Modem Reviewed-by: Arun R Murthy Thanks and Regards, Arun R Murthy ---
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi
On Tue, Apr 12, 2022 at 12:43:28AM +, Patchwork wrote: > == Series Details == > > Series: i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi > URL : https://patchwork.freedesktop.org/series/102553/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_11484 -> Patchwork_102553v1 > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_102553v1 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_102553v1, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/index.html > > Participating hosts (49 -> 36) > -- > > Additional (1): fi-hsw-4770 > Missing(14): shard-tglu bat-dg1-6 bat-dg2-8 shard-rkl bat-dg2-9 > fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-kbl-x1275 bat-rpls-1 bat-rpls-2 > shard-dg1 bat-jsl-2 bat-jsl-1 > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_102553v1: > > ### IGT changes ### > > Possible regressions > > * igt@i915_selftest@live@gt_engines: > - fi-glk-j4005: [PASS][1] -> [FAIL][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-glk-j4005/igt@i915_selftest@live@gt_engines.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-glk-j4005/igt@i915_selftest@live@gt_engines.html (i915_selftest:5830) igt_kmod-WARNING: rcs0 elapsed:100430ns, CTX_TIMESTAMP:145261ns, RING_TIMESTAMP:145261ns (i915_selftest:5830) igt_kmod-WARNING: rcs0 Mismatch between ring timestamp and walltime! (i915_selftest:5830) igt_kmod-WARNING: i915/live_engine_pm_selftests: live_engine_timestamps failed with error -22 Doesn't appear to be related to this series since the query interface isn't being used by the test. I don't see any similar failures from a quick fdo search though. Matt > > > Known issues > > > Here are the changes found in Patchwork_102553v1 that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_softpin@allocator-basic-reserve: > - fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271]) +9 similar issues >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html > > * igt@i915_pm_backlight@basic-brightness: > - fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#3012]) >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html > > * igt@kms_chamelium@dp-crc-fast: > - fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) > +8 similar issues >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html > > * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: > - fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#533]) >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html > > * igt@kms_psr@primary_mmap_gtt: > - fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1072]) +3 > similar issues >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html > > * igt@runner@aborted: > - fi-bdw-5557u: NOTRUN -> [FAIL][8] ([i915#4312]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-bdw-5557u/igt@run...@aborted.html > > > Possible fixes > > * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c: > - fi-cfl-8109u: [DMESG-WARN][9] ([i915#5341] / [i915#62]) -> > [PASS][10] >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html > > * igt@kms_pipe_crc_basic@read-crc-pipe-b: > - fi-cfl-8109u: [DMESG-WARN][11] ([i915#62]) -> [PASS][12] +11 > similar issues >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html > > > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 > [i915#3012]: https://gitlab.freedesktop.org/drm/intel/i
Re: [Intel-gfx] [V2 1/3] drm/debug: Expose connector's max supported bpc via debugfs
> +static int output_bpc_show(struct seq_file *m, void *data) {
Would it be better to have this function name as drm_output_bpc_show()
Thanks and Regards,
Arun R Murthy
Re: [Intel-gfx] [PATCH v5 04/10] drm/hdcp: Expand HDCP helper library for enable/disable/check
Hi Sean, I love your patch! Yet something to improve: [auto build test ERROR on drm-tip/drm-tip] [also build test ERROR on v5.18-rc2 next-20220411] [cannot apply to drm/drm-next drm-intel/for-linux-next robh/for-next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/intel-lab-lkp/linux/commits/Sean-Paul/drm-hdcp-Pull-HDCP-auth-exchange-check-into-helpers/20220412-045000 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip config: mips-buildonly-randconfig-r001-20220411 (https://download.01.org/0day-ci/archive/20220412/202204120922.hnbhbmc7-...@intel.com/config) compiler: mips-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/intel-lab-lkp/linux/commit/7486d07edbd9a137420102bc24535c5d29c53c12 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Sean-Paul/drm-hdcp-Pull-HDCP-auth-exchange-check-into-helpers/20220412-045000 git checkout 7486d07edbd9a137420102bc24535c5d29c53c12 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=mips SHELL=/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): mips-linux-ld: drivers/gpu/drm/drm_hdcp.o: in function `drm_hdcp_remote_dpcd_read': >> drm_hdcp.c:(.text+0x5e4): undefined reference to `drm_dp_dpcd_read' mips-linux-ld: drivers/gpu/drm/drm_hdcp.o: in function `drm_hdcp_remote_write': >> drm_hdcp.c:(.text+0xf48): undefined reference to `drm_dp_dpcd_write' -- 0-DAY CI Kernel Test Service https://01.org/lkp
[Intel-gfx] ✓ Fi.CI.IGT: success for Add DP MST DSC support to i915 (rev4)
== Series Details == Series: Add DP MST DSC support to i915 (rev4) URL : https://patchwork.freedesktop.org/series/101492/ State : success == Summary == CI Bug Log - changes from CI_DRM_11484_full -> Patchwork_101492v4_full Summary --- **SUCCESS** No regressions found. Participating hosts (13 -> 10) -- Missing(3): shard-rkl shard-dg1 shard-tglu Known issues Here are the changes found in Patchwork_101492v4_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-skl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [FAIL][12], [PASS][13], [PASS][14], [FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#5032]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl9/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl9/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl8/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl8/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl7/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl6/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl5/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl1/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl1/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl10/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl10/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl10/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl9/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl8/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl7/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl7/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl7/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl6/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl5/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl5/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl5/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl4/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl4/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/shard-skl4/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_1
Re: [Intel-gfx] [PATCH v2 4/7] drm/i915/guc: use the memcpy_from_wc call from the drm
On 3/21/2022 2:14 PM, Lucas De Marchi wrote:
On Thu, Mar 03, 2022 at 11:30:10PM +0530, Balasubramani Vivekanandan
wrote:
memcpy_from_wc functions in i915_memcpy.c will be removed and replaced
by the implementation in drm_cache.c.
Updated to use the functions provided by drm_cache.c.
v2: Check if the log object allocated from local memory or system memory
and according setup the iosys_map (Lucas)
Cc: Lucas De Marchi
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index a24dc6441872..b9db765627ea 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -3,6 +3,7 @@
* Copyright © 2014-2019 Intel Corporation
*/
+#include
#include
#include
@@ -206,6 +207,7 @@ static void guc_read_update_log_buffer(struct
intel_guc_log *log)
enum guc_log_buffer_type type;
void *src_data, *dst_data;
bool new_overflow;
+ struct iosys_map src_map;
mutex_lock(&log->relay.lock);
@@ -282,14 +284,21 @@ static void guc_read_update_log_buffer(struct
intel_guc_log *log)
}
/* Just copy the newly written data */
+ if (i915_gem_object_is_lmem(log->vma->obj))
+ iosys_map_set_vaddr_iomem(&src_map, (void __iomem
*)src_data);
+ else
+ iosys_map_set_vaddr(&src_map, src_data);
It would be better to keep this outside of the loop. So inside the loop
we can use only iosys_map_incr(&src_map, buffer_size). However you'd
also have to handle the read_offset. The iosys_map_ API has both a
src_offset and dst_offset due to situations like that. Maybe this is
missing in the new drm_memcpy_* function you're adding?
This function was not correct wrt to IO memory access with the other
2 places in this function doing plain memcpy(). Since we are starting to
use iosys_map here, we probably should handle this commit as "migrate to
iosys_map", and convert those. In your current final state
we have 3 variables aliasing the same memory location. IMO it will be
error prone to keep it like that
+Michal, some questions:
- I'm not very familiar with the relayfs API. Is the `dst_data +=
PAGE_SIZE;`
really correct?
This is a bit weird due to how i915 uses the relay for the GuC logs, but
it should be functionally correct. Each relay buffer is the same size of
the GuC log buffer in i915 (which is guaranteed to be greater than
PAGE_SIZE) and we always switch to a new relay buffer each time we dump
new data, so we're guaranteed to have the space we need. We do some
pointer magic because instead of just blindly copying the whole local
log buffer to the relay buffer, we copy the header (which is in the
first page) first, then we copy the rest of the logs (2nd page and
onwards) based on what the header tells us has been filled out.
- Could you double check this patch and ack if ok?
The approach looks good to me, but I agree that at this point we might
as well do a full conversion to iosys map. As you already mentioned, the
memcpy that copies the header would also need to be updated for that,
because it accesses the same memory as src_data, while the other memcpy
is from the local copy of the header to the relay, so it should be safe
to not convert.
Daniele
Heads up that since the log buffer is potentially in lmem, we will need
to convert this function to take that into account. All those accesses
to log_buf_state need to use the proper kernel abstraction for system vs
I/O memory.
thanks
Lucas De Marchi
+
if (read_offset > write_offset) {
- i915_memcpy_from_wc(dst_data, src_data, write_offset);
+ drm_memcpy_from_wc_vaddr(dst_data, &src_map,
+ write_offset);
bytes_to_copy = buffer_size - read_offset;
} else {
bytes_to_copy = write_offset - read_offset;
}
- i915_memcpy_from_wc(dst_data + read_offset,
- src_data + read_offset, bytes_to_copy);
+ iosys_map_incr(&src_map, read_offset);
+ drm_memcpy_from_wc_vaddr(dst_data + read_offset, &src_map,
+ bytes_to_copy);
src_data += buffer_size;
dst_data += buffer_size;
--
2.25.1
[Intel-gfx] ✗ Fi.CI.BAT: failure for i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi
== Series Details == Series: i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi URL : https://patchwork.freedesktop.org/series/102553/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11484 -> Patchwork_102553v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_102553v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_102553v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/index.html Participating hosts (49 -> 36) -- Additional (1): fi-hsw-4770 Missing(14): shard-tglu bat-dg1-6 bat-dg2-8 shard-rkl bat-dg2-9 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-kbl-x1275 bat-rpls-1 bat-rpls-2 shard-dg1 bat-jsl-2 bat-jsl-1 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_102553v1: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_engines: - fi-glk-j4005: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-glk-j4005/igt@i915_selftest@live@gt_engines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-glk-j4005/igt@i915_selftest@live@gt_engines.html Known issues Here are the changes found in Patchwork_102553v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_softpin@allocator-basic-reserve: - fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271]) +9 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html * igt@i915_pm_backlight@basic-brightness: - fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#3012]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html * igt@kms_chamelium@dp-crc-fast: - fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#533]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_mmap_gtt: - fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1072]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][8] ([i915#4312]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-bdw-5557u/igt@run...@aborted.html Possible fixes * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c: - fi-cfl-8109u: [DMESG-WARN][9] ([i915#5341] / [i915#62]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html * igt@kms_pipe_crc_basic@read-crc-pipe-b: - fi-cfl-8109u: [DMESG-WARN][11] ([i915#62]) -> [PASS][12] +11 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102553v1/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Build changes - * Linux: CI_DRM_11484 -> Patchwork_102553v1 CI-20190529: 20190529 CI_DRM_11484: 8034f05811fe63be8ced11c140e59a8cea07a3d6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6419: 33a5adf20dc435cc2c6dd584caa3674c89032762 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_102553v1: 102553v1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3e5b0ebc4047 drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES a2139ca1ff95 drm/i915/doc: Link qu
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: Add support for render/media decompression (rev2)
== Series Details == Series: drm/i915/dg2: Add support for render/media decompression (rev2) URL : https://patchwork.freedesktop.org/series/102147/ State : success == Summary == CI Bug Log - changes from CI_DRM_11484_full -> Patchwork_102147v2_full Summary --- **SUCCESS** No regressions found. Participating hosts (13 -> 10) -- Missing(3): shard-rkl shard-dg1 shard-tglu Known issues Here are the changes found in Patchwork_102147v2_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-skl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [FAIL][12], [PASS][13], [PASS][14], [FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#5032]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl9/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl9/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl8/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl8/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl7/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl6/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl5/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl2/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl1/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl1/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl10/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl10/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/shard-skl10/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl9/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl8/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl7/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl7/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl6/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl5/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl5/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl4/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl4/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl4/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/shard-skl2/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/sh
Re: [Intel-gfx] [PATCH 3/3] drm/i915/guc: Update to GuC version 70.1.1
On 4/8/2022 11:03 AM, john.c.harri...@intel.com wrote: From: John Harrison Update to the latest GuC firmware release. Signed-off-by: John Harrison Reviewed-by: Daniele Ceraolo Spurio Daniele --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index bb864655c495..cb5dd16421d0 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -53,22 +53,22 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, * firmware as TGL. */ #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \ - fw_def(DG2, 0, guc_def(dg2, 69, 0, 3)) \ - fw_def(ALDERLAKE_P, 0, guc_def(adlp, 69, 0, 3)) \ - fw_def(ALDERLAKE_S, 0, guc_def(tgl, 69, 0, 3)) \ - fw_def(DG1, 0, guc_def(dg1, 69, 0, 3)) \ - fw_def(ROCKETLAKE, 0, guc_def(tgl, 69, 0, 3)) \ - fw_def(TIGERLAKE,0, guc_def(tgl, 69, 0, 3)) \ - fw_def(JASPERLAKE, 0, guc_def(ehl, 69, 0, 3)) \ - fw_def(ELKHARTLAKE, 0, guc_def(ehl, 69, 0, 3)) \ - fw_def(ICELAKE, 0, guc_def(icl, 69, 0, 3)) \ - fw_def(COMETLAKE,5, guc_def(cml, 69, 0, 3)) \ - fw_def(COMETLAKE,0, guc_def(kbl, 69, 0, 3)) \ - fw_def(COFFEELAKE, 0, guc_def(kbl, 69, 0, 3)) \ - fw_def(GEMINILAKE, 0, guc_def(glk, 69, 0, 3)) \ - fw_def(KABYLAKE, 0, guc_def(kbl, 69, 0, 3)) \ - fw_def(BROXTON, 0, guc_def(bxt, 69, 0, 3)) \ - fw_def(SKYLAKE, 0, guc_def(skl, 69, 0, 3)) + fw_def(DG2, 0, guc_def(dg2, 70, 1, 1)) \ + fw_def(ALDERLAKE_P, 0, guc_def(adlp, 70, 1, 1)) \ + fw_def(ALDERLAKE_S, 0, guc_def(tgl, 70, 1, 1)) \ + fw_def(DG1, 0, guc_def(dg1, 70, 1, 1)) \ + fw_def(ROCKETLAKE, 0, guc_def(tgl, 70, 1, 1)) \ + fw_def(TIGERLAKE,0, guc_def(tgl, 70, 1, 1)) \ + fw_def(JASPERLAKE, 0, guc_def(ehl, 70, 1, 1)) \ + fw_def(ELKHARTLAKE, 0, guc_def(ehl, 70, 1, 1)) \ + fw_def(ICELAKE, 0, guc_def(icl, 70, 1, 1)) \ + fw_def(COMETLAKE,5, guc_def(cml, 70, 1, 1)) \ + fw_def(COMETLAKE,0, guc_def(kbl, 70, 1, 1)) \ + fw_def(COFFEELAKE, 0, guc_def(kbl, 70, 1, 1)) \ + fw_def(GEMINILAKE, 0, guc_def(glk, 70, 1, 1)) \ + fw_def(KABYLAKE, 0, guc_def(kbl, 70, 1, 1)) \ + fw_def(BROXTON, 0, guc_def(bxt, 70, 1, 1)) \ + fw_def(SKYLAKE, 0, guc_def(skl, 70, 1, 1)) #define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \ fw_def(ALDERLAKE_P, 0, huc_def(tgl, 7, 9, 3)) \
Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Update scheduling policies to new GuC API
On 4/8/2022 11:03 AM, john.c.harri...@intel.com wrote:
From: John Harrison
The latest GuC firmware drops the individual scheduling policy update
H2G commands in favour of a single KLV based H2G. So, change the
update wrappers accordingly.
Unfortunately, the API changes also mean losing the ability to set any
scheduling policy values during context registration. Instead the same
KLV based H2G must be sent after the registration. Of course, that
second H2G per registration might fail due to being backed up. The
registration code has a complicated state machine to cope with the
actual registration call failing. However, if that works then there is
no support for unwinding if a further call should fail. Unwinding
would require sending a H2G to de-register - but that can't be done
because the CTB is already backed up.
So instead, add a new flag to say whether the context has a pending
policy update. This is set if the policy H2G fails at registration
time. The submission code checks for this flag and retries the policy
update if set. If that call fails, the submission path early exists
with a retry error. This is something that is already supported for
other reasons.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 4 +-
drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 15 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 19 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 176 ++
4 files changed, 175 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 9ad6df1b6fbc..be9ac47fa9d0 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -122,11 +122,9 @@ enum intel_guc_action {
INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE = 0x1002,
INTEL_GUC_ACTION_SCHED_ENGINE_MODE_SET = 0x1003,
INTEL_GUC_ACTION_SCHED_ENGINE_MODE_DONE = 0x1004,
- INTEL_GUC_ACTION_SET_CONTEXT_PRIORITY = 0x1005,
- INTEL_GUC_ACTION_SET_CONTEXT_EXECUTION_QUANTUM = 0x1006,
- INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007,
INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,
INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
+ INTEL_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES = 0x100B,
INTEL_GUC_ACTION_SETUP_PC_GUCRC = 0x3004,
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_GET_HWCONFIG = 0x4100,
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
index f0814a57c191..4a59478c3b5c 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
@@ -6,6 +6,8 @@
#ifndef _ABI_GUC_KLVS_ABI_H
#define _ABI_GUC_KLVS_ABI_H
+#include
+
/**
* DOC: GuC KLV
*
@@ -79,4 +81,17 @@
#define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_KEY 0x0907
#define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_LEN 1u
+/*
+ * Per context scheduling policy update keys.
+ */
+enum {
+ GUC_CONTEXT_POLICIES_KLV_ID_EXECUTION_QUANTUM =
0x2001,
+ GUC_CONTEXT_POLICIES_KLV_ID_PREEMPTION_TIMEOUT =
0x2002,
+ GUC_CONTEXT_POLICIES_KLV_ID_SCHEDULING_PRIORITY =
0x2003,
+ GUC_CONTEXT_POLICIES_KLV_ID_PREEMPT_TO_IDLE_ON_QUANTUM_EXPIRY =
0x2004,
+ GUC_CONTEXT_POLICIES_KLV_ID_SLPM_GT_FREQUENCY =
0x2005,
+
+ GUC_CONTEXT_POLICIES_KLV_NUM_IDS = 5,
+};
+
#endif /* _ABI_GUC_KLVS_ABI_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 0e1e8d0079b5..c154b5efccde 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -221,11 +221,22 @@ struct guc_ctxt_registration_info {
};
#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
-#define CONTEXT_POLICY_DEFAULT_EXECUTION_QUANTUM_US 100
-#define CONTEXT_POLICY_DEFAULT_PREEMPTION_TIME_US 50
+/* 32-bit KLV structure as used by policy updates and others */
+struct guc_klv_generic_dw_t {
+ u32 kl;
+ u32 value;
+} __packed;
-/* Preempt to idle on quantum expiry */
-#define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLEBIT(0)
+/* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */
+struct guc_update_context_policy_header {
+ u32 action;
+ u32 ctx_id;
+} __packed;
+
+struct guc_update_context_policy {
+ struct guc_update_context_policy_header header;
+ struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS];
+} __packed;
#define GUC_POWER_UNSPECIFIED 0
#define GUC_POWER_D0 1
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index bd0584d7d489..2bd680064942 100644
--- a/drivers/gpu/drm/i915/gt/uc/int
Re: [Intel-gfx] [PATCH v5 10/10] drm/msm: Implement HDCP 1.x using the new drm HDCP helpers
Hi Sean, I love your patch! Yet something to improve: [auto build test ERROR on drm-tip/drm-tip] [also build test ERROR on v5.18-rc2 next-20220411] [cannot apply to drm/drm-next drm-intel/for-linux-next robh/for-next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/intel-lab-lkp/linux/commits/Sean-Paul/drm-hdcp-Pull-HDCP-auth-exchange-check-into-helpers/20220412-045000 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip config: parisc-buildonly-randconfig-r003-20220411 (https://download.01.org/0day-ci/archive/20220412/202204120815.mywhtgg5-...@intel.com/config) compiler: hppa-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/intel-lab-lkp/linux/commit/ba0d7728b853712a831745c4fddff8d72be1c9c8 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Sean-Paul/drm-hdcp-Pull-HDCP-auth-exchange-check-into-helpers/20220412-045000 git checkout ba0d7728b853712a831745c4fddff8d72be1c9c8 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=parisc SHELL=/bin/bash drivers/gpu/drm/msm/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): >> drivers/gpu/drm/msm/msm_atomic.c:10:10: fatal error: dp_drm.h: No such file >> or directory 10 | #include "dp_drm.h" | ^~ compilation terminated. vim +10 drivers/gpu/drm/msm/msm_atomic.c 9 > 10 #include "dp_drm.h" 11 #include "msm_atomic_trace.h" 12 #include "msm_drv.h" 13 #include "msm_gem.h" 14 #include "msm_kms.h" 15 -- 0-DAY CI Kernel Test Service https://01.org/lkp
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi
== Series Details == Series: i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi URL : https://patchwork.freedesktop.org/series/102553/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH 1/3] drm/i915/guc: Update context registration to new GuC API
On 4/8/2022 11:03 AM, john.c.harri...@intel.com wrote:
From: John Harrison
The latest GuC firmware drops the context descriptor pool in favour of
passing all creation data in the create H2G. It also greatly simplifies
the work queue and removes the process descriptor used for multi-LRC
submission. So, remove all mention of LRC and process descriptors and
update the registration code accordingly.
Unfortunately, the new API also removes the ability to set default
values for the scheduling policies at context registration time.
Instead, a follow up H2G must be sent. This will be addressed in the
next patch.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 5 -
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 52 ++---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 221 --
3 files changed, 116 insertions(+), 162 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 4e431c14b118..3f3373f68123 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -170,11 +170,6 @@ struct intel_guc {
/** @ads_engine_usage_size: size of engine usage in the ADS */
u32 ads_engine_usage_size;
- /** @lrc_desc_pool: object allocated to hold the GuC LRC descriptor pool */
- struct i915_vma *lrc_desc_pool;
- /** @lrc_desc_pool_vaddr: contents of the GuC LRC descriptor pool */
- void *lrc_desc_pool_vaddr;
-
/**
* @context_lookup: used to resolve intel_context from guc_id, if a
* context is present in this structure it is registered with the GuC
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index f21b6de46a99..0e1e8d0079b5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -197,20 +197,28 @@ struct guc_wq_item {
u32 fence_id;
} __packed;
-struct guc_process_desc {
- u32 stage_id;
- u64 db_base_addr;
+struct guc_sched_wq_desc {
u32 head;
u32 tail;
u32 error_offset;
- u64 wq_base_addr;
- u32 wq_size_bytes;
u32 wq_status;
- u32 engine_presence;
- u32 priority;
- u32 reserved[36];
+ u32 reserved[28];
} __packed;
+/* Helper for context registration H2G */
+struct guc_ctxt_registration_info {
+ u32 flags;
+ u32 context_idx;
+ u32 engine_class;
+ u32 engine_submit_mask;
+ u32 wq_desc_lo;
+ u32 wq_desc_hi;
+ u32 wq_base_lo;
+ u32 wq_base_hi;
+ u32 wq_size;
+ u32 hwlrca_lo;
+ u32 hwlrca_hi;
+};
#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
#define CONTEXT_POLICY_DEFAULT_EXECUTION_QUANTUM_US 100
@@ -219,34 +227,6 @@ struct guc_process_desc {
/* Preempt to idle on quantum expiry */
#define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE BIT(0)
-/*
- * GuC Context registration descriptor.
- * FIXME: This is only required to exist during context registration.
- * The current 1:1 between guc_lrc_desc and LRCs for the lifetime of the LRC
- * is not required.
- */
-struct guc_lrc_desc {
- u32 hw_context_desc;
- u32 slpm_perf_mode_hint;/* SPLC v1 only */
- u32 slpm_freq_hint;
- u32 engine_submit_mask; /* In logical space */
- u8 engine_class;
- u8 reserved0[3];
- u32 priority;
- u32 process_desc;
- u32 wq_addr;
- u32 wq_size;
- u32 context_flags; /* CONTEXT_REGISTRATION_* */
- /* Time for one workload to execute. (in micro seconds) */
- u32 execution_quantum;
- /* Time to wait for a preemption request to complete before issuing a
-* reset. (in micro seconds).
-*/
- u32 preemption_timeout;
- u32 policy_flags; /* CONTEXT_POLICY_* */
- u32 reserved1[19];
-} __packed;
-
#define GUC_POWER_UNSPECIFIED 0
#define GUC_POWER_D0 1
#define GUC_POWER_D1 2
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e1612c393781..bd0584d7d489 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -396,12 +396,12 @@ struct sync_semaphore {
};
struct parent_scratch {
- struct guc_process_desc pdesc;
+ struct guc_sched_wq_desc wq_desc;
struct sync_semaphore go;
struct sync_semaphore join[MAX_ENGINE_INSTANCE + 1];
- u8 unused[WQ_OFFSET - sizeof(struct guc_process_desc) -
+ u8 unused[WQ_OFFSET - sizeof(struct guc_sched_wq_desc) -
sizeof(struct sync_semaphore) * (MAX_ENGINE_INSTANCE + 2)];
u32 wq[WQ_SIZE / sizeof(u32)];
@@ -438,15 +438,15 @@ __get_parent_scratch(struct intel_context *ce)
LRC_STATE_OFFSET) / sizeof(u32)));
}
-static struct guc_process_desc *
-_
Re: [Intel-gfx] [PATCH v4 RFC] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
On Fri, Apr 01, 2022 at 03:19:26PM -0700, Francisco Jerez wrote:
> Daniel Vetter writes:
>
> > On Wed, Mar 30, 2022 at 02:53:11PM -0700, Matt Atwood wrote:
...
> >> @@ -2718,6 +2719,9 @@ struct drm_i915_query_item {
> >> * - DRM_I915_QUERY_PERF_CONFIG_LIST
> >> * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
> >> * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
> >> + *
> >> + * When query_id == DRM_I915_QUERY_GEOMETRY_SUBSLICES must have a valid
> >> + * i915_engine_class_instance struct.
>
> It would also be worth adding to the documentation that the specified engine
> must be a render engine instance.
>
> >> */
> >>__u32 flags;
> >> #define DRM_I915_QUERY_PERF_CONFIG_LIST 1
> >> @@ -2776,16 +2780,20 @@ struct drm_i915_query {
> >> };
> >>
> >> /*
> >
> > Can we please include this in the kerneldoc, and also make sure that the
> > queries are nicely all listed somewhere and link to each respective
> > information structure?
> >
> > Most of the doc for queries is there now, but the presentation and linking
> > lacks still a lot.
> > -Daniel
MattA is out at the moment, so I've picked this up in his absence; I
sent a new series here that includes various kerneldoc updates in
addition to his patch:
https://patchwork.freedesktop.org/series/102553/
Let me know if that's more along the lines of what you guys were looking
for.
Matt
> >
> >> - * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
> >> + * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO,
> >> + * DRM_I915_QUERY_GEOMETRY_SUBSLICE:
> >> *
> >> * data: contains the 3 pieces of information :
> >> *
> >> - * - the slice mask with one bit per slice telling whether a slice is
> >> - * available. The availability of slice X can be queried with the
> >> following
> >> - * formula :
> >> + * - For DRM_I915_QUERY_TOPOLOGY_INFO the slice mask with one bit per
> >> slice
> >> + * telling whether a slice is available. The availability of slice X
> >> can be
> >> + * queried with the following formula :
> >> *
> >> * (data[X / 8] >> (X % 8)) & 1
> >> *
> >> + * - For DRM_I915_QUERY_GEOMETRY_SUBSLICES Slices are equal to 1 and this
> >> field
> >> + * is not used.
> >> + *
> >> * - the subslice mask for each slice with one bit per subslice telling
> >> * whether a subslice is available. Gen12 has dual-subslices, which are
> >> * similar to two gen11 subslices. For gen12, this array represents
> >> dual-
> >> --
> >> 2.21.3
> >>
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: ttm for stolen region
== Series Details == Series: drm/i915: ttm for stolen region URL : https://patchwork.freedesktop.org/series/102540/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11484 -> Patchwork_102540v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_102540v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_102540v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/index.html Participating hosts (49 -> 38) -- Additional (2): fi-kbl-soraka fi-hsw-4770 Missing(13): shard-tglu bat-dg1-6 bat-dg2-8 shard-rkl bat-dg2-9 fi-bsw-cyan bat-adlp-6 bat-adlp-4 bat-rpls-1 bat-rpls-2 shard-dg1 bat-jsl-2 bat-jsl-1 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_102540v1: ### IGT changes ### Possible regressions * igt@i915_selftest@live@mman: - fi-ivb-3770:[PASS][1] -> [DMESG-FAIL][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-ivb-3770/igt@i915_selftest@l...@mman.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-ivb-3770/igt@i915_selftest@l...@mman.html * igt@runner@aborted: - fi-snb-2600:NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-snb-2600/igt@run...@aborted.html - fi-ilk-650: NOTRUN -> [FAIL][4] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-ilk-650/igt@run...@aborted.html - fi-bdw-gvtdvm: NOTRUN -> [FAIL][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-bdw-gvtdvm/igt@run...@aborted.html - fi-cfl-8700k: NOTRUN -> [FAIL][6] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-cfl-8700k/igt@run...@aborted.html - fi-cfl-8109u: NOTRUN -> [FAIL][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-cfl-8109u/igt@run...@aborted.html - fi-snb-2520m: NOTRUN -> [FAIL][8] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-snb-2520m/igt@run...@aborted.html - fi-bdw-5557u: NOTRUN -> [FAIL][9] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-bdw-5557u/igt@run...@aborted.html - fi-bwr-2160:NOTRUN -> [FAIL][10] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-bwr-2160/igt@run...@aborted.html - fi-hsw-g3258: NOTRUN -> [FAIL][11] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-hsw-g3258/igt@run...@aborted.html - fi-kbl-soraka: NOTRUN -> [FAIL][12] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-kbl-soraka/igt@run...@aborted.html - fi-kbl-7500u: NOTRUN -> [FAIL][13] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-kbl-7500u/igt@run...@aborted.html - fi-rkl-guc: NOTRUN -> [FAIL][14] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-rkl-guc/igt@run...@aborted.html - fi-bxt-dsi: NOTRUN -> [FAIL][15] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-bxt-dsi/igt@run...@aborted.html - fi-adl-ddr5:NOTRUN -> [FAIL][16] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-adl-ddr5/igt@run...@aborted.html - fi-elk-e7500: NOTRUN -> [FAIL][17] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-elk-e7500/igt@run...@aborted.html - fi-cfl-guc: NOTRUN -> [FAIL][18] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-cfl-guc/igt@run...@aborted.html - fi-glk-j4005: NOTRUN -> [FAIL][19] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-glk-j4005/igt@run...@aborted.html - fi-skl-guc: NOTRUN -> [FAIL][20] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-skl-guc/igt@run...@aborted.html - fi-skl-6700k2: NOTRUN -> [FAIL][21] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-skl-6700k2/igt@run...@aborted.html Warnings * igt@runner@aborted: - fi-kbl-8809g: [FAIL][22] ([i915#2722]) -> [FAIL][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-kbl-8809g/igt@run...@aborted.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-kbl-8809g/igt@run...@aborted.html - fi-apl-guc: [FAIL][24] ([i915#4312]) -> [FAIL][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-apl-guc/igt@run...@aborted.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102540v1/fi-apl-guc/igt@run...@a
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: ttm for stolen region
== Series Details == Series: drm/i915: ttm for stolen region URL : https://patchwork.freedesktop.org/series/102540/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for Add DP MST DSC support to i915 (rev4)
== Series Details == Series: Add DP MST DSC support to i915 (rev4) URL : https://patchwork.freedesktop.org/series/101492/ State : success == Summary == CI Bug Log - changes from CI_DRM_11484 -> Patchwork_101492v4 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/index.html Participating hosts (49 -> 37) -- Additional (2): fi-kbl-soraka fi-hsw-4770 Missing(14): shard-tglu bat-dg1-6 bat-dg2-8 shard-rkl bat-dg2-9 fi-bsw-cyan bat-adlp-6 bat-adlp-4 bat-rpls-1 bat-rpls-2 shard-dg1 bat-jsl-2 bat-jsl-1 fi-snb-2600 Known issues Here are the changes found in Patchwork_101492v4 that come from known issues: ### IGT changes ### Issues hit * igt@core_hotunplug@unbind-rebind: - fi-blb-e6850: [PASS][1] -> [FAIL][2] ([i915#3194]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +9 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_softpin@allocator-basic-reserve: - fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271]) +9 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html * igt@i915_pm_backlight@basic-brightness: - fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#3012]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][8] ([i915#1886]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@dp-crc-fast: - fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@dp-edid-read: - fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html - fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_mmap_gtt: - fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1072]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][14] ([i915#4312]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/fi-bdw-5557u/igt@run...@aborted.html Possible fixes * igt@kms_force_connector_basic@prune-stale-modes: - fi-cfl-8109u: [DMESG-WARN][15] ([i915#62]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-cfl-8109u/igt@kms_force_connector_ba...@prune-stale-modes.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v4/fi-cfl-8109u/igt@kms_force_connector_ba...@prune-stale-modes.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194 [i915#4312]: https://git
[Intel-gfx] [PATCH 1/4] drm/i915/doc: Convert drm_i915_query_topology_info comment to kerneldoc
This structure has a great comment describing the fields, but it's not
currently in kerneldoc form and does not show up in the generated
documentation. Let's fix that and also clarify the description of what
"subslice" refers to on gen12 platforms and beyond and that "slice" is
no longer meaningful on Xe_HP and beyond.
Signed-off-by: Matt Roper
---
include/uapi/drm/i915_drm.h | 110 +---
1 file changed, 78 insertions(+), 32 deletions(-)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 9ab021c4d632..73e1c6180ddb 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2775,66 +2775,112 @@ struct drm_i915_query {
__u64 items_ptr;
};
-/*
- * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
- *
- * data: contains the 3 pieces of information :
- *
- * - the slice mask with one bit per slice telling whether a slice is
- * available. The availability of slice X can be queried with the following
- * formula :
- *
- * (data[X / 8] >> (X % 8)) & 1
- *
- * - the subslice mask for each slice with one bit per subslice telling
- * whether a subslice is available. Gen12 has dual-subslices, which are
- * similar to two gen11 subslices. For gen12, this array represents dual-
- * subslices. The availability of subslice Y in slice X can be queried
- * with the following formula :
- *
- * (data[subslice_offset +
- * X * subslice_stride +
- * Y / 8] >> (Y % 8)) & 1
- *
- * - the EU mask for each subslice in each slice with one bit per EU telling
- * whether an EU is available. The availability of EU Z in subslice Y in
- * slice X can be queried with the following formula :
+/**
+ * struct drm_i915_query_topology_info
*
- * (data[eu_offset +
- * (X * max_subslices + Y) * eu_stride +
- * Z / 8] >> (Z % 8)) & 1
+ * Describes slice/subslice/EU information queried by
+ * %DRM_I915_QUERY_TOPOLOGY_INFO
*/
struct drm_i915_query_topology_info {
- /*
+ /**
+* @flags:
+*
* Unused for now. Must be cleared to zero.
*/
__u16 flags;
+ /**
+* @max_slices:
+*
+* The number of bits used to express the slice mask.
+*/
__u16 max_slices;
+
+ /**
+* @max_subslices:
+*
+* The number of bits used to express the subslice mask.
+*/
__u16 max_subslices;
+
+ /**
+* @max_eus_per_subslice:
+*
+* The number of bits in the EU mask that correspond to a single
+* subslice's EUs.
+*/
__u16 max_eus_per_subslice;
- /*
+ /**
+* @subslice_offset:
+*
* Offset in data[] at which the subslice masks are stored.
*/
__u16 subslice_offset;
- /*
+ /**
+* @subslice_stride:
+*
* Stride at which each of the subslice masks for each slice are
* stored.
*/
__u16 subslice_stride;
- /*
+ /**
+* @eu_offset:
+*
* Offset in data[] at which the EU masks are stored.
*/
__u16 eu_offset;
- /*
+ /**
+* @eu_stride:
+*
* Stride at which each of the EU masks for each subslice are stored.
*/
__u16 eu_stride;
+ /**
+* @data:
+*
+* Contains 3 pieces of information :
+*
+* - The slice mask with one bit per slice telling whether a slice is
+* available. The availability of slice X can be queried with the
+* following formula :
+*
+* .. code:: c
+*
+* (data[X / 8] >> (X % 8)) & 1
+*
+* Starting with Xe_HP platforms, Intel hardware no longer has
+* traditional slices so i915 will always report a single slice
+* (hardcoded slicemask = 0x1) which contains all of the platform's
+* subslices. I.e., the mask here does not reflect any of the newer
+* hardware concepts such as "gslices" or "cslices" since userspace
+* is capable of inferring those from the subslice mask.
+*
+* - The subslice mask for each slice with one bit per subslice telling
+* whether a subslice is available. Starting with Gen12 we use the
+* term "subslice" to refer to what the hardware documentation
+* describes as a "dual-subslices." The availability of subslice Y
+* in slice X can be queried with the following formula :
+*
+* .. code:: c
+*
+* (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y %
8)) & 1
+*
+* - The EU mask for each subslice in each slice, with one bit per EU
+* telling whether an EU is available. The availability of EU Z in
+* subslice Y in slice
[Intel-gfx] [PATCH 3/4] drm/i915/doc: Link query items to their uapi structs
Document the possible options for drm_i915_query_item.query_id with
links to the corresponding uapi structures.
Signed-off-by: Matt Roper
---
include/uapi/drm/i915_drm.h | 34 --
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 787dab98f7b0..097a7935a510 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2724,18 +2724,24 @@ struct drm_i915_perf_oa_config {
*
* The behaviour is determined by the @query_id. Note that exactly what
* @data_ptr is also depends on the specific @query_id.
- *
- * For specific queries see:
- * * `GuC HWCONFIG blob uAPI`_
*/
struct drm_i915_query_item {
- /** @query_id: The id for this query */
+ /**
+* @query_id:
+*
+* The id for this query. Currently accepted query IDs are:
+* - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct
drm_i915_query_topology_info)
+* - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info)
+* - %DRM_I915_QUERY_PERF_CONFIG (see struct
drm_i915_query_perf_config)
+* - %DRM_I915_QUERY_MEMORY_REGIONS (see struct
drm_i915_query_memory_regions)
+* - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`)
+*/
__u64 query_id;
-#define DRM_I915_QUERY_TOPOLOGY_INFO1
-#define DRM_I915_QUERY_ENGINE_INFO 2
-#define DRM_I915_QUERY_PERF_CONFIG 3
-#define DRM_I915_QUERY_MEMORY_REGIONS 4
-#define DRM_I915_QUERY_HWCONFIG_BLOB 5
+#define DRM_I915_QUERY_TOPOLOGY_INFO 1
+#define DRM_I915_QUERY_ENGINE_INFO 2
+#define DRM_I915_QUERY_PERF_CONFIG 3
+#define DRM_I915_QUERY_MEMORY_REGIONS 4
+#define DRM_I915_QUERY_HWCONFIG_BLOB 5
/* Must be kept compact -- no holes and well documented */
/**
@@ -2751,14 +2757,14 @@ struct drm_i915_query_item {
/**
* @flags:
*
-* When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
+* When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
*
-* When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
+* When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the
* following:
*
-* - DRM_I915_QUERY_PERF_CONFIG_LIST
-* - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
-* - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
+* - %DRM_I915_QUERY_PERF_CONFIG_LIST
+* - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
+* - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
*/
__u32 flags;
#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
--
2.34.1
[Intel-gfx] [PATCH 2/4] drm/i915/doc: Convert perf UAPI comments to kerneldoc
Convert the comments for drm_i915_query_perf_config and
drm_i915_perf_oa_config to kerneldoc so that they will show up in the
generated documentation. Also correct a couple places that referred to
query_id when they actually meant to refer to query_item.flags.
Signed-off-by: Matt Roper
---
include/uapi/drm/i915_drm.h | 116 ++--
1 file changed, 86 insertions(+), 30 deletions(-)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 73e1c6180ddb..787dab98f7b0 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2657,24 +2657,65 @@ enum drm_i915_perf_record_type {
DRM_I915_PERF_RECORD_MAX /* non-ABI */
};
-/*
+/**
+ * struct drm_i915_perf_oa_config
+ *
* Structure to upload perf dynamic configuration into the kernel.
*/
struct drm_i915_perf_oa_config {
- /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
+ /**
+* @uuid:
+*
+* String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"
+*/
char uuid[36];
+ /**
+* @n_mux_regs:
+*
+* Number of mux regs in &mux_regs_ptr.
+*/
__u32 n_mux_regs;
+
+ /**
+* @n_boolean_regs:
+*
+* Number of boolean regs in &boolean_regs_ptr.
+*/
__u32 n_boolean_regs;
+
+ /**
+* @n_flex_regs:
+*
+* Number of flex regs in &flex_regs_ptr.
+*/
__u32 n_flex_regs;
- /*
-* These fields are pointers to tuples of u32 values (register address,
-* value). For example the expected length of the buffer pointed by
-* mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
+ /**
+* @mux_regs_ptr:
+*
+* Pointer to tuples of u32 values (register address, value) for mux
+* registers. Expected length of buffer is (2 * sizeof(u32) *
+* &n_mux_regs).
*/
__u64 mux_regs_ptr;
+
+ /**
+* @boolean_regs_ptr:
+*
+* Pointer to tuples of u32 values (register address, value) for mux
+* registers. Expected length of buffer is (2 * sizeof(u32) *
+* &n_boolean_regs).
+*/
__u64 boolean_regs_ptr;
+
+ /**
+* @flex_regs_ptr:
+*
+* Pointer to tuples of u32 values (register address, value) for mux
+* registers. Expected length of buffer is (2 * sizeof(u32) *
+* &n_flex_regs).
+*/
__u64 flex_regs_ptr;
};
@@ -3001,52 +3042,67 @@ struct drm_i915_query_engine_info {
struct drm_i915_engine_info engines[];
};
-/*
- * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
+/**
+ * struct drm_i915_query_perf_config
+ *
+ * Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG.
*/
struct drm_i915_query_perf_config {
union {
- /*
-* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST,
i915 sets
-* this fields to the number of configurations available.
+ /**
+* @n_configs:
+*
+* When &drm_i915_query_item.flags ==
+* %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to
+* the number of configurations available.
*/
__u64 n_configs;
- /*
-* When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
-* i915 will use the value in this field as configuration
-* identifier to decide what data to write into config_ptr.
+ /**
+* @config:
+*
+* When &drm_i915_query_item.flags ==
+* %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the
+* value in this field as configuration identifier to decide
+* what data to write into config_ptr.
*/
__u64 config;
- /*
-* When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
-* i915 will use the value in this field as configuration
-* identifier to decide what data to write into config_ptr.
+ /**
+* @uuid:
+*
+* When &drm_i915_query_item.flags ==
+* %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the
+* value in this field as configuration identifier to decide
+* what data to write into config_ptr.
*
* String formatted like "%08x-%04x-%04x-%04x-%012x"
*/
char uuid[36];
};
- /*
+ /**
+* @flags:
+*
* Unused for now. Must be cleared to zero.
*/
__u32 flags;
- /*
-* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
-* write
[Intel-gfx] [PATCH 4/4] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
From: Matt Atwood
Newer platforms have DSS that aren't necessarily available for both
geometry and compute, two queries will need to exist. This introduces
the first, when passing a valid engine class and engine instance in the
flags returns a topology describing geometry.
Based on past discussion, we currently only support this new query item
on Xe_HP and beyond; earlier platforms do not need to worry about
geometry and compute pipelines having access to different topology and
should continue to use the existing topology query.
v2: fix white space errors
v3: change flags from hosting 2 8 bit numbers to holding a
i915_engine_class_instance struct
v4: add error if non rcs engine passed.
v5 (by MattR):
- Improve kerneldoc and cross references to related structs/enums.
(Daniel)
- Clarify that geometry query is only supported on render engines
(Francisco)
- Clarify that the new query is only supported on Xe_HP+.
- Fix checkpatch warnings.
Cc: Ashutosh Dixit
Cc: Matt Roper
Cc: Joonas Lahtinen
Cc: Francisco Jerez
UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
Signed-off-by: Matt Atwood
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_query.c | 71 ++-
include/uapi/drm/i915_drm.h | 27 ++--
2 files changed, 75 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index b5ca00cb6cf6..7584cec53d5d 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -9,6 +9,7 @@
#include "i915_drv.h"
#include "i915_perf.h"
#include "i915_query.h"
+#include "gt/intel_engine_user.h"
#include
static int copy_query_item(void *query_hdr, size_t query_sz,
@@ -28,36 +29,30 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
return 0;
}
-static int query_topology_info(struct drm_i915_private *dev_priv,
- struct drm_i915_query_item *query_item)
+static int fill_topology_info(const struct sseu_dev_info *sseu,
+ struct drm_i915_query_item *query_item,
+ const u8 *subslice_mask)
{
- const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
int ret;
- if (query_item->flags != 0)
- return -EINVAL;
+ BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
if (sseu->max_slices == 0)
return -ENODEV;
- BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
-
slice_length = sizeof(sseu->slice_mask);
subslice_length = sseu->max_slices * sseu->ss_stride;
eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
- ret = copy_query_item(&topo, sizeof(topo), total_length,
- query_item);
+ ret = copy_query_item(&topo, sizeof(topo), total_length, query_item);
+
if (ret != 0)
return ret;
- if (topo.flags != 0)
- return -EINVAL;
-
memset(&topo, 0, sizeof(topo));
topo.max_slices = sseu->max_slices;
topo.max_subslices = sseu->max_subslices;
@@ -69,27 +64,64 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
topo.eu_stride = sseu->eu_stride;
if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
- &topo, sizeof(topo)))
+&topo, sizeof(topo)))
return -EFAULT;
if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + sizeof(topo)),
- &sseu->slice_mask, slice_length))
+&sseu->slice_mask, slice_length))
return -EFAULT;
if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
- sizeof(topo) + slice_length),
- sseu->subslice_mask, subslice_length))
+sizeof(topo) + slice_length),
+subslice_mask, subslice_length))
return -EFAULT;
if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
- sizeof(topo) +
- slice_length + subslice_length),
- sseu->eu_mask, eu_length))
+sizeof(topo) +
+slice_length + subslice_length),
+sseu->eu_mask, eu_length))
return -EFAULT;
return total_length;
}
+static int query_topology_info(struct drm_i915_private *dev_priv,
+ struct drm_i915_query_item *query_item)
+{
+ const struct sseu_dev_inf
[Intel-gfx] [PATCH 0/4] i915: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES uapi
This is a continuation of Matt Atwood's new geometry topology query from here: https://patchwork.freedesktop.org/series/101219/#rev4 This does a bit of initial cleanup/clarification of the query interface documentation (including converting more of it to kerneldoc so it will actually show up in the generated html/pdf) and then applies MattA's changes on top of that. Cc: Matt Atwood Cc: Francisco Jerez Cc: Daniel Vetter UMD(Mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143 Matt Atwood (1): drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES Matt Roper (3): drm/i915/doc: Convert drm_i915_query_topology_info comment to kerneldoc drm/i915/doc: Convert perf UAPI comments to kerneldoc drm/i915/doc: Link query items to their uapi structs drivers/gpu/drm/i915/i915_query.c | 71 ++-- include/uapi/drm/i915_drm.h | 285 +- 2 files changed, 258 insertions(+), 98 deletions(-) -- 2.34.1
[Intel-gfx] ✗ Fi.CI.BAT: failure for drivers: Fix spelling mistake "writting" -> "writing"
== Series Details == Series: drivers: Fix spelling mistake "writting" -> "writing" URL : https://patchwork.freedesktop.org/series/102525/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11484 -> Patchwork_102525v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_102525v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_102525v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102525v1/index.html Participating hosts (49 -> 38) -- Additional (2): fi-kbl-soraka fi-hsw-4770 Missing(13): shard-tglu bat-dg1-6 bat-dg2-8 shard-rkl bat-dg2-9 fi-bsw-cyan bat-adlp-6 bat-adlp-4 bat-rpls-1 bat-rpls-2 shard-dg1 bat-jsl-2 bat-jsl-1 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_102525v1: ### IGT changes ### Possible regressions * igt@i915_selftest@live@mman: - fi-bdw-5557u: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102525v1/fi-bdw-5557u/igt@i915_selftest@l...@mman.html Known issues Here are the changes found in Patchwork_102525v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +9 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102525v1/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102525v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102525v1/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_softpin@allocator-basic-reserve: - fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102525v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html * igt@i915_pm_backlight@basic-brightness: - fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3012]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102525v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - fi-glk-j4005: [PASS][7] -> [DMESG-WARN][8] ([i915#118]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-glk-j4005/igt@i915_pm_...@basic-api.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102525v1/fi-glk-j4005/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102525v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - fi-hsw-g3258: [PASS][10] -> [INCOMPLETE][11] ([i915#3303] / [i915#4785]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102525v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@dp-crc-fast: - fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102525v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@dp-edid-read: - fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102525v1/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102525v1/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html - fi-kbl-soraka: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#533]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102525v1/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_mmap_gtt: - fi-hsw-4770:NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1072]) +3 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102525v1/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html * igt@kms_setmode@basic-clone-single-crtc: - fi-bdw-5557u: NOT
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drivers: Fix spelling mistake "writting" -> "writing"
== Series Details == Series: drivers: Fix spelling mistake "writting" -> "writing" URL : https://patchwork.freedesktop.org/series/102525/ State : warning == Summary == Error: dim checkpatch failed 6dc04b2a73d1 drivers: Fix spelling mistake "writting" -> "writing" -:4: WARNING:TYPO_SPELLING: 'writting' may be misspelled - perhaps 'writing'? #4: Subject: [PATCH] drivers: Fix spelling mistake "writting" -> "writing" -:20: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #20: FILE: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:7307: +* index will auto-inc after each data writing */ total: 0 errors, 2 warnings, 0 checks, 82 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Add support for render/media decompression (rev2)
== Series Details == Series: drm/i915/dg2: Add support for render/media decompression (rev2) URL : https://patchwork.freedesktop.org/series/102147/ State : success == Summary == CI Bug Log - changes from CI_DRM_11484 -> Patchwork_102147v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/index.html Participating hosts (49 -> 37) -- Additional (2): fi-kbl-soraka fi-hsw-4770 Missing(14): shard-tglu bat-dg1-6 bat-dg2-8 shard-rkl fi-icl-u2 bat-dg2-9 bat-adlp-6 fi-bsw-cyan bat-adlp-4 bat-rpls-1 bat-rpls-2 shard-dg1 bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_102147v2 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +9 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_softpin@allocator-basic-reserve: - fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html * igt@i915_pm_backlight@basic-brightness: - fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#3012]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][6] ([i915#1886]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[PASS][7] -> [INCOMPLETE][8] ([i915#3921]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@dp-crc-fast: - fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@dp-edid-read: - fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html - fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_mmap_gtt: - fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1072]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][14] ([i915#4312]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/fi-bdw-5557u/igt@run...@aborted.html Possible fixes * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c: - fi-cfl-8109u: [DMESG-WARN][15] ([i915#5341] / [i915#62]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html * igt@kms_pipe_crc_basic@read-crc-pipe-b: - fi-cfl-8109u: [DMESG-WARN][17] ([i915#62]) -> [PASS][18] +11 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11484/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102147v2/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?i
Re: [Intel-gfx] [PATCH 09/20] drm/i915/gsc: add slow_fw flag to the gsc device definition
On 4/7/2022 5:58 AM, Alexander Usyskin wrote:
Add slow_fw flag to the gsc device definition
and pass it to mei auxiliary device.
Signed-off-by: Alexander Usyskin
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c
b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 280dba4fd32d..175571c6f71d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -41,6 +41,7 @@ struct gsc_def {
unsigned long bar;
size_t bar_size;
bool use_polling;
+ bool slow_fw;
};
/* gsc resources and definitions (HECI1 and HECI2) */
@@ -125,6 +126,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
adev->bar.end = adev->bar.start + def->bar_size - 1;
adev->bar.flags = IORESOURCE_MEM;
adev->bar.desc = IORES_DESC_NONE;
+ adev->slow_fw = def->slow_fw;
aux_dev = &adev->aux_dev;
aux_dev->name = def->name;
Re: [Intel-gfx] [PATCH 08/20] drm/i915/gsc: add slow_fw flag to the mei auxiliary device
On 4/7/2022 5:58 AM, Alexander Usyskin wrote:
Add slow_fw flag to the mei auxiliary device info
to inform the mei driver about slow underlying firmware.
Such firmware will require to use larger operation timeouts.
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
Might be worth squashing this in one of the patches that makes use of
it, but I can see the benefit of having the interface added in a patch
that's neither mei nor i915.
Reviewed-by: Daniele Ceraolo Spurio
---
include/linux/mei_aux.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
index 587f25128848..a29f4064b9c0 100644
--- a/include/linux/mei_aux.h
+++ b/include/linux/mei_aux.h
@@ -11,6 +11,7 @@ struct mei_aux_device {
struct auxiliary_device aux_dev;
int irq;
struct resource bar;
+ bool slow_fw;
};
#define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \
Re: [Intel-gfx] [PATCH 07/20] drm/i915/gsc: skip irq initialization if using polling
On 4/7/2022 5:58 AM, Alexander Usyskin wrote:
From: Vitaly Lubart
If we use polling instead of interrupts,
irq initialization should be skipped.
This needs at least a 1 line explanation if why we might need to use
polling. Something like "some platforms require the host to poll on the
GSC reply instead of relaying on the interrupts. For those platforms,
irq initialization should be skipped."
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c
b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 21e860861f0b..280dba4fd32d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -40,6 +40,7 @@ struct gsc_def {
const char *name;
unsigned long bar;
size_t bar_size;
+ bool use_polling;
};
/* gsc resources and definitions (HECI1 and HECI2) */
@@ -97,6 +98,10 @@ static void gsc_init_one(struct drm_i915_private *i915,
return;
}
+ /* skip irq initialization */
+ if (def->use_polling)
+ goto add_device;
We tend to limit the use of gotos to the error paths, so I'd prefer it
if this was flipped to avoid it, i.e.:
if (!def->use_polling) {
/* set up irqs */
[...]
}
But not a blocker. With the commit message updated:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
+
intf->irq = irq_alloc_desc(0);
if (intf->irq < 0) {
drm_err(&i915->drm, "gsc irq error %d\n", intf->irq);
@@ -109,6 +114,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
goto fail;
}
+add_device:
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
if (!adev)
goto fail;
@@ -162,10 +168,8 @@ static void gsc_irq_handler(struct intel_gt *gt, unsigned
int intf_id)
return;
}
- if (gt->gsc.intf[intf_id].irq < 0) {
- drm_err_ratelimited(>->i915->drm, "GSC irq: irq not set");
+ if (gt->gsc.intf[intf_id].irq < 0)
return;
- }
ret = generic_handle_irq(gt->gsc.intf[intf_id].irq);
if (ret)
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg2: Add support for render/media decompression (rev2)
== Series Details == Series: drm/i915/dg2: Add support for render/media decompression (rev2) URL : https://patchwork.freedesktop.org/series/102147/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/edid: low level EDID block read refactoring etc. (rev5)
== Series Details == Series: drm/edid: low level EDID block read refactoring etc. (rev5) URL : https://patchwork.freedesktop.org/series/102329/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11482_full -> Patchwork_102329v5_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_102329v5_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_102329v5_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (13 -> 10) -- Missing(3): shard-rkl shard-dg1 shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_102329v5_full: ### IGT changes ### Possible regressions * igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-smem0: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/shard-skl2/igt@i915_pm_rpm@gem-execbuf-str...@extra-wait-smem0.html Known issues Here are the changes found in Patchwork_102329v5_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-suspend: - shard-skl: [PASS][2] -> [INCOMPLETE][3] ([i915#4547]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/shard-skl10/igt@gem_...@in-flight-suspend.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/shard-skl6/igt@gem_...@in-flight-suspend.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][4] -> [FAIL][5] ([i915#2846]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/shard-glk1/igt@gem_exec_f...@basic-deadline.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/shard-glk3/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/shard-glk9/igt@gem_exec_fair@basic-none-sh...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/shard-glk1/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/shard-kbl4/igt@gem_exec_fair@basic-p...@vecs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/shard-kbl1/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_flush@basic-batch-kernel-default-uc: - shard-snb: [PASS][10] -> [SKIP][11] ([fdo#109271]) +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/shard-snb2/igt@gem_exec_fl...@basic-batch-kernel-default-uc.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/shard-snb6/igt@gem_exec_fl...@basic-batch-kernel-default-uc.html * igt@gem_lmem_swapping@basic: - shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/shard-skl2/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-kbl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/shard-kbl3/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_pread@exhaustion: - shard-skl: NOTRUN -> [WARN][14] ([i915#2658]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/shard-skl7/igt@gem_pr...@exhaustion.html * igt@gem_render_copy@yf-tiled-to-vebox-x-tiled: - shard-kbl: NOTRUN -> [SKIP][15] ([fdo#109271]) +48 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/shard-kbl7/igt@gem_render_c...@yf-tiled-to-vebox-x-tiled.html * igt@i915_suspend@forcewake: - shard-apl: NOTRUN -> [DMESG-WARN][16] ([i915#180]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/shard-apl1/igt@i915_susp...@forcewake.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [FAIL][17] ([i915#3743]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/shard-skl5/igt@kms_big...@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3777]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/shard-skl10/igt@kms_big...@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip
[Intel-gfx] [PATCH v5 10/10] drm/msm: Implement HDCP 1.x using the new drm HDCP helpers
From: Sean Paul
This patch adds HDCP 1.x support to msm DP connectors using the new HDCP
helpers.
Cc: Stephen Boyd
Cc: Abhinav Kumar
Reviewed-by: Stephen Boyd
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-15-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-14-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-15-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20211105030434.2828845-15-s...@poorly.run
#v4
Changes in v2:
-Squash [1] into this patch with the following changes (Stephen)
-Update the sc7180 dtsi file
-Remove resource names and just use index (Stephen)
Changes in v3:
-Split out the dtsi change from v2 (Stephen)
-Fix set-but-unused warning identified by 0-day
-Fix up a couple of style nits (Stephen)
-Store HDCP key directly in dp_hdcp struct (Stephen)
-Remove wmb in HDCP key initialization, move an_seed (Stephen)
-Use FIELD_PREP for bstatus/bcaps (Stephen)
-#define read_poll_timeout values (Stephen)
-Remove unnecessary parentheses in dp_hdcp_store_ksv_fifo (Stephen)
-Add compatible string for hdcp (Stephen)
-Rename dp_hdcp_write_* functions (Abhinav)
-Add 1us delay between An reads (Abhinav)
-Delete unused dp_hdcp_read_* functions
Changes in v4:
-Rebase on Bjorn's multi-dp patchset
Changes in v5:
-Change return check of drm_hdcp_helper_initialize_dp() (Stephen)
[1]
https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-14-s...@poorly.run
---
drivers/gpu/drm/msm/Makefile| 1 +
drivers/gpu/drm/msm/dp/dp_debug.c | 46 ++-
drivers/gpu/drm/msm/dp/dp_debug.h | 6 +-
drivers/gpu/drm/msm/dp/dp_display.c | 46 ++-
drivers/gpu/drm/msm/dp/dp_display.h | 5 +
drivers/gpu/drm/msm/dp/dp_drm.c | 68 -
drivers/gpu/drm/msm/dp/dp_drm.h | 5 +
drivers/gpu/drm/msm/dp/dp_hdcp.c| 453
drivers/gpu/drm/msm/dp/dp_hdcp.h| 27 ++
drivers/gpu/drm/msm/dp/dp_parser.c | 20 +-
drivers/gpu/drm/msm/dp/dp_parser.h | 4 +
drivers/gpu/drm/msm/dp/dp_reg.h | 32 +-
drivers/gpu/drm/msm/msm_atomic.c| 15 +
13 files changed, 720 insertions(+), 8 deletions(-)
create mode 100644 drivers/gpu/drm/msm/dp/dp_hdcp.c
create mode 100644 drivers/gpu/drm/msm/dp/dp_hdcp.h
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index e9cc7d8ac301..e7b0e860c1f0 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -106,6 +106,7 @@ msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
dp/dp_ctrl.o \
dp/dp_display.o \
dp/dp_drm.o \
+ dp/dp_hdcp.o \
dp/dp_hpd.o \
dp/dp_link.o \
dp/dp_panel.o \
diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c
b/drivers/gpu/drm/msm/dp/dp_debug.c
index 2f9c943f12d5..12e65294258f 100644
--- a/drivers/gpu/drm/msm/dp/dp_debug.c
+++ b/drivers/gpu/drm/msm/dp/dp_debug.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include "dp_parser.h"
#include "dp_catalog.h"
@@ -15,6 +16,7 @@
#include "dp_ctrl.h"
#include "dp_debug.h"
#include "dp_display.h"
+#include "dp_hdcp.h"
#define DEBUG_NAME "msm_dp"
@@ -25,6 +27,7 @@ struct dp_debug_private {
struct dp_link *link;
struct dp_panel *panel;
struct drm_connector *connector;
+ struct dp_hdcp *hdcp;
struct device *dev;
struct drm_device *drm_dev;
@@ -198,6 +201,35 @@ static int dp_test_active_open(struct inode *inode,
inode->i_private);
}
+static ssize_t dp_hdcp_key_write(struct file *file, const char __user *ubuf,
+size_t len, loff_t *offp)
+{
+ char *input_buffer;
+ int ret;
+ struct dp_debug_private *debug = file->private_data;
+
+ if (len != (DRM_HDCP_KSV_LEN + DP_HDCP_NUM_KEYS * DP_HDCP_KEY_LEN))
+ return -EINVAL;
+
+ if (!debug->hdcp)
+ return -ENOENT;
+
+ input_buffer = memdup_user_nul(ubuf, len);
+ if (IS_ERR(input_buffer))
+ return PTR_ERR(input_buffer);
+
+ ret = dp_hdcp_ingest_key(debug->hdcp, input_buffer, len);
+
+ kfree(input_buffer);
+ if (ret < 0) {
+ DRM_ERROR("Could not ingest HDCP key, ret=%d\n", ret);
+ return ret;
+ }
+
+ *offp += len;
+ return len;
+}
+
static const struct file_operations test_active_fops = {
.owner = THIS_MODULE,
.open = dp_test_active_open,
@@ -207,6 +239,12 @@ static const struct file_operations test_active_fops = {
.write = dp_test_active_write
};
+static const struct file_operations dp_hdcp_key_fops = {
+ .owner = THIS_MODULE,
+ .open = simple_open,
+ .write = dp_hdcp_key_write,
+};
+
static void dp_debug_init(struct dp_debug *dp_debug, struct drm_minor *minor)
{
char path[64];
@@ -231,11 +269,16 @@ static void dp_debug_init(struct dp_debug *dp_debug,
st
[Intel-gfx] [PATCH v5 09/10] arm64: dts: qcom: sc7180: Add support for HDCP in dp-controller
From: Sean Paul
This patch adds the register ranges required for HDCP key injection and
HDCP TrustZone interaction as described in the dt-bindings for the
sc7180 dp controller. Now that these are supported, change the
compatible string to "dp-hdcp".
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-15-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-14-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-14-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20211105030434.2828845-14-s...@poorly.run
#v4
Changes in v3:
-Split off into a new patch containing just the dts change (Stephen)
-Add hdcp compatible string (Stephen)
Changes in v4:
-Rebase on Bjorn's multi-dp patchset
Changes in v5:
-Put the tz register offsets in trogdor dtsi (Rob C)
---
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 8
arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 +-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index 732e1181af48..c3559253aefc 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -815,6 +815,14 @@ &mdss_dp {
data-lanes = <0 1>;
vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>;
vdda-0p9-supply = <&vdda_usb_ss_dp_core>;
+
+ reg = <0 0x0ae9 0 0x200>,
+ <0 0x0ae90200 0 0x200>,
+ <0 0x0ae90400 0 0xc00>,
+ <0 0x0ae91000 0 0x400>,
+ <0 0x0ae91400 0 0x400>,
+ <0 0x0aed1000 0 0x175>,
+ <0 0x0aee1000 0 0x2c>;
};
&pm6150_adc {
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index e1c46b80f14a..3c3eef7a7d52 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3089,7 +3089,11 @@ mdss_dp: displayport-controller@ae9 {
compatible = "qcom,sc7180-dp";
status = "disabled";
- reg = <0 0x0ae9 0 0x1400>;
+ reg = <0 0x0ae9 0 0x200>,
+ <0 0x0ae90200 0 0x200>,
+ <0 0x0ae90400 0 0xc00>,
+ <0 0x0ae91000 0 0x400>,
+ <0 0x0ae91400 0 0x400>;
interrupt-parent = <&mdss>;
interrupts = <12>;
--
Sean Paul, Software Engineer, Google / Chromium OS
[Intel-gfx] [PATCH v5 08/10] dt-bindings: msm/dp: Add bindings for HDCP registers
From: Sean Paul This patch adds the bindings for the MSM DisplayPort HDCP registers which are required to write the HDCP key into the display controller as well as the registers to enable HDCP authentication/key exchange/encryption. We'll use a new compatible string for this since the fields are optional. Cc: Rob Herring Cc: Stephen Boyd Reviewed-by: Rob Herring Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-13-s...@poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-13-s...@poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-13-s...@poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20211105030434.2828845-13-s...@poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/2025202153.117244-1-s...@poorly.run #v4.5 Changes in v2: -Drop register range names (Stephen) -Fix yaml errors (Rob) Changes in v3: -Add new compatible string for dp-hdcp -Add descriptions to reg -Add minItems/maxItems to reg -Make reg depend on the new hdcp compatible string Changes in v4: -Rebase on Bjorn's multi-dp patchset Changes in v4.5: -Remove maxItems from reg (Rob) -Remove leading zeros in example (Rob) Changes in v5: -None --- .../devicetree/bindings/display/msm/dp-controller.yaml | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index cd05cfd76536..671d50f1f458 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -24,12 +24,15 @@ properties: - qcom,sm8350-dp reg: +minItems: 5 items: - description: ahb register block - description: aux register block - description: link register block - description: p0 register block - description: p1 register block + - description: (Optional) Registers for HDCP device key injection + - description: (Optional) Registers for HDCP TrustZone interaction interrupts: maxItems: 1 @@ -113,7 +116,9 @@ examples: <0xae90200 0x200>, <0xae90400 0xc00>, <0xae91000 0x400>, - <0xae91400 0x400>; + <0xae91400 0x400>, + <0xaed1000 0x174>, + <0xaee1000 0x2c>; interrupt-parent = <&mdss>; interrupts = <12>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, -- Sean Paul, Software Engineer, Google / Chromium OS
[Intel-gfx] [PATCH v5 07/10] drm/i915/hdcp: Use HDCP helpers for i915
From: Sean Paul
Now that all of the HDCP 1.x logic has been migrated to the central HDCP
helpers, use it in the i915 driver.
The majority of the driver code for HDCP 1.x will live in intel_hdcp.c,
however there are a few helper hooks which are connector-specific and
need to be partially or fully implemented in the intel_dp_hdcp.c or
intel_hdmi.c.
We'll leave most of the HDCP 2.x code alone since we don't have another
implementation of HDCP 2.x to use as reference for what should and
should not live in the drm helpers. The helper will call the overly
general enable/disable/is_capable HDCP 2.x callbacks and leave the
interesting stuff for the driver. Once we have another HDCP 2.x
implementation, we should do a similar migration.
Acked-by: Jani Nikula
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-8-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-8-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-8-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20211105030434.2828845-8-s...@poorly.run
#v4
Changes in v2:
-Fix mst helper function pointer reported by 0-day
Changes in v3:
-Add forward declaration for drm_atomic_state in intel_hdcp.h identified
by 0-day
Changes in v4:
-None
Changes in v5:
-None
---
drivers/gpu/drm/i915/display/intel_ddi.c | 29 +-
.../drm/i915/display/intel_display_debugfs.c | 6 +-
.../drm/i915/display/intel_display_types.h| 58 +-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 345 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 935 +++---
drivers/gpu/drm/i915/display/intel_hdcp.h | 31 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 256 ++---
8 files changed, 418 insertions(+), 1259 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index cec578efc4bd..a320c2b178e5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -29,6 +29,7 @@
#include
#include
+#include
#include "i915_drv.h"
#include "intel_audio.h"
@@ -2921,6 +2922,9 @@ static void intel_enable_ddi(struct intel_atomic_state
*state,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct intel_connector *connector =
to_intel_connector(conn_state->connector);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
if (!intel_crtc_is_bigjoiner_slave(crtc_state))
@@ -2937,12 +2941,10 @@ static void intel_enable_ddi(struct intel_atomic_state
*state,
else
intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
- /* Enable hdcp if it's desired */
- if (conn_state->content_protection ==
- DRM_MODE_CONTENT_PROTECTION_DESIRED)
- intel_hdcp_enable(to_intel_connector(conn_state->connector),
- crtc_state,
- (u8)conn_state->hdcp_content_type);
+ if (connector->hdcp_helper_data)
+ drm_hdcp_helper_atomic_commit(connector->hdcp_helper_data,
+ &state->base,
+ &dig_port->hdcp_mutex);
}
static void intel_disable_ddi_dp(struct intel_atomic_state *state,
@@ -2988,7 +2990,13 @@ static void intel_disable_ddi(struct intel_atomic_state
*state,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state *old_conn_state)
{
- intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
+ struct intel_connector *connector =
to_intel_connector(old_conn_state->connector);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+ if (connector->hdcp_helper_data)
+ drm_hdcp_helper_atomic_commit(connector->hdcp_helper_data,
+ &state->base,
+ &dig_port->hdcp_mutex);
if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
@@ -3016,13 +3024,18 @@ void intel_ddi_update_pipe(struct intel_atomic_state
*state,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct intel_connector *connector =
to_intel_connector(conn_state->connector);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
!intel_encoder_is_mst(encoder))
intel_ddi_update_pi
[Intel-gfx] [PATCH v5 06/10] drm/i915/hdcp: Retain hdcp_capable return codes
From: Sean Paul
The shim functions return error codes, but they are discarded in
intel_hdcp.c. This patch plumbs the return codes through so they are
properly handled.
Acked-by: Jani Nikula
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-7-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-7-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-7-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20211105030434.2828845-7-s...@poorly.run
#v4
Changes in v2:
-None
Changes in v3:
-None
Changes in v4:
-None
Changes in v5:
-None
---
.../drm/i915/display/intel_display_debugfs.c | 9 +++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 51 ++-
drivers/gpu/drm/i915/display/intel_hdcp.h | 4 +-
3 files changed, 37 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 452d773fd4e3..f18b4bec4dd4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -489,6 +489,7 @@ static void intel_panel_info(struct seq_file *m,
static void intel_hdcp_info(struct seq_file *m,
struct intel_connector *intel_connector)
{
+ int ret;
bool hdcp_cap, hdcp2_cap;
if (!intel_connector->hdcp.shim) {
@@ -496,8 +497,12 @@ static void intel_hdcp_info(struct seq_file *m,
goto out;
}
- hdcp_cap = intel_hdcp_capable(intel_connector);
- hdcp2_cap = intel_hdcp2_capable(intel_connector);
+ ret = intel_hdcp_capable(intel_connector, &hdcp_cap);
+ if (ret)
+ hdcp_cap = false;
+ ret = intel_hdcp2_capable(intel_connector, &hdcp2_cap);
+ if (ret)
+ hdcp2_cap = false;
if (hdcp_cap)
seq_puts(m, "HDCP1.4 ");
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 6bb5a3971ed9..771e94fa8dff 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -154,50 +154,49 @@ int intel_hdcp_read_valid_bksv(struct intel_digital_port
*dig_port,
}
/* Is HDCP1.4 capable on Platform and Sink */
-bool intel_hdcp_capable(struct intel_connector *connector)
+int intel_hdcp_capable(struct intel_connector *connector, bool *capable)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
const struct intel_hdcp_shim *shim = connector->hdcp.shim;
- bool capable = false;
u8 bksv[5];
+ *capable = false;
+
if (!shim)
- return capable;
+ return 0;
- if (shim->hdcp_capable) {
- shim->hdcp_capable(dig_port, &capable);
- } else {
- if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv))
- capable = true;
- }
+ if (shim->hdcp_capable)
+ return shim->hdcp_capable(dig_port, capable);
+
+ if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv))
+ *capable = true;
- return capable;
+ return 0;
}
/* Is HDCP2.2 capable on Platform and Sink */
-bool intel_hdcp2_capable(struct intel_connector *connector)
+int intel_hdcp2_capable(struct intel_connector *connector, bool *capable)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
- bool capable = false;
+
+ *capable = false;
/* I915 support for HDCP2.2 */
if (!hdcp->hdcp2_supported)
- return false;
+ return 0;
/* MEI interface is solid */
mutex_lock(&dev_priv->hdcp_comp_mutex);
if (!dev_priv->hdcp_comp_added || !dev_priv->hdcp_master) {
mutex_unlock(&dev_priv->hdcp_comp_mutex);
- return false;
+ return 0;
}
mutex_unlock(&dev_priv->hdcp_comp_mutex);
/* Sink's capability for HDCP2.2 */
- hdcp->shim->hdcp_2_2_capable(dig_port, &capable);
-
- return capable;
+ return hdcp->shim->hdcp_2_2_capable(dig_port, capable);
}
static bool intel_hdcp_in_use(struct drm_i915_private *dev_priv,
@@ -2332,6 +2331,7 @@ int intel_hdcp_enable(struct intel_connector *connector,
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct intel_hdcp *hdcp = &connector->hdcp;
unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS;
+ bool capable;
int ret = -EINVAL;
if (!hdcp->shim)
@@ -2350,21 +2350,27 @@ int intel_hdcp_enable(struct intel_connector *connector,
* Considering that HDCP2.2 is more secure than HDCP1.4, If
[Intel-gfx] [PATCH v5 05/10] drm/i915/hdcp: Consolidate HDCP setup/state cache
From: Sean Paul
Stick all of the setup for HDCP into a dedicated function. No functional
change, but this will facilitate moving HDCP logic into helpers.
Acked-by: Jani Nikula
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-6-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-6-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-6-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20211105030434.2828845-6-s...@poorly.run
#v4
Changes in v2:
-None
Changes in v3:
-None
Changes in v4:
-None
Changes in v5:
-None
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 52 +++
1 file changed, 35 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 861c550b5bd6..6bb5a3971ed9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2167,6 +2167,37 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum
transcoder cpu_transcoder)
}
}
+static int
+_intel_hdcp_setup(struct intel_connector *connector,
+ const struct intel_crtc_state *pipe_config, u8 content_type)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ int ret = 0;
+
+ if (!connector->encoder) {
+ drm_err(&dev_priv->drm, "[%s:%d] encoder is not initialized\n",
+ connector->base.name, connector->base.base.id);
+ return -ENODEV;
+ }
+
+ hdcp->content_type = content_type;
+
+ if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
+ hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
+ hdcp->stream_transcoder = pipe_config->cpu_transcoder;
+ } else {
+ hdcp->cpu_transcoder = pipe_config->cpu_transcoder;
+ hdcp->stream_transcoder = INVALID_TRANSCODER;
+ }
+
+ if (DISPLAY_VER(dev_priv) >= 12)
+ dig_port->hdcp_port_data.fw_tc =
intel_get_mei_fw_tc(hdcp->cpu_transcoder);
+
+ return ret;
+}
+
static int initialize_hdcp_port_data(struct intel_connector *connector,
struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
@@ -2306,28 +2337,14 @@ int intel_hdcp_enable(struct intel_connector *connector,
if (!hdcp->shim)
return -ENOENT;
- if (!connector->encoder) {
- drm_err(&dev_priv->drm, "[%s:%d] encoder is not initialized\n",
- connector->base.name, connector->base.base.id);
- return -ENODEV;
- }
-
mutex_lock(&hdcp->mutex);
mutex_lock(&dig_port->hdcp_mutex);
drm_WARN_ON(&dev_priv->drm,
hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
- hdcp->content_type = content_type;
-
- if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
- hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
- hdcp->stream_transcoder = pipe_config->cpu_transcoder;
- } else {
- hdcp->cpu_transcoder = pipe_config->cpu_transcoder;
- hdcp->stream_transcoder = INVALID_TRANSCODER;
- }
- if (DISPLAY_VER(dev_priv) >= 12)
- dig_port->hdcp_port_data.fw_tc =
intel_get_mei_fw_tc(hdcp->cpu_transcoder);
+ ret = _intel_hdcp_setup(connector, pipe_config, content_type);
+ if (ret)
+ goto out;
/*
* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
@@ -2355,6 +2372,7 @@ int intel_hdcp_enable(struct intel_connector *connector,
true);
}
+out:
mutex_unlock(&dig_port->hdcp_mutex);
mutex_unlock(&hdcp->mutex);
return ret;
--
Sean Paul, Software Engineer, Google / Chromium OS
[Intel-gfx] [PATCH v5 04/10] drm/hdcp: Expand HDCP helper library for enable/disable/check
From: Sean Paul
This patch expands upon the HDCP helper library to manage HDCP
enable, disable, and check.
Previous to this patch, the majority of the state management and sink
interaction is tucked inside the Intel driver with the understanding
that once a new platform supported HDCP we could make good decisions
about what should be centralized. With the addition of HDCP support
for Qualcomm, it's time to migrate the protocol-specific bits of HDCP
authentication, key exchange, and link checks to the HDCP helper.
In terms of functionality, this migration is 1:1 with the Intel driver,
however things are laid out a bit differently than with intel_hdcp.c,
which is why this is a separate patch from the i915 transition to the
helper. On i915, the shim vtable is used to account for HDMI vs. DP
vs. DP-MST differences whereas the helper library uses a LUT to
account for the register offsets and a remote read function to route
the messages. On i915, storing the sink information in the source is
done inline whereas now we use the new drm_hdcp_helper_funcs vtable
to store and fetch information to/from source hw. Finally, instead of
calling enable/disable directly from the driver, we'll leave that
decision to the helper and by calling drm_hdcp_helper_atomic_commit()
from the driver. All told, this will centralize the protocol and state
handling in the helper, ensuring we collect all of our bugs^Wlogic
in one place.
Cc: Abhinav Kumar
Acked-by: Jani Nikula
Reviewed-by: Abhinav Kumar
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-5-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-5-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-5-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20211105030434.2828845-5-s...@poorly.run
#v4
Changes in v2:
-Fixed set-but-unused variable identified by 0-day
Changes in v3:
-Fixed uninitialized variable warning identified by 0-day
Changes in v4:
-None
Changes in v5:
-None
---
drivers/gpu/drm/drm_hdcp.c | 1103
include/drm/drm_hdcp.h | 191 +++
2 files changed, 1294 insertions(+)
diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
index 8c851d40cd45..3e550c892751 100644
--- a/drivers/gpu/drm/drm_hdcp.c
+++ b/drivers/gpu/drm/drm_hdcp.c
@@ -6,15 +6,20 @@
* Ramalingam C
*/
+#include
#include
#include
#include
+#include
+#include
#include
#include
#include
+#include
#include
#include
+#include
#include
#include
#include
@@ -513,3 +518,1101 @@ bool drm_hdcp_atomic_check(struct drm_connector
*connector,
return old_hdcp != new_hdcp;
}
EXPORT_SYMBOL(drm_hdcp_atomic_check);
+
+struct drm_hdcp_helper_data {
+ struct mutex mutex;
+ struct mutex *driver_mutex;
+
+ struct drm_connector *connector;
+ const struct drm_hdcp_helper_funcs *funcs;
+
+ u64 value;
+ unsigned int enabled_type;
+
+ struct delayed_work check_work;
+ struct work_struct prop_work;
+
+ struct drm_dp_aux *aux;
+ const struct drm_hdcp_hdcp1_receiver_reg_lut *hdcp1_lut;
+};
+
+struct drm_hdcp_hdcp1_receiver_reg_lut {
+ unsigned int bksv;
+ unsigned int ri;
+ unsigned int aksv;
+ unsigned int an;
+ unsigned int ainfo;
+ unsigned int v[5];
+ unsigned int bcaps;
+ unsigned int bcaps_mask_repeater_present;
+ unsigned int bstatus;
+};
+
+static const struct drm_hdcp_hdcp1_receiver_reg_lut drm_hdcp_hdcp1_ddc_lut = {
+ .bksv = DRM_HDCP_DDC_BKSV,
+ .ri = DRM_HDCP_DDC_RI_PRIME,
+ .aksv = DRM_HDCP_DDC_AKSV,
+ .an = DRM_HDCP_DDC_AN,
+ .ainfo = DRM_HDCP_DDC_AINFO,
+ .v = { DRM_HDCP_DDC_V_PRIME(0), DRM_HDCP_DDC_V_PRIME(1),
+ DRM_HDCP_DDC_V_PRIME(2), DRM_HDCP_DDC_V_PRIME(3),
+ DRM_HDCP_DDC_V_PRIME(4) },
+ .bcaps = DRM_HDCP_DDC_BCAPS,
+ .bcaps_mask_repeater_present = DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT,
+ .bstatus = DRM_HDCP_DDC_BSTATUS,
+};
+
+static const struct drm_hdcp_hdcp1_receiver_reg_lut drm_hdcp_hdcp1_dpcd_lut = {
+ .bksv = DP_AUX_HDCP_BKSV,
+ .ri = DP_AUX_HDCP_RI_PRIME,
+ .aksv = DP_AUX_HDCP_AKSV,
+ .an = DP_AUX_HDCP_AN,
+ .ainfo = DP_AUX_HDCP_AINFO,
+ .v = { DP_AUX_HDCP_V_PRIME(0), DP_AUX_HDCP_V_PRIME(1),
+ DP_AUX_HDCP_V_PRIME(2), DP_AUX_HDCP_V_PRIME(3),
+ DP_AUX_HDCP_V_PRIME(4) },
+ .bcaps = DP_AUX_HDCP_BCAPS,
+ .bcaps_mask_repeater_present = DP_BCAPS_REPEATER_PRESENT,
+
+ /*
+* For some reason the HDMI and DP HDCP specs call this register
+* definition by different names. In the HDMI spec, it's called BSTATUS,
+* but in DP it's called BINFO.
+*/
+ .bstatus = DP_AUX_HDCP_BINFO,
+};
+
+static int drm_hdcp_remote_ddc_read(struct i2c_adapter *i2c,
+
[Intel-gfx] [PATCH v5 03/10] drm/hdcp: Update property value on content type and user changes
From: Sean Paul
This patch updates the connector's property value in 2 cases which were
previously missed:
1- Content type changes. The value should revert back to DESIRED from
ENABLED in case the driver must re-authenticate the link due to the
new content type.
2- Userspace sets value to DESIRED while ENABLED. In this case, the
value should be reset immediately to ENABLED since the link is
actively being encrypted.
To accommodate these changes, I've split up the conditionals to make
things a bit more clear (as much as one can with this mess of state).
Acked-by: Jani Nikula
Reviewed-by: Abhinav Kumar
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-4-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-4-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-4-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20211105030434.2828845-4-s...@poorly.run
#v4
Changes in v2:
-None
Changes in v3:
-Fixed indentation issue identified by 0-day
Changes in v4:
-None
Changes in v5:
-None
---
drivers/gpu/drm/drm_hdcp.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
index dd8fa91c51d6..8c851d40cd45 100644
--- a/drivers/gpu/drm/drm_hdcp.c
+++ b/drivers/gpu/drm/drm_hdcp.c
@@ -487,21 +487,29 @@ bool drm_hdcp_atomic_check(struct drm_connector
*connector,
return true;
/*
-* Nothing to do if content type is unchanged and one of:
-* - state didn't change
+* Content type changes require an HDCP disable/enable cycle.
+*/
+ if (new_conn_state->hdcp_content_type !=
old_conn_state->hdcp_content_type) {
+ new_conn_state->content_protection =
+ DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ return true;
+ }
+
+ /*
+* Ignore meaningless state changes:
* - HDCP was activated since the last commit
-* - attempting to set to desired while already enabled
+* - Attempting to set to desired while already enabled
*/
- if (old_hdcp == new_hdcp ||
- (old_hdcp == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
+ if ((old_hdcp == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
new_hdcp == DRM_MODE_CONTENT_PROTECTION_ENABLED) ||
(old_hdcp == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
new_hdcp == DRM_MODE_CONTENT_PROTECTION_DESIRED)) {
- if (old_conn_state->hdcp_content_type ==
- new_conn_state->hdcp_content_type)
- return false;
+ new_conn_state->content_protection =
+ DRM_MODE_CONTENT_PROTECTION_ENABLED;
+ return false;
}
- return true;
+ /* Finally, if state changes, we need action */
+ return old_hdcp != new_hdcp;
}
EXPORT_SYMBOL(drm_hdcp_atomic_check);
--
Sean Paul, Software Engineer, Google / Chromium OS
[Intel-gfx] [PATCH v5 02/10] drm/hdcp: Avoid changing crtc state in hdcp atomic check
From: Sean Paul
Instead of forcing a modeset in the hdcp atomic check, simply return
true if the content protection value is changing and let the driver
decide whether a modeset is required or not.
Acked-by: Jani Nikula
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-3-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-3-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-3-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20211105030434.2828845-3-s...@poorly.run
#v4
Changes in v2:
-None
Changes in v3:
-None
Changes in v4:
-None
Changes in v5:
-None
---
drivers/gpu/drm/drm_hdcp.c | 33 +++--
drivers/gpu/drm/i915/display/intel_atomic.c | 5 ++--
include/drm/drm_hdcp.h | 2 +-
3 files changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
index 522326b03e66..dd8fa91c51d6 100644
--- a/drivers/gpu/drm/drm_hdcp.c
+++ b/drivers/gpu/drm/drm_hdcp.c
@@ -430,11 +430,14 @@ EXPORT_SYMBOL(drm_hdcp_update_content_protection);
* @connector: drm_connector on which content protection state needs an update
*
* This function can be used by display drivers to perform an atomic check on
the
- * hdcp state elements. If hdcp state has changed, this function will set
- * mode_changed on the crtc driving the connector so it can update its hardware
- * to match the hdcp state.
+ * hdcp state elements. If hdcp state has changed in a manner which requires
the
+ * driver to enable or disable content protection, this function will return
+ * true.
+ *
+ * Returns:
+ * true if the driver must enable/disable hdcp, false otherwise
*/
-void drm_hdcp_atomic_check(struct drm_connector *connector,
+bool drm_hdcp_atomic_check(struct drm_connector *connector,
struct drm_atomic_state *state)
{
struct drm_connector_state *new_conn_state, *old_conn_state;
@@ -452,10 +455,12 @@ void drm_hdcp_atomic_check(struct drm_connector
*connector,
* If the connector is being disabled with CP enabled, mark it
* desired so it's re-enabled when the connector is brought back
*/
- if (old_hdcp == DRM_MODE_CONTENT_PROTECTION_ENABLED)
+ if (old_hdcp == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
new_conn_state->content_protection =
DRM_MODE_CONTENT_PROTECTION_DESIRED;
- return;
+ return true;
+ }
+ return false;
}
new_crtc_state = drm_atomic_get_new_crtc_state(state,
@@ -467,9 +472,19 @@ void drm_hdcp_atomic_check(struct drm_connector *connector,
*/
if (drm_atomic_crtc_needs_modeset(new_crtc_state) &&
(old_hdcp == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
-new_hdcp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED))
+new_hdcp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) {
new_conn_state->content_protection =
DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ return true;
+ }
+
+ /*
+* Coming back from disable or changing CRTC with DESIRED state requires
+* that the driver try CP enable.
+*/
+ if (new_hdcp == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
+ new_conn_state->crtc != old_conn_state->crtc)
+ return true;
/*
* Nothing to do if content type is unchanged and one of:
@@ -484,9 +499,9 @@ void drm_hdcp_atomic_check(struct drm_connector *connector,
new_hdcp == DRM_MODE_CONTENT_PROTECTION_DESIRED)) {
if (old_conn_state->hdcp_content_type ==
new_conn_state->hdcp_content_type)
- return;
+ return false;
}
- new_crtc_state->mode_changed = true;
+ return true;
}
EXPORT_SYMBOL(drm_hdcp_atomic_check);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index b301a4d1017e..6d24b3450399 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -124,8 +124,6 @@ int intel_digital_connector_atomic_check(struct
drm_connector *conn,
to_intel_digital_connector_state(old_state);
struct drm_crtc_state *crtc_state;
- drm_hdcp_atomic_check(conn, state);
-
if (!new_state->crtc)
return 0;
@@ -142,7 +140,8 @@ int intel_digital_connector_atomic_check(struct
drm_connector *conn,
new_conn_state->base.content_type !=
old_conn_state->base.content_type ||
new_conn_state->base.scaling_mode !=
old_conn_state->base.scaling_mode ||
new_conn_state->base.privacy_screen_sw_state !=
old
[Intel-gfx] [PATCH v5 01/10] drm/hdcp: Add drm_hdcp_atomic_check()
From: Sean Paul
This patch moves the hdcp atomic check from i915 to drm_hdcp so other
drivers can use it. No functional changes, just cleaned up some of the
code when moving it over.
Acked-by: Jani Nikula
Acked-by: Jani Nikula
Reviewed-by: Abhinav Kumar
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-2-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-2-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-2-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20211105030434.2828845-2-s...@poorly.run
#v4
Changes in v2:
-None
Changes in v3:
-None
Changes in v4:
-None
Changes in v5:
-None
---
drivers/gpu/drm/drm_hdcp.c | 71 -
drivers/gpu/drm/i915/display/intel_atomic.c | 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 47 --
drivers/gpu/drm/i915/display/intel_hdcp.h | 3 -
include/drm/drm_hdcp.h | 3 +
5 files changed, 75 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
index ca9b8f697202..522326b03e66 100644
--- a/drivers/gpu/drm/drm_hdcp.c
+++ b/drivers/gpu/drm/drm_hdcp.c
@@ -13,13 +13,14 @@
#include
#include
+#include
+#include
#include
#include
#include
#include
#include
#include
-#include
#include "drm_internal.h"
@@ -421,3 +422,71 @@ void drm_hdcp_update_content_protection(struct
drm_connector *connector,
dev->mode_config.content_protection_property);
}
EXPORT_SYMBOL(drm_hdcp_update_content_protection);
+
+/**
+ * drm_hdcp_atomic_check - Helper for drivers to call during
connector->atomic_check
+ *
+ * @state: pointer to the atomic state being checked
+ * @connector: drm_connector on which content protection state needs an update
+ *
+ * This function can be used by display drivers to perform an atomic check on
the
+ * hdcp state elements. If hdcp state has changed, this function will set
+ * mode_changed on the crtc driving the connector so it can update its hardware
+ * to match the hdcp state.
+ */
+void drm_hdcp_atomic_check(struct drm_connector *connector,
+ struct drm_atomic_state *state)
+{
+ struct drm_connector_state *new_conn_state, *old_conn_state;
+ struct drm_crtc_state *new_crtc_state;
+ u64 old_hdcp, new_hdcp;
+
+ old_conn_state = drm_atomic_get_old_connector_state(state, connector);
+ old_hdcp = old_conn_state->content_protection;
+
+ new_conn_state = drm_atomic_get_new_connector_state(state, connector);
+ new_hdcp = new_conn_state->content_protection;
+
+ if (!new_conn_state->crtc) {
+ /*
+* If the connector is being disabled with CP enabled, mark it
+* desired so it's re-enabled when the connector is brought back
+*/
+ if (old_hdcp == DRM_MODE_CONTENT_PROTECTION_ENABLED)
+ new_conn_state->content_protection =
+ DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ return;
+ }
+
+ new_crtc_state = drm_atomic_get_new_crtc_state(state,
+ new_conn_state->crtc);
+ /*
+ * Fix the HDCP uapi content protection state in case of modeset.
+ * FIXME: As per HDCP content protection property uapi doc, an uevent()
+ * need to be sent if there is transition from ENABLED->DESIRED.
+ */
+ if (drm_atomic_crtc_needs_modeset(new_crtc_state) &&
+ (old_hdcp == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
+new_hdcp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED))
+ new_conn_state->content_protection =
+ DRM_MODE_CONTENT_PROTECTION_DESIRED;
+
+ /*
+* Nothing to do if content type is unchanged and one of:
+* - state didn't change
+* - HDCP was activated since the last commit
+* - attempting to set to desired while already enabled
+*/
+ if (old_hdcp == new_hdcp ||
+ (old_hdcp == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
+new_hdcp == DRM_MODE_CONTENT_PROTECTION_ENABLED) ||
+ (old_hdcp == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
+new_hdcp == DRM_MODE_CONTENT_PROTECTION_DESIRED)) {
+ if (old_conn_state->hdcp_content_type ==
+ new_conn_state->hdcp_content_type)
+ return;
+ }
+
+ new_crtc_state->mode_changed = true;
+}
+EXPORT_SYMBOL(drm_hdcp_atomic_check);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 40da7910f845..b301a4d1017e 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -32,6 +32,7 @@
#include
#include
#include
+#in
[Intel-gfx] [PATCH v5 00/10] drm/hdcp: Pull HDCP auth/exchange/check into helpers
From: Sean Paul Rebased set from November. Fixed a nit from Stephen in the msm patch and moved hdcp registers into the trogdor dtsi file to avoid differences with sc7180-based windows devices. The set is 4 patches lighter since some of the changes were accepted into msm. I'm still waiting for Intel review of the first 7 patches. Rodrigo/Jani, would you please provide your input so we can move forward with this set? Thanks, Sean Link: https://patchwork.freedesktop.org/series/94623/ #v1 Link: https://patchwork.freedesktop.org/series/94713/ #v2 Link: https://patchwork.freedesktop.org/series/94712/ #v3 Link: https://patchwork.freedesktop.org/series/94712/ #v4 Sean Paul (10): drm/hdcp: Add drm_hdcp_atomic_check() drm/hdcp: Avoid changing crtc state in hdcp atomic check drm/hdcp: Update property value on content type and user changes drm/hdcp: Expand HDCP helper library for enable/disable/check drm/i915/hdcp: Consolidate HDCP setup/state cache drm/i915/hdcp: Retain hdcp_capable return codes drm/i915/hdcp: Use HDCP helpers for i915 dt-bindings: msm/dp: Add bindings for HDCP registers arm64: dts: qcom: sc7180: Add support for HDCP in dp-controller drm/msm: Implement HDCP 1.x using the new drm HDCP helpers .../bindings/display/msm/dp-controller.yaml |7 +- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi |8 + arch/arm64/boot/dts/qcom/sc7180.dtsi |6 +- drivers/gpu/drm/drm_hdcp.c| 1197 - drivers/gpu/drm/i915/display/intel_atomic.c |7 +- drivers/gpu/drm/i915/display/intel_ddi.c | 29 +- .../drm/i915/display/intel_display_debugfs.c | 11 +- .../drm/i915/display/intel_display_types.h| 58 +- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 345 ++--- drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 1011 +++--- drivers/gpu/drm/i915/display/intel_hdcp.h | 36 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 256 ++-- drivers/gpu/drm/msm/Makefile |1 + drivers/gpu/drm/msm/dp/dp_debug.c | 46 +- drivers/gpu/drm/msm/dp/dp_debug.h |6 +- drivers/gpu/drm/msm/dp/dp_display.c | 46 +- drivers/gpu/drm/msm/dp/dp_display.h |5 + drivers/gpu/drm/msm/dp/dp_drm.c | 68 +- drivers/gpu/drm/msm/dp/dp_drm.h |5 + drivers/gpu/drm/msm/dp/dp_hdcp.c | 453 +++ drivers/gpu/drm/msm/dp/dp_hdcp.h | 27 + drivers/gpu/drm/msm/dp/dp_parser.c| 20 +- drivers/gpu/drm/msm/dp/dp_parser.h|4 + drivers/gpu/drm/msm/dp/dp_reg.h | 32 +- drivers/gpu/drm/msm/msm_atomic.c | 15 + include/drm/drm_hdcp.h| 194 +++ 27 files changed, 2582 insertions(+), 1328 deletions(-) create mode 100644 drivers/gpu/drm/msm/dp/dp_hdcp.c create mode 100644 drivers/gpu/drm/msm/dp/dp_hdcp.h -- Sean Paul, Software Engineer, Google / Chromium OS
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,1/2] drm/dp: Factor out a function to probe a DPCD address (rev3)
== Series Details == Series: series starting with [v3,1/2] drm/dp: Factor out a function to probe a DPCD address (rev3) URL : https://patchwork.freedesktop.org/series/102428/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11482_full -> Patchwork_102428v3_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_102428v3_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_102428v3_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (13 -> 10) -- Missing(3): shard-rkl shard-dg1 shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_102428v3_full: ### IGT changes ### Possible regressions * igt@i915_pm_rpm@system-suspend-modeset: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/shard-skl10/igt@i915_pm_...@system-suspend-modeset.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/shard-skl6/igt@i915_pm_...@system-suspend-modeset.html Known issues Here are the changes found in Patchwork_102428v3_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_sseu@invalid-args: - shard-apl: NOTRUN -> [SKIP][3] ([fdo#109271]) +119 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/shard-apl1/igt@gem_ctx_s...@invalid-args.html * igt@gem_exec_balancer@parallel-contexts: - shard-kbl: NOTRUN -> [DMESG-WARN][4] ([i915#5076] / [i915#5614]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/shard-kbl3/igt@gem_exec_balan...@parallel-contexts.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2846]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/shard-glk1/igt@gem_exec_f...@basic-deadline.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/shard-glk2/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none@vcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/shard-glk4/igt@gem_exec_fair@basic-n...@vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/shard-glk1/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/shard-kbl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_flush@basic-batch-kernel-default-uc: - shard-snb: [PASS][11] -> [SKIP][12] ([fdo#109271]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/shard-snb2/igt@gem_exec_fl...@basic-batch-kernel-default-uc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/shard-snb6/igt@gem_exec_fl...@basic-batch-kernel-default-uc.html * igt@gem_exec_params@rsvd2-dirt: - shard-iclb: NOTRUN -> [SKIP][13] ([fdo#109283]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/shard-iclb6/igt@gem_exec_par...@rsvd2-dirt.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][14] -> [SKIP][15] ([i915#2190]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/shard-tglb8/igt@gem_huc_c...@huc-copy.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/shard-skl1/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_userptr_blits@input-checking: - shard-iclb: NOTRUN -> [DMESG-WARN][17] ([i915#4991]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/shard-iclb6/igt@gem_userptr_bl...@input-checking.html * igt@i915_suspend@forcewake: - shard-apl: NOTRUN -> [DMESG-WARN][18] ([i915#180]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/shard-apl8/igt@i915_susp...@forcewake.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [FAIL][19] ([i915#3743]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/shard-skl4/igt@kms_big...@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html * igt@kms_big_fb@x-tiled-ma
Re: [Intel-gfx] [PATCH] drm/ttm: stop passing NULL fence in ttm_bo_move_sync_cleanup
Am 11.04.22 um 10:56 schrieb Matthew Auld:
If we hit the sync case, like when skipping clearing for kernel internal
objects, or when falling back to cpu clearing, like in i915, we end up
trying to add a NULL fence, but with some recent changes in this area
this now just results in NULL deref in dma_resv_add_fence:
<1>[5.466383] BUG: kernel NULL pointer dereference, address:
0008
<1>[5.466384] #PF: supervisor read access in kernel mode
<1>[5.466385] #PF: error_code(0x) - not-present page
<6>[5.466386] PGD 0 P4D 0
<4>[5.466387] Oops: [#1] PREEMPT SMP NOPTI
<4>[5.466389] CPU: 5 PID: 267 Comm: modprobe Not tainted
5.18.0-rc2-CI-CI_DRM_11481+ #1
<4>[5.466391] RIP: 0010:dma_resv_add_fence+0x63/0x260
<4>[5.466395] Code: 38 85 c0 0f 84 df 01 00 00 0f 88 e8 01 00 00 83 c0 01 0f 88
df 01 00 00 8b 05 35 89 10 01 49 8d 5e 68 85 c0 0f 85 45 01 00 00 <48> 8b 45 08 48 3d
c0 a5 0a 82 0f 84 5c 01 00 00 48 3d 60 a5 0a 82
<4>[5.466396] RSP: 0018:c9e974f8 EFLAGS: 00010202
<4>[5.466397] RAX: 0001 RBX: 888123e88b28 RCX:
<4>[5.466398] RDX: 0001 RSI: 822e4f50 RDI:
8233f087
<4>[5.466399] RBP: R08: 8881313dbc80 R09:
0001
<4>[5.466399] R10: 0001 R11: da354294 R12:
<4>[5.466400] R13: 88810927dc58 R14: 888123e88ac0 R15:
88810a88d600
<4>[5.466401] FS: 7f5fa1193540() GS:88845d88()
knlGS:
<4>[5.466402] CS: 0010 DS: ES: CR0: 80050033
<4>[5.466402] CR2: 0008 CR3: 000106dd6003 CR4:
003706e0
<4>[5.466403] DR0: DR1: DR2:
<4>[5.466404] DR3: DR6: fffe0ff0 DR7:
0400
<4>[5.466404] Call Trace:
<4>[5.466405]
<4>[5.466406] ttm_bo_move_accel_cleanup+0x62/0x270 [ttm]
<4>[5.466411] ? i915_rsgt_from_buddy_resource+0x185/0x1e0 [i915]
<4>[5.466529] i915_ttm_move+0xfd/0x430 [i915]
<4>[5.466833] ? dma_resv_reserve_fences+0x4e/0x320
<4>[5.466836] ? ttm_bo_add_move_fence.constprop.20+0xf7/0x140 [ttm]
<4>[5.466841] ttm_bo_handle_move_mem+0xa1/0x140 [ttm]
<4>[5.466845] ttm_bo_validate+0xee/0x160 [ttm]
<4>[5.466849] __i915_ttm_get_pages+0x4f/0x210 [i915]
<4>[5.466976] i915_ttm_get_pages+0xad/0x140 [i915]
<4>[5.467094] i915_gem_object_get_pages+0x32/0xf0 [i915]
<4>[5.467210] __i915_gem_object_get_pages+0x89/0xa0 [i915]
<4>[5.467323] i915_vma_get_pages+0x114/0x1d0 [i915]
<4>[5.467446] i915_vma_pin_ww+0xd3/0xa90 [i915]
<4>[5.467570] i915_vma_pin.constprop.10+0x119/0x1b0 [i915]
<4>[5.467700] ? __mutex_unlock_slowpath+0x3e/0x2b0
<4>[5.467704] intel_alloc_initial_plane_obj.isra.6+0x1a9/0x390 [i915]
<4>[5.467833] intel_crtc_initial_plane_config+0x83/0x340 [i915]
In the ttm_bo_move_sync_cleanup() case it seems we only really care
about calling ttm_bo_wait_free_node(), so let's instead just call that
directly.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Christian König
Cc: Lucas De Marchi
Cc: Nirmoy Das
Tested-by: Thomas Zimmermann
with bochs on ppc64le.
---
drivers/gpu/drm/ttm/ttm_bo_util.c | 15 +++
include/drm/ttm/ttm_bo_driver.h | 11 +++
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index bc5190340b9c..1cbfb00c1d65 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -572,6 +572,21 @@ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
}
EXPORT_SYMBOL(ttm_bo_move_accel_cleanup);
+void ttm_bo_move_sync_cleanup(struct ttm_buffer_object *bo,
+ struct ttm_resource *new_mem)
+{
+ struct ttm_device *bdev = bo->bdev;
+ struct ttm_resource_manager *man = ttm_manager_type(bdev,
new_mem->mem_type);
+ int ret;
+
+ ret = ttm_bo_wait_free_node(bo, man->use_tt);
+ if (WARN_ON(ret))
+ return;
+
+ ttm_bo_assign_mem(bo, new_mem);
+}
+EXPORT_SYMBOL(ttm_bo_move_sync_cleanup);
+
/**
* ttm_bo_pipeline_gutting - purge the contents of a bo
* @bo: The buffer object
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index 059a595e14e5..897b88f0bd59 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -245,7 +245,7 @@ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
struct ttm_resource *new_mem);
/**
- * ttm_bo_move_accel_cleanup.
+ * ttm_bo_move_sync_cleanup.
*
* @bo: A pointer to a struct ttm_buffer_object.
* @new_mem: struct ttm_resource indicating where to move.
@@ -253,13 +253,8 @@ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
* Special case of ttm_bo_move_acce
[Intel-gfx] [PATCH 5/5] drm/i915: stolen memory use ttm backend
refactor stolen memory region to use ttm.
this necessitates using ttm resources to track reserved stolen regions
instead of drm_mm_nodes.
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/display/intel_fbc.c | 78 ++--
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 -
drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 405 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.h| 21 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 7 +
drivers/gpu/drm/i915/gt/intel_rc6.c | 4 +-
drivers/gpu/drm/i915/gt/selftest_reset.c | 16 +-
drivers/gpu/drm/i915/i915_debugfs.c | 7 +-
drivers/gpu/drm/i915/i915_drv.h | 5 -
drivers/gpu/drm/i915/intel_region_ttm.c | 36 +-
drivers/gpu/drm/i915/intel_region_ttm.h | 8 +-
drivers/gpu/drm/i915/selftests/mock_region.c | 3 +-
12 files changed, 232 insertions(+), 360 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index b653f3ba7c66..dbad1b6471b8 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -38,6 +38,7 @@
* forcibly disable it to allow proper screen updates.
*/
+#include "gem/i915_gem_stolen.h"
#include
#include
@@ -51,6 +52,7 @@
#include "intel_display_types.h"
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
+#include "gem/i915_gem_region.h"
#define for_each_fbc_id(__dev_priv, __fbc_id) \
for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS;
(__fbc_id)++) \
@@ -93,8 +95,8 @@ struct intel_fbc {
unsigned int possible_framebuffer_bits;
unsigned int busy_bits;
- struct drm_mm_node compressed_fb;
- struct drm_mm_node compressed_llb;
+ struct ttm_resource *compressed_fb;
+ struct ttm_resource *compressed_llb;
enum intel_fbc_id id;
@@ -332,16 +334,20 @@ static void i8xx_fbc_nuke(struct intel_fbc *fbc)
static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
{
struct drm_i915_private *i915 = fbc->i915;
+ u64 fb_offset = i915_gem_stolen_reserve_offset(fbc->compressed_fb);
+ u64 llb_offset = i915_gem_stolen_reserve_offset(fbc->compressed_llb);
+ GEM_BUG_ON(fb_offset == I915_BO_INVALID_OFFSET);
+ GEM_BUG_ON(llb_offset == I915_BO_INVALID_OFFSET);
GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start,
-fbc->compressed_fb.start, U32_MAX));
+fb_offset, U32_MAX));
GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start,
-fbc->compressed_llb.start, U32_MAX));
+llb_offset, U32_MAX));
intel_de_write(i915, FBC_CFB_BASE,
- i915->dsm.start + fbc->compressed_fb.start);
+ i915->dsm.start + fb_offset);
intel_de_write(i915, FBC_LL_BASE,
- i915->dsm.start + fbc->compressed_llb.start);
+ i915->dsm.start + llb_offset);
}
static const struct intel_fbc_funcs i8xx_fbc_funcs = {
@@ -449,8 +455,10 @@ static bool g4x_fbc_is_compressing(struct intel_fbc *fbc)
static void g4x_fbc_program_cfb(struct intel_fbc *fbc)
{
struct drm_i915_private *i915 = fbc->i915;
+ u64 fb_offset = i915_gem_stolen_reserve_offset(fbc->compressed_fb);
- intel_de_write(i915, DPFC_CB_BASE, fbc->compressed_fb.start);
+ GEM_BUG_ON(fb_offset == I915_BO_INVALID_OFFSET);
+ intel_de_write(i915, DPFC_CB_BASE, fb_offset);
}
static const struct intel_fbc_funcs g4x_fbc_funcs = {
@@ -500,8 +508,10 @@ static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
{
struct drm_i915_private *i915 = fbc->i915;
+ u64 fb_offset = i915_gem_stolen_reserve_offset(fbc->compressed_fb);
- intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id),
fbc->compressed_fb.start);
+ GEM_BUG_ON(fb_offset == I915_BO_INVALID_OFFSET);
+ intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), fb_offset);
}
static const struct intel_fbc_funcs ilk_fbc_funcs = {
@@ -741,21 +751,24 @@ static int find_compression_limit(struct intel_fbc *fbc,
{
struct drm_i915_private *i915 = fbc->i915;
u64 end = intel_fbc_stolen_end(i915);
- int ret, limit = min_limit;
+ int limit = min_limit;
+ struct ttm_resource *res;
size /= limit;
/* Try to over-allocate to reduce reallocations and fragmentation. */
- ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb,
- size <<= 1, 4096, 0, end);
- if (ret == 0)
+ res = i915_gem_stolen_reserve_range(i915, size <<= 1, 0, end);
+ if (!IS_ERR(res)) {
+ fbc->compressed_fb = res;
return limit;
+ }
for (; limit <= intel_fbc_max_limit(i915); limit <<=
[Intel-gfx] [PATCH 4/5] drm/i915: ttm backend dont provide mmap_offset for kernel buffers
stolen/kernel buffers should not be mmapable by userland.
do not provide callbacks to facilitate this for these buffers.
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 32 +
1 file changed, 27 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index a878910a563c..b20f81836c54 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -1092,8 +1092,8 @@ static void i915_ttm_unmap_virtual(struct
drm_i915_gem_object *obj)
ttm_bo_unmap_virtual(i915_gem_to_ttm(obj));
}
-static const struct drm_i915_gem_object_ops i915_gem_ttm_obj_ops = {
- .name = "i915_gem_object_ttm",
+static const struct drm_i915_gem_object_ops i915_gem_ttm_user_obj_ops = {
+ .name = "i915_gem_object_ttm_user",
.flags = I915_GEM_OBJECT_IS_SHRINKABLE |
I915_GEM_OBJECT_SELF_MANAGED_SHRINK_LIST,
@@ -,6 +,21 @@ static const struct drm_i915_gem_object_ops
i915_gem_ttm_obj_ops = {
.mmap_ops = &vm_ops_ttm,
};
+static const struct drm_i915_gem_object_ops i915_gem_ttm_kern_obj_ops = {
+ .name = "i915_gem_object_ttm_kern",
+ .flags = I915_GEM_OBJECT_IS_SHRINKABLE |
+I915_GEM_OBJECT_SELF_MANAGED_SHRINK_LIST,
+
+ .get_pages = i915_ttm_get_pages,
+ .put_pages = i915_ttm_put_pages,
+ .truncate = i915_ttm_truncate,
+ .shrink = i915_ttm_shrink,
+
+ .adjust_lru = i915_ttm_adjust_lru,
+ .delayed_free = i915_ttm_delayed_free,
+ .migrate = i915_ttm_migrate,
+};
+
void i915_ttm_bo_destroy(struct ttm_buffer_object *bo)
{
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
@@ -1165,10 +1180,19 @@ int __i915_gem_ttm_object_init(struct
intel_memory_region *mem,
.no_wait_gpu = false,
};
enum ttm_bo_type bo_type;
+ const struct drm_i915_gem_object_ops *ops;
int ret;
drm_gem_private_object_init(&i915->drm, &obj->base, size);
- i915_gem_object_init(obj, &i915_gem_ttm_obj_ops, &lock_class, flags);
+
+ if (flags & I915_BO_ALLOC_USER && intel_region_to_ttm_type(mem) !=
I915_PL_STOLEN) {
+ bo_type = ttm_bo_type_device;
+ ops = &i915_gem_ttm_user_obj_ops;
+ } else {
+ bo_type = ttm_bo_type_kernel;
+ ops = &i915_gem_ttm_kern_obj_ops;
+ }
+ i915_gem_object_init(obj, ops, &lock_class, flags);
obj->bo_offset = offset;
@@ -1178,8 +1202,6 @@ int __i915_gem_ttm_object_init(struct intel_memory_region
*mem,
INIT_RADIX_TREE(&obj->ttm.get_io_page.radix, GFP_KERNEL | __GFP_NOWARN);
mutex_init(&obj->ttm.get_io_page.lock);
- bo_type = (obj->flags & I915_BO_ALLOC_USER) ? ttm_bo_type_device :
- ttm_bo_type_kernel;
obj->base.vma_node.driver_private = i915_gem_to_ttm(obj);
--
2.25.1
[Intel-gfx] [PATCH 3/5] drm/i915: ttm move/clear logic fix
ttm managed buffers start off with system resource definitions and ttm_tt
tracking structures allocated (though unpopulated).
currently this prevents clearing of buffers on first move to desired
placements.
The desired behaviour is to clear user allocated buffers and any kernel
buffers that specifically requests it only.
Make the logic match the desired behaviour.
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 22 +++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 9fe8132de3b2..9cf85f91edb5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -3,6 +3,7 @@
* Copyright © 2021 Intel Corporation
*/
+#include "drm/ttm/ttm_tt.h"
#include
#include "i915_deps.h"
@@ -470,6 +471,25 @@ __i915_ttm_move(struct ttm_buffer_object *bo,
return fence;
}
+static bool
+allow_clear(struct drm_i915_gem_object *obj, struct ttm_tt *ttm, struct
ttm_resource *dst_mem)
+{
+ /* never clear stolen */
+ if (dst_mem->mem_type == I915_PL_STOLEN)
+ return false;
+ /*
+* we want to clear user buffers and any kernel buffers
+* that specifically request clearing.
+*/
+ if (obj->flags & I915_BO_ALLOC_USER)
+ return true;
+
+ if (ttm && ttm->page_flags & TTM_TT_FLAG_ZERO_ALLOC)
+ return true;
+
+ return false;
+}
+
/**
* i915_ttm_move - The TTM move callback used by i915.
* @bo: The buffer object.
@@ -520,7 +540,7 @@ int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
return PTR_ERR(dst_rsgt);
clear = !i915_ttm_cpu_maps_iomem(bo->resource) && (!ttm ||
!ttm_tt_is_populated(ttm));
- if (!(clear && ttm && !(ttm->page_flags & TTM_TT_FLAG_ZERO_ALLOC))) {
+ if (!clear || allow_clear(obj, ttm, dst_mem)) {
struct i915_deps deps;
i915_deps_init(&deps, GFP_KERNEL | __GFP_NORETRY |
__GFP_NOWARN);
--
2.25.1
[Intel-gfx] [PATCH 2/5] drm/i915: sanitize mem_flags for stolen buffers
stolen regions are not page backed or considered iomem. Signed-off-by: Robert Beckett --- drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c index 358f8a1a30ce..9fe8132de3b2 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c @@ -122,8 +122,9 @@ void i915_ttm_adjust_gem_after_move(struct drm_i915_gem_object *obj) obj->mem_flags &= ~(I915_BO_FLAG_STRUCT_PAGE | I915_BO_FLAG_IOMEM); - obj->mem_flags |= i915_ttm_cpu_maps_iomem(bo->resource) ? I915_BO_FLAG_IOMEM : - I915_BO_FLAG_STRUCT_PAGE; + if (obj->mm.region->id != INTEL_REGION_STOLEN_SMEM) + obj->mem_flags |= i915_ttm_cpu_maps_iomem(bo->resource) ? I915_BO_FLAG_IOMEM : + I915_BO_FLAG_STRUCT_PAGE; cache_level = i915_ttm_cache_level(to_i915(bo->base.dev), bo->resource, bo->ttm); -- 2.25.1
[Intel-gfx] [PATCH 0/5] drm/i915: ttm for stolen region
This series refactors i915's stolen memory region to use ttm. Robert Beckett (5): drm/i915: instantiate ttm ranger manager for stolen memory drm/i915: sanitize mem_flags for stolen buffers drm/i915: ttm move/clear logic fix drm/i915: ttm backend dont provide mmap_offset for kernel buffers drm/i915: stolen memory use ttm backend drivers/gpu/drm/i915/display/intel_fbc.c | 78 ++-- .../gpu/drm/i915/gem/i915_gem_object_types.h | 2 - drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 405 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.h| 21 +- drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 32 +- drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 7 + drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 33 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 4 +- drivers/gpu/drm/i915/gt/selftest_reset.c | 16 +- drivers/gpu/drm/i915/i915_debugfs.c | 7 +- drivers/gpu/drm/i915/i915_drv.h | 5 - drivers/gpu/drm/i915/intel_region_ttm.c | 67 ++- drivers/gpu/drm/i915/intel_region_ttm.h | 8 +- drivers/gpu/drm/i915/selftests/mock_region.c | 3 +- 14 files changed, 310 insertions(+), 378 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH 1/5] drm/i915: instantiate ttm ranger manager for stolen memory
prepare for ttm based stolen region by using ttm range manager
as the resource manager for stolen region.
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 6 ++--
drivers/gpu/drm/i915/intel_region_ttm.c | 31 +++-
2 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index a10716f4e717..358f8a1a30ce 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -58,11 +58,13 @@ i915_ttm_region(struct ttm_device *bdev, int ttm_mem_type)
struct drm_i915_private *i915 = container_of(bdev, typeof(*i915), bdev);
/* There's some room for optimization here... */
- GEM_BUG_ON(ttm_mem_type != I915_PL_SYSTEM &&
- ttm_mem_type < I915_PL_LMEM0);
+ GEM_BUG_ON(ttm_mem_type == I915_PL_GGTT);
+
if (ttm_mem_type == I915_PL_SYSTEM)
return intel_memory_region_lookup(i915, INTEL_MEMORY_SYSTEM,
0);
+ if (ttm_mem_type == I915_PL_STOLEN)
+ return i915->mm.stolen_region;
return intel_memory_region_lookup(i915, INTEL_MEMORY_LOCAL,
ttm_mem_type - I915_PL_LMEM0);
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c
b/drivers/gpu/drm/i915/intel_region_ttm.c
index 62ff77445b01..7d49ea72e33f 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -49,7 +49,7 @@ void intel_region_ttm_device_fini(struct drm_i915_private
*dev_priv)
/*
* Map the i915 memory regions to TTM memory types. We use the
- * driver-private types for now, reserving TTM_PL_VRAM for stolen
+ * driver-private types for now, reserving I915_PL_STOLEN for stolen
* memory and TTM_PL_TT for GGTT use if decided to implement this.
*/
int intel_region_to_ttm_type(const struct intel_memory_region *mem)
@@ -58,11 +58,17 @@ int intel_region_to_ttm_type(const struct
intel_memory_region *mem)
GEM_BUG_ON(mem->type != INTEL_MEMORY_LOCAL &&
mem->type != INTEL_MEMORY_MOCK &&
- mem->type != INTEL_MEMORY_SYSTEM);
+ mem->type != INTEL_MEMORY_SYSTEM &&
+ mem->type != INTEL_MEMORY_STOLEN_SYSTEM &&
+ mem->type != INTEL_MEMORY_STOLEN_LOCAL);
if (mem->type == INTEL_MEMORY_SYSTEM)
return TTM_PL_SYSTEM;
+ if (mem->type == INTEL_MEMORY_STOLEN_SYSTEM ||
+ mem->type == INTEL_MEMORY_STOLEN_LOCAL)
+ return I915_PL_STOLEN;
+
type = mem->instance + TTM_PL_PRIV;
GEM_BUG_ON(type >= TTM_NUM_MEM_TYPES);
@@ -86,10 +92,16 @@ int intel_region_ttm_init(struct intel_memory_region *mem)
int mem_type = intel_region_to_ttm_type(mem);
int ret;
- ret = i915_ttm_buddy_man_init(bdev, mem_type, false,
- resource_size(&mem->region),
- mem->io_size,
- mem->min_page_size, PAGE_SIZE);
+ if (mem_type == I915_PL_STOLEN) {
+ ret = ttm_range_man_init(bdev, mem_type, false,
+resource_size(&mem->region) >>
PAGE_SHIFT);
+ mem->is_range_manager = true;
+ } else {
+ ret = i915_ttm_buddy_man_init(bdev, mem_type, false,
+ resource_size(&mem->region),
+ mem->io_size,
+ mem->min_page_size, PAGE_SIZE);
+ }
if (ret)
return ret;
@@ -109,6 +121,7 @@ int intel_region_ttm_init(struct intel_memory_region *mem)
int intel_region_ttm_fini(struct intel_memory_region *mem)
{
struct ttm_resource_manager *man = mem->region_private;
+ int mem_type = intel_region_to_ttm_type(mem);
int ret = -EBUSY;
int count;
@@ -139,8 +152,10 @@ int intel_region_ttm_fini(struct intel_memory_region *mem)
if (ret || !man)
return ret;
- ret = i915_ttm_buddy_man_fini(&mem->i915->bdev,
- intel_region_to_ttm_type(mem));
+ if (mem_type == I915_PL_STOLEN)
+ ret = ttm_range_man_fini(&mem->i915->bdev, mem_type);
+ else
+ ret = i915_ttm_buddy_man_fini(&mem->i915->bdev, mem_type);
GEM_WARN_ON(ret);
mem->region_private = NULL;
--
2.25.1
Re: [Intel-gfx] [PATCH] drm/i915/dg2: Do not explode on phy calibration error
ICL issue is related to
https://gitlab.freedesktop.org/drm/intel/-/issues/4767
igt@kms_fbcon_fbt@fbc(-suspend)? - fail - Failed assertion:
feature->wait_until_update(drm)
Thanks,
Lakshmi.
-Original Message-
From: De Marchi, Lucas
Sent: Monday, April 11, 2022 11:17 AM
To: Roper, Matthew D
Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä
; Jani Nikula ;
Vudum, Lakshminarayana
Subject: Re: [PATCH] drm/i915/dg2: Do not explode on phy calibration error
On Mon, Apr 11, 2022 at 08:34:35AM -0700, Matt Roper wrote:
>On Sat, Apr 09, 2022 at 11:15:36PM -0700, Lucas De Marchi wrote:
>> When the PHY fails on calibration we were previously skipping the ddi
>> initialization. However the driver is not really prepared for that,
>> ultimately leading to a NULL pointer dereference:
>>
>> [ 75.748348] i915 :03:00.0: [drm:intel_modeset_init_nogem [i915]] SNPS
>> PHY A failed to calibrate; output will not be used.
>> ...
>> [ 75.750336] i915 :03:00.0: [drm:intel_modeset_setup_hw_state [i915]]
>> [CRTC:80:pipe A] hw state readout: enabled
>> ...
>>
>> ( no DDI A/PHY A )
>> [ 75.753080] i915 :03:00.0: [drm:intel_modeset_setup_hw_state [i915]]
>> [ENCODER:235:DDI B/PHY B] hw state readout: disabled, pipe A
>> [ 75.753164] i915 :03:00.0: [drm:intel_modeset_setup_hw_state [i915]]
>> [ENCODER:245:DDI C/PHY C] hw state readout: disabled, pipe A
>> ...
>> [ 75.754425] i915 :03:00.0: [drm] *ERROR* crtc 80: Can't calculate
>> constants, dotclock = 0!
>> [ 75.765558] i915 :03:00.0:
>> drm_WARN_ON_ONCE(drm_drv_uses_atomic_modeset(dev))
>> [ 75.765569] WARNING: CPU: 5 PID: 1759 at drivers/gpu/drm/drm_vblank.c:728
>> drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x347/0x360
>> ...
>> [ 75.781230] BUG: kernel NULL pointer dereference, address:
>> 007c
>> [ 75.788198] #PF: supervisor read access in kernel mode
>> [ 75.793347] #PF: error_code(0x) - not-present page
>> [ 75.798480] PGD 0 P4D 0
>> [ 75.801019] Oops: [#1] PREEMPT SMP NOPTI
>> [ 75.805377] CPU: 5 PID: 1759 Comm: modprobe Tainted: GW
>> 5.18.0-rc1-demarchi+ #199
>> [ 75.827613] RIP: 0010:icl_aux_power_well_disable+0x3b/0x200 [i915]
>> [ 75.833890] Code: 83 ec 30 65 48 8b 04 25 28 00 00 00 48 89 44 24 28 48
>> 8b 06 0f b6 70 1c f6 40 20 04 8d 56 fa 0f 45 f2 e8 88 bd ff ff 48 89 ef <8b>
>> 70 7c e8 ed 67 ff ff 48 89 ef 89 c6 e8 73 67 ff ff 84 c0 75 0a
>> [ 75.852629] RSP: 0018:c90003a7fb30 EFLAGS: 00010246
>> [ 75.857852] RAX: RBX: 8881145e8f10 RCX:
>>
>> [ 75.864978] RDX: 888115220840 RSI: RDI:
>> 88811522
>> [ 75.872106] RBP: 88811522 R08: 8ee8 R09:
>> fffd
>> [ 75.879234] R10: 8e20 R11: 8ed0 R12:
>> 8881145e8f10
>> [ 75.886363] R13: 0001 R14: 888115223240 R15:
>>
>> [ 75.893490] FS: 7ff6e753a740() GS:8f68()
>> knlGS:
>> [ 75.901573] CS: 0010 DS: ES: CR0: 80050033
>> [ 75.907313] CR2: 007c CR3: 0001216a6001 CR4:
>> 00770ee0
>> [ 75.914446] PKRU: 5554
>> [ 75.917153] Call Trace:
>> [ 75.919603]
>> [ 75.921709] intel_power_domains_sanitize_state+0x88/0xb0 [i915]
>> [ 75.927814] intel_modeset_init_nogem+0x317/0xef0 [i915]
>> [ 75.933205] i915_driver_probe+0x5f6/0xdf0 [i915]
>> [ 75.937976] i915_pci_probe+0x51/0x1d0 [i915]
>>
>> We skip the initialization of PHY A, but later we try to find out
>> what is the phy for that power well and dereference dig_port, which is NULL.
>>
>> Failing the PHY calibration could be left as a warning or error, like
>> it was before commit b4eb76d82a0e ("drm/i915/dg2: Skip output init on
>> PHY calibration failure"). However that often fails for outputs not
>> being used, which would make the warning/error appear on systems that
>> have no visible issues. Anyway, there is still a need to fix those
>> failures, but that is left for later.
>>
>> Signed-off-by: Lucas De Marchi
>
>Reviewed-by: Matt Roper
The only CI failure is on ICL, that doesn't have snps phy. +Lakshmi
Applied to drm-intel-next. Thanks.
Lucas De Marchi
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: Do not explode on phy calibration error
== Series Details ==
Series: drm/i915/dg2: Do not explode on phy calibration error
URL : https://patchwork.freedesktop.org/series/102458/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11480_full -> Patchwork_22834_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22834_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_whisper@basic-fds-priority-all:
- {shard-tglu}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-tglu-3/igt@gem_exec_whis...@basic-fds-priority-all.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22834/shard-tglu-4/igt@gem_exec_whis...@basic-fds-priority-all.html
Known issues
Here are the changes found in Patchwork_22834_full that come from known
issues:
### CI changes ###
Issues hit
* boot:
- shard-glk: ([PASS][3], [PASS][4], [PASS][5], [PASS][6],
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12],
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18],
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24],
[PASS][25], [PASS][26]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30],
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36],
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42],
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48],
[PASS][49], [FAIL][50], [PASS][51]) ([i915#4392])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk2/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk9/boot.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk9/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk9/boot.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk8/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk8/boot.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk8/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk7/boot.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk7/boot.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk7/boot.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk6/boot.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk6/boot.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk5/boot.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk5/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk5/boot.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk4/boot.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk4/boot.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk4/boot.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk1/boot.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk3/boot.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk1/boot.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk2/boot.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk2/boot.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11480/shard-glk3/boot.html
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22834/shard-glk9/boot.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22834/shard-glk9/boot.html
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22834/shard-glk8/boot.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22834/shard-glk8/boot.html
[31]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22834/shard-glk7/boot.html
[32]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22834/shard-glk7/boot.html
[33]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22834/shard-glk7/boot.html
[34]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22834/shard-glk6/boot.html
[35]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22834/shard-glk6/boot.html
[36]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22834/shard-glk5/boot.html
[37]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22834/shard-glk5/boot.html
[38]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22834/shard-glk5/boot.html
[39]:
Re: [Intel-gfx] [PATCH] drm/i915/dg2: Do not explode on phy calibration error
On Mon, Apr 11, 2022 at 08:34:35AM -0700, Matt Roper wrote:
On Sat, Apr 09, 2022 at 11:15:36PM -0700, Lucas De Marchi wrote:
When the PHY fails on calibration we were previously skipping the ddi
initialization. However the driver is not really prepared for that,
ultimately leading to a NULL pointer dereference:
[ 75.748348] i915 :03:00.0: [drm:intel_modeset_init_nogem [i915]] SNPS
PHY A failed to calibrate; output will not be used.
...
[ 75.750336] i915 :03:00.0: [drm:intel_modeset_setup_hw_state [i915]]
[CRTC:80:pipe A] hw state readout: enabled
...
( no DDI A/PHY A )
[ 75.753080] i915 :03:00.0: [drm:intel_modeset_setup_hw_state [i915]]
[ENCODER:235:DDI B/PHY B] hw state readout: disabled, pipe A
[ 75.753164] i915 :03:00.0: [drm:intel_modeset_setup_hw_state [i915]]
[ENCODER:245:DDI C/PHY C] hw state readout: disabled, pipe A
...
[ 75.754425] i915 :03:00.0: [drm] *ERROR* crtc 80: Can't calculate
constants, dotclock = 0!
[ 75.765558] i915 :03:00.0:
drm_WARN_ON_ONCE(drm_drv_uses_atomic_modeset(dev))
[ 75.765569] WARNING: CPU: 5 PID: 1759 at drivers/gpu/drm/drm_vblank.c:728
drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x347/0x360
...
[ 75.781230] BUG: kernel NULL pointer dereference, address: 007c
[ 75.788198] #PF: supervisor read access in kernel mode
[ 75.793347] #PF: error_code(0x) - not-present page
[ 75.798480] PGD 0 P4D 0
[ 75.801019] Oops: [#1] PREEMPT SMP NOPTI
[ 75.805377] CPU: 5 PID: 1759 Comm: modprobe Tainted: GW
5.18.0-rc1-demarchi+ #199
[ 75.827613] RIP: 0010:icl_aux_power_well_disable+0x3b/0x200 [i915]
[ 75.833890] Code: 83 ec 30 65 48 8b 04 25 28 00 00 00 48 89 44 24 28 48 8b 06 0f
b6 70 1c f6 40 20 04 8d 56 fa 0f 45 f2 e8 88 bd ff ff 48 89 ef <8b> 70 7c e8 ed
67 ff ff 48 89 ef 89 c6 e8 73 67 ff ff 84 c0 75 0a
[ 75.852629] RSP: 0018:c90003a7fb30 EFLAGS: 00010246
[ 75.857852] RAX: RBX: 8881145e8f10 RCX:
[ 75.864978] RDX: 888115220840 RSI: RDI: 88811522
[ 75.872106] RBP: 88811522 R08: 8ee8 R09: fffd
[ 75.879234] R10: 8e20 R11: 8ed0 R12: 8881145e8f10
[ 75.886363] R13: 0001 R14: 888115223240 R15:
[ 75.893490] FS: 7ff6e753a740() GS:8f68()
knlGS:
[ 75.901573] CS: 0010 DS: ES: CR0: 80050033
[ 75.907313] CR2: 007c CR3: 0001216a6001 CR4: 00770ee0
[ 75.914446] PKRU: 5554
[ 75.917153] Call Trace:
[ 75.919603]
[ 75.921709] intel_power_domains_sanitize_state+0x88/0xb0 [i915]
[ 75.927814] intel_modeset_init_nogem+0x317/0xef0 [i915]
[ 75.933205] i915_driver_probe+0x5f6/0xdf0 [i915]
[ 75.937976] i915_pci_probe+0x51/0x1d0 [i915]
We skip the initialization of PHY A, but later we try to find out what is the
phy
for that power well and dereference dig_port, which is NULL.
Failing the PHY calibration could be left as a warning or error, like it
was before commit b4eb76d82a0e ("drm/i915/dg2: Skip output init on PHY
calibration failure"). However that often fails for outputs not being
used, which would make the warning/error appear on systems that have no
visible issues. Anyway, there is still a need to fix those failures,
but that is left for later.
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
The only CI failure is on ICL, that doesn't have snps phy. +Lakshmi
Applied to drm-intel-next. Thanks.
Lucas De Marchi
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: low level EDID block read refactoring etc. (rev5)
== Series Details == Series: drm/edid: low level EDID block read refactoring etc. (rev5) URL : https://patchwork.freedesktop.org/series/102329/ State : success == Summary == CI Bug Log - changes from CI_DRM_11482 -> Patchwork_102329v5 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/index.html Participating hosts (53 -> 36) -- Additional (1): fi-pnv-d510 Missing(18): fi-bdw-samus shard-tglu bat-dg1-6 bat-dg2-8 shard-rkl bat-adlm-1 fi-icl-u2 bat-dg2-9 bat-adlp-6 fi-bsw-cyan bat-adlp-4 bat-hsw-1 fi-hsw-4770 bat-rpls-1 bat-rpls-2 shard-dg1 bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_102329v5 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-pnv-d510:NOTRUN -> [SKIP][1] ([fdo#109271]) +39 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[PASS][2] -> [INCOMPLETE][3] ([i915#3921]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_busy@basic@modeset: - fi-tgl-u2: [PASS][4] -> [DMESG-WARN][5] ([i915#402]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/fi-tgl-u2/igt@kms_busy@ba...@modeset.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/fi-tgl-u2/igt@kms_busy@ba...@modeset.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c: - fi-pnv-d510:NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#5341]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/fi-pnv-d510/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html Possible fixes * igt@i915_selftest@live@gt_lrc: - fi-rkl-guc: [INCOMPLETE][7] ([i915#2373] / [i915#4983]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@hangcheck: - fi-hsw-g3258: [INCOMPLETE][9] ([i915#3303] / [i915#4785]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html * igt@kms_busy@basic@flip: - fi-tgl-u2: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/fi-tgl-u2/igt@kms_busy@ba...@flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/fi-tgl-u2/igt@kms_busy@ba...@flip.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373 [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341 Build changes - * Linux: CI_DRM_11482 -> Patchwork_102329v5 CI-20190529: 20190529 CI_DRM_11482: 1745c71775af931726ab18afcd95f73ea8699e49 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6419: 33a5adf20dc435cc2c6dd584caa3674c89032762 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_102329v5: 102329v5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b98e5b2f7f7a drm/edid: add EDID block count and size helpers bfd304726831 drm/edid: add single point of return to drm_do_get_edid() e97dd84bf6aa drm/edid: drop extra local var 5c93dad479c5 drm/edid: convert extension block read to EDID block read helper 980c66c6bc38 drm/edid: use EDID block read helper in drm_do_get_edid() 999e727d99b6 drm/edid: abstract an EDID block read helper e17d66455d34 drm/edid: add typedef for block read function c1b8e0e1d4da drm/edid: pass struct edid to connector_bad_edid() d0399e6539bd drm/edid: add a helper to log dump an EDID block 7583233f5a43 drm/edid: refactor EDID block status printing 0d23358670a9 drm/edid: have edid_block_check() detect blocks that are all zero 4ccd25f176f2 drm/edid: convert edid_is_zero() to edid_block_is_zero() for blocks == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102329v5/index.html
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/dp: Factor out a function to probe a DPCD address (rev3)
== Series Details == Series: series starting with [v3,1/2] drm/dp: Factor out a function to probe a DPCD address (rev3) URL : https://patchwork.freedesktop.org/series/102428/ State : success == Summary == CI Bug Log - changes from CI_DRM_11482 -> Patchwork_102428v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/index.html Participating hosts (51 -> 36) -- Additional (1): fi-pnv-d510 Missing(16): fi-bdw-samus shard-tglu bat-dg1-6 fi-tgl-u2 bat-dg2-8 bat-adlm-1 fi-icl-u2 bat-dg2-9 bat-adlp-6 fi-bsw-cyan bat-adlp-4 bat-hsw-1 bat-rpls-1 bat-rpls-2 bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_102428v3 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[PASS][1] -> [INCOMPLETE][2] ([i915#4785]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html - fi-bdw-5557u: NOTRUN -> [INCOMPLETE][3] ([i915#3921]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/fi-bdw-5557u/igt@i915_selftest@l...@hangcheck.html - fi-snb-2600:[PASS][4] -> [INCOMPLETE][5] ([i915#3921]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c: - fi-pnv-d510:NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#5341]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/fi-pnv-d510/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html * igt@kms_setmode@basic-clone-single-crtc: - fi-bdw-5557u: NOTRUN -> [SKIP][8] ([fdo#109271]) +14 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/fi-bdw-5557u/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-userptr: - fi-pnv-d510:NOTRUN -> [SKIP][9] ([fdo#109271]) +39 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/fi-pnv-d510/igt@prime_v...@basic-userptr.html * igt@runner@aborted: - fi-hsw-4770:NOTRUN -> [FAIL][10] ([fdo#109271] / [i915#2722] / [i915#4312] / [i915#5594]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/fi-hsw-4770/igt@run...@aborted.html Possible fixes * igt@i915_selftest@live@gt_lrc: - fi-rkl-guc: [INCOMPLETE][11] ([i915#2373] / [i915#4983]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@hangcheck: - fi-hsw-g3258: [INCOMPLETE][13] ([i915#3303] / [i915#4785]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11482/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102428v3/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373 [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722 [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341 [i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594 Build changes - * Linux: CI_DRM_11482 -> Patchwork_102428v3 CI-20190529: 20190529 CI_DRM_11482: 1745c71775af931726ab18afcd95f73ea8699e49 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6419: 33a5adf20dc435cc2c6dd584caa3674c89032762 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_102428v3: 102428v3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e0e4dbd0fc90 drm/i915/dp: Add workaround for spurious AUX timeouts/hotplugs on LTTPR links 8dd6716eb7f8 drm/dp: Fact
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/2] drm/dp: Factor out a function to probe a DPCD address (rev3)
== Series Details == Series: series starting with [v3,1/2] drm/dp: Factor out a function to probe a DPCD address (rev3) URL : https://patchwork.freedesktop.org/series/102428/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info mus
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/2] drm/dp: Factor out a function to probe a DPCD address (rev3)
== Series Details == Series: series starting with [v3,1/2] drm/dp: Factor out a function to probe a DPCD address (rev3) URL : https://patchwork.freedesktop.org/series/102428/ State : warning == Summary == Error: dim checkpatch failed 7a09c6bb44f9 drm/dp: Factor out a function to probe a DPCD address -:15: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #15: v3: Add tracing for the 1-byte read even if the read was successful. (Khaled) total: 0 errors, 1 warnings, 0 checks, 58 lines checked 3e0afbca1857 drm/i915/dp: Add workaround for spurious AUX timeouts/hotplugs on LTTPR links -:76: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #76: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:200: + if (drm_dp_dpcd_probe(&intel_dp->aux, DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV)) total: 0 errors, 1 warnings, 0 checks, 49 lines checked
Re: [Intel-gfx] [PATCH 05/34] drm/i915/gvt: cleanup the Makefile
On Mon, Apr 11, 2022 at 07:11:03PM +0300, Jani Nikula wrote: > > Up to you but I usually sort these lists > > Yeah, please do. Otherwise matches what I sent, so ack. Let's just merge your 2 patch series ASAP and I'll rebase on top of that. What branch in drm-intel should I use as the base for the next version btw? Or does gvt go through yet another tree?
[Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 75 +-
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 143
3 files changed, 191 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 972c9ed46829..f5477f1bf622 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -114,7 +114,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -640,11 +639,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
return 6144 * 8;
}
-static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp)
+u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -656,7 +656,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
* for MST -> TimeSlotsPerMTP has to be calculated
*/
bits_per_pixel = (link_clock * lane_count * 8) /
-intel_dp_mode_to_fec_clock(mode_clock);
+(intel_dp_mode_to_fec_clock(mode_clock) * timeslots);
drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
@@ -710,9 +710,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
return bits_per_pixel << 4;
}
-static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
- int mode_clock, int mode_hdisplay,
- bool bigjoiner)
+u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 min_slice_count, i;
@@ -919,8 +919,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
return MODE_OK;
}
-static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
- int hdisplay, int clock)
+bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
+int hdisplay, int clock)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1007,7 +1007,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
target_clock,
mode->hdisplay,
bigjoiner,
- pipe_bpp) >> 4;
+ pipe_bpp, 1) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1311,7 +1311,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
return -EINVAL;
}
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
@@ -1401,10 +1401,11 @@ static int intel_dp_dsc_compute_params(struct
intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
-static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
- struct intel_crtc_state *pipe_config,
- struct drm_connector_state *conn_state,
- struct link_config_limits *limits)
+int intel_dp_dsc_compute_config(struct i
[Intel-gfx] [PATCH 1/2] drm: Add missing DP DSC extended capability definitions.
Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning v3: - Removed function which is not yet used(Jani Nikula) Signed-off-by: Stanislav Lisovskiy --- include/drm/dp/drm_dp_helper.h | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h index 1eccd9741943..272e687ae25f 100644 --- a/include/drm/dp/drm_dp_helper.h +++ b/include/drm/dp/drm_dp_helper.h @@ -246,6 +246,9 @@ struct drm_panel; #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP(1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -284,12 +287,15 @@ struct drm_panel; #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -351,11 +357,13 @@ struct drm_panel; # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_10x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED1 -- 2.24.1.485.gad05a3d8e5
[Intel-gfx] [PATCH 0/2] Add DP MST DSC support to i915
Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/i915/display/intel_dp.c | 75 +- drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 143 include/drm/dp/drm_dp_helper.h | 10 +- 4 files changed, 200 insertions(+), 45 deletions(-) -- 2.24.1.485.gad05a3d8e5
Re: [Intel-gfx] [PATCH 05/34] drm/i915/gvt: cleanup the Makefile
On Mon, 11 Apr 2022, Jason Gunthorpe wrote: > On Mon, Apr 11, 2022 at 04:13:34PM +0200, Christoph Hellwig wrote: >> Match the style of the main i915 Makefile in the gvt-specfic one and >> remove the GVT_DIR and GVT_SOURCE variables. >> >> Signed-off-by: Christoph Hellwig >> drivers/gpu/drm/i915/gvt/Makefile | 29 +++-- >> 1 file changed, 23 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gvt/Makefile >> b/drivers/gpu/drm/i915/gvt/Makefile >> index 4d70f4689479c..f2f6ea02714ec 100644 >> +++ b/drivers/gpu/drm/i915/gvt/Makefile >> @@ -1,8 +1,25 @@ >> # SPDX-License-Identifier: GPL-2.0 >> -GVT_DIR := gvt >> -GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o >> firmware.o \ >> -interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \ >> -execlist.o scheduler.o sched_policy.o mmio_context.o cmd_parser.o >> debugfs.o \ >> -fb_decoder.o dmabuf.o page_track.o >> >> -i915-y += $(addprefix $(GVT_DIR)/, >> $(GVT_SOURCE)) >> +i915-y += \ >> +gvt/gvt.o \ >> +gvt/aperture_gm.o \ >> +gvt/handlers.o \ >> +gvt/vgpu.o \ >> +gvt/trace_points.o \ >> +gvt/firmware.o \ >> +gvt/interrupt.o \ >> +gvt/gtt.o \ >> +gvt/cfg_space.o \ >> +gvt/opregion.o \ >> +gvt/mmio.o \ >> +gvt/display.o \ >> +gvt/edid.o \ >> +gvt/execlist.o \ >> +gvt/scheduler.o \ >> +gvt/sched_policy.o \ >> +gvt/mmio_context.o \ >> +gvt/cmd_parser.o \ >> +gvt/debugfs.o \ >> +gvt/fb_decoder.o \ >> +gvt/dmabuf.o \ >> +gvt/page_track.o > > Up to you but I usually sort these lists Yeah, please do. Otherwise matches what I sent, so ack. BR, Jani. > > Reviewed-by: Jason Gunthorpe > > Jason -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 04/34] drm/i915/gvt: don't override the include path
On Mon, 11 Apr 2022, Christoph Hellwig wrote: > drivers/gpu/drm/i915/gvt/Makefile is included > from drivers/gpu/drm/i915/Makefile and thus inherits the normal include > path relative to drivers/gpu/drm/i915/. Fix up the gvt-specific trace > header and just do away with the include path manipulation. > > Signed-off-by: Christoph Hellwig > --- > drivers/gpu/drm/i915/gvt/Makefile | 1 - > drivers/gpu/drm/i915/gvt/trace.h | 2 +- > 2 files changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gvt/Makefile > b/drivers/gpu/drm/i915/gvt/Makefile > index ea8324abc784a..4d70f4689479c 100644 > --- a/drivers/gpu/drm/i915/gvt/Makefile > +++ b/drivers/gpu/drm/i915/gvt/Makefile > @@ -5,5 +5,4 @@ GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o > trace_points.o firmware.o \ > execlist.o scheduler.o sched_policy.o mmio_context.o cmd_parser.o > debugfs.o \ > fb_decoder.o dmabuf.o page_track.o > > -ccflags-y+= -I $(srctree)/$(src) -I > $(srctree)/$(src)/$(GVT_DIR)/ > i915-y += $(addprefix $(GVT_DIR)/, > $(GVT_SOURCE)) > diff --git a/drivers/gpu/drm/i915/gvt/trace.h > b/drivers/gpu/drm/i915/gvt/trace.h > index 6d787750d279f..348f57f8301db 100644 > --- a/drivers/gpu/drm/i915/gvt/trace.h > +++ b/drivers/gpu/drm/i915/gvt/trace.h > @@ -379,5 +379,5 @@ TRACE_EVENT(render_mmio, > #undef TRACE_INCLUDE_PATH > #define TRACE_INCLUDE_PATH . > #undef TRACE_INCLUDE_FILE > -#define TRACE_INCLUDE_FILE trace > +#define TRACE_INCLUDE_FILE gvt/trace This is not actually correct. Please see my gvt Makefile cleanup [1][2]. BR, Jani. [1] https://lore.kernel.org/all/20220331082127.432171-1-jani.nik...@intel.com/ [2] https://lore.kernel.org/all/20220331082127.432171-2-jani.nik...@intel.com/ > #include -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH 14/16] drm/i915: drop bo->moving dependency
That should now be handled by the common dma_resv framework.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
Cc: intel-gfx@lists.freedesktop.org
---
drivers/gpu/drm/i915/gem/i915_gem_object.c| 41 ---
drivers/gpu/drm/i915/gem/i915_gem_object.h| 8 +---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 15 +--
.../drm/i915/gem/selftests/i915_gem_migrate.c | 3 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 3 +-
drivers/gpu/drm/i915/i915_vma.c | 9 +++-
6 files changed, 21 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 372bc220faeb..ffde7bc0a95d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -741,30 +741,19 @@ static const struct drm_gem_object_funcs
i915_gem_object_funcs = {
/**
* i915_gem_object_get_moving_fence - Get the object's moving fence if any
* @obj: The object whose moving fence to get.
+ * @fence: The resulting fence
*
* A non-signaled moving fence means that there is an async operation
* pending on the object that needs to be waited on before setting up
* any GPU- or CPU PTEs to the object's pages.
*
- * Return: A refcounted pointer to the object's moving fence if any,
- * NULL otherwise.
+ * Return: Negative error code or 0 for success.
*/
-struct dma_fence *
-i915_gem_object_get_moving_fence(struct drm_i915_gem_object *obj)
+int i915_gem_object_get_moving_fence(struct drm_i915_gem_object *obj,
+struct dma_fence **fence)
{
- return dma_fence_get(i915_gem_to_ttm(obj)->moving);
-}
-
-void i915_gem_object_set_moving_fence(struct drm_i915_gem_object *obj,
- struct dma_fence *fence)
-{
- struct dma_fence **moving = &i915_gem_to_ttm(obj)->moving;
-
- if (*moving == fence)
- return;
-
- dma_fence_put(*moving);
- *moving = dma_fence_get(fence);
+ return dma_resv_get_singleton(obj->base.resv, DMA_RESV_USAGE_KERNEL,
+ fence);
}
/**
@@ -782,23 +771,9 @@ void i915_gem_object_set_moving_fence(struct
drm_i915_gem_object *obj,
int i915_gem_object_wait_moving_fence(struct drm_i915_gem_object *obj,
bool intr)
{
- struct dma_fence *fence = i915_gem_to_ttm(obj)->moving;
- int ret;
-
assert_object_held(obj);
- if (!fence)
- return 0;
-
- ret = dma_fence_wait(fence, intr);
- if (ret)
- return ret;
-
- if (fence->error)
- return fence->error;
-
- i915_gem_to_ttm(obj)->moving = NULL;
- dma_fence_put(fence);
- return 0;
+ return dma_resv_wait_timeout(obj->base. resv, DMA_RESV_USAGE_KERNEL,
+intr, MAX_SCHEDULE_TIMEOUT);
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 02c37fe4a535..e11d82a9f7c3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -520,12 +520,8 @@ i915_gem_object_finish_access(struct drm_i915_gem_object
*obj)
i915_gem_object_unpin_pages(obj);
}
-struct dma_fence *
-i915_gem_object_get_moving_fence(struct drm_i915_gem_object *obj);
-
-void i915_gem_object_set_moving_fence(struct drm_i915_gem_object *obj,
- struct dma_fence *fence);
-
+int i915_gem_object_get_moving_fence(struct drm_i915_gem_object *obj,
+struct dma_fence **fence);
int i915_gem_object_wait_moving_fence(struct drm_i915_gem_object *obj,
bool intr);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 438b8a95b3d1..a10716f4e717 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -467,19 +467,6 @@ __i915_ttm_move(struct ttm_buffer_object *bo,
return fence;
}
-static int
-prev_deps(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx,
- struct i915_deps *deps)
-{
- int ret;
-
- ret = i915_deps_add_dependency(deps, bo->moving, ctx);
- if (!ret)
- ret = i915_deps_add_resv(deps, bo->base.resv, ctx);
-
- return ret;
-}
-
/**
* i915_ttm_move - The TTM move callback used by i915.
* @bo: The buffer object.
@@ -534,7 +521,7 @@ int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
struct i915_deps deps;
i915_deps_init(&deps, GFP_KERNEL | __GFP_NORETRY |
__GFP_NOWARN);
- ret = prev_deps(bo, ctx, &deps);
+ ret = i915_deps_add_resv(&deps, bo->base.resv, ctx);
if (ret) {
i915_refct_sgt_put(dst_rsgt);
[Intel-gfx] [PATCH 13/15] drm/ttm: remove bo->moving
This is now handled by the DMA-buf framework in the dma_resv obj.
Also remove the workaround inside VMWGFX to update the moving fence.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 13 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 5 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c| 11 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 11 --
drivers/gpu/drm/ttm/ttm_bo.c | 10 ++
drivers/gpu/drm/ttm/ttm_bo_util.c | 7
drivers/gpu/drm/ttm/ttm_bo_vm.c | 34 +++
drivers/gpu/drm/vmwgfx/vmwgfx_resource.c | 6
include/drm/ttm/ttm_bo_api.h | 2 --
9 files changed, 39 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 808e21dcb517..a4955ef76cfc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -2447,6 +2447,8 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info,
struct dma_fence **ef)
struct amdgpu_bo *bo = mem->bo;
uint32_t domain = mem->domain;
struct kfd_mem_attachment *attachment;
+ struct dma_resv_iter cursor;
+ struct dma_fence *fence;
total_size += amdgpu_bo_size(bo);
@@ -2461,10 +2463,13 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info,
struct dma_fence **ef)
goto validate_map_fail;
}
}
- ret = amdgpu_sync_fence(&sync_obj, bo->tbo.moving);
- if (ret) {
- pr_debug("Memory eviction: Sync BO fence failed. Try
again\n");
- goto validate_map_fail;
+ dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
+ DMA_RESV_USAGE_KERNEL, fence) {
+ ret = amdgpu_sync_fence(&sync_obj, fence);
+ if (ret) {
+ pr_debug("Memory eviction: Sync BO fence
failed. Try again\n");
+ goto validate_map_fail;
+ }
}
list_for_each_entry(attachment, &mem->attachments, list) {
if (!attachment->is_mapped)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 5832c05ab10d..ef93abec13b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -612,9 +612,8 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
if (unlikely(r))
goto fail_unreserve;
- amdgpu_bo_fence(bo, fence, false);
- dma_fence_put(bo->tbo.moving);
- bo->tbo.moving = dma_fence_get(fence);
+ dma_resv_add_fence(bo->tbo.base.resv, fence,
+ DMA_RESV_USAGE_KERNEL);
dma_fence_put(fence);
}
if (!bp->resv)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
index e3fbf0f10add..31913ae86de6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
@@ -74,13 +74,12 @@ static int amdgpu_vm_cpu_update(struct
amdgpu_vm_update_params *p,
{
unsigned int i;
uint64_t value;
- int r;
+ long r;
- if (vmbo->bo.tbo.moving) {
- r = dma_fence_wait(vmbo->bo.tbo.moving, true);
- if (r)
- return r;
- }
+ r = dma_resv_wait_timeout(vmbo->bo.tbo.base.resv, DMA_RESV_USAGE_KERNEL,
+ true, MAX_SCHEDULE_TIMEOUT);
+ if (r < 0)
+ return r;
pe += (unsigned long)amdgpu_bo_kptr(&vmbo->bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index 9485b541947e..9cd6f41896c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -205,14 +205,19 @@ static int amdgpu_vm_sdma_update(struct
amdgpu_vm_update_params *p,
struct amdgpu_bo *bo = &vmbo->bo;
enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE
: AMDGPU_IB_POOL_DELAYED;
+ struct dma_resv_iter cursor;
unsigned int i, ndw, nptes;
+ struct dma_fence *fence;
uint64_t *pte;
int r;
/* Wait for PD/PT moves to be completed */
- r = amdgpu_sync_fence(&p->job->sync, bo->tbo.moving);
- if (r)
- return r;
+ dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
+ DMA_RESV_USAGE_KERNEL, fence) {
+ r = amdgpu_sync_fence(&p->job->sync, fence);
+
[Intel-gfx] [PATCH 15/15] seqlock: drop seqcount_ww_mutex_t
Daniel pointed out that this series removes the last user of seqcount_ww_mutex_t, so let's drop this. Signed-off-by: Christian König Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Will Deacon Cc: Waiman Long Cc: Boqun Feng Cc: linux-ker...@vger.kernel.org --- include/linux/seqlock.h | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/include/linux/seqlock.h b/include/linux/seqlock.h index 37ded6b8fee6..3926e9027947 100644 --- a/include/linux/seqlock.h +++ b/include/linux/seqlock.h @@ -17,7 +17,6 @@ #include #include #include -#include #include #include @@ -164,7 +163,7 @@ static inline void seqcount_lockdep_reader_access(const seqcount_t *s) * static initializer or init function. This enables lockdep to validate * that the write side critical section is properly serialized. * - * LOCKNAME: raw_spinlock, spinlock, rwlock, mutex, or ww_mutex. + * LOCKNAME: raw_spinlock, spinlock, rwlock or mutex */ /* @@ -184,7 +183,6 @@ static inline void seqcount_lockdep_reader_access(const seqcount_t *s) #define seqcount_spinlock_init(s, lock) seqcount_LOCKNAME_init(s, lock, spinlock) #define seqcount_rwlock_init(s, lock) seqcount_LOCKNAME_init(s, lock, rwlock) #define seqcount_mutex_init(s, lock) seqcount_LOCKNAME_init(s, lock, mutex) -#define seqcount_ww_mutex_init(s, lock) seqcount_LOCKNAME_init(s, lock, ww_mutex) /* * SEQCOUNT_LOCKNAME() - Instantiate seqcount_LOCKNAME_t and helpers @@ -277,7 +275,6 @@ SEQCOUNT_LOCKNAME(raw_spinlock, raw_spinlock_t, false, s->lock,raw_s SEQCOUNT_LOCKNAME(spinlock, spinlock_t, __SEQ_RT, s->lock, spin, spin_lock(s->lock)) SEQCOUNT_LOCKNAME(rwlock, rwlock_t,__SEQ_RT, s->lock, read, read_lock(s->lock)) SEQCOUNT_LOCKNAME(mutex,struct mutex,true, s->lock, mutex,mutex_lock(s->lock)) -SEQCOUNT_LOCKNAME(ww_mutex, struct ww_mutex, true, &s->lock->base, ww_mutex, ww_mutex_lock(s->lock, NULL)) /* * SEQCNT_LOCKNAME_ZERO - static initializer for seqcount_LOCKNAME_t @@ -304,8 +301,7 @@ SEQCOUNT_LOCKNAME(ww_mutex, struct ww_mutex, true, &s->lock->base, ww_mu __seqprop_case((s), raw_spinlock, prop), \ __seqprop_case((s), spinlock, prop), \ __seqprop_case((s), rwlock, prop), \ - __seqprop_case((s), mutex, prop), \ - __seqprop_case((s), ww_mutex, prop)) + __seqprop_case((s), mutex, prop)) #define seqprop_ptr(s) __seqprop(s, ptr) #define seqprop_sequence(s)__seqprop(s, sequence) -- 2.25.1
Re: [Intel-gfx] [PATCH v3] drm: add a check to verify the size alignment
Am 11.04.22 um 11:47 schrieb Matthew Auld: On 11/04/2022 08:38, Arunpravin Paneer Selvam wrote: Add a simple check to reject any size not aligned to the min_page_size. when size is not aligned to min_page_size, driver module should handle in their own way either to round_up() the size value to min_page_size or just to enable WARN_ON(). If we dont handle the alignment properly, we may hit the following bug, Unigine Heaven has allocation requests for example required pages are 257 and alignment request is 256. To allocate the left over 1 page, continues the iteration to find the order value which is 0 and when it compares with min_order = 8, triggers the BUG_ON(order < min_order). v2: add more commit description v3: remove WARN_ON() Signed-off-by: Arunpravin Paneer Selvam Suggested-by: Matthew Auld Reviewed-by: Matthew Auld Question here is who will be pushing that to drm-misc-next? Should I take care of that? I think it's time that Arun should request push permission for drm-misc-next. Thanks, Christian.
[Intel-gfx] [PATCH 01/15] dma-buf: add enum dma_resv_usage v4
This change adds the dma_resv_usage enum and allows us to specify why a
dma_resv object is queried for its containing fences.
Additional to that a dma_resv_usage_rw() helper function is added to aid
retrieving the fences for a read or write userspace submission.
This is then deployed to the different query functions of the dma_resv
object and all of their users. When the write paratermer was previously
true we now use DMA_RESV_USAGE_WRITE and DMA_RESV_USAGE_READ otherwise.
v2: add KERNEL/OTHER in separate patch
v3: some kerneldoc suggestions by Daniel
v4: some more kerneldoc suggestions by Daniel, fix missing cases lost in
the rebase pointed out by Bas.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
---
drivers/dma-buf/dma-buf.c | 6 +-
drivers/dma-buf/dma-resv.c| 35 +
drivers/dma-buf/st-dma-resv.c | 48 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 7 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-
drivers/gpu/drm/drm_gem.c | 3 +-
drivers/gpu/drm/drm_gem_atomic_helper.c | 2 +-
drivers/gpu/drm/etnaviv/etnaviv_gem.c | 6 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_busy.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 6 +-
.../drm/i915/gem/selftests/i915_gem_dmabuf.c | 3 +-
drivers/gpu/drm/i915/i915_request.c | 3 +-
drivers/gpu/drm/i915/i915_sw_fence.c | 2 +-
drivers/gpu/drm/msm/msm_gem.c | 3 +-
drivers/gpu/drm/nouveau/dispnv50/wndw.c | 3 +-
drivers/gpu/drm/nouveau/nouveau_bo.c | 8 +-
drivers/gpu/drm/nouveau/nouveau_fence.c | 8 +-
drivers/gpu/drm/nouveau/nouveau_gem.c | 3 +-
drivers/gpu/drm/panfrost/panfrost_drv.c | 3 +-
drivers/gpu/drm/qxl/qxl_debugfs.c | 3 +-
drivers/gpu/drm/radeon/radeon_display.c | 3 +-
drivers/gpu/drm/radeon/radeon_gem.c | 9 ++-
drivers/gpu/drm/radeon/radeon_mn.c| 4 +-
drivers/gpu/drm/radeon/radeon_sync.c | 2 +-
drivers/gpu/drm/radeon/radeon_uvd.c | 4 +-
drivers/gpu/drm/scheduler/sched_main.c| 3 +-
drivers/gpu/drm/ttm/ttm_bo.c | 18 +++--
drivers/gpu/drm/vgem/vgem_fence.c | 4 +-
drivers/gpu/drm/virtio/virtgpu_ioctl.c| 5 +-
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c| 4 +-
drivers/gpu/drm/vmwgfx/vmwgfx_resource.c | 3 +-
drivers/infiniband/core/umem_dmabuf.c | 3 +-
include/linux/dma-buf.h | 8 +-
include/linux/dma-resv.h | 73 +++
46 files changed, 215 insertions(+), 126 deletions(-)
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index 775d3afb4169..1cddb65eafda 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -216,7 +216,8 @@ static bool dma_buf_poll_add_cb(struct dma_resv *resv, bool
write,
struct dma_fence *fence;
int r;
- dma_resv_for_each_fence(&cursor, resv, write, fence) {
+ dma_resv_for_each_fence(&cursor, resv, dma_resv_usage_rw(write),
+ fence) {
dma_fence_get(fence);
r = dma_fence_add_callback(fence, &dcb->cb, dma_buf_poll_cb);
if (!r)
@@ -1124,7 +1125,8 @@ static int __dma_buf_begin_cpu_access(struct dma_buf
*dmabuf,
long ret;
/* Wait on any implicit rendering fences */
- ret = dma_resv_wait_timeout(resv, write, true, MAX_SCHEDULE_TIMEOUT);
+ ret = dma_resv_wait_timeout(resv, dma_resv_usage_rw(write),
+ true, MAX_SCHEDULE_TIMEOUT);
if (ret < 0)
return ret;
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index 8c650b96357a..17237e6ee30c 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -384,7 +384,7 @@ static void dma_resv_iter_restart_unlocked(struct
dma_resv_iter *cursor)
cursor->seq = read_seqcount_begin(&cursor->obj->seq);
cursor->index = -1;
cursor->shared_count = 0;
- if (cursor->all_fences) {
+ if (cursor->usage >= DMA_RESV_USAGE_READ) {
cursor->fences = dma_resv_shared_list(cursor->obj);
if (cursor->fences)
[Intel-gfx] [PATCH 09/15] dma-buf: add DMA_RESV_USAGE_BOOKKEEP v3
Add an usage for submissions independent of implicit sync but still
interesting for memory management.
v2: cleanup the kerneldoc a bit
v3: separate amdgpu changes from this
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
---
drivers/dma-buf/dma-resv.c | 4 ++--
drivers/dma-buf/st-dma-resv.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 2 +-
drivers/gpu/drm/qxl/qxl_debugfs.c | 2 +-
drivers/gpu/drm/radeon/radeon_gem.c | 2 +-
drivers/gpu/drm/radeon/radeon_mn.c | 2 +-
drivers/gpu/drm/ttm/ttm_bo.c| 14 +++---
include/linux/dma-resv.h| 13 -
14 files changed, 35 insertions(+), 24 deletions(-)
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index f4860e5f2d8b..5b64aa554c36 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -520,7 +520,7 @@ int dma_resv_copy_fences(struct dma_resv *dst, struct
dma_resv *src)
list = NULL;
- dma_resv_iter_begin(&cursor, src, DMA_RESV_USAGE_READ);
+ dma_resv_iter_begin(&cursor, src, DMA_RESV_USAGE_BOOKKEEP);
dma_resv_for_each_fence_unlocked(&cursor, f) {
if (dma_resv_iter_is_restarted(&cursor)) {
@@ -726,7 +726,7 @@ EXPORT_SYMBOL_GPL(dma_resv_test_signaled);
*/
void dma_resv_describe(struct dma_resv *obj, struct seq_file *seq)
{
- static const char *usage[] = { "kernel", "write", "read" };
+ static const char *usage[] = { "kernel", "write", "read", "bookkeep" };
struct dma_resv_iter cursor;
struct dma_fence *fence;
diff --git a/drivers/dma-buf/st-dma-resv.c b/drivers/dma-buf/st-dma-resv.c
index 062b57d63fa6..8ace9e84c845 100644
--- a/drivers/dma-buf/st-dma-resv.c
+++ b/drivers/dma-buf/st-dma-resv.c
@@ -296,7 +296,7 @@ int dma_resv(void)
int r;
spin_lock_init(&fence_lock);
- for (usage = DMA_RESV_USAGE_KERNEL; usage <= DMA_RESV_USAGE_READ;
+ for (usage = DMA_RESV_USAGE_KERNEL; usage <= DMA_RESV_USAGE_BOOKKEEP;
++usage) {
r = subtests(tests, (void *)(unsigned long)usage);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 65998cbcd7f7..4ba4b54092f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -111,7 +111,7 @@ void amdgpu_pasid_free_delayed(struct dma_resv *resv,
struct dma_fence *fence;
int r;
- r = dma_resv_get_singleton(resv, DMA_RESV_USAGE_READ, &fence);
+ r = dma_resv_get_singleton(resv, DMA_RESV_USAGE_BOOKKEEP, &fence);
if (r)
goto fallback;
@@ -139,7 +139,7 @@ void amdgpu_pasid_free_delayed(struct dma_resv *resv,
/* Not enough memory for the delayed delete, as last resort
* block for all the fences to complete.
*/
- dma_resv_wait_timeout(resv, DMA_RESV_USAGE_READ,
+ dma_resv_wait_timeout(resv, DMA_RESV_USAGE_BOOKKEEP,
false, MAX_SCHEDULE_TIMEOUT);
amdgpu_pasid_free(pasid);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index 86f5248676b0..b86c0b8252a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -75,7 +75,7 @@ static bool amdgpu_mn_invalidate_gfx(struct
mmu_interval_notifier *mni,
mmu_interval_set_seq(mni, cur_seq);
- r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_READ,
+ r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP,
false, MAX_SCHEDULE_TIMEOUT);
mutex_unlock(&adev->notifier_lock);
if (r <= 0)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index 744e144e5fc2..11c46b3e4c60 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -260,7 +260,7 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct
amdgpu_sync *sync,
return -EINVAL;
/* TODO: Use DMA_RESV_USAGE_READ here */
- dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_READ, f) {
+ dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, f) {
dma_fence_chain_for_each(f, f) {
struct dma_fence *tmp = dma_fence_chain_contained(f);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 5db5066e74b4..49ffad312d5d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drive
[Intel-gfx] [PATCH 12/15] drm/i915: drop bo->moving dependency
That should now be handled by the common dma_resv framework.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
Cc: intel-gfx@lists.freedesktop.org
---
drivers/gpu/drm/i915/gem/i915_gem_object.c| 41 ---
drivers/gpu/drm/i915/gem/i915_gem_object.h| 8 +---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 15 +--
.../drm/i915/gem/selftests/i915_gem_migrate.c | 3 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 3 +-
drivers/gpu/drm/i915/i915_vma.c | 9 +++-
6 files changed, 21 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 372bc220faeb..ffde7bc0a95d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -741,30 +741,19 @@ static const struct drm_gem_object_funcs
i915_gem_object_funcs = {
/**
* i915_gem_object_get_moving_fence - Get the object's moving fence if any
* @obj: The object whose moving fence to get.
+ * @fence: The resulting fence
*
* A non-signaled moving fence means that there is an async operation
* pending on the object that needs to be waited on before setting up
* any GPU- or CPU PTEs to the object's pages.
*
- * Return: A refcounted pointer to the object's moving fence if any,
- * NULL otherwise.
+ * Return: Negative error code or 0 for success.
*/
-struct dma_fence *
-i915_gem_object_get_moving_fence(struct drm_i915_gem_object *obj)
+int i915_gem_object_get_moving_fence(struct drm_i915_gem_object *obj,
+struct dma_fence **fence)
{
- return dma_fence_get(i915_gem_to_ttm(obj)->moving);
-}
-
-void i915_gem_object_set_moving_fence(struct drm_i915_gem_object *obj,
- struct dma_fence *fence)
-{
- struct dma_fence **moving = &i915_gem_to_ttm(obj)->moving;
-
- if (*moving == fence)
- return;
-
- dma_fence_put(*moving);
- *moving = dma_fence_get(fence);
+ return dma_resv_get_singleton(obj->base.resv, DMA_RESV_USAGE_KERNEL,
+ fence);
}
/**
@@ -782,23 +771,9 @@ void i915_gem_object_set_moving_fence(struct
drm_i915_gem_object *obj,
int i915_gem_object_wait_moving_fence(struct drm_i915_gem_object *obj,
bool intr)
{
- struct dma_fence *fence = i915_gem_to_ttm(obj)->moving;
- int ret;
-
assert_object_held(obj);
- if (!fence)
- return 0;
-
- ret = dma_fence_wait(fence, intr);
- if (ret)
- return ret;
-
- if (fence->error)
- return fence->error;
-
- i915_gem_to_ttm(obj)->moving = NULL;
- dma_fence_put(fence);
- return 0;
+ return dma_resv_wait_timeout(obj->base. resv, DMA_RESV_USAGE_KERNEL,
+intr, MAX_SCHEDULE_TIMEOUT);
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 02c37fe4a535..e11d82a9f7c3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -520,12 +520,8 @@ i915_gem_object_finish_access(struct drm_i915_gem_object
*obj)
i915_gem_object_unpin_pages(obj);
}
-struct dma_fence *
-i915_gem_object_get_moving_fence(struct drm_i915_gem_object *obj);
-
-void i915_gem_object_set_moving_fence(struct drm_i915_gem_object *obj,
- struct dma_fence *fence);
-
+int i915_gem_object_get_moving_fence(struct drm_i915_gem_object *obj,
+struct dma_fence **fence);
int i915_gem_object_wait_moving_fence(struct drm_i915_gem_object *obj,
bool intr);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 438b8a95b3d1..a10716f4e717 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -467,19 +467,6 @@ __i915_ttm_move(struct ttm_buffer_object *bo,
return fence;
}
-static int
-prev_deps(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx,
- struct i915_deps *deps)
-{
- int ret;
-
- ret = i915_deps_add_dependency(deps, bo->moving, ctx);
- if (!ret)
- ret = i915_deps_add_resv(deps, bo->base.resv, ctx);
-
- return ret;
-}
-
/**
* i915_ttm_move - The TTM move callback used by i915.
* @bo: The buffer object.
@@ -534,7 +521,7 @@ int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
struct i915_deps deps;
i915_deps_init(&deps, GFP_KERNEL | __GFP_NORETRY |
__GFP_NOWARN);
- ret = prev_deps(bo, ctx, &deps);
+ ret = i915_deps_add_resv(&deps, bo->base.resv, ctx);
if (ret) {
i915_refct_sgt_put(dst_rsgt);
Re: [Intel-gfx] [PATCH v3] drm: add a check to verify the size alignment
Am 11.04.22 um 15:49 schrieb Arunpravin Paneer Selvam: On 11/04/22 7:02 pm, Matthew Auld wrote: On 11/04/2022 13:42, Christian König wrote: Am 11.04.22 um 11:47 schrieb Matthew Auld: On 11/04/2022 08:38, Arunpravin Paneer Selvam wrote: Add a simple check to reject any size not aligned to the min_page_size. when size is not aligned to min_page_size, driver module should handle in their own way either to round_up() the size value to min_page_size or just to enable WARN_ON(). If we dont handle the alignment properly, we may hit the following bug, Unigine Heaven has allocation requests for example required pages are 257 and alignment request is 256. To allocate the left over 1 page, continues the iteration to find the order value which is 0 and when it compares with min_order = 8, triggers the BUG_ON(order < min_order). v2: add more commit description v3: remove WARN_ON() Signed-off-by: Arunpravin Paneer Selvam Suggested-by: Matthew Auld Reviewed-by: Matthew Auld Question here is who will be pushing that to drm-misc-next? Should I take care of that? Yes, please do. I think it's time that Arun should request push permission for drm-misc-next. How to get push permission for drm-misc-next, should I send request mail to maintainers, may be next time I will push myself. See here https://drm.pages.freedesktop.org/maintainer-tools/commit-access.html Regards, Christian. Thanks, Arun Thanks, Christian.
[Intel-gfx] [PATCH 10/15] drm/amdgpu: use DMA_RESV_USAGE_BOOKKEEP
Use DMA_RESV_USAGE_BOOKKEEP for VM page table updates and KFD preemption fence.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 5031e26e6716..808e21dcb517 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -263,7 +263,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct
amdgpu_bo *bo,
*/
replacement = dma_fence_get_stub();
dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
- replacement, DMA_RESV_USAGE_READ);
+ replacement, DMA_RESV_USAGE_BOOKKEEP);
dma_fence_put(replacement);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index dbb551762805..9485b541947e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -112,7 +112,8 @@ static int amdgpu_vm_sdma_commit(struct
amdgpu_vm_update_params *p,
swap(p->vm->last_unlocked, f);
dma_fence_put(tmp);
} else {
- amdgpu_bo_fence(p->vm->root.bo, f, true);
+ dma_resv_add_fence(p->vm->root.bo->tbo.base.resv, f,
+ DMA_RESV_USAGE_BOOKKEEP);
}
if (fence && !p->immediate)
--
2.25.1
[Intel-gfx] [PATCH] drivers: Fix spelling mistake "writting" -> "writing"
From: Lv Ruyi
There are some spelling mistakes in the comments. Fix it.
Reported-by: Zeal Robot
Signed-off-by: Lv Ruyi
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/net/ethernet/sfc/mcdi_pcol.h| 4 ++--
drivers/net/ethernet/toshiba/tc35815.c | 2 +-
drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c | 4 ++--
drivers/platform/x86/hp_accel.c | 2 +-
drivers/rtc/rtc-sa1100.c| 2 +-
drivers/scsi/pmcraid.c | 4 ++--
8 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 9426e252d8aa..ce361fce7155 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7304,7 +7304,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct
amdgpu_device *adev)
return;
/* initialize cam_index to 0
-* index will auto-inc after each data writting */
+* index will auto-inc after each data writing */
WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
switch (adev->ip_versions[GC_HWIP][0]) {
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 582770360ad1..cf79a25cd98a 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -451,7 +451,7 @@ static bool __request_in_flight(const struct i915_request
*signal)
* to avoid tearing.]
*
* Note that the read of *execlists->active may race with the promotion
-* of execlists->pending[] to execlists->inflight[], overwritting
+* of execlists->pending[] to execlists->inflight[], overwriting
* the value at *execlists->active. This is fine. The promotion implies
* that we received an ACK from the HW, and so the context is not
* stuck -- if we do not see ourselves in *active, the inflight status
diff --git a/drivers/net/ethernet/sfc/mcdi_pcol.h
b/drivers/net/ethernet/sfc/mcdi_pcol.h
index d3fcbf930dba..ff617b1b38d3 100644
--- a/drivers/net/ethernet/sfc/mcdi_pcol.h
+++ b/drivers/net/ethernet/sfc/mcdi_pcol.h
@@ -73,8 +73,8 @@
* \-- Resync (always set)
*
* The client writes it's request into MC shared memory, and rings the
- * doorbell. Each request is completed by either by the MC writting
- * back into shared memory, or by writting out an event.
+ * doorbell. Each request is completed by either by the MC writing
+ * back into shared memory, or by writing out an event.
*
* All MCDI commands support completion by shared memory response. Each
* request may also contain additional data (accounted for by HEADER.LEN),
diff --git a/drivers/net/ethernet/toshiba/tc35815.c
b/drivers/net/ethernet/toshiba/tc35815.c
index ce38f7515225..1b4c207afb66 100644
--- a/drivers/net/ethernet/toshiba/tc35815.c
+++ b/drivers/net/ethernet/toshiba/tc35815.c
@@ -157,7 +157,7 @@ struct tc35815_regs {
#define PROM_Read 0x4000 /*10:Read operation*/
#define PROM_Write0x2000 /*01:Write operation */
#define PROM_Erase0x6000 /*11:Erase operation */
- /*00:Enable or Disable Writting, */
+ /*00:Enable or Disable Writing,*/
/* as specified in PROM_Addr. */
#define PROM_Addr_Ena 0x0030 /*11:PROM Write enable */
/*00: disable*/
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c
b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c
index eaba66113328..fbb4941d0da8 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c
@@ -520,7 +520,7 @@ static void _rtl92cu_init_queue_reserved_page(struct
ieee80211_hw *hw,
* 2 out-ep. Remainder pages have assigned to High queue */
if (outepnum > 1 && txqremaininpage)
numhq += txqremaininpage;
- /* NOTE: This step done before writting REG_RQPN. */
+ /* NOTE: This step done before writing REG_RQPN. */
if (ischipn) {
if (queue_sel & TX_SELE_NQ)
numnq = txqpageunit;
@@ -539,7 +539,7 @@ static void _rtl92cu_init_queue_reserved_page(struct
ieee80211_hw *hw,
numlq = ischipn ? WMM_CHIP_B_PAGE_NUM_LPQ :
WMM_CHIP_A_PAGE_NUM_LPQ;
}
- /* NOTE: This step done before writting REG_RQPN. */
+ /* NOTE: This step done before writing REG_RQPN. */
if (ischipn) {
Re: [Intel-gfx] [PATCH 12/15] drm/i915: drop bo->moving dependency
Am 08.04.22 um 11:33 schrieb Daniel Vetter:
On Fri, 8 Apr 2022 at 11:27, Christian König wrote:
Am 08.04.22 um 11:05 schrieb Jani Nikula:
On Thu, 07 Apr 2022, "Christian König" wrote:
That should now be handled by the common dma_resv framework.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
Cc: intel-gfx@lists.freedesktop.org
So, where are the i915 maintainer acks for merging this (and the other
patches in the series touching i915) via drm-misc-next?
Daniel's Reviewed-by is not an ack to merge outside drm-intel-next.
I had the impression that it would be sufficient.
We don't merge i915 stuff without passing CI results. Apparently this
one failed enough machines that the CI had to be stopped entirely.
That was unfortunately partially expected and pointed out by Matthew and
Daniel before the push.
Uh I didn't realize that CI never tested this. Usually the way then is
to rebase onto drm-tip and figure out the merge story. Doing subsystem
wide changes while not on linux-next or drm-tip or another integration
tree is just fraught with surprises due to conflicts.
Also "doesn't even compile" is really below the bar, and not the first
time this happened at all. And i915 isn't really an obscure driver
which is hard to compile test :-)
Yeah, I'm really wondering how the build breakage slipped as well.
I've double checked it multiple times now. My build system was certainly
not complaining about anything, but right after the push both i915, VC4
and one of the core header changes broke the build on drm-tip.
Going to try to figure out why that didn't worked as expected.
Thanks,
Christian
-Daniel
i915 for some reason extended the usage of the bo->moving fence despite
the fact we had patches on the mailing list to entirely remove this feature.
I couldn't get any sane CI results for weeks because of this and at some
point we just had to go ahead and fix the clash in drm-tip.
Sorry for any inconvenience cause by that. I hoped that we fixed all
cases, but looks like we still missed some.
Regards,
Christian.
BR,
Jani.
---
drivers/gpu/drm/i915/gem/i915_gem_object.c| 41 ---
drivers/gpu/drm/i915/gem/i915_gem_object.h| 8 +---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 15 +--
.../drm/i915/gem/selftests/i915_gem_migrate.c | 3 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 3 +-
drivers/gpu/drm/i915/i915_vma.c | 9 +++-
6 files changed, 21 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 372bc220faeb..ffde7bc0a95d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -741,30 +741,19 @@ static const struct drm_gem_object_funcs
i915_gem_object_funcs = {
/**
* i915_gem_object_get_moving_fence - Get the object's moving fence if any
* @obj: The object whose moving fence to get.
+ * @fence: The resulting fence
*
* A non-signaled moving fence means that there is an async operation
* pending on the object that needs to be waited on before setting up
* any GPU- or CPU PTEs to the object's pages.
*
- * Return: A refcounted pointer to the object's moving fence if any,
- * NULL otherwise.
+ * Return: Negative error code or 0 for success.
*/
-struct dma_fence *
-i915_gem_object_get_moving_fence(struct drm_i915_gem_object *obj)
+int i915_gem_object_get_moving_fence(struct drm_i915_gem_object *obj,
+ struct dma_fence **fence)
{
-return dma_fence_get(i915_gem_to_ttm(obj)->moving);
-}
-
-void i915_gem_object_set_moving_fence(struct drm_i915_gem_object *obj,
- struct dma_fence *fence)
-{
-struct dma_fence **moving = &i915_gem_to_ttm(obj)->moving;
-
-if (*moving == fence)
-return;
-
-dma_fence_put(*moving);
-*moving = dma_fence_get(fence);
+return dma_resv_get_singleton(obj->base.resv, DMA_RESV_USAGE_KERNEL,
+ fence);
}
/**
@@ -782,23 +771,9 @@ void i915_gem_object_set_moving_fence(struct
drm_i915_gem_object *obj,
int i915_gem_object_wait_moving_fence(struct drm_i915_gem_object *obj,
bool intr)
{
-struct dma_fence *fence = i915_gem_to_ttm(obj)->moving;
-int ret;
-
assert_object_held(obj);
-if (!fence)
-return 0;
-
-ret = dma_fence_wait(fence, intr);
-if (ret)
-return ret;
-
-if (fence->error)
-return fence->error;
-
-i915_gem_to_ttm(obj)->moving = NULL;
-dma_fence_put(fence);
-return 0;
+return dma_resv_wait_timeout(obj->base. resv, DMA_RESV_USAGE_KERNEL,
+ intr, MAX_SCHEDULE_TIMEOUT);
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 02c37fe4a535..e
[Intel-gfx] [PATCH 03/15] dma-buf & drm/amdgpu: remove dma_resv workaround
Rework the internals of the dma_resv object to allow adding more than one
write fence and remember for each fence what purpose it had.
This allows removing the workaround from amdgpu which used a container for
this instead.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
Cc: amd-...@lists.freedesktop.org
---
drivers/dma-buf/dma-resv.c | 353
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 53 +--
include/linux/dma-resv.h| 47 +--
4 files changed, 157 insertions(+), 297 deletions(-)
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index 543dae6566d2..378d47e1cfea 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -44,12 +44,12 @@
/**
* DOC: Reservation Object Overview
*
- * The reservation object provides a mechanism to manage shared and
- * exclusive fences associated with a buffer. A reservation object
- * can have attached one exclusive fence (normally associated with
- * write operations) or N shared fences (read operations). The RCU
- * mechanism is used to protect read access to fences from locked
- * write-side updates.
+ * The reservation object provides a mechanism to manage a container of
+ * dma_fence object associated with a resource. A reservation object
+ * can have any number of fences attaches to it. Each fence carries an usage
+ * parameter determining how the operation represented by the fence is using
the
+ * resource. The RCU mechanism is used to protect read access to fences from
+ * locked write-side updates.
*
* See struct dma_resv for more details.
*/
@@ -57,39 +57,59 @@
DEFINE_WD_CLASS(reservation_ww_class);
EXPORT_SYMBOL(reservation_ww_class);
+/* Mask for the lower fence pointer bits */
+#define DMA_RESV_LIST_MASK 0x3
+
struct dma_resv_list {
struct rcu_head rcu;
- u32 shared_count, shared_max;
- struct dma_fence __rcu *shared[];
+ u32 num_fences, max_fences;
+ struct dma_fence __rcu *table[];
};
-/**
- * dma_resv_list_alloc - allocate fence list
- * @shared_max: number of fences we need space for
- *
+/* Extract the fence and usage flags from an RCU protected entry in the list.
*/
+static void dma_resv_list_entry(struct dma_resv_list *list, unsigned int index,
+ struct dma_resv *resv, struct dma_fence **fence,
+ enum dma_resv_usage *usage)
+{
+ long tmp;
+
+ tmp = (long)rcu_dereference_check(list->table[index],
+ resv ? dma_resv_held(resv) : true);
+ *fence = (struct dma_fence *)(tmp & ~DMA_RESV_LIST_MASK);
+ if (usage)
+ *usage = tmp & DMA_RESV_LIST_MASK;
+}
+
+/* Set the fence and usage flags at the specific index in the list. */
+static void dma_resv_list_set(struct dma_resv_list *list,
+ unsigned int index,
+ struct dma_fence *fence,
+ enum dma_resv_usage usage)
+{
+ long tmp = ((long)fence) | usage;
+
+ RCU_INIT_POINTER(list->table[index], (struct dma_fence *)tmp);
+}
+
+/*
* Allocate a new dma_resv_list and make sure to correctly initialize
- * shared_max.
+ * max_fences.
*/
-static struct dma_resv_list *dma_resv_list_alloc(unsigned int shared_max)
+static struct dma_resv_list *dma_resv_list_alloc(unsigned int max_fences)
{
struct dma_resv_list *list;
- list = kmalloc(struct_size(list, shared, shared_max), GFP_KERNEL);
+ list = kmalloc(struct_size(list, table, max_fences), GFP_KERNEL);
if (!list)
return NULL;
- list->shared_max = (ksize(list) - offsetof(typeof(*list), shared)) /
- sizeof(*list->shared);
+ list->max_fences = (ksize(list) - offsetof(typeof(*list), table)) /
+ sizeof(*list->table);
return list;
}
-/**
- * dma_resv_list_free - free fence list
- * @list: list to free
- *
- * Free a dma_resv_list and make sure to drop all references.
- */
+/* Free a dma_resv_list and make sure to drop all references. */
static void dma_resv_list_free(struct dma_resv_list *list)
{
unsigned int i;
@@ -97,9 +117,12 @@ static void dma_resv_list_free(struct dma_resv_list *list)
if (!list)
return;
- for (i = 0; i < list->shared_count; ++i)
- dma_fence_put(rcu_dereference_protected(list->shared[i], true));
+ for (i = 0; i < list->num_fences; ++i) {
+ struct dma_fence *fence;
+ dma_resv_list_entry(list, i, NULL, &fence, NULL);
+ dma_fence_put(fence);
+ }
kfree_rcu(list, rcu);
}
@@ -112,8 +135,7 @@ void dma_resv_init(struct dma_resv *obj)
ww_mutex_init(&obj->lock, &reservation_ww_class);
seqcount_ww_mutex_init(&obj->seq, &obj->lock);
- RCU_INIT_POINTER(obj->fence, NULL);
- RCU_I
[Intel-gfx] [PATCH 08/15] RDMA: use DMA_RESV_USAGE_KERNEL
We only need to wait for kernel submissions here. Signed-off-by: Christian König Reviewed-by: Daniel Vetter --- drivers/infiniband/core/umem_dmabuf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/core/umem_dmabuf.c b/drivers/infiniband/core/umem_dmabuf.c index f9901d273b8e..fce80a4a5147 100644 --- a/drivers/infiniband/core/umem_dmabuf.c +++ b/drivers/infiniband/core/umem_dmabuf.c @@ -68,7 +68,7 @@ int ib_umem_dmabuf_map_pages(struct ib_umem_dmabuf *umem_dmabuf) * the migration. */ return dma_resv_wait_timeout(umem_dmabuf->attach->dmabuf->resv, -DMA_RESV_USAGE_WRITE, +DMA_RESV_USAGE_KERNEL, false, MAX_SCHEDULE_TIMEOUT); } EXPORT_SYMBOL(ib_umem_dmabuf_map_pages); -- 2.25.1
[Intel-gfx] [PATCH 02/15] dma-buf: specify usage while adding fences to dma_resv obj v7
Instead of distingting between shared and exclusive fences specify
the fence usage while adding fences.
Rework all drivers to use this interface instead and deprecate the old one.
v2: some kerneldoc comments suggested by Daniel
v3: fix a missing case in radeon
v4: rebase on nouveau changes, fix lockdep and temporary disable warning
v5: more documentation updates
v6: separate internal dma_resv changes from this patch, avoids to
disable warning temporary, rebase on upstream changes
v7: fix missed case in lima driver, minimize changes to i915_gem_busy_ioctl
Signed-off-by: Christian König
---
drivers/dma-buf/dma-resv.c| 48 +++--
drivers/dma-buf/st-dma-resv.c | 101 +-
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 6 +-
drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 10 +-
drivers/gpu/drm/i915/gem/i915_gem_busy.c | 6 +-
drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 5 +-
.../drm/i915/gem/selftests/i915_gem_migrate.c | 4 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 3 +-
drivers/gpu/drm/i915/i915_vma.c | 8 +-
.../drm/i915/selftests/intel_memory_region.c | 3 +-
drivers/gpu/drm/lima/lima_gem.c | 7 +-
drivers/gpu/drm/msm/msm_gem_submit.c | 6 +-
drivers/gpu/drm/nouveau/nouveau_bo.c | 9 +-
drivers/gpu/drm/nouveau/nouveau_fence.c | 4 +-
drivers/gpu/drm/panfrost/panfrost_job.c | 2 +-
drivers/gpu/drm/qxl/qxl_release.c | 3 +-
drivers/gpu/drm/radeon/radeon_object.c| 6 +-
drivers/gpu/drm/ttm/ttm_bo.c | 2 +-
drivers/gpu/drm/ttm/ttm_bo_util.c | 5 +-
drivers/gpu/drm/ttm/ttm_execbuf_util.c| 6 +-
drivers/gpu/drm/v3d/v3d_gem.c | 4 +-
drivers/gpu/drm/vc4/vc4_gem.c | 2 +-
drivers/gpu/drm/vgem/vgem_fence.c | 9 +-
drivers/gpu/drm/virtio/virtgpu_gem.c | 3 +-
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c| 3 +-
include/linux/dma-buf.h | 16 +--
include/linux/dma-resv.h | 25 +++--
30 files changed, 149 insertions(+), 166 deletions(-)
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index 17237e6ee30c..543dae6566d2 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -234,14 +234,14 @@ EXPORT_SYMBOL(dma_resv_reserve_fences);
#ifdef CONFIG_DEBUG_MUTEXES
/**
- * dma_resv_reset_shared_max - reset shared fences for debugging
+ * dma_resv_reset_max_fences - reset shared fences for debugging
* @obj: the dma_resv object to reset
*
* Reset the number of pre-reserved shared slots to test that drivers do
* correct slot allocation using dma_resv_reserve_fences(). See also
* &dma_resv_list.shared_max.
*/
-void dma_resv_reset_shared_max(struct dma_resv *obj)
+void dma_resv_reset_max_fences(struct dma_resv *obj)
{
struct dma_resv_list *fences = dma_resv_shared_list(obj);
@@ -251,7 +251,7 @@ void dma_resv_reset_shared_max(struct dma_resv *obj)
if (fences)
fences->shared_max = fences->shared_count;
}
-EXPORT_SYMBOL(dma_resv_reset_shared_max);
+EXPORT_SYMBOL(dma_resv_reset_max_fences);
#endif
/**
@@ -264,7 +264,8 @@ EXPORT_SYMBOL(dma_resv_reset_shared_max);
*
* See also &dma_resv.fence for a discussion of the semantics.
*/
-void dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence)
+static void dma_resv_add_shared_fence(struct dma_resv *obj,
+ struct dma_fence *fence)
{
struct dma_resv_list *fobj;
struct dma_fence *old;
@@ -305,13 +306,13 @@ void dma_resv_add_shared_fence(struct dma_resv *obj,
struct dma_fence *fence)
write_seqcount_end(&obj->seq);
dma_fence_put(old);
}
-EXPORT_SYMBOL(dma_resv_add_shared_fence);
/**
* dma_resv_replace_fences - replace fences in the dma_resv obj
* @obj: the reservation object
* @context: the context of the fences to replace
* @replacement: the new fence to use instead
+ * @usage: how the new fence is used, see enum dma_resv_usage
*
* Replace fences with a specified context with a new fence. Only valid if the
* operation represented by the original fence has no longer access to the
@@ -321,12 +322,16 @@ EXPORT_SYMBOL(dma_resv_add_shared_fence);
* update fence which makes the resource inaccessible.
*/
void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context,
-struct dma_fence *replacement)
+struct dma_fence *replacement,
+enum dma_resv_usage usage)
{
struct dma_resv_list *list;
struct dma_fence *old;
unsigned int i;
+ /* Only readers supported for now */
+ W
[Intel-gfx] [PATCH 11/15] dma-buf: wait for map to complete for static attachments
We have previously done that in the individual drivers but it is
more defensive to move that into the common code.
Dynamic attachments should wait for map operations to complete by themselves.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
---
drivers/dma-buf/dma-buf.c | 18 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 14 +-
drivers/gpu/drm/nouveau/nouveau_prime.c | 17 +
drivers/gpu/drm/radeon/radeon_prime.c | 16 +++-
4 files changed, 20 insertions(+), 45 deletions(-)
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index 1cddb65eafda..79795857be3e 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -661,12 +661,24 @@ static struct sg_table * __map_dma_buf(struct
dma_buf_attachment *attach,
enum dma_data_direction direction)
{
struct sg_table *sg_table;
+ signed long ret;
sg_table = attach->dmabuf->ops->map_dma_buf(attach, direction);
+ if (IS_ERR_OR_NULL(sg_table))
+ return sg_table;
+
+ if (!dma_buf_attachment_is_dynamic(attach)) {
+ ret = dma_resv_wait_timeout(attach->dmabuf->resv,
+ DMA_RESV_USAGE_KERNEL, true,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret < 0) {
+ attach->dmabuf->ops->unmap_dma_buf(attach, sg_table,
+ direction);
+ return ERR_PTR(ret);
+ }
+ }
- if (!IS_ERR_OR_NULL(sg_table))
- mangle_sg_table(sg_table);
-
+ mangle_sg_table(sg_table);
return sg_table;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index 579adfafe4d0..782cbca37538 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
@@ -102,21 +102,9 @@ static int amdgpu_dma_buf_pin(struct dma_buf_attachment
*attach)
{
struct drm_gem_object *obj = attach->dmabuf->priv;
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
- int r;
/* pin buffer into GTT */
- r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
- if (r)
- return r;
-
- if (bo->tbo.moving) {
- r = dma_fence_wait(bo->tbo.moving, true);
- if (r) {
- amdgpu_bo_unpin(bo);
- return r;
- }
- }
- return 0;
+ return amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
}
/**
diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c
b/drivers/gpu/drm/nouveau/nouveau_prime.c
index 60019d0532fc..347488685f74 100644
--- a/drivers/gpu/drm/nouveau/nouveau_prime.c
+++ b/drivers/gpu/drm/nouveau/nouveau_prime.c
@@ -93,22 +93,7 @@ int nouveau_gem_prime_pin(struct drm_gem_object *obj)
if (ret)
return -EINVAL;
- ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
- if (ret)
- goto error;
-
- if (nvbo->bo.moving)
- ret = dma_fence_wait(nvbo->bo.moving, true);
-
- ttm_bo_unreserve(&nvbo->bo);
- if (ret)
- goto error;
-
- return ret;
-
-error:
- nouveau_bo_unpin(nvbo);
- return ret;
+ return 0;
}
void nouveau_gem_prime_unpin(struct drm_gem_object *obj)
diff --git a/drivers/gpu/drm/radeon/radeon_prime.c
b/drivers/gpu/drm/radeon/radeon_prime.c
index 4a90807351e7..42a87948e28c 100644
--- a/drivers/gpu/drm/radeon/radeon_prime.c
+++ b/drivers/gpu/drm/radeon/radeon_prime.c
@@ -77,19 +77,9 @@ int radeon_gem_prime_pin(struct drm_gem_object *obj)
/* pin buffer into GTT */
ret = radeon_bo_pin(bo, RADEON_GEM_DOMAIN_GTT, NULL);
- if (unlikely(ret))
- goto error;
-
- if (bo->tbo.moving) {
- ret = dma_fence_wait(bo->tbo.moving, false);
- if (unlikely(ret)) {
- radeon_bo_unpin(bo);
- goto error;
- }
- }
-
- bo->prime_shared_count++;
-error:
+ if (likely(ret == 0))
+ bo->prime_shared_count++;
+
radeon_bo_unreserve(bo);
return ret;
}
--
2.25.1
[Intel-gfx] [PATCH 14/15] dma-buf: drop seq count based update
This should be possible now since we don't have the distinction
between exclusive and shared fences any more.
The only possible pitfall is that a dma_fence would be reused during the
RCU grace period, but even that could be handled with a single extra check.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
---
drivers/dma-buf/dma-resv.c| 33 -
drivers/dma-buf/st-dma-resv.c | 2 +-
include/linux/dma-resv.h | 12
3 files changed, 13 insertions(+), 34 deletions(-)
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index 5b64aa554c36..0cce6e4ec946 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -133,7 +133,6 @@ static void dma_resv_list_free(struct dma_resv_list *list)
void dma_resv_init(struct dma_resv *obj)
{
ww_mutex_init(&obj->lock, &reservation_ww_class);
- seqcount_ww_mutex_init(&obj->seq, &obj->lock);
RCU_INIT_POINTER(obj->fences, NULL);
}
@@ -292,28 +291,24 @@ void dma_resv_add_fence(struct dma_resv *obj, struct
dma_fence *fence,
fobj = dma_resv_fences_list(obj);
count = fobj->num_fences;
- write_seqcount_begin(&obj->seq);
-
for (i = 0; i < count; ++i) {
enum dma_resv_usage old_usage;
dma_resv_list_entry(fobj, i, obj, &old, &old_usage);
if ((old->context == fence->context && old_usage >= usage) ||
- dma_fence_is_signaled(old))
- goto replace;
+ dma_fence_is_signaled(old)) {
+ dma_resv_list_set(fobj, i, fence, usage);
+ dma_fence_put(old);
+ return;
+ }
}
BUG_ON(fobj->num_fences >= fobj->max_fences);
- old = NULL;
count++;
-replace:
dma_resv_list_set(fobj, i, fence, usage);
/* pointer update must be visible before we extend the num_fences */
smp_store_mb(fobj->num_fences, count);
-
- write_seqcount_end(&obj->seq);
- dma_fence_put(old);
}
EXPORT_SYMBOL(dma_resv_add_fence);
@@ -341,7 +336,6 @@ void dma_resv_replace_fences(struct dma_resv *obj, uint64_t
context,
dma_resv_assert_held(obj);
list = dma_resv_fences_list(obj);
- write_seqcount_begin(&obj->seq);
for (i = 0; list && i < list->num_fences; ++i) {
struct dma_fence *old;
@@ -352,14 +346,12 @@ void dma_resv_replace_fences(struct dma_resv *obj,
uint64_t context,
dma_resv_list_set(list, i, replacement, usage);
dma_fence_put(old);
}
- write_seqcount_end(&obj->seq);
}
EXPORT_SYMBOL(dma_resv_replace_fences);
/* Restart the unlocked iteration by initializing the cursor object. */
static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor)
{
- cursor->seq = read_seqcount_begin(&cursor->obj->seq);
cursor->index = 0;
cursor->num_fences = 0;
cursor->fences = dma_resv_fences_list(cursor->obj);
@@ -388,8 +380,10 @@ static void dma_resv_iter_walk_unlocked(struct
dma_resv_iter *cursor)
cursor->obj, &cursor->fence,
&cursor->fence_usage);
cursor->fence = dma_fence_get_rcu(cursor->fence);
- if (!cursor->fence)
- break;
+ if (!cursor->fence) {
+ dma_resv_iter_restart_unlocked(cursor);
+ continue;
+ }
if (!dma_fence_is_signaled(cursor->fence) &&
cursor->usage >= cursor->fence_usage)
@@ -415,7 +409,7 @@ struct dma_fence *dma_resv_iter_first_unlocked(struct
dma_resv_iter *cursor)
do {
dma_resv_iter_restart_unlocked(cursor);
dma_resv_iter_walk_unlocked(cursor);
- } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq));
+ } while (dma_resv_fences_list(cursor->obj) != cursor->fences);
rcu_read_unlock();
return cursor->fence;
@@ -438,13 +432,13 @@ struct dma_fence *dma_resv_iter_next_unlocked(struct
dma_resv_iter *cursor)
rcu_read_lock();
cursor->is_restarted = false;
- restart = read_seqcount_retry(&cursor->obj->seq, cursor->seq);
+ restart = dma_resv_fences_list(cursor->obj) != cursor->fences;
do {
if (restart)
dma_resv_iter_restart_unlocked(cursor);
dma_resv_iter_walk_unlocked(cursor);
restart = true;
- } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq));
+ } while (dma_resv_fences_list(cursor->obj) != cursor->fences);
rcu_read_unlock();
return cursor->fence;
@@ -540,10 +534,7 @@ int dma_resv_copy_fences(struct dma_resv *dst, struct
dma_resv *src)
}
dma_resv_iter_end(&cursor);
- write_seqcount_begin(&dst->seq);
[Intel-gfx] [PATCH 07/15] drm/nouveau: only wait for kernel fences in nouveau_bo_vm_cleanup
Don't wait for user space submissions. I'm not 100% sure if that is correct, but it seems to match what the code initially intended. Signed-off-by: Christian König --- drivers/gpu/drm/nouveau/nouveau_bo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 05076e530e7d..13deb6c70ba6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -962,10 +962,10 @@ nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, struct dma_fence *fence; int ret; - ret = dma_resv_get_singleton(bo->base.resv, DMA_RESV_USAGE_WRITE, + ret = dma_resv_get_singleton(bo->base.resv, DMA_RESV_USAGE_KERNEL, &fence); if (ret) - dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_WRITE, + dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_KERNEL, false, MAX_SCHEDULE_TIMEOUT); nv10_bo_put_tile_region(dev, *old_tile, fence); -- 2.25.1
[Intel-gfx] [PATCH 04/15] dma-buf: add DMA_RESV_USAGE_KERNEL v3
Add an usage for kernel submissions. Waiting for those are mandatory for
dynamic DMA-bufs.
As a precaution this patch also changes all occurrences where fences are
added as part of memory management in TTM, VMWGFX and i915 to use the
new value because it now becomes possible for drivers to ignore fences
with the WRITE usage.
v2: use "must" in documentation, fix whitespaces
v3: separate out some driver changes and better document why some
changes should still be part of this patch.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
---
drivers/dma-buf/dma-resv.c | 2 +-
drivers/dma-buf/st-dma-resv.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 2 +-
drivers/gpu/drm/ttm/ttm_bo.c| 2 +-
drivers/gpu/drm/ttm/ttm_bo_util.c | 4 ++--
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 2 +-
include/linux/dma-resv.h| 24 ++---
7 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index 378d47e1cfea..f4860e5f2d8b 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -726,7 +726,7 @@ EXPORT_SYMBOL_GPL(dma_resv_test_signaled);
*/
void dma_resv_describe(struct dma_resv *obj, struct seq_file *seq)
{
- static const char *usage[] = { "write", "read" };
+ static const char *usage[] = { "kernel", "write", "read" };
struct dma_resv_iter cursor;
struct dma_fence *fence;
diff --git a/drivers/dma-buf/st-dma-resv.c b/drivers/dma-buf/st-dma-resv.c
index d0f7c2bfd4f0..062b57d63fa6 100644
--- a/drivers/dma-buf/st-dma-resv.c
+++ b/drivers/dma-buf/st-dma-resv.c
@@ -296,7 +296,7 @@ int dma_resv(void)
int r;
spin_lock_init(&fence_lock);
- for (usage = DMA_RESV_USAGE_WRITE; usage <= DMA_RESV_USAGE_READ;
+ for (usage = DMA_RESV_USAGE_KERNEL; usage <= DMA_RESV_USAGE_READ;
++usage) {
r = subtests(tests, (void *)(unsigned long)usage);
if (r)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
index f5f2b8b115ea..0512afdd20d8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
@@ -117,7 +117,7 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj,
i915_fence_timeout(i915),
I915_FENCE_GFP);
dma_resv_add_fence(obj->base.resv, &clflush->base.dma,
- DMA_RESV_USAGE_WRITE);
+ DMA_RESV_USAGE_KERNEL);
dma_fence_work_commit(&clflush->base);
/*
* We must have successfully populated the pages(since we are
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index d74f9eea855e..6bf3fb1c8045 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -739,7 +739,7 @@ static int ttm_bo_add_move_fence(struct ttm_buffer_object
*bo,
return ret;
}
- dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_WRITE);
+ dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_KERNEL);
ret = dma_resv_reserve_fences(bo->base.resv, 1);
if (unlikely(ret)) {
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 7a96a1db13a7..99deb45894f4 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -508,7 +508,7 @@ static int ttm_bo_move_to_ghost(struct ttm_buffer_object
*bo,
return ret;
dma_resv_add_fence(&ghost_obj->base._resv, fence,
- DMA_RESV_USAGE_WRITE);
+ DMA_RESV_USAGE_KERNEL);
/**
* If we're not moving to fixed memory, the TTM object
@@ -562,7 +562,7 @@ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
struct ttm_resource_manager *man = ttm_manager_type(bdev,
new_mem->mem_type);
int ret = 0;
- dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_WRITE);
+ dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_KERNEL);
if (!evict)
ret = ttm_bo_move_to_ghost(bo, fence, man->use_tt);
else if (!from->use_tt && pipeline)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
index bec50223efe5..408ede1f967f 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
@@ -759,7 +759,7 @@ void vmw_bo_fence_single(struct ttm_buffer_object *bo,
ret = dma_resv_reserve_fences(bo->base.resv, 1);
if (!ret)
dma_resv_add_fence(bo->base.resv, &fence->base,
- DMA_RESV_USAGE_WRITE);
+ DMA_RESV_USAGE_KERNEL);
else
/* Last re
[Intel-gfx] [PATCH 05/15] drm/amdgpu: use DMA_RESV_USAGE_KERNEL
Wait only for kernel fences before kmap or UVD direct submission.
This also makes sure that we always wait in amdgpu_bo_kmap() even when
returning a cached pointer.
Signed-off-by: Christian König
Acked-by: Daniel Vetter
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c| 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index a3cdf8a24377..5832c05ab10d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -761,6 +761,11 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
return -EPERM;
+ r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL,
+ false, MAX_SCHEDULE_TIMEOUT);
+ if (r < 0)
+ return r;
+
kptr = amdgpu_bo_kptr(bo);
if (kptr) {
if (ptr)
@@ -768,11 +773,6 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
return 0;
}
- r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_WRITE,
- false, MAX_SCHEDULE_TIMEOUT);
- if (r < 0)
- return r;
-
r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.resource->num_pages, &bo->kmap);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 3654326219e0..6eac649499d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -1164,7 +1164,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring,
struct amdgpu_bo *bo,
if (direct) {
r = dma_resv_wait_timeout(bo->tbo.base.resv,
- DMA_RESV_USAGE_WRITE, false,
+ DMA_RESV_USAGE_KERNEL, false,
msecs_to_jiffies(10));
if (r == 0)
r = -ETIMEDOUT;
--
2.25.1
[Intel-gfx] [PATCH 06/15] drm/radeon: use DMA_RESV_USAGE_KERNEL
Always wait for kernel fences before kmap and not only for UVD kmaps.
Signed-off-by: Christian König
Acked-by: Daniel Vetter
---
drivers/gpu/drm/radeon/radeon_object.c | 7 ++-
drivers/gpu/drm/radeon/radeon_uvd.c| 12 ++--
2 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_object.c
b/drivers/gpu/drm/radeon/radeon_object.c
index cb5c4aa45cef..6c4a6802ca96 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -219,7 +219,12 @@ int radeon_bo_create(struct radeon_device *rdev,
int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
{
bool is_iomem;
- int r;
+ long r;
+
+ r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL,
+ false, MAX_SCHEDULE_TIMEOUT);
+ if (r < 0)
+ return r;
if (bo->kptr) {
if (ptr) {
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c
b/drivers/gpu/drm/radeon/radeon_uvd.c
index a50750740ab0..a2cda184b2b2 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -470,24 +470,16 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p,
struct radeon_bo *bo,
int32_t *msg, msg_type, handle;
unsigned img_size = 0;
void *ptr;
- long r;
- int i;
+ int i, r;
if (offset & 0x3F) {
DRM_ERROR("UVD messages must be 64 byte aligned!\n");
return -EINVAL;
}
- r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_WRITE,
- false, MAX_SCHEDULE_TIMEOUT);
- if (r <= 0) {
- DRM_ERROR("Failed waiting for UVD message (%ld)!\n", r);
- return r ? r : -ETIME;
- }
-
r = radeon_bo_kmap(bo, &ptr);
if (r) {
- DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
+ DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
return r;
}
--
2.25.1
[Intel-gfx] DMA-resv usage
Hi Daniel, only patch #2 had some significant changes. The rest ist pretty much the same except for the dropped exynos change and the added cleanup for the seqlock. Thanks, Christian.
Re: [Intel-gfx] [PATCH] drm/i915/dg2: Do not explode on phy calibration error
On Sat, Apr 09, 2022 at 11:15:36PM -0700, Lucas De Marchi wrote:
> When the PHY fails on calibration we were previously skipping the ddi
> initialization. However the driver is not really prepared for that,
> ultimately leading to a NULL pointer dereference:
>
> [ 75.748348] i915 :03:00.0: [drm:intel_modeset_init_nogem [i915]] SNPS
> PHY A failed to calibrate; output will not be used.
> ...
> [ 75.750336] i915 :03:00.0: [drm:intel_modeset_setup_hw_state [i915]]
> [CRTC:80:pipe A] hw state readout: enabled
> ...
>
> ( no DDI A/PHY A )
> [ 75.753080] i915 :03:00.0: [drm:intel_modeset_setup_hw_state [i915]]
> [ENCODER:235:DDI B/PHY B] hw state readout: disabled, pipe A
> [ 75.753164] i915 :03:00.0: [drm:intel_modeset_setup_hw_state [i915]]
> [ENCODER:245:DDI C/PHY C] hw state readout: disabled, pipe A
> ...
> [ 75.754425] i915 :03:00.0: [drm] *ERROR* crtc 80: Can't calculate
> constants, dotclock = 0!
> [ 75.765558] i915 :03:00.0:
> drm_WARN_ON_ONCE(drm_drv_uses_atomic_modeset(dev))
> [ 75.765569] WARNING: CPU: 5 PID: 1759 at drivers/gpu/drm/drm_vblank.c:728
> drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x347/0x360
> ...
> [ 75.781230] BUG: kernel NULL pointer dereference, address: 007c
> [ 75.788198] #PF: supervisor read access in kernel mode
> [ 75.793347] #PF: error_code(0x) - not-present page
> [ 75.798480] PGD 0 P4D 0
> [ 75.801019] Oops: [#1] PREEMPT SMP NOPTI
> [ 75.805377] CPU: 5 PID: 1759 Comm: modprobe Tainted: GW
> 5.18.0-rc1-demarchi+ #199
> [ 75.827613] RIP: 0010:icl_aux_power_well_disable+0x3b/0x200 [i915]
> [ 75.833890] Code: 83 ec 30 65 48 8b 04 25 28 00 00 00 48 89 44 24 28 48 8b
> 06 0f b6 70 1c f6 40 20 04 8d 56 fa 0f 45 f2 e8 88 bd ff ff 48 89 ef <8b> 70
> 7c e8 ed 67 ff ff 48 89 ef 89 c6 e8 73 67 ff ff 84 c0 75 0a
> [ 75.852629] RSP: 0018:c90003a7fb30 EFLAGS: 00010246
> [ 75.857852] RAX: RBX: 8881145e8f10 RCX:
>
> [ 75.864978] RDX: 888115220840 RSI: RDI:
> 88811522
> [ 75.872106] RBP: 88811522 R08: 8ee8 R09:
> fffd
> [ 75.879234] R10: 8e20 R11: 8ed0 R12:
> 8881145e8f10
> [ 75.886363] R13: 0001 R14: 888115223240 R15:
>
> [ 75.893490] FS: 7ff6e753a740() GS:8f68()
> knlGS:
> [ 75.901573] CS: 0010 DS: ES: CR0: 80050033
> [ 75.907313] CR2: 007c CR3: 0001216a6001 CR4:
> 00770ee0
> [ 75.914446] PKRU: 5554
> [ 75.917153] Call Trace:
> [ 75.919603]
> [ 75.921709] intel_power_domains_sanitize_state+0x88/0xb0 [i915]
> [ 75.927814] intel_modeset_init_nogem+0x317/0xef0 [i915]
> [ 75.933205] i915_driver_probe+0x5f6/0xdf0 [i915]
> [ 75.937976] i915_pci_probe+0x51/0x1d0 [i915]
>
> We skip the initialization of PHY A, but later we try to find out what is the
> phy
> for that power well and dereference dig_port, which is NULL.
>
> Failing the PHY calibration could be left as a warning or error, like it
> was before commit b4eb76d82a0e ("drm/i915/dg2: Skip output init on PHY
> calibration failure"). However that often fails for outputs not being
> used, which would make the warning/error appear on systems that have no
> visible issues. Anyway, there is still a need to fix those failures,
> but that is left for later.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index cec578efc4bd..027cc4cc38d9 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4300,9 +4300,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> if (intel_phy_is_snps(dev_priv, phy) &&
> dev_priv->snps_phy_failed_calibration & BIT(phy)) {
> drm_dbg_kms(&dev_priv->drm,
> - "SNPS PHY %c failed to calibrate; output will not
> be used.\n",
> + "SNPS PHY %c failed to calibrate, proceeding
> anyway\n",
> phy_name(phy));
> - return;
> }
>
> dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
> --
> 2.35.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
Re: [Intel-gfx] [PATCH 0/4] drm/i915/dg2: Add support for render/media decompression
On Mon, Apr 11, 2022 at 04:38:16PM +0300, Jani Nikula wrote:
> On Mon, 11 Apr 2022, Imre Deak wrote:
> > Hi Rodrigo, Jani,
>
> TL;DR, all done, for details read on. ;)
>
> > On Mon, Apr 04, 2022 at 04:38:42PM +0300, Imre Deak wrote:
> >> This is a rebased version of patches 15-17 of [1], adding DG2 display
> >> engine support for decompressing render and media compressed
> >> framebuffers.
> >>
> >> The dependency patches from [1] should be merged already to drm-tip.
> >>
> >> It addresses the review comments on the modifier layout description from
> >> Nanley, updates the commit logs vs. flat CCS and Tile4 and splits out
> >> the changes adding the modifiers to drm_fourcc.h to separate patches.
> >>
> >> [1] https://patchwork.freedesktop.org/series/95686/
> >>
> >> Cc: Anshuman Gupta
> >> Cc: Ramalingam C
> >> Cc: Radhakrishna Sripada
> >> Cc: Matt Roper
> >> Cc: Mika Kahola
> >> Cc: Juha-Pekka Heikkilä
> >> Cc: Nanley Chery
> >
> > I'd like to push this patchset to drm-intel-next, but it depends on
> > https://patchwork.freedesktop.org/patch/475167/?series=100419&rev=1
>
> Please reference commits, looking that up is just an extra step for me.
>
> > which is only in drm-intel-gt-next. According to Joonas, this should be
> > resolved by backmerging drm-intel-gt-next to drm-intel-next, could you
> > help with this?
>
> To set the record straight, we don't crossmerge drm-intel-gt-next to
> drm-intel-next. The other direction is possible. These are the valid
> merges:
>
> drm-intel-next -> drm-nextfeature pull
> drm-intel-gt-next -> drm-next feature pull
> drm-next -> drm-intel-nextbackmerge
> drm-next -> drm-intel-gt-next backmerge
> drm-intel-next -> drm-intel-gt-next crossmerge
> topic/* -> * topic merge
>
> Anyway, drm-intel-gt-next with the commit in question 5e3094cfd9fb
> ("drm/i915/xehpsdv: Add has_flat_ccs to device info") has already been
> merged to drm-next and -rc1. I've done a backmerge and pushed it out.
>
> Because we don't do drm-intel-gt-next -> drm-intel-next crossmerges, it
> might be better to apply things like feature flags to drm-intel-next,
> because the route from gt back to drm-intel-next is longer.
>
> I might be prudent to trigger a retest with the new baseline before
> merging.
Ok thanks for the explanation, resent the patchset now for retesting.
> BR,
> Jani.
>
> >
> >> Anshuman Gupta (1):
> >> drm/i915/dg2: Add support for DG2 clear color compression
> >>
> >> Matt Roper (2):
> >> drm/fourcc: Introduce format modifiers for DG2 render and media
> >> compression
> >> drm/i915/dg2: Add support for DG2 render and media compression
> >>
> >> Mika Kahola (1):
> >> drm/fourcc: Introduce format modifier for DG2 clear color
> >>
> >> drivers/gpu/drm/i915/display/intel_display.c | 4 +-
> >> drivers/gpu/drm/i915/display/intel_fb.c | 53 +++
> >> .../drm/i915/display/skl_universal_plane.c| 49 +
> >> include/uapi/drm/drm_fourcc.h | 36 +
> >> 4 files changed, 122 insertions(+), 20 deletions(-)
> >>
> >> --
> >> 2.30.2
> >>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH v2 4/4] drm/i915/dg2: Add support for DG2 clear color compression
From: Juha-Pekka Heikkilä
Add support for the DG2 specific render compression with clear color
framebuffer format.
DG2 onwards discrete gfx has support for new flat CCS mapping,
which brings in display feature in to avoid Aux walk for compressed
surface. This support build on top of Flat CCS support added in XEHPSDV.
FLAT CCS surface base address should be 64k aligned,
Compressed displayable surfaces must use tile4 format.
HAS: 1407880786
B.Spec : 7655
B.Spec : 53902
v2: Merge all bits required for the support of functionality into this
patch from the patch adding the corresponding modifier.
Cc: Mika Kahola
Signed-off-by: Anshuman Gupta
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Ramalingam C
Signed-off-by: Imre Deak
Acked-by: Anshuman Gupta
Reviewed-by: Imre Deak
Link:
https://patchwork.freedesktop.org/patch/msgid/20220404133846.131401-5-imre.d...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
drivers/gpu/drm/i915/display/intel_fb.c | 40 ++-
.../drm/i915/display/skl_universal_plane.c| 25
3 files changed, 52 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index eee185ed41c3e..ca997a0a05174 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8477,7 +8477,9 @@ static void
intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
/*
* The layout of the fast clear color value expected by HW
-* (the DRM ABI requiring this value to be located in fb at
offset 0 of plane#2):
+* (the DRM ABI requiring this value to be located in fb at
+* offset 0 of cc plane, plane #2 previous generations or
+* plane #1 for flat ccs):
* - 4 x 4 bytes per-channel value
* (in surface type specific float/int format provided by the
fb user)
* - 8 bytes native color value used by the display
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 447003a91160e..9f5a6b79e95b5 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -107,6 +107,21 @@ static const struct drm_format_info gen12_ccs_cc_formats[]
= {
.hsub = 1, .vsub = 1, .has_alpha = true },
};
+static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
+ .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, },
+ { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
+ .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, },
+ { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
+ .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
+ .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+};
+
struct intel_modifier_desc {
u64 modifier;
struct {
@@ -144,6 +159,14 @@ static const struct intel_modifier_desc intel_modifiers[]
= {
.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
.display_ver = { 13, 13 },
.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
+ }, {
+ .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
+ .display_ver = { 13, 13 },
+ .plane_caps = INTEL_PLANE_CAP_TILING_4 |
INTEL_PLANE_CAP_CCS_RC_CC,
+
+ .ccs.cc_planes = BIT(1),
+
+ FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats),
}, {
.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
.display_ver = { 13, 13 },
@@ -393,17 +416,13 @@ bool intel_fb_plane_supports_modifier(struct intel_plane
*plane, u64 modifier)
static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md,
const struct drm_format_info *info)
{
- int yuv_planes;
-
if (!info->is_yuv)
return false;
- if (plane_caps_contain_any(md->plane_caps, INTEL_PLANE_CAP_CCS_MASK))
- yuv_planes = 4;
+ if (hweight8(md->ccs.planar_aux_planes) == 2)
+ return info->num_planes == 4;
else
- yuv_planes = 2;
-
- return info->num_planes == yuv_planes;
+ return info->num_planes == 2;
}
/**
@@ -528,12 +547,13 @@ static unsigned int gen12_ccs_aux_stride(struct
intel_framebuffer *fb, int ccs_p
int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
{
+ const st
[Intel-gfx] [PATCH v2 3/4] drm/fourcc: Introduce format modifier for DG2 clear color
From: Mika Kahola
DG2 clear color render compression uses Tile4 layout. Therefore, we need
to define a new format modifier for uAPI to support clear color rendering.
v2:
Display version is fixed. [Imre]
KDoc is enhanced for cc modifier. [Nanley & Lionel]
v3:
Split out the modifier addition to a separate patch.
Clarify the modifier layout description.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Mika Kahola
cc: Anshuman Gupta
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Ramalingam C
Signed-off-by: Imre Deak
Acked-by: Nanley Chery
Reviewed-by: Juha-Pekka Heikkila
Acked-by: Maarten Lankhorst
Link:
https://patchwork.freedesktop.org/patch/msgid/20220404133846.131401-4-imre.d...@intel.com
---
include/uapi/drm/drm_fourcc.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 4a5117715db3c..e5074162bcdd4 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -605,6 +605,20 @@ extern "C" {
*/
#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for DG2 render
compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. The CCS data is stored
+ * outside of the GEM object in a reserved memory area dedicated for the
+ * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
+ * main surface pitch is required to be a multiple of four Tile 4 widths. The
+ * clear color is stored at plane index 1 and the pitch should be ignored. The
+ * format of the 256 bits of clear color data matches the one used for the
+ * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
+ * for details.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.30.2
[Intel-gfx] [PATCH v2 2/4] drm/i915/dg2: Add support for DG2 render and media compression
From: Matt Roper
Add support for DG2 render and media compression, for the description of
buffer layouts see the previous patch adding the corresponding
frame buffer modifiers.
v2:
Display version fix [Imre]
v3:
Split out modifier addition to separate patch.
Signed-off-by: Matt Roper
cc: Radhakrishna Sripada
Signed-off-by: Mika Kahola
cc: Anshuman Gupta
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Ramalingam C
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
Link:
https://patchwork.freedesktop.org/patch/msgid/20220404133846.131401-3-imre.d...@intel.com
---
drivers/gpu/drm/i915/display/intel_fb.c | 13 ++
.../drm/i915/display/skl_universal_plane.c| 26 ---
2 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index e9ad142ac40fa..447003a91160e 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -141,6 +141,14 @@ struct intel_modifier_desc {
static const struct intel_modifier_desc intel_modifiers[] = {
{
+ .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
+ .display_ver = { 13, 13 },
+ .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
+ }, {
+ .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
+ .display_ver = { 13, 13 },
+ .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
+ }, {
.modifier = I915_FORMAT_MOD_4_TILED,
.display_ver = { 13, 13 },
.plane_caps = INTEL_PLANE_CAP_TILING_4,
@@ -550,6 +558,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
return 128;
else
return 512;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
case I915_FORMAT_MOD_4_TILED:
/*
* Each 4K tile consists of 64B(8*8) subtiles, with
@@ -752,6 +762,9 @@ unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
case I915_FORMAT_MOD_4_TILED:
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+ return 16 * 1024;
default:
MISSING_CASE(fb->modifier);
return 0;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index c57fca1fe6788..b939c503bc6ff 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -773,6 +773,14 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_Y;
case I915_FORMAT_MOD_4_TILED:
return PLANE_CTL_TILED_4;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ return PLANE_CTL_TILED_4 |
+ PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+ PLANE_CTL_CLEAR_COLOR_DISABLE;
+ case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+ return PLANE_CTL_TILED_4 |
+ PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
+ PLANE_CTL_CLEAR_COLOR_DISABLE;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y |
PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -2168,6 +2176,10 @@ static bool gen12_plane_has_mc_ccs(struct
drm_i915_private *i915,
if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
return false;
+ /* Wa_14013215631 */
+ if (IS_DG2_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+ return false;
+
return plane_id < PLANE_SPRITE4;
}
@@ -2415,9 +2427,10 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
case PLANE_CTL_TILED_Y:
plane_config->tiling = I915_TILING_Y;
if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = DISPLAY_VER(dev_priv) >= 12 ?
- I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
- I915_FORMAT_MOD_Y_TILED_CCS;
+ if (DISPLAY_VER(dev_priv) >= 12)
+ fb->modifier =
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
+ else
+ fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
else
@@ -2425,7 +2438,12 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
break;
case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
if (HAS_4TILE(dev_priv)) {
-
[Intel-gfx] [PATCH v2 1/4] drm/fourcc: Introduce format modifiers for DG2 render and media compression
From: Matt Roper
The render/media engines on DG2 unify render compression and media
compression into a single format for the first time, using the Tile 4
layout for main surfaces. The compression algorithm is different from
any previous platform and the display engine must still be configured to
decompress either a render or media compressed surface; as such, we
need new RC and MC framebuffer modifiers to represent buffers in this
format.
v2: Clarify modifier layout description.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Matt Roper
Signed-off-by: Imre Deak
Acked-by: Nanley Chery
Reviewed-by: Juha-Pekka Heikkila
Acked-by: Maarten Lankhorst
Link:
https://patchwork.freedesktop.org/patch/msgid/20220404133846.131401-2-imre.d...@intel.com
---
include/uapi/drm/drm_fourcc.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index b73fe6797fc37..4a5117715db3c 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -583,6 +583,28 @@ extern "C" {
*/
#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
+/*
+ * Intel color control surfaces (CCS) for DG2 render compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. The CCS data is stored
+ * outside of the GEM object in a reserved memory area dedicated for the
+ * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
+ * main surface pitch is required to be a multiple of four Tile 4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
+
+/*
+ * Intel color control surfaces (CCS) for DG2 media compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. For semi-planar formats
+ * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
+ * 0 and 1, respectively. The CCS for all planes are stored outside of the
+ * GEM object in a reserved memory area dedicated for the storage of the
+ * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
+ * pitch is required to be a multiple of four Tile 4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.30.2
[Intel-gfx] [PATCH v2 0/4] drm/i915/dg2: Add support for render/media decompression
This is v2 of [1] amending the authorship and commit log in patch 4 and adding the r-bs, acks. Resending for CI as well for retesting on drm-tip where the dependency patchset [2] is now also part of the drm-intel-next branch. [1] https://patchwork.freedesktop.org/series/102147/ [2] https://patchwork.freedesktop.org/series/100419/ Cc: Anshuman Gupta Cc: Ramalingam C Cc: Radhakrishna Sripada Cc: Matt Roper Cc: Mika Kahola Cc: Juha-Pekka Heikkilä Cc: Nanley Chery Cc: Jani Nikula Juha-Pekka Heikkilä (1): drm/i915/dg2: Add support for DG2 clear color compression Matt Roper (2): drm/fourcc: Introduce format modifiers for DG2 render and media compression drm/i915/dg2: Add support for DG2 render and media compression Mika Kahola (1): drm/fourcc: Introduce format modifier for DG2 clear color drivers/gpu/drm/i915/display/intel_display.c | 4 +- drivers/gpu/drm/i915/display/intel_fb.c | 53 +++ .../drm/i915/display/skl_universal_plane.c| 49 + include/uapi/drm/drm_fourcc.h | 36 + 4 files changed, 122 insertions(+), 20 deletions(-) -- 2.30.2
[Intel-gfx] [PATCH 34/34] vfio/mdev: Remove mdev drvdata
From: Jason Gunthorpe
This is no longer used, remove it.
All usages were moved over to either use container_of() from a vfio_device
or to use dev_drvdata() directly on the mdev.
Signed-off-by: Jason Gunthorpe
Signed-off-by: Christoph Hellwig
---
include/linux/mdev.h | 9 -
1 file changed, 9 deletions(-)
diff --git a/include/linux/mdev.h b/include/linux/mdev.h
index 1f6f57a3c3168..bb539794f54a8 100644
--- a/include/linux/mdev.h
+++ b/include/linux/mdev.h
@@ -15,7 +15,6 @@ struct mdev_type;
struct mdev_device {
struct device dev;
guid_t uuid;
- void *driver_data;
struct list_head next;
struct mdev_type *type;
bool active;
@@ -66,14 +65,6 @@ struct mdev_driver {
struct device_driver driver;
};
-static inline void *mdev_get_drvdata(struct mdev_device *mdev)
-{
- return mdev->driver_data;
-}
-static inline void mdev_set_drvdata(struct mdev_device *mdev, void *data)
-{
- mdev->driver_data = data;
-}
static inline const guid_t *mdev_uuid(struct mdev_device *mdev)
{
return &mdev->uuid;
--
2.30.2
[Intel-gfx] [PATCH 33/34] vfio/mdev: Use the driver core to create the 'remove' file
From: Jason Gunthorpe
The device creator is supposed to use the dev.groups value to add sysfs
files before device_add is called, not call sysfs_create_files() after
device_add() returns. This creates a race with uevent delivery where the
extra attribute will not be visible.
This was being done because the groups had been co-opted by the mdev
driver, now that prior patches have moved the driver's groups to the
struct device_driver the dev.group is properly free for use here.
Signed-off-by: Jason Gunthorpe
Signed-off-by: Christoph Hellwig
---
drivers/vfio/mdev/mdev_core.c| 1 +
drivers/vfio/mdev/mdev_private.h | 2 ++
drivers/vfio/mdev/mdev_sysfs.c | 19 ++-
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
index 19a20ff420b7f..b8b9e7911e559 100644
--- a/drivers/vfio/mdev/mdev_core.c
+++ b/drivers/vfio/mdev/mdev_core.c
@@ -269,6 +269,7 @@ int mdev_device_create(struct mdev_type *type, const guid_t
*uuid)
mdev->dev.parent = parent->dev;
mdev->dev.bus = &mdev_bus_type;
mdev->dev.release = mdev_device_release;
+ mdev->dev.groups = mdev_device_groups;
mdev->type = type;
/* Pairs with the put in mdev_device_release() */
kobject_get(&type->kobj);
diff --git a/drivers/vfio/mdev/mdev_private.h b/drivers/vfio/mdev/mdev_private.h
index 5a7ffd4e770fd..7c9fc79f3d838 100644
--- a/drivers/vfio/mdev/mdev_private.h
+++ b/drivers/vfio/mdev/mdev_private.h
@@ -32,6 +32,8 @@ struct mdev_type {
unsigned int type_group_id;
};
+extern const struct attribute_group *mdev_device_groups[];
+
#define to_mdev_type_attr(_attr) \
container_of(_attr, struct mdev_type_attribute, attr)
#define to_mdev_type(_kobj)\
diff --git a/drivers/vfio/mdev/mdev_sysfs.c b/drivers/vfio/mdev/mdev_sysfs.c
index 5a3873d1a275a..0ccfeb3dda245 100644
--- a/drivers/vfio/mdev/mdev_sysfs.c
+++ b/drivers/vfio/mdev/mdev_sysfs.c
@@ -244,11 +244,20 @@ static ssize_t remove_store(struct device *dev, struct
device_attribute *attr,
static DEVICE_ATTR_WO(remove);
-static const struct attribute *mdev_device_attrs[] = {
+static struct attribute *mdev_device_attrs[] = {
&dev_attr_remove.attr,
NULL,
};
+static const struct attribute_group mdev_device_group = {
+ .attrs = mdev_device_attrs,
+};
+
+const struct attribute_group *mdev_device_groups[] = {
+ &mdev_device_group,
+ NULL
+};
+
int mdev_create_sysfs_files(struct mdev_device *mdev)
{
struct mdev_type *type = mdev->type;
@@ -262,15 +271,8 @@ int mdev_create_sysfs_files(struct mdev_device *mdev)
ret = sysfs_create_link(kobj, &type->kobj, "mdev_type");
if (ret)
goto type_link_failed;
-
- ret = sysfs_create_files(kobj, mdev_device_attrs);
- if (ret)
- goto create_files_failed;
-
return ret;
-create_files_failed:
- sysfs_remove_link(kobj, "mdev_type");
type_link_failed:
sysfs_remove_link(mdev->type->devices_kobj, dev_name(&mdev->dev));
return ret;
@@ -280,7 +282,6 @@ void mdev_remove_sysfs_files(struct mdev_device *mdev)
{
struct kobject *kobj = &mdev->dev.kobj;
- sysfs_remove_files(kobj, mdev_device_attrs);
sysfs_remove_link(kobj, "mdev_type");
sysfs_remove_link(mdev->type->devices_kobj, dev_name(&mdev->dev));
}
--
2.30.2
[Intel-gfx] [PATCH 32/34] vfio/mdev: Remove mdev_parent_ops
From: Jason Gunthorpe
The last useful member in this struct is the supported_type_groups, move
it to the mdev_driver and delete mdev_parent_ops.
Replace it with mdev_driver as an argument to mdev_register_device()
Signed-off-by: Jason Gunthorpe
Signed-off-by: Christoph Hellwig
---
.../driver-api/vfio-mediated-device.rst | 24 --
drivers/gpu/drm/i915/gvt/kvmgt.c | 7 +-
drivers/s390/cio/vfio_ccw_ops.c | 7 +-
drivers/s390/crypto/vfio_ap_ops.c | 9 ++-
drivers/vfio/mdev/mdev_core.c | 13 --
drivers/vfio/mdev/mdev_private.h | 2 +-
drivers/vfio/mdev/mdev_sysfs.c| 6 ++---
include/linux/mdev.h | 25 +++
samples/vfio-mdev/mbochs.c| 9 ++-
samples/vfio-mdev/mdpy.c | 9 ++-
samples/vfio-mdev/mtty.c | 9 ++-
11 files changed, 28 insertions(+), 92 deletions(-)
diff --git a/Documentation/driver-api/vfio-mediated-device.rst
b/Documentation/driver-api/vfio-mediated-device.rst
index 5a6e18a651a18..784bbeb22adcf 100644
--- a/Documentation/driver-api/vfio-mediated-device.rst
+++ b/Documentation/driver-api/vfio-mediated-device.rst
@@ -105,6 +105,7 @@ structure to represent a mediated device's driver::
struct mdev_driver {
int (*probe) (struct mdev_device *dev);
void (*remove) (struct mdev_device *dev);
+struct attribute_group **supported_type_groups;
struct device_driverdriver;
};
@@ -119,30 +120,15 @@ to register and unregister itself with the core driver:
extern void mdev_unregister_driver(struct mdev_driver *drv);
-The mediated bus driver is responsible for adding mediated devices to the VFIO
-group when devices are bound to the driver and removing mediated devices from
-the VFIO when devices are unbound from the driver.
-
-
-Physical Device Driver Interface
-
-
-The physical device driver interface provides the mdev_parent_ops[3] structure
-to define the APIs to manage work in the mediated core driver that is related
-to the physical device.
-
-The structures in the mdev_parent_ops structure are as follows:
-
-* dev_attr_groups: attributes of the parent device
-* mdev_attr_groups: attributes of the mediated device
-* supported_config: attributes to define supported configurations
-* device_driver: device driver to bind for mediated device instances
+The mediated bus driver's probe function should create a vfio_device on top of
+the mdev_device and connect it to an appropriate implementation of
+vfio_device_ops.
When a driver wants to add the GUID creation sysfs to an existing device it has
probe'd to then it should call::
extern int mdev_register_device(struct device *dev,
-const struct mdev_parent_ops *ops);
+struct mdev_driver *mdev_driver);
This will provide the 'mdev_supported_types/XX/create' files which can then be
used to trigger the creation of a mdev_device. The created mdev_device will be
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index f033031c676da..0787ba5c301f5 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -1723,12 +1723,7 @@ static struct mdev_driver intel_vgpu_mdev_driver = {
},
.probe = intel_vgpu_probe,
.remove = intel_vgpu_remove,
-};
-
-static const struct mdev_parent_ops intel_vgpu_mdev_ops = {
- .owner = THIS_MODULE,
.supported_type_groups = gvt_vgpu_type_groups,
- .device_driver = &intel_vgpu_mdev_driver,
};
int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn)
@@ -2131,7 +2126,7 @@ static int intel_gvt_init_device(struct drm_i915_private
*i915)
if (ret)
goto out_destroy_idle_vgpu;
- ret = mdev_register_device(i915->drm.dev, &intel_vgpu_mdev_ops);
+ ret = mdev_register_device(i915->drm.dev, &intel_vgpu_mdev_driver);
if (ret)
goto out_cleanup_vgpu_type_groups;
diff --git a/drivers/s390/cio/vfio_ccw_ops.c b/drivers/s390/cio/vfio_ccw_ops.c
index d8589afac272f..c4d60cdbf247b 100644
--- a/drivers/s390/cio/vfio_ccw_ops.c
+++ b/drivers/s390/cio/vfio_ccw_ops.c
@@ -656,17 +656,12 @@ struct mdev_driver vfio_ccw_mdev_driver = {
},
.probe = vfio_ccw_mdev_probe,
.remove = vfio_ccw_mdev_remove,
-};
-
-static const struct mdev_parent_ops vfio_ccw_mdev_ops = {
- .owner = THIS_MODULE,
- .device_driver = &vfio_ccw_mdev_driver,
.supported_type_groups = mdev_type_groups,
};
int vfio_ccw_mdev_reg(struct subchannel *sch)
{
- return mdev_register_device(&sch->dev, &vfio_ccw_mdev_ops);
+ return mdev_register_device(&sch->dev, &vfio
