[Intel-gfx] ✗ Fi.CI.BAT: failure for Remove unnecessary GuC err capture noise
== Series Details == Series: Remove unnecessary GuC err capture noise URL : https://patchwork.freedesktop.org/series/103709/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11620 -> Patchwork_103709v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_103709v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_103709v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103709v1/index.html Participating hosts (47 -> 34) -- Missing(13): bat-adls-5 bat-dg1-6 bat-dg1-5 bat-dg2-8 bat-dg2-9 fi-bsw-cyan bat-adlp-6 fi-kbl-guc bat-adln-1 bat-rpls-1 bat-rpls-2 bat-jsl-2 bat-jsl-1 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_103709v1: ### IGT changes ### Possible regressions * igt@i915_selftest@live@late_gt_pm: - fi-bdw-gvtdvm: NOTRUN -> [DMESG-FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103709v1/fi-bdw-gvtdvm/igt@i915_selftest@live@late_gt_pm.html Known issues Here are the changes found in Patchwork_103709v1 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@requests: - fi-blb-e6850: [PASS][2] -> [DMESG-FAIL][3] ([i915#4528]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11620/fi-blb-e6850/igt@i915_selftest@l...@requests.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103709v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103709v1/fi-snb-2600/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-bdw-gvtdvm: NOTRUN -> [SKIP][5] ([fdo#109271]) +26 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103709v1/fi-bdw-gvtdvm/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html * igt@runner@aborted: - fi-blb-e6850: NOTRUN -> [FAIL][6] ([fdo#109271] / [i915#2403] / [i915#4312]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103709v1/fi-blb-e6850/igt@run...@aborted.html Possible fixes * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[INCOMPLETE][7] ([i915#3921]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11620/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103709v1/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_force_connector_basic@force-connector-state: - fi-bdw-gvtdvm: [DMESG-WARN][9] ([i915#5922]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11620/fi-bdw-gvtdvm/igt@kms_force_connector_ba...@force-connector-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103709v1/fi-bdw-gvtdvm/igt@kms_force_connector_ba...@force-connector-state.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#5922]: https://gitlab.freedesktop.org/drm/intel/issues/5922 Build changes - * Linux: CI_DRM_11620 -> Patchwork_103709v1 CI-20190529: 20190529 CI_DRM_11620: 21604008b69633f65286f7bb4106ccc6c7f87c98 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_103709v1: 21604008b69633f65286f7bb4106ccc6c7f87c98 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits f0fd1b406611 drm/i915/guc: Remove unnecessary GuC err capture noise == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103709v1/index.html
[Intel-gfx] [PATCH 0/1] Remove unnecessary GuC err capture noise
This series remove unnecessary GuC err capture noise. Alan Previn (1): drm/i915/guc: Remove unnecessary GuC err capture noise .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 77 +-- 1 file changed, 2 insertions(+), 75 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH 1/1] drm/i915/guc: Remove unnecessary GuC err capture noise
GuC error capture blurts some debug messages about empty
register lists for certain register types on engines during
firmware initialization.
These are not errors or warnings, so get rid of them.
Signed-off-by: Alan Previn
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 77 +--
1 file changed, 2 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index c4e25966d3e9..97a32e610c30 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -420,72 +420,6 @@ guc_capture_get_device_reglist(struct intel_guc *guc)
return default_lists;
}
-static const char *
-__stringify_owner(u32 owner)
-{
- switch (owner) {
- case GUC_CAPTURE_LIST_INDEX_PF:
- return "PF";
- case GUC_CAPTURE_LIST_INDEX_VF:
- return "VF";
- default:
- return "unknown";
- }
-
- return "";
-}
-
-static const char *
-__stringify_type(u32 type)
-{
- switch (type) {
- case GUC_CAPTURE_LIST_TYPE_GLOBAL:
- return "Global";
- case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS:
- return "Class";
- case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE:
- return "Instance";
- default:
- return "unknown";
- }
-
- return "";
-}
-
-static const char *
-__stringify_engclass(u32 class)
-{
- switch (class) {
- case GUC_RENDER_CLASS:
- return "Render";
- case GUC_VIDEO_CLASS:
- return "Video";
- case GUC_VIDEOENHANCE_CLASS:
- return "VideoEnhance";
- case GUC_BLITTER_CLASS:
- return "Blitter";
- case GUC_COMPUTE_CLASS:
- return "Compute";
- default:
- return "unknown";
- }
-
- return "";
-}
-
-static void
-guc_capture_warn_with_list_info(struct drm_i915_private *i915, char *msg,
- u32 owner, u32 type, u32 classid)
-{
- if (type == GUC_CAPTURE_LIST_TYPE_GLOBAL)
- drm_dbg(>drm, "GuC-capture: %s for %s %s-Registers.\n",
msg,
- __stringify_owner(owner), __stringify_type(type));
- else
- drm_dbg(>drm, "GuC-capture: %s for %s %s-Registers on
%s-Engine\n", msg,
- __stringify_owner(owner), __stringify_type(type),
- __stringify_engclass(classid));
-}
-
static int
guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
struct guc_mmio_reg *ptr, u16 num_entries)
@@ -501,11 +435,8 @@ guc_capture_list_init(struct intel_guc *guc, u32 owner,
u32 type, u32 classid,
return -ENODEV;
match = guc_capture_get_one_list(reglists, owner, type, classid);
- if (!match) {
- guc_capture_warn_with_list_info(i915, "Missing register list
init", owner, type,
- classid);
+ if (!match)
return -ENODATA;
- }
for (i = 0; i < num_entries && i < match->num_regs; ++i) {
ptr[i].offset = match->list[i].reg.reg;
@@ -556,7 +487,6 @@ int
intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32
classid,
size_t *size)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct intel_guc_state_capture *gc = guc->capture;
struct __guc_capture_ads_cache *cache =
>ads_cache[owner][type][classid];
int num_regs;
@@ -570,11 +500,8 @@ intel_guc_capture_getlistsize(struct intel_guc *guc, u32
owner, u32 type, u32 cl
}
num_regs = guc_cap_list_num_regs(gc, owner, type, classid);
- if (!num_regs) {
- guc_capture_warn_with_list_info(i915, "Missing register list
size",
- owner, type, classid);
+ if (!num_regs)
return -ENODATA;
- }
*size = PAGE_ALIGN((sizeof(struct guc_debug_capture_list)) +
(num_regs * sizeof(struct guc_mmio_reg)));
--
2.25.1
Re: [Intel-gfx] [PATCH 5/5] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
On Thu, Apr 28, 2022 at 01:18:42PM +0100, Tvrtko Ursulin wrote:
>
> Hi,
>
> On 28/04/2022 00:07, Matt Roper wrote:
> > Rather than storing subslice masks internally as u8[] (inside the sseu
> > structure) and u32 (everywhere else), let's move over to using an
> > intel_sseu_ss_mask_t typedef compatible with the operations in
> > linux/bitmap.h. We're soon going to start adding code for a new
> > platform where subslice masks are spread across two 32-bit registers
> > (requiring 64 bits to represent), and we expect future platforms will
> > likely take this even farther, requiring bitmask storage larger than a
> > simple u64 can hold.
>
> I won't have time to look into this in a detailed way for a few days. Until
> then a couple questions comments only.
>
> First, out of curiousity, were you able to end up with less code after your
> series? With my bitmap conversion I think actually ended up with couple KB
> smaller text which was a good sign eliminating the internal layout
> complications was a good approach.
Yeah, looks like I did:
$ size i915.ko.orig i915.ko
textdata bss dec hex filename
3479050 1324986760 3618308 373604 i915.ko.orig
3476552 1324666760 3615778 372c22 i915.ko
>
> For your series I am not convinced by sseu->has_common_ss_eumask. Why the
> duality, just to save a few u32 at runtime?
With this flag, eu_mask is an array of GEN_MAX_HSW_SLICES *
GEN_MAX_SS_PER_HSW_SLICE (i.e., 3*6 = 18). If we store the replicated
EU masks, then we'll have 64 u16's on PVC (where we have a DSS mask
spread across two registers) and 96 u16's on a future platform that
spreads the mask across three fuse registers. 18 -> 96 (or possibly
even more farther in the future). I think we've eliminated all of the
stack allocations of sseu structures now, so it probably isn't as
important as it used to be though; I can drop it if you think the size
savings aren't worth the extra complexity.
>
> I am also not convinced with leaving the eu_mask and subslice_mask
> being manually indexed with stride, calculcated by the driver. In my
> approach I simply went with multi-dimensional arrays which I think
> ends up with simpler code.
So something like
enum {
u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
u16 xehp[GEN_MAX_DSS];
} eu_mask;
? Or should we just skip the enum and live with allocating three times
as much space as the largest Xe_HP platform needs?
>
> For all bitmap API call sites and *pb printk format sites, I suggest not
> hard-coding the widths from SSEU defines by querying the type itsef via
> wrappers. (See my BITMAP_BITS macro and helpers which wrap it for fields.)
>
> Ie instead:
>
> bitmap_shift_left(to_mask->b, to_mask->b, offset, I915_MAX_SS_FUSE_BITS);
>
> I suggest:
>
> bitmap_zero(slices.b, BITMAP_BITS(slices.b));
>
> Also, all accesses to the bitmap type from outside intel_sse*.c|h should use
> intel_sseu wrappers and not embed knowledge of the typedef (that it has an
> member named .b etc).
>
> And finally I would also use the opportunity to clean up the pointless u8
> types for counts and such since I think they just result in worse code
> generation.
>
> You can of course counter with what you did not like in my attempt. :) I know
> I did not finish the wrappers and possibly made an overkill by converting the
> slice mask to bitmap.
These suggestions all make sense. I'll work on incorporating them into
the next version.
Matt
>
> Regards,
>
> Tvrtko
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +-
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +-
> > drivers/gpu/drm/i915/gt/intel_gt.c | 14 +-
> > drivers/gpu/drm/i915/gt/intel_sseu.c | 197 +++
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 48 ++---
> > drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 28 +--
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 28 ++-
> > drivers/gpu/drm/i915/i915_getparam.c | 2 +-
> > drivers/gpu/drm/i915/i915_query.c| 8 +-
> > 9 files changed, 183 insertions(+), 148 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index ab4c5ab28e4d..ea012ee3a8de 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -1901,7 +1901,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> > if (user->slice_mask & ~device->slice_mask)
> > return -EINVAL;
> > - if (user->subslice_mask & ~device->subslice_mask[0])
> > + if (user->subslice_mask & ~device->subslice_mask.b[0])
> > return -EINVAL;
> > if (user->max_eus_per_subslice > device->max_eus_per_subslice)
> > @@ -1915,7 +1915,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> > /* Part specific restrictions. */
> >
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/dmabuf: dmabuf cleanup
== Series Details == Series: series starting with [1/2] drm/i915/dmabuf: dmabuf cleanup URL : https://patchwork.freedesktop.org/series/103696/ State : success == Summary == CI Bug Log - changes from CI_DRM_11618_full -> Patchwork_103696v1_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103696v1/index.html Participating hosts (10 -> 7) -- Missing(3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 Known issues Here are the changes found in Patchwork_103696v1_full that come from known issues: ### IGT changes ### Possible fixes * igt@gem_exec_flush@basic-wb-pro-default: - shard-snb: [SKIP][1] ([fdo#109271]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-snb6/igt@gem_exec_fl...@basic-wb-pro-default.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103696v1/shard-snb7/igt@gem_exec_fl...@basic-wb-pro-default.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 Build changes - * Linux: CI_DRM_11618 -> Patchwork_103696v1 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_11618: 07c7d578e3b8a85c79e9a7f8dace075192d5fd91 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_103696v1: 07c7d578e3b8a85c79e9a7f8dace075192d5fd91 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103696v1/index.html
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dmc: Add MMIO range restrictions
== Series Details == Series: drm/i915/dmc: Add MMIO range restrictions URL : https://patchwork.freedesktop.org/series/103693/ State : success == Summary == CI Bug Log - changes from CI_DRM_11618_full -> Patchwork_103693v1_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103693v1/index.html Participating hosts (10 -> 7) -- Missing(3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 Known issues Here are the changes found in Patchwork_103693v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@close-race: - shard-snb: [PASS][1] -> [TIMEOUT][2] ([i915#5748]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-snb7/igt@gem_b...@close-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103693v1/shard-snb7/igt@gem_b...@close-race.html * igt@gem_exec_flush@basic-uc-rw-default: - shard-snb: [PASS][3] -> [SKIP][4] ([fdo#109271]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-snb5/igt@gem_exec_fl...@basic-uc-rw-default.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103693v1/shard-snb6/igt@gem_exec_fl...@basic-uc-rw-default.html Possible fixes * igt@gem_exec_flush@basic-batch-kernel-default-wb: - shard-snb: [SKIP][5] ([fdo#109271]) -> [PASS][6] +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-snb6/igt@gem_exec_fl...@basic-batch-kernel-default-wb.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103693v1/shard-snb7/igt@gem_exec_fl...@basic-batch-kernel-default-wb.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#5748]: https://gitlab.freedesktop.org/drm/intel/issues/5748 Build changes - * Linux: CI_DRM_11618 -> Patchwork_103693v1 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_11618: 07c7d578e3b8a85c79e9a7f8dace075192d5fd91 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_103693v1: 07c7d578e3b8a85c79e9a7f8dace075192d5fd91 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103693v1/index.html
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dmc: Load DMC on DG2 (rev4)
== Series Details == Series: drm/i915/dmc: Load DMC on DG2 (rev4) URL : https://patchwork.freedesktop.org/series/103625/ State : success == Summary == CI Bug Log - changes from CI_DRM_11618_full -> Patchwork_103625v4_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/index.html Participating hosts (10 -> 7) -- Missing(3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 Known issues Here are the changes found in Patchwork_103625v4_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-apl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [FAIL][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#4386]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl7/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl7/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl7/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl6/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl8/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl8/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl6/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl8/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl8/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl4/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl4/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl3/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl3/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl3/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl3/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl2/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl2/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl2/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl1/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl1/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl1/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-apl1/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl1/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl1/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl1/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl2/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl2/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl2/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl2/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl3/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl3/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl3/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl4/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl4/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl4/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl4/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl6/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/shard-apl6/boot.html [42]:
Re: [Intel-gfx] [PATCH] drm/i915/reset: Add Wa_22011802037 for gen11 and execlist backend
On Fri, May 06, 2022 at 10:13:28AM -0700, Umesh Nerlige Ramappa wrote:
On Wed, May 04, 2022 at 07:09:09PM +0100, Tvrtko Ursulin wrote:
On 04/05/2022 18:35, Umesh Nerlige Ramappa wrote:
On Wed, May 04, 2022 at 09:10:42AM +0100, Tvrtko Ursulin wrote:
On 03/05/2022 20:49, Umesh Nerlige Ramappa wrote:
On Tue, May 03, 2022 at 09:42:52AM +0100, Tvrtko Ursulin wrote:
On 02/05/2022 23:18, Umesh Nerlige Ramappa wrote:
Current implementation of Wa_22011802037 is limited to the GuC backend
and gen12. Add support for execlist backend and gen11 as well.
Is the implication f6aa0d713c88 ("drm/i915: Add
Wa_22011802037 force cs halt") does not work on Tigerlake?
Fixes: tag probably required in that case since I have sold
that fix as a, well, fix.
After the fix was made, the WA has evolved and added some more
steps for handling pending MI_FORCE_WAKEs. This patch is the
additional set of steps needed for the WA. As you mentioned
offline, I should correct the commit message to indicate that
the WA does exist for execlists, but needs additional steps.
Will add Fixes: tag.
Ok, that would be good then since it does sound they need to be
tied together (as in cherry picked for fixes).
Will it be followed up with preempt-to-idle implementation to
avoid the, as I understand it, potential for activity on one CCS
engine defeating the WA on another by timing out the wait for
idle?
fwiu, for the case where we want to limit the reset to a single
engine, the preempt-to-idle implementation may be required -
https://patchwork.freedesktop.org/series/101432/. If
preempt-to-idle fails, the hangcheck should kick in and then do a
gt-reset. If that happens, then the WA flow in the patch should be
applied.
Okay I read that as yes. That is fine by me since this patch alone
is better than without it.
I have a general doubt for engines that do NOT share a reset domain,
specifically for execlist backend.
What is the expectation/behavior with the hangcheck initiated reset.
It says resetting chip for the engine that it decides is hung. In that
path it calls gt_reset which loops through engines (reset_prepare,
rewind, etc.). Are all running contexts victimized? OR is there an
attempt to preempt-to-idle contexts on other (innocent) engines and
then resubmit them if successfully preempted?
nvm, I notice that all active contexts are marked as guilty, which is
what I was expecting. I think I ran into a test bug when trying to
understand this behavior, so wanted to ask. The test was running more
than one batch on the targeted engine and checking that both batches are
guilty, but that cannot happen, only the active contexts are marked
guilty.
Regards,
Umesh
Thanks,
Umesh
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dmabuf: dmabuf cleanup
== Series Details ==
Series: series starting with [1/2] drm/i915/dmabuf: dmabuf cleanup
URL : https://patchwork.freedesktop.org/series/103696/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11618 -> Patchwork_103696v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103696v1/index.html
Participating hosts (35 -> 44)
--
Additional (11): bat-adls-5 bat-dg1-6 bat-dg2-8 fi-icl-u2 bat-dg2-9
bat-adlp-6 bat-adln-1 bat-rpls-1 bat-rpls-2 bat-jsl-2 bat-jsl-1
Missing(2): fi-bsw-cyan fi-bdw-5557u
Known issues
Here are the changes found in Patchwork_103696v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@runner@aborted:
- fi-icl-u2: NOTRUN -> [FAIL][1] ([i915#3690])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103696v1/fi-icl-u2/igt@run...@aborted.html
- bat-dg1-6: NOTRUN -> [FAIL][2] ([i915#5616])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103696v1/bat-dg1-6/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3690]: https://gitlab.freedesktop.org/drm/intel/issues/3690
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5602]: https://gitlab.freedesktop.org/drm/intel/issues/5602
[i915#5616]: https://gitlab.freedesktop.org/drm/intel/issues/5616
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
[i915#5917]: https://gitlab.freedesktop.org/drm/intel/issues/5917
Build changes
-
* Linux: CI_DRM_11618 -> Patchwork_103696v1
CI-20190529: 20190529
CI_DRM_11618: 07c7d578e3b8a85c79e9a7f8dace075192d5fd91 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103696v1: 07c7d578e3b8a85c79e9a7f8dace075192d5fd91 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
faf34fa0cba3 drm/i915/dmabuf: Use scatterlist for_each_sg API
1383a2c06fc0 drm/i915/dmabuf: dmabuf cleanup
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103696v1/index.html
[Intel-gfx] [PATCH 2/2] drm/i915/dmabuf: Use scatterlist for_each_sg API
Update open coded for loop to use the standard scatterlist
for_each_sg API.
Cc: Tvrtko Ursulin
Signed-off-by: Michael J. Ruhl
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index 5f327eac26e6..3006e60e2d51 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -47,12 +47,10 @@ static struct sg_table *i915_gem_map_dma_buf(struct
dma_buf_attachment *attach,
if (ret)
goto err_free;
- src = obj->mm.pages->sgl;
dst = sgt->sgl;
- for (i = 0; i < obj->mm.pages->nents; i++) {
+ for_each_sg(obj->mm.pages->sgl, src, obj->mm.pages->nents, i) {
sg_set_page(dst, sg_page(src), src->length, 0);
dst = sg_next(dst);
- src = sg_next(src);
}
ret = dma_map_sgtable(attach->dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC);
--
2.31.1
[Intel-gfx] [PATCH 1/2] drm/i915/dmabuf: dmabuf cleanup
Some minor cleanup of some variables for consistency.
Normalize struct sg_table to sgt.
Normalize struct dma_buf_attachment to attach.
checkpatch issues sizeof(), !NULL updates.
Cc: Tvrtko Ursulin
Signed-off-by: Michael J. Ruhl
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 47 --
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index f5062d0c6333..5f327eac26e6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -25,43 +25,46 @@ static struct drm_i915_gem_object *dma_buf_to_obj(struct
dma_buf *buf)
return to_intel_bo(buf->priv);
}
-static struct sg_table *i915_gem_map_dma_buf(struct dma_buf_attachment
*attachment,
+static struct sg_table *i915_gem_map_dma_buf(struct dma_buf_attachment *attach,
enum dma_data_direction dir)
{
- struct drm_i915_gem_object *obj = dma_buf_to_obj(attachment->dmabuf);
- struct sg_table *st;
+ struct drm_i915_gem_object *obj = dma_buf_to_obj(attach->dmabuf);
+ struct sg_table *sgt;
struct scatterlist *src, *dst;
int ret, i;
- /* Copy sg so that we make an independent mapping */
- st = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
- if (st == NULL) {
+ /*
+* Make a copy of the object's sgt, so that we can make an independent
+* mapping
+*/
+ sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
+ if (!sgt) {
ret = -ENOMEM;
goto err;
}
- ret = sg_alloc_table(st, obj->mm.pages->nents, GFP_KERNEL);
+ ret = sg_alloc_table(sgt, obj->mm.pages->nents, GFP_KERNEL);
if (ret)
goto err_free;
src = obj->mm.pages->sgl;
- dst = st->sgl;
+ dst = sgt->sgl;
for (i = 0; i < obj->mm.pages->nents; i++) {
sg_set_page(dst, sg_page(src), src->length, 0);
dst = sg_next(dst);
src = sg_next(src);
}
- ret = dma_map_sgtable(attachment->dev, st, dir, DMA_ATTR_SKIP_CPU_SYNC);
+ ret = dma_map_sgtable(attach->dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC);
if (ret)
goto err_free_sg;
- return st;
+ return sgt;
err_free_sg:
- sg_free_table(st);
+ sg_free_table(sgt);
err_free:
- kfree(st);
+ kfree(sgt);
err:
return ERR_PTR(ret);
}
@@ -236,15 +239,15 @@ struct dma_buf *i915_gem_prime_export(struct
drm_gem_object *gem_obj, int flags)
static int i915_gem_object_get_pages_dmabuf(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct sg_table *pages;
+ struct sg_table *sgt;
unsigned int sg_page_sizes;
assert_object_held(obj);
- pages = dma_buf_map_attachment(obj->base.import_attach,
- DMA_BIDIRECTIONAL);
- if (IS_ERR(pages))
- return PTR_ERR(pages);
+ sgt = dma_buf_map_attachment(obj->base.import_attach,
+DMA_BIDIRECTIONAL);
+ if (IS_ERR(sgt))
+ return PTR_ERR(sgt);
/*
* DG1 is special here since it still snoops transactions even with
@@ -261,16 +264,16 @@ static int i915_gem_object_get_pages_dmabuf(struct
drm_i915_gem_object *obj)
(!HAS_LLC(i915) && !IS_DG1(i915)))
wbinvd_on_all_cpus();
- sg_page_sizes = i915_sg_dma_sizes(pages->sgl);
- __i915_gem_object_set_pages(obj, pages, sg_page_sizes);
+ sg_page_sizes = i915_sg_dma_sizes(sgt->sgl);
+ __i915_gem_object_set_pages(obj, sgt, sg_page_sizes);
return 0;
}
static void i915_gem_object_put_pages_dmabuf(struct drm_i915_gem_object *obj,
-struct sg_table *pages)
+struct sg_table *sgt)
{
- dma_buf_unmap_attachment(obj->base.import_attach, pages,
+ dma_buf_unmap_attachment(obj->base.import_attach, sgt,
DMA_BIDIRECTIONAL);
}
@@ -313,7 +316,7 @@ struct drm_gem_object *i915_gem_prime_import(struct
drm_device *dev,
get_dma_buf(dma_buf);
obj = i915_gem_object_alloc();
- if (obj == NULL) {
+ if (!obj) {
ret = -ENOMEM;
goto fail_detach;
}
--
2.31.1
[Intel-gfx] i915 dmabuf cleanup
While studying this code I noticed a few inconsistencies and possible cleanups. Please consider these patches.
Re: [Intel-gfx] [PATCH 1/2] drm/i915/psr: Use full update In case of area calculation fails
On Fri, 2022-05-06 at 18:28 +, Hogander, Jouni wrote: > On Fri, 2022-05-06 at 15:29 +, Souza, Jose wrote: > > On Fri, 2022-05-06 at 08:48 +0300, Jouni Högander wrote: > > > Currently we have some corner cases where area calculation > > > fails. For > > > these sel fetch are calculation ends up having update area as y1 = > > > 0, > > > y2 = 4. Instead of these values safer option is full update. > > > > Aren't you able to reproduce this scenarios with IGT? So why not > > probably fix the calculations? > > There were some discussion with Ville Syrjälä that the proper fix for > this would be to move psr update area calculation into where other > calculations for planes are done. Currently we don't have e.g. proper > offset information available here. I have this in my tasklist, but been > busy with other tracks. Okay so please add some of that to the commit description. > > I'm also concerned generally on the first loop possibly ending up with > y1=-1,y2=-1 values due to other reasons as well. So using that > full_update prevents this posibility completely. > > If I forget how I originally found this problem with bigfb I think this > backup using full update if something goes wrong is generally a good > idea. Currently it's just using y1=0,y2=4. > > > > > > Cc: José Roberto de Souza > > > Cc: Mika Kahola > > > Tested-by: Mark Pearson > > > Signed-off-by: Jouni Högander > > > --- > > > drivers/gpu/drm/i915/display/intel_psr.c | 3 +++ > > > 1 file changed, 3 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > > b/drivers/gpu/drm/i915/display/intel_psr.c > > > index 06db407e2749..8c099d24de86 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > > @@ -1770,6 +1770,9 @@ int intel_psr2_sel_fetch_update(struct > > > intel_atomic_state *state, > > > clip_area_update(_clip, _area); > > > } > > > Add a TODO and a "drm_DEBUG_ONCE()"(check drm_WARN_ONCE) here so we get a warning about this at least once and this is not forgot. > > > +if (pipe_clip.y1 == -1) > > > +full_update = true; > > > + > > > if (full_update) > > > goto skip_sel_fetch_set_loop; > > > >
[Intel-gfx] ✓ Fi.CI.IGT: success for Expose max and current bpc via debugfs (rev4)
== Series Details == Series: Expose max and current bpc via debugfs (rev4) URL : https://patchwork.freedesktop.org/series/102502/ State : success == Summary == CI Bug Log - changes from CI_DRM_11617_full -> Patchwork_102502v4_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v4/index.html Participating hosts (11 -> 7) -- Missing(4): pig-skl-6260u pig-kbl-iris shard-tglu pig-glk-j5005 Known issues Here are the changes found in Patchwork_102502v4_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-cleanup: - shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v4/shard-snb2/igt@gem_ctx_persiste...@engines-cleanup.html * igt@gem_exec_flush@basic-uc-prw-default: - shard-snb: [PASS][2] -> [SKIP][3] ([fdo#109271]) +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11617/shard-snb4/igt@gem_exec_fl...@basic-uc-prw-default.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v4/shard-snb6/igt@gem_exec_fl...@basic-uc-prw-default.html * igt@i915_hangman@engine-engine-hang: - shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271]) +108 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v4/shard-snb2/igt@i915_hang...@engine-engine-hang.html * igt@kms_chamelium@hdmi-hpd-enable-disable-mode: - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v4/shard-snb4/igt@kms_chamel...@hdmi-hpd-enable-disable-mode.html * igt@syncobj_timeline@transfer-timeline-point: - shard-snb: NOTRUN -> [DMESG-FAIL][6] ([i915#5098]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v4/shard-snb2/igt@syncobj_timel...@transfer-timeline-point.html Possible fixes * igt@gem_exec_flush@basic-wb-prw-default: - shard-snb: [SKIP][7] ([fdo#109271]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11617/shard-snb6/igt@gem_exec_fl...@basic-wb-prw-default.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v4/shard-snb7/igt@gem_exec_fl...@basic-wb-prw-default.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098 Build changes - * IGT: IGT_6468 -> IGTPW_7046 * Linux: CI_DRM_11617 -> Patchwork_102502v4 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_11617: d96cea3d7ffb524248fcc8db433c579cf262eaea @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_7046: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7046/index.html IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_102502v4: d96cea3d7ffb524248fcc8db433c579cf262eaea @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v4/index.html
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dmc: Add MMIO range restrictions
== Series Details == Series: drm/i915/dmc: Add MMIO range restrictions URL : https://patchwork.freedesktop.org/series/103693/ State : success == Summary == CI Bug Log - changes from CI_DRM_11618 -> Patchwork_103693v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103693v1/index.html Participating hosts (35 -> 32) -- Missing(3): fi-bsw-cyan fi-bxt-dsi fi-bdw-5557u Changes --- No changes found Build changes - * Linux: CI_DRM_11618 -> Patchwork_103693v1 CI-20190529: 20190529 CI_DRM_11618: 07c7d578e3b8a85c79e9a7f8dace075192d5fd91 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_103693v1: 07c7d578e3b8a85c79e9a7f8dace075192d5fd91 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits c83bc7a1ef9d drm/i915/dmc: Add MMIO range restrictions == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103693v1/index.html
Re: [Intel-gfx] [PATCH 1/2] drm/i915/psr: Use full update In case of area calculation fails
On Fri, 2022-05-06 at 15:29 +, Souza, Jose wrote: > On Fri, 2022-05-06 at 08:48 +0300, Jouni Högander wrote: > > Currently we have some corner cases where area calculation > > fails. For > > these sel fetch are calculation ends up having update area as y1 = > > 0, > > y2 = 4. Instead of these values safer option is full update. > > Aren't you able to reproduce this scenarios with IGT? So why not > probably fix the calculations? There were some discussion with Ville Syrjälä that the proper fix for this would be to move psr update area calculation into where other calculations for planes are done. Currently we don't have e.g. proper offset information available here. I have this in my tasklist, but been busy with other tracks. I'm also concerned generally on the first loop possibly ending up with y1=-1,y2=-1 values due to other reasons as well. So using that full_update prevents this posibility completely. If I forget how I originally found this problem with bigfb I think this backup using full update if something goes wrong is generally a good idea. Currently it's just using y1=0,y2=4. > > > Cc: José Roberto de Souza > > Cc: Mika Kahola > > Tested-by: Mark Pearson > > Signed-off-by: Jouni Högander > > --- > > drivers/gpu/drm/i915/display/intel_psr.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index 06db407e2749..8c099d24de86 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -1770,6 +1770,9 @@ int intel_psr2_sel_fetch_update(struct > > intel_atomic_state *state, > > clip_area_update(_clip, _area); > > } > > > > +if (pipe_clip.y1 == -1) > > +full_update = true; > > + > > if (full_update) > > goto skip_sel_fetch_set_loop; > >
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc: Add MMIO range restrictions
== Series Details ==
Series: drm/i915/dmc: Add MMIO range restrictions
URL : https://patchwork.freedesktop.org/series/103693/
State : warning
== Summary ==
Error: dim checkpatch failed
dfd1ba4479c1 drm/i915/dmc: Add MMIO range restrictions
-:77: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#77: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:483:
+ if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count,
dmc_header->header_ver, dmc_id)) {
total: 0 errors, 1 warnings, 0 checks, 78 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dmc: Load DMC on DG2 (rev4)
== Series Details == Series: drm/i915/dmc: Load DMC on DG2 (rev4) URL : https://patchwork.freedesktop.org/series/103625/ State : success == Summary == CI Bug Log - changes from CI_DRM_11618 -> Patchwork_103625v4 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/index.html Participating hosts (35 -> 34) -- Missing(1): fi-bsw-cyan Known issues Here are the changes found in Patchwork_103625v4 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[PASS][1] -> [INCOMPLETE][2] ([i915#3921]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 Build changes - * Linux: CI_DRM_11618 -> Patchwork_103625v4 CI-20190529: 20190529 CI_DRM_11618: 07c7d578e3b8a85c79e9a7f8dace075192d5fd91 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_103625v4: 07c7d578e3b8a85c79e9a7f8dace075192d5fd91 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits f59f3563ba3e drm/i915/dmc: Load DMC on DG2 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v4/index.html
Re: [Intel-gfx] [PATCH 17/25] drm/edid: add drm_edid helper for drm_edid_to_sad()
On Fri, May 06, 2022 at 01:10:24PM +0300, Jani Nikula wrote:
> +int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
> +{
> + struct drm_edid drm_edid = {
> + .edid = edid,
> + .size = edid_size(edid),
> + };
> +
> + return _drm_edid_to_sad(_edid, sads);
No need to check for NULL edid in these wrappers?
> +}
> EXPORT_SYMBOL(drm_edid_to_sad);
>
> /**
> --
> 2.30.2
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 02/25] drm/edid: convert drm_for_each_detailed_block() to edid iter
On Fri, May 06, 2022 at 01:10:09PM +0300, Jani Nikula wrote:
> We have an iterator for this, use it. It does include the base block,
> but its tag is 0 and will be skipped.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_edid.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index efc1999b9573..dcef92c8887a 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -2574,6 +2574,8 @@ vtb_for_each_detailed_block(const u8 *ext, detailed_cb
> *cb, void *closure)
> static void
> drm_for_each_detailed_block(const struct edid *edid, detailed_cb *cb, void
> *closure)
> {
> + struct drm_edid_iter edid_iter;
> + const u8 *ext;
> int i;
>
> if (edid == NULL)
> @@ -2582,9 +2584,8 @@ drm_for_each_detailed_block(const struct edid *edid,
> detailed_cb *cb, void *clos
> for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
> cb(&(edid->detailed_timings[i]), closure);
>
> - for (i = 0; i < edid_extension_block_count(edid); i++) {
> - const u8 *ext = edid_extension_block_data(edid, i);
> -
> + drm_edid_iter_begin(edid, _iter);
> + drm_edid_iter_for_each(ext, _iter) {
> switch (*ext) {
> case CEA_EXT:
> cea_for_each_detailed_block(ext, cb, closure);
> @@ -2596,6 +2597,7 @@ drm_for_each_detailed_block(const struct edid *edid,
> detailed_cb *cb, void *clos
> break;
> }
> }
> + drm_edid_iter_end(_iter);
> }
>
> static void
> --
> 2.30.2
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 01/25] drm/edid: use else-if in CTA extension parsing
On Fri, May 06, 2022 at 01:10:08PM +0300, Jani Nikula wrote: > Only one of the conditions can be true. > > Suggested-by: Ville Syrjälä > Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/drm_edid.c | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > index 47d121e99201..efc1999b9573 100644 > --- a/drivers/gpu/drm/drm_edid.c > +++ b/drivers/gpu/drm/drm_edid.c > @@ -5473,16 +5473,16 @@ static void drm_parse_cea_ext(struct drm_connector > *connector, > > if (cea_db_is_hdmi_vsdb(db)) > drm_parse_hdmi_vsdb_video(connector, data); > - if (cea_db_is_hdmi_forum_vsdb(db) || > - cea_db_is_hdmi_forum_scdb(db)) > + else if (cea_db_is_hdmi_forum_vsdb(db) || > + cea_db_is_hdmi_forum_scdb(db)) > drm_parse_hdmi_forum_scds(connector, data); > - if (cea_db_is_microsoft_vsdb(db)) > + else if (cea_db_is_microsoft_vsdb(db)) > drm_parse_microsoft_vsdb(connector, data); > - if (cea_db_is_y420cmdb(db)) > + else if (cea_db_is_y420cmdb(db)) > drm_parse_y420cmdb_bitmap(connector, data); > - if (cea_db_is_vcdb(db)) > + else if (cea_db_is_vcdb(db)) > drm_parse_vcdb(connector, data); > - if (cea_db_is_hdmi_hdr_metadata_block(db)) > + else if (cea_db_is_hdmi_hdr_metadata_block(db)) > drm_parse_hdr_metadata_block(connector, data); > } > cea_db_iter_end(); > -- > 2.30.2 -- Ville Syrjälä Intel
[Intel-gfx] [PATCH] drm/i915/dmc: Add MMIO range restrictions
Bspec has added some steps that check forDMC MMIO range before
programming them
v2: Fix for CI
v3: move register defines to .h (Anusha)
- Check MMIO restrictions per pipe
- Add MMIO restricton for v1 dmc header as well (Lucas)
v4: s/_PICK/_PICK_EVEN and use it only for Pipe DMC scenario.
- clean up sanity check logic.(Lucas)
- Add MMIO range for RKL as well.(Anusha)
v5: Use DISPLAY_VER instead of per platform check (Lucas)
BSpec: 49193
Cc:
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 42 +++
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 18 +++-
2 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 2f01aca4d981..f545cc7367e3 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -378,6 +378,43 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc,
}
}
+static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, const u32
*mmioaddr,
+ u32 mmio_count, int header_ver, u8
dmc_id)
+{
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ u32 start_range, end_range;
+ int i;
+
+ if (dmc_id >= DMC_FW_MAX) {
+ drm_warn(>drm, "Unsupported firmware id %u\n", dmc_id);
+ return false;
+ }
+
+ if (header_ver == 1) {
+ start_range = DMC_MMIO_START_RANGE;
+ end_range = DMC_MMIO_END_RANGE;
+ } else if (dmc_id == DMC_FW_MAIN) {
+ start_range = TGL_MAIN_MMIO_START;
+ end_range = TGL_MAIN_MMIO_END;
+ } else if (DISPLAY_VER(i915) >= 13) {
+ start_range = ADLP_PIPE_MMIO_START;
+ end_range = ADLP_PIPE_MMIO_END;
+ } else if (DISPLAY_VER(i915) >= 12) {
+ start_range = TGL_PIPE_MMIO_START(dmc_id);
+ end_range = TGL_PIPE_MMIO_END(dmc_id);
+ } else {
+ drm_warn(>drm, "Unknown mmio range for sanity check");
+ return false;
+ }
+
+ for (i = 0; i < mmio_count; i++) {
+ if (mmioaddr[i] < start_range || mmioaddr[i] > end_range)
+ return false;
+ }
+
+ return true;
+}
+
static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
const struct intel_dmc_header_base *dmc_header,
size_t rem_size, u8 dmc_id)
@@ -447,6 +484,11 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
return 0;
}
+ if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count,
dmc_header->header_ver, dmc_id)) {
+ drm_err(>drm, "DMC firmware has Wrong MMIO Addresses\n");
+ return 0;
+ }
+
for (i = 0; i < mmio_count; i++) {
dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
dmc_info->mmiodata[i] = mmiodata[i];
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index d65e698832eb..67e14eb96a7a 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -16,7 +16,23 @@
#define DMC_LAST_WRITE _MMIO(0x8F034)
#define DMC_LAST_WRITE_VALUE 0xc003b400
#define DMC_MMIO_START_RANGE 0x8
-#define DMC_MMIO_END_RANGE 0x8
+#define DMC_MMIO_END_RANGE 0x8
+#define DMC_V1_MMIO_START_RANGE0x8
+#define TGL_MAIN_MMIO_START0x8F000
+#define TGL_MAIN_MMIO_END 0x8
+#define _TGL_PIPEA_MMIO_START 0x92000
+#define _TGL_PIPEA_MMIO_END0x93FFF
+#define _TGL_PIPEB_MMIO_START 0x96000
+#define _TGL_PIPEB_MMIO_END0x97FFF
+#define ADLP_PIPE_MMIO_START 0x5F000
+#define ADLP_PIPE_MMIO_END 0x5
+
+#define TGL_PIPE_MMIO_START(dmc_id)_PICK_EVEN(((dmc_id) - 1),
_TGL_PIPEA_MMIO_START,\
+ _TGL_PIPEB_MMIO_START)
+
+#define TGL_PIPE_MMIO_END(dmc_id) _PICK_EVEN(((dmc_id) - 1),
_TGL_PIPEA_MMIO_END,\
+ _TGL_PIPEB_MMIO_END)
+
#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
--
2.25.1
Re: [Intel-gfx] [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
On Fri, May 06, 2022 at 10:23:41AM -0700, Lucas De Marchi wrote: > On Thu, May 05, 2022 at 02:38:05PM -0700, Matt Roper wrote: > > From: Stuart Summers > > > > Although we already strip 3D-specific flags from PIPE_CONTROL > > instructions when submitting to a compute engine, there are some > > additional flags that need to be removed when the platform as a whole > > lacks a 3D pipeline. Add those restrictions here. > > > > Bspec: 47112 > > Signed-off-by: Stuart Summers > > Signed-off-by: Matt Roper > > --- > > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 -- > > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 ++-- > > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > > drivers/gpu/drm/i915/i915_pci.c | 3 ++- > > drivers/gpu/drm/i915/intel_device_info.h | 3 ++- > > 5 files changed, 28 insertions(+), 10 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > > b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > > index 3e13960615bd..11c72792573d 100644 > > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > > @@ -197,8 +197,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 > > mode) > > > > flags |= PIPE_CONTROL_CS_STALL; > > > > - if (engine->class == COMPUTE_CLASS) > > - flags &= ~PIPE_CONTROL_3D_FLAGS; > > + if (LACKS_3D_PIPELINE(engine->i915)) > > + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; > > + else if (engine->class == COMPUTE_CLASS) > > + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > > > > cs = intel_ring_begin(rq, 6); > > if (IS_ERR(cs)) > > @@ -227,8 +229,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 > > mode) > > > > flags |= PIPE_CONTROL_CS_STALL; > > > > - if (engine->class == COMPUTE_CLASS) > > - flags &= ~PIPE_CONTROL_3D_FLAGS; > > + if (LACKS_3D_PIPELINE(engine->i915)) > > + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; > > + else if (engine->class == COMPUTE_CLASS) > > + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > > > > if (!HAS_FLAT_CCS(rq->engine->i915)) > > count = 8 + 4; > > @@ -716,8 +720,10 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct > > i915_request *rq, u32 *cs) > > /* Wa_1409600907 */ > > flags |= PIPE_CONTROL_DEPTH_STALL; > > > > - if (rq->engine->class == COMPUTE_CLASS) > > - flags &= ~PIPE_CONTROL_3D_FLAGS; > > + if (LACKS_3D_PIPELINE(rq->engine->i915)) > > + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; > > + else if (rq->engine->class == COMPUTE_CLASS) > > + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > > > > cs = gen12_emit_ggtt_write_rcs(cs, > >rq->fence.seqno, > > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > > b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > > index 556bca3be804..900755f4b787 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > > @@ -288,8 +288,8 @@ > > #define PIPE_CONTROL_DEPTH_CACHE_FLUSH(1<<0) > > #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ > > > > -/* 3D-related flags can't be set on compute engine */ > > -#define PIPE_CONTROL_3D_FLAGS (\ > > +/* 3D-related flags that can't be set on _engines_ that lack a 3D pipeline > > */ > > +#define PIPE_CONTROL_3D_ENGINE_FLAGS (\ > > PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \ > > PIPE_CONTROL_DEPTH_CACHE_FLUSH | \ > > PIPE_CONTROL_TILE_CACHE_FLUSH | \ > > @@ -300,6 +300,14 @@ > > PIPE_CONTROL_VF_CACHE_INVALIDATE | \ > > PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET) > > > > +/* 3D-related flags that can't be set on _platforms_ that lack a 3D > > pipeline */ > > +#define PIPE_CONTROL_3D_ARCH_FLAGS ( \ > > names and comments here I think are confusing. In the code we do: > > if (LACKS_3D_PIPELINE(engine->i915)) > flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; > else if (engine->class == COMPUTE_CLASS) > flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > > coments give the _engines_ that lack a 3D pipeline doens't seem accurate > as bcs, vcs, vecs also lack a 3d pipeline. Maybe be explicit about the > flags being set on compute engine: PIPE_CONTROL_COMPUTE_ENGINE_FLAGS > > And LACKS_3D_PIPELINE... may be better to invert the condition to follow > the other macros: HAS_3D_PIPELINE. > > > + PIPE_CONTROL_3D_ENGINE_FLAGS | \ > > + PIPE_CONTROL_INDIRECT_STATE_DISABLE | \ > > + PIPE_CONTROL_FLUSH_ENABLE | \ > > + PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \ > > + PIPE_CONTROL_DC_FLUSH_ENABLE) > > + > > #define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) > > #define
Re: [Intel-gfx] [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
On Thu, May 05, 2022 at 02:38:05PM -0700, Matt Roper wrote: From: Stuart Summers Although we already strip 3D-specific flags from PIPE_CONTROL instructions when submitting to a compute engine, there are some additional flags that need to be removed when the platform as a whole lacks a 3D pipeline. Add those restrictions here. Bspec: 47112 Signed-off-by: Stuart Summers Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 -- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 ++-- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_pci.c | 3 ++- drivers/gpu/drm/i915/intel_device_info.h | 3 ++- 5 files changed, 28 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index 3e13960615bd..11c72792573d 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -197,8 +197,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) flags |= PIPE_CONTROL_CS_STALL; - if (engine->class == COMPUTE_CLASS) - flags &= ~PIPE_CONTROL_3D_FLAGS; + if (LACKS_3D_PIPELINE(engine->i915)) + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; + else if (engine->class == COMPUTE_CLASS) + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; cs = intel_ring_begin(rq, 6); if (IS_ERR(cs)) @@ -227,8 +229,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) flags |= PIPE_CONTROL_CS_STALL; - if (engine->class == COMPUTE_CLASS) - flags &= ~PIPE_CONTROL_3D_FLAGS; + if (LACKS_3D_PIPELINE(engine->i915)) + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; + else if (engine->class == COMPUTE_CLASS) + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; if (!HAS_FLAT_CCS(rq->engine->i915)) count = 8 + 4; @@ -716,8 +720,10 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) /* Wa_1409600907 */ flags |= PIPE_CONTROL_DEPTH_STALL; - if (rq->engine->class == COMPUTE_CLASS) - flags &= ~PIPE_CONTROL_3D_FLAGS; + if (LACKS_3D_PIPELINE(rq->engine->i915)) + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; + else if (rq->engine->class == COMPUTE_CLASS) + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; cs = gen12_emit_ggtt_write_rcs(cs, rq->fence.seqno, diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index 556bca3be804..900755f4b787 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -288,8 +288,8 @@ #define PIPE_CONTROL_DEPTH_CACHE_FLUSH(1<<0) #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ -/* 3D-related flags can't be set on compute engine */ -#define PIPE_CONTROL_3D_FLAGS (\ +/* 3D-related flags that can't be set on _engines_ that lack a 3D pipeline */ +#define PIPE_CONTROL_3D_ENGINE_FLAGS (\ PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \ PIPE_CONTROL_DEPTH_CACHE_FLUSH | \ PIPE_CONTROL_TILE_CACHE_FLUSH | \ @@ -300,6 +300,14 @@ PIPE_CONTROL_VF_CACHE_INVALIDATE | \ PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET) +/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */ +#define PIPE_CONTROL_3D_ARCH_FLAGS ( \ names and comments here I think are confusing. In the code we do: if (LACKS_3D_PIPELINE(engine->i915)) flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; else if (engine->class == COMPUTE_CLASS) flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; coments give the _engines_ that lack a 3D pipeline doens't seem accurate as bcs, vcs, vecs also lack a 3d pipeline. Maybe be explicit about the flags being set on compute engine: PIPE_CONTROL_COMPUTE_ENGINE_FLAGS And LACKS_3D_PIPELINE... may be better to invert the condition to follow the other macros: HAS_3D_PIPELINE. + PIPE_CONTROL_3D_ENGINE_FLAGS | \ + PIPE_CONTROL_INDIRECT_STATE_DISABLE | \ + PIPE_CONTROL_FLUSH_ENABLE | \ + PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \ + PIPE_CONTROL_DC_FLUSH_ENABLE) + #define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) #define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) /* Opcodes for MI_MATH_INSTR */ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b389674b5210..1e153cefc92e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1403,6 +1403,8 @@
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/display: Add smem fallback allocation for dpt
== Series Details == Series: series starting with [1/2] drm/i915/display: Add smem fallback allocation for dpt URL : https://patchwork.freedesktop.org/series/103678/ State : success == Summary == CI Bug Log - changes from CI_DRM_11617_full -> Patchwork_103678v1_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103678v1/index.html Participating hosts (11 -> 7) -- Missing(4): pig-skl-6260u pig-kbl-iris shard-tglu pig-glk-j5005 Known issues Here are the changes found in Patchwork_103678v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_flush@basic-batch-kernel-default-uc: - shard-snb: [PASS][1] -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11617/shard-snb7/igt@gem_exec_fl...@basic-batch-kernel-default-uc.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103678v1/shard-snb6/igt@gem_exec_fl...@basic-batch-kernel-default-uc.html * igt@kms_chamelium@dp-hpd-storm: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103678v1/shard-snb7/igt@kms_chamel...@dp-hpd-storm.html * igt@kms_hdmi_inject@inject-4k: - shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271]) +8 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103678v1/shard-snb7/igt@kms_hdmi_inj...@inject-4k.html Possible fixes * igt@gem_exec_flush@basic-wb-prw-default: - shard-snb: [SKIP][5] ([fdo#109271]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11617/shard-snb6/igt@gem_exec_fl...@basic-wb-prw-default.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103678v1/shard-snb5/igt@gem_exec_fl...@basic-wb-prw-default.html * igt@i915_selftest@live@hangcheck: - shard-snb: [INCOMPLETE][7] ([i915#3921]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11617/shard-snb5/igt@i915_selftest@l...@hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103678v1/shard-snb7/igt@i915_selftest@l...@hangcheck.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 Build changes - * Linux: CI_DRM_11617 -> Patchwork_103678v1 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_11617: d96cea3d7ffb524248fcc8db433c579cf262eaea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_103678v1: d96cea3d7ffb524248fcc8db433c579cf262eaea @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103678v1/index.html
[Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2
Add Support for DC states on Dg2.
v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)
v4: Add FIXME (Rodrigo)
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi (v1)
---
drivers/gpu/drm/i915/display/intel_display_power.c | 11 +--
drivers/gpu/drm/i915/display/intel_dmc.c | 10 +-
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1d9bd5808849..2271f88e9a25 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -906,8 +906,15 @@ static u32 get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
if (!HAS_DISPLAY(dev_priv))
return 0;
-
- if (IS_DG1(dev_priv))
+ /* FIXME: change max_dc back to 3 once
+* we have DC5 bugs resolved. Till then,
+* DG2 will use only DC9. Though DC9 does
+* not depend on DMC, loading it in order
+* to unblock runtime PM
+*/
+ if (IS_DG2(dev_priv))
+ max_dc = 0;
+ else if (IS_DG1(dev_priv))
max_dc = 3;
else if (DISPLAY_VER(dev_priv) >= 12)
max_dc = 4;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 257cf662f9f4..2f01aca4d981 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -52,6 +52,10 @@
#define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define DG2_DMC_PATH DMC_PATH(dg2, 2, 06)
+#define DG2_DMC_VERSION_REQUIRED DMC_VERSION(2, 06)
+MODULE_FIRMWARE(DG2_DMC_PATH);
+
#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 16)
#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 16)
MODULE_FIRMWARE(ADLP_DMC_PATH);
@@ -688,7 +692,11 @@ void intel_dmc_ucode_init(struct drm_i915_private
*dev_priv)
*/
intel_dmc_runtime_pm_get(dev_priv);
- if (IS_ALDERLAKE_P(dev_priv)) {
+ if (IS_DG2(dev_priv)) {
+ dmc->fw_path = DG2_DMC_PATH;
+ dmc->required_version = DG2_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
+ } else if (IS_ALDERLAKE_P(dev_priv)) {
dmc->fw_path = ADLP_DMC_PATH;
dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
--
2.25.1
[Intel-gfx] [PATCH 0/1] DG2 DMC Support
While DG2 supports DC5 and DC9, some of the tests in fast-feedback blew up DG2 when the tests forced transition from dc5->dc9 on suspend and dc9->dc5 on resume. Some local experiments performed with Rodrigo on a RIL system showed promising results when dc5 was completely diabled and i915 took only dc9 paths. Sending this so we can check the CI results to confirm the findings from local testing which will hopefully help narrow down the root cause of MMIO BAR lost issue Cc: Rodrigo Vivi Cc: Imre Deak Anusha Srivatsa (1): drm/i915/dmc: Load DMC on DG2 drivers/gpu/drm/i915/display/intel_display_power.c | 4 +++- drivers/gpu/drm/i915/display/intel_dmc.c | 10 +- 2 files changed, 12 insertions(+), 2 deletions(-) -- 2.25.1
Re: [Intel-gfx] [PATCH] drm/i915/reset: Add Wa_22011802037 for gen11 and execlist backend
On Wed, May 04, 2022 at 07:09:09PM +0100, Tvrtko Ursulin wrote:
On 04/05/2022 18:35, Umesh Nerlige Ramappa wrote:
On Wed, May 04, 2022 at 09:10:42AM +0100, Tvrtko Ursulin wrote:
On 03/05/2022 20:49, Umesh Nerlige Ramappa wrote:
On Tue, May 03, 2022 at 09:42:52AM +0100, Tvrtko Ursulin wrote:
On 02/05/2022 23:18, Umesh Nerlige Ramappa wrote:
Current implementation of Wa_22011802037 is limited to the GuC backend
and gen12. Add support for execlist backend and gen11 as well.
Is the implication f6aa0d713c88 ("drm/i915: Add Wa_22011802037
force cs halt") does not work on Tigerlake? Fixes: tag
probably required in that case since I have sold that fix as
a, well, fix.
After the fix was made, the WA has evolved and added some more
steps for handling pending MI_FORCE_WAKEs. This patch is the
additional set of steps needed for the WA. As you mentioned
offline, I should correct the commit message to indicate that
the WA does exist for execlists, but needs additional steps.
Will add Fixes: tag.
Ok, that would be good then since it does sound they need to be
tied together (as in cherry picked for fixes).
Will it be followed up with preempt-to-idle implementation to
avoid the, as I understand it, potential for activity on one CCS
engine defeating the WA on another by timing out the wait for
idle?
fwiu, for the case where we want to limit the reset to a single
engine, the preempt-to-idle implementation may be required -
https://patchwork.freedesktop.org/series/101432/. If preempt-to-idle
fails, the hangcheck should kick in and then do a gt-reset. If that
happens, then the WA flow in the patch should be applied.
Okay I read that as yes. That is fine by me since this patch alone is
better than without it.
I have a general doubt for engines that do NOT share a reset domain,
specifically for execlist backend.
What is the expectation/behavior with the hangcheck initiated reset. It
says resetting chip for the engine that it decides is hung. In that path
it calls gt_reset which loops through engines (reset_prepare, rewind,
etc.). Are all running contexts victimized? OR is there an attempt to
preempt-to-idle contexts on other (innocent) engines and then resubmit
them if successfully preempted?
Thanks,
Umesh
Re: [Intel-gfx] [PATCH v2 03/12] drm/i915/pvc: Define MOCS table for PVC
On Thu, May 05, 2022 at 02:38:03PM -0700, Matt Roper wrote:
From: Ayaz A Siddiqui
v2 (MattR):
- Clarify comment above RING_CMD_CCTL programming.
- Remove bspec reference from field definition. (Lucas)
- Add WARN if we try to use a (presumably uninitialized) wb_index of 0.
On most platforms 0 is an invalid MOCS entry and even on the ones
where it isn't, it isn't the right setting for wb_index. (Lucas)
Bspec: 45101, 72161
Cc: Lucas De Marchi
Signed-off-by: Ayaz A Siddiqui
Signed-off-by: Fei Yang
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_types.h| 1 +
drivers/gpu/drm/i915/gt/intel_mocs.c| 24 -
drivers/gpu/drm/i915/gt/intel_workarounds.c | 30 -
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/intel_device_info.h| 1 +
6 files changed, 53 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index b06611c1d4ad..7853ea194ea6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -221,6 +221,7 @@ struct intel_gt {
struct {
u8 uc_index;
+ u8 wb_index; /* Only for platforms listed in Bspec: 72161 */
doesn't correspond to changelog
other than that, Reviewed-by: Lucas De Marchi
Lucas De Marchi
} mocs;
struct intel_pxp pxp;
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index c4c37585ae8c..c6ebe2781076 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -23,6 +23,7 @@ struct drm_i915_mocs_table {
unsigned int n_entries;
const struct drm_i915_mocs_entry *table;
u8 uc_index;
+ u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */
u8 unused_entries_index;
};
@@ -47,6 +48,7 @@ struct drm_i915_mocs_table {
/* Helper defines */
#define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
+#define PVC_NUM_MOCS_ENTRIES 3
/* (e)LLC caching options */
/*
@@ -394,6 +396,17 @@ static const struct drm_i915_mocs_entry
dg2_mocs_table_g10_ax[] = {
MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
};
+static const struct drm_i915_mocs_entry pvc_mocs_table[] = {
+ /* Error */
+ MOCS_ENTRY(0, 0, L3_3_WB),
+
+ /* UC */
+ MOCS_ENTRY(1, 0, L3_1_UC),
+
+ /* WB */
+ MOCS_ENTRY(2, 0, L3_3_WB),
+};
+
enum {
HAS_GLOBAL_MOCS = BIT(0),
HAS_ENGINE_MOCS = BIT(1),
@@ -423,7 +436,14 @@ static unsigned int get_mocs_settings(const struct
drm_i915_private *i915,
memset(table, 0, sizeof(struct drm_i915_mocs_table));
table->unused_entries_index = I915_MOCS_PTE;
- if (IS_DG2(i915)) {
+ if (IS_PONTEVECCHIO(i915)) {
+ table->size = ARRAY_SIZE(pvc_mocs_table);
+ table->table = pvc_mocs_table;
+ table->n_entries = PVC_NUM_MOCS_ENTRIES;
+ table->uc_index = 1;
+ table->wb_index = 2;
+ table->unused_entries_index = 2;
+ } else if (IS_DG2(i915)) {
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
table->size = ARRAY_SIZE(dg2_mocs_table_g10_ax);
table->table = dg2_mocs_table_g10_ax;
@@ -622,6 +642,8 @@ void intel_set_mocs_index(struct intel_gt *gt)
get_mocs_settings(gt->i915, );
gt->mocs.uc_index = table.uc_index;
+ if (HAS_L3_CCS_READ(gt->i915))
+ gt->mocs.wb_index = table.wb_index;
}
void intel_mocs_init(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a05c4b99b3fb..756807c4b405 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1994,19 +1994,37 @@ void intel_engine_apply_whitelist(struct
intel_engine_cs *engine)
static void
engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
- u8 mocs;
+ u8 mocs_w, mocs_r;
/*
-* RING_CMD_CCTL are need to be programed to un-cached
-* for memory writes and reads outputted by Command
-* Streamers on Gen12 onward platforms.
+* RING_CMD_CCTL specifies the default MOCS entry that will be used
+* by the command streamer when executing commands that don't have
+* a way to explicitly specify a MOCS setting. The default should
+* usually reference whichever MOCS entry corresponds to uncached
+* behavior, although use of a WB cached entry is recommended by the
+* spec in certain circumstances on specific platforms.
*/
if (GRAPHICS_VER(engine->i915) >= 12) {
- mocs = engine->gt->mocs.uc_index;
+ mocs_r = engine->gt->mocs.uc_index;
+ mocs_w =
Re: [Intel-gfx] [PATCH] fbdev: efifb: Fix a use-after-free due early fb_info cleanup
On 06.05.2022 15:22, Javier Martinez Canillas wrote:
Commit d258d00fb9c7 ("fbdev: efifb: Cleanup fb_info in .fb_destroy rather
than .remove") attempted to fix a use-after-free error due driver freeing
the fb_info in the .remove handler instead of doing it in .fb_destroy.
But ironically that change introduced yet another use-after-free since the
fb_info was still used after the free.
This should fix for good by freeing the fb_info at the end of the handler.
Fixes: d258d00fb9c7 ("fbdev: efifb: Cleanup fb_info in .fb_destroy rather than
.remove")
Reported-by: Ville Syrjälä
Reported-by: Andrzej Hajda
Signed-off-by: Javier Martinez Canillas
---
Reviewed-by: Andrzej Hajda
Regards
Andrzej
drivers/video/fbdev/efifb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/fbdev/efifb.c b/drivers/video/fbdev/efifb.c
index cfa3dc0b4eee..b3d5f884c544 100644
--- a/drivers/video/fbdev/efifb.c
+++ b/drivers/video/fbdev/efifb.c
@@ -259,12 +259,12 @@ static void efifb_destroy(struct fb_info *info)
memunmap(info->screen_base);
}
- framebuffer_release(info);
-
if (request_mem_succeeded)
release_mem_region(info->apertures->ranges[0].base,
info->apertures->ranges[0].size);
fb_dealloc_cmap(>cmap);
+
+ framebuffer_release(info);
}
static const struct fb_ops efifb_ops = {
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pxp: fix sparse warning for not declared symbol
== Series Details == Series: drm/i915/pxp: fix sparse warning for not declared symbol URL : https://patchwork.freedesktop.org/series/103673/ State : success == Summary == CI Bug Log - changes from CI_DRM_11617_full -> Patchwork_103673v1_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103673v1/index.html Participating hosts (11 -> 7) -- Missing(4): pig-skl-6260u pig-kbl-iris shard-tglu pig-glk-j5005 Known issues Here are the changes found in Patchwork_103673v1_full that come from known issues: ### IGT changes ### Issues hit * igt@kms_big_fb@linear-64bpp-rotate-0: - shard-snb: [PASS][1] -> [SKIP][2] ([fdo#109271]) +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11617/shard-snb4/igt@kms_big...@linear-64bpp-rotate-0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103673v1/shard-snb7/igt@kms_big...@linear-64bpp-rotate-0.html Possible fixes * igt@gem_mmap_gtt@coherency: - shard-snb: [SKIP][3] ([fdo#109271]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11617/shard-snb6/igt@gem_mmap_...@coherency.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103673v1/shard-snb4/igt@gem_mmap_...@coherency.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 Build changes - * Linux: CI_DRM_11617 -> Patchwork_103673v1 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_11617: d96cea3d7ffb524248fcc8db433c579cf262eaea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_103673v1: d96cea3d7ffb524248fcc8db433c579cf262eaea @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103673v1/index.html
Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Use non-blocking H2G for waitboost
On 5/6/2022 00:18, Tvrtko Ursulin wrote: On 05/05/2022 19:36, John Harrison wrote: On 5/5/2022 10:21, Belgaumkar, Vinay wrote: On 5/5/2022 5:13 AM, Tvrtko Ursulin wrote: On 05/05/2022 06:40, Vinay Belgaumkar wrote: SLPC min/max frequency updates require H2G calls. We are seeing timeouts when GuC channel is backed up and it is unable to respond in a timely fashion causing warnings and affecting CI. Is it the "Unable to force min freq" error? Do you have a link to the GitLab issue to add to commit message? We don't have a specific error for this one, but have seen similar issues with other H2G which are blocking. This is seen when waitboosting happens during a stress test. this patch updates the waitboost path to use a non-blocking H2G call instead, which returns as soon as the message is successfully transmitted. AFAIU with this approach, when CT channel is congested, you instead achieve silent dropping of the waitboost request, right? We are hoping it makes it, but just not waiting for it to complete. We are not 'hoping it makes it'. We know for a fact that it will make it. We just don't know when. The issue is not about whether the waitboost request itself gets dropped/lost it is about the ack that comes back. The GuC will process the message and it will send an ack. It's just a question of whether the i915 driver has given up waiting for it yet. And if it has, then you get the initial 'timed out waiting for ack' followed by a later 'got unexpected ack' message. Whereas, if we make the call asynchronous, there is no ack. i915 doesn't bother waiting and it won't get surprised later. Also, note that this is only an issue when GuC itself is backed up. Normally that requires the creation/destruction of large numbers of contexts in rapid succession (context management is about the slowest thing we do with GuC). Some of the IGTs and selftests do that with thousands of contexts all at once. Those are generally where we see this kind of problem. It would be highly unlikely (but not impossible) to hit it in real world usage. Goto -> The general design philosophy of H2G messages is that asynchronous mode should be used for everything if at all possible. It is fire and forget and will all get processed in the order sent (same as batch buffer execution, really). Synchronous messages should only be used when an ack/status is absolutely required. E.g. start of day initialisation or things like TLB invalidation where we need to know that a cache has been cleared/flushed before updating memory from the CPU. John. It sounds like a potentially important feedback from the field to lose so easily. How about you added drm_notice to the worker when it fails? Or simply a "one line patch" to replace i915_probe_error (!?) with drm_notice and keep the blocking behavior. (I have no idea what is the typical time to drain the CT buffer, and so to decide whether waiting or dropping makes more sense for effectiveness of waitboosting.) Or since the congestion /should not/ happen in production, then the argument is why complicate with more code, in which case going with one line patch is an easy way forward? Here. Where I did hint I understood the "should not happen in production angle". So statement is GuC is congested in processing requests, but the h2g buffer is not congested so no chance intel_guc_send_nb() will fail with no space in that buffer? Sounds a bit un-intuitive. That's two different things. The problem of no space in the H2G buffer is the same whether the call is sent blocking or non-blocking. The wait-for-space version is intel_guc_send_busy_loop() rather than intel_guc_send_nb(). NB: _busy_loop is a wrapper around _nb, so the wait-for-space version is also non-blocking ;). If a non-looping version is used (blocking or otherwise) it will return -EBUSY if there is no space. So both the original SLPC call and this non-blocking version will still get an immediate EBUSY return code if the H2G channel is backed up completely. Whether the code should be handling EBUSY or not is another matter. Vinay, does anything higher up do a loop on EBUSY? If not, maybe it should be using the _busy_loop() call instead? The blocking vs non-blocking is about waiting for a response if the command is successfully sent. The blocking case will sit and spin for a reply, the non-blocking assumes success and expects an asynchronous error report on failure. The assumption being that the call can't fail unless something is already broken - i915 sending invalid data to GuC for example. And thus any failure is in the BUG_ON category rather than the try again with a different approach and/or try again later category. This is the point of the change. We are currently getting timeout errors when the H2G channel has space so the command can be sent, but the channel already contains a lot of slow operations. The command has been sent and will be processed
Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Use non-blocking H2G for waitboost
On 5/6/2022 12:18 AM, Tvrtko Ursulin wrote:
On 05/05/2022 19:36, John Harrison wrote:
On 5/5/2022 10:21, Belgaumkar, Vinay wrote:
On 5/5/2022 5:13 AM, Tvrtko Ursulin wrote:
On 05/05/2022 06:40, Vinay Belgaumkar wrote:
SLPC min/max frequency updates require H2G calls. We are seeing
timeouts when GuC channel is backed up and it is unable to respond
in a timely fashion causing warnings and affecting CI.
Is it the "Unable to force min freq" error? Do you have a link to
the GitLab issue to add to commit message?
We don't have a specific error for this one, but have seen similar
issues with other H2G which are blocking.
This is seen when waitboosting happens during a stress test.
this patch updates the waitboost path to use a non-blocking
H2G call instead, which returns as soon as the message is
successfully transmitted.
AFAIU with this approach, when CT channel is congested, you instead
achieve silent dropping of the waitboost request, right?
We are hoping it makes it, but just not waiting for it to complete.
We are not 'hoping it makes it'. We know for a fact that it will make
it. We just don't know when. The issue is not about whether the
waitboost request itself gets dropped/lost it is about the ack that
comes back. The GuC will process the message and it will send an ack.
It's just a question of whether the i915 driver has given up waiting
for it yet. And if it has, then you get the initial 'timed out
waiting for ack' followed by a later 'got unexpected ack' message.
Whereas, if we make the call asynchronous, there is no ack. i915
doesn't bother waiting and it won't get surprised later.
Also, note that this is only an issue when GuC itself is backed up.
Normally that requires the creation/destruction of large numbers of
contexts in rapid succession (context management is about the slowest
thing we do with GuC). Some of the IGTs and selftests do that with
thousands of contexts all at once. Those are generally where we see
this kind of problem. It would be highly unlikely (but not
impossible) to hit it in real world usage.
Goto ->
The general design philosophy of H2G messages is that asynchronous
mode should be used for everything if at all possible. It is fire and
forget and will all get processed in the order sent (same as batch
buffer execution, really). Synchronous messages should only be used
when an ack/status is absolutely required. E.g. start of day
initialisation or things like TLB invalidation where we need to know
that a cache has been cleared/flushed before updating memory from the
CPU.
John.
It sounds like a potentially important feedback from the field to
lose so easily. How about you added drm_notice to the worker when
it fails?
Or simply a "one line patch" to replace i915_probe_error (!?) with
drm_notice and keep the blocking behavior. (I have no idea what is
the typical time to drain the CT buffer, and so to decide whether
waiting or dropping makes more sense for effectiveness of
waitboosting.)
Or since the congestion /should not/ happen in production, then the
argument is why complicate with more code, in which case going with
one line patch is an easy way forward?
Here. Where I did hint I understood the "should not happen in
production angle".
So statement is GuC is congested in processing requests, but the h2g
buffer is not congested so no chance intel_guc_send_nb() will fail
with no space in that buffer? Sounds a bit un-intuitive.
Anyway, it sounds okay to me to use the non-blocking, but I would like
to see some logging if the unexpected does happen. Hence I was
suggesting the option of adding drm_notice logging if the send fails
from the worker. (Because I think other callers would already
propagate the error, like sysfs.)
err = slpc_force_min_freq(slpc, slpc->boost_freq);
if (!err)
slpc->num_boosts++;
else
drm_notice(... "Failed to send waitboost request (%d)", err);
Ok, makes sense. Will send out another rev with this change.
Thanks,
Vinay.
Something like that.
Regards,
Tvrtko
Even if we soften the blow here, the actual timeout error occurs in
the intel_guc_ct.c code, so we cannot hide that error anyways.
Making this call non-blocking will achieve both things.
Thanks,
Vinay.
Regards,
Tvrtko
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 38
-
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 1db833da42df..c852f73cf521 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -98,6 +98,30 @@ static u32 slpc_get_state(struct intel_guc_slpc
*slpc)
return data->header.global_state;
}
+static int guc_action_slpc_set_param_nb(struct intel_guc *guc,
u8 id, u32 value)
+{
+ u32 request[] = {
+ GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Eliminate PIPECONF RMWs from .color_commit() (rev4)
== Series Details == Series: drm/i915: Eliminate PIPECONF RMWs from .color_commit() (rev4) URL : https://patchwork.freedesktop.org/series/102666/ State : success == Summary == CI Bug Log - changes from CI_DRM_11617_full -> Patchwork_102666v4_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102666v4/index.html Participating hosts (11 -> 7) -- Missing(4): pig-skl-6260u pig-kbl-iris shard-tglu pig-glk-j5005 Known issues Here are the changes found in Patchwork_102666v4_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_flush@basic-wb-pro-default: - shard-snb: [PASS][1] -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11617/shard-snb2/igt@gem_exec_fl...@basic-wb-pro-default.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102666v4/shard-snb6/igt@gem_exec_fl...@basic-wb-pro-default.html Possible fixes * igt@gem_mmap_gtt@coherency: - shard-snb: [SKIP][3] ([fdo#109271]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11617/shard-snb6/igt@gem_mmap_...@coherency.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102666v4/shard-snb4/igt@gem_mmap_...@coherency.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 Build changes - * Linux: CI_DRM_11617 -> Patchwork_102666v4 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_11617: d96cea3d7ffb524248fcc8db433c579cf262eaea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_102666v4: d96cea3d7ffb524248fcc8db433c579cf262eaea @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102666v4/index.html
[Intel-gfx] ✓ Fi.CI.BAT: success for Expose max and current bpc via debugfs (rev4)
== Series Details ==
Series: Expose max and current bpc via debugfs (rev4)
URL : https://patchwork.freedesktop.org/series/102502/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11617 -> Patchwork_102502v4
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v4/index.html
Participating hosts (45 -> 45)
--
Additional (2): bat-rpls-1 fi-snb-2520m
Missing(2): bat-adlm-1 fi-bsw-cyan
Known issues
Here are the changes found in Patchwork_102502v4 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@basic:
- fi-snb-2520m: NOTRUN -> [SKIP][1] ([fdo#109271]) +24 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v4/fi-snb-2520m/igt@gem_lmem_swapp...@basic.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-snb-2520m: NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#111827]) +8
similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v4/fi-snb-2520m/igt@kms_chamel...@hdmi-hpd-fast.html
Warnings
* igt@runner@aborted:
- bat-dg1-6: [FAIL][3] ([i915#4312] / [i915#5257]) -> [FAIL][4]
([i915#5616])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11617/bat-dg1-6/igt@run...@aborted.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v4/bat-dg1-6/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5616]: https://gitlab.freedesktop.org/drm/intel/issues/5616
[i915#5879]: https://gitlab.freedesktop.org/drm/intel/issues/5879
Build changes
-
* IGT: IGT_6468 -> IGTPW_7046
* Linux: CI_DRM_11617 -> Patchwork_102502v4
CI-20190529: 20190529
CI_DRM_11617: d96cea3d7ffb524248fcc8db433c579cf262eaea @
git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7046: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7046/index.html
IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_102502v4: d96cea3d7ffb524248fcc8db433c579cf262eaea @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
e655dc1adebf drm/amd/display: Move connector debugfs to drm
baf252b9eabb drm/i915/display/debug: Expose crtc current bpc via debugfs
9d7caa37779d drm/debug: Expose connector's max supported bpc via debugfs
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v4/index.html
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Expose max and current bpc via debugfs (rev4)
== Series Details == Series: Expose max and current bpc via debugfs (rev4) URL : https://patchwork.freedesktop.org/series/102502/ State : warning == Summary == Error: dim checkpatch failed e8b34c163d1c drm/debug: Expose connector's max supported bpc via debugfs -:21: WARNING:BAD_SIGN_OFF: 'Reviewed-by:' is the preferred signature form #21: Reviewed-By: Arun R Murthy total: 0 errors, 1 warnings, 0 checks, 33 lines checked 73d767b83f8e drm/i915/display/debug: Expose crtc current bpc via debugfs f14f0c99554a drm/amd/display: Move connector debugfs to drm
Re: [Intel-gfx] [PATCH] fbdev: efifb: Fix a use-after-free due early fb_info cleanup
Hi Javier,
On Fri, May 06, 2022 at 03:22:25PM +0200, Javier Martinez Canillas wrote:
> Commit d258d00fb9c7 ("fbdev: efifb: Cleanup fb_info in .fb_destroy rather
> than .remove") attempted to fix a use-after-free error due driver freeing
> the fb_info in the .remove handler instead of doing it in .fb_destroy.
>
> But ironically that change introduced yet another use-after-free since the
> fb_info was still used after the free.
>
> This should fix for good by freeing the fb_info at the end of the handler.
>
> Fixes: d258d00fb9c7 ("fbdev: efifb: Cleanup fb_info in .fb_destroy rather
> than .remove")
> Reported-by: Ville Syrjälä
> Reported-by: Andrzej Hajda
> Signed-off-by: Javier Martinez Canillas
Reviewed-by: Andi Shyti
Andi
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Ensure damage clip area is within pipe area
On Fri, 2022-05-06 at 08:48 +0300, Jouni Högander wrote:
> Current update area calculation is not handling situation where
> e.g. cursor plane is fully or partially outside pipe area.
>
> Fix this by checking damage area against pipe_src area using
> drm_rect_intersect.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5440
> Cc: José Roberto de Souza
> Cc: Mika Kahola
> Tested-by: Mark Pearson
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 17 +
> 1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8c099d24de86..5229ba89a079 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1724,6 +1724,10 @@ int intel_psr2_sel_fetch_update(struct
> intel_atomic_state *state,
> break;
> }
>
> + /* Set x1 and x2 for drm_rect_intersect usage */
> + damaged_area.x1 = 0;
> + damaged_area.x2 = INT_MAX;
Move the above to the variable definition and initialization.
> +
> /*
>* If visibility or plane moved, mark the whole plane area as
>* damaged as it needs to be complete redraw in the new and old
> @@ -1735,20 +1739,23 @@ int intel_psr2_sel_fetch_update(struct
> intel_atomic_state *state,
> if (old_plane_state->uapi.visible) {
> damaged_area.y1 = old_plane_state->uapi.dst.y1;
> damaged_area.y2 = old_plane_state->uapi.dst.y2;
> - clip_area_update(_clip, _area);
> + if (drm_rect_intersect(_area,
> _state->pipe_src))
> + clip_area_update(_clip,
> _area);
> }
>
> if (new_plane_state->uapi.visible) {
> damaged_area.y1 = new_plane_state->uapi.dst.y1;
> damaged_area.y2 = new_plane_state->uapi.dst.y2;
> - clip_area_update(_clip, _area);
> + if (drm_rect_intersect(_area,
> _state->pipe_src))
> + clip_area_update(_clip,
> _area);
> }
> continue;
> } else if (new_plane_state->uapi.alpha !=
> old_plane_state->uapi.alpha) {
> /* If alpha changed mark the whole plane area as
> damaged */
> damaged_area.y1 = new_plane_state->uapi.dst.y1;
> damaged_area.y2 = new_plane_state->uapi.dst.y2;
> - clip_area_update(_clip, _area);
> + if (drm_rect_intersect(_area,
> _state->pipe_src))
> + clip_area_update(_clip, _area);
> continue;
> }
>
> @@ -1767,7 +1774,9 @@ int intel_psr2_sel_fetch_update(struct
> intel_atomic_state *state,
>
> damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1;
> damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1;
> - clip_area_update(_clip, _area);
> +
> + if (drm_rect_intersect(_area, _state->pipe_src))
> + clip_area_update(_clip, _area);
As it is repeating move the drm_rect_intersect() call to clip_area_update(),
adding a crtc_state parameter or pipe_src, your call.
Also please include a Fixes tag to some commit that makes sense so this patch
is backported to older kernels with selective fetch enabled.
> }
>
> if (pipe_clip.y1 == -1)
Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Support programming the EU priority in the GuC descriptor
On 5/6/2022 12:51 AM, Tvrtko Ursulin wrote:
On 05/05/2022 19:56, John Harrison wrote:
On 5/4/2022 16:46, Daniele Ceraolo Spurio wrote:
From: Matthew Brost
In GuC submission mode the EU priority must be updated by the GuC
rather
than the driver as the GuC owns the programming of the context
descriptor.
Given that the GuC code uses the GuC priorities, we can't use a generic
function using i915 priorities for both execlists and GuC submission.
The existing function has therefore been pushed to the execlists
back-end while a new one has been added for GuC.
v2: correctly use the GuC prio.
Cc: John Harrison
Cc: Matt Roper
Signed-off-by: Matthew Brost
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: John Harrison
I've asked for this already - since this seems a fix relevant for DG2,
but now that it has been merged without a Fixes: tag, it will not get
picked up for 5.19 by the scripts.
Maybe I can cherry pick it manually in a few weeks, or maybe you guys
can send it to stable manually once 5.19 is released, please make a
reminder item if you think 5.19 should have it.
I didn't add the tag because DG2 still requires force_probe. If sending
fixes for DG2 is ok, I'll make a reminder and I'll send it manually later.
Thanks,
Daniele
Regards,
Tvrtko
---
.../drm/i915/gt/intel_execlists_submission.c | 12 +-
drivers/gpu/drm/i915/gt/intel_lrc.h | 10 -
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 22
+++
3 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 86f7a9ac1c394..2b0266cab66b9 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -661,6 +661,16 @@ static inline void
execlists_schedule_out(struct i915_request *rq)
i915_request_put(rq);
}
+static u32 map_i915_prio_to_lrc_desc_prio(int prio)
+{
+ if (prio > I915_PRIORITY_NORMAL)
+ return GEN12_CTX_PRIORITY_HIGH;
+ else if (prio < I915_PRIORITY_NORMAL)
+ return GEN12_CTX_PRIORITY_LOW;
+ else
+ return GEN12_CTX_PRIORITY_NORMAL;
+}
+
static u64 execlists_update_context(struct i915_request *rq)
{
struct intel_context *ce = rq->context;
@@ -669,7 +679,7 @@ static u64 execlists_update_context(struct
i915_request *rq)
desc = ce->lrc.desc;
if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
- desc |= lrc_desc_priority(rq_prio(rq));
+ desc |= map_i915_prio_to_lrc_desc_prio(rq_prio(rq));
/*
* WaIdleLiteRestore:bdw,skl
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h
b/drivers/gpu/drm/i915/gt/intel_lrc.h
index 31be734010db3..a390f0813c8b6 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -111,16 +111,6 @@ enum {
#define XEHP_SW_COUNTER_SHIFT 58
#define XEHP_SW_COUNTER_WIDTH 6
-static inline u32 lrc_desc_priority(int prio)
-{
- if (prio > I915_PRIORITY_NORMAL)
- return GEN12_CTX_PRIORITY_HIGH;
- else if (prio < I915_PRIORITY_NORMAL)
- return GEN12_CTX_PRIORITY_LOW;
- else
- return GEN12_CTX_PRIORITY_NORMAL;
-}
-
static inline void lrc_runtime_start(struct intel_context *ce)
{
struct intel_context_stats *stats = >stats;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 75291e9846c50..8bf8b6d588d43 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2394,6 +2394,26 @@ static int guc_context_policy_init(struct
intel_context *ce, bool loop)
return ret;
}
+static u32 map_guc_prio_to_lrc_desc_prio(u8 prio)
+{
+ /*
+ * this matches the mapping we do in map_i915_prio_to_guc_prio()
+ * (e.g. prio < I915_PRIORITY_NORMAL maps to
GUC_CLIENT_PRIORITY_NORMAL)
+ */
+ switch (prio) {
+ default:
+ MISSING_CASE(prio);
+ fallthrough;
+ case GUC_CLIENT_PRIORITY_KMD_NORMAL:
+ return GEN12_CTX_PRIORITY_NORMAL;
+ case GUC_CLIENT_PRIORITY_NORMAL:
+ return GEN12_CTX_PRIORITY_LOW;
+ case GUC_CLIENT_PRIORITY_HIGH:
+ case GUC_CLIENT_PRIORITY_KMD_HIGH:
+ return GEN12_CTX_PRIORITY_HIGH;
+ }
+}
+
static void prepare_context_registration_info(struct intel_context
*ce,
struct guc_ctxt_registration_info *info)
{
@@ -2420,6 +2440,8 @@ static void
prepare_context_registration_info(struct intel_context *ce,
*/
info->hwlrca_lo = lower_32_bits(ce->lrc.lrca);
info->hwlrca_hi = upper_32_bits(ce->lrc.lrca);
+ if (engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
+ info->hwlrca_lo |=
map_guc_prio_to_lrc_desc_prio(ce->guc_state.prio);
info->flags = CONTEXT_REGISTRATION_FLAG_KMD;
/*
Re: [Intel-gfx] [PATCH 1/2] drm/i915/psr: Use full update In case of area calculation fails
On Fri, 2022-05-06 at 08:48 +0300, Jouni Högander wrote: > Currently we have some corner cases where area calculation fails. For > these sel fetch are calculation ends up having update area as y1 = 0, > y2 = 4. Instead of these values safer option is full update. Aren't you able to reproduce this scenarios with IGT? So why not probably fix the calculations? > > Cc: José Roberto de Souza > Cc: Mika Kahola > Tested-by: Mark Pearson > Signed-off-by: Jouni Högander > --- > drivers/gpu/drm/i915/display/intel_psr.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 06db407e2749..8c099d24de86 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1770,6 +1770,9 @@ int intel_psr2_sel_fetch_update(struct > intel_atomic_state *state, > clip_area_update(_clip, _area); > } > > + if (pipe_clip.y1 == -1) > + full_update = true; > + > if (full_update) > goto skip_sel_fetch_set_loop; >
Re: [Intel-gfx] [PATCH v7 6/7] drm/i915/gt: Create per-tile RPS sysfs interfaces
Hi Jani, On Fri, May 06, 2022 at 02:53:50PM +0300, Jani Nikula wrote: > On Sat, 19 Mar 2022, Andi Shyti wrote: > > +#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \ > > + struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, > > _show, _store); \ > > + struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, > > _mode, _show, _store) > > Consider this macro... > > > + > > +#define INTEL_GT_RPS_SYSFS_ATTR_RO(_name) \ > > + INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL) > > +#define INTEL_GT_RPS_SYSFS_ATTR_RW(_name) \ > > + INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, > > _name##_store) > > + > > +static INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz); > > +static INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz); > > +static INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz); > > +static INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz); > > +static INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz); > > +static INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz); > > +static INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz); > > +static INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz); > > ...and the static keyword here. > > All of the dev_attr_rps_* attributes become non-static, as the static > only applies to the dev_attr_gt_* attributes: right! Missed that! Thanks, will send the fix. Thanks, Andi > CHECK drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c > drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:468:8: warning: symbol > 'dev_attr_rps_act_freq_mhz' was not declared. Should it be static? > drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:469:8: warning: symbol > 'dev_attr_rps_cur_freq_mhz' was not declared. Should it be static? > drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:470:8: warning: symbol > 'dev_attr_rps_boost_freq_mhz' was not declared. Should it be static? > drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:471:8: warning: symbol > 'dev_attr_rps_RP0_freq_mhz' was not declared. Should it be static? > drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:472:8: warning: symbol > 'dev_attr_rps_RP1_freq_mhz' was not declared. Should it be static? > drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:473:8: warning: symbol > 'dev_attr_rps_RPn_freq_mhz' was not declared. Should it be static? > drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:474:8: warning: symbol > 'dev_attr_rps_max_freq_mhz' was not declared. Should it be static? > drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:475:8: warning: symbol > 'dev_attr_rps_min_freq_mhz' was not declared. Should it be static? > > BR, > Jani. > > > -- > Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.BAT: failure for fbdev: efifb: Fix a use-after-free due early fb_info cleanup
== Series Details == Series: fbdev: efifb: Fix a use-after-free due early fb_info cleanup URL : https://patchwork.freedesktop.org/series/103680/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11617 -> Patchwork_103680v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_103680v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_103680v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/index.html Participating hosts (45 -> 33) -- Additional (1): fi-snb-2520m Missing(13): fi-rkl-11600 bat-adls-5 bat-dg1-6 bat-dg2-8 bat-adlm-1 bat-dg2-9 fi-bsw-cyan bat-adlp-6 fi-cfl-guc bat-adln-1 bat-rpls-2 bat-jsl-2 bat-jsl-1 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_103680v1: ### IGT changes ### Possible regressions * igt@gem_tiled_pread_basic: - fi-icl-u2: NOTRUN -> [DMESG-WARN][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-icl-u2/igt@gem_tiled_pread_basic.html Known issues Here are the changes found in Patchwork_103680v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@read_all_entries: - fi-apl-guc: NOTRUN -> [DMESG-WARN][2] ([i915#5595]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-apl-guc/igt@debugfs_test@read_all_entries.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-guc: NOTRUN -> [SKIP][3] ([fdo#109271]) +18 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-kbl-guc/igt@gem_exec_fence@basic-b...@bcs0.html - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_suspend@basic-s0@smem: - fi-tgl-1115g4: NOTRUN -> [DMESG-WARN][5] ([i915#5122]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271]) +9 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-hsw-4770/igt@gem_huc_c...@huc-copy.html - fi-skl-6700k2: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-skl-6700k2/igt@gem_huc_c...@huc-copy.html - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html - fi-kbl-7500u: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-kbl-7500u/igt@gem_huc_c...@huc-copy.html - fi-kbl-8809g: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#2190]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html - fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([i915#2190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html - fi-glk-j4005: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#2190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html - fi-cfl-8109u: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#2190]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html - fi-bxt-dsi: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-bxt-dsi/igt@gem_huc_c...@huc-copy.html - fi-cfl-8700k: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-cfl-8700k/igt@gem_huc_c...@huc-copy.html - fi-icl-u2: NOTRUN -> [SKIP][16] ([i915#2190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-skl-guc: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-skl-guc/igt@gem_lmem_swapp...@basic.html - fi-glk-j4005: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103680v1/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html - fi-snb-2520m:
Re: [Intel-gfx] [PATCH 07/11] drm/i915/pvc: Engines definitions for new copy engines
On Fri, May 06, 2022 at 08:21:46AM +0100, Tvrtko Ursulin wrote:
>
> On 05/05/2022 21:59, Matt Roper wrote:
> > On Tue, May 03, 2022 at 09:05:43AM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 02/05/2022 17:34, Matt Roper wrote:
> > > > This patch adds the basic definitions needed to support
> > > > new copy engines. Also updating the cmd_info to accommodate
> > > > new engines, as the engine id's of legacy engines have been
> > > > changed.
> > > >
> > > > Original-author: CQ Tang
> > > > Signed-off-by: Matt Roper
> > > > ---
> > > >drivers/gpu/drm/i915/gt/intel_engine_cs.c| 56
> > > >
> > > >drivers/gpu/drm/i915/gt/intel_engine_types.h | 10 +++-
> > > >drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +++
> > > >drivers/gpu/drm/i915/gvt/cmd_parser.c| 2 +-
> > > >drivers/gpu/drm/i915/i915_reg.h | 8 +++
> > > >5 files changed, 82 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > > index 14c6ddbbfde8..4532c3ea9ace 100644
> > > > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > > @@ -71,6 +71,62 @@ static const struct engine_info intel_engines[] = {
> > > > { .graphics_ver = 6, .base = BLT_RING_BASE }
> > > > },
> > > > },
> > > > + [BCS1] = {
> > > > + .class = COPY_ENGINE_CLASS,
> > > > + .instance = 1,
> > > > + .mmio_bases = {
> > > > + { .graphics_ver = 12, .base =
> > > > XEHPC_BCS1_RING_BASE }
> > > > + },
> > > > + },
> > > > + [BCS2] = {
> > > > + .class = COPY_ENGINE_CLASS,
> > > > + .instance = 2,
> > > > + .mmio_bases = {
> > > > + { .graphics_ver = 12, .base =
> > > > XEHPC_BCS2_RING_BASE }
> > > > + },
> > > > + },
> > > > + [BCS3] = {
> > > > + .class = COPY_ENGINE_CLASS,
> > > > + .instance = 3,
> > > > + .mmio_bases = {
> > > > + { .graphics_ver = 12, .base =
> > > > XEHPC_BCS3_RING_BASE }
> > > > + },
> > > > + },
> > > > + [BCS4] = {
> > > > + .class = COPY_ENGINE_CLASS,
> > > > + .instance = 4,
> > > > + .mmio_bases = {
> > > > + { .graphics_ver = 12, .base =
> > > > XEHPC_BCS4_RING_BASE }
> > > > + },
> > > > + },
> > > > + [BCS5] = {
> > > > + .class = COPY_ENGINE_CLASS,
> > > > + .instance = 5,
> > > > + .mmio_bases = {
> > > > + { .graphics_ver = 12, .base =
> > > > XEHPC_BCS5_RING_BASE }
> > > > + },
> > > > + },
> > > > + [BCS6] = {
> > > > + .class = COPY_ENGINE_CLASS,
> > > > + .instance = 6,
> > > > + .mmio_bases = {
> > > > + { .graphics_ver = 12, .base =
> > > > XEHPC_BCS6_RING_BASE }
> > > > + },
> > > > + },
> > > > + [BCS7] = {
> > > > + .class = COPY_ENGINE_CLASS,
> > > > + .instance = 7,
> > > > + .mmio_bases = {
> > > > + { .graphics_ver = 12, .base =
> > > > XEHPC_BCS7_RING_BASE }
> > > > + },
> > > > + },
> > > > + [BCS8] = {
> > > > + .class = COPY_ENGINE_CLASS,
> > > > + .instance = 8,
> > > > + .mmio_bases = {
> > > > + { .graphics_ver = 12, .base =
> > > > XEHPC_BCS8_RING_BASE }
> > > > + },
> > > > + },
> > > > [VCS0] = {
> > > > .class = VIDEO_DECODE_CLASS,
> > > > .instance = 0,
> > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > > b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > > index 298f2cc7a879..356c15cdccf0 100644
> > > > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > > @@ -35,7 +35,7 @@
> > > >#define OTHER_CLASS 4
> > > >#define COMPUTE_CLASS5
> > > >#define MAX_ENGINE_CLASS 5
> > > > -#define MAX_ENGINE_INSTANCE7
> > > > +#define MAX_ENGINE_INSTANCE8
> > > >#define I915_MAX_SLICES 3
> > > >#define I915_MAX_SUBSLICES 8
> > > > @@ -107,6 +107,14 @@ struct i915_ctx_workarounds {
> > > >enum intel_engine_id {
> > > > RCS0 = 0,
> > > > BCS0,
> > > > + BCS1,
> > > > + BCS2,
> > > > + BCS3,
> > > > + BCS4,
> > > > + BCS5,
> > > > + BCS6,
> > > > + BCS7,
> > > > + BCS8,
> > >
> > > _BCS(n) macro will not be required?
> > >
> > > > VCS0,
> > > > VCS1,
> > > > VCS2,
> > > >
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Add smem fallback allocation for dpt
== Series Details == Series: series starting with [1/2] drm/i915/display: Add smem fallback allocation for dpt URL : https://patchwork.freedesktop.org/series/103678/ State : success == Summary == CI Bug Log - changes from CI_DRM_11617 -> Patchwork_103678v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103678v1/index.html Participating hosts (45 -> 34) -- Additional (1): fi-snb-2520m Missing(12): fi-bxt-dsi bat-adls-5 bat-dg1-6 bat-dg2-8 bat-adlm-1 bat-dg2-9 fi-bsw-cyan bat-adlp-6 bat-adln-1 bat-rpls-2 bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_103678v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@basic: - fi-snb-2520m: NOTRUN -> [SKIP][1] ([fdo#109271]) +24 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103678v1/fi-snb-2520m/igt@gem_lmem_swapp...@basic.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-snb-2520m: NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#111827]) +8 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103678v1/fi-snb-2520m/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 Build changes - * Linux: CI_DRM_11617 -> Patchwork_103678v1 CI-20190529: 20190529 CI_DRM_11617: d96cea3d7ffb524248fcc8db433c579cf262eaea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_103678v1: d96cea3d7ffb524248fcc8db433c579cf262eaea @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 917898e4eee6 drm/i915: Fix i915_vma_pin_iomap() 07c3d8bd88b1 drm/i915/display: Add smem fallback allocation for dpt == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103678v1/index.html
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display: Add smem fallback allocation for dpt
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Add smem fallback
allocation for dpt
URL : https://patchwork.freedesktop.org/series/103678/
State : warning
== Summary ==
Error: dim checkpatch failed
cb0cd39c87aa drm/i915/display: Add smem fallback allocation for dpt
5fc338ca8432 drm/i915: Fix i915_vma_pin_iomap()
-:44: CHECK:BRACES: Unbalanced braces around else statement
#44: FILE: drivers/gpu/drm/i915/i915_vma.c:572:
+ else {
-:47: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#47: FILE: drivers/gpu/drm/i915/i915_vma.c:575:
+ i915_gem_object_pin_map_unlocked(vma->obj,
+ I915_MAP_WC);
total: 0 errors, 0 warnings, 2 checks, 73 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pxp: fix sparse warning for not declared symbol
== Series Details == Series: drm/i915/pxp: fix sparse warning for not declared symbol URL : https://patchwork.freedesktop.org/series/103673/ State : success == Summary == CI Bug Log - changes from CI_DRM_11617 -> Patchwork_103673v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103673v1/index.html Participating hosts (45 -> 34) -- Additional (1): fi-snb-2520m Missing(12): bat-adls-5 bat-dg1-6 bat-dg2-8 fi-skl-guc bat-adlm-1 bat-dg2-9 fi-bsw-cyan bat-adlp-6 bat-adln-1 bat-rpls-2 bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_103673v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@basic: - fi-snb-2520m: NOTRUN -> [SKIP][1] ([fdo#109271]) +24 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103673v1/fi-snb-2520m/igt@gem_lmem_swapp...@basic.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#111827]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103673v1/fi-snb-2600/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-snb-2520m: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103673v1/fi-snb-2520m/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[INCOMPLETE][4] ([i915#3921]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11617/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103673v1/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 Build changes - * Linux: CI_DRM_11617 -> Patchwork_103673v1 CI-20190529: 20190529 CI_DRM_11617: d96cea3d7ffb524248fcc8db433c579cf262eaea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_103673v1: d96cea3d7ffb524248fcc8db433c579cf262eaea @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 5ddacc70a7f9 drm/i915/pxp: fix sparse warning for not declared symbol == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103673v1/index.html
[Intel-gfx] ✓ Fi.CI.IGT: success for Expose max and current bpc via debugfs (rev3)
== Series Details ==
Series: Expose max and current bpc via debugfs (rev3)
URL : https://patchwork.freedesktop.org/series/102502/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11616_full -> Patchwork_102502v3_full
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/index.html
Participating hosts (12 -> 8)
--
Missing(4): pig-skl-6260u pig-kbl-iris shard-rkl pig-glk-j5005
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_102502v3_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_hdr@bpc-switch@bpc-switch-hdmi-a-1-pipe-a:
- {shard-tglu}: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/shard-tglu-6/igt@kms_hdr@bpc-swi...@bpc-switch-hdmi-a-1-pipe-a.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- {shard-tglu}: ([PASS][2], [PASS][3]) -> [DMESG-WARN][4]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-tglu-5/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-tglu-8/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/shard-tglu-4/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html
Known issues
Here are the changes found in Patchwork_102502v3_full that come from known
issues:
### CI changes ###
Possible fixes
* boot:
- shard-snb: ([PASS][5], [PASS][6], [PASS][7], [PASS][8],
[PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14],
[PASS][15], [PASS][16], [PASS][17], [FAIL][18], [PASS][19], [PASS][20],
[PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26],
[PASS][27], [PASS][28], [PASS][29]) ([i915#4338]) -> ([PASS][30], [PASS][31],
[PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37],
[PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43],
[PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49],
[PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb7/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb7/boot.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb7/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb7/boot.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb7/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb6/boot.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb6/boot.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb6/boot.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb6/boot.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb6/boot.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb5/boot.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb5/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb5/boot.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb5/boot.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb5/boot.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb5/boot.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb4/boot.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb4/boot.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb4/boot.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb4/boot.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb4/boot.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb2/boot.html
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb2/boot.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb2/boot.html
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb2/boot.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/shard-snb5/boot.html
[31]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/shard-snb4/boot.html
[32]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/shard-snb4/boot.html
[33]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/shard-snb4/boot.html
[34]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pxp: fix sparse warning for not declared symbol
== Series Details == Series: drm/i915/pxp: fix sparse warning for not declared symbol URL : https://patchwork.freedesktop.org/series/103673/ State : warning == Summary == Error: dim checkpatch failed 151a8d341bdd drm/i915/pxp: fix sparse warning for not declared symbol -:4: WARNING:EMAIL_SUBJECT: A patch subject line should describe the change not the tool that found it #4: Subject: [PATCH] drm/i915/pxp: fix sparse warning for not declared symbol total: 0 errors, 1 warnings, 0 checks, 12 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Eliminate PIPECONF RMWs from .color_commit() (rev4)
== Series Details ==
Series: drm/i915: Eliminate PIPECONF RMWs from .color_commit() (rev4)
URL : https://patchwork.freedesktop.org/series/102666/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11617 -> Patchwork_102666v4
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102666v4/index.html
Participating hosts (45 -> 44)
--
Additional (2): bat-rpls-1 fi-snb-2520m
Missing(3): bat-dg2-8 bat-adlm-1 fi-bsw-cyan
Known issues
Here are the changes found in Patchwork_102666v4 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@basic:
- fi-snb-2520m: NOTRUN -> [SKIP][1] ([fdo#109271]) +24 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102666v4/fi-snb-2520m/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][2] -> [DMESG-FAIL][3] ([i915#4528])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11617/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102666v4/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102666v4/fi-snb-2600/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-snb-2520m: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102666v4/fi-snb-2520m/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][6] ([fdo#109271] / [i915#2403] /
[i915#4312])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102666v4/fi-pnv-d510/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][7] ([i915#3921]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11617/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102666v4/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@runner@aborted:
- bat-dg1-6: [FAIL][9] ([i915#4312] / [i915#5257]) -> [FAIL][10]
([i915#5616])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11617/bat-dg1-6/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102666v4/bat-dg1-6/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5616]: https://gitlab.freedesktop.org/drm/intel/issues/5616
Build changes
-
* Linux: CI_DRM_11617 -> Patchwork_102666v4
CI-20190529: 20190529
CI_DRM_11617: d96cea3d7ffb524248fcc8db433c579cf262eaea @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_102666v4: d96cea3d7ffb524248fcc8db433c579cf262eaea @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
ed44c091a502 drm/i915: Eliminate PIPECONF RMWs from .color_commit()
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102666v4/index.html
Re: [Intel-gfx] [PATCH] fbdev: efifb: Fix a use-after-free due early fb_info cleanup
Am 06.05.22 um 15:22 schrieb Javier Martinez Canillas:
Commit d258d00fb9c7 ("fbdev: efifb: Cleanup fb_info in .fb_destroy rather
than .remove") attempted to fix a use-after-free error due driver freeing
the fb_info in the .remove handler instead of doing it in .fb_destroy.
But ironically that change introduced yet another use-after-free since the
fb_info was still used after the free.
This should fix for good by freeing the fb_info at the end of the handler.
Fixes: d258d00fb9c7 ("fbdev: efifb: Cleanup fb_info in .fb_destroy rather than
.remove")
Reported-by: Ville Syrjälä
Reported-by: Andrzej Hajda
Signed-off-by: Javier Martinez Canillas
Reviewed-by: Thomas Zimmermann
---
drivers/video/fbdev/efifb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/fbdev/efifb.c b/drivers/video/fbdev/efifb.c
index cfa3dc0b4eee..b3d5f884c544 100644
--- a/drivers/video/fbdev/efifb.c
+++ b/drivers/video/fbdev/efifb.c
@@ -259,12 +259,12 @@ static void efifb_destroy(struct fb_info *info)
memunmap(info->screen_base);
}
- framebuffer_release(info);
-
if (request_mem_succeeded)
release_mem_region(info->apertures->ranges[0].base,
info->apertures->ranges[0].size);
fb_dealloc_cmap(>cmap);
+
+ framebuffer_release(info);
}
static const struct fb_ops efifb_ops = {
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Ivo Totev
OpenPGP_signature
Description: OpenPGP digital signature
[Intel-gfx] ✓ Fi.CI.IGT: success for Fixes for selective fetch area calculation
== Series Details == Series: Fixes for selective fetch area calculation URL : https://patchwork.freedesktop.org/series/103659/ State : success == Summary == CI Bug Log - changes from CI_DRM_11616_full -> Patchwork_103659v1_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/index.html Participating hosts (12 -> 8) -- Missing(4): pig-skl-6260u pig-kbl-iris shard-rkl pig-glk-j5005 Known issues Here are the changes found in Patchwork_103659v1_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-snb: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [FAIL][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#4338]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb4/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb2/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb2/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb2/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb2/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb7/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb7/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb7/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb6/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb6/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb6/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb5/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb5/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb5/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb5/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb5/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb5/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb4/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb4/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb4/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/shard-snb4/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb6/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb5/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb5/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb5/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb5/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb5/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb4/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb4/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb4/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb4/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb4/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb2/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb2/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb2/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb2/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/shard-snb2/boot.html [42]:
[Intel-gfx] [PATCH] fbdev: efifb: Fix a use-after-free due early fb_info cleanup
Commit d258d00fb9c7 ("fbdev: efifb: Cleanup fb_info in .fb_destroy rather
than .remove") attempted to fix a use-after-free error due driver freeing
the fb_info in the .remove handler instead of doing it in .fb_destroy.
But ironically that change introduced yet another use-after-free since the
fb_info was still used after the free.
This should fix for good by freeing the fb_info at the end of the handler.
Fixes: d258d00fb9c7 ("fbdev: efifb: Cleanup fb_info in .fb_destroy rather than
.remove")
Reported-by: Ville Syrjälä
Reported-by: Andrzej Hajda
Signed-off-by: Javier Martinez Canillas
---
drivers/video/fbdev/efifb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/fbdev/efifb.c b/drivers/video/fbdev/efifb.c
index cfa3dc0b4eee..b3d5f884c544 100644
--- a/drivers/video/fbdev/efifb.c
+++ b/drivers/video/fbdev/efifb.c
@@ -259,12 +259,12 @@ static void efifb_destroy(struct fb_info *info)
memunmap(info->screen_base);
}
- framebuffer_release(info);
-
if (request_mem_succeeded)
release_mem_region(info->apertures->ranges[0].base,
info->apertures->ranges[0].size);
fb_dealloc_cmap(>cmap);
+
+ framebuffer_release(info);
}
static const struct fb_ops efifb_ops = {
--
2.35.1
[Intel-gfx] [PATCH 2/2] drm/i915: Fix i915_vma_pin_iomap()
From: CQ Tang
Display might allocate a smem object and call
i915_vma_pin_iomap(), the existing code will fail.
This fix was suggested by Chris P Wilson, that we pin
the smem with i915_gem_object_pin_map_unlocked().
Signed-off-by: CQ Tang
Signed-off-by: Juha-Pekka Heikkila
Cc: Chris Wilson
Cc: Jari Tahvanainen
---
drivers/gpu/drm/i915/i915_vma.c | 34 ++---
1 file changed, 23 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 162e8d83691b..8ce016ef3dba 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -550,13 +550,6 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
if (WARN_ON_ONCE(vma->obj->flags & I915_BO_ALLOC_GPU_ONLY))
return IO_ERR_PTR(-EINVAL);
- if (!i915_gem_object_is_lmem(vma->obj)) {
- if (GEM_WARN_ON(!i915_vma_is_map_and_fenceable(vma))) {
- err = -ENODEV;
- goto err;
- }
- }
-
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND));
GEM_BUG_ON(i915_vma_verify_bind_complete(vma));
@@ -572,17 +565,31 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
if (i915_gem_object_is_lmem(vma->obj))
ptr = i915_gem_object_lmem_io_map(vma->obj, 0,
vma->obj->base.size);
- else
+ else if (i915_vma_is_map_and_fenceable(vma))
ptr =
io_mapping_map_wc(_vm_to_ggtt(vma->vm)->iomap,
vma->node.start,
vma->node.size);
+ else {
+ ptr = (void __iomem *)
+ i915_gem_object_pin_map_unlocked(vma->obj,
+ I915_MAP_WC);
+ if (IS_ERR(ptr)) {
+ err = PTR_ERR(ptr);
+ goto err;
+ }
+ ptr = page_pack_bits(ptr, 1);
+ }
+
if (ptr == NULL) {
err = -ENOMEM;
goto err;
}
if (unlikely(cmpxchg(>iomap, NULL, ptr))) {
- io_mapping_unmap(ptr);
+ if (page_unmask_bits(ptr))
+ __i915_gem_object_release_map(vma->obj);
+ else
+ io_mapping_unmap(ptr);
ptr = vma->iomap;
}
}
@@ -596,7 +603,7 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
i915_vma_set_ggtt_write(vma);
/* NB Access through the GTT requires the device to be awake. */
- return ptr;
+ return page_mask_bits(ptr);
err_unpin:
__i915_vma_unpin(vma);
@@ -614,6 +621,8 @@ void i915_vma_unpin_iomap(struct i915_vma *vma)
{
GEM_BUG_ON(vma->iomap == NULL);
+ /* XXX We keep the mapping until __i915_vma_unbind()/evict() */
+
i915_vma_flush_writes(vma);
i915_vma_unpin_fence(vma);
@@ -1761,7 +1770,10 @@ static void __i915_vma_iounmap(struct i915_vma *vma)
if (vma->iomap == NULL)
return;
- io_mapping_unmap(vma->iomap);
+ if (page_unmask_bits(vma->iomap))
+ __i915_gem_object_release_map(vma->obj);
+ else
+ io_mapping_unmap(vma->iomap);
vma->iomap = NULL;
}
--
2.25.1
[Intel-gfx] [PATCH 1/2] drm/i915/display: Add smem fallback allocation for dpt
Add fallback smem allocation for dpt if stolen memory allocation failed.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_dpt.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index fb0e7e79e0cd..10008699656e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -10,6 +10,7 @@
#include "intel_display_types.h"
#include "intel_dpt.h"
#include "intel_fb.h"
+#include "gem/i915_gem_internal.h"
struct i915_dpt {
struct i915_address_space vm;
@@ -128,6 +129,10 @@ struct i915_vma *intel_dpt_pin(struct i915_address_space
*vm)
void __iomem *iomem;
struct i915_gem_ww_ctx ww;
int err;
+ u64 pin_flags = 0;
+
+ if (!i915_gem_object_is_lmem(dpt->obj))
+ pin_flags |= PIN_MAPPABLE;
wakeref = intel_runtime_pm_get(>runtime_pm);
atomic_inc(>gpu_error.pending_fb_pin);
@@ -138,7 +143,7 @@ struct i915_vma *intel_dpt_pin(struct i915_address_space
*vm)
continue;
vma = i915_gem_object_ggtt_pin_ww(dpt->obj, , NULL, 0, 4096,
- HAS_LMEM(i915) ? 0 :
PIN_MAPPABLE);
+ pin_flags);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
continue;
@@ -248,10 +253,13 @@ intel_dpt_create(struct intel_framebuffer *fb)
size = round_up(size * sizeof(gen8_pte_t), I915_GTT_PAGE_SIZE);
- if (HAS_LMEM(i915))
- dpt_obj = i915_gem_object_create_lmem(i915, size,
I915_BO_ALLOC_CONTIGUOUS);
- else
+ dpt_obj = i915_gem_object_create_lmem(i915, size,
I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(dpt_obj) && i915_ggtt_has_aperture(to_gt(i915)->ggtt))
dpt_obj = i915_gem_object_create_stolen(i915, size);
+ if (IS_ERR(dpt_obj) && !HAS_LMEM(i915)) {
+ drm_dbg_kms(>drm, "Allocating dpt from smem\n");
+ dpt_obj = i915_gem_object_create_internal(i915, size);
+ }
if (IS_ERR(dpt_obj))
return ERR_CAST(dpt_obj);
--
2.25.1
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/edid: introduce struct drm_edid (rev2)
== Series Details ==
Series: drm/edid: introduce struct drm_edid (rev2)
URL : https://patchwork.freedesktop.org/series/103665/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11616 -> Patchwork_103665v2
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_103665v2 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_103665v2, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v2/index.html
Participating hosts (42 -> 36)
--
Additional (3): fi-icl-u2 bat-jsl-1 bat-dg2-9
Missing(9): fi-kbl-7567u fi-bdw-5557u bat-adlm-1 fi-bsw-cyan fi-ilk-650
fi-snb-2520m fi-kbl-8809g fi-elk-e7500 fi-snb-2600
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_103665v2:
### CI changes ###
Possible regressions
* boot:
- fi-bdw-gvtdvm: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/fi-bdw-gvtdvm/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v2/fi-bdw-gvtdvm/boot.html
### IGT changes ###
Possible regressions
* igt@kms_force_connector_basic@force-connector-state:
- fi-pnv-d510:[PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/fi-pnv-d510/igt@kms_force_connector_ba...@force-connector-state.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v2/fi-pnv-d510/igt@kms_force_connector_ba...@force-connector-state.html
- fi-bwr-2160:[PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/fi-bwr-2160/igt@kms_force_connector_ba...@force-connector-state.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v2/fi-bwr-2160/igt@kms_force_connector_ba...@force-connector-state.html
- fi-blb-e6850: [PASS][7] -> [INCOMPLETE][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/fi-blb-e6850/igt@kms_force_connector_ba...@force-connector-state.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v2/fi-blb-e6850/igt@kms_force_connector_ba...@force-connector-state.html
Known issues
Here are the changes found in Patchwork_103665v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][9] ([i915#2403] / [i915#4312])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v2/fi-pnv-d510/igt@run...@aborted.html
- fi-icl-u2: NOTRUN -> [FAIL][10] ([i915#3690])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v2/fi-icl-u2/igt@run...@aborted.html
- fi-bwr-2160:NOTRUN -> [FAIL][11] ([i915#4312])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v2/fi-bwr-2160/igt@run...@aborted.html
- fi-blb-e6850: NOTRUN -> [FAIL][12] ([i915#2403] / [i915#4312])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v2/fi-blb-e6850/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#3690]: https://gitlab.freedesktop.org/drm/intel/issues/3690
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#5602]: https://gitlab.freedesktop.org/drm/intel/issues/5602
[i915#5616]: https://gitlab.freedesktop.org/drm/intel/issues/5616
[i915#5917]: https://gitlab.freedesktop.org/drm/intel/issues/5917
Build changes
-
* Linux: CI_DRM_11616 -> Patchwork_103665v2
CI-20190529: 20190529
CI_DRM_11616: 65a5fe9ac96c60bd6dfcc44a0bb8d584912ea53d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6467: 929abc51cdd48d673efa03e025b1f31b557972ed @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103665v2: 65a5fe9ac96c60bd6dfcc44a0bb8d584912ea53d @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
9734c8e38d6c drm/edid: convert version_greater() to drm_edid
8939e8e87b70 drm/displayid: convert to drm_edid
4616e8e39130 drm/edid: add drm_edid helper for drm_update_tile_info()
ce9cf6c3f3bd drm/edid: convert drm_edid_iter_begin() to drm_edid
88cf2acc4d23 drm/edid: convert cea_db_iter_edid_begin() to drm_edid
3697803e34fc drm/edid: add drm_edid helper for drm_detect_monitor_audio()
198071639b3e drm/edid: add drm_edid helper for drm_detect_hdmi_monitor()
c7c8274be0e0 drm/edid: add drm_edid helper for drm_edid_to_speaker_allocation()
10ad8b7391e0 drm/edid: add drm_edid helper for drm_edid_to_sad()
e891c81d67f3 drm/edid: convert
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/edid: introduce struct drm_edid (rev2)
== Series Details == Series: drm/edid: introduce struct drm_edid (rev2) URL : https://patchwork.freedesktop.org/series/103665/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/edid: introduce struct drm_edid (rev2)
== Series Details ==
Series: drm/edid: introduce struct drm_edid (rev2)
URL : https://patchwork.freedesktop.org/series/103665/
State : warning
== Summary ==
Error: dim checkpatch failed
49478b13e157 drm/edid: use else-if in CTA extension parsing
253ce252ebb2 drm/edid: convert drm_for_each_detailed_block() to edid iter
c8d7ad09c4aa drm/edid: add struct drm_edid container
8e89b03ed6a0 drm/edid: start propagating drm_edid to lower levels
-:32: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!drm_edid"
#32: FILE: drivers/gpu/drm/drm_edid.c:5823:
+ if (drm_edid == NULL) {
total: 0 errors, 0 warnings, 1 checks, 43 lines checked
da470150559b drm/edid: keep propagating drm_edid to display info
ab5bc257050a drm/edid: propagate drm_edid to drm_edid_to_eld()
a741fdf94b61 drm/edid: convert drm_edid_connector_update() to drm_edid fully
09ad0a7d5307 drm/edid: convert struct detailed_mode_closure to drm_edid
7b6af4143dd1 drm/edid: convert drm_mode_detailed() to drm_edid
eec9950bca92 drm/edid: convert drm_dmt_modes_for_range() to drm_edid
838b672aecc4 drm/edid: convert drm_gtf_modes_for_range() to drm_edid
3c5ab00b051b drm/edid: convert drm_cvt_modes_for_range() to drm_edid
4dcf8a802425 drm/edid: convert drm_mode_std() and children to drm_edid
ee06f362cf11 drm/edid: convert mode_in_range() and drm_monitor_supports_rb() to
drm_edid
508406f1b73b drm/edid: convert get_monitor_name() to drm_edid
ccbe240b4563 drm/edid: convert drm_for_each_detailed_block() to drm_edid
-:33: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around
drm_edid->edid->detailed_timings[i]
#33: FILE: drivers/gpu/drm/drm_edid.c:2594:
+ cb(&(drm_edid->edid->detailed_timings[i]), closure);
total: 0 errors, 0 warnings, 1 checks, 129 lines checked
64317639af4b drm/edid: add drm_edid helper for drm_edid_to_sad()
990d6dd977b3 drm/edid: add drm_edid helper for drm_edid_to_speaker_allocation()
8f27b7c1913d drm/edid: add drm_edid helper for drm_detect_hdmi_monitor()
c231a095dbf1 drm/edid: add drm_edid helper for drm_detect_monitor_audio()
6cdff6355337 drm/edid: convert cea_db_iter_edid_begin() to drm_edid
eaa41b2334bb drm/edid: convert drm_edid_iter_begin() to drm_edid
8b926179bfd0 drm/edid: add drm_edid helper for drm_update_tile_info()
e09326603eec drm/displayid: convert to drm_edid
e5bea8a49f5c drm/edid: convert version_greater() to drm_edid
[Intel-gfx] [PATCH] drm/i915/pxp: fix sparse warning for not declared symbol
Fix:
drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c:61:6: warning: symbol
'intel_pxp_debugfs_register' was not declared. Should it be static?
Sort and remove the redundant pxp prefixes from the includes while at
it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
index c9da1015eb42..e888b5124a07 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
@@ -9,9 +9,10 @@
#include
#include "gt/intel_gt_debugfs.h"
-#include "pxp/intel_pxp.h"
-#include "pxp/intel_pxp_irq.h"
#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_debugfs.h"
+#include "intel_pxp_irq.h"
static int pxp_info_show(struct seq_file *m, void *data)
{
--
2.30.2
Re: [Intel-gfx] [CI 14/18] drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform
On Fri, 15 Apr 2022, Imre Deak wrote:
> Atm the port -> DDI and AUX power domain mapping is specified by relying
> on the aliasing of the platform specific intel_display_power_domain enum
> values. For instance D12+ platforms refer to the 'D' port and power
> domain instances, which doesn't match the bspec terminology, on these
> platforms the corresponding port is TC1. To make it clear what
> port/domain the code refers to add a mapping between them which matches
> the bspec terms on different display versions.
>
> This also allows for removing the aliasing in enum values in a follow-up
> patch.
>
> v2: Add the functions to intel_display_power.c, use
> intel_display_power_ prefix.
>
> Signed-off-by: Imre Deak
> Reviewed-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/g4x_dp.c | 3 +-
> drivers/gpu/drm/i915/display/g4x_hdmi.c | 3 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +-
> drivers/gpu/drm/i915/display/intel_display.c | 85 +---
> drivers/gpu/drm/i915/display/intel_display.h | 4 +-
> .../drm/i915/display/intel_display_power.c| 206 ++
> .../drm/i915/display/intel_display_power.h| 12 +
> drivers/gpu/drm/i915/display/intel_tc.c | 5 +-
> 8 files changed, 235 insertions(+), 89 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 16bb21ad898b3..5a957acebfd62 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -13,6 +13,7 @@
> #include "intel_connector.h"
> #include "intel_crtc.h"
> #include "intel_de.h"
> +#include "intel_display_power.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_dp_link_training.h"
> @@ -1375,7 +1376,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
> dig_port->max_lanes = 4;
>
> intel_encoder->type = INTEL_OUTPUT_DP;
> - intel_encoder->power_domain = intel_port_to_power_domain(port);
> + intel_encoder->power_domain =
> intel_display_power_ddi_lanes_domain(dev_priv, port);
> if (IS_CHERRYVIEW(dev_priv)) {
> if (port == PORT_D)
> intel_encoder->pipe_mask = BIT(PIPE_C);
> diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> index 8bfef08b7c43f..5fbd2ae958692 100644
> --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> @@ -10,6 +10,7 @@
> #include "intel_connector.h"
> #include "intel_crtc.h"
> #include "intel_de.h"
> +#include "intel_display_power.h"
> #include "intel_display_types.h"
> #include "intel_dpio_phy.h"
> #include "intel_fifo_underrun.h"
> @@ -574,7 +575,7 @@ void g4x_hdmi_init(struct drm_i915_private *dev_priv,
> intel_encoder->shutdown = intel_hdmi_encoder_shutdown;
>
> intel_encoder->type = INTEL_OUTPUT_HDMI;
> - intel_encoder->power_domain = intel_port_to_power_domain(port);
> + intel_encoder->power_domain =
> intel_display_power_ddi_lanes_domain(dev_priv, port);
> intel_encoder->port = port;
> if (IS_CHERRYVIEW(dev_priv)) {
> if (port == PORT_D)
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 01463c4711d3e..d9f238edf547f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -40,6 +40,7 @@
> #include "intel_ddi.h"
> #include "intel_ddi_buf_trans.h"
> #include "intel_de.h"
> +#include "intel_display_power.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_dp_link_training.h"
> @@ -4364,7 +4365,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> encoder->get_power_domains = intel_ddi_get_power_domains;
>
> encoder->type = INTEL_OUTPUT_DDI;
> - encoder->power_domain = intel_port_to_power_domain(port);
> + encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv,
> port);
> encoder->port = port;
> encoder->cloneable = 0;
> encoder->pipe_mask = ~0;
> @@ -4492,8 +4493,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> }
>
> drm_WARN_ON(_priv->drm, port > PORT_I);
> - dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_IO_A +
> - port - PORT_A;
> + dig_port->ddi_io_power_domain =
> intel_display_power_ddi_io_domain(dev_priv, port);
>
> if (init_dp) {
> if (!intel_ddi_init_dp_connector(dig_port))
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 7e9abcbbbcc2f..2bff98908d67f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -51,6 +51,7 @@
> #include "display/intel_crt.h"
> #include "display/intel_ddi.h"
> #include
Re: [Intel-gfx] [PATCH v7 6/7] drm/i915/gt: Create per-tile RPS sysfs interfaces
On Sat, 19 Mar 2022, Andi Shyti wrote: > +#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \ > + struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, > _show, _store); \ > + struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, > _mode, _show, _store) Consider this macro... > + > +#define INTEL_GT_RPS_SYSFS_ATTR_RO(_name)\ > + INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL) > +#define INTEL_GT_RPS_SYSFS_ATTR_RW(_name)\ > + INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, > _name##_store) > + > +static INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz); > +static INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz); > +static INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz); > +static INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz); > +static INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz); > +static INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz); > +static INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz); > +static INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz); ...and the static keyword here. All of the dev_attr_rps_* attributes become non-static, as the static only applies to the dev_attr_gt_* attributes: CHECK drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:468:8: warning: symbol 'dev_attr_rps_act_freq_mhz' was not declared. Should it be static? drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:469:8: warning: symbol 'dev_attr_rps_cur_freq_mhz' was not declared. Should it be static? drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:470:8: warning: symbol 'dev_attr_rps_boost_freq_mhz' was not declared. Should it be static? drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:471:8: warning: symbol 'dev_attr_rps_RP0_freq_mhz' was not declared. Should it be static? drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:472:8: warning: symbol 'dev_attr_rps_RP1_freq_mhz' was not declared. Should it be static? drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:473:8: warning: symbol 'dev_attr_rps_RPn_freq_mhz' was not declared. Should it be static? drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:474:8: warning: symbol 'dev_attr_rps_max_freq_mhz' was not declared. Should it be static? drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:475:8: warning: symbol 'dev_attr_rps_min_freq_mhz' was not declared. Should it be static? BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] amdgpu sparse warnings (was: Re: ✗ Fi.CI.SPARSE: warning for drm/edid: introduce struct drm_edid)
Hey, do you ever run sparse on your driver? Whenever our CI ends up recompiling amdgpu, there's quite the spew. See below. You're not alone, but, sorry to say, the _Static_assert() from amdgv_sriovmsg.h has been pretty obnoxious for quite some time now. First, I don't think you should be using _Static_assert() directly; there's an in-kernel static_assert() wrapper. However, it's the #pragma pack(push, 1) and #pragma pack(pop) pair that sparse does not understand, leaves the structs unpacked, and leads to warnings. BR, Jani. On Fri, 06 May 2022, Patchwork wrote: > == Series Details == > > Series: drm/edid: introduce struct drm_edid > URL : https://patchwork.freedesktop.org/series/103665/ > State : warning > > == Summary == > > Error: dim sparse failed > Sparse version: v0.6.2 > Fast mode used, each commit won't be checked separately. > - > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" > +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: > static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" >
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/edid: introduce struct drm_edid
== Series Details ==
Series: drm/edid: introduce struct drm_edid
URL : https://patchwork.freedesktop.org/series/103665/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11616 -> Patchwork_103665v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_103665v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_103665v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v1/index.html
Participating hosts (42 -> 36)
--
Additional (3): fi-icl-u2 bat-jsl-1 bat-dg2-9
Missing(9): fi-kbl-7567u fi-bxt-dsi fi-bdw-5557u bat-adlm-1 fi-bsw-cyan
fi-ilk-650 fi-snb-2520m fi-kbl-8809g fi-elk-e7500
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_103665v1:
### CI changes ###
Possible regressions
* boot:
- fi-bdw-gvtdvm: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/fi-bdw-gvtdvm/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v1/fi-bdw-gvtdvm/boot.html
### IGT changes ###
Possible regressions
* igt@kms_force_connector_basic@force-connector-state:
- fi-pnv-d510:[PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/fi-pnv-d510/igt@kms_force_connector_ba...@force-connector-state.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v1/fi-pnv-d510/igt@kms_force_connector_ba...@force-connector-state.html
- fi-bwr-2160:[PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/fi-bwr-2160/igt@kms_force_connector_ba...@force-connector-state.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v1/fi-bwr-2160/igt@kms_force_connector_ba...@force-connector-state.html
- fi-blb-e6850: [PASS][7] -> [INCOMPLETE][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/fi-blb-e6850/igt@kms_force_connector_ba...@force-connector-state.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v1/fi-blb-e6850/igt@kms_force_connector_ba...@force-connector-state.html
Known issues
Here are the changes found in Patchwork_103665v1 that come from known issues:
### CI changes ###
Issues hit
* boot:
- fi-snb-2600:[PASS][9] -> [FAIL][10] ([i915#4338])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/fi-snb-2600/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v1/fi-snb-2600/boot.html
### IGT changes ###
Issues hit
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][11] ([i915#2403] / [i915#4312])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v1/fi-pnv-d510/igt@run...@aborted.html
- fi-icl-u2: NOTRUN -> [FAIL][12] ([i915#3690])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v1/fi-icl-u2/igt@run...@aborted.html
- fi-bwr-2160:NOTRUN -> [FAIL][13] ([i915#4312])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v1/fi-bwr-2160/igt@run...@aborted.html
- fi-blb-e6850: NOTRUN -> [FAIL][14] ([i915#2403] / [i915#4312])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103665v1/fi-blb-e6850/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#3690]: https://gitlab.freedesktop.org/drm/intel/issues/3690
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4338]: https://gitlab.freedesktop.org/drm/intel/issues/4338
[i915#5602]: https://gitlab.freedesktop.org/drm/intel/issues/5602
[i915#5616]: https://gitlab.freedesktop.org/drm/intel/issues/5616
[i915#5917]: https://gitlab.freedesktop.org/drm/intel/issues/5917
Build changes
-
* Linux: CI_DRM_11616 -> Patchwork_103665v1
CI-20190529: 20190529
CI_DRM_11616: 65a5fe9ac96c60bd6dfcc44a0bb8d584912ea53d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6467: 929abc51cdd48d673efa03e025b1f31b557972ed @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103665v1: 65a5fe9ac96c60bd6dfcc44a0bb8d584912ea53d @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
c116ae5ca936 drm/edid: convert version_greater() to drm_edid
17eb09103c8a drm/displayid: convert to drm_edid
4e57cd1461b2 drm/edid: add drm_edid helper for drm_update_tile_info()
93fc0eff94e8 drm/edid: convert drm_edid_iter_begin() to drm_edid
136b20f635b7 drm/edid: convert
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/edid: introduce struct drm_edid
== Series Details == Series: drm/edid: introduce struct drm_edid URL : https://patchwork.freedesktop.org/series/103665/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/edid: introduce struct drm_edid
== Series Details ==
Series: drm/edid: introduce struct drm_edid
URL : https://patchwork.freedesktop.org/series/103665/
State : warning
== Summary ==
Error: dim checkpatch failed
d886c554f1a8 drm/edid: use else-if in CTA extension parsing
4cbaa4d285a2 drm/edid: convert drm_for_each_detailed_block() to edid iter
5a728625bfb4 drm/edid: add struct drm_edid container
4f87a69d8848 drm/edid: start propagating drm_edid to lower levels
-:32: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!drm_edid"
#32: FILE: drivers/gpu/drm/drm_edid.c:5823:
+ if (drm_edid == NULL) {
total: 0 errors, 0 warnings, 1 checks, 43 lines checked
b3ace29ad531 drm/edid: keep propagating drm_edid to display info
c9fe2b156008 drm/edid: propagate drm_edid to drm_edid_to_eld()
b4b764dfd316 drm/edid: convert drm_edid_connector_update() to drm_edid fully
c25559b7e2cf drm/edid: convert struct detailed_mode_closure to drm_edid
0c4403bc2931 drm/edid: convert drm_mode_detailed() to drm_edid
68d3e834de47 drm/edid: convert drm_dmt_modes_for_range() to drm_edid
78e7de5f61ff drm/edid: convert drm_gtf_modes_for_range() to drm_edid
a1bce597df2d drm/edid: convert drm_cvt_modes_for_range() to drm_edid
727ea972b7bc drm/edid: convert drm_mode_std() and children to drm_edid
7a6eb5cdaf09 drm/edid: convert mode_in_range() and drm_monitor_supports_rb() to
drm_edid
eb58907519c4 drm/edid: convert get_monitor_name() to drm_edid
07189e36c881 drm/edid: convert drm_for_each_detailed_block() to drm_edid
-:33: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around
drm_edid->edid->detailed_timings[i]
#33: FILE: drivers/gpu/drm/drm_edid.c:2594:
+ cb(&(drm_edid->edid->detailed_timings[i]), closure);
total: 0 errors, 0 warnings, 1 checks, 129 lines checked
b3c6e86982ba drm/edid: add drm_edid helper for drm_edid_to_sad()
ae55ee36f30d drm/edid: add drm_edid helper for drm_edid_to_speaker_allocation()
3a0b663d0761 drm/edid: add drm_edid helper for drm_detect_hdmi_monitor()
47e3c35b33c5 drm/edid: add drm_edid helper for drm_detect_monitor_audio()
42f9ecf45903 drm/edid: convert cea_db_iter_edid_begin() to drm_edid
2f064307b607 drm/edid: convert drm_edid_iter_begin() to drm_edid
84170f97f641 drm/edid: add drm_edid helper for drm_update_tile_info()
4919fb4097cb drm/displayid: convert to drm_edid
45a163aa8771 drm/edid: convert version_greater() to drm_edid
[Intel-gfx] ✓ Fi.CI.BAT: success for Expose max and current bpc via debugfs (rev3)
== Series Details == Series: Expose max and current bpc via debugfs (rev3) URL : https://patchwork.freedesktop.org/series/102502/ State : success == Summary == CI Bug Log - changes from CI_DRM_11616 -> Patchwork_102502v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/index.html Participating hosts (42 -> 43) -- Additional (4): fi-icl-u2 bat-jsl-1 bat-dg2-9 bat-dg1-5 Missing(3): bat-adlm-1 fi-rkl-11600 fi-bsw-cyan Known issues Here are the changes found in Patchwork_102502v3 that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@write: - bat-dg1-5: NOTRUN -> [SKIP][1] ([i915#2582]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@fb...@write.html * igt@gem_mmap@basic: - bat-dg1-5: NOTRUN -> [SKIP][2] ([i915#4083]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@gem_m...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-5: NOTRUN -> [SKIP][3] ([i915#4077]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-5: NOTRUN -> [SKIP][4] ([i915#4079]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-5: NOTRUN -> [SKIP][5] ([i915#1155]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@gt_engines: - bat-dg1-5: NOTRUN -> [INCOMPLETE][6] ([i915#4418]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@i915_selftest@live@gt_engines.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-5: NOTRUN -> [SKIP][7] ([i915#4215]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@tile-pitch-mismatch: - bat-dg1-5: NOTRUN -> [SKIP][8] ([i915#4212]) +7 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@kms_addfb_ba...@tile-pitch-mismatch.html * igt@kms_busy@basic: - bat-dg1-5: NOTRUN -> [SKIP][9] ([i915#4303]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@kms_b...@basic.html * igt@kms_chamelium@hdmi-hpd-fast: - bat-dg1-5: NOTRUN -> [SKIP][10] ([fdo#111827]) +7 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-dg1-5: NOTRUN -> [SKIP][11] ([i915#4103] / [i915#4213]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_flip@basic-flip-vs-dpms: - bat-dg1-5: NOTRUN -> [SKIP][12] ([i915#4078]) +23 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@kms_f...@basic-flip-vs-dpms.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg1-5: NOTRUN -> [SKIP][13] ([fdo#109285]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@primary_page_flip: - bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#1072] / [i915#4078]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@kms_psr@primary_page_flip.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#3555]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-mmap: - bat-dg1-5: NOTRUN -> [SKIP][16] ([i915#3708] / [i915#4077]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@prime_v...@basic-fence-mmap.html * igt@prime_vgem@basic-userptr: - bat-dg1-5: NOTRUN -> [SKIP][17] ([i915#3708] / [i915#4873]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@prime_v...@basic-userptr.html * igt@prime_vgem@basic-write: - bat-dg1-5: NOTRUN -> [SKIP][18] ([i915#3708]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102502v3/bat-dg1-5/igt@prime_v...@basic-write.html * igt@runner@aborted: - fi-icl-u2: NOTRUN -> [FAIL][19] ([i915#3690])
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Expose max and current bpc via debugfs (rev3)
== Series Details == Series: Expose max and current bpc via debugfs (rev3) URL : https://patchwork.freedesktop.org/series/102502/ State : warning == Summary == Error: dim checkpatch failed a180df33d330 drm/debug: Expose connector's max supported bpc via debugfs -:21: WARNING:BAD_SIGN_OFF: 'Reviewed-by:' is the preferred signature form #21: Reviewed-By: Arun R Murthy total: 0 errors, 1 warnings, 0 checks, 33 lines checked c6e9ca4740c6 drm/i915/display/debug: Expose crtc current bpc via debugfs c8507520a0e2 drm/amd/display: Move connector debugfs to drm
[Intel-gfx] [PULL] drm-intel-next
Hi Dave & Daniel -
drm-intel-next-2022-05-06:
drm/i915 feature pull #2 for v5.19:
Features and functionality:
- Add first set of DG2 PCI IDs for "motherboard down" designs (Matt Roper)
- Add initial RPL-P PCI IDs as ADL-P subplatform (Matt Atwood)
Refactoring and cleanups:
- Power well refactoring and cleanup (Imre)
- GVT-g refactor and mdev API cleanup (Christoph, Jason, Zhi)
- DPLL refactoring and cleanup (Ville)
- VBT panel specific data parsing cleanup (Ville)
- Use drm_mode_init() for on-stack modes (Ville)
Fixes:
- Fix PSR state pipe A/B confusion by clearing more state on disable (José)
- Fix FIFO underruns caused by not taking DRAM channel into account (Vinod)
- Fix FBC flicker on display 11+ by enabling a workaround (José)
- Fix VBT seamless DRRS min refresh rate check (Ville)
- Fix panel type assumption on bogus VBT data (Ville)
- Fix panel data parsing for VBT that misses panel data pointers block (Ville)
- Fix spurious AUX timeout/hotplug handling on LTTPR links (Imre)
Merges:
- Backmerge drm-next (Jani)
- GVT changes (Jani)
BR,
Jani.
The following changes since commit 19df0cfa258cd42f7f106f6085f1e625f26283db:
Merge tag 'drm-misc-next-2022-04-21' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next (2022-04-22 11:15:30
+1000)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2022-05-06
for you to fetch changes up to 949665a6e237a6fd49ff207e3876d71b20b7e9f2:
drm/i915: Respect VBT seamless DRRS min refresh rate (2022-05-05 18:27:53
+0300)
drm/i915 feature pull #2 for v5.19:
Features and functionality:
- Add first set of DG2 PCI IDs for "motherboard down" designs (Matt Roper)
- Add initial RPL-P PCI IDs as ADL-P subplatform (Matt Atwood)
Refactoring and cleanups:
- Power well refactoring and cleanup (Imre)
- GVT-g refactor and mdev API cleanup (Christoph, Jason, Zhi)
- DPLL refactoring and cleanup (Ville)
- VBT panel specific data parsing cleanup (Ville)
- Use drm_mode_init() for on-stack modes (Ville)
Fixes:
- Fix PSR state pipe A/B confusion by clearing more state on disable (José)
- Fix FIFO underruns caused by not taking DRAM channel into account (Vinod)
- Fix FBC flicker on display 11+ by enabling a workaround (José)
- Fix VBT seamless DRRS min refresh rate check (Ville)
- Fix panel type assumption on bogus VBT data (Ville)
- Fix panel data parsing for VBT that misses panel data pointers block (Ville)
- Fix spurious AUX timeout/hotplug handling on LTTPR links (Imre)
Merges:
- Backmerge drm-next (Jani)
- GVT changes (Jani)
Christoph Hellwig (27):
drm/i915/gvt: remove module refcounting in
intel_gvt_{,un}register_hypervisor
drm/i915/gvt: remove enum hypervisor_type
drm/i915/gvt: rename intel_vgpu_ops to intel_vgpu_mdev_ops
drm/i915/gvt: move the gvt code into kvmgt.ko
drm/i915/gvt: remove intel_gvt_ops
drm/i915/gvt: remove the map_gfn_to_mfn and set_trap_area ops
drm/i915/gvt: remove the unused from_virt_to_mfn op
drm/i915/gvt: merge struct kvmgt_vdev into struct intel_vgpu
drm/i915/gvt: merge struct kvmgt_guest_info into strut intel_vgpu
drm/i915/gvt: remove vgpu->handle
drm/i915/gvt: devirtualize ->{read,write}_gpa
drm/i915/gvt: devirtualize ->{get,put}_vfio_device
drm/i915/gvt: devirtualize ->set_edid and ->set_opregion
drm/i915/gvt: devirtualize ->detach_vgpu
drm/i915/gvt: devirtualize ->inject_msi
drm/i915/gvt: devirtualize ->is_valid_gfn
drm/i915/gvt: devirtualize ->gfn_to_mfn
drm/i915/gvt: devirtualize ->{enable,disable}_page_track
drm/i915/gvt: devirtualize ->dma_{,un}map_guest_page
drm/i915/gvt: devirtualize dma_pin_guest_page
drm/i915/gvt: remove struct intel_gvt_mpt
drm/i915/gvt: remove the extra vfio_device refcounting for dmabufs
drm/i915/gvt: streamline intel_vgpu_create
drm/i915/gvt: pass a struct intel_vgpu to the vfio read/write helpers
drm/i915/gvt: remove kvmgt_guest_{init,exit}
drm/i915/gvt: convert to use vfio_register_emulated_iommu_dev
drm/i915/gvt: merge gvt.c into kvmgvt.c
Hans de Goede (1):
drm/i915: Fix DISP_POS_Y and DISP_HEIGHT defines
Imre Deak (21):
drm/i915: Move per-platform power well hooks to intel_display_power_well.c
drm/i915: Unexport the for_each_power_well() macros
drm/i915: Move the power domain->well mappings to
intel_display_power_map.c
drm/i915: Move the dg2 fixed_enable_delay power well param to a common
bitfield
drm/i915: Move the HSW power well flags to a common bitfield
drm/i915: Rename the power domain names to end with pipes/ports
drm/i915: Sanitize the power well names
drm/i915: Convert the power well descriptor domain mask to an array of
domains
drm/i915: Convert the u64 power well domains mask to a
[Intel-gfx] ✓ Fi.CI.BAT: success for Fixes for selective fetch area calculation
== Series Details == Series: Fixes for selective fetch area calculation URL : https://patchwork.freedesktop.org/series/103659/ State : success == Summary == CI Bug Log - changes from CI_DRM_11616 -> Patchwork_103659v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/index.html Participating hosts (42 -> 36) -- Additional (1): fi-icl-u2 Missing(7): bat-adls-5 bat-adlm-1 fi-bsw-cyan bat-adlp-6 bat-adln-1 bat-rpls-1 bat-rpls-2 Known issues Here are the changes found in Patchwork_103659v1 that come from known issues: ### CI changes ### Issues hit * boot: - fi-snb-2600:[PASS][1] -> [FAIL][2] ([i915#4338]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11616/fi-snb-2600/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/fi-snb-2600/boot.html ### IGT changes ### Issues hit * igt@runner@aborted: - fi-icl-u2: NOTRUN -> [FAIL][3] ([i915#3690]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/fi-icl-u2/igt@run...@aborted.html [i915#3690]: https://gitlab.freedesktop.org/drm/intel/issues/3690 [i915#4338]: https://gitlab.freedesktop.org/drm/intel/issues/4338 Build changes - * Linux: CI_DRM_11616 -> Patchwork_103659v1 CI-20190529: 20190529 CI_DRM_11616: 65a5fe9ac96c60bd6dfcc44a0bb8d584912ea53d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6467: 929abc51cdd48d673efa03e025b1f31b557972ed @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_103659v1: 65a5fe9ac96c60bd6dfcc44a0bb8d584912ea53d @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 699ac7b731d4 drm/i915: Ensure damage clip area is within pipe area 259af3dc5feb drm/i915/psr: Use full update In case of area calculation fails == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v1/index.html
Re: [Intel-gfx] [PATCH 05/25] drm/edid: keep propagating drm_edid to display info
On Fri, 06 May 2022, Jani Nikula wrote:
> We'll need to propagate drm_edid everywhere.
I seem to have copy-pasted a TAB in some of the commit messages, in a
way that does not show up in git log.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/drm_edid.c | 50 +++---
> 1 file changed, 31 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 946296632b2e..c9d48fbd0a76 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -2419,13 +2419,13 @@ EXPORT_SYMBOL(drm_edid_duplicate);
>
> /**
> * edid_get_quirks - return quirk flags for a given EDID
> - * @edid: EDID to process
> + * @drm_edid: EDID to process
> *
> * This tells subsequent routines what fixes they need to apply.
> */
> -static u32 edid_get_quirks(const struct edid *edid)
> +static u32 edid_get_quirks(const struct drm_edid *drm_edid)
> {
> - u32 panel_id = edid_extract_panel_id(edid);
> + u32 panel_id = edid_extract_panel_id(drm_edid->edid);
> const struct edid_quirk *quirk;
> int i;
>
> @@ -5448,7 +5448,7 @@ static void drm_parse_microsoft_vsdb(struct
> drm_connector *connector,
> }
>
> static void drm_parse_cea_ext(struct drm_connector *connector,
> - const struct edid *edid)
> + const struct drm_edid *drm_edid)
> {
> struct drm_display_info *info = >display_info;
> struct drm_edid_iter edid_iter;
> @@ -5456,7 +5456,7 @@ static void drm_parse_cea_ext(struct drm_connector
> *connector,
> struct cea_db_iter iter;
> const u8 *edid_ext;
>
> - drm_edid_iter_begin(edid, _iter);
> + drm_edid_iter_begin(drm_edid->edid, _iter);
> drm_edid_iter_for_each(edid_ext, _iter) {
> if (edid_ext[0] != CEA_EXT)
> continue;
> @@ -5477,7 +5477,7 @@ static void drm_parse_cea_ext(struct drm_connector
> *connector,
> }
> drm_edid_iter_end(_iter);
>
> - cea_db_iter_edid_begin(edid, );
> + cea_db_iter_edid_begin(drm_edid->edid, );
> cea_db_iter_for_each(db, ) {
> /* FIXME: convert parsers to use struct cea_db */
> const u8 *data = (const u8 *)db;
> @@ -5523,16 +5523,15 @@ void get_monitor_range(const struct detailed_timing
> *timing,
> monitor_range->max_vfreq = range->max_vfreq;
> }
>
> -static
> -void drm_get_monitor_range(struct drm_connector *connector,
> -const struct edid *edid)
> +static void drm_get_monitor_range(struct drm_connector *connector,
> + const struct drm_edid *drm_edid)
> {
> struct drm_display_info *info = >display_info;
>
> - if (!version_greater(edid, 1, 1))
> + if (!version_greater(drm_edid->edid, 1, 1))
> return;
>
> - drm_for_each_detailed_block(edid, get_monitor_range,
> + drm_for_each_detailed_block(drm_edid->edid, get_monitor_range,
> >monitor_range);
>
> DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
> @@ -5592,12 +5591,13 @@ static void drm_parse_vesa_mso_data(struct
> drm_connector *connector,
> info->mso_stream_count, info->mso_pixel_overlap);
> }
>
> -static void drm_update_mso(struct drm_connector *connector, const struct
> edid *edid)
> +static void drm_update_mso(struct drm_connector *connector,
> +const struct drm_edid *drm_edid)
> {
> const struct displayid_block *block;
> struct displayid_iter iter;
>
> - displayid_iter_edid_begin(edid, );
> + displayid_iter_edid_begin(drm_edid->edid, );
> displayid_iter_for_each(block, ) {
> if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
> drm_parse_vesa_mso_data(connector, block);
> @@ -5636,18 +5636,20 @@ drm_reset_display_info(struct drm_connector
> *connector)
> info->mso_pixel_overlap = 0;
> }
>
> -u32 drm_add_display_info(struct drm_connector *connector, const struct edid
> *edid)
> +static u32 update_display_info(struct drm_connector *connector,
> +const struct drm_edid *drm_edid)
> {
> struct drm_display_info *info = >display_info;
> + const struct edid *edid = drm_edid->edid;
>
> - u32 quirks = edid_get_quirks(edid);
> + u32 quirks = edid_get_quirks(drm_edid);
>
> drm_reset_display_info(connector);
>
> info->width_mm = edid->width_cm * 10;
> info->height_mm = edid->height_cm * 10;
>
> - drm_get_monitor_range(connector, edid);
> + drm_get_monitor_range(connector, drm_edid);
>
> if (edid->revision < 3)
> goto out;
> @@ -5656,7 +5658,7 @@ u32 drm_add_display_info(struct drm_connector
> *connector, const struct edid *edi
> goto out;
>
> info->color_formats |= DRM_COLOR_FORMAT_RGB444;
> - drm_parse_cea_ext(connector, edid);
[Intel-gfx] [PATCH 25/25] drm/edid: convert version_greater() to drm_edid
We'll need to propagate drm_edid everywhere. Also make version_greater()
a function for type safety.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index bc64837ad706..df48189ba2c7 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -45,10 +45,6 @@
#include "drm_crtc_internal.h"
-#define version_greater(edid, maj, min) \
- (((edid)->version > (maj)) || \
-((edid)->version == (maj) && (edid)->revision > (min)))
-
static int oui(u8 first, u8 second, u8 third)
{
return (first << 16) | (second << 8) | third;
@@ -1576,6 +1572,15 @@ struct drm_edid {
const struct edid *edid;
};
+static bool version_greater(const struct drm_edid *drm_edid,
+ u8 version, u8 revision)
+{
+ const struct edid *edid = drm_edid->edid;
+
+ return edid->version > version ||
+ (edid->version == version && edid->revision > revision);
+}
+
static int edid_extension_block_count(const struct edid *edid)
{
return edid->extensions;
@@ -3214,7 +3219,7 @@ do_inferred_modes(const struct detailed_timing *timing,
void *c)
closure->drm_edid,
timing);
- if (!version_greater(closure->drm_edid->edid, 1, 1))
+ if (!version_greater(closure->drm_edid, 1, 1))
return; /* GTF not defined yet */
switch (range->flags) {
@@ -3225,7 +3230,7 @@ do_inferred_modes(const struct detailed_timing *timing,
void *c)
timing);
break;
case 0x04: /* cvt, only in 1.4+ */
- if (!version_greater(closure->drm_edid->edid, 1, 3))
+ if (!version_greater(closure->drm_edid, 1, 3))
break;
closure->modes += drm_cvt_modes_for_range(closure->connector,
@@ -3246,7 +3251,7 @@ static int add_inferred_modes(struct drm_connector
*connector,
.drm_edid = drm_edid,
};
- if (version_greater(drm_edid->edid, 1, 0))
+ if (version_greater(drm_edid, 1, 0))
drm_for_each_detailed_block(drm_edid, do_inferred_modes,
);
return closure.modes;
@@ -3323,7 +3328,7 @@ static int add_established_modes(struct drm_connector
*connector,
}
}
- if (version_greater(edid, 1, 0))
+ if (version_greater(drm_edid, 1, 0))
drm_for_each_detailed_block(drm_edid, do_established_modes,
);
@@ -3378,7 +3383,7 @@ static int add_standard_modes(struct drm_connector
*connector,
}
}
- if (version_greater(drm_edid->edid, 1, 0))
+ if (version_greater(drm_edid, 1, 0))
drm_for_each_detailed_block(drm_edid, do_standard_modes,
);
@@ -3458,7 +3463,7 @@ add_cvt_modes(struct drm_connector *connector, const
struct drm_edid *drm_edid)
.drm_edid = drm_edid,
};
- if (version_greater(drm_edid->edid, 1, 2))
+ if (version_greater(drm_edid, 1, 2))
drm_for_each_detailed_block(drm_edid, do_cvt_mode, );
/* XXX should also look for CVT codes in VTB blocks */
@@ -3514,7 +3519,7 @@ static int add_detailed_modes(struct drm_connector
*connector,
.quirks = quirks,
};
- if (closure.preferred && !version_greater(drm_edid->edid, 1, 3))
+ if (closure.preferred && !version_greater(drm_edid, 1, 3))
closure.preferred =
(drm_edid->edid->features &
DRM_EDID_FEATURE_PREFERRED_TIMING);
@@ -5584,7 +5589,7 @@ static void drm_get_monitor_range(struct drm_connector
*connector,
{
struct drm_display_info *info = >display_info;
- if (!version_greater(drm_edid->edid, 1, 1))
+ if (!version_greater(drm_edid, 1, 1))
return;
drm_for_each_detailed_block(drm_edid, get_monitor_range,
--
2.30.2
[Intel-gfx] [PATCH 24/25] drm/displayid: convert to drm_edid
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_displayid.c | 16
drivers/gpu/drm/drm_edid.c | 17 ++---
include/drm/drm_displayid.h | 6 +++---
include/drm/drm_edid.h | 6 --
4 files changed, 25 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/drm_displayid.c b/drivers/gpu/drm/drm_displayid.c
index 32da557b960f..38ea8203df45 100644
--- a/drivers/gpu/drm/drm_displayid.c
+++ b/drivers/gpu/drm/drm_displayid.c
@@ -33,11 +33,11 @@ static int validate_displayid(const u8 *displayid, int
length, int idx)
return 0;
}
-static const u8 *drm_find_displayid_extension(const struct edid *edid,
+static const u8 *drm_find_displayid_extension(const struct drm_edid *drm_edid,
int *length, int *idx,
int *ext_index)
{
- const u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT,
ext_index);
+ const u8 *displayid = drm_find_edid_extension(drm_edid, DISPLAYID_EXT,
ext_index);
const struct displayid_header *base;
int ret;
@@ -58,12 +58,12 @@ static const u8 *drm_find_displayid_extension(const struct
edid *edid,
return displayid;
}
-void displayid_iter_edid_begin(const struct edid *edid,
+void displayid_iter_edid_begin(const struct drm_edid *drm_edid,
struct displayid_iter *iter)
{
memset(iter, 0, sizeof(*iter));
- iter->edid = edid;
+ iter->drm_edid = drm_edid;
}
static const struct displayid_block *
@@ -88,7 +88,7 @@ __displayid_iter_next(struct displayid_iter *iter)
{
const struct displayid_block *block;
- if (!iter->edid)
+ if (!iter->drm_edid)
return NULL;
if (iter->section) {
@@ -96,7 +96,7 @@ __displayid_iter_next(struct displayid_iter *iter)
block = displayid_iter_block(iter);
if (WARN_ON(!block)) {
iter->section = NULL;
- iter->edid = NULL;
+ iter->drm_edid = NULL;
return NULL;
}
@@ -109,12 +109,12 @@ __displayid_iter_next(struct displayid_iter *iter)
}
for (;;) {
- iter->section = drm_find_displayid_extension(iter->edid,
+ iter->section = drm_find_displayid_extension(iter->drm_edid,
>length,
>idx,
>ext_index);
if (!iter->section) {
- iter->edid = NULL;
+ iter->drm_edid = NULL;
return NULL;
}
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 82db7afb4f8e..bc64837ad706 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3545,10 +3545,13 @@ static int add_detailed_modes(struct drm_connector
*connector,
/*
* Search EDID for CEA extension block.
+ *
+ * FIXME: Prefer not returning pointers to raw EDID data.
*/
-const u8 *drm_find_edid_extension(const struct edid *edid,
+const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
int ext_id, int *ext_index)
{
+ const struct edid *edid = drm_edid ? drm_edid->edid : NULL;
const u8 *edid_ext = NULL;
int i;
@@ -3580,11 +3583,11 @@ static bool drm_edid_has_cta_extension(const struct
drm_edid *drm_edid)
bool found = false;
/* Look for a top level CEA extension block */
- if (drm_find_edid_extension(drm_edid->edid, CEA_EXT, _index))
+ if (drm_find_edid_extension(drm_edid, CEA_EXT, _index))
return true;
/* CEA blocks can also be found embedded in a DisplayID block */
- displayid_iter_edid_begin(drm_edid->edid, );
+ displayid_iter_edid_begin(drm_edid, );
displayid_iter_for_each(block, ) {
if (block->tag == DATA_BLOCK_CTA) {
found = true;
@@ -4436,7 +4439,7 @@ static void cea_db_iter_edid_begin(const struct drm_edid
*drm_edid,
memset(iter, 0, sizeof(*iter));
drm_edid_iter_begin(drm_edid, >edid_iter);
- displayid_iter_edid_begin(drm_edid->edid, >displayid_iter);
+ displayid_iter_edid_begin(drm_edid, >displayid_iter);
}
static const struct cea_db *
@@ -5650,7 +5653,7 @@ static void drm_update_mso(struct drm_connector
*connector,
const struct displayid_block *block;
struct displayid_iter iter;
- displayid_iter_edid_begin(drm_edid->edid, );
+ displayid_iter_edid_begin(drm_edid, );
displayid_iter_for_each(block, ) {
if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
drm_parse_vesa_mso_data(connector, block);
[Intel-gfx] [PATCH 23/25] drm/edid: add drm_edid helper for drm_update_tile_info()
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index b453bbf2f642..82db7afb4f8e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6363,15 +6363,15 @@ static void drm_parse_tiled_block(struct drm_connector
*connector,
}
}
-void drm_update_tile_info(struct drm_connector *connector,
- const struct edid *edid)
+static void _drm_update_tile_info(struct drm_connector *connector,
+ const struct drm_edid *drm_edid)
{
const struct displayid_block *block;
struct displayid_iter iter;
connector->has_tile = false;
- displayid_iter_edid_begin(edid, );
+ displayid_iter_edid_begin(drm_edid ? drm_edid->edid : NULL, );
displayid_iter_for_each(block, ) {
if (block->tag == DATA_BLOCK_TILED_DISPLAY)
drm_parse_tiled_block(connector, block);
@@ -6383,3 +6383,14 @@ void drm_update_tile_info(struct drm_connector
*connector,
connector->tile_group = NULL;
}
}
+
+void drm_update_tile_info(struct drm_connector *connector,
+ const struct edid *edid)
+{
+ struct drm_edid drm_edid = {
+ .edid = edid,
+ .size = edid_size(edid),
+ };
+
+ _drm_update_tile_info(connector, _edid);
+}
--
2.30.2
[Intel-gfx] [PATCH 22/25] drm/edid: convert drm_edid_iter_begin() to drm_edid
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 82a242a71ecf..b453bbf2f642 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1614,36 +1614,36 @@ static const void *edid_extension_block_data(const
struct edid *edid, int index)
* struct drm_edid_iter iter;
* const u8 *block;
*
- * drm_edid_iter_begin(edid, );
+ * drm_edid_iter_begin(drm_edid, );
* drm_edid_iter_for_each(block, ) {
* // do stuff with block
* }
* drm_edid_iter_end();
*/
struct drm_edid_iter {
- const struct edid *edid;
+ const struct drm_edid *drm_edid;
/* Current block index. */
int index;
};
-static void drm_edid_iter_begin(const struct edid *edid,
+static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
struct drm_edid_iter *iter)
{
memset(iter, 0, sizeof(*iter));
- iter->edid = edid;
+ iter->drm_edid = drm_edid;
}
static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
{
const void *block = NULL;
- if (!iter->edid)
+ if (!iter->drm_edid)
return NULL;
- if (iter->index < edid_block_count(iter->edid))
- block = edid_block_data(iter->edid, iter->index++);
+ if (iter->index < edid_block_count(iter->drm_edid->edid))
+ block = edid_block_data(iter->drm_edid->edid, iter->index++);
return block;
}
@@ -2593,7 +2593,7 @@ static void drm_for_each_detailed_block(const struct
drm_edid *drm_edid,
for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
cb(&(drm_edid->edid->detailed_timings[i]), closure);
- drm_edid_iter_begin(drm_edid->edid, _iter);
+ drm_edid_iter_begin(drm_edid, _iter);
drm_edid_iter_for_each(ext, _iter) {
switch (*ext) {
case CEA_EXT:
@@ -4435,7 +4435,7 @@ static void cea_db_iter_edid_begin(const struct drm_edid
*drm_edid,
{
memset(iter, 0, sizeof(*iter));
- drm_edid_iter_begin(drm_edid->edid, >edid_iter);
+ drm_edid_iter_begin(drm_edid, >edid_iter);
displayid_iter_edid_begin(drm_edid->edid, >displayid_iter);
}
@@ -5153,7 +5153,7 @@ static bool _drm_detect_monitor_audio(const struct
drm_edid *drm_edid)
const u8 *edid_ext;
bool has_audio = false;
- drm_edid_iter_begin(drm_edid->edid, _iter);
+ drm_edid_iter_begin(drm_edid, _iter);
drm_edid_iter_for_each(edid_ext, _iter) {
if (edid_ext[0] == CEA_EXT) {
has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
@@ -5509,7 +5509,7 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
struct cea_db_iter iter;
const u8 *edid_ext;
- drm_edid_iter_begin(drm_edid->edid, _iter);
+ drm_edid_iter_begin(drm_edid, _iter);
drm_edid_iter_for_each(edid_ext, _iter) {
if (edid_ext[0] != CEA_EXT)
continue;
--
2.30.2
[Intel-gfx] [PATCH 21/25] drm/edid: convert cea_db_iter_edid_begin() to drm_edid
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 706552ae00ea..82a242a71ecf 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4430,12 +4430,13 @@ static bool cea_db_is_vendor(const struct cea_db *db,
int vendor_oui)
oui(data[2], data[1], data[0]) == vendor_oui;
}
-static void cea_db_iter_edid_begin(const struct edid *edid, struct cea_db_iter
*iter)
+static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
+ struct cea_db_iter *iter)
{
memset(iter, 0, sizeof(*iter));
- drm_edid_iter_begin(edid, >edid_iter);
- displayid_iter_edid_begin(edid, >displayid_iter);
+ drm_edid_iter_begin(drm_edid->edid, >edid_iter);
+ displayid_iter_edid_begin(drm_edid->edid, >displayid_iter);
}
static const struct cea_db *
@@ -4657,7 +4658,7 @@ static int add_cea_modes(struct drm_connector *connector,
struct cea_db_iter iter;
int modes = 0;
- cea_db_iter_edid_begin(drm_edid->edid, );
+ cea_db_iter_edid_begin(drm_edid, );
cea_db_iter_for_each(db, ) {
const u8 *hdmi = NULL, *video = NULL;
u8 hdmi_len = 0, video_len = 0;
@@ -4908,7 +4909,7 @@ static void drm_edid_to_eld(struct drm_connector
*connector,
eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
- cea_db_iter_edid_begin(drm_edid->edid, );
+ cea_db_iter_edid_begin(drm_edid, );
cea_db_iter_for_each(db, ) {
const u8 *data = cea_db_data(db);
int len = cea_db_payload_len(db);
@@ -4961,7 +4962,7 @@ static int _drm_edid_to_sad(const struct drm_edid
*drm_edid,
struct cea_db_iter iter;
int count = 0;
- cea_db_iter_edid_begin(drm_edid->edid, );
+ cea_db_iter_edid_begin(drm_edid, );
cea_db_iter_for_each(db, ) {
if (cea_db_tag(db) == CTA_DB_AUDIO) {
int j;
@@ -5017,7 +5018,7 @@ static int _drm_edid_to_speaker_allocation(const struct
drm_edid *drm_edid,
struct cea_db_iter iter;
int count = 0;
- cea_db_iter_edid_begin(drm_edid->edid, );
+ cea_db_iter_edid_begin(drm_edid, );
cea_db_iter_for_each(db, ) {
if (cea_db_tag(db) == CTA_DB_SPEAKER &&
cea_db_payload_len(db) == 3) {
@@ -5110,7 +5111,7 @@ static bool _drm_detect_hdmi_monitor(const struct
drm_edid *drm_edid)
* Because HDMI identifier is in Vendor Specific Block,
* search it from all data blocks of CEA extension.
*/
- cea_db_iter_edid_begin(drm_edid->edid, );
+ cea_db_iter_edid_begin(drm_edid, );
cea_db_iter_for_each(db, ) {
if (cea_db_is_hdmi_vsdb(db)) {
hdmi = true;
@@ -5167,7 +5168,7 @@ static bool _drm_detect_monitor_audio(const struct
drm_edid *drm_edid)
goto end;
}
- cea_db_iter_edid_begin(drm_edid->edid, );
+ cea_db_iter_edid_begin(drm_edid, );
cea_db_iter_for_each(db, ) {
if (cea_db_tag(db) == CTA_DB_AUDIO) {
const u8 *data = cea_db_data(db);
@@ -5529,7 +5530,7 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
}
drm_edid_iter_end(_iter);
- cea_db_iter_edid_begin(drm_edid->edid, );
+ cea_db_iter_edid_begin(drm_edid, );
cea_db_iter_for_each(db, ) {
/* FIXME: convert parsers to use struct cea_db */
const u8 *data = (const u8 *)db;
--
2.30.2
[Intel-gfx] [PATCH 20/25] drm/edid: add drm_edid helper for drm_detect_monitor_audio()
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 40 --
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 3277b4fd33ce..706552ae00ea 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -5144,19 +5144,7 @@ bool drm_detect_hdmi_monitor(const struct edid *edid)
}
EXPORT_SYMBOL(drm_detect_hdmi_monitor);
-/**
- * drm_detect_monitor_audio - check monitor audio capability
- * @edid: EDID block to scan
- *
- * Monitor should have CEA extension block.
- * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
- * audio' only. If there is any audio extension block and supported
- * audio format, assume at least 'basic audio' support, even if 'basic
- * audio' is not defined in EDID.
- *
- * Return: True if the monitor supports audio, false otherwise.
- */
-bool drm_detect_monitor_audio(const struct edid *edid)
+static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
{
struct drm_edid_iter edid_iter;
const struct cea_db *db;
@@ -5164,7 +5152,7 @@ bool drm_detect_monitor_audio(const struct edid *edid)
const u8 *edid_ext;
bool has_audio = false;
- drm_edid_iter_begin(edid, _iter);
+ drm_edid_iter_begin(drm_edid->edid, _iter);
drm_edid_iter_for_each(edid_ext, _iter) {
if (edid_ext[0] == CEA_EXT) {
has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
@@ -5179,7 +5167,7 @@ bool drm_detect_monitor_audio(const struct edid *edid)
goto end;
}
- cea_db_iter_edid_begin(edid, );
+ cea_db_iter_edid_begin(drm_edid->edid, );
cea_db_iter_for_each(db, ) {
if (cea_db_tag(db) == CTA_DB_AUDIO) {
const u8 *data = cea_db_data(db);
@@ -5197,6 +5185,28 @@ bool drm_detect_monitor_audio(const struct edid *edid)
end:
return has_audio;
}
+
+/**
+ * drm_detect_monitor_audio - check monitor audio capability
+ * @edid: EDID block to scan
+ *
+ * Monitor should have CEA extension block.
+ * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
+ * audio' only. If there is any audio extension block and supported
+ * audio format, assume at least 'basic audio' support, even if 'basic
+ * audio' is not defined in EDID.
+ *
+ * Return: True if the monitor supports audio, false otherwise.
+ */
+bool drm_detect_monitor_audio(const struct edid *edid)
+{
+ struct drm_edid drm_edid = {
+ .edid = edid,
+ .size = edid_size(edid),
+ };
+
+ return _drm_detect_monitor_audio(_edid);
+}
EXPORT_SYMBOL(drm_detect_monitor_audio);
--
2.30.2
[Intel-gfx] [PATCH 19/25] drm/edid: add drm_edid helper for drm_detect_hdmi_monitor()
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 36 +++-
1 file changed, 23 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 51aee048bcff..3277b4fd33ce 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -5100,18 +5100,7 @@ int drm_av_sync_delay(struct drm_connector *connector,
}
EXPORT_SYMBOL(drm_av_sync_delay);
-/**
- * drm_detect_hdmi_monitor - detect whether monitor is HDMI
- * @edid: monitor EDID information
- *
- * Parse the CEA extension according to CEA-861-B.
- *
- * Drivers that have added the modes parsed from EDID to drm_display_info
- * should use _display_info.is_hdmi instead of calling this function.
- *
- * Return: True if the monitor is HDMI, false if not or unknown.
- */
-bool drm_detect_hdmi_monitor(const struct edid *edid)
+static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
{
const struct cea_db *db;
struct cea_db_iter iter;
@@ -5121,7 +5110,7 @@ bool drm_detect_hdmi_monitor(const struct edid *edid)
* Because HDMI identifier is in Vendor Specific Block,
* search it from all data blocks of CEA extension.
*/
- cea_db_iter_edid_begin(edid, );
+ cea_db_iter_edid_begin(drm_edid->edid, );
cea_db_iter_for_each(db, ) {
if (cea_db_is_hdmi_vsdb(db)) {
hdmi = true;
@@ -5132,6 +5121,27 @@ bool drm_detect_hdmi_monitor(const struct edid *edid)
return hdmi;
}
+
+/**
+ * drm_detect_hdmi_monitor - detect whether monitor is HDMI
+ * @edid: monitor EDID information
+ *
+ * Parse the CEA extension according to CEA-861-B.
+ *
+ * Drivers that have added the modes parsed from EDID to drm_display_info
+ * should use _display_info.is_hdmi instead of calling this function.
+ *
+ * Return: True if the monitor is HDMI, false if not or unknown.
+ */
+bool drm_detect_hdmi_monitor(const struct edid *edid)
+{
+ struct drm_edid drm_edid = {
+ .edid = edid,
+ .size = edid_size(edid),
+ };
+
+ return _drm_detect_hdmi_monitor(_edid);
+}
EXPORT_SYMBOL(drm_detect_hdmi_monitor);
/**
--
2.30.2
[Intel-gfx] [PATCH 18/25] drm/edid: add drm_edid helper for drm_edid_to_speaker_allocation()
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 39 --
1 file changed, 25 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 52ea187394dd..51aee048bcff 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -5010,25 +5010,14 @@ int drm_edid_to_sad(const struct edid *edid, struct
cea_sad **sads)
}
EXPORT_SYMBOL(drm_edid_to_sad);
-/**
- * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks
from EDID
- * @edid: EDID to parse
- * @sadb: pointer to the speaker block
- *
- * Looks for CEA EDID block and extracts the Speaker Allocation Data Block
from it.
- *
- * Note: The returned pointer needs to be freed using kfree().
- *
- * Return: The number of found Speaker Allocation Blocks or negative number on
- * error.
- */
-int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
+static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
+ u8 **sadb)
{
const struct cea_db *db;
struct cea_db_iter iter;
int count = 0;
- cea_db_iter_edid_begin(edid, );
+ cea_db_iter_edid_begin(drm_edid->edid, );
cea_db_iter_for_each(db, ) {
if (cea_db_tag(db) == CTA_DB_SPEAKER &&
cea_db_payload_len(db) == 3) {
@@ -5046,6 +5035,28 @@ int drm_edid_to_speaker_allocation(const struct edid
*edid, u8 **sadb)
return count;
}
+
+/**
+ * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks
from EDID
+ * @edid: EDID to parse
+ * @sadb: pointer to the speaker block
+ *
+ * Looks for CEA EDID block and extracts the Speaker Allocation Data Block
from it.
+ *
+ * Note: The returned pointer needs to be freed using kfree().
+ *
+ * Return: The number of found Speaker Allocation Blocks or negative number on
+ * error.
+ */
+int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
+{
+ struct drm_edid drm_edid = {
+ .edid = edid,
+ .size = edid_size(edid),
+ };
+
+ return _drm_edid_to_speaker_allocation(_edid, sadb);
+}
EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
/**
--
2.30.2
[Intel-gfx] [PATCH 17/25] drm/edid: add drm_edid helper for drm_edid_to_sad()
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 37 -
1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 2017feecbe1c..52ea187394dd 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4954,24 +4954,14 @@ static void drm_edid_to_eld(struct drm_connector
*connector,
drm_eld_size(eld), total_sad_count);
}
-/**
- * drm_edid_to_sad - extracts SADs from EDID
- * @edid: EDID to parse
- * @sads: pointer that will be set to the extracted SADs
- *
- * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from
it.
- *
- * Note: The returned pointer needs to be freed using kfree().
- *
- * Return: The number of found SADs or negative number on error.
- */
-int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
+static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
+ struct cea_sad **sads)
{
const struct cea_db *db;
struct cea_db_iter iter;
int count = 0;
- cea_db_iter_edid_begin(edid, );
+ cea_db_iter_edid_begin(drm_edid->edid, );
cea_db_iter_for_each(db, ) {
if (cea_db_tag(db) == CTA_DB_AUDIO) {
int j;
@@ -4997,6 +4987,27 @@ int drm_edid_to_sad(const struct edid *edid, struct
cea_sad **sads)
return count;
}
+
+/**
+ * drm_edid_to_sad - extracts SADs from EDID
+ * @edid: EDID to parse
+ * @sads: pointer that will be set to the extracted SADs
+ *
+ * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from
it.
+ *
+ * Note: The returned pointer needs to be freed using kfree().
+ *
+ * Return: The number of found SADs or negative number on error.
+ */
+int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
+{
+ struct drm_edid drm_edid = {
+ .edid = edid,
+ .size = edid_size(edid),
+ };
+
+ return _drm_edid_to_sad(_edid, sads);
+}
EXPORT_SYMBOL(drm_edid_to_sad);
/**
--
2.30.2
[Intel-gfx] [PATCH 16/25] drm/edid: convert drm_for_each_detailed_block() to drm_edid
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 4fd2ee976d39..2017feecbe1c 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2580,20 +2580,20 @@ vtb_for_each_detailed_block(const u8 *ext, detailed_cb
*cb, void *closure)
cb((const struct detailed_timing *)(det_base + 18 * i),
closure);
}
-static void
-drm_for_each_detailed_block(const struct edid *edid, detailed_cb *cb, void
*closure)
+static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
+ detailed_cb *cb, void *closure)
{
struct drm_edid_iter edid_iter;
const u8 *ext;
int i;
- if (edid == NULL)
+ if (!drm_edid)
return;
for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
- cb(&(edid->detailed_timings[i]), closure);
+ cb(&(drm_edid->edid->detailed_timings[i]), closure);
- drm_edid_iter_begin(edid, _iter);
+ drm_edid_iter_begin(drm_edid->edid, _iter);
drm_edid_iter_for_each(ext, _iter) {
switch (*ext) {
case CEA_EXT:
@@ -2632,7 +2632,7 @@ drm_monitor_supports_rb(const struct drm_edid *drm_edid)
if (drm_edid->edid->revision >= 4) {
bool ret = false;
- drm_for_each_detailed_block(drm_edid->edid, is_rb, );
+ drm_for_each_detailed_block(drm_edid, is_rb, );
return ret;
}
@@ -2659,7 +2659,7 @@ drm_gtf2_hbreak(const struct drm_edid *drm_edid)
{
const struct detailed_timing *descriptor = NULL;
- drm_for_each_detailed_block(drm_edid->edid, find_gtf2, );
+ drm_for_each_detailed_block(drm_edid, find_gtf2, );
BUILD_BUG_ON(offsetof(typeof(*descriptor),
data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
@@ -2671,7 +2671,7 @@ drm_gtf2_2c(const struct drm_edid *drm_edid)
{
const struct detailed_timing *descriptor = NULL;
- drm_for_each_detailed_block(drm_edid->edid, find_gtf2, );
+ drm_for_each_detailed_block(drm_edid, find_gtf2, );
BUILD_BUG_ON(offsetof(typeof(*descriptor),
data.other_data.data.range.formula.gtf2.c) != 13);
@@ -2683,7 +2683,7 @@ drm_gtf2_m(const struct drm_edid *drm_edid)
{
const struct detailed_timing *descriptor = NULL;
- drm_for_each_detailed_block(drm_edid->edid, find_gtf2, );
+ drm_for_each_detailed_block(drm_edid, find_gtf2, );
BUILD_BUG_ON(offsetof(typeof(*descriptor),
data.other_data.data.range.formula.gtf2.m) != 14);
@@ -2695,7 +2695,7 @@ drm_gtf2_k(const struct drm_edid *drm_edid)
{
const struct detailed_timing *descriptor = NULL;
- drm_for_each_detailed_block(drm_edid->edid, find_gtf2, );
+ drm_for_each_detailed_block(drm_edid, find_gtf2, );
BUILD_BUG_ON(offsetof(typeof(*descriptor),
data.other_data.data.range.formula.gtf2.k) != 16);
@@ -2707,7 +2707,7 @@ drm_gtf2_2j(const struct drm_edid *drm_edid)
{
const struct detailed_timing *descriptor = NULL;
- drm_for_each_detailed_block(drm_edid->edid, find_gtf2, );
+ drm_for_each_detailed_block(drm_edid, find_gtf2, );
BUILD_BUG_ON(offsetof(typeof(*descriptor),
data.other_data.data.range.formula.gtf2.j) != 17);
@@ -3247,7 +3247,7 @@ static int add_inferred_modes(struct drm_connector
*connector,
};
if (version_greater(drm_edid->edid, 1, 0))
- drm_for_each_detailed_block(drm_edid->edid, do_inferred_modes,
);
+ drm_for_each_detailed_block(drm_edid, do_inferred_modes,
);
return closure.modes;
}
@@ -3324,7 +3324,7 @@ static int add_established_modes(struct drm_connector
*connector,
}
if (version_greater(edid, 1, 0))
- drm_for_each_detailed_block(drm_edid->edid,
do_established_modes,
+ drm_for_each_detailed_block(drm_edid, do_established_modes,
);
return modes + closure.modes;
@@ -3379,7 +3379,7 @@ static int add_standard_modes(struct drm_connector
*connector,
}
if (version_greater(drm_edid->edid, 1, 0))
- drm_for_each_detailed_block(drm_edid->edid, do_standard_modes,
+ drm_for_each_detailed_block(drm_edid, do_standard_modes,
);
/* XXX should also look for standard codes in VTB blocks */
@@ -3459,7 +3459,7 @@ add_cvt_modes(struct drm_connector *connector, const
struct drm_edid *drm_edid)
};
if (version_greater(drm_edid->edid, 1, 2))
- drm_for_each_detailed_block(drm_edid->edid, do_cvt_mode,
);
+ drm_for_each_detailed_block(drm_edid, do_cvt_mode, );
/* XXX should
[Intel-gfx] [PATCH 15/25] drm/edid: convert get_monitor_name() to drm_edid
We'll need to propagate drm_edid everywhere.
v2: Drop incorrect NULL name check (Dan Carpenter)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index b8deced8de01..4fd2ee976d39 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4812,15 +4812,15 @@ monitor_name(const struct detailed_timing *timing, void
*data)
*res = timing->data.other_data.data.str.str;
}
-static int get_monitor_name(const struct edid *edid, char name[13])
+static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
{
const char *edid_name = NULL;
int mnl;
- if (!edid || !name)
+ if (!drm_edid || !name)
return 0;
- drm_for_each_detailed_block(edid, monitor_name, _name);
+ drm_for_each_detailed_block(drm_edid->edid, monitor_name, _name);
for (mnl = 0; edid_name && mnl < 13; mnl++) {
if (edid_name[mnl] == 0x0a)
break;
@@ -4840,14 +4840,22 @@ static int get_monitor_name(const struct edid *edid,
char name[13])
*/
void drm_edid_get_monitor_name(const struct edid *edid, char *name, int
bufsize)
{
- int name_length;
- char buf[13];
+ int name_length = 0;
if (bufsize <= 0)
return;
- name_length = min(get_monitor_name(edid, buf), bufsize - 1);
- memcpy(name, buf, name_length);
+ if (edid) {
+ char buf[13];
+ struct drm_edid drm_edid = {
+ .edid = edid,
+ .size = edid_size(edid),
+ };
+
+ name_length = min(get_monitor_name(_edid, buf), bufsize -
1);
+ memcpy(name, buf, name_length);
+ }
+
name[name_length] = '\0';
}
EXPORT_SYMBOL(drm_edid_get_monitor_name);
@@ -4887,7 +4895,7 @@ static void drm_edid_to_eld(struct drm_connector
*connector,
if (!drm_edid)
return;
- mnl = get_monitor_name(drm_edid->edid,
[DRM_ELD_MONITOR_NAME_STRING]);
+ mnl = get_monitor_name(drm_edid, [DRM_ELD_MONITOR_NAME_STRING]);
DRM_DEBUG_KMS("ELD monitor %s\n", [DRM_ELD_MONITOR_NAME_STRING]);
eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev <<
DRM_ELD_CEA_EDID_VER_SHIFT;
--
2.30.2
[Intel-gfx] [PATCH 14/25] drm/edid: convert mode_in_range() and drm_monitor_supports_rb() to drm_edid
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 4b2d3453fc5c..b8deced8de01 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2627,16 +2627,16 @@ is_rb(const struct detailed_timing *descriptor, void
*data)
/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
static bool
-drm_monitor_supports_rb(const struct edid *edid)
+drm_monitor_supports_rb(const struct drm_edid *drm_edid)
{
- if (edid->revision >= 4) {
+ if (drm_edid->edid->revision >= 4) {
bool ret = false;
- drm_for_each_detailed_block(edid, is_rb, );
+ drm_for_each_detailed_block(drm_edid->edid, is_rb, );
return ret;
}
- return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
+ return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
}
static void
@@ -2820,7 +2820,7 @@ static struct drm_display_mode *drm_mode_std(struct
drm_connector *connector,
}
/* check whether it can be found in default mode table */
- if (drm_monitor_supports_rb(drm_edid->edid)) {
+ if (drm_monitor_supports_rb(drm_edid)) {
mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
true);
if (mode)
@@ -3059,10 +3059,11 @@ range_pixel_clock(const struct edid *edid, const u8 *t)
return t[9] * 1 + 5001;
}
-static bool
-mode_in_range(const struct drm_display_mode *mode, const struct edid *edid,
- const struct detailed_timing *timing)
+static bool mode_in_range(const struct drm_display_mode *mode,
+ const struct drm_edid *drm_edid,
+ const struct detailed_timing *timing)
{
+ const struct edid *edid = drm_edid->edid;
u32 max_clock;
const u8 *t = (const u8 *)timing;
@@ -3081,7 +3082,7 @@ mode_in_range(const struct drm_display_mode *mode, const
struct edid *edid,
if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3
return false;
- if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
+ if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
return false;
return true;
@@ -3114,7 +3115,7 @@ static int drm_dmt_modes_for_range(struct drm_connector
*connector,
struct drm_device *dev = connector->dev;
for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
- if (mode_in_range(drm_dmt_modes + i, drm_edid->edid, timing) &&
+ if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
valid_inferred_mode(connector, drm_dmt_modes + i)) {
newmode = drm_mode_duplicate(dev, _dmt_modes[i]);
if (newmode) {
@@ -3156,7 +3157,7 @@ static int drm_gtf_modes_for_range(struct drm_connector
*connector,
return modes;
drm_mode_fixup_1366x768(newmode);
- if (!mode_in_range(newmode, drm_edid->edid, timing) ||
+ if (!mode_in_range(newmode, drm_edid, timing) ||
!valid_inferred_mode(connector, newmode)) {
drm_mode_destroy(dev, newmode);
continue;
@@ -3176,7 +3177,7 @@ static int drm_cvt_modes_for_range(struct drm_connector
*connector,
int i, modes = 0;
struct drm_display_mode *newmode;
struct drm_device *dev = connector->dev;
- bool rb = drm_monitor_supports_rb(drm_edid->edid);
+ bool rb = drm_monitor_supports_rb(drm_edid);
for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
const struct minimode *m = _modes[i];
@@ -3186,7 +3187,7 @@ static int drm_cvt_modes_for_range(struct drm_connector
*connector,
return modes;
drm_mode_fixup_1366x768(newmode);
- if (!mode_in_range(newmode, drm_edid->edid, timing) ||
+ if (!mode_in_range(newmode, drm_edid, timing) ||
!valid_inferred_mode(connector, newmode)) {
drm_mode_destroy(dev, newmode);
continue;
--
2.30.2
[Intel-gfx] [PATCH 13/25] drm/edid: convert drm_mode_std() and children to drm_edid
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 52 --
1 file changed, 27 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 27655da6ef9c..4b2d3453fc5c 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2655,11 +2655,11 @@ find_gtf2(const struct detailed_timing *descriptor,
void *data)
/* Secondary GTF curve kicks in above some break frequency */
static int
-drm_gtf2_hbreak(const struct edid *edid)
+drm_gtf2_hbreak(const struct drm_edid *drm_edid)
{
const struct detailed_timing *descriptor = NULL;
- drm_for_each_detailed_block(edid, find_gtf2, );
+ drm_for_each_detailed_block(drm_edid->edid, find_gtf2, );
BUILD_BUG_ON(offsetof(typeof(*descriptor),
data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
@@ -2667,11 +2667,11 @@ drm_gtf2_hbreak(const struct edid *edid)
}
static int
-drm_gtf2_2c(const struct edid *edid)
+drm_gtf2_2c(const struct drm_edid *drm_edid)
{
const struct detailed_timing *descriptor = NULL;
- drm_for_each_detailed_block(edid, find_gtf2, );
+ drm_for_each_detailed_block(drm_edid->edid, find_gtf2, );
BUILD_BUG_ON(offsetof(typeof(*descriptor),
data.other_data.data.range.formula.gtf2.c) != 13);
@@ -2679,11 +2679,11 @@ drm_gtf2_2c(const struct edid *edid)
}
static int
-drm_gtf2_m(const struct edid *edid)
+drm_gtf2_m(const struct drm_edid *drm_edid)
{
const struct detailed_timing *descriptor = NULL;
- drm_for_each_detailed_block(edid, find_gtf2, );
+ drm_for_each_detailed_block(drm_edid->edid, find_gtf2, );
BUILD_BUG_ON(offsetof(typeof(*descriptor),
data.other_data.data.range.formula.gtf2.m) != 14);
@@ -2691,11 +2691,11 @@ drm_gtf2_m(const struct edid *edid)
}
static int
-drm_gtf2_k(const struct edid *edid)
+drm_gtf2_k(const struct drm_edid *drm_edid)
{
const struct detailed_timing *descriptor = NULL;
- drm_for_each_detailed_block(edid, find_gtf2, );
+ drm_for_each_detailed_block(drm_edid->edid, find_gtf2, );
BUILD_BUG_ON(offsetof(typeof(*descriptor),
data.other_data.data.range.formula.gtf2.k) != 16);
@@ -2703,11 +2703,11 @@ drm_gtf2_k(const struct edid *edid)
}
static int
-drm_gtf2_2j(const struct edid *edid)
+drm_gtf2_2j(const struct drm_edid *drm_edid)
{
const struct detailed_timing *descriptor = NULL;
- drm_for_each_detailed_block(edid, find_gtf2, );
+ drm_for_each_detailed_block(drm_edid->edid, find_gtf2, );
BUILD_BUG_ON(offsetof(typeof(*descriptor),
data.other_data.data.range.formula.gtf2.j) != 17);
@@ -2715,12 +2715,14 @@ drm_gtf2_2j(const struct edid *edid)
}
/* Get standard timing level (CVT/GTF/DMT). */
-static int standard_timing_level(const struct edid *edid)
+static int standard_timing_level(const struct drm_edid *drm_edid)
{
+ const struct edid *edid = drm_edid->edid;
+
if (edid->revision >= 2) {
if (edid->revision >= 4 && (edid->features &
DRM_EDID_FEATURE_DEFAULT_GTF))
return LEVEL_CVT;
- if (drm_gtf2_hbreak(edid))
+ if (drm_gtf2_hbreak(drm_edid))
return LEVEL_GTF2;
if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
return LEVEL_GTF;
@@ -2752,9 +2754,9 @@ static int drm_mode_hsync(const struct drm_display_mode
*mode)
* Take the standard timing params (in this case width, aspect, and refresh)
* and convert them into a real mode using CVT/GTF/DMT.
*/
-static struct drm_display_mode *
-drm_mode_std(struct drm_connector *connector, const struct edid *edid,
-const struct std_timing *t)
+static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
+const struct drm_edid *drm_edid,
+const struct std_timing *t)
{
struct drm_device *dev = connector->dev;
struct drm_display_mode *m, *mode = NULL;
@@ -2764,7 +2766,7 @@ drm_mode_std(struct drm_connector *connector, const
struct edid *edid,
>> EDID_TIMING_ASPECT_SHIFT;
unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
>> EDID_TIMING_VFREQ_SHIFT;
- int timing_level = standard_timing_level(edid);
+ int timing_level = standard_timing_level(drm_edid);
if (bad_std_timing(t->hsize, t->vfreq_aspect))
return NULL;
@@ -2775,7 +2777,7 @@ drm_mode_std(struct drm_connector *connector, const
struct edid *edid,
vrefresh_rate = vfreq + 60;
/* the vdisplay is calculated based on the aspect ratio */
if (aspect_ratio == 0) {
- if (edid->revision < 3)
+ if (drm_edid->edid->revision < 3)
vsize = hsize;
else
[Intel-gfx] [PATCH 12/25] drm/edid: convert drm_cvt_modes_for_range() to drm_edid
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 3931c3318cf7..27655da6ef9c 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3167,14 +3167,14 @@ static int drm_gtf_modes_for_range(struct drm_connector
*connector,
return modes;
}
-static int
-drm_cvt_modes_for_range(struct drm_connector *connector, const struct edid
*edid,
- const struct detailed_timing *timing)
+static int drm_cvt_modes_for_range(struct drm_connector *connector,
+ const struct drm_edid *drm_edid,
+ const struct detailed_timing *timing)
{
int i, modes = 0;
struct drm_display_mode *newmode;
struct drm_device *dev = connector->dev;
- bool rb = drm_monitor_supports_rb(edid);
+ bool rb = drm_monitor_supports_rb(drm_edid->edid);
for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
const struct minimode *m = _modes[i];
@@ -3184,7 +3184,7 @@ drm_cvt_modes_for_range(struct drm_connector *connector,
const struct edid *edid
return modes;
drm_mode_fixup_1366x768(newmode);
- if (!mode_in_range(newmode, edid, timing) ||
+ if (!mode_in_range(newmode, drm_edid->edid, timing) ||
!valid_inferred_mode(connector, newmode)) {
drm_mode_destroy(dev, newmode);
continue;
@@ -3226,7 +3226,7 @@ do_inferred_modes(const struct detailed_timing *timing,
void *c)
break;
closure->modes += drm_cvt_modes_for_range(closure->connector,
-
closure->drm_edid->edid,
+ closure->drm_edid,
timing);
break;
case 0x01: /* just the ranges, no formula */
--
2.30.2
[Intel-gfx] [PATCH 11/25] drm/edid: convert drm_gtf_modes_for_range() to drm_edid
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 88bb6c7ac97c..3931c3318cf7 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3138,9 +3138,9 @@ void drm_mode_fixup_1366x768(struct drm_display_mode
*mode)
}
}
-static int
-drm_gtf_modes_for_range(struct drm_connector *connector, const struct edid
*edid,
- const struct detailed_timing *timing)
+static int drm_gtf_modes_for_range(struct drm_connector *connector,
+ const struct drm_edid *drm_edid,
+ const struct detailed_timing *timing)
{
int i, modes = 0;
struct drm_display_mode *newmode;
@@ -3154,7 +3154,7 @@ drm_gtf_modes_for_range(struct drm_connector *connector,
const struct edid *edid
return modes;
drm_mode_fixup_1366x768(newmode);
- if (!mode_in_range(newmode, edid, timing) ||
+ if (!mode_in_range(newmode, drm_edid->edid, timing) ||
!valid_inferred_mode(connector, newmode)) {
drm_mode_destroy(dev, newmode);
continue;
@@ -3218,7 +3218,7 @@ do_inferred_modes(const struct detailed_timing *timing,
void *c)
case 0x02: /* secondary gtf, XXX could do more */
case 0x00: /* default gtf */
closure->modes += drm_gtf_modes_for_range(closure->connector,
-
closure->drm_edid->edid,
+ closure->drm_edid,
timing);
break;
case 0x04: /* cvt, only in 1.4+ */
--
2.30.2
[Intel-gfx] [PATCH 10/25] drm/edid: convert drm_dmt_modes_for_range() to drm_edid
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index b5d7347f32d9..88bb6c7ac97c 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3103,16 +3103,16 @@ static bool valid_inferred_mode(const struct
drm_connector *connector,
return ok;
}
-static int
-drm_dmt_modes_for_range(struct drm_connector *connector, const struct edid
*edid,
- const struct detailed_timing *timing)
+static int drm_dmt_modes_for_range(struct drm_connector *connector,
+ const struct drm_edid *drm_edid,
+ const struct detailed_timing *timing)
{
int i, modes = 0;
struct drm_display_mode *newmode;
struct drm_device *dev = connector->dev;
for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
- if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
+ if (mode_in_range(drm_dmt_modes + i, drm_edid->edid, timing) &&
valid_inferred_mode(connector, drm_dmt_modes + i)) {
newmode = drm_mode_duplicate(dev, _dmt_modes[i]);
if (newmode) {
@@ -3208,7 +3208,7 @@ do_inferred_modes(const struct detailed_timing *timing,
void *c)
return;
closure->modes += drm_dmt_modes_for_range(closure->connector,
- closure->drm_edid->edid,
+ closure->drm_edid,
timing);
if (!version_greater(closure->drm_edid->edid, 1, 1))
--
2.30.2
[Intel-gfx] [PATCH 08/25] drm/edid: convert struct detailed_mode_closure to drm_edid
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index fdc6ad651d3f..1abdd88ff64b 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -96,7 +96,7 @@ static int oui(u8 first, u8 second, u8 third)
struct detailed_mode_closure {
struct drm_connector *connector;
- const struct edid *edid;
+ const struct drm_edid *drm_edid;
bool preferred;
u32 quirks;
int modes;
@@ -3208,25 +3208,25 @@ do_inferred_modes(const struct detailed_timing *timing,
void *c)
return;
closure->modes += drm_dmt_modes_for_range(closure->connector,
- closure->edid,
+ closure->drm_edid->edid,
timing);
- if (!version_greater(closure->edid, 1, 1))
+ if (!version_greater(closure->drm_edid->edid, 1, 1))
return; /* GTF not defined yet */
switch (range->flags) {
case 0x02: /* secondary gtf, XXX could do more */
case 0x00: /* default gtf */
closure->modes += drm_gtf_modes_for_range(closure->connector,
- closure->edid,
+
closure->drm_edid->edid,
timing);
break;
case 0x04: /* cvt, only in 1.4+ */
- if (!version_greater(closure->edid, 1, 3))
+ if (!version_greater(closure->drm_edid->edid, 1, 3))
break;
closure->modes += drm_cvt_modes_for_range(closure->connector,
- closure->edid,
+
closure->drm_edid->edid,
timing);
break;
case 0x01: /* just the ranges, no formula */
@@ -3240,7 +3240,7 @@ static int add_inferred_modes(struct drm_connector
*connector,
{
struct detailed_mode_closure closure = {
.connector = connector,
- .edid = drm_edid->edid,
+ .drm_edid = drm_edid,
};
if (version_greater(drm_edid->edid, 1, 0))
@@ -3305,7 +3305,7 @@ static int add_established_modes(struct drm_connector
*connector,
int i, modes = 0;
struct detailed_mode_closure closure = {
.connector = connector,
- .edid = edid,
+ .drm_edid = drm_edid,
};
for (i = 0; i <= EDID_EST_TIMINGS; i++) {
@@ -,7 +,6 @@ do_standard_modes(const struct detailed_timing *timing,
void *c)
struct detailed_mode_closure *closure = c;
const struct detailed_non_pixel *data = >data.other_data;
struct drm_connector *connector = closure->connector;
- const struct edid *edid = closure->edid;
int i;
if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
@@ -3343,7 +3342,7 @@ do_standard_modes(const struct detailed_timing *timing,
void *c)
const struct std_timing *std = >data.timings[i];
struct drm_display_mode *newmode;
- newmode = drm_mode_std(connector, edid, std);
+ newmode = drm_mode_std(connector, closure->drm_edid->edid, std);
if (newmode) {
drm_mode_probed_add(connector, newmode);
closure->modes++;
@@ -3362,7 +3361,7 @@ static int add_standard_modes(struct drm_connector
*connector,
int i, modes = 0;
struct detailed_mode_closure closure = {
.connector = connector,
- .edid = drm_edid->edid,
+ .drm_edid = drm_edid,
};
for (i = 0; i < EDID_STD_TIMINGS; i++) {
@@ -3453,7 +3452,7 @@ add_cvt_modes(struct drm_connector *connector, const
struct drm_edid *drm_edid)
{
struct detailed_mode_closure closure = {
.connector = connector,
- .edid = drm_edid->edid,
+ .drm_edid = drm_edid,
};
if (version_greater(drm_edid->edid, 1, 2))
@@ -3476,7 +3475,7 @@ do_detailed_mode(const struct detailed_timing *timing,
void *c)
return;
newmode = drm_mode_detailed(closure->connector->dev,
- closure->edid, timing,
+ closure->drm_edid->edid, timing,
closure->quirks);
if (!newmode)
return;
@@ -3507,7 +3506,7 @@ static int add_detailed_modes(struct drm_connector
*connector,
{
struct detailed_mode_closure closure = {
[Intel-gfx] [PATCH 09/25] drm/edid: convert drm_mode_detailed() to drm_edid
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 1abdd88ff64b..b5d7347f32d9 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2910,7 +2910,7 @@ drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
* drm_display_mode.
*/
static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
- const struct edid *edid,
+ const struct drm_edid
*drm_edid,
const struct detailed_timing
*timing,
u32 quirks)
{
@@ -2998,8 +2998,8 @@ static struct drm_display_mode *drm_mode_detailed(struct
drm_device *dev,
}
if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
- mode->width_mm = edid->width_cm * 10;
- mode->height_mm = edid->height_cm * 10;
+ mode->width_mm = drm_edid->edid->width_cm * 10;
+ mode->height_mm = drm_edid->edid->height_cm * 10;
}
mode->type = DRM_MODE_TYPE_DRIVER;
@@ -3475,7 +3475,7 @@ do_detailed_mode(const struct detailed_timing *timing,
void *c)
return;
newmode = drm_mode_detailed(closure->connector->dev,
- closure->drm_edid->edid, timing,
+ closure->drm_edid, timing,
closure->quirks);
if (!newmode)
return;
--
2.30.2
[Intel-gfx] [PATCH 07/25] drm/edid: convert drm_edid_connector_update() to drm_edid fully
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 95 ++
1 file changed, 46 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 74038be72ad3..fdc6ad651d3f 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3235,16 +3235,16 @@ do_inferred_modes(const struct detailed_timing *timing,
void *c)
}
}
-static int
-add_inferred_modes(struct drm_connector *connector, const struct edid *edid)
+static int add_inferred_modes(struct drm_connector *connector,
+ const struct drm_edid *drm_edid)
{
struct detailed_mode_closure closure = {
.connector = connector,
- .edid = edid,
+ .edid = drm_edid->edid,
};
- if (version_greater(edid, 1, 0))
- drm_for_each_detailed_block(edid, do_inferred_modes, );
+ if (version_greater(drm_edid->edid, 1, 0))
+ drm_for_each_detailed_block(drm_edid->edid, do_inferred_modes,
);
return closure.modes;
}
@@ -3294,10 +3294,11 @@ do_established_modes(const struct detailed_timing
*timing, void *c)
* bitmap of the supported "established modes" list (defined above). Tease them
* out and add them to the global modes list.
*/
-static int
-add_established_modes(struct drm_connector *connector, const struct edid *edid)
+static int add_established_modes(struct drm_connector *connector,
+const struct drm_edid *drm_edid)
{
struct drm_device *dev = connector->dev;
+ const struct edid *edid = drm_edid->edid;
unsigned long est_bits = edid->established_timings.t1 |
(edid->established_timings.t2 << 8) |
((edid->established_timings.mfg_rsvd & 0x80) << 9);
@@ -3320,7 +3321,7 @@ add_established_modes(struct drm_connector *connector,
const struct edid *edid)
}
if (version_greater(edid, 1, 0))
- drm_for_each_detailed_block(edid, do_established_modes,
+ drm_for_each_detailed_block(drm_edid->edid,
do_established_modes,
);
return modes + closure.modes;
@@ -3355,28 +3356,28 @@ do_standard_modes(const struct detailed_timing *timing,
void *c)
* using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
* add them to the list.
*/
-static int
-add_standard_modes(struct drm_connector *connector, const struct edid *edid)
+static int add_standard_modes(struct drm_connector *connector,
+ const struct drm_edid *drm_edid)
{
int i, modes = 0;
struct detailed_mode_closure closure = {
.connector = connector,
- .edid = edid,
+ .edid = drm_edid->edid,
};
for (i = 0; i < EDID_STD_TIMINGS; i++) {
struct drm_display_mode *newmode;
- newmode = drm_mode_std(connector, edid,
- >standard_timings[i]);
+ newmode = drm_mode_std(connector, drm_edid->edid,
+ _edid->edid->standard_timings[i]);
if (newmode) {
drm_mode_probed_add(connector, newmode);
modes++;
}
}
- if (version_greater(edid, 1, 0))
- drm_for_each_detailed_block(edid, do_standard_modes,
+ if (version_greater(drm_edid->edid, 1, 0))
+ drm_for_each_detailed_block(drm_edid->edid, do_standard_modes,
);
/* XXX should also look for standard codes in VTB blocks */
@@ -3448,15 +3449,15 @@ do_cvt_mode(const struct detailed_timing *timing, void
*c)
}
static int
-add_cvt_modes(struct drm_connector *connector, const struct edid *edid)
+add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
{
struct detailed_mode_closure closure = {
.connector = connector,
- .edid = edid,
+ .edid = drm_edid->edid,
};
- if (version_greater(edid, 1, 2))
- drm_for_each_detailed_block(edid, do_cvt_mode, );
+ if (version_greater(drm_edid->edid, 1, 2))
+ drm_for_each_detailed_block(drm_edid->edid, do_cvt_mode,
);
/* XXX should also look for CVT codes in VTB blocks */
@@ -3501,22 +3502,21 @@ do_detailed_mode(const struct detailed_timing *timing,
void *c)
* @edid: EDID block to scan
* @quirks: quirks to apply
*/
-static int
-add_detailed_modes(struct drm_connector *connector, const struct edid *edid,
- u32 quirks)
+static int add_detailed_modes(struct drm_connector *connector,
+ const struct drm_edid *drm_edid, u32 quirks)
{
struct detailed_mode_closure closure = {
[Intel-gfx] [PATCH 06/25] drm/edid: propagate drm_edid to drm_edid_to_eld()
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index c9d48fbd0a76..74038be72ad3 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4865,13 +4865,13 @@ static void clear_eld(struct drm_connector *connector)
/*
* drm_edid_to_eld - build ELD from EDID
* @connector: connector corresponding to the HDMI/DP sink
- * @edid: EDID to parse
+ * @drm_edid: EDID to parse
*
* Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
* HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
*/
static void drm_edid_to_eld(struct drm_connector *connector,
- const struct edid *edid)
+ const struct drm_edid *drm_edid)
{
const struct drm_display_info *info = >display_info;
const struct cea_db *db;
@@ -4882,10 +4882,10 @@ static void drm_edid_to_eld(struct drm_connector
*connector,
clear_eld(connector);
- if (!edid)
+ if (!drm_edid)
return;
- mnl = get_monitor_name(edid, [DRM_ELD_MONITOR_NAME_STRING]);
+ mnl = get_monitor_name(drm_edid->edid,
[DRM_ELD_MONITOR_NAME_STRING]);
DRM_DEBUG_KMS("ELD monitor %s\n", [DRM_ELD_MONITOR_NAME_STRING]);
eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev <<
DRM_ELD_CEA_EDID_VER_SHIFT;
@@ -4893,12 +4893,12 @@ static void drm_edid_to_eld(struct drm_connector
*connector,
eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
- eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
- eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
- eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
- eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
+ eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
+ eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
+ eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
+ eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
- cea_db_iter_edid_begin(edid, );
+ cea_db_iter_edid_begin(drm_edid->edid, );
cea_db_iter_for_each(db, ) {
const u8 *data = cea_db_data(db);
int len = cea_db_payload_len(db);
@@ -5848,7 +5848,7 @@ static int drm_edid_connector_update(struct drm_connector
*connector,
quirks = update_display_info(connector, drm_edid);
/* Depends on info->cea_rev set by drm_add_display_info() above */
- drm_edid_to_eld(connector, edid);
+ drm_edid_to_eld(connector, drm_edid);
/*
* EDID spec says modes should be preferred in this order:
--
2.30.2
[Intel-gfx] [PATCH 05/25] drm/edid: keep propagating drm_edid to display info
We'll need to propagate drm_edid everywhere.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 50 +++---
1 file changed, 31 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 946296632b2e..c9d48fbd0a76 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2419,13 +2419,13 @@ EXPORT_SYMBOL(drm_edid_duplicate);
/**
* edid_get_quirks - return quirk flags for a given EDID
- * @edid: EDID to process
+ * @drm_edid: EDID to process
*
* This tells subsequent routines what fixes they need to apply.
*/
-static u32 edid_get_quirks(const struct edid *edid)
+static u32 edid_get_quirks(const struct drm_edid *drm_edid)
{
- u32 panel_id = edid_extract_panel_id(edid);
+ u32 panel_id = edid_extract_panel_id(drm_edid->edid);
const struct edid_quirk *quirk;
int i;
@@ -5448,7 +5448,7 @@ static void drm_parse_microsoft_vsdb(struct drm_connector
*connector,
}
static void drm_parse_cea_ext(struct drm_connector *connector,
- const struct edid *edid)
+ const struct drm_edid *drm_edid)
{
struct drm_display_info *info = >display_info;
struct drm_edid_iter edid_iter;
@@ -5456,7 +5456,7 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
struct cea_db_iter iter;
const u8 *edid_ext;
- drm_edid_iter_begin(edid, _iter);
+ drm_edid_iter_begin(drm_edid->edid, _iter);
drm_edid_iter_for_each(edid_ext, _iter) {
if (edid_ext[0] != CEA_EXT)
continue;
@@ -5477,7 +5477,7 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
}
drm_edid_iter_end(_iter);
- cea_db_iter_edid_begin(edid, );
+ cea_db_iter_edid_begin(drm_edid->edid, );
cea_db_iter_for_each(db, ) {
/* FIXME: convert parsers to use struct cea_db */
const u8 *data = (const u8 *)db;
@@ -5523,16 +5523,15 @@ void get_monitor_range(const struct detailed_timing
*timing,
monitor_range->max_vfreq = range->max_vfreq;
}
-static
-void drm_get_monitor_range(struct drm_connector *connector,
- const struct edid *edid)
+static void drm_get_monitor_range(struct drm_connector *connector,
+ const struct drm_edid *drm_edid)
{
struct drm_display_info *info = >display_info;
- if (!version_greater(edid, 1, 1))
+ if (!version_greater(drm_edid->edid, 1, 1))
return;
- drm_for_each_detailed_block(edid, get_monitor_range,
+ drm_for_each_detailed_block(drm_edid->edid, get_monitor_range,
>monitor_range);
DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
@@ -5592,12 +5591,13 @@ static void drm_parse_vesa_mso_data(struct
drm_connector *connector,
info->mso_stream_count, info->mso_pixel_overlap);
}
-static void drm_update_mso(struct drm_connector *connector, const struct edid
*edid)
+static void drm_update_mso(struct drm_connector *connector,
+ const struct drm_edid *drm_edid)
{
const struct displayid_block *block;
struct displayid_iter iter;
- displayid_iter_edid_begin(edid, );
+ displayid_iter_edid_begin(drm_edid->edid, );
displayid_iter_for_each(block, ) {
if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
drm_parse_vesa_mso_data(connector, block);
@@ -5636,18 +5636,20 @@ drm_reset_display_info(struct drm_connector *connector)
info->mso_pixel_overlap = 0;
}
-u32 drm_add_display_info(struct drm_connector *connector, const struct edid
*edid)
+static u32 update_display_info(struct drm_connector *connector,
+ const struct drm_edid *drm_edid)
{
struct drm_display_info *info = >display_info;
+ const struct edid *edid = drm_edid->edid;
- u32 quirks = edid_get_quirks(edid);
+ u32 quirks = edid_get_quirks(drm_edid);
drm_reset_display_info(connector);
info->width_mm = edid->width_cm * 10;
info->height_mm = edid->height_cm * 10;
- drm_get_monitor_range(connector, edid);
+ drm_get_monitor_range(connector, drm_edid);
if (edid->revision < 3)
goto out;
@@ -5656,7 +5658,7 @@ u32 drm_add_display_info(struct drm_connector *connector,
const struct edid *edi
goto out;
info->color_formats |= DRM_COLOR_FORMAT_RGB444;
- drm_parse_cea_ext(connector, edid);
+ drm_parse_cea_ext(connector, drm_edid);
/*
* Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
@@ -5709,7 +5711,7 @@ u32 drm_add_display_info(struct drm_connector *connector,
const struct edid *edi
if (edid->features &
[Intel-gfx] [PATCH 04/25] drm/edid: start propagating drm_edid to lower levels
We'll need to propagate drm_edid everywhere. This is a clunky start, but
a start nonetheless. We'll eventually convert all of the EDID parsing to
struct drm_edid.
Initially, we'll just create the struct drm_edid in stack. This will be
the compat layer for legacy struct edid code. In the future, we'll have
EDID read return drm_edid objects.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 480fd9fbe412..946296632b2e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -5814,17 +5814,20 @@ static int add_displayid_detailed_modes(struct
drm_connector *connector,
}
static int drm_edid_connector_update(struct drm_connector *connector,
-const struct edid *edid)
+const struct drm_edid *drm_edid)
{
+ const struct edid *edid;
int num_modes = 0;
u32 quirks;
- if (edid == NULL) {
+ if (drm_edid == NULL) {
drm_reset_display_info(connector);
clear_eld(connector);
return 0;
}
+ edid = drm_edid->edid;
+
/*
* CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
* To avoid multiple parsing of same block, lets parse that map
@@ -5890,13 +5893,20 @@ static int drm_edid_connector_update(struct
drm_connector *connector,
*/
int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
{
+ struct drm_edid drm_edid = {};
+
if (edid && !drm_edid_is_valid(edid)) {
drm_warn(connector->dev, "%s: EDID invalid.\n",
connector->name);
edid = NULL;
}
- return drm_edid_connector_update(connector, edid);
+ if (edid) {
+ drm_edid.edid = edid;
+ drm_edid.size = edid_size(edid);
+ }
+
+ return drm_edid_connector_update(connector, edid ? _edid : NULL);
}
EXPORT_SYMBOL(drm_add_edid_modes);
--
2.30.2
[Intel-gfx] [PATCH 03/25] drm/edid: add struct drm_edid container
Introduce new opaque type struct drm_edid to encapsulate the EDID data
and the size allocated for it. The contents will be private to
drm_edid.c.
There are a number of reasons for adding a container around struct edid:
* struct edid is a raw blob pointer to data that usually originates
outside of the kernel. Its size is contained within the structure.
* There's no way to attach meta information (such as allocated memory
size) to struct edid.
* Validation of the EDID blob and its size become crucial, and it's
spread all over the subsystem, with varying levels of accuracy.
* HDMI Forum has introduced an HF-EEODB extension that defines an
override EDID size within an EDID extension. The size allocated for an
EDID depends on whether the allocator understands the HF-EEODB
extension. Given a struct edid *, it's impossible to know how much
memory was actually allocated for it.
There are also some reasons for making the container type struct
drm_edid opaque and private to drm_edid.c:
* Have only one place for creating and parsing the EDID, to avoid
duplicating bugs.
* Prepare for reading a pure DisplayID 2.0 from its own DDC address, and
adding it within the same struct drm_edid container, transparently,
and for all drivers.
* With the idea that the drm_edid objects are immutable during their
lifetimes, it will be possible to refcount them and reduce EDID
copying everywhere (this is left for future work).
Initially, just add the type. In follow-up, we'll start converting the
guts of drm_edid.c to use it, and finally add interfaces around it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index dcef92c8887a..480fd9fbe412 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1567,6 +1567,15 @@ static const struct drm_display_mode edid_4k_modes[] = {
/*** DDC fetch and block validation ***/
+/*
+ * The opaque EDID type, internal to drm_edid.c.
+ */
+struct drm_edid {
+ /* Size allocated for edid */
+ size_t size;
+ const struct edid *edid;
+};
+
static int edid_extension_block_count(const struct edid *edid)
{
return edid->extensions;
--
2.30.2
[Intel-gfx] [PATCH 02/25] drm/edid: convert drm_for_each_detailed_block() to edid iter
We have an iterator for this, use it. It does include the base block,
but its tag is 0 and will be skipped.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index efc1999b9573..dcef92c8887a 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2574,6 +2574,8 @@ vtb_for_each_detailed_block(const u8 *ext, detailed_cb
*cb, void *closure)
static void
drm_for_each_detailed_block(const struct edid *edid, detailed_cb *cb, void
*closure)
{
+ struct drm_edid_iter edid_iter;
+ const u8 *ext;
int i;
if (edid == NULL)
@@ -2582,9 +2584,8 @@ drm_for_each_detailed_block(const struct edid *edid,
detailed_cb *cb, void *clos
for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
cb(&(edid->detailed_timings[i]), closure);
- for (i = 0; i < edid_extension_block_count(edid); i++) {
- const u8 *ext = edid_extension_block_data(edid, i);
-
+ drm_edid_iter_begin(edid, _iter);
+ drm_edid_iter_for_each(ext, _iter) {
switch (*ext) {
case CEA_EXT:
cea_for_each_detailed_block(ext, cb, closure);
@@ -2596,6 +2597,7 @@ drm_for_each_detailed_block(const struct edid *edid,
detailed_cb *cb, void *clos
break;
}
}
+ drm_edid_iter_end(_iter);
}
static void
--
2.30.2
[Intel-gfx] [PATCH 01/25] drm/edid: use else-if in CTA extension parsing
Only one of the conditions can be true. Suggested-by: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/drm_edid.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 47d121e99201..efc1999b9573 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -5473,16 +5473,16 @@ static void drm_parse_cea_ext(struct drm_connector *connector, if (cea_db_is_hdmi_vsdb(db)) drm_parse_hdmi_vsdb_video(connector, data); - if (cea_db_is_hdmi_forum_vsdb(db) || - cea_db_is_hdmi_forum_scdb(db)) + else if (cea_db_is_hdmi_forum_vsdb(db) || +cea_db_is_hdmi_forum_scdb(db)) drm_parse_hdmi_forum_scds(connector, data); - if (cea_db_is_microsoft_vsdb(db)) + else if (cea_db_is_microsoft_vsdb(db)) drm_parse_microsoft_vsdb(connector, data); - if (cea_db_is_y420cmdb(db)) + else if (cea_db_is_y420cmdb(db)) drm_parse_y420cmdb_bitmap(connector, data); - if (cea_db_is_vcdb(db)) + else if (cea_db_is_vcdb(db)) drm_parse_vcdb(connector, data); - if (cea_db_is_hdmi_hdr_metadata_block(db)) + else if (cea_db_is_hdmi_hdr_metadata_block(db)) drm_parse_hdr_metadata_block(connector, data); } cea_db_iter_end(); -- 2.30.2
[Intel-gfx] [PATCH 00/25] drm/edid: introduce struct drm_edid
Introduce struct drm_edid and start converting struct edid * to struct drm_edid * in the EDID parsing. The rationale for drm_edid is explained in depth in commit message for patch 3. Initially, there's little functional benefit in the series, it's mostly just prep work. It's also intended to be relatively straightforward to review. Later on, we'll add interfaces around drm_edid that let us utilize the actual EDID buffer allocation size as metadata outside of the size contained within the EDID blob. This is a requirement for safely handling HF-EEODB without a huge flag day switch from struct edid usage. See [1] for that work. BR, Jani. [1] https://cgit.freedesktop.org/~jani/drm/log/?h=edid-hfeeodb-2022-05-06 Jani Nikula (25): drm/edid: use else-if in CTA extension parsing drm/edid: convert drm_for_each_detailed_block() to edid iter drm/edid: add struct drm_edid container drm/edid: start propagating drm_edid to lower levels drm/edid: keep propagating drm_edid to display info drm/edid: propagate drm_edid to drm_edid_to_eld() drm/edid: convert drm_edid_connector_update() to drm_edid fully drm/edid: convert struct detailed_mode_closure to drm_edid drm/edid: convert drm_mode_detailed() to drm_edid drm/edid: convert drm_dmt_modes_for_range() to drm_edid drm/edid: convert drm_gtf_modes_for_range() to drm_edid drm/edid: convert drm_cvt_modes_for_range() to drm_edid drm/edid: convert drm_mode_std() and children to drm_edid drm/edid: convert mode_in_range() and drm_monitor_supports_rb() to drm_edid drm/edid: convert get_monitor_name() to drm_edid drm/edid: convert drm_for_each_detailed_block() to drm_edid drm/edid: add drm_edid helper for drm_edid_to_sad() drm/edid: add drm_edid helper for drm_edid_to_speaker_allocation() drm/edid: add drm_edid helper for drm_detect_hdmi_monitor() drm/edid: add drm_edid helper for drm_detect_monitor_audio() drm/edid: convert cea_db_iter_edid_begin() to drm_edid drm/edid: convert drm_edid_iter_begin() to drm_edid drm/edid: add drm_edid helper for drm_update_tile_info() drm/displayid: convert to drm_edid drm/edid: convert version_greater() to drm_edid drivers/gpu/drm/drm_displayid.c | 16 +- drivers/gpu/drm/drm_edid.c | 542 +++- include/drm/drm_displayid.h | 6 +- include/drm/drm_edid.h | 6 +- 4 files changed, 337 insertions(+), 233 deletions(-) -- 2.30.2
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc/rc: Use i915_probe_error instead of drm_error
== Series Details ==
Series: drm/i915/guc/rc: Use i915_probe_error instead of drm_error
URL : https://patchwork.freedesktop.org/series/103656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11614_full -> Patchwork_103656v1_full
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103656v1/index.html
Participating hosts (12 -> 9)
--
Missing(3): pig-skl-6260u pig-kbl-iris pig-glk-j5005
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_103656v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane_scaling@upscale-with-modifier-20x20}:
- {shard-rkl}:NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103656v1/shard-rkl-1/igt@kms_plane_scal...@upscale-with-modifier-20x20.html
Known issues
Here are the changes found in Patchwork_103656v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@drm_buddy@all@buddy_alloc_smoke:
- shard-skl: [PASS][2] -> [INCOMPLETE][3] ([i915#5800])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11614/shard-skl10/igt@drm_buddy@all@buddy_alloc_smoke.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103656v1/shard-skl10/igt@drm_buddy@all@buddy_alloc_smoke.html
* igt@gem_exec_balancer@parallel:
- shard-kbl: NOTRUN -> [DMESG-WARN][4] ([i915#5076] / [i915#5614])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103656v1/shard-kbl7/igt@gem_exec_balan...@parallel.html
* igt@gem_exec_endless@dispatch@vcs0:
- shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([i915#3778])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11614/shard-tglb6/igt@gem_exec_endless@dispa...@vcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103656v1/shard-tglb3/igt@gem_exec_endless@dispa...@vcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11614/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103656v1/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-iclb: NOTRUN -> [FAIL][9] ([i915#2842]) +3 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103656v1/shard-iclb7/igt@gem_exec_fair@basic-n...@vecs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: NOTRUN -> [FAIL][10] ([i915#2842]) +1 similar issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103656v1/shard-kbl7/igt@gem_exec_fair@basic-p...@vecs0.html
* igt@gem_exec_flush@basic-uc-pro-default:
- shard-snb: [PASS][11] -> [SKIP][12] ([fdo#109271]) +1 similar
issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11614/shard-snb2/igt@gem_exec_fl...@basic-uc-pro-default.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103656v1/shard-snb6/igt@gem_exec_fl...@basic-uc-pro-default.html
* igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][13] ([fdo#112283])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103656v1/shard-iclb7/igt@gem_exec_par...@secure-non-root.html
* igt@gem_huc_copy@huc-copy:
- shard-iclb: NOTRUN -> [SKIP][14] ([i915#2190])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103656v1/shard-iclb7/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@random:
- shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103656v1/shard-skl4/igt@gem_lmem_swapp...@random.html
* igt@gem_lmem_swapping@smem-oom:
- shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +1
similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103656v1/shard-kbl7/igt@gem_lmem_swapp...@smem-oom.html
* igt@gem_pxp@create-protected-buffer:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#4270]) +2 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103656v1/shard-iclb7/igt@gem_...@create-protected-buffer.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#768])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103656v1/shard-iclb7/igt@gem_render_c...@y-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_softpin@evict-single-offset:
- shard-kbl: NOTRUN -> [FAIL][19] ([i915#4171])
[19]:
Re: [Intel-gfx] [PATCH -next] drm/i915/gt: Fix build error without CONFIG_PM
Hi YueHaibing,
On Fri, May 06, 2022 at 11:26:52AM +0800, YueHaibing wrote:
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c: In function ‘act_freq_mhz_show’:
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:276:20: error: implicit
> declaration of function ‘sysfs_gt_attribute_r_max_func’
> [-Werror=implicit-function-declaration]
> 276 | u32 actual_freq = sysfs_gt_attribute_r_max_func(dev, attr,
> |^
>
> Move sysfs_gt_attribute_* macros out of #ifdef block to fix this.
>
> Fixes: 56a709cf7746 ("drm/i915/gt: Create per-tile RPS sysfs interfaces")
> Signed-off-by: YueHaibing
Reviewed-by: Andi Shyti
Thanks,
Andi
> ---
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> index 26cbfa6477d1..e92990d514b2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> @@ -17,7 +17,6 @@
> #include "intel_rc6.h"
> #include "intel_rps.h"
>
> -#ifdef CONFIG_PM
> enum intel_gt_sysfs_op {
> INTEL_GT_SYSFS_MIN = 0,
> INTEL_GT_SYSFS_MAX,
> @@ -92,6 +91,7 @@ sysfs_gt_attribute_r_func(struct device *dev, struct
> device_attribute *attr,
> #define sysfs_gt_attribute_r_max_func(d, a, f) \
> sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
>
> +#ifdef CONFIG_PM
> static u32 get_residency(struct intel_gt *gt, i915_reg_t reg)
> {
> intel_wakeref_t wakeref;
> --
> 2.17.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Fix build error without CONFIG_PM
== Series Details ==
Series: drm/i915/gt: Fix build error without CONFIG_PM
URL : https://patchwork.freedesktop.org/series/103654/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11614_full -> Patchwork_103654v1_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_103654v1_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_103654v1_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (12 -> 12)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_103654v1_full:
### IGT changes ###
Possible regressions
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-skl: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103654v1/shard-skl3/igt@gem_partial_pwrite_pr...@writes-after-reads-uncached.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane_scaling@upscale-with-modifier-20x20}:
- {shard-rkl}:NOTRUN -> [SKIP][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103654v1/shard-rkl-5/igt@kms_plane_scal...@upscale-with-modifier-20x20.html
Known issues
Here are the changes found in Patchwork_103654v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_create@create-massive:
- shard-snb: NOTRUN -> [DMESG-WARN][3] ([i915#4991])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103654v1/shard-snb4/igt@gem_cre...@create-massive.html
* igt@gem_eio@in-flight-1us:
- shard-skl: [PASS][4] -> [TIMEOUT][5] ([i915#3063])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11614/shard-skl3/igt@gem_...@in-flight-1us.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103654v1/shard-skl7/igt@gem_...@in-flight-1us.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) +3 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103654v1/shard-iclb5/igt@gem_exec_fair@basic-n...@vecs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: NOTRUN -> [FAIL][7] ([i915#2842]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103654v1/shard-kbl7/igt@gem_exec_fair@basic-p...@vecs0.html
* igt@gem_exec_flush@basic-wb-pro-default:
- shard-snb: [PASS][8] -> [SKIP][9] ([fdo#109271]) +4 similar
issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11614/shard-snb7/igt@gem_exec_fl...@basic-wb-pro-default.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103654v1/shard-snb6/igt@gem_exec_fl...@basic-wb-pro-default.html
* igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][10] ([fdo#112283])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103654v1/shard-iclb5/igt@gem_exec_par...@secure-non-root.html
* igt@gem_exec_whisper@basic-forked:
- shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#118])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11614/shard-glk5/igt@gem_exec_whis...@basic-forked.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103654v1/shard-glk5/igt@gem_exec_whis...@basic-forked.html
* igt@gem_huc_copy@huc-copy:
- shard-iclb: NOTRUN -> [SKIP][13] ([i915#2190])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103654v1/shard-iclb5/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@random:
- shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103654v1/shard-skl3/igt@gem_lmem_swapp...@random.html
* igt@gem_lmem_swapping@smem-oom:
- shard-kbl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103654v1/shard-kbl4/igt@gem_lmem_swapp...@smem-oom.html
* igt@gem_pxp@create-protected-buffer:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#4270]) +1 similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103654v1/shard-iclb5/igt@gem_...@create-protected-buffer.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#768])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103654v1/shard-iclb5/igt@gem_render_c...@y-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_softpin@evict-single-offset:
- shard-kbl: NOTRUN -> [FAIL][18]
Re: [Intel-gfx] [PATCH -next] drm/i915/gt: Fix build error without CONFIG_PM
On 06/05/2022 04:26, YueHaibing wrote:
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c: In function ‘act_freq_mhz_show’:
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:276:20: error: implicit declaration
of function ‘sysfs_gt_attribute_r_max_func’
[-Werror=implicit-function-declaration]
276 | u32 actual_freq = sysfs_gt_attribute_r_max_func(dev, attr,
|^
Move sysfs_gt_attribute_* macros out of #ifdef block to fix this.
Fixes: 56a709cf7746 ("drm/i915/gt: Create per-tile RPS sysfs interfaces")
Signed-off-by: YueHaibing
Reviewed-by: Tvrtko Ursulin
Thanks for the fix, will merge.
Regards,
Tvrtko
---
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 26cbfa6477d1..e92990d514b2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -17,7 +17,6 @@
#include "intel_rc6.h"
#include "intel_rps.h"
-#ifdef CONFIG_PM
enum intel_gt_sysfs_op {
INTEL_GT_SYSFS_MIN = 0,
INTEL_GT_SYSFS_MAX,
@@ -92,6 +91,7 @@ sysfs_gt_attribute_r_func(struct device *dev, struct
device_attribute *attr,
#define sysfs_gt_attribute_r_max_func(d, a, f) \
sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
+#ifdef CONFIG_PM
static u32 get_residency(struct intel_gt *gt, i915_reg_t reg)
{
intel_wakeref_t wakeref;
Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Support programming the EU priority in the GuC descriptor
On 05/05/2022 19:56, John Harrison wrote:
On 5/4/2022 16:46, Daniele Ceraolo Spurio wrote:
From: Matthew Brost
In GuC submission mode the EU priority must be updated by the GuC rather
than the driver as the GuC owns the programming of the context
descriptor.
Given that the GuC code uses the GuC priorities, we can't use a generic
function using i915 priorities for both execlists and GuC submission.
The existing function has therefore been pushed to the execlists
back-end while a new one has been added for GuC.
v2: correctly use the GuC prio.
Cc: John Harrison
Cc: Matt Roper
Signed-off-by: Matthew Brost
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: John Harrison
I've asked for this already - since this seems a fix relevant for DG2,
but now that it has been merged without a Fixes: tag, it will not get
picked up for 5.19 by the scripts.
Maybe I can cherry pick it manually in a few weeks, or maybe you guys
can send it to stable manually once 5.19 is released, please make a
reminder item if you think 5.19 should have it.
Regards,
Tvrtko
---
.../drm/i915/gt/intel_execlists_submission.c | 12 +-
drivers/gpu/drm/i915/gt/intel_lrc.h | 10 -
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 22 +++
3 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 86f7a9ac1c394..2b0266cab66b9 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -661,6 +661,16 @@ static inline void execlists_schedule_out(struct
i915_request *rq)
i915_request_put(rq);
}
+static u32 map_i915_prio_to_lrc_desc_prio(int prio)
+{
+ if (prio > I915_PRIORITY_NORMAL)
+ return GEN12_CTX_PRIORITY_HIGH;
+ else if (prio < I915_PRIORITY_NORMAL)
+ return GEN12_CTX_PRIORITY_LOW;
+ else
+ return GEN12_CTX_PRIORITY_NORMAL;
+}
+
static u64 execlists_update_context(struct i915_request *rq)
{
struct intel_context *ce = rq->context;
@@ -669,7 +679,7 @@ static u64 execlists_update_context(struct
i915_request *rq)
desc = ce->lrc.desc;
if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
- desc |= lrc_desc_priority(rq_prio(rq));
+ desc |= map_i915_prio_to_lrc_desc_prio(rq_prio(rq));
/*
* WaIdleLiteRestore:bdw,skl
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h
b/drivers/gpu/drm/i915/gt/intel_lrc.h
index 31be734010db3..a390f0813c8b6 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -111,16 +111,6 @@ enum {
#define XEHP_SW_COUNTER_SHIFT 58
#define XEHP_SW_COUNTER_WIDTH 6
-static inline u32 lrc_desc_priority(int prio)
-{
- if (prio > I915_PRIORITY_NORMAL)
- return GEN12_CTX_PRIORITY_HIGH;
- else if (prio < I915_PRIORITY_NORMAL)
- return GEN12_CTX_PRIORITY_LOW;
- else
- return GEN12_CTX_PRIORITY_NORMAL;
-}
-
static inline void lrc_runtime_start(struct intel_context *ce)
{
struct intel_context_stats *stats = >stats;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 75291e9846c50..8bf8b6d588d43 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2394,6 +2394,26 @@ static int guc_context_policy_init(struct
intel_context *ce, bool loop)
return ret;
}
+static u32 map_guc_prio_to_lrc_desc_prio(u8 prio)
+{
+ /*
+ * this matches the mapping we do in map_i915_prio_to_guc_prio()
+ * (e.g. prio < I915_PRIORITY_NORMAL maps to
GUC_CLIENT_PRIORITY_NORMAL)
+ */
+ switch (prio) {
+ default:
+ MISSING_CASE(prio);
+ fallthrough;
+ case GUC_CLIENT_PRIORITY_KMD_NORMAL:
+ return GEN12_CTX_PRIORITY_NORMAL;
+ case GUC_CLIENT_PRIORITY_NORMAL:
+ return GEN12_CTX_PRIORITY_LOW;
+ case GUC_CLIENT_PRIORITY_HIGH:
+ case GUC_CLIENT_PRIORITY_KMD_HIGH:
+ return GEN12_CTX_PRIORITY_HIGH;
+ }
+}
+
static void prepare_context_registration_info(struct intel_context *ce,
struct guc_ctxt_registration_info *info)
{
@@ -2420,6 +2440,8 @@ static void
prepare_context_registration_info(struct intel_context *ce,
*/
info->hwlrca_lo = lower_32_bits(ce->lrc.lrca);
info->hwlrca_hi = upper_32_bits(ce->lrc.lrca);
+ if (engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
+ info->hwlrca_lo |=
map_guc_prio_to_lrc_desc_prio(ce->guc_state.prio);
info->flags = CONTEXT_REGISTRATION_FLAG_KMD;
/*
