[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/doc/rfc: i915 VM_BIND feature design + uapi

[Patchwork]

== Series Details ==

Series: drm/doc/rfc: i915 VM_BIND feature design + uapi
URL   : https://patchwork.freedesktop.org/series/105267/
State : failure

== Summary ==

Error: make failed
  CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  DESCEND objtool
  CHK include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/i915_driver.o
In file included from ./drivers/gpu/drm/i915/i915_pmu.h:13,
 from ./drivers/gpu/drm/i915/gt/intel_engine_types.h:21,
 from ./drivers/gpu/drm/i915/gt/intel_context_types.h:18,
 from ./drivers/gpu/drm/i915/gem/i915_gem_context_types.h:20,
 from ./drivers/gpu/drm/i915/i915_request.h:34,
 from ./drivers/gpu/drm/i915/i915_active.h:13,
 from ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h:12,
 from ./drivers/gpu/drm/i915/i915_vma.h:33,
 from drivers/gpu/drm/i915/display/intel_display_types.h:48,
 from drivers/gpu/drm/i915/i915_driver.c:52:
./include/uapi/drm/i915_drm.h:1934:2: error: "/*" within comment 
[-Werror=comment]
  /** @param: Parameter to set or query */
   
cc1: all warnings being treated as errors
scripts/Makefile.build:249: recipe for target 
'drivers/gpu/drm/i915/i915_driver.o' failed
make[4]: *** [drivers/gpu/drm/i915/i915_driver.o] Error 1
scripts/Makefile.build:466: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:466: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:466: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1843: recipe for target 'drivers' failed
make: *** [drivers] Error 2

[Intel-gfx] [PATCH v2 3/3] drm/doc/rfc: VM_BIND uapi definition

[Niranjana Vishwanathapura]

VM_BIND and related uapi definitions

v2: Reduce the scope to simple Mesa use case.

Signed-off-by: Niranjana Vishwanathapura 
---
 Documentation/gpu/rfc/i915_vm_bind.h | 226 +++
 1 file changed, 226 insertions(+)
 create mode 100644 Documentation/gpu/rfc/i915_vm_bind.h

diff --git a/Documentation/gpu/rfc/i915_vm_bind.h 
b/Documentation/gpu/rfc/i915_vm_bind.h
new file mode 100644
index ..b7540ddb526d
--- /dev/null
+++ b/Documentation/gpu/rfc/i915_vm_bind.h
@@ -0,0 +1,226 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+/**
+ * DOC: I915_PARAM_HAS_VM_BIND
+ *
+ * VM_BIND feature availability.
+ * See typedef drm_i915_getparam_t param.
+ */
+#define I915_PARAM_HAS_VM_BIND 57
+
+/**
+ * DOC: I915_VM_CREATE_FLAGS_USE_VM_BIND
+ *
+ * Flag to opt-in for VM_BIND mode of binding during VM creation.
+ * See struct drm_i915_gem_vm_control flags.
+ *
+ * The older execbuf2 ioctl will not support VM_BIND mode of operation.
+ * For VM_BIND mode, we have new execbuf3 ioctl which will not accept any
+ * execlist (See struct drm_i915_gem_execbuffer3 for more details).
+ *
+ */
+#define I915_VM_CREATE_FLAGS_USE_VM_BIND   (1 << 0)
+
+/* VM_BIND related ioctls */
+#define DRM_I915_GEM_VM_BIND   0x3d
+#define DRM_I915_GEM_VM_UNBIND 0x3e
+#define DRM_I915_GEM_EXECBUFFER3   0x3f
+
+#define DRM_IOCTL_I915_GEM_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + 
DRM_I915_GEM_VM_BIND, struct drm_i915_gem_vm_bind)
+#define DRM_IOCTL_I915_GEM_VM_UNBIND   DRM_IOWR(DRM_COMMAND_BASE + 
DRM_I915_GEM_VM_UNBIND, struct drm_i915_gem_vm_bind)
+#define DRM_IOCTL_I915_GEM_EXECBUFFER3 DRM_IOWR(DRM_COMMAND_BASE + 
DRM_I915_GEM_EXECBUFFER3, struct drm_i915_gem_execbuffer3)
+
+/**
+ * struct drm_i915_gem_vm_bind_fence - Bind/unbind completion notification.
+ *
+ * A timeline out fence for vm_bind/unbind completion notification.
+ */
+struct drm_i915_gem_vm_bind_fence {
+   /** @handle: User's handle for a drm_syncobj to signal. */
+   __u32 handle;
+
+   /** @rsvd: Reserved, MBZ */
+   __u32 rsvd;
+
+   /**
+* @value: A point in the timeline.
+* Value must be 0 for a binary drm_syncobj. A Value of 0 for a
+* timeline drm_syncobj is invalid as it turns a drm_syncobj into a
+* binary one.
+*/
+   __u64 value;
+};
+
+/**
+ * struct drm_i915_gem_vm_bind - VA to object mapping to bind.
+ *
+ * This structure is passed to VM_BIND ioctl and specifies the mapping of GPU
+ * virtual address (VA) range to the section of an object that should be bound
+ * in the device page table of the specified address space (VM).
+ * The VA range specified must be unique (ie., not currently bound) and can
+ * be mapped to whole object or a section of the object (partial binding).
+ * Multiple VA mappings can be created to the same section of the object
+ * (aliasing).
+ *
+ * The @start, @offset and @length should be 4K page aligned. However the DG2
+ * and XEHPSDV has 64K page size for device local-memory and has compact page
+ * table. On those platforms, for binding device local-memory objects, the
+ * @start should be 2M aligned, @offset and @length should be 64K aligned.
+ * Also, on those platforms, it is not allowed to bind an device local-memory
+ * object and a system memory object in a single 2M section of VA range.
+ */
+struct drm_i915_gem_vm_bind {
+   /** @vm_id: VM (address space) id to bind */
+   __u32 vm_id;
+
+   /** @handle: Object handle */
+   __u32 handle;
+
+   /** @start: Virtual Address start to bind */
+   __u64 start;
+
+   /** @offset: Offset in object to bind */
+   __u64 offset;
+
+   /** @length: Length of mapping to bind */
+   __u64 length;
+
+   /**
+* @flags: Supported flags are:
+*
+* I915_GEM_VM_BIND_READONLY:
+* Mapping is read-only.
+*
+* I915_GEM_VM_BIND_CAPTURE:
+* Capture this mapping in the dump upon GPU error.
+*/
+   __u64 flags;
+#define I915_GEM_VM_BIND_READONLY(1 << 0)
+#define I915_GEM_VM_BIND_CAPTURE (1 << 1)
+
+   /** @fence: Timeline fence for bind completion signaling */
+   struct drm_i915_gem_vm_bind_fence fence;
+
+   /** @extensions: 0-terminated chain of extensions */
+   __u64 extensions;
+};
+
+/**
+ * struct drm_i915_gem_vm_unbind - VA to object mapping to unbind.
+ *
+ * This structure is passed to VM_UNBIND ioctl and specifies the GPU virtual
+ * address (VA) range that should be unbound from the device page table of the
+ * specified address space (VM). The specified VA range must match one of the
+ * mappings created with the VM_BIND ioctl. TLB is flushed upon unbind
+ * completion.
+ *
+ * The @start and @length musy specify a unique mapping bound with VM_BIND
+ * ioctl.
+ */
+struct drm_i915_gem_vm_unbind {
+   /** @vm_id: VM (address space) id to bind */
+   __u32 vm_id;
+
+  

[Intel-gfx] [PATCH v2 2/3] drm/i915: Update i915 uapi documentation

[Niranjana Vishwanathapura]

Add some missing i915 upai documentation which the new
i915 VM_BIND feature documentation will be refer to.

Signed-off-by: Niranjana Vishwanathapura 
Reviewed-by: Matthew Auld 
---
 include/uapi/drm/i915_drm.h | 205 
 1 file changed, 160 insertions(+), 45 deletions(-)

diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index de49b68b4fc8..f5ce34d447b1 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -751,14 +751,27 @@ typedef struct drm_i915_irq_wait {
 
 /* Must be kept compact -- no holes and well documented */
 
-typedef struct drm_i915_getparam {
+/**
+ * struct drm_i915_getparam - Driver parameter query structure.
+ */
+struct drm_i915_getparam {
+   /** @param: Driver parameter to query. */
__s32 param;
-   /*
+
+   /**
+* @value: Address of memory where queried value should be put.
+*
 * WARNING: Using pointers instead of fixed-size u64 means we need to 
write
 * compat32 code. Don't repeat this mistake.
 */
int __user *value;
-} drm_i915_getparam_t;
+};
+
+/**
+ * typedef drm_i915_getparam_t - Driver parameter query structure.
+ * See struct drm_i915_getparam.
+ */
+typedef struct drm_i915_getparam drm_i915_getparam_t;
 
 /* Ioctl to set kernel params:
  */
@@ -1239,76 +1252,119 @@ struct drm_i915_gem_exec_object2 {
__u64 rsvd2;
 };
 
+/**
+ * struct drm_i915_gem_exec_fence - An input or output fence for the execbuf
+ * ioctl.
+ *
+ * The request will wait for input fence to signal before submission.
+ *
+ * The returned output fence will be signaled after the completion of the
+ * request.
+ */
 struct drm_i915_gem_exec_fence {
-   /**
-* User's handle for a drm_syncobj to wait on or signal.
-*/
+   /** @handle: User's handle for a drm_syncobj to wait on or signal. */
__u32 handle;
 
+   /**
+* @flags: Supported flags are:
+*
+* I915_EXEC_FENCE_WAIT:
+* Wait for the input fence before request submission.
+*
+* I915_EXEC_FENCE_SIGNAL:
+* Return request completion fence as output
+*/
+   __u32 flags;
 #define I915_EXEC_FENCE_WAIT(1<<0)
 #define I915_EXEC_FENCE_SIGNAL  (1<<1)
 #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
-   __u32 flags;
 };
 
-/*
- * See drm_i915_gem_execbuffer_ext_timeline_fences.
- */
-#define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
-
-/*
+/**
+ * struct drm_i915_gem_execbuffer_ext_timeline_fences - Timeline fences
+ * for execbuf ioctl.
+ *
  * This structure describes an array of drm_syncobj and associated points for
  * timeline variants of drm_syncobj. It is invalid to append this structure to
  * the execbuf if I915_EXEC_FENCE_ARRAY is set.
  */
 struct drm_i915_gem_execbuffer_ext_timeline_fences {
+#define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
+   /** @base: Extension link. See struct i915_user_extension. */
struct i915_user_extension base;
 
/**
-* Number of element in the handles_ptr & value_ptr arrays.
+* @fence_count: Number of elements in the @handles_ptr & @value_ptr
+* arrays.
 */
__u64 fence_count;
 
/**
-* Pointer to an array of struct drm_i915_gem_exec_fence of length
-* fence_count.
+* @handles_ptr: Pointer to an array of struct drm_i915_gem_exec_fence
+* of length @fence_count.
 */
__u64 handles_ptr;
 
/**
-* Pointer to an array of u64 values of length fence_count. Values
-* must be 0 for a binary drm_syncobj. A Value of 0 for a timeline
-* drm_syncobj is invalid as it turns a drm_syncobj into a binary one.
+* @values_ptr: Pointer to an array of u64 values of length
+* @fence_count.
+* Values must be 0 for a binary drm_syncobj. A Value of 0 for a
+* timeline drm_syncobj is invalid as it turns a drm_syncobj into a
+* binary one.
 */
__u64 values_ptr;
 };
 
+/**
+ * struct drm_i915_gem_execbuffer2 - Structure for DRM_I915_GEM_EXECBUFFER2
+ * ioctl.
+ */
 struct drm_i915_gem_execbuffer2 {
-   /**
-* List of gem_exec_object2 structs
-*/
+   /** @buffers_ptr: Pointer to a list of gem_exec_object2 structs */
__u64 buffers_ptr;
+
+   /** @buffer_count: Number of elements in @buffers_ptr array */
__u32 buffer_count;
 
-   /** Offset in the batchbuffer to start execution from. */
+   /**
+* @batch_start_offset: Offset in the batchbuffer to start execution
+* from.
+*/
__u32 batch_start_offset;
-   /** Bytes used in batchbuffer from batch_start_offset */
+
+   /**
+* @batch_len: Length in bytes of the batch buffer, starting from the
+* @batch_start_offset. If 0, length is assumed to be the batch buffer
+* object size.
+*/
   

[Intel-gfx] [PATCH v2 1/3] drm/doc/rfc: VM_BIND feature design document

[Niranjana Vishwanathapura]

VM_BIND design document with description of intended use cases.

v2: Reduce the scope to simple Mesa use case.

Signed-off-by: Niranjana Vishwanathapura 
---
 Documentation/gpu/rfc/i915_vm_bind.rst | 238 +
 Documentation/gpu/rfc/index.rst|   4 +
 2 files changed, 242 insertions(+)
 create mode 100644 Documentation/gpu/rfc/i915_vm_bind.rst

diff --git a/Documentation/gpu/rfc/i915_vm_bind.rst 
b/Documentation/gpu/rfc/i915_vm_bind.rst
new file mode 100644
index ..4ab590ef11fd
--- /dev/null
+++ b/Documentation/gpu/rfc/i915_vm_bind.rst
@@ -0,0 +1,238 @@
+==
+I915 VM_BIND feature design and use cases
+==
+
+VM_BIND feature
+
+DRM_I915_GEM_VM_BIND/UNBIND ioctls allows UMD to bind/unbind GEM buffer
+objects (BOs) or sections of a BOs at specified GPU virtual addresses on a
+specified address space (VM). These mappings (also referred to as persistent
+mappings) will be persistent across multiple GPU submissions (execbuf calls)
+issued by the UMD, without user having to provide a list of all required
+mappings during each submission (as required by older execbuf mode).
+
+The VM_BIND/UNBIND calls allow UMDs to request a timeline fence for signaling
+the completion of bind/unbind operation.
+
+VM_BIND feature is advertised to user via I915_PARAM_HAS_VM_BIND.
+User has to opt-in for VM_BIND mode of binding for an address space (VM)
+during VM creation time via I915_VM_CREATE_FLAGS_USE_VM_BIND extension.
+
+Normally, vm_bind/unbind operations will get completed synchronously,
+but if the object is being moved, the binding will happen once that the
+moving is complete and out fence will be signaled after binding is complete.
+The bind/unbind operation can get completed out of submission order.
+
+VM_BIND features include:
+
+* Multiple Virtual Address (VA) mappings can map to the same physical pages
+  of an object (aliasing).
+* VA mapping can map to a partial section of the BO (partial binding).
+* Support capture of persistent mappings in the dump upon GPU error.
+* TLB is flushed upon unbind completion. Batching of TLB flushes in some
+  use cases will be helpful.
+* Support for userptr gem objects (no special uapi is required for this).
+
+Execbuf ioctl in VM_BIND mode
+---
+A VM in VM_BIND mode will not support older execbuf mode of binding.
+The execbuf ioctl handling in VM_BIND mode differs significantly from the
+older execbuf2 ioctl (See struct drm_i915_gem_execbuffer2).
+Hence, a new execbuf3 ioctl has been added to support VM_BIND mode. (See
+struct drm_i915_gem_execbuffer3). The execbuf3 ioctl will not accept any
+execlist. Hence, no support for implicit sync. It is expected that the below
+work will be able to support requirements of object dependency setting in all
+use cases:
+
+"dma-buf: Add an API for exporting sync files"
+(https://lwn.net/Articles/859290/)
+
+The execbuf3 ioctl directly specifies the batch addresses instead of as
+object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not
+support many of the older features like in/out/submit fences, fence array,
+default gem context and many more (See struct drm_i915_gem_execbuffer3).
+
+In VM_BIND mode, VA allocation is completely managed by the user instead of
+the i915 driver. Hence all VA assignment, eviction are not applicable in
+VM_BIND mode. Also, for determining object activeness, VM_BIND mode will not
+be using the i915_vma active reference tracking. It will instead use dma-resv
+object for that (See `VM_BIND dma_resv usage`_).
+
+So, a lot of existing code supporting execbuf2 ioctl, like relocations, VA
+evictions, vma lookup table, implicit sync, vma active reference tracking etc.,
+are not applicable for execbuf3 ioctl. Hence, all execbuf3 specific handling
+should be in a separate file and only functionalities common to these ioctls
+can be the shared code where possible.
+
+VM_PRIVATE objects
+---
+By default, BOs can be mapped on multiple VMs and can also be dma-buf
+exported. Hence these BOs are referred to as Shared BOs.
+During each execbuf submission, the request fence must be added to the
+dma-resv fence list of all shared BOs mapped on the VM.
+
+VM_BIND feature introduces an optimization where user can create BO which
+is private to a specified VM via I915_GEM_CREATE_EXT_VM_PRIVATE flag during
+BO creation. Unlike Shared BOs, these VM private BOs can only be mapped on
+the VM they are private to and can't be dma-buf exported.
+All private BOs of a VM share the dma-resv object. Hence during each execbuf
+submission, they need only one dma-resv fence list updated. Thus, the fast
+path (where required mappings are already bound) submission latency is O(1)
+w.r.t the number of VM private BOs.
+
+VM_BIND locking hirarchy
+-
+The locking design here supports the older (execlist based) execbuf mode, the
+newer VM_BIND 

[Intel-gfx] [PATCH v2 0/3] drm/doc/rfc: i915 VM_BIND feature design + uapi

[Niranjana Vishwanathapura]

This is the i915 driver VM_BIND feature design RFC patch series along
with the required uapi definition and description of intended use cases.

v2: Reduce the scope to simple Mesa use case.
Remove all compute related uapi, vm_bind/unbind queue support and
only support a timeline out fence instead of an in/out timeline
fence array.

Signed-off-by: Niranjana Vishwanathapura 

Niranjana Vishwanathapura (3):
  drm/doc/rfc: VM_BIND feature design document
  drm/i915: Update i915 uapi documentation
  drm/doc/rfc: VM_BIND uapi definition

 Documentation/gpu/rfc/i915_vm_bind.h   | 226 +++
 Documentation/gpu/rfc/i915_vm_bind.rst | 238 +
 Documentation/gpu/rfc/index.rst|   4 +
 include/uapi/drm/i915_drm.h| 205 -
 4 files changed, 628 insertions(+), 45 deletions(-)
 create mode 100644 Documentation/gpu/rfc/i915_vm_bind.h
 create mode 100644 Documentation/gpu/rfc/i915_vm_bind.rst

-- 
2.21.0.rc0.32.g243a4c7e27

Re: [Intel-gfx] [PATCH 0/3] drm/doc/rfc: i915 VM_BIND feature design + uapi

[Niranjana Vishwanathapura]

On Fri, Jun 10, 2022 at 12:07:08AM -0700, Niranjana Vishwanathapura wrote:

This is the i915 driver VM_BIND feature design RFC patch series along
with the required uapi definition and description of intended use cases.



Some of us had an offline dicussion on this.
Based on that,

1) The scope of this work (VM_BIND support in i915) will reduced to
  support simple Mesa use case. So, I will remove all compute related
  uapi for now.
2) VM_BIND/UNBIND will only support an 'out' fence. ie., it won't
  support 'in' fences and hence no timeline fence array as well.
  UMDs are expected to handle any 'in' fence requirement.
3) We will not support any VM_BIND/UNBIND queues. The binding and
  unbinding operations can get completed out of submission order.
  Normally, they will get completed synchronously, but if the object
  is being moved, the binding will happen once that is complete
  and out fence will be signaled after binding is complete.
4) We will still have execbuf3 for VM_BIND mode.

I will update the patch series and send out.

Thanks,
Niranjana


This series is an updated version of the below RFC series. It address
the review feedback by adding execbuf3 ioctl for vm_bind, adding
multiple queues support for vm_bind/unbind ioctls and some formatting
and documentation updates.
https://www.spinics.net/lists/dri-devel/msg347731.html

Signed-off-by: Niranjana Vishwanathapura 

Niranjana Vishwanathapura (3):
 drm/doc/rfc: VM_BIND feature design document
 drm/i915: Update i915 uapi documentation
 drm/doc/rfc: VM_BIND uapi definition

Documentation/driver-api/dma-buf.rst   |   2 +
Documentation/gpu/rfc/i915_vm_bind.h   | 490 +
Documentation/gpu/rfc/i915_vm_bind.rst | 309 
Documentation/gpu/rfc/index.rst|   4 +
include/uapi/drm/i915_drm.h| 203 +++---
5 files changed, 963 insertions(+), 45 deletions(-)
create mode 100644 Documentation/gpu/rfc/i915_vm_bind.h
create mode 100644 Documentation/gpu/rfc/i915_vm_bind.rst

--
2.21.0.rc0.32.g243a4c7e27

Re: [Intel-gfx] [PATCH] drm/i915/guc: Check for ct enabled while waiting for response

[Dixit, Ashutosh]

On Thu, 16 Jun 2022 15:01:59 -0700, Zhanjun Dong wrote:
>
> We are seeing error message of "No response for request". Some cases
> happened while waiting for response and reset/suspend action was triggered.
> In this case, no response is not an error, active requests will be
> cancelled.
>
> This patch will handle this condition and change the error message into
> debug message.
>
> Signed-off-by: Zhanjun Dong 
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 24 ---
>  1 file changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index f01325cd1b62..f07a7666b1ad 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -455,6 +455,7 @@ static int ct_write(struct intel_guc_ct *ct,
>
>  /**
>   * wait_for_ct_request_update - Wait for CT request state update.
> + * @ct:  pointer to CT
>   * @req: pointer to pending request
>   * @status:  placeholder for status
>   *
> @@ -467,9 +468,10 @@ static int ct_write(struct intel_guc_ct *ct,
>   * * 0 response received (status is valid)
>   * * -ETIMEDOUT no response within hardcoded timeout
>   */
> -static int wait_for_ct_request_update(struct ct_request *req, u32 *status)
> +static int wait_for_ct_request_update(struct intel_guc_ct *ct, struct 
> ct_request *req, u32 *status)
>  {
>   int err;
> + bool ct_enabled;
>
>   /*
>* Fast commands should complete in less than 10us, so sample quickly
> @@ -481,12 +483,15 @@ static int wait_for_ct_request_update(struct ct_request 
> *req, u32 *status)
>  #define GUC_CTB_RESPONSE_TIMEOUT_SHORT_MS 10
>  #define GUC_CTB_RESPONSE_TIMEOUT_LONG_MS 1000
>  #define done \
> - (FIELD_GET(GUC_HXG_MSG_0_ORIGIN, READ_ONCE(req->status)) == \
> + (!(ct_enabled = intel_guc_ct_enabled(ct)) || \
> +  FIELD_GET(GUC_HXG_MSG_0_ORIGIN, READ_ONCE(req->status)) == \
>GUC_HXG_ORIGIN_GUC)
>   err = wait_for_us(done, GUC_CTB_RESPONSE_TIMEOUT_SHORT_MS);
>   if (err)
>   err = wait_for(done, GUC_CTB_RESPONSE_TIMEOUT_LONG_MS);
>  #undef done
> + if (!ct_enabled)
> + err = -ECANCELED;

Actually here's an even simpler suggestion. We could just do:

if (!ct_enabled)
CT_DEBUG(ct, "Request %#x (fence %u) cancelled as CTB is 
disabled\n", ...);

And return 0 as before. This way we won't have to make any changes in
either ct_send() or intel_guc_ct_send(). So intel_guc_ct_enabled() just
serves to get us out of the wait early and prevent the -ETIMEDOUT return
(and 0 return avoids all the error messages we are trying to eliminate).

Re: [Intel-gfx] [PATCH] drm/i915/guc: Check for ct enabled while waiting for response

[Dixit, Ashutosh]

On Thu, 16 Jun 2022 15:01:59 -0700, Zhanjun Dong wrote:
>
> We are seeing error message of "No response for request". Some cases
> happened while waiting for response and reset/suspend action was triggered.
> In this case, no response is not an error, active requests will be
> cancelled.
>
> This patch will handle this condition and change the error message into
> debug message.

The convention we follow in drm is to record the version of the patch and
what changed in that version.

Generally I am ok with this version of the patch but still have a couple of
questions.

> -static int wait_for_ct_request_update(struct ct_request *req, u32 *status)
> +static int wait_for_ct_request_update(struct intel_guc_ct *ct, struct 
> ct_request *req, u32 *status)
>  {
>   int err;
> + bool ct_enabled;
>
>   /*
>* Fast commands should complete in less than 10us, so sample quickly
> @@ -481,12 +483,15 @@ static int wait_for_ct_request_update(struct ct_request 
> *req, u32 *status)
>  #define GUC_CTB_RESPONSE_TIMEOUT_SHORT_MS 10
>  #define GUC_CTB_RESPONSE_TIMEOUT_LONG_MS 1000
>  #define done \
> - (FIELD_GET(GUC_HXG_MSG_0_ORIGIN, READ_ONCE(req->status)) == \
> + (!(ct_enabled = intel_guc_ct_enabled(ct)) || \
> +  FIELD_GET(GUC_HXG_MSG_0_ORIGIN, READ_ONCE(req->status)) == \
>GUC_HXG_ORIGIN_GUC)
>   err = wait_for_us(done, GUC_CTB_RESPONSE_TIMEOUT_SHORT_MS);
>   if (err)
>   err = wait_for(done, GUC_CTB_RESPONSE_TIMEOUT_LONG_MS);
>  #undef done
> + if (!ct_enabled)
> + err = -ECANCELED;

So we have the choice of either setting the request status here as I was
suggesting earlier, e.g. as follows:

#define   GUC_HXG_TYPE_REQUEST_CANCELED4u // unused value

if (!ct_enabled)
req->status = GUC_HXG_TYPE_REQUEST_CANCELED;

We would return 0 in this case and would check for the req->status value
above where needed.

Or we can return -ECANCELED. I don't know if -ECANCELED is the right value
to return but whatever we return will have to be unique (ununsed elsewhere)
since we are relying on the return value. -ECANCELED is unique so that part
is ok.

Do other reviewers have a preference whether we should set req->status or
return a unique return value?

>   *status = req->status;
>   return err;
> @@ -703,11 +708,15 @@ static int ct_send(struct intel_guc_ct *ct,
>
>   intel_guc_notify(ct_to_guc(ct));
>
> - err = wait_for_ct_request_update(, status);
> + err = wait_for_ct_request_update(ct, , status);
>   g2h_release_space(ct, GUC_CTB_HXG_MSG_MAX_LEN);
>   if (unlikely(err)) {
> - CT_ERROR(ct, "No response for request %#x (fence %u)\n",
> -  action[0], request.fence);
> + if (err == -ECANCELED)
> + CT_DEBUG(ct, "Request %#x (fence %u) cancelled as CTB 
> is disabled\n",
> +  action[0], request.fence);
> + else
> + CT_ERROR(ct, "No response for request %#x (fence %u)\n",
> +  action[0], request.fence);
>   goto unlink;
>   }
>
> @@ -771,8 +780,9 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 
> *action, u32 len,
>
>   ret = ct_send(ct, action, len, response_buf, response_buf_size, 
> );
>   if (unlikely(ret < 0)) {
> - CT_ERROR(ct, "Sending action %#x failed (%pe) status=%#X\n",
> -  action[0], ERR_PTR(ret), status);
> + if (ret != -ECANCELED)
> + CT_ERROR(ct, "Sending action %#x failed (%pe) 
> status=%#X\n",
> +  action[0], ERR_PTR(ret), status);

I am wondering why we even have this print and should we just delete it or
convert it to CT_DEBUG(). The reason is that only error prints closest to
where the actual error occurs are useful since they pin-point the error
clearly. This to be seems to be a "second" print from a higher level
function which does not seem particularly useful.


>   } else if (unlikely(ret)) {
>   CT_DEBUG(ct, "send action %#x returned %d (%#x)\n",
>action[0], ret, ret);
> --
> 2.36.0
>

[Intel-gfx] ✓ Fi.CI.IGT: success for Add support for LMEM PCIe resizable bar

[Patchwork]

== Series Details ==

Series: Add support for LMEM PCIe resizable bar
URL   : https://patchwork.freedesktop.org/series/105231/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11769_full -> Patchwork_105231v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_105231v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ccs@ctrl-surf-copy:
- shard-iclb: NOTRUN -> [SKIP][1] ([i915#5327])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb1/igt@gem_...@ctrl-surf-copy.html

  * igt@gem_create@create-massive:
- shard-skl:  NOTRUN -> [DMESG-WARN][2] ([i915#4991])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl4/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_persistence@hang:
- shard-skl:  NOTRUN -> [SKIP][3] ([fdo#109271]) +314 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl7/igt@gem_ctx_persiste...@hang.html

  * igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2410])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-tglb7/igt@gem_ctx_persiste...@many-contexts.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html

  * igt@gem_eio@in-flight-suspend:
- shard-kbl:  [PASS][6] -> [DMESG-WARN][7] ([i915#180])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-kbl1/igt@gem_...@in-flight-suspend.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-kbl4/igt@gem_...@in-flight-suspend.html

  * igt@gem_eio@kms:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#5784])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-tglb6/igt@gem_...@kms.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb2/igt@gem_...@kms.html

  * igt@gem_exec_balancer@parallel-ordering:
- shard-kbl:  NOTRUN -> [FAIL][10] ([i915#6117])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-kbl7/igt@gem_exec_balan...@parallel-ordering.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-iclb6/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl6/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842]) +1 similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2842])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-tglb8/igt@gem_exec_fair@basic-p...@vcs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb6/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_whisper@basic-queues-priority-all:
- shard-iclb: [PASS][18] -> [INCOMPLETE][19] ([i915#5498])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-iclb4/igt@gem_exec_whis...@basic-queues-priority-all.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb1/igt@gem_exec_whis...@basic-queues-priority-all.html

  * igt@gem_huc_copy@huc-copy:
- shard-skl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#2190])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl7/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-glk:  NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-glk6/igt@gem_lmem_swapp...@heavy-verify-multi-ccs.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-kbl:  NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4613])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-kbl7/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@verify-ccs:
- shard-skl:  NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [23]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] agp/intel: Rename intel-gtt symbols

[Patchwork]

== Series Details ==

Series: series starting with [1/2] agp/intel: Rename intel-gtt symbols
URL   : https://patchwork.freedesktop.org/series/105261/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11773 -> Patchwork_105261v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105261v1/index.html

Participating hosts (35 -> 32)
--

  Missing(3): fi-bdw-samus fi-snb-2520m fi-pnv-d510 

Known issues


  Here are the changes found in Patchwork_105261v1 that come from known issues:

### IGT changes ###

 Possible fixes 

  * igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050:   [DMESG-FAIL][1] ([i915#2373]) -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105261v1/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html

  
  [i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373


Build changes
-

  * Linux: CI_DRM_11773 -> Patchwork_105261v1

  CI-20190529: 20190529
  CI_DRM_11773: 8025a295b7aa707f64c7984b7781c6f25e22a901 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6533: 6b5107d91827962808441db6b98e478aa9e67bdb @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_105261v1: 8025a295b7aa707f64c7984b7781c6f25e22a901 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

0ccd88c50693 drm/i915/gt: Re-do the intel-gtt split
8a9df0f87182 agp/intel: Rename intel-gtt symbols

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105261v1/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] agp/intel: Rename intel-gtt symbols

[Patchwork]

== Series Details ==

Series: series starting with [1/2] agp/intel: Rename intel-gtt symbols
URL   : https://patchwork.freedesktop.org/series/105261/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] agp/intel: Rename intel-gtt symbols

[Patchwork]

== Series Details ==

Series: series starting with [1/2] agp/intel: Rename intel-gtt symbols
URL   : https://patchwork.freedesktop.org/series/105261/
State : warning

== Summary ==

Error: dim checkpatch failed
e1bbe8530903 agp/intel: Rename intel-gtt symbols
deae3fe392d9 drm/i915/gt: Re-do the intel-gtt split
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:661: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#661: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 856 lines checked

[Intel-gfx] ✓ Fi.CI.BAT: success for i915/pmu: Wire GuC backend to per-client busyness (rev3)

[Patchwork]

== Series Details ==

Series: i915/pmu: Wire GuC backend to per-client busyness (rev3)
URL   : https://patchwork.freedesktop.org/series/105085/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11773 -> Patchwork_105085v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v3/index.html

Participating hosts (35 -> 33)
--

  Missing(2): fi-rkl-11600 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105085v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@gem:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][1] ([i915#4528])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v3/fi-pnv-d510/igt@i915_selftest@l...@gem.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- fi-tgl-u2:  [PASS][2] -> [DMESG-WARN][3] ([i915#402])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v3/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050:   [DMESG-FAIL][4] ([i915#2373]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v3/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][6] ([i915#4528]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v3/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- fi-tgl-u2:  [DMESG-WARN][8] ([i915#402]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v3/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  
  [i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528


Build changes
-

  * Linux: CI_DRM_11773 -> Patchwork_105085v3

  CI-20190529: 20190529
  CI_DRM_11773: 8025a295b7aa707f64c7984b7781c6f25e22a901 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6533: 6b5107d91827962808441db6b98e478aa9e67bdb @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_105085v3: 8025a295b7aa707f64c7984b7781c6f25e22a901 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

753bc34ac867 i915/pmu: Wire GuC backend to per-client busyness

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v3/index.html

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/fdinfo: Don't show engine classes not present

[Patchwork]

== Series Details ==

Series: drm/i915/fdinfo: Don't show engine classes not present
URL   : https://patchwork.freedesktop.org/series/105228/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11768_full -> Patchwork_105228v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 10)
--

  Missing(2): shard-rkl shard-tglu 

Known issues


  Here are the changes found in Patchwork_105228v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-apl:  NOTRUN -> [DMESG-WARN][1] ([i915#180])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/shard-apl6/igt@gem_ctx_isolation@preservation...@vecs0.html

  * igt@gem_eio@in-flight-contexts-1us:
- shard-tglb: [PASS][2] -> [TIMEOUT][3] ([i915#3063])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-tglb3/igt@gem_...@in-flight-contexts-1us.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/shard-tglb2/igt@gem_...@in-flight-contexts-1us.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#5784])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-tglb7/igt@gem_...@unwedge-stress.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/shard-tglb1/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [PASS][6] -> [SKIP][7] ([i915#4525])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb4/igt@gem_exec_balan...@parallel-keep-submit-fence.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/shard-iclb3/igt@gem_exec_balan...@parallel-keep-submit-fence.html

  * igt@gem_exec_balancer@parallel-ordering:
- shard-kbl:  NOTRUN -> [FAIL][8] ([i915#6117])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/shard-kbl6/igt@gem_exec_balan...@parallel-ordering.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html
- shard-apl:  [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-apl3/igt@gem_exec_fair@basic-n...@vcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/shard-apl3/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][13] ([fdo#109283])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/shard-iclb1/igt@gem_exec_par...@no-vebox.html

  * igt@gem_lmem_swapping@basic:
- shard-apl:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/shard-apl1/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-skl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/shard-skl7/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/shard-kbl6/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#4613])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/shard-iclb1/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html

  * igt@gem_render_copy@y-tiled-to-vebox-yf-tiled:
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#768])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/shard-iclb1/igt@gem_render_c...@y-tiled-to-vebox-yf-tiled.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-skl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3323])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/shard-skl7/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gem_workarounds@suspend-resume-fd:
- shard-kbl:  [PASS][20] -> [DMESG-WARN][21] ([i915#180]) +2 
similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-kbl6/igt@gem_workarou...@suspend-resume-fd.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/shard-kbl4/igt@gem_workarou...@suspend-resume-fd.html

  * igt@gen9_exec_parse@allowed-single:
- shard-glk:  [PASS][22] -> [DMESG-WARN][23] ([i915#5566] / 
[i915#716])
 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915/pmu: Wire GuC backend to per-client busyness (rev3)

[Patchwork]

== Series Details ==

Series: i915/pmu: Wire GuC backend to per-client busyness (rev3)
URL   : https://patchwork.freedesktop.org/series/105085/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Check for ct enabled while waiting for response

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Check for ct enabled while waiting for response
URL   : https://patchwork.freedesktop.org/series/105258/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11773 -> Patchwork_105258v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/index.html

Participating hosts (35 -> 34)
--

  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105258v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@gem:
- fi-blb-e6850:   NOTRUN -> [DMESG-FAIL][1] ([i915#4528])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/fi-blb-e6850/igt@i915_selftest@l...@gem.html
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][2] ([i915#4528])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/fi-pnv-d510/igt@i915_selftest@l...@gem.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- fi-tgl-u2:  [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar 
issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050:   [DMESG-FAIL][5] ([i915#2373]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [DMESG-FAIL][7] ([i915#4528]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html
- fi-pnv-d510:[DMESG-FAIL][9] ([i915#4528]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- fi-tgl-u2:  [DMESG-WARN][11] ([i915#402]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  
  [i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528


Build changes
-

  * Linux: CI_DRM_11773 -> Patchwork_105258v1

  CI-20190529: 20190529
  CI_DRM_11773: 8025a295b7aa707f64c7984b7781c6f25e22a901 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6533: 6b5107d91827962808441db6b98e478aa9e67bdb @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_105258v1: 8025a295b7aa707f64c7984b7781c6f25e22a901 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

746f27f6bf8f drm/i915/guc: Check for ct enabled while waiting for response

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/index.html

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/glk: ECS Liva Q2 needs GLK HDMI port timing quirk

[Patchwork]

== Series Details ==

Series: drm/i915/glk: ECS Liva Q2 needs GLK HDMI port timing quirk
URL   : https://patchwork.freedesktop.org/series/105226/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11768_full -> Patchwork_105226v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_105226v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_105226v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 10)
--

  Missing(2): shard-rkl shard-tglu 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105226v1_full:

### Piglit changes ###

 Possible regressions 

  * spec@glsl-4.30@execution@built-in-functions@cs-op-neg-int:
- pig-kbl-iris:   NOTRUN -> [CRASH][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/pig-kbl-iris/spec@glsl-4.30@execution@built-in-functi...@cs-op-neg-int.html

  
Known issues


  Here are the changes found in Patchwork_105226v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-glk:  ([PASS][2], [PASS][3], [PASS][4], [PASS][5], 
[PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
[PASS][25], [PASS][26]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], 
[FAIL][49], [PASS][50], [PASS][51]) ([i915#4392])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk9/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk9/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk8/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk8/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk8/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk7/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk6/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk6/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk6/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk5/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk5/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk5/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk4/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk4/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk3/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk3/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk3/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk2/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk2/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk2/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk1/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk1/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/shard-glk9/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/shard-glk9/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/shard-glk9/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/shard-glk8/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/shard-glk8/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/shard-glk8/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/shard-glk7/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/shard-glk7/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/shard-glk7/boot.html
   [36]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display: Add smem fallback allocation for dpt (rev5)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/display: Add smem fallback 
allocation for dpt (rev5)
URL   : https://patchwork.freedesktop.org/series/104983/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11772 -> Patchwork_104983v5


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/index.html

Participating hosts (34 -> 33)
--

  Additional (1): fi-kbl-soraka 
  Missing(2): fi-rkl-11600 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_104983v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][3] ([i915#1886])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][4] -> [INCOMPLETE][5] ([i915#4785])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][6] -> [DMESG-FAIL][7] ([i915#4528])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/fi-kbl-soraka/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271]) +9 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#533])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#4312] / 
[i915#5594])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/fi-hsw-4770/igt@run...@aborted.html
- fi-pnv-d510:NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/fi-pnv-d510/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [DMESG-WARN][13] ([i915#5122]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html

  * igt@kms_busy@basic@flip:
- fi-tgl-u2:  [DMESG-WARN][15] ([i915#402]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/fi-tgl-u2/igt@kms_busy@ba...@flip.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/fi-tgl-u2/igt@kms_busy@ba...@flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#533]: 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dgfx: Disable d3cold Correctly (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dgfx: Disable d3cold Correctly (rev2)
URL   : https://patchwork.freedesktop.org/series/104770/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11768_full -> Patchwork_104770v2_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_104770v2_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_104770v2_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 10)
--

  Missing(2): shard-rkl shard-tglu 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_104770v2_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_concurrent@pipe-b:
- shard-glk:  NOTRUN -> [TIMEOUT][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/shard-glk7/igt@kms_concurr...@pipe-b.html

  * igt@perf@enable-disable:
- shard-glk:  [PASS][2] -> [TIMEOUT][3] +1 similar issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk7/igt@p...@enable-disable.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/shard-glk7/igt@p...@enable-disable.html

  
 Warnings 

  * igt@kms_chamelium@dp-crc-single:
- shard-glk:  [SKIP][4] ([fdo#109271] / [fdo#111827]) -> 
[TIMEOUT][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk7/igt@kms_chamel...@dp-crc-single.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/shard-glk7/igt@kms_chamel...@dp-crc-single.html

  
Known issues


  Here are the changes found in Patchwork_104770v2_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@in-flight-contexts-immediate:
- shard-apl:  [PASS][6] -> [TIMEOUT][7] ([i915#3063])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-apl6/igt@gem_...@in-flight-contexts-immediate.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/shard-apl4/igt@gem_...@in-flight-contexts-immediate.html

  * igt@gem_eio@in-flight-immediate:
- shard-tglb: [PASS][8] -> [TIMEOUT][9] ([i915#3063]) +1 similar 
issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-tglb3/igt@gem_...@in-flight-immediate.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/shard-tglb3/igt@gem_...@in-flight-immediate.html

  * igt@gem_eio@suspend:
- shard-skl:  [PASS][10] -> [DMESG-WARN][11] ([i915#1982])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-skl10/igt@gem_...@suspend.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/shard-skl9/igt@gem_...@suspend.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][12] -> [FAIL][13] ([i915#5784])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-tglb7/igt@gem_...@unwedge-stress.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/shard-tglb1/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][14] -> [SKIP][15] ([i915#4525])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb1/igt@gem_exec_balan...@parallel.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/shard-iclb5/igt@gem_exec_balan...@parallel.html

  * igt@gem_exec_capture@pi@vcs0:
- shard-iclb: [PASS][16] -> [INCOMPLETE][17] ([i915#3371])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb1/igt@gem_exec_capture@p...@vcs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/shard-iclb5/igt@gem_exec_capture@p...@vcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  [PASS][18] -> [FAIL][19] ([i915#2842]) +2 similar 
issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][20] -> [FAIL][21] ([i915#2842])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][22] ([fdo#109283])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/shard-iclb2/igt@gem_exec_par...@no-vebox.html

  * igt@gem_lmem_swapping@basic:
- shard-apl:  NOTRUN -> 

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Matt Roper]

On Thu, Jun 16, 2022 at 05:31:00PM +0530, Anshuman Gupta wrote:
> DG2 NB SKU need to distinguish between MBD and AIC to probe
> the VRAM Self Refresh feature support. Adding those sub platform
> accordingly.
> 
> Cc: Matt Roper 
> Signed-off-by: Anshuman Gupta 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  3 +++
>  drivers/gpu/drm/i915/intel_device_info.c | 21 +
>  drivers/gpu/drm/i915/intel_device_info.h | 11 +++
>  include/drm/i915_pciids.h| 23 ---
>  4 files changed, 47 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a5bc6a774c5a..f1f8699eedfd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
>  
>  #define IS_DG2_G10(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
>   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
>  #define IS_DG2_G11(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \
>   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
>  #define IS_DG2_G12(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
>   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
>  #define IS_ADLS_RPLS(dev_priv) \
>   IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
> b/drivers/gpu/drm/i915/intel_device_info.c
> index f0bf23726ed8..93da555adc4e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
>   INTEL_RPLP_IDS(0),
>  };
>  
> +static const u16 subplatform_g10_mb_mbd_ids[] = {
> + INTEL_DG2_G10_NB_MBD_IDS(0),
> +};
> +
> +static const u16 subplatform_g11_mb_mbd_ids[] = {
> + INTEL_DG2_G11_NB_MBD_IDS(0),
> +};
> +
> +static const u16 subplatform_g12_mb_mbd_ids[] = {
> + INTEL_DG2_G12_NB_MBD_IDS(0),
> +};

We only need a single MBD subplatform, not three new subplatforms.
Unless I'm forgetting something, a single device ID can be assigned two
two independent subplatforms at the same time.  So the decision about
whether to set the G10, G11, or G12 bit is one decision.  The decision
about whether to set the MBD bit is a completely separate decision that
doesn't care about the G10/G11/G12 stuff.

> +
>  static const u16 subplatform_g10_ids[] = {
>   INTEL_DG2_G10_IDS(0),
>   INTEL_ATS_M150_IDS(0),
> @@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct 
> drm_i915_private *i915)
>   } else if (find_devid(devid, subplatform_rpl_ids,
> ARRAY_SIZE(subplatform_rpl_ids))) {
>   mask = BIT(INTEL_SUBPLATFORM_RPL);
> + } else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
> +   ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
> + mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
> + } else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
> +   ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
> + mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
> + } else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
> +   ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
> + mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);

Assuming you consolidate MBD back down to just a single extra
subplatform, the lookup and bit setting should happen in a separate 'if'
statement (not an 'else' block).

if (find_devid(devid, subplatform_mbd_ids,
   ARRAY_SIZE(subplatform_mbd_ids)))
mask |= BIT(INTEL_SUBPLATFORM_MBD);


Matt

>   } else if (find_devid(devid, subplatform_g10_ids,
> ARRAY_SIZE(subplatform_g10_ids))) {
>   mask = BIT(INTEL_SUBPLATFORM_G10);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 08341174ee0a..c929e2d7e59c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -97,7 +97,7 @@ enum intel_platform {
>   * it is fine for the same bit to be used on multiple parent platforms.
>   */
>  
> -#define INTEL_SUBPLATFORM_BITS (3)
> +#define INTEL_SUBPLATFORM_BITS (6)
>  #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
>  
>  /* HSW/BDW/SKL/KBL/CFL */
> @@ -111,9 +111,12 @@ enum intel_platform {
>  #define INTEL_SUBPLATFORM_UY (0)
>  
>  /* DG2 */
> -#define INTEL_SUBPLATFORM_G100
> -#define INTEL_SUBPLATFORM_G111
> -#define INTEL_SUBPLATFORM_G122
> +#define INTEL_SUBPLATFORM_G10_NB_MBD 0
> +#define INTEL_SUBPLATFORM_G11_NB_MBD 1
> +#define 

[Intel-gfx] ✗ Fi.CI.IGT: failure for DG2 VRAM_SR Support (rev3)

[Patchwork]

== Series Details ==

Series: DG2 VRAM_SR Support (rev3)
URL   : https://patchwork.freedesktop.org/series/104128/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11768_full -> Patchwork_104128v3_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_104128v3_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_104128v3_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 10)
--

  Missing(2): shard-rkl shard-tglu 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_104128v3_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@execlists:
- shard-skl:  [PASS][1] -> [INCOMPLETE][2] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-skl4/igt@i915_selftest@l...@execlists.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl6/igt@i915_selftest@l...@execlists.html

  
Known issues


  Here are the changes found in Patchwork_104128v3_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@create-ext:
- shard-skl:  [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-skl10/igt@gem_...@create-ext.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl1/igt@gem_...@create-ext.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#5784])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-tglb7/igt@gem_...@unwedge-stress.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-tglb3/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#4525])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb4/igt@gem_exec_balan...@parallel-keep-submit-fence.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb6/igt@gem_exec_balan...@parallel-keep-submit-fence.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][13] ([fdo#109283])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb4/igt@gem_exec_par...@no-vebox.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][14] -> [SKIP][15] ([i915#2190])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-tglb2/igt@gem_huc_c...@huc-copy.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-tglb6/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-skl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl10/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#4613])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb4/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@verify-ccs:
- shard-kbl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@gem_lmem_swapp...@verify-ccs.html

  * igt@gem_render_copy@y-tiled-to-vebox-yf-tiled:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#768])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb4/igt@gem_render_c...@y-tiled-to-vebox-yf-tiled.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-skl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3323])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl10/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gen9_exec_parse@allowed-all:
- shard-glk:  [PASS][21] -> 

[Intel-gfx] [PATCH 1/2] agp/intel: Rename intel-gtt symbols

[Lucas De Marchi]

Exporting the symbols like intel_gtt_* creates some confusion inside
i915 that has symbols named similarly. In an attempt to isolate
platforms needing intel-gtt.ko, commit 7a5c922377b4 ("drm/i915/gt: Split
intel-gtt functions by arch") moved way too much
inside gt/intel_gt_gmch.c, even the functions that don't callout to this
module. Rename the symbols to make the separation clear.

Signed-off-by: Lucas De Marchi 
---
 drivers/char/agp/intel-gtt.c| 58 -
 drivers/gpu/drm/i915/gt/intel_gt_gmch.c | 16 +++
 include/drm/intel-gtt.h | 24 +-
 3 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 79a1b65527c2..fe7e2105e766 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -744,7 +744,7 @@ static void i830_write_entry(dma_addr_t addr, unsigned int 
entry,
writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
 }
 
-bool intel_enable_gtt(void)
+bool intel_gmch_enable_gtt(void)
 {
u8 __iomem *reg;
 
@@ -787,7 +787,7 @@ bool intel_enable_gtt(void)
 
return true;
 }
-EXPORT_SYMBOL(intel_enable_gtt);
+EXPORT_SYMBOL(intel_gmch_enable_gtt);
 
 static int i830_setup(void)
 {
@@ -821,8 +821,8 @@ static int intel_fake_agp_free_gatt_table(struct 
agp_bridge_data *bridge)
 
 static int intel_fake_agp_configure(void)
 {
-   if (!intel_enable_gtt())
-   return -EIO;
+   if (!intel_gmch_enable_gtt())
+   return -EIO;
 
intel_private.clear_fake_agp = true;
agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
@@ -844,20 +844,20 @@ static bool i830_check_flags(unsigned int flags)
return false;
 }
 
-void intel_gtt_insert_page(dma_addr_t addr,
-  unsigned int pg,
-  unsigned int flags)
+void intel_gmch_gtt_insert_page(dma_addr_t addr,
+   unsigned int pg,
+   unsigned int flags)
 {
intel_private.driver->write_entry(addr, pg, flags);
readl(intel_private.gtt + pg);
if (intel_private.driver->chipset_flush)
intel_private.driver->chipset_flush();
 }
-EXPORT_SYMBOL(intel_gtt_insert_page);
+EXPORT_SYMBOL(intel_gmch_gtt_insert_page);
 
-void intel_gtt_insert_sg_entries(struct sg_table *st,
-unsigned int pg_start,
-unsigned int flags)
+void intel_gmch_gtt_insert_sg_entries(struct sg_table *st,
+ unsigned int pg_start,
+ unsigned int flags)
 {
struct scatterlist *sg;
unsigned int len, m;
@@ -879,13 +879,13 @@ void intel_gtt_insert_sg_entries(struct sg_table *st,
if (intel_private.driver->chipset_flush)
intel_private.driver->chipset_flush();
 }
-EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
+EXPORT_SYMBOL(intel_gmch_gtt_insert_sg_entries);
 
 #if IS_ENABLED(CONFIG_AGP_INTEL)
-static void intel_gtt_insert_pages(unsigned int first_entry,
-  unsigned int num_entries,
-  struct page **pages,
-  unsigned int flags)
+static void intel_gmch_gtt_insert_pages(unsigned int first_entry,
+   unsigned int num_entries,
+   struct page **pages,
+   unsigned int flags)
 {
int i, j;
 
@@ -905,7 +905,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory 
*mem,
if (intel_private.clear_fake_agp) {
int start = intel_private.stolen_size / PAGE_SIZE;
int end = intel_private.gtt_mappable_entries;
-   intel_gtt_clear_range(start, end - start);
+   intel_gmch_gtt_clear_range(start, end - start);
intel_private.clear_fake_agp = false;
}
 
@@ -934,12 +934,12 @@ static int intel_fake_agp_insert_entries(struct 
agp_memory *mem,
if (ret != 0)
return ret;
 
-   intel_gtt_insert_sg_entries(, pg_start, type);
+   intel_gmch_gtt_insert_sg_entries(, pg_start, type);
mem->sg_list = st.sgl;
mem->num_sg = st.nents;
} else
-   intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
-  type);
+   intel_gmch_gtt_insert_pages(pg_start, mem->page_count, 
mem->pages,
+   type);
 
 out:
ret = 0;
@@ -949,7 +949,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory 
*mem,
 }
 #endif
 
-void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
+void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int 
num_entries)
 {
unsigned int i;
 
@@ -959,7 +959,7 @@ void 

[Intel-gfx] [PATCH 2/2] drm/i915/gt: Re-do the intel-gtt split

[Lucas De Marchi]

Re-do what was attempted in commit 7a5c922377b4 ("drm/i915/gt: Split
intel-gtt functions by arch"). The goal of that commit was to split the
handlers for older hardware that depend on intel-gtt.ko so i915 can
be built for non-x86 archs, after some more patches. Other archs do not
need intel-gtt.ko.

Main issue with the previous approach: it moved all the hooks, including
the gen8, which is used by all platforms gen8 and newer.  Re-do the
split moving only the handlers for gen < 6, which are the only ones
calling out to the separate module.

Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/Makefile |   2 +-
 drivers/gpu/drm/i915/gt/intel_ggtt.c  | 559 +-
 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c | 132 +
 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h |  27 +
 drivers/gpu/drm/i915/gt/intel_gt.c|   5 +-
 drivers/gpu/drm/i915/gt/intel_gt.h|   9 -
 drivers/gpu/drm/i915/gt/intel_gt_gmch.c   | 654 --
 drivers/gpu/drm/i915/gt/intel_gt_gmch.h   |  46 --
 drivers/gpu/drm/i915/gt/intel_gtt.h   |  12 +-
 9 files changed, 713 insertions(+), 733 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h
 delete mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.c
 delete mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d2b18f03a33c..4166cd76997e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -129,7 +129,7 @@ gt-y += \
gt/shmem_utils.o \
gt/sysfs_engines.o
 # x86 intel-gtt module support
-gt-$(CONFIG_X86) += gt/intel_gt_gmch.o
+gt-$(CONFIG_X86) += gt/intel_ggtt_gmch.o
 # autogenerated null render state
 gt-y += \
gt/gen6_renderstate.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index e6b2eb122ad7..a83d6858b766 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -3,16 +3,18 @@
  * Copyright © 2020 Intel Corporation
  */
 
-#include 
 #include 
 #include 
+#include 
+#include 
 
 #include 
+#include 
 
 #include "gem/i915_gem_lmem.h"
 
+#include "intel_ggtt_gmch.h"
 #include "intel_gt.h"
-#include "intel_gt_gmch.h"
 #include "intel_gt_regs.h"
 #include "i915_drv.h"
 #include "i915_scatterlist.h"
@@ -181,7 +183,7 @@ void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
spin_unlock_irq(>lock);
 }
 
-void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
+static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 
@@ -218,11 +220,232 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
return pte;
 }
 
+static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
+{
+   writeq(pte, addr);
+}
+
+static void gen8_ggtt_insert_page(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ enum i915_cache_level level,
+ u32 flags)
+{
+   struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+   gen8_pte_t __iomem *pte =
+   (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
+
+   gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
+
+   ggtt->invalidate(ggtt);
+}
+
+static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
+struct i915_vma_resource *vma_res,
+enum i915_cache_level level,
+u32 flags)
+{
+   const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
+   struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+   gen8_pte_t __iomem *gte;
+   gen8_pte_t __iomem *end;
+   struct sgt_iter iter;
+   dma_addr_t addr;
+
+   /*
+* Note that we ignore PTE_READ_ONLY here. The caller must be careful
+* not to allow the user to override access to a read only page.
+*/
+
+   gte = (gen8_pte_t __iomem *)ggtt->gsm;
+   gte += vma_res->start / I915_GTT_PAGE_SIZE;
+   end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
+
+   for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
+   gen8_set_pte(gte++, pte_encode | addr);
+   GEM_BUG_ON(gte > end);
+
+   /* Fill the allocated but "unused" space beyond the end of the buffer */
+   while (gte < end)
+   gen8_set_pte(gte++, vm->scratch[0]->encode);
+
+   /*
+* We want to flush the TLBs only after we're certain all the PTE
+* updates have finished.
+*/
+   ggtt->invalidate(ggtt);
+}
+
+static void gen6_ggtt_insert_page(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ enum i915_cache_level level,
+   

Re: [Intel-gfx] [PATCH i-g-t] tests/drm_fdinfo: Test virtual engines

[Umesh Nerlige Ramappa]

Thanks for adding these tests. I ran these with the kernel patch I had 
posted for GuC support and updated the patch to work with virtual 
engines - https://patchwork.freedesktop.org/series/105085/#rev3


I have listed some changes I had to do in the below patch. With those 
(or similar changes), this is:


Reviewed-by: Umesh Nerlige Ramappa 

On Thu, Jun 16, 2022 at 02:32:03PM +0100, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

We need some coverage of the virtual engines.

Signed-off-by: Tvrtko Ursulin 
Cc: Umesh Nerlige Ramappa 
---
tests/i915/drm_fdinfo.c | 284 +++-
1 file changed, 282 insertions(+), 2 deletions(-)

diff --git a/tests/i915/drm_fdinfo.c b/tests/i915/drm_fdinfo.c
index 3475d35b23b9..0a42370d54ce 100644
--- a/tests/i915/drm_fdinfo.c
+++ b/tests/i915/drm_fdinfo.c
@@ -27,6 +27,7 @@
#include "igt_device.h"
#include "igt_drm_fdinfo.h"
#include "i915/gem.h"
+#include "i915/gem_vm.h"
#include "intel_ctx.h"

IGT_TEST_DESCRIPTION("Test the i915 drm fdinfo data");
@@ -90,10 +91,10 @@ static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const 
intel_ctx_t *ctx,
struct igt_spin_factory opts = {
.ahnd = ahnd,
.ctx = ctx,
-   .engine = e->flags,
+   .engine = e ? e->flags : 0,
};

-   if (gem_class_can_store_dword(fd, e->class))
+   if (!e || gem_class_can_store_dword(fd, e->class))
opts.flags |= IGT_SPIN_POLL_RUN;

return __igt_spin_factory(fd, );
@@ -440,6 +441,265 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
gem_quiescent_gpu(gem_fd);
}

+static struct i915_engine_class_instance *
+list_engines(const intel_ctx_cfg_t *cfg,
+unsigned int class, unsigned int *out)
+{
+   struct i915_engine_class_instance *ci;
+   unsigned int count = 0, i;
+
+   ci = malloc(cfg->num_engines * sizeof(*ci));
+   igt_assert(ci);
+
+   for (i = 0; i < cfg->num_engines; i++) {
+   if (class == cfg->engines[i].engine_class)
+   ci[count++] = cfg->engines[i];
+   }
+
+   if (!count) {
+   free(ci);
+   ci = NULL;
+   }
+
+   *out = count;
+   return ci;
+}
+
+static size_t sizeof_load_balance(int count)
+{
+   return offsetof(struct i915_context_engines_load_balance,
+   engines[count]);
+}
+
+static size_t sizeof_param_engines(int count)
+{
+   return offsetof(struct i915_context_param_engines,
+   engines[count]);
+}
+
+#define alloca0(sz) ({ size_t sz__ = (sz); memset(alloca(sz__), 0, sz__); })
+
+static int __set_load_balancer(int i915, uint32_t ctx,
+  const struct i915_engine_class_instance *ci,
+  unsigned int count,
+  void *ext)
+{
+   struct i915_context_engines_load_balance *balancer =
+   alloca0(sizeof_load_balance(count));
+   struct i915_context_param_engines *engines =
+   alloca0(sizeof_param_engines(count + 1));
+   struct drm_i915_gem_context_param p = {
+   .ctx_id = ctx,
+   .param = I915_CONTEXT_PARAM_ENGINES,
+   .size = sizeof_param_engines(count + 1),
+   .value = to_user_pointer(engines)
+   };
+
+   balancer->base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE;
+   balancer->base.next_extension = to_user_pointer(ext);
+
+   igt_assert(count);
+   balancer->num_siblings = count;
+   memcpy(balancer->engines, ci, count * sizeof(*ci));
+
+   engines->extensions = to_user_pointer(balancer);
+   engines->engines[0].engine_class =
+   I915_ENGINE_CLASS_INVALID;
+   engines->engines[0].engine_instance =
+   I915_ENGINE_CLASS_INVALID_NONE;
+   memcpy(engines->engines + 1, ci, count * sizeof(*ci));
+
+   return __gem_context_set_param(i915, );
+}
+
+static void set_load_balancer(int i915, uint32_t ctx,
+ const struct i915_engine_class_instance *ci,
+ unsigned int count,
+ void *ext)
+{
+   igt_assert_eq(__set_load_balancer(i915, ctx, ci, count, ext), 0);
+}
+


static void context_unban(int i915, uint32_t context_id)
{
struct drm_i915_gem_context_param param = {
.ctx_id = context_id,
.param = I915_CONTEXT_PARAM_BANNABLE,
.value = 0,
};

gem_context_set_param(i915, );
}


+static void
+virtual(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
+{
+   intel_ctx_cfg_t cfg = {};
+
+   cfg.vm = gem_vm_create(i915);
+
+   for (int class = 0; class < 32; class++) {
+   struct i915_engine_class_instance *ci;
+   unsigned int count;
+
+   if (!gem_class_can_store_dword(i915, class))
+   continue;
+
+   ci = 

[Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness

[Nerlige Ramappa, Umesh]

From: John Harrison 

GuC provides engine_id and last_switch_in ticks for an active context in
the pphwsp. The context image provides a 32 bit total ticks which is the
accumulated by the context (a.k.a. context[CTX_TIMESTAMP]). This
information is used to calculate the context busyness as follows:

If the engine_id is valid, then busyness is the sum of accumulated total
ticks and active ticks. Active ticks is calculated with current gt time
as reference.

If engine_id is invalid, busyness is equal to accumulated total ticks.

Since KMD (CPU) retrieves busyness data from 2 sources - GPU and GuC, a
potential race was highlighted in an earlier review that can lead to
double accounting of busyness. While the solution to this is a wip,
busyness is still usable for platforms running GuC submission.

v2: (Tvrtko)
- Use COPS_RUNTIME_ACTIVE_TOTAL
- Add code comment for the race
- Undo local variables initializations

v3:
- Add support for virtual engines based on
  https://patchwork.freedesktop.org/series/105227/

Signed-off-by: John Harrison 
Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/gt/intel_context.c   | 12 +++-
 drivers/gpu/drm/i915/gt/intel_context.h   |  6 +-
 drivers/gpu/drm/i915/gt/intel_context_types.h |  6 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |  5 ++
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 65 ++-
 drivers/gpu/drm/i915/i915_drm_client.c|  6 +-
 6 files changed, 89 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_context.c 
b/drivers/gpu/drm/i915/gt/intel_context.c
index 4070cb5711d8..4a84146710e0 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -576,16 +576,24 @@ void intel_context_bind_parent_child(struct intel_context 
*parent,
child->parallel.parent = parent;
 }
 
-u64 intel_context_get_total_runtime_ns(const struct intel_context *ce)
+u64 intel_context_get_total_runtime_ns(struct intel_context *ce)
 {
u64 total, active;
 
+   if (ce->ops->update_stats)
+   ce->ops->update_stats(ce);
+
total = ce->stats.runtime.total;
if (ce->ops->flags & COPS_RUNTIME_CYCLES)
total *= ce->engine->gt->clock_period_ns;
 
active = READ_ONCE(ce->stats.active);
-   if (active)
+   /*
+* When COPS_RUNTIME_ACTIVE_TOTAL is set for ce->cops, the backend
+* already provides the total active time of the context, so skip this
+* calculation when this flag is set.
+*/
+   if (active && !(ce->ops->flags & COPS_RUNTIME_ACTIVE_TOTAL))
active = intel_context_clock() - active;
 
return total + active;
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h 
b/drivers/gpu/drm/i915/gt/intel_context.h
index b7d3214d2cdd..5fc7c19ab29b 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -56,7 +56,7 @@ static inline bool intel_context_is_parent(struct 
intel_context *ce)
return !!ce->parallel.number_children;
 }
 
-static inline bool intel_context_is_pinned(struct intel_context *ce);
+static inline bool intel_context_is_pinned(const struct intel_context *ce);
 
 static inline struct intel_context *
 intel_context_to_parent(struct intel_context *ce)
@@ -116,7 +116,7 @@ static inline int intel_context_lock_pinned(struct 
intel_context *ce)
  * Returns: true if the context is currently pinned for use by the GPU.
  */
 static inline bool
-intel_context_is_pinned(struct intel_context *ce)
+intel_context_is_pinned(const struct intel_context *ce)
 {
return atomic_read(>pin_count);
 }
@@ -351,7 +351,7 @@ intel_context_clear_nopreempt(struct intel_context *ce)
clear_bit(CONTEXT_NOPREEMPT, >flags);
 }
 
-u64 intel_context_get_total_runtime_ns(const struct intel_context *ce);
+u64 intel_context_get_total_runtime_ns(struct intel_context *ce);
 u64 intel_context_get_avg_runtime_ns(struct intel_context *ce);
 
 static inline u64 intel_context_clock(void)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h 
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 09f82545789f..797bb4242c18 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -38,6 +38,9 @@ struct intel_context_ops {
 #define COPS_RUNTIME_CYCLES_BIT 1
 #define COPS_RUNTIME_CYCLES BIT(COPS_RUNTIME_CYCLES_BIT)
 
+#define COPS_RUNTIME_ACTIVE_TOTAL_BIT 2
+#define COPS_RUNTIME_ACTIVE_TOTAL BIT(COPS_RUNTIME_ACTIVE_TOTAL_BIT)
+
int (*alloc)(struct intel_context *ce);
 
void (*ban)(struct intel_context *ce, struct i915_request *rq);
@@ -55,6 +58,8 @@ struct intel_context_ops {
 
void (*sched_disable)(struct intel_context *ce);
 
+   void (*update_stats)(struct intel_context *ce);
+
void (*reset)(struct intel_context *ce);
void (*destroy)(struct kref *kref);
 
@@ -146,6 +151,7 @@ struct intel_context {
struct 

[Intel-gfx] [PATCH] drm/i915/guc: Check for ct enabled while waiting for response

[Zhanjun Dong]

We are seeing error message of "No response for request". Some cases
happened while waiting for response and reset/suspend action was triggered.
In this case, no response is not an error, active requests will be
cancelled.

This patch will handle this condition and change the error message into
debug message.

Signed-off-by: Zhanjun Dong 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 24 ---
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index f01325cd1b62..f07a7666b1ad 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -455,6 +455,7 @@ static int ct_write(struct intel_guc_ct *ct,
 
 /**
  * wait_for_ct_request_update - Wait for CT request state update.
+ * @ct:pointer to CT
  * @req:   pointer to pending request
  * @status:placeholder for status
  *
@@ -467,9 +468,10 @@ static int ct_write(struct intel_guc_ct *ct,
  * *   0 response received (status is valid)
  * *   -ETIMEDOUT no response within hardcoded timeout
  */
-static int wait_for_ct_request_update(struct ct_request *req, u32 *status)
+static int wait_for_ct_request_update(struct intel_guc_ct *ct, struct 
ct_request *req, u32 *status)
 {
int err;
+   bool ct_enabled;
 
/*
 * Fast commands should complete in less than 10us, so sample quickly
@@ -481,12 +483,15 @@ static int wait_for_ct_request_update(struct ct_request 
*req, u32 *status)
 #define GUC_CTB_RESPONSE_TIMEOUT_SHORT_MS 10
 #define GUC_CTB_RESPONSE_TIMEOUT_LONG_MS 1000
 #define done \
-   (FIELD_GET(GUC_HXG_MSG_0_ORIGIN, READ_ONCE(req->status)) == \
+   (!(ct_enabled = intel_guc_ct_enabled(ct)) || \
+FIELD_GET(GUC_HXG_MSG_0_ORIGIN, READ_ONCE(req->status)) == \
 GUC_HXG_ORIGIN_GUC)
err = wait_for_us(done, GUC_CTB_RESPONSE_TIMEOUT_SHORT_MS);
if (err)
err = wait_for(done, GUC_CTB_RESPONSE_TIMEOUT_LONG_MS);
 #undef done
+   if (!ct_enabled)
+   err = -ECANCELED;
 
*status = req->status;
return err;
@@ -703,11 +708,15 @@ static int ct_send(struct intel_guc_ct *ct,
 
intel_guc_notify(ct_to_guc(ct));
 
-   err = wait_for_ct_request_update(, status);
+   err = wait_for_ct_request_update(ct, , status);
g2h_release_space(ct, GUC_CTB_HXG_MSG_MAX_LEN);
if (unlikely(err)) {
-   CT_ERROR(ct, "No response for request %#x (fence %u)\n",
-action[0], request.fence);
+   if (err == -ECANCELED)
+   CT_DEBUG(ct, "Request %#x (fence %u) cancelled as CTB 
is disabled\n",
+action[0], request.fence);
+   else
+   CT_ERROR(ct, "No response for request %#x (fence %u)\n",
+action[0], request.fence);
goto unlink;
}
 
@@ -771,8 +780,9 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 
*action, u32 len,
 
ret = ct_send(ct, action, len, response_buf, response_buf_size, 
);
if (unlikely(ret < 0)) {
-   CT_ERROR(ct, "Sending action %#x failed (%pe) status=%#X\n",
-action[0], ERR_PTR(ret), status);
+   if (ret != -ECANCELED)
+   CT_ERROR(ct, "Sending action %#x failed (%pe) 
status=%#X\n",
+action[0], ERR_PTR(ret), status);
} else if (unlikely(ret)) {
CT_DEBUG(ct, "send action %#x returned %d (%#x)\n",
 action[0], ret, ret);
-- 
2.36.0

[Intel-gfx] ✓ Fi.CI.BAT: success for i915/pmu: Wire GuC backend to per-client busyness (rev2)

[Patchwork]

== Series Details ==

Series: i915/pmu: Wire GuC backend to per-client busyness (rev2)
URL   : https://patchwork.freedesktop.org/series/105085/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11770 -> Patchwork_105085v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v2/index.html

Participating hosts (33 -> 34)
--

  Additional (2): fi-kbl-soraka fi-hsw-4770 
  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105085v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v2/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v2/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#3012])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v2/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][4] ([i915#1886])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v2/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v2/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-soraka:  NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v2/fi-kbl-soraka/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271]) +9 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v2/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- fi-tgl-u2:  [PASS][9] -> [DMESG-WARN][10] ([i915#402])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11770/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v2/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-guc: NOTRUN -> [SKIP][11] ([fdo#109271])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v2/fi-kbl-guc/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v2/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v2/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1072]) +3 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v2/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- {fi-ehl-2}: [INCOMPLETE][15] ([i915#5153]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11770/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v2/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3012]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915/pmu: Wire GuC backend to per-client busyness (rev2)

[Patchwork]

== Series Details ==

Series: i915/pmu: Wire GuC backend to per-client busyness (rev2)
URL   : https://patchwork.freedesktop.org/series/105085/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp/mst: Read the extended DPCD capabilities during system resume

[Patchwork]

== Series Details ==

Series: drm/dp/mst: Read the extended DPCD capabilities during system resume
URL   : https://patchwork.freedesktop.org/series/105102/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11756_full -> Patchwork_105102v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_105102v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_105102v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105102v1_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_eio@reset-stress:
- shard-snb:  [PASS][1] -> [TIMEOUT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-snb7/igt@gem_...@reset-stress.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-snb2/igt@gem_...@reset-stress.html

  
New tests
-

  New tests have been introduced between CI_DRM_11756_full and 
Patchwork_105102v1_full:

### New IGT tests (4) ###

  * igt@kms_plane_lowres@tiling-none@pipe-a-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [8.02] s

  * igt@kms_plane_lowres@tiling-none@pipe-b-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [7.91] s

  * igt@kms_plane_lowres@tiling-none@pipe-c-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [7.93] s

  * igt@kms_plane_lowres@tiling-none@pipe-d-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [7.94] s

  

Known issues


  Here are the changes found in Patchwork_105102v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@in-flight-contexts-1us:
- shard-apl:  [PASS][3] -> [TIMEOUT][4] ([i915#3063])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-apl2/igt@gem_...@in-flight-contexts-1us.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-apl2/igt@gem_...@in-flight-contexts-1us.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) +2 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-iclb2/igt@gem_exec_balan...@parallel-keep-in-fence.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-iclb5/igt@gem_exec_balan...@parallel-keep-in-fence.html

  * igt@gem_exec_capture@pi@vcs0:
- shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([i915#3371])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-iclb7/igt@gem_exec_capture@p...@vcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-iclb1/igt@gem_exec_capture@p...@vcs0.html

  * igt@gem_exec_endless@dispatch@bcs0:
- shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([i915#3778])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-tglb2/igt@gem_exec_endless@dispa...@bcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-tglb1/igt@gem_exec_endless@dispa...@bcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl:  NOTRUN -> [FAIL][11] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar 
issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-tglb1/igt@gem_exec_fair@basic-p...@bcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-tglb2/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-iclb3/igt@gem_exec_fair@basic-p...@vecs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-iclb6/igt@gem_exec_fair@basic-p...@vecs0.html
- shard-kbl:  [PASS][16] -> [FAIL][17] ([i915#2842]) +1 similar 
issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-kbl3/igt@gem_exec_fair@basic-p...@vecs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-kbl7/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_params@rsvd2-dirt:
- shard-iclb: NOTRUN -> [SKIP][18] ([fdo#109283])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-iclb2/igt@gem_exec_par...@rsvd2-dirt.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#4613])
   [19]: 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp/mst: Read the extended DPCD capabilities during system resume

[Vudum, Lakshminarayana]

Failure is related to https://gitlab.freedesktop.org/drm/intel/-/issues/3063

Lakshmi.

-Original Message-
From: Deak, Imre  
Sent: Thursday, June 16, 2022 11:58 AM
To: intel-gfx@lists.freedesktop.org; Nikula, Jani ; 
Lyude Paul ; Vudum, Lakshminarayana 

Cc: dri-de...@lists.freedesktop.org
Subject: Re: ✗ Fi.CI.IGT: failure for drm/dp/mst: Read the extended DPCD 
capabilities during system resume

On Wed, Jun 15, 2022 at 04:25:34AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/dp/mst: Read the extended DPCD capabilities during system resume
> URL   : https://patchwork.freedesktop.org/series/105102/
> State : failure

Thanks for the reviews, pushed the patch to drm-misc-next also adding
Cc: stable.

The failure is unrelated, see below.

> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_11756_full -> Patchwork_105102v1_full
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_105102v1_full absolutely need 
> to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_105102v1_full, please notify your bug team to allow 
> them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (13 -> 13)
> --
> 
>   No changes in participating hosts
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_105102v1_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@gem_eio@reset-stress:
> - shard-snb:  [PASS][1] -> [TIMEOUT][2]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-snb7/igt@gem_...@reset-stress.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-snb2/igt@gem_...@reset-stress.html

<7> [109.948420] heartbeat vcs0 heartbeat {seqno:5:11771, prio:-2147483648} not 
ticking

SNB doesn't support MST, so it's some unrelated issue.

> New tests
> -
> 
>   New tests have been introduced between CI_DRM_11756_full and 
> Patchwork_105102v1_full:
> 
> ### New IGT tests (5) ###
> 
>   * igt@kms_atomic_interruptible@legacy-setmode@hdmi-a-3-pipe-a:
> - Statuses : 1 pass(s)
> - Exec time: [6.14] s
> 
>   * igt@kms_plane_lowres@tiling-none@pipe-a-hdmi-a-3:
> - Statuses : 1 pass(s)
> - Exec time: [8.02] s
> 
>   * igt@kms_plane_lowres@tiling-none@pipe-b-hdmi-a-3:
> - Statuses : 1 pass(s)
> - Exec time: [7.91] s
> 
>   * igt@kms_plane_lowres@tiling-none@pipe-c-hdmi-a-3:
> - Statuses : 1 pass(s)
> - Exec time: [7.93] s
> 
>   * igt@kms_plane_lowres@tiling-none@pipe-d-hdmi-a-3:
> - Statuses : 1 pass(s)
> - Exec time: [7.94] s
> 
>   
> 
> Known issues
> 
> 
>   Here are the changes found in Patchwork_105102v1_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_eio@in-flight-contexts-1us:
> - shard-apl:  [PASS][3] -> [TIMEOUT][4] ([i915#3063])
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-apl2/igt@gem_...@in-flight-contexts-1us.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-apl2/igt@gem_...@in-flight-contexts-1us.html
> 
>   * igt@gem_exec_balancer@parallel-keep-in-fence:
> - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) +2 similar 
> issues
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-iclb2/igt@gem_exec_balan...@parallel-keep-in-fence.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-iclb5/igt@gem_exec_balan...@parallel-keep-in-fence.html
> 
>   * igt@gem_exec_capture@pi@vcs0:
> - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([i915#3371])
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-iclb7/igt@gem_exec_capture@p...@vcs0.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-iclb1/igt@gem_exec_capture@p...@vcs0.html
> 
>   * igt@gem_exec_endless@dispatch@bcs0:
> - shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([i915#3778])
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-tglb2/igt@gem_exec_endless@dispa...@bcs0.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-tglb1/igt@gem_exec_endless@dispa...@bcs0.html
> 
>   * igt@gem_exec_fair@basic-none-solo@rcs0:
> - shard-kbl:  NOTRUN -> [FAIL][11] ([i915#2842])
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
> 
>   * igt@gem_exec_fair@basic-pace@bcs0:
> - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar 
> issue
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-tglb1/igt@gem_exec_fair@basic-p...@bcs0.html
>

[Intel-gfx] ✓ Fi.CI.BAT: success for Add support for LMEM PCIe resizable bar

[Patchwork]

== Series Details ==

Series: Add support for LMEM PCIe resizable bar
URL   : https://patchwork.freedesktop.org/series/105231/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11769 -> Patchwork_105231v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/index.html

Participating hosts (34 -> 34)
--

  Additional (1): fi-bdw-gvtdvm 
  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105231v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [PASS][1] -> [INCOMPLETE][2] ([i915#3303] / 
[i915#4785])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-bdw-gvtdvm:  NOTRUN -> [INCOMPLETE][5] ([i915#4817])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-bdw-gvtdvm/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-bdw-gvtdvm:  NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-bdw-gvtdvm/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_flip@basic-plain-flip:
- fi-bdw-gvtdvm:  NOTRUN -> [SKIP][8] ([fdo#109271]) +47 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-bdw-gvtdvm/igt@kms_f...@basic-plain-flip.html

  * igt@kms_flip@basic-plain-flip@a-edp1:
- fi-tgl-u2:  [PASS][9] -> [DMESG-WARN][10] ([i915#402])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/fi-tgl-u2/igt@kms_flip@basic-plain-f...@a-edp1.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-tgl-u2/igt@kms_flip@basic-plain-f...@a-edp1.html

  * igt@runner@aborted:
- fi-blb-e6850:   NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-blb-e6850/igt@run...@aborted.html
- fi-hsw-g3258:   NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#4312])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-hsw-g3258/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [DMESG-WARN][13] ([i915#5122]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][15] ([i915#4785]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_busy@basic@flip:
- fi-tgl-u2:  [DMESG-WARN][17] ([i915#402]) -> [PASS][18] +1 
similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/fi-tgl-u2/igt@kms_busy@ba...@flip.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-tgl-u2/igt@kms_busy@ba...@flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
  [i915#5122]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add support for LMEM PCIe resizable bar

[Patchwork]

== Series Details ==

Series: Add support for LMEM PCIe resizable bar
URL   : https://patchwork.freedesktop.org/series/105231/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness

[Nerlige Ramappa, Umesh]

From: John Harrison 

GuC provides engine_id and last_switch_in ticks for an active context in
the pphwsp. The context image provides a 32 bit total ticks which is the
accumulated by the context (a.k.a. context[CTX_TIMESTAMP]). This
information is used to calculate the context busyness as follows:

If the engine_id is valid, then busyness is the sum of accumulated total
ticks and active ticks. Active ticks is calculated with current gt time
as reference.

If engine_id is invalid, busyness is equal to accumulated total ticks.

Since KMD (CPU) retrieves busyness data from 2 sources - GPU and GuC, a
potential race was highlighted in an earlier review that can lead to
double accounting of busyness. While the solution to this is a wip,
busyness is still usable for platforms running GuC submission.

v2: (Tvrtko)
- Use COPS_RUNTIME_ACTIVE_TOTAL
- Add code comment for the race
- Undo local variables initializations

Signed-off-by: John Harrison 
Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/gt/intel_context.c   | 12 +++-
 drivers/gpu/drm/i915/gt/intel_context.h   |  6 +-
 drivers/gpu/drm/i915/gt/intel_context_types.h |  6 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |  5 ++
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 63 ++-
 drivers/gpu/drm/i915/i915_drm_client.c|  6 +-
 6 files changed, 87 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_context.c 
b/drivers/gpu/drm/i915/gt/intel_context.c
index 4070cb5711d8..4a84146710e0 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -576,16 +576,24 @@ void intel_context_bind_parent_child(struct intel_context 
*parent,
child->parallel.parent = parent;
 }
 
-u64 intel_context_get_total_runtime_ns(const struct intel_context *ce)
+u64 intel_context_get_total_runtime_ns(struct intel_context *ce)
 {
u64 total, active;
 
+   if (ce->ops->update_stats)
+   ce->ops->update_stats(ce);
+
total = ce->stats.runtime.total;
if (ce->ops->flags & COPS_RUNTIME_CYCLES)
total *= ce->engine->gt->clock_period_ns;
 
active = READ_ONCE(ce->stats.active);
-   if (active)
+   /*
+* When COPS_RUNTIME_ACTIVE_TOTAL is set for ce->cops, the backend
+* already provides the total active time of the context, so skip this
+* calculation when this flag is set.
+*/
+   if (active && !(ce->ops->flags & COPS_RUNTIME_ACTIVE_TOTAL))
active = intel_context_clock() - active;
 
return total + active;
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h 
b/drivers/gpu/drm/i915/gt/intel_context.h
index b7d3214d2cdd..5fc7c19ab29b 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -56,7 +56,7 @@ static inline bool intel_context_is_parent(struct 
intel_context *ce)
return !!ce->parallel.number_children;
 }
 
-static inline bool intel_context_is_pinned(struct intel_context *ce);
+static inline bool intel_context_is_pinned(const struct intel_context *ce);
 
 static inline struct intel_context *
 intel_context_to_parent(struct intel_context *ce)
@@ -116,7 +116,7 @@ static inline int intel_context_lock_pinned(struct 
intel_context *ce)
  * Returns: true if the context is currently pinned for use by the GPU.
  */
 static inline bool
-intel_context_is_pinned(struct intel_context *ce)
+intel_context_is_pinned(const struct intel_context *ce)
 {
return atomic_read(>pin_count);
 }
@@ -351,7 +351,7 @@ intel_context_clear_nopreempt(struct intel_context *ce)
clear_bit(CONTEXT_NOPREEMPT, >flags);
 }
 
-u64 intel_context_get_total_runtime_ns(const struct intel_context *ce);
+u64 intel_context_get_total_runtime_ns(struct intel_context *ce);
 u64 intel_context_get_avg_runtime_ns(struct intel_context *ce);
 
 static inline u64 intel_context_clock(void)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h 
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 09f82545789f..797bb4242c18 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -38,6 +38,9 @@ struct intel_context_ops {
 #define COPS_RUNTIME_CYCLES_BIT 1
 #define COPS_RUNTIME_CYCLES BIT(COPS_RUNTIME_CYCLES_BIT)
 
+#define COPS_RUNTIME_ACTIVE_TOTAL_BIT 2
+#define COPS_RUNTIME_ACTIVE_TOTAL BIT(COPS_RUNTIME_ACTIVE_TOTAL_BIT)
+
int (*alloc)(struct intel_context *ce);
 
void (*ban)(struct intel_context *ce, struct i915_request *rq);
@@ -55,6 +58,8 @@ struct intel_context_ops {
 
void (*sched_disable)(struct intel_context *ce);
 
+   void (*update_stats)(struct intel_context *ce);
+
void (*reset)(struct intel_context *ce);
void (*destroy)(struct kref *kref);
 
@@ -146,6 +151,7 @@ struct intel_context {
struct ewma_runtime avg;
u64 total;
u32 last;
+ 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp/mst: Read the extended DPCD capabilities during system resume

[Imre Deak]

On Thu, Jun 16, 2022 at 09:57:43PM +0300, Imre Deak wrote:
> On Wed, Jun 15, 2022 at 04:25:34AM +, Patchwork wrote:
> > == Series Details ==
> > 
> > Series: drm/dp/mst: Read the extended DPCD capabilities during system resume
> > URL   : https://patchwork.freedesktop.org/series/105102/
> > State : failure
> 
> Thanks for the reviews, pushed the patch to drm-misc-next also adding
> Cc: stable.
> 
> The failure is unrelated, see below.
> 
> > == Summary ==
> > 
> > CI Bug Log - changes from CI_DRM_11756_full -> Patchwork_105102v1_full
> > 
> > 
> > Summary
> > ---
> > 
> >   **FAILURE**
> > 
> >   Serious unknown changes coming with Patchwork_105102v1_full absolutely 
> > need to be
> >   verified manually.
> >   
> >   If you think the reported changes have nothing to do with the changes
> >   introduced in Patchwork_105102v1_full, please notify your bug team to 
> > allow them
> >   to document this new failure mode, which will reduce false positives in 
> > CI.
> > 
> >   
> > 
> > Participating hosts (13 -> 13)
> > --
> > 
> >   No changes in participating hosts
> > 
> > Possible new issues
> > ---
> > 
> >   Here are the unknown changes that may have been introduced in 
> > Patchwork_105102v1_full:
> > 
> > ### IGT changes ###
> > 
> >  Possible regressions 
> > 
> >   * igt@gem_eio@reset-stress:
> > - shard-snb:  [PASS][1] -> [TIMEOUT][2]
> >[1]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-snb7/igt@gem_...@reset-stress.html
> >[2]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-snb2/igt@gem_...@reset-stress.html
> 
> <7> [109.948420] heartbeat vcs0 heartbeat {seqno:5:11771, prio:-2147483648} 
> not ticking

Hm, the above is probably expected after a manual reset, the actual
failure being the subsequent:

<5> [121.901521] i915 :00:02.0: [drm] Resetting chip for Manually reset 
engine mask to 
<4> [219.007508] [IGT] Per-test timeout exceeded. Killing the current test with 
SIGQUIT.

> SNB doesn't support MST, so it's some unrelated issue.
> 
> > New tests
> > -
> > 
> >   New tests have been introduced between CI_DRM_11756_full and 
> > Patchwork_105102v1_full:
> > 
> > ### New IGT tests (5) ###
> > 
> >   * igt@kms_atomic_interruptible@legacy-setmode@hdmi-a-3-pipe-a:
> > - Statuses : 1 pass(s)
> > - Exec time: [6.14] s
> > 
> >   * igt@kms_plane_lowres@tiling-none@pipe-a-hdmi-a-3:
> > - Statuses : 1 pass(s)
> > - Exec time: [8.02] s
> > 
> >   * igt@kms_plane_lowres@tiling-none@pipe-b-hdmi-a-3:
> > - Statuses : 1 pass(s)
> > - Exec time: [7.91] s
> > 
> >   * igt@kms_plane_lowres@tiling-none@pipe-c-hdmi-a-3:
> > - Statuses : 1 pass(s)
> > - Exec time: [7.93] s
> > 
> >   * igt@kms_plane_lowres@tiling-none@pipe-d-hdmi-a-3:
> > - Statuses : 1 pass(s)
> > - Exec time: [7.94] s
> > 
> >   
> > 
> > Known issues
> > 
> > 
> >   Here are the changes found in Patchwork_105102v1_full that come from 
> > known issues:
> > 
> > ### IGT changes ###
> > 
> >  Issues hit 
> > 
> >   * igt@gem_eio@in-flight-contexts-1us:
> > - shard-apl:  [PASS][3] -> [TIMEOUT][4] ([i915#3063])
> >[3]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-apl2/igt@gem_...@in-flight-contexts-1us.html
> >[4]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-apl2/igt@gem_...@in-flight-contexts-1us.html
> > 
> >   * igt@gem_exec_balancer@parallel-keep-in-fence:
> > - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) +2 similar 
> > issues
> >[5]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-iclb2/igt@gem_exec_balan...@parallel-keep-in-fence.html
> >[6]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-iclb5/igt@gem_exec_balan...@parallel-keep-in-fence.html
> > 
> >   * igt@gem_exec_capture@pi@vcs0:
> > - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([i915#3371])
> >[7]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-iclb7/igt@gem_exec_capture@p...@vcs0.html
> >[8]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-iclb1/igt@gem_exec_capture@p...@vcs0.html
> > 
> >   * igt@gem_exec_endless@dispatch@bcs0:
> > - shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([i915#3778])
> >[9]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-tglb2/igt@gem_exec_endless@dispa...@bcs0.html
> >[10]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-tglb1/igt@gem_exec_endless@dispa...@bcs0.html
> > 
> >   * igt@gem_exec_fair@basic-none-solo@rcs0:
> > - shard-kbl:  NOTRUN -> [FAIL][11] ([i915#2842])
> >[11]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
> > 
> >   * 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp/mst: Read the extended DPCD capabilities during system resume

[Imre Deak]

On Wed, Jun 15, 2022 at 04:25:34AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/dp/mst: Read the extended DPCD capabilities during system resume
> URL   : https://patchwork.freedesktop.org/series/105102/
> State : failure

Thanks for the reviews, pushed the patch to drm-misc-next also adding
Cc: stable.

The failure is unrelated, see below.

> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_11756_full -> Patchwork_105102v1_full
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_105102v1_full absolutely need 
> to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_105102v1_full, please notify your bug team to allow 
> them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (13 -> 13)
> --
> 
>   No changes in participating hosts
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_105102v1_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@gem_eio@reset-stress:
> - shard-snb:  [PASS][1] -> [TIMEOUT][2]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-snb7/igt@gem_...@reset-stress.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-snb2/igt@gem_...@reset-stress.html

<7> [109.948420] heartbeat vcs0 heartbeat {seqno:5:11771, prio:-2147483648} not 
ticking

SNB doesn't support MST, so it's some unrelated issue.

> New tests
> -
> 
>   New tests have been introduced between CI_DRM_11756_full and 
> Patchwork_105102v1_full:
> 
> ### New IGT tests (5) ###
> 
>   * igt@kms_atomic_interruptible@legacy-setmode@hdmi-a-3-pipe-a:
> - Statuses : 1 pass(s)
> - Exec time: [6.14] s
> 
>   * igt@kms_plane_lowres@tiling-none@pipe-a-hdmi-a-3:
> - Statuses : 1 pass(s)
> - Exec time: [8.02] s
> 
>   * igt@kms_plane_lowres@tiling-none@pipe-b-hdmi-a-3:
> - Statuses : 1 pass(s)
> - Exec time: [7.91] s
> 
>   * igt@kms_plane_lowres@tiling-none@pipe-c-hdmi-a-3:
> - Statuses : 1 pass(s)
> - Exec time: [7.93] s
> 
>   * igt@kms_plane_lowres@tiling-none@pipe-d-hdmi-a-3:
> - Statuses : 1 pass(s)
> - Exec time: [7.94] s
> 
>   
> 
> Known issues
> 
> 
>   Here are the changes found in Patchwork_105102v1_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_eio@in-flight-contexts-1us:
> - shard-apl:  [PASS][3] -> [TIMEOUT][4] ([i915#3063])
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-apl2/igt@gem_...@in-flight-contexts-1us.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-apl2/igt@gem_...@in-flight-contexts-1us.html
> 
>   * igt@gem_exec_balancer@parallel-keep-in-fence:
> - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) +2 similar 
> issues
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-iclb2/igt@gem_exec_balan...@parallel-keep-in-fence.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-iclb5/igt@gem_exec_balan...@parallel-keep-in-fence.html
> 
>   * igt@gem_exec_capture@pi@vcs0:
> - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([i915#3371])
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-iclb7/igt@gem_exec_capture@p...@vcs0.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-iclb1/igt@gem_exec_capture@p...@vcs0.html
> 
>   * igt@gem_exec_endless@dispatch@bcs0:
> - shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([i915#3778])
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-tglb2/igt@gem_exec_endless@dispa...@bcs0.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-tglb1/igt@gem_exec_endless@dispa...@bcs0.html
> 
>   * igt@gem_exec_fair@basic-none-solo@rcs0:
> - shard-kbl:  NOTRUN -> [FAIL][11] ([i915#2842])
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
> 
>   * igt@gem_exec_fair@basic-pace@bcs0:
> - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar 
> issue
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-tglb1/igt@gem_exec_fair@basic-p...@bcs0.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105102v1/shard-tglb2/igt@gem_exec_fair@basic-p...@bcs0.html
> 
>   * igt@gem_exec_fair@basic-pace@vecs0:
> - shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842])
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11756/shard-iclb3/igt@gem_exec_fair@basic-p...@vecs0.html
>[15]: 
> 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: drm/i915/display: split out verification, hw readout and dump from intel_display.c

[Patchwork]

== Series Details ==

Series: drm/i915: drm/i915/display: split out verification, hw readout and dump 
from intel_display.c
URL   : https://patchwork.freedesktop.org/series/105220/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11767_full -> Patchwork_105220v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_105220v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_105220v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 12)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105220v1_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rpm@debugfs-forcewake-user:
- shard-tglb: [PASS][1] -> [SKIP][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/shard-tglb6/igt@i915_pm_...@debugfs-forcewake-user.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/shard-tglb5/igt@i915_pm_...@debugfs-forcewake-user.html

  
Known issues


  Here are the changes found in Patchwork_105220v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ccs@block-copy-compressed:
- shard-iclb: NOTRUN -> [SKIP][3] ([i915#5327])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/shard-iclb7/igt@gem_...@block-copy-compressed.html

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-apl:  [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +5 similar 
issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/shard-apl3/igt@gem_ctx_isolation@preservation...@vecs0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/shard-apl8/igt@gem_ctx_isolation@preservation...@vecs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/shard-iclb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
- shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][14] ([i915#2842]) +1 similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][15] ([fdo#112283])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/shard-iclb7/igt@gem_exec_par...@secure-non-root.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][16] -> [SKIP][17] ([i915#2190])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/shard-tglb8/igt@gem_huc_c...@huc-copy.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/shard-tglb7/igt@gem_huc_c...@huc-copy.html
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#2190])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/shard-iclb7/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-skl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/shard-skl6/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-apl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/shard-apl4/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-snb: 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fdinfo: Don't show engine classes not present

[Patchwork]

== Series Details ==

Series: drm/i915/fdinfo: Don't show engine classes not present
URL   : https://patchwork.freedesktop.org/series/105228/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11768 -> Patchwork_105228v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/index.html

Participating hosts (43 -> 34)
--

  Missing(9): bat-dg1-6 bat-dg1-5 bat-dg2-8 bat-dg2-9 bat-adlp-6 bat-adlp-4 
fi-bdw-samus bat-jsl-2 bat-jsl-1 

Known issues


  Here are the changes found in Patchwork_105228v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#111827])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [INCOMPLETE][2] ([i915#4785]) -> [PASS][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785


Build changes
-

  * Linux: CI_DRM_11768 -> Patchwork_105228v1

  CI-20190529: 20190529
  CI_DRM_11768: 6da0a0872a9b44e2be9645c1d7045fe88e035c25 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6533: 6b5107d91827962808441db6b98e478aa9e67bdb @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_105228v1: 6da0a0872a9b44e2be9645c1d7045fe88e035c25 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

00b9e54624f4 drm/i915/fdinfo: Don't show engine classes not present

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105228v1/index.html

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/glk: ECS Liva Q2 needs GLK HDMI port timing quirk

[Patchwork]

== Series Details ==

Series: drm/i915/glk: ECS Liva Q2 needs GLK HDMI port timing quirk
URL   : https://patchwork.freedesktop.org/series/105226/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11768 -> Patchwork_105226v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/index.html

Participating hosts (43 -> 42)
--

  Additional (2): bat-adlm-1 bat-atsm-1 
  Missing(3): fi-hsw-4770 bat-jsl-2 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105226v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@workarounds:
- {bat-adlm-1}:   NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/bat-adlm-1/igt@i915_selftest@l...@workarounds.html

  
Known issues


  Here are the changes found in Patchwork_105226v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][2] -> [INCOMPLETE][3] ([i915#3921])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][4] -> [DMESG-FAIL][5] ([i915#4528])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@kms_busy@basic@flip:
- bat-adlp-4: [PASS][6] -> [DMESG-WARN][7] ([i915#3576]) +1 similar 
issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-adlp-4/igt@kms_busy@ba...@flip.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/bat-adlp-4/igt@kms_busy@ba...@flip.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- fi-tgl-u2:  [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +1 similar 
issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [INCOMPLETE][11] ([i915#4785]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
- bat-dg1-6:  [DMESG-FAIL][13] ([i915#4494] / [i915#4957]) -> 
[PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}:   [DMESG-WARN][15] ([i915#3576]) -> [PASS][16] +1 
similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  * igt@kms_flip@basic-flip-vs-modeset@b-edp1:
- bat-adlp-4: [DMESG-WARN][17] ([i915#3576]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-adlp-4/igt@kms_flip@basic-flip-vs-mode...@b-edp1.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105226v1/bat-adlp-4/igt@kms_flip@basic-flip-vs-mode...@b-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: 

[Intel-gfx] ✓ Fi.CI.IGT: success for Do not enable PSR2 if no active planes (rev3)

[Patchwork]

== Series Details ==

Series: Do not enable PSR2 if no active planes (rev3)
URL   : https://patchwork.freedesktop.org/series/105109/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11767_full -> Patchwork_105109v3_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105109v3_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_fair@basic-pace@bcs0:
- {shard-rkl}:[FAIL][1] ([i915#2842]) -> [SKIP][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/shard-rkl-1/igt@gem_exec_fair@basic-p...@bcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/shard-rkl-5/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@i915_hangman@gt-engine-error@bcs0:
- {shard-rkl}:[PASS][3] -> [SKIP][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/shard-rkl-2/igt@i915_hangman@gt-engine-er...@bcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/shard-rkl-5/igt@i915_hangman@gt-engine-er...@bcs0.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
- {shard-rkl}:[SKIP][5] ([i915#4070]) -> [SKIP][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/shard-rkl-1/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-c.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/shard-rkl-5/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-c.html

  
Known issues


  Here are the changes found in Patchwork_105109v3_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ccs@block-copy-compressed:
- shard-iclb: NOTRUN -> [SKIP][7] ([i915#5327])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/shard-iclb6/igt@gem_...@block-copy-compressed.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) +1 similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/shard-iclb4/igt@gem_exec_balan...@parallel-keep-submit-fence.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/shard-iclb5/igt@gem_exec_balan...@parallel-keep-submit-fence.html

  * igt@gem_exec_balancer@parallel-ordering:
- shard-kbl:  NOTRUN -> [FAIL][10] ([i915#6117])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/shard-kbl1/igt@gem_exec_balan...@parallel-ordering.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl:  [PASS][13] -> [FAIL][14] ([i915#2842]) +2 similar 
issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/shard-kbl1/igt@gem_exec_fair@basic-n...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/shard-kbl1/igt@gem_exec_fair@basic-n...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842]) +1 similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][16] ([fdo#112283])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/shard-iclb6/igt@gem_exec_par...@secure-non-root.html

  * igt@gem_huc_copy@huc-copy:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#2190])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/shard-iclb6/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-skl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/shard-skl7/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-kbl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/shard-kbl1/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-snb:  NOTRUN -> [SKIP][20] ([fdo#109271]) +20 similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/shard-snb6/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html

  * igt@gem_mmap_gtt@coherency:
- 

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/display: Add smem fallback allocation for dpt (rev4)

[Juha-Pekka Heikkilä]

Hi Lakshmi,

Here would be another false positive, I don't see how my changes would
affect debugfs_test@read_all_entries test on kbl.

/Juha-Pekka

to 16. kesäk. 2022 klo 19.31 Patchwork 
kirjoitti:

> *Patch Details*
> *Series:* series starting with [1/3] drm/i915/display: Add smem fallback
> allocation for dpt (rev4)
> *URL:* https://patchwork.freedesktop.org/series/104983/
> *State:* failure
> *Details:*
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v4/index.html CI
> Bug Log - changes from CI_DRM_11768 -> Patchwork_104983v4 Summary
>
> *FAILURE*
>
> Serious unknown changes coming with Patchwork_104983v4 absolutely need to
> be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_104983v4, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v4/index.html
> Participating hosts (43 -> 41)
>
> Additional (2): bat-adlm-1 bat-atsm-1
> Missing (4): bat-dg2-8 bat-jsl-2 bat-dg2-9 fi-bdw-samus
> Possible new issues
>
> Here are the unknown changes that may have been introduced in
> Patchwork_104983v4:
> IGT changes Possible regressions
>
>- igt@debugfs_test@read_all_entries:
>   - fi-kbl-guc: PASS
>   
> 
>   -> FAIL
>   
> 
>
> Known issues
>
> Here are the changes found in Patchwork_104983v4 that come from known
> issues:
> IGT changes Issues hit
>
>-
>
>igt@i915_selftest@live@requests:
>- fi-blb-e6850: PASS
>   
> 
>   -> DMESG-FAIL
>   
> 
>   (i915#4528 )
>-
>
>igt@kms_busy@basic@flip:
>- fi-tgl-u2: PASS
>   
> 
>   -> DMESG-WARN
>   
> 
>   (i915#402 ) +1
>   similar issue
>-
>
>igt@kms_chamelium@common-hpd-after-suspend:
>-
>
>   fi-hsw-g3258: NOTRUN -> SKIP
>   
> 
>   (fdo#109271  /
>   fdo#111827 )
>   -
>
>   fi-hsw-4770: NOTRUN -> SKIP
>   
> 
>   (fdo#109271  /
>   fdo#111827 )
>   -
>
>igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
>- bat-adlp-4: PASS
>   
> 
>   -> DMESG-WARN
>   
> 
>   (i915#3576 )
>
> Possible fixes
>
>-
>
>igt@i915_pm_rpm@module-reload:
>- bat-adlp-4: DMESG-WARN
>   
> 
>   (i915#3576 )
>   -> PASS
>   
> 
>   +3 similar issues
>-
>
>igt@i915_selftest@live@hangcheck:
>-
>
>   fi-hsw-4770: INCOMPLETE
>   
> 
>   (i915#3303  /
>   i915#4785 )
>   -> PASS
>   
> 
>   -
>
>   fi-hsw-g3258: INCOMPLETE
>   
> 
>   (i915#4785 )
>   -> PASS
>   
> 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dgfx: Disable d3cold Correctly (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dgfx: Disable d3cold Correctly (rev2)
URL   : https://patchwork.freedesktop.org/series/104770/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11768 -> Patchwork_104770v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/index.html

Participating hosts (43 -> 40)
--

  Additional (1): bat-atsm-1 
  Missing(4): bat-dg2-8 bat-jsl-2 bat-dg2-9 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_104770v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@gem:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][1] ([i915#4528])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/fi-pnv-d510/igt@i915_selftest@l...@gem.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][2] -> [DMESG-FAIL][3] ([i915#4528])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@kms_busy@basic@flip:
- fi-tgl-u2:  [PASS][4] -> [DMESG-WARN][5] ([i915#402])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-tgl-u2/igt@kms_busy@ba...@flip.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/fi-tgl-u2/igt@kms_busy@ba...@flip.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- bat-adlp-4: [PASS][8] -> [DMESG-WARN][9] ([i915#3576])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-adlp-4/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/bat-adlp-4/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html

  * igt@runner@aborted:
- fi-adl-ddr5:NOTRUN -> [FAIL][10] ([i915#4312])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/fi-adl-ddr5/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- bat-adlp-4: [DMESG-WARN][11] ([i915#3576]) -> [PASS][12] +1 
similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-adlp-4/igt@i915_pm_...@module-reload.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/bat-adlp-4/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][13] ([i915#3303] / [i915#4785]) -> 
[PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-g3258:   [INCOMPLETE][15] ([i915#4785]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][17] ([i915#4528]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}:   [DMESG-WARN][19] ([i915#3576]) -> [PASS][20] +1 
similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104770v2/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for DG2 VRAM_SR Support (rev3)

[Patchwork]

== Series Details ==

Series: DG2 VRAM_SR Support (rev3)
URL   : https://patchwork.freedesktop.org/series/104128/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11768 -> Patchwork_104128v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/index.html

Participating hosts (43 -> 41)
--

  Additional (1): bat-atsm-1 
  Missing(3): bat-dg2-8 fi-rkl-11600 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_104128v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][1] -> [DMESG-FAIL][2] ([i915#4528])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- fi-tgl-u2:  [PASS][4] -> [DMESG-WARN][5] ([i915#402])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- bat-adlp-4: [PASS][6] -> [DMESG-WARN][7] ([i915#3576])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-adlp-4/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/bat-adlp-4/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html

  * igt@kms_psr@cursor_plane_move:
- fi-tgl-u2:  [PASS][8] -> [SKIP][9] ([i915#668]) +3 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-tgl-u2/igt@kms_psr@cursor_plane_move.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/fi-tgl-u2/igt@kms_psr@cursor_plane_move.html

  
 Possible fixes 

  * igt@gem_mmap@basic:
- {bat-jsl-2}:[TIMEOUT][10] -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-jsl-2/igt@gem_m...@basic.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/bat-jsl-2/igt@gem_m...@basic.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- {bat-jsl-2}:[INCOMPLETE][12] -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-jsl-2/igt@i915_pm_...@basic-pci-d3-state.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/bat-jsl-2/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_pm_rpm@module-reload:
- bat-adlp-4: [DMESG-WARN][14] ([i915#3576]) -> [PASS][15] +2 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-adlp-4/igt@i915_pm_...@module-reload.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/bat-adlp-4/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [INCOMPLETE][16] ([i915#4785]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
- bat-dg1-5:  [DMESG-FAIL][18] ([i915#4494] / [i915#4957]) -> 
[PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@hugepages:
- {bat-dg2-9}:[DMESG-WARN][20] ([i915#5763]) -> [PASS][21] +6 
similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-dg2-9/igt@i915_selftest@l...@hugepages.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/bat-dg2-9/igt@i915_selftest@l...@hugepages.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#402]: 

Re: [Intel-gfx] [Intel-gfx 1/1] drm/i915/guc: Don't update engine busyness stats too frequently

[Tvrtko Ursulin]

On 15/06/2022 19:59, Lucas De Marchi wrote:

On Tue, Jun 14, 2022 at 08:07:04AM +0100, Tvrtko Ursulin wrote:


On 14/06/2022 02:10, Umesh Nerlige Ramappa wrote:

On Sat, Jun 11, 2022 at 10:27:11AM -0700, Alan Previn wrote:

Using igt's gem-create and with additional patches to track object
creation time, it was measured that guc_update_engine_gt_clks was
getting called over 188 thousand times in the span of 15 seconds
(running the test three times).

Get a jiffies sample on every trigger and ensure we skip sampling
if we are being called too soon. Use half of the ping_delay as a
safe threshold.

NOTE: with this change, the number of calls went down to just 14
over the same span of time (matching the original intent of running
about once every 24 seconds, at 19.2Mhz GT freq, per engine).

Signed-off-by: Alan Previn 
---
drivers/gpu/drm/i915/gt/intel_engine_types.h  | 10 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c |  9 +
2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h 
b/drivers/gpu/drm/i915/gt/intel_engine_types.h

index 2286f96f5f87..63f4ecdf1606 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -323,6 +323,16 @@ struct intel_engine_guc_stats {
 * @start_gt_clk: GT clock time of last idle to active transition.
 */
u64 start_gt_clk;
+
+    /**
+ * @last_jiffies: Jiffies at last actual stats collection time
+ *
+ * We use this timestamp to ensure we don't oversample the
+ * stats because runtime power management events can trigger
+ * stats collection at much higher rates than required.
+ */
+    u64 last_jiffies;
+
};

struct intel_engine_cs {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

index 5a1dfacf24ea..8f8bf6e40ccb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1167,6 +1167,15 @@ static void guc_update_engine_gt_clks(struct 
intel_engine_cs *engine)


A user query will end up in guc_engine_busyness which will call 
guc_update_engine_gt_clks. Adding this logic here will affect accuracy.
The other place where guc_update_engine_gt_clks is called is in the 
ping worker, but that worker runs at 1/8th the wrap around time for 
the gt clocks (32 bit). The last I checked the wrap around was at 22 
seconds.


That leaves only the gt_park path. fwiu, this path runs too 
frequently and here we are updating the busyness stats. That is 
causing the enormous PCI traffic (lmem accesses). Only this path 
needs to be fixed, as in just use the same logic in the 
intel_guc_busyness_park() to decide whether to call 
__update_guc_busyness_stats or not.


Not updating the driver state in park will not negatively impact 
accuracy in some scenarios? That needs to balanced against the 
questions whether or not there are real world scenarios impacted by 
the update cost or it is just for IGT.


there is, which was what motivated 
https://patchwork.freedesktop.org/series/105011/ and in parallel Alan

worked on this. I view both as orthogonal  thought. I used it to make
the single-word-from-lmem faster, but if we can reduce
the frequency this code path is called, it should be even better.
Per Umesh's and your comment I'm unsure if we can... but if
there is no user monitoring the usage, should we still be calling this?
"Nobody is looking, why are we sampling?" kind of thought.


Who did you find is doing the sampling in the real world use case? AFAIR 
if one one is querying busyness, I thought there would only be the GuC 
ping worker which runs extremely infrequently (to avoid some counter 
overflow).


Regards,

Tvrtko


Summarizing the first patch in my series: it improved igt in ~50% and a
real world case in ~12%

Lucas De Marchi

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DG2 VRAM_SR Support (rev3)

[Patchwork]

== Series Details ==

Series: DG2 VRAM_SR Support (rev3)
URL   : https://patchwork.freedesktop.org/series/104128/
State : warning

== Summary ==

Error: dim checkpatch failed
ee513fcc2693 drm/i915/dgfx: OpRegion VRAM Self Refresh Support
341133e9b9ad drm/i915/dg1: OpRegion PCON DG1 MBD config support
b0e90ba1012b drm/i915/dg2: Add DG2_NB_MBD subplatform
-:108: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#108: FILE: include/drm/i915_pciids.h:696:
+#define INTEL_DG2_G10_NB_MBD_IDS(info) \
INTEL_VGA_DEVICE(0x5690, info), \
INTEL_VGA_DEVICE(0x5691, info), \
+   INTEL_VGA_DEVICE(0x5692, info)

-:108: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible 
side-effects?
#108: FILE: include/drm/i915_pciids.h:696:
+#define INTEL_DG2_G10_NB_MBD_IDS(info) \
INTEL_VGA_DEVICE(0x5690, info), \
INTEL_VGA_DEVICE(0x5691, info), \
+   INTEL_VGA_DEVICE(0x5692, info)

-:114: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#114: FILE: include/drm/i915_pciids.h:701:
+#define INTEL_DG2_G11_NB_MBD_IDS(info) \
+   INTEL_VGA_DEVICE(0x5693, info), \
+   INTEL_VGA_DEVICE(0x5694, info), \
+   INTEL_VGA_DEVICE(0x5695, info)

-:114: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible 
side-effects?
#114: FILE: include/drm/i915_pciids.h:701:
+#define INTEL_DG2_G11_NB_MBD_IDS(info) \
+   INTEL_VGA_DEVICE(0x5693, info), \
+   INTEL_VGA_DEVICE(0x5694, info), \
+   INTEL_VGA_DEVICE(0x5695, info)

-:119: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#119: FILE: include/drm/i915_pciids.h:706:
+#define INTEL_DG2_G12_NB_MBD_IDS(info) \
+   INTEL_VGA_DEVICE(0x5696, info), \
+   INTEL_VGA_DEVICE(0x5697, info)

-:119: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible 
side-effects?
#119: FILE: include/drm/i915_pciids.h:706:
+#define INTEL_DG2_G12_NB_MBD_IDS(info) \
+   INTEL_VGA_DEVICE(0x5696, info), \
+   INTEL_VGA_DEVICE(0x5697, info)

-:123: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#123: FILE: include/drm/i915_pciids.h:710:
+#define INTEL_DG2_G10_IDS(info) \
INTEL_VGA_DEVICE(0x56A0, info), \
INTEL_VGA_DEVICE(0x56A1, info), \
INTEL_VGA_DEVICE(0x56A2, info)

-:123: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible 
side-effects?
#123: FILE: include/drm/i915_pciids.h:710:
+#define INTEL_DG2_G10_IDS(info) \
INTEL_VGA_DEVICE(0x56A0, info), \
INTEL_VGA_DEVICE(0x56A1, info), \
INTEL_VGA_DEVICE(0x56A2, info)

total: 4 errors, 0 warnings, 4 checks, 117 lines checked
b835f2871301 drm/i915/dg2: DG2 MBD config
-:50: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible 
side-effects?
#50: FILE: drivers/gpu/drm/i915/i915_drv.h:1025:
+#define IS_DG2_MBD(dev_priv) (IS_DG2_G10_NB_MBD(dev_priv) || 
IS_DG2_G11_NB_MBD(dev_priv) || \
+ IS_DG2_G12_NB_MBD(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 29 lines checked
28151cba023d drm/i915/dgfx: Add has_lmem_sr
78ead46ad383 drm/i915/dgfx: Setup VRAM SR with D3COLD
-:101: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#101: FILE: drivers/gpu/drm/i915/intel_pcode.c:271:
+ REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND,
+ DG1_PCODE_D3_VRAM_SR) |

-:103: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#103: FILE: drivers/gpu/drm/i915/intel_pcode.c:273:
+ REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1,
+ DG1_ENABLE_SR), 0); /* no data needed for this 
cmd */

total: 0 errors, 0 warnings, 2 checks, 138 lines checked
434f8395d301 drm/i915/rpm: Enable D3Cold VRAM SR Support
3824ea24e1b1 drm/i915/xehpsdv: Store lmem region in gt
993fde5ec166 drm/i915/rpm: d3cold Policy
-:73: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#73: FILE: drivers/gpu/drm/i915/i915_params.c:201:
+i915_param_named_unsafe(d3cold_sr_lmem_threshold, int, 0400,
+   "Enable Vidoe RAM Self refresh when size of lmem is greater to this 
threshold. "

total: 0 errors, 0 warnings, 1 checks, 58 lines checked

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/display: Add smem fallback allocation for dpt (rev4)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/display: Add smem fallback 
allocation for dpt (rev4)
URL   : https://patchwork.freedesktop.org/series/104983/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11768 -> Patchwork_104983v4


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_104983v4 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_104983v4, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v4/index.html

Participating hosts (43 -> 41)
--

  Additional (2): bat-adlm-1 bat-atsm-1 
  Missing(4): bat-dg2-8 bat-jsl-2 bat-dg2-9 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_104983v4:

### IGT changes ###

 Possible regressions 

  * igt@debugfs_test@read_all_entries:
- fi-kbl-guc: [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-kbl-guc/igt@debugfs_test@read_all_entries.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v4/fi-kbl-guc/igt@debugfs_test@read_all_entries.html

  
Known issues


  Here are the changes found in Patchwork_104983v4 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v4/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@kms_busy@basic@flip:
- fi-tgl-u2:  [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar 
issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-tgl-u2/igt@kms_busy@ba...@flip.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v4/fi-tgl-u2/igt@kms_busy@ba...@flip.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v4/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v4/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- bat-adlp-4: [PASS][9] -> [DMESG-WARN][10] ([i915#3576])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-adlp-4/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v4/bat-adlp-4/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- bat-adlp-4: [DMESG-WARN][11] ([i915#3576]) -> [PASS][12] +3 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-adlp-4/igt@i915_pm_...@module-reload.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v4/bat-adlp-4/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][13] ([i915#3303] / [i915#4785]) -> 
[PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v4/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-g3258:   [INCOMPLETE][15] ([i915#4785]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v4/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_busy@basic@modeset:
- {bat-adlp-6}:   [DMESG-WARN][17] ([i915#3576]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-adlp-6/igt@kms_busy@ba...@modeset.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v4/bat-adlp-6/igt@kms_busy@ba...@modeset.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/display: Add smem fallback allocation for dpt (rev4)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/display: Add smem fallback 
allocation for dpt (rev4)
URL   : https://patchwork.freedesktop.org/series/104983/
State : warning

== Summary ==

Error: dim checkpatch failed
4c23115bcf5b drm/i915/display: Add smem fallback allocation for dpt
4ea7ed8461f9 drm/i915: Fix i915_vma_pin_iomap()
-:48: CHECK:BRACES: Unbalanced braces around else statement
#48: FILE: drivers/gpu/drm/i915/i915_vma.c:573:
+   else {

total: 0 errors, 0 warnings, 1 checks, 72 lines checked
7127125aa4ab drm/i915: don't leak lmem mapping in vma_evict

Re: [Intel-gfx] [PATCH i-g-t 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[kernel test robot]

Hi,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-tip/drm-tip]

url:
https://github.com/intel-lab-lkp/linux/commits/priyanka-dandamudi-intel-com/Add-support-for-LMEM-PCIe-resizable-bar/20220616-201631
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-a013 
(https://download.01.org/0day-ci/archive/20220616/202206162313.aymhl5br-...@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 
f0e608de27b3d56846eebf3712ab542979d6)
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# 
https://github.com/intel-lab-lkp/linux/commit/0242b37c1e2e73134035a0847c34367331f16cca
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review 
priyanka-dandamudi-intel-com/Add-support-for-LMEM-PCIe-resizable-bar/20220616-201631
git checkout 0242b37c1e2e73134035a0847c34367331f16cca
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 
O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot 

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/i915_driver.c:374:44: warning: result of comparison of 
>> constant 4294967296 with expression of type 'resource_size_t' (aka 'unsigned 
>> int') is always false [-Wtautological-constant-out-of-range-compare]
   IORESOURCE_MEM_64) && 
root_res->start > 0x1ull)
 
~~~ ^ ~~
   1 warning generated.


vim +374 drivers/gpu/drm/i915/i915_driver.c

   354  
   355  #define LMEM_BAR_NUM 2
   356  static void i915_resize_lmem_bar(struct drm_i915_private *i915)
   357  {
   358  struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
   359  struct pci_bus *root = pdev->bus;
   360  struct resource *root_res;
   361  resource_size_t rebar_size = __lmem_rebar_size(i915, 
LMEM_BAR_NUM);
   362  u32 pci_cmd;
   363  int i;
   364  
   365  if (!rebar_size)
   366  return;
   367  
   368  /* Find out if root bus contains 64bit memory addressing */
   369  while (root->parent)
   370  root = root->parent;
   371  
   372  pci_bus_for_each_resource(root, root_res, i) {
   373  if (root_res && root_res->flags & (IORESOURCE_MEM |
 > 374  IORESOURCE_MEM_64) && 
 > root_res->start > 0x1ull)
   375  break;
   376  }
   377  
   378  /* pci_resize_resource will fail anyways */
   379  if (!root_res) {
   380  drm_info(>drm, "Can't resize LMEM BAR - platform 
support is missing\n");
   381  return;
   382  }
   383  
   384  /* First disable PCI memory decoding references */
   385  pci_read_config_dword(pdev, PCI_COMMAND, _cmd);
   386  pci_write_config_dword(pdev, PCI_COMMAND,
   387 pci_cmd & ~PCI_COMMAND_MEMORY);
   388  
   389  __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
   390  
   391  pci_assign_unassigned_bus_resources(pdev->bus);
   392  pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
   393  }
   394  

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

Re: [Intel-gfx] [PATCH 3/3] drm/i915/ttm: remove shmem memory region and gem object backend

[kernel test robot]

Hi Adrian,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-tip/drm-tip]

url:
https://github.com/intel-lab-lkp/linux/commits/Adrian-Larumbe/remove-shmem-backend-and-region-and-unify-them-with-TTM/20220614-091628
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-a004 
(https://download.01.org/0day-ci/archive/20220616/202206162323.1npq58gh-...@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 
f0e608de27b3d56846eebf3712ab542979d6)
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# 
https://github.com/intel-lab-lkp/linux/commit/c04ba9928dafe2d5889457af0f770e96da5798e1
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review 
Adrian-Larumbe/remove-shmem-backend-and-region-and-unify-them-with-TTM/20220614-091628
git checkout c04ba9928dafe2d5889457af0f770e96da5798e1
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 
O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot 

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gem/i915_gem_ttm.c:1398: warning: expecting prototype 
>> for intel_region_ttm_shmem_init(). Prototype was for 
>> intel_region_ttm_init_shmem() instead
   drivers/gpu/drm/i915/gem/i915_gem_ttm.c:1419: warning: Function parameter or 
member 'offset' not described in '__i915_gem_ttm_object_init'
   drivers/gpu/drm/i915/gem/i915_gem_ttm.c:1419: warning: Function parameter or 
member 'page_size' not described in '__i915_gem_ttm_object_init'


vim +1398 drivers/gpu/drm/i915/gem/i915_gem_ttm.c

  1390  
  1391  /**
  1392   * intel_region_ttm_shmem_init - Initialize a memory region for TTM.
  1393   * @mem: The region to initialize.
  1394   *
  1395   * Return: 0 on success, negative error code on failure.
  1396   */
  1397  static int intel_region_ttm_init_shmem(struct intel_memory_region *mem)
> 1398  {
  1399  i915_gemfs_init(mem->i915);
  1400  
  1401  return 0; /* Don't error, we can simply fallback to the kernel 
mnt */
  1402  }
  1403  

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Extract, polish, and document multicast handling

[Vudum, Lakshminarayana]

We have a bug for a similar test timeout on KBL
https://gitlab.freedesktop.org/drm/intel/-/issues/6048
igt@kms_cursor_legacy@pipe-b-torture-move - incomplete - Received signal 
SIGQUIT. Per-test timeout exceeded. Killing the current test with SIGQUIT.

Thanks,
Lakshmi.

-Original Message-
From: Roper, Matthew D  
Sent: Wednesday, June 15, 2022 9:34 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana 
Subject: Re: ✗ Fi.CI.IGT: failure for i915: Extract, polish, and document 
multicast handling

On Thu, Jun 16, 2022 at 03:11:40AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: i915: Extract, polish, and document multicast handling
> URL   : https://patchwork.freedesktop.org/series/105134/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_11758_full -> Patchwork_105134v1_full 
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_105134v1_full absolutely need 
> to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_105134v1_full, please notify your bug team to allow 
> them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (13 -> 12)
> --
> 
>   Missing(1): shard-dg1 
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_105134v1_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@kms_cursor_legacy@pipe-c-torture-bo:
> - shard-skl:  [PASS][1] -> [INCOMPLETE][2]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11758/shard-skl2/igt@kms_cursor_leg...@pipe-c-torture-bo.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105134v1/shard-skl4
> /igt@kms_cursor_leg...@pipe-c-torture-bo.html

Appears to be a deadlock:

  <3> [923.922958] INFO: task kms_cursor_lega:1361 blocked for more than 61 
seconds.
  <3> [923.923073]   Tainted: G U  W 
5.19.0-rc2-Patchwork_105134v1-ga2644b16f1f0+ #1
  <3> [923.923104] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables 
this message.

This display test wouldn't be affected by the changes to multicast registers in 
this series, so it seems unrelated.

I don't see any matching issue signatures in gitlab, although there are a 
couple incompletes filed against similar tests due to timeout that might have a 
related root cause (e.g., #6216).


Matt

> 
>   
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * {igt@kms_plane_lowres@tiling-y@pipe-a-edp-1}:
> - {shard-rkl}:NOTRUN -> [SKIP][3] +3 similar issues
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105134v1/shard-rkl-
> 6/igt@kms_plane_lowres@tilin...@pipe-a-edp-1.html
> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_105134v1_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_ctx_persistence@smoketest:
> - shard-apl:  [PASS][4] -> [FAIL][5] ([i915#5099])
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11758/shard-apl7/igt@gem_ctx_persiste...@smoketest.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105134v1/shard-apl1
> /igt@gem_ctx_persiste...@smoketest.html
> 
>   * igt@gem_eio@unwedge-stress:
> - shard-iclb: [PASS][6] -> [TIMEOUT][7] ([i915#3070])
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11758/shard-iclb6/igt@gem_...@unwedge-stress.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105134v1/shard-iclb
> 6/igt@gem_...@unwedge-stress.html
> 
>   * igt@gem_exec_balancer@parallel-keep-submit-fence:
> - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) +2 similar 
> issues
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11758/shard-iclb2/igt@gem_exec_balan...@parallel-keep-submit-fence.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105134v1/shard-iclb
> 8/igt@gem_exec_balan...@parallel-keep-submit-fence.html
> 
>   * igt@gem_exec_fair@basic-none-solo@rcs0:
> - shard-apl:  [PASS][10] -> [FAIL][11] ([i915#2842])
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11758/shard-apl3/igt@gem_exec_fair@basic-none-s...@rcs0.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105134v1/shard-apl6
> /igt@gem_exec_fair@basic-none-s...@rcs0.html
> 
>   * igt@gem_exec_fair@basic-none@vcs1:
> - shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842])
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105134v1/shard-iclb
> 1/igt@gem_exec_fair@basic-n...@vcs1.html
> 
>   * igt@gem_exec_fair@basic-pace-solo@rcs0:
> - shard-iclb: [PASS][13] -> 

[Intel-gfx] [PATCH 2/2] drm/i915: Add lmem_bar_size modparam

[priyanka . dandamudi]

From: Priyanka Dandamudi 

For testing purposes, support forcing the lmem_bar_size through a new
modparam. In CI we only have a limited number of configurations for DG2,
but we still need to be reasonably sure we get a usable device (also
verifying we report the correct values for things like
probed_cpu_visible_size etc) with all the potential lmem_bar sizes that
we might expect see in the wild.

v2: Update commit message and a minor modification.(Matt)

Cc: Matthew Auld 
Signed-off-by: Priyanka Dandamudi 
---
 drivers/gpu/drm/i915/gt/intel_region_lmem.c |  4 +++
 drivers/gpu/drm/i915/i915_driver.c  | 28 -
 drivers/gpu/drm/i915/i915_params.c  |  2 ++
 drivers/gpu/drm/i915/i915_params.h  |  1 +
 4 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c 
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index e9c12e0d6f59..4614c30f878f 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -111,6 +111,10 @@ static struct intel_memory_region *setup_lmem(struct 
intel_gt *gt)
flat_ccs_base = intel_gt_read_register(gt, 
XEHPSDV_FLAT_CCS_BASE_ADDR);
flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * 
SZ_64K;
 
+   /* XXX: Remove this once we have small-bar uapi bits */
+   if (i915->params.lmem_bar_size > 0)
+   lmem_size = pci_resource_len(pdev, 2);
+
/* FIXME: Remove this when we have small-bar enabled */
if (pci_resource_len(pdev, 2) < lmem_size) {
drm_err(>drm, "System requires small-BAR support, 
which is currently unsupported on this kernel\n");
diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index 4bdb471cb2e2..b2763b032012 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -362,8 +362,34 @@ static void i915_resize_lmem_bar(struct drm_i915_private 
*i915)
u32 pci_cmd;
int i;
 
-   if (!rebar_size)
+   if (i915->params.lmem_bar_size > 0) {
+   u32 lmem_bar_size;
+   u32 set_bit;
+   u32 rebar;
+   u32 msb;
+   int k;
+
+   lmem_bar_size = i915->params.lmem_bar_size;
+   rebar = pci_rebar_get_possible_sizes(pdev, LMEM_BAR_NUM);
+   msb = __fls(rebar);
+
+   for (k = msb; k >= 0; k--) {
+   set_bit = (1 << k);
+
+   if (set_bit & rebar) {
+   if (set_bit == lmem_bar_size) {
+   rebar_size = 1ULL << 
(__fls(lmem_bar_size) +
+   BAR_SIZE_SHIFT);
+
+   if (rebar_size == 
pci_resource_len(pdev, LMEM_BAR_NUM))
+   return;
+   break;
+   }
+   }
+   }
+   } else if (!rebar_size) {
return;
+   }
 
/* Find out if root bus contains 64bit memory addressing */
while (root->parent)
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 701fbc98afa0..6fc475a5db61 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -204,6 +204,8 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
 
 i915_param_named_unsafe(lmem_size, uint, 0400,
"Set the lmem size(in MiB) for each region. (default: 
0, all memory)");
+i915_param_named_unsafe(lmem_bar_size, uint, 0400,
+   "Set the lmem bar size(in MiB).");
 
 static __always_inline void _print_param(struct drm_printer *p,
 const char *name,
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index b5e7ea45d191..2733cb6cfe09 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -74,6 +74,7 @@ struct drm_printer;
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
param(unsigned int, request_timeout_ms, 
CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
param(unsigned int, lmem_size, 0, 0400) \
+   param(unsigned int, lmem_bar_size, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, load_detect_test, false, 0600) \
-- 
2.25.1

[Intel-gfx] [PATCH 0/2] Add support for LMEM PCIe resizable bar

[priyanka . dandamudi]

From: Priyanka Dandamudi 

Added support to resize the bar to maximum supported.
Also, added new modparam lmem_bar_size which can resize the bar to one of the 
supported sizes.

Akeem G Abodunrin (1):
  drm/i915: Add support for LMEM PCIe resizable bar

Priyanka Dandamudi (1):
  drm/i915: Add lmem_bar_size modparam

 drivers/gpu/drm/i915/gt/intel_region_lmem.c |   4 +
 drivers/gpu/drm/i915/i915_driver.c  | 118 
 drivers/gpu/drm/i915/i915_params.c  |   2 +
 drivers/gpu/drm/i915/i915_params.h  |   1 +
 4 files changed, 125 insertions(+)

-- 
2.25.1

[Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[priyanka . dandamudi]

From: Akeem G Abodunrin 

Add support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
systems. So, those devices cannot claim larger memory BAR windows size due
to the system BIOS limitation. With this change, it would be possible to
reprogram the windows of the bridge directly above the requesting device
on the same BAR type.

Signed-off-by: Akeem G Abodunrin 
Signed-off-by: Michał Winiarski 
Cc: Stuart Summers 
Cc: Michael J Ruhl 
Cc: Prathap Kumar Valsan 
Signed-off-by: Priyanka Dandamudi 
Reviewed-by: Matthew Auld 
---
 drivers/gpu/drm/i915/i915_driver.c | 92 ++
 1 file changed, 92 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index d26dcca7e654..4bdb471cb2e2 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
__intel_gt_reset(to_gt(i915), ALL_ENGINES);
 }
 
+static void __release_bars(struct pci_dev *pdev)
+{
+   int resno;
+
+   for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
+   if (pci_resource_len(pdev, resno))
+   pci_release_resource(pdev, resno);
+   }
+}
+
+static void
+__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
+{
+   struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+   int bar_size = pci_rebar_bytes_to_size(size);
+   int ret;
+
+   __release_bars(pdev);
+
+   ret = pci_resize_resource(pdev, resno, bar_size);
+   if (ret) {
+   drm_info(>drm, "Failed to resize BAR%d to %dM (%pe)\n",
+resno, 1 << bar_size, ERR_PTR(ret));
+   return;
+   }
+
+   drm_info(>drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
+}
+
+/* BAR size starts from 1MB - 2^20 */
+#define BAR_SIZE_SHIFT 20
+static resource_size_t
+__lmem_rebar_size(struct drm_i915_private *i915, int resno)
+{
+   struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+   u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
+   resource_size_t size;
+
+   if (!rebar)
+   return 0;
+
+   size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
+
+   if (size <= pci_resource_len(pdev, resno))
+   return 0;
+
+   return size;
+}
+
+#define LMEM_BAR_NUM 2
+static void i915_resize_lmem_bar(struct drm_i915_private *i915)
+{
+   struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+   struct pci_bus *root = pdev->bus;
+   struct resource *root_res;
+   resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
+   u32 pci_cmd;
+   int i;
+
+   if (!rebar_size)
+   return;
+
+   /* Find out if root bus contains 64bit memory addressing */
+   while (root->parent)
+   root = root->parent;
+
+   pci_bus_for_each_resource(root, root_res, i) {
+   if (root_res && root_res->flags & (IORESOURCE_MEM |
+   IORESOURCE_MEM_64) && root_res->start > 
0x1ull)
+   break;
+   }
+
+   /* pci_resize_resource will fail anyways */
+   if (!root_res) {
+   drm_info(>drm, "Can't resize LMEM BAR - platform support 
is missing\n");
+   return;
+   }
+
+   /* First disable PCI memory decoding references */
+   pci_read_config_dword(pdev, PCI_COMMAND, _cmd);
+   pci_write_config_dword(pdev, PCI_COMMAND,
+  pci_cmd & ~PCI_COMMAND_MEMORY);
+
+   __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
+
+   pci_assign_unassigned_bus_resources(pdev->bus);
+   pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
+}
+
 /**
  * i915_driver_early_probe - setup state not requiring device access
  * @dev_priv: device private
@@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct 
pci_device_id *ent)
 
disable_rpm_wakeref_asserts(>runtime_pm);
 
+   if (HAS_LMEM(i915))
+   i915_resize_lmem_bar(i915);
+
intel_vgpu_detect(i915);
 
ret = intel_gt_probe_all(i915);
-- 
2.25.1

Re: [Intel-gfx] [PATCH i-g-t 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[Jani Nikula]

On Thu, 16 Jun 2022, priyanka.dandam...@intel.com wrote:
> From: Akeem G Abodunrin 
>
> This patch adds support for the local memory PICe resizable bar, so that

Please use imperative. "Add support ..."

Please don't refer to "this patch".

Please fix your git settings to not prefix with "i-g-t" when sending
i915 changes.

BR,
Jani.

> local memory can be resized to the maximum size supported by the device,
> and mapped correctly to the PCIe memory bar. It is usual that GPU
> devices expose only 256MB BARs primarily to be compatible with 32-bit
> systems. So, those devices cannot claim larger memory BAR windows size due
> to the system BIOS limitation. With this change, it would be possible to
> reprogram the windows of the bridge directly above the requesting device
> on the same BAR type.
>
> Signed-off-by: Akeem G Abodunrin 
> Signed-off-by: Michał Winiarski 
> Cc: Stuart Summers 
> Cc: Michael J Ruhl 
> Cc: Prathap Kumar Valsan 
> Signed-off-by: Priyanka Dandamudi 
> Reviewed-by: Matthew Auld 
> ---
>  drivers/gpu/drm/i915/i915_driver.c | 92 ++
>  1 file changed, 92 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c 
> b/drivers/gpu/drm/i915/i915_driver.c
> index d26dcca7e654..4bdb471cb2e2 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
>   __intel_gt_reset(to_gt(i915), ALL_ENGINES);
>  }
>  
> +static void __release_bars(struct pci_dev *pdev)
> +{
> + int resno;
> +
> + for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
> + if (pci_resource_len(pdev, resno))
> + pci_release_resource(pdev, resno);
> + }
> +}
> +
> +static void
> +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + int bar_size = pci_rebar_bytes_to_size(size);
> + int ret;
> +
> + __release_bars(pdev);
> +
> + ret = pci_resize_resource(pdev, resno, bar_size);
> + if (ret) {
> + drm_info(>drm, "Failed to resize BAR%d to %dM (%pe)\n",
> +  resno, 1 << bar_size, ERR_PTR(ret));
> + return;
> + }
> +
> + drm_info(>drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
> +}
> +
> +/* BAR size starts from 1MB - 2^20 */
> +#define BAR_SIZE_SHIFT 20
> +static resource_size_t
> +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
> + resource_size_t size;
> +
> + if (!rebar)
> + return 0;
> +
> + size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
> +
> + if (size <= pci_resource_len(pdev, resno))
> + return 0;
> +
> + return size;
> +}
> +
> +#define LMEM_BAR_NUM 2
> +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + struct pci_bus *root = pdev->bus;
> + struct resource *root_res;
> + resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
> + u32 pci_cmd;
> + int i;
> +
> + if (!rebar_size)
> + return;
> +
> + /* Find out if root bus contains 64bit memory addressing */
> + while (root->parent)
> + root = root->parent;
> +
> + pci_bus_for_each_resource(root, root_res, i) {
> + if (root_res && root_res->flags & (IORESOURCE_MEM |
> + IORESOURCE_MEM_64) && root_res->start > 
> 0x1ull)
> + break;
> + }
> +
> + /* pci_resize_resource will fail anyways */
> + if (!root_res) {
> + drm_info(>drm, "Can't resize LMEM BAR - platform support 
> is missing\n");
> + return;
> + }
> +
> + /* First disable PCI memory decoding references */
> + pci_read_config_dword(pdev, PCI_COMMAND, _cmd);
> + pci_write_config_dword(pdev, PCI_COMMAND,
> +pci_cmd & ~PCI_COMMAND_MEMORY);
> +
> + __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
> +
> + pci_assign_unassigned_bus_resources(pdev->bus);
> + pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
> +}
> +
>  /**
>   * i915_driver_early_probe - setup state not requiring device access
>   * @dev_priv: device private
> @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct 
> pci_device_id *ent)
>  
>   disable_rpm_wakeref_asserts(>runtime_pm);
>  
> + if (HAS_LMEM(i915))
> + i915_resize_lmem_bar(i915);
> +
>   intel_vgpu_detect(i915);
>  
>   ret = intel_gt_probe_all(i915);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH i-g-t 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[Jani Nikula]

On Thu, 16 Jun 2022, priyanka.dandam...@intel.com wrote:
> From: Akeem G Abodunrin 
>
> This patch adds support for the local memory PICe resizable bar, so that
> local memory can be resized to the maximum size supported by the device,
> and mapped correctly to the PCIe memory bar. It is usual that GPU
> devices expose only 256MB BARs primarily to be compatible with 32-bit
> systems. So, those devices cannot claim larger memory BAR windows size due
> to the system BIOS limitation. With this change, it would be possible to
> reprogram the windows of the bridge directly above the requesting device
> on the same BAR type.
>
> Signed-off-by: Akeem G Abodunrin 
> Signed-off-by: Michał Winiarski 
> Cc: Stuart Summers 
> Cc: Michael J Ruhl 
> Cc: Prathap Kumar Valsan 
> Signed-off-by: Priyanka Dandamudi 
> Reviewed-by: Matthew Auld 
> ---
>  drivers/gpu/drm/i915/i915_driver.c | 92 ++
>  1 file changed, 92 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c 
> b/drivers/gpu/drm/i915/i915_driver.c
> index d26dcca7e654..4bdb471cb2e2 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
>   __intel_gt_reset(to_gt(i915), ALL_ENGINES);
>  }
>  
> +static void __release_bars(struct pci_dev *pdev)

What's with the double underscores? 

> +{
> + int resno;
> +
> + for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
> + if (pci_resource_len(pdev, resno))
> + pci_release_resource(pdev, resno);
> + }
> +}
> +
> +static void
> +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + int bar_size = pci_rebar_bytes_to_size(size);
> + int ret;
> +
> + __release_bars(pdev);
> +
> + ret = pci_resize_resource(pdev, resno, bar_size);
> + if (ret) {
> + drm_info(>drm, "Failed to resize BAR%d to %dM (%pe)\n",
> +  resno, 1 << bar_size, ERR_PTR(ret));
> + return;
> + }
> +
> + drm_info(>drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
> +}
> +
> +/* BAR size starts from 1MB - 2^20 */
> +#define BAR_SIZE_SHIFT 20
> +static resource_size_t
> +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
> + resource_size_t size;
> +
> + if (!rebar)
> + return 0;
> +
> + size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
> +
> + if (size <= pci_resource_len(pdev, resno))
> + return 0;
> +
> + return size;
> +}
> +
> +#define LMEM_BAR_NUM 2
> +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + struct pci_bus *root = pdev->bus;
> + struct resource *root_res;
> + resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
> + u32 pci_cmd;
> + int i;
> +
> + if (!rebar_size)
> + return;
> +
> + /* Find out if root bus contains 64bit memory addressing */
> + while (root->parent)
> + root = root->parent;
> +
> + pci_bus_for_each_resource(root, root_res, i) {
> + if (root_res && root_res->flags & (IORESOURCE_MEM |
> + IORESOURCE_MEM_64) && root_res->start > 
> 0x1ull)
> + break;
> + }
> +
> + /* pci_resize_resource will fail anyways */
> + if (!root_res) {
> + drm_info(>drm, "Can't resize LMEM BAR - platform support 
> is missing\n");
> + return;
> + }
> +
> + /* First disable PCI memory decoding references */
> + pci_read_config_dword(pdev, PCI_COMMAND, _cmd);
> + pci_write_config_dword(pdev, PCI_COMMAND,
> +pci_cmd & ~PCI_COMMAND_MEMORY);
> +
> + __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
> +
> + pci_assign_unassigned_bus_resources(pdev->bus);
> + pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
> +}

Doesn't feel like the above code belongs in this file. The file is
supposed to be very high level. The mchbar stuff is the only low level
thing here, and that feels out of place too. Maybe this and the mchbar
stuff belong in a new file.

BR,
Jani.


> +
>  /**
>   * i915_driver_early_probe - setup state not requiring device access
>   * @dev_priv: device private
> @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct 
> pci_device_id *ent)
>  
>   disable_rpm_wakeref_asserts(>runtime_pm);
>  
> + if (HAS_LMEM(i915))
> + i915_resize_lmem_bar(i915);
> +
>   intel_vgpu_detect(i915);
>  
>   ret = intel_gt_probe_all(i915);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 3/3] drm/i915/ttm: remove shmem memory region and gem object backend

[kernel test robot]

Hi Adrian,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-tip/drm-tip]

url:
https://github.com/intel-lab-lkp/linux/commits/Adrian-Larumbe/remove-shmem-backend-and-region-and-unify-them-with-TTM/20220614-091628
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-defconfig 
(https://download.01.org/0day-ci/archive/20220616/202206162239.am4qoo2c-...@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-3) 11.3.0
reproduce (this is a W=1 build):
# 
https://github.com/intel-lab-lkp/linux/commit/c04ba9928dafe2d5889457af0f770e96da5798e1
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review 
Adrian-Larumbe/remove-shmem-backend-and-region-and-unify-them-with-TTM/20220614-091628
git checkout c04ba9928dafe2d5889457af0f770e96da5798e1
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot 

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gem/i915_gem_ttm.c:1398: warning: expecting prototype 
>> for intel_region_ttm_shmem_init(). Prototype was for 
>> intel_region_ttm_init_shmem() instead
   drivers/gpu/drm/i915/gem/i915_gem_ttm.c:1419: warning: Function parameter or 
member 'offset' not described in '__i915_gem_ttm_object_init'
   drivers/gpu/drm/i915/gem/i915_gem_ttm.c:1419: warning: Function parameter or 
member 'page_size' not described in '__i915_gem_ttm_object_init'


vim +1398 drivers/gpu/drm/i915/gem/i915_gem_ttm.c

  1390  
  1391  /**
  1392   * intel_region_ttm_shmem_init - Initialize a memory region for TTM.
  1393   * @mem: The region to initialize.
  1394   *
  1395   * Return: 0 on success, negative error code on failure.
  1396   */
  1397  static int intel_region_ttm_init_shmem(struct intel_memory_region *mem)
> 1398  {
  1399  i915_gemfs_init(mem->i915);
  1400  
  1401  return 0; /* Don't error, we can simply fallback to the kernel 
mnt */
  1402  }
  1403  

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Jani Nikula]

On Thu, 16 Jun 2022, Tvrtko Ursulin  wrote:
> On 16/06/2022 15:15, Jani Nikula wrote:
>> On Thu, 16 Jun 2022, Tvrtko Ursulin  wrote:
>>> On 16/06/2022 13:01, Anshuman Gupta wrote:
 DG2 NB SKU need to distinguish between MBD and AIC to probe
 the VRAM Self Refresh feature support. Adding those sub platform
 accordingly.

 Cc: Matt Roper 
 Signed-off-by: Anshuman Gupta 
 ---
drivers/gpu/drm/i915/i915_drv.h  |  3 +++
drivers/gpu/drm/i915/intel_device_info.c | 21 +
drivers/gpu/drm/i915/intel_device_info.h | 11 +++
include/drm/i915_pciids.h| 23 ---
4 files changed, 47 insertions(+), 11 deletions(-)

 diff --git a/drivers/gpu/drm/i915/i915_drv.h 
 b/drivers/gpu/drm/i915/i915_drv.h
 index a5bc6a774c5a..f1f8699eedfd 100644
 --- a/drivers/gpu/drm/i915/i915_drv.h
 +++ b/drivers/gpu/drm/i915/i915_drv.h
 @@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, 
 INTEL_PONTEVECCHIO)

#define IS_DG2_G10(dev_priv) \
 +  IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
#define IS_DG2_G11(dev_priv) \
 +  IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
#define IS_DG2_G12(dev_priv) \
 +  IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
#define IS_ADLS_RPLS(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, 
 INTEL_SUBPLATFORM_RPL)
 diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
 b/drivers/gpu/drm/i915/intel_device_info.c
 index f0bf23726ed8..93da555adc4e 100644
 --- a/drivers/gpu/drm/i915/intel_device_info.c
 +++ b/drivers/gpu/drm/i915/intel_device_info.c
 @@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
INTEL_RPLP_IDS(0),
};

 +static const u16 subplatform_g10_mb_mbd_ids[] = {
 +  INTEL_DG2_G10_NB_MBD_IDS(0),
 +};
 +
 +static const u16 subplatform_g11_mb_mbd_ids[] = {
 +  INTEL_DG2_G11_NB_MBD_IDS(0),
 +};
 +
 +static const u16 subplatform_g12_mb_mbd_ids[] = {
 +  INTEL_DG2_G12_NB_MBD_IDS(0),
 +};
 +
static const u16 subplatform_g10_ids[] = {
INTEL_DG2_G10_IDS(0),
INTEL_ATS_M150_IDS(0),
 @@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct 
 drm_i915_private *i915)
} else if (find_devid(devid, subplatform_rpl_ids,
  ARRAY_SIZE(subplatform_rpl_ids))) {
mask = BIT(INTEL_SUBPLATFORM_RPL);
 +  } else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
 +ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
 +  mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
 +  } else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
 +ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
 +  mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
 +  } else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
 +ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
 +  mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);
} else if (find_devid(devid, subplatform_g10_ids,
  ARRAY_SIZE(subplatform_g10_ids))) {
mask = BIT(INTEL_SUBPLATFORM_G10);
 diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
 b/drivers/gpu/drm/i915/intel_device_info.h
 index 08341174ee0a..c929e2d7e59c 100644
 --- a/drivers/gpu/drm/i915/intel_device_info.h
 +++ b/drivers/gpu/drm/i915/intel_device_info.h
 @@ -97,7 +97,7 @@ enum intel_platform {
 * it is fine for the same bit to be used on multiple parent platforms.
 */

 -#define INTEL_SUBPLATFORM_BITS (3)
 +#define INTEL_SUBPLATFORM_BITS (6)
#define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)

/* HSW/BDW/SKL/KBL/CFL */
 @@ -111,9 +111,12 @@ enum intel_platform {
#define INTEL_SUBPLATFORM_UY(0)

/* DG2 */
 -#define INTEL_SUBPLATFORM_G10 0
 -#define INTEL_SUBPLATFORM_G11 1
 -#define INTEL_SUBPLATFORM_G12 2
 +#define INTEL_SUBPLATFORM_G10_NB_MBD  0
 +#define INTEL_SUBPLATFORM_G11_NB_MBD  1
 +#define INTEL_SUBPLATFORM_G12_NB_MBD  2
 +#define INTEL_SUBPLATFORM_G10 3
 +#define INTEL_SUBPLATFORM_G11 4
 +#define INTEL_SUBPLATFORM_G12 5
>>>
>>> Ugh I feel this "breaks" the subplatform idea.. feels like it is just
>>> too many bits 

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Tvrtko Ursulin]

On 16/06/2022 15:15, Jani Nikula wrote:

On Thu, 16 Jun 2022, Tvrtko Ursulin  wrote:

On 16/06/2022 13:01, Anshuman Gupta wrote:

DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.

Cc: Matt Roper 
Signed-off-by: Anshuman Gupta 
---
   drivers/gpu/drm/i915/i915_drv.h  |  3 +++
   drivers/gpu/drm/i915/intel_device_info.c | 21 +
   drivers/gpu/drm/i915/intel_device_info.h | 11 +++
   include/drm/i915_pciids.h| 23 ---
   4 files changed, 47 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a5bc6a774c5a..f1f8699eedfd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
   #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
   
   #define IS_DG2_G10(dev_priv) \

+   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
   #define IS_DG2_G11(dev_priv) \
+   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
   #define IS_DG2_G12(dev_priv) \
+   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
   #define IS_ADLS_RPLS(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index f0bf23726ed8..93da555adc4e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
INTEL_RPLP_IDS(0),
   };
   
+static const u16 subplatform_g10_mb_mbd_ids[] = {

+   INTEL_DG2_G10_NB_MBD_IDS(0),
+};
+
+static const u16 subplatform_g11_mb_mbd_ids[] = {
+   INTEL_DG2_G11_NB_MBD_IDS(0),
+};
+
+static const u16 subplatform_g12_mb_mbd_ids[] = {
+   INTEL_DG2_G12_NB_MBD_IDS(0),
+};
+
   static const u16 subplatform_g10_ids[] = {
INTEL_DG2_G10_IDS(0),
INTEL_ATS_M150_IDS(0),
@@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct 
drm_i915_private *i915)
} else if (find_devid(devid, subplatform_rpl_ids,
  ARRAY_SIZE(subplatform_rpl_ids))) {
mask = BIT(INTEL_SUBPLATFORM_RPL);
+   } else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
+ ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
+   mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
+   } else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
+ ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
+   mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
+   } else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
+ ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
+   mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);
} else if (find_devid(devid, subplatform_g10_ids,
  ARRAY_SIZE(subplatform_g10_ids))) {
mask = BIT(INTEL_SUBPLATFORM_G10);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 08341174ee0a..c929e2d7e59c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -97,7 +97,7 @@ enum intel_platform {
* it is fine for the same bit to be used on multiple parent platforms.
*/
   
-#define INTEL_SUBPLATFORM_BITS (3)

+#define INTEL_SUBPLATFORM_BITS (6)
   #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
   
   /* HSW/BDW/SKL/KBL/CFL */

@@ -111,9 +111,12 @@ enum intel_platform {
   #define INTEL_SUBPLATFORM_UY (0)
   
   /* DG2 */

-#define INTEL_SUBPLATFORM_G10  0
-#define INTEL_SUBPLATFORM_G11  1
-#define INTEL_SUBPLATFORM_G12  2
+#define INTEL_SUBPLATFORM_G10_NB_MBD   0
+#define INTEL_SUBPLATFORM_G11_NB_MBD   1
+#define INTEL_SUBPLATFORM_G12_NB_MBD   2
+#define INTEL_SUBPLATFORM_G10  3
+#define INTEL_SUBPLATFORM_G11  4
+#define INTEL_SUBPLATFORM_G12  5


Ugh I feel this "breaks" the subplatform idea.. feels like it is just
too many bits when two separate sets of information get tracked (Gxx
plus MBD).


I think they could be specified independent of each other, though. The
subplatform if-else ladder would have to be replaced with independent
ifs. You'd have the G10/G11/G12 and 1 bit separately for MBD.

Only the macros for PCI IDs need to be separate (MBD vs not). You'll
then have:

static const u16 subplatform_g10_ids[] = {
INTEL_DG2_G10_IDS(0),
INTEL_DG2_G10_NB_MBD_IDS(0),
INTEL_ATS_M150_IDS(0),
};

Ditto for g11 and g12, and separately:

static const u16 

Re: [Intel-gfx] [PATCH v2 7/9] drm/i915/rpm: Enable D3Cold VRAM SR Support

[Jani Nikula]

On Thu, 16 Jun 2022, Anshuman Gupta  wrote:
> Intel Client DGFX card supports D3Cold with two option.
> D3Cold-off zero watt, D3Cold-VRAM Self Refresh.
>
> i915 requires to evict the lmem objects to smem in order to
> support D3Cold-Off, which increases i915 the suspend/resume
> latency. Enabling VRAM Self Refresh feature optimize the
> latency with additional power cost which required to retain
> the lmem.
>
> Adding intel_runtime_idle (runtime_idle callback) to enable
> VRAM_SR, it will be used for policy to choose
> between D3Cold-off vs D3Cold-VRAM_SR.
>
> Since we have introduced i915 runtime_idle callback.
> It need to be warranted that Runtime PM Core invokes runtime_idle
> callback when runtime usages count becomes zero. That requires
> to use pm_runtime_put instead of pm_runtime_put_autosuspend.
>
> TODO: GuC interface state save/restore.
>
> Cc: Rodrigo Vivi 
> Cc: Chris Wilson 
> Signed-off-by: Anshuman Gupta 
> ---
>  drivers/gpu/drm/i915/i915_driver.c  | 26 +
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  3 +--
>  2 files changed, 27 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c 
> b/drivers/gpu/drm/i915/i915_driver.c
> index aa1fb15b1f11..fcff5f3fe05e 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -1557,6 +1557,31 @@ static int i915_pm_restore(struct device *kdev)
>   return i915_pm_resume(kdev);
>  }
>  
> +static int intel_runtime_idle(struct device *kdev)
> +{
> + struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> + int ret = 1;
> +
> + if (!HAS_LMEM_SR(dev_priv)) {
> + /*TODO: Prepare for D3Cold-Off */
> + goto out;
> + }
> +
> + disable_rpm_wakeref_asserts(_priv->runtime_pm);
> +
> + ret = intel_pm_vram_sr(dev_priv, true);
> + if (!ret)
> + drm_dbg(_priv->drm, "VRAM Self Refresh enabled\n");

Please add the debug in the intel_pm_vram_sr() function instead.

BR,
Jani.

> +
> + enable_rpm_wakeref_asserts(_priv->runtime_pm);
> +
> +out:
> + pm_runtime_mark_last_busy(kdev);
> + pm_runtime_autosuspend(kdev);
> +
> + return ret;
> +}
> +
>  static int intel_runtime_suspend(struct device *kdev)
>  {
>   struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> @@ -1742,6 +1767,7 @@ const struct dev_pm_ops i915_pm_ops = {
>   .restore = i915_pm_restore,
>  
>   /* S0ix (via runtime suspend) event handlers */
> + .runtime_idle = intel_runtime_idle,
>   .runtime_suspend = intel_runtime_suspend,
>   .runtime_resume = intel_runtime_resume,
>  };
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 6ed5786bcd29..4dade7e8a795 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -492,8 +492,7 @@ static void __intel_runtime_pm_put(struct 
> intel_runtime_pm *rpm,
>  
>   intel_runtime_pm_release(rpm, wakelock);
>  
> - pm_runtime_mark_last_busy(kdev);
> - pm_runtime_put_autosuspend(kdev);
> + pm_runtime_put(kdev);
>  }
>  
>  /**

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 8/9] drm/i915/xehpsdv: Store lmem region in gt

[Jani Nikula]

On Thu, 16 Jun 2022, Anshuman Gupta  wrote:
> From: Tvrtko Ursulin 
>
> Store a pointer to respective local memory region in intel_gt so it can be
> used when memory local to a GT needs to be allocated.
>
> Cc: Andi Shyti 
> Signed-off-by: Tvrtko Ursulin 
> Signed-off-by: Anshuman Gupta 
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c   | 1 +
>  drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
>  2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index f33290358c51..7a535f670ae1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -91,6 +91,7 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
>   GEM_BUG_ON(!HAS_REGION(i915, id));
>   GEM_BUG_ON(i915->mm.regions[id]);
>   i915->mm.regions[id] = mem;
> + gt->lmem = mem;
>  
>   return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index df708802889d..cd7744eaaeaa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -23,6 +23,7 @@
>  #include "intel_gt_buffer_pool_types.h"
>  #include "intel_hwconfig.h"
>  #include "intel_llc_types.h"
> +#include "intel_memory_region.h"

Please never add includes in headers when a forward declaration is
sufficient. I'm spending a lot of time trying to reduce the include
dependencies we have.

BR,
Jani.

>  #include "intel_reset_types.h"
>  #include "intel_rc6_types.h"
>  #include "intel_rps_types.h"
> @@ -202,6 +203,8 @@ struct intel_gt {
>*/
>   phys_addr_t phys_addr;
>  
> + struct intel_memory_region *lmem;
> +
>   struct intel_gt_info {
>   unsigned int id;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Extract intel_sanitize_fifo_underrun_reporting()

[Ville Syrjälä]

On Thu, Jun 16, 2022 at 01:52:38PM +0300, Jani Nikula wrote:
> On Wed, 15 Jun 2022, Ville Syrjala  wrote:
> > From: Ville Syrjälä 
> >
> > Pull the underrun status sanitation into its own helper.
> >
> > Signed-off-by: Ville Syrjälä 
> 
> On the series,
> 
> Reviewed-by: Jani Nikula 

Thanks.

> 
> I'll respin my state readout extraction on top of this once you've
> merged.

Pushed now.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 3/3] drm/i915/bios: Introduce panel_bits() and panel_bool()

[Ville Syrjälä]

On Thu, Jun 16, 2022 at 01:48:16PM +0300, Jani Nikula wrote:
> On Wed, 15 Jun 2022, Ville Syrjala  wrote:
> > From: Ville Syrjälä 
> >
> > Abstract the bit extraction from the VBT per-panel bitfields
> > slightly.
> >
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/display/intel_bios.c | 31 +--
> >  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  3 --
> >  2 files changed, 21 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index 807184fd5618..76e86358adb9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -743,6 +743,16 @@ static int get_panel_type(struct drm_i915_private 
> > *i915,
> > return panel_types[i].panel_type;
> >  }
> >  
> > +static unsigned int panel_bits(unsigned int value, int panel_type, int 
> > num_bits)
> > +{
> > +   return (value >> (panel_type * num_bits)) & (BIT(num_bits) - 1);
> 
> Nitpick, this might be easier to parse with GENMASK and friends, but
> *shrug*.

Pondered about it a bit myself, but decided to keep the current
form for the time being at least.

> Reviewed-by: Jani Nikula 

Ta. Series pushed.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v2 9/9] drm/i915/rpm: d3cold Policy

[Jani Nikula]

On Thu, 16 Jun 2022, Anshuman Gupta  wrote:
> Add d3cold_sr_lmem_threshold modparam to choose between
> d3cold-off zero watt and d3cold-VRAM Self Refresh.
> i915 requires to evict the lmem objects to smem in order to
> support d3cold-Off.
>
> If gfx root port is not capable of sending PME from d3cold
> then i915 don't need to program d3cold-off/d3cold-vram_sr
> sequence.
>
> FIXME: Eviction of lmem objects in case of D3Cold off is wip.
>
> Cc: Rodrigo Vivi 
> Signed-off-by: Anshuman Gupta 
> ---
>  drivers/gpu/drm/i915/i915_driver.c | 27 ---
>  drivers/gpu/drm/i915/i915_params.c |  4 
>  drivers/gpu/drm/i915/i915_params.h |  3 ++-
>  3 files changed, 30 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c 
> b/drivers/gpu/drm/i915/i915_driver.c
> index fcff5f3fe05e..aef4b17efdbe 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -1560,15 +1560,36 @@ static int i915_pm_restore(struct device *kdev)
>  static int intel_runtime_idle(struct device *kdev)
>  {
>   struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> + struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> + u64 lmem_total = to_gt(dev_priv)->lmem->total;
> + u64 lmem_avail = to_gt(dev_priv)->lmem->avail;
> + u64 lmem_used = lmem_total - lmem_avail;
> + struct pci_dev *root_pdev;
>   int ret = 1;
>  
> - if (!HAS_LMEM_SR(dev_priv)) {
> - /*TODO: Prepare for D3Cold-Off */
> + root_pdev = pcie_find_root_port(pdev);
> + if (!root_pdev)
> + goto out;
> +
> + if (!pci_pme_capable(root_pdev, PCI_D3cold))
>   goto out;
> - }
>  
>   disable_rpm_wakeref_asserts(_priv->runtime_pm);
>  
> + if (lmem_used < dev_priv->params.d3cold_sr_lmem_threshold  * 1024 * 
> 1024) {
> + drm_dbg(_priv->drm, "Prepare for D3Cold off\n");
> + pci_d3cold_enable(root_pdev);
> + /* FIXME: Eviction of lmem objects and guc reset is wip */
> + intel_pm_vram_sr(dev_priv, false);
> + enable_rpm_wakeref_asserts(_priv->runtime_pm);
> + goto out;
> + } else if (!HAS_LMEM_SR(dev_priv)) {
> + /* Disable D3Cold to reduce the eviction latency */
> + pci_d3cold_disable(root_pdev);
> + enable_rpm_wakeref_asserts(_priv->runtime_pm);
> + goto out;
> + }

This is *way* too low level code for such high level function. This
needs to be abstracted better.

> +
>   ret = intel_pm_vram_sr(dev_priv, true);
>   if (!ret)
>   drm_dbg(_priv->drm, "VRAM Self Refresh enabled\n");
> diff --git a/drivers/gpu/drm/i915/i915_params.c 
> b/drivers/gpu/drm/i915/i915_params.c
> index 701fbc98afa0..6c6b3c372d4d 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -197,6 +197,10 @@ i915_param_named(enable_gvt, bool, 0400,
>   "Enable support for Intel GVT-g graphics virtualization host 
> support(default:false)");
>  #endif
>  
> +i915_param_named_unsafe(d3cold_sr_lmem_threshold, int, 0400,
> + "Enable Vidoe RAM Self refresh when size of lmem is greater to this 
> threshold. "
> + "It helps to optimize the suspend/resume latecy. (default: 300mb)");
> +
>  #if CONFIG_DRM_I915_REQUEST_TIMEOUT
>  i915_param_named_unsafe(request_timeout_ms, uint, 0600,
>   "Default request/fence/batch buffer expiration 
> timeout.");
> diff --git a/drivers/gpu/drm/i915/i915_params.h 
> b/drivers/gpu/drm/i915/i915_params.h
> index b5e7ea45d191..28f20ebaf41f 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -83,7 +83,8 @@ struct drm_printer;
>   param(bool, verbose_state_checks, true, 0) \
>   param(bool, nuclear_pageflip, false, 0400) \
>   param(bool, enable_dp_mst, true, 0600) \
> - param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 
> 0)
> + param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 
> 0) \
> + param(int, d3cold_sr_lmem_threshold, 300, 0600) \

What's the point of the parameter?

Also, please read the comment /* leave bools at the end to not create
holes */ above.


BR,
Jani.


>  
>  #define MEMBER(T, member, ...) T member;
>  struct i915_params {

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH] drm/i915/fdinfo: Don't show engine classes not present

[Umesh Nerlige Ramappa]

On Thu, Jun 16, 2022 at 03:00:56PM +0100, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

Stop displaying engine classes with no engines - it is not a huge problem
if they are shown, since the values will correctly be all zeroes, but it
does count as misleading.

Signed-off-by: Tvrtko Ursulin 
Fixes: 055634e4b62f ("drm/i915: Expose client engine utilisation via fdinfo")
Cc: Umesh Nerlige Ramappa 
---
drivers/gpu/drm/i915/i915_drm_client.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drm_client.c 
b/drivers/gpu/drm/i915/i915_drm_client.c
index 18d38cb59923..b09d1d386574 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -116,8 +116,9 @@ show_client_class(struct seq_file *m,
total += busy_add(ctx, class);
rcu_read_unlock();

-   seq_printf(m, "drm-engine-%s:\t%llu ns\n",
-  uabi_class_names[class], total);
+   if (capacity)
+   seq_printf(m, "drm-engine-%s:\t%llu ns\n",
+  uabi_class_names[class], total);


Reviewed-by: Umesh Nerlige Ramappa 

Regards,
Umesh


if (capacity > 1)
seq_printf(m, "drm-engine-capacity-%s:\t%u\n",
--
2.34.1

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Jani Nikula]

On Thu, 16 Jun 2022, Tvrtko Ursulin  wrote:
> On 16/06/2022 13:01, Anshuman Gupta wrote:
>> DG2 NB SKU need to distinguish between MBD and AIC to probe
>> the VRAM Self Refresh feature support. Adding those sub platform
>> accordingly.
>> 
>> Cc: Matt Roper 
>> Signed-off-by: Anshuman Gupta 
>> ---
>>   drivers/gpu/drm/i915/i915_drv.h  |  3 +++
>>   drivers/gpu/drm/i915/intel_device_info.c | 21 +
>>   drivers/gpu/drm/i915/intel_device_info.h | 11 +++
>>   include/drm/i915_pciids.h| 23 ---
>>   4 files changed, 47 insertions(+), 11 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index a5bc6a774c5a..f1f8699eedfd 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>   #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
>>   
>>   #define IS_DG2_G10(dev_priv) \
>> +IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
>>  IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
>>   #define IS_DG2_G11(dev_priv) \
>> +IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \
>>  IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
>>   #define IS_DG2_G12(dev_priv) \
>> +IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
>>  IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
>>   #define IS_ADLS_RPLS(dev_priv) \
>>  IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
>> b/drivers/gpu/drm/i915/intel_device_info.c
>> index f0bf23726ed8..93da555adc4e 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
>>  INTEL_RPLP_IDS(0),
>>   };
>>   
>> +static const u16 subplatform_g10_mb_mbd_ids[] = {
>> +INTEL_DG2_G10_NB_MBD_IDS(0),
>> +};
>> +
>> +static const u16 subplatform_g11_mb_mbd_ids[] = {
>> +INTEL_DG2_G11_NB_MBD_IDS(0),
>> +};
>> +
>> +static const u16 subplatform_g12_mb_mbd_ids[] = {
>> +INTEL_DG2_G12_NB_MBD_IDS(0),
>> +};
>> +
>>   static const u16 subplatform_g10_ids[] = {
>>  INTEL_DG2_G10_IDS(0),
>>  INTEL_ATS_M150_IDS(0),
>> @@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct 
>> drm_i915_private *i915)
>>  } else if (find_devid(devid, subplatform_rpl_ids,
>>ARRAY_SIZE(subplatform_rpl_ids))) {
>>  mask = BIT(INTEL_SUBPLATFORM_RPL);
>> +} else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
>> +  ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
>> +mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
>> +} else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
>> +  ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
>> +mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
>> +} else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
>> +  ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
>> +mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);
>>  } else if (find_devid(devid, subplatform_g10_ids,
>>ARRAY_SIZE(subplatform_g10_ids))) {
>>  mask = BIT(INTEL_SUBPLATFORM_G10);
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
>> b/drivers/gpu/drm/i915/intel_device_info.h
>> index 08341174ee0a..c929e2d7e59c 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -97,7 +97,7 @@ enum intel_platform {
>>* it is fine for the same bit to be used on multiple parent platforms.
>>*/
>>   
>> -#define INTEL_SUBPLATFORM_BITS (3)
>> +#define INTEL_SUBPLATFORM_BITS (6)
>>   #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
>>   
>>   /* HSW/BDW/SKL/KBL/CFL */
>> @@ -111,9 +111,12 @@ enum intel_platform {
>>   #define INTEL_SUBPLATFORM_UY   (0)
>>   
>>   /* DG2 */
>> -#define INTEL_SUBPLATFORM_G10   0
>> -#define INTEL_SUBPLATFORM_G11   1
>> -#define INTEL_SUBPLATFORM_G12   2
>> +#define INTEL_SUBPLATFORM_G10_NB_MBD0
>> +#define INTEL_SUBPLATFORM_G11_NB_MBD1
>> +#define INTEL_SUBPLATFORM_G12_NB_MBD2
>> +#define INTEL_SUBPLATFORM_G10   3
>> +#define INTEL_SUBPLATFORM_G11   4
>> +#define INTEL_SUBPLATFORM_G12   5
>
> Ugh I feel this "breaks" the subplatform idea.. feels like it is just 
> too many bits when two separate sets of information get tracked (Gxx 
> plus MBD).

I think they could be specified independent of each other, though. The
subplatform if-else ladder would have to be replaced with independent
ifs. You'd have the G10/G11/G12 and 1 bit separately for MBD.

Only the macros for PCI IDs need to be separate (MBD vs not). You'll
then have:

[Intel-gfx] [PATCH i-g-t 8/8] gputop: Basic vendor agnostic GPU top tool

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Rudimentary vendor agnostic example of how lib_igt_drm_clients can be used
to display a sorted by card and usage list of processes using GPUs.

Borrows a bit of code from intel_gpu_top but for now omits the fancy
features like interactive functionality, card selection, client
aggregation, sort modes, JSON output  and pretty engine names. Also no
support for global GPU or system metrics.

On the other hand it shows clients from all DRM cards which
intel_gpu_top does not do.

Signed-off-by: Tvrtko Ursulin 
Cc: Rob Clark 
Cc: Christian König 
---
 tools/gputop.c| 260 ++
 tools/meson.build |   5 +
 2 files changed, 265 insertions(+)
 create mode 100644 tools/gputop.c

diff --git a/tools/gputop.c b/tools/gputop.c
new file mode 100644
index ..d259cac1ab17
--- /dev/null
+++ b/tools/gputop.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "igt_drm_clients.h"
+#include "igt_drm_fdinfo.h"
+
+static const char *bars[] = { " ", "▏", "▎", "▍", "▌", "▋", "▊", "▉", "█" };
+
+static void n_spaces(const unsigned int n)
+{
+   unsigned int i;
+
+   for (i = 0; i < n; i++)
+   putchar(' ');
+}
+
+static void print_percentage_bar(double percent, int max_len)
+{
+   int bar_len, i, len = max_len - 2;
+   const int w = 8;
+
+   assert(max_len > 0);
+
+   bar_len = ceil(w * percent * len / 100.0);
+   if (bar_len > w * len)
+   bar_len = w * len;
+
+   putchar('|');
+
+   for (i = bar_len; i >= w; i -= w)
+   printf("%s", bars[w]);
+   if (i)
+   printf("%s", bars[i]);
+
+   len -= (bar_len + (w - 1)) / w;
+   n_spaces(len);
+
+   putchar('|');
+}
+
+static int
+print_client_header(struct igt_drm_client *c, int lines, int con_w, int con_h,
+   int *engine_w)
+{
+   const char *pidname = "PID   NAME ";
+   int ret, len = strlen(pidname);
+
+   if (lines++ >= con_h || len >= con_w)
+   return lines;
+   printf("\033[7m");
+   ret = printf("DRM minor %u", c->drm_minor);
+   n_spaces(con_w - ret);
+
+   if (lines++ >= con_h)
+   return lines;
+   printf("\n%s", pidname);
+
+   if (c->engines->num_engines) {
+   unsigned int i;
+   int width;
+
+   *engine_w = width = (con_w - len) / c->engines->num_engines;
+
+   for (i = 0; i <= c->engines->max_engine_id; i++) {
+   const char *name = c->engines->names[i];
+   int name_len = strlen(name);
+   int pad = (width - name_len) / 2;
+   int spaces = width - pad - name_len;
+
+   if (!name)
+   continue;
+
+   if (pad < 0 || spaces < 0)
+   continue;
+
+   n_spaces(pad);
+   printf("%s", name);
+   n_spaces(spaces);
+   len += pad + name_len + spaces;
+   }
+   }
+
+   n_spaces(con_w - len);
+   printf("\033[0m\n");
+
+   return lines;
+}
+
+
+static bool
+newheader(const struct igt_drm_client *c, const struct igt_drm_client *pc)
+{
+   return !pc || c->drm_minor != pc->drm_minor;
+}
+
+static int
+print_client(struct igt_drm_client *c, struct igt_drm_client **prevc,
+double t, int lines, int con_w, int con_h,
+unsigned int period_us, int *engine_w)
+{
+   unsigned int i;
+
+   /* Filter out idle clients. */
+   if (!c->total_runtime || c->samples < 2)
+   return lines;
+
+   /* Print header when moving to a different DRM card. */
+   if (newheader(c, *prevc)) {
+   lines = print_client_header(c, lines, con_w, con_h, engine_w);
+   if (lines >= con_h)
+   return lines;
+   }
+
+   *prevc = c;
+
+   printf("%8u %17s ", c->pid, c->print_name);
+   lines++;
+
+   for (i = 0; c->samples > 1 && i <= c->engines->max_engine_id; i++) {
+   double pct;
+
+   if (!c->engines->capacity[i])
+   continue;
+
+   pct = (double)c->val[i] / period_us / 1e3 * 100 /
+ c->engines->capacity[i];
+
+   /*
+* Guard against fluctuations between our scanning period and
+* GPU times as exported by the kernel in fdinfo.
+*/
+   if (pct > 100.0)
+   pct = 100.0;
+
+   print_percentage_bar(pct, *engine_w);
+   }
+
+ 

[Intel-gfx] [PATCH i-g-t 7/8] libdrmclient: Enforce client status sort order in the library

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Some libdrmclient operations require that inactive clients are last in the
list. Rather than relying on callers of the library sort routine to
implement their comparison callbacks correctly, enforce this order
directly in the library and let callers comparison callbacks concern
themselves only with ordering they are interested in.

Signed-off-by: Tvrtko Ursulin 
---
 lib/igt_drm_clients.c | 37 +++-
 lib/igt_drm_clients.h |  2 +-
 tools/intel_gpu_top.c | 81 +++
 3 files changed, 65 insertions(+), 55 deletions(-)

diff --git a/lib/igt_drm_clients.c b/lib/igt_drm_clients.c
index d507c07fec87..b3eda39cd226 100644
--- a/lib/igt_drm_clients.c
+++ b/lib/igt_drm_clients.c
@@ -191,22 +191,38 @@ void igt_drm_client_free(struct igt_drm_client *c, bool 
clear)
memset(c, 0, sizeof(*c));
 }
 
+struct sort_context
+{
+   int (*user_cmp)(const void *, const void *, void *);
+};
+
+static int sort_cmp(const void *_a, const void *_b, void *_ctx)
+{
+   const struct sort_context *ctx = _ctx;
+   const struct igt_drm_client *a = _a;
+   const struct igt_drm_client *b = _b;
+   int cmp = b->status - a->status;
+
+   if (cmp == 0)
+   return ctx->user_cmp(_a, _b, _ctx);
+   else
+   return cmp;
+}
+
 /**
  * igt_drm_clients_sort:
  * @clients: Previously initialised clients object
  * @cmp: Client comparison callback
  *
  * Sort the clients array according to the passed in comparison callback which
- * is compatible with the qsort(3) semantics.
- *
- * Caller has to ensure the callback is putting all active
- * (IGT_DRM_CLIENT_ALIVE) clients in a single group at the head of the array
- * before any other sorting criteria.
+ * is compatible with the qsort(3) semantics, with the third void * argument
+ * being unused.
  */
 struct igt_drm_clients *
 igt_drm_clients_sort(struct igt_drm_clients *clients,
-int (*cmp)(const void *, const void *))
+int (*cmp)(const void *, const void *, void *))
 {
+   struct sort_context ctx = { .user_cmp = cmp };
unsigned int active, free;
struct igt_drm_client *c;
int tmp;
@@ -214,8 +230,13 @@ igt_drm_clients_sort(struct igt_drm_clients *clients,
if (!clients)
return clients;
 
-   qsort(clients->client, clients->num_clients, sizeof(*clients->client),
- cmp);
+   /*
+* Enforce client->status ordering (active followed by free) by running
+* the user provided comparison callback wrapped in the one internal
+* to the library.
+*/
+   qsort_r(clients->client, clients->num_clients, sizeof(*clients->client),
+ sort_cmp, );
 
/* Trim excessive array space. */
active = 0;
diff --git a/lib/igt_drm_clients.h b/lib/igt_drm_clients.h
index 0a903b431eaa..df8022d42098 100644
--- a/lib/igt_drm_clients.h
+++ b/lib/igt_drm_clients.h
@@ -82,6 +82,6 @@ igt_drm_clients_scan(struct igt_drm_clients *clients,
 
 struct igt_drm_clients *
 igt_drm_clients_sort(struct igt_drm_clients *clients,
-int (*cmp)(const void *, const void *));
+int (*cmp)(const void *, const void *, void *));
 
 #endif /* IGT_DRM_CLIENTS_H */
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index e92a7fb69b48..d931e96e8ee2 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -674,85 +674,74 @@ static void pmu_sample(struct engines *engines)
}
 }
 
-static int client_last_cmp(const void *_a, const void *_b)
+static int
+__client_id_cmp(const struct igt_drm_client *a,
+   const struct igt_drm_client *b)
+{
+   if (a->id > b->id)
+   return 1;
+   else if (a->id < b->id)
+   return -1;
+   else
+   return 0;
+}
+
+static int client_last_cmp(const void *_a, const void *_b, void *unused)
 {
const struct igt_drm_client *a = _a;
const struct igt_drm_client *b = _b;
-   long tot_a, tot_b;
+   long val_a = a->last_runtime, val_b = b->last_runtime;
 
/*
 * Sort clients in descending order of runtime in the previous sampling
-* period for active ones, followed by inactive. Tie-breaker is client
-* id.
+* period. Tie-breaker is client id.
 */
 
-   tot_a = a->status == IGT_DRM_CLIENT_ALIVE ? a->last_runtime : -1;
-   tot_b = b->status == IGT_DRM_CLIENT_ALIVE ? b->last_runtime : -1;
-
-   tot_b -= tot_a;
-   if (tot_b > 0)
+   if (val_a == val_b)
+   return __client_id_cmp(a, b);
+   else if (val_b > val_a)
return 1;
-   if (tot_b < 0)
+   else
return -1;
-
-   return (int)b->id - a->id;
 }
 
-static int client_total_cmp(const void *_a, const void *_b)
+static int client_total_cmp(const void *_a, const void *_b, void *unused)
 {
const struct igt_drm_client 

[Intel-gfx] [PATCH i-g-t 5/8] libdrmfdinfo: Track largest engine index

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Prep code for incoming work.

Signed-off-by: Tvrtko Ursulin 
---
 lib/igt_drm_fdinfo.c | 2 ++
 lib/igt_drm_fdinfo.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/lib/igt_drm_fdinfo.c b/lib/igt_drm_fdinfo.c
index 68c89ad2c17e..b850d2210ae7 100644
--- a/lib/igt_drm_fdinfo.c
+++ b/lib/igt_drm_fdinfo.c
@@ -162,6 +162,8 @@ __igt_parse_drm_fdinfo(int dir, const char *fd, struct 
drm_client_fdinfo *info,
info->capacity[idx] = 1;
info->busy[idx] = val;
info->num_engines++;
+   if (idx > info->last_engine_index)
+   info->last_engine_index = idx;
}
} else if (!strncmp(l, "drm-engine-capacity-", 20)) {
idx = parse_engine(l, info,
diff --git a/lib/igt_drm_fdinfo.h b/lib/igt_drm_fdinfo.h
index fa4982f4030e..6284e05e868a 100644
--- a/lib/igt_drm_fdinfo.h
+++ b/lib/igt_drm_fdinfo.h
@@ -38,6 +38,7 @@ struct drm_client_fdinfo {
unsigned long id;
 
unsigned int num_engines;
+   unsigned int last_engine_index;
unsigned int capacity[DRM_CLIENT_FDINFO_MAX_ENGINES];
char names[DRM_CLIENT_FDINFO_MAX_ENGINES][256];
uint64_t busy[DRM_CLIENT_FDINFO_MAX_ENGINES];
-- 
2.34.1

[Intel-gfx] [PATCH i-g-t 6/8] libdrmclient/intel_gpu_top: Decouple hardcoded engine assumptions

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Intel_gpu_top gets it's main engine configuration data via PMU probe and
uses that for per client view as well. Furthemore code so far assumed only
clients belonging from a single DRM card would be tracked in a single
clients list.

Break this inter-dependency by moving the engine data to be per client and
also have libdrmclient probe the engine configuration independently using
the previously added libdrmfdinfo facilities.

Signed-off-by: Tvrtko Ursulin 
---
 lib/igt_drm_clients.c |  38 +++--
 lib/igt_drm_clients.h |  14 ++---
 tools/intel_gpu_top.c | 127 +++---
 3 files changed, 134 insertions(+), 45 deletions(-)

diff --git a/lib/igt_drm_clients.c b/lib/igt_drm_clients.c
index e11c8b18188f..d507c07fec87 100644
--- a/lib/igt_drm_clients.c
+++ b/lib/igt_drm_clients.c
@@ -97,7 +97,7 @@ igt_drm_client_update(struct igt_drm_client *c, unsigned int 
pid, char *name,
c->last_runtime = 0;
c->total_runtime = 0;
 
-   for (i = 0; i < c->clients->num_classes; i++) {
+   for (i = 0; i <= c->engines->max_engine_id; i++) {
assert(i < ARRAY_SIZE(info->busy));
 
if (info->busy[i] < c->last[i])
@@ -119,6 +119,7 @@ igt_drm_client_add(struct igt_drm_clients *clients,
   unsigned int pid, char *name, unsigned int drm_minor)
 {
struct igt_drm_client *c;
+   unsigned int i;
 
assert(!igt_drm_clients_find(clients, IGT_DRM_CLIENT_ALIVE,
 drm_minor, info->id));
@@ -144,8 +145,28 @@ igt_drm_client_add(struct igt_drm_clients *clients,
c->id = info->id;
c->drm_minor = drm_minor;
c->clients = clients;
-   c->val = calloc(clients->num_classes, sizeof(c->val));
-   c->last = calloc(clients->num_classes, sizeof(c->last));
+   c->engines = malloc(sizeof(*c->engines));
+   assert(c->engines);
+   memset(c->engines, 0, sizeof(*c->engines));
+   c->engines->capacity = calloc(info->last_engine_index + 1,
+ sizeof(*c->engines->capacity));
+   assert(c->engines->capacity);
+   c->engines->names = calloc(info->last_engine_index + 1,
+  sizeof(*c->engines->names));
+   assert(c->engines->names);
+
+   for (i = 0; i <= info->last_engine_index; i++) {
+   if (!info->capacity[i])
+   continue;
+
+   c->engines->capacity[i] = info->capacity[i];
+   c->engines->names[i] = strdup(info->names[i]);
+   assert(c->engines->names[i]);
+   c->engines->num_engines++;
+   c->engines->max_engine_id = i;
+   }
+   c->val = calloc(c->engines->max_engine_id + 1, sizeof(c->val));
+   c->last = calloc(c->engines->max_engine_id + 1, sizeof(c->last));
assert(c->val && c->last);
 
igt_drm_client_update(c, pid, name, info);
@@ -154,6 +175,15 @@ igt_drm_client_add(struct igt_drm_clients *clients,
 static
 void igt_drm_client_free(struct igt_drm_client *c, bool clear)
 {
+   unsigned int i;
+
+   if (c->engines) {
+   for (i = 0; i <= c->engines->max_engine_id; i++)
+   free(c->engines->names[i]);
+   free(c->engines->capacity);
+   free(c->engines->names);
+   }
+   free(c->engines);
free(c->val);
free(c->last);
 
@@ -323,7 +353,7 @@ static bool is_drm_fd(int fd_dir, const char *name, 
unsigned int *minor)
  *
  * If @name_map is not provided engine names will be auto-detected (this is
  * less performant) and indices will correspond with auto-detected names as
- * listed int clients->engine_class[].
+ * listed int clients->engines->names[].
  */
 struct igt_drm_clients *
 igt_drm_clients_scan(struct igt_drm_clients *clients,
diff --git a/lib/igt_drm_clients.h b/lib/igt_drm_clients.h
index ffa219c9c9fd..0a903b431eaa 100644
--- a/lib/igt_drm_clients.h
+++ b/lib/igt_drm_clients.h
@@ -31,10 +31,12 @@ enum igt_drm_client_status {
IGT_DRM_CLIENT_PROBE
 };
 
-struct igt_drm_client_engine_class {
-   unsigned int engine_class;
-   const char *name;
-   unsigned int num_engines;
+struct igt_drm_client_engines {
+   unsigned int num_engines; /* Number of discovered active engines. */
+   unsigned int max_engine_id; /* Largest engine index discovered.
+  (Can differ from num_engines - 1 when 
using the engine map facility.) */
+   unsigned int *capacity; /* Array of engine capacities as parsed from 
fdinfo. */
+   char **names; /* Array of engine names, either auto-detected or from 
the passed in engine map. */
 };
 
 struct igt_drm_clients;
@@ -43,6 +45,7 @@ struct igt_drm_client {
struct igt_drm_clients *clients; /* Owning list. */
 
enum igt_drm_client_status status;
+   struct igt_drm_client_engines *engines; /* Engines used by this client, 
to map with 

[Intel-gfx] [PATCH i-g-t 4/8] libdrmclient: Support multiple DRM cards

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Require DRM minor match during client lookup.

Signed-off-by: Tvrtko Ursulin 
---
 lib/igt_drm_clients.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/lib/igt_drm_clients.c b/lib/igt_drm_clients.c
index c23a3fae9793..e11c8b18188f 100644
--- a/lib/igt_drm_clients.c
+++ b/lib/igt_drm_clients.c
@@ -49,7 +49,7 @@ struct igt_drm_clients *igt_drm_clients_init(void 
*private_data)
 static struct igt_drm_client *
 igt_drm_clients_find(struct igt_drm_clients *clients,
 enum igt_drm_client_status status,
-unsigned int id)
+unsigned int drm_minor, unsigned int id)
 {
unsigned int start, num;
struct igt_drm_client *c;
@@ -61,7 +61,8 @@ igt_drm_clients_find(struct igt_drm_clients *clients,
if (status != c->status)
continue;
 
-   if (status == IGT_DRM_CLIENT_FREE || c->id == id)
+   if (status == IGT_DRM_CLIENT_FREE ||
+   (drm_minor == c->drm_minor && c->id == id))
return c;
}
 
@@ -119,9 +120,10 @@ igt_drm_client_add(struct igt_drm_clients *clients,
 {
struct igt_drm_client *c;
 
-   assert(!igt_drm_clients_find(clients, IGT_DRM_CLIENT_ALIVE, info->id));
+   assert(!igt_drm_clients_find(clients, IGT_DRM_CLIENT_ALIVE,
+drm_minor, info->id));
 
-   c = igt_drm_clients_find(clients, IGT_DRM_CLIENT_FREE, 0);
+   c = igt_drm_clients_find(clients, IGT_DRM_CLIENT_FREE, 0, 0);
if (!c) {
unsigned int idx = clients->num_clients;
 
@@ -411,11 +413,11 @@ igt_drm_clients_scan(struct igt_drm_clients *clients,
continue;
 
if (igt_drm_clients_find(clients, IGT_DRM_CLIENT_ALIVE,
-   info.id))
+minor, info.id))
continue; /* Skip duplicate fds. */
 
c = igt_drm_clients_find(clients, IGT_DRM_CLIENT_PROBE,
-   info.id);
+minor, info.id);
if (!c)
igt_drm_client_add(clients, , client_pid,
   client_name, minor);
-- 
2.34.1

[Intel-gfx] [PATCH i-g-t 0/8] Vendor agnostic gputop

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Just a re-send having rebased on top of latest tree.

Tvrtko Ursulin (8):
  lib: Extract igt_drm_clients from intel_gpu_top
  libdrmfdinfo: Allow specifying custom engine map
  libdrmclients: Record client drm minor
  libdrmclient: Support multiple DRM cards
  libdrmfdinfo: Track largest engine index
  libdrmclient/intel_gpu_top: Decouple hardcoded engine assumptions
  libdrmclient: Enforce client status sort order in the library
  gputop: Basic vendor agnostic GPU top tool

 lib/igt_drm_clients.c   | 503 +
 lib/igt_drm_clients.h   |  87 ++
 lib/igt_drm_fdinfo.c|  50 ++-
 lib/igt_drm_fdinfo.h|  16 +-
 lib/meson.build |   8 +
 tests/i915/drm_fdinfo.c |  19 +-
 tools/gputop.c  | 260 +++
 tools/intel_gpu_top.c   | 677 +++-
 tools/meson.build   |   7 +-
 9 files changed, 1113 insertions(+), 514 deletions(-)
 create mode 100644 lib/igt_drm_clients.c
 create mode 100644 lib/igt_drm_clients.h
 create mode 100644 tools/gputop.c

-- 
2.34.1

[Intel-gfx] [PATCH i-g-t 2/8] libdrmfdinfo: Allow specifying custom engine map

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Instead of hard coding the engine names, allow a map of names to indices
to either be passed in or it gets auto-detected (less efficient) while
parsing.
---
 lib/igt_drm_clients.c   | 18 +---
 lib/igt_drm_clients.h   |  3 ++-
 lib/igt_drm_fdinfo.c| 48 +++--
 lib/igt_drm_fdinfo.h| 15 ++---
 tests/i915/drm_fdinfo.c | 19 
 tools/intel_gpu_top.c   | 16 +++---
 6 files changed, 89 insertions(+), 30 deletions(-)

diff --git a/lib/igt_drm_clients.c b/lib/igt_drm_clients.c
index 45de2d0f1cc5..eabd43773f2d 100644
--- a/lib/igt_drm_clients.c
+++ b/lib/igt_drm_clients.c
@@ -302,14 +302,26 @@ static bool is_drm_fd(int fd_dir, const char *name)
  * igt_drm_clients_scan:
  * @clients: Previously initialised clients object
  * @filter_client: Callback for client filtering
+ * @name_map: Array of engine name strings
+ * @map_entries: Number of items in the @name_map array
  *
  * Scan all open file descriptors from all processes in order to find all DRM
  * clients and manage our internal list.
+ *
+ * If @name_map is provided each found engine in the fdinfo struct must
+ * correspond to one of the provided names. In this case the index of the 
engine
+ * stats tracked in struct igt_drm_client will be tracked under the same index
+ * as the engine name provided.
+ *
+ * If @name_map is not provided engine names will be auto-detected (this is
+ * less performant) and indices will correspond with auto-detected names as
+ * listed int clients->engine_class[].
  */
 struct igt_drm_clients *
 igt_drm_clients_scan(struct igt_drm_clients *clients,
 bool (*filter_client)(const struct igt_drm_clients *,
-  const struct drm_client_fdinfo *))
+  const struct drm_client_fdinfo *),
+const char **name_map, unsigned int map_entries)
 {
struct dirent *proc_dent;
struct igt_drm_client *c;
@@ -385,8 +397,8 @@ igt_drm_clients_scan(struct igt_drm_clients *clients,
continue;
 
if (!__igt_parse_drm_fdinfo(dirfd(fdinfo_dir),
-   fdinfo_dent->d_name,
-   ))
+   fdinfo_dent->d_name, ,
+   name_map, map_entries))
continue;
 
if (filter_client && !filter_client(clients, ))
diff --git a/lib/igt_drm_clients.h b/lib/igt_drm_clients.h
index 969793d5b51e..bced19adb055 100644
--- a/lib/igt_drm_clients.h
+++ b/lib/igt_drm_clients.h
@@ -76,7 +76,8 @@ void igt_drm_clients_free(struct igt_drm_clients *clients);
 struct igt_drm_clients *
 igt_drm_clients_scan(struct igt_drm_clients *clients,
 bool (*filter_client)(const struct igt_drm_clients *,
-  const struct drm_client_fdinfo *));
+  const struct drm_client_fdinfo *),
+const char **name_map, unsigned int map_entries);
 
 struct igt_drm_clients *
 igt_drm_clients_sort(struct igt_drm_clients *clients,
diff --git a/lib/igt_drm_fdinfo.c b/lib/igt_drm_fdinfo.c
index 250d9e8917f2..68c89ad2c17e 100644
--- a/lib/igt_drm_fdinfo.c
+++ b/lib/igt_drm_fdinfo.c
@@ -22,6 +22,7 @@
  *
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -53,14 +54,10 @@ static size_t read_fdinfo(char *buf, const size_t sz, int 
at, const char *name)
 }
 
 static int parse_engine(char *line, struct drm_client_fdinfo *info,
-   size_t prefix_len, uint64_t *val)
+   size_t prefix_len,
+   const char **name_map, unsigned int map_entries,
+   uint64_t *val)
 {
-   static const char *e2class[] = {
-   "render",
-   "copy",
-   "video",
-   "video-enhance",
-   };
ssize_t name_len;
char *name, *p;
int found = -1;
@@ -76,10 +73,26 @@ static int parse_engine(char *line, struct 
drm_client_fdinfo *info,
 
name = line + prefix_len;
 
-   for (i = 0; i < ARRAY_SIZE(e2class); i++) {
-   if (!strncmp(name, e2class[i], name_len)) {
-   found = i;
-   break;
+   if (name_map) {
+   for (i = 0; i < map_entries; i++) {
+   if (!strncmp(name, name_map[i], name_len)) {
+   found = i;
+   break;
+   }
+   }
+   } else {
+   for (i = 0; i < info->num_engines; i++) {
+   if (!strncmp(name, info->names[i], name_len)) {
+   found = i;
+   break;
+   }

[Intel-gfx] [PATCH i-g-t 3/8] libdrmclients: Record client drm minor

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Prepare for supporting clients belonging to multiple DRM cards by storing
the DRM minor in the client record.

Signed-off-by: Tvrtko Ursulin 
---
 lib/igt_drm_clients.c | 22 ++
 lib/igt_drm_clients.h |  1 +
 2 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/lib/igt_drm_clients.c b/lib/igt_drm_clients.c
index eabd43773f2d..c23a3fae9793 100644
--- a/lib/igt_drm_clients.c
+++ b/lib/igt_drm_clients.c
@@ -115,7 +115,7 @@ igt_drm_client_update(struct igt_drm_client *c, unsigned 
int pid, char *name,
 static void
 igt_drm_client_add(struct igt_drm_clients *clients,
   const struct drm_client_fdinfo *info,
-  unsigned int pid, char *name)
+  unsigned int pid, char *name, unsigned int drm_minor)
 {
struct igt_drm_client *c;
 
@@ -140,6 +140,7 @@ igt_drm_client_add(struct igt_drm_clients *clients,
}
 
c->id = info->id;
+   c->drm_minor = drm_minor;
c->clients = clients;
c->val = calloc(clients->num_classes, sizeof(c->val));
c->last = calloc(clients->num_classes, sizeof(c->last));
@@ -286,16 +287,21 @@ static bool get_task_name(const char *buffer, char *out, 
unsigned long sz)
return true;
 }
 
-static bool is_drm_fd(int fd_dir, const char *name)
+static bool is_drm_fd(int fd_dir, const char *name, unsigned int *minor)
 {
struct stat stat;
int ret;
 
ret = fstatat(fd_dir, name, , 0);
 
-   return ret == 0 &&
-  (stat.st_mode & S_IFMT) == S_IFCHR &&
-  major(stat.st_rdev) == 226;
+   if (ret == 0 &&
+   (stat.st_mode & S_IFMT) == S_IFCHR &&
+   major(stat.st_rdev) == 226) {
+   *minor = minor(stat.st_rdev);
+   return true;
+   }
+
+   return false;
 }
 
 /**
@@ -348,10 +354,10 @@ igt_drm_clients_scan(struct igt_drm_clients *clients,
return clients;
 
while ((proc_dent = readdir(proc_dir)) != NULL) {
+   unsigned int client_pid, minor = 0;
int pid_dir = -1, fd_dir = -1;
struct dirent *fdinfo_dent;
char client_name[64] = { };
-   unsigned int client_pid;
DIR *fdinfo_dir = NULL;
char buf[4096];
size_t count;
@@ -393,7 +399,7 @@ igt_drm_clients_scan(struct igt_drm_clients *clients,
if (!isdigit(fdinfo_dent->d_name[0]))
continue;
 
-   if (!is_drm_fd(fd_dir, fdinfo_dent->d_name))
+   if (!is_drm_fd(fd_dir, fdinfo_dent->d_name, ))
continue;
 
if (!__igt_parse_drm_fdinfo(dirfd(fdinfo_dir),
@@ -412,7 +418,7 @@ igt_drm_clients_scan(struct igt_drm_clients *clients,
info.id);
if (!c)
igt_drm_client_add(clients, , client_pid,
-  client_name);
+  client_name, minor);
else
igt_drm_client_update(c, client_pid,
  client_name, );
diff --git a/lib/igt_drm_clients.h b/lib/igt_drm_clients.h
index bced19adb055..ffa219c9c9fd 100644
--- a/lib/igt_drm_clients.h
+++ b/lib/igt_drm_clients.h
@@ -44,6 +44,7 @@ struct igt_drm_client {
 
enum igt_drm_client_status status;
unsigned int id; /* DRM client id from fdinfo. */
+   unsigned int drm_minor; /* DRM minor of this client. */
unsigned int pid; /* PID which has this DRM fd open. */
char name[24]; /* Process name of the owning PID. */
char print_name[24]; /* Name without any non-printable characters. */
-- 
2.34.1

[Intel-gfx] [PATCH i-g-t 1/8] lib: Extract igt_drm_clients from intel_gpu_top

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Extract some code into a new library to prepare for further work towards
making a vendor agnostic gputop tool.

Signed-off-by: Tvrtko Ursulin 
---
 lib/igt_drm_clients.c | 432 ++
 lib/igt_drm_clients.h |  85 +++
 lib/meson.build   |   8 +
 tools/intel_gpu_top.c | 521 +++---
 tools/meson.build |   2 +-
 5 files changed, 606 insertions(+), 442 deletions(-)
 create mode 100644 lib/igt_drm_clients.c
 create mode 100644 lib/igt_drm_clients.h

diff --git a/lib/igt_drm_clients.c b/lib/igt_drm_clients.c
new file mode 100644
index ..45de2d0f1cc5
--- /dev/null
+++ b/lib/igt_drm_clients.c
@@ -0,0 +1,432 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "igt_drm_clients.h"
+#include "igt_drm_fdinfo.h"
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(array) (sizeof(array) / sizeof(array[0]))
+#endif
+
+/**
+ * igt_drm_clients_init:
+ * @private_data: private data to store in the struct
+ *
+ * Allocate and initialise the clients structure to be used with further API
+ * calls.
+ */
+struct igt_drm_clients *igt_drm_clients_init(void *private_data)
+{
+   struct igt_drm_clients *clients;
+
+   clients = malloc(sizeof(*clients));
+   if (!clients)
+   return NULL;
+
+   memset(clients, 0, sizeof(*clients));
+
+   clients->private_data = private_data;
+
+   return clients;
+}
+
+static struct igt_drm_client *
+igt_drm_clients_find(struct igt_drm_clients *clients,
+enum igt_drm_client_status status,
+unsigned int id)
+{
+   unsigned int start, num;
+   struct igt_drm_client *c;
+
+   start = status == IGT_DRM_CLIENT_FREE ? clients->active_clients : 0; /* 
Free block at the end. */
+   num = clients->num_clients - start;
+
+   for (c = >client[start]; num; c++, num--) {
+   if (status != c->status)
+   continue;
+
+   if (status == IGT_DRM_CLIENT_FREE || c->id == id)
+   return c;
+   }
+
+   return NULL;
+}
+
+static void
+igt_drm_client_update(struct igt_drm_client *c, unsigned int pid, char *name,
+ const struct drm_client_fdinfo *info)
+{
+   unsigned int i;
+
+   /* Update client pid if it changed (fd sharing). */
+   if (c->pid != pid)
+   c->pid = pid;
+
+   /* Update client name if it changed (fd sharing). */
+   if (strcmp(c->name, name)) {
+   char *p;
+
+   strncpy(c->name, name, sizeof(c->name) - 1);
+   strncpy(c->print_name, name, sizeof(c->print_name) - 1);
+
+   p = c->print_name;
+   while (*p) {
+   if (!isprint(*p))
+   *p = '*';
+   p++;
+   }
+   }
+
+   c->last_runtime = 0;
+   c->total_runtime = 0;
+
+   for (i = 0; i < c->clients->num_classes; i++) {
+   assert(i < ARRAY_SIZE(info->busy));
+
+   if (info->busy[i] < c->last[i])
+   continue; /* It will catch up soon. */
+
+   c->total_runtime += info->busy[i];
+   c->val[i] = info->busy[i] - c->last[i];
+   c->last_runtime += c->val[i];
+   c->last[i] = info->busy[i];
+   }
+
+   c->samples++;
+   c->status = IGT_DRM_CLIENT_ALIVE;
+}
+
+static void
+igt_drm_client_add(struct igt_drm_clients *clients,
+  const struct drm_client_fdinfo *info,
+  unsigned int pid, char *name)
+{
+   struct igt_drm_client *c;
+
+   assert(!igt_drm_clients_find(clients, IGT_DRM_CLIENT_ALIVE, info->id));
+
+   c = igt_drm_clients_find(clients, IGT_DRM_CLIENT_FREE, 0);
+   if (!c) {
+   unsigned int idx = clients->num_clients;
+
+   /*
+* Grow the array a bit past the current requirement to avoid
+* constant reallocation when clients are dynamically appearing
+* and disappearing.
+*/
+   clients->num_clients += (clients->num_clients + 2) / 2;
+   clients->client = realloc(clients->client,
+ clients->num_clients * sizeof(*c));
+   assert(clients->client);
+
+   c = >client[idx];
+   memset(c, 0, (clients->num_clients - idx) * sizeof(*c));
+   }
+
+   c->id = info->id;
+   c->clients = clients;
+   c->val = calloc(clients->num_classes, sizeof(c->val));
+   c->last = calloc(clients->num_classes, sizeof(c->last));
+   assert(c->val && c->last);
+
+   igt_drm_client_update(c, pid, name, info);
+}
+
+static
+void igt_drm_client_free(struct igt_drm_client *c, 

[Intel-gfx] [PATCH] drm/i915/fdinfo: Don't show engine classes not present

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Stop displaying engine classes with no engines - it is not a huge problem
if they are shown, since the values will correctly be all zeroes, but it
does count as misleading.

Signed-off-by: Tvrtko Ursulin 
Fixes: 055634e4b62f ("drm/i915: Expose client engine utilisation via fdinfo")
Cc: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/i915_drm_client.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drm_client.c 
b/drivers/gpu/drm/i915/i915_drm_client.c
index 18d38cb59923..b09d1d386574 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -116,8 +116,9 @@ show_client_class(struct seq_file *m,
total += busy_add(ctx, class);
rcu_read_unlock();
 
-   seq_printf(m, "drm-engine-%s:\t%llu ns\n",
-  uabi_class_names[class], total);
+   if (capacity)
+   seq_printf(m, "drm-engine-%s:\t%llu ns\n",
+  uabi_class_names[class], total);
 
if (capacity > 1)
seq_printf(m, "drm-engine-capacity-%s:\t%u\n",
-- 
2.34.1

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Remove bogus LPT iCLKIP WARN

[Patchwork]

== Series Details ==

Series: drm/i915: Remove bogus LPT iCLKIP WARN
URL   : https://patchwork.freedesktop.org/series/105221/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11767 -> Patchwork_105221v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_105221v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_105221v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105221v1/index.html

Participating hosts (42 -> 43)
--

  Additional (2): bat-dg2-9 bat-atsm-1 
  Missing(1): fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105221v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rpm@module-reload:
- fi-bsw-n3050:   [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/fi-bsw-n3050/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105221v1/fi-bsw-n3050/igt@i915_pm_...@module-reload.html

  
Known issues


  Here are the changes found in Patchwork_105221v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-hsw-g3258:   NOTRUN -> [SKIP][3] ([fdo#109271]) +9 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105221v1/fi-hsw-g3258/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105221v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#3012])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105221v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
- fi-hsw-g3258:   NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3012])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105221v1/fi-hsw-g3258/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rpm@module-reload:
- bat-adlp-4: [PASS][7] -> [DMESG-WARN][8] ([i915#3576]) +2 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/bat-adlp-4/igt@i915_pm_...@module-reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105221v1/bat-adlp-4/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@gem:
- fi-blb-e6850:   NOTRUN -> [DMESG-FAIL][9] ([i915#4528])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105221v1/fi-blb-e6850/igt@i915_selftest@l...@gem.html

  * igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [PASS][10] -> [INCOMPLETE][11] ([i915#4983])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105221v1/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   NOTRUN -> [INCOMPLETE][12] ([i915#4785])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105221v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- bat-adlp-4: [PASS][13] -> [DMESG-FAIL][14] ([i915#5087])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/bat-adlp-4/igt@i915_selftest@l...@requests.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105221v1/bat-adlp-4/igt@i915_selftest@l...@requests.html
- fi-pnv-d510:[PASS][15] -> [DMESG-FAIL][16] ([i915#4528])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105221v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105221v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
- fi-hsw-g3258:   NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105221v1/fi-hsw-g3258/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-g3258:   NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#533])
   [19]: 

[Intel-gfx] [PATCH i-g-t] tests/drm_fdinfo: Test virtual engines

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

We need some coverage of the virtual engines.

Signed-off-by: Tvrtko Ursulin 
Cc: Umesh Nerlige Ramappa 
---
 tests/i915/drm_fdinfo.c | 284 +++-
 1 file changed, 282 insertions(+), 2 deletions(-)

diff --git a/tests/i915/drm_fdinfo.c b/tests/i915/drm_fdinfo.c
index 3475d35b23b9..0a42370d54ce 100644
--- a/tests/i915/drm_fdinfo.c
+++ b/tests/i915/drm_fdinfo.c
@@ -27,6 +27,7 @@
 #include "igt_device.h"
 #include "igt_drm_fdinfo.h"
 #include "i915/gem.h"
+#include "i915/gem_vm.h"
 #include "intel_ctx.h"
 
 IGT_TEST_DESCRIPTION("Test the i915 drm fdinfo data");
@@ -90,10 +91,10 @@ static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const 
intel_ctx_t *ctx,
struct igt_spin_factory opts = {
.ahnd = ahnd,
.ctx = ctx,
-   .engine = e->flags,
+   .engine = e ? e->flags : 0,
};
 
-   if (gem_class_can_store_dword(fd, e->class))
+   if (!e || gem_class_can_store_dword(fd, e->class))
opts.flags |= IGT_SPIN_POLL_RUN;
 
return __igt_spin_factory(fd, );
@@ -440,6 +441,265 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
gem_quiescent_gpu(gem_fd);
 }
 
+static struct i915_engine_class_instance *
+list_engines(const intel_ctx_cfg_t *cfg,
+unsigned int class, unsigned int *out)
+{
+   struct i915_engine_class_instance *ci;
+   unsigned int count = 0, i;
+
+   ci = malloc(cfg->num_engines * sizeof(*ci));
+   igt_assert(ci);
+
+   for (i = 0; i < cfg->num_engines; i++) {
+   if (class == cfg->engines[i].engine_class)
+   ci[count++] = cfg->engines[i];
+   }
+
+   if (!count) {
+   free(ci);
+   ci = NULL;
+   }
+
+   *out = count;
+   return ci;
+}
+
+static size_t sizeof_load_balance(int count)
+{
+   return offsetof(struct i915_context_engines_load_balance,
+   engines[count]);
+}
+
+static size_t sizeof_param_engines(int count)
+{
+   return offsetof(struct i915_context_param_engines,
+   engines[count]);
+}
+
+#define alloca0(sz) ({ size_t sz__ = (sz); memset(alloca(sz__), 0, sz__); })
+
+static int __set_load_balancer(int i915, uint32_t ctx,
+  const struct i915_engine_class_instance *ci,
+  unsigned int count,
+  void *ext)
+{
+   struct i915_context_engines_load_balance *balancer =
+   alloca0(sizeof_load_balance(count));
+   struct i915_context_param_engines *engines =
+   alloca0(sizeof_param_engines(count + 1));
+   struct drm_i915_gem_context_param p = {
+   .ctx_id = ctx,
+   .param = I915_CONTEXT_PARAM_ENGINES,
+   .size = sizeof_param_engines(count + 1),
+   .value = to_user_pointer(engines)
+   };
+
+   balancer->base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE;
+   balancer->base.next_extension = to_user_pointer(ext);
+
+   igt_assert(count);
+   balancer->num_siblings = count;
+   memcpy(balancer->engines, ci, count * sizeof(*ci));
+
+   engines->extensions = to_user_pointer(balancer);
+   engines->engines[0].engine_class =
+   I915_ENGINE_CLASS_INVALID;
+   engines->engines[0].engine_instance =
+   I915_ENGINE_CLASS_INVALID_NONE;
+   memcpy(engines->engines + 1, ci, count * sizeof(*ci));
+
+   return __gem_context_set_param(i915, );
+}
+
+static void set_load_balancer(int i915, uint32_t ctx,
+ const struct i915_engine_class_instance *ci,
+ unsigned int count,
+ void *ext)
+{
+   igt_assert_eq(__set_load_balancer(i915, ctx, ci, count, ext), 0);
+}
+
+static void
+virtual(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
+{
+   intel_ctx_cfg_t cfg = {};
+
+   cfg.vm = gem_vm_create(i915);
+
+   for (int class = 0; class < 32; class++) {
+   struct i915_engine_class_instance *ci;
+   unsigned int count;
+
+   if (!gem_class_can_store_dword(i915, class))
+   continue;
+
+   ci = list_engines(base_cfg, class, );
+   if (!ci)
+   continue;
+
+   for (unsigned int pass = 0; pass < count; pass++) {
+   const intel_ctx_t *ctx;
+   unsigned long slept;
+   uint64_t ahnd, val;
+   igt_spin_t *spin;
+
+   igt_assert(sizeof(*ci) == sizeof(int));
+   igt_permute_array(ci, count, igt_exchange_int);
+
+   igt_debug("class %u, pass %u/%u...\n", class, pass, 
count);
+
+   ctx = intel_ctx_create(i915, );
+   ahnd = get_reloc_ahnd(i915, ctx->id);
+
+ 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: drm/i915/display: split out verification, hw readout and dump from intel_display.c

[Patchwork]

== Series Details ==

Series: drm/i915: drm/i915/display: split out verification, hw readout and dump 
from intel_display.c
URL   : https://patchwork.freedesktop.org/series/105220/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11767 -> Patchwork_105220v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/index.html

Participating hosts (42 -> 42)
--

  Additional (2): bat-adlm-1 bat-atsm-1 
  Missing(2): fi-kbl-soraka fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105220v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rpm@basic-rte:
- fi-cfl-8109u:   [PASS][1] -> [DMESG-WARN][2] ([i915#1888] / [i915#62])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/fi-cfl-8109u/igt@i915_pm_...@basic-rte.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/fi-cfl-8109u/igt@i915_pm_...@basic-rte.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- bat-adlp-4: [PASS][5] -> [DMESG-WARN][6] ([i915#3576])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/bat-adlp-4/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/bat-adlp-4/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- fi-tgl-u2:  [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar 
issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-cfl-8109u:   [PASS][9] -> [DMESG-WARN][10] ([i915#62]) +15 similar 
issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/fi-cfl-8109u/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-a-frame-sequence.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/fi-cfl-8109u/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-a-frame-sequence.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-5:  [DMESG-FAIL][11] ([i915#4494] / [i915#4957]) -> 
[PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}:   [DMESG-WARN][13] ([i915#3576]) -> [PASS][14] +1 
similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- bat-adlp-4: [DMESG-WARN][15] ([i915#3576]) -> [PASS][16] +2 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/bat-adlp-4/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105220v1/bat-adlp-4/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4613]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: drm/i915/display: split out verification, hw readout and dump from intel_display.c

[Patchwork]

== Series Details ==

Series: drm/i915: drm/i915/display: split out verification, hw readout and dump 
from intel_display.c
URL   : https://patchwork.freedesktop.org/series/105220/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: drm/i915/display: split out verification, hw readout and dump from intel_display.c

[Patchwork]

== Series Details ==

Series: drm/i915: drm/i915/display: split out verification, hw readout and dump 
from intel_display.c
URL   : https://patchwork.freedesktop.org/series/105220/
State : warning

== Summary ==

Error: dim checkpatch failed
ab29d65b77e1 drm/i915/wm: move wm state verification to intel_pm.c
d7c89dd74933 drm/i915/dpll: move shared dpll state verification to 
intel_dpll_mgr.c
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#13: 
v2: intel_shared_dpll_verify_state -> intel_shared_dpll_state_verify (Ville)

total: 0 errors, 1 warnings, 0 checks, 215 lines checked
3fb0167385c7 drm/i915/mpllb: use I915_STATE_WARN() for state mismatch warnings
-:32: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__name' - possible 
side-effects?
#32: FILE: drivers/gpu/drm/i915/display/intel_display.c:6604:
+#define MPLLB_CHECK(__name)\
+   I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,
\
+   "[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, 
found 0x%08x)", \
+   crtc->base.base.id, crtc->base.name,\
+   __stringify(__name),\
+   mpllb_sw_state->__name, mpllb_hw_state.__name)

-:32: CHECK:MACRO_ARG_PRECEDENCE: Macro argument '__name' may be better as 
'(__name)' to avoid precedence issues
#32: FILE: drivers/gpu/drm/i915/display/intel_display.c:6604:
+#define MPLLB_CHECK(__name)\
+   I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,
\
+   "[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, 
found 0x%08x)", \
+   crtc->base.base.id, crtc->base.name,\
+   __stringify(__name),\
+   mpllb_sw_state->__name, mpllb_hw_state.__name)

total: 0 errors, 0 warnings, 2 checks, 20 lines checked
2c6e11c59640 drm/i915/mpllb: move mpllb state check to intel_snps_phy.c
-:108: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__name' - possible 
side-effects?
#108: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:835:
+#define MPLLB_CHECK(__name)\
+   I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,
\
+   "[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, 
found 0x%08x)", \
+   crtc->base.base.id, crtc->base.name,\
+   __stringify(__name),\
+   mpllb_sw_state->__name, mpllb_hw_state.__name)

-:108: CHECK:MACRO_ARG_PRECEDENCE: Macro argument '__name' may be better as 
'(__name)' to avoid precedence issues
#108: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:835:
+#define MPLLB_CHECK(__name)\
+   I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,
\
+   "[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, 
found 0x%08x)", \
+   crtc->base.base.id, crtc->base.name,\
+   __stringify(__name),\
+   mpllb_sw_state->__name, mpllb_hw_state.__name)

total: 0 errors, 0 warnings, 2 checks, 121 lines checked
2dc25c9664a8 drm/i915/display: split out modeset verification code
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
-:365: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#365: 
new file mode 100644

-:459: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#459: FILE: drivers/gpu/drm/i915/display/intel_modeset_verify.c:90:
+   int fdi_dotclock = 
intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),

total: 0 errors, 2 warnings, 0 checks, 585 lines checked
7ed4f068 drm/i915/display: split out crtc state dump to a separate file
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
-:27: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#27: 
new file mode 100644

-:90: ERROR:BRACKET_SPACE: space prohibited before open square bracket '['
#90: FILE: drivers/gpu/drm/i915/display/intel_crtc_state_dump.c:59:
+#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x

total: 1 errors, 1 warnings, 0 checks, 708 lines checked
6001a929f514 drm/i915/display: change who adds 

Re: [Intel-gfx] [PATCH v2 2/9] drm/i915/dg1: OpRegion PCON DG1 MBD config support

[Jani Nikula]

On Thu, 16 Jun 2022, Anshuman Gupta  wrote:
> DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD)
> configs. MBD config requires HOST BIOS GPIO toggling support
> in order to enable/disable VRAM SR using ACPI OpRegion.
>
> i915 requires to check OpRegion PCON MBD Config bits to
> discover whether Gfx Card is MBD config before enabling
> VRSR.
>
> BSpec: 53440
> Cc: Jani Nikula 
> Cc: Rodrigo Vivi 
> Signed-off-by: Anshuman Gupta 
> ---
>  drivers/gpu/drm/i915/display/intel_opregion.c | 43 +++
>  drivers/gpu/drm/i915/display/intel_opregion.h |  6 +++
>  2 files changed, 49 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c 
> b/drivers/gpu/drm/i915/display/intel_opregion.c
> index 11d8c5bb23ac..c8cdcde89dfc 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> @@ -53,6 +53,8 @@
>  #define MBOX_ASLE_EXTBIT(4)  /* Mailbox #5 */
>  #define MBOX_BACKLIGHT   BIT(5)  /* Mailbox #2 (valid from v3.x) 
> */
>  
> +#define PCON_DG1_MBD_CONFIG  BIT(9)
> +#define PCON_DG1_MBD_CONFIG_FIELD_VALID  BIT(10)
>  #define PCON_DGFX_BIOS_SUPPORTS_VRSR BIT(11)
>  #define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID BIT(12)
>  #define PCON_HEADLESS_SKUBIT(13)
> @@ -1255,6 +1257,44 @@ void intel_opregion_unregister(struct drm_i915_private 
> *i915)
>   opregion->lid_state = NULL;
>  }
>  
> +static bool intel_opregion_dg1_mbd_config(struct drm_i915_private *i915)
> +{
> + struct intel_opregion *opregion = >opregion;
> +
> + if (!IS_DG1(i915))
> + return false;
> +
> + if (!opregion)

Like in previous patch, opregion is always non-NULL. Check for
!opregion->header.

> + return false;
> +
> + if (opregion->header->pcon & PCON_DG1_MBD_CONFIG_FIELD_VALID)
> + return opregion->header->pcon & PCON_DG1_MBD_CONFIG;
> + else
> + return false;
> +}
> +
> +/**
> + * intel_opregion_vram_sr_required().
> + * @i915 i915 device priv data.
> + *
> + * It checks whether a DGFX card is Mother Board Down config depending
> + * on respective discrete platform.
> + *
> + * Returns:
> + * It returns a boolean whether opregion vram_sr support is required.
> + */
> +bool
> +intel_opregion_vram_sr_required(struct drm_i915_private *i915)
> +{
> + if (!IS_DGFX(i915))
> + return false;
> +
> + if (IS_DG1(i915))
> + return intel_opregion_dg1_mbd_config(i915);

Only check for IS_DG1() here or in the function being called, not both.

> +
> + return false;
> +}
> +
>  /**
>   * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self
>   * Refresh capability support.
> @@ -1298,6 +1338,9 @@ void intel_opregion_vram_sr(struct drm_i915_private 
> *i915, bool enable)
>   if (!opregion)
>   return;
>  
> + if (!intel_opregion_vram_sr_required(i915))
> + return;

Feels like maybe this patch should be combined with the previous patch
due to this dependency.

> +
>   if (drm_WARN(>drm, !opregion->asle, "ASLE MAILBOX3 is not 
> available\n"))
>   return;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h 
> b/drivers/gpu/drm/i915/display/intel_opregion.h
> index 73c9d81d5ee6..ad40c97f9565 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.h
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.h
> @@ -77,6 +77,7 @@ int intel_opregion_get_panel_type(struct drm_i915_private 
> *dev_priv);
>  struct edid *intel_opregion_get_edid(struct intel_connector *connector);
>  bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915);
>  void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable);
> +bool intel_opregion_vram_sr_required(struct drm_i915_private *i915);
>  
>  bool intel_opregion_headless_sku(struct drm_i915_private *i915);
>  
> @@ -145,6 +146,11 @@ static void intel_opregion_vram_sr(struct 
> drm_i915_private *i915, bool enable)
>  {
>  }
>  
> +static bool intel_opregion_vram_sr_required(struct drm_i915_private *i915)

static inline.

BR,
Jani.

> +{
> + return false;
> +}
> +
>  #endif /* CONFIG_ACPI */
>  
>  #endif

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 1/9] drm/i915/dgfx: OpRegion VRAM Self Refresh Support

[Jani Nikula]

On Thu, 16 Jun 2022, Anshuman Gupta  wrote:
> Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR).
> DGFX VRSR can be enabled with runtime suspend D3Cold flow and with
> opportunistic S0ix system wide suspend flow as well.
>
> Without VRSR enablement i915 has to evict the lmem objects to
> system memory. Depending on some heuristics driver will evict
> lmem objects without VRSR.
>
> VRSR feature requires Host BIOS support, VRSR will be enable/disable
> by HOST BIOS using ACPI OpRegion.
>
> Adding OpRegion VRSR support in order to enable/disable
> VRSR on discrete cards.
>
> BSpec: 53440
> Cc: Jani Nikula 
> Cc: Rodrigo Vivi 
> Signed-off-by: Anshuman Gupta 
> ---
>  drivers/gpu/drm/i915/display/intel_opregion.c | 62 ++-
>  drivers/gpu/drm/i915/display/intel_opregion.h | 11 
>  2 files changed, 72 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c 
> b/drivers/gpu/drm/i915/display/intel_opregion.c
> index 6876ba30d5a9..11d8c5bb23ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> @@ -53,6 +53,8 @@
>  #define MBOX_ASLE_EXTBIT(4)  /* Mailbox #5 */
>  #define MBOX_BACKLIGHT   BIT(5)  /* Mailbox #2 (valid from v3.x) 
> */
>  
> +#define PCON_DGFX_BIOS_SUPPORTS_VRSR BIT(11)
> +#define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID BIT(12)
>  #define PCON_HEADLESS_SKUBIT(13)
>  
>  struct opregion_header {
> @@ -130,7 +132,8 @@ struct opregion_asle {
>   u64 rvda;   /* Physical (2.0) or relative from opregion (2.1+)
>* address of raw VBT data. */
>   u32 rvds;   /* Size of raw vbt data */
> - u8 rsvd[58];
> + u8 vrsr;/* DGFX Video Ram Self Refresh */
> + u8 rsvd[57];
>  } __packed;
>  
>  /* OpRegion mailbox #5: ASLE ext */
> @@ -201,6 +204,9 @@ struct opregion_asle_ext {
>  
>  #define ASLE_PHED_EDID_VALID_MASK0x3
>  
> +/* VRAM SR */
> +#define ASLE_VRSR_ENABLE BIT(0)
> +
>  /* Software System Control Interrupt (SWSCI) */
>  #define SWSCI_SCIC_INDICATOR (1 << 0)
>  #define SWSCI_SCIC_MAIN_FUNCTION_SHIFT   1
> @@ -921,6 +927,8 @@ int intel_opregion_setup(struct drm_i915_private 
> *dev_priv)
>   opregion->header->over.minor,
>   opregion->header->over.revision);
>  
> + drm_dbg(_priv->drm, "OpRegion PCON values 0x%x\n", 
> opregion->header->pcon);
> +
>   mboxes = opregion->header->mboxes;
>   if (mboxes & MBOX_ACPI) {
>   drm_dbg(_priv->drm, "Public ACPI methods supported\n");
> @@ -1246,3 +1254,55 @@ void intel_opregion_unregister(struct drm_i915_private 
> *i915)
>   opregion->vbt = NULL;
>   opregion->lid_state = NULL;
>  }
> +
> +/**
> + * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self
> + * Refresh capability support.
> + * @i915: pointer to i915 device.
> + *
> + * It checks opregion pcon vram_sr fields to get HOST BIOS vram_sr
> + * capability support. It is only applocable to DGFX.
> + *
> + * Returns:
> + * true when bios supports vram_sr, or false if bios doesn't support.
> + */
> +bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915)
> +{
> + struct intel_opregion *opregion = >opregion;
> +
> + if (!IS_DGFX(i915))
> + return false;
> +
> + if (!opregion)

This is always true. You should check for !opregion->header.

> + return false;
> +
> + if (opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID)
> + return opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR;
> + else
> + return false;
> +}
> +
> +/**
> + * intel_opregion_vram_sr() - enable/disable VRAM Self Refresh.
> + * @i915: pointer to i915 device.
> + * @enable: Argument to enable/disable VRSR.
> + *
> + * It enables/disables vram_sr in opregion ASLE MBOX, based upon that
> + * HOST BIOS will enables and disbales VRAM_SR during
> + * ACPI _PS3/_OFF and _PS/_ON glue method.
> + */
> +void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
> +{
> + struct intel_opregion *opregion = >opregion;
> +
> + if (!opregion)

Same as above.

> + return;
> +
> + if (drm_WARN(>drm, !opregion->asle, "ASLE MAILBOX3 is not 
> available\n"))
> + return;

I'd just bundle !opregion->asle into the early return.

> +
> + if (enable)
> + opregion->asle->vrsr |= ASLE_VRSR_ENABLE;
> + else
> + opregion->asle->vrsr &= ~ASLE_VRSR_ENABLE;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h 
> b/drivers/gpu/drm/i915/display/intel_opregion.h
> index 2f261f985400..73c9d81d5ee6 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.h
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.h
> @@ -75,6 +75,8 @@ int intel_opregion_notify_adapter(struct drm_i915_private 
> *dev_priv,
> pci_power_t state);
>  

[Intel-gfx] ✓ Fi.CI.BAT: success for Do not enable PSR2 if no active planes (rev3)

[Patchwork]

== Series Details ==

Series: Do not enable PSR2 if no active planes (rev3)
URL   : https://patchwork.freedesktop.org/series/105109/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11767 -> Patchwork_105109v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/index.html

Participating hosts (42 -> 43)
--

  Additional (2): bat-dg2-9 bat-atsm-1 
  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105109v3 that come from known issues:

### IGT changes ###

 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [DMESG-WARN][1] ([i915#5122]) -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-5:  [DMESG-FAIL][3] ([i915#4494] / [i915#4957]) -> 
[PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_busy@basic@flip:
- fi-tgl-u2:  [DMESG-WARN][5] ([i915#402]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/fi-tgl-u2/igt@kms_busy@ba...@flip.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/fi-tgl-u2/igt@kms_busy@ba...@flip.html

  * igt@kms_flip@basic-flip-vs-modeset@b-edp1:
- {bat-adlp-6}:   [DMESG-WARN][7] ([i915#3576]) -> [PASS][8] +1 similar 
issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@b-edp1.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@b-edp1.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- bat-adlp-4: [DMESG-WARN][9] ([i915#3576]) -> [PASS][10] +2 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11767/bat-adlp-4/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105109v3/bat-adlp-4/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
  [i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
  [i915#6244]: https://gitlab.freedesktop.org/drm/intel/issues/6244


Build changes
-

  * Linux: CI_DRM_11767 -> Patchwork_105109v3

  CI-20190529: 20190529
  CI_DRM_11767: 822a8442835012ce405080cb40f6317ef1e854ac @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6533: 6b5107d91827962808441db6b98e478aa9e67bdb @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_105109v3: 

Re: [Intel-gfx] [PATCH v2 6/9] drm/i915/dgfx: Setup VRAM SR with D3COLD

[Jani Nikula]

On Thu, 16 Jun 2022, Anshuman Gupta  wrote:
> Setup VRAM Self Refresh with D3COLD state.
> VRAM Self Refresh will retain the context of VRAM, driver
> need to save any corresponding hardware state that needs
> to be restore on D3COLD exit, example PCI state.
>
> Cc: Jani Nikula 
> Cc: Rodrigo Vivi 
> Signed-off-by: Anshuman Gupta 
> ---
>  drivers/gpu/drm/i915/i915_driver.c |  2 ++
>  drivers/gpu/drm/i915/i915_drv.h|  7 +
>  drivers/gpu/drm/i915/i915_reg.h|  4 +++
>  drivers/gpu/drm/i915/intel_pcode.c | 28 +++
>  drivers/gpu/drm/i915/intel_pcode.h |  2 ++
>  drivers/gpu/drm/i915/intel_pm.c| 43 ++
>  drivers/gpu/drm/i915/intel_pm.h|  2 ++
>  7 files changed, 88 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c 
> b/drivers/gpu/drm/i915/i915_driver.c
> index d26dcca7e654..aa1fb15b1f11 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -649,6 +649,8 @@ static int i915_driver_hw_probe(struct drm_i915_private 
> *dev_priv)
>   if (ret)
>   goto err_msi;
>  
> + intel_pm_vram_sr_setup(dev_priv);
> +
>   /*
>* Fill the dram structure to get the system dram info. This will be
>* used for memory latency calculation.
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7983b36c1720..09f53aeda8d0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -624,6 +624,13 @@ struct drm_i915_private {
>   u32 bxt_phy_grc;
>  
>   u32 suspend_count;
> +
> + struct {
> + /* lock to protect vram_sr flags */
> + struct mutex lock;
> + bool supported;
> + } vram_sr;
> +
>   struct i915_suspend_saved_registers regfile;
>   struct vlv_s0ix_state *vlv_s0ix_state;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 932bd6aa4a0a..0e3dc4a8846a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6766,6 +6766,8 @@
>  #define   DG1_PCODE_STATUS   0x7E
>  #define DG1_UNCORE_GET_INIT_STATUS   0x0
>  #define DG1_UNCORE_INIT_STATUS_COMPLETE  0x1
> +#define   DG1_PCODE_D3_VRAM_SR  0x71
> +#define DG1_ENABLE_SR0x1
>  #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US  0x23
>  #define   XEHPSDV_PCODE_FREQUENCY_CONFIG 0x6e/* xehpsdv, pvc 
> */
>  /* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
> @@ -6779,6 +6781,8 @@
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
>  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT   16
>  #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
> +#define VRAM_CAPABILITY _MMIO(0x138144)
> +#define   VRAM_SUPPORTEDREG_BIT(0)
>  
>  /* IVYBRIDGE DPF */
>  #define GEN7_L3CDERRST1(slice)   _MMIO(0xB008 + (slice) * 0x200) 
> /* L3CD Error Status 1 */
> diff --git a/drivers/gpu/drm/i915/intel_pcode.c 
> b/drivers/gpu/drm/i915/intel_pcode.c
> index a234d9b4ed14..88bd1f44cfb2 100644
> --- a/drivers/gpu/drm/i915/intel_pcode.c
> +++ b/drivers/gpu/drm/i915/intel_pcode.c
> @@ -246,3 +246,31 @@ int snb_pcode_write_p(struct intel_uncore *uncore, u32 
> mbcmd, u32 p1, u32 p2, u3
>  
>   return err;
>  }
> +
> +/**
> + * intel_pcode_enable_vram_sr - Enable pcode vram_sr.
> + * @dev_priv: i915 device
> + *
> + * This function triggers the required pcode flow to enable vram_sr.
> + * This function stictly need to call from rpm handlers, as i915 is
> + * transitioning to rpm idle/suspend, it doesn't require to grab
> + * rpm wakeref.
> + *
> + * Returns:
> + * returns returned value from pcode mbox write.
> + */
> +int intel_pcode_enable_vram_sr(struct drm_i915_private *i915)
> +{
> + int ret = 0;
> +
> + if (!HAS_LMEM_SR(i915))
> + return ret;
> +
> + ret = snb_pcode_write(>uncore,
> +   REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND,
> +   DG1_PCODE_D3_VRAM_SR) |
> +   REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1,
> +   DG1_ENABLE_SR), 0); /* no data needed for this 
> cmd */
> +
> + return ret;
> +}

This function doesn't belong here. intel_pcode.c provides the
*mechanisms* for pcode access, not specific stuff like this. Just put
this near the use in intel_pm.c I think.


> diff --git a/drivers/gpu/drm/i915/intel_pcode.h 
> b/drivers/gpu/drm/i915/intel_pcode.h
> index 8d2198e29422..295594514d49 100644
> --- a/drivers/gpu/drm/i915/intel_pcode.h
> +++ b/drivers/gpu/drm/i915/intel_pcode.h
> @@ -9,6 +9,7 @@
>  #include 
>  
>  struct intel_uncore;
> +struct drm_i915_private;
>  
>  int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 
> *val1);
>  int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
> @@ -26,5 +27,6 @@ int intel_pcode_init(struct 

[Intel-gfx] [PATCH] drm/i915/glk: ECS Liva Q2 needs GLK HDMI port timing quirk

[Jani Nikula]

From: Diego Santa Cruz 

The quirk added in upstream commit 90c3e2198777 ("drm/i915/glk: Add
Quirk for GLK NUC HDMI port issues.") is also required on the ECS Liva
Q2.

Note: Would be nicer to figure out the extra delay required for the
retimer without quirks, however don't know how to check for that.

Cc: sta...@vger.kernel.org
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1326
Signed-off-by: Diego Santa Cruz 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_quirks.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c 
b/drivers/gpu/drm/i915/display/intel_quirks.c
index c8488f5ebd04..e415cd7c0b84 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.c
+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
@@ -191,6 +191,9 @@ static struct intel_quirk intel_quirks[] = {
/* ASRock ITX*/
{ 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
{ 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
+   /* ECS Liva Q2 */
+   { 0x3185, 0x1019, 0xa94d, quirk_increase_ddi_disabled_time },
+   { 0x3184, 0x1019, 0xa94d, quirk_increase_ddi_disabled_time },
 };
 
 void intel_init_quirks(struct drm_i915_private *i915)
-- 
2.30.2

[Intel-gfx] [PATCH v2] drm/i915/dgfx: Disable d3cold at gfx root port

[Anshuman Gupta]

Currently i915 disables d3cold for i915 pci dev.
This blocks D3 for i915 gfx pci upstream bridge (VSP).
Let's disable d3cold at gfx root port to make sure that
i915 gfx VSP can transition to D3 to save some power.

We don't need to disable/enable d3cold in rpm, s2idle
suspend/resume handlers. Disabling/Enabling d3cold at
gfx root port in probe/remove phase is sufficient.

Fixes: 1a085e23411d ("drm/i915: Disable D3Cold in s2idle and runtime pm")
Cc: Rodrigo Vivi 
Signed-off-by: Anshuman Gupta 
Reviewed-by: Badal Nilawar 
---
 drivers/gpu/drm/i915/i915_driver.c | 34 +-
 1 file changed, 15 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index d26dcca7e654..86f9f0be76a6 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -546,6 +546,7 @@ static int i915_pcode_init(struct drm_i915_private *i915)
 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 {
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+   struct pci_dev *root_pdev;
int ret;
 
if (i915_inject_probe_failure(dev_priv))
@@ -657,6 +658,15 @@ static int i915_driver_hw_probe(struct drm_i915_private 
*dev_priv)
 
intel_bw_init_hw(dev_priv);
 
+   /*
+* FIXME: Temporary hammer to avoid freezing the machine on our DGFX
+* This should be totally removed when we handle the pci states properly
+* on runtime PM and on s2idle cases.
+*/
+   root_pdev = pcie_find_root_port(pdev);
+   if (root_pdev)
+   pci_d3cold_disable(root_pdev);
+
return 0;
 
 err_msi:
@@ -680,11 +690,16 @@ static int i915_driver_hw_probe(struct drm_i915_private 
*dev_priv)
 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 {
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+   struct pci_dev *root_pdev;
 
i915_perf_fini(dev_priv);
 
if (pdev->msi_enabled)
pci_disable_msi(pdev);
+
+   root_pdev = pcie_find_root_port(pdev);
+   if (root_pdev)
+   pci_d3cold_enable(root_pdev);
 }
 
 /**
@@ -1209,14 +1224,6 @@ static int i915_drm_suspend_late(struct drm_device *dev, 
bool hibernation)
goto out;
}
 
-   /*
-* FIXME: Temporary hammer to avoid freezing the machine on our DGFX
-* This should be totally removed when we handle the pci states properly
-* on runtime PM and on s2idle cases.
-*/
-   if (suspend_to_idle(dev_priv))
-   pci_d3cold_disable(pdev);
-
pci_disable_device(pdev);
/*
 * During hibernation on some platforms the BIOS may try to access
@@ -1381,8 +1388,6 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
pci_set_master(pdev);
 
-   pci_d3cold_enable(pdev);
-
disable_rpm_wakeref_asserts(_priv->runtime_pm);
 
ret = vlv_resume_prepare(dev_priv, false);
@@ -1559,7 +1564,6 @@ static int intel_runtime_suspend(struct device *kdev)
 {
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
struct intel_runtime_pm *rpm = _priv->runtime_pm;
-   struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
int ret;
 
if (drm_WARN_ON_ONCE(_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
@@ -1605,12 +1609,6 @@ static int intel_runtime_suspend(struct device *kdev)
drm_err(_priv->drm,
"Unclaimed access detected prior to suspending\n");
 
-   /*
-* FIXME: Temporary hammer to avoid freezing the machine on our DGFX
-* This should be totally removed when we handle the pci states properly
-* on runtime PM and on s2idle cases.
-*/
-   pci_d3cold_disable(pdev);
rpm->suspended = true;
 
/*
@@ -1649,7 +1647,6 @@ static int intel_runtime_resume(struct device *kdev)
 {
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
struct intel_runtime_pm *rpm = _priv->runtime_pm;
-   struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
int ret;
 
if (drm_WARN_ON_ONCE(_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
@@ -1662,7 +1659,6 @@ static int intel_runtime_resume(struct device *kdev)
 
intel_opregion_notify_adapter(dev_priv, PCI_D0);
rpm->suspended = false;
-   pci_d3cold_enable(pdev);
if (intel_uncore_unclaimed_mmio(_priv->uncore))
drm_dbg(_priv->drm,
"Unclaimed access during suspend, bios?\n");
-- 
2.26.2

[Intel-gfx] [PATCH i-g-t 2/2] drm/i915: Add lmem_bar_size modparam

[priyanka . dandamudi]

From: Priyanka Dandamudi 

For testing purposes, support forcing the lmem_bar_size through a new
modparam. In CI we only have a limited number of configurations for DG2,
but we still need to be reasonably sure we get a usable device (also
verifying we report the correct values for things like
probed_cpu_visible_size etc) with all the potential lmem_bar sizes that
we might expect see in the wild.

v2: Minor correction.(Matt)

Cc: Matthew Auld 
Signed-off-by: Priyanka Dandamudi 
---
 drivers/gpu/drm/i915/gt/intel_region_lmem.c |  4 +++
 drivers/gpu/drm/i915/i915_driver.c  | 28 -
 drivers/gpu/drm/i915/i915_params.c  |  2 ++
 drivers/gpu/drm/i915/i915_params.h  |  1 +
 4 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c 
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index e9c12e0d6f59..4614c30f878f 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -111,6 +111,10 @@ static struct intel_memory_region *setup_lmem(struct 
intel_gt *gt)
flat_ccs_base = intel_gt_read_register(gt, 
XEHPSDV_FLAT_CCS_BASE_ADDR);
flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * 
SZ_64K;
 
+   /* XXX: Remove this once we have small-bar uapi bits */
+   if (i915->params.lmem_bar_size > 0)
+   lmem_size = pci_resource_len(pdev, 2);
+
/* FIXME: Remove this when we have small-bar enabled */
if (pci_resource_len(pdev, 2) < lmem_size) {
drm_err(>drm, "System requires small-BAR support, 
which is currently unsupported on this kernel\n");
diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index 4bdb471cb2e2..b2763b032012 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -362,8 +362,34 @@ static void i915_resize_lmem_bar(struct drm_i915_private 
*i915)
u32 pci_cmd;
int i;
 
-   if (!rebar_size)
+   if (i915->params.lmem_bar_size > 0) {
+   u32 lmem_bar_size;
+   u32 set_bit;
+   u32 rebar;
+   u32 msb;
+   int k;
+
+   lmem_bar_size = i915->params.lmem_bar_size;
+   rebar = pci_rebar_get_possible_sizes(pdev, LMEM_BAR_NUM);
+   msb = __fls(rebar);
+
+   for (k = msb; k >= 0; k--) {
+   set_bit = (1 << k);
+
+   if (set_bit & rebar) {
+   if (set_bit == lmem_bar_size) {
+   rebar_size = 1ULL << 
(__fls(lmem_bar_size) +
+   BAR_SIZE_SHIFT);
+
+   if (rebar_size == 
pci_resource_len(pdev, LMEM_BAR_NUM))
+   return;
+   break;
+   }
+   }
+   }
+   } else if (!rebar_size) {
return;
+   }
 
/* Find out if root bus contains 64bit memory addressing */
while (root->parent)
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 701fbc98afa0..6fc475a5db61 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -204,6 +204,8 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
 
 i915_param_named_unsafe(lmem_size, uint, 0400,
"Set the lmem size(in MiB) for each region. (default: 
0, all memory)");
+i915_param_named_unsafe(lmem_bar_size, uint, 0400,
+   "Set the lmem bar size(in MiB).");
 
 static __always_inline void _print_param(struct drm_printer *p,
 const char *name,
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index b5e7ea45d191..2733cb6cfe09 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -74,6 +74,7 @@ struct drm_printer;
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
param(unsigned int, request_timeout_ms, 
CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
param(unsigned int, lmem_size, 0, 0400) \
+   param(unsigned int, lmem_bar_size, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, load_detect_test, false, 0600) \
-- 
2.25.1

[Intel-gfx] [PATCH i-g-t 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[priyanka . dandamudi]

From: Akeem G Abodunrin 

This patch adds support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
systems. So, those devices cannot claim larger memory BAR windows size due
to the system BIOS limitation. With this change, it would be possible to
reprogram the windows of the bridge directly above the requesting device
on the same BAR type.

Signed-off-by: Akeem G Abodunrin 
Signed-off-by: Michał Winiarski 
Cc: Stuart Summers 
Cc: Michael J Ruhl 
Cc: Prathap Kumar Valsan 
Signed-off-by: Priyanka Dandamudi 
Reviewed-by: Matthew Auld 
---
 drivers/gpu/drm/i915/i915_driver.c | 92 ++
 1 file changed, 92 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index d26dcca7e654..4bdb471cb2e2 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
__intel_gt_reset(to_gt(i915), ALL_ENGINES);
 }
 
+static void __release_bars(struct pci_dev *pdev)
+{
+   int resno;
+
+   for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
+   if (pci_resource_len(pdev, resno))
+   pci_release_resource(pdev, resno);
+   }
+}
+
+static void
+__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
+{
+   struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+   int bar_size = pci_rebar_bytes_to_size(size);
+   int ret;
+
+   __release_bars(pdev);
+
+   ret = pci_resize_resource(pdev, resno, bar_size);
+   if (ret) {
+   drm_info(>drm, "Failed to resize BAR%d to %dM (%pe)\n",
+resno, 1 << bar_size, ERR_PTR(ret));
+   return;
+   }
+
+   drm_info(>drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
+}
+
+/* BAR size starts from 1MB - 2^20 */
+#define BAR_SIZE_SHIFT 20
+static resource_size_t
+__lmem_rebar_size(struct drm_i915_private *i915, int resno)
+{
+   struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+   u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
+   resource_size_t size;
+
+   if (!rebar)
+   return 0;
+
+   size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
+
+   if (size <= pci_resource_len(pdev, resno))
+   return 0;
+
+   return size;
+}
+
+#define LMEM_BAR_NUM 2
+static void i915_resize_lmem_bar(struct drm_i915_private *i915)
+{
+   struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+   struct pci_bus *root = pdev->bus;
+   struct resource *root_res;
+   resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
+   u32 pci_cmd;
+   int i;
+
+   if (!rebar_size)
+   return;
+
+   /* Find out if root bus contains 64bit memory addressing */
+   while (root->parent)
+   root = root->parent;
+
+   pci_bus_for_each_resource(root, root_res, i) {
+   if (root_res && root_res->flags & (IORESOURCE_MEM |
+   IORESOURCE_MEM_64) && root_res->start > 
0x1ull)
+   break;
+   }
+
+   /* pci_resize_resource will fail anyways */
+   if (!root_res) {
+   drm_info(>drm, "Can't resize LMEM BAR - platform support 
is missing\n");
+   return;
+   }
+
+   /* First disable PCI memory decoding references */
+   pci_read_config_dword(pdev, PCI_COMMAND, _cmd);
+   pci_write_config_dword(pdev, PCI_COMMAND,
+  pci_cmd & ~PCI_COMMAND_MEMORY);
+
+   __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
+
+   pci_assign_unassigned_bus_resources(pdev->bus);
+   pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
+}
+
 /**
  * i915_driver_early_probe - setup state not requiring device access
  * @dev_priv: device private
@@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct 
pci_device_id *ent)
 
disable_rpm_wakeref_asserts(>runtime_pm);
 
+   if (HAS_LMEM(i915))
+   i915_resize_lmem_bar(i915);
+
intel_vgpu_detect(i915);
 
ret = intel_gt_probe_all(i915);
-- 
2.25.1

[Intel-gfx] [PATCH i-g-t 0/2] Add support for LMEM PCIe resizable bar

[priyanka . dandamudi]

From: Priyanka Dandamudi 

Added support to resize the bar to maximum supported.
Also, added new modparam lmem_bar_size which can resize the bar
to one of the supported sizes.

Akeem G Abodunrin (1):
  drm/i915: Add support for LMEM PCIe resizable bar

Priyanka Dandamudi (1):
  drm/i915: Add lmem_bar_size modparam

 drivers/gpu/drm/i915/gt/intel_region_lmem.c |   4 +
 drivers/gpu/drm/i915/i915_driver.c  | 118 
 drivers/gpu/drm/i915/i915_params.c  |   2 +
 drivers/gpu/drm/i915/i915_params.h  |   1 +
 4 files changed, 125 insertions(+)

-- 
2.25.1

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Tvrtko Ursulin]

On 16/06/2022 13:01, Anshuman Gupta wrote:

DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.

Cc: Matt Roper 
Signed-off-by: Anshuman Gupta 
---
  drivers/gpu/drm/i915/i915_drv.h  |  3 +++
  drivers/gpu/drm/i915/intel_device_info.c | 21 +
  drivers/gpu/drm/i915/intel_device_info.h | 11 +++
  include/drm/i915_pciids.h| 23 ---
  4 files changed, 47 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a5bc6a774c5a..f1f8699eedfd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
  #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
  
  #define IS_DG2_G10(dev_priv) \

+   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
  #define IS_DG2_G11(dev_priv) \
+   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
  #define IS_DG2_G12(dev_priv) \
+   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
  #define IS_ADLS_RPLS(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index f0bf23726ed8..93da555adc4e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
INTEL_RPLP_IDS(0),
  };
  
+static const u16 subplatform_g10_mb_mbd_ids[] = {

+   INTEL_DG2_G10_NB_MBD_IDS(0),
+};
+
+static const u16 subplatform_g11_mb_mbd_ids[] = {
+   INTEL_DG2_G11_NB_MBD_IDS(0),
+};
+
+static const u16 subplatform_g12_mb_mbd_ids[] = {
+   INTEL_DG2_G12_NB_MBD_IDS(0),
+};
+
  static const u16 subplatform_g10_ids[] = {
INTEL_DG2_G10_IDS(0),
INTEL_ATS_M150_IDS(0),
@@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct 
drm_i915_private *i915)
} else if (find_devid(devid, subplatform_rpl_ids,
  ARRAY_SIZE(subplatform_rpl_ids))) {
mask = BIT(INTEL_SUBPLATFORM_RPL);
+   } else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
+ ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
+   mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
+   } else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
+ ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
+   mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
+   } else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
+ ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
+   mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);
} else if (find_devid(devid, subplatform_g10_ids,
  ARRAY_SIZE(subplatform_g10_ids))) {
mask = BIT(INTEL_SUBPLATFORM_G10);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 08341174ee0a..c929e2d7e59c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -97,7 +97,7 @@ enum intel_platform {
   * it is fine for the same bit to be used on multiple parent platforms.
   */
  
-#define INTEL_SUBPLATFORM_BITS (3)

+#define INTEL_SUBPLATFORM_BITS (6)
  #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
  
  /* HSW/BDW/SKL/KBL/CFL */

@@ -111,9 +111,12 @@ enum intel_platform {
  #define INTEL_SUBPLATFORM_UY  (0)
  
  /* DG2 */

-#define INTEL_SUBPLATFORM_G10  0
-#define INTEL_SUBPLATFORM_G11  1
-#define INTEL_SUBPLATFORM_G12  2
+#define INTEL_SUBPLATFORM_G10_NB_MBD   0
+#define INTEL_SUBPLATFORM_G11_NB_MBD   1
+#define INTEL_SUBPLATFORM_G12_NB_MBD   2
+#define INTEL_SUBPLATFORM_G10  3
+#define INTEL_SUBPLATFORM_G11  4
+#define INTEL_SUBPLATFORM_G12  5


Ugh I feel this "breaks" the subplatform idea.. feels like it is just 
too many bits when two separate sets of information get tracked (Gxx 
plus MBD).


How about a separate "is_mbd" flag in runtime_info? You can split the 
PCI IDs split as you have done, but do a search against the MBD ones and 
set the flag.


Regards,

Tvrtko

  
  /* ADL */

  #define INTEL_SUBPLATFORM_RPL 0
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 4585fed4e41e..198be417bb2d 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -693,32 +693,41 @@
INTEL_VGA_DEVICE(0xA7A9, info)
  
  /* DG2 */

-#define INTEL_DG2_G10_IDS(info) \
+#define INTEL_DG2_G10_NB_MBD_IDS(info) \
INTEL_VGA_DEVICE(0x5690, info), 

[Intel-gfx] [PATCH v2 9/9] drm/i915/rpm: d3cold Policy

[Anshuman Gupta]

Add d3cold_sr_lmem_threshold modparam to choose between
d3cold-off zero watt and d3cold-VRAM Self Refresh.
i915 requires to evict the lmem objects to smem in order to
support d3cold-Off.

If gfx root port is not capable of sending PME from d3cold
then i915 don't need to program d3cold-off/d3cold-vram_sr
sequence.

FIXME: Eviction of lmem objects in case of D3Cold off is wip.

Cc: Rodrigo Vivi 
Signed-off-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/i915_driver.c | 27 ---
 drivers/gpu/drm/i915/i915_params.c |  4 
 drivers/gpu/drm/i915/i915_params.h |  3 ++-
 3 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index fcff5f3fe05e..aef4b17efdbe 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1560,15 +1560,36 @@ static int i915_pm_restore(struct device *kdev)
 static int intel_runtime_idle(struct device *kdev)
 {
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+   struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+   u64 lmem_total = to_gt(dev_priv)->lmem->total;
+   u64 lmem_avail = to_gt(dev_priv)->lmem->avail;
+   u64 lmem_used = lmem_total - lmem_avail;
+   struct pci_dev *root_pdev;
int ret = 1;
 
-   if (!HAS_LMEM_SR(dev_priv)) {
-   /*TODO: Prepare for D3Cold-Off */
+   root_pdev = pcie_find_root_port(pdev);
+   if (!root_pdev)
+   goto out;
+
+   if (!pci_pme_capable(root_pdev, PCI_D3cold))
goto out;
-   }
 
disable_rpm_wakeref_asserts(_priv->runtime_pm);
 
+   if (lmem_used < dev_priv->params.d3cold_sr_lmem_threshold  * 1024 * 
1024) {
+   drm_dbg(_priv->drm, "Prepare for D3Cold off\n");
+   pci_d3cold_enable(root_pdev);
+   /* FIXME: Eviction of lmem objects and guc reset is wip */
+   intel_pm_vram_sr(dev_priv, false);
+   enable_rpm_wakeref_asserts(_priv->runtime_pm);
+   goto out;
+   } else if (!HAS_LMEM_SR(dev_priv)) {
+   /* Disable D3Cold to reduce the eviction latency */
+   pci_d3cold_disable(root_pdev);
+   enable_rpm_wakeref_asserts(_priv->runtime_pm);
+   goto out;
+   }
+
ret = intel_pm_vram_sr(dev_priv, true);
if (!ret)
drm_dbg(_priv->drm, "VRAM Self Refresh enabled\n");
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 701fbc98afa0..6c6b3c372d4d 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -197,6 +197,10 @@ i915_param_named(enable_gvt, bool, 0400,
"Enable support for Intel GVT-g graphics virtualization host 
support(default:false)");
 #endif
 
+i915_param_named_unsafe(d3cold_sr_lmem_threshold, int, 0400,
+   "Enable Vidoe RAM Self refresh when size of lmem is greater to this 
threshold. "
+   "It helps to optimize the suspend/resume latecy. (default: 300mb)");
+
 #if CONFIG_DRM_I915_REQUEST_TIMEOUT
 i915_param_named_unsafe(request_timeout_ms, uint, 0600,
"Default request/fence/batch buffer expiration 
timeout.");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index b5e7ea45d191..28f20ebaf41f 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -83,7 +83,8 @@ struct drm_printer;
param(bool, verbose_state_checks, true, 0) \
param(bool, nuclear_pageflip, false, 0400) \
param(bool, enable_dp_mst, true, 0600) \
-   param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 
0)
+   param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 
0) \
+   param(int, d3cold_sr_lmem_threshold, 300, 0600) \
 
 #define MEMBER(T, member, ...) T member;
 struct i915_params {
-- 
2.26.2

[Intel-gfx] [PATCH v2 8/9] drm/i915/xehpsdv: Store lmem region in gt

[Anshuman Gupta]

From: Tvrtko Ursulin 

Store a pointer to respective local memory region in intel_gt so it can be
used when memory local to a GT needs to be allocated.

Cc: Andi Shyti 
Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/gt/intel_gt.c   | 1 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f33290358c51..7a535f670ae1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -91,6 +91,7 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
GEM_BUG_ON(!HAS_REGION(i915, id));
GEM_BUG_ON(i915->mm.regions[id]);
i915->mm.regions[id] = mem;
+   gt->lmem = mem;
 
return 0;
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index df708802889d..cd7744eaaeaa 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -23,6 +23,7 @@
 #include "intel_gt_buffer_pool_types.h"
 #include "intel_hwconfig.h"
 #include "intel_llc_types.h"
+#include "intel_memory_region.h"
 #include "intel_reset_types.h"
 #include "intel_rc6_types.h"
 #include "intel_rps_types.h"
@@ -202,6 +203,8 @@ struct intel_gt {
 */
phys_addr_t phys_addr;
 
+   struct intel_memory_region *lmem;
+
struct intel_gt_info {
unsigned int id;
 
-- 
2.26.2

[Intel-gfx] [PATCH v2 7/9] drm/i915/rpm: Enable D3Cold VRAM SR Support

[Anshuman Gupta]

Intel Client DGFX card supports D3Cold with two option.
D3Cold-off zero watt, D3Cold-VRAM Self Refresh.

i915 requires to evict the lmem objects to smem in order to
support D3Cold-Off, which increases i915 the suspend/resume
latency. Enabling VRAM Self Refresh feature optimize the
latency with additional power cost which required to retain
the lmem.

Adding intel_runtime_idle (runtime_idle callback) to enable
VRAM_SR, it will be used for policy to choose
between D3Cold-off vs D3Cold-VRAM_SR.

Since we have introduced i915 runtime_idle callback.
It need to be warranted that Runtime PM Core invokes runtime_idle
callback when runtime usages count becomes zero. That requires
to use pm_runtime_put instead of pm_runtime_put_autosuspend.

TODO: GuC interface state save/restore.

Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Signed-off-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/i915_driver.c  | 26 +
 drivers/gpu/drm/i915/intel_runtime_pm.c |  3 +--
 2 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index aa1fb15b1f11..fcff5f3fe05e 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1557,6 +1557,31 @@ static int i915_pm_restore(struct device *kdev)
return i915_pm_resume(kdev);
 }
 
+static int intel_runtime_idle(struct device *kdev)
+{
+   struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+   int ret = 1;
+
+   if (!HAS_LMEM_SR(dev_priv)) {
+   /*TODO: Prepare for D3Cold-Off */
+   goto out;
+   }
+
+   disable_rpm_wakeref_asserts(_priv->runtime_pm);
+
+   ret = intel_pm_vram_sr(dev_priv, true);
+   if (!ret)
+   drm_dbg(_priv->drm, "VRAM Self Refresh enabled\n");
+
+   enable_rpm_wakeref_asserts(_priv->runtime_pm);
+
+out:
+   pm_runtime_mark_last_busy(kdev);
+   pm_runtime_autosuspend(kdev);
+
+   return ret;
+}
+
 static int intel_runtime_suspend(struct device *kdev)
 {
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
@@ -1742,6 +1767,7 @@ const struct dev_pm_ops i915_pm_ops = {
.restore = i915_pm_restore,
 
/* S0ix (via runtime suspend) event handlers */
+   .runtime_idle = intel_runtime_idle,
.runtime_suspend = intel_runtime_suspend,
.runtime_resume = intel_runtime_resume,
 };
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6ed5786bcd29..4dade7e8a795 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -492,8 +492,7 @@ static void __intel_runtime_pm_put(struct intel_runtime_pm 
*rpm,
 
intel_runtime_pm_release(rpm, wakelock);
 
-   pm_runtime_mark_last_busy(kdev);
-   pm_runtime_put_autosuspend(kdev);
+   pm_runtime_put(kdev);
 }
 
 /**
-- 
2.26.2

[Intel-gfx] [PATCH v2 6/9] drm/i915/dgfx: Setup VRAM SR with D3COLD

[Anshuman Gupta]

Setup VRAM Self Refresh with D3COLD state.
VRAM Self Refresh will retain the context of VRAM, driver
need to save any corresponding hardware state that needs
to be restore on D3COLD exit, example PCI state.

Cc: Jani Nikula 
Cc: Rodrigo Vivi 
Signed-off-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/i915_driver.c |  2 ++
 drivers/gpu/drm/i915/i915_drv.h|  7 +
 drivers/gpu/drm/i915/i915_reg.h|  4 +++
 drivers/gpu/drm/i915/intel_pcode.c | 28 +++
 drivers/gpu/drm/i915/intel_pcode.h |  2 ++
 drivers/gpu/drm/i915/intel_pm.c| 43 ++
 drivers/gpu/drm/i915/intel_pm.h|  2 ++
 7 files changed, 88 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index d26dcca7e654..aa1fb15b1f11 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -649,6 +649,8 @@ static int i915_driver_hw_probe(struct drm_i915_private 
*dev_priv)
if (ret)
goto err_msi;
 
+   intel_pm_vram_sr_setup(dev_priv);
+
/*
 * Fill the dram structure to get the system dram info. This will be
 * used for memory latency calculation.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7983b36c1720..09f53aeda8d0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -624,6 +624,13 @@ struct drm_i915_private {
u32 bxt_phy_grc;
 
u32 suspend_count;
+
+   struct {
+   /* lock to protect vram_sr flags */
+   struct mutex lock;
+   bool supported;
+   } vram_sr;
+
struct i915_suspend_saved_registers regfile;
struct vlv_s0ix_state *vlv_s0ix_state;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 932bd6aa4a0a..0e3dc4a8846a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6766,6 +6766,8 @@
 #define   DG1_PCODE_STATUS 0x7E
 #define DG1_UNCORE_GET_INIT_STATUS 0x0
 #define DG1_UNCORE_INIT_STATUS_COMPLETE0x1
+#define   DG1_PCODE_D3_VRAM_SR  0x71
+#define DG1_ENABLE_SR0x1
 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
 #define   XEHPSDV_PCODE_FREQUENCY_CONFIG   0x6e/* xehpsdv, pvc 
*/
 /* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
@@ -6779,6 +6781,8 @@
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT   8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
 #define GEN6_PCODE_DATA1   _MMIO(0x13812C)
+#define VRAM_CAPABILITY _MMIO(0x138144)
+#define   VRAM_SUPPORTEDREG_BIT(0)
 
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
diff --git a/drivers/gpu/drm/i915/intel_pcode.c 
b/drivers/gpu/drm/i915/intel_pcode.c
index a234d9b4ed14..88bd1f44cfb2 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -246,3 +246,31 @@ int snb_pcode_write_p(struct intel_uncore *uncore, u32 
mbcmd, u32 p1, u32 p2, u3
 
return err;
 }
+
+/**
+ * intel_pcode_enable_vram_sr - Enable pcode vram_sr.
+ * @dev_priv: i915 device
+ *
+ * This function triggers the required pcode flow to enable vram_sr.
+ * This function stictly need to call from rpm handlers, as i915 is
+ * transitioning to rpm idle/suspend, it doesn't require to grab
+ * rpm wakeref.
+ *
+ * Returns:
+ * returns returned value from pcode mbox write.
+ */
+int intel_pcode_enable_vram_sr(struct drm_i915_private *i915)
+{
+   int ret = 0;
+
+   if (!HAS_LMEM_SR(i915))
+   return ret;
+
+   ret = snb_pcode_write(>uncore,
+ REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND,
+ DG1_PCODE_D3_VRAM_SR) |
+ REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1,
+ DG1_ENABLE_SR), 0); /* no data needed for this 
cmd */
+
+   return ret;
+}
diff --git a/drivers/gpu/drm/i915/intel_pcode.h 
b/drivers/gpu/drm/i915/intel_pcode.h
index 8d2198e29422..295594514d49 100644
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -9,6 +9,7 @@
 #include 
 
 struct intel_uncore;
+struct drm_i915_private;
 
 int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
 int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
@@ -26,5 +27,6 @@ int intel_pcode_init(struct intel_uncore *uncore);
  */
 int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, 
u32 *val);
 int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, 
u32 val);
+int intel_pcode_enable_vram_sr(struct drm_i915_private *i915);
 
 #endif /* _INTEL_PCODE_H */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5a61fc3f26c1..299fbc5375a9 100644
--- 

[Intel-gfx] [PATCH v2 5/9] drm/i915/dgfx: Add has_lmem_sr

[Anshuman Gupta]

Add has_lmem_sr platform specific flag to know,
whether platform has VRAM self refresh support.
As of now both DG1 and DG2 client platforms supports VRAM self refresh
with D3Cold but let it enable first on DG2 as primary lead platform
for D3Cold support. Let it get enable on DG1 once this feature
is stable.

Cc: Rodrigo Vivi 
Signed-off-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/i915_drv.h  | 1 +
 drivers/gpu/drm/i915/i915_pci.c  | 2 ++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 28eee8088822..7983b36c1720 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1313,6 +1313,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
+#define HAS_LMEM_SR(i915) (INTEL_INFO(i915)->has_lmem_sr)
 
 /*
  * Platform has the dedicated compression control state for each lmem surfaces
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5e51fc29bb8b..04aad54033dd 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -917,6 +917,7 @@ static const struct intel_device_info dg1_info = {
DGFX_FEATURES,
.graphics.rel = 10,
PLATFORM(INTEL_DG1),
+   .has_lmem_sr = 0,
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | 
BIT(PIPE_D),
.require_force_probe = 1,
.platform_engine_mask =
@@ -1074,6 +1075,7 @@ static const struct intel_device_info xehpsdv_info = {
 static const struct intel_device_info dg2_info = {
DG2_FEATURES,
XE_LPD_FEATURES,
+   .has_lmem_sr = 1,
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
   BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
.require_force_probe = 1,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index c929e2d7e59c..db51cdb9e09a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -157,6 +157,7 @@ enum intel_ppgtt_type {
func(has_l3_ccs_read); \
func(has_l3_dpf); \
func(has_llc); \
+   func(has_lmem_sr); \
func(has_logical_ring_contexts); \
func(has_logical_ring_elsq); \
func(has_media_ratio_mode); \
-- 
2.26.2

[Intel-gfx] [PATCH v2 4/9] drm/i915/dg2: DG2 MBD config

[Anshuman Gupta]

Add DG2 Motherboard Down Config check support.

v2:
- Don't use pciid to check DG2 MBD. [Jani]

BSpec: 44477
Cc: Rodrigo Vivi 
Signed-off-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++
 drivers/gpu/drm/i915/i915_drv.h   | 9 +
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c 
b/drivers/gpu/drm/i915/display/intel_opregion.c
index c8cdcde89dfc..50dcd6d3558e 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -1291,6 +1291,8 @@ intel_opregion_vram_sr_required(struct drm_i915_private 
*i915)
 
if (IS_DG1(i915))
return intel_opregion_dg1_mbd_config(i915);
+   else if (IS_DG2_MBD(i915))
+   return true;
 
return false;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f1f8699eedfd..28eee8088822 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1006,6 +1006,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_DG2(dev_priv)   IS_PLATFORM(dev_priv, INTEL_DG2)
 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
 
+#define IS_DG2_G10_NB_MBD(dev_priv) \
+   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD)
+#define IS_DG2_G11_NB_MBD(dev_priv) \
+   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD)
+#define IS_DG2_G12_NB_MBD(dev_priv) \
+   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD)
 #define IS_DG2_G10(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
@@ -1015,6 +1021,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_DG2_G12(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
+
+#define IS_DG2_MBD(dev_priv) (IS_DG2_G10_NB_MBD(dev_priv) || 
IS_DG2_G11_NB_MBD(dev_priv) || \
+ IS_DG2_G12_NB_MBD(dev_priv))
 #define IS_ADLS_RPLS(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_N(dev_priv) \
-- 
2.26.2

[Intel-gfx] [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Anshuman Gupta]

DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.

Cc: Matt Roper 
Signed-off-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/i915_drv.h  |  3 +++
 drivers/gpu/drm/i915/intel_device_info.c | 21 +
 drivers/gpu/drm/i915/intel_device_info.h | 11 +++
 include/drm/i915_pciids.h| 23 ---
 4 files changed, 47 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a5bc6a774c5a..f1f8699eedfd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
 
 #define IS_DG2_G10(dev_priv) \
+   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
 #define IS_DG2_G11(dev_priv) \
+   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 #define IS_DG2_G12(dev_priv) \
+   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
 #define IS_ADLS_RPLS(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index f0bf23726ed8..93da555adc4e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
INTEL_RPLP_IDS(0),
 };
 
+static const u16 subplatform_g10_mb_mbd_ids[] = {
+   INTEL_DG2_G10_NB_MBD_IDS(0),
+};
+
+static const u16 subplatform_g11_mb_mbd_ids[] = {
+   INTEL_DG2_G11_NB_MBD_IDS(0),
+};
+
+static const u16 subplatform_g12_mb_mbd_ids[] = {
+   INTEL_DG2_G12_NB_MBD_IDS(0),
+};
+
 static const u16 subplatform_g10_ids[] = {
INTEL_DG2_G10_IDS(0),
INTEL_ATS_M150_IDS(0),
@@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct 
drm_i915_private *i915)
} else if (find_devid(devid, subplatform_rpl_ids,
  ARRAY_SIZE(subplatform_rpl_ids))) {
mask = BIT(INTEL_SUBPLATFORM_RPL);
+   } else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
+ ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
+   mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
+   } else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
+ ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
+   mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
+   } else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
+ ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
+   mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);
} else if (find_devid(devid, subplatform_g10_ids,
  ARRAY_SIZE(subplatform_g10_ids))) {
mask = BIT(INTEL_SUBPLATFORM_G10);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 08341174ee0a..c929e2d7e59c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -97,7 +97,7 @@ enum intel_platform {
  * it is fine for the same bit to be used on multiple parent platforms.
  */
 
-#define INTEL_SUBPLATFORM_BITS (3)
+#define INTEL_SUBPLATFORM_BITS (6)
 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
 
 /* HSW/BDW/SKL/KBL/CFL */
@@ -111,9 +111,12 @@ enum intel_platform {
 #define INTEL_SUBPLATFORM_UY   (0)
 
 /* DG2 */
-#define INTEL_SUBPLATFORM_G10  0
-#define INTEL_SUBPLATFORM_G11  1
-#define INTEL_SUBPLATFORM_G12  2
+#define INTEL_SUBPLATFORM_G10_NB_MBD   0
+#define INTEL_SUBPLATFORM_G11_NB_MBD   1
+#define INTEL_SUBPLATFORM_G12_NB_MBD   2
+#define INTEL_SUBPLATFORM_G10  3
+#define INTEL_SUBPLATFORM_G11  4
+#define INTEL_SUBPLATFORM_G12  5
 
 /* ADL */
 #define INTEL_SUBPLATFORM_RPL  0
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 4585fed4e41e..198be417bb2d 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -693,32 +693,41 @@
INTEL_VGA_DEVICE(0xA7A9, info)
 
 /* DG2 */
-#define INTEL_DG2_G10_IDS(info) \
+#define INTEL_DG2_G10_NB_MBD_IDS(info) \
INTEL_VGA_DEVICE(0x5690, info), \
INTEL_VGA_DEVICE(0x5691, info), \
-   INTEL_VGA_DEVICE(0x5692, info), \
+   INTEL_VGA_DEVICE(0x5692, info)
+
+#define INTEL_DG2_G11_NB_MBD_IDS(info) \
+   INTEL_VGA_DEVICE(0x5693, info), \
+   INTEL_VGA_DEVICE(0x5694, info), \
+   INTEL_VGA_DEVICE(0x5695, info)
+
+#define INTEL_DG2_G12_NB_MBD_IDS(info) \
+   INTEL_VGA_DEVICE(0x5696, info), \
+   INTEL_VGA_DEVICE(0x5697, 

[Intel-gfx] [PATCH v2 2/9] drm/i915/dg1: OpRegion PCON DG1 MBD config support

[Anshuman Gupta]

DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD)
configs. MBD config requires HOST BIOS GPIO toggling support
in order to enable/disable VRAM SR using ACPI OpRegion.

i915 requires to check OpRegion PCON MBD Config bits to
discover whether Gfx Card is MBD config before enabling
VRSR.

BSpec: 53440
Cc: Jani Nikula 
Cc: Rodrigo Vivi 
Signed-off-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 43 +++
 drivers/gpu/drm/i915/display/intel_opregion.h |  6 +++
 2 files changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c 
b/drivers/gpu/drm/i915/display/intel_opregion.c
index 11d8c5bb23ac..c8cdcde89dfc 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -53,6 +53,8 @@
 #define MBOX_ASLE_EXT  BIT(4)  /* Mailbox #5 */
 #define MBOX_BACKLIGHT BIT(5)  /* Mailbox #2 (valid from v3.x) */
 
+#define PCON_DG1_MBD_CONFIGBIT(9)
+#define PCON_DG1_MBD_CONFIG_FIELD_VALIDBIT(10)
 #define PCON_DGFX_BIOS_SUPPORTS_VRSR   BIT(11)
 #define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID   BIT(12)
 #define PCON_HEADLESS_SKU  BIT(13)
@@ -1255,6 +1257,44 @@ void intel_opregion_unregister(struct drm_i915_private 
*i915)
opregion->lid_state = NULL;
 }
 
+static bool intel_opregion_dg1_mbd_config(struct drm_i915_private *i915)
+{
+   struct intel_opregion *opregion = >opregion;
+
+   if (!IS_DG1(i915))
+   return false;
+
+   if (!opregion)
+   return false;
+
+   if (opregion->header->pcon & PCON_DG1_MBD_CONFIG_FIELD_VALID)
+   return opregion->header->pcon & PCON_DG1_MBD_CONFIG;
+   else
+   return false;
+}
+
+/**
+ * intel_opregion_vram_sr_required().
+ * @i915 i915 device priv data.
+ *
+ * It checks whether a DGFX card is Mother Board Down config depending
+ * on respective discrete platform.
+ *
+ * Returns:
+ * It returns a boolean whether opregion vram_sr support is required.
+ */
+bool
+intel_opregion_vram_sr_required(struct drm_i915_private *i915)
+{
+   if (!IS_DGFX(i915))
+   return false;
+
+   if (IS_DG1(i915))
+   return intel_opregion_dg1_mbd_config(i915);
+
+   return false;
+}
+
 /**
  * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self
  * Refresh capability support.
@@ -1298,6 +1338,9 @@ void intel_opregion_vram_sr(struct drm_i915_private 
*i915, bool enable)
if (!opregion)
return;
 
+   if (!intel_opregion_vram_sr_required(i915))
+   return;
+
if (drm_WARN(>drm, !opregion->asle, "ASLE MAILBOX3 is not 
available\n"))
return;
 
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h 
b/drivers/gpu/drm/i915/display/intel_opregion.h
index 73c9d81d5ee6..ad40c97f9565 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.h
+++ b/drivers/gpu/drm/i915/display/intel_opregion.h
@@ -77,6 +77,7 @@ int intel_opregion_get_panel_type(struct drm_i915_private 
*dev_priv);
 struct edid *intel_opregion_get_edid(struct intel_connector *connector);
 bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915);
 void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable);
+bool intel_opregion_vram_sr_required(struct drm_i915_private *i915);
 
 bool intel_opregion_headless_sku(struct drm_i915_private *i915);
 
@@ -145,6 +146,11 @@ static void intel_opregion_vram_sr(struct drm_i915_private 
*i915, bool enable)
 {
 }
 
+static bool intel_opregion_vram_sr_required(struct drm_i915_private *i915)
+{
+   return false;
+}
+
 #endif /* CONFIG_ACPI */
 
 #endif
-- 
2.26.2

[Intel-gfx] [PATCH v2 1/9] drm/i915/dgfx: OpRegion VRAM Self Refresh Support

[Anshuman Gupta]

Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR).
DGFX VRSR can be enabled with runtime suspend D3Cold flow and with
opportunistic S0ix system wide suspend flow as well.

Without VRSR enablement i915 has to evict the lmem objects to
system memory. Depending on some heuristics driver will evict
lmem objects without VRSR.

VRSR feature requires Host BIOS support, VRSR will be enable/disable
by HOST BIOS using ACPI OpRegion.

Adding OpRegion VRSR support in order to enable/disable
VRSR on discrete cards.

BSpec: 53440
Cc: Jani Nikula 
Cc: Rodrigo Vivi 
Signed-off-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 62 ++-
 drivers/gpu/drm/i915/display/intel_opregion.h | 11 
 2 files changed, 72 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c 
b/drivers/gpu/drm/i915/display/intel_opregion.c
index 6876ba30d5a9..11d8c5bb23ac 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -53,6 +53,8 @@
 #define MBOX_ASLE_EXT  BIT(4)  /* Mailbox #5 */
 #define MBOX_BACKLIGHT BIT(5)  /* Mailbox #2 (valid from v3.x) */
 
+#define PCON_DGFX_BIOS_SUPPORTS_VRSR   BIT(11)
+#define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID   BIT(12)
 #define PCON_HEADLESS_SKU  BIT(13)
 
 struct opregion_header {
@@ -130,7 +132,8 @@ struct opregion_asle {
u64 rvda;   /* Physical (2.0) or relative from opregion (2.1+)
 * address of raw VBT data. */
u32 rvds;   /* Size of raw vbt data */
-   u8 rsvd[58];
+   u8 vrsr;/* DGFX Video Ram Self Refresh */
+   u8 rsvd[57];
 } __packed;
 
 /* OpRegion mailbox #5: ASLE ext */
@@ -201,6 +204,9 @@ struct opregion_asle_ext {
 
 #define ASLE_PHED_EDID_VALID_MASK  0x3
 
+/* VRAM SR */
+#define ASLE_VRSR_ENABLE   BIT(0)
+
 /* Software System Control Interrupt (SWSCI) */
 #define SWSCI_SCIC_INDICATOR   (1 << 0)
 #define SWSCI_SCIC_MAIN_FUNCTION_SHIFT 1
@@ -921,6 +927,8 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
opregion->header->over.minor,
opregion->header->over.revision);
 
+   drm_dbg(_priv->drm, "OpRegion PCON values 0x%x\n", 
opregion->header->pcon);
+
mboxes = opregion->header->mboxes;
if (mboxes & MBOX_ACPI) {
drm_dbg(_priv->drm, "Public ACPI methods supported\n");
@@ -1246,3 +1254,55 @@ void intel_opregion_unregister(struct drm_i915_private 
*i915)
opregion->vbt = NULL;
opregion->lid_state = NULL;
 }
+
+/**
+ * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self
+ * Refresh capability support.
+ * @i915: pointer to i915 device.
+ *
+ * It checks opregion pcon vram_sr fields to get HOST BIOS vram_sr
+ * capability support. It is only applocable to DGFX.
+ *
+ * Returns:
+ * true when bios supports vram_sr, or false if bios doesn't support.
+ */
+bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915)
+{
+   struct intel_opregion *opregion = >opregion;
+
+   if (!IS_DGFX(i915))
+   return false;
+
+   if (!opregion)
+   return false;
+
+   if (opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID)
+   return opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR;
+   else
+   return false;
+}
+
+/**
+ * intel_opregion_vram_sr() - enable/disable VRAM Self Refresh.
+ * @i915: pointer to i915 device.
+ * @enable: Argument to enable/disable VRSR.
+ *
+ * It enables/disables vram_sr in opregion ASLE MBOX, based upon that
+ * HOST BIOS will enables and disbales VRAM_SR during
+ * ACPI _PS3/_OFF and _PS/_ON glue method.
+ */
+void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
+{
+   struct intel_opregion *opregion = >opregion;
+
+   if (!opregion)
+   return;
+
+   if (drm_WARN(>drm, !opregion->asle, "ASLE MAILBOX3 is not 
available\n"))
+   return;
+
+   if (enable)
+   opregion->asle->vrsr |= ASLE_VRSR_ENABLE;
+   else
+   opregion->asle->vrsr &= ~ASLE_VRSR_ENABLE;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h 
b/drivers/gpu/drm/i915/display/intel_opregion.h
index 2f261f985400..73c9d81d5ee6 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.h
+++ b/drivers/gpu/drm/i915/display/intel_opregion.h
@@ -75,6 +75,8 @@ int intel_opregion_notify_adapter(struct drm_i915_private 
*dev_priv,
  pci_power_t state);
 int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
 struct edid *intel_opregion_get_edid(struct intel_connector *connector);
+bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915);
+void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable);
 
 bool intel_opregion_headless_sku(struct drm_i915_private *i915);
 
@@ -134,6 +136,15 @@ 

[Intel-gfx] [PATCH v2 0/9] DG2 VRAM_SR Support

[Anshuman Gupta]

This series add DG2 D3Cold VRAM_SR support.

TODO: GuC Interface state save/restore on VRAM_SR entry/exit.

Anshuman Gupta (8):
  drm/i915/dgfx: OpRegion VRAM Self Refresh Support
  drm/i915/dg1: OpRegion PCON DG1 MBD config support
  drm/i915/dg2: Add DG2_NB_MBD subplatform
  drm/i915/dg2: DG2 MBD config
  drm/i915/dgfx: Add has_lmem_sr
  drm/i915/dgfx: Setup VRAM SR with D3COLD
  drm/i915/rpm: Enable D3Cold VRAM SR Support
  drm/i915/rpm: d3cold Policy

Tvrtko Ursulin (1):
  drm/i915/xehpsdv: Store lmem region in gt

 drivers/gpu/drm/i915/display/intel_opregion.c | 107 +-
 drivers/gpu/drm/i915/display/intel_opregion.h |  17 +++
 drivers/gpu/drm/i915/gt/intel_gt.c|   1 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h  |   3 +
 drivers/gpu/drm/i915/i915_driver.c|  49 
 drivers/gpu/drm/i915/i915_drv.h   |  20 
 drivers/gpu/drm/i915/i915_params.c|   4 +
 drivers/gpu/drm/i915/i915_params.h|   3 +-
 drivers/gpu/drm/i915/i915_pci.c   |   2 +
 drivers/gpu/drm/i915/i915_reg.h   |   4 +
 drivers/gpu/drm/i915/intel_device_info.c  |  21 
 drivers/gpu/drm/i915/intel_device_info.h  |  12 +-
 drivers/gpu/drm/i915/intel_pcode.c|  28 +
 drivers/gpu/drm/i915/intel_pcode.h|   2 +
 drivers/gpu/drm/i915/intel_pm.c   |  43 +++
 drivers/gpu/drm/i915/intel_pm.h   |   2 +
 drivers/gpu/drm/i915/intel_runtime_pm.c   |   3 +-
 include/drm/i915_pciids.h |  23 ++--
 18 files changed, 329 insertions(+), 15 deletions(-)

-- 
2.26.2

Re: [Intel-gfx] [PATCH 02/10] drm/i915/uapi: add probed_cpu_visible_size

[Intel]

On 5/25/22 20:43, Matthew Auld wrote:

Userspace wants to know the size of CPU visible portion of device
local-memory, and on small BAR devices the probed_size is no longer
enough. In Vulkan, for example, it would like to know the size in bytes
for CPU visible VkMemoryHeap. We already track the io_size for each
region, so it's just case of plumbing that through to the region query.

Nit: so plumb that through (imperative)


Testcase: igt@i915_query@query-regions-sanity-check
Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Lionel Landwerlin 
Cc: Tvrtko Ursulin 
Cc: Jon Bloomfield 
Cc: Daniel Vetter 
Cc: Jordan Justen 
Cc: Kenneth Graunke 
Cc: Akeem G Abodunrin 
---
  drivers/gpu/drm/i915/i915_query.c |  6 +++
  include/uapi/drm/i915_drm.h   | 74 +--
  2 files changed, 47 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index 7584cec53d5d..9aa0b28aa6ee 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -496,6 +496,12 @@ static int query_memregion_info(struct drm_i915_private 
*i915,
info.region.memory_class = mr->type;
info.region.memory_instance = mr->instance;
info.probed_size = mr->total;
+
+   if (mr->type == INTEL_MEMORY_LOCAL)
+   info.probed_cpu_visible_size = mr->io_size;
+   else
+   info.probed_cpu_visible_size = mr->total;
+
info.unallocated_size = mr->avail;
  
  		if (__copy_to_user(info_ptr, , sizeof(info)))

diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index de49b68b4fc8..9df419a45244 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3207,36 +3207,6 @@ struct drm_i915_gem_memory_class_instance {
   * struct drm_i915_memory_region_info - Describes one region as known to the
   * driver.
   *
- * Note that we reserve some stuff here for potential future work. As an 
example
- * we might want expose the capabilities for a given region, which could 
include
- * things like if the region is CPU mappable/accessible, what are the supported
- * mapping types etc.
- *
- * Note that to extend struct drm_i915_memory_region_info and struct
- * drm_i915_query_memory_regions in the future the plan is to do the following:
- *
- * .. code-block:: C
- *
- * struct drm_i915_memory_region_info {
- * struct drm_i915_gem_memory_class_instance region;
- * union {
- * __u32 rsvd0;
- * __u32 new_thing1;
- * };
- * ...
- * union {
- * __u64 rsvd1[8];
- * struct {
- * __u64 new_thing2;
- * __u64 new_thing3;
- * ...
- * };
- * };
- * };
- *
- * With this things should remain source compatible between versions for
- * userspace, even as we add new fields.
- *
   * Note this is using both struct drm_i915_query_item and struct 
drm_i915_query.
   * For this new query we are adding the new query id 
DRM_I915_QUERY_MEMORY_REGIONS
   * at _i915_query_item.query_id.
@@ -3248,14 +3218,52 @@ struct drm_i915_memory_region_info {
/** @rsvd0: MBZ */
__u32 rsvd0;
  
-	/** @probed_size: Memory probed by the driver (-1 = unknown) */

+   /**
+* @probed_size: Memory probed by the driver (-1 = unknown)
+*
+* Note that it should not be possible to ever encounter a zero value
+* here, also note that no current region type will ever return -1 here.
+* Although for future region types, this might be a possibility. The
+* same applies to the other size fields.
+*/
__u64 probed_size;
  
  	/** @unallocated_size: Estimate of memory remaining (-1 = unknown) */

__u64 unallocated_size;
  
-	/** @rsvd1: MBZ */

-   __u64 rsvd1[8];
+   union {
+   /** @rsvd1: MBZ */
+   __u64 rsvd1[8];
+   struct {
+   /**
+* @probed_cpu_visible_size: Memory probed by the driver
+* that is CPU accessible. (-1 = unknown).
+*
+* This will be always be <= @probed_size, and the
+* remainder (if there is any) will not be CPU
+* accessible.
+*
+* On systems without small BAR, the @probed_size will
+* always equal the @probed_cpu_visible_size, since all
+* of it will be CPU accessible.
+*
+* Note this is only tracked for
+* I915_MEMORY_CLASS_DEVICE regions (for other types the
+* value here will always