[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Don't update engine busyness stats too frequently (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Don't update engine busyness stats too frequently (rev3)
URL   : https://patchwork.freedesktop.org/series/105023/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11776 -> Patchwork_105023v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/index.html

Participating hosts (35 -> 35)
--

  Additional (2): fi-cml-u2 fi-icl-u2 
  Missing(2): fi-rkl-11600 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105023v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][1] ([i915#1208]) +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_exec_suspend@basic-s0@smem:
- fi-cml-u2:  NOTRUN -> [DMESG-WARN][2] ([i915#5122])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/fi-cml-u2/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-cml-u2:  NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/fi-cml-u2/igt@gem_huc_c...@huc-copy.html
- fi-icl-u2:  NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-cml-u2:  NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/fi-cml-u2/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [PASS][7] -> [DMESG-FAIL][8] ([i915#62])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][9] -> [DMESG-FAIL][10] ([i915#4528])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@ring_submission:
- fi-cfl-8109u:   [PASS][11] -> [DMESG-WARN][12] ([i915#5904]) +11 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u:   [PASS][13] -> [DMESG-WARN][14] ([i915#5904] / 
[i915#62])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([i915#5903])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/fi-icl-u2/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@invalid-set-prop:
- fi-cfl-8109u:   [PASS][16] -> [DMESG-WARN][17] ([i915#62]) +78 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-cfl-8109u/igt@kms_addfb_ba...@invalid-set-prop.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/fi-cfl-8109u/igt@kms_addfb_ba...@invalid-set-prop.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][18] ([fdo#111827]) +8 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_chamelium@vga-hpd-fast:
- fi-cml-u2:  NOTRUN -> [SKIP][19] ([fdo#109284] / [fdo#111827]) +7 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/fi-cml-u2/igt@kms_chamel...@vga-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-cml-u2:  NOTRUN -> [SKIP][20] ([fdo#109278]) +1 similar issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105023v3/fi-cml-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
- fi-icl-u2:  NOTRUN -> [SKIP][21] ([fdo#109278] / [i915#4103]) +1 
similar issue
   [21]: 
https://

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix a lockdep warning at error capture

[Patchwork]

== Series Details ==

Series: drm/i915: Fix a lockdep warning at error capture
URL   : https://patchwork.freedesktop.org/series/105291/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11776_full -> Patchwork_105291v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_105291v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_105291v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105291v1_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_atomic_transition@modeset-transition-nonblocking@1x-outputs:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-tglb7/igt@kms_atomic_transition@modeset-transition-nonblock...@1x-outputs.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/shard-tglb8/igt@kms_atomic_transition@modeset-transition-nonblock...@1x-outputs.html

  
Known issues


  Here are the changes found in Patchwork_105291v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-glk:  ([PASS][3], [PASS][4], [PASS][5], [PASS][6], 
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
[PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44], [FAIL][45], [PASS][46], [PASS][47], [PASS][48], 
[PASS][49], [PASS][50], [PASS][51], [PASS][52]) ([i915#4392])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk1/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk1/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk1/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk2/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk2/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk2/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk3/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk3/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk3/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk4/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk4/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk4/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk5/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk5/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk5/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk6/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk6/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk6/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk7/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk7/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk8/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk8/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk8/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk9/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/shard-glk9/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/shard-glk9/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/shard-glk9/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/shard-glk9/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/shard-glk8/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/shard-glk8/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/shard-glk8/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/shard-glk7/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tr

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Don't update engine busyness stats too frequently (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Don't update engine busyness stats too frequently (rev3)
URL   : https://patchwork.freedesktop.org/series/105023/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] [Intel-gfx v2 1/1] drm/i915/guc: Don't update engine busyness stats too frequently

[Alan Previn]

Using igt's gem-create and with additional patches to track object
creation time, it was measured that guc_update_engine_gt_clks was
getting called over 188 thousand times in the span of 15 seconds
(running the test three times).

Get a jiffies sample on every trigger and ensure we skip sampling
if we are being called too soon. Use half of the ping_delay as a
safe threshold.

NOTE: with this change, the number of calls went down to just 14
over the same span of time (matching the original intent of running
about once every 24 seconds, at 19.2Mhz GT freq, per engine).

Signed-off-by: Alan Previn 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  8 
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 966e69a8b1c1..26f3e4403de7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -230,6 +230,14 @@ struct intel_guc {
 * @shift: Right shift value for the gpm timestamp
 */
u32 shift;
+
+   /**
+* @last_jiffies: jiffies at last actual stats collection time
+* We use this timestamp to ensure we don't oversample the
+* stats because runtime power management events can trigger
+* stats collection at much higher rates than required.
+*/
+   u64 last_stat_jiffs;
} timestamp;
 
 #ifdef CONFIG_DRM_I915_SELFTEST
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e62ea35513ea..05c945f14ef5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1314,6 +1314,8 @@ static void __update_guc_busyness_stats(struct intel_guc 
*guc)
unsigned long flags;
ktime_t unused;
 
+   guc->timestamp.last_stat_jiffs = get_jiffies_64();
+
spin_lock_irqsave(&guc->timestamp.lock, flags);
 
guc_update_pm_timestamp(guc, &unused);
@@ -1386,6 +1388,16 @@ void intel_guc_busyness_park(struct intel_gt *gt)
return;
 
cancel_delayed_work(&guc->timestamp.work);
+
+   /*
+* Before parking, we should sample engine busyness stats if we need to.
+* We can skip it if we are less than half a ping from the last time we
+* sampled the business stats.
+*/
+   if (guc->timestamp.last_stat_jiffs && (get_jiffies_64() - 
guc->timestamp.last_stat_jiffs  <
+  (guc->timestamp.ping_delay >> 1)))
+   return;
+
__update_guc_busyness_stats(guc);
 }
 
-- 
2.25.1

[Intel-gfx] [Intel-gfx v2 0/1] drm/i915/guc: Don't update engine busyness stats too frequently

[Alan Previn]

This change ensures we don't collect new stat counters too soon
after the last sample.

Changes from prior revs:
  v1:  - Move the location of the new logic to higher up
 the callstack in intel_guc_busyness_park (Umesh).
   - Fix typo threshold of jiffies-since-last from double
 to half of ping_delay (Umesh)

Alan Previn (1):
  drm/i915/guc: Don't update engine busyness stats too frequently

 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  8 
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 
 2 files changed, 20 insertions(+)


base-commit: ac17a5249380aaabe5d1eaebd9b3a2eedc08ccdc
-- 
2.25.1

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Fix HDMI transcoder clock vs. DDI BUF disabling order

[Patchwork]

== Series Details ==

Series: drm/i915/tgl+: Fix HDMI transcoder clock vs. DDI BUF disabling order
URL   : https://patchwork.freedesktop.org/series/105290/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11775_full -> Patchwork_105290v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_105290v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_105290v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 10)
--

  Missing(3): shard-rkl shard-dg1 shard-tglu 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105290v1_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_atomic_transition@modeset-transition-nonblocking@1x-outputs:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-tglb5/igt@kms_atomic_transition@modeset-transition-nonblock...@1x-outputs.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/shard-tglb3/igt@kms_atomic_transition@modeset-transition-nonblock...@1x-outputs.html

  
Known issues


  Here are the changes found in Patchwork_105290v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-apl:  ([PASS][3], [PASS][4], [PASS][5], [PASS][6], 
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
[PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], 
[PASS][49], [PASS][50], [FAIL][51], [PASS][52]) ([i915#4386])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl8/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl8/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl8/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl8/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl7/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl7/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl6/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl6/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl6/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl4/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl3/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl3/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl3/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl3/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl2/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl2/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl2/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl2/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl1/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl1/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl1/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/shard-apl2/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/shard-apl1/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/shard-apl8/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/shard-apl1/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/shard-apl8/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/shard-apl8/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/shard-apl7/boot.html
   [35

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] agp/intel: Rename intel-gtt symbols

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] agp/intel: Rename intel-gtt symbols
URL   : https://patchwork.freedesktop.org/series/105322/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11776 -> Patchwork_105322v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105322v1/index.html

Participating hosts (35 -> 35)
--

  Additional (2): fi-cml-u2 fi-icl-u2 
  Missing(2): fi-bdw-samus fi-kbl-8809g 

Known issues


  Here are the changes found in Patchwork_105322v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_create@basic-files:
- fi-icl-u2:  NOTRUN -> [DMESG-WARN][1] ([i915#4890])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105322v1/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][2] ([i915#1208]) +1 similar issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105322v1/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-cml-u2:  NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105322v1/fi-cml-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-cml-u2:  NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105322v1/fi-cml-u2/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [PASS][5] -> [DMESG-FAIL][6] ([i915#62])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105322v1/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@gem:
- fi-blb-e6850:   NOTRUN -> [DMESG-FAIL][7] ([i915#4528])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105322v1/fi-blb-e6850/igt@i915_selftest@l...@gem.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][8] -> [INCOMPLETE][9] ([i915#3921])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105322v1/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][10] -> [DMESG-FAIL][11] ([i915#4528])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105322v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@ring_submission:
- fi-cfl-8109u:   [PASS][12] -> [DMESG-WARN][13] ([i915#5904]) +29 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105322v1/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u:   [PASS][14] -> [DMESG-WARN][15] ([i915#5904] / 
[i915#62])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105322v1/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [PASS][16] -> [INCOMPLETE][17] ([i915#5982])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105322v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@vga-hpd-fast:
- fi-cml-u2:  NOTRUN -> [SKIP][18] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105322v1/fi-cml-u2/igt@kms_chamel...@vga-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-cml-u2:  NOTRUN -> [SKIP][19] ([fdo#109278]) +1 similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105322v1/fi-cml-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- fi-tgl-u2:  [PASS][20] -> [DMESG-WARN][21] ([i915#402]) +1 
similar issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105322v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2

Re: [Intel-gfx] [PATCH v2 1/1] i915/gem: drop wbinvd_on_all_cpus usage

[Lucas De Marchi]

On Thu, Apr 14, 2022 at 11:19:23AM -0700, Michael Cheng wrote:

Previous concern with using drm_clflush_sg was that we don't know what the
sg_table is pointing to, thus the usage of wbinvd_on_all_cpus to flush
everything at once to avoid paranoia.


humn... and now we know it is backed by struct pages? I'm not sure I
follow what we didn't know before and now we do.

Thomas / Matthew, could you take another look herer if it seems correct
to you.


thanks
Lucas De Marchi



To make i915 more architecture-neutral and be less paranoid, lets attempt to
use drm_clflush_sg to flush the pages for when the GPU wants to read
from main memory.

Signed-off-by: Michael Cheng 
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c 
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index f5062d0c6333..b0a5baaebc43 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -8,6 +8,7 @@
#include 
#include 
#include 
+#include 

#include 

@@ -250,16 +251,10 @@ static int i915_gem_object_get_pages_dmabuf(struct 
drm_i915_gem_object *obj)
 * DG1 is special here since it still snoops transactions even with
 * CACHE_NONE. This is not the case with other HAS_SNOOP platforms. We
 * might need to revisit this as we add new discrete platforms.
-*
-* XXX: Consider doing a vmap flush or something, where possible.
-* Currently we just do a heavy handed wbinvd_on_all_cpus() here since
-* the underlying sg_table might not even point to struct pages, so we
-* can't just call drm_clflush_sg or similar, like we do elsewhere in
-* the driver.
 */
if (i915_gem_object_can_bypass_llc(obj) ||
(!HAS_LLC(i915) && !IS_DG1(i915)))
-   wbinvd_on_all_cpus();
+   drm_clflush_sg(pages);

sg_page_sizes = i915_sg_dma_sizes(pages->sgl);
__i915_gem_object_set_pages(obj, pages, sg_page_sizes);
--
2.25.1

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/bios: calculate panel type as per child device index in VBT (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/bios: calculate panel type as per child device index in VBT 
(rev2)
URL   : https://patchwork.freedesktop.org/series/104943/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11775_full -> Patchwork_104943v2_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 10)
--

  Missing(3): shard-rkl shard-dg1 shard-tglu 

Known issues


  Here are the changes found in Patchwork_104943v2_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][1] -> [SKIP][2] ([i915#4525])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb1/igt@gem_exec_balan...@parallel-out-fence.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/shard-iclb5/igt@gem_exec_balan...@parallel-out-fence.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  NOTRUN -> [FAIL][3] ([i915#2842]) +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2842])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-tglb5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl:  [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl6/igt@gem_exec_fair@basic-p...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/shard-kbl3/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_huc_copy@huc-copy:
- shard-apl:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/shard-apl6/igt@gem_huc_c...@huc-copy.html
- shard-tglb: [PASS][9] -> [SKIP][10] ([i915#2190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-tglb5/igt@gem_huc_c...@huc-copy.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/shard-tglb7/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@heavy-verify-random:
- shard-kbl:  NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/shard-kbl4/igt@gem_lmem_swapp...@heavy-verify-random.html
- shard-skl:  NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/shard-skl4/igt@gem_lmem_swapp...@heavy-verify-random.html

  * igt@gem_lmem_swapping@verify:
- shard-apl:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/shard-apl6/igt@gem_lmem_swapp...@verify.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-skl:  NOTRUN -> [WARN][14] ([i915#2658])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/shard-skl4/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_userptr_blits@vma-merge:
- shard-kbl:  NOTRUN -> [FAIL][15] ([i915#3318])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/shard-kbl4/igt@gem_userptr_bl...@vma-merge.html

  * igt@gen9_exec_parse@allowed-all:
- shard-glk:  [PASS][16] -> [DMESG-WARN][17] ([i915#5566] / 
[i915#716]) +1 similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-glk5/igt@gen9_exec_pa...@allowed-all.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/shard-glk6/igt@gen9_exec_pa...@allowed-all.html

  * igt@i915_module_load@load:
- shard-skl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#6227])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/shard-skl4/igt@i915_module_l...@load.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- shard-skl:  [PASS][19] -> [DMESG-WARN][20] ([i915#1982])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl7/igt@i915_susp...@basic-s2idle-without-i915.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/shard-skl4/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@i915_suspend@sysfs-reader:
- shard-apl:  [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +2 
similar issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl8/igt@i915_susp...@sysfs-reader.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/shard-apl3/igt@i915_susp...@sysfs-reader.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-ap

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/2] agp/intel: Rename intel-gtt symbols

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] agp/intel: Rename intel-gtt symbols
URL   : https://patchwork.freedesktop.org/series/105322/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] agp/intel: Rename intel-gtt symbols

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] agp/intel: Rename intel-gtt symbols
URL   : https://patchwork.freedesktop.org/series/105322/
State : warning

== Summary ==

Error: dim checkpatch failed
7c8c549dd225 agp/intel: Rename intel-gtt symbols
3ed50cac8cf9 drm/i915/gt: Re-do the intel-gtt split
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:674: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#674: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 857 lines checked

Re: [Intel-gfx] [PATCH v2 2/2] vfio: Replace the iommu notifier with a device list

[Alex Williamson]

On Tue,  7 Jun 2022 20:02:12 -0300
Jason Gunthorpe  wrote:

> Instead of bouncing the function call to the driver op through a blocking
> notifier just have the iommu layer call it directly.
> 
> Register each device that is being attached to the iommu with the lower
> driver which then threads them on a linked list and calls the appropriate
> driver op at the right time.
> 
> Currently the only use is if dma_unmap() is defined.
> 
> Also, fully lock all the debugging tests on the pinning path that a
> dma_unmap is registered.
> 
> Signed-off-by: Jason Gunthorpe 
> ---
>  drivers/vfio/vfio.c |  42 -
>  drivers/vfio/vfio.h |  14 ++---
>  drivers/vfio/vfio_iommu_type1.c | 103 
>  include/linux/vfio.h|   2 +-
>  4 files changed, 83 insertions(+), 78 deletions(-)
> 
> diff --git a/drivers/vfio/vfio.c b/drivers/vfio/vfio.c
> index f005b644ab9e69..065b57e601bff7 100644
> --- a/drivers/vfio/vfio.c
> +++ b/drivers/vfio/vfio.c
> @@ -619,6 +619,9 @@ EXPORT_SYMBOL_GPL(vfio_register_group_dev);
>   */
>  int vfio_register_emulated_iommu_dev(struct vfio_device *device)
>  {
> + if (WARN_ON(!device->ops->dma_unmap))
> + return -EINVAL;
> +
>   return __vfio_register_dev(device,
>   vfio_noiommu_group_alloc(device->dev, VFIO_EMULATED_IOMMU));
>  }
> @@ -1077,17 +1080,6 @@ static void vfio_device_unassign_container(struct 
> vfio_device *device)
>   up_write(&device->group->group_rwsem);
>  }
>  
> -static int vfio_iommu_notifier(struct notifier_block *nb, unsigned long 
> action,
> -void *data)
> -{
> - struct vfio_device *vfio_device =
> - container_of(nb, struct vfio_device, iommu_nb);
> - struct vfio_iommu_type1_dma_unmap *unmap = data;
> -
> - vfio_device->ops->dma_unmap(vfio_device, unmap->iova, unmap->size);
> - return NOTIFY_OK;
> -}
> -
>  static struct file *vfio_device_open(struct vfio_device *device)
>  {
>   struct vfio_iommu_driver *iommu_driver;
> @@ -1123,15 +1115,9 @@ static struct file *vfio_device_open(struct 
> vfio_device *device)
>   }
>  
>   iommu_driver = device->group->container->iommu_driver;
> - if (device->ops->dma_unmap && iommu_driver &&
> - iommu_driver->ops->register_notifier) {
> - unsigned long events = VFIO_IOMMU_NOTIFY_DMA_UNMAP;
> -
> - device->iommu_nb.notifier_call = vfio_iommu_notifier;
> - iommu_driver->ops->register_notifier(
> - device->group->container->iommu_data, &events,
> - &device->iommu_nb);
> - }
> + if (iommu_driver && iommu_driver->ops->register_device)
> + iommu_driver->ops->register_device(
> + device->group->container->iommu_data, device);
>  
>   up_read(&device->group->group_rwsem);
>   }
> @@ -1171,11 +1157,9 @@ static struct file *vfio_device_open(struct 
> vfio_device *device)
>   device->ops->close_device(device);
>  
>   iommu_driver = device->group->container->iommu_driver;
> - if (device->ops->dma_unmap && iommu_driver &&
> - iommu_driver->ops->register_notifier)
> - iommu_driver->ops->unregister_notifier(
> - device->group->container->iommu_data,
> - &device->iommu_nb);
> + if (iommu_driver && iommu_driver->ops->register_device)
> + iommu_driver->ops->unregister_device(
> + device->group->container->iommu_data, device);

But let's fix this in the next respin too, ie. test register but call
unregister.  Got it right below in this one.

>   }
>  err_undo_count:
>   device->open_count--;
> @@ -1380,11 +1364,9 @@ static int vfio_device_fops_release(struct inode 
> *inode, struct file *filep)
>   device->ops->close_device(device);
>  
>   iommu_driver = device->group->container->iommu_driver;
> - if (device->ops->dma_unmap && iommu_driver &&
> - iommu_driver->ops->register_notifier)
> - iommu_driver->ops->unregister_notifier(
> - device->group->container->iommu_data,
> - &device->iommu_nb);
> + if (iommu_driver && iommu_driver->ops->unregister_device)
> + iommu_driver->ops->unregister_device(
> + device->group->container->iommu_data, device);
>   up_read(&device->group->group_rwsem);
>   device->open_count--;
>   if (device->open_count == 0)
> diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
> index cb2e4e9baa8fe8..4a7db1f3c33e7e 100644
> --- a/drivers/vfio/vfio.h
> +++ b/drivers/vfio/vfio.h
> @@ -33,11 +33,6 @@ enum vfio_iommu_notify_type {
>   VFIO_IOMMU_CONTAINER_CLOSE = 0,
>  };
>  
> -/* events for regist

[Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Re-do the intel-gtt split

[Lucas De Marchi]

Re-do what was attempted in commit 7a5c922377b4 ("drm/i915/gt: Split
intel-gtt functions by arch"). The goal of that commit was to split the
handlers for older hardware that depend on intel-gtt.ko so i915 can
be built for non-x86 archs, after some more patches. Other archs do not
need intel-gtt.ko.

Main issue with the previous approach: it moved all the hooks, including
the gen8, which is used by all platforms gen8 and newer.  Re-do the
split moving only the handlers for gen < 6, which are the only ones
calling out to the separate module.

While at it do some minor cleanups:
  - Rename the prefix s/gen5_/gmch_/ to be more accurate what platforms
are covered by intel_ggtt_gmch.c
  - Remove dead code for gen12 out of needs_idle_maps()
  - Remove TODO comment leftover
  - Re-order if/else ladder in ggtt_probe_hw() to keep newest platforms
first

v2: Add minor cleanups (Matt Roper)

Signed-off-by: Lucas De Marchi 
Acked-by: Tvrtko Ursulin 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/Makefile |   2 +-
 drivers/gpu/drm/i915/gt/intel_ggtt.c  | 561 ++-
 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c | 132 +
 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h |  27 +
 drivers/gpu/drm/i915/gt/intel_gt.c|   5 +-
 drivers/gpu/drm/i915/gt/intel_gt.h|   9 -
 drivers/gpu/drm/i915/gt/intel_gt_gmch.c   | 654 --
 drivers/gpu/drm/i915/gt/intel_gt_gmch.h   |  46 --
 drivers/gpu/drm/i915/gt/intel_gtt.h   |  12 +-
 9 files changed, 714 insertions(+), 734 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h
 delete mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.c
 delete mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6c17d3d6db24..2d9815fd2f88 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -130,7 +130,7 @@ gt-y += \
gt/shmem_utils.o \
gt/sysfs_engines.o
 # x86 intel-gtt module support
-gt-$(CONFIG_X86) += gt/intel_gt_gmch.o
+gt-$(CONFIG_X86) += gt/intel_ggtt_gmch.o
 # autogenerated null render state
 gt-y += \
gt/gen6_renderstate.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index e6b2eb122ad7..d4f1d1626e81 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -3,16 +3,18 @@
  * Copyright © 2020 Intel Corporation
  */
 
-#include 
 #include 
 #include 
+#include 
+#include 
 
 #include 
+#include 
 
 #include "gem/i915_gem_lmem.h"
 
+#include "intel_ggtt_gmch.h"
 #include "intel_gt.h"
-#include "intel_gt_gmch.h"
 #include "intel_gt_regs.h"
 #include "i915_drv.h"
 #include "i915_scatterlist.h"
@@ -181,7 +183,7 @@ void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
spin_unlock_irq(&uncore->lock);
 }
 
-void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
+static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 
@@ -218,11 +220,232 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
return pte;
 }
 
+static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
+{
+   writeq(pte, addr);
+}
+
+static void gen8_ggtt_insert_page(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ enum i915_cache_level level,
+ u32 flags)
+{
+   struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+   gen8_pte_t __iomem *pte =
+   (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
+
+   gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
+
+   ggtt->invalidate(ggtt);
+}
+
+static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
+struct i915_vma_resource *vma_res,
+enum i915_cache_level level,
+u32 flags)
+{
+   const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
+   struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+   gen8_pte_t __iomem *gte;
+   gen8_pte_t __iomem *end;
+   struct sgt_iter iter;
+   dma_addr_t addr;
+
+   /*
+* Note that we ignore PTE_READ_ONLY here. The caller must be careful
+* not to allow the user to override access to a read only page.
+*/
+
+   gte = (gen8_pte_t __iomem *)ggtt->gsm;
+   gte += vma_res->start / I915_GTT_PAGE_SIZE;
+   end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
+
+   for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
+   gen8_set_pte(gte++, pte_encode | addr);
+   GEM_BUG_ON(gte > end);
+
+   /* Fill the allocated but "unused" space beyond the end of the buffer */
+   while (gte < end)
+   gen8_set_pte(gte++, vm->scratch[0]->enc

[Intel-gfx] [PATCH v2 1/2] agp/intel: Rename intel-gtt symbols

[Lucas De Marchi]

Exporting the symbols like intel_gtt_* creates some confusion inside
i915 that has symbols named similarly. In an attempt to isolate
platforms needing intel-gtt.ko, commit 7a5c922377b4 ("drm/i915/gt: Split
intel-gtt functions by arch") moved way too much
inside gt/intel_gt_gmch.c, even the functions that don't callout to this
module. Rename the symbols to make the separation clear.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/char/agp/intel-gtt.c| 58 -
 drivers/gpu/drm/i915/gt/intel_gt_gmch.c | 16 +++
 include/drm/intel-gtt.h | 24 +-
 3 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 79a1b65527c2..fe7e2105e766 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -744,7 +744,7 @@ static void i830_write_entry(dma_addr_t addr, unsigned int 
entry,
writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
 }
 
-bool intel_enable_gtt(void)
+bool intel_gmch_enable_gtt(void)
 {
u8 __iomem *reg;
 
@@ -787,7 +787,7 @@ bool intel_enable_gtt(void)
 
return true;
 }
-EXPORT_SYMBOL(intel_enable_gtt);
+EXPORT_SYMBOL(intel_gmch_enable_gtt);
 
 static int i830_setup(void)
 {
@@ -821,8 +821,8 @@ static int intel_fake_agp_free_gatt_table(struct 
agp_bridge_data *bridge)
 
 static int intel_fake_agp_configure(void)
 {
-   if (!intel_enable_gtt())
-   return -EIO;
+   if (!intel_gmch_enable_gtt())
+   return -EIO;
 
intel_private.clear_fake_agp = true;
agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
@@ -844,20 +844,20 @@ static bool i830_check_flags(unsigned int flags)
return false;
 }
 
-void intel_gtt_insert_page(dma_addr_t addr,
-  unsigned int pg,
-  unsigned int flags)
+void intel_gmch_gtt_insert_page(dma_addr_t addr,
+   unsigned int pg,
+   unsigned int flags)
 {
intel_private.driver->write_entry(addr, pg, flags);
readl(intel_private.gtt + pg);
if (intel_private.driver->chipset_flush)
intel_private.driver->chipset_flush();
 }
-EXPORT_SYMBOL(intel_gtt_insert_page);
+EXPORT_SYMBOL(intel_gmch_gtt_insert_page);
 
-void intel_gtt_insert_sg_entries(struct sg_table *st,
-unsigned int pg_start,
-unsigned int flags)
+void intel_gmch_gtt_insert_sg_entries(struct sg_table *st,
+ unsigned int pg_start,
+ unsigned int flags)
 {
struct scatterlist *sg;
unsigned int len, m;
@@ -879,13 +879,13 @@ void intel_gtt_insert_sg_entries(struct sg_table *st,
if (intel_private.driver->chipset_flush)
intel_private.driver->chipset_flush();
 }
-EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
+EXPORT_SYMBOL(intel_gmch_gtt_insert_sg_entries);
 
 #if IS_ENABLED(CONFIG_AGP_INTEL)
-static void intel_gtt_insert_pages(unsigned int first_entry,
-  unsigned int num_entries,
-  struct page **pages,
-  unsigned int flags)
+static void intel_gmch_gtt_insert_pages(unsigned int first_entry,
+   unsigned int num_entries,
+   struct page **pages,
+   unsigned int flags)
 {
int i, j;
 
@@ -905,7 +905,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory 
*mem,
if (intel_private.clear_fake_agp) {
int start = intel_private.stolen_size / PAGE_SIZE;
int end = intel_private.gtt_mappable_entries;
-   intel_gtt_clear_range(start, end - start);
+   intel_gmch_gtt_clear_range(start, end - start);
intel_private.clear_fake_agp = false;
}
 
@@ -934,12 +934,12 @@ static int intel_fake_agp_insert_entries(struct 
agp_memory *mem,
if (ret != 0)
return ret;
 
-   intel_gtt_insert_sg_entries(&st, pg_start, type);
+   intel_gmch_gtt_insert_sg_entries(&st, pg_start, type);
mem->sg_list = st.sgl;
mem->num_sg = st.nents;
} else
-   intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
-  type);
+   intel_gmch_gtt_insert_pages(pg_start, mem->page_count, 
mem->pages,
+   type);
 
 out:
ret = 0;
@@ -949,7 +949,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory 
*mem,
 }
 #endif
 
-void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
+void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int 
num_entries)
 {
unsigned 

Re: [Intel-gfx] [PATCH v2 1/2] vfio: Replace the DMA unmapping notifier with a callback

[Alex Williamson]

On Fri, 17 Jun 2022 16:42:30 -0600
Alex Williamson  wrote:

> On Tue,  7 Jun 2022 20:02:11 -0300
> Jason Gunthorpe  wrote:
> > diff --git a/drivers/vfio/vfio.c b/drivers/vfio/vfio.c
> > index 61e71c1154be67..f005b644ab9e69 100644
> > --- a/drivers/vfio/vfio.c
> > +++ b/drivers/vfio/vfio.c
> > @@ -1077,8 +1077,20 @@ static void vfio_device_unassign_container(struct 
> > vfio_device *device)
> > up_write(&device->group->group_rwsem);
> >  }
> >  
> > +static int vfio_iommu_notifier(struct notifier_block *nb, unsigned long 
> > action,
> > +  void *data)
> > +{
> > +   struct vfio_device *vfio_device =
> > +   container_of(nb, struct vfio_device, iommu_nb);
> > +   struct vfio_iommu_type1_dma_unmap *unmap = data;
> > +
> > +   vfio_device->ops->dma_unmap(vfio_device, unmap->iova, unmap->size);
> > +   return NOTIFY_OK;
> > +}
> > +
> >  static struct file *vfio_device_open(struct vfio_device *device)
> >  {
> > +   struct vfio_iommu_driver *iommu_driver;
> > struct file *filep;
> > int ret;
> >  
> > @@ -1109,6 +1121,18 @@ static struct file *vfio_device_open(struct 
> > vfio_device *device)
> > if (ret)
> > goto err_undo_count;
> > }
> > +
> > +   iommu_driver = device->group->container->iommu_driver;
> > +   if (device->ops->dma_unmap && iommu_driver &&
> > +   iommu_driver->ops->register_notifier) {
> > +   unsigned long events = VFIO_IOMMU_NOTIFY_DMA_UNMAP;
> > +
> > +   device->iommu_nb.notifier_call = vfio_iommu_notifier;
> > +   iommu_driver->ops->register_notifier(
> > +   device->group->container->iommu_data, &events,
> > +   &device->iommu_nb);
> > +   }
> > +
> > up_read(&device->group->group_rwsem);
> > }
> > mutex_unlock(&device->dev_set->lock);
> > @@ -1143,8 +1167,16 @@ static struct file *vfio_device_open(struct 
> > vfio_device *device)
> >  err_close_device:
> > mutex_lock(&device->dev_set->lock);
> > down_read(&device->group->group_rwsem);
> > -   if (device->open_count == 1 && device->ops->close_device)
> > +   if (device->open_count == 1 && device->ops->close_device) {
> > device->ops->close_device(device);
> > +
> > +   iommu_driver = device->group->container->iommu_driver;
> > +   if (device->ops->dma_unmap && iommu_driver &&
> > +   iommu_driver->ops->register_notifier)  
> 
> Test for register_notifier callback...
> 
> > +   iommu_driver->ops->unregister_notifier(
> > +   device->group->container->iommu_data,
> > +   &device->iommu_nb);  
> 
> use unregister_notifier callback.  Same below.
> 
> > +   }
> >  err_undo_count:
> > device->open_count--;
> > if (device->open_count == 0 && device->kvm)
> > @@ -1339,12 +1371,20 @@ static const struct file_operations vfio_group_fops 
> > = {
> >  static int vfio_device_fops_release(struct inode *inode, struct file 
> > *filep)
> >  {
> > struct vfio_device *device = filep->private_data;
> > +   struct vfio_iommu_driver *iommu_driver;
> >  
> > mutex_lock(&device->dev_set->lock);
> > vfio_assert_device_open(device);
> > down_read(&device->group->group_rwsem);
> > if (device->open_count == 1 && device->ops->close_device)
> > device->ops->close_device(device);
> > +
> > +   iommu_driver = device->group->container->iommu_driver;
> > +   if (device->ops->dma_unmap && iommu_driver &&
> > +   iommu_driver->ops->register_notifier)
> > +   iommu_driver->ops->unregister_notifier(
> > +   device->group->container->iommu_data,
> > +   &device->iommu_nb);
> > up_read(&device->group->group_rwsem);
> > device->open_count--;
> > if (device->open_count == 0)
> > @@ -2027,90 +2067,6 @@ int vfio_dma_rw(struct vfio_device *device, 
> > dma_addr_t user_iova, void *data,
> >  }
> >  EXPORT_SYMBOL(vfio_dma_rw);
> >  
> > -static int vfio_register_iommu_notifier(struct vfio_group *group,
> > -   unsigned long *events,
> > -   struct notifier_block *nb)
> > -{
> > -   struct vfio_container *container;
> > -   struct vfio_iommu_driver *driver;
> > -   int ret;
> > -
> > -   lockdep_assert_held_read(&group->group_rwsem);
> > -
> > -   container = group->container;
> > -   driver = container->iommu_driver;
> > -   if (likely(driver && driver->ops->register_notifier))
> > -   ret = driver->ops->register_notifier(container->iommu_data,
> > -events, nb);
> > -   else
> > -   ret = -ENOTTY;
> > -
> > -   return ret;
> > -}
> > -
> > -static int vfio_unregister_iommu_notifier(struct vfio_group *group,
> > - struct notifier_block *nb)
> > -{
> > -   struct vfio

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add global forcewake request to drpc

[Patchwork]

== Series Details ==

Series: drm/i915: Add global forcewake request to drpc
URL   : https://patchwork.freedesktop.org/series/105319/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11776 -> Patchwork_105319v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105319v1/index.html

Participating hosts (35 -> 34)
--

  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105319v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [PASS][1] -> [INCOMPLETE][2] ([i915#4785])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105319v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105319v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [PASS][5] -> [INCOMPLETE][6] ([i915#5982])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105319v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105319v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- fi-tgl-u2:  [PASS][8] -> [DMESG-WARN][9] ([i915#402])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105319v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  * igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][10] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105319v1/fi-pnv-d510/igt@run...@aborted.html
- fi-hsw-g3258:   NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#4312])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105319v1/fi-hsw-g3258/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [DMESG-WARN][12] ([i915#5122]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105319v1/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][14] ([i915#3303] / [i915#4785]) -> 
[PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105319v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982


Build changes
-

  * Linux: CI_DRM_11776 -> Patchwork_105319v1

  CI-20190529: 20190529
  CI_DRM_11776: ac17a5249380aaabe5d1eaebd9b3a2eedc08ccdc @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6536: e3de4d32b7a509635fbff4d5131c05a7767699f7 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_105319v1: ac17a5249380aaabe5d1eaebd9b3a2eedc08ccdc @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

ff7780f521b0 drm/i915: Add global forcewake request to drpc

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105319v1/index.html

Re: [Intel-gfx] [PATCH v2 1/2] vfio: Replace the DMA unmapping notifier with a callback

[Alex Williamson]

On Tue,  7 Jun 2022 20:02:11 -0300
Jason Gunthorpe  wrote:
> diff --git a/drivers/vfio/vfio.c b/drivers/vfio/vfio.c
> index 61e71c1154be67..f005b644ab9e69 100644
> --- a/drivers/vfio/vfio.c
> +++ b/drivers/vfio/vfio.c
> @@ -1077,8 +1077,20 @@ static void vfio_device_unassign_container(struct 
> vfio_device *device)
>   up_write(&device->group->group_rwsem);
>  }
>  
> +static int vfio_iommu_notifier(struct notifier_block *nb, unsigned long 
> action,
> +void *data)
> +{
> + struct vfio_device *vfio_device =
> + container_of(nb, struct vfio_device, iommu_nb);
> + struct vfio_iommu_type1_dma_unmap *unmap = data;
> +
> + vfio_device->ops->dma_unmap(vfio_device, unmap->iova, unmap->size);
> + return NOTIFY_OK;
> +}
> +
>  static struct file *vfio_device_open(struct vfio_device *device)
>  {
> + struct vfio_iommu_driver *iommu_driver;
>   struct file *filep;
>   int ret;
>  
> @@ -1109,6 +1121,18 @@ static struct file *vfio_device_open(struct 
> vfio_device *device)
>   if (ret)
>   goto err_undo_count;
>   }
> +
> + iommu_driver = device->group->container->iommu_driver;
> + if (device->ops->dma_unmap && iommu_driver &&
> + iommu_driver->ops->register_notifier) {
> + unsigned long events = VFIO_IOMMU_NOTIFY_DMA_UNMAP;
> +
> + device->iommu_nb.notifier_call = vfio_iommu_notifier;
> + iommu_driver->ops->register_notifier(
> + device->group->container->iommu_data, &events,
> + &device->iommu_nb);
> + }
> +
>   up_read(&device->group->group_rwsem);
>   }
>   mutex_unlock(&device->dev_set->lock);
> @@ -1143,8 +1167,16 @@ static struct file *vfio_device_open(struct 
> vfio_device *device)
>  err_close_device:
>   mutex_lock(&device->dev_set->lock);
>   down_read(&device->group->group_rwsem);
> - if (device->open_count == 1 && device->ops->close_device)
> + if (device->open_count == 1 && device->ops->close_device) {
>   device->ops->close_device(device);
> +
> + iommu_driver = device->group->container->iommu_driver;
> + if (device->ops->dma_unmap && iommu_driver &&
> + iommu_driver->ops->register_notifier)

Test for register_notifier callback...

> + iommu_driver->ops->unregister_notifier(
> + device->group->container->iommu_data,
> + &device->iommu_nb);

use unregister_notifier callback.  Same below.

> + }
>  err_undo_count:
>   device->open_count--;
>   if (device->open_count == 0 && device->kvm)
> @@ -1339,12 +1371,20 @@ static const struct file_operations vfio_group_fops = 
> {
>  static int vfio_device_fops_release(struct inode *inode, struct file *filep)
>  {
>   struct vfio_device *device = filep->private_data;
> + struct vfio_iommu_driver *iommu_driver;
>  
>   mutex_lock(&device->dev_set->lock);
>   vfio_assert_device_open(device);
>   down_read(&device->group->group_rwsem);
>   if (device->open_count == 1 && device->ops->close_device)
>   device->ops->close_device(device);
> +
> + iommu_driver = device->group->container->iommu_driver;
> + if (device->ops->dma_unmap && iommu_driver &&
> + iommu_driver->ops->register_notifier)
> + iommu_driver->ops->unregister_notifier(
> + device->group->container->iommu_data,
> + &device->iommu_nb);
>   up_read(&device->group->group_rwsem);
>   device->open_count--;
>   if (device->open_count == 0)
> @@ -2027,90 +2067,6 @@ int vfio_dma_rw(struct vfio_device *device, dma_addr_t 
> user_iova, void *data,
>  }
>  EXPORT_SYMBOL(vfio_dma_rw);
>  
> -static int vfio_register_iommu_notifier(struct vfio_group *group,
> - unsigned long *events,
> - struct notifier_block *nb)
> -{
> - struct vfio_container *container;
> - struct vfio_iommu_driver *driver;
> - int ret;
> -
> - lockdep_assert_held_read(&group->group_rwsem);
> -
> - container = group->container;
> - driver = container->iommu_driver;
> - if (likely(driver && driver->ops->register_notifier))
> - ret = driver->ops->register_notifier(container->iommu_data,
> -  events, nb);
> - else
> - ret = -ENOTTY;
> -
> - return ret;
> -}
> -
> -static int vfio_unregister_iommu_notifier(struct vfio_group *group,
> -   struct notifier_block *nb)
> -{
> - struct vfio_container *container;
> - struct vfio_iommu_driver *driver;
> - int ret;
> -
> - lockdep_assert_held_read(&group->group_rwsem);
> -
> - container = group->contain

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add global forcewake status to drpc

[Patchwork]

== Series Details ==

Series: drm/i915: Add global forcewake status to drpc
URL   : https://patchwork.freedesktop.org/series/105316/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11776 -> Patchwork_105316v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105316v1/index.html

Participating hosts (35 -> 34)
--

  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105316v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][1] -> [DMESG-FAIL][2] ([i915#4528])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105316v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [PASS][3] -> [INCOMPLETE][4] ([i915#5982])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105316v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105316v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][6] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105316v1/fi-pnv-d510/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [DMESG-WARN][7] ([i915#5122]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105316v1/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][9] ([i915#3303] / [i915#4785]) -> 
[PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105316v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982


Build changes
-

  * Linux: CI_DRM_11776 -> Patchwork_105316v1

  CI-20190529: 20190529
  CI_DRM_11776: ac17a5249380aaabe5d1eaebd9b3a2eedc08ccdc @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6536: e3de4d32b7a509635fbff4d5131c05a7767699f7 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_105316v1: ac17a5249380aaabe5d1eaebd9b3a2eedc08ccdc @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

8826ab02ff1c drm/i915: Add global forcewake status to drpc

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105316v1/index.html

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/display: split out hw state readout and sanitize

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/display: split out hw state readout 
and sanitize
URL   : https://patchwork.freedesktop.org/series/105281/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11775_full -> Patchwork_105281v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 10)
--

  Missing(3): shard-rkl shard-dg1 shard-tglu 

Known issues


  Here are the changes found in Patchwork_105281v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl:  [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +7 similar 
issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl4/igt@gem_ctx_isolation@preservation...@bcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl6/igt@gem_ctx_isolation@preservation...@bcs0.html

  * igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb1/igt@gem_exec_balan...@parallel-out-fence.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb8/igt@gem_exec_balan...@parallel-out-fence.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  NOTRUN -> [FAIL][5] ([i915#2842]) +1 similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-tglb5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl6/igt@gem_exec_fair@basic-p...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2849])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_lmem_swapping@heavy-verify-random:
- shard-kbl:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl4/igt@gem_lmem_swapp...@heavy-verify-random.html
- shard-skl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl10/igt@gem_lmem_swapp...@heavy-verify-random.html

  * igt@gem_lmem_swapping@random:
- shard-apl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-apl6/igt@gem_lmem_swapp...@random.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-skl:  NOTRUN -> [WARN][17] ([i915#2658])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl10/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_userptr_blits@vma-merge:
- shard-kbl:  NOTRUN -> [FAIL][18] ([i915#3318])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl4/igt@gem_userptr_bl...@vma-merge.html

  * igt@i915_module_load@load:
- shard-skl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#6227])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl10/igt@i915_module_l...@load.html

  * igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][20] -> [FAIL][21] ([i915#454]) +1 similar issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb7/igt@i915_pm...@dc6-dpms.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb3/igt@i915_pm...@dc6-dpms.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl:  [PASS][22] -> [INCOMPLETE][23] ([i915#4939])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl1/igt@i915_pm_...@system-suspend-execbuf.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281

Re: [Intel-gfx] [Intel-gfx 1/1] drm/i915/guc: Don't update engine busyness stats too frequently

[Teres Alexis, Alan Previn]

> > > Not updating the driver state in park will not negatively impact 
> > > accuracy in some scenarios? That needs to balanced against the 
> > > questions whether or not there are real world scenarios impacted by 
> > > the update cost or it is just for IGT.
> > 
If i understand it correctly (how its calculated), no. not capturing on every 
park/unpark
does not mean less accuracy. Umesh mentioned to verify that with 
igt@perf-pmu@accuracy
tests

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Skip wm/ddb readout for disabled pipes

[Patchwork]

== Series Details ==

Series: drm/i915: Skip wm/ddb readout for disabled pipes
URL   : https://patchwork.freedesktop.org/series/105314/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11776 -> Patchwork_105314v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/index.html

Participating hosts (35 -> 35)
--

  Additional (1): fi-icl-u2 
  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105314v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][1] ([i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_selftest@live@gem:
- fi-blb-e6850:   NOTRUN -> [DMESG-FAIL][3] ([i915#4528])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-blb-e6850/igt@i915_selftest@l...@gem.html
- fi-pnv-d510:[PASS][4] -> [DMESG-FAIL][5] ([i915#4528])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-pnv-d510/igt@i915_selftest@l...@gem.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-pnv-d510/igt@i915_selftest@l...@gem.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [PASS][6] -> [INCOMPLETE][7] ([i915#5982])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
- fi-icl-u2:  NOTRUN -> [SKIP][8] ([i915#5903])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-icl-u2/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([fdo#109278] / [i915#4103]) +1 
similar issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- fi-tgl-u2:  [PASS][11] -> [DMESG-WARN][12] ([i915#402]) +1 
similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  * igt@kms_force_connector_basic@force-connector-state:
- fi-icl-u2:  NOTRUN -> [WARN][13] ([i915#6008])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-icl-u2/igt@kms_force_connector_ba...@force-connector-state.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][14] ([fdo#109285])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([fdo#109278])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-icl-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][16] ([i915#3555])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][17] ([fdo#109295] / [i915#3301])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-icl-u2/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][18] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-pnv-d510/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [DMESG-FAIL][19] ([i915#4528]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105314v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=1092

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Re-do the intel-gtt split

[Lucas De Marchi]

On Fri, Jun 17, 2022 at 12:15:51PM -0700, Matt Roper wrote:

On Thu, Jun 16, 2022 at 03:49:43PM -0700, Lucas De Marchi wrote:

Re-do what was attempted in commit 7a5c922377b4 ("drm/i915/gt: Split
intel-gtt functions by arch"). The goal of that commit was to split the
handlers for older hardware that depend on intel-gtt.ko so i915 can
be built for non-x86 archs, after some more patches. Other archs do not
need intel-gtt.ko.

Main issue with the previous approach: it moved all the hooks, including
the gen8, which is used by all platforms gen8 and newer.  Re-do the
split moving only the handlers for gen < 6, which are the only ones
calling out to the separate module.

Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/Makefile |   2 +-
 drivers/gpu/drm/i915/gt/intel_ggtt.c  | 559 +-
 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c | 132 +
 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h |  27 +
 drivers/gpu/drm/i915/gt/intel_gt.c|   5 +-
 drivers/gpu/drm/i915/gt/intel_gt.h|   9 -
 drivers/gpu/drm/i915/gt/intel_gt_gmch.c   | 654 --
 drivers/gpu/drm/i915/gt/intel_gt_gmch.h   |  46 --
 drivers/gpu/drm/i915/gt/intel_gtt.h   |  12 +-
 9 files changed, 713 insertions(+), 733 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h
 delete mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.c
 delete mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d2b18f03a33c..4166cd76997e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -129,7 +129,7 @@ gt-y += \
gt/shmem_utils.o \
gt/sysfs_engines.o
 # x86 intel-gtt module support
-gt-$(CONFIG_X86) += gt/intel_gt_gmch.o
+gt-$(CONFIG_X86) += gt/intel_ggtt_gmch.o
 # autogenerated null render state
 gt-y += \
gt/gen6_renderstate.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index e6b2eb122ad7..a83d6858b766 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -3,16 +3,18 @@
  * Copyright © 2020 Intel Corporation
  */

-#include 
 #include 
 #include 
+#include 
+#include 

 #include 
+#include 

 #include "gem/i915_gem_lmem.h"

+#include "intel_ggtt_gmch.h"
 #include "intel_gt.h"
-#include "intel_gt_gmch.h"
 #include "intel_gt_regs.h"
 #include "i915_drv.h"
 #include "i915_scatterlist.h"
@@ -181,7 +183,7 @@ void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
spin_unlock_irq(&uncore->lock);
 }

-void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
+static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
struct intel_uncore *uncore = ggtt->vm.gt->uncore;

@@ -218,11 +220,232 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
return pte;
 }

+static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
+{
+   writeq(pte, addr);
+}
+
+static void gen8_ggtt_insert_page(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ enum i915_cache_level level,
+ u32 flags)
+{
+   struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+   gen8_pte_t __iomem *pte =
+   (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
+
+   gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
+
+   ggtt->invalidate(ggtt);
+}
+
+static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
+struct i915_vma_resource *vma_res,
+enum i915_cache_level level,
+u32 flags)
+{
+   const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
+   struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+   gen8_pte_t __iomem *gte;
+   gen8_pte_t __iomem *end;
+   struct sgt_iter iter;
+   dma_addr_t addr;
+
+   /*
+* Note that we ignore PTE_READ_ONLY here. The caller must be careful
+* not to allow the user to override access to a read only page.
+*/
+
+   gte = (gen8_pte_t __iomem *)ggtt->gsm;
+   gte += vma_res->start / I915_GTT_PAGE_SIZE;
+   end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
+
+   for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
+   gen8_set_pte(gte++, pte_encode | addr);
+   GEM_BUG_ON(gte > end);
+
+   /* Fill the allocated but "unused" space beyond the end of the buffer */
+   while (gte < end)
+   gen8_set_pte(gte++, vm->scratch[0]->encode);
+
+   /*
+* We want to flush the TLBs only after we're certain all the PTE
+* updates have finished.
+*/
+   ggtt->invalidate(ggtt);
+}
+
+static void gen6_ggtt_insert_page(struct i915_address_space *vm,
+ dma_addr_

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[Lucas De Marchi]

On Fri, Jun 17, 2022 at 03:32:52PM -0500, Bjorn Helgaas wrote:

[+cc Christian, author of pci_resize_resource(), Sergei, author of
rebalancing patches]

Hi Lucas,

On Fri, Jun 17, 2022 at 11:44:41AM -0700, Lucas De Marchi wrote:

Cc'ing intel-pci, lkml, Bjorn

On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
> On Thu, 16 Jun 2022, priyanka.dandam...@intel.com wrote:
> > From: Akeem G Abodunrin 
> >
> > Add support for the local memory PICe resizable bar, so that
> > local memory can be resized to the maximum size supported by the device,
> > and mapped correctly to the PCIe memory bar. It is usual that GPU
> > devices expose only 256MB BARs primarily to be compatible with 32-bit
> > systems. So, those devices cannot claim larger memory BAR windows size due
> > to the system BIOS limitation. With this change, it would be possible to
> > reprogram the windows of the bridge directly above the requesting device
> > on the same BAR type.

There is a big caveat here that this may be too late as other drivers
may have already mapped their BARs - so probably too late in the pci scan
for it to be effective. In fact, after using this for a while, it seems
to fail too often, particularly on CFL systems.


Help me understand the "too late" part.  Do you mean that there is
enough available space for the max BAR size, but it's fragmented and
therefore not usable?  And that if we could do something earlier,
before drivers have claimed their devices, we might be able to compact
the BARs of other devices to make a larger contiguous available space?


yes. I will dig some logs I had in the past to confirm.



That is theoretically possible, but I think the current
pci_resize_resource() only supports resizing of the specified BAR and
any upstream bridge windows.  I don't think it supports moving BARs of
other devices.

Sergei did some nice work that might help with this situation because
it can move BARs around more generally.  It hasn't quite achieved
critical mass yet, but maybe this would help get there:

 
https://lore.kernel.org/linux-pci/20201218174011.340514-1-s.miroshniche...@yadro.com/


oh... I hadn't thought about pause/ioremap/unpause. That looks rad :).
So it seems this would integrate neatly with
pci_resize_resource() (what this patch is doing), as long as drivers for
devices affected implement
.bar_fixed()/.rescan_prepare()/.rescan_done(). That seems it would solve
our issues too.

thanks
Lucas De Marchi



If I understand Sergei's series correctly, this rebalancing actually
cannot be done during enumeration because we only move BARs if a
driver for the device indicates that it supports it, so there would be
no requirement to do this early.


Do we have any alternative to be done in the PCI subsystem during the
scan?  There is other work in progress to allow i915 to use the rest of
the device memory even with a smaller BAR, but it would be better if we
can improve our chances of succeeding the resize.



> > Signed-off-by: Akeem G Abodunrin 
> > Signed-off-by: Michał Winiarski 
> > Cc: Stuart Summers 
> > Cc: Michael J Ruhl 
> > Cc: Prathap Kumar Valsan 
> > Signed-off-by: Priyanka Dandamudi 
> > Reviewed-by: Matthew Auld 
>
> Please see https://lore.kernel.org/r/87pmj8vesm@intel.com
>
> > ---
> >  drivers/gpu/drm/i915/i915_driver.c | 92 ++
> >  1 file changed, 92 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
> > index d26dcca7e654..4bdb471cb2e2 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
> >   __intel_gt_reset(to_gt(i915), ALL_ENGINES);
> >  }
> >
> > +static void __release_bars(struct pci_dev *pdev)
> > +{
> > + int resno;
> > +
> > + for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; 
resno++) {
> > + if (pci_resource_len(pdev, resno))
> > + pci_release_resource(pdev, resno);
> > + }
> > +}
> > +
> > +static void
> > +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t 
size)
> > +{
> > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > + int bar_size = pci_rebar_bytes_to_size(size);
> > + int ret;
> > +
> > + __release_bars(pdev);
> > +
> > + ret = pci_resize_resource(pdev, resno, bar_size);
> > + if (ret) {
> > + drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
> > +  resno, 1 << bar_size, ERR_PTR(ret));
> > + return;
> > + }
> > +
> > + drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
> > +}
> > +
> > +/* BAR size starts from 1MB - 2^20 */
> > +#define BAR_SIZE_SHIFT 20
> > +static resource_size_t
> > +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
> > +{
> > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > + u32 rebar = pci_rebar_get_possible

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] iosys-map: Add per-word read

[Patchwork]

== Series Details ==

Series: series starting with [1/2] iosys-map: Add per-word read
URL   : https://patchwork.freedesktop.org/series/105273/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11775_full -> Patchwork_105273v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_105273v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_105273v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 10)
--

  Missing(3): shard-rkl shard-dg1 shard-tglu 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105273v1_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-edp-1:
- shard-skl:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl3/igt@kms_async_flips@async-flip-with-page-flip-eve...@pipe-b-edp-1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/shard-skl9/igt@kms_async_flips@async-flip-with-page-flip-eve...@pipe-b-edp-1.html

  
Known issues


  Here are the changes found in Patchwork_105273v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-skl:  [PASS][3] -> [INCOMPLETE][4] ([i915#4793])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl10/igt@gem_ctx_isolation@preservation...@vcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/shard-skl1/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@gem_eio@in-flight-suspend:
- shard-apl:  [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +1 similar 
issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl8/igt@gem_...@in-flight-suspend.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/shard-apl6/igt@gem_...@in-flight-suspend.html

  * igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#4525])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb2/igt@gem_exec_balan...@parallel-bb-first.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/shard-iclb6/igt@gem_exec_balan...@parallel-bb-first.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/shard-apl6/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl:  [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl6/igt@gem_exec_fair@basic-p...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/shard-kbl3/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2849])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_huc_copy@huc-copy:
- shard-apl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/shard-apl3/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@heavy-verify-random:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/shard-kbl4/igt@gem_lmem_swapp...@heavy-verify-random.html
- shard-skl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/shard-skl7/igt@gem_lmem_swapp...@heavy-verify-random.html

  * igt@gem_lmem_swapping@verify:
- shard-apl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/shard-apl3/igt@gem_lmem_swapp...@verify.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-skl:  NOTRUN -> [WARN][19] ([i915#2658])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/shard-skl7/igt@gem_pwr...@basic-exhaustion.html

  * igt@gen9_exec_parse@allowed-all:
- shard-glk:  [PASS][20] -> [DMESG-WARN][21] ([i915#5566] / 
[i915#716])
   [20]: 
https://intel-gfx-ci.01.

[Intel-gfx] [PATCH] drm/i915: Add global forcewake request to drpc

[Vinay Belgaumkar]

We have seen multiple RC6 issues where it is useful to know
which global forcewake bits are set. Add this to the 'drpc'
debugfs output.

v2: Review comments (Ashutosh)

Reviewed-by: Ashutosh Dixit 
Signed-off-by: Vinay Belgaumkar 
---
 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c 
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 90a440865037..40bdd4cb629f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -100,14 +100,16 @@ static int vlv_drpc(struct seq_file *m)
 {
struct intel_gt *gt = m->private;
struct intel_uncore *uncore = gt->uncore;
-   u32 rcctl1, pw_status;
+   u32 rcctl1, pw_status, mt_fwake_req;
 
+   mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS);
rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
 
seq_printf(m, "RC6 Enabled: %s\n",
   str_yes_no(rcctl1 & (GEN7_RC_CTL_TO_MODE |
GEN6_RC_CTL_EI_MODE(1;
+   seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req);
seq_printf(m, "Render Power Well: %s\n",
   (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : 
"Down");
seq_printf(m, "Media Power Well: %s\n",
@@ -124,9 +126,10 @@ static int gen6_drpc(struct seq_file *m)
struct intel_gt *gt = m->private;
struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore = gt->uncore;
-   u32 gt_core_status, rcctl1, rc6vids = 0;
+   u32 gt_core_status, mt_fwake_req, rcctl1, rc6vids = 0;
u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
 
+   mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
 
rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
@@ -178,6 +181,7 @@ static int gen6_drpc(struct seq_file *m)
 
seq_printf(m, "Core Power Down: %s\n",
   str_yes_no(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
+   seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req);
if (GRAPHICS_VER(i915) >= 9) {
seq_printf(m, "Render Power Well: %s\n",
   (gen9_powergate_status &
-- 
2.35.1

Re: [Intel-gfx] [PATCH] drm/i915: Add global forcewake status to drpc

[Belgaumkar, Vinay]

On 6/17/2022 1:53 PM, Dixit, Ashutosh wrote:

On Fri, 17 Jun 2022 13:25:34 -0700, Vinay Belgaumkar wrote:

We have seen multiple RC6 issues where it is useful to know
which global forcewake bits are set. Add this to the 'drpc'
debugfs output.

A couple of optional nits below to look at but otherwise this is:

Reviewed-by: Ashutosh Dixit 


+static u32 mt_fwake_status(struct intel_uncore *uncore)
+{
+   return intel_uncore_read_fw(uncore, FORCEWAKE_MT);
+}
+
  static int vlv_drpc(struct seq_file *m)
  {
struct intel_gt *gt = m->private;
struct intel_uncore *uncore = gt->uncore;
-   u32 rcctl1, pw_status;
+   u32 rcctl1, pw_status, mt_fwake;

+   mt_fwake = mt_fwake_status(uncore);

I would get rid of the function and just duplicate the intel_uncore_read_fw().
Made it a function in case we can find the equivalent register for ILK. 
Though, I am not sure if ILK even had the concept of MT fwake.



pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS);
rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);

seq_printf(m, "RC6 Enabled: %s\n",
   str_yes_no(rcctl1 & (GEN7_RC_CTL_TO_MODE |
GEN6_RC_CTL_EI_MODE(1;
+   seq_printf(m, "Multi-threaded Forcewake: 0x%x\n", mt_fwake);

Is "Multi-threaded Forcewake Request" (the Bspec register name) a more
descriptive print?

Same for gen6_drpc() below. Thanks!


Sure.

Thanks,

Vinay.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Call i915_gem_suspend() only after display is turned off

[Patchwork]

== Series Details ==

Series: drm/i915: Call i915_gem_suspend() only after display is turned off
URL   : https://patchwork.freedesktop.org/series/105306/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11776 -> Patchwork_105306v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/index.html

Participating hosts (35 -> 35)
--

  Additional (1): fi-cml-u2 
  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105306v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][1] ([i915#1208]) +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-cml-u2:  NOTRUN -> [SKIP][2] ([i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-cml-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-cml-u2:  NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-cml-u2/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [PASS][4] -> [INCOMPLETE][5] ([i915#3303] / 
[i915#4785])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][6] -> [DMESG-FAIL][7] ([i915#4528])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [PASS][8] -> [INCOMPLETE][9] ([i915#5982])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@vga-hpd-fast:
- fi-cml-u2:  NOTRUN -> [SKIP][10] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-cml-u2/igt@kms_chamel...@vga-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-cml-u2:  NOTRUN -> [SKIP][11] ([fdo#109278]) +1 similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-cml-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- fi-tgl-u2:  [PASS][12] -> [DMESG-WARN][13] ([i915#402])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2:  NOTRUN -> [SKIP][14] ([fdo#109285])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-cml-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2:  NOTRUN -> [DMESG-WARN][15] ([i915#4269])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2:  NOTRUN -> [SKIP][16] ([fdo#109278] / [i915#533])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-cml-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-cml-u2:  NOTRUN -> [SKIP][17] ([i915#3555])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-cml-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-cml-u2:  NOTRUN -> [SKIP][18] ([fdo#109295] / [i915#3301])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-cml-u2/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][19] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-pnv-d510/igt@run...@aborted.html
- fi-hsw-g3258:   NOTRUN -> [FAIL][20] ([fdo#109271] / [i915#4312])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105306v1/fi-hsw-g3258/igt@run...@aborted.html

  
 Possible fixes 

Re: [Intel-gfx] [PATCH] drm/i915: Add global forcewake status to drpc

[Dixit, Ashutosh]

On Fri, 17 Jun 2022 13:25:34 -0700, Vinay Belgaumkar wrote:
>
> We have seen multiple RC6 issues where it is useful to know
> which global forcewake bits are set. Add this to the 'drpc'
> debugfs output.

A couple of optional nits below to look at but otherwise this is:

Reviewed-by: Ashutosh Dixit 

> +static u32 mt_fwake_status(struct intel_uncore *uncore)
> +{
> + return intel_uncore_read_fw(uncore, FORCEWAKE_MT);
> +}
> +
>  static int vlv_drpc(struct seq_file *m)
>  {
>   struct intel_gt *gt = m->private;
>   struct intel_uncore *uncore = gt->uncore;
> - u32 rcctl1, pw_status;
> + u32 rcctl1, pw_status, mt_fwake;
>
> + mt_fwake = mt_fwake_status(uncore);

I would get rid of the function and just duplicate the intel_uncore_read_fw().

>   pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS);
>   rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
>
>   seq_printf(m, "RC6 Enabled: %s\n",
>  str_yes_no(rcctl1 & (GEN7_RC_CTL_TO_MODE |
>   GEN6_RC_CTL_EI_MODE(1;
> + seq_printf(m, "Multi-threaded Forcewake: 0x%x\n", mt_fwake);

Is "Multi-threaded Forcewake Request" (the Bspec register name) a more
descriptive print?

Same for gen6_drpc() below. Thanks!

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: ttm for stolen (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: ttm for stolen (rev2)
URL   : https://patchwork.freedesktop.org/series/101396/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11776 -> Patchwork_101396v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v2/index.html

Participating hosts (35 -> 34)
--

  Additional (1): fi-icl-u2 
  Missing(2): fi-bdw-samus fi-tgl-u2 

Known issues


  Here are the changes found in Patchwork_101396v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][1] ([i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v2/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v2/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [PASS][3] -> [INCOMPLETE][4] ([i915#5982])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v2/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
- fi-icl-u2:  NOTRUN -> [SKIP][5] ([i915#5903])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v2/fi-icl-u2/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v2/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][7] ([fdo#111827]) +8 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v2/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2:  NOTRUN -> [SKIP][8] ([fdo#109278] / [i915#4103]) +1 
similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v2/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-connector-state:
- fi-icl-u2:  NOTRUN -> [WARN][9] ([i915#6008])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v2/fi-icl-u2/igt@kms_force_connector_ba...@force-connector-state.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([fdo#109285])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v2/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-icl-u2:  NOTRUN -> [SKIP][11] ([fdo#109278])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v2/fi-icl-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][12] ([i915#3555])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v2/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][13] ([fdo#109295] / [i915#3301])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v2/fi-icl-u2/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][14] ([i915#3303] / [i915#4785]) -> 
[PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v2/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
  [i915#5982]: https://gitlab.

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[Bjorn Helgaas]

[+cc Christian, author of pci_resize_resource(), Sergei, author of
rebalancing patches]

Hi Lucas,

On Fri, Jun 17, 2022 at 11:44:41AM -0700, Lucas De Marchi wrote:
> Cc'ing intel-pci, lkml, Bjorn
> 
> On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
> > On Thu, 16 Jun 2022, priyanka.dandam...@intel.com wrote:
> > > From: Akeem G Abodunrin 
> > > 
> > > Add support for the local memory PICe resizable bar, so that
> > > local memory can be resized to the maximum size supported by the device,
> > > and mapped correctly to the PCIe memory bar. It is usual that GPU
> > > devices expose only 256MB BARs primarily to be compatible with 32-bit
> > > systems. So, those devices cannot claim larger memory BAR windows size due
> > > to the system BIOS limitation. With this change, it would be possible to
> > > reprogram the windows of the bridge directly above the requesting device
> > > on the same BAR type.
> 
> There is a big caveat here that this may be too late as other drivers
> may have already mapped their BARs - so probably too late in the pci scan
> for it to be effective. In fact, after using this for a while, it seems
> to fail too often, particularly on CFL systems.

Help me understand the "too late" part.  Do you mean that there is
enough available space for the max BAR size, but it's fragmented and
therefore not usable?  And that if we could do something earlier,
before drivers have claimed their devices, we might be able to compact
the BARs of other devices to make a larger contiguous available space?

That is theoretically possible, but I think the current
pci_resize_resource() only supports resizing of the specified BAR and
any upstream bridge windows.  I don't think it supports moving BARs of
other devices.

Sergei did some nice work that might help with this situation because
it can move BARs around more generally.  It hasn't quite achieved
critical mass yet, but maybe this would help get there:

  
https://lore.kernel.org/linux-pci/20201218174011.340514-1-s.miroshniche...@yadro.com/

If I understand Sergei's series correctly, this rebalancing actually
cannot be done during enumeration because we only move BARs if a
driver for the device indicates that it supports it, so there would be
no requirement to do this early.

> Do we have any alternative to be done in the PCI subsystem during the
> scan?  There is other work in progress to allow i915 to use the rest of
> the device memory even with a smaller BAR, but it would be better if we
> can improve our chances of succeeding the resize.

> > > Signed-off-by: Akeem G Abodunrin 
> > > Signed-off-by: Michał Winiarski 
> > > Cc: Stuart Summers 
> > > Cc: Michael J Ruhl 
> > > Cc: Prathap Kumar Valsan 
> > > Signed-off-by: Priyanka Dandamudi 
> > > Reviewed-by: Matthew Auld 
> > 
> > Please see https://lore.kernel.org/r/87pmj8vesm@intel.com
> > 
> > > ---
> > >  drivers/gpu/drm/i915/i915_driver.c | 92 ++
> > >  1 file changed, 92 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_driver.c 
> > > b/drivers/gpu/drm/i915/i915_driver.c
> > > index d26dcca7e654..4bdb471cb2e2 100644
> > > --- a/drivers/gpu/drm/i915/i915_driver.c
> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > > @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private 
> > > *i915)
> > >   __intel_gt_reset(to_gt(i915), ALL_ENGINES);
> > >  }
> > > 
> > > +static void __release_bars(struct pci_dev *pdev)
> > > +{
> > > + int resno;
> > > +
> > > + for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
> > > + if (pci_resource_len(pdev, resno))
> > > + pci_release_resource(pdev, resno);
> > > + }
> > > +}
> > > +
> > > +static void
> > > +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t 
> > > size)
> > > +{
> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > > + int bar_size = pci_rebar_bytes_to_size(size);
> > > + int ret;
> > > +
> > > + __release_bars(pdev);
> > > +
> > > + ret = pci_resize_resource(pdev, resno, bar_size);
> > > + if (ret) {
> > > + drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
> > > +  resno, 1 << bar_size, ERR_PTR(ret));
> > > + return;
> > > + }
> > > +
> > > + drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
> > > +}
> > > +
> > > +/* BAR size starts from 1MB - 2^20 */
> > > +#define BAR_SIZE_SHIFT 20
> > > +static resource_size_t
> > > +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
> > > +{
> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > > + u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
> > > + resource_size_t size;
> > > +
> > > + if (!rebar)
> > > + return 0;
> > > +
> > > + size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
> > > +
> > > + if (size <= pci_resource_len(pdev, resno))
> > > + return 0;
> > > +
> > > + return size;
> > > +}
> > > +
> > > +#define LMEM_BAR_NUM 2
> > > +static void i915

[Intel-gfx] [PATCH] drm/i915: Add global forcewake status to drpc

[Vinay Belgaumkar]

We have seen multiple RC6 issues where it is useful to know
which global forcewake bits are set. Add this to the 'drpc'
debugfs output.

Signed-off-by: Vinay Belgaumkar 
---
 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c 
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 90a440865037..2a157ca28dda 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -96,18 +96,25 @@ static void print_rc6_res(struct seq_file *m,
   intel_rc6_residency_us(>->rc6, reg));
 }
 
+static u32 mt_fwake_status(struct intel_uncore *uncore)
+{
+   return intel_uncore_read_fw(uncore, FORCEWAKE_MT);
+}
+
 static int vlv_drpc(struct seq_file *m)
 {
struct intel_gt *gt = m->private;
struct intel_uncore *uncore = gt->uncore;
-   u32 rcctl1, pw_status;
+   u32 rcctl1, pw_status, mt_fwake;
 
+   mt_fwake = mt_fwake_status(uncore);
pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS);
rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
 
seq_printf(m, "RC6 Enabled: %s\n",
   str_yes_no(rcctl1 & (GEN7_RC_CTL_TO_MODE |
GEN6_RC_CTL_EI_MODE(1;
+   seq_printf(m, "Multi-threaded Forcewake: 0x%x\n", mt_fwake);
seq_printf(m, "Render Power Well: %s\n",
   (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : 
"Down");
seq_printf(m, "Media Power Well: %s\n",
@@ -124,9 +131,10 @@ static int gen6_drpc(struct seq_file *m)
struct intel_gt *gt = m->private;
struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore = gt->uncore;
-   u32 gt_core_status, rcctl1, rc6vids = 0;
+   u32 gt_core_status, mt_fwake, rcctl1, rc6vids = 0;
u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
 
+   mt_fwake = mt_fwake_status(uncore);
gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
 
rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
@@ -178,6 +186,7 @@ static int gen6_drpc(struct seq_file *m)
 
seq_printf(m, "Core Power Down: %s\n",
   str_yes_no(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
+   seq_printf(m, "Multi-threaded Forcewake: 0x%x\n", mt_fwake);
if (GRAPHICS_VER(i915) >= 9) {
seq_printf(m, "Render Power Well: %s\n",
   (gen9_powergate_status &
-- 
2.35.1

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: ttm for stolen (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: ttm for stolen (rev2)
URL   : https://patchwork.freedesktop.org/series/101396/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Make fastset not suck and allow seamless M/N changes (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev5)
URL   : https://patchwork.freedesktop.org/series/103491/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11776 -> Patchwork_103491v5


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_103491v5 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_103491v5, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v5/index.html

Participating hosts (35 -> 34)
--

  Missing(1): fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103491v5:

### IGT changes ###

 Possible regressions 

  * igt@i915_module_load@load:
- fi-bxt-dsi: [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-bxt-dsi/igt@i915_module_l...@load.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v5/fi-bxt-dsi/igt@i915_module_l...@load.html
- fi-glk-dsi: [PASS][3] -> [DMESG-WARN][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-glk-dsi/igt@i915_module_l...@load.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v5/fi-glk-dsi/igt@i915_module_l...@load.html

  
Known issues


  Here are the changes found in Patchwork_103491v5 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-snb-2600:[PASS][5] -> [FAIL][6] ([i915#4338])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-snb-2600/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v5/fi-snb-2600/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@gem:
- fi-blb-e6850:   NOTRUN -> [DMESG-FAIL][7] ([i915#4528])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v5/fi-blb-e6850/igt@i915_selftest@l...@gem.html
- fi-pnv-d510:[PASS][8] -> [DMESG-FAIL][9] ([i915#4528])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-pnv-d510/igt@i915_selftest@l...@gem.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v5/fi-pnv-d510/igt@i915_selftest@l...@gem.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [PASS][10] -> [INCOMPLETE][11] ([i915#5982])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v5/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v5/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_flip@basic-plain-flip@a-edp1:
- fi-tgl-u2:  [PASS][13] -> [DMESG-WARN][14] ([i915#402])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-tgl-u2/igt@kms_flip@basic-plain-f...@a-edp1.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v5/fi-tgl-u2/igt@kms_flip@basic-plain-f...@a-edp1.html

  * igt@runner@aborted:
- fi-bxt-dsi: NOTRUN -> [FAIL][15] ([i915#4312] / [i915#5257])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v5/fi-bxt-dsi/igt@run...@aborted.html
- fi-glk-dsi: NOTRUN -> [FAIL][16] ([i915#4312] / [i915#5257])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v5/fi-glk-dsi/igt@run...@aborted.html
- fi-pnv-d510:NOTRUN -> [FAIL][17] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v5/fi-pnv-d510/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [DMESG-WARN][18] ([i915#5122]) -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v5/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][20] ([i915#3303] / [i915#4785]) -> 
[PASS][21]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v5/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [DMESG-FAIL][22] ([i915#4528]) -> [PASS][23]
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-

[Intel-gfx] [PATCH] drm/i915: Skip wm/ddb readout for disabled pipes

[Ville Syrjala]

From: Ville Syrjälä 

The stuff programmed into the wm/ddb registers of planes
on disabled pipes doesn't matter. So during readout just
leave our software state tracking for those zeroed.

This should avoid us trying too hard to clean up after
whatever mess the VBIOS/GOP left in there. The actual
hardware state will get cleaned up if/when we enable
the pipe anyway.

References: https://gitlab.freedesktop.org/drm/intel/-/issues/5711
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 174fab564d10..d083964d5470 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6560,7 +6560,10 @@ void skl_wm_get_hw_state(struct drm_i915_private 
*dev_priv)
enum plane_id plane_id;
u8 slices;
 
-   skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
+   memset(&crtc_state->wm.skl.optimal, 0,
+  sizeof(crtc_state->wm.skl.optimal));
+   if (crtc_state->hw.active)
+   skl_pipe_wm_get_hw_state(crtc, 
&crtc_state->wm.skl.optimal);
crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;
 
memset(&dbuf_state->ddb[pipe], 0, 
sizeof(dbuf_state->ddb[pipe]));
@@ -6571,6 +6574,9 @@ void skl_wm_get_hw_state(struct drm_i915_private 
*dev_priv)
struct skl_ddb_entry *ddb_y =
&crtc_state->wm.skl.plane_ddb_y[plane_id];
 
+   if (!crtc_state->hw.active)
+   continue;
+
skl_ddb_get_hw_plane_state(dev_priv, crtc->pipe,
   plane_id, ddb, ddb_y);
 
-- 
2.35.1

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev5)
URL   : https://patchwork.freedesktop.org/series/103491/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Implement a bit of bw_state readout

[Patchwork]

== Series Details ==

Series: drm/i915: Implement a bit of bw_state readout
URL   : https://patchwork.freedesktop.org/series/105299/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11776 -> Patchwork_105299v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/index.html

Participating hosts (35 -> 34)
--

  Additional (1): fi-cml-u2 
  Missing(2): fi-blb-e6850 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105299v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][1] ([i915#1208]) +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-cml-u2:  NOTRUN -> [SKIP][2] ([i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-cml-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-cml-u2:  NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-cml-u2/igt@gem_lmem_swapp...@verify-random.html
- fi-tgl-u2:  NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-tgl-u2/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [PASS][5] -> [INCOMPLETE][6] ([i915#4785])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][7] -> [DMESG-FAIL][8] ([i915#4528])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-tgl-u2:  NOTRUN -> [SKIP][9] ([i915#5903])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-tgl-u2/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-u2:  NOTRUN -> [SKIP][10] ([fdo#109284] / [fdo#111827])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-tgl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@vga-hpd-fast:
- fi-cml-u2:  NOTRUN -> [SKIP][12] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-cml-u2/igt@kms_chamel...@vga-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-cml-u2:  NOTRUN -> [SKIP][13] ([fdo#109278]) +1 similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-cml-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2:  NOTRUN -> [SKIP][14] ([fdo#109285])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-cml-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2:  NOTRUN -> [SKIP][15] ([fdo#109278] / [i915#533])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-cml-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-cml-u2:  NOTRUN -> [SKIP][16] ([i915#3555])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-cml-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-cml-u2:  NOTRUN -> [SKIP][17] ([fdo#109295] / [i915#3301])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-cml-u2/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][18] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-pnv-d510/igt@run...@aborted.html
- fi-hsw-g3258:   NOTRUN -> [FAIL][19] ([fdo#109271] / [i915#4312])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105299v1/fi-hsw-g3258/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][20] ([i915#

Re: [Intel-gfx] [PATCH] drm/i915: Call i915_gem_suspend() only after display is turned off

[Matt Roper]

On Fri, Jun 17, 2022 at 12:06:29PM -0700, José Roberto de Souza wrote:
> Gem buffers could still be in use by display after i915_gem_suspend()
> is executed so there is chances that i915_gem_flush_free_objects()
> will be being executed at the same time that
> intel_runtime_pm_driver_release() is executed printing warnings about
> wakerefs will being held.

By the same logic do we need to adjust i915_driver_remove() too?


Matt

> 
> So here only calling i915_gem_suspend() and by consequence
> i915_gem_drain_freed_objects() only after display is down making
> sure all buffers are freed.
> 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/i915_driver.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_driver.c 
> b/drivers/gpu/drm/i915/i915_driver.c
> index d26dcca7e654a..4227675dd1cfe 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -1067,8 +1067,6 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
>   intel_runtime_pm_disable(&i915->runtime_pm);
>   intel_power_domains_disable(i915);
>  
> - i915_gem_suspend(i915);
> -
>   if (HAS_DISPLAY(i915)) {
>   drm_kms_helper_poll_disable(&i915->drm);
>  
> @@ -1085,6 +1083,8 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
>  
>   intel_dmc_ucode_suspend(i915);
>  
> + i915_gem_suspend(i915);
> +
>   /*
>* The only requirement is to reboot with display DC states disabled,
>* for now leaving all display power wells in the INIT power domain
> -- 
> 2.36.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Re-do the intel-gtt split

[Matt Roper]

On Thu, Jun 16, 2022 at 03:49:43PM -0700, Lucas De Marchi wrote:
> Re-do what was attempted in commit 7a5c922377b4 ("drm/i915/gt: Split
> intel-gtt functions by arch"). The goal of that commit was to split the
> handlers for older hardware that depend on intel-gtt.ko so i915 can
> be built for non-x86 archs, after some more patches. Other archs do not
> need intel-gtt.ko.
> 
> Main issue with the previous approach: it moved all the hooks, including
> the gen8, which is used by all platforms gen8 and newer.  Re-do the
> split moving only the handlers for gen < 6, which are the only ones
> calling out to the separate module.
> 
> Signed-off-by: Lucas De Marchi 
> ---
>  drivers/gpu/drm/i915/Makefile |   2 +-
>  drivers/gpu/drm/i915/gt/intel_ggtt.c  | 559 +-
>  drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c | 132 +
>  drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h |  27 +
>  drivers/gpu/drm/i915/gt/intel_gt.c|   5 +-
>  drivers/gpu/drm/i915/gt/intel_gt.h|   9 -
>  drivers/gpu/drm/i915/gt/intel_gt_gmch.c   | 654 --
>  drivers/gpu/drm/i915/gt/intel_gt_gmch.h   |  46 --
>  drivers/gpu/drm/i915/gt/intel_gtt.h   |  12 +-
>  9 files changed, 713 insertions(+), 733 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
>  create mode 100644 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h
>  delete mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.c
>  delete mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index d2b18f03a33c..4166cd76997e 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -129,7 +129,7 @@ gt-y += \
>   gt/shmem_utils.o \
>   gt/sysfs_engines.o
>  # x86 intel-gtt module support
> -gt-$(CONFIG_X86) += gt/intel_gt_gmch.o
> +gt-$(CONFIG_X86) += gt/intel_ggtt_gmch.o
>  # autogenerated null render state
>  gt-y += \
>   gt/gen6_renderstate.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index e6b2eb122ad7..a83d6858b766 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -3,16 +3,18 @@
>   * Copyright © 2020 Intel Corporation
>   */
>  
> -#include 
>  #include 
>  #include 
> +#include 
> +#include 
>  
>  #include 
> +#include 
>  
>  #include "gem/i915_gem_lmem.h"
>  
> +#include "intel_ggtt_gmch.h"
>  #include "intel_gt.h"
> -#include "intel_gt_gmch.h"
>  #include "intel_gt_regs.h"
>  #include "i915_drv.h"
>  #include "i915_scatterlist.h"
> @@ -181,7 +183,7 @@ void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
>   spin_unlock_irq(&uncore->lock);
>  }
>  
> -void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
> +static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
>  {
>   struct intel_uncore *uncore = ggtt->vm.gt->uncore;
>  
> @@ -218,11 +220,232 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
>   return pte;
>  }
>  
> +static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
> +{
> + writeq(pte, addr);
> +}
> +
> +static void gen8_ggtt_insert_page(struct i915_address_space *vm,
> +   dma_addr_t addr,
> +   u64 offset,
> +   enum i915_cache_level level,
> +   u32 flags)
> +{
> + struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> + gen8_pte_t __iomem *pte =
> + (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
> +
> + gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
> +
> + ggtt->invalidate(ggtt);
> +}
> +
> +static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
> +  struct i915_vma_resource *vma_res,
> +  enum i915_cache_level level,
> +  u32 flags)
> +{
> + const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
> + struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> + gen8_pte_t __iomem *gte;
> + gen8_pte_t __iomem *end;
> + struct sgt_iter iter;
> + dma_addr_t addr;
> +
> + /*
> +  * Note that we ignore PTE_READ_ONLY here. The caller must be careful
> +  * not to allow the user to override access to a read only page.
> +  */
> +
> + gte = (gen8_pte_t __iomem *)ggtt->gsm;
> + gte += vma_res->start / I915_GTT_PAGE_SIZE;
> + end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
> +
> + for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
> + gen8_set_pte(gte++, pte_encode | addr);
> + GEM_BUG_ON(gte > end);
> +
> + /* Fill the allocated but "unused" space beyond the end of the buffer */
> + while (gte < end)
> + gen8_set_pte(gte++, vm->scratch[0]->encode);
> +
> + /*
> +  * We want to flush the TLBs only after we're certain all the PTE
> +  * updates have finished.
> +  */
> + ggtt->invali

[Intel-gfx] [PATCH] drm/i915: Call i915_gem_suspend() only after display is turned off

[José Roberto de Souza]

Gem buffers could still be in use by display after i915_gem_suspend()
is executed so there is chances that i915_gem_flush_free_objects()
will be being executed at the same time that
intel_runtime_pm_driver_release() is executed printing warnings about
wakerefs will being held.

So here only calling i915_gem_suspend() and by consequence
i915_gem_drain_freed_objects() only after display is down making
sure all buffers are freed.

Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_driver.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index d26dcca7e654a..4227675dd1cfe 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1067,8 +1067,6 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
intel_runtime_pm_disable(&i915->runtime_pm);
intel_power_domains_disable(i915);
 
-   i915_gem_suspend(i915);
-
if (HAS_DISPLAY(i915)) {
drm_kms_helper_poll_disable(&i915->drm);
 
@@ -1085,6 +1083,8 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
 
intel_dmc_ucode_suspend(i915);
 
+   i915_gem_suspend(i915);
+
/*
 * The only requirement is to reboot with display DC states disabled,
 * for now leaving all display power wells in the INIT power domain
-- 
2.36.1

[Intel-gfx] [PATCH v6 10/10] drm/i915: stolen memory use ttm backend

[Robert Beckett]

refactor stolen memory region to use ttm.
this necessitates using ttm resources to track reserved stolen regions
instead of drm_mm_nodes.

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/display/intel_fbc.c  |  78 ++--
 .../gpu/drm/i915/gem/i915_gem_object_types.h  |   2 -
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 440 +++---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.h|  21 +-
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   |   3 +-
 drivers/gpu/drm/i915/gem/i915_gem_ttm.h   |   7 +
 drivers/gpu/drm/i915/gt/intel_rc6.c   |   4 +-
 drivers/gpu/drm/i915/gt/selftest_reset.c  |  16 +-
 drivers/gpu/drm/i915/i915_debugfs.c   |   7 +-
 drivers/gpu/drm/i915/i915_drv.h   |   5 -
 drivers/gpu/drm/i915/intel_region_ttm.c   |  42 +-
 drivers/gpu/drm/i915/intel_region_ttm.h   |   8 +-
 drivers/gpu/drm/i915/selftests/mock_region.c  |   3 +-
 13 files changed, 294 insertions(+), 342 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 8b807284cde1..6f3afac5e8c9 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -38,6 +38,7 @@
  * forcibly disable it to allow proper screen updates.
  */
 
+#include "gem/i915_gem_stolen.h"
 #include 
 
 #include 
@@ -51,6 +52,7 @@
 #include "intel_display_types.h"
 #include "intel_fbc.h"
 #include "intel_frontbuffer.h"
+#include "gem/i915_gem_region.h"
 
 #define for_each_fbc_id(__dev_priv, __fbc_id) \
for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; 
(__fbc_id)++) \
@@ -92,8 +94,8 @@ struct intel_fbc {
struct mutex lock;
unsigned int busy_bits;
 
-   struct drm_mm_node compressed_fb;
-   struct drm_mm_node compressed_llb;
+   struct ttm_resource *compressed_fb;
+   struct ttm_resource *compressed_llb;
 
enum intel_fbc_id id;
 
@@ -331,16 +333,20 @@ static void i8xx_fbc_nuke(struct intel_fbc *fbc)
 static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
 {
struct drm_i915_private *i915 = fbc->i915;
+   u64 fb_offset = i915_gem_stolen_reserve_offset(fbc->compressed_fb);
+   u64 llb_offset = i915_gem_stolen_reserve_offset(fbc->compressed_llb);
 
+   GEM_BUG_ON(fb_offset == I915_BO_INVALID_OFFSET);
+   GEM_BUG_ON(llb_offset == I915_BO_INVALID_OFFSET);
GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start,
-fbc->compressed_fb.start, U32_MAX));
+fb_offset, U32_MAX));
GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start,
-fbc->compressed_llb.start, U32_MAX));
+llb_offset, U32_MAX));
 
intel_de_write(i915, FBC_CFB_BASE,
-  i915->dsm.start + fbc->compressed_fb.start);
+  i915->dsm.start + fb_offset);
intel_de_write(i915, FBC_LL_BASE,
-  i915->dsm.start + fbc->compressed_llb.start);
+  i915->dsm.start + llb_offset);
 }
 
 static const struct intel_fbc_funcs i8xx_fbc_funcs = {
@@ -448,8 +454,10 @@ static bool g4x_fbc_is_compressing(struct intel_fbc *fbc)
 static void g4x_fbc_program_cfb(struct intel_fbc *fbc)
 {
struct drm_i915_private *i915 = fbc->i915;
+   u64 fb_offset = i915_gem_stolen_reserve_offset(fbc->compressed_fb);
 
-   intel_de_write(i915, DPFC_CB_BASE, fbc->compressed_fb.start);
+   GEM_BUG_ON(fb_offset == I915_BO_INVALID_OFFSET);
+   intel_de_write(i915, DPFC_CB_BASE, fb_offset);
 }
 
 static const struct intel_fbc_funcs g4x_fbc_funcs = {
@@ -499,8 +507,10 @@ static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
 static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
 {
struct drm_i915_private *i915 = fbc->i915;
+   u64 fb_offset = i915_gem_stolen_reserve_offset(fbc->compressed_fb);
 
-   intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), 
fbc->compressed_fb.start);
+   GEM_BUG_ON(fb_offset == I915_BO_INVALID_OFFSET);
+   intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), fb_offset);
 }
 
 static const struct intel_fbc_funcs ilk_fbc_funcs = {
@@ -744,21 +754,24 @@ static int find_compression_limit(struct intel_fbc *fbc,
 {
struct drm_i915_private *i915 = fbc->i915;
u64 end = intel_fbc_stolen_end(i915);
-   int ret, limit = min_limit;
+   int limit = min_limit;
+   struct ttm_resource *res;
 
size /= limit;
 
/* Try to over-allocate to reduce reallocations and fragmentation. */
-   ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb,
-  size <<= 1, 4096, 0, end);
-   if (ret == 0)
+   res = i915_gem_stolen_reserve_range(i915, size <<= 1, 0, end);
+   if (!IS_ERR(res)) {
+   fbc->compressed_fb = res;
return limit;
+   }
 
for (; limit <= in

[Intel-gfx] [PATCH v6 05/10] drm/i915: instantiate ttm ranger manager for stolen memory

[Robert Beckett]

prepare for ttm based stolen region by using ttm range manager
as the resource manager for stolen region.

Signed-off-by: Robert Beckett 
Reviewed-by: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c |  6 ++--
 drivers/gpu/drm/i915/intel_region_ttm.c  | 31 +++-
 2 files changed, 27 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 40249fa28a7a..675e9ab30396 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -60,11 +60,13 @@ i915_ttm_region(struct ttm_device *bdev, int ttm_mem_type)
struct drm_i915_private *i915 = container_of(bdev, typeof(*i915), bdev);
 
/* There's some room for optimization here... */
-   GEM_BUG_ON(ttm_mem_type != I915_PL_SYSTEM &&
-  ttm_mem_type < I915_PL_LMEM0);
+   GEM_BUG_ON(ttm_mem_type == I915_PL_GGTT);
+
if (ttm_mem_type == I915_PL_SYSTEM)
return intel_memory_region_lookup(i915, INTEL_MEMORY_SYSTEM,
  0);
+   if (ttm_mem_type == I915_PL_STOLEN)
+   return i915->mm.stolen_region;
 
return intel_memory_region_lookup(i915, INTEL_MEMORY_LOCAL,
  ttm_mem_type - I915_PL_LMEM0);
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c 
b/drivers/gpu/drm/i915/intel_region_ttm.c
index fd2ecfdd8fa1..694e9acb69e2 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -54,7 +54,7 @@ void intel_region_ttm_device_fini(struct drm_i915_private 
*dev_priv)
 
 /*
  * Map the i915 memory regions to TTM memory types. We use the
- * driver-private types for now, reserving TTM_PL_VRAM for stolen
+ * driver-private types for now, reserving I915_PL_STOLEN for stolen
  * memory and TTM_PL_TT for GGTT use if decided to implement this.
  */
 int intel_region_to_ttm_type(const struct intel_memory_region *mem)
@@ -63,11 +63,17 @@ int intel_region_to_ttm_type(const struct 
intel_memory_region *mem)
 
GEM_BUG_ON(mem->type != INTEL_MEMORY_LOCAL &&
   mem->type != INTEL_MEMORY_MOCK &&
-  mem->type != INTEL_MEMORY_SYSTEM);
+  mem->type != INTEL_MEMORY_SYSTEM &&
+  mem->type != INTEL_MEMORY_STOLEN_SYSTEM &&
+  mem->type != INTEL_MEMORY_STOLEN_LOCAL);
 
if (mem->type == INTEL_MEMORY_SYSTEM)
return TTM_PL_SYSTEM;
 
+   if (mem->type == INTEL_MEMORY_STOLEN_SYSTEM ||
+   mem->type == INTEL_MEMORY_STOLEN_LOCAL)
+   return I915_PL_STOLEN;
+
type = mem->instance + TTM_PL_PRIV;
GEM_BUG_ON(type >= TTM_NUM_MEM_TYPES);
 
@@ -91,10 +97,16 @@ int intel_region_ttm_init(struct intel_memory_region *mem)
int mem_type = intel_region_to_ttm_type(mem);
int ret;
 
-   ret = i915_ttm_buddy_man_init(bdev, mem_type, false,
- resource_size(&mem->region),
- mem->io_size,
- mem->min_page_size, PAGE_SIZE);
+   if (mem_type == I915_PL_STOLEN) {
+   ret = ttm_range_man_init(bdev, mem_type, false,
+resource_size(&mem->region) >> 
PAGE_SHIFT);
+   mem->is_range_manager = true;
+   } else {
+   ret = i915_ttm_buddy_man_init(bdev, mem_type, false,
+ resource_size(&mem->region),
+ mem->io_size,
+ mem->min_page_size, PAGE_SIZE);
+   }
if (ret)
return ret;
 
@@ -114,6 +126,7 @@ int intel_region_ttm_init(struct intel_memory_region *mem)
 int intel_region_ttm_fini(struct intel_memory_region *mem)
 {
struct ttm_resource_manager *man = mem->region_private;
+   int mem_type = intel_region_to_ttm_type(mem);
int ret = -EBUSY;
int count;
 
@@ -144,8 +157,10 @@ int intel_region_ttm_fini(struct intel_memory_region *mem)
if (ret || !man)
return ret;
 
-   ret = i915_ttm_buddy_man_fini(&mem->i915->bdev,
- intel_region_to_ttm_type(mem));
+   if (mem_type == I915_PL_STOLEN)
+   ret = ttm_range_man_fini(&mem->i915->bdev, mem_type);
+   else
+   ret = i915_ttm_buddy_man_fini(&mem->i915->bdev, mem_type);
GEM_WARN_ON(ret);
mem->region_private = NULL;
 
-- 
2.25.1

[Intel-gfx] [PATCH v6 06/10] drm/i915: sanitize mem_flags for stolen buffers

[Robert Beckett]

Stolen regions are not page backed or considered iomem.
Prevent flags indicating such.
This correctly prevents stolen buffers from attempting to directly map
them.

See i915_gem_object_has_struct_page() and i915_gem_object_has_iomem()
usage for where it would break otherwise.

Signed-off-by: Robert Beckett 
Reviewed-by: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 675e9ab30396..81c67ca9edda 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -14,6 +14,7 @@
 #include "gem/i915_gem_region.h"
 #include "gem/i915_gem_ttm.h"
 #include "gem/i915_gem_ttm_move.h"
+#include "gem/i915_gem_stolen.h"
 
 #include "gt/intel_engine_pm.h"
 #include "gt/intel_gt.h"
@@ -124,8 +125,9 @@ void i915_ttm_adjust_gem_after_move(struct 
drm_i915_gem_object *obj)
 
obj->mem_flags &= ~(I915_BO_FLAG_STRUCT_PAGE | I915_BO_FLAG_IOMEM);
 
-   obj->mem_flags |= i915_ttm_cpu_maps_iomem(bo->resource) ? 
I915_BO_FLAG_IOMEM :
-   I915_BO_FLAG_STRUCT_PAGE;
+   if (!i915_gem_object_is_stolen(obj))
+   obj->mem_flags |= i915_ttm_cpu_maps_iomem(bo->resource) ? 
I915_BO_FLAG_IOMEM :
+   I915_BO_FLAG_STRUCT_PAGE;
 
if (!obj->ttm.cache_level_override) {
cache_level = i915_ttm_cache_level(to_i915(bo->base.dev),
-- 
2.25.1

[Intel-gfx] [PATCH v6 07/10] drm/i915: ttm move/clear logic fix

[Robert Beckett]

ttm managed buffers start off with system resource definitions and ttm_tt
tracking structures allocated (though unpopulated).
currently this prevents clearing of buffers on first move to desired
placements.

The desired behaviour is to clear user allocated buffers and any kernel
buffers that specifically requests it only.
Make the logic match the desired behaviour.

Signed-off-by: Robert Beckett 
Reviewed-by: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 22 +++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 81c67ca9edda..a3f8fc056dbc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -3,6 +3,7 @@
  * Copyright © 2021 Intel Corporation
  */
 
+#include "drm/ttm/ttm_tt.h"
 #include 
 
 #include "i915_deps.h"
@@ -476,6 +477,25 @@ __i915_ttm_move(struct ttm_buffer_object *bo,
return fence;
 }
 
+static bool
+allow_clear(struct drm_i915_gem_object *obj, struct ttm_tt *ttm, struct 
ttm_resource *dst_mem)
+{
+   /* never clear stolen */
+   if (dst_mem->mem_type == I915_PL_STOLEN)
+   return false;
+   /*
+* we want to clear user buffers and any kernel buffers
+* that specifically request clearing.
+*/
+   if (obj->flags & I915_BO_ALLOC_USER)
+   return true;
+
+   if (ttm && ttm->page_flags & TTM_TT_FLAG_ZERO_ALLOC)
+   return true;
+
+   return false;
+}
+
 /**
  * i915_ttm_move - The TTM move callback used by i915.
  * @bo: The buffer object.
@@ -526,7 +546,7 @@ int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
return PTR_ERR(dst_rsgt);
 
clear = !i915_ttm_cpu_maps_iomem(bo->resource) && (!ttm || 
!ttm_tt_is_populated(ttm));
-   if (!(clear && ttm && !(ttm->page_flags & TTM_TT_FLAG_ZERO_ALLOC))) {
+   if (!clear || allow_clear(obj, ttm, dst_mem)) {
struct i915_deps deps;
 
i915_deps_init(&deps, GFP_KERNEL | __GFP_NORETRY | 
__GFP_NOWARN);
-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Improve on suspend / resume time with VT-d enabled (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Improve on suspend / resume time with VT-d enabled (rev2)
URL   : https://patchwork.freedesktop.org/series/102187/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11776 -> Patchwork_102187v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/index.html

Participating hosts (35 -> 35)
--

  Additional (1): fi-cml-u2 
  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_102187v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][1] ([i915#1208]) +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-cml-u2:  NOTRUN -> [SKIP][2] ([i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/fi-cml-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-cml-u2:  NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/fi-cml-u2/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050:   [PASS][4] -> [DMESG-FAIL][5] ([i915#2373])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][6] -> [DMESG-FAIL][7] ([i915#4528])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [PASS][8] -> [INCOMPLETE][9] ([i915#5982])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@vga-hpd-fast:
- fi-cml-u2:  NOTRUN -> [SKIP][11] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/fi-cml-u2/igt@kms_chamel...@vga-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-cml-u2:  NOTRUN -> [SKIP][12] ([fdo#109278]) +1 similar issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/fi-cml-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- fi-tgl-u2:  [PASS][13] -> [DMESG-WARN][14] ([i915#402]) +1 
similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2:  NOTRUN -> [SKIP][15] ([fdo#109285])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/fi-cml-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2:  NOTRUN -> [DMESG-WARN][16] ([i915#4269])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2:  NOTRUN -> [SKIP][17] ([fdo#109278] / [i915#533])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/fi-cml-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-cml-u2:  NOTRUN -> [SKIP][18] ([i915#3555])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/fi-cml-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-cml-u2:  NOTRUN -> [SKIP][19] ([fdo#109295] / [i915#3301])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102187v2/fi-cml-u2/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- fi-bsw-n3050:   NOTRUN -> [FAIL][20] ([fdo#109271] / [i915#3428] / 
[i915#4312])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10218

[Intel-gfx] [PATCH v6 08/10] drm/i915: allow memory region creators to alloc and free the region

[Robert Beckett]

add callbacks for alloc and free.
this allows region creators to allocate any extra storage they may
require.

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/intel_memory_region.c | 16 +---
 drivers/gpu/drm/i915/intel_memory_region.h |  2 ++
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_memory_region.c 
b/drivers/gpu/drm/i915/intel_memory_region.c
index e38d2db1c3e3..3da07a712f90 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -231,7 +231,10 @@ intel_memory_region_create(struct drm_i915_private *i915,
struct intel_memory_region *mem;
int err;
 
-   mem = kzalloc(sizeof(*mem), GFP_KERNEL);
+   if (ops->alloc)
+   mem = ops->alloc();
+   else
+   mem = kzalloc(sizeof(*mem), GFP_KERNEL);
if (!mem)
return ERR_PTR(-ENOMEM);
 
@@ -265,7 +268,10 @@ intel_memory_region_create(struct drm_i915_private *i915,
if (mem->ops->release)
mem->ops->release(mem);
 err_free:
-   kfree(mem);
+   if (mem->ops->free)
+   mem->ops->free(mem);
+   else
+   kfree(mem);
return ERR_PTR(err);
 }
 
@@ -288,7 +294,11 @@ void intel_memory_region_destroy(struct 
intel_memory_region *mem)
 
GEM_WARN_ON(!list_empty_careful(&mem->objects.list));
mutex_destroy(&mem->objects.lock);
-   if (!ret)
+   if (ret)
+   return;
+   if (mem->ops->free)
+   mem->ops->free(mem);
+   else
kfree(mem);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h 
b/drivers/gpu/drm/i915/intel_memory_region.h
index 3d8378c1b447..048955b5429f 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -61,6 +61,8 @@ struct intel_memory_region_ops {
   resource_size_t size,
   resource_size_t page_size,
   unsigned int flags);
+   struct intel_memory_region *(*alloc)(void);
+   void (*free)(struct intel_memory_region *mem);
 };
 
 struct intel_memory_region {
-- 
2.25.1

[Intel-gfx] [PATCH v6 09/10] drm/i915/ttm: add buffer pin on alloc flag

[Robert Beckett]

For situations where allocations need to fail on alloc instead of
delayed get_pages, add a new alloc flag to pin the ttm bo.
This makes sure that the resource has been allocated during buffer
creation, allowing it to fail with an error if the placement is
exhausted.
This allows existing fallback options for stolen backend allocation like
create_ring_vma to work as expected.

Signed-off-by: Robert Beckett 
---
 .../gpu/drm/i915/gem/i915_gem_object_types.h  | 13 ++
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   | 25 ++-
 2 files changed, 32 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 6632ed52e919..07bc11247a3e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -325,17 +325,20 @@ struct drm_i915_gem_object {
  * dealing with userspace objects the CPU fault handler is free to ignore this.
  */
 #define I915_BO_ALLOC_GPU_ONLY   BIT(6)
+/* object should be pinned in destination region from allocation */
+#define I915_BO_ALLOC_PINNED BIT(7)
 #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
 I915_BO_ALLOC_VOLATILE | \
 I915_BO_ALLOC_CPU_CLEAR | \
 I915_BO_ALLOC_USER | \
 I915_BO_ALLOC_PM_VOLATILE | \
 I915_BO_ALLOC_PM_EARLY | \
-I915_BO_ALLOC_GPU_ONLY)
-#define I915_BO_READONLY  BIT(7)
-#define I915_TILING_QUIRK_BIT 8 /* unknown swizzling; do not release! */
-#define I915_BO_PROTECTED BIT(9)
-#define I915_BO_WAS_BOUND_BIT 10
+I915_BO_ALLOC_GPU_ONLY | \
+I915_BO_ALLOC_PINNED)
+#define I915_BO_READONLY  BIT(8)
+#define I915_TILING_QUIRK_BIT 9 /* unknown swizzling; do not release! */
+#define I915_BO_PROTECTED BIT(10)
+#define I915_BO_WAS_BOUND_BIT 11
/**
 * @mem_flags - Mutable placement-related flags
 *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 27d59639177f..bb988608296d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -998,6 +998,13 @@ static void i915_ttm_delayed_free(struct 
drm_i915_gem_object *obj)
 {
GEM_BUG_ON(!obj->ttm.created);
 
+   /* stolen objects are pinned for lifetime. Unpin before putting */
+   if (obj->flags & I915_BO_ALLOC_PINNED) {
+   ttm_bo_reserve(i915_gem_to_ttm(obj), true, false, NULL);
+   ttm_bo_unpin(i915_gem_to_ttm(obj));
+   ttm_bo_unreserve(i915_gem_to_ttm(obj));
+   }
+
ttm_bo_put(i915_gem_to_ttm(obj));
 }
 
@@ -1193,6 +1200,9 @@ int __i915_gem_ttm_object_init(struct intel_memory_region 
*mem,
.no_wait_gpu = false,
};
enum ttm_bo_type bo_type;
+   struct ttm_place _place;
+   struct ttm_placement _placement;
+   struct ttm_placement *placement;
int ret;
 
drm_gem_private_object_init(&i915->drm, &obj->base, size);
@@ -1222,6 +1232,17 @@ int __i915_gem_ttm_object_init(struct 
intel_memory_region *mem,
 */
i915_gem_object_make_unshrinkable(obj);
 
+   if (obj->flags & I915_BO_ALLOC_PINNED) {
+   i915_ttm_place_from_region(mem, &_place, obj->bo_offset,
+  obj->base.size, obj->flags);
+   _placement.num_placement = 1;
+   _placement.placement = &_place;
+   _placement.num_busy_placement = 0;
+   _placement.busy_placement = NULL;
+   placement = &_placement;
+   } else {
+   placement = &i915_sys_placement;
+   }
/*
 * If this function fails, it will call the destructor, but
 * our caller still owns the object. So no freeing in the
@@ -1230,7 +1251,7 @@ int __i915_gem_ttm_object_init(struct intel_memory_region 
*mem,
 * until successful initialization.
 */
ret = ttm_bo_init_reserved(&i915->bdev, i915_gem_to_ttm(obj), size,
-  bo_type, &i915_sys_placement,
+  bo_type, placement,
   page_size >> PAGE_SHIFT,
   &ctx, NULL, NULL, i915_ttm_bo_destroy);
if (ret)
@@ -1242,6 +1263,8 @@ int __i915_gem_ttm_object_init(struct intel_memory_region 
*mem,
i915_ttm_adjust_domains_after_move(obj);
i915_ttm_adjust_gem_after_move(obj);
obj->ttm.cache_level_override = false;
+   if (obj->flags & I915_BO_ALLOC_PINNED)
+   ttm_bo_pin(i915_gem_to_ttm(obj));
i915_gem_object_unlock(obj);
 
return 0;
-- 
2.25.1

[Intel-gfx] [PATCH v6 03/10] drm/i915/ttm: only trust snooping for dgfx when deciding default cache_level

[Robert Beckett]

By default i915_ttm_cache_level() decides I915_CACHE_LLC if HAS_SNOOP.
This is divergent from existing backends code which only considers
HAS_LLC.
Testing shows that trusting snooping on gen5- is unreliable and bsw via
ggtt mappings, so limit DGFX for now and maintain previous behaviour.

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 4c1de0b4a10f..40249fa28a7a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -46,7 +46,9 @@ static enum i915_cache_level
 i915_ttm_cache_level(struct drm_i915_private *i915, struct ttm_resource *res,
 struct ttm_tt *ttm)
 {
-   return ((HAS_LLC(i915) || HAS_SNOOP(i915)) &&
+   bool can_snoop = HAS_SNOOP(i915) && IS_DGFX(i915);
+
+   return ((HAS_LLC(i915) || can_snoop) &&
!i915_ttm_gtt_binds_lmem(res) &&
ttm->caching == ttm_cached) ? I915_CACHE_LLC :
I915_CACHE_NONE;
-- 
2.25.1

[Intel-gfx] [PATCH v6 04/10] drm/i915/gem: selftest should not attempt mmap of private regions

[Robert Beckett]

During testing make can_mmap consider whether the region is private.

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 5bc93a1ce3e3..76181e28c75e 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -869,6 +869,9 @@ static bool can_mmap(struct drm_i915_gem_object *obj, enum 
i915_mmap_type type)
struct drm_i915_private *i915 = to_i915(obj->base.dev);
bool no_map;
 
+   if (obj->mm.region && obj->mm.region->private)
+   return false;
+
if (obj->ops->mmap_offset)
return type == I915_MMAP_TYPE_FIXED;
else if (type == I915_MMAP_TYPE_FIXED)
-- 
2.25.1

[Intel-gfx] [PATCH v6 02/10] drm/i915: limit ttm to dma32 for i965G[M]

[Robert Beckett]

i965G[M] cannot relocate objects above 4GiB.
Ensure ttm uses dma32 on these systems.

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/intel_region_ttm.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c 
b/drivers/gpu/drm/i915/intel_region_ttm.c
index 62ff77445b01..fd2ecfdd8fa1 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -32,10 +32,15 @@
 int intel_region_ttm_device_init(struct drm_i915_private *dev_priv)
 {
struct drm_device *drm = &dev_priv->drm;
+   bool use_dma32 = false;
+
+   /* i965g[m] cannot relocate objects above 4GiB. */
+   if (IS_I965GM(dev_priv) || IS_I965G(dev_priv))
+   use_dma32 = true;
 
return ttm_device_init(&dev_priv->bdev, i915_ttm_driver(),
   drm->dev, drm->anon_inode->i_mapping,
-  drm->vma_offset_manager, false, false);
+  drm->vma_offset_manager, false, use_dma32);
 }
 
 /**
-- 
2.25.1

[Intel-gfx] [PATCH v6 01/10] drm/i915/ttm: dont trample cache_level overrides during ttm move

[Robert Beckett]

Various places within the driver override the default chosen cache_level.
Before ttm, these overrides were permanent until explicitly changed again
or for the lifetime of the buffer.

TTM movement code came along and decided that it could make that
decision at that time, which is usually well after object creation, so
overrode the cache_level decision and reverted it back to its default
decision.

Add logic to indicate whether the caching mode has been set by anything
other than the move logic. If so, assume that the code that overrode the
defaults knows best and keep it.

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/gem/i915_gem_object.c   | 1 +
 drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c  | 1 +
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 9 ++---
 4 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 06b1b188ce5a..519887769c08 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -125,6 +125,7 @@ void i915_gem_object_set_cache_coherency(struct 
drm_i915_gem_object *obj,
struct drm_i915_private *i915 = to_i915(obj->base.dev);
 
obj->cache_level = cache_level;
+   obj->ttm.cache_level_override = true;
 
if (cache_level != I915_CACHE_NONE)
obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ |
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 2c88bdb8ff7c..6632ed52e919 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -605,6 +605,7 @@ struct drm_i915_gem_object {
struct i915_gem_object_page_iter get_io_page;
struct drm_i915_gem_object *backup;
bool created:1;
+   bool cache_level_override:1;
} ttm;
 
/*
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 4c25d9b2f138..27d59639177f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -1241,6 +1241,7 @@ int __i915_gem_ttm_object_init(struct intel_memory_region 
*mem,
i915_gem_object_init_memory_region(obj, mem);
i915_ttm_adjust_domains_after_move(obj);
i915_ttm_adjust_gem_after_move(obj);
+   obj->ttm.cache_level_override = false;
i915_gem_object_unlock(obj);
 
return 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index a10716f4e717..4c1de0b4a10f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -123,9 +123,12 @@ void i915_ttm_adjust_gem_after_move(struct 
drm_i915_gem_object *obj)
obj->mem_flags |= i915_ttm_cpu_maps_iomem(bo->resource) ? 
I915_BO_FLAG_IOMEM :
I915_BO_FLAG_STRUCT_PAGE;
 
-   cache_level = i915_ttm_cache_level(to_i915(bo->base.dev), bo->resource,
-  bo->ttm);
-   i915_gem_object_set_cache_coherency(obj, cache_level);
+   if (!obj->ttm.cache_level_override) {
+   cache_level = i915_ttm_cache_level(to_i915(bo->base.dev),
+  bo->resource, bo->ttm);
+   i915_gem_object_set_cache_coherency(obj, cache_level);
+   obj->ttm.cache_level_override = false;
+   }
 }
 
 /**
-- 
2.25.1

[Intel-gfx] [PATCH v6 00/10] drm/i915: ttm for stolen

[Robert Beckett]

This series refactors i915's stolen memory region to use ttm.

v2: handle disabled stolen similar to legacy version.
relying on ttm to fail allocs works fine, but is dmesg noisy and causes 
testing
dmesg warning regressions.

v3: rebase to latest drm-tip.
fix v2 code refactor which could leave a buffer pinned.
locally passes fftl again now.

v4: - Allow memory regions creators to do allocation. Allows stolen region 
to track
  it's own reservations.
- Pre-reserve first page of stolen mem (add back 
WaSkipStolenMemoryFirstPage:bdw+)
- Improve commit descritpion for "drm/i915: sanitize mem_flags for 
stolen buffers"
- replace i915_gem_object_pin_pages_unlocked() call with manual locking 
and pinning.
  this avoids ww ctx class reuse during context creation -> ring vma 
obj alloc.

v5: - detect both types of stolen as stolen buffers in
  "drm/i915: sanitize mem_flags for stolen buffers"
- in stolen_object_init limit page size to mem region minimum.
  The range allocator expects the page_size to define the
  alignment

v6: - Share first 4 patches from ttm for internal series as generic
  i915 ttm fixes
- Drop patch 4 from v5. We don't need separate object ops just
  to satisfy test interfaces. The tests have now been fixed via
  checking whether the memory region is private to decide
  whether to mmap
- Add new buffer pin alloc flag to allow creation of buffers in
  their final ttm placement instead of deferring until
  get_pages. This fixes legacy fallback paths for buffer
  allocations during stolen memory pressure.

Robert Beckett (10):
  drm/i915/ttm: dont trample cache_level overrides during ttm move
  drm/i915: limit ttm to dma32 for i965G[M]
  drm/i915/ttm: only trust snooping for dgfx when deciding default
cache_level
  drm/i915/gem: selftest should not attempt mmap of private regions
  drm/i915: instantiate ttm ranger manager for stolen memory
  drm/i915: sanitize mem_flags for stolen buffers
  drm/i915: ttm move/clear logic fix
  drm/i915: allow memory region creators to alloc and free the region
  drm/i915/ttm: add buffer pin on alloc flag
  drm/i915: stolen memory use ttm backend

 drivers/gpu/drm/i915/display/intel_fbc.c  |  78 ++--
 drivers/gpu/drm/i915/gem/i915_gem_object.c|   1 +
 .../gpu/drm/i915/gem/i915_gem_object_types.h  |  16 +-
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 440 +++---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.h|  21 +-
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   |  29 +-
 drivers/gpu/drm/i915/gem/i915_gem_ttm.h   |   7 +
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c  |  47 +-
 .../drm/i915/gem/selftests/i915_gem_mman.c|   3 +
 drivers/gpu/drm/i915/gt/intel_rc6.c   |   4 +-
 drivers/gpu/drm/i915/gt/selftest_reset.c  |  16 +-
 drivers/gpu/drm/i915/i915_debugfs.c   |   7 +-
 drivers/gpu/drm/i915/i915_drv.h   |   5 -
 drivers/gpu/drm/i915/intel_memory_region.c|  16 +-
 drivers/gpu/drm/i915/intel_memory_region.h|   2 +
 drivers/gpu/drm/i915/intel_region_ttm.c   |  80 +++-
 drivers/gpu/drm/i915/intel_region_ttm.h   |   8 +-
 drivers/gpu/drm/i915/selftests/mock_region.c  |   3 +-
 18 files changed, 414 insertions(+), 369 deletions(-)

-- 
2.25.1

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Improve on suspend / resume time with VT-d enabled (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Improve on suspend / resume time with VT-d enabled (rev2)
URL   : https://patchwork.freedesktop.org/series/102187/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[Lucas De Marchi]

Cc'ing intel-pci, lkml, Bjorn

On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:

On Thu, 16 Jun 2022, priyanka.dandam...@intel.com wrote:

From: Akeem G Abodunrin 

Add support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
systems. So, those devices cannot claim larger memory BAR windows size due
to the system BIOS limitation. With this change, it would be possible to
reprogram the windows of the bridge directly above the requesting device
on the same BAR type.


There is a big caveat here that this may be too late as other drivers
may have already mapped their BARs - so probably too late in the pci scan
for it to be effective. In fact, after using this for a while, it seems
to fail too often, particularly on CFL systems.

Do we have any alternative to be done in the PCI subsystem during the
scan?  There is other work in progress to allow i915 to use the rest of
the device memory even with a smaller BAR, but it would be better if we
can improve our chances of succeeding the resize.

thanks
Lucas De Marchi




Signed-off-by: Akeem G Abodunrin 
Signed-off-by: Michał Winiarski 
Cc: Stuart Summers 
Cc: Michael J Ruhl 
Cc: Prathap Kumar Valsan 
Signed-off-by: Priyanka Dandamudi 
Reviewed-by: Matthew Auld 


Please see https://lore.kernel.org/r/87pmj8vesm@intel.com


---
 drivers/gpu/drm/i915/i915_driver.c | 92 ++
 1 file changed, 92 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index d26dcca7e654..4bdb471cb2e2 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
__intel_gt_reset(to_gt(i915), ALL_ENGINES);
 }

+static void __release_bars(struct pci_dev *pdev)
+{
+   int resno;
+
+   for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
+   if (pci_resource_len(pdev, resno))
+   pci_release_resource(pdev, resno);
+   }
+}
+
+static void
+__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
+{
+   struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+   int bar_size = pci_rebar_bytes_to_size(size);
+   int ret;
+
+   __release_bars(pdev);
+
+   ret = pci_resize_resource(pdev, resno, bar_size);
+   if (ret) {
+   drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
+resno, 1 << bar_size, ERR_PTR(ret));
+   return;
+   }
+
+   drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
+}
+
+/* BAR size starts from 1MB - 2^20 */
+#define BAR_SIZE_SHIFT 20
+static resource_size_t
+__lmem_rebar_size(struct drm_i915_private *i915, int resno)
+{
+   struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+   u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
+   resource_size_t size;
+
+   if (!rebar)
+   return 0;
+
+   size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
+
+   if (size <= pci_resource_len(pdev, resno))
+   return 0;
+
+   return size;
+}
+
+#define LMEM_BAR_NUM 2
+static void i915_resize_lmem_bar(struct drm_i915_private *i915)
+{
+   struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+   struct pci_bus *root = pdev->bus;
+   struct resource *root_res;
+   resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
+   u32 pci_cmd;
+   int i;
+
+   if (!rebar_size)
+   return;
+
+   /* Find out if root bus contains 64bit memory addressing */
+   while (root->parent)
+   root = root->parent;
+
+   pci_bus_for_each_resource(root, root_res, i) {
+   if (root_res && root_res->flags & (IORESOURCE_MEM |
+   IORESOURCE_MEM_64) && root_res->start > 
0x1ull)
+   break;
+   }
+
+   /* pci_resize_resource will fail anyways */
+   if (!root_res) {
+   drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is 
missing\n");
+   return;
+   }
+
+   /* First disable PCI memory decoding references */
+   pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
+   pci_write_config_dword(pdev, PCI_COMMAND,
+  pci_cmd & ~PCI_COMMAND_MEMORY);
+
+   __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
+
+   pci_assign_unassigned_bus_resources(pdev->bus);
+   pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
+}
+
 /**
  * i915_driver_early_probe - setup state not requiring device access
  * @dev_priv: device private
@@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct 
pci_device_id *ent)

disable_rpm_wa

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix a lockdep warning at error capture

[Patchwork]

== Series Details ==

Series: drm/i915: Fix a lockdep warning at error capture
URL   : https://patchwork.freedesktop.org/series/105291/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11776 -> Patchwork_105291v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/index.html

Participating hosts (35 -> 35)
--

  Additional (1): fi-icl-u2 
  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105291v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][1] ([i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [PASS][4] -> [INCOMPLETE][5] ([i915#4983])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][6] -> [DMESG-FAIL][7] ([i915#4528])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [PASS][8] -> [INCOMPLETE][9] ([i915#5982])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([i915#5903])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-icl-u2/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-apl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][13] ([fdo#111827]) +8 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2:  NOTRUN -> [SKIP][14] ([fdo#109278] / [i915#4103]) +1 
similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- fi-tgl-u2:  [PASS][15] -> [DMESG-WARN][16] ([i915#402])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11776/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html

  * igt@kms_force_connector_basic@force-connector-state:
- fi-icl-u2:  NOTRUN -> [WARN][17] ([i915#6008])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-icl-u2/igt@kms_force_connector_ba...@force-connector-state.html
- fi-apl-guc: NOTRUN -> [SKIP][18] ([fdo#109271]) +14 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-apl-guc/igt@kms_force_connector_ba...@force-connector-state.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][19] ([fdo#109285])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-icl-u2:  NOTRUN -> [SKIP][20] ([fdo#109278])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105291v1/fi-icl-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.h

[Intel-gfx] [PATCH v2 05/16] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()

[Ville Syrjala]

From: Ville Syrjälä 

Only reassign the pipe's DPLL if it's going through a full
.compute_config() cycle. If OTOH it's just getting modeset
eg. in order to change cdclk there doesn't seem much point in
picking a new DPLL for it.

This should also prevent .get_dplls() from seeing a funky port_clock
for DP even in cases where the readout produces a non-standard
clock and we (for some reason) have decided to not fully recompute
the state to remedy the situation.

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 17 +
 drivers/gpu/drm/i915/display/intel_dpll.c|  6 ++
 2 files changed, 3 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index b8c0ede1f7fd..59dd66642c5f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6201,20 +6201,6 @@ intel_crtc_update_active_timings(const struct 
intel_crtc_state *crtc_state)
}
 }
 
-static void intel_modeset_clear_plls(struct intel_atomic_state *state)
-{
-   struct intel_crtc_state *new_crtc_state;
-   struct intel_crtc *crtc;
-   int i;
-
-   for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
-   if (!intel_crtc_needs_modeset(new_crtc_state))
-   continue;
-
-   intel_release_shared_dplls(state, crtc);
-   }
-}
-
 /*
  * This implements the workaround described in the "notes" section of the mode
  * set sequence documentation. When going from no pipes or single pipe to
@@ -7048,6 +7034,7 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
 
+   intel_release_shared_dplls(state, crtc);
continue;
}
 
@@ -7095,8 +7082,6 @@ static int intel_atomic_check(struct drm_device *dev,
ret = intel_modeset_calc_cdclk(state);
if (ret)
return ret;
-
-   intel_modeset_clear_plls(state);
}
 
ret = intel_atomic_check_crtcs(state);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 8d095f28fa20..69dc018385db 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1436,11 +1436,9 @@ int intel_dpll_crtc_get_shared_dpll(struct 
intel_atomic_state *state,
int ret;
 
drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
+   drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && 
crtc_state->shared_dpll);
 
-   if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
-   return 0;
-
-   if (!crtc_state->hw.enable)
+   if (!crtc_state->hw.enable || crtc_state->shared_dpll)
return 0;
 
if (!i915->dpll_funcs->crtc_get_shared_dpll)
-- 
2.35.1

[Intel-gfx] [PATCH v2 11/16] drm/i915: Nuke fastet state copy hacks

[Ville Syrjala]

From: Ville Syrjälä 

Now that we no longer do the fuzzy clock and M/N checks we can
get rid of the fastset state copy hacks.

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 28 +++-
 1 file changed, 3 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index c98c93500a43..16a4ea183746 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6262,23 +6262,6 @@ static void intel_crtc_check_fastset(const struct 
intel_crtc_state *old_crtc_sta
new_crtc_state->update_pipe = true;
 }
 
-static void intel_crtc_copy_fastset(const struct intel_crtc_state 
*old_crtc_state,
-   struct intel_crtc_state *new_crtc_state)
-{
-   /*
-* If we're not doing the full modeset we want to
-* keep the current M/N values as they may be
-* sufficiently different to the computed values
-* to cause problems.
-*
-* FIXME: should really copy more fuzzy state here
-*/
-   new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
-   new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
-   new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
-   new_crtc_state->has_drrs = old_crtc_state->has_drrs;
-}
-
 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
  struct intel_crtc *crtc,
  u8 plane_ids_mask)
@@ -6988,17 +6971,12 @@ static int intel_atomic_check(struct drm_device *dev,
 
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
-   if (intel_crtc_needs_modeset(new_crtc_state)) {
-   any_ms = true;
-
-   intel_release_shared_dplls(state, crtc);
+   if (!intel_crtc_needs_modeset(new_crtc_state))
continue;
-   }
 
-   if (!new_crtc_state->update_pipe)
-   continue;
+   any_ms = true;
 
-   intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
+   intel_release_shared_dplls(state, crtc);
}
 
if (any_ms && !check_digital_port_conflicts(state)) {
-- 
2.35.1

Re: [Intel-gfx] [Intel-gfx 1/1] drm/i915/guc: Don't update engine busyness stats too frequently

[Teres Alexis, Alan Previn]

> Who did you find is doing the sampling in the real world use case? AFAIR 
> if one one is querying busyness, I thought there would only be the GuC 
> ping worker which runs extremely infrequently (to avoid some counter 
> overflow).
> 
> Regards,
> 
> Tvrtko
> 
> > 

Hi Tvrtko, the case where we are launching many tiny transcode workloads in 
quick succession sees the gt_unpark/park
getting his hundreds or thousands of time - this is where the biggest hit comes 
from (as per the worst case example
number in the comment). 

...alan

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Cleanup interface for MCR operations

[Harish Chegondi]

On Tue, Jun 14, 2022 at 05:10:19PM -0700, Matt Roper wrote:
> Let's replace the assortment of intel_gt_* and intel_uncore_* functions
> that operate on MCR registers with a cleaner set of interfaces:
> 
>   * intel_gt_mcr_read -- unicast read from specific instance
>   * intel_gt_mcr_read_any[_fw] -- unicast read from any non-terminated
> instance
>   * intel_gt_mcr_unicast_write -- unicast write to specific instance
>   * intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances
> 
> We'll also replace the historic "slice" and "subslice" terminology with
> "group" and "instance" to match the documentation for more recent
> platforms; these days MCR steering applies to more types of replication
> than just slice/subslice.
> 
> v2:
>  - Reference the new kerneldoc from i915.rst.  (Jani)
>  - Tweak the wording of the documentation for a couple functions to
>clarify the difference between "_fw" and non-"_fw" forms.
> 
> Signed-off-by: Matt Roper 
> Acked-by: Jani Nikula 
> ---
>  Documentation/gpu/i915.rst  |  12 +
>  drivers/gpu/drm/i915/gem/i915_gem_stolen.c  |   2 +-
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c   |  33 ++-
>  drivers/gpu/drm/i915/gt/intel_gt_debugfs.c  |   2 +-
>  drivers/gpu/drm/i915/gt/intel_gt_mcr.c  | 239 
>  drivers/gpu/drm/i915/gt/intel_gt_mcr.h  |  43 ++--
>  drivers/gpu/drm/i915/gt/intel_region_lmem.c |   4 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c |   8 +-
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c  |   2 +-
>  9 files changed, 200 insertions(+), 145 deletions(-)
> 
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index 54060cd6c419..4e59db1cfb00 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -246,6 +246,18 @@ Display State Buffer
>  .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
> :internal:
>  
> +GT Programming
> +==
> +
> +Multicast/Replicated (MCR) Registers
> +
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +   :doc: GT Multicast/Replicated (MCR) Register Support
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +   :internal:
> +
>  Memory Management and Command Submission
>  
>  
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index da30503d3ca2..fa54823d1219 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -835,7 +835,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, 
> u16 type,
>   } else {
>   resource_size_t lmem_range;
>  
> - lmem_range = intel_gt_read_register(&i915->gt0, 
> XEHPSDV_TILE0_ADDR_RANGE) & 0x;
> + lmem_range = intel_gt_mcr_read_any(&i915->gt0, 
> XEHPSDV_TILE0_ADDR_RANGE) & 0x;
>   lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
>   lmem_size *= SZ_1G;
>   }
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 244af1bdb7db..136cc44c3deb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1428,14 +1428,6 @@ void intel_engine_cancel_stop_cs(struct 
> intel_engine_cs *engine)
>   ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
>  }
>  
> -static u32
> -read_subslice_reg(const struct intel_engine_cs *engine,
> -   int slice, int subslice, i915_reg_t reg)
> -{
> - return intel_uncore_read_with_mcr_steering(engine->uncore, reg,
> -slice, subslice);
> -}
> -
>  /* NB: please notice the memset */
>  void intel_engine_get_instdone(const struct intel_engine_cs *engine,
>  struct intel_instdone *instdone)
> @@ -1469,28 +1461,33 @@ void intel_engine_get_instdone(const struct 
> intel_engine_cs *engine,
>   if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
>   for_each_instdone_gslice_dss_xehp(i915, sseu, iter, 
> slice, subslice) {
>   instdone->sampler[slice][subslice] =
> - read_subslice_reg(engine, slice, 
> subslice,
> -   
> GEN7_SAMPLER_INSTDONE);
> + intel_gt_mcr_read(engine->gt,
> +   GEN7_SAMPLER_INSTDONE,
> +   slice, subslice);
>   instdone->row[slice][subslice] =
> - read_subslice_reg(engine, slice, 
> subslice,
> -   GEN7_ROW_INSTDONE);
> + intel_gt_mcr_read(engine->gt,
> + 

[Intel-gfx] [PATCH v2 16/16] drm/i915: Round TMDS clock to nearest

[Ville Syrjala]

From: Ville Syrjälä 

Use round-to-nearest behavour when calculating the TMDS clock.
Matches what we do for most other clock related things.

Acked-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
 drivers/gpu/drm/i915/display/intel_hdmi.c| 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 7e45dd99d03c..1ec9f3d54031 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4585,7 +4585,8 @@ int intel_crtc_dotclock(const struct intel_crtc_state 
*pipe_config)
dotclock = intel_dotclock_calculate(pipe_config->port_clock,
&pipe_config->dp_m_n);
else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
-   dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
+   dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
+pipe_config->pipe_bpp);
else
dotclock = pipe_config->port_clock;
 
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 1ae09431f53a..0b04b3800cd4 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1891,7 +1891,7 @@ int intel_hdmi_tmds_clock(int clock, int bpc, bool 
ycbcr420_output)
 *  1.5x for 12bpc
 *  1.25x for 10bpc
 */
-   return clock * bpc / 8;
+   return DIV_ROUND_CLOSEST(clock * bpc, 8);
 }
 
 static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int 
bpc)
-- 
2.35.1

[Intel-gfx] [PATCH v2 04/16] drm/i915: Do .crtc_compute_clock() earlier

[Ville Syrjala]

From: Ville Syrjälä 

Currently we calculate a lot of things (pixel rate, watermarks,
cdclk) trusting that the DPLL can generate the exact frequency
we ask it. In practice that is not true and there can be
certain amount of rounding involved.

To allow us to eventually get accurate numbers for all our
DPLL clock derived state we need to move the DPLL calculation
to hapen much earlier. To that end we hoist it up to the just
after the fastset checks. For now we just do the easy code
motion, and the actual back feeding of the final DPLL clock
into the state will come later.

A slight change here is that now .crtc_compute_clock()
can get called while the shared_dpll is still assigned.
But since .crtc_compute_clock() no longer assignes new
shared_dplls this is perfectly fine.

TODO: I'd actually like to do this before the fastset check
so that if the DPLL state should change we actually do the
modeset. Which I think is what the video aficionados want,
but it might not be what the fans of fastboot want. Not yet
sure how to reconcile those conflicting requirements...

v2: s/return/goto/ in error handling

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 9 +
 drivers/gpu/drm/i915/display/intel_dpll.c| 3 ---
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 5559688047b3..b8c0ede1f7fd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4900,10 +4900,6 @@ static int intel_crtc_atomic_check(struct 
intel_atomic_state *state,
crtc_state->update_wm_post = true;
 
if (mode_changed) {
-   ret = intel_dpll_crtc_compute_clock(state, crtc);
-   if (ret)
-   return ret;
-
ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
if (ret)
return ret;
@@ -7047,6 +7043,11 @@ static int intel_atomic_check(struct drm_device *dev,
new_crtc_state, i) {
if (intel_crtc_needs_modeset(new_crtc_state)) {
any_ms = true;
+
+   ret = intel_dpll_crtc_compute_clock(state, crtc);
+   if (ret)
+   goto fail;
+
continue;
}
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 5262f16b45ac..8d095f28fa20 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1411,9 +1411,6 @@ int intel_dpll_crtc_compute_clock(struct 
intel_atomic_state *state,
 
drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
 
-   if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
-   return 0;
-
memset(&crtc_state->dpll_hw_state, 0,
   sizeof(crtc_state->dpll_hw_state));
 
-- 
2.35.1

[Intel-gfx] [PATCH v2 00/16] drm/i915: Make fastset not suck and allow seamless M/N changes

[Ville Syrjala]

From: Ville Syrjälä 

And with fastset made to not suck we can consider allowing
seameless M/N changes on eDP panels that support such things.
I've given that a quick test here on a TGL and it seemed to work
OK.

The rough parts:
- The DPLL stuff is kinda messy still, a lot of which is due to
  the dpll_mgr vs. not depending on platform/output type. Maybe
  it's finally time to start cleaning that mess up...
- the port_dpll[] stuff probably needs to be reworked at some
  point to make a bit more sense
- fastboot I *think* should mostly keep working now that we
  try to match the GOP/VBIOS M/N behaviour. FDI M/N vs. DPLL is
  a bit of a challenge for the platforms where the encoder live
  in the PCH, but I'm going to declare that as not so important
- DSI clock handling is snafu
- DP link computation policy might need a bit more work since we
  may now consume more bandwidth than before on machines where
  seamless M/N changes are possible

I also did a quick smoke test through the series on tgl and 
snb in the hopes of keeping this at least mostly bisectable.

Changes in v2:
- bunch of stuff already merged
- a bit more refactoring to make things nicer
- Tweak the M/N rounding for fastboot
- don't mess with the DP link rate on platforms (pre-BDW)
  where we haven't implemented seamsless M/N chages

Ville Syrjälä (16):
  drm/i915: Relocate intel_crtc_dotclock()
  drm/i915: Shuffle some PLL code around
  drm/i915: Extract has_double_buffered_m_n()
  drm/i915: Do .crtc_compute_clock() earlier
  drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
  drm/i915: Feed the DPLL output freq back into crtc_state
  drm/i915: Compute clocks earlier
  drm/i915: Make M/N checks non-fuzzy
  drm/i915: Make all clock checks non-fuzzy
  drm/i915: Set active dpll early for icl+
  drm/i915: Nuke fastet state copy hacks
  drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not
enabled
  drm/i915: Add intel_panel_highest_mode()
  drm/i915: Allow M/N change during fastset on bdw+
  drm/i915: Use a fixed N value always
  drm/i915: Round TMDS clock to nearest

 drivers/gpu/drm/i915/display/intel_crt.c  |   3 +
 drivers/gpu/drm/i915/display/intel_ddi.c  |  22 --
 drivers/gpu/drm/i915/display/intel_display.c  | 204 +++---
 drivers/gpu/drm/i915/display/intel_display.h  |   3 +-
 .../drm/i915/display/intel_display_types.h|   1 +
 drivers/gpu/drm/i915/display/intel_dp.c   |  50 +++--
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   3 +-
 drivers/gpu/drm/i915/display/intel_dpll.c |  69 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 204 ++
 drivers/gpu/drm/i915/display/intel_fdi.c  |   2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c |   2 +-
 .../drm/i915/display/intel_modeset_verify.c   |   6 +-
 drivers/gpu/drm/i915/display/intel_panel.c|  15 ++
 drivers/gpu/drm/i915/display/intel_panel.h|   3 +
 .../gpu/drm/i915/display/intel_pch_refclk.c   |  10 +
 .../gpu/drm/i915/display/intel_pch_refclk.h   |   1 +
 16 files changed, 333 insertions(+), 265 deletions(-)

-- 
2.35.1

Re: [Intel-gfx] [PATCH v3] drm/i915/bios: calculate panel type as per child device index in VBT

[Jani Nikula]

On Fri, 17 Jun 2022, Animesh Manna  wrote:
> Each LFP may have different panel type which is stored in LFP data
> data block. Based on the child device index respective panel-type/
> panel-type2 field will be used.
>
> v1: Initial rfc verion.
> v2: Based on review comments from Jani,
> - Used panel-type instead addition panel-index variable.
> - DEVICE_HANDLE_* name changed and placed before DEVICE_TYPE_*
> macro.
> v3:
> - Passing intel_bios_encoder_data as argument of
> intel_bios_init_panel(). Passing NULL to indicate encoder is not
> initialized yet for dsi as current focus is to enable dual EDP. [Jani]
>
> Signed-off-by: Animesh Manna 
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c|  2 +-
>  drivers/gpu/drm/i915/display/intel_bios.c | 16 ++--
>  drivers/gpu/drm/i915/display/intel_bios.h |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c   |  4 +++-
>  drivers/gpu/drm/i915/display/intel_lvds.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_sdvo.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  4 
>  drivers/gpu/drm/i915/display/vlv_dsi.c|  2 +-
>  8 files changed, 26 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 3b5305c219ba..5dcfa7feffa9 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -2050,7 +2050,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
>   /* attach connector to encoder */
>   intel_connector_attach_encoder(intel_connector, encoder);
>  
> - intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL);
> + intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL, NULL);
>  
>   mutex_lock(&dev->mode_config.mutex);
>   intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 76e86358adb9..e97f1f979a48 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -604,12 +604,14 @@ get_lfp_data_tail(const struct bdb_lvds_lfp_data *data,
>  }
>  
>  static int opregion_get_panel_type(struct drm_i915_private *i915,
> +const struct intel_bios_encoder_data 
> *devdata,
>  const struct edid *edid)
>  {
>   return intel_opregion_get_panel_type(i915);
>  }
>  
>  static int vbt_get_panel_type(struct drm_i915_private *i915,
> +   const struct intel_bios_encoder_data *devdata,
> const struct edid *edid)
>  {
>   const struct bdb_lvds_options *lvds_options;
> @@ -625,10 +627,16 @@ static int vbt_get_panel_type(struct drm_i915_private 
> *i915,
>   return -1;
>   }
>  
> + if (devdata && devdata->child.handle == DEVICE_HANDLE_LFP2)
> + return lvds_options->panel_type2;
> +
> + drm_WARN_ON(&i915->drm, devdata && devdata->child.handle != 
> DEVICE_HANDLE_LFP1);
> +
>   return lvds_options->panel_type;
>  }
>  
>  static int pnpid_get_panel_type(struct drm_i915_private *i915,
> + const struct intel_bios_encoder_data *devdata,
>   const struct edid *edid)
>  {
>   const struct bdb_lvds_lfp_data *data;
> @@ -675,6 +683,7 @@ static int pnpid_get_panel_type(struct drm_i915_private 
> *i915,
>  }
>  
>  static int fallback_get_panel_type(struct drm_i915_private *i915,
> +const struct intel_bios_encoder_data 
> *devdata,
>  const struct edid *edid)
>  {
>   return 0;
> @@ -688,11 +697,13 @@ enum panel_type {
>  };
>  
>  static int get_panel_type(struct drm_i915_private *i915,
> +   const struct intel_bios_encoder_data *devdata,
> const struct edid *edid)
>  {
>   struct {
>   const char *name;
>   int (*get_panel_type)(struct drm_i915_private *i915,
> +   const struct intel_bios_encoder_data 
> *devdata,
> const struct edid *edid);
>   int panel_type;
>   } panel_types[] = {
> @@ -716,7 +727,7 @@ static int get_panel_type(struct drm_i915_private *i915,
>   int i;
>  
>   for (i = 0; i < ARRAY_SIZE(panel_types); i++) {
> - panel_types[i].panel_type = panel_types[i].get_panel_type(i915, 
> edid);
> + panel_types[i].panel_type = panel_types[i].get_panel_type(i915, 
> devdata, edid);
>  
>   drm_WARN_ON(&i915->drm, panel_types[i].panel_type > 0xf &&
>   panel_types[i].panel_type != 0xff);
> @@ -3127,11 +3138,12 @@ void intel_bios_init(struct drm_i915_private *i915)
>  
>  void intel_bios_init_panel(struct drm_i915_private *i915,
>  struct intel_panel *panel,
> + 

[Intel-gfx] [PATCH] drm/i915: Implement a bit of bw_state readout

[Ville Syrjala]

From: Ville Syrjälä 

We currently fail to reconstruct the bw related cdclk limits
during readout, which triggers a  cdclk reclaculation during
fastboot, which is then likely forces a full modeset anyway.
Reconstruct some of the missing state so that we can skip
the cdclk recomputation and thus have a higher chance for
flicker free boot.

Cc: Stanislav Lisovskiy 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_bw.c  | 9 ++---
 drivers/gpu/drm/i915/display/intel_display.c | 7 +--
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index 79269d2c476b..30ffec63f9a3 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -627,11 +627,14 @@ void intel_bw_crtc_update(struct intel_bw_state *bw_state,
intel_bw_crtc_data_rate(crtc_state);
bw_state->num_active_planes[crtc->pipe] =
intel_bw_crtc_num_active_planes(crtc_state);
+   bw_state->min_cdclk[crtc->pipe] =
+   intel_bw_crtc_min_cdclk(crtc_state);
 
-   drm_dbg_kms(&i915->drm, "pipe %c data rate %u num active planes %u\n",
-   pipe_name(crtc->pipe),
+   drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] data rate %u num active planes %u 
min cdclk %d kHz\n",
+   crtc->base.base.id, crtc->base.name,
bw_state->data_rate[crtc->pipe],
-   bw_state->num_active_planes[crtc->pipe]);
+   bw_state->num_active_planes[crtc->pipe],
+   bw_state->min_cdclk[crtc->pipe]);
 }
 
 static unsigned int intel_bw_num_active_planes(struct drm_i915_private 
*dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 90bd26431e31..b17b9493c68f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2498,6 +2498,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc 
*crtc,
 
bw_state->data_rate[pipe] = 0;
bw_state->num_active_planes[pipe] = 0;
+   bw_state->min_cdclk[pipe] = 0;
 }
 
 /*
@@ -9310,6 +9311,8 @@ static void intel_modeset_readout_hw_state(struct 
drm_device *dev)
to_intel_cdclk_state(dev_priv->cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(dev_priv->dbuf.obj.state);
+   struct intel_bw_state *bw_state =
+   to_intel_bw_state(dev_priv->bw_obj.state);
enum pipe pipe;
struct intel_crtc *crtc;
struct intel_encoder *encoder;
@@ -9425,8 +9428,6 @@ static void intel_modeset_readout_hw_state(struct 
drm_device *dev)
drm_connector_list_iter_end(&conn_iter);
 
for_each_intel_crtc(dev, crtc) {
-   struct intel_bw_state *bw_state =
-   to_intel_bw_state(dev_priv->bw_obj.state);
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_plane *plane;
@@ -9490,6 +9491,8 @@ static void intel_modeset_readout_hw_state(struct 
drm_device *dev)
 
intel_bw_crtc_update(bw_state, crtc_state);
}
+
+   cdclk_state->bw_min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state);
 }
 
 static void
-- 
2.35.1

[Intel-gfx] [PATCH v2 07/16] drm/i915: Compute clocks earlier

[Ville Syrjala]

From: Ville Syrjälä 

Do the DPLL computation before fastset checks. This should
allow us to get rid of all that horrible fuzzy clock handling
for fastsets. Who knows how many bugs there are caused by our
state not actually matching what the hardware will generate.

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 59dd66642c5f..ef7454c5b947 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2782,6 +2782,10 @@ static int intel_crtc_compute_config(struct 
intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
int ret;
 
+   ret = intel_dpll_crtc_compute_clock(state, crtc);
+   if (ret)
+   return ret;
+
ret = intel_crtc_compute_pipe_src(crtc_state);
if (ret)
return ret;
@@ -7030,10 +7034,6 @@ static int intel_atomic_check(struct drm_device *dev,
if (intel_crtc_needs_modeset(new_crtc_state)) {
any_ms = true;
 
-   ret = intel_dpll_crtc_compute_clock(state, crtc);
-   if (ret)
-   goto fail;
-
intel_release_shared_dplls(state, crtc);
continue;
}
-- 
2.35.1

[Intel-gfx] [PATCH v2 06/16] drm/i915: Feed the DPLL output freq back into crtc_state

[Ville Syrjala]

From: Ville Syrjälä 

Fill port_clock and hw.adjusted_mode.crtc_clock with the actual
frequency we're going to be getting from the hardware. This will
let us accurately compute all derived state that depends on those.

v2: Reintroduce iCLKIP WARN

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_crt.c  |  3 +
 drivers/gpu/drm/i915/display/intel_dpll.c | 60 ++-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++-
 .../gpu/drm/i915/display/intel_pch_refclk.c   | 10 
 .../gpu/drm/i915/display/intel_pch_refclk.h   |  1 +
 5 files changed, 94 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c 
b/drivers/gpu/drm/i915/display/intel_crt.c
index 6a3893c8ff22..a225af030ad7 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -46,6 +46,7 @@
 #include "intel_gmbus.h"
 #include "intel_hotplug.h"
 #include "intel_pch_display.h"
+#include "intel_pch_refclk.h"
 
 /* Here's the desired hotplug mode */
 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |   \
@@ -444,6 +445,8 @@ static int hsw_crt_compute_config(struct intel_encoder 
*encoder,
/* FDI must always be 2.7 GHz */
pipe_config->port_clock = 135000 * 2;
 
+   adjusted_mode->crtc_clock = lpt_iclkip(pipe_config);
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 69dc018385db..cffce8b86d64 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -938,12 +938,25 @@ static int hsw_crtc_compute_clock(struct 
intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder =
intel_get_crtc_new_encoder(state, crtc_state);
+   int ret;
 
if (DISPLAY_VER(dev_priv) < 11 &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
 
-   return intel_compute_shared_dplls(state, crtc, encoder);
+   ret = intel_compute_shared_dplls(state, crtc, encoder);
+   if (ret)
+   return ret;
+
+   /* FIXME this is a mess */
+   if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+   return 0;
+
+   /* CRT dotclock is determined via other means */
+   if (!crtc_state->has_pch_encoder)
+   crtc_state->hw.adjusted_mode.crtc_clock = 
intel_crtc_dotclock(crtc_state);
+
+   return 0;
 }
 
 static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
@@ -969,8 +982,15 @@ static int dg2_crtc_compute_clock(struct 
intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder =
intel_get_crtc_new_encoder(state, crtc_state);
+   int ret;
 
-   return intel_mpllb_calc_state(crtc_state, encoder);
+   ret = intel_mpllb_calc_state(crtc_state, encoder);
+   if (ret)
+   return ret;
+
+   crtc_state->hw.adjusted_mode.crtc_clock = 
intel_crtc_dotclock(crtc_state);
+
+   return 0;
 }
 
 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
@@ -1096,6 +1116,7 @@ static int ilk_crtc_compute_clock(struct 
intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit;
int refclk = 12;
+   int ret;
 
/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
if (!crtc_state->has_pch_encoder)
@@ -1132,7 +1153,14 @@ static int ilk_crtc_compute_clock(struct 
intel_atomic_state *state,
ilk_compute_dpll(crtc_state, &crtc_state->dpll,
 &crtc_state->dpll);
 
-   return intel_compute_shared_dplls(state, crtc, NULL);
+   ret = intel_compute_shared_dplls(state, crtc, NULL);
+   if (ret)
+   return ret;
+
+   crtc_state->port_clock = crtc_state->dpll.dot;
+   crtc_state->hw.adjusted_mode.crtc_clock = 
intel_crtc_dotclock(crtc_state);
+
+   return ret;
 }
 
 static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
@@ -1198,6 +1226,13 @@ static int chv_crtc_compute_clock(struct 
intel_atomic_state *state,
 
chv_compute_dpll(crtc_state);
 
+   /* FIXME this is a mess */
+   if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+   return 0;
+
+   crtc_state->port_clock = crtc_state->dpll.dot;
+   crtc_state->hw.adjusted_mode.crtc_clock = 
intel_crtc_dotclock(crtc_state);
+
return 0;
 }
 
@@ -1217,6 +1252,13 @@ static int vlv_crtc_compute_clock(struct 
intel_atomic_state *state,
 
vlv_compute_dpll(crtc_state);
 
+   /* FIXME this is a mess */
+   if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+   return 0;
+
+   crtc_state->port_clock = crtc_state->dpll.dot;
+   crtc_state->hw.adjusted_mode.cr

Re: [Intel-gfx] [PATCH 1/2] iosys-map: Add per-word read

[Lucas De Marchi]

On Fri, Jun 17, 2022 at 01:52:03AM -0700, Lucas De Marchi wrote:

Instead of always falling back to memcpy_fromio() for any size, prefer
using read{b,w,l}(). When reading struct members it's common to read
individual integer variables individually. Going through memcpy_fromio()
for each of them poses a high penalty.

Employ a similar trick as __seqprop() by using _Generic() to generate
only the specific call based on a type-compatible variable.

For a pariticular i915 workload producing GPU context switches,
__get_engine_usage_record() is particularly hot since the engine usage
is read from device local memory with dgfx, possibly multiple times
since it's racy. Test execution time for this test shows a ~12.5%
improvement with DG2:

Before:
nrepeats = 1000; min = 7.63243e+06; max = 1.01817e+07;
median = 9.52548e+06; var = 526149;
After:
nrepeats = 1000; min = 7.03402e+06; max = 8.8832e+06;
median = 8.33955e+06; var = 333113;

Other things attempted that didn't prove very useful:
1) Change the _Generic() on x86 to just dereference the memory address
2) Change __get_engine_usage_record() to do just 1 read per loop,
  comparing with the previous value read
3) Change __get_engine_usage_record() to access the fields directly as it
  was before the conversion to iosys-map

(3) did gave a small improvement (~3%), but doesn't seem to scale well
to other similar cases in the driver.

Additional test by Chris Wilson using gem_create from igt with some
changes to track object creation time. This happens to accidentally
stress this code path:

Pre iosys_map conversion of engine busyness:
lmem0: Creating262144 4KiB objects took 59274.2ms

Unpatched:
lmem0: Creating262144 4KiB objects took 108830.2ms

With readl (this patch):
lmem0: Creating262144 4KiB objects took 61348.6ms

s/readl/READ_ONCE/
lmem0: Creating262144 4KiB objects took 61333.2ms

So we do take a little bit more time than before the conversion, but
that is due to other factors: bringing the READ_ONCE back would be as
good as just doing this conversion.

v2:
- Remove default from _Generic() - callers wanting to read more
 than u64 should use iosys_map_memcpy_from()
- Add READ_ONCE() cases dereferencing the pointer when using system
 memory

Signed-off-by: Lucas De Marchi 
Reviewed-by: Christian König  # v1
---
include/linux/iosys-map.h | 45 +++
1 file changed, 36 insertions(+), 9 deletions(-)

diff --git a/include/linux/iosys-map.h b/include/linux/iosys-map.h
index 4b8406ee8bc4..f59dd00ed202 100644
--- a/include/linux/iosys-map.h
+++ b/include/linux/iosys-map.h
@@ -6,6 +6,7 @@
#ifndef __IOSYS_MAP_H__
#define __IOSYS_MAP_H__

+#include 
#include 
#include 

@@ -333,6 +334,26 @@ static inline void iosys_map_memset(struct iosys_map *dst, 
size_t offset,
memset(dst->vaddr + offset, value, len);
}

+#ifdef CONFIG_64BIT
+#define __iosys_map_rd_io_u64_case(val_, vaddr_iomem_) 
\
+   u64: val_ = readq(vaddr_iomem_)
+#else
+#define __iosys_map_rd_io_u64_case(val_, vaddr_iomem_) 
\
+   u64: memcpy_fromio(&(val_), vaddr_iomem__, sizeof(u64))


I tested io/sys and forgot again to test it for 32-bit :(. This
should fix the build for 32-bits:

diff --git a/include/linux/iosys-map.h b/include/linux/iosys-map.h
index 580e14cd360c..f8bc052f8975 100644
--- a/include/linux/iosys-map.h
+++ b/include/linux/iosys-map.h
@@ -341,7 +341,7 @@ static inline void iosys_map_memset(struct iosys_map *dst, 
size_t offset,
u64: writeq(val_, vaddr_iomem_)
 #else
 #define __iosys_map_rd_io_u64_case(val_, vaddr_iomem_) 
\
-   u64: memcpy_fromio(&(val_), vaddr_iomem__, sizeof(u64))
+   u64: memcpy_fromio(&(val_), vaddr_iomem_, sizeof(u64))
 #define __iosys_map_wr_io_u64_case(val_, vaddr_iomem_) \
u64: memcpy_toio(vaddr_iomem_, &(val_), sizeof(u64))
 #endif

Lucas De Marchi

[Intel-gfx] [PATCH v2 03/16] drm/i915: Extract has_double_buffered_m_n()

[Ville Syrjala]

From: Ville Syrjälä 

We have a couple of places that want to make distinction between
double buffered M/N registers vs. the split M1/N1+M2/N2 registers.
Add a helper for that.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 7 ++-
 drivers/gpu/drm/i915/display/intel_display.h | 1 +
 drivers/gpu/drm/i915/display/intel_dp.c  | 3 +--
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index b24784c4522d..5559688047b3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2798,6 +2798,11 @@ static int intel_crtc_compute_config(struct 
intel_atomic_state *state,
return 0;
 }
 
+bool has_double_buffered_m_n(struct drm_i915_private *i915)
+{
+   return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915);
+}
+
 static void
 intel_reduce_m_n_ratio(u32 *num, u32 *den)
 {
@@ -5900,7 +5905,7 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
PIPE_CONF_CHECK_I(lane_count);
PIPE_CONF_CHECK_X(lane_lat_optim_mask);
 
-   if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
+   if (has_double_buffered_m_n(dev_priv)) {
PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
} else {
PIPE_CONF_CHECK_M_N(dp_m_n);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h 
b/drivers/gpu/drm/i915/display/intel_display.h
index 2feb8ae5d5d4..44c88aadfc30 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -543,6 +543,7 @@ int intel_atomic_add_affected_planes(struct 
intel_atomic_state *state,
 struct intel_crtc *crtc);
 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
   u8 active_pipes);
+bool has_double_buffered_m_n(struct drm_i915_private *i915);
 void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2fac76bcf06d..75645508080a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1842,8 +1842,7 @@ intel_dp_compute_hdr_metadata_infoframe_sdp(struct 
intel_dp *intel_dp,
 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
enum transcoder cpu_transcoder)
 {
-   /* M1/N1 is double buffered */
-   if (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
+   if (has_double_buffered_m_n(i915))
return true;
 
return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
-- 
2.35.1

Re: [Intel-gfx] [PATCH v2 8/9] drm/i915/xehpsdv: Store lmem region in gt

[Andi Shyti]

Hi,

On Thu, Jun 16, 2022 at 05:31:05PM +0530, Anshuman Gupta wrote:
> From: Tvrtko Ursulin 
> 
> Store a pointer to respective local memory region in intel_gt so it can be
> used when memory local to a GT needs to be allocated.
> 
> Cc: Andi Shyti 
> Signed-off-by: Tvrtko Ursulin 
> Signed-off-by: Anshuman Gupta 
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c   | 1 +
>  drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index f33290358c51..7a535f670ae1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -91,6 +91,7 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
>   GEM_BUG_ON(!HAS_REGION(i915, id));
>   GEM_BUG_ON(i915->mm.regions[id]);
>   i915->mm.regions[id] = mem;
> + gt->lmem = mem;
>  
>   return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index df708802889d..cd7744eaaeaa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -23,6 +23,7 @@
>  #include "intel_gt_buffer_pool_types.h"
>  #include "intel_hwconfig.h"
>  #include "intel_llc_types.h"
> +#include "intel_memory_region.h"
>  #include "intel_reset_types.h"
>  #include "intel_rc6_types.h"
>  #include "intel_rps_types.h"
> @@ -202,6 +203,8 @@ struct intel_gt {
>*/
>   phys_addr_t phys_addr;
>  
> + struct intel_memory_region *lmem;
> +

this was somewhere in my next patch that is getting very
delayed... anyway, with Jani's include note:

Reviewed-by: Andi Shyti 

Thanks,
Andi

>   struct intel_gt_info {
>   unsigned int id;
>  
> -- 
> 2.26.2

[Intel-gfx] [PATCH v4] drm/i915: Improve on suspend / resume time with VT-d enabled

[Thomas Hellström]

When DMAR / VT-d is enabled, the display engine uses overfetching,
presumably to deal with the increased latency. To avoid display engine
errors and DMAR faults, as a workaround the GGTT is populated with scatch
PTEs when VT-d is enabled. However starting with gen10, Write-combined
writing of scratch PTES is no longer possible and as a result, populating
the full GGTT with scratch PTEs like on resume becomes very slow as
uncached access is needed.

Therefore, on integrated GPUs utilize the fact that the PTEs are stored in
stolen memory which retain content across S3 suspend. Don't clear the PTEs
on suspend and resume. This improves on resume time with around 100 ms.
While 100+ms might appear like a short time it's 10% to 20% of total resume
time and important in some applications.

One notable exception is Intel Rapid Start Technology which may cause
stolen memory to be lost across what the OS percieves as S3 suspend.
If IRST is enabled or if we can't detect whether IRST is enabled, retain
the old workaround, clearing and re-instating PTEs.

As an additional measure, if we detect that the last ggtt pte was lost
during suspend, print a warning and re-populate the GGTT ptes

On discrete GPUs, the display engine scans out from LMEM which isn't
subject to DMAR, and presumably the workaround is therefore not needed,
but that needs to be verified and disabling the workaround for dGPU,
if possible, will be deferred to a follow-up patch.

v2:
- Rely on retained ptes to also speed up suspend and resume re-binding.
- Re-build GGTT ptes if Intel rst is enabled.
v3:
- Re-build GGTT ptes also if we can't detect whether Intel rst is enabled,
  and if the guard page PTE and end of GGTT was lost.
v4:
- Fix some kerneldoc issues (Matthew Auld), rebase.

Signed-off-by: Thomas Hellström 
Acked-by: Daniel Vetter 
Reviewed-by: Matthew Auld 
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c | 56 +---
 drivers/gpu/drm/i915/gt/intel_gtt.h  | 24 
 drivers/gpu/drm/i915/i915_driver.c   | 16 
 3 files changed, 90 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index e6b2eb122ad7..0849a6f66309 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -22,6 +22,13 @@
 #include "intel_gtt.h"
 #include "gen8_ppgtt.h"
 
+static inline bool suspend_retains_ptes(struct i915_address_space *vm)
+{
+   return GRAPHICS_VER(vm->i915) >= 8 &&
+   !HAS_LMEM(vm->i915) &&
+   vm->is_ggtt;
+}
+
 static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
   unsigned long color,
   u64 *start,
@@ -93,6 +100,23 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
return 0;
 }
 
+/*
+ * Return the value of the last GGTT pte cast to an u64, if
+ * the system is supposed to retain ptes across resume. 0 otherwise.
+ */
+static u64 read_last_pte(struct i915_address_space *vm)
+{
+   struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+   gen8_pte_t __iomem *ptep;
+
+   if (!suspend_retains_ptes(vm))
+   return 0;
+
+   GEM_BUG_ON(GRAPHICS_VER(vm->i915) < 8);
+   ptep = (typeof(ptep))ggtt->gsm + (ggtt_total_entries(ggtt) - 1);
+   return readq(ptep);
+}
+
 /**
  * i915_ggtt_suspend_vm - Suspend the memory mappings for a GGTT or DPT VM
  * @vm: The VM to suspend the mappings for
@@ -156,7 +180,10 @@ void i915_ggtt_suspend_vm(struct i915_address_space *vm)
i915_gem_object_unlock(obj);
}
 
-   vm->clear_range(vm, 0, vm->total);
+   if (!suspend_retains_ptes(vm))
+   vm->clear_range(vm, 0, vm->total);
+   else
+   i915_vm_to_ggtt(vm)->probed_pte = read_last_pte(vm);
 
vm->skip_pte_rewrite = save_skip_rewrite;
 
@@ -299,6 +326,8 @@ static int init_ggtt(struct i915_ggtt *ggtt)
struct drm_mm_node *entry;
int ret;
 
+   ggtt->pte_lost = true;
+
/*
 * GuC requires all resources that we're sharing with it to be placed in
 * non-WOPCM memory. If GuC is not present or not in use we still need a
@@ -675,11 +704,20 @@ bool i915_ggtt_resume_vm(struct i915_address_space *vm)
 {
struct i915_vma *vma;
bool write_domain_objs = false;
+   bool retained_ptes;
 
drm_WARN_ON(&vm->i915->drm, !vm->is_ggtt && !vm->is_dpt);
 
-   /* First fill our portion of the GTT with scratch pages */
-   vm->clear_range(vm, 0, vm->total);
+   /*
+* First fill our portion of the GTT with scratch pages if
+* they were not retained across suspend.
+*/
+   retained_ptes = suspend_retains_ptes(vm) &&
+   !i915_vm_to_ggtt(vm)->pte_lost &&
+   !GEM_WARN_ON(i915_vm_to_ggtt(vm)->probed_pte != 
read_last_pte(vm));
+
+   if (!retained_ptes)
+   vm->clear_range(vm, 0, vm->total);
 
/* clflush objects bou

Re: [Intel-gfx] [PATCH] drm/i915: Fix a lockdep warning at error capture

[Das, Nirmoy]

Missed the fdo issue ref:

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5595

On 6/17/2022 1:55 PM, Nirmoy Das wrote:

For some platfroms we use stop_machine version of
gen8_ggtt_insert_page/gen8_ggtt_insert_entries to avoid a
concurrent GGTT access bug but this causes a circular locking
dependency warning:

   Possible unsafe locking scenario:
 CPU0CPU1
 
lock(&ggtt->error_mutex);
 lock(dma_fence_map);
 lock(&ggtt->error_mutex);
lock(cpu_hotplug_lock);

Fix this by calling gen8_ggtt_insert_page/gen8_ggtt_insert_entries
directly at error capture which is concurrent GGTT access safe because
reset path make sure of that.

Suggested-by: Chris Wilson 
Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/i915/gt/intel_gt_gmch.c  | 2 ++
  drivers/gpu/drm/i915/gt/intel_gtt.h  | 9 +
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 5 -
  drivers/gpu/drm/i915/i915_gpu_error.c| 8 ++--
  4 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_gmch.c 
b/drivers/gpu/drm/i915/gt/intel_gt_gmch.c
index 18e488672d1b..2260ed576776 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_gmch.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_gmch.c
@@ -629,6 +629,8 @@ int intel_gt_gmch_gen8_probe(struct i915_ggtt *ggtt)
if (intel_vm_no_concurrent_access_wa(i915)) {
ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
ggtt->vm.insert_page= bxt_vtd_ggtt_insert_page__BKL;
+   ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;
+   ggtt->vm.raw_insert_entries = gen8_ggtt_insert_entries;
ggtt->vm.bind_async_flags =
I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h 
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index a40d928b3888..f9a1f3d17272 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -306,6 +306,15 @@ struct i915_address_space {
   struct i915_vma_resource *vma_res,
   enum i915_cache_level cache_level,
   u32 flags);
+   void (*raw_insert_page)(struct i915_address_space *vm,
+   dma_addr_t addr,
+   u64 offset,
+   enum i915_cache_level cache_level,
+   u32 flags);
+   void (*raw_insert_entries)(struct i915_address_space *vm,
+  struct i915_vma_resource *vma_res,
+  enum i915_cache_level cache_level,
+  u32 flags);
void (*cleanup)(struct i915_address_space *vm);
  
  	void (*foreach)(struct i915_address_space *vm,

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index d2c5c9367cc4..c06e83872c34 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -493,7 +493,10 @@ static void uc_fw_bind_ggtt(struct intel_uc_fw *uc_fw)
if (i915_gem_object_is_lmem(obj))
pte_flags |= PTE_LM;
  
-	ggtt->vm.insert_entries(&ggtt->vm, dummy, I915_CACHE_NONE, pte_flags);

+   if (ggtt->vm.raw_insert_entries)
+   ggtt->vm.raw_insert_entries(&ggtt->vm, dummy, I915_CACHE_NONE, 
pte_flags);
+   else
+   ggtt->vm.insert_entries(&ggtt->vm, dummy, I915_CACHE_NONE, 
pte_flags);
  }
  
  static void uc_fw_unbind_ggtt(struct intel_uc_fw *uc_fw)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index bff8a111424a..f9b1969ed7ed 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1104,8 +1104,12 @@ i915_vma_coredump_create(const struct intel_gt *gt,
  
  		for_each_sgt_daddr(dma, iter, vma_res->bi.pages) {

mutex_lock(&ggtt->error_mutex);
-   ggtt->vm.insert_page(&ggtt->vm, dma, slot,
-I915_CACHE_NONE, 0);
+   if (ggtt->vm.raw_insert_page)
+   ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot,
+I915_CACHE_NONE, 0);
+   else
+   ggtt->vm.insert_page(&ggtt->vm, dma, slot,
+I915_CACHE_NONE, 0);
mb();
  
  			s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);

[Intel-gfx] [PATCH v2 13/16] drm/i915: Add intel_panel_highest_mode()

[Ville Syrjala]

From: Ville Syrjälä 

Add a function to get the fixed_mode with the highest clock.
The plan is to use this for the link bw calculation on seamless
DRRS panels so that we alwasy end up with the same link params
regardless of the requested refresh rate. This will allow fastset
to do seamless refresh rate changes based on userspace request
instead of having to go for a full modeset.

TODO: the function name isn't great

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_panel.c | 15 +++
 drivers/gpu/drm/i915/display/intel_panel.h |  3 +++
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_panel.c 
b/drivers/gpu/drm/i915/display/intel_panel.c
index 237a40623dd7..c738de27e49b 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -114,6 +114,21 @@ intel_panel_downclock_mode(struct intel_connector 
*connector,
return best_mode;
 }
 
+const struct drm_display_mode *
+intel_panel_highest_mode(struct intel_connector *connector,
+const struct drm_display_mode *adjusted_mode)
+{
+   const struct drm_display_mode *fixed_mode, *best_mode = adjusted_mode;
+
+   /* pick the fixed_mode that has the highest clock */
+   list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) {
+   if (fixed_mode->clock > best_mode->clock)
+   best_mode = fixed_mode;
+   }
+
+   return best_mode;
+}
+
 int intel_panel_get_modes(struct intel_connector *connector)
 {
const struct drm_display_mode *fixed_mode;
diff --git a/drivers/gpu/drm/i915/display/intel_panel.h 
b/drivers/gpu/drm/i915/display/intel_panel.h
index b087c0c3cc6d..eff3ffd3d082 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.h
+++ b/drivers/gpu/drm/i915/display/intel_panel.h
@@ -31,6 +31,9 @@ intel_panel_fixed_mode(struct intel_connector *connector,
 const struct drm_display_mode *
 intel_panel_downclock_mode(struct intel_connector *connector,
   const struct drm_display_mode *adjusted_mode);
+const struct drm_display_mode *
+intel_panel_highest_mode(struct intel_connector *connector,
+const struct drm_display_mode *adjusted_mode);
 int intel_panel_get_modes(struct intel_connector *connector);
 enum drrs_type intel_panel_drrs_type(struct intel_connector *connector);
 enum drm_mode_status
-- 
2.35.1

[Intel-gfx] [PATCH v2 15/16] drm/i915: Use a fixed N value always

[Ville Syrjala]

From: Ville Syrjälä 

Windows/BIOS always uses fixed N values. Let's match that
behaviour.

Allows us to also get rid of that constant_n quirk stuff.

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 36 +---
 drivers/gpu/drm/i915/display/intel_display.h |  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c  | 10 +++---
 drivers/gpu/drm/i915/display/intel_dp_mst.c  |  3 +-
 drivers/gpu/drm/i915/display/intel_fdi.c |  2 +-
 5 files changed, 24 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 4e33ce635112..7e45dd99d03c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2817,19 +2817,11 @@ intel_reduce_m_n_ratio(u32 *num, u32 *den)
}
 }
 
-static void compute_m_n(unsigned int m, unsigned int n,
-   u32 *ret_m, u32 *ret_n,
-   bool constant_n)
+static void compute_m_n(u32 *ret_m, u32 *ret_n,
+   u32 m, u32 n, u32 constant_n)
 {
-   /*
-* Several DP dongles in particular seem to be fussy about
-* too large link M/N values. Give N value as 0x8000 that
-* should be acceptable by specific devices. 0x8000 is the
-* specified fixed N value for asynchronous clock mode,
-* which the devices expect also in synchronous clock mode.
-*/
if (constant_n)
-   *ret_n = DP_LINK_CONSTANT_N_VALUE;
+   *ret_n = constant_n;
else
*ret_n = min_t(unsigned int, roundup_pow_of_two(n), 
DATA_LINK_N_MAX);
 
@@ -2841,22 +2833,28 @@ void
 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
   int pixel_clock, int link_clock,
   struct intel_link_m_n *m_n,
-  bool constant_n, bool fec_enable)
+  bool fec_enable)
 {
u32 data_clock = bits_per_pixel * pixel_clock;
 
if (fec_enable)
data_clock = intel_dp_mode_to_fec_clock(data_clock);
 
+   /*
+* Windows/BIOS uses fixed M/N values always. Follow suit.
+*
+* Also several DP dongles in particular seem to be fussy
+* about too large link M/N values. Presumably the 20bit
+* value used by Windows/BIOS is acceptable to everyone.
+*/
m_n->tu = 64;
-   compute_m_n(data_clock,
-   link_clock * nlanes * 8,
-   &m_n->data_m, &m_n->data_n,
-   constant_n);
+   compute_m_n(&m_n->data_m, &m_n->data_n,
+   data_clock, link_clock * nlanes * 8,
+   0x800);
 
-   compute_m_n(pixel_clock, link_clock,
-   &m_n->link_m, &m_n->link_n,
-   constant_n);
+   compute_m_n(&m_n->link_m, &m_n->link_n,
+   pixel_clock, link_clock,
+   0x8);
 }
 
 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h 
b/drivers/gpu/drm/i915/display/intel_display.h
index 44c88aadfc30..ee02fe4d43a5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -547,7 +547,7 @@ bool has_double_buffered_m_n(struct drm_i915_private *i915);
 void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
-   bool constant_n, bool fec_enable);
+   bool fec_enable);
 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
  u32 pixel_format, u64 modifier);
 enum drm_mode_status
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7c091c601e30..6750a359a555 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1904,7 +1904,7 @@ static bool can_enable_drrs(struct intel_connector 
*connector,
 static void
 intel_dp_drrs_compute_config(struct intel_connector *connector,
 struct intel_crtc_state *pipe_config,
-int output_bpp, bool constant_n)
+int output_bpp)
 {
struct drm_i915_private *i915 = to_i915(connector->base.dev);
const struct drm_display_mode *downclock_mode =
@@ -1931,7 +1931,7 @@ intel_dp_drrs_compute_config(struct intel_connector 
*connector,
 
intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
   pipe_config->port_clock, &pipe_config->dp_m2_n2,
-  constant_n, pipe_config->fec_enable);
+  pipe_config->fec_enable);
 
/* FIXME: abstract this better */
if (pipe_config->splitter.

[Intel-gfx] [PATCH v2 14/16] drm/i915: Allow M/N change during fastset on bdw+

[Ville Syrjala]

From: Ville Syrjälä 

On BDW+ M/N are double buffered and so we can easily reprogram them
during a fastset. So for eDP panels that support seamless DRRS we
can just change these without a full modeset.

For earlier platforms we'd need to play tricks with M1/N1 vs.
M2/N2 during the fastset to make sure we do the switch atomically.
Not sure the added complexity is worth the hassle, so leave it
alone for now.

The slight downside is that we have to keep the link running at
a link rate capable of supporting the highest refresh rate we
want to use. For the moment we just pick the highest mode the
panel reports and calculate the link based on that. This might
need further refinement (eg. if we run into bandwidth
restrictions)...

v2: Only use the high link rate if the platform really supports
the seamless M/N change uring fastset (ie. bdw+)

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c  | 13 +--
 .../drm/i915/display/intel_display_types.h|  1 +
 drivers/gpu/drm/i915/display/intel_dp.c   | 37 ---
 3 files changed, 43 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 4f7e119f1cd3..4e33ce635112 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5864,7 +5864,8 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
PIPE_CONF_CHECK_X(lane_lat_optim_mask);
 
if (has_double_buffered_m_n(dev_priv)) {
-   PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
+   if (!fastset || !pipe_config->seamless_m_n)
+   PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
} else {
PIPE_CONF_CHECK_M_N(dp_m_n);
PIPE_CONF_CHECK_M_N(dp_m2_n2);
@@ -5996,8 +5997,10 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
 
-   PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
-   PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
+   if (!fastset || !pipe_config->seamless_m_n) {
+   PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
+   PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
+   }
PIPE_CONF_CHECK_I(port_clock);
 
PIPE_CONF_CHECK_I(min_voltage_level);
@@ -7137,6 +7140,10 @@ static void intel_pipe_fastset(const struct 
intel_crtc_state *old_crtc_state,
if (DISPLAY_VER(dev_priv) >= 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
hsw_set_linetime_wm(new_crtc_state);
+
+   if (new_crtc_state->seamless_m_n)
+   intel_cpu_transcoder_set_m1_n1(crtc, 
new_crtc_state->cpu_transcoder,
+  &new_crtc_state->dp_m_n);
 }
 
 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8b0949b6dc75..95159d1c8ca8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1129,6 +1129,7 @@ struct intel_crtc_state {
/* m2_n2 for eDP downclock */
struct intel_link_m_n dp_m2_n2;
bool has_drrs;
+   bool seamless_m_n;
 
/* PSR is supported but might not be enabled due the lack of enabled 
planes */
bool has_psr;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 75645508080a..7c091c601e30 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1285,21 +1285,45 @@ intel_dp_adjust_compliance_config(struct intel_dp 
*intel_dp,
}
 }
 
+static bool has_seamless_m_n(struct intel_connector *connector)
+{
+   struct drm_i915_private *i915 = to_i915(connector->base.dev);
+
+   /*
+* Seamless M/N reprogramming only implemented
+* for BDW+ double buffered M/N registers so far.
+*/
+   return has_double_buffered_m_n(i915) &&
+   intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
+}
+
+static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
+  const struct drm_connector_state *conn_state)
+{
+   struct intel_connector *connector = 
to_intel_connector(conn_state->connector);
+   const struct drm_display_mode *adjusted_mode = 
&crtc_state->hw.adjusted_mode;
+
+   /* FIXME a bit of a mess wrt clock vs. crtc_clock */
+   if (has_seamless_m_n(connector))
+   return intel_panel_highest_mode(connector, 
adjusted_mode)->clock;
+   else
+   return adjusted_mode->crtc_clock;
+}
+
 /* Optimize link config in order: max bpp, min clock, min lanes */
 static int
 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp

Re: [Intel-gfx] [PATCH 09/10] drm/i915: turn on small BAR support

[Thomas Hellström]

On 5/25/22 20:43, Matthew Auld wrote:

With the uAPI in place we should now have enough in place to ensure a
working system on small BAR configurations.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Lionel Landwerlin 
Cc: Tvrtko Ursulin 
Cc: Jon Bloomfield 
Cc: Daniel Vetter 
Cc: Jordan Justen 
Cc: Kenneth Graunke 
Cc: Akeem G Abodunrin 
---
  drivers/gpu/drm/i915/gt/intel_region_lmem.c | 10 --
  1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c 
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index e9c12e0d6f59..6c6f8cbd7321 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -111,12 +111,6 @@ static struct intel_memory_region *setup_lmem(struct 
intel_gt *gt)
flat_ccs_base = intel_gt_read_register(gt, 
XEHPSDV_FLAT_CCS_BASE_ADDR);
flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * 
SZ_64K;
  
-		/* FIXME: Remove this when we have small-bar enabled */

-   if (pci_resource_len(pdev, 2) < lmem_size) {
-   drm_err(&i915->drm, "System requires small-BAR support, 
which is currently unsupported on this kernel\n");
-   return ERR_PTR(-EINVAL);
-   }
-
if (GEM_WARN_ON(lmem_size < flat_ccs_base))
return ERR_PTR(-EIO);
  
@@ -169,6 +163,10 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)

drm_info(&i915->drm, "Local memory available: %pa\n",
 &lmem_size);
  
+	if (io_size < lmem_size)

+   drm_info(&i915->drm, "Using a reduced BAR size of %lluMiB. Consider 
enabling the full BAR size if available in the BIOS.\n",
+(u64)io_size >> 20);
+


Hmm. I wonder what BIOS uis typically call the mappable portion of VRAM. 
I'll se if I can check that on my DG1 system. Might be that an average 
user misinterprets "full BAR".


/Thomas




return mem;
  
  err_region_put:

[Intel-gfx] [PATCH v2 12/16] drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled

[Ville Syrjala]

From: Ville Syrjälä 

No sense in calling intel_modeset_pipe_config_late() for a disabled
pipe.

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 16a4ea183746..4f7e119f1cd3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6918,9 +6918,11 @@ static int intel_atomic_check(struct drm_device *dev,
if (!intel_crtc_needs_modeset(new_crtc_state))
continue;
 
-   ret = intel_modeset_pipe_config_late(state, crtc);
-   if (ret)
-   goto fail;
+   if (new_crtc_state->hw.enable) {
+   ret = intel_modeset_pipe_config_late(state, crtc);
+   if (ret)
+   goto fail;
+   }
 
intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
}
-- 
2.35.1

Re: [Intel-gfx] [PATCH 04/10] drm/i915: remove intel_memory_region avail

[Thomas Hellström]

On 5/25/22 20:43, Matthew Auld wrote:

No longer used.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Lionel Landwerlin 
Cc: Tvrtko Ursulin 
Cc: Jon Bloomfield 
Cc: Daniel Vetter 
Cc: Jordan Justen 
Cc: Kenneth Graunke 
Cc: Akeem G Abodunrin 
---
  drivers/gpu/drm/i915/intel_memory_region.c | 4 +---
  drivers/gpu/drm/i915/intel_memory_region.h | 1 -
  2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_memory_region.c 
b/drivers/gpu/drm/i915/intel_memory_region.c
index 94ee26e99549..9a4a7fb55582 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -198,8 +198,7 @@ void intel_memory_region_debug(struct intel_memory_region 
*mr,
if (mr->region_private)
ttm_resource_manager_debug(mr->region_private, printer);
else
-   drm_printf(printer, "total:%pa, available:%pa bytes\n",
-  &mr->total, &mr->avail);
+   drm_printf(printer, "total:%pa bytes\n", &mr->total);
  }
  
  static int intel_memory_region_memtest(struct intel_memory_region *mem,

@@ -242,7 +241,6 @@ intel_memory_region_create(struct drm_i915_private *i915,
mem->min_page_size = min_page_size;
mem->ops = ops;
mem->total = size;
-   mem->avail = mem->total;
mem->type = type;
mem->instance = instance;
  
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h

index 2214f251bec3..2953ed5c3248 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -75,7 +75,6 @@ struct intel_memory_region {
resource_size_t io_size;
resource_size_t min_page_size;
resource_size_t total;
-   resource_size_t avail;
  
  	u16 type;

u16 instance;


Reviewed-by: Thomas Hellström 

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Cleanup interface for MCR operations

[Matt Roper]

On Fri, Jun 17, 2022 at 06:57:20AM -0700, Harish Chegondi wrote:
> On Tue, Jun 14, 2022 at 05:10:19PM -0700, Matt Roper wrote:
> > Let's replace the assortment of intel_gt_* and intel_uncore_* functions
> > that operate on MCR registers with a cleaner set of interfaces:
> > 
> >   * intel_gt_mcr_read -- unicast read from specific instance
> >   * intel_gt_mcr_read_any[_fw] -- unicast read from any non-terminated
> > instance
> >   * intel_gt_mcr_unicast_write -- unicast write to specific instance
> >   * intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances
> > 
> > We'll also replace the historic "slice" and "subslice" terminology with
> > "group" and "instance" to match the documentation for more recent
> > platforms; these days MCR steering applies to more types of replication
> > than just slice/subslice.
> > 
> > v2:
> >  - Reference the new kerneldoc from i915.rst.  (Jani)
> >  - Tweak the wording of the documentation for a couple functions to
> >clarify the difference between "_fw" and non-"_fw" forms.
> > 
> > Signed-off-by: Matt Roper 
> > Acked-by: Jani Nikula 
> > ---
> >  Documentation/gpu/i915.rst  |  12 +
> >  drivers/gpu/drm/i915/gem/i915_gem_stolen.c  |   2 +-
> >  drivers/gpu/drm/i915/gt/intel_engine_cs.c   |  33 ++-
> >  drivers/gpu/drm/i915/gt/intel_gt_debugfs.c  |   2 +-
> >  drivers/gpu/drm/i915/gt/intel_gt_mcr.c  | 239 
> >  drivers/gpu/drm/i915/gt/intel_gt_mcr.h  |  43 ++--
> >  drivers/gpu/drm/i915/gt/intel_region_lmem.c |   4 +-
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c |   8 +-
> >  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c  |   2 +-
> >  9 files changed, 200 insertions(+), 145 deletions(-)
> > 
> > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> > index 54060cd6c419..4e59db1cfb00 100644
> > --- a/Documentation/gpu/i915.rst
> > +++ b/Documentation/gpu/i915.rst
> > @@ -246,6 +246,18 @@ Display State Buffer
> >  .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
> > :internal:
> >  
> > +GT Programming
> > +==
> > +
> > +Multicast/Replicated (MCR) Registers
> > +
> > +
> > +.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > +   :doc: GT Multicast/Replicated (MCR) Register Support
> > +
> > +.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > +   :internal:
> > +
> >  Memory Management and Command Submission
> >  
> >  
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c 
> > b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> > index da30503d3ca2..fa54823d1219 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> > @@ -835,7 +835,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private 
> > *i915, u16 type,
> > } else {
> > resource_size_t lmem_range;
> >  
> > -   lmem_range = intel_gt_read_register(&i915->gt0, 
> > XEHPSDV_TILE0_ADDR_RANGE) & 0x;
> > +   lmem_range = intel_gt_mcr_read_any(&i915->gt0, 
> > XEHPSDV_TILE0_ADDR_RANGE) & 0x;
> > lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
> > lmem_size *= SZ_1G;
> > }
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
> > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index 244af1bdb7db..136cc44c3deb 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -1428,14 +1428,6 @@ void intel_engine_cancel_stop_cs(struct 
> > intel_engine_cs *engine)
> > ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
> >  }
> >  
> > -static u32
> > -read_subslice_reg(const struct intel_engine_cs *engine,
> > - int slice, int subslice, i915_reg_t reg)
> > -{
> > -   return intel_uncore_read_with_mcr_steering(engine->uncore, reg,
> > -  slice, subslice);
> > -}
> > -
> >  /* NB: please notice the memset */
> >  void intel_engine_get_instdone(const struct intel_engine_cs *engine,
> >struct intel_instdone *instdone)
> > @@ -1469,28 +1461,33 @@ void intel_engine_get_instdone(const struct 
> > intel_engine_cs *engine,
> > if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> > for_each_instdone_gslice_dss_xehp(i915, sseu, iter, 
> > slice, subslice) {
> > instdone->sampler[slice][subslice] =
> > -   read_subslice_reg(engine, slice, 
> > subslice,
> > - 
> > GEN7_SAMPLER_INSTDONE);
> > +   intel_gt_mcr_read(engine->gt,
> > + GEN7_SAMPLER_INSTDONE,
> > + slice, subslice);
> > instdone->row[slice][subslice] =
> > -

[Intel-gfx] [PATCH v2 01/16] drm/i915: Relocate intel_crtc_dotclock()

[Ville Syrjala]

From: Ville Syrjälä 

intel_crtc_dotclock() is a bit misplaced. In lieu of a better
place let's just move it next to its friends in intel_display.c.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 22 
 drivers/gpu/drm/i915/display/intel_display.c | 22 
 2 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 272e1bf6006b..51bf26dcb209 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -323,28 +323,6 @@ static int icl_calc_tbt_pll_link(struct drm_i915_private 
*dev_priv,
}
 }
 
-int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
-{
-   int dotclock;
-
-   if (intel_crtc_has_dp_encoder(pipe_config))
-   dotclock = intel_dotclock_calculate(pipe_config->port_clock,
-   &pipe_config->dp_m_n);
-   else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
-   dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
-   else
-   dotclock = pipe_config->port_clock;
-
-   if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
-   !intel_crtc_has_dp_encoder(pipe_config))
-   dotclock *= 2;
-
-   if (pipe_config->pixel_multiplier)
-   dotclock /= pipe_config->pixel_multiplier;
-
-   return dotclock;
-}
-
 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 {
/* CRT dotclock is determined via other means */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 90bd26431e31..b24784c4522d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4569,6 +4569,28 @@ int intel_dotclock_calculate(int link_freq,
return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
 }
 
+int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
+{
+   int dotclock;
+
+   if (intel_crtc_has_dp_encoder(pipe_config))
+   dotclock = intel_dotclock_calculate(pipe_config->port_clock,
+   &pipe_config->dp_m_n);
+   else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
+   dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
+   else
+   dotclock = pipe_config->port_clock;
+
+   if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
+   !intel_crtc_has_dp_encoder(pipe_config))
+   dotclock *= 2;
+
+   if (pipe_config->pixel_multiplier)
+   dotclock /= pipe_config->pixel_multiplier;
+
+   return dotclock;
+}
+
 /* Returns the currently programmed mode of the given encoder. */
 struct drm_display_mode *
 intel_encoder_current_mode(struct intel_encoder *encoder)
-- 
2.35.1

[Intel-gfx] [PATCH v2 10/16] drm/i915: Set active dpll early for icl+

[Ville Syrjala]

From: Ville Syrjälä 

To make the fastboot checks at least somewhat sensible let's mark
the expected DPLL as the active one right after we finished the
state computation. Otherwise intel_pipe_config_compare() will
always be comparing things against NULL/0.

TODO: This is still not really right. If the previous commit
had to fall back to the other PLL then the comparisong will
now fail. I guess intel_pipe_config_compare() should rather
be comparing port_dplls[] instead. But to do that we really
should just unify every platform to use the port_dplls[]
approach whether they have any need for PLL fallbacks or not.

Acked-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 09816526c5e4..c99ec8da20e0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3213,6 +3213,9 @@ static int icl_compute_combo_phy_dpll(struct 
intel_atomic_state *state,
 
icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
 
+   /* this is mainly for the fastset check */
+   icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
+
crtc_state->port_clock = icl_ddi_combo_pll_get_freq(dev_priv, NULL,

&port_dpll->hw_state);
 
@@ -3301,6 +3304,9 @@ static int icl_compute_tc_phy_dplls(struct 
intel_atomic_state *state,
if (ret)
return ret;
 
+   /* this is mainly for the fastset check */
+   icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
+
crtc_state->port_clock = icl_ddi_mg_pll_get_freq(dev_priv, NULL,
 &port_dpll->hw_state);
 
-- 
2.35.1

[Intel-gfx] [PATCH v2 09/16] drm/i915: Make all clock checks non-fuzzy

[Ville Syrjala]

From: Ville Syrjälä 

Now that we backfeed the actual DPLL frequency into the
compute crtc state all our clocks should come out exact.

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 19 ---
 1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 81ed371e8700..c98c93500a43 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5808,16 +5808,6 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
} \
 } while (0)
 
-#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
-   if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) 
{ \
-   pipe_config_mismatch(fastset, crtc, __stringify(name), \
-"(expected %i, found %i)", \
-current_config->name, \
-pipe_config->name); \
-   ret = false; \
-   } \
-} while (0)
-
 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
if (!intel_compare_infoframe(¤t_config->infoframes.name, \
 &pipe_config->infoframes.name)) { \
@@ -5936,7 +5926,7 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
PIPE_CONF_CHECK_RECT(pch_pfit.dst);
 
PIPE_CONF_CHECK_I(scaler_state.scaler_id);
-   PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
+   PIPE_CONF_CHECK_I(pixel_rate);
 
PIPE_CONF_CHECK_X(gamma_mode);
if (IS_CHERRYVIEW(dev_priv))
@@ -6006,9 +5996,9 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
 
-   PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
-   PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
-   PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
+   PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
+   PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
+   PIPE_CONF_CHECK_I(port_clock);
 
PIPE_CONF_CHECK_I(min_voltage_level);
 
@@ -6050,7 +6040,6 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
 #undef PIPE_CONF_CHECK_P
 #undef PIPE_CONF_CHECK_FLAGS
-#undef PIPE_CONF_CHECK_CLOCK_FUZZY
 #undef PIPE_CONF_CHECK_COLOR_LUT
 #undef PIPE_CONF_CHECK_TIMINGS
 #undef PIPE_CONF_CHECK_RECT
-- 
2.35.1

[Intel-gfx] [PATCH v2 02/16] drm/i915: Shuffle some PLL code around

[Ville Syrjala]

From: Ville Syrjälä 

Shuffle some PLL functions around a bit to avoid ugle
forward declarations later on. No functional changes.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 176 +-
 1 file changed, 88 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ddae7e42ac46..bfccc96f16fe 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -905,37 +905,6 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
*r2_out = best.r2;
 }
 
-static int
-hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
-  struct intel_crtc *crtc)
-{
-   struct intel_crtc_state *crtc_state =
-   intel_atomic_get_new_crtc_state(state, crtc);
-   unsigned int p, n2, r2;
-
-   hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
-
-   crtc_state->dpll_hw_state.wrpll =
-   WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
-   WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
-   WRPLL_DIVIDER_POST(p);
-
-   return 0;
-}
-
-static struct intel_shared_dpll *
-hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
-  struct intel_crtc *crtc)
-{
-   struct intel_crtc_state *crtc_state =
-   intel_atomic_get_new_crtc_state(state, crtc);
-
-   return intel_find_shared_dpll(state, crtc,
- &crtc_state->dpll_hw_state,
- BIT(DPLL_ID_WRPLL2) |
- BIT(DPLL_ID_WRPLL1));
-}
-
 static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
  const struct intel_shared_dpll *pll,
  const struct intel_dpll_hw_state *pll_state)
@@ -976,6 +945,37 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private 
*dev_priv,
return (refclk * n / 10) / (p * r) * 2;
 }
 
+static int
+hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
+  struct intel_crtc *crtc)
+{
+   struct intel_crtc_state *crtc_state =
+   intel_atomic_get_new_crtc_state(state, crtc);
+   unsigned int p, n2, r2;
+
+   hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
+
+   crtc_state->dpll_hw_state.wrpll =
+   WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
+   WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
+   WRPLL_DIVIDER_POST(p);
+
+   return 0;
+}
+
+static struct intel_shared_dpll *
+hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
+  struct intel_crtc *crtc)
+{
+   struct intel_crtc_state *crtc_state =
+   intel_atomic_get_new_crtc_state(state, crtc);
+
+   return intel_find_shared_dpll(state, crtc,
+ &crtc_state->dpll_hw_state,
+ BIT(DPLL_ID_WRPLL2) |
+ BIT(DPLL_ID_WRPLL1));
+}
+
 static int
 hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
 {
@@ -1618,43 +1618,6 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
return 0;
 }
 
-static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
-{
-   struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
-   struct skl_wrpll_params wrpll_params = {};
-   u32 ctrl1, cfgcr1, cfgcr2;
-   int ret;
-
-   /*
-* See comment in intel_dpll_hw_state to understand why we always use 0
-* as the DPLL id in this function.
-*/
-   ctrl1 = DPLL_CTRL1_OVERRIDE(0);
-
-   ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
-
-   ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
- i915->dpll.ref_clks.nssc, &wrpll_params);
-   if (ret)
-   return ret;
-
-   cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
-   DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
-   wrpll_params.dco_integer;
-
-   cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
-   DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
-   DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
-   DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
-   wrpll_params.central_freq;
-
-   crtc_state->dpll_hw_state.ctrl1 = ctrl1;
-   crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
-   crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
-
-   return 0;
-}
-
 static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
  const struct intel_shared_dpll *pll,
  const struct intel_dpll_hw_state *pll_state)
@@ -1726,6 +1689,43 @@ static int skl_ddi_wrpll_get_freq(struct 
drm_i915_private *i915,
return dco_freq / (p0 * p1 * p2 * 5);
 }

[Intel-gfx] [PATCH v2 08/16] drm/i915: Make M/N checks non-fuzzy

[Ville Syrjala]

From: Ville Syrjälä 

Now that we no longer fuzz M/N during fastset these should
match exctly.

In order to get a match with what the BIOS does we need to round
M/N down. And we do the opposite rounding when doing the readback.
That gets us pretty much the same thing back.

There can still be slight rounding differences between FDI M/N
vs. the DPLL output so we allow for tiny deviation in
intel_pipe_config_sanity_check().

v2: Tweak rounding/sanity check stuff a bit

Reviewed-by: Jani Nikula  #v1
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c  | 52 ---
 .../drm/i915/display/intel_modeset_verify.c   |  6 +--
 2 files changed, 13 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index ef7454c5b947..81ed371e8700 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4575,7 +4575,8 @@ int intel_dotclock_calculate(int link_freq,
if (!m_n->link_n)
return 0;
 
-   return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
+   return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq),
+   m_n->link_n);
 }
 
 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
@@ -5521,47 +5522,15 @@ bool intel_fuzzy_clock_check(int clock1, int clock2)
return false;
 }
 
-static bool
-intel_compare_m_n(unsigned int m, unsigned int n,
- unsigned int m2, unsigned int n2,
- bool exact)
-{
-   if (m == m2 && n == n2)
-   return true;
-
-   if (exact || !m || !n || !m2 || !n2)
-   return false;
-
-   BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
-
-   if (n > n2) {
-   while (n > n2) {
-   m2 <<= 1;
-   n2 <<= 1;
-   }
-   } else if (n < n2) {
-   while (n < n2) {
-   m <<= 1;
-   n <<= 1;
-   }
-   }
-
-   if (n != n2)
-   return false;
-
-   return intel_fuzzy_clock_check(m, m2);
-}
-
 static bool
 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
-  const struct intel_link_m_n *m2_n2,
-  bool exact)
+  const struct intel_link_m_n *m2_n2)
 {
return m_n->tu == m2_n2->tu &&
-   intel_compare_m_n(m_n->data_m, m_n->data_n,
- m2_n2->data_m, m2_n2->data_n, exact) &&
-   intel_compare_m_n(m_n->link_m, m_n->link_n,
- m2_n2->link_m, m2_n2->link_n, exact);
+   m_n->data_m == m2_n2->data_m &&
+   m_n->data_n == m2_n2->data_n &&
+   m_n->link_m == m2_n2->link_m &&
+   m_n->link_n == m2_n2->link_n;
 }
 
 static bool
@@ -5755,8 +5724,7 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
 
 #define PIPE_CONF_CHECK_M_N(name) do { \
if (!intel_compare_link_m_n(¤t_config->name, \
-   &pipe_config->name,\
-   !fastset)) { \
+   &pipe_config->name)) { \
pipe_config_mismatch(fastset, crtc, __stringify(name), \
 "(expected tu %i data %i/%i link %i/%i, " \
 "found tu %i, data %i/%i link %i/%i)", \
@@ -5803,9 +5771,9 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
  */
 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
if (!intel_compare_link_m_n(¤t_config->name, \
-   &pipe_config->name, !fastset) && \
+   &pipe_config->name) && \
!intel_compare_link_m_n(¤t_config->alt_name, \
-   &pipe_config->name, !fastset)) { \
+   &pipe_config->name)) { \
pipe_config_mismatch(fastset, crtc, __stringify(name), \
 "(expected tu %i data %i/%i link %i/%i, " \
 "or tu %i data %i/%i link %i/%i, " \
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c 
b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index a91586d77cb6..073607162acc 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -94,10 +94,10 @@ static void intel_pipe_config_sanity_check(struct 
drm_i915_private *dev_priv,
 
/*
 * FDI already provided one idea for the dotclock.
-* Yell if the encoder disagrees.
+* Yell if the encoder disagrees. Allow for slight
+* rounding differences.
 */
-   drm_WARN(&dev_priv->drm,
-  

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915/display: Add smem fallback allocation for dpt (rev5)

[Vudum, Lakshminarayana]

Issue is related to #5726. Updated the filters.

-Original Message-
From: Juha-Pekka Heikkila  
Sent: Friday, June 17, 2022 4:36 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Subject: Re: ✗ Fi.CI.IGT: failure for series starting with [1/3] 
drm/i915/display: Add smem fallback allocation for dpt (rev5)

Hi Lakshmi,

here would be another false positive from ci. My changes are not affecting this 
error with busyness on skl with igt@kms_flip@busy-flip@a-edp1

/Juha-Pekka

On 17.6.2022 13.19, Patchwork wrote:
> *Patch Details*
> *Series:* series starting with [1/3] drm/i915/display: Add smem fallback 
> allocation for dpt (rev5)
> *URL:*https://patchwork.freedesktop.org/series/104983/ 
> 
> *State:*  failure
> *Details:*
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/index.html
>  l>
> 
> 
>   CI Bug Log - changes from CI_DRM_11772_full -> 
> Patchwork_104983v5_full
> 
> 
> Summary
> 
> *FAILURE*
> 
> Serious unknown changes coming with Patchwork_104983v5_full absolutely 
> need to be verified manually.
> 
> If you think the reported changes have nothing to do with the changes 
> introduced in Patchwork_104983v5_full, please notify your bug team to 
> allow them to document this new failure mode, which will reduce false 
> positives in CI.
> 
> 
> Participating hosts (10 -> 10)
> 
> No changes in participating hosts
> 
> 
> Possible new issues
> 
> Here are the unknown changes that may have been introduced in
> Patchwork_104983v5_full:
> 
> 
>   IGT changes
> 
> 
> Possible regressions
> 
>   * igt@kms_flip@busy-flip@a-edp1:
>   o shard-skl: PASS
> 
> 
> -> FAIL
> 
>  4/igt@kms_flip@busy-f...@a-edp1.html>
> 
> 
> Known issues
> 
> Here are the changes found in Patchwork_104983v5_full that come from 
> known issues:
> 
> 
>   CI changes
> 
> 
> Issues hit
> 
>   * boot:
>   o shard-glk: (PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> ,
> PASS
> 
> )
> -> (PASS
> 
> ,
>   

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/display: Add smem fallback allocation for dpt (rev5)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/display: Add smem fallback 
allocation for dpt (rev5)
URL   : https://patchwork.freedesktop.org/series/104983/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11772_full -> Patchwork_104983v5_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_104983v5_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-glk:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [FAIL][46], [PASS][47], 
[PASS][48], [PASS][49], [PASS][50]) ([i915#4392])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk9/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk9/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk8/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk8/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk8/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk7/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk6/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk6/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk6/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk5/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk5/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk5/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk4/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk3/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk3/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk3/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk2/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk2/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk2/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk1/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk1/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11772/shard-glk1/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk1/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk1/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk1/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk2/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk2/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk2/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk3/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk3/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk3/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk4/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk4/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk5/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk5/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk6/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk6/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk6/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/shard-glk7/boot.html
   [43]: 
https://intel-gfx-ci.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl+: Fix HDMI transcoder clock vs. DDI BUF disabling order

[Patchwork]

== Series Details ==

Series: drm/i915/tgl+: Fix HDMI transcoder clock vs. DDI BUF disabling order
URL   : https://patchwork.freedesktop.org/series/105290/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11775 -> Patchwork_105290v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/index.html

Participating hosts (32 -> 33)
--

  Additional (3): fi-kbl-soraka fi-tgl-dsi fi-pnv-d510 
  Missing(2): fi-bsw-nick fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105290v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][3] ([i915#1886])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [PASS][4] -> [INCOMPLETE][5] ([i915#4785])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][6] ([i915#4528])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-soraka:  NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/fi-kbl-soraka/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271]) +9 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- fi-tgl-u2:  [PASS][9] -> [DMESG-WARN][10] ([i915#402])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-guc: NOTRUN -> [SKIP][11] ([fdo#109271])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/fi-kbl-guc/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_page_flip:
- fi-pnv-d510:NOTRUN -> [SKIP][13] ([fdo#109271]) +39 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html

  * igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][14] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/fi-pnv-d510/igt@run...@aborted.html
- fi-hsw-g3258:   NOTRUN -> [FAIL][15] ([fdo#109271] / [i915#4312])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/fi-hsw-g3258/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [DMESG-WARN][16] ([i915#5122]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_pm_rpm@module-reload:
- fi-bsw-n3050:   [FAIL][18] ([i915#6042]) -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-bsw-n3050/igt@i915_pm_...@module-reload.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105290v1/fi-bsw-n3050/igt@i915_pm_...@module-reload.html

  * igt@kms_flip@basic-flip-vs-dpms@a-edp1:
- fi-tgl-u2:  [DMESG-WARN][20] ([i915#402]) -> [PASS][21]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-tgl-u2/igt@kms_flip@basic-fl

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/bios: calculate panel type as per child device index in VBT (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/bios: calculate panel type as per child device index in VBT 
(rev2)
URL   : https://patchwork.freedesktop.org/series/104943/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11775 -> Patchwork_104943v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/index.html

Participating hosts (32 -> 33)
--

  Additional (3): fi-icl-u2 fi-tgl-dsi fi-pnv-d510 
  Missing(2): fi-bsw-nick fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_104943v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][1] ([i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_selftest@live@gem:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][3] ([i915#4528])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-pnv-d510/igt@i915_selftest@l...@gem.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][4] -> [INCOMPLETE][5] ([i915#3303] / 
[i915#4785])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-icl-u2:  NOTRUN -> [SKIP][6] ([i915#5903])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-icl-u2/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][7] ([fdo#111827]) +8 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2:  NOTRUN -> [SKIP][8] ([fdo#109278] / [i915#4103]) +1 
similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-connector-state:
- fi-icl-u2:  NOTRUN -> [WARN][9] ([i915#6008])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-icl-u2/igt@kms_force_connector_ba...@force-connector-state.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-guc: NOTRUN -> [SKIP][10] ([fdo#109271])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-kbl-guc/igt@kms_force_connector_ba...@force-load-detect.html
- fi-icl-u2:  NOTRUN -> [SKIP][11] ([fdo#109285])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-icl-u2:  NOTRUN -> [SKIP][12] ([fdo#109278])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-icl-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_page_flip:
- fi-pnv-d510:NOTRUN -> [SKIP][13] ([fdo#109271]) +39 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-pnv-d510/igt@kms_psr@primary_page_flip.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][14] ([i915#3555])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([fdo#109295] / [i915#3301])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-icl-u2/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#4312] / 
[i915#5594])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-hsw-4770/igt@run...@aborted.html
- fi-pnv-d510:NOTRUN -> [FAIL][17] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-pnv-d510/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- fi-bsw-n3050:   [FAIL][18] ([i915#6042]) -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-bsw-n3050/igt@i915_pm_...@module-reload.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104943v2/fi-bsw-n3050/igt@i915_pm_...@module-reload.html

  * igt@kms_flip@basic-flip-

Re: [Intel-gfx] [PATCH 06/10] drm/i915/uapi: add NEEDS_CPU_ACCESS hint

[Intel]

On 5/25/22 20:43, Matthew Auld wrote:

If set, force the allocation to be placed in the mappable portion of
I915_MEMORY_CLASS_DEVICE. One big restriction here is that system memory
(i.e I915_MEMORY_CLASS_SYSTEM) must be given as a potential placement for the
object, that way we can always spill the object into system memory if we
can't make space.

Testcase: igt@gem-create@create-ext-cpu-access-sanity-check
Testcase: igt@gem-create@create-ext-cpu-access-big
Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Lionel Landwerlin 
Cc: Jon Bloomfield 
Cc: Daniel Vetter 
Cc: Jordan Justen 
Cc: Kenneth Graunke 
Cc: Akeem G Abodunrin 
---
  drivers/gpu/drm/i915/gem/i915_gem_create.c | 26 ++---
  include/uapi/drm/i915_drm.h| 61 +++---
  2 files changed, 71 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c 
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index d094cae0ddf1..33673fe7ee0a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -241,6 +241,7 @@ struct create_ext {
struct drm_i915_private *i915;
struct intel_memory_region *placements[INTEL_REGION_UNKNOWN];
unsigned int n_placements;
+   unsigned int placement_mask;
unsigned long flags;
  };
  
@@ -337,6 +338,7 @@ static int set_placements(struct drm_i915_gem_create_ext_memory_regions *args,

for (i = 0; i < args->num_regions; i++)
ext_data->placements[i] = placements[i];
  
+	ext_data->placement_mask = mask;

return 0;
  
  out_dump:

@@ -411,7 +413,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void 
*data,
struct drm_i915_gem_object *obj;
int ret;
  
-	if (args->flags)

+   if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS)
return -EINVAL;
  
  	ret = i915_user_extensions(u64_to_user_ptr(args->extensions),

@@ -427,13 +429,21 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void 
*data,
ext_data.n_placements = 1;
}
  
-	/*

-* TODO: add a userspace hint to force CPU_ACCESS for the object, which
-* can override this.
-*/
-   if (ext_data.n_placements > 1 ||
-   ext_data.placements[0]->type != INTEL_MEMORY_SYSTEM)
-   ext_data.flags |= I915_BO_ALLOC_GPU_ONLY;
+   if (args->flags & I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS) {
+   if (ext_data.n_placements == 1)
+   return -EINVAL;
+
+   /*
+* We always need to be able to spill to system memory, if we
+* can't place in the mappable part of LMEM.
+*/
+   if (!(ext_data.placement_mask & BIT(INTEL_REGION_SMEM)))
+   return -EINVAL;
+   } else {
+   if (ext_data.n_placements > 1 ||
+   ext_data.placements[0]->type != INTEL_MEMORY_SYSTEM)
+   ext_data.flags |= I915_BO_ALLOC_GPU_ONLY;
+   }
  
  	obj = __i915_gem_object_create_user_ext(i915, args->size,

ext_data.placements,
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index e30f31a440b3..5b0a10e6a1b8 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3366,11 +3366,11 @@ struct drm_i915_query_memory_regions {
   * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
   * extension support using struct i915_user_extension.
   *
- * Note that in the future we want to have our buffer flags here, at least for
- * the stuff that is immutable. Previously we would have two ioctls, one to
- * create the object with gem_create, and another to apply various parameters,
- * however this creates some ambiguity for the params which are considered
- * immutable. Also in general we're phasing out the various SET/GET ioctls.
+ * Note that new buffer flags should be added here, at least for the stuff that
+ * is immutable. Previously we would have two ioctls, one to create the object
+ * with gem_create, and another to apply various parameters, however this
+ * creates some ambiguity for the params which are considered immutable. Also 
in
+ * general we're phasing out the various SET/GET ioctls.
   */
  struct drm_i915_gem_create_ext {
/**
@@ -3378,7 +3378,6 @@ struct drm_i915_gem_create_ext {
 *
 * The (page-aligned) allocated size for the object will be returned.
 *
-*
 * DG2 64K min page size implications:
 *
 * On discrete platforms, starting from DG2, we have to contend with GTT
@@ -3390,7 +3389,9 @@ struct drm_i915_gem_create_ext {
 *
 * Note that the returned size here will always reflect any required
 * rounding up done by the kernel, i.e 4K will now become 64K on devices
-* such as DG2.
+* such as DG2. The kernel will always select the largest

Re: [Intel-gfx] [PATCH 07/10] drm/i915/error: skip non-mappable pages

[Intel]

On 5/25/22 20:43, Matthew Auld wrote:

Skip capturing any lmem pages that can't be copied using the CPU. This
in now only best effort on platforms that have small BAR.

Testcase: igt@gem-exec-capture@capture-invisible
Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Lionel Landwerlin 
Cc: Tvrtko Ursulin 
Cc: Jon Bloomfield 
Cc: Daniel Vetter 
Cc: Jordan Justen 
Cc: Kenneth Graunke 
Cc: Akeem G Abodunrin 
---
  drivers/gpu/drm/i915/i915_gpu_error.c | 10 +++---
  1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0512c66fa4f3..77df899123c2 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1116,11 +1116,15 @@ i915_vma_coredump_create(const struct intel_gt *gt,
dma_addr_t dma;
  
  		for_each_sgt_daddr(dma, iter, vma_res->bi.pages) {

+   dma_addr_t offset = dma - mem->region.start;
void __iomem *s;
  
-			s = io_mapping_map_wc(&mem->iomap,

- dma - mem->region.start,
- PAGE_SIZE);
+   if (offset + PAGE_SIZE > mem->io_size) {
+   ret = -EINVAL;
+   break;
+   }
+
+   s = io_mapping_map_wc(&mem->iomap, offset, PAGE_SIZE);
ret = compress_page(compress,
(void __force *)s, dst,
true);


Reviewed-by: Thomas Hellström 

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: split out hw state readout and sanitize

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/display: split out hw state readout 
and sanitize
URL   : https://patchwork.freedesktop.org/series/105281/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11775 -> Patchwork_105281v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/index.html

Participating hosts (32 -> 34)
--

  Additional (3): fi-kbl-soraka fi-tgl-dsi fi-pnv-d510 
  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105281v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gem:
- fi-blb-e6850:   NOTRUN -> [DMESG-FAIL][3] ([i915#4528])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-blb-e6850/igt@i915_selftest@l...@gem.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][4] ([i915#1886])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-soraka:  NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-kbl-soraka/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][6] ([fdo#109271]) +9 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-guc: NOTRUN -> [SKIP][7] ([fdo#109271])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-kbl-guc/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_page_flip:
- fi-pnv-d510:NOTRUN -> [SKIP][9] ([fdo#109271]) +40 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- fi-bsw-n3050:   [FAIL][10] ([i915#6042]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-bsw-n3050/igt@i915_pm_...@module-reload.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-bsw-n3050/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [DMESG-FAIL][12] ([i915#4528]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@kms_flip@basic-plain-flip@a-edp1:
- fi-tgl-u2:  [DMESG-WARN][14] ([i915#402]) -> [PASS][15] +1 
similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-tgl-u2/igt@kms_flip@basic-plain-f...@a-edp1.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-tgl-u2/igt@kms_flip@basic-plain-f...@a-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issue

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/display: split out hw state readout and sanitize

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/display: split out hw state readout 
and sanitize
URL   : https://patchwork.freedesktop.org/series/105281/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display: split out hw state readout and sanitize

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/display: split out hw state readout 
and sanitize
URL   : https://patchwork.freedesktop.org/series/105281/
State : warning

== Summary ==

Error: dim checkpatch failed
4bf73e0fb102 drm/i915/display: split out hw state readout and sanitize
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
-:289: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#289: FILE: drivers/gpu/drm/i915/display/intel_display.c:7532:
+   intel_modeset_get_crtc_power_domains(new_crtc_state, 
&put_domains[crtc->pipe]);

-:928: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#928: 
new file mode 100644

-:1410: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#1410: FILE: drivers/gpu/drm/i915/display/intel_modeset_setup.c:478:
+
intel_crtc_bigjoiner_slave_pipes(crtc_state)) {

-:1413: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#1413: FILE: drivers/gpu/drm/i915/display/intel_modeset_setup.c:481:
+   slave_crtc_state = 
to_intel_crtc_state(slave_crtc->base.state);

total: 0 errors, 4 warnings, 0 checks, 1627 lines checked
918eac730201 drm/i915/display: convert modeset setup to struct drm_i915_private 
*i915

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] iosys-map: Add per-word read

[Patchwork]

== Series Details ==

Series: series starting with [1/2] iosys-map: Add per-word read
URL   : https://patchwork.freedesktop.org/series/105273/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11775 -> Patchwork_105273v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/index.html

Participating hosts (32 -> 35)
--

  Additional (4): fi-kbl-soraka fi-icl-u2 fi-tgl-dsi fi-pnv-d510 
  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_105273v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][1] ([i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-n3050:   [PASS][5] -> [INCOMPLETE][6] ([i915#5847])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gem:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][7] ([i915#4528])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-pnv-d510/igt@i915_selftest@l...@gem.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][8] ([i915#1886])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][9] -> [INCOMPLETE][10] ([i915#4785])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-icl-u2:  NOTRUN -> [SKIP][11] ([i915#5903])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-icl-u2/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][12] ([fdo#111827]) +8 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-kbl-soraka/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][14] ([fdo#109271]) +9 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([fdo#109278] / [i915#4103]) +1 
similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- fi-tgl-u2:  [PASS][16] -> [DMESG-WARN][17] ([i915#402])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html

  * igt@kms_force_connector_basic@force-connector-state:
- fi-icl-u2:  NOTRUN -> [WARN][18] ([i915#6008])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-icl-u2/igt@kms_force_connector_ba...@force-connector-state.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][19] ([fdo#109285])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105273v1/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-icl-u2:  NOTRUN -> [SKIP][20

[Intel-gfx] ✗ Fi.CI.BUILD: failure for tests/drm_fdinfo: Test virtual engines

[Patchwork]

== Series Details ==

Series: tests/drm_fdinfo: Test virtual engines
URL   : https://patchwork.freedesktop.org/series/105278/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/105278/revisions/1/mbox/ not 
applied
Applying: tests/drm_fdinfo: Test virtual engines
error: sha1 information is lacking or useless (tests/i915/drm_fdinfo.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 tests/drm_fdinfo: Test virtual engines
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] iosys-map: Add per-word read

[Patchwork]

== Series Details ==

Series: series starting with [1/2] iosys-map: Add per-word read
URL   : https://patchwork.freedesktop.org/series/105273/
State : warning

== Summary ==

Error: dim checkpatch failed
59710fe2242f iosys-map: Add per-word read
-:87: ERROR:SPACING: spaces required around that ':' (ctx:VxW)
#87: FILE: include/linux/iosys-map.h:339:
+   u64: val_ = readq(vaddr_iomem_)
   ^

-:87: WARNING:INDENTED_LABEL: labels should not be indented
#87: FILE: include/linux/iosys-map.h:339:
+   u64: val_ = readq(vaddr_iomem_)

-:90: ERROR:SPACING: spaces required around that ':' (ctx:VxW)
#90: FILE: include/linux/iosys-map.h:342:
+   u64: memcpy_fromio(&(val_), vaddr_iomem__, sizeof(u64))
   ^

-:90: WARNING:INDENTED_LABEL: labels should not be indented
#90: FILE: include/linux/iosys-map.h:342:
+   u64: memcpy_fromio(&(val_), vaddr_iomem__, sizeof(u64))

-:93: CHECK:CAMELCASE: Avoid CamelCase: <_Generic>
#93: FILE: include/linux/iosys-map.h:345:
+#define __iosys_map_rd_io(val__, vaddr_iomem__, type__) _Generic(val__,
\

-:93: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'val__' - possible 
side-effects?
#93: FILE: include/linux/iosys-map.h:345:
+#define __iosys_map_rd_io(val__, vaddr_iomem__, type__) _Generic(val__,
\
+   u8: val__ = readb(vaddr_iomem__),   
\
+   u16: val__ = readw(vaddr_iomem__),  
\
+   u32: val__ = readl(vaddr_iomem__),  
\
+   __iosys_map_rd_io_u64_case(val__, vaddr_iomem__))

-:93: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'vaddr_iomem__' - possible 
side-effects?
#93: FILE: include/linux/iosys-map.h:345:
+#define __iosys_map_rd_io(val__, vaddr_iomem__, type__) _Generic(val__,
\
+   u8: val__ = readb(vaddr_iomem__),   
\
+   u16: val__ = readw(vaddr_iomem__),  
\
+   u32: val__ = readl(vaddr_iomem__),  
\
+   __iosys_map_rd_io_u64_case(val__, vaddr_iomem__))

-:94: ERROR:SPACING: spaces required around that ':' (ctx:VxW)
#94: FILE: include/linux/iosys-map.h:346:
+   u8: val__ = readb(vaddr_iomem__),   
\
  ^

-:94: WARNING:INDENTED_LABEL: labels should not be indented
#94: FILE: include/linux/iosys-map.h:346:
+   u8: val__ = readb(vaddr_iomem__),   
\

-:95: ERROR:SPACING: spaces required around that ':' (ctx:VxW)
#95: FILE: include/linux/iosys-map.h:347:
+   u16: val__ = readw(vaddr_iomem__),  
\
   ^

-:95: WARNING:INDENTED_LABEL: labels should not be indented
#95: FILE: include/linux/iosys-map.h:347:
+   u16: val__ = readw(vaddr_iomem__),  
\

-:96: ERROR:SPACING: spaces required around that ':' (ctx:VxW)
#96: FILE: include/linux/iosys-map.h:348:
+   u32: val__ = readl(vaddr_iomem__),  
\
   ^

-:96: WARNING:INDENTED_LABEL: labels should not be indented
#96: FILE: include/linux/iosys-map.h:348:
+   u32: val__ = readl(vaddr_iomem__),  
\

-:99: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'type__' may be better as 
'(type__)' to avoid precedence issues
#99: FILE: include/linux/iosys-map.h:351:
+#define __iosys_map_rd_sys(val__, vaddr__, type__) ({  
\
+   compiletime_assert(sizeof(type__) <= sizeof(u64),   
\
+  "Unsupported access size for __iosys_map_rd_sys()"); 
\
+   val__ = READ_ONCE(*((type__ *)vaddr__));
\
+})

-:125: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'map__' - possible 
side-effects?
#125: FILE: include/linux/iosys-map.h:371:
+#define iosys_map_rd(map__, offset__, type__) ({   
\
+   type__ val; 
\
+   if ((map__)->is_iomem) {
\
+   __iosys_map_rd_io(val, (map__)->vaddr_iomem + (offset__), 
type__);\
+   } else {
\
+   __iosys_map_rd_sys(val, (map__)->vaddr + (offset__), type__);   
\
+   }   
\
+   val;
\
 })

-:125: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'offset__' - possible 
side-effects?
#125: FILE: include/linux/iosys-map.h:371:
+#define iosys_map_rd(map__, offset__, type__) ({   
\
+   type__ val; 
\
+   if ((map__)->is_iomem) {
\
+   __iosys

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] agp/intel: Rename intel-gtt symbols

[Patchwork]

== Series Details ==

Series: series starting with [1/2] agp/intel: Rename intel-gtt symbols
URL   : https://patchwork.freedesktop.org/series/105261/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11773_full -> Patchwork_105261v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_105261v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_105261v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105261v1_full:

### IGT changes ###

 Possible regressions 

  * igt@api_intel_allocator@two-level-inception-interruptible:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-tglb7/igt@api_intel_alloca...@two-level-inception-interruptible.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105261v1/shard-tglb6/igt@api_intel_alloca...@two-level-inception-interruptible.html

  
Known issues


  Here are the changes found in Patchwork_105261v1_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- shard-skl:  ([PASS][3], [PASS][4], [PASS][5], [PASS][6], 
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [FAIL][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24]) 
([i915#5032]) -> ([PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl9/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl9/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl9/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl7/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl6/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl6/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl6/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl4/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl4/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl4/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl3/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl3/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl2/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl2/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl1/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl1/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl1/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl1/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl10/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl10/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-skl10/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105261v1/shard-skl9/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105261v1/shard-skl9/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105261v1/shard-skl7/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105261v1/shard-skl7/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105261v1/shard-skl7/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105261v1/shard-skl6/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105261v1/shard-skl6/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105261v1/shard-skl6/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105261v1/shard-skl4/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105261v1/shard-skl4/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105261v1/shard-skl4/boot.html
   [36]: 
htt

Re: [Intel-gfx] [PATCH 08/10] drm/i915/uapi: disable capturing objects on recoverable contexts

[Intel]

On 5/25/22 20:43, Matthew Auld wrote:

A non-recoverable context must be used if the user wants proper error
capture on discrete platforms. In the future the kernel may want to blit
the contents of some objects when later doing the capture stage.

Testcase: igt@gem_exec_capture@capture-recoverable-discrete
Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Lionel Landwerlin 
Cc: Tvrtko Ursulin 
Cc: Jon Bloomfield 
Cc: Daniel Vetter 
Cc: Jordan Justen 
Cc: Kenneth Graunke 
Cc: Akeem G Abodunrin 
---
  drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 12 ++--
  1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index b279588c0672..e27ccfa50dc3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1961,7 +1961,7 @@ eb_find_first_request_added(struct i915_execbuffer *eb)
  #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
  
  /* Stage with GFP_KERNEL allocations before we enter the signaling critical path */

-static void eb_capture_stage(struct i915_execbuffer *eb)
+static int eb_capture_stage(struct i915_execbuffer *eb)
  {
const unsigned int count = eb->buffer_count;
unsigned int i = count, j;
@@ -1974,6 +1974,10 @@ static void eb_capture_stage(struct i915_execbuffer *eb)
if (!(flags & EXEC_OBJECT_CAPTURE))
continue;
  
+		if (i915_gem_context_is_recoverable(eb->gem_context) &&

+   IS_DGFX(eb->i915))
+   return -EINVAL;
+


We should also require this for future integrated, for capture buffer 
memory allocation purposes.


Otherwise Reviewed-by: Thomas Hellström 

[Intel-gfx] ✗ Fi.CI.IGT: failure for i915/pmu: Wire GuC backend to per-client busyness (rev3)

[Patchwork]

== Series Details ==

Series: i915/pmu: Wire GuC backend to per-client busyness (rev3)
URL   : https://patchwork.freedesktop.org/series/105085/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11773_full -> Patchwork_105085v3_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_105085v3_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_105085v3_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105085v3_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_whisper@basic-sync:
- shard-glk:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-glk7/igt@gem_exec_whis...@basic-sync.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v3/shard-glk3/igt@gem_exec_whis...@basic-sync.html

  * igt@kms_concurrent@pipe-b:
- shard-glk:  NOTRUN -> [TIMEOUT][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v3/shard-glk3/igt@kms_concurr...@pipe-b.html

  * igt@perf@enable-disable:
- shard-glk:  [PASS][4] -> [TIMEOUT][5] +1 similar issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-glk7/igt@p...@enable-disable.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v3/shard-glk3/igt@p...@enable-disable.html

  
 Warnings 

  * igt@kms_chamelium@dp-crc-single:
- shard-glk:  [SKIP][6] ([fdo#109271] / [fdo#111827]) -> 
[TIMEOUT][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-glk7/igt@kms_chamel...@dp-crc-single.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v3/shard-glk3/igt@kms_chamel...@dp-crc-single.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt:
- shard-glk:  [SKIP][8] ([fdo#109271]) -> [INCOMPLETE][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-glk7/igt@kms_frontbuffer_track...@psr-rgb565-draw-blt.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v3/shard-glk3/igt@kms_frontbuffer_track...@psr-rgb565-draw-blt.html

  
Known issues


  Here are the changes found in Patchwork_105085v3_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-apl:  ([PASS][10], [PASS][11], [PASS][12], [PASS][13], 
[PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], 
[PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], 
[PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], 
[PASS][32], [PASS][33], [PASS][34]) -> ([PASS][35], [PASS][36], [PASS][37], 
[PASS][38], [PASS][39], [PASS][40], [FAIL][41], [PASS][42], [PASS][43], 
[PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], 
[PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], 
[PASS][56], [PASS][57], [PASS][58], [PASS][59]) ([i915#4386])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl2/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl6/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl6/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl4/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl4/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl1/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl3/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl3/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl3/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl2/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl2/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl2/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl1/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl8/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl1/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl8/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl8/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl8/boot.html
   [29]: 
htt

[Intel-gfx] [PATCH] drm/i915: Fix a lockdep warning at error capture

[Nirmoy Das]

For some platfroms we use stop_machine version of
gen8_ggtt_insert_page/gen8_ggtt_insert_entries to avoid a
concurrent GGTT access bug but this causes a circular locking
dependency warning:

  Possible unsafe locking scenario:
CPU0CPU1

   lock(&ggtt->error_mutex);
lock(dma_fence_map);
lock(&ggtt->error_mutex);
   lock(cpu_hotplug_lock);

Fix this by calling gen8_ggtt_insert_page/gen8_ggtt_insert_entries
directly at error capture which is concurrent GGTT access safe because
reset path make sure of that.

Suggested-by: Chris Wilson 
Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/i915/gt/intel_gt_gmch.c  | 2 ++
 drivers/gpu/drm/i915/gt/intel_gtt.h  | 9 +
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 5 -
 drivers/gpu/drm/i915/i915_gpu_error.c| 8 ++--
 4 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_gmch.c 
b/drivers/gpu/drm/i915/gt/intel_gt_gmch.c
index 18e488672d1b..2260ed576776 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_gmch.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_gmch.c
@@ -629,6 +629,8 @@ int intel_gt_gmch_gen8_probe(struct i915_ggtt *ggtt)
if (intel_vm_no_concurrent_access_wa(i915)) {
ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
ggtt->vm.insert_page= bxt_vtd_ggtt_insert_page__BKL;
+   ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;
+   ggtt->vm.raw_insert_entries = gen8_ggtt_insert_entries;
ggtt->vm.bind_async_flags =
I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h 
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index a40d928b3888..f9a1f3d17272 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -306,6 +306,15 @@ struct i915_address_space {
   struct i915_vma_resource *vma_res,
   enum i915_cache_level cache_level,
   u32 flags);
+   void (*raw_insert_page)(struct i915_address_space *vm,
+   dma_addr_t addr,
+   u64 offset,
+   enum i915_cache_level cache_level,
+   u32 flags);
+   void (*raw_insert_entries)(struct i915_address_space *vm,
+  struct i915_vma_resource *vma_res,
+  enum i915_cache_level cache_level,
+  u32 flags);
void (*cleanup)(struct i915_address_space *vm);
 
void (*foreach)(struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index d2c5c9367cc4..c06e83872c34 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -493,7 +493,10 @@ static void uc_fw_bind_ggtt(struct intel_uc_fw *uc_fw)
if (i915_gem_object_is_lmem(obj))
pte_flags |= PTE_LM;
 
-   ggtt->vm.insert_entries(&ggtt->vm, dummy, I915_CACHE_NONE, pte_flags);
+   if (ggtt->vm.raw_insert_entries)
+   ggtt->vm.raw_insert_entries(&ggtt->vm, dummy, I915_CACHE_NONE, 
pte_flags);
+   else
+   ggtt->vm.insert_entries(&ggtt->vm, dummy, I915_CACHE_NONE, 
pte_flags);
 }
 
 static void uc_fw_unbind_ggtt(struct intel_uc_fw *uc_fw)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index bff8a111424a..f9b1969ed7ed 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1104,8 +1104,12 @@ i915_vma_coredump_create(const struct intel_gt *gt,
 
for_each_sgt_daddr(dma, iter, vma_res->bi.pages) {
mutex_lock(&ggtt->error_mutex);
-   ggtt->vm.insert_page(&ggtt->vm, dma, slot,
-I915_CACHE_NONE, 0);
+   if (ggtt->vm.raw_insert_page)
+   ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot,
+I915_CACHE_NONE, 0);
+   else
+   ggtt->vm.insert_page(&ggtt->vm, dma, slot,
+I915_CACHE_NONE, 0);
mb();
 
s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
-- 
2.35.1

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915/display: Add smem fallback allocation for dpt (rev5)

[Juha-Pekka Heikkila]

Hi Lakshmi,

here would be another false positive from ci. My changes are not 
affecting this error with busyness on skl with igt@kms_flip@busy-flip@a-edp1


/Juha-Pekka

On 17.6.2022 13.19, Patchwork wrote:

*Patch Details*
*Series:*	series starting with [1/3] drm/i915/display: Add smem fallback 
allocation for dpt (rev5)
*URL:*	https://patchwork.freedesktop.org/series/104983/ 


*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104983v5/index.html 




  CI Bug Log - changes from CI_DRM_11772_full -> Patchwork_104983v5_full


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_104983v5_full absolutely 
need to be

verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_104983v5_full, please notify your bug team to 
allow them

to document this new failure mode, which will reduce false positives in CI.


Participating hosts (10 -> 10)

No changes in participating hosts


Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_104983v5_full:



  IGT changes


Possible regressions

  * igt@kms_flip@busy-flip@a-edp1:
  o shard-skl: PASS


-> FAIL




Known issues

Here are the changes found in Patchwork_104983v5_full that come from 
known issues:



  CI changes


Issues hit

  * boot:
  o shard-glk: (PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

)
-> (PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Check for ct enabled while waiting for response

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Check for ct enabled while waiting for response
URL   : https://patchwork.freedesktop.org/series/105258/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11773_full -> Patchwork_105258v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_105258v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@in-flight-10ms:
- shard-tglb: [PASS][1] -> [TIMEOUT][2] ([i915#3063]) +1 similar 
issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-tglb3/igt@gem_...@in-flight-10ms.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/shard-tglb8/igt@gem_...@in-flight-10ms.html

  * igt@gem_eio@in-flight-contexts-1us:
- shard-snb:  [PASS][3] -> [FAIL][4] ([i915#4409])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-snb5/igt@gem_...@in-flight-contexts-1us.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/shard-snb5/igt@gem_...@in-flight-contexts-1us.html

  * igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-iclb2/igt@gem_exec_balan...@parallel-bb-first.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/shard-iclb5/igt@gem_exec_balan...@parallel-bb-first.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/shard-tglb6/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/shard-iclb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none@vecs0:
- shard-apl:  [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl:  [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar 
issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-kbl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_whisper@basic-queues-all:
- shard-glk:  [PASS][15] -> [DMESG-WARN][16] ([i915#118])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-glk2/igt@gem_exec_whis...@basic-queues-all.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/shard-glk5/igt@gem_exec_whis...@basic-queues-all.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl:  [PASS][17] -> [DMESG-WARN][18] ([i915#180])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-apl7/igt@i915_susp...@fence-restore-tiled2untiled.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl:  [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +2 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11773/shard-kbl4/igt@kms_cursor_...@pipe-a-cursor-suspend.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/shard-kbl7/igt@kms_cursor_...@pipe-a-cursor-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-apl:  NOTRUN -> [SKIP][21] ([fdo#109271]) +12 similar issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/shard-apl6/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-apl:  NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#533])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105258v1/shard-apl6/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-d-frame-sequence.html

  * 
igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [PASS][23] -> [SKIP][24] ([i915#5235]) +2 similar 
issues
   [23]: 
https://intel-gfx-ci.0