[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: stop HPD workers before display driver unregister (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/display: stop HPD workers before display driver unregister 
(rev6)
URL   : https://patchwork.freedesktop.org/series/105557/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11877 -> Patchwork_105557v6


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/index.html

Participating hosts (39 -> 40)
--

  Additional (3): bat-adlm-1 bat-dg2-9 bat-adlp-4 
  Missing(2): bat-adln-1 bat-dg1-5 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105557v6:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_module_load@reload:
- {bat-rpls-2}:   [DMESG-WARN][1] ([i915#5950]) -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/bat-rpls-2/igt@i915_module_l...@reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/bat-rpls-2/igt@i915_module_l...@reload.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- {bat-adlm-1}:   NOTRUN -> [SKIP][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/bat-adlm-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  
Known issues


  Here are the changes found in Patchwork_105557v6 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600:   NOTRUN -> [FAIL][4] ([fdo#103375])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_lmem_swapping@verify-random:
- bat-adlp-4: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/bat-adlp-4/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_tiled_pread_basic:
- bat-adlp-4: NOTRUN -> [SKIP][6] ([i915#3282])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/bat-adlp-4/igt@gem_tiled_pread_basic.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-adlp-4: NOTRUN -> [SKIP][7] ([i915#5903])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/bat-adlp-4/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-rkl-11600:   NOTRUN -> [SKIP][8] ([fdo#111827])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/fi-rkl-11600/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- bat-adlp-4: NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/bat-adlp-4/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-adlp-4: NOTRUN -> [SKIP][10] ([i915#4103])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/bat-adlp-4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-adlp-4: NOTRUN -> [SKIP][11] ([i915#4093]) +3 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/bat-adlp-4/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-adlp-4: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#4579])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/bat-adlp-4/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- bat-adlp-4: NOTRUN -> [SKIP][13] ([fdo#109295] / [i915#3301] / 
[i915#3708])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/bat-adlp-4/igt@prime_v...@basic-userptr.html

  * igt@prime_vgem@basic-write:
- bat-adlp-4: NOTRUN -> [SKIP][14] ([fdo#109295] / [i915#3291] / 
[i915#3708]) +2 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/bat-adlp-4/igt@prime_v...@basic-write.html

  
 Possible fixes 

  * igt@i915_module_load@load:
- {fi-tgl-dsi}:   [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-tgl-dsi/igt@i915_module_l...@load.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/fi-tgl-dsi/igt@i915_module_l...@load.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [INCOMPLETE][17] ([i915#5982]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v6/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  
  {name}: This element is suppressed. This means it is ig

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: stop HPD workers before display driver unregister (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/display: stop HPD workers before display driver unregister 
(rev6)
URL   : https://patchwork.freedesktop.org/series/105557/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH v2 07/39] drm/i915: gvt: fix kernel-doc trivial warnings

[Zhenyu Wang]

On 2022.07.13 09:11:55 +0100, Mauro Carvalho Chehab wrote:
> Some functions seem to have been renamed without updating the kernel-doc
> markup causing warnings. Also, struct intel_vgpu_dmabuf_obj is not
> properly documented, but has a kerneld-doc markup.
> 
> Fix those warnings:
>   drivers/gpu/drm/i915/gvt/aperture_gm.c:308: warning: expecting 
> prototype for inte_gvt_free_vgpu_resource(). Prototype was for 
> intel_vgpu_free_resource() instead
>   drivers/gpu/drm/i915/gvt/aperture_gm.c:344: warning: expecting 
> prototype for intel_alloc_vgpu_resource(). Prototype was for 
> intel_vgpu_alloc_resource() instead
>   drivers/gpu/drm/i915/gvt/cfg_space.c:257: warning: expecting prototype 
> for intel_vgpu_emulate_cfg_read(). Prototype was for 
> intel_vgpu_emulate_cfg_write() instead
>   drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or 
> member 'vgpu' not described in 'intel_vgpu_dmabuf_obj'
>   drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or 
> member 'info' not described in 'intel_vgpu_dmabuf_obj'
>   drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or 
> member 'dmabuf_id' not described in 'intel_vgpu_dmabuf_obj'
>   drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or 
> member 'kref' not described in 'intel_vgpu_dmabuf_obj'
>   drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or 
> member 'initref' not described in 'intel_vgpu_dmabuf_obj'
>   drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or 
> member 'list' not described in 'intel_vgpu_dmabuf_obj'
>   drivers/gpu/drm/i915/gvt/handlers.c:3066: warning: expecting prototype 
> for intel_t_default_mmio_write(). Prototype was for 
> intel_vgpu_default_mmio_write() instead
>   drivers/gpu/drm/i915/gvt/mmio_context.c:560: warning: expecting 
> prototype for intel_gvt_switch_render_mmio(). Prototype was for 
> intel_gvt_switch_mmio() instead
>   drivers/gpu/drm/i915/gvt/page_track.c:131: warning: expecting prototype 
> for intel_vgpu_enable_page_track(). Prototype was for 
> intel_vgpu_disable_page_track() instead
>   drivers/gpu/drm/i915/gvt/vgpu.c:215: warning: expecting prototype for 
> intel_gvt_active_vgpu(). Prototype was for intel_gvt_activate_vgpu() instead
>   drivers/gpu/drm/i915/gvt/vgpu.c:230: warning: expecting prototype for 
> intel_gvt_deactive_vgpu(). Prototype was for intel_gvt_deactivate_vgpu() 
> instead
>   drivers/gpu/drm/i915/gvt/vgpu.c:358: warning: expecting prototype for 
> intel_gvt_destroy_vgpu(). Prototype was for intel_gvt_destroy_idle_vgpu() 
> instead
> 
> Signed-off-by: Mauro Carvalho Chehab 
> ---
> 
> To avoid mailbombing on a large number of people, only mailing lists were C/C 
> on the cover.
> See [PATCH v2 00/39] at: 
> https://lore.kernel.org/all/cover.1657699522.git.mche...@kernel.org/
> 
>  drivers/gpu/drm/i915/gvt/cfg_space.c  | 2 +-
>  drivers/gpu/drm/i915/gvt/dmabuf.h | 2 +-
>  drivers/gpu/drm/i915/gvt/page_track.c | 2 +-
>  drivers/gpu/drm/i915/gvt/vgpu.c   | 6 +++---
>  4 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c 
> b/drivers/gpu/drm/i915/gvt/cfg_space.c
> index dad3a6054335..a0fc6d356588 100644
> --- a/drivers/gpu/drm/i915/gvt/cfg_space.c
> +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c
> @@ -243,7 +243,7 @@ static void emulate_pci_bar_write(struct intel_vgpu 
> *vgpu, unsigned int offset,
>  }
>  
>  /**
> - * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write
> + * intel_vgpu_emulate_cfg_write - emulate vGPU configuration space write
>   * @vgpu: target vgpu
>   * @offset: offset
>   * @p_data: write data ptr
> diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.h 
> b/drivers/gpu/drm/i915/gvt/dmabuf.h
> index 5f8f03fb1d1b..3dcdb6570eda 100644
> --- a/drivers/gpu/drm/i915/gvt/dmabuf.h
> +++ b/drivers/gpu/drm/i915/gvt/dmabuf.h
> @@ -48,7 +48,7 @@ struct intel_vgpu_fb_info {
>   struct intel_vgpu_dmabuf_obj *obj;
>  };
>  
> -/**
> +/*
>   * struct intel_vgpu_dmabuf_obj- Intel vGPU device buffer object
>   */
>  struct intel_vgpu_dmabuf_obj {
> diff --git a/drivers/gpu/drm/i915/gvt/page_track.c 
> b/drivers/gpu/drm/i915/gvt/page_track.c
> index 3375b51c75f1..df34e73cba41 100644
> --- a/drivers/gpu/drm/i915/gvt/page_track.c
> +++ b/drivers/gpu/drm/i915/gvt/page_track.c
> @@ -120,7 +120,7 @@ int intel_vgpu_enable_page_track(struct intel_vgpu *vgpu, 
> unsigned long gfn)
>  }
>  
>  /**
> - * intel_vgpu_enable_page_track - cancel write-protection on guest page
> + * intel_vgpu_disable_page_track - cancel write-protection on guest page
>   * @vgpu: a vGPU
>   * @gfn: the gfn of guest page
>   *
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> index 46da19b3225d..8e71cda19995 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -205,7 +205,7 @@ static void intel_gvt_update_vgpu_types(struct intel_gvt

Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/display: add hotplug.suspended flag

[Murthy, Arun R]

> -Original Message-
> From: Hajda, Andrzej 
> Sent: Wednesday, July 13, 2022 8:50 PM
> To: Jani Nikula ; Ville Syrjälä
> ; Murthy, Arun R 
> Cc: Hajda, Andrzej ; Joonas Lahtinen
> ; Vivi, Rodrigo ;
> Tvrtko Ursulin ; Daniel Vetter
> ; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Subject: [PATCH v3 3/3] drm/i915/display: add hotplug.suspended flag
> 
> HPD events during driver removal can be generated by hardware and
> software frameworks - drm_dp_mst, the former we can avoid by disabling
> interrupts, the latter can be triggered by any drm_dp_mst transaction, and
> this is too late. Introducing suspended flag allows to solve this chicken-egg
> problem.
> 
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5950
> Signed-off-by: Andrzej Hajda 
> ---
Reviewed-by: Arun R Murthy 

Thanks and Regards,
Arun R Murthy

Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/fbdev: suspend HPD before fbdev unregistration

[Murthy, Arun R]

> -Original Message-
> From: Hajda, Andrzej 
> Sent: Wednesday, July 13, 2022 8:50 PM
> To: Jani Nikula ; Ville Syrjälä
> ; Murthy, Arun R 
> Cc: Hajda, Andrzej ; Joonas Lahtinen
> ; Vivi, Rodrigo ;
> Tvrtko Ursulin ; Daniel Vetter
> ; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Subject: [PATCH v3 2/3] drm/i915/fbdev: suspend HPD before fbdev
> unregistration
> 
> HPD event after fbdev unregistration can cause registration of deferred fbdev
> which will not be unregistered later, causing use-after-free.
> To avoid it HPD handling should be suspended before fbdev unregistration.
> 
> It should fix following GPF:
> [272.634530] general protection fault, probably for non-canonical address
> 0x6b6b6b6b6b6b6b6b:  [#1] PREEMPT SMP NOPTI
> [272.634536] CPU: 0 PID: 6030 Comm: i915_selftest Tainted: G U
> 5.18.0-rc5-CI_DRM_11603-g12dccf4f5eef+ #1
> [272.634541] Hardware name: Intel Corporation Raptor Lake Client
> Platform/RPL-S ADP-S DDR5 UDIMM CRB, BIOS
> RPLSFWI1.R00.2397.A01.2109300731 09/30/2021 [272.634545] RIP:
> 0010:fb_do_apertures_overlap.part.14+0x26/0x60
> ...
> [272.634582] Call Trace:
> [272.634583]  
> [272.634585]  do_remove_conflicting_framebuffers+0x59/0xa0
> [272.634589]  remove_conflicting_framebuffers+0x2d/0xc0
> [272.634592]  remove_conflicting_pci_framebuffers+0xc8/0x110
> [272.634595]
> drm_aperture_remove_conflicting_pci_framebuffers+0x52/0x70
> [272.634604]  i915_driver_probe+0x63a/0xdd0 [i915]
> 
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5329
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5510
> Signed-off-by: Andrzej Hajda 
> ---
Reviewed-by: Arun R Murthy 

Thanks and Regards,
Arun R Murthy

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: stop HPD workers before display driver unregister (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/display: stop HPD workers before display driver unregister 
(rev5)
URL   : https://patchwork.freedesktop.org/series/105557/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11877_full -> Patchwork_105557v5_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_105557v5_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_105557v5_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 12)
--

  Missing(1): shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105557v5_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_fair@basic-deadline:
- shard-kbl:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-kbl7/igt@gem_exec_f...@basic-deadline.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/shard-kbl6/igt@gem_exec_f...@basic-deadline.html

  * igt@i915_selftest@live@hangcheck:
- shard-skl:  NOTRUN -> [INCOMPLETE][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/shard-skl10/igt@i915_selftest@l...@hangcheck.html

  
Known issues


  Here are the changes found in Patchwork_105557v5_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-skl:  ([PASS][4], [PASS][5], [PASS][6], [PASS][7], 
[PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], 
[PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], 
[PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24]) -> ([PASS][25], 
[PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], 
[PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], 
[PASS][38], [PASS][39], [PASS][40], [PASS][41], [FAIL][42], [PASS][43], 
[PASS][44], [PASS][45], [PASS][46], [PASS][47]) ([i915#5032])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl9/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl9/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl7/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl6/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl6/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl5/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl5/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl4/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl4/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl4/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl3/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl3/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl2/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl2/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl1/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl1/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl1/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl10/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl10/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl10/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/shard-skl2/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/shard-skl1/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/shard-skl1/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/shard-skl1/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/shard-skl10/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/shard-skl10/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/shard-skl9/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/shard-skl9/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/shard-skl9/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/shard-skl7/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patch

[Intel-gfx] ✗ Fi.CI.IGT: failure for Random assortment of (mostly) GuC related patches (rev2)

[Patchwork]

== Series Details ==

Series: Random assortment of (mostly) GuC related patches (rev2)
URL   : https://patchwork.freedesktop.org/series/106272/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11877_full -> Patchwork_106272v2_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_106272v2_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_106272v2_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 12)
--

  Missing(1): shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_106272v2_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_fair@basic-deadline:
- shard-kbl:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-kbl7/igt@gem_exec_f...@basic-deadline.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/shard-kbl6/igt@gem_exec_f...@basic-deadline.html

  * igt@i915_selftest@live@objects:
- shard-skl:  [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl6/igt@i915_selftest@l...@objects.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/shard-skl2/igt@i915_selftest@l...@objects.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_whisper@basic-fds-priority-all:
- {shard-rkl}:[PASS][5] -> [DMESG-WARN][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-rkl-2/igt@gem_exec_whis...@basic-fds-priority-all.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/shard-rkl-5/igt@gem_exec_whis...@basic-fds-priority-all.html

  
New tests
-

  New tests have been introduced between CI_DRM_11877_full and 
Patchwork_106272v2_full:

### New IGT tests (1) ###

  * igt@i915_selftest@live@guc_hang:
- Statuses : 8 pass(s)
- Exec time: [0.48, 1.81] s

  

Known issues


  Here are the changes found in Patchwork_106272v2_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl:  [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +7 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-kbl1/igt@gem_ctx_isolation@preservation...@vcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@gem_eio@kms:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#5784])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-tglb7/igt@gem_...@kms.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/shard-tglb5/igt@gem_...@kms.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2842])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-iclb1/igt@gem_exec_fair@basic-p...@vecs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/shard-iclb4/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][18] -> [FAIL][19] ([i915#2849])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_whisper@basic-queues-forked-all:
- shard-glk:  [PASS][20] -> [DMESG-WARN][21] ([i915#118])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-glk9/igt@gem_exec_whis...@basic-queues-forked-all.html

Re: [Intel-gfx] [PATCH v2 09/39] drm/i915: intel_wakeref.h: fix some kernel-doc markups

[Rodrigo Vivi]

On Wed, Jul 13, 2022 at 09:11:57AM +0100, Mauro Carvalho Chehab wrote:
> Two documented functions don't match the kernel-doc comments,
> as reported by kernel-doc:
> 
>   drivers/gpu/drm/i915/intel_wakeref.h:117: warning: expecting prototype 
> for intel_wakeref_get_if_in_use(). Prototype was for 
> intel_wakeref_get_if_active() instead
>   drivers/gpu/drm/i915/intel_wakeref.h:149: warning: expecting prototype 
> for intel_wakeref_put_flags(). Prototype was for __intel_wakeref_put() instead
> 
> Fix them.
> 
> Additionally, improve title for intel_wakeref_get_if_active().
> 
> Signed-off-by: Mauro Carvalho Chehab 

Reviewed-by: Rodrigo Vivi 

> ---
> 
> To avoid mailbombing on a large number of people, only mailing lists were C/C 
> on the cover.
> See [PATCH v2 00/39] at: 
> https://lore.kernel.org/all/cover.1657699522.git.mche...@kernel.org/
> 
>  drivers/gpu/drm/i915/intel_wakeref.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_wakeref.h 
> b/drivers/gpu/drm/i915/intel_wakeref.h
> index 4f4c2e15e736..63e539c9b1f3 100644
> --- a/drivers/gpu/drm/i915/intel_wakeref.h
> +++ b/drivers/gpu/drm/i915/intel_wakeref.h
> @@ -104,7 +104,7 @@ __intel_wakeref_get(struct intel_wakeref *wf)
>  }
>  
>  /**
> - * intel_wakeref_get_if_in_use: Acquire the wakeref
> + * intel_wakeref_get_if_active: Acquire the wakeref if active
>   * @wf: the wakeref
>   *
>   * Acquire a hold on the wakeref, but only if the wakeref is already
> @@ -130,7 +130,7 @@ intel_wakeref_might_get(struct intel_wakeref *wf)
>  }
>  
>  /**
> - * intel_wakeref_put_flags: Release the wakeref
> + * __intel_wakeref_put: Release the wakeref
>   * @wf: the wakeref
>   * @flags: control flags
>   *
> -- 
> 2.36.1
> 

Re: [Intel-gfx] [PATCH v2 07/39] drm/i915: gvt: fix kernel-doc trivial warnings

[Rodrigo Vivi]

On Wed, Jul 13, 2022 at 09:11:55AM +0100, Mauro Carvalho Chehab wrote:
> Some functions seem to have been renamed without updating the kernel-doc
> markup causing warnings. Also, struct intel_vgpu_dmabuf_obj is not
> properly documented, but has a kerneld-doc markup.
> 
> Fix those warnings:
>   drivers/gpu/drm/i915/gvt/aperture_gm.c:308: warning: expecting 
> prototype for inte_gvt_free_vgpu_resource(). Prototype was for 
> intel_vgpu_free_resource() instead
>   drivers/gpu/drm/i915/gvt/aperture_gm.c:344: warning: expecting 
> prototype for intel_alloc_vgpu_resource(). Prototype was for 
> intel_vgpu_alloc_resource() instead
>   drivers/gpu/drm/i915/gvt/cfg_space.c:257: warning: expecting prototype 
> for intel_vgpu_emulate_cfg_read(). Prototype was for 
> intel_vgpu_emulate_cfg_write() instead
>   drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or 
> member 'vgpu' not described in 'intel_vgpu_dmabuf_obj'
>   drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or 
> member 'info' not described in 'intel_vgpu_dmabuf_obj'
>   drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or 
> member 'dmabuf_id' not described in 'intel_vgpu_dmabuf_obj'
>   drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or 
> member 'kref' not described in 'intel_vgpu_dmabuf_obj'
>   drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or 
> member 'initref' not described in 'intel_vgpu_dmabuf_obj'
>   drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or 
> member 'list' not described in 'intel_vgpu_dmabuf_obj'
>   drivers/gpu/drm/i915/gvt/handlers.c:3066: warning: expecting prototype 
> for intel_t_default_mmio_write(). Prototype was for 
> intel_vgpu_default_mmio_write() instead
>   drivers/gpu/drm/i915/gvt/mmio_context.c:560: warning: expecting 
> prototype for intel_gvt_switch_render_mmio(). Prototype was for 
> intel_gvt_switch_mmio() instead
>   drivers/gpu/drm/i915/gvt/page_track.c:131: warning: expecting prototype 
> for intel_vgpu_enable_page_track(). Prototype was for 
> intel_vgpu_disable_page_track() instead
>   drivers/gpu/drm/i915/gvt/vgpu.c:215: warning: expecting prototype for 
> intel_gvt_active_vgpu(). Prototype was for intel_gvt_activate_vgpu() instead
>   drivers/gpu/drm/i915/gvt/vgpu.c:230: warning: expecting prototype for 
> intel_gvt_deactive_vgpu(). Prototype was for intel_gvt_deactivate_vgpu() 
> instead
>   drivers/gpu/drm/i915/gvt/vgpu.c:358: warning: expecting prototype for 
> intel_gvt_destroy_vgpu(). Prototype was for intel_gvt_destroy_idle_vgpu() 
> instead
> 
> Signed-off-by: Mauro Carvalho Chehab 

Reviewed-by: Rodrigo Vivi 

> ---
> 
> To avoid mailbombing on a large number of people, only mailing lists were C/C 
> on the cover.
> See [PATCH v2 00/39] at: 
> https://lore.kernel.org/all/cover.1657699522.git.mche...@kernel.org/
> 
>  drivers/gpu/drm/i915/gvt/cfg_space.c  | 2 +-
>  drivers/gpu/drm/i915/gvt/dmabuf.h | 2 +-
>  drivers/gpu/drm/i915/gvt/page_track.c | 2 +-
>  drivers/gpu/drm/i915/gvt/vgpu.c   | 6 +++---
>  4 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c 
> b/drivers/gpu/drm/i915/gvt/cfg_space.c
> index dad3a6054335..a0fc6d356588 100644
> --- a/drivers/gpu/drm/i915/gvt/cfg_space.c
> +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c
> @@ -243,7 +243,7 @@ static void emulate_pci_bar_write(struct intel_vgpu 
> *vgpu, unsigned int offset,
>  }
>  
>  /**
> - * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write
> + * intel_vgpu_emulate_cfg_write - emulate vGPU configuration space write
>   * @vgpu: target vgpu
>   * @offset: offset
>   * @p_data: write data ptr
> diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.h 
> b/drivers/gpu/drm/i915/gvt/dmabuf.h
> index 5f8f03fb1d1b..3dcdb6570eda 100644
> --- a/drivers/gpu/drm/i915/gvt/dmabuf.h
> +++ b/drivers/gpu/drm/i915/gvt/dmabuf.h
> @@ -48,7 +48,7 @@ struct intel_vgpu_fb_info {
>   struct intel_vgpu_dmabuf_obj *obj;
>  };
>  
> -/**
> +/*
>   * struct intel_vgpu_dmabuf_obj- Intel vGPU device buffer object
>   */
>  struct intel_vgpu_dmabuf_obj {
> diff --git a/drivers/gpu/drm/i915/gvt/page_track.c 
> b/drivers/gpu/drm/i915/gvt/page_track.c
> index 3375b51c75f1..df34e73cba41 100644
> --- a/drivers/gpu/drm/i915/gvt/page_track.c
> +++ b/drivers/gpu/drm/i915/gvt/page_track.c
> @@ -120,7 +120,7 @@ int intel_vgpu_enable_page_track(struct intel_vgpu *vgpu, 
> unsigned long gfn)
>  }
>  
>  /**
> - * intel_vgpu_enable_page_track - cancel write-protection on guest page
> + * intel_vgpu_disable_page_track - cancel write-protection on guest page
>   * @vgpu: a vGPU
>   * @gfn: the gfn of guest page
>   *
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> index 46da19b3225d..8e71cda19995 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -205,7 +205,7 @@ static void int

Re: [Intel-gfx] [PATCH v2 06/39] drm/i915: gt: fix some Kernel-doc issues

[Rodrigo Vivi]

On Wed, Jul 13, 2022 at 09:11:54AM +0100, Mauro Carvalho Chehab wrote:
> There are several trivial warnings there, due to trivial things:
>   - lack of function name at the kerneldoc markup;
>   - undocumented structs with kernel-doc markups;
>   - wrong parameter syntax.
> 
> Fix such warnings:
> 
>   drivers/gpu/drm/i915/gt/intel_context.h:107: warning: Function 
> parameter or member 'ce' not described in 'intel_context_lock_pinned'
>   drivers/gpu/drm/i915/gt/intel_context.h:122: warning: Function 
> parameter or member 'ce' not described in 'intel_context_is_pinned'
>   drivers/gpu/drm/i915/gt/intel_context.h:141: warning: Function 
> parameter or member 'ce' not described in 'intel_context_unlock_pinned'
>   drivers/gpu/drm/i915/gt/intel_gtt.h:510: warning: Function parameter or 
> member 'vm' not described in 'i915_vm_resv_put'
>   drivers/gpu/drm/i915/gt/intel_gtt.h:510: warning: Excess function 
> parameter 'resv' description in 'i915_vm_resv_put'
>   drivers/gpu/drm/i915/gt/intel_gtt.h:615: warning: Function parameter or 
> member 'i915' not described in 'i915_ggtt_mark_pte_lost'
>   drivers/gpu/drm/i915/gt/intel_gtt.h:615: warning: Function parameter or 
> member 'val' not described in 'i915_ggtt_mark_pte_lost'
>   drivers/gpu/drm/i915/gt/intel_rps.c:2343: warning: This comment starts 
> with '/**', but isn't a kernel-doc comment. Refer 
> Documentation/doc-guide/kernel-doc.rst
>* Tells the intel_ips driver that the i915 driver is now loaded, if
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:28: warning: Function 
> parameter or member 'size' not described in '__guc_capture_bufstate'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:28: warning: Function 
> parameter or member 'data' not described in '__guc_capture_bufstate'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:28: warning: Function 
> parameter or member 'rd' not described in '__guc_capture_bufstate'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:28: warning: Function 
> parameter or member 'wr' not described in '__guc_capture_bufstate'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:60: warning: Function 
> parameter or member 'link' not described in '__guc_capture_parsed_output'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:60: warning: Function 
> parameter or member 'is_partial' not described in 
> '__guc_capture_parsed_output'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:60: warning: Function 
> parameter or member 'eng_class' not described in '__guc_capture_parsed_output'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:60: warning: Function 
> parameter or member 'eng_inst' not described in '__guc_capture_parsed_output'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:60: warning: Function 
> parameter or member 'guc_id' not described in '__guc_capture_parsed_output'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:60: warning: Function 
> parameter or member 'lrca' not described in '__guc_capture_parsed_output'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:60: warning: Function 
> parameter or member 'reginfo' not described in '__guc_capture_parsed_output'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:63: warning: wrong 
> kernel-doc identifier on line:
>* struct guc_debug_capture_list_header / struct guc_debug_capture_list
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:81: warning: wrong 
> kernel-doc identifier on line:
>* struct __guc_mmio_reg_descr / struct __guc_mmio_reg_descr_group
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:106: warning: wrong 
> kernel-doc identifier on line:
>* struct guc_state_capture_header_t / struct guc_state_capture_t /
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:164: warning: Function 
> parameter or member 'is_valid' not described in '__guc_capture_ads_cache'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:164: warning: Function 
> parameter or member 'ptr' not described in '__guc_capture_ads_cache'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:164: warning: Function 
> parameter or member 'size' not described in '__guc_capture_ads_cache'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:164: warning: Function 
> parameter or member 'status' not described in '__guc_capture_ads_cache'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:217: warning: Function 
> parameter or member 'ads_null_cache' not described in 
> 'intel_guc_state_capture'
>   drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:217: warning: Function 
> parameter or member 'max_mmio_per_node' not described in 
> 'intel_guc_state_capture'
>   drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:401: warning: Function 
> parameter or member 'marker' not described in 'guc_log_buffer_state'
>   drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:401: warning: Function 
> parameter or member 'read_ptr' not described in 'guc_log_buffer_stat

Re: [Intel-gfx] [PATCH v2 05/39] drm/i915: display: fix kernel-doc markup warnings

[Rodrigo Vivi]

On Wed, Jul 13, 2022 at 09:11:53AM +0100, Mauro Carvalho Chehab wrote:
> There are a couple of issues at i915 display kernel-doc markups:
> 
>   drivers/gpu/drm/i915/display/intel_display_debugfs.c:2238: warning: 
> Function parameter or member 'intel_connector' not described in 
> 'intel_connector_debugfs_add'
>   drivers/gpu/drm/i915/display/intel_display_debugfs.c:2238: warning: 
> Excess function parameter 'connector' description in 
> 'intel_connector_debugfs_add'
>   drivers/gpu/drm/i915/display/intel_display_power.c:700: warning: 
> expecting prototype for intel_display_power_put_async(). Prototype was for 
> __intel_display_power_put_async() instead
>   drivers/gpu/drm/i915/display/intel_tc.c:807: warning: Function 
> parameter or member 'work' not described in 
> 'intel_tc_port_disconnect_phy_work'
>   drivers/gpu/drm/i915/display/intel_tc.c:807: warning: Excess function 
> parameter 'dig_port' description in 'intel_tc_port_disconnect_phy_work'
> 
> Those are due to wrong parameter of function name. Address them.
> 
> Signed-off-by: Mauro Carvalho Chehab 
> ---
> 
> To avoid mailbombing on a large number of people, only mailing lists were C/C 
> on the cover.
> See [PATCH v2 00/39] at: 
> https://lore.kernel.org/all/cover.1657699522.git.mche...@kernel.org/
> 
>  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
>  drivers/gpu/drm/i915/display/intel_display_power.c   | 2 +-
>  drivers/gpu/drm/i915/display/intel_tc.c  | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 6c3954479047..1e35eb01742b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2229,7 +2229,7 @@ DEFINE_SHOW_ATTRIBUTE(i915_current_bpc);
>  
>  /**
>   * intel_connector_debugfs_add - add i915 specific connector debugfs files
> - * @connector: pointer to a registered drm_connector
> + * @intel_connector: pointer to a registered drm_connector
>   *
>   * Cleanup will be done by drm_connector_unregister() through a call to
>   * drm_debugfs_connector_remove().
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 589af257edeb..fd6b71160a06 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -685,7 +685,7 @@ intel_display_power_put_async_work(struct work_struct 
> *work)
>  }
>  
>  /**
> - * intel_display_power_put_async - release a power domain reference 
> asynchronously
> + * __intel_display_power_put_async - release a power domain reference 
> asynchronously

oh, we are really using __ prefix for non-static functions?! o.O

anyway, with that ditto "()" consistency,

Reviewed-by: Rodrigo Vivi 



>   * @i915: i915 device instance
>   * @domain: power domain to reference
>   * @wakeref: wakeref acquired for the reference that is being released
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c 
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index 6773840f6cc7..7ce0cbe0de05 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -797,7 +797,7 @@ void intel_tc_port_lock(struct intel_digital_port 
> *dig_port)
>  
>  /**
>   * intel_tc_port_disconnect_phy_work: disconnect TypeC PHY from display port
> - * @dig_port: digital port
> + * @work: workqueue struct
>   *
>   * Disconnect the given digital port from its TypeC PHY (handing back the
>   * control of the PHY to the TypeC subsystem). This will happen in a delayed
> -- 
> 2.36.1
> 

Re: [Intel-gfx] [PATCH v2 03/39] drm/i915/gvt: Fix kernel-doc for intel_vgpu_*_resource()

[Rodrigo Vivi]

On Wed, Jul 13, 2022 at 09:11:51AM +0100, Mauro Carvalho Chehab wrote:
> From: Jiapeng Chong 
> 
> Fix the following W=1 kernel warnings:
> 
> drivers/gpu/drm/i915/gvt/aperture_gm.c:308: warning: expecting prototype
> for inte_gvt_free_vgpu_resource(). Prototype was for
> intel_vgpu_free_resource() instead.
> 
> drivers/gpu/drm/i915/gvt/aperture_gm.c:344: warning: expecting prototype
> for intel_alloc_vgpu_resource(). Prototype was for
> intel_vgpu_alloc_resource() instead.
> 
> Reported-by: Abaci Robot 
> Signed-off-by: Jiapeng Chong 
> Acked-by: Zhenyu Wang 
> Signed-off-by: Mauro Carvalho Chehab 
> ---
> 
> To avoid mailbombing on a large number of people, only mailing lists were C/C 
> on the cover.
> See [PATCH v2 00/39] at: 
> https://lore.kernel.org/all/cover.1657699522.git.mche...@kernel.org/
> 
>  drivers/gpu/drm/i915/gvt/aperture_gm.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c 
> b/drivers/gpu/drm/i915/gvt/aperture_gm.c
> index 557f3314291a..3b81a6d35a7b 100644
> --- a/drivers/gpu/drm/i915/gvt/aperture_gm.c
> +++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c
> @@ -298,7 +298,7 @@ static int alloc_resource(struct intel_vgpu *vgpu,
>  }
>  
>  /**
> - * inte_gvt_free_vgpu_resource - free HW resource owned by a vGPU
> + * intel_vgpu_free_resource() - free HW resource owned by a vGPU

with the consistency in the usage of "()" feel free to use

Reviewed-by: Rodrigo Vivi 



>   * @vgpu: a vGPU
>   *
>   * This function is used to free the HW resource owned by a vGPU.
> @@ -328,7 +328,7 @@ void intel_vgpu_reset_resource(struct intel_vgpu *vgpu)
>  }
>  
>  /**
> - * intel_alloc_vgpu_resource - allocate HW resource for a vGPU
> + * intel_vgpu_alloc_resource() - allocate HW resource for a vGPU
>   * @vgpu: vGPU
>   * @param: vGPU creation params
>   *
> -- 
> 2.36.1
> 

Re: [Intel-gfx] [PATCH v2 04/39] drm/i915: fix kernel-doc trivial warnings on i915/*.[ch] files

[Rodrigo Vivi]

On Wed, Jul 13, 2022 at 09:11:52AM +0100, Mauro Carvalho Chehab wrote:
> There are several trivial warnings there, due to trivial things:
>   - lack of function name at the kerneldoc markup;
>   - renamed functions;
>   - wrong parameter syntax.
> 
> Fix such warnings:
>   drivers/gpu/drm/i915/i915_active.h:66: warning: Function parameter or 
> member 'active' not described in '__i915_active_fence_init'
>   drivers/gpu/drm/i915/i915_active.h:66: warning: Function parameter or 
> member 'fence' not described in '__i915_active_fence_init'
>   drivers/gpu/drm/i915/i915_active.h:66: warning: Function parameter or 
> member 'fn' not described in '__i915_active_fence_init'
>   drivers/gpu/drm/i915/i915_active.h:89: warning: Function parameter or 
> member 'active' not described in 'i915_active_fence_set'
>   drivers/gpu/drm/i915/i915_active.h:89: warning: Function parameter or 
> member 'rq' not described in 'i915_active_fence_set'
>   drivers/gpu/drm/i915/i915_active.h:102: warning: Function parameter or 
> member 'active' not described in 'i915_active_fence_get'
>   drivers/gpu/drm/i915/i915_active.h:122: warning: Function parameter or 
> member 'active' not described in 'i915_active_fence_isset'
>   drivers/gpu/drm/i915/i915_gem.c:443: warning: This comment starts with 
> '/**', but isn't a kernel-doc comment. Refer 
> Documentation/doc-guide/kernel-doc.rst
>* Reads data from the object referenced by handle.
>   drivers/gpu/drm/i915/i915_gem.c:532: warning: This comment starts with 
> '/**', but isn't a kernel-doc comment. Refer 
> Documentation/doc-guide/kernel-doc.rst
>* This is the fast pwrite path, where we copy the data directly from 
> the
>   drivers/gpu/drm/i915/i915_gem.c:717: warning: This comment starts with 
> '/**', but isn't a kernel-doc comment. Refer 
> Documentation/doc-guide/kernel-doc.rst
>* Writes data to the object referenced by handle.
>   drivers/gpu/drm/i915/i915_gem.c:802: warning: This comment starts with 
> '/**', but isn't a kernel-doc comment. Refer 
> Documentation/doc-guide/kernel-doc.rst
>* Called when user space has done writes to this buffer
>   drivers/gpu/drm/i915/i915_pmu.h:22: warning: cannot understand function 
> prototype: 'enum i915_pmu_tracked_events '
>   drivers/gpu/drm/i915/i915_pmu.h:33: warning: cannot understand function 
> prototype: 'enum '
>   drivers/gpu/drm/i915/i915_pmu.h:42: warning: This comment starts with 
> '/**', but isn't a kernel-doc comment. Refer 
> Documentation/doc-guide/kernel-doc.rst
>* How many different events we track in the global PMU mask.
>   drivers/gpu/drm/i915/i915_request.h:177: warning: This comment starts 
> with '/**', but isn't a kernel-doc comment. Refer 
> Documentation/doc-guide/kernel-doc.rst
>* Request queue structure.
>   drivers/gpu/drm/i915/i915_request.h:473: warning: This comment starts 
> with '/**', but isn't a kernel-doc comment. Refer 
> Documentation/doc-guide/kernel-doc.rst
>* Returns true if seq1 is later than seq2.
>   drivers/gpu/drm/i915/i915_scatterlist.c:63: warning: Function parameter 
> or member 'size' not described in 'i915_refct_sgt_init'
>   drivers/gpu/drm/i915/i915_scatterlist.h:153: warning: Incorrect use of 
> kernel-doc format:  * release() - Free the memory of the struct 
> i915_refct_sgt
>   drivers/gpu/drm/i915/i915_scatterlist.h:157: warning: Function 
> parameter or member 'release' not described in 'i915_refct_sgt_ops'
>   drivers/gpu/drm/i915/i915_scatterlist.h:180: warning: Function 
> parameter or member 'rsgt' not described in 'i915_refct_sgt_put'
>   drivers/gpu/drm/i915/i915_scatterlist.h:191: warning: Function 
> parameter or member 'rsgt' not described in 'i915_refct_sgt_get'
>   drivers/gpu/drm/i915/i915_scatterlist.h:207: warning: Function 
> parameter or member 'rsgt' not described in '__i915_refct_sgt_init'
>   drivers/gpu/drm/i915/i915_utils.h:291: warning: Function parameter or 
> member 'OP' not described in '__wait_for'
>   drivers/gpu/drm/i915/i915_utils.h:291: warning: Function parameter or 
> member 'COND' not described in '__wait_for'
>   drivers/gpu/drm/i915/i915_utils.h:291: warning: Function parameter or 
> member 'US' not described in '__wait_for'
>   drivers/gpu/drm/i915/i915_utils.h:291: warning: Function parameter or 
> member 'Wmin' not described in '__wait_for'
>   drivers/gpu/drm/i915/i915_utils.h:291: warning: Function parameter or 
> member 'Wmax' not described in '__wait_for'
>   drivers/gpu/drm/i915/i915_vma_resource.h:88: warning: Incorrect use of 
> kernel-doc format:  * struct i915_vma_bindinfo - Information needed 
> for async bind
>   drivers/gpu/drm/i915/i915_vma_resource.h:123: warning: Function 
> parameter or member 'bi' not described in 'i915_vma_resource'
> 
> Signed-off-by: Mauro Carvalho Chehab 

functions should change to have "()" or not?
whatev

Re: [Intel-gfx] [PATCH v2 01/39] drm/i915/gvt: Fix kernel-doc for intel_gvt_switch_mmio()

[Rodrigo Vivi]

On Wed, Jul 13, 2022 at 05:54:44PM -0400, Rodrigo Vivi wrote:
> On Wed, Jul 13, 2022 at 09:11:49AM +0100, Mauro Carvalho Chehab wrote:
> > From: Jiapeng Chong 
> > 
> > Fix the following W=1 kernel warnings:
> > 
> > drivers/gpu/drm/i915/gvt/mmio_context.c:560: warning: expecting
> > prototype for intel_gvt_switch_render_mmio(). Prototype was for
> > intel_gvt_switch_mmio() instead.
> > 
> > Reported-by: Abaci Robot 
> > Signed-off-by: Jiapeng Chong 
> > Acked-by: Zhenyu Wang 
> > Signed-off-by: Mauro Carvalho Chehab 
> 
> Reviewed-by: Rodrigo Vivi 

I actually changed my mind after seeing that in most cases you use "()"
for the functions and you didn't use for this case...

which one should we pick for consistency?

> 
> > ---
> > 
> > To avoid mailbombing on a large number of people, only mailing lists were 
> > C/C on the cover.
> > See [PATCH v2 00/39] at: 
> > https://lore.kernel.org/all/cover.1657699522.git.mche...@kernel.org/
> > 
> >  drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c 
> > b/drivers/gpu/drm/i915/gvt/mmio_context.c
> > index c85bafe7539e..1c6e941c9666 100644
> > --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> > +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> > @@ -546,7 +546,7 @@ static void switch_mmio(struct intel_vgpu *pre,
> >  }
> >  
> >  /**
> > - * intel_gvt_switch_render_mmio - switch mmio context of specific engine
> > + * intel_gvt_switch_mmio - switch mmio context of specific engine
> >   * @pre: the last vGPU that own the engine
> >   * @next: the vGPU to switch to
> >   * @engine: the engine
> > -- 
> > 2.36.1
> > 

Re: [Intel-gfx] [PATCH v2 02/39] drm/i915/gvt: Fix kernel-doc for intel_vgpu_default_mmio_write

[Rodrigo Vivi]

On Wed, Jul 13, 2022 at 09:11:50AM +0100, Mauro Carvalho Chehab wrote:
> From: Jiapeng Chong 
> 
> Fix the following W=1 kernel warnings:
> 
> drivers/gpu/drm/i915/gvt/handlers.c:3066: warning: expecting prototype
> for intel_t_default_mmio_write(). Prototype was for
> intel_vgpu_default_mmio_write() instead.
> 
> Reported-by: Abaci Robot 
> Signed-off-by: Jiapeng Chong 
> Acked-by: Zhenyu Wang 
> Signed-off-by: Mauro Carvalho Chehab 

Reviewed-by: Rodrigo Vivi 

> ---
> 
> To avoid mailbombing on a large number of people, only mailing lists were C/C 
> on the cover.
> See [PATCH v2 00/39] at: 
> https://lore.kernel.org/all/cover.1657699522.git.mche...@kernel.org/
> 
>  drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c 
> b/drivers/gpu/drm/i915/gvt/handlers.c
> index beea5895e499..9c8dde079cb4 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -3052,7 +3052,7 @@ int intel_vgpu_default_mmio_read(struct intel_vgpu 
> *vgpu, unsigned int offset,
>  }
>  
>  /**
> - * intel_t_default_mmio_write - default MMIO write handler
> + * intel_vgpu_default_mmio_write() - default MMIO write handler
>   * @vgpu: a vGPU
>   * @offset: access offset
>   * @p_data: write data buffer
> -- 
> 2.36.1
> 

Re: [Intel-gfx] [PATCH v2 01/39] drm/i915/gvt: Fix kernel-doc for intel_gvt_switch_mmio()

[Rodrigo Vivi]

On Wed, Jul 13, 2022 at 09:11:49AM +0100, Mauro Carvalho Chehab wrote:
> From: Jiapeng Chong 
> 
> Fix the following W=1 kernel warnings:
> 
> drivers/gpu/drm/i915/gvt/mmio_context.c:560: warning: expecting
> prototype for intel_gvt_switch_render_mmio(). Prototype was for
> intel_gvt_switch_mmio() instead.
> 
> Reported-by: Abaci Robot 
> Signed-off-by: Jiapeng Chong 
> Acked-by: Zhenyu Wang 
> Signed-off-by: Mauro Carvalho Chehab 

Reviewed-by: Rodrigo Vivi 

> ---
> 
> To avoid mailbombing on a large number of people, only mailing lists were C/C 
> on the cover.
> See [PATCH v2 00/39] at: 
> https://lore.kernel.org/all/cover.1657699522.git.mche...@kernel.org/
> 
>  drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c 
> b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index c85bafe7539e..1c6e941c9666 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -546,7 +546,7 @@ static void switch_mmio(struct intel_vgpu *pre,
>  }
>  
>  /**
> - * intel_gvt_switch_render_mmio - switch mmio context of specific engine
> + * intel_gvt_switch_mmio - switch mmio context of specific engine
>   * @pre: the last vGPU that own the engine
>   * @next: the vGPU to switch to
>   * @engine: the engine
> -- 
> 2.36.1
> 

Re: [Intel-gfx] [PATCH] drm/i915/guc: Check for ct enabled while waiting for response

[Dong, Zhanjun]

> -Original Message-
> From: Dixit, Ashutosh 
> Sent: July 12, 2022 3:48 PM
> To: Dong, Zhanjun 
> Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/guc: Check for ct enabled while
> waiting for response
> 
> On Thu, 16 Jun 2022 21:50:55 -0700, Dixit, Ashutosh wrote:
> >
> > On Thu, 16 Jun 2022 15:01:59 -0700, Zhanjun Dong wrote:
> > >
> > > We are seeing error message of "No response for request". Some cases
> > > happened while waiting for response and reset/suspend action was
> triggered.
> > > In this case, no response is not an error, active requests will be
> > > cancelled.
> > >
> > > This patch will handle this condition and change the error message
> > > into debug message.
> > >
> > > Signed-off-by: Zhanjun Dong 
> > > ---
> > >  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 24
> > > ---
> > >  1 file changed, 17 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > > b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > > index f01325cd1b62..f07a7666b1ad 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > > @@ -455,6 +455,7 @@ static int ct_write(struct intel_guc_ct *ct,
> > >
> > >  /**
> > >   * wait_for_ct_request_update - Wait for CT request state update.
> > > + * @ct:  pointer to CT
> > >   * @req: pointer to pending request
> > >   * @status:  placeholder for status
> > >   *
> > > @@ -467,9 +468,10 @@ static int ct_write(struct intel_guc_ct *ct,
> > >   * * 0 response received (status is valid)
> > >   * * -ETIMEDOUT no response within hardcoded timeout
> > >   */
> > > -static int wait_for_ct_request_update(struct ct_request *req, u32
> > > *status)
> > > +static int wait_for_ct_request_update(struct intel_guc_ct *ct,
> > > +struct ct_request *req, u32 *status)
> > >  {
> > >   int err;
> > > + bool ct_enabled;
> > >
> > >   /*
> > >* Fast commands should complete in less than 10us, so sample
> > >quickly  @@ -481,12 +483,15 @@ static int
> > >wait_for_ct_request_update(struct ct_request *req, u32 *status)
> > >  #define GUC_CTB_RESPONSE_TIMEOUT_SHORT_MS 10
> > >  #define GUC_CTB_RESPONSE_TIMEOUT_LONG_MS 1000
> > >  #define done \
> > > - (FIELD_GET(GUC_HXG_MSG_0_ORIGIN, READ_ONCE(req->status)) ==
> \
> > > + (!(ct_enabled = intel_guc_ct_enabled(ct)) || \
> > > +  FIELD_GET(GUC_HXG_MSG_0_ORIGIN, READ_ONCE(req->status)) ==
> \
> > >GUC_HXG_ORIGIN_GUC)
> > >   err = wait_for_us(done, GUC_CTB_RESPONSE_TIMEOUT_SHORT_MS);
> > >   if (err)
> > >   err = wait_for(done,
> GUC_CTB_RESPONSE_TIMEOUT_LONG_MS);
> > >  #undef done
> > > + if (!ct_enabled)
> > > + err = -ECANCELED;
> >
> > Actually here's an even simpler suggestion. We could just do:
> >
> > if (!ct_enabled)
> > CT_DEBUG(ct, "Request %#x (fence %u) cancelled as CTB is
> disabled\n",
> >...);
> >
> > And return 0 as before. This way we won't have to make any changes in
> > either ct_send() or intel_guc_ct_send(). So intel_guc_ct_enabled()
> > just serves to get us out of the wait early and prevent the -ETIMEDOUT
> > return (and 0 return avoids all the error messages we are trying to
> eliminate).
> 
> Actually will need to unlink the request too, so it will be something like:
> 
>   if (!ct_enabled) {
>   CT_DEBUG(ct, "Request %#x (fence %u) cancelled as CTB is
> disabled\n", ...);
> 
>   spin_lock_irqsave(&ct->requests.lock, flags);
>   list_del(&request.link);
>   spin_unlock_irqrestore(&ct->requests.lock, flags);
>   }

I agree, the caller function need the err is non-zero to know the request is 
not success, and unlink the request.
The caller function ct_send will do the unlink.

For the err code ECANCELED, while in intel_guc_ct_send, it returns ENODEV if ct 
is disabled. This patch will be changed to ENODEV to match it.

[Intel-gfx] [PULL] drm-intel-fixes

[Rodrigo Vivi]

Hi Dave and Daniel,

On behalf of Jani, here goes the drm-intel-fixes targeting
5.19-rc7.

Please notice that this also includes the patches you already
pulled last week. But for some reason they are not in the
5.19-rc6 yet.

Well, we always use the official -rc as the base, but if it
gets easier for you to use the drm/drm-fixes this round just
let me know that I can force-push and generate another one
tomorrow.

But I hope the official dim flow works.

Thanks,
Rodrigo.

drm-intel-fixes-2022-07-13:
- Selftest fix (Andrzej)
- TTM fix sg_table construction (Matt Auld)
- Error return fixes (Dan)
- Fix a performance regression related to waitboost (Chri\
s)
- Fix GT resets (Chris)
- Fix a possible refcount leak in DP MST connector (Hangy\
u)
- Fix on loading guc on ADL-N (Daniele)
- Fix vm use-after-free in vma destruction (Thomas)

Thanks,
Rodrigo.

The following changes since commit 32346491ddf24599decca06190ebca03ff9de7f8:

  Linux 5.19-rc6 (2022-07-10 14:40:51 -0700)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2022-07-13

for you to fetch changes up to 333991c4e66b3d4b5613315f18016da80344f659:

  drm/i915/selftests: fix subtraction overflow bug (2022-07-12 18:21:58 -0400)


- Selftest fix (Andrzej)
- TTM fix sg_table construction (Matt Auld)
- Error return fixes (Dan)
- Fix a performance regression related to waitboost (Chri\
s)
- Fix GT resets (Chris)
- Fix a possible refcount leak in DP MST connector (Hangy\
u)
- Fix on loading guc on ADL-N (Daniele)
- Fix vm use-after-free in vma destruction (Thomas)


Andrzej Hajda (1):
  drm/i915/selftests: fix subtraction overflow bug

Chris Wilson (3):
  drm/i915/gt: Serialize GRDOM access between multiple engine resets
  drm/i915/gt: Serialize TLB invalidates with GT resets
  drm/i915/gem: Look for waitboosting across the whole object prior to 
individual waits

Dan Carpenter (2):
  drm/i915/gvt: IS_ERR() vs NULL bug in intel_gvt_update_reg_whitelist()
  drm/i915/selftests: fix a couple IS_ERR() vs NULL tests

Daniele Ceraolo Spurio (1):
  drm/i915/guc: ADL-N should use the same GuC FW as ADL-S

Hangyu Hua (1):
  drm/i915: fix a possible refcount leak in intel_dp_add_mst_connector()

Matthew Auld (1):
  drm/i915/ttm: fix sg_table construction

Rodrigo Vivi (1):
  Merge tag 'gvt-fixes-2022-07-11' of https://github.com/intel/gvt-linux 
into drm-intel-fixes

Thomas Hellström (1):
  drm/i915: Fix vm use-after-free in vma destruction

 drivers/gpu/drm/i915/display/intel_dp_mst.c|  1 +
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c| 11 +--
 drivers/gpu/drm/i915/gem/i915_gem_wait.c   | 34 
 drivers/gpu/drm/i915/gt/intel_gt.c | 15 -
 drivers/gpu/drm/i915/gt/intel_reset.c  | 37 --
 drivers/gpu/drm/i915/gt/selftest_lrc.c |  8 ++---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c   |  9 ++
 drivers/gpu/drm/i915/gvt/cmd_parser.c  |  6 ++--
 drivers/gpu/drm/i915/i915_scatterlist.c| 19 ---
 drivers/gpu/drm/i915/i915_scatterlist.h|  6 ++--
 drivers/gpu/drm/i915/i915_vma.c| 12 ---
 drivers/gpu/drm/i915/intel_region_ttm.c| 10 --
 drivers/gpu/drm/i915/intel_region_ttm.h|  3 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c  |  2 +-
 .../gpu/drm/i915/selftests/intel_memory_region.c   | 21 ++--
 drivers/gpu/drm/i915/selftests/mock_region.c   |  3 +-
 16 files changed, 160 insertions(+), 37 deletions(-)

[Intel-gfx] [PULL] drm-intel-gt-next

[Rodrigo Vivi]

Hi Dave and Daniel,

On behalf of Tvrtko, who is recovering from Covid,
here goes the latest drm-intel-gt-next pull request
targeting 5.20.

Thanks,
Rodrigo.

Driver uAPI changes:
- All related to the Small BAR support: (and all by Matt Auld)
 * add probed_cpu_visible_size
 * expose the avail memory region tracking
 * apply ALLOC_GPU only by default
 * add NEEDS_CPU_ACCESS hint
 * tweak error capture on recoverable contexts

Driver highlights:
- Add Small BAR support (Matt)
- Add MeteorLake support (RK)
- Add support for LMEM PCIe resizable BAR (Akeem)

Driver important fixes:
- ttm related fixes (Matt Auld)
- Fix a performance regression related to waitboost (Chris)
- Fix GT resets (Chris)

Driver others:
- Adding GuC SLPC selftest (Vinay)
- Fix ADL-N GuC load (Daniele)
- Add platform workaround (Gustavo, Matt Roper)
- DG2 and ATS-M device ID updates (Matt Roper)
- Add VM_BIND doc rfc with uAPI documentation (Niranjana)
- Fix user-after-free in vma destruction (Thomas)
- Async flush of GuC log regions (Alan)
- Fixes in selftests (Chris, Dan, Andrzej)
- Convert to drm_dbg (Umesh)
- Disable OA sseu config param for newer hardware (Umesh)
- Multi-cast register steering changes (Matt Roper)
- Add lmem_bar_size modparam (Priyanka)

Thanks,
Rodrigo.

The following changes since commit a06968563775181690125091f470a8655742dcbf:

  drm/i915: Fix a lockdep warning at error capture (2022-06-29 14:52:50 +0530)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-gt-next-2022-07-13

for you to fetch changes up to 17cd10a44a8962860ff4ba351b2a290e752dbbde:

  drm/i915: Add lmem_bar_size modparam (2022-07-13 17:47:51 +0100)


Driver uAPI changes:
- All related to the Small BAR support: (and all by Matt Auld)
 * add probed_cpu_visible_size
 * expose the avail memory region tracking
 * apply ALLOC_GPU only by default
 * add NEEDS_CPU_ACCESS hint
 * tweak error capture on recoverable contexts

Driver highlights:
- Add Small BAR support (Matt)
- Add MeteorLake support (RK)
- Add support for LMEM PCIe resizable BAR (Akeem)

Driver important fixes:
- ttm related fixes (Matt Auld)
- Fix a performance regression related to waitboost (Chris)
- Fix GT resets (Chris)

Driver others:
- Adding GuC SLPC selftest (Vinay)
- Fix ADL-N GuC load (Daniele)
- Add platform workaround (Gustavo, Matt Roper)
- DG2 and ATS-M device ID updates (Matt Roper)
- Add VM_BIND doc rfc with uAPI documentation (Niranjana)
- Fix user-after-free in vma destruction (Thomas)
- Async flush of GuC log regions (Alan)
- Fixes in selftests (Chris, Dan, Andrzej)
- Convert to drm_dbg (Umesh)
- Disable OA sseu config param for newer hardware (Umesh)
- Multi-cast register steering changes (Matt Roper)
- Add lmem_bar_size modparam (Priyanka)


Akeem G Abodunrin (1):
  drm/i915: Add support for LMEM PCIe resizable bar

Alan Previn (1):
  drm/i915/guc: Asynchronous flush of GuC log regions

Andrzej Hajda (1):
  drm/i915/selftests: fix subtraction overflow bug

Chris Wilson (6):
  drm/i915/selftests: Grab the runtime pm in shrink_thp
  drm/i915/gt: Serialize GRDOM access between multiple engine resets
  drm/i915/gt: Serialize TLB invalidates with GT resets
  drm/i915/gem: Look for waitboosting across the whole object prior to 
individual waits
  drm/i915: Bump GT idling delay to 2 jiffies
  drm/i915/gt: Only kick the signal worker if there's been an update

Dan Carpenter (1):
  drm/i915/selftests: fix a couple IS_ERR() vs NULL tests

Daniele Ceraolo Spurio (1):
  drm/i915/guc: ADL-N should use the same GuC FW as ADL-S

Gustavo Sousa (1):
  drm/i915/pvc: Implement w/a 16016694945

Matt Roper (4):
  drm/i915: DG2 and ATS-M device ID updates
  drm/i915/gt: Add general DSS steering iterator to intel_gt_mcr
  drm/i915/dg2: Add Wa_15010599737
  drm/i915: Correct ss -> steering calculation for pre-Xe_HP platforms

Matthew Auld (15):
  drm/doc: add rfc section for small BAR uapi
  drm/i915/uapi: add probed_cpu_visible_size
  drm/i915/uapi: expose the avail tracking
  drm/i915: remove intel_memory_region avail
  drm/i915/uapi: apply ALLOC_GPU_ONLY by default
  drm/i915/uapi: add NEEDS_CPU_ACCESS hint
  drm/i915/error: skip non-mappable pages
  drm/i915/uapi: tweak error capture on recoverable contexts
  drm/i915/selftests: skip the mman tests for stolen
  drm/i915/selftests: ensure we reserve a fence slot
  drm/i915/ttm: handle blitter failure on DG2
  drm/i915/ttm: disallow CPU fallback mode for ccs pages
  drm/i915: turn on small BAR support
  drm/i915/ttm: fix sg_table construction
  drm/i915/ttm: fix 32b build

Niranjana Vishwanathapura (3):
  drm/doc/rfc: VM_BIND feature design document
  drm/i915: Update i915 uapi documentation
  drm/doc/rfc: VM_BIND uapi definition

Re: [Intel-gfx] [PATCH v2] drm/i915/display: Ensure PSR gets disabled if no encoders in new state

[Souza, Jose]

On Wed, 2022-07-13 at 20:58 +, Souza, Jose wrote:
> On Mon, 2022-07-11 at 14:17 +0300, Jouni Högander wrote:
> > Currently PSR is left enabled when all planes are disabled if there
> > is no attached encoder in new state. This seems to be causing FIFO
> > underruns.
> 
> What is the case were there is no attached encoder and active_planes > 0?

Can you point to some test?
I believe that a pipe to be enabled needs to have a enconder/port attached, 
otherwise it will be disabled. 

> 
> > 
> > Fix this by checking if encoder exists in new crtc state and disable
> > PSR if it doesn't.
> > 
> > v2: Unify disable logic with existing
> > 
> > Cc: Mika Kahola 
> > Reported-by: Stanislav Lisovskiy 
> > Signed-off-by: Jouni Högander 
> > Signed-off-by: Stanislav Lisovskiy 
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 53 ++--
> >  1 file changed, 31 insertions(+), 22 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index e6a870641cd2..90599dd1cb1b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1863,36 +1863,45 @@ void intel_psr_pre_plane_update(struct 
> > intel_atomic_state *state,
> > struct intel_crtc *crtc)
> >  {
> > struct drm_i915_private *i915 = to_i915(state->base.dev);
> > -   const struct intel_crtc_state *crtc_state =
> > -   intel_atomic_get_new_crtc_state(state, crtc);
> > -   struct intel_encoder *encoder;
> > +   struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> > +   int i;
> >  
> > if (!HAS_PSR(i915))
> > return;
> >  
> > -   for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
> > -crtc_state->uapi.encoder_mask) {
> > -   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > -   struct intel_psr *psr = &intel_dp->psr;
> > -   bool needs_to_disable = false;
> > +   for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > +   new_crtc_state, i) {
> > +   struct intel_encoder *encoder;
> > +   u32 old_new_encoder_mask = old_crtc_state->uapi.encoder_mask |
> > +   new_crtc_state->uapi.encoder_mask;
> >  
> > -   mutex_lock(&psr->lock);
> > +   for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
> > +old_new_encoder_mask) {
> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +   struct intel_psr *psr = &intel_dp->psr;
> > +   bool needs_to_disable = false;
> >  
> > -   /*
> > -* Reasons to disable:
> > -* - PSR disabled in new state
> > -* - All planes will go inactive
> > -* - Changing between PSR versions
> > -*/
> > -   needs_to_disable |= intel_crtc_needs_modeset(crtc_state);
> > -   needs_to_disable |= !crtc_state->has_psr;
> > -   needs_to_disable |= !crtc_state->active_planes;
> > -   needs_to_disable |= crtc_state->has_psr2 != psr->psr2_enabled;
> > +   mutex_lock(&psr->lock);
> >  
> > -   if (psr->enabled && needs_to_disable)
> > -   intel_psr_disable_locked(intel_dp);
> > +   /*
> > +* Reasons to disable:
> > +* - PSR disabled in new state
> > +* - All planes will go inactive
> > +* - Changing between PSR versions
> > +* - Encoder isn't present in new mask
> > +*/
> > +   needs_to_disable |= 
> > intel_crtc_needs_modeset(new_crtc_state);
> > +   needs_to_disable |= !new_crtc_state->has_psr;
> > +   needs_to_disable |= !new_crtc_state->active_planes;
> > +   needs_to_disable |= new_crtc_state->has_psr2 != 
> > psr->psr2_enabled;
> > +   needs_to_disable |= !(new_crtc_state->uapi.encoder_mask 
> > &
> > + 
> > drm_encoder_mask(&(encoder)->base));
> >  
> > -   mutex_unlock(&psr->lock);
> > +   if (psr->enabled && needs_to_disable)
> > +   intel_psr_disable_locked(intel_dp);
> > +
> > +   mutex_unlock(&psr->lock);
> > +   }
> > }
> >  }
> >  
> 

Re: [Intel-gfx] [PATCH v2] drm/i915/display: Ensure PSR gets disabled if no encoders in new state

[Souza, Jose]

On Mon, 2022-07-11 at 14:17 +0300, Jouni Högander wrote:
> Currently PSR is left enabled when all planes are disabled if there
> is no attached encoder in new state. This seems to be causing FIFO
> underruns.

What is the case were there is no attached encoder and active_planes > 0?

> 
> Fix this by checking if encoder exists in new crtc state and disable
> PSR if it doesn't.
> 
> v2: Unify disable logic with existing
> 
> Cc: Mika Kahola 
> Reported-by: Stanislav Lisovskiy 
> Signed-off-by: Jouni Högander 
> Signed-off-by: Stanislav Lisovskiy 
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 53 ++--
>  1 file changed, 31 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index e6a870641cd2..90599dd1cb1b 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1863,36 +1863,45 @@ void intel_psr_pre_plane_update(struct 
> intel_atomic_state *state,
>   struct intel_crtc *crtc)
>  {
>   struct drm_i915_private *i915 = to_i915(state->base.dev);
> - const struct intel_crtc_state *crtc_state =
> - intel_atomic_get_new_crtc_state(state, crtc);
> - struct intel_encoder *encoder;
> + struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> + int i;
>  
>   if (!HAS_PSR(i915))
>   return;
>  
> - for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
> -  crtc_state->uapi.encoder_mask) {
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> - struct intel_psr *psr = &intel_dp->psr;
> - bool needs_to_disable = false;
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> + new_crtc_state, i) {
> + struct intel_encoder *encoder;
> + u32 old_new_encoder_mask = old_crtc_state->uapi.encoder_mask |
> + new_crtc_state->uapi.encoder_mask;
>  
> - mutex_lock(&psr->lock);
> + for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
> +  old_new_encoder_mask) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> + struct intel_psr *psr = &intel_dp->psr;
> + bool needs_to_disable = false;
>  
> - /*
> -  * Reasons to disable:
> -  * - PSR disabled in new state
> -  * - All planes will go inactive
> -  * - Changing between PSR versions
> -  */
> - needs_to_disable |= intel_crtc_needs_modeset(crtc_state);
> - needs_to_disable |= !crtc_state->has_psr;
> - needs_to_disable |= !crtc_state->active_planes;
> - needs_to_disable |= crtc_state->has_psr2 != psr->psr2_enabled;
> + mutex_lock(&psr->lock);
>  
> - if (psr->enabled && needs_to_disable)
> - intel_psr_disable_locked(intel_dp);
> + /*
> +  * Reasons to disable:
> +  * - PSR disabled in new state
> +  * - All planes will go inactive
> +  * - Changing between PSR versions
> +  * - Encoder isn't present in new mask
> +  */
> + needs_to_disable |= 
> intel_crtc_needs_modeset(new_crtc_state);
> + needs_to_disable |= !new_crtc_state->has_psr;
> + needs_to_disable |= !new_crtc_state->active_planes;
> + needs_to_disable |= new_crtc_state->has_psr2 != 
> psr->psr2_enabled;
> + needs_to_disable |= !(new_crtc_state->uapi.encoder_mask 
> &
> +   
> drm_encoder_mask(&(encoder)->base));
>  
> - mutex_unlock(&psr->lock);
> + if (psr->enabled && needs_to_disable)
> + intel_psr_disable_locked(intel_dp);
> +
> + mutex_unlock(&psr->lock);
> + }
>   }
>  }
>  

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: stop HPD workers before display driver unregister (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/display: stop HPD workers before display driver unregister 
(rev5)
URL   : https://patchwork.freedesktop.org/series/105557/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11877 -> Patchwork_105557v5


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/index.html

Participating hosts (39 -> 33)
--

  Additional (1): bat-jsl-3 
  Missing(7): fi-rkl-11600 bat-dg1-5 bat-dg2-8 bat-adlp-6 bat-adln-1 
bat-rpls-2 bat-jsl-1 

Known issues


  Here are the changes found in Patchwork_105557v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick:[PASS][1] -> [DMESG-FAIL][2] ([i915#3428])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html

  * 
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka:   [PASS][3] -> [FAIL][4] ([i915#6298])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html

  * igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][5] ([fdo#109271] / [i915#4312])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/fi-bsw-nick/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_module_load@load:
- {fi-tgl-dsi}:   [DMESG-WARN][6] ([i915#1982]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-tgl-dsi/igt@i915_module_l...@load.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/fi-tgl-dsi/igt@i915_module_l...@load.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298


Build changes
-

  * Linux: CI_DRM_11877 -> Patchwork_105557v5

  CI-20190529: 20190529
  CI_DRM_11877: e55cefc370de5a38ee848aa96082d9d9f4cacdb9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6578: 7d289d89131ec37c1145bcdb86149914587d7406 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_105557v5: e55cefc370de5a38ee848aa96082d9d9f4cacdb9 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

c43a83715cc6 drm/i915/display: add hotplug.suspended flag
5e5a685335ad drm/i915/fbdev: suspend HPD before fbdev unregistration
67a933d3c309 drm/i915/hpd: postpone HPD cancel work after last user suspension

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v5/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: stop HPD workers before display driver unregister (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/display: stop HPD workers before display driver unregister 
(rev5)
URL   : https://patchwork.freedesktop.org/series/105557/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Random assortment of (mostly) GuC related patches (rev2)

[Patchwork]

== Series Details ==

Series: Random assortment of (mostly) GuC related patches (rev2)
URL   : https://patchwork.freedesktop.org/series/106272/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11877 -> Patchwork_106272v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/index.html

Participating hosts (39 -> 39)
--

  Additional (5): bat-adlm-1 bat-dg2-9 bat-adlp-4 bat-jsl-3 bat-rpls-1 
  Missing(5): fi-kbl-soraka fi-bxt-dsi fi-rkl-11600 bat-dg1-5 bat-adln-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_106272v2:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- {bat-adlm-1}:   NOTRUN -> [SKIP][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/bat-adlm-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  
New tests
-

  New tests have been introduced between CI_DRM_11877 and Patchwork_106272v2:

### New IGT tests (1) ###

  * igt@i915_selftest@live@guc_hang:
- Statuses : 1 dmesg-warn(s) 31 pass(s)
- Exec time: [0.42, 4.13] s

  

Known issues


  Here are the changes found in Patchwork_106272v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@verify-random:
- bat-adlp-4: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/bat-adlp-4/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_tiled_pread_basic:
- bat-adlp-4: NOTRUN -> [SKIP][3] ([i915#3282])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/bat-adlp-4/igt@gem_tiled_pread_basic.html

  * igt@i915_selftest@live@gem:
- fi-blb-e6850:   NOTRUN -> [DMESG-FAIL][4] ([i915#4528])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/fi-blb-e6850/igt@i915_selftest@l...@gem.html

  * {igt@i915_selftest@live@guc_hang} (NEW):
- {bat-dg2-8}:NOTRUN -> [DMESG-WARN][5] ([i915#5763])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/bat-dg2-8/igt@i915_selftest@live@guc_hang.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [PASS][6] -> [INCOMPLETE][7] ([i915#3303] / 
[i915#4785])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
- fi-snb-2600:[PASS][8] -> [INCOMPLETE][9] ([i915#3921])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-adlp-4: NOTRUN -> [SKIP][10] ([i915#5903])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/bat-adlp-4/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@dp-crc-fast:
- bat-adlp-4: NOTRUN -> [SKIP][11] ([fdo#111827]) +8 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/bat-adlp-4/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-adlp-4: NOTRUN -> [SKIP][12] ([i915#4103])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/bat-adlp-4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-adlp-4: NOTRUN -> [SKIP][13] ([i915#4093]) +3 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/bat-adlp-4/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-adlp-4: NOTRUN -> [SKIP][14] ([i915#3555] / [i915#4579])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/bat-adlp-4/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- bat-adlp-4: NOTRUN -> [SKIP][15] ([fdo#109295] / [i915#3301] / 
[i915#3708])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/bat-adlp-4/igt@prime_v...@basic-userptr.html

  * igt@prime_vgem@basic-write:
- bat-adlp-4: NOTRUN -> [SKIP][16] ([fdo#109295] / [i915#3291] / 
[i915#3708]) +2 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v2/bat-adlp-4/igt@prime_v...@basic-write.html

  * igt@runner@aborted:
- fi-hsw-g3258:   NOTRUN -> [FAIL][17] ([fdo#109271] / [i915#4312] / 
[i915#6246])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwo

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Random assortment of (mostly) GuC related patches (rev2)

[Patchwork]

== Series Details ==

Series: Random assortment of (mostly) GuC related patches (rev2)
URL   : https://patchwork.freedesktop.org/series/106272/
State : warning

== Summary ==

Error: dim checkpatch failed
dea3dbd81ade drm/i915: Remove bogus GEM_BUG_ON in unpark
909eeb72fb3d drm/i915/guc: Don't call ring_is_idle in GuC submission
53760fb38f4a drm/i915/guc: Fix issues with live_preempt_cancel
f56a0551c6ad drm/i915/guc: Add GuC <-> kernel time stamp translation information
9ec48f9590e4 drm/i915/guc: Record CTB info in error logs
9de35e4d864c drm/i915/guc: Use streaming loads to speed up dumping the guc log
263f1e938c10 drm/i915/guc: Route semaphores to GuC for Gen12+
cf9a04633964 drm/i915/guc: Add selftest for a hung GuC
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:22: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#22: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 170 lines checked
e9a1fdbc7625 drm/i915/selftest: Cope with not having an RCS engine
6bac7cf93b56 drm/i915/guc: Support larger contexts on newer hardware
4d462f42d5f1 drm/i915/guc: Don't abort on CTB_UNUSED status
85fefd30d816 drm/i915/guc: Add a helper for log buffer size

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: stop HPD workers before display driver unregister (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/display: stop HPD workers before display driver unregister 
(rev4)
URL   : https://patchwork.freedesktop.org/series/105557/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11877 -> Patchwork_105557v4


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v4/index.html

Participating hosts (39 -> 39)
--

  Additional (4): bat-rpls-1 bat-adlm-1 bat-dg2-9 bat-adlp-4 
  Missing(4): bat-rpls-2 fi-bxt-dsi bat-adln-1 bat-dg1-5 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105557v4:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- {bat-adlm-1}:   NOTRUN -> [SKIP][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v4/bat-adlm-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  
Known issues


  Here are the changes found in Patchwork_105557v4 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@verify-random:
- bat-adlp-4: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v4/bat-adlp-4/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_tiled_pread_basic:
- bat-adlp-4: NOTRUN -> [SKIP][3] ([i915#3282])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v4/bat-adlp-4/igt@gem_tiled_pread_basic.html

  * igt@i915_selftest@live@hangcheck:
- fi-ivb-3770:[PASS][4] -> [INCOMPLETE][5] ([i915#3303] / 
[i915#5370])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v4/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html
- fi-snb-2600:[PASS][6] -> [INCOMPLETE][7] ([i915#3921])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v4/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@mman:
- fi-bdw-5557u:   [PASS][8] -> [INCOMPLETE][9] ([i915#5704])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-bdw-5557u/igt@i915_selftest@l...@mman.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v4/fi-bdw-5557u/igt@i915_selftest@l...@mman.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-adlp-4: NOTRUN -> [SKIP][10] ([i915#5903])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v4/bat-adlp-4/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@dp-crc-fast:
- bat-adlp-4: NOTRUN -> [SKIP][11] ([fdo#111827]) +8 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v4/bat-adlp-4/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-adlp-4: NOTRUN -> [SKIP][12] ([i915#4103])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v4/bat-adlp-4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [PASS][13] -> [FAIL][14] ([i915#6298])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v4/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-adlp-4: NOTRUN -> [SKIP][15] ([i915#4093]) +3 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v4/bat-adlp-4/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-adlp-4: NOTRUN -> [SKIP][16] ([i915#3555] / [i915#4579])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v4/bat-adlp-4/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- bat-adlp-4: NOTRUN -> [SKIP][17] ([fdo#109295] / [i915#3301] / 
[i915#3708])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v4/bat-adlp-4/igt@prime_v...@basic-userptr.html

  * igt@prime_vgem@basic-write:
- bat-adlp-4: NOTRUN -> [SKIP][18] ([fdo#109295] / [i915#3291] / 
[i915#3708]) +2 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v4/bat-adlp-4/igt@prime_v...@basic-write.html

  * igt@runner@aborted:
- fi-ivb-3770:NOTRUN -> [FAIL][19] ([fdo#109271] / 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: stop HPD workers before display driver unregister (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/display: stop HPD workers before display driver unregister 
(rev4)
URL   : https://patchwork.freedesktop.org/series/105557/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: ttm for stolen (rev9)

[Patchwork]

== Series Details ==

Series: drm/i915: ttm for stolen (rev9)
URL   : https://patchwork.freedesktop.org/series/101396/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11877_full -> Patchwork_101396v9_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_101396v9_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_101396v9_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 12)
--

  Missing(1): shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_101396v9_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@reset:
- shard-skl:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/shard-skl1/igt@i915_selftest@l...@reset.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-glk:  [PASS][2] -> [FAIL][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-glk7/igt@kms_big...@y-tiled-8bpp-rotate-180.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/shard-glk5/igt@kms_big...@y-tiled-8bpp-rotate-180.html

  * igt@kms_plane_cursor@pipe-d-overlay-size-256:
- shard-tglb: [PASS][4] -> [INCOMPLETE][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-tglb1/igt@kms_plane_cur...@pipe-d-overlay-size-256.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/shard-tglb8/igt@kms_plane_cur...@pipe-d-overlay-size-256.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_rotation_crc@sprite-rotation-270:
- {shard-rkl}:NOTRUN -> [INCOMPLETE][6]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/shard-rkl-6/igt@kms_rotation_...@sprite-rotation-270.html

  
Known issues


  Here are the changes found in Patchwork_101396v9_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-apl:  [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +4 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-apl6/igt@gem_ctx_isolation@preservation...@vecs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/shard-apl4/igt@gem_ctx_isolation@preservation...@vecs0.html

  * igt@gem_eio@kms:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#5784])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-tglb7/igt@gem_...@kms.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/shard-tglb3/igt@gem_...@kms.html

  * igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][11] -> [TIMEOUT][12] ([i915#3070])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-iclb1/igt@gem_...@unwedge-stress.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/shard-iclb1/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][13] -> [SKIP][14] ([i915#4525])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-iclb1/igt@gem_exec_balan...@parallel-balancer.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/shard-iclb7/igt@gem_exec_balan...@parallel-balancer.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][17] ([i915#2842])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][18] -> [FAIL][19] ([i915#2842])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
- shard-tglb: [PASS][20] -> [FAIL][21] ([i915#2842])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: ttm for internal (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: ttm for internal (rev3)
URL   : https://patchwork.freedesktop.org/series/104909/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11877_full -> Patchwork_104909v3_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_104909v3_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_104909v3_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 12)
--

  Missing(1): shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_104909v3_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_fair@basic-deadline:
- shard-kbl:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-kbl7/igt@gem_exec_f...@basic-deadline.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/shard-kbl7/igt@gem_exec_f...@basic-deadline.html

  * igt@i915_selftest@perf@region:
- shard-skl:  [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl5/igt@i915_selftest@p...@region.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/shard-skl6/igt@i915_selftest@p...@region.html

  
 Warnings 

  * igt@device_reset@unbind-reset-rebind:
- shard-snb:  [DMESG-WARN][5] ([i915#4528]) -> [DMESG-WARN][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-snb2/igt@device_re...@unbind-reset-rebind.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/shard-snb2/igt@device_re...@unbind-reset-rebind.html

  
Known issues


  Here are the changes found in Patchwork_104909v3_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_busy@close-race:
- shard-snb:  [PASS][7] -> [INCOMPLETE][8] ([i915#6234])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-snb4/igt@gem_b...@close-race.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/shard-snb5/igt@gem_b...@close-race.html

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl:  [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +11 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-kbl1/igt@gem_ctx_isolation@preservation...@vcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/shard-kbl6/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@gem_eio@kms:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#5784])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-tglb7/igt@gem_...@kms.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/shard-tglb1/igt@gem_...@kms.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar 
issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-iclb1/igt@gem_exec_fair@basic-p...@vecs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/shard-iclb2/igt@gem_exec_fair@basic-p...@vecs0.html
- shard-kbl:  [PASS][17] -> [SKIP][18] ([fdo#109271])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-kbl1/igt@gem_exec_fair@basic-p...@vecs0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
- shard-skl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/shard-skl9/igt@gem_lmem_swapp...@heavy-verify-multi.html

  * igt@gem_lmem_swapping@heavy-verify-random:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#4613])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/shard-tglb7/igt@gem_lmem_swapp...@heavy-verify-random.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-kbl:  NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/shard-kbl7/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-kbl:  NOTRUN -> [WARN][22] ([i915#2658])
   [22]: 
http

Re: [Intel-gfx] [PATCH v2 27/29] ACPI: video: Drop Clevo/TUXEDO NL5xRU and NL5xNU acpi_backlight=native quirks

[Werner Sembach]

Hi,

On 7/12/22 21:39, Hans de Goede wrote:

acpi_backlight=native is the default for these, but as the comment
explains the quirk was still necessary because even briefly registering
the acpi_video0 backlight; and then unregistering it once the native
driver showed up, was leading to issues.

After the "ACPI: video: Make backlight class device registration
a separate step" patch from earlier in this patch-series, we no
longer briefly register the acpi_video0 backlight on systems where
the native driver should be used.

So this is no longer an issue an the quirks are no longer needed.

Cc: Werner Sembach 
Signed-off-by: Hans de Goede 


Tested and can confirm: The quirks are no longer needed with this Patchset.

Tested-by: Werner Sembach 

Kind Regards,

Werner Sembach


---
  drivers/acpi/video_detect.c | 75 -
  1 file changed, 75 deletions(-)

diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c
index 2a4d376a703e..4b9395d1bda7 100644
--- a/drivers/acpi/video_detect.c
+++ b/drivers/acpi/video_detect.c
@@ -599,81 +599,6 @@ static const struct dmi_system_id video_detect_dmi_table[] 
= {
DMI_MATCH(DMI_BOARD_NAME, "N250P"),
},
},
-   /*
-* Clevo NL5xRU and NL5xNU/TUXEDO Aura 15 Gen1 and Gen2 have both a
-* working native and video interface. However the default detection
-* mechanism first registers the video interface before unregistering
-* it again and switching to the native interface during boot. This
-* results in a dangling SBIOS request for backlight change for some
-* reason, causing the backlight to switch to ~2% once per boot on the
-* first power cord connect or disconnect event. Setting the native
-* interface explicitly circumvents this buggy behaviour, by avoiding
-* the unregistering process.
-*/
-   {
-   .callback = video_detect_force_native,
-   .ident = "Clevo NL5xRU",
-   .matches = {
-   DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"),
-   DMI_MATCH(DMI_BOARD_NAME, "NL5xRU"),
-   },
-   },
-   {
-   .callback = video_detect_force_native,
-   .ident = "Clevo NL5xRU",
-   .matches = {
-   DMI_MATCH(DMI_SYS_VENDOR, "SchenkerTechnologiesGmbH"),
-   DMI_MATCH(DMI_BOARD_NAME, "NL5xRU"),
-   },
-   },
-   {
-   .callback = video_detect_force_native,
-   .ident = "Clevo NL5xRU",
-   .matches = {
-   DMI_MATCH(DMI_SYS_VENDOR, "Notebook"),
-   DMI_MATCH(DMI_BOARD_NAME, "NL5xRU"),
-   },
-   },
-   {
-   .callback = video_detect_force_native,
-   .ident = "Clevo NL5xRU",
-   .matches = {
-   DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"),
-   DMI_MATCH(DMI_BOARD_NAME, "AURA1501"),
-   },
-   },
-   {
-   .callback = video_detect_force_native,
-   .ident = "Clevo NL5xRU",
-   .matches = {
-   DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"),
-   DMI_MATCH(DMI_BOARD_NAME, "EDUBOOK1502"),
-   },
-   },
-   {
-   .callback = video_detect_force_native,
-   .ident = "Clevo NL5xNU",
-   .matches = {
-   DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"),
-   DMI_MATCH(DMI_BOARD_NAME, "NL5xNU"),
-   },
-   },
-   {
-   .callback = video_detect_force_native,
-   .ident = "Clevo NL5xNU",
-   .matches = {
-   DMI_MATCH(DMI_SYS_VENDOR, "SchenkerTechnologiesGmbH"),
-   DMI_MATCH(DMI_BOARD_NAME, "NL5xNU"),
-   },
-   },
-   {
-   .callback = video_detect_force_native,
-   .ident = "Clevo NL5xNU",
-   .matches = {
-   DMI_MATCH(DMI_SYS_VENDOR, "Notebook"),
-   DMI_MATCH(DMI_BOARD_NAME, "NL5xNU"),
-   },
-   },
  
  	/*

 * Desktops which falsely report a backlight and which our heuristics

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Correct ss -> steering calculation for pre-Xe_HP platforms

[Vudum, Lakshminarayana]

We are tracking igt@i915_selftest@live@hangcheck failures with no logs here
https://gitlab.freedesktop.org/drm/intel/-/issues/6172
igt@i915_selftest@live@hangcheck - incomplete - No warnings/errors

Lakshmi.
-Original Message-
From: Roper, Matthew D  
Sent: Wednesday, July 13, 2022 9:26 AM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana 
Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915: Correct ss -> steering 
calculation for pre-Xe_HP platforms

On Wed, Jul 13, 2022 at 03:50:35AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Correct ss -> steering calculation for pre-Xe_HP platforms
> URL   : https://patchwork.freedesktop.org/series/106269/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_11877_full -> Patchwork_106269v1_full
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_106269v1_full absolutely need 
> to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_106269v1_full, please notify your bug team to allow 
> them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (13 -> 13)
> --
> 
>   No changes in participating hosts
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_106269v1_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@i915_selftest@live@hangcheck:
> - shard-skl:  NOTRUN -> [INCOMPLETE][1]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106269v1/shard-skl9/igt@i915_selftest@l...@hangcheck.html

Random incomplete (logs cut off abruptly with no errors reported).  Does
not appear to be related to this patch.

Patch applied to drm-intel-gt-next.  Thanks Lucas for the review.


Matt

> 
>   
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * igt@drm_buddy@all:
> - {shard-dg1}:NOTRUN -> [SKIP][2] +4 similar issues
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106269v1/shard-dg1-15/igt@drm_bu...@all.html
> 
>   * igt@kms_setmode@clone-exclusive-crtc:
> - {shard-dg1}:NOTRUN -> [INCOMPLETE][3]
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106269v1/shard-dg1-16/igt@kms_setm...@clone-exclusive-crtc.html
> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_106269v1_full that come from known 
> issues:
> 
> ### CI changes ###
> 
>  Issues hit 
> 
>   * boot:
> - shard-skl:  ([PASS][4], [PASS][5], [PASS][6], [PASS][7], 
> [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], 
> [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], 
> [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24]) -> ([PASS][25], 
> [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], 
> [PASS][32], [PASS][33], [PASS][34], [FAIL][35], [PASS][36], [PASS][37], 
> [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], 
> [PASS][44]) ([i915#5032])
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl9/boot.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl9/boot.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl7/boot.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl7/boot.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl6/boot.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl6/boot.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl5/boot.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl5/boot.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl4/boot.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl4/boot.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl4/boot.html
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl3/boot.html
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl3/boot.html
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl2/boot.html
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl2/boot.html
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl1/boot.html
>[20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl1/boot.html
>[21]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl1/boot.html
>[22]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/sh

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Correct ss -> steering calculation for pre-Xe_HP platforms

[Matt Roper]

On Wed, Jul 13, 2022 at 03:50:35AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Correct ss -> steering calculation for pre-Xe_HP platforms
> URL   : https://patchwork.freedesktop.org/series/106269/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_11877_full -> Patchwork_106269v1_full
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_106269v1_full absolutely need 
> to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_106269v1_full, please notify your bug team to allow 
> them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (13 -> 13)
> --
> 
>   No changes in participating hosts
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_106269v1_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@i915_selftest@live@hangcheck:
> - shard-skl:  NOTRUN -> [INCOMPLETE][1]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106269v1/shard-skl9/igt@i915_selftest@l...@hangcheck.html

Random incomplete (logs cut off abruptly with no errors reported).  Does
not appear to be related to this patch.

Patch applied to drm-intel-gt-next.  Thanks Lucas for the review.


Matt

> 
>   
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * igt@drm_buddy@all:
> - {shard-dg1}:NOTRUN -> [SKIP][2] +4 similar issues
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106269v1/shard-dg1-15/igt@drm_bu...@all.html
> 
>   * igt@kms_setmode@clone-exclusive-crtc:
> - {shard-dg1}:NOTRUN -> [INCOMPLETE][3]
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106269v1/shard-dg1-16/igt@kms_setm...@clone-exclusive-crtc.html
> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_106269v1_full that come from known 
> issues:
> 
> ### CI changes ###
> 
>  Issues hit 
> 
>   * boot:
> - shard-skl:  ([PASS][4], [PASS][5], [PASS][6], [PASS][7], 
> [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], 
> [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], 
> [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24]) -> ([PASS][25], 
> [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], 
> [PASS][32], [PASS][33], [PASS][34], [FAIL][35], [PASS][36], [PASS][37], 
> [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], 
> [PASS][44]) ([i915#5032])
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl9/boot.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl9/boot.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl7/boot.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl7/boot.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl6/boot.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl6/boot.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl5/boot.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl5/boot.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl4/boot.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl4/boot.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl4/boot.html
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl3/boot.html
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl3/boot.html
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl2/boot.html
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl2/boot.html
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl1/boot.html
>[20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl1/boot.html
>[21]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl1/boot.html
>[22]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl10/boot.html
>[23]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl10/boot.html
>[24]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl10/boot.html
>[25]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106269v1/shard-skl9/boot.html
>[26]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106269v1/shard-skl9/boot.html
>[27]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106269v1/shard-sk

Re: [Intel-gfx] [PATCH v3 2/7] drm: Add drm_memcpy_from_wc() variant which accepts destination address

[Lucas De Marchi]

On Tue, Apr 26, 2022 at 10:21:43PM +0530, Balasubramani Vivekanandan wrote:

Fast copy using non-temporal instructions for x86 currently exists at two
locations. One is implemented in i915 driver at i915/i915_memcpy.c and
another copy at drm_cache.c. The plan is to remove the duplicate
implementation in i915 driver and use the functions from drm_cache.c.

A variant of drm_memcpy_from_wc() is added in drm_cache.c which accepts
address as argument instead of iosys_map for destination. It is a very
common scenario in i915 to copy from a WC memory type, which may be an
io memory or a system memory to a destination address pointing to system
memory. To avoid the overhead of creating iosys_map type for the
destination, new variant is created to accept the address directly.

Also a new function is exported in drm_cache.c to find if the fast copy
is supported by the platform or not. It is required for i915.

v2: Added a new argument to drm_memcpy_from_wc_vaddr() which provides
the offset into the src address to start copy from.

Cc: Maarten Lankhorst 
Cc: Maxime Ripard 
Cc: Thomas Zimmermann 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: Thomas Hellstr_m 


   ^ utf-8 error?



Signed-off-by: Balasubramani Vivekanandan 
Reviewed-by: Lucas De Marchi 
Reviewed-by: Nirmoy Das 
---
drivers/gpu/drm/drm_cache.c | 55 +
include/drm/drm_cache.h |  3 ++
2 files changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 2e2545df3310..8c7af755f7bc 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -358,6 +358,55 @@ void drm_memcpy_from_wc(struct iosys_map *dst,
}
EXPORT_SYMBOL(drm_memcpy_from_wc);

+/**
+ * drm_memcpy_from_wc_vaddr - Perform the fastest available memcpy from a 
source
+ * that may be WC to a destination in system memory.
+ * @dst: The destination pointer
+ * @src: The source pointer
+ * @src_offset: The offset from which to copy
+ * @len: The size of the area to transfer in bytes
+ *
+ * Same as drm_memcpy_from_wc except destination is accepted as system memory
+ * address. Useful in situations where passing destination address as iosys_map
+ * is simply an overhead and can be avoided.
+ */
+void drm_memcpy_from_wc_vaddr(void *dst, const struct iosys_map *src,
+ size_t src_offset, unsigned long len)
+{
+   const void *src_addr = src->is_iomem ?
+   (void const __force *)src->vaddr_iomem :
+   src->vaddr;


checking this again... this is a layer violation. We do have some in
the codebase, but it'd be good not to add more.

later I'd like these memcpy variants to be moved iosys-map. I'm not sure
if Thomas Zimmermann or Christian agree. Cc'ing them here.

Maybe we could scan the codebase and add a function in iosys-map like:

void *iosys_map_get_ptr(struct iosys_map *map, bool is_lmem)

... which is similar to the ttm_kmap_obj_virtual() function we have in
ttm.

so the cases where the layer is violated at least they come from a
single function call in iosys_map API rather than directly accessing
is_iomem/vaddr_iomem/vaddr. Thomas/Christian, any opinion here?

Lucas De Marchi


+
+   if (WARN_ON(in_interrupt())) {
+   iosys_map_memcpy_from(dst, src, src_offset, len);
+   return;
+   }
+
+   if (static_branch_likely(&has_movntdqa)) {
+   __drm_memcpy_from_wc(dst, src_addr + src_offset, len);
+   return;
+   }
+
+   iosys_map_memcpy_from(dst, src, src_offset, len);
+}
+EXPORT_SYMBOL(drm_memcpy_from_wc_vaddr);
+
+/*
+ * drm_memcpy_fastcopy_supported - Returns if fast copy using non-temporal
+ * instructions is supported
+ *
+ * Returns true if platform has support for fast copying from wc memory type
+ * using non-temporal instructions. Else false.
+ */
+bool drm_memcpy_fastcopy_supported(void)
+{
+   if (static_branch_likely(&has_movntdqa))
+   return true;
+
+   return false;
+}
+EXPORT_SYMBOL(drm_memcpy_fastcopy_supported);
+
/*
 * drm_memcpy_init_early - One time initialization of the WC memcpy code
 */
@@ -382,6 +431,12 @@ void drm_memcpy_from_wc(struct iosys_map *dst,
}
EXPORT_SYMBOL(drm_memcpy_from_wc);

+bool drm_memcpy_fastcopy_supported(void)
+{
+   return false;
+}
+EXPORT_SYMBOL(drm_memcpy_fastcopy_supported);
+
void drm_memcpy_init_early(void)
{
}
diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
index 22deb216b59c..d1b57c84a659 100644
--- a/include/drm/drm_cache.h
+++ b/include/drm/drm_cache.h
@@ -77,4 +77,7 @@ void drm_memcpy_init_early(void);
void drm_memcpy_from_wc(struct iosys_map *dst,
const struct iosys_map *src,
unsigned long len);
+bool drm_memcpy_fastcopy_supported(void);
+void drm_memcpy_from_wc_vaddr(void *dst, const struct iosys_map *src,
+ size_t src_offset, unsigned long len);
#endif
--
2.25.1

Re: [Intel-gfx] [PATCH] drm/i915: Correct ss -> steering calculation for pre-Xe_HP platforms

[Lucas De Marchi]

On Tue, Jul 12, 2022 at 03:05:13PM -0700, Matt Roper wrote:

Accidental use of a "SLICE" macro where a "SUBSLICE" macro was intended
causes the group ID for steering to be calculated incorrectly on
pre-Xe_HP platforms.

Fixes: 9a92732f040a ("drm/i915/gt: Add general DSS steering iterator to 
intel_gt_mcr")
Signed-off-by: Matt Roper 



Reviewed-by: Lucas De Marchi 

Lucas De Marchi


---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c 
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index f8c64ab9d3ca..e79405a45312 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -515,7 +515,7 @@ void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, 
unsigned int dss,
*group = dss / GEN_DSS_PER_GSLICE;
*instance = dss % GEN_DSS_PER_GSLICE;
} else {
-   *group = dss / GEN_MAX_HSW_SLICES;
+   *group = dss / GEN_MAX_SS_PER_HSW_SLICE;
*instance = dss % GEN_MAX_SS_PER_HSW_SLICE;
return;
}
--
2.36.1

[Intel-gfx] ✗ Fi.CI.IGT: failure for Add support for LMEM PCIe resizable bar

[Patchwork]

== Series Details ==

Series: Add support for LMEM PCIe resizable bar
URL   : https://patchwork.freedesktop.org/series/106298/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11877_full -> Patchwork_106298v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_106298v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_106298v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 12)
--

  Missing(1): shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_106298v1_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_fair@basic-deadline:
- shard-kbl:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-kbl7/igt@gem_exec_f...@basic-deadline.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/shard-kbl6/igt@gem_exec_f...@basic-deadline.html

  * igt@i915_selftest@live@hangcheck:
- shard-skl:  NOTRUN -> [INCOMPLETE][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/shard-skl7/igt@i915_selftest@l...@hangcheck.html

  
Known issues


  Here are the changes found in Patchwork_106298v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl:  [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +1 similar 
issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-apl6/igt@gem_ctx_isolation@preservation...@rcs0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/shard-apl6/igt@gem_ctx_isolation@preservation...@rcs0.html

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl:  [PASS][6] -> [DMESG-WARN][7] ([i915#180]) +8 similar 
issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-kbl1/igt@gem_ctx_isolation@preservation...@vcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/shard-kbl7/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-apl:  [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-apl6/igt@gem_exec_fair@basic-n...@vcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/shard-apl1/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/shard-tglb5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl:  [PASS][15] -> [FAIL][16] ([i915#2842]) +2 similar 
issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/shard-kbl7/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2842])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-iclb1/igt@gem_exec_fair@basic-p...@vecs0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/shard-iclb3/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_whisper@basic-fds-all:
- shard-glk:  [PASS][19] -> [DMESG-WARN][20] ([i915#118])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-glk2/igt@gem_exec_whis...@basic-fds-all.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/shard-glk3/igt@gem_exec_whis...@basic-fds-all.html

  * igt@gem_huc_copy@huc-copy:
- shard-skl:  NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#2190])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/shard-skl7/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
- shard-skl:  NOTRUN -> [SKIP][22] ([fdo#1092

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: ttm for stolen (rev9)

[Patchwork]

== Series Details ==

Series: drm/i915: ttm for stolen (rev9)
URL   : https://patchwork.freedesktop.org/series/101396/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11877 -> Patchwork_101396v9


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/index.html

Participating hosts (39 -> 41)
--

  Additional (4): bat-rpls-1 bat-adlm-1 bat-dg2-9 bat-adlp-4 
  Missing(2): bat-adln-1 bat-dg1-5 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_101396v9:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_busy@basic@flip:
- {bat-dg2-9}:NOTRUN -> [DMESG-WARN][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/bat-dg2-9/igt@kms_busy@ba...@flip.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- {bat-adlm-1}:   NOTRUN -> [SKIP][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/bat-adlm-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  
Known issues


  Here are the changes found in Patchwork_101396v9 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlp-4: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/bat-adlp-4/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
- bat-adlp-4: NOTRUN -> [SKIP][4] ([i915#3282])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/bat-adlp-4/igt@gem_tiled_pread_basic.html

  * igt@i915_selftest@live@late_gt_pm:
- fi-bdw-gvtdvm:  [PASS][5] -> [DMESG-FAIL][6] ([i915#6217])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-bdw-gvtdvm/igt@i915_selftest@live@late_gt_pm.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/fi-bdw-gvtdvm/igt@i915_selftest@live@late_gt_pm.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-adlp-4: NOTRUN -> [SKIP][7] ([i915#5903])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/bat-adlp-4/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-pnv-d510:NOTRUN -> [SKIP][8] ([fdo#109271])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- bat-adlp-4: NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/bat-adlp-4/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-adlp-4: NOTRUN -> [SKIP][10] ([i915#4103])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/bat-adlp-4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-adlp-4: NOTRUN -> [SKIP][11] ([i915#4093]) +3 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/bat-adlp-4/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-adlp-4: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#4579])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/bat-adlp-4/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- bat-adlp-4: NOTRUN -> [SKIP][13] ([fdo#109295] / [i915#3301] / 
[i915#3708])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/bat-adlp-4/igt@prime_v...@basic-userptr.html

  * igt@prime_vgem@basic-write:
- bat-adlp-4: NOTRUN -> [SKIP][14] ([fdo#109295] / [i915#3291] / 
[i915#3708]) +2 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/bat-adlp-4/igt@prime_v...@basic-write.html

  * igt@runner@aborted:
- fi-bdw-gvtdvm:  NOTRUN -> [FAIL][15] ([i915#4312])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/fi-bdw-gvtdvm/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_module_load@load:
- {fi-tgl-dsi}:   [DMESG-WARN][16] ([i915#1982]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-tgl-dsi/igt@i915_module_l...@load.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101396v9/fi-tgl-dsi/igt@i915_module_l...@load.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][18] ([i915#4528]) -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [19]: 
https://intel-gfx-ci.01

[Intel-gfx] [PATCH v3 3/3] drm/i915/display: add hotplug.suspended flag

[Andrzej Hajda]

HPD events during driver removal can be generated by hardware and
software frameworks - drm_dp_mst, the former we can avoid by disabling
interrupts, the latter can be triggered by any drm_dp_mst transaction,
and this is too late. Introducing suspended flag allows to solve this
chicken-egg problem.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5950
Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/display/intel_hotplug.c | 13 -
 drivers/gpu/drm/i915/display/intel_hotplug.h |  2 +-
 drivers/gpu/drm/i915/i915_driver.c   |  4 ++--
 drivers/gpu/drm/i915/i915_drv.h  |  2 ++
 5 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index ec8e59b3adaea7..b969635b212ba9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9008,7 +9008,7 @@ void intel_modeset_driver_remove_noirq(struct 
drm_i915_private *i915)
intel_dp_mst_suspend(i915);
 
/* MST is the last user of HPD work */
-   intel_hpd_cancel_work(i915);
+   intel_hpd_suspend(i915);
 
/* poll work can call into fbdev, hence clean that up afterwards */
intel_fbdev_fini(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c 
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 5f8b4f481cff9a..2d505db1f6476b 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -353,6 +353,10 @@ void intel_hpd_trigger_irq(struct intel_digital_port 
*dig_port)
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 
spin_lock_irq(&i915->irq_lock);
+   if (i915->hotplug.suspended) {
+   spin_unlock_irq(&i915->irq_lock);
+   return;
+   }
i915->hotplug.short_port_mask |= BIT(dig_port->base.port);
spin_unlock_irq(&i915->irq_lock);
 
@@ -475,6 +479,11 @@ void intel_hpd_irq_handler(struct drm_i915_private 
*dev_priv,
 
spin_lock(&dev_priv->irq_lock);
 
+   if (dev_priv->hotplug.suspended) {
+   spin_unlock(&dev_priv->irq_lock);
+   return;
+   }
+
/*
 * Determine whether ->hpd_pulse() exists for each pin, and
 * whether we have a short or a long pulse. This is needed
@@ -603,6 +612,7 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
 * just to make the assert_spin_locked checks happy.
 */
spin_lock_irq(&dev_priv->irq_lock);
+   dev_priv->hotplug.suspended = false;
intel_hpd_irq_setup(dev_priv);
spin_unlock_irq(&dev_priv->irq_lock);
 }
@@ -721,13 +731,14 @@ void intel_hpd_init_work(struct drm_i915_private 
*dev_priv)
  intel_hpd_irq_storm_reenable_work);
 }
 
-void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
+void intel_hpd_suspend(struct drm_i915_private *dev_priv)
 {
if (!HAS_DISPLAY(dev_priv))
return;
 
spin_lock_irq(&dev_priv->irq_lock);
 
+   dev_priv->hotplug.suspended = true;
dev_priv->hotplug.long_port_mask = 0;
dev_priv->hotplug.short_port_mask = 0;
dev_priv->hotplug.event_bits = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h 
b/drivers/gpu/drm/i915/display/intel_hotplug.h
index b87e95d606e668..54bddc4dd63421 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.h
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.h
@@ -23,7 +23,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
 void intel_hpd_trigger_irq(struct intel_digital_port *dig_port);
 void intel_hpd_init(struct drm_i915_private *dev_priv);
 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
-void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
+void intel_hpd_suspend(struct drm_i915_private *dev_priv);
 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
   enum port port);
 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index be932a6d9c7dfa..5f87719a74337c 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1079,7 +1079,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
intel_dp_mst_suspend(i915);
 
intel_runtime_pm_disable_interrupts(i915);
-   intel_hpd_cancel_work(i915);
+   intel_hpd_suspend(i915);
 
intel_suspend_encoders(i915);
intel_shutdown_encoders(i915);
@@ -1148,7 +1148,7 @@ static int i915_drm_suspend(struct drm_device *dev)
intel_dp_mst_suspend(dev_priv);
 
intel_runtime_pm_disable_interrupts(dev_priv);
-   intel_hpd_cancel_work(dev_priv);
+   intel_hpd_suspend(dev_priv);
 
intel_suspend_encoders(dev_priv);
 
diff --git a/

[Intel-gfx] [PATCH v3 2/3] drm/i915/fbdev: suspend HPD before fbdev unregistration

[Andrzej Hajda]

HPD event after fbdev unregistration can cause registration of deferred
fbdev which will not be unregistered later, causing use-after-free.
To avoid it HPD handling should be suspended before fbdev unregistration.

It should fix following GPF:
[272.634530] general protection fault, probably for non-canonical address 
0x6b6b6b6b6b6b6b6b:  [#1] PREEMPT SMP NOPTI
[272.634536] CPU: 0 PID: 6030 Comm: i915_selftest Tainted: G U
5.18.0-rc5-CI_DRM_11603-g12dccf4f5eef+ #1
[272.634541] Hardware name: Intel Corporation Raptor Lake Client Platform/RPL-S 
ADP-S DDR5 UDIMM CRB, BIOS RPLSFWI1.R00.2397.A01.2109300731 09/30/2021
[272.634545] RIP: 0010:fb_do_apertures_overlap.part.14+0x26/0x60
...
[272.634582] Call Trace:
[272.634583]  
[272.634585]  do_remove_conflicting_framebuffers+0x59/0xa0
[272.634589]  remove_conflicting_framebuffers+0x2d/0xc0
[272.634592]  remove_conflicting_pci_framebuffers+0xc8/0x110
[272.634595]  drm_aperture_remove_conflicting_pci_framebuffers+0x52/0x70
[272.634604]  i915_driver_probe+0x63a/0xdd0 [i915]

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5329
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5510
Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/i915/display/intel_fbdev.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c 
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 221336178991f0..b682fd72d4bf25 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -573,7 +573,8 @@ void intel_fbdev_unregister(struct drm_i915_private 
*dev_priv)
if (!ifbdev)
return;
 
-   cancel_work_sync(&dev_priv->fbdev_suspend_work);
+   intel_fbdev_set_suspend(&dev_priv->drm, FBINFO_STATE_SUSPENDED, true);
+
if (!current_is_async())
intel_fbdev_sync(ifbdev);
 
-- 
2.25.1

[Intel-gfx] [PATCH v3 1/3] drm/i915/hpd: postpone HPD cancel work after last user suspension

[Andrzej Hajda]

i915->hotplug.dig_port_work can be queued from intel_hpd_irq_handler
called by IRQ handler or by intel_hpd_trigger_irq called from dp_mst.
Since dp_mst is suspended after irq handler uninstall, a cleaner approach
is to cancel hpd work after intel_dp_mst_suspend, otherwise we risk
use-after-free.

It should fix following WARNINGS:
[283.405824] cpu_latency_qos_update_request called for unknown object
[283.405866] WARNING: CPU: 2 PID: 240 at kernel/power/qos.c:296 
cpu_latency_qos_update_request+0x2d/0x100
[283.405912] CPU: 2 PID: 240 Comm: kworker/u64:9 Not tainted 
5.18.0-rc6-Patchwork_103738v3-g1672d1c43e43+ #1
[283.405915] Hardware name: Intel Corporation Raptor Lake Client Platform/RPL-S 
ADP-S DDR5 UDIMM CRB, BIOS RPLSFWI1.R00.2397.A01.2109300731 09/30/2021
[283.405916] Workqueue: i915-dp i915_digport_work_func [i915]
[283.406020] RIP: 0010:cpu_latency_qos_update_request+0x2d/0x100
...
[283.406040] Call Trace:
[283.406041]  
[283.406044]  intel_dp_aux_xfer+0x60e/0x8e0 [i915]
[283.406131]  ? finish_swait+0x80/0x80
[283.406139]  intel_dp_aux_transfer+0xc5/0x2b0 [i915]
[283.406218]  drm_dp_dpcd_access+0x79/0x130 [drm_display_helper]
[283.406227]  drm_dp_dpcd_read+0xe2/0xf0 [drm_display_helper]
[283.406233]  intel_dp_hpd_pulse+0x134/0x570 [i915]
[283.406308]  ? __down_killable+0x70/0x140
[283.406313]  i915_digport_work_func+0xba/0x150 [i915]

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4586
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5558
Signed-off-by: Andrzej Hajda 
Reviewed-by: Arun R Murthy 
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 drivers/gpu/drm/i915/i915_irq.c  | 1 -
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 903226e2a6260d..ec8e59b3adaea7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9007,6 +9007,9 @@ void intel_modeset_driver_remove_noirq(struct 
drm_i915_private *i915)
 */
intel_dp_mst_suspend(i915);
 
+   /* MST is the last user of HPD work */
+   intel_hpd_cancel_work(i915);
+
/* poll work can call into fbdev, hence clean that up afterwards */
intel_fbdev_fini(i915);
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 73cebc6aa65072..db14787aef95dd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4597,7 +4597,6 @@ void intel_irq_uninstall(struct drm_i915_private 
*dev_priv)
 
free_irq(irq, dev_priv);
 
-   intel_hpd_cancel_work(dev_priv);
dev_priv->runtime_pm.irqs_enabled = false;
 }
 
-- 
2.25.1

[Intel-gfx] [PATCH v3 0/3] drm/i915/display: stop HPD workers before display driver unregister

[Andrzej Hajda]

Hi Jani, Ville, Arun,

This patchset is replacement of patch
"drm/i915/display: disable HPD workers before display driver unregister" [1].
Ive decided to split patch into two parts - fbdev and MST, there are different
issues.
Ive also dropped shutdown path, as it has slightly different requirements,
and more importantly I am not able to test properly.

v2 (thx Arun for review):
  - reword of commit message (Arun)
  - intel_fbdev_hpd_set_suspend replaced with intel_fbdev_set_suspend (Arun)
v3:
  - new patch adding suspended flag, to handle
https://gitlab.freedesktop.org/drm/intel/-/issues/5950

[1]: https://patchwork.freedesktop.org/series/103811/

Regards
Andrzej


Andrzej Hajda (3):
  drm/i915/hpd: postpone HPD cancel work after last user suspension
  drm/i915/fbdev: suspend HPD before fbdev unregistration
  drm/i915/display: add hotplug.suspended flag

 drivers/gpu/drm/i915/display/intel_display.c |  3 +++
 drivers/gpu/drm/i915/display/intel_fbdev.c   |  3 ++-
 drivers/gpu/drm/i915/display/intel_hotplug.c | 13 -
 drivers/gpu/drm/i915/display/intel_hotplug.h |  2 +-
 drivers/gpu/drm/i915/i915_driver.c   |  4 ++--
 drivers/gpu/drm/i915/i915_drv.h  |  2 ++
 drivers/gpu/drm/i915/i915_irq.c  |  1 -
 7 files changed, 22 insertions(+), 6 deletions(-)

-- 
2.25.1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: ttm for stolen (rev9)

[Patchwork]

== Series Details ==

Series: drm/i915: ttm for stolen (rev9)
URL   : https://patchwork.freedesktop.org/series/101396/
State : warning

== Summary ==

Error: dim checkpatch failed
a9138083bda2 drm/i915/ttm: dont trample cache_level overrides during ttm move
9d3769792d14 drm/i915: limit ttm to dma32 for i965G[M]
166ce17314f9 drm/i915/ttm: only trust snooping for dgfx when deciding default 
cache_level
e70eb7cbad94 drm/i915: instantiate ttm ranger manager for stolen memory
69c6082b5850 drm/i915: sanitize mem_flags for stolen buffers
f22bb8043fe7 drm/i915: ttm move/clear logic fix
78f205280831 drm/i915/ttm: add buffer pin on alloc flag
a289bd6556e6 drm/i915/selftest: don't attempt engine reset of guc submission 
engines
d9506eb9243a drm/i915/selftest: maintain context ref during reset test
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#6: 
Commit "bcb9aa45d5a0 Revert "drm/i915: Hold reference to intel_context over 
life of i915_request""

total: 0 errors, 1 warnings, 0 checks, 48 lines checked
e6558b94b26e drm/i915: stolen memory use ttm backend

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: ttm for stolen (rev9)

[Patchwork]

== Series Details ==

Series: drm/i915: ttm for stolen (rev9)
URL   : https://patchwork.freedesktop.org/series/101396/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: ttm for internal (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: ttm for internal (rev3)
URL   : https://patchwork.freedesktop.org/series/104909/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11877 -> Patchwork_104909v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/index.html

Participating hosts (39 -> 43)
--

  Additional (5): bat-adlm-1 fi-icl-u2 bat-dg2-9 bat-adlp-4 bat-rpls-1 
  Missing(1): bat-adln-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_104909v3:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_busy@basic@flip:
- {bat-dg2-9}:NOTRUN -> [DMESG-WARN][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/bat-dg2-9/igt@kms_busy@ba...@flip.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- {bat-adlm-1}:   NOTRUN -> [SKIP][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/bat-adlm-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  
Known issues


  Here are the changes found in Patchwork_104909v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlp-4: NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/bat-adlp-4/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_tiled_pread_basic:
- bat-adlp-4: NOTRUN -> [SKIP][6] ([i915#3282])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/bat-adlp-4/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [PASS][7] -> [DMESG-FAIL][8] ([i915#62])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-5:  [PASS][9] -> [DMESG-FAIL][10] ([i915#4494] / 
[i915#4957])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u:   [PASS][11] -> [DMESG-WARN][12] ([i915#5904]) +29 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u:   [PASS][13] -> [DMESG-WARN][14] ([i915#5904] / 
[i915#62])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([i915#5903])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/fi-icl-u2/igt@i915_susp...@basic-s3-without-i915.html
- bat-adlp-4: NOTRUN -> [SKIP][16] ([i915#5903])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/bat-adlp-4/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-rkl-11600:   NOTRUN -> [SKIP][17] ([fdo#111827])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/fi-rkl-11600/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-pnv-d510:NOTRUN -> [SKIP][18] ([fdo#109271])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-blb-e6850:   NOTRUN -> [SKIP][19] ([fdo#109271])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104909v3/fi-blb-e6850/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- bat-adlp-4: NOTRUN -> [SKIP][20] ([fdo#111827]) +8 similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104

Re: [Intel-gfx] [PATCH] drm/i915/ttm: fix 32b build

[Das, Nirmoy]

Reviewed-by: Nirmoy Das 

On 7/12/2022 7:40 PM, Matthew Auld wrote:

Since segment_pages is no longer a compile time constant, it looks the
DIV_ROUND_UP(node->size, segment_pages) breaks the 32b build. Simplest
is just to use the ULL variant, but really we should need not need more
than u32 for the page alignment (also we are limited by that due to the
sg->length type), so also make it all u32.

Reported-by: Ville Syrjälä 
Fixes: bc99f1209f19 ("drm/i915/ttm: fix sg_table construction")
Signed-off-by: Matthew Auld 
Cc: Nirmoy Das 
---
  drivers/gpu/drm/i915/gem/i915_gem_region.c |  2 ++
  drivers/gpu/drm/i915/gem/i915_gem_ttm.c|  2 +-
  drivers/gpu/drm/i915/i915_scatterlist.c| 16 
  drivers/gpu/drm/i915/i915_scatterlist.h|  4 ++--
  drivers/gpu/drm/i915/intel_region_ttm.c|  2 +-
  drivers/gpu/drm/i915/intel_region_ttm.h|  2 +-
  6 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c 
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index f46ee16a323a..a4fb577eceb4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -60,6 +60,8 @@ __i915_gem_object_create_region(struct intel_memory_region 
*mem,
if (page_size)
default_page_size = page_size;
  
+	/* We should be able to fit a page within an sg entry */

+   GEM_BUG_ON(overflows_type(default_page_size, u32));
GEM_BUG_ON(!is_power_of_2_u64(default_page_size));
GEM_BUG_ON(default_page_size < PAGE_SIZE);
  
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c

index 053b0022ddd0..5a5cf332d8a5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -602,7 +602,7 @@ i915_ttm_resource_get_st(struct drm_i915_gem_object *obj,
 struct ttm_resource *res)
  {
struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
-   u64 page_alignment;
+   u32 page_alignment;
  
  	if (!i915_ttm_gtt_binds_lmem(res))

return i915_ttm_tt_get_st(bo->ttm);
diff --git a/drivers/gpu/drm/i915/i915_scatterlist.c 
b/drivers/gpu/drm/i915/i915_scatterlist.c
index f63b50b71e10..dcc081874ec8 100644
--- a/drivers/gpu/drm/i915/i915_scatterlist.c
+++ b/drivers/gpu/drm/i915/i915_scatterlist.c
@@ -79,10 +79,10 @@ void i915_refct_sgt_init(struct i915_refct_sgt *rsgt, 
size_t size)
   */
  struct i915_refct_sgt *i915_rsgt_from_mm_node(const struct drm_mm_node *node,
  u64 region_start,
- u64 page_alignment)
+ u32 page_alignment)
  {
-   const u64 max_segment = round_down(UINT_MAX, page_alignment);
-   u64 segment_pages = max_segment >> PAGE_SHIFT;
+   const u32 max_segment = round_down(UINT_MAX, page_alignment);
+   const u32 segment_pages = max_segment >> PAGE_SHIFT;
u64 block_size, offset, prev_end;
struct i915_refct_sgt *rsgt;
struct sg_table *st;
@@ -96,7 +96,7 @@ struct i915_refct_sgt *i915_rsgt_from_mm_node(const struct 
drm_mm_node *node,
  
  	i915_refct_sgt_init(rsgt, node->size << PAGE_SHIFT);

st = &rsgt->table;
-   if (sg_alloc_table(st, DIV_ROUND_UP(node->size, segment_pages),
+   if (sg_alloc_table(st, DIV_ROUND_UP_ULL(node->size, segment_pages),
   GFP_KERNEL)) {
i915_refct_sgt_put(rsgt);
return ERR_PTR(-ENOMEM);
@@ -123,7 +123,7 @@ struct i915_refct_sgt *i915_rsgt_from_mm_node(const struct 
drm_mm_node *node,
st->nents++;
}
  
-		len = min(block_size, max_segment - sg->length);

+   len = min_t(u64, block_size, max_segment - sg->length);
sg->length += len;
sg_dma_len(sg) += len;
  
@@ -155,11 +155,11 @@ struct i915_refct_sgt *i915_rsgt_from_mm_node(const struct drm_mm_node *node,

   */
  struct i915_refct_sgt *i915_rsgt_from_buddy_resource(struct ttm_resource *res,
 u64 region_start,
-u64 page_alignment)
+u32 page_alignment)
  {
struct i915_ttm_buddy_resource *bman_res = to_ttm_buddy_resource(res);
const u64 size = res->num_pages << PAGE_SHIFT;
-   const u64 max_segment = round_down(UINT_MAX, page_alignment);
+   const u32 max_segment = round_down(UINT_MAX, page_alignment);
struct drm_buddy *mm = bman_res->mm;
struct list_head *blocks = &bman_res->blocks;
struct drm_buddy_block *block;
@@ -207,7 +207,7 @@ struct i915_refct_sgt *i915_rsgt_from_buddy_resource(struct 
ttm_resource *res,
st->nents++;
}
  
-			len = min(block_size, max_segment - sg->length);

+   len = min_t(u

[Intel-gfx] ✓ Fi.CI.BAT: success for Add support for LMEM PCIe resizable bar

[Patchwork]

== Series Details ==

Series: Add support for LMEM PCIe resizable bar
URL   : https://patchwork.freedesktop.org/series/106298/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11877 -> Patchwork_106298v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/index.html

Participating hosts (39 -> 39)
--

  Additional (3): bat-rpls-1 bat-adlm-1 bat-dg2-9 
  Missing(3): bat-rpls-2 bat-adln-1 bat-adlp-6 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_106298v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_suspend@basic-s0@smem:
- {bat-adlm-1}:   NOTRUN -> [DMESG-WARN][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- {bat-adlm-1}:   NOTRUN -> [SKIP][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/bat-adlm-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  
Known issues


  Here are the changes found in Patchwork_106298v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][3] -> [INCOMPLETE][4] ([i915#3921])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  
 Possible fixes 

  * igt@i915_module_load@load:
- {fi-tgl-dsi}:   [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/fi-tgl-dsi/igt@i915_module_l...@load.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106298v1/fi-tgl-dsi/igt@i915_module_l...@load.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
  [i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
  [i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
  [i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257


Build changes
-

  * Linux: CI_DRM_11877 -> Patchwork_106298v1

  CI-20190529: 20190529
  CI_DRM_11877: e55cefc370de5a38ee848aa96082d9d9f4cacdb9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6578: 7d289d89131ec37c1145bcdb86149914587d74

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add support for LMEM PCIe resizable bar

[Patchwork]

== Series Details ==

Series: Add support for LMEM PCIe resizable bar
URL   : https://patchwork.freedesktop.org/series/106298/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] [PATCH v11 09/10] drm/i915/selftest: maintain context ref during reset test

[Robert Beckett]

Commit "bcb9aa45d5a0 Revert "drm/i915: Hold reference to intel_context over 
life of i915_request""
Stopped requests from maintaining a ref on the context.
This caused the contexts to be freed, releasing stolen memory while
under test, leading to false positive detection of stolen corruption.
Fix this by maintaining a ref on the contexts until testing is complete.

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/gt/selftest_reset.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c 
b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 55f3b34e5f6e..ba536e8a2e32 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -6,6 +6,7 @@
 #include 
 
 #include "gem/i915_gem_stolen.h"
+#include "gt/intel_gt.h"
 
 #include "i915_memcpy.h"
 #include "i915_selftest.h"
@@ -26,6 +27,7 @@ __igt_reset_stolen(struct intel_gt *gt,
intel_wakeref_t wakeref;
enum intel_engine_id id;
struct igt_spinner spin;
+   struct intel_context *contexts[I915_NUM_ENGINES] = {0};
long max, count;
void *tmp;
u32 *crc;
@@ -71,12 +73,12 @@ __igt_reset_stolen(struct intel_gt *gt,
goto err_spin;
}
rq = igt_spinner_create_request(&spin, ce, MI_ARB_CHECK);
-   intel_context_put(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto err_spin;
}
i915_request_add(rq);
+   contexts[id] = ce;
}
 
for (page = 0; page < num_pages; page++) {
@@ -165,8 +167,21 @@ __igt_reset_stolen(struct intel_gt *gt,
err = -EINVAL;
}
 
+   err = intel_gt_wait_for_idle(gt, HZ);
+   if (err < 0) {
+   pr_err("%s failed to wait for gt idle: %d\n", msg, err);
+   goto err_spin;
+   }
+
+   err = 0;
+
 err_spin:
igt_spinner_fini(&spin);
+   for (id = 0; id < I915_NUM_ENGINES; id++) {
+   if (!contexts[id])
+   continue;
+   intel_context_put(contexts[id]);
+   }
 
 err_lock:
intel_runtime_pm_put(gt->uncore->rpm, wakeref);
-- 
2.25.1

[Intel-gfx] [PATCH v11 10/10] drm/i915: stolen memory use ttm backend

[Robert Beckett]

refactor stolen memory region to use ttm.
this necessitates using ttm resources to track reserved stolen regions
instead of drm_mm_nodes.

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/display/intel_fbc.c  |  78 ++--
 .../gpu/drm/i915/gem/i915_gem_object_types.h  |   2 -
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 425 ++
 drivers/gpu/drm/i915/gem/i915_gem_stolen.h|  21 +-
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   |   3 +-
 drivers/gpu/drm/i915/gem/i915_gem_ttm.h   |   7 +
 drivers/gpu/drm/i915/gt/intel_rc6.c   |   4 +-
 drivers/gpu/drm/i915/gt/selftest_reset.c  |  16 +-
 drivers/gpu/drm/i915/i915_debugfs.c   |   7 +-
 drivers/gpu/drm/i915/i915_drv.h   |   6 +-
 drivers/gpu/drm/i915/intel_region_ttm.c   |  42 +-
 drivers/gpu/drm/i915/intel_region_ttm.h   |   8 +-
 drivers/gpu/drm/i915/selftests/mock_region.c  |  12 +-
 13 files changed, 280 insertions(+), 351 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 16537830ccf0..7dd42b11f4b8 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -38,6 +38,7 @@
  * forcibly disable it to allow proper screen updates.
  */
 
+#include "gem/i915_gem_stolen.h"
 #include 
 
 #include 
@@ -52,6 +53,7 @@
 #include "intel_display_types.h"
 #include "intel_fbc.h"
 #include "intel_frontbuffer.h"
+#include "gem/i915_gem_region.h"
 
 #define for_each_fbc_id(__dev_priv, __fbc_id) \
for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; 
(__fbc_id)++) \
@@ -93,8 +95,8 @@ struct intel_fbc {
struct mutex lock;
unsigned int busy_bits;
 
-   struct drm_mm_node compressed_fb;
-   struct drm_mm_node compressed_llb;
+   struct ttm_resource *compressed_fb;
+   struct ttm_resource *compressed_llb;
 
enum intel_fbc_id id;
 
@@ -332,16 +334,20 @@ static void i8xx_fbc_nuke(struct intel_fbc *fbc)
 static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
 {
struct drm_i915_private *i915 = fbc->i915;
+   u64 fb_offset = i915_gem_stolen_reserve_offset(fbc->compressed_fb);
+   u64 llb_offset = i915_gem_stolen_reserve_offset(fbc->compressed_llb);
 
+   GEM_BUG_ON(fb_offset == I915_BO_INVALID_OFFSET);
+   GEM_BUG_ON(llb_offset == I915_BO_INVALID_OFFSET);
GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start,
-fbc->compressed_fb.start, U32_MAX));
+fb_offset, U32_MAX));
GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start,
-fbc->compressed_llb.start, U32_MAX));
+llb_offset, U32_MAX));
 
intel_de_write(i915, FBC_CFB_BASE,
-  i915->dsm.start + fbc->compressed_fb.start);
+  i915->dsm.start + fb_offset);
intel_de_write(i915, FBC_LL_BASE,
-  i915->dsm.start + fbc->compressed_llb.start);
+  i915->dsm.start + llb_offset);
 }
 
 static const struct intel_fbc_funcs i8xx_fbc_funcs = {
@@ -449,8 +455,10 @@ static bool g4x_fbc_is_compressing(struct intel_fbc *fbc)
 static void g4x_fbc_program_cfb(struct intel_fbc *fbc)
 {
struct drm_i915_private *i915 = fbc->i915;
+   u64 fb_offset = i915_gem_stolen_reserve_offset(fbc->compressed_fb);
 
-   intel_de_write(i915, DPFC_CB_BASE, fbc->compressed_fb.start);
+   GEM_BUG_ON(fb_offset == I915_BO_INVALID_OFFSET);
+   intel_de_write(i915, DPFC_CB_BASE, fb_offset);
 }
 
 static const struct intel_fbc_funcs g4x_fbc_funcs = {
@@ -500,8 +508,10 @@ static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
 static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
 {
struct drm_i915_private *i915 = fbc->i915;
+   u64 fb_offset = i915_gem_stolen_reserve_offset(fbc->compressed_fb);
 
-   intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), 
fbc->compressed_fb.start);
+   GEM_BUG_ON(fb_offset == I915_BO_INVALID_OFFSET);
+   intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), fb_offset);
 }
 
 static const struct intel_fbc_funcs ilk_fbc_funcs = {
@@ -745,21 +755,24 @@ static int find_compression_limit(struct intel_fbc *fbc,
 {
struct drm_i915_private *i915 = fbc->i915;
u64 end = intel_fbc_stolen_end(i915);
-   int ret, limit = min_limit;
+   int limit = min_limit;
+   struct ttm_resource *res;
 
size /= limit;
 
/* Try to over-allocate to reduce reallocations and fragmentation. */
-   ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb,
-  size <<= 1, 4096, 0, end);
-   if (ret == 0)
+   res = i915_gem_stolen_reserve_range(i915, size <<= 1, 0, end);
+   if (!IS_ERR(res)) {
+   fbc->compressed_fb = res;
return limit;
+   }
 
for (; limit <= i

[Intel-gfx] [PATCH v11 08/10] drm/i915/selftest: don't attempt engine reset of guc submission engines

[Robert Beckett]

igt_reset_engines_stolen tries to reset engines without checking if it
is possible.
Engines using GuC submission are not able to be reset from the host.

In this scenario, the reset exits early, then on the next iteration of
the each engine loop, the async teardown of the spinner request
context's ring occurs while the next engine is under test.

This is seen as a stolen memory corruption as the ring buffer was busy
initially, but free during the confirmation check and had been poisoned
during cleanup.

Fix this by not testing GuC submission using engines.

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/gt/selftest_reset.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c 
b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 37c38bdd5f47..55f3b34e5f6e 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -194,6 +194,8 @@ static int igt_reset_engines_stolen(void *arg)
return 0;
 
for_each_engine(engine, gt, id) {
+   if (intel_engine_uses_guc(engine))
+   continue;
err = __igt_reset_stolen(gt, engine->mask, engine->name);
if (err)
return err;
-- 
2.25.1

[Intel-gfx] [PATCH v11 05/10] drm/i915: sanitize mem_flags for stolen buffers

[Robert Beckett]

Stolen regions are not page backed or considered iomem.
Prevent flags indicating such.
This correctly prevents stolen buffers from attempting to directly map
them.

See i915_gem_object_has_struct_page() and i915_gem_object_has_iomem()
usage for where it would break otherwise.

Signed-off-by: Robert Beckett 
Reviewed-by: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 2cc2c08bd50f..18d574ac167f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -14,6 +14,7 @@
 #include "gem/i915_gem_region.h"
 #include "gem/i915_gem_ttm.h"
 #include "gem/i915_gem_ttm_move.h"
+#include "gem/i915_gem_stolen.h"
 
 #include "gt/intel_engine_pm.h"
 #include "gt/intel_gt.h"
@@ -130,8 +131,9 @@ void i915_ttm_adjust_gem_after_move(struct 
drm_i915_gem_object *obj)
 
obj->mem_flags &= ~(I915_BO_FLAG_STRUCT_PAGE | I915_BO_FLAG_IOMEM);
 
-   obj->mem_flags |= i915_ttm_cpu_maps_iomem(bo->resource) ? 
I915_BO_FLAG_IOMEM :
-   I915_BO_FLAG_STRUCT_PAGE;
+   if (!i915_gem_object_is_stolen(obj))
+   obj->mem_flags |= i915_ttm_cpu_maps_iomem(bo->resource) ? 
I915_BO_FLAG_IOMEM :
+   I915_BO_FLAG_STRUCT_PAGE;
 
if (!obj->ttm.cache_level_override) {
cache_level = i915_ttm_cache_level(to_i915(bo->base.dev),
-- 
2.25.1

[Intel-gfx] [PATCH v11 06/10] drm/i915: ttm move/clear logic fix

[Robert Beckett]

ttm managed buffers start off with system resource definitions and ttm_tt
tracking structures allocated (though unpopulated).
currently this prevents clearing of buffers on first move to desired
placements.

The desired behaviour is to clear user allocated buffers and any kernel
buffers that specifically requests it only.
Make the logic match the desired behaviour.

Signed-off-by: Robert Beckett 
Reviewed-by: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 22 +++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 18d574ac167f..6671345b2abe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -3,6 +3,7 @@
  * Copyright © 2021 Intel Corporation
  */
 
+#include "drm/ttm/ttm_tt.h"
 #include 
 
 #include "i915_deps.h"
@@ -546,6 +547,25 @@ __i915_ttm_move(struct ttm_buffer_object *bo,
return fence;
 }
 
+static bool
+allow_clear(struct drm_i915_gem_object *obj, struct ttm_tt *ttm, struct 
ttm_resource *dst_mem)
+{
+   /* never clear stolen */
+   if (dst_mem->mem_type == I915_PL_STOLEN)
+   return false;
+   /*
+* we want to clear user buffers and any kernel buffers
+* that specifically request clearing.
+*/
+   if (obj->flags & I915_BO_ALLOC_USER)
+   return true;
+
+   if (ttm && ttm->page_flags & TTM_TT_FLAG_ZERO_ALLOC)
+   return true;
+
+   return false;
+}
+
 /**
  * i915_ttm_move - The TTM move callback used by i915.
  * @bo: The buffer object.
@@ -596,7 +616,7 @@ int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
return PTR_ERR(dst_rsgt);
 
clear = !i915_ttm_cpu_maps_iomem(bo->resource) && (!ttm || 
!ttm_tt_is_populated(ttm));
-   if (!(clear && ttm && !(ttm->page_flags & TTM_TT_FLAG_ZERO_ALLOC))) {
+   if (!clear || allow_clear(obj, ttm, dst_mem)) {
struct i915_deps deps;
 
i915_deps_init(&deps, GFP_KERNEL | __GFP_NORETRY | 
__GFP_NOWARN);
-- 
2.25.1

[Intel-gfx] [PATCH v11 07/10] drm/i915/ttm: add buffer pin on alloc flag

[Robert Beckett]

For situations where allocations need to fail on alloc instead of
delayed get_pages, add a new alloc flag to pin the ttm bo.
This makes sure that the resource has been allocated during buffer
creation, allowing it to fail with an error if the placement is
exhausted.
This allows existing fallback options for stolen backend allocation like
create_ring_vma to work as expected.

Signed-off-by: Robert Beckett 
---
 .../gpu/drm/i915/gem/i915_gem_object_types.h  | 13 ++
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   | 25 ++-
 2 files changed, 32 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 14937cf1daaa..283a4b84971a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -325,17 +325,20 @@ struct drm_i915_gem_object {
  * dealing with userspace objects the CPU fault handler is free to ignore this.
  */
 #define I915_BO_ALLOC_GPU_ONLY   BIT(6)
+/* object should be pinned in destination region from allocation */
+#define I915_BO_ALLOC_PINNED BIT(7)
 #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
 I915_BO_ALLOC_VOLATILE | \
 I915_BO_ALLOC_CPU_CLEAR | \
 I915_BO_ALLOC_USER | \
 I915_BO_ALLOC_PM_VOLATILE | \
 I915_BO_ALLOC_PM_EARLY | \
-I915_BO_ALLOC_GPU_ONLY)
-#define I915_BO_READONLY  BIT(7)
-#define I915_TILING_QUIRK_BIT 8 /* unknown swizzling; do not release! */
-#define I915_BO_PROTECTED BIT(9)
-#define I915_BO_WAS_BOUND_BIT 10
+I915_BO_ALLOC_GPU_ONLY | \
+I915_BO_ALLOC_PINNED)
+#define I915_BO_READONLY  BIT(8)
+#define I915_TILING_QUIRK_BIT 9 /* unknown swizzling; do not release! */
+#define I915_BO_PROTECTED BIT(10)
+#define I915_BO_WAS_BOUND_BIT 11
/**
 * @mem_flags - Mutable placement-related flags
 *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index b6c3fc25d9d1..d34ebe9fcff8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -1011,6 +1011,13 @@ static void i915_ttm_delayed_free(struct 
drm_i915_gem_object *obj)
 {
GEM_BUG_ON(!obj->ttm.created);
 
+   /* stolen objects are pinned for lifetime. Unpin before putting */
+   if (obj->flags & I915_BO_ALLOC_PINNED) {
+   ttm_bo_reserve(i915_gem_to_ttm(obj), true, false, NULL);
+   ttm_bo_unpin(i915_gem_to_ttm(obj));
+   ttm_bo_unreserve(i915_gem_to_ttm(obj));
+   }
+
ttm_bo_put(i915_gem_to_ttm(obj));
 }
 
@@ -1206,6 +1213,9 @@ int __i915_gem_ttm_object_init(struct intel_memory_region 
*mem,
.no_wait_gpu = false,
};
enum ttm_bo_type bo_type;
+   struct ttm_place _place;
+   struct ttm_placement _placement;
+   struct ttm_placement *placement;
int ret;
 
drm_gem_private_object_init(&i915->drm, &obj->base, size);
@@ -1235,6 +1245,17 @@ int __i915_gem_ttm_object_init(struct 
intel_memory_region *mem,
 */
i915_gem_object_make_unshrinkable(obj);
 
+   if (obj->flags & I915_BO_ALLOC_PINNED) {
+   i915_ttm_place_from_region(mem, &_place, obj->bo_offset,
+  obj->base.size, obj->flags);
+   _placement.num_placement = 1;
+   _placement.placement = &_place;
+   _placement.num_busy_placement = 0;
+   _placement.busy_placement = NULL;
+   placement = &_placement;
+   } else {
+   placement = &i915_sys_placement;
+   }
/*
 * If this function fails, it will call the destructor, but
 * our caller still owns the object. So no freeing in the
@@ -1243,7 +1264,7 @@ int __i915_gem_ttm_object_init(struct intel_memory_region 
*mem,
 * until successful initialization.
 */
ret = ttm_bo_init_reserved(&i915->bdev, i915_gem_to_ttm(obj), bo_type,
-  &i915_sys_placement, page_size >> PAGE_SHIFT,
+  placement, page_size >> PAGE_SHIFT,
   &ctx, NULL, NULL, i915_ttm_bo_destroy);
if (ret)
return i915_ttm_err_to_gem(ret);
@@ -1254,6 +1275,8 @@ int __i915_gem_ttm_object_init(struct intel_memory_region 
*mem,
i915_ttm_adjust_domains_after_move(obj);
i915_ttm_adjust_gem_after_move(obj);
obj->ttm.cache_level_override = false;
+   if (obj->flags & I915_BO_ALLOC_PINNED)
+   ttm_bo_pin(i915_gem_to_ttm(obj));
i915_gem_object_unlock(obj);
 
return 0;
-- 
2.25.1

[Intel-gfx] [PATCH v11 04/10] drm/i915: instantiate ttm ranger manager for stolen memory

[Robert Beckett]

prepare for ttm based stolen region by using ttm range manager
as the resource manager for stolen region.

Signed-off-by: Robert Beckett 
Reviewed-by: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c |  6 ++--
 drivers/gpu/drm/i915/intel_region_ttm.c  | 31 +++-
 2 files changed, 27 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index a949594237d9..2cc2c08bd50f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -66,11 +66,13 @@ i915_ttm_region(struct ttm_device *bdev, int ttm_mem_type)
struct drm_i915_private *i915 = container_of(bdev, typeof(*i915), bdev);
 
/* There's some room for optimization here... */
-   GEM_BUG_ON(ttm_mem_type != I915_PL_SYSTEM &&
-  ttm_mem_type < I915_PL_LMEM0);
+   GEM_BUG_ON(ttm_mem_type == I915_PL_GGTT);
+
if (ttm_mem_type == I915_PL_SYSTEM)
return intel_memory_region_lookup(i915, INTEL_MEMORY_SYSTEM,
  0);
+   if (ttm_mem_type == I915_PL_STOLEN)
+   return i915->mm.stolen_region;
 
return intel_memory_region_lookup(i915, INTEL_MEMORY_LOCAL,
  ttm_mem_type - I915_PL_LMEM0);
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c 
b/drivers/gpu/drm/i915/intel_region_ttm.c
index 642cd1587976..caac110a0a2c 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -54,7 +54,7 @@ void intel_region_ttm_device_fini(struct drm_i915_private 
*dev_priv)
 
 /*
  * Map the i915 memory regions to TTM memory types. We use the
- * driver-private types for now, reserving TTM_PL_VRAM for stolen
+ * driver-private types for now, reserving I915_PL_STOLEN for stolen
  * memory and TTM_PL_TT for GGTT use if decided to implement this.
  */
 int intel_region_to_ttm_type(const struct intel_memory_region *mem)
@@ -63,11 +63,17 @@ int intel_region_to_ttm_type(const struct 
intel_memory_region *mem)
 
GEM_BUG_ON(mem->type != INTEL_MEMORY_LOCAL &&
   mem->type != INTEL_MEMORY_MOCK &&
-  mem->type != INTEL_MEMORY_SYSTEM);
+  mem->type != INTEL_MEMORY_SYSTEM &&
+  mem->type != INTEL_MEMORY_STOLEN_SYSTEM &&
+  mem->type != INTEL_MEMORY_STOLEN_LOCAL);
 
if (mem->type == INTEL_MEMORY_SYSTEM)
return TTM_PL_SYSTEM;
 
+   if (mem->type == INTEL_MEMORY_STOLEN_SYSTEM ||
+   mem->type == INTEL_MEMORY_STOLEN_LOCAL)
+   return I915_PL_STOLEN;
+
type = mem->instance + TTM_PL_PRIV;
GEM_BUG_ON(type >= TTM_NUM_MEM_TYPES);
 
@@ -91,10 +97,16 @@ int intel_region_ttm_init(struct intel_memory_region *mem)
int mem_type = intel_region_to_ttm_type(mem);
int ret;
 
-   ret = i915_ttm_buddy_man_init(bdev, mem_type, false,
- resource_size(&mem->region),
- mem->io_size,
- mem->min_page_size, PAGE_SIZE);
+   if (mem_type == I915_PL_STOLEN) {
+   ret = ttm_range_man_init(bdev, mem_type, false,
+resource_size(&mem->region) >> 
PAGE_SHIFT);
+   mem->is_range_manager = true;
+   } else {
+   ret = i915_ttm_buddy_man_init(bdev, mem_type, false,
+ resource_size(&mem->region),
+ mem->io_size,
+ mem->min_page_size, PAGE_SIZE);
+   }
if (ret)
return ret;
 
@@ -114,6 +126,7 @@ int intel_region_ttm_init(struct intel_memory_region *mem)
 int intel_region_ttm_fini(struct intel_memory_region *mem)
 {
struct ttm_resource_manager *man = mem->region_private;
+   int mem_type = intel_region_to_ttm_type(mem);
int ret = -EBUSY;
int count;
 
@@ -144,8 +157,10 @@ int intel_region_ttm_fini(struct intel_memory_region *mem)
if (ret || !man)
return ret;
 
-   ret = i915_ttm_buddy_man_fini(&mem->i915->bdev,
- intel_region_to_ttm_type(mem));
+   if (mem_type == I915_PL_STOLEN)
+   ret = ttm_range_man_fini(&mem->i915->bdev, mem_type);
+   else
+   ret = i915_ttm_buddy_man_fini(&mem->i915->bdev, mem_type);
GEM_WARN_ON(ret);
mem->region_private = NULL;
 
-- 
2.25.1

[Intel-gfx] [PATCH v11 03/10] drm/i915/ttm: only trust snooping for dgfx when deciding default cache_level

[Robert Beckett]

By default i915_ttm_cache_level() decides I915_CACHE_LLC if HAS_SNOOP.
This is divergent from existing backends code which only considers
HAS_LLC.
Testing shows that trusting snooping on gen5- is unreliable and bsw via
ggtt mappings, so limit DGFX for now and maintain previous behaviour.

Signed-off-by: Robert Beckett 
Reviewed-by: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 042c2237e287..a949594237d9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -52,7 +52,9 @@ static enum i915_cache_level
 i915_ttm_cache_level(struct drm_i915_private *i915, struct ttm_resource *res,
 struct ttm_tt *ttm)
 {
-   return ((HAS_LLC(i915) || HAS_SNOOP(i915)) &&
+   bool can_snoop = HAS_SNOOP(i915) && IS_DGFX(i915);
+
+   return ((HAS_LLC(i915) || can_snoop) &&
!i915_ttm_gtt_binds_lmem(res) &&
ttm->caching == ttm_cached) ? I915_CACHE_LLC :
I915_CACHE_NONE;
-- 
2.25.1

[Intel-gfx] [PATCH v11 02/10] drm/i915: limit ttm to dma32 for i965G[M]

[Robert Beckett]

i965G[M] cannot relocate objects above 4GiB.
Ensure ttm uses dma32 on these systems.

Signed-off-by: Robert Beckett 
Reviewed-by: Thomas Hellström 
---
 drivers/gpu/drm/i915/intel_region_ttm.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c 
b/drivers/gpu/drm/i915/intel_region_ttm.c
index 6873808a7015..642cd1587976 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -32,10 +32,15 @@
 int intel_region_ttm_device_init(struct drm_i915_private *dev_priv)
 {
struct drm_device *drm = &dev_priv->drm;
+   bool use_dma32 = false;
+
+   /* i965g[m] cannot relocate objects above 4GiB. */
+   if (IS_I965GM(dev_priv) || IS_I965G(dev_priv))
+   use_dma32 = true;
 
return ttm_device_init(&dev_priv->bdev, i915_ttm_driver(),
   drm->dev, drm->anon_inode->i_mapping,
-  drm->vma_offset_manager, false, false);
+  drm->vma_offset_manager, false, use_dma32);
 }
 
 /**
-- 
2.25.1

[Intel-gfx] [PATCH v11 01/10] drm/i915/ttm: dont trample cache_level overrides during ttm move

[Robert Beckett]

Various places within the driver override the default chosen cache_level.
Before ttm, these overrides were permanent until explicitly changed again
or for the lifetime of the buffer.

TTM movement code came along and decided that it could make that
decision at that time, which is usually well after object creation, so
overrode the cache_level decision and reverted it back to its default
decision.

Add logic to indicate whether the caching mode has been set by anything
other than the move logic. If so, assume that the code that overrode the
defaults knows best and keep it.

Signed-off-by: Robert Beckett 
Reviewed-by: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_object.c   | 1 +
 drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c  | 1 +
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 9 ++---
 4 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index ccec4055fde3..966ac2d778d5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -125,6 +125,7 @@ void i915_gem_object_set_cache_coherency(struct 
drm_i915_gem_object *obj,
struct drm_i915_private *i915 = to_i915(obj->base.dev);
 
obj->cache_level = cache_level;
+   obj->ttm.cache_level_override = true;
 
if (cache_level != I915_CACHE_NONE)
obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ |
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 5cf36a130061..14937cf1daaa 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -623,6 +623,7 @@ struct drm_i915_gem_object {
struct i915_gem_object_page_iter get_io_page;
struct drm_i915_gem_object *backup;
bool created:1;
+   bool cache_level_override:1;
} ttm;
 
/*
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 053b0022ddd0..b6c3fc25d9d1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -1253,6 +1253,7 @@ int __i915_gem_ttm_object_init(struct intel_memory_region 
*mem,
i915_gem_object_init_memory_region(obj, mem);
i915_ttm_adjust_domains_after_move(obj);
i915_ttm_adjust_gem_after_move(obj);
+   obj->ttm.cache_level_override = false;
i915_gem_object_unlock(obj);
 
return 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 9a7e50534b84..042c2237e287 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -129,9 +129,12 @@ void i915_ttm_adjust_gem_after_move(struct 
drm_i915_gem_object *obj)
obj->mem_flags |= i915_ttm_cpu_maps_iomem(bo->resource) ? 
I915_BO_FLAG_IOMEM :
I915_BO_FLAG_STRUCT_PAGE;
 
-   cache_level = i915_ttm_cache_level(to_i915(bo->base.dev), bo->resource,
-  bo->ttm);
-   i915_gem_object_set_cache_coherency(obj, cache_level);
+   if (!obj->ttm.cache_level_override) {
+   cache_level = i915_ttm_cache_level(to_i915(bo->base.dev),
+  bo->resource, bo->ttm);
+   i915_gem_object_set_cache_coherency(obj, cache_level);
+   obj->ttm.cache_level_override = false;
+   }
 }
 
 /**
-- 
2.25.1

[Intel-gfx] [PATCH v11 00/10] drm/i915: ttm for stolen

[Robert Beckett]

This series refactors i915's stolen memory region to use ttm.

v2: handle disabled stolen similar to legacy version.
relying on ttm to fail allocs works fine, but is dmesg noisy and causes 
testing
dmesg warning regressions.

v3: rebase to latest drm-tip.
fix v2 code refactor which could leave a buffer pinned.
locally passes fftl again now.

v4: - Allow memory regions creators to do allocation. Allows stolen region 
to track
  it's own reservations.
- Pre-reserve first page of stolen mem (add back 
WaSkipStolenMemoryFirstPage:bdw+)
- Improve commit descritpion for "drm/i915: sanitize mem_flags for 
stolen buffers"
- replace i915_gem_object_pin_pages_unlocked() call with manual locking 
and pinning.
  this avoids ww ctx class reuse during context creation -> ring vma 
obj alloc.

v5: - detect both types of stolen as stolen buffers in
  "drm/i915: sanitize mem_flags for stolen buffers"
- in stolen_object_init limit page size to mem region minimum.
  The range allocator expects the page_size to define the
  alignment

v6: - Share first 4 patches from ttm for internal series as generic
  i915 ttm fixes
- Drop patch 4 from v5. We don't need separate object ops just
  to satisfy test interfaces. The tests have now been fixed via
  checking whether the memory region is private to decide
  whether to mmap
- Add new buffer pin alloc flag to allow creation of buffers in
  their final ttm placement instead of deferring until
  get_pages. This fixes legacy fallback paths for buffer
  allocations during stolen memory pressure.

v7: - fix mock_region_get_pages() to correctly handle I915_BO_INVALID_OFFSET

v8: - Reserve I915_GEM_STOLEN_BIAS area from stolen

v9: - drop patch 8 "drm/i915: allow memory region creators to alloc and 
free the region"
  store bias reservation in drm_i915_private instead.
- Restrict reset selftest to only test !GuC engines.
  Resetting individual GuC engines from host is not supported
- Wait for outstanding requests in reset selftest
  This prevents previous engine test context cleanup appearing
  as false positive stolen corruption check

v10:- Fix wiating on requests early error path during reset selftest
  If a single request fails to complete, the others would not be
  put, resulting in leaks. Make sure all requests are put before
  test exit.

v11:- rebased to latest drm-tip
- commit "bcb9aa45d5a0 Revert "drm/i915: Hold reference to 
intel_context over life of i915_request""
  broke the selftest@live@reset test, causing the context ringbuffer to
  be freed during testing. Fixed via maintinaing context ref
  during testing.
- drop patch 4 "drm/i915/gem: selftest should not attempt mmap of 
private regions"
  it is no longer needed.

Robert Beckett (10):
  drm/i915/ttm: dont trample cache_level overrides during ttm move
  drm/i915: limit ttm to dma32 for i965G[M]
  drm/i915/ttm: only trust snooping for dgfx when deciding default
cache_level
  drm/i915: instantiate ttm ranger manager for stolen memory
  drm/i915: sanitize mem_flags for stolen buffers
  drm/i915: ttm move/clear logic fix
  drm/i915/ttm: add buffer pin on alloc flag
  drm/i915/selftest: don't attempt engine reset of guc submission
engines
  drm/i915/selftest: maintain context ref during reset test
  drm/i915: stolen memory use ttm backend

 drivers/gpu/drm/i915/display/intel_fbc.c  |  78 ++--
 drivers/gpu/drm/i915/gem/i915_gem_object.c|   1 +
 .../gpu/drm/i915/gem/i915_gem_object_types.h  |  16 +-
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 425 ++
 drivers/gpu/drm/i915/gem/i915_gem_stolen.h|  21 +-
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   |  29 +-
 drivers/gpu/drm/i915/gem/i915_gem_ttm.h   |   7 +
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c  |  47 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c   |   4 +-
 drivers/gpu/drm/i915/gt/selftest_reset.c  |  35 +-
 drivers/gpu/drm/i915/i915_debugfs.c   |   7 +-
 drivers/gpu/drm/i915/i915_drv.h   |   6 +-
 drivers/gpu/drm/i915/intel_region_ttm.c   |  80 +++-
 drivers/gpu/drm/i915/intel_region_ttm.h   |   8 +-
 drivers/gpu/drm/i915/selftests/mock_region.c  |  12 +-
 15 files changed, 400 insertions(+), 376 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH v4 8/8] drm/i915: internal buffers use ttm backend

[Robert Beckett]

Create a kernel only internal memory region that uses ttm pool allocator to
allocate volatile system pages.
Refactor internal buffer backend to simply allocate from this new
region.

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/gem/i915_gem_internal.c  | 187 +-
 drivers/gpu/drm/i915/gem/i915_gem_internal.h  |   5 -
 drivers/gpu/drm/i915/i915_pci.c   |   4 +-
 drivers/gpu/drm/i915/intel_memory_region.c|   8 +-
 drivers/gpu/drm/i915/intel_memory_region.h|   2 +
 .../gpu/drm/i915/selftests/mock_gem_device.c  |   2 +-
 6 files changed, 17 insertions(+), 191 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c 
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index c698f95af15f..a83751867ac7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -4,188 +4,9 @@
  * Copyright © 2014-2016 Intel Corporation
  */
 
-#include 
-#include 
-#include 
-
+#include "gem/i915_gem_internal.h"
+#include "gem/i915_gem_region.h"
 #include "i915_drv.h"
-#include "i915_gem.h"
-#include "i915_gem_internal.h"
-#include "i915_gem_object.h"
-#include "i915_scatterlist.h"
-#include "i915_utils.h"
-
-#define QUIET (__GFP_NORETRY | __GFP_NOWARN)
-#define MAYFAIL (__GFP_RETRY_MAYFAIL | __GFP_NOWARN)
-
-static void internal_free_pages(struct sg_table *st)
-{
-   struct scatterlist *sg;
-
-   for (sg = st->sgl; sg; sg = __sg_next(sg)) {
-   if (sg_page(sg))
-   __free_pages(sg_page(sg), get_order(sg->length));
-   }
-
-   sg_free_table(st);
-   kfree(st);
-}
-
-static int i915_gem_object_get_pages_internal(struct drm_i915_gem_object *obj)
-{
-   struct drm_i915_private *i915 = to_i915(obj->base.dev);
-   struct sg_table *st;
-   struct scatterlist *sg;
-   unsigned int sg_page_sizes;
-   unsigned int npages;
-   int max_order;
-   gfp_t gfp;
-
-   max_order = MAX_ORDER;
-#ifdef CONFIG_SWIOTLB
-   if (is_swiotlb_active(obj->base.dev->dev)) {
-   unsigned int max_segment;
-
-   max_segment = swiotlb_max_segment();
-   if (max_segment) {
-   max_segment = max_t(unsigned int, max_segment,
-   PAGE_SIZE) >> PAGE_SHIFT;
-   max_order = min(max_order, ilog2(max_segment));
-   }
-   }
-#endif
-
-   gfp = GFP_KERNEL | __GFP_HIGHMEM | __GFP_RECLAIMABLE;
-   if (IS_I965GM(i915) || IS_I965G(i915)) {
-   /* 965gm cannot relocate objects above 4GiB. */
-   gfp &= ~__GFP_HIGHMEM;
-   gfp |= __GFP_DMA32;
-   }
-
-create_st:
-   st = kmalloc(sizeof(*st), GFP_KERNEL);
-   if (!st)
-   return -ENOMEM;
-
-   npages = obj->base.size / PAGE_SIZE;
-   if (sg_alloc_table(st, npages, GFP_KERNEL)) {
-   kfree(st);
-   return -ENOMEM;
-   }
-
-   sg = st->sgl;
-   st->nents = 0;
-   sg_page_sizes = 0;
-
-   do {
-   int order = min(fls(npages) - 1, max_order);
-   struct page *page;
-
-   do {
-   page = alloc_pages(gfp | (order ? QUIET : MAYFAIL),
-  order);
-   if (page)
-   break;
-   if (!order--)
-   goto err;
-
-   /* Limit subsequent allocations as well */
-   max_order = order;
-   } while (1);
-
-   sg_set_page(sg, page, PAGE_SIZE << order, 0);
-   sg_page_sizes |= PAGE_SIZE << order;
-   st->nents++;
-
-   npages -= 1 << order;
-   if (!npages) {
-   sg_mark_end(sg);
-   break;
-   }
-
-   sg = __sg_next(sg);
-   } while (1);
-
-   if (i915_gem_gtt_prepare_pages(obj, st)) {
-   /* Failed to dma-map try again with single page sg segments */
-   if (get_order(st->sgl->length)) {
-   internal_free_pages(st);
-   max_order = 0;
-   goto create_st;
-   }
-   goto err;
-   }
-
-   __i915_gem_object_set_pages(obj, st, sg_page_sizes);
-
-   return 0;
-
-err:
-   sg_set_page(sg, NULL, 0, 0);
-   sg_mark_end(sg);
-   internal_free_pages(st);
-
-   return -ENOMEM;
-}
-
-static void i915_gem_object_put_pages_internal(struct drm_i915_gem_object *obj,
-  struct sg_table *pages)
-{
-   i915_gem_gtt_finish_pages(obj, pages);
-   internal_free_pages(pages);
-
-   obj->mm.dirty = false;
-
-   __start_cpu_write(obj);
-}
-
-static const struct drm_i915_gem_object_ops i915_gem_object_internal_ops = {
-   .name = "i915_gem_object_internal",
-   .flags = I

[Intel-gfx] [PATCH v4 6/8] drm/i915: allow volatile buffers to use ttm pool allocator

[Robert Beckett]

Internal/volatile buffers should not be shmem backed.
If a volatile buffer is requested, allow ttm to use the pool allocator
to provide volatile pages as backing.
Fix i915_ttm_shrink to handle !is_shmem volatile buffers by purging.

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index b6c3fc25d9d1..599ed2713359 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -291,7 +291,8 @@ static struct ttm_tt *i915_ttm_tt_create(struct 
ttm_buffer_object *bo,
page_flags |= TTM_TT_FLAG_ZERO_ALLOC;
 
caching = i915_ttm_select_tt_caching(obj);
-   if (i915_gem_object_is_shrinkable(obj) && caching == ttm_cached) {
+   if (i915_gem_object_is_shrinkable(obj) && caching == ttm_cached &&
+   !i915_gem_object_is_volatile(obj)) {
page_flags |= TTM_TT_FLAG_EXTERNAL |
  TTM_TT_FLAG_EXTERNAL_MAPPABLE;
i915_tt->is_shmem = true;
@@ -513,9 +514,9 @@ static int i915_ttm_shrink(struct drm_i915_gem_object *obj, 
unsigned int flags)
if (!bo->ttm || bo->resource->mem_type != TTM_PL_SYSTEM)
return 0;
 
-   GEM_BUG_ON(!i915_tt->is_shmem);
+   GEM_BUG_ON(!i915_tt->is_shmem && obj->mm.madv != I915_MADV_DONTNEED);
 
-   if (!i915_tt->filp)
+   if (i915_tt->is_shmem && !i915_tt->filp)
return 0;
 
ret = ttm_bo_wait_ctx(bo, &ctx);
-- 
2.25.1

[Intel-gfx] [PATCH v4 7/8] drm/i915/gem: further fix mman selftest

[Robert Beckett]

In commit 450cede7f380 ("drm/i915/gem: Fix the mman selftest") we fixed up
the mman selftest to allocate user buffers via smem only if we have lmem,
otherwise it uses internal buffers.

As the commit message asserts, we should only be using buffers that
userland should be able to create.
Internal buffers are not intended to be used by userland.

Instead, fix the code to always create buffers from smem.
In the case of integrated, this will create them from the shmem non-ttm
backend, which is fine.

This also fixes up the code to allow conversion of internal backend to
ttm without breaking this test.

Signed-off-by: Robert Beckett 
---
 .../gpu/drm/i915/gem/selftests/i915_gem_mman.c  | 17 ++---
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 3ced9948a331..e529eb8461ff 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -596,17 +596,12 @@ static enum i915_mmap_type default_mapping(struct 
drm_i915_private *i915)
 }
 
 static struct drm_i915_gem_object *
-create_sys_or_internal(struct drm_i915_private *i915,
-  unsigned long size)
+create_sys(struct drm_i915_private *i915, unsigned long size)
 {
-   if (HAS_LMEM(i915)) {
-   struct intel_memory_region *sys_region =
-   i915->mm.regions[INTEL_REGION_SMEM];
+   struct intel_memory_region *sys_region =
+   i915->mm.regions[INTEL_REGION_SMEM];
 
-   return __i915_gem_object_create_user(i915, size, &sys_region, 
1);
-   }
-
-   return i915_gem_object_create_internal(i915, size);
+   return __i915_gem_object_create_user(i915, size, &sys_region, 1);
 }
 
 static bool assert_mmap_offset(struct drm_i915_private *i915,
@@ -617,7 +612,7 @@ static bool assert_mmap_offset(struct drm_i915_private 
*i915,
u64 offset;
int ret;
 
-   obj = create_sys_or_internal(i915, size);
+   obj = create_sys(i915, size);
if (IS_ERR(obj))
return expected && expected == PTR_ERR(obj);
 
@@ -719,7 +714,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
}
 
/* Fill the hole, further allocation attempts should then fail */
-   obj = create_sys_or_internal(i915, PAGE_SIZE);
+   obj = create_sys(i915, PAGE_SIZE);
if (IS_ERR(obj)) {
err = PTR_ERR(obj);
pr_err("Unable to create object for reclaimed hole\n");
-- 
2.25.1

[Intel-gfx] [PATCH v4 1/8] drm/i915/ttm: dont trample cache_level overrides during ttm move

[Robert Beckett]

Various places within the driver override the default chosen cache_level.
Before ttm, these overrides were permanent until explicitly changed again
or for the lifetime of the buffer.

TTM movement code came along and decided that it could make that
decision at that time, which is usually well after object creation, so
overrode the cache_level decision and reverted it back to its default
decision.

Add logic to indicate whether the caching mode has been set by anything
other than the move logic. If so, assume that the code that overrode the
defaults knows best and keep it.

Signed-off-by: Robert Beckett 
Reviewed-by: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_object.c   | 1 +
 drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c  | 1 +
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 9 ++---
 4 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index ccec4055fde3..966ac2d778d5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -125,6 +125,7 @@ void i915_gem_object_set_cache_coherency(struct 
drm_i915_gem_object *obj,
struct drm_i915_private *i915 = to_i915(obj->base.dev);
 
obj->cache_level = cache_level;
+   obj->ttm.cache_level_override = true;
 
if (cache_level != I915_CACHE_NONE)
obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ |
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 5cf36a130061..14937cf1daaa 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -623,6 +623,7 @@ struct drm_i915_gem_object {
struct i915_gem_object_page_iter get_io_page;
struct drm_i915_gem_object *backup;
bool created:1;
+   bool cache_level_override:1;
} ttm;
 
/*
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 053b0022ddd0..b6c3fc25d9d1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -1253,6 +1253,7 @@ int __i915_gem_ttm_object_init(struct intel_memory_region 
*mem,
i915_gem_object_init_memory_region(obj, mem);
i915_ttm_adjust_domains_after_move(obj);
i915_ttm_adjust_gem_after_move(obj);
+   obj->ttm.cache_level_override = false;
i915_gem_object_unlock(obj);
 
return 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 9a7e50534b84..042c2237e287 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -129,9 +129,12 @@ void i915_ttm_adjust_gem_after_move(struct 
drm_i915_gem_object *obj)
obj->mem_flags |= i915_ttm_cpu_maps_iomem(bo->resource) ? 
I915_BO_FLAG_IOMEM :
I915_BO_FLAG_STRUCT_PAGE;
 
-   cache_level = i915_ttm_cache_level(to_i915(bo->base.dev), bo->resource,
-  bo->ttm);
-   i915_gem_object_set_cache_coherency(obj, cache_level);
+   if (!obj->ttm.cache_level_override) {
+   cache_level = i915_ttm_cache_level(to_i915(bo->base.dev),
+  bo->resource, bo->ttm);
+   i915_gem_object_set_cache_coherency(obj, cache_level);
+   obj->ttm.cache_level_override = false;
+   }
 }
 
 /**
-- 
2.25.1

[Intel-gfx] [PATCH v4 5/8] drm/i915: setup ggtt scratch page after memory regions

[Robert Beckett]

Reorder scratch page allocation so that memory regions are available
to allocate the buffers

Signed-off-by: Robert Beckett 
Reviewed-by: Thomas Hellström 
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c | 20 ++--
 drivers/gpu/drm/i915/gt/intel_gtt.h  |  1 +
 drivers/gpu/drm/i915/i915_driver.c   | 16 ++--
 3 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 15a915bb4088..c4ad03e53236 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -866,8 +866,6 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 
size)
struct drm_i915_private *i915 = ggtt->vm.i915;
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
phys_addr_t phys_addr;
-   u32 pte_flags;
-   int ret;
 
GEM_WARN_ON(pci_resource_len(pdev, 0) != gen6_gttmmadr_size(i915));
phys_addr = pci_resource_start(pdev, 0) + gen6_gttadr_offset(i915);
@@ -889,6 +887,24 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 
size)
}
 
kref_init(&ggtt->vm.resv_ref);
+
+   return 0;
+}
+
+/**
+ * i915_ggtt_setup_scratch_page - setup ggtt scratch page
+ * @i915: i915 device
+ */
+int i915_ggtt_setup_scratch_page(struct drm_i915_private *i915)
+{
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
+   u32 pte_flags;
+   int ret;
+
+   /* gen5- scratch setup currently happens in @intel_gtt_init */
+   if (GRAPHICS_VER(i915) <= 5)
+   return 0;
+
ret = setup_scratch_page(&ggtt->vm);
if (ret) {
drm_err(&i915->drm, "Scratch setup failed\n");
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h 
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index e639434e97fd..4ebdf70b5273 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -579,6 +579,7 @@ void intel_ggtt_unbind_vma(struct i915_address_space *vm,
   struct i915_vma_resource *vma_res);
 
 int i915_ggtt_probe_hw(struct drm_i915_private *i915);
+int i915_ggtt_setup_scratch_page(struct drm_i915_private *i915);
 int i915_ggtt_init_hw(struct drm_i915_private *i915);
 int i915_ggtt_enable_hw(struct drm_i915_private *i915);
 void i915_ggtt_enable_guc(struct i915_ggtt *ggtt);
diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index deb8a8b76965..fa0956840fcc 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -69,6 +69,7 @@
 #include "gem/i915_gem_mman.h"
 #include "gem/i915_gem_pm.h"
 #include "gt/intel_gt.h"
+#include "gt/intel_gtt.h"
 #include "gt/intel_gt_pm.h"
 #include "gt/intel_rc6.h"
 
@@ -609,12 +610,16 @@ static int i915_driver_hw_probe(struct drm_i915_private 
*dev_priv)
 
ret = intel_gt_tiles_init(dev_priv);
if (ret)
-   goto err_mem_regions;
+   goto err_ggtt;
+
+   ret = i915_ggtt_setup_scratch_page(dev_priv);
+   if (ret)
+   goto err_ggtt;
 
ret = i915_ggtt_enable_hw(dev_priv);
if (ret) {
drm_err(&dev_priv->drm, "failed to enable GGTT\n");
-   goto err_mem_regions;
+   goto err_ggtt;
}
 
pci_set_master(pdev);
@@ -675,11 +680,10 @@ static int i915_driver_hw_probe(struct drm_i915_private 
*dev_priv)
 err_msi:
if (pdev->msi_enabled)
pci_disable_msi(pdev);
-err_mem_regions:
-   intel_memory_regions_driver_release(dev_priv);
 err_ggtt:
i915_ggtt_driver_release(dev_priv);
i915_gem_drain_freed_objects(dev_priv);
+   intel_memory_regions_driver_release(dev_priv);
i915_ggtt_driver_late_release(dev_priv);
 err_perf:
i915_perf_fini(dev_priv);
@@ -928,9 +932,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct 
pci_device_id *ent)
intel_modeset_driver_remove_nogem(i915);
 out_cleanup_hw:
i915_driver_hw_remove(i915);
-   intel_memory_regions_driver_release(i915);
i915_ggtt_driver_release(i915);
i915_gem_drain_freed_objects(i915);
+   intel_memory_regions_driver_release(i915);
i915_ggtt_driver_late_release(i915);
 out_cleanup_mmio:
i915_driver_mmio_release(i915);
@@ -987,9 +991,9 @@ static void i915_driver_release(struct drm_device *dev)
 
i915_gem_driver_release(dev_priv);
 
-   intel_memory_regions_driver_release(dev_priv);
i915_ggtt_driver_release(dev_priv);
i915_gem_drain_freed_objects(dev_priv);
+   intel_memory_regions_driver_release(dev_priv);
i915_ggtt_driver_late_release(dev_priv);
 
i915_driver_mmio_release(dev_priv);
-- 
2.25.1

[Intel-gfx] [PATCH v4 4/8] drm/i915: add gen6 ppgtt dummy creation function

[Robert Beckett]

Internal gem objects will soon just be volatile system memory region
objects.
To enable this, create a separate dummy object creation function
for gen6 ppgtt. The object only exists as a fake object pointing to ggtt
and gains no benefit in going via the internal backend.
Instead, create a dummy gem object and avoid having to maintain a custom
ops api in the internal backend, which makes later refactoring easier.

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 43 ++--
 1 file changed, 40 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c 
b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 1bb766c79dcb..f3b660cfeb7f 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -372,6 +372,45 @@ static const struct drm_i915_gem_object_ops 
pd_dummy_obj_ops = {
.put_pages = pd_dummy_obj_put_pages,
 };
 
+static struct drm_i915_gem_object *
+i915_gem_object_create_dummy(struct drm_i915_private *i915, phys_addr_t size)
+{
+   static struct lock_class_key lock_class;
+   struct drm_i915_gem_object *obj;
+   unsigned int cache_level;
+
+   GEM_BUG_ON(!size);
+   GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE));
+
+   if (overflows_type(size, obj->base.size))
+   return ERR_PTR(-E2BIG);
+
+   obj = i915_gem_object_alloc();
+   if (!obj)
+   return ERR_PTR(-ENOMEM);
+
+   drm_gem_private_object_init(&i915->drm, &obj->base, size);
+   i915_gem_object_init(obj, &pd_dummy_obj_ops, &lock_class, 0);
+   obj->mem_flags |= I915_BO_FLAG_STRUCT_PAGE;
+
+   /*
+* Mark the object as volatile, such that the pages are marked as
+* dontneed whilst they are still pinned. As soon as they are unpinned
+* they are allowed to be reaped by the shrinker, and the caller is
+* expected to repopulate - the contents of this object are only valid
+* whilst active and pinned.
+*/
+   i915_gem_object_set_volatile(obj);
+
+   obj->read_domains = I915_GEM_DOMAIN_CPU;
+   obj->write_domain = I915_GEM_DOMAIN_CPU;
+
+   cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE;
+   i915_gem_object_set_cache_coherency(obj, cache_level);
+
+   return obj;
+}
+
 static struct i915_page_directory *
 gen6_alloc_top_pd(struct gen6_ppgtt *ppgtt)
 {
@@ -383,9 +422,7 @@ gen6_alloc_top_pd(struct gen6_ppgtt *ppgtt)
if (unlikely(!pd))
return ERR_PTR(-ENOMEM);
 
-   pd->pt.base = __i915_gem_object_create_internal(ppgtt->base.vm.gt->i915,
-   &pd_dummy_obj_ops,
-   I915_PDES * SZ_4K);
+   pd->pt.base = i915_gem_object_create_dummy(ppgtt->base.vm.gt->i915, 
I915_PDES * SZ_4K);
if (IS_ERR(pd->pt.base)) {
err = PTR_ERR(pd->pt.base);
pd->pt.base = NULL;
-- 
2.25.1

[Intel-gfx] [PATCH v4 3/8] drm/i915/ttm: only trust snooping for dgfx when deciding default cache_level

[Robert Beckett]

By default i915_ttm_cache_level() decides I915_CACHE_LLC if HAS_SNOOP.
This is divergent from existing backends code which only considers
HAS_LLC.
Testing shows that trusting snooping on gen5- is unreliable and bsw via
ggtt mappings, so limit DGFX for now and maintain previous behaviour.

Signed-off-by: Robert Beckett 
Reviewed-by: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 042c2237e287..a949594237d9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -52,7 +52,9 @@ static enum i915_cache_level
 i915_ttm_cache_level(struct drm_i915_private *i915, struct ttm_resource *res,
 struct ttm_tt *ttm)
 {
-   return ((HAS_LLC(i915) || HAS_SNOOP(i915)) &&
+   bool can_snoop = HAS_SNOOP(i915) && IS_DGFX(i915);
+
+   return ((HAS_LLC(i915) || can_snoop) &&
!i915_ttm_gtt_binds_lmem(res) &&
ttm->caching == ttm_cached) ? I915_CACHE_LLC :
I915_CACHE_NONE;
-- 
2.25.1

[Intel-gfx] [PATCH v4 2/8] drm/i915: limit ttm to dma32 for i965G[M]

[Robert Beckett]

i965G[M] cannot relocate objects above 4GiB.
Ensure ttm uses dma32 on these systems.

Signed-off-by: Robert Beckett 
Reviewed-by: Thomas Hellström 
---
 drivers/gpu/drm/i915/intel_region_ttm.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c 
b/drivers/gpu/drm/i915/intel_region_ttm.c
index 6873808a7015..642cd1587976 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -32,10 +32,15 @@
 int intel_region_ttm_device_init(struct drm_i915_private *dev_priv)
 {
struct drm_device *drm = &dev_priv->drm;
+   bool use_dma32 = false;
+
+   /* i965g[m] cannot relocate objects above 4GiB. */
+   if (IS_I965GM(dev_priv) || IS_I965G(dev_priv))
+   use_dma32 = true;
 
return ttm_device_init(&dev_priv->bdev, i915_ttm_driver(),
   drm->dev, drm->anon_inode->i_mapping,
-  drm->vma_offset_manager, false, false);
+  drm->vma_offset_manager, false, use_dma32);
 }
 
 /**
-- 
2.25.1

[Intel-gfx] [PATCH v4 0/8] drm/i915: ttm for internal

[Robert Beckett]

This series refactors i915's internal buffer backend to use ttm.
It uses ttm's pool allocator to allocate volatile pages in place of the
old code which rolled its own via alloc_pages.
This is continuing progress to align all backends on using ttm.

v2: - commit message improvements to add detail
- fix i915_ttm_shrink to purge !is_shmem volatile buffers
- limit ttm pool allocator to using dma32 on i965G[M]
- fix mman selftest to always use smem buffers
- create new internal memory region
- make internal backend allocate from internal region
- Fixed various issues with tests and i915 ttm usage as a result
  of supporting regions other than lmem via ttm.

v3: - limit i915 ttm default cache_level selection to only trust
  HAS_SNOOP on DGFX.

v4: - rebase to drm-tip and handle conflicts

Robert Beckett (8):
  drm/i915/ttm: dont trample cache_level overrides during ttm move
  drm/i915: limit ttm to dma32 for i965G[M]
  drm/i915/ttm: only trust snooping for dgfx when deciding default
cache_level
  drm/i915: add gen6 ppgtt dummy creation function
  drm/i915: setup ggtt scratch page after memory regions
  drm/i915: allow volatile buffers to use ttm pool allocator
  drm/i915/gem: further fix mman selftest
  drm/i915: internal buffers use ttm backend

 drivers/gpu/drm/i915/gem/i915_gem_internal.c  | 187 +-
 drivers/gpu/drm/i915/gem/i915_gem_internal.h  |   5 -
 drivers/gpu/drm/i915/gem/i915_gem_object.c|   1 +
 .../gpu/drm/i915/gem/i915_gem_object_types.h  |   1 +
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   |   8 +-
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c  |  13 +-
 .../drm/i915/gem/selftests/i915_gem_mman.c|  17 +-
 drivers/gpu/drm/i915/gt/gen6_ppgtt.c  |  43 +++-
 drivers/gpu/drm/i915/gt/intel_ggtt.c  |  20 +-
 drivers/gpu/drm/i915/gt/intel_gtt.h   |   1 +
 drivers/gpu/drm/i915/i915_driver.c|  16 +-
 drivers/gpu/drm/i915/i915_pci.c   |   4 +-
 drivers/gpu/drm/i915/intel_memory_region.c|   8 +-
 drivers/gpu/drm/i915/intel_memory_region.h|   2 +
 drivers/gpu/drm/i915/intel_region_ttm.c   |   7 +-
 .../gpu/drm/i915/selftests/mock_gem_device.c  |   2 +-
 16 files changed, 114 insertions(+), 221 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH v5 2/2] drm/i915: Add lmem_bar_size modparam

[priyanka . dandamudi]

From: Priyanka Dandamudi 

For testing purposes, support forcing the lmem_bar_size through a new
modparam. In CI we only have a limited number of configurations for DG2,
but we still need to be reasonably sure we get a usable device (also
verifying we report the correct values for things like
probed_cpu_visible_size etc) with all the potential lmem_bar sizes that
we might expect see in the wild.

v2: Update commit message and a minor modification.(Matt)

v3: Optimised lmem bar size code and modified code to resize
bar maximum upto lmem_size instead of maximum supported size.(Nirmoy)

v4: Optimised lmem bar size code.(Nirmoy)

Cc: Matthew Auld 
Cc: Nirmoy Das 

Signed-off-by: Priyanka Dandamudi 
Reviewed-by: Nirmoy Das 
---
 drivers/gpu/drm/i915/gt/intel_region_lmem.c | 34 ++---
 drivers/gpu/drm/i915/i915_params.c  |  2 ++
 drivers/gpu/drm/i915/i915_params.h  |  1 +
 3 files changed, 32 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c 
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 72491ba9e72f..5ee6982248d4 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -51,15 +51,39 @@ static void i915_resize_lmem_bar(struct drm_i915_private 
*i915, resource_size_t
struct pci_bus *root = pdev->bus;
struct resource *root_res;
resource_size_t rebar_size;
+   resource_size_t current_size;
u32 pci_cmd;
int i;
 
-   rebar_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
+   current_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
 
-   if (rebar_size != roundup_pow_of_two(lmem_size))
-   rebar_size = lmem_size;
-   else
-   return;
+   if (i915->params.lmem_bar_size) {
+   u32 bar_sizes;
+
+   rebar_size = i915->params.lmem_bar_size *
+   (resource_size_t)SZ_1M;
+   bar_sizes = pci_rebar_get_possible_sizes(pdev,
+LMEM_BAR_NUM);
+
+   if (rebar_size == current_size)
+   return;
+
+   if (!(bar_sizes & BIT(pci_rebar_bytes_to_size(rebar_size))) ||
+   rebar_size >= roundup_pow_of_two(lmem_size)) {
+   rebar_size = lmem_size;
+
+   drm_info(&i915->drm,
+"Given bar size is not within supported 
size,setting it to default: %llu\n",
+(u64)lmem_size >> 20);
+   }
+   } else {
+   rebar_size = current_size;
+
+   if (rebar_size != roundup_pow_of_two(lmem_size))
+   rebar_size = lmem_size;
+   else
+   return;
+   }
 
/* Find out if root bus contains 64bit memory addressing */
while (root->parent)
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 701fbc98afa0..6fc475a5db61 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -204,6 +204,8 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
 
 i915_param_named_unsafe(lmem_size, uint, 0400,
"Set the lmem size(in MiB) for each region. (default: 
0, all memory)");
+i915_param_named_unsafe(lmem_bar_size, uint, 0400,
+   "Set the lmem bar size(in MiB).");
 
 static __always_inline void _print_param(struct drm_printer *p,
 const char *name,
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index b5e7ea45d191..2733cb6cfe09 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -74,6 +74,7 @@ struct drm_printer;
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
param(unsigned int, request_timeout_ms, 
CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
param(unsigned int, lmem_size, 0, 0400) \
+   param(unsigned int, lmem_bar_size, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, load_detect_test, false, 0600) \
-- 
2.27.0

[Intel-gfx] [PATCH v5 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[priyanka . dandamudi]

From: Akeem G Abodunrin 

Add support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
systems. So, those devices cannot claim larger memory BAR windows size due
to the system BIOS limitation. With this change, it would be possible to
reprogram the windows of the bridge directly above the requesting device
on the same BAR type.

v2:Moved code to gt/intel_region_lmem.c and used only
single underscore for function names.(Jani)

v3: Optimised code.

Signed-off-by: Akeem G Abodunrin 
Signed-off-by: Michał Winiarski 
Cc: Stuart Summers 
Cc: Michael J Ruhl 
Cc: Prathap Kumar Valsan 
Cc: Jani Nikula 
Signed-off-by: Priyanka Dandamudi 
Reviewed-by: Matthew Auld 
Reviewed-by: Nirmoy Das 
---
 drivers/gpu/drm/i915/gt/intel_region_lmem.c | 75 +
 1 file changed, 75 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c 
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index fa7b86f83e7b..72491ba9e72f 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -15,6 +15,79 @@
 #include "gt/intel_gt_mcr.h"
 #include "gt/intel_gt_regs.h"
 
+static void _release_bars(struct pci_dev *pdev)
+{
+   int resno;
+
+   for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
+   if (pci_resource_len(pdev, resno))
+   pci_release_resource(pdev, resno);
+   }
+}
+
+static void
+_resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
+{
+   struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+   int bar_size = pci_rebar_bytes_to_size(size);
+   int ret;
+
+   _release_bars(pdev);
+
+   ret = pci_resize_resource(pdev, resno, bar_size);
+   if (ret) {
+   drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
+resno, 1 << bar_size, ERR_PTR(ret));
+   return;
+   }
+
+   drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
+}
+
+#define LMEM_BAR_NUM 2
+static void i915_resize_lmem_bar(struct drm_i915_private *i915, 
resource_size_t lmem_size)
+{
+   struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+   struct pci_bus *root = pdev->bus;
+   struct resource *root_res;
+   resource_size_t rebar_size;
+   u32 pci_cmd;
+   int i;
+
+   rebar_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
+
+   if (rebar_size != roundup_pow_of_two(lmem_size))
+   rebar_size = lmem_size;
+   else
+   return;
+
+   /* Find out if root bus contains 64bit memory addressing */
+   while (root->parent)
+   root = root->parent;
+
+   pci_bus_for_each_resource(root, root_res, i) {
+   if (root_res && root_res->flags & (IORESOURCE_MEM |
+   IORESOURCE_MEM_64) && 
upper_32_bits(root_res->start) != 0)
+   break;
+   }
+
+   /* pci_resize_resource will fail anyways */
+   if (!root_res) {
+   drm_info(&i915->drm, "Can't resize LMEM BAR - platform support 
is missing\n");
+   return;
+   }
+
+   /* First disable PCI memory decoding references */
+   pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
+   pci_write_config_dword(pdev, PCI_COMMAND,
+  pci_cmd & ~PCI_COMMAND_MEMORY);
+
+   _resize_bar(i915, LMEM_BAR_NUM, rebar_size);
+
+   pci_assign_unassigned_bus_resources(pdev->bus);
+   pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
+}
+
 static int
 region_lmem_release(struct intel_memory_region *mem)
 {
@@ -128,6 +201,8 @@ static struct intel_memory_region *setup_lmem(struct 
intel_gt *gt)
lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
}
 
+   i915_resize_lmem_bar(i915, lmem_size);
+
if (i915->params.lmem_size > 0) {
lmem_size = min_t(resource_size_t, lmem_size,
  mul_u32_u32(i915->params.lmem_size, SZ_1M));
-- 
2.27.0

[Intel-gfx] [PATCH v5 0/2] Add support for LMEM PCIe resizable bar

[priyanka . dandamudi]

From: Priyanka Dandamudi 

Added support to resize the bar to maximum supported.
Also, added new modparam lmem_bar_size which can resize the bar to one of the 
supported sizes.

Akeem G Abodunrin (1):
  drm/i915: Add support for LMEM PCIe resizable bar

Priyanka Dandamudi (1):
  drm/i915: Add lmem_bar_size modparam

 drivers/gpu/drm/i915/gt/intel_region_lmem.c | 99 +
 drivers/gpu/drm/i915/i915_params.c  |  2 +
 drivers/gpu/drm/i915/i915_params.h  |  1 +
 3 files changed, 102 insertions(+)

-- 
2.27.0

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Fix performance regressions with TLB and add GuC support (rev2)

[Patchwork]

== Series Details ==

Series: Fix performance regressions with TLB and add GuC support (rev2)
URL   : https://patchwork.freedesktop.org/series/106293/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/106293/revisions/2/mbox/ not 
applied
Applying: drm/i915/gt: Ignore TLB invalidations on idle engines
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/gt/intel_gt.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/intel_gt.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_gt.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915/gt: Ignore TLB invalidations on idle engines
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

[Intel-gfx] linux-next: build failure after merge of the drm-intel-fixes tree

[Stephen Rothwell]

Hi all,

After merging the drm-intel-fixes tree, today's linux-next build (i386
defconfig) failed like this:

x86_64-linux-gnu-ld: drivers/gpu/drm/i915/i915_scatterlist.o: in function 
`i915_rsgt_from_mm_node':
i915_scatterlist.c:(.text+0x196): undefined reference to `__udivdi3'

Caused by commit

  aff1e0b09b54 ("drm/i915/ttm: fix sg_table construction")

I have reverted that commit for today.

-- 
Cheers,
Stephen Rothwell


pgpSnJ_MEUDdd.pgp
Description: OpenPGP digital signature

Re: [Intel-gfx] [PATCH 1/3] drm/i915: audit bo->resource usage

[Matthew Auld]

On Tue, 12 Jul 2022 at 12:46, Christian König
 wrote:
>
> Make sure we can at least move and alloc TT objects without backing store.
>
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_ttm.c  | 6 ++
>  drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 2 +-
>  2 files changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> index 70e2ed4e99df..5449738c262f 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> @@ -289,8 +289,6 @@ static struct ttm_tt *i915_ttm_tt_create(struct 
> ttm_buffer_object *bo,
>  {
> struct drm_i915_private *i915 = container_of(bo->bdev, typeof(*i915),
>  bdev);
> -   struct ttm_resource_manager *man =
> -   ttm_manager_type(bo->bdev, bo->resource->mem_type);
> struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
> unsigned long ccs_pages = 0;
> enum ttm_caching caching;
> @@ -304,8 +302,8 @@ static struct ttm_tt *i915_ttm_tt_create(struct 
> ttm_buffer_object *bo,
> if (!i915_tt)
> return NULL;
>
> -   if (obj->flags & I915_BO_ALLOC_CPU_CLEAR &&
> -   man->use_tt)
> +   if (obj->flags & I915_BO_ALLOC_CPU_CLEAR && bo->resource &&
> +   ttm_manager_type(bo->bdev, bo->resource->mem_type)->use_tt)
> page_flags |= TTM_TT_FLAG_ZERO_ALLOC;

AFAICT it should be safe to make this:

if (obj->flags & I915_BO_ALLOC_CPU_CLEAR)
page_flags |= TTM_TT_FLAG_ZERO_ALLOC;

Hopefully that fixes the igt_lmem_create_cleared_cpu subtest?

>
> caching = i915_ttm_select_tt_caching(obj);
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> index a10716f4e717..dcb838dffd7b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> @@ -490,7 +490,7 @@ int i915_ttm_move(struct ttm_buffer_object *bo, bool 
> evict,
> bool clear;
> int ret;
>
> -   if (GEM_WARN_ON(!obj)) {
> +   if (!bo->resource || GEM_WARN_ON(!obj)) {

IIUC in patch 3 we now nuke the bo->resource when doing the "pipeline
gutting" thing, but I think i915 is (ab)using that when swapping out
shmem objects (see i915_ttm_shrink), so I think here we need to
somehow inspect the tt to see if something needs to be swapped in? We
might also need to move it back to lmem after. Or maybe this is
already handled somehow? CI should hopefully be able to confirm
(gem_lmem_swapping).

> ttm_bo_move_null(bo, dst_mem);
> return 0;
> }
> --
> 2.25.1
>

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Fix performance regressions with TLB and add GuC support

[Patchwork]

== Series Details ==

Series: Fix performance regressions with TLB and add GuC support
URL   : https://patchwork.freedesktop.org/series/106293/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/106293/revisions/1/mbox/ not 
found

[Intel-gfx] [PATCH 00/21] Fix performance regressions with TLB and add GuC support

[Mauro Carvalho Chehab]

TLB invalidation is a slow operation. It should not be doing lightly, as it
causes performance regressions, like this:

[178.821002] i915 :00:02.0: [drm] *ERROR* rcs0 TLB invalidation did not 
complete in 4ms!

This series contain 

1) some patches that makes TLB invalidation to happen only on
active, non-wedged engines, doing cache invalidation in batch 
and only when GT objects are exposed to userspace:

  drm/i915/gt: Ignore TLB invalidations on idle engines
  drm/i915/gt: Only invalidate TLBs exposed to user manipulation
  drm/i915/gt: Skip TLB invalidations once wedged
  drm/i915/gt: Batch TLB invalidations
  drm/i915/gt: Move TLB invalidation to its own file

2) It fixes two bugs, being the first a workaround:

  drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations
  drm/i915: Invalidate the TLBs on each GT

  drm/i915/guc: Introduce TLB_INVALIDATION_ALL action

3) It adds GuC support. Besides providing TLB invalidation on some
additional hardware, this should also help serializing GuC operations
with TLB invalidation:

  drm/i915/guc: Introduce TLB_INVALIDATION_ALL action
  drm/i915/guc: Define CTB based TLB invalidation routines
  drm/i915: Add platform macro for selective tlb flush
  drm/i915: Define GuC Based TLB invalidation routines
  drm/i915: Add generic interface for tlb invalidation for XeHP
  drm/i915: Use selective tlb invalidations where supported

4) It adds the corresponding kernel-doc markups for the kAPI
used for TLB invalidation.

While I could have split this into smaller pieces, I'm opting to send
them altogether, in order for CI trybot to better verify what issues
will be closed with this series.

---

Chris Wilson (7):
  drm/i915/gt: Ignore TLB invalidations on idle engines
  drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations
  drm/i915/gt: Only invalidate TLBs exposed to user manipulation
  drm/i915/gt: Skip TLB invalidations once wedged
  drm/i915/gt: Batch TLB invalidations
  drm/i915/gt: Move TLB invalidation to its own file
  drm/i915: Invalidate the TLBs on each GT

Mauro Carvalho Chehab (8):
  drm/i915/gt: document with_intel_gt_pm_if_awake()
  drm/i915/gt: describe the new tlb parameter at i915_vma_resource
  drm/i915/guc: use kernel-doc for enum intel_guc_tlb_inval_mode
  drm/i915/guc: document the TLB invalidation struct members
  drm/i915: document tlb field at struct drm_i915_gem_object
  drm/i915/gt: document TLB cache invalidation functions
  drm/i915/guc: describe enum intel_guc_tlb_invalidation_type
  drm/i915/guc: document TLB cache invalidation functions

Piotr Piórkowski (1):
  drm/i915/guc: Introduce TLB_INVALIDATION_ALL action

Prathap Kumar Valsan (5):
  drm/i915/guc: Define CTB based TLB invalidation routines
  drm/i915: Add platform macro for selective tlb flush
  drm/i915: Define GuC Based TLB invalidation routines
  drm/i915: Add generic interface for tlb invalidation for XeHP
  drm/i915: Use selective tlb invalidations where supported

 drivers/gpu/drm/i915/Makefile |   1 +
 .../gpu/drm/i915/gem/i915_gem_object_types.h  |   6 +-
 drivers/gpu/drm/i915/gem/i915_gem_pages.c |  28 +-
 drivers/gpu/drm/i915/gt/intel_engine.h|   1 +
 drivers/gpu/drm/i915/gt/intel_gt.c| 125 +---
 drivers/gpu/drm/i915/gt/intel_gt.h|   2 -
 .../gpu/drm/i915/gt/intel_gt_buffer_pool.h|   3 +-
 drivers/gpu/drm/i915/gt/intel_gt_defines.h|  11 +
 drivers/gpu/drm/i915/gt/intel_gt_pm.h |  10 +
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   |   8 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h  |  22 +-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c |   8 +-
 drivers/gpu/drm/i915/gt/intel_tlb.c   | 295 ++
 drivers/gpu/drm/i915/gt/intel_tlb.h   |  30 ++
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  54 
 drivers/gpu/drm/i915/gt/uc/intel_guc.c| 232 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  36 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |  24 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   9 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  91 +-
 drivers/gpu/drm/i915/i915_drv.h   |   4 +-
 drivers/gpu/drm/i915/i915_pci.c   |   1 +
 drivers/gpu/drm/i915/i915_vma.c   |  46 ++-
 drivers/gpu/drm/i915/i915_vma.h   |   2 +
 drivers/gpu/drm/i915/i915_vma_resource.c  |   9 +-
 drivers/gpu/drm/i915/i915_vma_resource.h  |   6 +-
 drivers/gpu/drm/i915/intel_device_info.h  |   1 +
 27 files changed, 910 insertions(+), 155 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_defines.h
 create mode 100644 drivers/gpu/drm/i915/gt/intel_tlb.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_tlb.h

-- 
2.36.1

[Intel-gfx] [PATCH 08/21] drm/i915/gt: Move TLB invalidation to its own file

[Mauro Carvalho Chehab]

From: Chris Wilson 

Prepare for supporting more TLB invalidation scenarios by moving
the current MMIO invalidation to its own file.

Signed-off-by: Chris Wilson 
Cc: Fei Yang 
Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/gem/i915_gem_pages.c |   4 +-
 drivers/gpu/drm/i915/gt/intel_gt.c| 168 +---
 drivers/gpu/drm/i915/gt/intel_gt.h|  12 --
 drivers/gpu/drm/i915/gt/intel_tlb.c   | 183 ++
 drivers/gpu/drm/i915/gt/intel_tlb.h   |  29 
 drivers/gpu/drm/i915/i915_vma.c   |   1 +
 7 files changed, 219 insertions(+), 179 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_tlb.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_tlb.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 522ef9b4aff3..d3df9832d1f7 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -126,6 +126,7 @@ gt-y += \
gt/intel_sseu.o \
gt/intel_sseu_debugfs.o \
gt/intel_timeline.o \
+   gt/intel_tlb.o \
gt/intel_workarounds.o \
gt/shmem_utils.o \
gt/sysfs_engines.o
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c 
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 8357dbdcab5c..1cd76cc5d9f3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -7,7 +7,7 @@
 #include 
 
 #include "gt/intel_gt.h"
-#include "gt/intel_gt_pm.h"
+#include "gt/intel_tlb.h"
 
 #include "i915_drv.h"
 #include "i915_gem_object.h"
@@ -199,7 +199,7 @@ static void flush_tlb_invalidate(struct drm_i915_gem_object 
*obj)
if (!obj->mm.tlb)
return;
 
-   intel_gt_invalidate_tlb(gt, obj->mm.tlb);
+   intel_gt_invalidate_tlb_full(gt, obj->mm.tlb);
obj->mm.tlb = 0;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f435e06125aa..18d82cd620bd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -11,9 +11,7 @@
 #include "pxp/intel_pxp.h"
 
 #include "i915_drv.h"
-#include "i915_perf_oa_regs.h"
 #include "intel_context.h"
-#include "intel_engine_pm.h"
 #include "intel_engine_regs.h"
 #include "intel_ggtt_gmch.h"
 #include "intel_gt.h"
@@ -31,6 +29,7 @@
 #include "intel_renderstate.h"
 #include "intel_rps.h"
 #include "intel_gt_sysfs.h"
+#include "intel_tlb.h"
 #include "intel_uncore.h"
 #include "shmem_utils.h"
 
@@ -48,8 +47,7 @@ static void __intel_gt_init_early(struct intel_gt *gt)
intel_gt_init_reset(gt);
intel_gt_init_requests(gt);
intel_gt_init_timelines(gt);
-   mutex_init(>->tlb.invalidate_lock);
-   seqcount_mutex_init(>->tlb.seqno, >->tlb.invalidate_lock);
+   intel_gt_init_tlb(gt);
intel_gt_pm_init_early(gt);
 
intel_uc_init_early(>->uc);
@@ -770,7 +768,7 @@ void intel_gt_driver_late_release_all(struct 
drm_i915_private *i915)
intel_gt_fini_requests(gt);
intel_gt_fini_reset(gt);
intel_gt_fini_timelines(gt);
-   mutex_destroy(>->tlb.invalidate_lock);
+   intel_gt_fini_tlb(gt);
intel_engines_free(gt);
}
 }
@@ -881,163 +879,3 @@ void intel_gt_info_print(const struct intel_gt_info *info,
 
intel_sseu_dump(&info->sseu, p);
 }
-
-struct reg_and_bit {
-   i915_reg_t reg;
-   u32 bit;
-};
-
-static struct reg_and_bit
-get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8,
-   const i915_reg_t *regs, const unsigned int num)
-{
-   const unsigned int class = engine->class;
-   struct reg_and_bit rb = { };
-
-   if (drm_WARN_ON_ONCE(&engine->i915->drm,
-class >= num || !regs[class].reg))
-   return rb;
-
-   rb.reg = regs[class];
-   if (gen8 && class == VIDEO_DECODE_CLASS)
-   rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */
-   else
-   rb.bit = engine->instance;
-
-   rb.bit = BIT(rb.bit);
-
-   return rb;
-}
-
-static void mmio_invalidate_full(struct intel_gt *gt)
-{
-   static const i915_reg_t gen8_regs[] = {
-   [RENDER_CLASS]  = GEN8_RTCR,
-   [VIDEO_DECODE_CLASS]= GEN8_M1TCR, /* , GEN8_M2TCR */
-   [VIDEO_ENHANCEMENT_CLASS]   = GEN8_VTCR,
-   [COPY_ENGINE_CLASS] = GEN8_BTCR,
-   };
-   static const i915_reg_t gen12_regs[] = {
-   [RENDER_CLASS]  = GEN12_GFX_TLB_INV_CR,
-   [VIDEO_DECODE_CLASS]= GEN12_VD_TLB_INV_CR,
-   [VIDEO_ENHANCEMENT_CLASS]   = GEN12_VE_TLB_INV_CR,
-   [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
-   [COMPUTE_CLASS] = G

[Intel-gfx] [PATCH 04/21] drm/i915/gt: Only invalidate TLBs exposed to user manipulation

[Mauro Carvalho Chehab]

From: Chris Wilson 

Don't flush TLBs when the buffer is only used in the GGTT under full
control of the kernel, as there's no risk of concurrent access
and stale access from prefetch.

We only need to invalidate the TLB if they are accessible by the user.
That helps to reduce the performance regression introduced by TLB
invalidate logic.

Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Signed-off-by: Chris Wilson 
Cc: Fei Yang 
Cc: Andi Shyti 
Acked-by: Thomas Hellström 
Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/i915_vma.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index ef3b04c7e153..646f419b2035 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -538,7 +538,8 @@ int i915_vma_bind(struct i915_vma *vma,
   bind_flags);
}
 
-   set_bit(I915_BO_WAS_BOUND_BIT, &vma->obj->flags);
+   if (bind_flags & I915_VMA_LOCAL_BIND)
+   set_bit(I915_BO_WAS_BOUND_BIT, &vma->obj->flags);
 
atomic_or(bind_flags, &vma->flags);
return 0;
-- 
2.36.1

[Intel-gfx] [PATCH 21/21] drm/i915/guc: document TLB cache invalidation functions

[Mauro Carvalho Chehab]

Add documentation for the kAPI functions that do TLB cache
invalidation via GuC.

Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/gt/uc/intel_guc.c | 52 ++
 1 file changed, 45 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 98260a7bc90b..173833bc3a62 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -923,7 +923,14 @@ static int guc_send_invalidate_tlb(struct intel_guc *guc, 
u32 *action, u32 size)
return err;
 }
 
- /* Full TLB invalidation */
+/**
+ * intel_guc_invalidate_tlb_full - GuC full TLB invalidation
+ *
+ * @guc: the guc
+ * @mode: mode of TLB cache invalidation (heavy or lite)
+ *
+ * Use GuC to do a full TLB cache invalidation if supported.
+ */
 int intel_guc_invalidate_tlb_full(struct intel_guc *guc,
  enum intel_guc_tlb_inval_mode mode)
 {
@@ -943,8 +950,17 @@ int intel_guc_invalidate_tlb_full(struct intel_guc *guc,
return guc_send_invalidate_tlb(guc, action, ARRAY_SIZE(action));
 }
 
-/*
- * Selective TLB Invalidation for Address Range:
+/**
+ * intel_guc_invalidate_tlb_page_selective - GuC selective TLB invalidation
+ * for an address range
+ *
+ * @guc: the guc
+ * @mode: mode of TLB cache invalidation (heavy or lite)
+ * @start: range start
+ * @length: range length
+ *
+ * Use GuC to do a selective TLB invalidation if supported.
+ *
  * TLB's in the Address Range is Invalidated across all engines.
  */
 int intel_guc_invalidate_tlb_page_selective(struct intel_guc *guc,
@@ -978,8 +994,18 @@ int intel_guc_invalidate_tlb_page_selective(struct 
intel_guc *guc,
return guc_send_invalidate_tlb(guc, action, ARRAY_SIZE(action));
 }
 
-/*
- * Selective TLB Invalidation for Context:
+/**
+ * intel_guc_invalidate_tlb_page_selective_ctx - GuC selective TLB
+ * invalidation for a context
+ *
+ * @guc: the guc
+ * @mode: mode of TLB cache invalidation (heavy or lite)
+ * @start: range start
+ * @length: range length
+ * @ctxid: context ID
+ *
+ * Use GuC to do a selective TLB invalidation on a context if supported.
+ *
  * Invalidates all TLB's for a specific context across all engines.
  */
 int intel_guc_invalidate_tlb_page_selective_ctx(struct intel_guc *guc,
@@ -1013,8 +1039,13 @@ int intel_guc_invalidate_tlb_page_selective_ctx(struct 
intel_guc *guc,
return guc_send_invalidate_tlb(guc, action, ARRAY_SIZE(action));
 }
 
-/*
- * Guc TLB Invalidation: Invalidate the TLB's of GuC itself.
+/**
+ * intel_guc_invalidate_tlb_guc - GuC self TLB invalidation
+ *
+ * @guc: the guc
+ * @mode: mode of TLB cache invalidation (heavy or lite)
+ *
+ * Use GuC to invalidate the TLB's of GuC itself.
  */
 int intel_guc_invalidate_tlb_guc(struct intel_guc *guc,
 enum intel_guc_tlb_inval_mode mode)
@@ -1035,6 +1066,13 @@ int intel_guc_invalidate_tlb_guc(struct intel_guc *guc,
return guc_send_invalidate_tlb(guc, action, ARRAY_SIZE(action));
 }
 
+/**
+ * intel_guc_invalidate_tlb_all - GuC global TLB invalidation
+ *
+ * @guc: the guc
+ *
+ * Use GuC to do a complete TLB invalidation on all tables
+ */
 int intel_guc_invalidate_tlb_all(struct intel_guc *guc)
 {
u32 action[] = {
-- 
2.36.1

[Intel-gfx] [PATCH 17/21] drm/i915: Add generic interface for tlb invalidation for XeHP

[Mauro Carvalho Chehab]

From: Prathap Kumar Valsan 

Add an interface for GuC TLB actions, supporting both selective and
full TLB invalidations. After this change, when GuC is enabled,
tlb invalidations use GuC ct. Otherwise, use mmio interface.

Signed-off-by: Prathap Kumar Valsan 
Cc: Niranjana Vishwanathapura 
Cc: Fei Yang 
Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/gt/intel_gt_regs.h |  8 +++
 drivers/gpu/drm/i915/gt/intel_tlb.c | 78 -
 drivers/gpu/drm/i915/gt/intel_tlb.h |  1 +
 3 files changed, 86 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 60d6eb5f245b..52508a9c23e5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1054,6 +1054,14 @@
 
 #define GEN12_GAM_DONE _MMIO(0xcf68)
 
+#define XEHP_TLB_INV_DESC0 _MMIO(0xcf7c)
+#define   XEHP_TLB_INV_DESC0_ADDR_LO   REG_GENMASK(31, 12)
+#define   XEHP_TLB_INV_DESC0_ADDR_MASK REG_GENMASK(8, 3)
+#define   XEHP_TLB_INV_DESC0_G REG_GENMASK(2, 1)
+#define   XEHP_TLB_INV_DESC0_VALID REG_BIT(0)
+#define XEHP_TLB_INV_DESC1 _MMIO(0xcf80)
+#define   XEHP_TLB_INV_DESC0_ADDR_HI   REG_GENMASK(31, 0)
+
 #define GEN7_HALF_SLICE_CHICKEN1   _MMIO(0xe100) /* IVB GT1 + VLV 
*/
 #define   GEN7_MAX_PS_THREAD_DEP   (8 << 12)
 #define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE  (1 << 10)
diff --git a/drivers/gpu/drm/i915/gt/intel_tlb.c 
b/drivers/gpu/drm/i915/gt/intel_tlb.c
index af8cae979489..15ed83226676 100644
--- a/drivers/gpu/drm/i915/gt/intel_tlb.c
+++ b/drivers/gpu/drm/i915/gt/intel_tlb.c
@@ -10,6 +10,7 @@
 #include "intel_gt_pm.h"
 #include "intel_gt_regs.h"
 #include "intel_tlb.h"
+#include "uc/intel_guc.h"
 
 struct reg_and_bit {
i915_reg_t reg;
@@ -159,11 +160,16 @@ void intel_gt_invalidate_tlb_full(struct intel_gt *gt, 
u32 seqno)
return;
 
with_intel_gt_pm_if_awake(gt, wakeref) {
+   struct intel_guc *guc = >->uc.guc;
+
mutex_lock(>->tlb.invalidate_lock);
if (tlb_seqno_passed(gt, seqno))
goto unlock;
 
-   mmio_invalidate_full(gt);
+   if (INTEL_GUC_SUPPORTS_TLB_INVALIDATION(guc))
+   intel_guc_invalidate_tlb_full(guc, 
INTEL_GUC_TLB_INVAL_MODE_HEAVY);
+   else
+   mmio_invalidate_full(gt);
 
write_seqcount_invalidate(>->tlb.seqno);
 unlock:
@@ -171,6 +177,76 @@ void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 
seqno)
}
 }
 
+static bool mmio_invalidate_range(struct intel_gt *gt, u64 start, u64 length)
+{
+   u32 address_mask = (ilog2(length) - ilog2(I915_GTT_PAGE_SIZE_4K));
+   u64 vm_total = BIT_ULL(INTEL_INFO(gt->i915)->ppgtt_size);
+   intel_wakeref_t wakeref;
+   u32 dw0, dw1;
+   int err;
+
+   GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE_4K));
+   GEM_BUG_ON(!IS_ALIGNED(length, I915_GTT_PAGE_SIZE_4K));
+   GEM_BUG_ON(range_overflows(start, length, vm_total));
+
+   dw0 = FIELD_PREP(XEHP_TLB_INV_DESC0_ADDR_LO, (lower_32_bits(start) >> 
12)) |
+   FIELD_PREP(XEHP_TLB_INV_DESC0_ADDR_MASK, address_mask) |
+   FIELD_PREP(XEHP_TLB_INV_DESC0_G, 0x3) |
+   FIELD_PREP(XEHP_TLB_INV_DESC0_VALID, 0x1);
+   dw1 = upper_32_bits(start);
+
+   err = 0;
+   with_intel_gt_pm_if_awake(gt, wakeref) {
+   struct intel_uncore *uncore = gt->uncore;
+
+   intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
+
+   mutex_lock(>->tlb.invalidate_lock);
+   intel_uncore_write_fw(uncore, XEHP_TLB_INV_DESC1, dw1);
+   intel_uncore_write_fw(uncore, XEHP_TLB_INV_DESC0, dw0);
+   err = __intel_wait_for_register_fw(uncore,
+  XEHP_TLB_INV_DESC0,
+  XEHP_TLB_INV_DESC0_VALID,
+  0, 100, 10, NULL);
+   mutex_unlock(>->tlb.invalidate_lock);
+
+   intel_uncore_forcewake_put_delayed(uncore, FORCEWAKE_ALL);
+   }
+
+   if (err)
+   drm_err_ratelimited(>->i915->drm,
+   "TLB invalidation response timed out\n");
+
+   return err == 0;
+}
+
+bool intel_gt_invalidate_tlb_range(struct intel_gt *gt,
+  u64 start, u64 length)
+{
+   struct intel_guc *guc = >->uc.guc;
+   intel_wakeref_t wakeref;
+
+   if (intel_gt_is_wedged(gt))
+   return true;
+
+   if (!INTEL_GUC_SUPPORTS_TLB_INVALIDATION_SELECTIVE(guc))
+   return false;
+
+   /*XXX: We are seeing timeouts on g

[Intel-gfx] [PATCH 18/21] drm/i915: Use selective tlb invalidations where supported

[Mauro Carvalho Chehab]

From: Prathap Kumar Valsan 

For platforms supporting selective tlb invalidations, we don't need to
do a full tlb invalidation. Rather do a range based tlb invalidation for
every unbind of purged vma belongs to an active vm.

[mchehab: change moved from intel_ppgtt.c to i915_vma.c]
Signed-off-by: Prathap Kumar Valsan 
Cc: Niranjana Vishwanathapura 
Cc: Fei Yang 
Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/gt/intel_ppgtt.c |  2 +-
 drivers/gpu/drm/i915/i915_vma.c   | 14 +-
 drivers/gpu/drm/i915/i915_vma.h   |  3 ++-
 3 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c 
b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index f764d250e929..74782fb2ccbd 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -211,7 +211,7 @@ void ppgtt_unbind_vma(struct i915_address_space *vm,
return;
 
vm->clear_range(vm, vma_res->start, vma_res->vma_size);
-   vma_invalidate_tlb(vm, vma_res->tlb);
+   vma_invalidate_tlb(vm, vma_res->tlb, vma_res->start, vma_res->vma_size);
 }
 
 static unsigned long pd_count(u64 size, int shift)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 5edc745dcc51..6d881a6b403a 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1309,7 +1309,8 @@ I915_SELFTEST_EXPORT int i915_vma_get_pages(struct 
i915_vma *vma)
return err;
 }
 
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb,
+   u64 start, u64 size)
 {
struct intel_gt *gt;
int id;
@@ -1325,9 +1326,11 @@ void vma_invalidate_tlb(struct i915_address_space *vm, 
u32 *tlb)
 * the most recent TLB invalidation seqno, and if we have not yet
 * flushed the TLBs upon release, perform a full invalidation.
 */
-   for_each_gt(gt, vm->i915, id)
-   WRITE_ONCE(tlb[id],
-  intel_gt_next_invalidate_tlb_full(vm->gt));
+   for_each_gt(gt, vm->i915, id) {
+   if (!intel_gt_invalidate_tlb_range(gt, start, size))
+   WRITE_ONCE(tlb[id],
+  intel_gt_next_invalidate_tlb_full(vm->gt));
+   }
 }
 
 static void __vma_put_pages(struct i915_vma *vma, unsigned int count)
@@ -1980,7 +1983,8 @@ struct dma_fence *__i915_vma_evict(struct i915_vma *vma, 
bool async)
dma_fence_put(unbind_fence);
unbind_fence = NULL;
}
-   vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb);
+   vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb,
+  vma->node.start, vma->size);
}
 
/*
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 33a58f605d75..3f0af9595e59 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -213,7 +213,8 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
u64 size, u64 alignment, u64 flags);
 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
 void i915_vma_revoke_mmap(struct i915_vma *vma);
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb);
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb,
+   u64 start, u64 size);
 struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async);
 int __i915_vma_unbind(struct i915_vma *vma);
 int __must_check i915_vma_unbind(struct i915_vma *vma);
-- 
2.36.1

[Intel-gfx] [PATCH 16/21] drm/i915: Define GuC Based TLB invalidation routines

[Mauro Carvalho Chehab]

From: Prathap Kumar Valsan 

Add routines to interface with GuC firmware for selective TLB invalidation
supported on XeHP.

Signed-off-by: Prathap Kumar Valsan 
Cc: Matthew Brost 
Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  3 +
 drivers/gpu/drm/i915/gt/uc/intel_guc.c| 90 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc.h| 10 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |  3 +
 4 files changed, 106 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index fb0af33e43cc..5c019856a269 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -188,6 +188,9 @@ enum intel_guc_state_capture_event_status {
 #define INTEL_GUC_TLB_INVAL_FLUSH_CACHE (1 << 31)
 
 enum intel_guc_tlb_invalidation_type {
+   INTEL_GUC_TLB_INVAL_FULL = 0x0,
+   INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE = 0x1,
+   INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX = 0x2,
INTEL_GUC_TLB_INVAL_GUC = 0x3,
 };
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 8a104a292598..98260a7bc90b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -923,6 +923,96 @@ static int guc_send_invalidate_tlb(struct intel_guc *guc, 
u32 *action, u32 size)
return err;
 }
 
+ /* Full TLB invalidation */
+int intel_guc_invalidate_tlb_full(struct intel_guc *guc,
+ enum intel_guc_tlb_inval_mode mode)
+{
+   u32 action[] = {
+   INTEL_GUC_ACTION_TLB_INVALIDATION,
+   0,
+   INTEL_GUC_TLB_INVAL_FULL << INTEL_GUC_TLB_INVAL_TYPE_SHIFT |
+   mode << INTEL_GUC_TLB_INVAL_MODE_SHIFT |
+   INTEL_GUC_TLB_INVAL_FLUSH_CACHE,
+   };
+
+   if (!INTEL_GUC_SUPPORTS_TLB_INVALIDATION(guc)) {
+   DRM_ERROR("Tlb invalidation: Operation not supported in this 
platform!\n");
+   return 0;
+   }
+
+   return guc_send_invalidate_tlb(guc, action, ARRAY_SIZE(action));
+}
+
+/*
+ * Selective TLB Invalidation for Address Range:
+ * TLB's in the Address Range is Invalidated across all engines.
+ */
+int intel_guc_invalidate_tlb_page_selective(struct intel_guc *guc,
+   enum intel_guc_tlb_inval_mode mode,
+   u64 start, u64 length)
+{
+   u64 vm_total = BIT_ULL(INTEL_INFO(guc_to_gt(guc)->i915)->ppgtt_size);
+   u32 address_mask = (ilog2(length) - ilog2(I915_GTT_PAGE_SIZE_4K));
+   u32 full_range = vm_total == length;
+   u32 action[] = {
+   INTEL_GUC_ACTION_TLB_INVALIDATION,
+   0,
+   INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE << 
INTEL_GUC_TLB_INVAL_TYPE_SHIFT |
+   mode << INTEL_GUC_TLB_INVAL_MODE_SHIFT |
+   INTEL_GUC_TLB_INVAL_FLUSH_CACHE,
+   0,
+   full_range ? full_range : lower_32_bits(start),
+   full_range ? 0 : upper_32_bits(start),
+   full_range ? 0 : address_mask,
+   };
+
+   if (!INTEL_GUC_SUPPORTS_TLB_INVALIDATION_SELECTIVE(guc)) {
+   DRM_ERROR("Tlb invalidation: Operation not supported in this 
platform!\n");
+   return 0;
+   }
+
+   GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE_4K));
+   GEM_BUG_ON(!IS_ALIGNED(length, I915_GTT_PAGE_SIZE_4K));
+   GEM_BUG_ON(range_overflows(start, length, vm_total));
+
+   return guc_send_invalidate_tlb(guc, action, ARRAY_SIZE(action));
+}
+
+/*
+ * Selective TLB Invalidation for Context:
+ * Invalidates all TLB's for a specific context across all engines.
+ */
+int intel_guc_invalidate_tlb_page_selective_ctx(struct intel_guc *guc,
+   enum intel_guc_tlb_inval_mode 
mode,
+   u64 start, u64 length, u32 
ctxid)
+{
+   u64 vm_total = BIT_ULL(INTEL_INFO(guc_to_gt(guc)->i915)->ppgtt_size);
+   u32 address_mask = (ilog2(length) - ilog2(I915_GTT_PAGE_SIZE_4K));
+   u32 full_range = vm_total == length;
+   u32 action[] = {
+   INTEL_GUC_ACTION_TLB_INVALIDATION,
+   0,
+   INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX << 
INTEL_GUC_TLB_INVAL_TYPE_SHIFT |
+   mode << INTEL_GUC_TLB_INVAL_MODE_SHIFT |
+   INTEL_GUC_TLB_INVAL_FLUSH_CACHE,
+   ctxid,
+   full_range ? full_range : lower_32_bits(start),
+   full_range ? 0 : upper_32_bits(start),
+   full_range ? 0 : address_mask,
+   };
+
+   if (!INTEL_GUC_SUPPORTS_TLB_INVALIDATION_SELECTIVE(guc)) {
+   DRM_ERROR("Tlb invalidation: Operation not sup

[Intel-gfx] [PATCH 07/21] drm/i915/gt: describe the new tlb parameter at i915_vma_resource

[Mauro Carvalho Chehab]

TLB cache invalidation can happen on two different situations:

1. synchronously, at __vma_put_pages();
2. asynchronously.

On the first case, TLB cache invalidation happens inside
__vma_put_pages(). So, no need to do it later on.

However, on the second case, the pages will keep in memory
until __i915_vma_evict() is called.

So, we need to store the TLB data at struct i915_vma_resource,
in order to do a TLB cache invalidation before allowing
userspace to re-use the same memory.

So, i915_vma_resource_unbind() has gained a new parameter
in order to store the TLB data at the second case.

Document it.

Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/i915_vma_resource.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_vma_resource.c 
b/drivers/gpu/drm/i915/i915_vma_resource.c
index 5a67995ea5fe..4fe09ea0a825 100644
--- a/drivers/gpu/drm/i915/i915_vma_resource.c
+++ b/drivers/gpu/drm/i915/i915_vma_resource.c
@@ -216,6 +216,10 @@ i915_vma_resource_fence_notify(struct i915_sw_fence *fence,
 /**
  * i915_vma_resource_unbind - Unbind a vma resource
  * @vma_res: The vma resource to unbind.
+ * @tlb: pointer to vma->obj->mm.tlb associated with the resource
+ *  to be stored at vma_res->tlb. When not-NULL, it will be used
+ *  to do TLB cache invalidation before freeing a VMA resource.
+ *  used only for async unbind.
  *
  * At this point this function does little more than publish a fence that
  * signals immediately unless signaling is held back.
-- 
2.36.1

[Intel-gfx] [PATCH 13/21] drm/i915: Invalidate the TLBs on each GT

[Mauro Carvalho Chehab]

From: Chris Wilson 

With multi-GT devices, the object may have been bound on each GT.
Invalidate the TLBs across all GT before releasing the pages
back to the system.

Signed-off-by: Chris Wilson 
Cc: Fei Yang 
Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/gem/i915_gem_object_types.h |  4 +++-
 drivers/gpu/drm/i915/gem/i915_gem_pages.c| 13 -
 drivers/gpu/drm/i915/gt/intel_engine.h   |  1 +
 drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h   |  3 ++-
 drivers/gpu/drm/i915/gt/intel_gt_defines.h   | 11 +++
 drivers/gpu/drm/i915/gt/intel_gt_types.h |  4 +++-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c|  4 ++--
 drivers/gpu/drm/i915/i915_drv.h  |  1 -
 drivers/gpu/drm/i915/i915_vma.c  | 14 +++---
 drivers/gpu/drm/i915/i915_vma.h  |  2 +-
 10 files changed, 42 insertions(+), 15 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_defines.h

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 9f6b14ec189a..3c1d0b750a67 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -17,6 +17,8 @@
 #include "i915_selftest.h"
 #include "i915_vma_resource.h"
 
+#include "gt/intel_gt_defines.h"
+
 struct drm_i915_gem_object;
 struct intel_fronbuffer;
 struct intel_memory_region;
@@ -616,7 +618,7 @@ struct drm_i915_gem_object {
 */
bool dirty:1;
 
-   u32 tlb;
+   u32 tlb[I915_MAX_GT];
} mm;
 
struct {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c 
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 1cd76cc5d9f3..4a6a2f2e8148 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -194,13 +194,16 @@ static void unmap_object(struct drm_i915_gem_object *obj, 
void *ptr)
 static void flush_tlb_invalidate(struct drm_i915_gem_object *obj)
 {
struct drm_i915_private *i915 = to_i915(obj->base.dev);
-   struct intel_gt *gt = to_gt(i915);
+   struct intel_gt *gt;
+   int id;
 
-   if (!obj->mm.tlb)
-   return;
+   for_each_gt(gt, i915, id) {
+   if (!obj->mm.tlb[id])
+   continue;
 
-   intel_gt_invalidate_tlb_full(gt, obj->mm.tlb);
-   obj->mm.tlb = 0;
+   intel_gt_invalidate_tlb_full(gt, obj->mm.tlb[id]);
+   obj->mm.tlb[id] = 0;
+   }
 }
 
 struct sg_table *
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h 
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 04e435bce79b..fe1dc55bf8f7 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -18,6 +18,7 @@
 #include "intel_gt_types.h"
 #include "intel_timeline.h"
 #include "intel_workarounds.h"
+#include "uc/intel_guc_submission.h"
 
 struct drm_printer;
 struct intel_context;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h 
b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h
index 487b8a5520f1..8d41cf0c937a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h
@@ -11,8 +11,9 @@
 #include "i915_active.h"
 #include "intel_gt_buffer_pool_types.h"
 
-struct intel_gt;
+enum i915_map_type;
 struct i915_request;
+struct intel_gt;
 
 struct intel_gt_buffer_pool_node *
 intel_gt_get_buffer_pool(struct intel_gt *gt, size_t size,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_defines.h 
b/drivers/gpu/drm/i915/gt/intel_gt_defines.h
new file mode 100644
index ..7c711726d663
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_defines.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __INTEL_GT_DEFINES__
+#define __INTEL_GT_DEFINES__
+
+#define I915_MAX_GT 4
+
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 3804a583382b..b857c3972251 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -19,7 +19,6 @@
 #include "uc/intel_uc.h"
 #include "intel_gsc.h"
 
-#include "i915_vma.h"
 #include "intel_engine_types.h"
 #include "intel_gt_buffer_pool_types.h"
 #include "intel_hwconfig.h"
@@ -31,8 +30,11 @@
 #include "intel_wakeref.h"
 #include "pxp/intel_pxp_types.h"
 
+#include "intel_gt_defines.h"
+
 struct drm_i915_private;
 struct i915_ggtt;
+struct i915_vma;
 struct intel_engine_cs;
 struct intel_uncore;
 
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c 
b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 2da6c82a8bd2..f764d250e929 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -8,6 +8,7 @@
 #include "gem/i915_gem_lmem.h"
 
 #include "i915_trace.h"
+#include "intel_gt.h"

[Intel-gfx] [PATCH 01/21] drm/i915/gt: Ignore TLB invalidations on idle engines

[Mauro Carvalho Chehab]

From: Chris Wilson 

Check if the device is powered down prior to any engine activity,
as, on such cases, all the TLBs were already invalidated, so an
explicit TLB invalidation is not needed, thus reducing the
performance regression impact due to it.

This becomes more significant with GuC, as it can only do so when
the connection to the GuC is awake.

Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Signed-off-by: Chris Wilson 
Cc: Fei Yang 
Cc: Andi Shyti 
Cc: Thomas Hellström 
Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 10 ++
 drivers/gpu/drm/i915/gt/intel_gt.c| 17 ++---
 drivers/gpu/drm/i915/gt/intel_gt_pm.h |  3 +++
 3 files changed, 19 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c 
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 97c820eee115..6835279943df 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -6,14 +6,15 @@
 
 #include 
 
+#include "gt/intel_gt.h"
+#include "gt/intel_gt_pm.h"
+
 #include "i915_drv.h"
 #include "i915_gem_object.h"
 #include "i915_scatterlist.h"
 #include "i915_gem_lmem.h"
 #include "i915_gem_mman.h"
 
-#include "gt/intel_gt.h"
-
 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
 struct sg_table *pages,
 unsigned int sg_page_sizes)
@@ -217,10 +218,11 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object 
*obj)
 
if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) {
struct drm_i915_private *i915 = to_i915(obj->base.dev);
+   struct intel_gt *gt = to_gt(i915);
intel_wakeref_t wakeref;
 
-   with_intel_runtime_pm_if_active(&i915->runtime_pm, wakeref)
-   intel_gt_invalidate_tlbs(to_gt(i915));
+   with_intel_gt_pm_if_awake(gt, wakeref)
+   intel_gt_invalidate_tlbs(gt);
}
 
return pages;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 68c2b0d8f187..c4d43da84d8e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -12,6 +12,7 @@
 
 #include "i915_drv.h"
 #include "intel_context.h"
+#include "intel_engine_pm.h"
 #include "intel_engine_regs.h"
 #include "intel_ggtt_gmch.h"
 #include "intel_gt.h"
@@ -924,6 +925,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore = gt->uncore;
struct intel_engine_cs *engine;
+   intel_engine_mask_t awake, tmp;
enum intel_engine_id id;
const i915_reg_t *regs;
unsigned int num = 0;
@@ -947,26 +949,31 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
 
GEM_TRACE("\n");
 
-   assert_rpm_wakelock_held(&i915->runtime_pm);
-
mutex_lock(>->tlb_invalidate_lock);
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 
spin_lock_irq(&uncore->lock); /* serialise invalidate with GT reset */
 
+   awake = 0;
for_each_engine(engine, gt, id) {
struct reg_and_bit rb;
 
+   if (!intel_engine_pm_is_awake(engine))
+   continue;
+
rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
if (!i915_mmio_reg_offset(rb.reg))
continue;
 
intel_uncore_write_fw(uncore, rb.reg, rb.bit);
+   awake |= engine->mask;
}
 
spin_unlock_irq(&uncore->lock);
 
-   for_each_engine(engine, gt, id) {
+   for_each_engine_masked(engine, gt, awake, tmp) {
+   struct reg_and_bit rb;
+
/*
 * HW architecture suggest typical invalidation time at 40us,
 * with pessimistic cases up to 100us and a recommendation to
@@ -974,12 +981,8 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
 */
const unsigned int timeout_us = 100;
const unsigned int timeout_ms = 4;
-   struct reg_and_bit rb;
 
rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
-   if (!i915_mmio_reg_offset(rb.reg))
-   continue;
-
if (__intel_wait_for_register_fw(uncore,
 rb.reg, rb.bit, 0,
 timeout_us, timeout_ms,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h 
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index bc898df7a48c..a334787a4939 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -55,6 +55,9 @@ static inline void intel_gt_pm_might_put(struct intel_gt *gt)

[Intel-gfx] [PATCH 06/21] drm/i915/gt: Batch TLB invalidations

[Mauro Carvalho Chehab]

From: Chris Wilson 

Invalidate TLB in patch, in order to reduce performance regressions.

Currently, every caller performs a full barrier around a TLB
invalidation, ignoring all other invalidations that may have already
removed their PTEs from the cache. As this is a synchronous operation
and can be quite slow, we cause multiple threads to contend on the TLB
invalidate mutex blocking userspace.

We only need to invalidate the TLB once after replacing our PTE to
ensure that there is no possible continued access to the physical
address before releasing our pages. By tracking a seqno for each full
TLB invalidate we can quickly determine if one has been performed since
rewriting the PTE, and only if necessary trigger one for ourselves.

That helps to reduce the performance regression introduced by TLB
invalidate logic.

[mchehab: rebased to not require moving the code to a separate file]

Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Suggested-by: Tvrtko Ursulin 
Signed-off-by: Chris Wilson 
Cc: Fei Yang 
Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 .../gpu/drm/i915/gem/i915_gem_object_types.h  |  3 +-
 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 21 +---
 drivers/gpu/drm/i915/gt/intel_gt.c| 53 ++-
 drivers/gpu/drm/i915/gt/intel_gt.h| 12 -
 drivers/gpu/drm/i915/gt/intel_gt_types.h  | 18 ++-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c |  8 ++-
 drivers/gpu/drm/i915/i915_vma.c   | 34 +---
 drivers/gpu/drm/i915/i915_vma.h   |  1 +
 drivers/gpu/drm/i915/i915_vma_resource.c  |  5 +-
 drivers/gpu/drm/i915/i915_vma_resource.h  |  6 ++-
 10 files changed, 125 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 5cf36a130061..9f6b14ec189a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -335,7 +335,6 @@ struct drm_i915_gem_object {
 #define I915_BO_READONLY  BIT(7)
 #define I915_TILING_QUIRK_BIT 8 /* unknown swizzling; do not release! */
 #define I915_BO_PROTECTED BIT(9)
-#define I915_BO_WAS_BOUND_BIT 10
/**
 * @mem_flags - Mutable placement-related flags
 *
@@ -616,6 +615,8 @@ struct drm_i915_gem_object {
 * pages were last acquired.
 */
bool dirty:1;
+
+   u32 tlb;
} mm;
 
struct {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c 
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 6835279943df..8357dbdcab5c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -191,6 +191,18 @@ static void unmap_object(struct drm_i915_gem_object *obj, 
void *ptr)
vunmap(ptr);
 }
 
+static void flush_tlb_invalidate(struct drm_i915_gem_object *obj)
+{
+   struct drm_i915_private *i915 = to_i915(obj->base.dev);
+   struct intel_gt *gt = to_gt(i915);
+
+   if (!obj->mm.tlb)
+   return;
+
+   intel_gt_invalidate_tlb(gt, obj->mm.tlb);
+   obj->mm.tlb = 0;
+}
+
 struct sg_table *
 __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
 {
@@ -216,14 +228,7 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object 
*obj)
__i915_gem_object_reset_page_iter(obj);
obj->mm.page_sizes.phys = obj->mm.page_sizes.sg = 0;
 
-   if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) {
-   struct drm_i915_private *i915 = to_i915(obj->base.dev);
-   struct intel_gt *gt = to_gt(i915);
-   intel_wakeref_t wakeref;
-
-   with_intel_gt_pm_if_awake(gt, wakeref)
-   intel_gt_invalidate_tlbs(gt);
-   }
+   flush_tlb_invalidate(obj);
 
return pages;
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5c55a90672f4..f435e06125aa 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -38,8 +38,6 @@ static void __intel_gt_init_early(struct intel_gt *gt)
 {
spin_lock_init(>->irq_lock);
 
-   mutex_init(>->tlb_invalidate_lock);
-
INIT_LIST_HEAD(>->closed_vma);
spin_lock_init(>->closed_lock);
 
@@ -50,6 +48,8 @@ static void __intel_gt_init_early(struct intel_gt *gt)
intel_gt_init_reset(gt);
intel_gt_init_requests(gt);
intel_gt_init_timelines(gt);
+   mutex_init(>->tlb.invalidate_lock);
+   seqcount_mutex_init(>->tlb.seqno, >->tlb.invalidate_lock);
intel_gt_pm_init_early(gt);
 
intel_uc_init_early(>->uc);
@@ -770,6 +770,7 @@ void intel_gt_driver_late_release_all(struct 
drm_i915_private *i915)
intel_gt_fini_requests(gt);
intel_gt_f

[Intel-gfx] [PATCH 09/21] drm/i915/guc: Define CTB based TLB invalidation routines

[Mauro Carvalho Chehab]

From: Prathap Kumar Valsan 

Add routines to interface with GuC firmware for TLB invalidation.

Signed-off-by: Prathap Kumar Valsan 
Cc: Bruce Chang 
Cc: Michal Wajdeczko 
Cc: Matthew Brost 
Cc: Chris Wilson 
Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  | 35 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc.c| 90 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc.h| 13 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 24 -
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |  6 ++
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 91 ++-
 6 files changed, 253 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 4ef9990ed7f8..2e39d8df4c82 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -134,6 +134,10 @@ enum intel_guc_action {
INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
INTEL_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
INTEL_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
+   INTEL_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
+   INTEL_GUC_ACTION_PAGE_FAULT_NOTIFICATION = 0x6001,
+   INTEL_GUC_ACTION_TLB_INVALIDATION = 0x7000,
+   INTEL_GUC_ACTION_TLB_INVALIDATION_DONE = 0x7001,
INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 0x8002,
INTEL_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,
INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,
@@ -177,4 +181,35 @@ enum intel_guc_state_capture_event_status {
 
 #define INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_MASK  0x00FF
 
+#define INTEL_GUC_TLB_INVAL_TYPE_SHIFT 0
+#define INTEL_GUC_TLB_INVAL_MODE_SHIFT 8
+/* Flush PPC or SMRO caches along with TLB invalidation request */
+#define INTEL_GUC_TLB_INVAL_FLUSH_CACHE (1 << 31)
+
+enum intel_guc_tlb_invalidation_type {
+   INTEL_GUC_TLB_INVAL_GUC = 0x3,
+};
+
+/*
+ * 0: Heavy mode of Invalidation:
+ * The pipeline of the engine(s) for which the invalidation is targeted to is
+ * blocked, and all the in-flight transactions are guaranteed to be Globally
+ * Observed before completing the TLB invalidation
+ * 1: Lite mode of Invalidation:
+ * TLBs of the targeted engine(s) are immediately invalidated.
+ * In-flight transactions are NOT guaranteed to be Globally Observed before
+ * completing TLB invalidation.
+ * Light Invalidation Mode is to be used only when
+ * it can be guaranteed (by SW) that the address translations remain invariant
+ * for the in-flight transactions across the TLB invalidation. In other words,
+ * this mode can be used when the TLB invalidation is intended to clear out the
+ * stale cached translations that are no longer in use. Light Invalidation Mode
+ * is much faster than the Heavy Invalidation Mode, as it does not wait for the
+ * in-flight transactions to be GOd.
+ */
+enum intel_guc_tlb_inval_mode {
+   INTEL_GUC_TLB_INVAL_MODE_HEAVY = 0x0,
+   INTEL_GUC_TLB_INVAL_MODE_LITE = 0x1,
+};
+
 #endif /* _ABI_GUC_ACTIONS_ABI_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2706a8c65090..5c59f9b144a3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -855,6 +855,96 @@ int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, 
u64 value)
return __guc_self_cfg(guc, key, 2, value);
 }
 
+static int guc_send_invalidate_tlb(struct intel_guc *guc, u32 *action, u32 
size)
+{
+   struct intel_guc_tlb_wait _wq, *wq = &_wq;
+   DEFINE_WAIT_FUNC(wait, woken_wake_function);
+   int err = 0;
+   u32 seqno;
+
+   init_waitqueue_head(&_wq.wq);
+
+   if (xa_alloc_cyclic_irq(&guc->tlb_lookup, &seqno, wq,
+   xa_limit_32b, &guc->next_seqno,
+   GFP_ATOMIC | __GFP_NOWARN) < 0) {
+   /* Under severe memory pressure? Serialise TLB allocations */
+   xa_lock_irq(&guc->tlb_lookup);
+   wq = xa_load(&guc->tlb_lookup, guc->serial_slot);
+   wait_event_lock_irq(wq->wq,
+   !READ_ONCE(wq->status),
+   guc->tlb_lookup.xa_lock);
+   /*
+* Update wq->status under lock to ensure only one waiter can
+* issue the tlb invalidation command using the serial slot at a
+* time. The condition is set to false before releasing the lock
+* so that other caller continue to wait until woken up again.
+*/
+   wq->status = 1;
+   xa_unlock_irq(&guc->tlb_lookup);
+
+   seqno = guc->serial_slot;
+   }
+
+   action[1] = seqno;
+
+   add_wait_queue(&wq->wq, &wait);
+
+   err = intel_guc_send_bus

[Intel-gfx] [PATCH 19/21] drm/i915/gt: document TLB cache invalidation functions

[Mauro Carvalho Chehab]

Add a description for the kAPI functions inside intel_tlb.c.

Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/gt/intel_tlb.c | 36 +
 1 file changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_tlb.c 
b/drivers/gpu/drm/i915/gt/intel_tlb.c
index 15ed83226676..aa2e0086ae88 100644
--- a/drivers/gpu/drm/i915/gt/intel_tlb.c
+++ b/drivers/gpu/drm/i915/gt/intel_tlb.c
@@ -146,6 +146,18 @@ static void mmio_invalidate_full(struct intel_gt *gt)
intel_uncore_forcewake_put_delayed(uncore, FORCEWAKE_ALL);
 }
 
+/**
+ * intel_gt_invalidate_tlb_full - do full TLB cache invalidation
+ * @gt: GT structure
+ * @seqno: sequence number
+ *
+ * Do a full TLB cache invalidation if the @seqno is bigger than the last
+ * full TLB cache invalidation.
+ *
+ * Note:
+ * The TLB cache invalidation logic depends on GEN-specific registers.
+ * It currently supports GEN8 to GEN12 and GuC-based TLB cache invalidation.
+ */
 void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno)
 {
intel_wakeref_t wakeref;
@@ -220,6 +232,17 @@ static bool mmio_invalidate_range(struct intel_gt *gt, u64 
start, u64 length)
return err == 0;
 }
 
+/**
+ * intel_gt_invalidate_tlb_range - do full TLB cache invalidation
+ * @gt: GT structure
+ * @start: range start
+ * @length: range length
+ *
+ * Do a selected TLB cache invalidation on a range pointed by @start
+ * with @length size.
+ *
+ * Only some GuC-based GPUs can do a selective cache invalidation.
+ */
 bool intel_gt_invalidate_tlb_range(struct intel_gt *gt,
   u64 start, u64 length)
 {
@@ -247,12 +270,25 @@ bool intel_gt_invalidate_tlb_range(struct intel_gt *gt,
return true;
 }
 
+/**
+ * intel_gt_init_tlb - initialize TLB-specific vars
+ * @gt: GT structure
+ *
+ * TLB cache invalidation logic internally uses some resources that require
+ * initialization. Should be called before doing any TLB cache invalidation.
+ */
 void intel_gt_init_tlb(struct intel_gt *gt)
 {
mutex_init(>->tlb.invalidate_lock);
seqcount_mutex_init(>->tlb.seqno, >->tlb.invalidate_lock);
 }
 
+/**
+ * intel_gt_fini_tlb - initialize TLB-specific vars
+ * @gt: GT structure
+ *
+ * Frees any resources needed by TLB cache invalidation logic.
+ */
 void intel_gt_fini_tlb(struct intel_gt *gt)
 {
mutex_destroy(>->tlb.invalidate_lock);
-- 
2.36.1

[Intel-gfx] [PATCH 15/21] drm/i915: Add platform macro for selective tlb flush

[Mauro Carvalho Chehab]

From: Prathap Kumar Valsan 

Add support for selective TLB invalidation, which is a platform
feature supported on XeHP.

Signed-off-by: Prathap Kumar Valsan 
Cc: Niranjana Vishwanathapura 
Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/i915_drv.h  | 3 +++
 drivers/gpu/drm/i915/i915_pci.c  | 1 +
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f1f70257dbe0..73494960a3a8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1312,6 +1312,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
 
+#define HAS_SELECTIVE_TLB_INVALIDATION(dev_priv) \
+   (INTEL_INFO(dev_priv)->has_selective_tlb_invalidation)
+
 #define HAS_POOLED_EU(dev_priv)(INTEL_INFO(dev_priv)->has_pooled_eu)
 
 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)
(INTEL_INFO(dev_priv)->has_global_mocs)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index aacc10f2e73f..30d945fe384b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1022,6 +1022,7 @@ static const struct intel_device_info adl_p_info = {
.has_reset_engine = 1, \
.has_rps = 1, \
.has_runtime_pm = 1, \
+   .has_selective_tlb_invalidation = 1, \
.ppgtt_size = 48, \
.ppgtt_type = INTEL_PPGTT_FULL
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 23bf230aa104..92a38b8f7c47 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -170,6 +170,7 @@ enum intel_ppgtt_type {
func(has_rc6p); \
func(has_rps); \
func(has_runtime_pm); \
+   func(has_selective_tlb_invalidation); \
func(has_snoop); \
func(has_coherent_ggtt); \
func(unfenced_needs_alignment); \
-- 
2.36.1

[Intel-gfx] [PATCH 20/21] drm/i915/guc: describe enum intel_guc_tlb_invalidation_type

[Mauro Carvalho Chehab]

Add a description for intel_guc_tlb_invalidation_type enum.

Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 5c019856a269..e97065c62d28 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -187,6 +187,18 @@ enum intel_guc_state_capture_event_status {
 /* Flush PPC or SMRO caches along with TLB invalidation request */
 #define INTEL_GUC_TLB_INVAL_FLUSH_CACHE (1 << 31)
 
+/**
+ * enum intel_guc_tlb_invalidation_type - type of TLB cache invalidation
+ *
+ * @INTEL_GUC_TLB_INVAL_FULL:
+ * Global TLB invalidation
+ * @INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE:
+ * Page-selective TLB cache invalidation
+ * @INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX:
+ * Context-selective TLB cache invalidation
+ * @INTEL_GUC_TLB_INVAL_GUC:
+ * Invalidate TLB on GuC itself
+ */
 enum intel_guc_tlb_invalidation_type {
INTEL_GUC_TLB_INVAL_FULL = 0x0,
INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE = 0x1,
-- 
2.36.1

[Intel-gfx] [PATCH 14/21] drm/i915: document tlb field at struct drm_i915_gem_object

[Mauro Carvalho Chehab]

Add documentation to the TLB field inside
struct drm_i915_gem_object.

Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3c1d0b750a67..6f5b9e34a4d7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -618,6 +618,7 @@ struct drm_i915_gem_object {
 */
bool dirty:1;
 
+   /** @mm.tlb: array with TLB invalidate IDs */
u32 tlb[I915_MAX_GT];
} mm;
 
-- 
2.36.1

[Intel-gfx] [PATCH 05/21] drm/i915/gt: Skip TLB invalidations once wedged

[Mauro Carvalho Chehab]

From: Chris Wilson 

Skip all further TLB invalidations once the device is wedged and
had been reset, as, on such cases, it can no longer process instructions
on the GPU and the user no longer has access to the TLB's in each engine.

That helps to reduce the performance regression introduced by TLB
invalidate logic.

Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Signed-off-by: Chris Wilson 
Cc: Fei Yang 
Cc: Andi Shyti 
Acked-by: Thomas Hellström 
Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 1d84418e8676..5c55a90672f4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -934,6 +934,9 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
if (I915_SELFTEST_ONLY(gt->awake == -ENODEV))
return;
 
+   if (intel_gt_is_wedged(gt))
+   return;
+
if (GRAPHICS_VER(i915) == 12) {
regs = gen12_regs;
num = ARRAY_SIZE(gen12_regs);
-- 
2.36.1

[Intel-gfx] [PATCH 11/21] drm/i915/guc: document the TLB invalidation struct members

[Mauro Carvalho Chehab]

Add documentation for the 3 new members of struct intel_guc
that are used to handle TLB cache invalidation logic.

Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/gt/uc/intel_guc.h | 14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index f82a121b0838..73c46d405dc4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -76,11 +76,23 @@ struct intel_guc {
 */
atomic_t outstanding_submission_g2h;
 
-   /** @interrupts: pointers to GuC interrupt-managing functions. */
+   /**
+* @tlb_lookup: TLB cache invalidation lookup table.
+*/
struct xarray tlb_lookup;
+
+   /**
+* @serial_slot: index to the latest allocated element at the
+* @tlb_lookup xarray.
+*/
u32 serial_slot;
+
+   /**
+* @next_seqno: next index to be allocated at the @tlb_lookup xarray.
+*/
u32 next_seqno;
 
+   /** @interrupts: pointers to GuC interrupt-managing functions. */
struct {
void (*reset)(struct intel_guc *guc);
void (*enable)(struct intel_guc *guc);
-- 
2.36.1

[Intel-gfx] [PATCH 12/21] drm/i915/guc: Introduce TLB_INVALIDATION_ALL action

[Mauro Carvalho Chehab]

From: Piotr Piórkowski 

Add a new way to invalidate TLB via GuC using actions 0x7002
(TLB_INVALIDATION_ALL).

Those actions will be used on upcoming patches.

Signed-off-by: Piotr Piórkowski 
Cc: Michal Wajdeczko 
Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h |  1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc.c   | 14 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc.h   |  1 +
 3 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 14e35a2f8306..fb0af33e43cc 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -138,6 +138,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_PAGE_FAULT_NOTIFICATION = 0x6001,
INTEL_GUC_ACTION_TLB_INVALIDATION = 0x7000,
INTEL_GUC_ACTION_TLB_INVALIDATION_DONE = 0x7001,
+   INTEL_GUC_ACTION_TLB_INVALIDATION_ALL = 0x7002,
INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 0x8002,
INTEL_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,
INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 5c59f9b144a3..8a104a292598 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -945,6 +945,20 @@ int intel_guc_invalidate_tlb_guc(struct intel_guc *guc,
return guc_send_invalidate_tlb(guc, action, ARRAY_SIZE(action));
 }
 
+int intel_guc_invalidate_tlb_all(struct intel_guc *guc)
+{
+   u32 action[] = {
+   INTEL_GUC_ACTION_TLB_INVALIDATION_ALL,
+   0,
+   INTEL_GUC_TLB_INVAL_MODE_HEAVY << 
INTEL_GUC_TLB_INVAL_MODE_SHIFT |
+   INTEL_GUC_TLB_INVAL_FLUSH_CACHE,
+   };
+
+   GEM_BUG_ON(!INTEL_GUC_SUPPORTS_TLB_INVALIDATION(guc));
+
+   return guc_send_invalidate_tlb(guc, action, ARRAY_SIZE(action));
+}
+
 /**
  * intel_guc_load_status - dump information about GuC load status
  * @guc: the GuC
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 73c46d405dc4..01c6478451cc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -386,6 +386,7 @@ int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, 
u64 value);
 
 int intel_guc_invalidate_tlb_guc(struct intel_guc *guc,
 enum intel_guc_tlb_inval_mode mode);
+int intel_guc_invalidate_tlb_all(struct intel_guc *guc);
 
 static inline bool intel_guc_is_supported(struct intel_guc *guc)
 {
-- 
2.36.1

[Intel-gfx] [PATCH 02/21] drm/i915/gt: document with_intel_gt_pm_if_awake()

[Mauro Carvalho Chehab]

Add a kernel-doc markup to document this new macro.

Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/gt/intel_gt_pm.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h 
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index a334787a4939..4d4caf612fdc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -55,6 +55,13 @@ static inline void intel_gt_pm_might_put(struct intel_gt *gt)
for (tmp = 1, intel_gt_pm_get(gt); tmp; \
 intel_gt_pm_put(gt), tmp = 0)
 
+/**
+ * with_intel_gt_pm_if_awake - if GT is PM awake, get a reference to prevent
+ * it to sleep, run some code and then put the reference away.
+ *
+ * @gt: pointer to the gt
+ * @wf: pointer to a temporary wakeref.
+ */
 #define with_intel_gt_pm_if_awake(gt, wf) \
for (wf = intel_gt_pm_get_if_awake(gt); wf; intel_gt_pm_put_async(gt), 
wf = 0)
 
-- 
2.36.1

[Intel-gfx] [PATCH 10/21] drm/i915/guc: use kernel-doc for enum intel_guc_tlb_inval_mode

[Mauro Carvalho Chehab]

Transform the comments for intel_guc_tlb_inval_mode into a
kernel-doc markup.

Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 2e39d8df4c82..14e35a2f8306 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -190,15 +190,18 @@ enum intel_guc_tlb_invalidation_type {
INTEL_GUC_TLB_INVAL_GUC = 0x3,
 };
 
-/*
- * 0: Heavy mode of Invalidation:
+/**
+ * enum intel_guc_tlb_inval_mode - define the mode for TLB cache invlidation
+ *
+ * @INTEL_GUC_TLB_INVAL_MODE_HEAVY: Heavy Invalidation Mode.
  * The pipeline of the engine(s) for which the invalidation is targeted to is
  * blocked, and all the in-flight transactions are guaranteed to be Globally
- * Observed before completing the TLB invalidation
- * 1: Lite mode of Invalidation:
+ * Observed before completing the TLB invalidation.
+ * @INTEL_GUC_TLB_INVAL_MODE_LITE: Light Invalidation Mode.
  * TLBs of the targeted engine(s) are immediately invalidated.
  * In-flight transactions are NOT guaranteed to be Globally Observed before
  * completing TLB invalidation.
+ *
  * Light Invalidation Mode is to be used only when
  * it can be guaranteed (by SW) that the address translations remain invariant
  * for the in-flight transactions across the TLB invalidation. In other words,
-- 
2.36.1

[Intel-gfx] [PATCH 03/21] drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations

[Mauro Carvalho Chehab]

From: Chris Wilson 

Ensure that the TLB of the OA unit is also invalidated
on gen12 HW, as just invalidating the TLB of an engine is not
enough.

Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Signed-off-by: Chris Wilson 
Cc: Fei Yang 
Cc: Andi Shyti 
Acked-by: Thomas Hellström 
Signed-off-by: Mauro Carvalho Chehab 
---

See [PATCH 00/21] at: 
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/

 drivers/gpu/drm/i915/gt/intel_gt.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index c4d43da84d8e..1d84418e8676 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -11,6 +11,7 @@
 #include "pxp/intel_pxp.h"
 
 #include "i915_drv.h"
+#include "i915_perf_oa_regs.h"
 #include "intel_context.h"
 #include "intel_engine_pm.h"
 #include "intel_engine_regs.h"
@@ -969,6 +970,15 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
awake |= engine->mask;
}
 
+   /* Wa_2207587034:tgl,dg1,rkl,adl-s,adl-p */
+   if (awake &&
+   (IS_TIGERLAKE(i915) ||
+IS_DG1(i915) ||
+IS_ROCKETLAKE(i915) ||
+IS_ALDERLAKE_S(i915) ||
+IS_ALDERLAKE_P(i915)))
+   intel_uncore_write_fw(uncore, GEN12_OA_TLB_INV_CR, 1);
+
spin_unlock_irq(&uncore->lock);
 
for_each_engine_masked(engine, gt, awake, tmp) {
-- 
2.36.1

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Dual LFP/EDP enablement (rev2)

[Patchwork]

== Series Details ==

Series: Dual LFP/EDP enablement (rev2)
URL   : https://patchwork.freedesktop.org/series/104663/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/104663/revisions/2/mbox/ not 
applied
Applying: drm/i915/bios: calculate drrs mode using panel index for dual LFP
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/display/icl_dsi.c
M   drivers/gpu/drm/i915/display/intel_bios.c
M   drivers/gpu/drm/i915/display/intel_bios.h
M   drivers/gpu/drm/i915/display/intel_dp.c
M   drivers/gpu/drm/i915/display/intel_lvds.c
M   drivers/gpu/drm/i915/display/intel_sdvo.c
M   drivers/gpu/drm/i915/display/intel_vbt_defs.h
M   drivers/gpu/drm/i915/display/vlv_dsi.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/vlv_dsi.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/vlv_dsi.c
Auto-merging drivers/gpu/drm/i915/display/intel_vbt_defs.h
Auto-merging drivers/gpu/drm/i915/display/intel_sdvo.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_sdvo.c
Auto-merging drivers/gpu/drm/i915/display/intel_lvds.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_lvds.c
Auto-merging drivers/gpu/drm/i915/display/intel_dp.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_dp.c
Auto-merging drivers/gpu/drm/i915/display/intel_bios.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_bios.h
Auto-merging drivers/gpu/drm/i915/display/intel_bios.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_bios.c
Auto-merging drivers/gpu/drm/i915/display/icl_dsi.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/icl_dsi.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915/bios: calculate drrs mode using panel index for 
dual LFP
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

[Intel-gfx] [PATCH] drm/i915: clear plane color ctl setting when turn full plane off

[Lee Shawn C]

Customer report abnormal display output while switch eDP off sometimes.
In current display disable flow, plane will be off at first. Then turn
eDP off and disable HW pipe line. We found the abnormal pixel comes
after turn plane off. Clear plane color ctl register when driver disable
plane can solve this symptom.

Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Shankar Uma 
Cc: Stanislav Lisovskiy 
Cc: William Tseng 
Signed-off-by: Lee Shawn C 
---
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index caa03324a733..90977cfb7ebb 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -620,6 +620,8 @@ skl_plane_disable_arm(struct intel_plane *plane,
 
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
+   if (DISPLAY_VER(dev_priv) >= 10)
+   intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), 0);
 }
 
 static void
@@ -638,6 +640,7 @@ icl_plane_disable_arm(struct intel_plane *plane,
intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
+   intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), 0);
 }
 
 static bool
-- 
2.17.1

Re: [Intel-gfx] [PATCH v2 12/39] drm/i915: gem: add kernel-doc description for some function parameters

[Das, Nirmoy]

|Reviewed-by: Nirmoy Das |

On 7/13/2022 10:12 AM, Mauro Carvalho Chehab wrote:

There are some parameters missing at the kernel-doc markups on
some gem files. Some of those are trivial enough to be added.

Document them.

Signed-off-by: Mauro Carvalho Chehab
---

To avoid mailbombing on a large number of people, only mailing lists were C/C 
on the cover.
See [PATCH v2 00/39] 
at:https://lore.kernel.org/all/cover.1657699522.git.mche...@kernel.org/

  drivers/gpu/drm/i915/gem/i915_gem_object.c   | 2 ++
  drivers/gpu/drm/i915/gem/i915_gem_ttm.h  | 1 +
  drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 2 ++
  3 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index ccec4055fde3..b5dd43405355 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -820,6 +820,8 @@ int i915_gem_object_wait_moving_fence(struct 
drm_i915_gem_object *obj,
   * in an unknown_state. This means that userspace must NEVER be allowed to 
touch
   * the pages, with either the GPU or CPU.
   *
+ * @obj: The object to check its state.
+ *
   * ONLY valid to be called after ensuring that all kernel fences have 
signalled
   * (in particular the fence for moving/clearing the object).
   */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
index e4842b4296fc..64151f40098f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
@@ -30,6 +30,7 @@ void i915_ttm_bo_destroy(struct ttm_buffer_object *bo);
  /**
   * i915_ttm_to_gem - Convert a struct ttm_buffer_object to an embedding
   * struct drm_i915_gem_object.
+ * @bo: The ttm buffer object.
   *
   * Return: Pointer to the embedding struct ttm_buffer_object, or NULL
   * if the object was not an i915 ttm object.
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 9a7e50534b84..56217d324a9b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -237,6 +237,7 @@ static struct dma_fence *i915_ttm_accel_move(struct 
ttm_buffer_object *bo,
   * @_src_iter: Storage space for the source kmap iterator.
   * @dst_iter: Pointer to the destination kmap iterator.
   * @src_iter: Pointer to the source kmap iterator.
+ * @num_pages: Number of pages to copy or to be cleared.
   * @clear: Whether to clear instead of copy.
   * @src_rsgt: Refcounted scatter-gather list of source memory.
   * @dst_rsgt: Refcounted scatter-gather list of destination memory.
@@ -541,6 +542,7 @@ __i915_ttm_move(struct ttm_buffer_object *bo,
   * i915_ttm_move - The TTM move callback used by i915.
   * @bo: The buffer object.
   * @evict: Whether this is an eviction.
+ * @ctx: Pointer to a struct ttm_operation_ctx
   * @dst_mem: The destination ttm resource.
   * @hop: If we need multihop, what temporary memory type to move to.
   *

Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de 
Managing Directors: Christin Eisenschmid, Sharon Heck, Tiffany Doon Silva  
Chairperson of the Supervisory Board: Nicole Lau

Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928

Re: [Intel-gfx] [PATCH v2 10/39] drm/i915: i915_gem_ttm: fix a kernel-doc markup

[Das, Nirmoy]

|Reviewed-by: Nirmoy Das|

On 7/13/2022 10:11 AM, Mauro Carvalho Chehab wrote:

Two new fields were added to __i915_gem_ttm_object_init() without
their corresponding documentation.

Document them.

Fixes: 9b78b5dade2d ("drm/i915: add i915_gem_object_create_region_at()")
Signed-off-by: Mauro Carvalho Chehab
---

To avoid mailbombing on a large number of people, only mailing lists were C/C 
on the cover.
See [PATCH v2 00/39] 
at:https://lore.kernel.org/all/cover.1657699522.git.mche...@kernel.org/

  drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 053b0022ddd0..e8cfb47b5f5a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -1187,7 +1187,9 @@ void i915_ttm_bo_destroy(struct ttm_buffer_object *bo)
   * __i915_gem_ttm_object_init - Initialize a ttm-backed i915 gem object
   * @mem: The initial memory region for the object.
   * @obj: The gem object.
+ * @offset: The range start.
   * @size: Object size in bytes.
+ * @page_size: The requested page size in bytes for this object.
   * @flags: gem object flags.
   *
   * Return: 0 on success, negative error code on failure.

Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de 
Managing Directors: Christin Eisenschmid, Sharon Heck, Tiffany Doon Silva  
Chairperson of the Supervisory Board: Nicole Lau

Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928

Re: [Intel-gfx] [PATCH v2 08/39] drm/i915: gem: fix some Kernel-doc issues

[Das, Nirmoy]

On 7/13/2022 10:11 AM, Mauro Carvalho Chehab wrote:

There are several trivial issueson kernel-doc markups at gem:

drivers/gpu/drm/i915/gem/i915_gem_create.c:146: warning: This comment 
starts with '/**', but isn't a kernel-doc comment. Refer 
Documentation/doc-guide/kernel-doc.rst
drivers/gpu/drm/i915/gem/i915_gem_create.c:217: warning: This comment 
starts with '/**', but isn't a kernel-doc comment. Refer 
Documentation/doc-guide/kernel-doc.rst
drivers/gpu/drm/i915/gem/i915_gem_create.c:401: warning: This comment 
starts with '/**', but isn't a kernel-doc comment. Refer 
Documentation/doc-guide/kernel-doc.rst
drivers/gpu/drm/i915/gem/i915_gem_domain.c:116: warning: This comment 
starts with '/**', but isn't a kernel-doc comment. Refer 
Documentation/doc-guide/kernel-doc.rst
drivers/gpu/drm/i915/gem/i915_gem_domain.c:177: warning: This comment 
starts with '/**', but isn't a kernel-doc comment. Refer 
Documentation/doc-guide/kernel-doc.rst
drivers/gpu/drm/i915/gem/i915_gem_domain.c:262: warning: expecting 
prototype for Changes the cache(). Prototype was for 
i915_gem_object_set_cache_level() instead
drivers/gpu/drm/i915/gem/i915_gem_domain.c:456: warning: This comment 
starts with '/**', but isn't a kernel-doc comment. Refer 
Documentation/doc-guide/kernel-doc.rst
drivers/gpu/drm/i915/gem/i915_gem_domain.c:500: warning: This comment 
starts with '/**', but isn't a kernel-doc comment. Refer 
Documentation/doc-guide/kernel-doc.rst
drivers/gpu/drm/i915/gem/i915_gem_object.h:110: warning: Function 
parameter or member 'file' not described in 'i915_gem_object_lookup_rcu'
drivers/gpu/drm/i915/gem/i915_gem_object.h:110: warning: Excess 
function parameter 'filp' description in 'i915_gem_object_lookup_rcu'
drivers/gpu/drm/i915/gem/i915_gem_region.h:35: warning: Function 
parameter or member 'process_obj' not described in 
'i915_gem_apply_to_region_ops'
drivers/gpu/drm/i915/gem/i915_gem_wait.c:130: warning: This comment 
starts with '/**', but isn't a kernel-doc comment. Refer 
Documentation/doc-guide/kernel-doc.rst

Caused by:
- lack of function name at the kernel-doc markup;
- renamed parameters.

Address them.

Signed-off-by: Mauro Carvalho Chehab


|Reviewed-by: Nirmoy Das|


---

To avoid mailbombing on a large number of people, only mailing lists were C/C 
on the cover.
See [PATCH v2 00/39] 
at:https://lore.kernel.org/all/cover.1657699522.git.mche...@kernel.org/

  drivers/gpu/drm/i915/gem/i915_gem_create.c |  8 +---
  drivers/gpu/drm/i915/gem/i915_gem_domain.c | 17 +++--
  drivers/gpu/drm/i915/gem/i915_gem_object.h |  2 +-
  drivers/gpu/drm/i915/gem/i915_gem_wait.c   |  2 +-
  4 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c 
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 33673fe7ee0a..8cb2eb092031 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -143,7 +143,8 @@ __i915_gem_object_create_user_ext(struct drm_i915_private 
*i915, u64 size,
  }
  
  /**

- * Creates a new object using the same path as DRM_I915_GEM_CREATE_EXT
+ * __i915_gem_object_create_user - Creates a new object using the same path
+ * as DRM_I915_GEM_CREATE_EXT
   * @i915: i915 private
   * @size: size of the buffer, in bytes
   * @placements: possible placement regions, in priority order
@@ -214,7 +215,7 @@ i915_gem_dumb_create(struct drm_file *file,
  }
  
  /**

- * Creates a new mm object and returns a handle to it.
+ * i915_gem_create_ioctl - Creates a new mm object and returns a handle to it.
   * @dev: drm device pointer
   * @data: ioctl data blob
   * @file: drm file pointer
@@ -398,7 +399,8 @@ static const i915_user_extension_fn create_extensions[] = {
  };
  
  /**

- * Creates a new mm object and returns a handle to it.
+ * i915_gem_create_ext_ioctl - Creates a new mm object and returns a handle
+ * to it.
   * @dev: drm device pointer
   * @data: ioctl data blob
   * @file: drm file pointer
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c 
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 1674b0c5802b..49d7841ba979 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -113,7 +113,8 @@ void i915_gem_object_flush_if_display_locked(struct 
drm_i915_gem_object *obj)
  }
  
  /**

- * Moves a single object to the WC read, and possibly write domain.
+ * i915_gem_object_set_to_wc_domain - Moves a single object to the WC read,
+ * and possibly write domain.
   * @obj: object to act on
   * @write: ask for write access or read only
   *
@@ -174,7 +175,8 @@ i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object 
*obj, bool write)
  }
  
  /**

- * Moves a single object to the GTT read, and possibly write domain.
+ * i915_gem_object_set_to_gtt_domain - Moves a single object to the GTT read,
+ * and possibly