[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/d12+: Disable DMC handlers during loading/disabling the firmware (rev2)
== Series Details == Series: series starting with [1/2] drm/i915/d12+: Disable DMC handlers during loading/disabling the firmware (rev2) URL : https://patchwork.freedesktop.org/series/106767/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] [v1.1 01/23] drm/i915: Read graphics/media/display arch version from hw
From: Matt Roper
Going forward, the hardware teams no longer consider new platforms to
have a "generation" in the way we've defined it for past platforms.
Instead, each IP block (graphics, media, display) will have their own
architecture major.minor versions and stepping ID's which should be read
directly from a register in the MMIO space. New hardware programming
styles, features, and workarounds should be conditional solely on the
architecture version, and should no longer be derived from the PCI
device ID, revision ID, or platform-specific feature flags.
v1.1: Fix build error
Bspec: 63361, 64111
Signed-off-by: Matt Roper
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +
drivers/gpu/drm/i915/i915_driver.c| 80 ++-
drivers/gpu/drm/i915/i915_drv.h | 16 ++--
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_device_info.c | 32
drivers/gpu/drm/i915/intel_device_info.h | 14
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
8 files changed, 128 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 60d6eb5f245b..fab8e4ff74d5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -39,6 +39,8 @@
#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)
+#define GMD_ID_GRAPHICS_MMIO(0xd8c)
+
#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
#define SF_MCR_SELECTOR_MMIO(0xfd8)
#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index deb8a8b76965..33566f6e9546 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -70,6 +70,7 @@
#include "gem/i915_gem_pm.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
+#include "gt/intel_gt_regs.h"
#include "gt/intel_rc6.h"
#include "pxp/intel_pxp_pm.h"
@@ -306,15 +307,83 @@ static void sanitize_gpu(struct drm_i915_private *i915)
__intel_gt_reset(to_gt(i915), ALL_ENGINES);
}
+#define IP_VER_READ(offset, ri_prefix) \
+ addr = pci_iomap_range(pdev, 0, offset, sizeof(u32)); \
+ if (drm_WARN_ON(>drm, !addr)) { \
+ /* Fall back to whatever was in the device info */ \
+ RUNTIME_INFO(i915)->ri_prefix.ver =
INTEL_INFO(i915)->ri_prefix.ver; \
+ RUNTIME_INFO(i915)->ri_prefix.rel =
INTEL_INFO(i915)->ri_prefix.rel; \
+ goto ri_prefix##done; \
+ } \
+ \
+ ver = ioread32(addr); \
+ pci_iounmap(pdev, addr); \
+ \
+ RUNTIME_INFO(i915)->ri_prefix.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK,
ver); \
+ RUNTIME_INFO(i915)->ri_prefix.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK,
ver); \
+ RUNTIME_INFO(i915)->ri_prefix.step = REG_FIELD_GET(GMD_ID_STEP, ver); \
+ \
+ /* Sanity check against expected versions from device info */ \
+ if (RUNTIME_INFO(i915)->ri_prefix.ver !=
INTEL_INFO(i915)->ri_prefix.ver || \
+ RUNTIME_INFO(i915)->ri_prefix.rel >
INTEL_INFO(i915)->ri_prefix.rel) \
+ drm_dbg(>drm, \
+ "Hardware reports " #ri_prefix " IP version %u.%u but
minimum expected is %u.%u\n", \
+ RUNTIME_INFO(i915)->ri_prefix.ver, \
+ RUNTIME_INFO(i915)->ri_prefix.rel, \
+ INTEL_INFO(i915)->ri_prefix.ver, \
+ INTEL_INFO(i915)->ri_prefix.rel); \
+ri_prefix##done:
+
+/**
+ * intel_ipver_early_init - setup IP version values
+ * @dev_priv: device private
+ *
+ * Setup the graphics version for the current device. This must be done before
+ * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this
+ * function should be called very early in the driver initialization sequence.
+ *
+ * Regular MMIO access is not yet setup at the point this function is called so
+ * we peek at the appropriate MMIO offset directly. The GMD_ID register is
+ * part of an 'always on' power well by design, so we don't need to worry about
+ * forcewake while reading it.
+ */
+static void intel_ipver_early_init(struct drm_i915_private *i915)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ void __iomem *addr;
+ u32 ver;
+
+ if (!HAS_GMD_ID(i915)) {
+ drm_WARN_ON(>drm, INTEL_INFO(i915)->graphics.ver > 12);
+
+ RUNTIME_INFO(i915)->graphics.ver =
INTEL_INFO(i915)->graphics.ver;
+ RUNTIME_INFO(i915)->graphics.rel =
INTEL_INFO(i915)->graphics.rel;
+ /* media ver = graphics ver for older platforms */
+ RUNTIME_INFO(i915)->media.ver =
[Intel-gfx] ✓ Fi.CI.BAT: success for Random assortment of (mostly) GuC related patches (rev3)
== Series Details ==
Series: Random assortment of (mostly) GuC related patches (rev3)
URL : https://patchwork.freedesktop.org/series/106272/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106272v3
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v3/index.html
Participating hosts (38 -> 34)
--
Additional (2): fi-hsw-4770 bat-jsl-1
Missing(6): bat-dg1-5 bat-dg2-8 bat-adlm-1 bat-jsl-3 bat-rplp-1
fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_106272v3:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_engines:
- {bat-rpls-1}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-rpls-1/igt@i915_selftest@live@gt_engines.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v3/bat-rpls-1/igt@i915_selftest@live@gt_engines.html
New tests
-
New tests have been introduced between CI_DRM_11946 and Patchwork_106272v3:
### New IGT tests (1) ###
* igt@i915_selftest@live@guc_hang:
- Statuses : 28 pass(s)
- Exec time: [0.42, 3.83] s
Known issues
Here are the changes found in Patchwork_106272v3 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#3012])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v3/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [PASS][4] -> [INCOMPLETE][5] ([i915#3303] /
[i915#4785])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v3/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][6] -> [DMESG-FAIL][7] ([i915#4528])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v3/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271]) +9 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v3/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v3/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1072]) +3
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v3/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@runner@aborted:
- fi-blb-e6850: NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#2403] /
[i915#4312])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v3/fi-blb-e6850/igt@run...@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][12] ([i915#4312])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v3/fi-bdw-5557u/igt@run...@aborted.html
- fi-hsw-g3258: NOTRUN -> [FAIL][13] ([fdo#109271] / [i915#4312] /
[i915#6246])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v3/fi-hsw-g3258/igt@run...@aborted.html
Possible fixes
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][14] ([i915#2582]) -> [PASS][15] +4 similar
issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-rpls-2/igt@fb...@read.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v3/bat-rpls-2/igt@fb...@read.html
* igt@i915_selftest@live@gtt:
- {bat-dg2-9}:[DMESG-WARN][16] ([i915#5763]) -> [PASS][17] +5
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-dg2-9/igt@i915_selftest@l...@gtt.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v3/bat-dg2-9/igt@i915_selftest@l...@gtt.html
* igt@kms_frontbuffer_tracking@basic:
- {bat-rpls-2}: [SKIP][18] ([i915#1849]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-rpls-2/igt@kms_frontbuffer_track...@basic.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106272v3/bat-rpls-2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-fence-flip:
- {bat-rpls-2}:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Random assortment of (mostly) GuC related patches (rev3)
== Series Details == Series: Random assortment of (mostly) GuC related patches (rev3) URL : https://patchwork.freedesktop.org/series/106272/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Random assortment of (mostly) GuC related patches (rev3)
== Series Details == Series: Random assortment of (mostly) GuC related patches (rev3) URL : https://patchwork.freedesktop.org/series/106272/ State : warning == Summary == Error: dim checkpatch failed fe6417b35380 drm/i915/guc: Route semaphores to GuC for Gen12+ 383e87c640b2 drm/i915/guc: Fix issues with live_preempt_cancel e13f86d5e8df drm/i915/guc: Add selftest for a hung GuC Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in import git ModuleNotFoundError: No module named 'git' -:23: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #23: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 170 lines checked 62827ece554d drm/i915/selftest: Cope with not having an RCS engine d91bb3719581 drm/i915/guc: Support larger contexts on newer hardware d0928d5d4461 drm/i915/guc: Don't abort on CTB_UNUSED status
[Intel-gfx] ✓ Fi.CI.BAT: success for Fixes and improvements to GuC logging and error capture
== Series Details ==
Series: Fixes and improvements to GuC logging and error capture
URL : https://patchwork.freedesktop.org/series/106789/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106789v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/index.html
Participating hosts (38 -> 36)
--
Additional (2): fi-hsw-4770 bat-jsl-1
Missing(4): bat-rplp-1 bat-adlm-1 fi-bdw-samus bat-dg1-5
Known issues
Here are the changes found in Patchwork_106789v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#3012])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][2] ([i915#4785])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-g3258: [PASS][3] -> [INCOMPLETE][4] ([i915#3303] /
[i915#4785])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][5] -> [DMESG-FAIL][6] ([i915#4528])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-bdw-5557u: [PASS][7] -> [INCOMPLETE][8] ([i915#146])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271]) +9 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-pnv-d510:NOTRUN -> [SKIP][10] ([fdo#109271])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +7
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1072]) +3
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][13] ([fdo#109271] / [i915#4312] /
[i915#5594] / [i915#6246])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/fi-hsw-4770/igt@run...@aborted.html
- fi-blb-e6850: NOTRUN -> [FAIL][14] ([fdo#109271] / [i915#2403] /
[i915#4312])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/fi-blb-e6850/igt@run...@aborted.html
- fi-hsw-g3258: NOTRUN -> [FAIL][15] ([fdo#109271] / [i915#4312] /
[i915#6246])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/fi-hsw-g3258/igt@run...@aborted.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- fi-kbl-guc: [FAIL][16] ([i915#6253]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-kbl-guc/igt@debugfs_test@read_all_entries.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/fi-kbl-guc/igt@debugfs_test@read_all_entries.html
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][18] ([i915#2582]) -> [PASS][19] +4 similar
issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-rpls-2/igt@fb...@read.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/bat-rpls-2/igt@fb...@read.html
* igt@i915_selftest@live@gtt:
- {bat-dg2-9}:[DMESG-WARN][20] ([i915#5763]) -> [PASS][21] +5
similar issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-dg2-9/igt@i915_selftest@l...@gtt.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106789v1/bat-dg2-9/igt@i915_selftest@l...@gtt.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][22] ([i915#4528]) ->
Re: [Intel-gfx] [PATCH 5/6] drm/i915/guc: Support larger contexts on newer hardware
On 7/27/2022 19:42, john.c.harri...@intel.com wrote:
From: Matthew Brost
The GuC needs a copy of a golden context for implementing watchdog
resets (aka media resets). This context is larger on newer platforms.
So adjust the size being allocated/copied accordingly.
Signed-off-by: Matthew Brost
Signed-off-by: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index ba7541f3ca610..74cbe8eaf5318 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -464,7 +464,11 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
}
#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
-#define LRC_SKIP_SIZE (LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE)
+#define XEHP_LR_HW_CONTEXT_SIZE (96 * sizeof(u32))
+#define LR_HW_CONTEXT_SZ(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50) ? \
+ XEHP_LR_HW_CONTEXT_SIZE : \
+ LR_HW_CONTEXT_SIZE)
+#define LRC_SKIP_SIZE(i915) (LRC_PPHWSP_SZ * PAGE_SIZE +
LR_HW_CONTEXT_SZ(i915))
static int guc_prep_golden_context(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
@@ -525,7 +529,7 @@ static int guc_prep_golden_context(struct intel_guc *guc)
* on all engines).
*/
ads_blob_write(guc, ads.eng_state_size[guc_class],
- real_size - LRC_SKIP_SIZE);
+ real_size - LRC_SKIP_SIZE(gt->i915));
ads_blob_write(guc, ads.golden_context_lrca[guc_class],
addr_ggtt);
@@ -599,7 +603,7 @@ static void guc_init_golden_context(struct intel_guc *guc)
}
GEM_BUG_ON(ads_blob_read(guc, ads.eng_state_size[guc_class]) !=
- real_size - LRC_SKIP_SIZE);
+ real_size - LRC_SKIP_SIZE(gt->i915));
GEM_BUG_ON(ads_blob_read(guc,
ads.golden_context_lrca[guc_class]) != addr_ggtt);
addr_ggtt += alloc_size;
Re: [Intel-gfx] [PATCH 2/6] drm/i915/guc: Fix issues with live_preempt_cancel
On 7/27/2022 19:42, john.c.harri...@intel.com wrote:
From: Matthew Brost
Having semaphores results in different behavior when a dependent request
is cancelled. In the case of semaphores the request could be on the HW
and complete successfully while without the request is held in the
driver and the error from the dependent request is propagated. Fix
live_preempt_cancel to take this behavior into account.
Also update live_preempt_cancel to use new function intel_context_ban
rather than intel_context_set_banned.
Signed-off-by: Matthew Brost
Signed-off-by: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 02fc97a0ab502..015f8cd3463e2 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -2087,7 +2087,7 @@ static int __cancel_active0(struct live_preempt_cancel
*arg)
goto out;
}
- intel_context_set_banned(rq->context);
+ intel_context_ban(rq->context, rq);
err = intel_engine_pulse(arg->engine);
if (err)
goto out;
@@ -2146,7 +2146,7 @@ static int __cancel_active1(struct live_preempt_cancel
*arg)
if (err)
goto out;
- intel_context_set_banned(rq[1]->context);
+ intel_context_ban(rq[1]->context, rq[1]);
err = intel_engine_pulse(arg->engine);
if (err)
goto out;
@@ -2229,7 +2229,7 @@ static int __cancel_queued(struct live_preempt_cancel
*arg)
if (err)
goto out;
- intel_context_set_banned(rq[2]->context);
+ intel_context_ban(rq[2]->context, rq[2]);
err = intel_engine_pulse(arg->engine);
if (err)
goto out;
@@ -2244,7 +2244,13 @@ static int __cancel_queued(struct live_preempt_cancel
*arg)
goto out;
}
- if (rq[1]->fence.error != 0) {
+ /*
+* The behavior between having semaphores and not is different. With
+* semaphores the subsequent request is on the hardware and not
cancelled
+* while without the request is held in the driver and cancelled.
+*/
+ if (intel_engine_has_semaphores(rq[1]->engine) &&
+ rq[1]->fence.error != 0) {
pr_err("Normal inflight1 request did not complete\n");
err = -EINVAL;
goto out;
@@ -2292,7 +2298,7 @@ static int __cancel_hostile(struct live_preempt_cancel
*arg)
goto out;
}
- intel_context_set_banned(rq->context);
+ intel_context_ban(rq->context, rq);
err = intel_engine_pulse(arg->engine); /* force reset */
if (err)
goto out;
[Intel-gfx] [PATCH 5/6] drm/i915/guc: Support larger contexts on newer hardware
From: Matthew Brost
The GuC needs a copy of a golden context for implementing watchdog
resets (aka media resets). This context is larger on newer platforms.
So adjust the size being allocated/copied accordingly.
Signed-off-by: Matthew Brost
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index ba7541f3ca610..74cbe8eaf5318 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -464,7 +464,11 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
}
#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
-#define LRC_SKIP_SIZE (LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE)
+#define XEHP_LR_HW_CONTEXT_SIZE (96 * sizeof(u32))
+#define LR_HW_CONTEXT_SZ(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50) ? \
+ XEHP_LR_HW_CONTEXT_SIZE : \
+ LR_HW_CONTEXT_SIZE)
+#define LRC_SKIP_SIZE(i915) (LRC_PPHWSP_SZ * PAGE_SIZE +
LR_HW_CONTEXT_SZ(i915))
static int guc_prep_golden_context(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
@@ -525,7 +529,7 @@ static int guc_prep_golden_context(struct intel_guc *guc)
* on all engines).
*/
ads_blob_write(guc, ads.eng_state_size[guc_class],
- real_size - LRC_SKIP_SIZE);
+ real_size - LRC_SKIP_SIZE(gt->i915));
ads_blob_write(guc, ads.golden_context_lrca[guc_class],
addr_ggtt);
@@ -599,7 +603,7 @@ static void guc_init_golden_context(struct intel_guc *guc)
}
GEM_BUG_ON(ads_blob_read(guc, ads.eng_state_size[guc_class]) !=
- real_size - LRC_SKIP_SIZE);
+ real_size - LRC_SKIP_SIZE(gt->i915));
GEM_BUG_ON(ads_blob_read(guc,
ads.golden_context_lrca[guc_class]) != addr_ggtt);
addr_ggtt += alloc_size;
--
2.37.1
[Intel-gfx] [PATCH 2/6] drm/i915/guc: Fix issues with live_preempt_cancel
From: Matthew Brost
Having semaphores results in different behavior when a dependent request
is cancelled. In the case of semaphores the request could be on the HW
and complete successfully while without the request is held in the
driver and the error from the dependent request is propagated. Fix
live_preempt_cancel to take this behavior into account.
Also update live_preempt_cancel to use new function intel_context_ban
rather than intel_context_set_banned.
Signed-off-by: Matthew Brost
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 02fc97a0ab502..015f8cd3463e2 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -2087,7 +2087,7 @@ static int __cancel_active0(struct live_preempt_cancel
*arg)
goto out;
}
- intel_context_set_banned(rq->context);
+ intel_context_ban(rq->context, rq);
err = intel_engine_pulse(arg->engine);
if (err)
goto out;
@@ -2146,7 +2146,7 @@ static int __cancel_active1(struct live_preempt_cancel
*arg)
if (err)
goto out;
- intel_context_set_banned(rq[1]->context);
+ intel_context_ban(rq[1]->context, rq[1]);
err = intel_engine_pulse(arg->engine);
if (err)
goto out;
@@ -2229,7 +2229,7 @@ static int __cancel_queued(struct live_preempt_cancel
*arg)
if (err)
goto out;
- intel_context_set_banned(rq[2]->context);
+ intel_context_ban(rq[2]->context, rq[2]);
err = intel_engine_pulse(arg->engine);
if (err)
goto out;
@@ -2244,7 +2244,13 @@ static int __cancel_queued(struct live_preempt_cancel
*arg)
goto out;
}
- if (rq[1]->fence.error != 0) {
+ /*
+* The behavior between having semaphores and not is different. With
+* semaphores the subsequent request is on the hardware and not
cancelled
+* while without the request is held in the driver and cancelled.
+*/
+ if (intel_engine_has_semaphores(rq[1]->engine) &&
+ rq[1]->fence.error != 0) {
pr_err("Normal inflight1 request did not complete\n");
err = -EINVAL;
goto out;
@@ -2292,7 +2298,7 @@ static int __cancel_hostile(struct live_preempt_cancel
*arg)
goto out;
}
- intel_context_set_banned(rq->context);
+ intel_context_ban(rq->context, rq);
err = intel_engine_pulse(arg->engine); /* force reset */
if (err)
goto out;
--
2.37.1
[Intel-gfx] [PATCH 4/6] drm/i915/selftest: Cope with not having an RCS engine
From: John Harrison
It is no longer guaranteed that there will always be an RCS engine.
So, use the helper function for finding the first available engine that
can be used for general purpose selftets.
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 6493265d5f642..7f3bb1d34dfbf 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1302,13 +1302,15 @@ static int igt_reset_wait(void *arg)
{
struct intel_gt *gt = arg;
struct i915_gpu_error *global = >i915->gpu_error;
- struct intel_engine_cs *engine = gt->engine[RCS0];
+ struct intel_engine_cs *engine;
struct i915_request *rq;
unsigned int reset_count;
struct hang h;
long timeout;
int err;
+ engine = intel_selftest_find_any_engine(gt);
+
if (!engine || !intel_engine_can_store_dword(engine))
return 0;
@@ -1432,7 +1434,7 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
int (*fn)(void *),
unsigned int flags)
{
- struct intel_engine_cs *engine = gt->engine[RCS0];
+ struct intel_engine_cs *engine;
struct drm_i915_gem_object *obj;
struct task_struct *tsk = NULL;
struct i915_request *rq;
@@ -1444,6 +1446,8 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
if (!gt->ggtt->num_fences && flags & EXEC_OBJECT_NEEDS_FENCE)
return 0;
+ engine = intel_selftest_find_any_engine(gt);
+
if (!engine || !intel_engine_can_store_dword(engine))
return 0;
@@ -1819,12 +1823,14 @@ static int igt_handle_error(void *arg)
{
struct intel_gt *gt = arg;
struct i915_gpu_error *global = >i915->gpu_error;
- struct intel_engine_cs *engine = gt->engine[RCS0];
+ struct intel_engine_cs *engine;
struct hang h;
struct i915_request *rq;
struct i915_gpu_coredump *error;
int err;
+ engine = intel_selftest_find_any_engine(gt);
+
/* Check that we can issue a global GPU and engine reset */
if (!intel_has_reset_engine(gt))
--
2.37.1
[Intel-gfx] [PATCH 1/6] drm/i915/guc: Route semaphores to GuC for Gen12+
From: Michał Winiarski
In GuC submission mode, there is an option to use auto-switch out
semaphores and have GuC auto-switch in a waiting context. This
requires routing the semaphore interrupt to GuC.
Signed-off-by: Michał Winiarski
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h| 4
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 14 ++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index 8dc063f087eb1..a7092f711e9cd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -102,6 +102,10 @@
#define GUC_SEND_TRIGGER (1<<0)
#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0)
+#define GEN12_GUC_SEM_INTR_ENABLES _MMIO(0xc71c)
+#define GUC_SEM_INTR_ROUTE_TO_GUCBIT(31)
+#define GUC_SEM_INTR_ENABLE_ALL (0xff)
+
#define GUC_NUM_DOORBELLS 256
/* format of the HW-monitored doorbell cacheline */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 76916aed897ad..0b8c6450fa344 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4191,13 +4191,27 @@ int intel_guc_submission_setup(struct intel_engine_cs
*engine)
void intel_guc_submission_enable(struct intel_guc *guc)
{
+ struct intel_gt *gt = guc_to_gt(guc);
+
+ /* Enable and route to GuC */
+ if (GRAPHICS_VER(gt->i915) >= 12)
+ intel_uncore_write(gt->uncore, GEN12_GUC_SEM_INTR_ENABLES,
+ GUC_SEM_INTR_ROUTE_TO_GUC |
+ GUC_SEM_INTR_ENABLE_ALL);
+
guc_init_lrc_mapping(guc);
guc_init_engine_stats(guc);
}
void intel_guc_submission_disable(struct intel_guc *guc)
{
+ struct intel_gt *gt = guc_to_gt(guc);
+
/* Note: By the time we're here, GuC may have already been reset */
+
+ /* Disable and route to host */
+ if (GRAPHICS_VER(gt->i915) >= 12)
+ intel_uncore_write(gt->uncore, GEN12_GUC_SEM_INTR_ENABLES, 0x0);
}
static bool __guc_submission_supported(struct intel_guc *guc)
--
2.37.1
[Intel-gfx] [PATCH 6/6] drm/i915/guc: Don't abort on CTB_UNUSED status
From: John Harrison
When the KMD sends a CLIENT_RESET request to GuC (as part of the
suspend sequence), GuC will mark the CTB buffer as 'UNUSED'. If the
KMD then checked the CTB queue, it would see a non-zero status value
and report the buffer as corrupted.
Technically, no G2H messages should be received once the CLIENT_RESET
has been sent. However, if a context was outstanding on an engine then
it would get reset and a reset notification would be sent. So, don't
actually treat UNUSED as a catastrophic error. Just flag it up as
unexpected and keep going.
Signed-off-by: John Harrison
---
.../i915/gt/uc/abi/guc_communication_ctb_abi.h | 8 +---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 18 --
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
index df83c1cc7c7a6..28b8387f97b77 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
@@ -37,6 +37,7 @@
* | | | - _`GUC_CTB_STATUS_OVERFLOW` = 1 (head/tail too large)
|
* | | | - _`GUC_CTB_STATUS_UNDERFLOW` = 2 (truncated message)
|
* | | | - _`GUC_CTB_STATUS_MISMATCH` = 4 (head/tail modified)
|
+ * | | | - _`GUC_CTB_STATUS_UNUSED` = 8 (CTB is not in use)
|
*
+---+---+--+
* |...| | RESERVED = MBZ
|
*
+---+---+--+
@@ -49,9 +50,10 @@ struct guc_ct_buffer_desc {
u32 tail;
u32 status;
#define GUC_CTB_STATUS_NO_ERROR0
-#define GUC_CTB_STATUS_OVERFLOW(1 << 0)
-#define GUC_CTB_STATUS_UNDERFLOW (1 << 1)
-#define GUC_CTB_STATUS_MISMATCH(1 << 2)
+#define GUC_CTB_STATUS_OVERFLOWBIT(0)
+#define GUC_CTB_STATUS_UNDERFLOW BIT(1)
+#define GUC_CTB_STATUS_MISMATCHBIT(2)
+#define GUC_CTB_STATUS_UNUSED BIT(3)
u32 reserved[13];
} __packed;
static_assert(sizeof(struct guc_ct_buffer_desc) == 64);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index f01325cd1b625..11b5d4ddb19ce 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -816,8 +816,22 @@ static int ct_read(struct intel_guc_ct *ct, struct
ct_incoming_msg **msg)
if (unlikely(ctb->broken))
return -EPIPE;
- if (unlikely(desc->status))
- goto corrupted;
+ if (unlikely(desc->status)) {
+ u32 status = desc->status;
+
+ if (status & GUC_CTB_STATUS_UNUSED) {
+ /*
+* Potentially valid if a CLIENT_RESET request resulted
in
+* contexts/engines being reset. But should never
happen as
+* no contexts should be active when CLIENT_RESET is
sent.
+*/
+ CT_ERROR(ct, "Unexpected G2H after GuC has stopped!\n");
+ status &= ~GUC_CTB_STATUS_UNUSED;
+ }
+
+ if (status)
+ goto corrupted;
+ }
GEM_BUG_ON(head > size);
--
2.37.1
[Intel-gfx] [PATCH 3/6] drm/i915/guc: Add selftest for a hung GuC
From: Rahul Kumar Singh
Add a test to check that the hangcheck will recover from a submission
hang in the GuC.
Signed-off-by: Rahul Kumar Singh
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 +
.../drm/i915/gt/uc/selftest_guc_hangcheck.c | 159 ++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
3 files changed, 161 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0b8c6450fa344..ff205c4125857 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -5177,4 +5177,5 @@ bool intel_guc_virtual_engine_has_heartbeat(const struct
intel_engine_cs *ve)
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_guc.c"
#include "selftest_guc_multi_lrc.c"
+#include "selftest_guc_hangcheck.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
new file mode 100644
index 0..af913c4b09d37
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright �� 2019 Intel Corporation
+ */
+
+#include "selftests/igt_spinner.h"
+#include "selftests/igt_reset.h"
+#include "selftests/intel_scheduler_helpers.h"
+#include "gt/intel_engine_heartbeat.h"
+#include "gem/selftests/mock_context.h"
+
+#define BEAT_INTERVAL 100
+
+static struct i915_request *nop_request(struct intel_engine_cs *engine)
+{
+ struct i915_request *rq;
+
+ rq = intel_engine_create_kernel_request(engine);
+ if (IS_ERR(rq))
+ return rq;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ return rq;
+}
+
+static int intel_hang_guc(void *arg)
+{
+ struct intel_gt *gt = arg;
+ int ret = 0;
+ struct i915_gem_context *ctx;
+ struct intel_context *ce;
+ struct igt_spinner spin;
+ struct i915_request *rq;
+ intel_wakeref_t wakeref;
+ struct i915_gpu_error *global = >i915->gpu_error;
+ struct intel_engine_cs *engine;
+ unsigned int reset_count;
+ u32 guc_status;
+ u32 old_beat;
+
+ ctx = kernel_context(gt->i915, NULL);
+ if (IS_ERR(ctx)) {
+ pr_err("Failed get kernel context: %ld\n", PTR_ERR(ctx));
+ return PTR_ERR(ctx);
+ }
+
+ wakeref = intel_runtime_pm_get(gt->uncore->rpm);
+
+ ce = intel_context_create(gt->engine[BCS0]);
+ if (IS_ERR(ce)) {
+ ret = PTR_ERR(ce);
+ pr_err("Failed to create spinner request: %d\n", ret);
+ goto err;
+ }
+
+ engine = ce->engine;
+ reset_count = i915_reset_count(global);
+
+ old_beat = engine->props.heartbeat_interval_ms;
+ ret = intel_engine_set_heartbeat(engine, BEAT_INTERVAL);
+ if (ret) {
+ pr_err("Failed to boost heatbeat interval: %d\n", ret);
+ goto err;
+ }
+
+ ret = igt_spinner_init(, engine->gt);
+ if (ret) {
+ pr_err("Failed to create spinner: %d\n", ret);
+ goto err;
+ }
+
+ rq = igt_spinner_create_request(, ce, MI_NOOP);
+ intel_context_put(ce);
+ if (IS_ERR(rq)) {
+ ret = PTR_ERR(rq);
+ pr_err("Failed to create spinner request: %d\n", ret);
+ goto err_spin;
+ }
+
+ ret = request_add_spin(rq, );
+ if (ret) {
+ i915_request_put(rq);
+ pr_err("Failed to add Spinner request: %d\n", ret);
+ goto err_spin;
+ }
+
+ ret = intel_reset_guc(gt);
+ if (ret) {
+ i915_request_put(rq);
+ pr_err("Failed to reset GuC, ret = %d\n", ret);
+ goto err_spin;
+ }
+
+ guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
+ if (!(guc_status & GS_MIA_IN_RESET)) {
+ i915_request_put(rq);
+ pr_err("GuC failed to reset: status = 0x%08X\n", guc_status);
+ ret = -EIO;
+ goto err_spin;
+ }
+
+ /* Wait for the heartbeat to cause a reset */
+ ret = intel_selftest_wait_for_rq(rq);
+ i915_request_put(rq);
+ if (ret) {
+ pr_err("Request failed to complete: %d\n", ret);
+ goto err_spin;
+ }
+
+ if (i915_reset_count(global) == reset_count) {
+ pr_err("Failed to record a GPU reset\n");
+ ret = -EINVAL;
+ goto err_spin;
+ }
+
+err_spin:
+ igt_spinner_end();
+ igt_spinner_fini();
+ intel_engine_set_heartbeat(engine, old_beat);
+
+ if (ret == 0) {
+ rq = nop_request(engine);
+ if (IS_ERR(rq)) {
+ ret = PTR_ERR(rq);
+
[Intel-gfx] [PATCH 0/6] Random assortment of (mostly) GuC related patches
From: John Harrison Pushing a bunch of patches which had gotten forgotten about. Signed-off-by: John Harrison John Harrison (2): drm/i915/selftest: Cope with not having an RCS engine drm/i915/guc: Don't abort on CTB_UNUSED status Matthew Brost (2): drm/i915/guc: Fix issues with live_preempt_cancel drm/i915/guc: Support larger contexts on newer hardware Michał Winiarski (1): drm/i915/guc: Route semaphores to GuC for Gen12+ Rahul Kumar Singh (1): drm/i915/guc: Add selftest for a hung GuC drivers/gpu/drm/i915/gt/selftest_execlists.c | 16 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 12 +- .../gt/uc/abi/guc_communication_ctb_abi.h | 8 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 10 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 18 +- drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h| 4 + .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 15 ++ .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 159 ++ .../drm/i915/selftests/i915_live_selftests.h | 1 + 9 files changed, 227 insertions(+), 16 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c -- 2.37.1
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Fixes and improvements to GuC logging and error capture
== Series Details == Series: Fixes and improvements to GuC logging and error capture URL : https://patchwork.freedesktop.org/series/106789/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fixes and improvements to GuC logging and error capture
== Series Details == Series: Fixes and improvements to GuC logging and error capture URL : https://patchwork.freedesktop.org/series/106789/ State : warning == Summary == Error: dim checkpatch failed 77f455e72ebc drm/i915/guc: Add a helper for log buffer size f49ac6e6709a drm/i915/guc: Fix capture size warning and bump the size c88ca5a46e03 drm/i915/guc: Add GuC <-> kernel time stamp translation information 1ea2fd778459 drm/i915/guc: Record CTB info in error logs eb7e76603266 drm/i915/guc: Use streaming loads to speed up dumping the guc log 01657cac8399 drm/i915/guc: Make GuC log sizes runtime configurable -:462: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #462: FILE: drivers/gpu/drm/i915/i915_params.c:175: +i915_param_named(guc_log_size_crash, int, 0400, + "GuC firmware logging buffer size for crash dumps (in MB)" -:466: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #466: FILE: drivers/gpu/drm/i915/i915_params.c:179: +i915_param_named(guc_log_size_debug, int, 0400, + "GuC firmware logging buffer size for debug logs (in MB)" -:470: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #470: FILE: drivers/gpu/drm/i915/i915_params.c:183: +i915_param_named(guc_log_size_capture, int, 0400, + "GuC error capture register dump buffer size (in MB)" total: 0 errors, 0 warnings, 3 checks, 434 lines checked bec1c0368504 drm/i915/guc: Reduce spam from error capture -:129: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #129: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:1481: + i915_error_printf(ebuf, "[%ld][%ld]", + FIELD_GET(GUC_REGSET_STEERING_GROUP, regs[j].flags), total: 0 errors, 0 warnings, 1 checks, 118 lines checked
[Intel-gfx] [PATCH 2/7] drm/i915/guc: Fix capture size warning and bump the size
From: John Harrison
There was a size check to warn if the GuC error state capture buffer
allocation would be too small to fit a reasonable amount of capture
data for the current platform. Unfortunately, the test was done too
early in the boot sequence and was actually testing 'if(-ENODEV >
size)'.
Move the check to be later. The check is only used to print a warning
message, so it doesn't really matter how early or late it is done.
Note that it is not possible to dynamically size the buffer because
the allocation needs to be done before the engine information is
available (at least, it would be in the intended two-phase GuC init
process).
Now that the check works, it is reporting size too small for newer
platforms. The check includes a 3x oversample multiplier to allow for
multiple error captures to be bufferd by GuC before i915 has a chance
to read them out. This is less important than simply being big enough
to fit the first capture.
So a) bump the default size to be large enough for one capture minimum
and b) make the warning only if one capture won't fit, instead use a
notice for the 3x size.
Note that the size estimate is a worst case scenario. Actual captures
will likely be smaller.
Lastly, use drm_warn istead of DRM_WARN as the former provides more
infmration and the latter is deprecated.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 40 ++-
.../gpu/drm/i915/gt/uc/intel_guc_capture.h| 1 -
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 4 --
drivers/gpu/drm/i915/gt/uc/intel_guc_log.h| 4 +-
4 files changed, 31 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 75257bd20ff01..b54b7883320b1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -600,10 +600,8 @@ intel_guc_capture_getnullheader(struct intel_guc *guc,
return 0;
}
-#define GUC_CAPTURE_OVERBUFFER_MULTIPLIER 3
-
-int
-intel_guc_capture_output_min_size_est(struct intel_guc *guc)
+static int
+guc_capture_output_min_size_est(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
struct intel_engine_cs *engine;
@@ -623,13 +621,8 @@ intel_guc_capture_output_min_size_est(struct intel_guc
*guc)
* For each engine instance, there would be 1 x
guc_state_capture_group_t output
* followed by 3 x guc_state_capture_t lists. The latter is how the
register
* dumps are split across different register types (where the '3' are
global vs class
-* vs instance). Finally, let's multiply the whole thing by 3x (just so
we are
-* not limited to just 1 round of data in a worst case full register
dump log)
-*
-* NOTE: intel_guc_log that allocates the log buffer would round this
size up to
-* a power of two.
+* vs instance).
*/
-
for_each_engine(engine, gt, id) {
worst_min_size += sizeof(struct
guc_state_capture_group_header_t) +
(3 * sizeof(struct
guc_state_capture_header_t));
@@ -649,7 +642,30 @@ intel_guc_capture_output_min_size_est(struct intel_guc
*guc)
worst_min_size += (num_regs * sizeof(struct guc_mmio_reg));
- return (worst_min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER);
+ return worst_min_size;
+}
+
+/*
+ * Add on a 3x multiplier to allow for multiple back-to-back captures occurring
+ * before the i915 can read the data out and process it
+ */
+#define GUC_CAPTURE_OVERBUFFER_MULTIPLIER 3
+
+static void check_guc_capture_size(struct intel_guc *guc)
+{
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+ int min_size = guc_capture_output_min_size_est(guc);
+ int spare_size = min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER;
+
+ if (min_size < 0)
+ drm_warn(>drm, "Failed to calculate GuC error state
capture buffer minimum size: %d!\n",
+min_size);
+ else if (min_size > CAPTURE_BUFFER_SIZE)
+ drm_warn(>drm, "GuC error state capture buffer is too
small: %d < %d\n",
+CAPTURE_BUFFER_SIZE, min_size);
+ else if (spare_size > CAPTURE_BUFFER_SIZE)
+ drm_notice(>drm, "GuC error state capture buffer maybe
too small: %d < %d (min = %d)\n",
+ CAPTURE_BUFFER_SIZE, spare_size, min_size);
}
/*
@@ -1580,5 +1596,7 @@ int intel_guc_capture_init(struct intel_guc *guc)
INIT_LIST_HEAD(>capture->outlist);
INIT_LIST_HEAD(>capture->cachelist);
+ check_guc_capture_size(guc);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
index d3d7bd0b6db64..fbd3713c7832d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
@@ -21,7 +21,6
[Intel-gfx] [PATCH 3/7] drm/i915/guc: Add GuC <-> kernel time stamp translation information
From: John Harrison
It is useful to be able to match GuC events to kernel events when
looking at the GuC log. That requires being able to convert GuC
timestamps to kernel time. So, when dumping error captures and/or GuC
logs, include a stamp in both time zones plus the clock frequency.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h| 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 19 +++
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 2 ++
drivers/gpu/drm/i915/i915_gpu_error.c | 12
drivers/gpu/drm/i915/i915_gpu_error.h | 3 +++
6 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 60d6eb5f245b7..fc7979bd91db5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1007,6 +1007,8 @@
#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
+#define GUCPMTIMESTAMP _MMIO(0xc3e8)
+
#define __GEN9_RCS0_MOCS0 0xc800
#define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) *
4)
#define __GEN9_VCS0_MOCS0 0xc900
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2706a8c650900..ab4aacc516aa4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -389,6 +389,25 @@ void intel_guc_write_params(struct intel_guc *guc)
intel_uncore_forcewake_put(uncore, FORCEWAKE_GT);
}
+void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p)
+{
+ struct intel_gt *gt = guc_to_gt(guc);
+ intel_wakeref_t wakeref;
+ u32 stamp = 0;
+ u64 ktime;
+
+ intel_device_info_print_runtime(RUNTIME_INFO(gt->i915), p);
+
+ with_intel_runtime_pm(>i915->runtime_pm, wakeref)
+ stamp = intel_uncore_read(gt->uncore, GUCPMTIMESTAMP);
+ ktime = ktime_get_boottime_ns();
+
+ drm_printf(p, "Kernel timestamp: 0x%08llX [%llu]\n", ktime, ktime);
+ drm_printf(p, "GuC timestamp: 0x%08X [%u]\n", stamp, stamp);
+ drm_printf(p, "CS timestamp frequency: %u Hz, %u ns\n",
+ gt->clock_frequency, gt->clock_period_ns);
+}
+
int intel_guc_init(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index a7acffbf15d1f..804133df1ac9b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -464,4 +464,6 @@ void intel_guc_load_status(struct intel_guc *guc, struct
drm_printer *p);
void intel_guc_write_barrier(struct intel_guc *guc);
+void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p);
+
#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 991d4a02248dc..07d31ae32f765 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -764,6 +764,8 @@ int intel_guc_log_dump(struct intel_guc_log *log, struct
drm_printer *p,
if (!obj)
return 0;
+ intel_guc_dump_time_info(guc, p);
+
map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
if (IS_ERR(map)) {
DRM_DEBUG("Failed to pin object\n");
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 32e92651ef7c2..addba75252343 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -678,6 +678,7 @@ static void err_print_uc(struct drm_i915_error_state_buf *m,
intel_uc_fw_dump(_uc->guc_fw, );
intel_uc_fw_dump(_uc->huc_fw, );
+ err_printf(m, "GuC timestamp: 0x%08x\n", error_uc->timestamp);
intel_gpu_error_print_vma(m, NULL, error_uc->guc_log);
}
@@ -720,6 +721,8 @@ static void err_print_gt_global_nonguc(struct
drm_i915_error_state_buf *m,
int i;
err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake));
+ err_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
+ gt->clock_frequency, gt->clock_period_ns);
err_printf(m, "EIR: 0x%08x\n", gt->eir);
err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
@@ -1675,6 +1678,13 @@ gt_record_uc(struct intel_gt_coredump *gt,
*/
error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL);
error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL);
+
+ /*
+* Save the GuC log and include a timestamp reference for converting the
+* log times to system times (in conjunction with the error->boottime
and
+* gt->clock_frequency fields saved elsewhere).
+*/
+ error_uc->timestamp =
[Intel-gfx] [PATCH 6/7] drm/i915/guc: Make GuC log sizes runtime configurable
From: John Harrison
The GuC log buffer sizes had to be configured statically at compile
time. This can be quite troublesome when needing to get larger logs
out of a released driver. So re-organise the code to allow a boot time
module parameter override.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 53 ++
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 14 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 176 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.h| 42 +++--
drivers/gpu/drm/i915/i915_params.c| 12 ++
drivers/gpu/drm/i915/i915_params.h| 3 +
6 files changed, 226 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index ab4aacc516aa4..01f2705cb94a3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -224,53 +224,22 @@ static u32 guc_ctl_feature_flags(struct intel_guc *guc)
static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
{
- u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT;
- u32 flags;
-
- #if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0)
- #define LOG_UNIT SZ_1M
- #define LOG_FLAG GUC_LOG_LOG_ALLOC_UNITS
- #else
- #define LOG_UNIT SZ_4K
- #define LOG_FLAG 0
- #endif
-
- #if (((CAPTURE_BUFFER_SIZE) % SZ_1M) == 0)
- #define CAPTURE_UNIT SZ_1M
- #define CAPTURE_FLAG GUC_LOG_CAPTURE_ALLOC_UNITS
- #else
- #define CAPTURE_UNIT SZ_4K
- #define CAPTURE_FLAG 0
- #endif
-
- BUILD_BUG_ON(!CRASH_BUFFER_SIZE);
- BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, LOG_UNIT));
- BUILD_BUG_ON(!DEBUG_BUFFER_SIZE);
- BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, LOG_UNIT));
- BUILD_BUG_ON(!CAPTURE_BUFFER_SIZE);
- BUILD_BUG_ON(!IS_ALIGNED(CAPTURE_BUFFER_SIZE, CAPTURE_UNIT));
-
- BUILD_BUG_ON((CRASH_BUFFER_SIZE / LOG_UNIT - 1) >
- (GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT));
- BUILD_BUG_ON((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) >
- (GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT));
- BUILD_BUG_ON((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) >
- (GUC_LOG_CAPTURE_MASK >> GUC_LOG_CAPTURE_SHIFT));
+ struct intel_guc_log *log = >log;
+ u32 offset, flags;
+
+ GEM_BUG_ON(!log->sizes_initialised);
+
+ offset = intel_guc_ggtt_offset(guc, log->vma) >> PAGE_SHIFT;
flags = GUC_LOG_VALID |
GUC_LOG_NOTIFY_ON_HALF_FULL |
- CAPTURE_FLAG |
- LOG_FLAG |
- ((CRASH_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_CRASH_SHIFT) |
- ((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_DEBUG_SHIFT) |
- ((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) <<
GUC_LOG_CAPTURE_SHIFT) |
+ log->sizes[GUC_LOG_SECTIONS_DEBUG].flag |
+ log->sizes[GUC_LOG_SECTIONS_CAPTURE].flag |
+ (log->sizes[GUC_LOG_SECTIONS_CRASH].count <<
GUC_LOG_CRASH_SHIFT) |
+ (log->sizes[GUC_LOG_SECTIONS_DEBUG].count <<
GUC_LOG_DEBUG_SHIFT) |
+ (log->sizes[GUC_LOG_SECTIONS_CAPTURE].count <<
GUC_LOG_CAPTURE_SHIFT) |
(offset << GUC_LOG_BUF_ADDR_SHIFT);
- #undef LOG_UNIT
- #undef LOG_FLAG
- #undef CAPTURE_UNIT
- #undef CAPTURE_FLAG
-
return flags;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index b54b7883320b1..d2ac53d4f3b6e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -656,16 +656,17 @@ static void check_guc_capture_size(struct intel_guc *guc)
struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
int min_size = guc_capture_output_min_size_est(guc);
int spare_size = min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER;
+ u32 buffer_size = intel_guc_log_section_size_capture(>log);
if (min_size < 0)
drm_warn(>drm, "Failed to calculate GuC error state
capture buffer minimum size: %d!\n",
min_size);
- else if (min_size > CAPTURE_BUFFER_SIZE)
+ else if (min_size > buffer_size)
drm_warn(>drm, "GuC error state capture buffer is too
small: %d < %d\n",
-CAPTURE_BUFFER_SIZE, min_size);
- else if (spare_size > CAPTURE_BUFFER_SIZE)
+buffer_size, min_size);
+ else if (spare_size > buffer_size)
drm_notice(>drm, "GuC error state capture buffer maybe
too small: %d < %d (min = %d)\n",
- CAPTURE_BUFFER_SIZE, spare_size, min_size);
+ buffer_size, spare_size, min_size);
}
/*
@@ -1294,7 +1295,8 @@ static void __guc_capture_process_output(struct intel_guc
*guc)
log_buf_state =
[Intel-gfx] [PATCH 7/7] drm/i915/guc: Reduce spam from error capture
From: John Harrison
Some debug code got left in when the GuC based register save for error
capture was added. Remove that.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 67 ---
1 file changed, 28 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index d2ac53d4f3b6e..8f11651460131 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -1383,33 +1383,22 @@ guc_capture_reg_to_str(const struct intel_guc *guc, u32
owner, u32 type,
return NULL;
}
-#ifdef CONFIG_DRM_I915_DEBUG_GUC
-#define __out(a, ...) \
- do { \
- drm_warn((&(a)->i915->drm), __VA_ARGS__); \
- i915_error_printf((a), __VA_ARGS__); \
- } while (0)
-#else
-#define __out(a, ...) \
- i915_error_printf(a, __VA_ARGS__)
-#endif
-
#define GCAP_PRINT_INTEL_ENG_INFO(ebuf, eng) \
do { \
- __out(ebuf, "i915-Eng-Name: %s command stream\n", \
- (eng)->name); \
- __out(ebuf, "i915-Eng-Inst-Class: 0x%02x\n", (eng)->class);
\
- __out(ebuf, "i915-Eng-Inst-Id: 0x%02x\n", (eng)->instance);
\
- __out(ebuf, "i915-Eng-LogicalMask: 0x%08x\n", \
- (eng)->logical_mask); \
+ i915_error_printf(ebuf, "i915-Eng-Name: %s command
stream\n", \
+ (eng)->name); \
+ i915_error_printf(ebuf, "i915-Eng-Inst-Class: 0x%02x\n",
(eng)->class); \
+ i915_error_printf(ebuf, "i915-Eng-Inst-Id: 0x%02x\n",
(eng)->instance); \
+ i915_error_printf(ebuf, "i915-Eng-LogicalMask: 0x%08x\n", \
+ (eng)->logical_mask); \
} while (0)
#define GCAP_PRINT_GUC_INST_INFO(ebuf, node) \
do { \
- __out(ebuf, "GuC-Engine-Inst-Id: 0x%08x\n", \
- (node)->eng_inst); \
- __out(ebuf, "GuC-Context-Id: 0x%08x\n", (node)->guc_id); \
- __out(ebuf, "LRCA: 0x%08x\n", (node)->lrca); \
+ i915_error_printf(ebuf, "GuC-Engine-Inst-Id: 0x%08x\n", \
+ (node)->eng_inst); \
+ i915_error_printf(ebuf, "GuC-Context-Id: 0x%08x\n",
(node)->guc_id); \
+ i915_error_printf(ebuf, "LRCA: 0x%08x\n", (node)->lrca); \
} while (0)
int intel_guc_capture_print_engine_node(struct drm_i915_error_state_buf *ebuf,
@@ -1441,57 +1430,57 @@ int intel_guc_capture_print_engine_node(struct
drm_i915_error_state_buf *ebuf,
guc = >engine->gt->uc.guc;
- __out(ebuf, "global --- GuC Error Capture on %s command stream:\n",
- ee->engine->name);
+ i915_error_printf(ebuf, "global --- GuC Error Capture on %s command
stream:\n",
+ ee->engine->name);
node = ee->guc_capture_node;
if (!node) {
- __out(ebuf, " No matching ee-node\n");
+ i915_error_printf(ebuf, " No matching ee-node\n");
return 0;
}
- __out(ebuf, "Coverage: %s\n", grptype[node->is_partial]);
+ i915_error_printf(ebuf, "Coverage: %s\n", grptype[node->is_partial]);
for (i = GUC_CAPTURE_LIST_TYPE_GLOBAL; i < GUC_CAPTURE_LIST_TYPE_MAX;
++i) {
- __out(ebuf, " RegListType: %s\n",
- datatype[i % GUC_CAPTURE_LIST_TYPE_MAX]);
- __out(ebuf, "Owner-Id: %d\n", node->reginfo[i].vfid);
+ i915_error_printf(ebuf, " RegListType: %s\n",
+ datatype[i % GUC_CAPTURE_LIST_TYPE_MAX]);
+ i915_error_printf(ebuf, "Owner-Id: %d\n",
node->reginfo[i].vfid);
switch (i) {
case GUC_CAPTURE_LIST_TYPE_GLOBAL:
default:
break;
case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS:
- __out(ebuf, "GuC-Eng-Class: %d\n", node->eng_class);
- __out(ebuf, "i915-Eng-Class: %d\n",
- guc_class_to_engine_class(node->eng_class));
+ i915_error_printf(ebuf, "GuC-Eng-Class: %d\n",
node->eng_class);
+ i915_error_printf(ebuf, "i915-Eng-Class: %d\n",
+
guc_class_to_engine_class(node->eng_class));
break;
case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE:
eng = intel_guc_lookup_engine(guc, node->eng_class,
node->eng_inst);
if (eng)
GCAP_PRINT_INTEL_ENG_INFO(ebuf, eng);
else
- __out(ebuf, "i915-Eng-Lookup Fail!\n");
+
[Intel-gfx] [PATCH 0/7] Fixes and improvements to GuC logging and error capture
From: John Harrison Fix bugs and improve the usability/effectiveness of GuC logging and GuC related error captures. Signed-off-by: John Harrison Alan Previn (1): drm/i915/guc: Add a helper for log buffer size Chris Wilson (1): drm/i915/guc: Use streaming loads to speed up dumping the guc log John Harrison (5): drm/i915/guc: Fix capture size warning and bump the size drm/i915/guc: Add GuC <-> kernel time stamp translation information drm/i915/guc: Record CTB info in error logs drm/i915/guc: Make GuC log sizes runtime configurable drm/i915/guc: Reduce spam from error capture drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 + drivers/gpu/drm/i915/gt/uc/intel_guc.c| 72 +++-- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 + .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 113 .../gpu/drm/i915/gt/uc/intel_guc_capture.h| 1 - drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 253 +++--- drivers/gpu/drm/i915/gt/uc/intel_guc_log.h| 42 +-- drivers/gpu/drm/i915/i915_gpu_error.c | 67 - drivers/gpu/drm/i915/i915_gpu_error.h | 21 +- drivers/gpu/drm/i915/i915_params.c| 12 + drivers/gpu/drm/i915/i915_params.h| 3 + 11 files changed, 427 insertions(+), 161 deletions(-) -- 2.37.1
[Intel-gfx] [PATCH 5/7] drm/i915/guc: Use streaming loads to speed up dumping the guc log
From: Chris Wilson
Use a temporary page and mempy_from_wc to reduce the time it takes to
dump the guc log to debugfs.
Signed-off-by: Chris Wilson
Signed-off-by: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 24 --
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 07d31ae32f765..4722d4b18ed19 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -750,8 +750,9 @@ int intel_guc_log_dump(struct intel_guc_log *log, struct
drm_printer *p,
struct intel_guc *guc = log_to_guc(log);
struct intel_uc *uc = container_of(guc, struct intel_uc, guc);
struct drm_i915_gem_object *obj = NULL;
- u32 *map;
- int i = 0;
+ void *map;
+ u32 *page;
+ int i, j;
if (!intel_guc_is_supported(guc))
return -ENODEV;
@@ -764,23 +765,34 @@ int intel_guc_log_dump(struct intel_guc_log *log, struct
drm_printer *p,
if (!obj)
return 0;
+ page = (u32 *)__get_free_page(GFP_KERNEL);
+ if (!page)
+ return -ENOMEM;
+
intel_guc_dump_time_info(guc, p);
map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
if (IS_ERR(map)) {
DRM_DEBUG("Failed to pin object\n");
drm_puts(p, "(log data unaccessible)\n");
+ free_page((unsigned long)page);
return PTR_ERR(map);
}
- for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
- drm_printf(p, "0x%08x 0x%08x 0x%08x 0x%08x\n",
- *(map + i), *(map + i + 1),
- *(map + i + 2), *(map + i + 3));
+ for (i = 0; i < obj->base.size; i += PAGE_SIZE) {
+ if (!i915_memcpy_from_wc(page, map + i, PAGE_SIZE))
+ memcpy(page, map + i, PAGE_SIZE);
+
+ for (j = 0; j < PAGE_SIZE / sizeof(u32); j += 4)
+ drm_printf(p, "0x%08x 0x%08x 0x%08x 0x%08x\n",
+ *(page + j + 0), *(page + j + 1),
+ *(page + j + 2), *(page + j + 3));
+ }
drm_puts(p, "\n");
i915_gem_object_unpin_map(obj);
+ free_page((unsigned long)page);
return 0;
}
--
2.37.1
[Intel-gfx] [PATCH 4/7] drm/i915/guc: Record CTB info in error logs
From: John Harrison
When debugging GuC communication issues, it is useful to have the CTB
info available. So add the state and buffer contents to the error
capture log.
Also, add a sub-structure for the GuC specific error capture info as
it is now becoming numerous.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/i915_gpu_error.c | 59 +++
drivers/gpu/drm/i915/i915_gpu_error.h | 20 +++--
2 files changed, 67 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index addba75252343..543ba63f958ea 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -671,6 +671,18 @@ static void err_print_pciid(struct
drm_i915_error_state_buf *m,
pdev->subsystem_device);
}
+static void err_print_guc_ctb(struct drm_i915_error_state_buf *m,
+ const char *name,
+ const struct intel_ctb_coredump *ctb)
+{
+ if (!ctb->size)
+ return;
+
+ err_printf(m, "GuC %s CTB: raw: 0x%08X, 0x%08X/%08X, cached:
0x%08X/%08X, desc = 0x%08X, buf = 0x%08X x 0x%08X\n",
+ name, ctb->raw_status, ctb->raw_head, ctb->raw_tail,
+ ctb->head, ctb->tail, ctb->desc_offset, ctb->cmds_offset,
ctb->size);
+}
+
static void err_print_uc(struct drm_i915_error_state_buf *m,
const struct intel_uc_coredump *error_uc)
{
@@ -678,8 +690,12 @@ static void err_print_uc(struct drm_i915_error_state_buf
*m,
intel_uc_fw_dump(_uc->guc_fw, );
intel_uc_fw_dump(_uc->huc_fw, );
- err_printf(m, "GuC timestamp: 0x%08x\n", error_uc->timestamp);
- intel_gpu_error_print_vma(m, NULL, error_uc->guc_log);
+ err_printf(m, "GuC timestamp: 0x%08x\n", error_uc->guc.timestamp);
+ intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_log);
+ err_printf(m, "GuC CTB fence: %d\n", error_uc->guc.last_fence);
+ err_print_guc_ctb(m, "Send", error_uc->guc.ctb + 0);
+ err_print_guc_ctb(m, "Recv", error_uc->guc.ctb + 1);
+ intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_ctb);
}
static void err_free_sgl(struct scatterlist *sgl)
@@ -854,7 +870,7 @@ static void __err_print_to_sgl(struct
drm_i915_error_state_buf *m,
if (error->gt) {
bool print_guc_capture = false;
- if (error->gt->uc && error->gt->uc->is_guc_capture)
+ if (error->gt->uc && error->gt->uc->guc.is_guc_capture)
print_guc_capture = true;
err_print_gt_display(m, error->gt);
@@ -1009,7 +1025,8 @@ static void cleanup_uc(struct intel_uc_coredump *uc)
{
kfree(uc->guc_fw.path);
kfree(uc->huc_fw.path);
- i915_vma_coredump_free(uc->guc_log);
+ i915_vma_coredump_free(uc->guc.vma_log);
+ i915_vma_coredump_free(uc->guc.vma_ctb);
kfree(uc);
}
@@ -1658,6 +1675,23 @@ gt_record_engines(struct intel_gt_coredump *gt,
}
}
+static void gt_record_guc_ctb(struct intel_ctb_coredump *saved,
+ const struct intel_guc_ct_buffer *ctb,
+ const void *blob_ptr, struct intel_guc *guc)
+{
+ if (!ctb || !ctb->desc)
+ return;
+
+ saved->raw_status = ctb->desc->status;
+ saved->raw_head = ctb->desc->head;
+ saved->raw_tail = ctb->desc->tail;
+ saved->head = ctb->head;
+ saved->tail = ctb->tail;
+ saved->size = ctb->size;
+ saved->desc_offset = ((void *)ctb->desc) - blob_ptr;
+ saved->cmds_offset = ((void *)ctb->cmds) - blob_ptr;
+}
+
static struct intel_uc_coredump *
gt_record_uc(struct intel_gt_coredump *gt,
struct i915_vma_compress *compress)
@@ -1684,9 +1718,16 @@ gt_record_uc(struct intel_gt_coredump *gt,
* log times to system times (in conjunction with the error->boottime
and
* gt->clock_frequency fields saved elsewhere).
*/
- error_uc->timestamp = intel_uncore_read(gt->_gt->uncore,
GUCPMTIMESTAMP);
- error_uc->guc_log = create_vma_coredump(gt->_gt, uc->guc.log.vma,
- "GuC log buffer", compress);
+ error_uc->guc.timestamp = intel_uncore_read(gt->_gt->uncore,
GUCPMTIMESTAMP);
+ error_uc->guc.vma_log = create_vma_coredump(gt->_gt, uc->guc.log.vma,
+ "GuC log buffer", compress);
+ error_uc->guc.vma_ctb = create_vma_coredump(gt->_gt, uc->guc.ct.vma,
+ "GuC CT buffer", compress);
+ error_uc->guc.last_fence = uc->guc.ct.requests.last_fence;
+ gt_record_guc_ctb(error_uc->guc.ctb + 0, >guc.ct.ctbs.send,
+ uc->guc.ct.ctbs.send.desc, (struct intel_guc
*)>guc);
+ gt_record_guc_ctb(error_uc->guc.ctb + 1, >guc.ct.ctbs.recv,
+
[Intel-gfx] [PATCH 1/7] drm/i915/guc: Add a helper for log buffer size
From: Alan Previn
Add a helper to get GuC log buffer size.
Signed-off-by: Alan Previn
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 49 --
1 file changed, 27 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 25b2d7ce6640d..492bbf419d4df 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -15,6 +15,32 @@
static void guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log);
+static u32 intel_guc_log_size(struct intel_guc_log *log)
+{
+ /*
+* GuC Log buffer Layout:
+*
+* NB: Ordering must follow "enum guc_log_buffer_type".
+*
+* +===+ 00B
+* | Debug state header |
+* +---+ 32B
+* |Crash dump state header|
+* +---+ 64B
+* | Capture state header |
+* +---+ 96B
+* | |
+* +===+ PAGE_SIZE (4KB)
+* | Debug logs |
+* +===+ + DEBUG_SIZE
+* |Crash Dump logs|
+* +===+ + CRASH_SIZE
+* | Capture logs |
+* +===+ + CAPTURE_SIZE
+*/
+ return PAGE_SIZE + CRASH_BUFFER_SIZE + DEBUG_BUFFER_SIZE +
CAPTURE_BUFFER_SIZE;
+}
+
/**
* DOC: GuC firmware log
*
@@ -461,32 +487,11 @@ int intel_guc_log_create(struct intel_guc_log *log)
GEM_BUG_ON(log->vma);
- /*
-* GuC Log buffer Layout
-* (this ordering must follow "enum guc_log_buffer_type" definition)
-*
-* +===+ 00B
-* | Debug state header |
-* +---+ 32B
-* |Crash dump state header|
-* +---+ 64B
-* | Capture state header |
-* +---+ 96B
-* | |
-* +===+ PAGE_SIZE (4KB)
-* | Debug logs |
-* +===+ + DEBUG_SIZE
-* |Crash Dump logs|
-* +===+ + CRASH_SIZE
-* | Capture logs |
-* +===+ + CAPTURE_SIZE
-*/
if (intel_guc_capture_output_min_size_est(guc) > CAPTURE_BUFFER_SIZE)
DRM_WARN("GuC log buffer for state_capture maybe too small. %d
< %d\n",
CAPTURE_BUFFER_SIZE,
intel_guc_capture_output_min_size_est(guc));
- guc_log_size = PAGE_SIZE + CRASH_BUFFER_SIZE + DEBUG_BUFFER_SIZE +
- CAPTURE_BUFFER_SIZE;
+ guc_log_size = intel_guc_log_size(log);
vma = intel_guc_allocate_vma(guc, guc_log_size);
if (IS_ERR(vma)) {
--
2.37.1
Re: [Intel-gfx] [PATCH] drm/i915/guc: Don't send policy update for child contexts.
On 7/27/2022 18:50, Ceraolo Spurio, Daniele wrote:
On 7/27/2022 6:44 PM, John Harrison wrote:
On 7/27/2022 17:33, Daniele Ceraolo Spurio wrote:
The GuC FW applies the parent context policy to all the children,
so individual updates to the children are not supported and we
should not send them.
Note that sending the message did not have any functional consequences,
because the GuC just drops it and logs an error; since we were trying
to set the child policy to match the parent anyway the message being
dropped was not a problem.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Needs a Fixes tag for the original v70 update patch?
I don't think so. I added the explanation about it not being a
functional issue to make it clear that everything still works as
expected without this patch, just with a bit of extra noise in the GuC
logs. If you think it is still worth applying to older kernels I'll
add the tag in.
Daniele
Hmm. It is strictly speaking a bug fix. But yes, the only impact is
extra H2G traffic on context registration and in the GuC log. So maybe
not worth worrying about.
Reviewed-by: John Harrison
John.
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 26
+--
1 file changed, 1 insertion(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 76916aed897a..5e31e2540297 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2420,7 +2420,6 @@ static int guc_context_policy_init_v70(struct
intel_context *ce, bool loop)
struct context_policy policy;
u32 execution_quantum;
u32 preemption_timeout;
- bool missing = false;
unsigned long flags;
int ret;
@@ -2438,32 +2437,9 @@ static int
guc_context_policy_init_v70(struct intel_context *ce, bool loop)
__guc_context_policy_add_preempt_to_idle(, 1);
ret = __guc_context_set_context_policies(guc, , loop);
- missing = ret != 0;
-
- if (!missing && intel_context_is_parent(ce)) {
- struct intel_context *child;
-
- for_each_child(ce, child) {
- __guc_context_policy_start_klv(, child->guc_id.id);
-
- if (engine->flags & I915_ENGINE_WANT_FORCED_PREEMPTION)
- __guc_context_policy_add_preempt_to_idle(, 1);
-
- child->guc_state.prio = ce->guc_state.prio;
- __guc_context_policy_add_priority(,
ce->guc_state.prio);
- __guc_context_policy_add_execution_quantum(,
execution_quantum);
- __guc_context_policy_add_preemption_timeout(,
preemption_timeout);
-
- ret = __guc_context_set_context_policies(guc, ,
loop);
- if (ret) {
- missing = true;
- break;
- }
- }
- }
spin_lock_irqsave(>guc_state.lock, flags);
- if (missing)
+ if (ret != 0)
set_context_policy_required(ce);
else
clr_context_policy_required(ce);
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Initial Meteorlake Support
== Series Details == Series: Initial Meteorlake Support URL : https://patchwork.freedesktop.org/series/106786/ State : failure == Summary == Error: make failed CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/i915_driver.o drivers/gpu/drm/i915/i915_driver.c: In function ‘i915_driver_probe’: drivers/gpu/drm/i915/i915_driver.c:929:7: error: ‘match_info’ undeclared (first use in this function); did you mean ‘mtd_info’? !match_info->has_gmd_id && DISPLAY_VER(i915) < 5) ^~ mtd_info drivers/gpu/drm/i915/i915_driver.c:929:7: note: each undeclared identifier is reported only once for each function it appears in scripts/Makefile.build:249: recipe for target 'drivers/gpu/drm/i915/i915_driver.o' failed make[4]: *** [drivers/gpu/drm/i915/i915_driver.o] Error 1 scripts/Makefile.build:466: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:466: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:466: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1843: recipe for target 'drivers' failed make: *** [drivers] Error 2
Re: [Intel-gfx] [PATCH] drm/i915/guc: Don't send policy update for child contexts.
On 7/27/2022 6:44 PM, John Harrison wrote:
On 7/27/2022 17:33, Daniele Ceraolo Spurio wrote:
The GuC FW applies the parent context policy to all the children,
so individual updates to the children are not supported and we
should not send them.
Note that sending the message did not have any functional consequences,
because the GuC just drops it and logs an error; since we were trying
to set the child policy to match the parent anyway the message being
dropped was not a problem.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Needs a Fixes tag for the original v70 update patch?
I don't think so. I added the explanation about it not being a
functional issue to make it clear that everything still works as
expected without this patch, just with a bit of extra noise in the GuC
logs. If you think it is still worth applying to older kernels I'll add
the tag in.
Daniele
John.
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 26 +--
1 file changed, 1 insertion(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 76916aed897a..5e31e2540297 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2420,7 +2420,6 @@ static int guc_context_policy_init_v70(struct
intel_context *ce, bool loop)
struct context_policy policy;
u32 execution_quantum;
u32 preemption_timeout;
- bool missing = false;
unsigned long flags;
int ret;
@@ -2438,32 +2437,9 @@ static int
guc_context_policy_init_v70(struct intel_context *ce, bool loop)
__guc_context_policy_add_preempt_to_idle(, 1);
ret = __guc_context_set_context_policies(guc, , loop);
- missing = ret != 0;
-
- if (!missing && intel_context_is_parent(ce)) {
- struct intel_context *child;
-
- for_each_child(ce, child) {
- __guc_context_policy_start_klv(, child->guc_id.id);
-
- if (engine->flags & I915_ENGINE_WANT_FORCED_PREEMPTION)
- __guc_context_policy_add_preempt_to_idle(, 1);
-
- child->guc_state.prio = ce->guc_state.prio;
- __guc_context_policy_add_priority(,
ce->guc_state.prio);
- __guc_context_policy_add_execution_quantum(,
execution_quantum);
- __guc_context_policy_add_preemption_timeout(,
preemption_timeout);
-
- ret = __guc_context_set_context_policies(guc, ,
loop);
- if (ret) {
- missing = true;
- break;
- }
- }
- }
spin_lock_irqsave(>guc_state.lock, flags);
- if (missing)
+ if (ret != 0)
set_context_policy_required(ce);
else
clr_context_policy_required(ce);
Re: [Intel-gfx] [PATCH] drm/i915/guc: Don't send policy update for child contexts.
On 7/27/2022 17:33, Daniele Ceraolo Spurio wrote:
The GuC FW applies the parent context policy to all the children,
so individual updates to the children are not supported and we
should not send them.
Note that sending the message did not have any functional consequences,
because the GuC just drops it and logs an error; since we were trying
to set the child policy to match the parent anyway the message being
dropped was not a problem.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Needs a Fixes tag for the original v70 update patch?
John.
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 26 +--
1 file changed, 1 insertion(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 76916aed897a..5e31e2540297 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2420,7 +2420,6 @@ static int guc_context_policy_init_v70(struct
intel_context *ce, bool loop)
struct context_policy policy;
u32 execution_quantum;
u32 preemption_timeout;
- bool missing = false;
unsigned long flags;
int ret;
@@ -2438,32 +2437,9 @@ static int guc_context_policy_init_v70(struct intel_context *ce, bool loop)
__guc_context_policy_add_preempt_to_idle(, 1);
ret = __guc_context_set_context_policies(guc, , loop);
- missing = ret != 0;
-
- if (!missing && intel_context_is_parent(ce)) {
- struct intel_context *child;
-
- for_each_child(ce, child) {
- __guc_context_policy_start_klv(,
child->guc_id.id);
-
- if (engine->flags & I915_ENGINE_WANT_FORCED_PREEMPTION)
-
__guc_context_policy_add_preempt_to_idle(, 1);
-
- child->guc_state.prio = ce->guc_state.prio;
- __guc_context_policy_add_priority(,
ce->guc_state.prio);
- __guc_context_policy_add_execution_quantum(,
execution_quantum);
- __guc_context_policy_add_preemption_timeout(,
preemption_timeout);
-
- ret = __guc_context_set_context_policies(guc, ,
loop);
- if (ret) {
- missing = true;
- break;
- }
- }
- }
spin_lock_irqsave(>guc_state.lock, flags);
- if (missing)
+ if (ret != 0)
set_context_policy_required(ce);
else
clr_context_policy_required(ce);
Re: [Intel-gfx] [PATCH] drm/i915/guc: Cancel GuC engine busyness worker synchronously
On 7/26/2022 13:51, Nerlige Ramappa, Umesh wrote:
The worker is canceled in gt_park path, but earlier it was assumed that
gt_park path cannot sleep and the cancel is asynchronous. This caused a
race with suspend flow where the worker runs after suspend and causes an
unclaimed register access warning. Cancel the worker synchronously since
the gt_park is indeed allowed to sleep.
Signed-off-by: Umesh Nerlige Ramappa
Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
pmu")
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 76916aed897a..0b7a5ecb640a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1438,7 +1438,12 @@ void intel_guc_busyness_park(struct intel_gt *gt)
if (!guc_submission_initialized(guc))
return;
- cancel_delayed_work(>timestamp.work);
+ /*
+* There is a race with suspend flow where the worker runs after suspend
+* and causes an unclaimed register access warning. Cancel the worker
+* synchronously here.
+*/
+ cancel_delayed_work_sync(>timestamp.work);
/*
* Before parking, we should sample engine busyness stats if we need to.
[Intel-gfx] [PATCH 07/23] drm/i915/mtl: Add gmbus and gpio support
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
>From spec we have registers GPIO_CTL[1-5] mapped to combo phys and
GPIO_CTL[9-14] are mapped to TC ports.
BSpec: 49306
Original Author: Brian J Lovin
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_gmbus.c | 17 +
drivers/gpu/drm/i915/display/intel_gmbus.h | 1 +
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index a6ba7fb72339..542b8b2654be 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -116,6 +116,20 @@ static const struct gmbus_pin gmbus_pins_dg2[] = {
[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
};
+static const struct gmbus_pin gmbus_pins_mtp[] = {
+ [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+ [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+ [GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
+ [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+ [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
+ [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
+ [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
+ [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
+ [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
+};
+
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
unsigned int pin)
{
@@ -128,6 +142,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct
drm_i915_private *i915,
} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
pins = gmbus_pins_dg1;
size = ARRAY_SIZE(gmbus_pins_dg1);
+ } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) {
+ pins = gmbus_pins_mtp;
+ size = ARRAY_SIZE(gmbus_pins_mtp);
} else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
pins = gmbus_pins_icp;
size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h
b/drivers/gpu/drm/i915/display/intel_gmbus.h
index 8edc2e99cf53..20f704bd4e70 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.h
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
@@ -24,6 +24,7 @@ struct i2c_adapter;
#define GMBUS_PIN_2_BXT2
#define GMBUS_PIN_3_BXT3
#define GMBUS_PIN_4_CNP4
+#define GMBUS_PIN_5_MTP5
#define GMBUS_PIN_9_TC1_ICP9
#define GMBUS_PIN_10_TC2_ICP 10
#define GMBUS_PIN_11_TC3_ICP 11
--
2.25.1
[Intel-gfx] [PATCH 18/23] drm/i915/mtl: DBUF handling is same as adlp
Meteorlake uses a similar DBUF programming as ADL-P. Reuse the call flow for meteorlake. Bspec: 49255 Cc: Matt Roper Original Author: Caz Yokoyama Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 58a3c72418a7..d73be4bbaaa3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4934,7 +4934,7 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool if (IS_DG2(dev_priv)) return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus); - else if (IS_ALDERLAKE_P(dev_priv)) + else if (DISPLAY_VER(dev_priv) >= 14 || IS_ALDERLAKE_P(dev_priv)) return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus); else if (DISPLAY_VER(dev_priv) == 12) return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus); -- 2.25.1
[Intel-gfx] [PATCH 22/23] drm/i915/mtl: Update CHICKEN_TRANS* register addresses
From: Madhumitha Tolakanahalli Pradeep
In Display version 14, Transcoder Chicken Registers are moved from DPRZ to DRPOS
to reduce register signal crossings for Unit Interface Optimization.
This patch modifies the CHICKEN_TRANS macro to add a DISPLAY_VER check for
calculating the correct platform offsets.
(And also updates existing CHICKEN_TRANS occurrences to the new definition)
Bspec: 34387, 50054
Signed-off-by: Madhumitha Tolakanahalli Pradeep
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 7 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 6 +++--
drivers/gpu/drm/i915/i915_reg.h | 25 +++-
5 files changed, 29 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index a4c8493f3ce7..26c99bfa5ec6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2854,7 +2854,7 @@ gen9_chicken_trans_reg_by_port(struct drm_i915_private
*dev_priv,
if (drm_WARN_ON(_priv->drm, port < PORT_A || port > PORT_E))
port = PORT_A;
- return CHICKEN_TRANS(trans[port]);
+ return CHICKEN_TRANS(dev_priv, trans[port]);
}
static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index bf170bd83ef7..9e6809d11b02 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -620,7 +620,7 @@ void intel_disable_transcoder(const struct intel_crtc_state
*old_crtc_state)
val &= ~PIPECONF_ENABLE;
if (DISPLAY_VER(dev_priv) >= 12)
- intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
+ intel_de_rmw(dev_priv, CHICKEN_TRANS(dev_priv, cpu_transcoder),
FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
intel_de_write(dev_priv, reg, val);
@@ -1839,7 +1839,7 @@ static void hsw_set_frame_start_delay(const struct
intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
+ i915_reg_t reg = CHICKEN_TRANS(dev_priv, crtc_state->cpu_transcoder);
u32 val;
val = intel_de_read(dev_priv, reg);
@@ -4127,7 +4127,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
}
if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
- tmp = intel_de_read(dev_priv,
CHICKEN_TRANS(pipe_config->cpu_transcoder));
+ tmp = intel_de_read(dev_priv,
+ CHICKEN_TRANS(dev_priv,
pipe_config->cpu_transcoder));
pipe_config->framestart_delay =
REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 14d2a64193b2..9c2c032c051c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -591,7 +591,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state
*state,
drm_dp_update_payload_part2(_dp->mst_mgr);
if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
- intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0,
+ intel_de_rmw(dev_priv, CHICKEN_TRANS(dev_priv, trans), 0,
FECSTALL_DIS_DPTSTREAM_DPTTG);
intel_enable_transcoder(pipe_config);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 98c3c8015a5c..532d5592c61e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1139,7 +1139,8 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
if (intel_dp->psr.psr2_enabled) {
if (DISPLAY_VER(dev_priv) == 9)
- intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
+ intel_de_rmw(dev_priv,
+CHICKEN_TRANS(dev_priv, cpu_transcoder), 0,
PSR2_VSC_ENABLE_PROG_HEADER |
PSR2_ADD_VERTICAL_LINE_COUNT);
@@ -1149,7 +1150,8 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
* cause issues if non-supported panels are used.
*/
if (IS_ALDERLAKE_P(dev_priv))
- intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
+ intel_de_rmw(dev_priv,
+CHICKEN_TRANS(dev_priv, cpu_transcoder), 0,
[Intel-gfx] [PATCH 13/23] drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM
Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers
instead of GT driver mailbox.
Bspec: 64608
Cc: Matt Roper
Original Author: Caz Yokoyama
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++
drivers/gpu/drm/i915/intel_pm.c | 105 +++-
2 files changed, 71 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6087d40eed70..23b50d671550 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8754,4 +8754,11 @@ enum skl_power_gate {
#define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC)
#define MTL_MEDIA_GSI_BASE 0x38
+
+#define MTL_LATENCY_LP0_LP1_MMIO(0x45780)
+#define MTL_LATENCY_LP2_LP3_MMIO(0x45784)
+#define MTL_LATENCY_LP4_LP5_MMIO(0x45788)
+#define MTL_LATENCY_LEVEL0_2_4_MASK REG_GENMASK(12, 0)
+#define MTL_LATENCY_LEVEL1_3_5_MASK REG_GENMASK(28, 16)
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ef7553b494ea..fac565d23d57 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2861,16 +2861,75 @@ static void ilk_compute_wm_level(const struct
drm_i915_private *dev_priv,
result->enable = true;
}
+static void
+adjust_wm_latency(u16 wm[], int max_level, int read_latency,
+ bool wm_lv_0_adjust_needed)
+{
+ int i, level;
+
+ /*
+* If a level n (n > 1) has a 0us latency, all levels m (m >= n)
+* need to be disabled. We make sure to sanitize the values out
+* of the punit to satisfy this requirement.
+*/
+ for (level = 1; level <= max_level; level++) {
+ if (wm[level] == 0) {
+ for (i = level + 1; i <= max_level; i++)
+ wm[i] = 0;
+
+ max_level = level - 1;
+ break;
+ }
+ }
+
+ /*
+* WaWmMemoryReadLatency
+*
+* punit doesn't take into account the read latency so we need
+* to add proper adjustement to each valid level we retrieve
+* from the punit when level 0 response data is 0us.
+*/
+ if (wm[0] == 0) {
+ for (level = 0; level <= max_level; level++)
+ wm[level] += read_latency;
+ }
+
+ /*
+* WA Level-0 adjustment for 16GB DIMMs: SKL+
+* If we could not get dimm info enable this WA to prevent from
+* any underrun. If not able to get Dimm info assume 16GB dimm
+* to avoid any underrun.
+*/
+ if (wm_lv_0_adjust_needed)
+ wm[0] += 1;
+}
+
static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
u16 wm[])
{
struct intel_uncore *uncore = _priv->uncore;
+ int max_level = ilk_wm_max_level(dev_priv);
- if (DISPLAY_VER(dev_priv) >= 9) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
u32 val;
- int ret, i;
- int level, max_level = ilk_wm_max_level(dev_priv);
+
+ val = intel_uncore_read(uncore, MTL_LATENCY_LP0_LP1);
+ wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val);
+ wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val);
+ val = intel_uncore_read(uncore, MTL_LATENCY_LP2_LP3);
+ wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val);
+ wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val);
+ val = intel_uncore_read(uncore, MTL_LATENCY_LP4_LP5);
+ wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val);
+ wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val);
+
+ adjust_wm_latency(wm, max_level, 6,
+ dev_priv->dram_info.wm_lv_0_adjust_needed);
+ } else if (DISPLAY_VER(dev_priv) >= 9) {
+ int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
int mult = IS_DG2(dev_priv) ? 2 : 1;
+ u32 val;
+ int ret;
/* read the first set of memory latencies[0:3] */
val = 0; /* data0 to be programmed to 0 for first set */
@@ -2909,44 +2968,8 @@ static void intel_read_wm_latency(struct
drm_i915_private *dev_priv,
wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
- /*
-* If a level n (n > 1) has a 0us latency, all levels m (m >= n)
-* need to be disabled. We make sure to sanitize the values out
-* of the punit to satisfy this requirement.
-*/
- for (level = 1; level <= max_level; level++) {
- if (wm[level] == 0) {
- for (i =
[Intel-gfx] [PATCH 09/23] drm/i915/mtl: Add support for MTL in Display Init sequences
The initialization sequence for Meteorlake reuses the sequence for icelake for most parts. Some changes viz. reset PICA handshake are added. Bspec: 49189 Cc: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h| 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 589af257edeb..ccc3f78b1607 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1381,6 +1381,9 @@ static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, reset_bits = RESET_PCH_HANDSHAKE_ENABLE; } + if (DISPLAY_VER(dev_priv) >= 14) + reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN; + val = intel_de_read(dev_priv, reg); if (enable) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 50ddc5ba72b9..baf747adf1db 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5926,7 +5926,8 @@ _BW_BUDDY1_PAGE_MASK)) #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) -#define RESET_PCH_HANDSHAKE_ENABLE(1 << 4) +#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) +#define RESET_PCH_HANDSHAKE_ENABLEREG_BIT(4) #define GEN8_CHICKEN_DCPR_1_MMIO(0x46430) #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) -- 2.25.1
[Intel-gfx] [PATCH 02/23] drm/i915: Parse and set stepping for platforms with GMD
From: José Roberto de Souza
The GMD step field do not properly match the current stepping convention
that we use(STEP_A0, STEP_A1, STEP_B0...).
One platform could have { arch = 12, rel = 70, step = 1 } and the
actual stepping is STEP_B0 but without the translation of the step
field would mean STEP_A1.
That is why we will need to have gmd_to_intel_step tables for each IP.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_step.c | 60 +++
1 file changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 42b3133d8387..0fa7147c7d0f 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -135,6 +135,48 @@ static const struct intel_step_info adlp_n_revids[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
};
+struct gmd_to_intel_step {
+ struct ip_version gmd;
+ enum intel_step step;
+};
+
+static const struct gmd_to_intel_step gmd_graphics_table[] = {
+ { .gmd.ver = 12, .gmd.rel = 70, .gmd.step = 0, .step = STEP_A0 },
+ { .gmd.ver = 12, .gmd.rel = 70, .gmd.step = 4, .step = STEP_B0 },
+ { .gmd.ver = 12, .gmd.rel = 71, .gmd.step = 0, .step = STEP_A0 },
+ { .gmd.ver = 12, .gmd.rel = 71, .gmd.step = 4, .step = STEP_B0 },
+ { .gmd.ver = 12, .gmd.rel = 73, .gmd.step = 0, .step = STEP_A0 },
+ { .gmd.ver = 12, .gmd.rel = 73, .gmd.step = 4, .step = STEP_B0 },
+};
+
+static const struct gmd_to_intel_step gmd_media_table[] = {
+ { .gmd.ver = 13, .gmd.rel = 70, .gmd.step = 0, .step = STEP_A0 },
+ { .gmd.ver = 13, .gmd.rel = 70, .gmd.step = 4, .step = STEP_B0 },
+};
+
+static const struct gmd_to_intel_step gmd_display_table[] = {
+ { .gmd.ver = 14, .gmd.rel = 0, .gmd.step = 0, .step = STEP_A0 },
+ { .gmd.ver = 14, .gmd.rel = 0, .gmd.step = 4, .step = STEP_B0 },
+};
+
+static u8 gmd_to_intel_step(struct drm_i915_private *i915,
+ struct ip_version *gmd,
+ const struct gmd_to_intel_step *table,
+ int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (table[i].gmd.ver == gmd->ver &&
+ table[i].gmd.rel == gmd->rel &&
+ table[i].gmd.step == gmd->step)
+ return table[i].step;
+ }
+
+ drm_dbg(>drm, "Using future steppings\n");
+ return STEP_FUTURE;
+}
+
static void pvc_step_init(struct drm_i915_private *i915, int pci_revid);
void intel_step_init(struct drm_i915_private *i915)
@@ -144,6 +186,24 @@ void intel_step_init(struct drm_i915_private *i915)
int revid = INTEL_REVID(i915);
struct intel_step_info step = {};
+ if (HAS_GMD_ID(i915)) {
+ step.graphics_step = gmd_to_intel_step(i915,
+
_INFO(i915)->graphics,
+ gmd_graphics_table,
+
ARRAY_SIZE(gmd_graphics_table));
+ step.media_step = gmd_to_intel_step(i915,
+ _INFO(i915)->media,
+ gmd_media_table,
+
ARRAY_SIZE(gmd_media_table));
+ step.display_step = gmd_to_intel_step(i915,
+
_INFO(i915)->display,
+ gmd_display_table,
+
ARRAY_SIZE(gmd_display_table));
+ RUNTIME_INFO(i915)->step = step;
+
+ return;
+ }
+
if (IS_PONTEVECCHIO(i915)) {
pvc_step_init(i915, revid);
return;
--
2.25.1
[Intel-gfx] [PATCH 20/23] drm/i915/dmc: Load DMC on MTL
From: Madhumitha Tolakanahalli Pradeep
Adding support to load DMC v2.08 on MTL.
Signed-off-by: Madhumitha Tolakanahalli Pradeep
---
drivers/gpu/drm/i915/display/intel_dmc.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index fa9ef591b885..9c4f442fa407 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -52,6 +52,11 @@
#define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define MTL_DMC_PATH DMC_PATH(mtl, 2, 08)
+#define MTL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8)
+#define MTL_DMC_MAX_FW_SIZE0x1
+MODULE_FIRMWARE(MTL_DMC_PATH);
+
#define DG2_DMC_PATH DMC_PATH(dg2, 2, 06)
#define DG2_DMC_VERSION_REQUIRED DMC_VERSION(2, 06)
MODULE_FIRMWARE(DG2_DMC_PATH);
@@ -827,7 +832,11 @@ void intel_dmc_ucode_init(struct drm_i915_private
*dev_priv)
*/
intel_dmc_runtime_pm_get(dev_priv);
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ dmc->fw_path = MTL_DMC_PATH;
+ dmc->required_version = MTL_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = MTL_DMC_MAX_FW_SIZE;
+ } else if (IS_DG2(dev_priv)) {
dmc->fw_path = DG2_DMC_PATH;
dmc->required_version = DG2_DMC_VERSION_REQUIRED;
dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
--
2.25.1
[Intel-gfx] [PATCH 08/23] drm/i915/mtl: Add VBT port and AUX_CH mapping
From: Imre Deak
Add the proper VBT port,AUX_CH -> i915 port,AUX_CH mapping which just
follows the ADL_P one.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_bios.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 51dde5bfd956..2971505bcf2a 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2418,7 +2418,7 @@ static enum port dvo_port_to_port(struct drm_i915_private
*i915,
[PORT_TC4] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },
};
- if (DISPLAY_VER(i915) == 13)
+ if (DISPLAY_VER(i915) >= 13)
return __dvo_port_to_port(ARRAY_SIZE(xelpd_port_mapping),
ARRAY_SIZE(xelpd_port_mapping[0]),
xelpd_port_mapping,
@@ -3576,7 +3576,7 @@ enum aux_ch intel_bios_port_aux_ch(struct
drm_i915_private *i915,
aux_ch = AUX_CH_C;
break;
case DP_AUX_D:
- if (DISPLAY_VER(i915) == 13)
+ if (DISPLAY_VER(i915) >= 13)
aux_ch = AUX_CH_D_XELPD;
else if (IS_ALDERLAKE_S(i915))
aux_ch = AUX_CH_USBC3;
@@ -3586,7 +3586,7 @@ enum aux_ch intel_bios_port_aux_ch(struct
drm_i915_private *i915,
aux_ch = AUX_CH_D;
break;
case DP_AUX_E:
- if (DISPLAY_VER(i915) == 13)
+ if (DISPLAY_VER(i915) >= 13)
aux_ch = AUX_CH_E_XELPD;
else if (IS_ALDERLAKE_S(i915))
aux_ch = AUX_CH_USBC4;
@@ -3594,25 +3594,25 @@ enum aux_ch intel_bios_port_aux_ch(struct
drm_i915_private *i915,
aux_ch = AUX_CH_E;
break;
case DP_AUX_F:
- if (DISPLAY_VER(i915) == 13)
+ if (DISPLAY_VER(i915) >= 13)
aux_ch = AUX_CH_USBC1;
else
aux_ch = AUX_CH_F;
break;
case DP_AUX_G:
- if (DISPLAY_VER(i915) == 13)
+ if (DISPLAY_VER(i915) >= 13)
aux_ch = AUX_CH_USBC2;
else
aux_ch = AUX_CH_G;
break;
case DP_AUX_H:
- if (DISPLAY_VER(i915) == 13)
+ if (DISPLAY_VER(i915) >= 13)
aux_ch = AUX_CH_USBC3;
else
aux_ch = AUX_CH_H;
break;
case DP_AUX_I:
- if (DISPLAY_VER(i915) == 13)
+ if (DISPLAY_VER(i915) >= 13)
aux_ch = AUX_CH_USBC4;
else
aux_ch = AUX_CH_I;
--
2.25.1
[Intel-gfx] [PATCH 00/23] Initial Meteorlake Support
The PCI Id's and platform definition are posted earlier. This series adds handful of early enablement patches including support for display power wells, VBT and AUX Channel mapping, PCH and gmbus support, dbus, mbus, sagv and memory bandwidth support. This series also add the support for a new way to read Graphics, Media and Display versions. Anusha Srivatsa (2): drm/i915/mtl: Add CDCLK Support drm/i915/dmc: MTL DMC debugfs entries Clint Taylor (1): drm/i915/mtl: Fix rawclk for Meteorlake PCH Imre Deak (3): drm/i915/mtl: Add VBT port and AUX_CH mapping drm/i915/mtl: Add display power wells drm/i915/mtl: Add DP AUX support on TypeC ports José Roberto de Souza (2): drm/i915: Parse and set stepping for platforms with GMD drm/i915/display/mtl: Extend MBUS programming Madhumitha Tolakanahalli Pradeep (2): drm/i915/dmc: Load DMC on MTL drm/i915/mtl: Update CHICKEN_TRANS* register addresses Matt Roper (4): drm/i915: Read graphics/media/display arch version from hw drm/i915/mtl: MMIO range is now 4MB drm/i915/mtl: Don't mask off CCS according to DSS fusing drm/i915/mtl: Define engine context layouts Radhakrishna Sripada (9): drm/i915/mtl: Add PCH support drm/i915/mtl: Add gmbus and gpio support drm/i915/mtl: Add support for MTL in Display Init sequences drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox drm/i915/mtl: Update memory bandwidth parameters drm/i915/mtl: Update MBUS_DBOX credits drm/i915/mtl: DBUF handling is same as adlp drm/i915/mtl: Do not update GV point, mask value drivers/gpu/drm/i915/display/intel_bios.c | 14 +- drivers/gpu/drm/i915/display/intel_bw.c | 87 - drivers/gpu/drm/i915/display/intel_bw.h | 9 + drivers/gpu/drm/i915/display/intel_cdclk.c| 351 -- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 7 +- .../drm/i915/display/intel_display_power.c| 5 +- .../i915/display/intel_display_power_map.c| 115 +- .../i915/display/intel_display_power_well.c | 43 +++ .../i915/display/intel_display_power_well.h | 4 + drivers/gpu/drm/i915/display/intel_dmc.c | 19 +- drivers/gpu/drm/i915/display/intel_dp_aux.c | 53 ++- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- drivers/gpu/drm/i915/display/intel_gmbus.c| 17 + drivers/gpu/drm/i915/display/intel_gmbus.h| 1 + drivers/gpu/drm/i915/display/intel_psr.c | 6 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 + drivers/gpu/drm/i915/gt/intel_lrc.c | 47 ++- drivers/gpu/drm/i915/i915_driver.c| 85 - drivers/gpu/drm/i915/i915_drv.h | 18 +- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 91 - drivers/gpu/drm/i915/intel_device_info.c | 32 +- drivers/gpu/drm/i915/intel_device_info.h | 14 + drivers/gpu/drm/i915/intel_dram.c | 41 +- drivers/gpu/drm/i915/intel_pch.c | 9 +- drivers/gpu/drm/i915/intel_pch.h | 4 + drivers/gpu/drm/i915/intel_pm.c | 180 ++--- drivers/gpu/drm/i915/intel_step.c | 60 +++ drivers/gpu/drm/i915/intel_uncore.c | 11 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 1 + 32 files changed, 1178 insertions(+), 155 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH 10/23] drm/i915/mtl: Add display power wells
From: Imre Deak
Add support for display power wells on MTL. The differences from D13:
- The AUX HW block is moved to the PICA block, where the registers are on
an always-on power well and the functionality needs to be powered on/off
via the AUX_CH_CTL register: [1], [2]
- The DDI IO power on/off programming sequence is moved to the PHY PLL
enable/disable sequence. [3], [4], [5]
Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450
Signed-off-by: Imre Deak
---
.../i915/display/intel_display_power_map.c| 115 +-
.../i915/display/intel_display_power_well.c | 43 +++
.../i915/display/intel_display_power_well.h | 4 +
drivers/gpu/drm/i915/display/intel_dp_aux.c | 8 ++
drivers/gpu/drm/i915/i915_reg.h | 30 +
5 files changed, 199 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 97b367f39f35..cd28976f8076 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1350,6 +1350,117 @@ static const struct i915_power_well_desc_list
xelpd_power_wells[] = {
I915_PW_DESCRIPTORS(xelpd_power_wells_main),
};
+/*
+ * MTL is based on XELPD power domains with the exception of power gating for:
+ * - DDI_IO (moved to PLL logic)
+ * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA
always-on)
+ */
+#define XELPDP_PW_2_POWER_DOMAINS \
+ XELPD_PW_B_POWER_DOMAINS, \
+ XELPD_PW_C_POWER_DOMAINS, \
+ XELPD_PW_D_POWER_DOMAINS, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC3, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC4
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2,
+ XELPDP_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
+ XELPDP_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1,
+ POWER_DOMAIN_AUX_USBC1,
+ POWER_DOMAIN_AUX_TBT1);
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2,
+ POWER_DOMAIN_AUX_USBC2,
+ POWER_DOMAIN_AUX_TBT2);
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3,
+ POWER_DOMAIN_AUX_USBC3,
+ POWER_DOMAIN_AUX_TBT3);
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4,
+ POWER_DOMAIN_AUX_USBC4,
+ POWER_DOMAIN_AUX_TBT4);
+
+static const struct i915_power_well_desc xelpdp_power_wells_main[] = {
+ {
+ .instances = _PW_INSTANCES(
+ I915_PW("DC_off", _pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
+ .ops = _dc_off_power_well_ops,
+ }, {
+ .instances = _PW_INSTANCES(
+ I915_PW("PW_2", _pwdoms_pw_2,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
+ .ops = _power_well_ops,
+ .has_vga = true,
+ .has_fuses = true,
+ }, {
+ .instances = _PW_INSTANCES(
+ I915_PW("PW_A", _pwdoms_pw_a,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_A),
+ ),
+ .ops = _power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_A),
+ .has_fuses = true,
+ }, {
+ .instances = _PW_INSTANCES(
+ I915_PW("PW_B", _pwdoms_pw_b,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_B),
+ ),
+ .ops = _power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_B),
+ .has_fuses = true,
+ }, {
+ .instances = _PW_INSTANCES(
+ I915_PW("PW_C", _pwdoms_pw_c,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_C),
+ ),
+ .ops = _power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_C),
+ .has_fuses = true,
+ }, {
+ .instances = _PW_INSTANCES(
+ I915_PW("PW_D", _pwdoms_pw_d,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_D),
+ ),
+ .ops = _power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_D),
+ .has_fuses = true,
+ }, {
+ .instances = _PW_INSTANCES(
+ I915_PW("AUX_A", _pwdoms_aux_a, .xelpdp.aux_ch =
AUX_CH_A),
+ I915_PW("AUX_B", _pwdoms_aux_b, .xelpdp.aux_ch =
AUX_CH_B),
+ I915_PW("AUX_TC1", _pwdoms_aux_tc1,
.xelpdp.aux_ch = AUX_CH_USBC1),
+ I915_PW("AUX_TC2", _pwdoms_aux_tc2,
.xelpdp.aux_ch = AUX_CH_USBC2),
+
[Intel-gfx] [PATCH 23/23] drm/i915/mtl: Do not update GV point, mask value
No need to update mask value/restrict because
"Pcode only wants to use GV bandwidth value, not the mask value."
for Display version greater than 14.
Bspec: 646365
Cc: Matt Roper
Original Author: Caz Yokoyama
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d73be4bbaaa3..c9250d849e35 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3924,6 +3924,14 @@ void intel_sagv_pre_plane_update(struct
intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
+ /*
+* No need to update mask value/restrict because
+* "Pcode only wants to use GV bandwidth value, not the mask value."
+* for DISPLAY_VER() >= 14.
+*/
+ if (DISPLAY_VER(i915) >= 14)
+ return;
+
/*
* Just return if we can't control SAGV or don't have it.
* This is different from situation when we have SAGV but just can't
@@ -3944,6 +3952,16 @@ void intel_sagv_post_plane_update(struct
intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
+ /*
+* No need to update mask value/restrict because
+* "Pcode only wants to use GV bandwidth value, not the mask value."
+* for DISPLAY_VER() >= 14.
+*
+* GV bandwidth will be set by intel_pmdemand_post_plane_update()
+*/
+ if (DISPLAY_VER(i915) >= 14)
+ return;
+
/*
* Just return if we can't control SAGV or don't have it.
* This is different from situation when we have SAGV but just can't
--
2.25.1
[Intel-gfx] [PATCH 01/23] drm/i915: Read graphics/media/display arch version from hw
From: Matt Roper
Going forward, the hardware teams no longer consider new platforms to
have a "generation" in the way we've defined it for past platforms.
Instead, each IP block (graphics, media, display) will have their own
architecture major.minor versions and stepping ID's which should be read
directly from a register in the MMIO space. New hardware programming
styles, features, and workarounds should be conditional solely on the
architecture version, and should no longer be derived from the PCI
device ID, revision ID, or platform-specific feature flags.
Bspec: 63361, 64111
Signed-off-by: Matt Roper
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +
drivers/gpu/drm/i915/i915_driver.c| 85 ++-
drivers/gpu/drm/i915/i915_drv.h | 16 ++--
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_device_info.c | 32 +++
drivers/gpu/drm/i915/intel_device_info.h | 14 +++
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
8 files changed, 131 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 60d6eb5f245b..fab8e4ff74d5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -39,6 +39,8 @@
#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)
+#define GMD_ID_GRAPHICS_MMIO(0xd8c)
+
#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
#define SF_MCR_SELECTOR_MMIO(0xfd8)
#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index deb8a8b76965..057ed966bd8e 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -70,6 +70,7 @@
#include "gem/i915_gem_pm.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
+#include "gt/intel_gt_regs.h"
#include "gt/intel_rc6.h"
#include "pxp/intel_pxp_pm.h"
@@ -306,17 +307,86 @@ static void sanitize_gpu(struct drm_i915_private *i915)
__intel_gt_reset(to_gt(i915), ALL_ENGINES);
}
+#define IP_VER_READ(offset, ri_prefix) \
+ addr = pci_iomap_range(pdev, 0, offset, sizeof(u32)); \
+ if (drm_WARN_ON(>drm, !addr)) { \
+ /* Fall back to whatever was in the device info */ \
+ RUNTIME_INFO(i915)->ri_prefix.ver =
INTEL_INFO(i915)->ri_prefix.ver; \
+ RUNTIME_INFO(i915)->ri_prefix.rel =
INTEL_INFO(i915)->ri_prefix.rel; \
+ goto ri_prefix##done; \
+ } \
+ \
+ ver = ioread32(addr); \
+ pci_iounmap(pdev, addr); \
+ \
+ RUNTIME_INFO(i915)->ri_prefix.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK,
ver); \
+ RUNTIME_INFO(i915)->ri_prefix.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK,
ver); \
+ RUNTIME_INFO(i915)->ri_prefix.step = REG_FIELD_GET(GMD_ID_STEP, ver); \
+ \
+ /* Sanity check against expected versions from device info */ \
+ if (RUNTIME_INFO(i915)->ri_prefix.ver !=
INTEL_INFO(i915)->ri_prefix.ver || \
+ RUNTIME_INFO(i915)->ri_prefix.rel >
INTEL_INFO(i915)->ri_prefix.rel) \
+ drm_dbg(>drm, \
+ "Hardware reports " #ri_prefix " IP version %u.%u but
minimum expected is %u.%u\n", \
+ RUNTIME_INFO(i915)->ri_prefix.ver, \
+ RUNTIME_INFO(i915)->ri_prefix.rel, \
+ INTEL_INFO(i915)->ri_prefix.ver, \
+ INTEL_INFO(i915)->ri_prefix.rel); \
+ri_prefix##done:
+
+/**
+ * intel_ipver_early_init - setup IP version values
+ * @dev_priv: device private
+ *
+ * Setup the graphics version for the current device. This must be done before
+ * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this
+ * function should be called very early in the driver initialization sequence.
+ *
+ * Regular MMIO access is not yet setup at the point this function is called so
+ * we peek at the appropriate MMIO offset directly. The GMD_ID register is
+ * part of an 'always on' power well by design, so we don't need to worry about
+ * forcewake while reading it.
+ */
+static void intel_ipver_early_init(struct drm_i915_private *i915)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ void __iomem *addr;
+ u32 ver;
+
+ if (!HAS_GMD_ID(i915)) {
+ drm_WARN_ON(>drm, INTEL_INFO(i915)->graphics.ver > 12);
+
+ RUNTIME_INFO(i915)->graphics.ver =
INTEL_INFO(i915)->graphics.ver;
+ RUNTIME_INFO(i915)->graphics.rel =
INTEL_INFO(i915)->graphics.rel;
+ /* media ver = graphics ver for older platforms */
+ RUNTIME_INFO(i915)->media.ver = INTEL_INFO(i915)->graphics.ver;
+
[Intel-gfx] [PATCH 19/23] drm/i915/display/mtl: Extend MBUS programming
From: José Roberto de Souza Display version 14 also supports MBUS joining just like ADL-P and also it don't need MBUS initialization, so extending ADL-P code paths to display version 14 and higher. Bspec: 49213 Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- drivers/gpu/drm/i915/i915_drv.h| 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index ccc3f78b1607..c0bc5c30cef3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1101,7 +1101,7 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask; u32 mask, val, i; - if (IS_ALDERLAKE_P(dev_priv)) + if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) return; mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5767bbba2260..6a876cd53228 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1360,7 +1360,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \ IS_ALDERLAKE_S(dev_priv)) -#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915)) +#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline) -- 2.25.1
[Intel-gfx] [PATCH 03/23] drm/i915/mtl: MMIO range is now 4MB
From: Matt Roper
Previously only dgfx platforms had a 4MB MMIO range, but starting with
MTL we now use the larger range for all platforms.
Bspec: 63834, 63830
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_uncore.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index a852c471d1b3..e0a8a8cb2052 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2232,14 +2232,15 @@ int intel_uncore_setup_mmio(struct intel_uncore
*uncore, phys_addr_t phys_addr)
* clobbering the GTT which we want ioremap_wc instead. Fortunately,
* the register BAR remains the same size for all the earlier
* generations up to Ironlake.
-* For dgfx chips register range is expanded to 4MB.
+* For dgfx chips register range is expanded to 4MB, and this larger
+* range is also used for integrated gpus beginning with Meteor Lake.
*/
- if (GRAPHICS_VER(i915) < 5)
- mmio_size = 512 * 1024;
- else if (IS_DGFX(i915))
+ if (IS_DGFX(i915) || GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
mmio_size = 4 * 1024 * 1024;
- else
+ else if (GRAPHICS_VER(i915) >= 5)
mmio_size = 2 * 1024 * 1024;
+ else
+ mmio_size = 512 * 1024;
uncore->regs = ioremap(phys_addr, mmio_size);
if (uncore->regs == NULL) {
--
2.25.1
[Intel-gfx] [PATCH 16/23] drm/i915/mtl: Update memory bandwidth parameters
Like ADL_P, Meteorlake has different memory characteristics from
past platforms. Update the values used by our memory bandwidth
calculations accordingly.
Bspec: 64631
Cc: Matt Roper
Cc: Caz Yokoyama
Signed-off-by: Radhakrishna Sripada
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bw.c | 42 ++---
1 file changed, 38 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 8bbf47da1716..447a15f2c18a 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -178,7 +178,32 @@ static int icl_get_qgv_points(struct drm_i915_private
*dev_priv,
qi->num_points = dram_info->num_qgv_points;
qi->num_psf_points = dram_info->num_psf_gv_points;
- if (DISPLAY_VER(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ switch (dram_info->type) {
+ case INTEL_DRAM_DDR4:
+ qi->t_bl = 4;
+ qi->max_numchannels = 2;
+ qi->channel_width = 64;
+ qi->deinterleave = 2;
+ break;
+ case INTEL_DRAM_DDR5:
+ qi->t_bl = 8;
+ qi->max_numchannels = 4;
+ qi->channel_width = 32;
+ qi->deinterleave = 2;
+ break;
+ case INTEL_DRAM_LPDDR4:
+ case INTEL_DRAM_LPDDR5:
+ qi->t_bl = 16;
+ qi->max_numchannels = 8;
+ qi->channel_width = 16;
+ qi->deinterleave = 4;
+ break;
+ default:
+ MISSING_CASE(dram_info->type);
+ return -EINVAL;
+ }
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
switch (dram_info->type) {
case INTEL_DRAM_DDR4:
qi->t_bl = is_y_tile ? 8 : 4;
@@ -212,7 +237,7 @@ static int icl_get_qgv_points(struct drm_i915_private
*dev_priv,
qi->max_numchannels = 1;
break;
}
- else if (DISPLAY_VER(dev_priv) == 11) {
+ } else if (DISPLAY_VER(dev_priv) == 11) {
qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
qi->max_numchannels = 1;
}
@@ -311,6 +336,13 @@ static const struct intel_sa_info adlp_sa_info = {
.derating = 20,
};
+static const struct intel_sa_info mtl_sa_info = {
+ .deburst = 32,
+ .deprogbwlimit = 38, /* GB/s */
+ .displayrtids = 256,
+ .derating = 20,
+};
+
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct
intel_sa_info *sa)
{
struct intel_qgv_info qi = {};
@@ -585,9 +617,11 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_DG2(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 14)
+ tgl_get_bw_info(dev_priv, _sa_info);
+ else if (IS_DG2(dev_priv))
dg2_get_bw_info(dev_priv);
- else if (DISPLAY_VER(dev_priv) >= 13 || IS_ALDERLAKE_P(dev_priv))
+ else if (IS_ALDERLAKE_P(dev_priv))
tgl_get_bw_info(dev_priv, _sa_info);
else if (IS_ALDERLAKE_S(dev_priv))
tgl_get_bw_info(dev_priv, _sa_info);
--
2.25.1
[Intel-gfx] [PATCH 17/23] drm/i915/mtl: Update MBUS_DBOX credits
Display version 14 platforms has different credits values compared to ADL-P.
Update the credits based on pipe usage.
Bspec: 49213
Cc: Jose Roberto de Souza
Cc: Matt Roper
Original Author: Caz Yokoyama
Signed-off-by: José Roberto de Souza
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++
drivers/gpu/drm/i915/intel_pm.c | 47 ++---
2 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d37607109398..2f9cbdd068e8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1125,8 +1125,12 @@
#define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
#define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)
#define MBUS_DBOX_BW_CREDIT(x)
REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)
+#define MBUS_DBOX_BW_4CREDITS_MTL 0x2
+#define MBUS_DBOX_BW_8CREDITS_MTL 0x3
#define MBUS_DBOX_B_CREDIT_MASKREG_GENMASK(12, 8)
#define MBUS_DBOX_B_CREDIT(x)
REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)
+#define MBUS_DBOX_I_CREDIT_MASKREG_GENMASK(7, 5)
+#define MBUS_DBOX_I_CREDIT(x)
REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x)
#define MBUS_DBOX_A_CREDIT_MASKREG_GENMASK(3, 0)
#define MBUS_DBOX_A_CREDIT(x)
REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f71b3b8b590c..58a3c72418a7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8443,6 +8443,27 @@ void intel_dbuf_post_plane_update(struct
intel_atomic_state *state)
new_dbuf_state->enabled_slices);
}
+static bool xelpdp_is_one_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
+{
+ switch (pipe) {
+ case PIPE_A:
+ case PIPE_D:
+ if (is_power_of_2(active_pipes & (BIT(PIPE_A) | BIT(PIPE_D
+ return true;
+ break;
+ case PIPE_B:
+ case PIPE_C:
+ if (is_power_of_2(active_pipes & (BIT(PIPE_B) | BIT(PIPE_C
+ return true;
+ break;
+ default: /* to suppress compiler warning */
+ MISSING_CASE(pipe);
+ break;
+ }
+
+ return false;
+}
+
void intel_mbus_dbox_update(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
@@ -8462,20 +8483,28 @@ void intel_mbus_dbox_update(struct intel_atomic_state
*state)
new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
return;
+ if (DISPLAY_VER(i915) >= 14)
+ val |= MBUS_DBOX_I_CREDIT(2);
+
if (DISPLAY_VER(i915) >= 12) {
val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
}
- /* Wa_22010947358:adl-p */
- if (IS_ALDERLAKE_P(i915))
+ if (DISPLAY_VER(i915) >= 14)
+ val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
+MBUS_DBOX_A_CREDIT(8);
+ else if (IS_ALDERLAKE_P(i915))
+ /* Wa_22010947358:adl-p */
val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
MBUS_DBOX_A_CREDIT(4);
else
val |= MBUS_DBOX_A_CREDIT(2);
- if (IS_ALDERLAKE_P(i915)) {
+ if (DISPLAY_VER(i915) >= 14) {
+ val |= MBUS_DBOX_B_CREDIT(0xA);
+ } else if (IS_ALDERLAKE_P(i915)) {
val |= MBUS_DBOX_BW_CREDIT(2);
val |= MBUS_DBOX_B_CREDIT(8);
} else if (DISPLAY_VER(i915) >= 12) {
@@ -8487,10 +8516,20 @@ void intel_mbus_dbox_update(struct intel_atomic_state
*state)
}
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ u32 pipe_val = val;
+
if (!new_crtc_state->hw.active ||
!intel_crtc_needs_modeset(new_crtc_state))
continue;
- intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), val);
+ if (DISPLAY_VER(i915) >= 14) {
+ if (xelpdp_is_one_pipe_per_dbuf_bank(crtc->pipe,
+
new_dbuf_state->active_pipes))
+ pipe_val |=
MBUS_DBOX_BW_CREDIT(MBUS_DBOX_BW_8CREDITS_MTL);
+ else
+ pipe_val |=
MBUS_DBOX_BW_CREDIT(MBUS_DBOX_BW_4CREDITS_MTL);
+ }
+
+ intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
}
}
--
2.25.1
[Intel-gfx] [PATCH 21/23] drm/i915/dmc: MTL DMC debugfs entries
From: Anusha Srivatsa
MTL needs both Pipe A and Pipe B DMC to be loaded
along with Main DMC. Patch also adds
DMC debug register for MTL.
BSpec: 49788
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 9c4f442fa407..2fabb2760474 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1005,7 +1005,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file
*m, void *unused)
seq_printf(m, "Pipe A fw loaded: %s\n",
str_yes_no(dmc->dmc_info[DMC_FW_PIPEA].payload));
seq_printf(m, "Pipe B fw support: %s\n",
- str_yes_no(IS_ALDERLAKE_P(i915)));
+ str_yes_no(DISPLAY_VER(i915) >= 13));
seq_printf(m, "Pipe B fw loaded: %s\n",
str_yes_no(dmc->dmc_info[DMC_FW_PIPEB].payload));
@@ -1029,9 +1029,9 @@ static int intel_dmc_debugfs_status_show(struct seq_file
*m, void *unused)
* reg for DC3CO debugging and validation,
* but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
*/
- seq_printf(m, "DC3CO count: %d\n",
- intel_de_read(i915, IS_DGFX(i915) ?
-DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3));
+ seq_printf(m, "DC3CO count: %d\n", intel_de_read(i915,
+ (IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) ?
+ DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3));
} else {
dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT :
SKL_DMC_DC3_DC5_COUNT;
--
2.25.1
[Intel-gfx] [PATCH 11/23] drm/i915/mtl: Add DP AUX support on TypeC ports
From: Imre Deak
On MTL TypeC ports the AUX_CH_CTL and AUX_CH_DATA addresses have
changed wrt. previous platforms, adjust the code accordingly.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 45 -
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 40c4bdd9cb26..10616e18dc18 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -637,6 +637,46 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp
*intel_dp, int index)
}
}
+static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ return XELPDP_DP_AUX_CH_CTL(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return XELPDP_DP_AUX_CH_CTL(AUX_CH_A);
+ }
+}
+
+static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ return XELPDP_DP_AUX_CH_DATA(aux_ch, index);
+ default:
+ MISSING_CASE(aux_ch);
+ return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index);
+ }
+}
+
void intel_dp_aux_fini(struct intel_dp *intel_dp)
{
if (cpu_latency_qos_request_active(_dp->pm_qos))
@@ -652,7 +692,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
struct intel_encoder *encoder = _port->base;
enum aux_ch aux_ch = dig_port->aux_ch;
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
+ intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
} else if (DISPLAY_VER(dev_priv) >= 9) {
--
2.25.1
[Intel-gfx] [PATCH 14/23] drm/i915/mtl: Add CDCLK Support
From: Anusha Srivatsa
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
bxt_get_cdclk() is not properly calculating HW clock for MTL, because
the squash formula is only prepared for DG2, so for now checking
all parameters against the table.
Out of what is explicit in specification this is also implementing
a legacy cdclk method that is to be used when cdclk needs sanitization,
this will be used when GPU is reset or not initialized by firmware.
BSpec: 65243
Cc: José Roberto de Souza
Signed-off-by: Anusha Srivatsa
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 344 +++--
1 file changed, 314 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 390a198b0011..03a1dfd0f3c9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -38,6 +38,33 @@
#include "intel_psr.h"
#include "vlv_sideband.h"
+#define MTL_CDCLK_THRESHOLD307200
+
+#define HAS_SQUASH_AND_CRAWL(i915) (has_cdclk_squasher(i915) &&
HAS_CDCLK_CRAWL(i915))
+
+#define MTL_SQUASH_ONLY(i915, cdclk) ((i915)->cdclk.hw.cdclk <=
MTL_CDCLK_THRESHOLD && \
+(cdclk) < MTL_CDCLK_THRESHOLD)
+#define MTL_SQUASH_CRAWL(i915, cdclk) ((i915)->cdclk.hw.cdclk <
MTL_CDCLK_THRESHOLD && \
+(cdclk) > MTL_CDCLK_THRESHOLD)
+#define MTL_SQUASH_THRESHOLD(i915, cdclk) ((i915)->cdclk.hw.cdclk <
MTL_CDCLK_THRESHOLD && \
+(cdclk) == MTL_CDCLK_THRESHOLD)
+#define MTL_CRAWL_THRESHOLD(i915, cdclk) ((i915)->cdclk.hw.cdclk >
MTL_CDCLK_THRESHOLD && \
+(cdclk) == MTL_CDCLK_THRESHOLD)
+#define MTL_CRAWL_ONLY(i915, cdclk)((i915)->cdclk.hw.cdclk >
MTL_CDCLK_THRESHOLD && \
+(cdclk) > MTL_CDCLK_THRESHOLD)
+#define MTL_CRAWL_SQUASH(i915, cdclk) ((i915)->cdclk.hw.cdclk >
MTL_CDCLK_THRESHOLD && \
+(cdclk) <= MTL_CDCLK_THRESHOLD)
+
+enum mtl_cdclk_sequence {
+ CDCLK_INVALID_ACTION = -1,
+
+ CDCLK_SQUASH_ONLY = 0,
+ CDCLK_CRAWL_ONLY,
+ CDCLK_SQUASH_THRESHOLD_CRAWL,
+ CDCLK_CRAWL_THRESHOLD_SQUASH,
+ CDCLK_LEGACY_CHANGE,
+};
+
/**
* DOC: CDCLK / RAWCLK
*
@@ -1222,7 +1249,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private
*dev_priv)
static bool has_cdclk_squasher(struct drm_i915_private *i915)
{
- return IS_DG2(i915);
+ return DISPLAY_VER(i915) >= 14 || IS_DG2(i915);
}
struct intel_cdclk_vals {
@@ -1350,6 +1377,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] =
{
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16,
.waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16,
.waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16,
.waveform = 0x },
+ { .refclk = 38400, .cdclk = 48, .divider = 2, .ratio = 25,
.waveform = 0x },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29,
.waveform = 0x },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34,
.waveform = 0x },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
@@ -1479,6 +1516,75 @@ static void bxt_de_pll_readout(struct drm_i915_private
*dev_priv,
cdclk_config->vco = ratio * cdclk_config->ref;
}
+static void mtl_get_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_config *cdclk_config)
+{
+ const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+ u32 squash_ctl, divider, waveform;
+ int div, i, ratio;
+
+ bxt_de_pll_readout(dev_priv, cdclk_config);
+
+ cdclk_config->bypass = cdclk_config->ref / 2;
+
+ if (cdclk_config->vco == 0) {
+ cdclk_config->cdclk = cdclk_config->bypass;
+ goto out;
+ }
+
+ divider = intel_de_read(dev_priv, CDCLK_CTL) &
BXT_CDCLK_CD2X_DIV_SEL_MASK;
+ switch (divider) {
+ case BXT_CDCLK_CD2X_DIV_SEL_1:
+ div = 2;
+ break;
+ case BXT_CDCLK_CD2X_DIV_SEL_1_5:
+ div = 3;
+ break;
+ case BXT_CDCLK_CD2X_DIV_SEL_2:
+ div = 4;
+ break;
+ case BXT_CDCLK_CD2X_DIV_SEL_4:
+ div = 8;
+ break;
+ default:
+ MISSING_CASE(divider);
+ return;
+
[Intel-gfx] [PATCH 12/23] drm/i915/mtl: Fix rawclk for Meteorlake PCH
From: Clint Taylor MTL has a fixed rawclk of 38400Mhz. Register does not need to be reprogrammed. Bspec: 49304 Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_cdclk.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 86a22c3766e5..390a198b0011 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3036,6 +3036,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) freq = dg1_rawclk(dev_priv); + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP) + /* + * MTL always uses a 38.4 MHz rawclk. The bspec tells us + * "RAWCLK_FREQ defaults to the values for 38.4 and does + * not need to be programmed." + */ + freq = 38400; else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) freq = cnp_rawclk(dev_priv); else if (HAS_PCH_SPLIT(dev_priv)) -- 2.25.1
[Intel-gfx] [PATCH 05/23] drm/i915/mtl: Define engine context layouts
From: Matt Roper
The part of the media and blitter engine contexts that we care about for
setting up an initial state are the same on MTL as they were on on DG2
(and PVC), so we need to update the driver conditions to re-use the DG2
context table.
For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.
Bspec: 46261, 46260, 45585
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 47 -
1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index eec73c66406c..d3833cbaabcb 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -606,6 +606,49 @@ static const u8 dg2_rcs_offsets[] = {
END
};
+static const u8 mtl_rcs_offsets[] = {
+ NOP(1),
+ LRI(15, POSTED),
+ REG16(0x244),
+ REG(0x034),
+ REG(0x030),
+ REG(0x038),
+ REG(0x03c),
+ REG(0x168),
+ REG(0x140),
+ REG(0x110),
+ REG(0x1c0),
+ REG(0x1c4),
+ REG(0x1c8),
+ REG(0x180),
+ REG16(0x2b4),
+ REG(0x120),
+ REG(0x124),
+
+ NOP(1),
+ LRI(9, POSTED),
+ REG16(0x3a8),
+ REG16(0x28c),
+ REG16(0x288),
+ REG16(0x284),
+ REG16(0x280),
+ REG16(0x27c),
+ REG16(0x278),
+ REG16(0x274),
+ REG16(0x270),
+
+ NOP(2),
+ LRI(2, POSTED),
+ REG16(0x5a8),
+ REG16(0x5ac),
+
+ NOP(6),
+ LRI(1, 0),
+ REG(0x0c8),
+
+ END
+};
+
#undef END
#undef REG16
#undef REG
@@ -624,7 +667,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs
*engine)
!intel_engine_has_relative_mmio(engine));
if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+ return mtl_rcs_offsets;
+ else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_rcs_offsets;
else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
return xehp_rcs_offsets;
--
2.25.1
[Intel-gfx] [PATCH 06/23] drm/i915/mtl: Add PCH support
Add support for Meteorpoint(MTP) PCH used with Meteorlake.
Cc: Matt Roper
Cc: Anusha Srivatsa
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_pch.c | 9 -
drivers/gpu/drm/i915/intel_pch.h | 4
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index 0fec25be146a..ba9843cb1b13 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -138,6 +138,11 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
unsigned short id)
drm_WARN_ON(_priv->drm, !IS_ALDERLAKE_S(dev_priv) &&
!IS_ALDERLAKE_P(dev_priv));
return PCH_ADP;
+ case INTEL_PCH_MTP_DEVICE_ID_TYPE:
+ case INTEL_PCH_MTP2_DEVICE_ID_TYPE:
+ drm_dbg_kms(_priv->drm, "Found Meteor Lake PCH\n");
+ drm_WARN_ON(_priv->drm, !IS_METEORLAKE(dev_priv));
+ return PCH_MTP;
default:
return PCH_NONE;
}
@@ -166,7 +171,9 @@ intel_virt_detect_pch(const struct drm_i915_private
*dev_priv,
* make an educated guess as to which PCH is really there.
*/
- if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
+ if (IS_METEORLAKE(dev_priv))
+ id = INTEL_PCH_MTP_DEVICE_ID_TYPE;
+ else if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 7c8ce9781d1a..32aff5a70d04 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -25,6 +25,7 @@ enum intel_pch {
PCH_ICP,/* Ice Lake/Jasper Lake PCH */
PCH_TGP,/* Tiger Lake/Mule Creek Canyon PCH */
PCH_ADP,/* Alder Lake PCH */
+ PCH_MTP,/* Meteor Lake PCH */
/* Fake PCHs, functionality handled on the same PCI dev */
PCH_DG1 = 1024,
@@ -57,12 +58,15 @@ enum intel_pch {
#define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180
#define INTEL_PCH_ADP3_DEVICE_ID_TYPE 0x7A00
#define INTEL_PCH_ADP4_DEVICE_ID_TYPE 0x5480
+#define INTEL_PCH_MTP_DEVICE_ID_TYPE 0x7E00
+#define INTEL_PCH_MTP2_DEVICE_ID_TYPE 0xAE00
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
+#define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_MTP)
#define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_DG2)
#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_ADP)
#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_DG1)
--
2.25.1
[Intel-gfx] [PATCH 15/23] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox
>From Meteorlake, Latency Level, SAGV bloack time are read from
LATENCY_SAGV register instead of the GT driver pcode mailbox. DDR type
and QGV information are also tob read from Mem SS registers.
Bspec: 49324, 64636
Cc: Matt Roper
Original Author: Caz Yokoyama
Signed-off-by: José Roberto de Souza
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_bw.c | 49 +++--
drivers/gpu/drm/i915/display/intel_bw.h | 9 +
drivers/gpu/drm/i915/i915_reg.h | 16
drivers/gpu/drm/i915/intel_dram.c | 41 -
drivers/gpu/drm/i915/intel_pm.c | 8 +++-
5 files changed, 110 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 79269d2c476b..8bbf47da1716 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -15,11 +15,6 @@
#include "intel_pcode.h"
#include "intel_pm.h"
-/* Parameters for Qclk Geyserville (QGV) */
-struct intel_qgv_point {
- u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
-};
-
struct intel_psf_gv_point {
u8 clk; /* clock in multiples of 16. MHz */
};
@@ -137,6 +132,42 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private
*dev_priv,
return 0;
}
+static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
+ struct intel_qgv_point *sp, int point)
+{
+ u32 val, val2;
+ u16 dclk;
+
+ val = intel_uncore_read(_priv->uncore,
+ MTL_MEM_SS_INFO_QGV_POINT(point, 0));
+ val2 = intel_uncore_read(_priv->uncore,
+MTL_MEM_SS_INFO_QGV_POINT(point, 1));
+ dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
+ sp->dclk = DIV_ROUND_UP((16667 * dclk) + 500, 1000);
+ sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
+ sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
+
+ sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2);
+ sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2);
+
+ sp->t_rc = sp->t_rp + sp->t_ras;
+
+ return 0;
+}
+
+int
+intel_read_qgv_point_info(struct drm_i915_private *dev_priv,
+ struct intel_qgv_point *sp,
+ int point)
+{
+ if (DISPLAY_VER(dev_priv) >= 14)
+ return mtl_read_qgv_point_info(dev_priv, sp, point);
+ else if (IS_DG1(dev_priv))
+ return dg1_mchbar_read_qgv_point_info(dev_priv, sp, point);
+ else
+ return icl_pcode_read_qgv_point_info(dev_priv, sp, point);
+}
+
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi,
bool is_y_tile)
@@ -193,11 +224,7 @@ static int icl_get_qgv_points(struct drm_i915_private
*dev_priv,
for (i = 0; i < qi->num_points; i++) {
struct intel_qgv_point *sp = >points[i];
- if (IS_DG1(dev_priv))
- ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i);
- else
- ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
-
+ ret = intel_read_qgv_point_info(dev_priv, sp, i);
if (ret)
return ret;
@@ -560,7 +587,7 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
if (IS_DG2(dev_priv))
dg2_get_bw_info(dev_priv);
- else if (IS_ALDERLAKE_P(dev_priv))
+ else if (DISPLAY_VER(dev_priv) >= 13 || IS_ALDERLAKE_P(dev_priv))
tgl_get_bw_info(dev_priv, _sa_info);
else if (IS_ALDERLAKE_S(dev_priv))
tgl_get_bw_info(dev_priv, _sa_info);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
b/drivers/gpu/drm/i915/display/intel_bw.h
index cb7ee3a24a58..b4c6665b0cf0 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -46,6 +46,11 @@ struct intel_bw_state {
u8 num_active_planes[I915_MAX_PIPES];
};
+/* Parameters for Qclk Geyserville (QGV) */
+struct intel_qgv_point {
+ u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
+};
+
#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
struct intel_bw_state *
@@ -69,4 +74,8 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
int intel_bw_min_cdclk(struct drm_i915_private *i915,
const struct intel_bw_state *bw_state);
+int intel_read_qgv_point_info(struct drm_i915_private *dev_priv,
+ struct intel_qgv_point *sp,
+ int point);
+
#endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 23b50d671550..d37607109398 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8761,4 +8761,20 @@ enum skl_power_gate {
#define MTL_LATENCY_LEVEL0_2_4_MASK
[Intel-gfx] [PATCH 04/23] drm/i915/mtl: Don't mask off CCS according to DSS fusing
From: Matt Roper Unlike the Xe_HP platforms, MTL only has a single CCS engine; the quad-based engine masking logic does not apply to this platform (or presumably any future platforms that only have 0 or 1 CCS). Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 37fa813af766..17e7f20bbb48 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -672,7 +672,7 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt) unsigned long ccs_mask; unsigned int i; - if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) + if (hweight32(CCS_MASK(gt)) <= 1) return; ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask, -- 2.25.1
[Intel-gfx] [CI] PR for new GuC v70.4.1 for DG2
The following changes since commit 150864a4d73e8c448eb1e2c68e65f07635fe1a66: amdgpu partially revert "amdgpu: update beige goby to release 22.20" (2022-07-25 14:16:04 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware dg2_guc_v70.4.1 for you to fetch changes up to a4235e0aa4d4753119fd81f582eef84addf3f4a1: i915: Add GuC v70.4.1 for DG2 (2022-07-27 18:03:49 -0700) John Harrison (1): i915: Add GuC v70.4.1 for DG2 WHENCE | 3 +++ i915/dg2_guc_70.4.1.bin | Bin 0 -> 369600 bytes 2 files changed, 3 insertions(+) create mode 100644 i915/dg2_guc_70.4.1.bin
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Don't send policy update for child contexts.
== Series Details ==
Series: drm/i915/guc: Don't send policy update for child contexts.
URL : https://patchwork.freedesktop.org/series/106783/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106783v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106783v1/index.html
Participating hosts (38 -> 35)
--
Additional (2): fi-hsw-4770 bat-jsl-1
Missing(5): bat-dg1-5 bat-adlm-1 bat-jsl-3 bat-rplp-1 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_106783v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#3012])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106783v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][2] -> [DMESG-FAIL][3] ([i915#4528])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106783v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106783v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106783v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-n3050: [PASS][6] -> [FAIL][7] ([i915#6298])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106783v1/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1072]) +3
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106783v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@runner@aborted:
- fi-blb-e6850: NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#2403] /
[i915#4312])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106783v1/fi-blb-e6850/igt@run...@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][10] ([i915#4312])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106783v1/fi-bdw-5557u/igt@run...@aborted.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- fi-kbl-guc: [FAIL][11] ([i915#6253]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-kbl-guc/igt@debugfs_test@read_all_entries.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106783v1/fi-kbl-guc/igt@debugfs_test@read_all_entries.html
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][13] ([i915#2582]) -> [PASS][14] +4 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-rpls-2/igt@fb...@read.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106783v1/bat-rpls-2/igt@fb...@read.html
* igt@i915_selftest@live@gtt:
- {bat-dg2-9}:[DMESG-WARN][15] ([i915#5763]) -> [PASS][16] +8
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-dg2-9/igt@i915_selftest@l...@gtt.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106783v1/bat-dg2-9/igt@i915_selftest@l...@gtt.html
* igt@kms_frontbuffer_tracking@basic:
- {bat-rpls-2}: [SKIP][17] ([i915#1849]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-rpls-2/igt@kms_frontbuffer_track...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106783v1/bat-rpls-2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-fence-flip:
- {bat-rpls-2}: [SKIP][19] ([fdo#109295] / [i915#1845] / [i915#3708])
-> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-rpls-2/igt@prime_v...@basic-fence-flip.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106783v1/bat-rpls-2/igt@prime_v...@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]:
[Intel-gfx] [PATCH] drm/i915/guc: Don't send policy update for child contexts.
The GuC FW applies the parent context policy to all the children,
so individual updates to the children are not supported and we
should not send them.
Note that sending the message did not have any functional consequences,
because the GuC just drops it and logs an error; since we were trying
to set the child policy to match the parent anyway the message being
dropped was not a problem.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 26 +--
1 file changed, 1 insertion(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 76916aed897a..5e31e2540297 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2420,7 +2420,6 @@ static int guc_context_policy_init_v70(struct
intel_context *ce, bool loop)
struct context_policy policy;
u32 execution_quantum;
u32 preemption_timeout;
- bool missing = false;
unsigned long flags;
int ret;
@@ -2438,32 +2437,9 @@ static int guc_context_policy_init_v70(struct
intel_context *ce, bool loop)
__guc_context_policy_add_preempt_to_idle(, 1);
ret = __guc_context_set_context_policies(guc, , loop);
- missing = ret != 0;
-
- if (!missing && intel_context_is_parent(ce)) {
- struct intel_context *child;
-
- for_each_child(ce, child) {
- __guc_context_policy_start_klv(,
child->guc_id.id);
-
- if (engine->flags & I915_ENGINE_WANT_FORCED_PREEMPTION)
-
__guc_context_policy_add_preempt_to_idle(, 1);
-
- child->guc_state.prio = ce->guc_state.prio;
- __guc_context_policy_add_priority(,
ce->guc_state.prio);
- __guc_context_policy_add_execution_quantum(,
execution_quantum);
- __guc_context_policy_add_preemption_timeout(,
preemption_timeout);
-
- ret = __guc_context_set_context_policies(guc, ,
loop);
- if (ret) {
- missing = true;
- break;
- }
- }
- }
spin_lock_irqsave(>guc_state.lock, flags);
- if (missing)
+ if (ret != 0)
set_context_policy_required(ce);
else
clr_context_policy_required(ce);
--
2.25.1
[Intel-gfx] ✗ Fi.CI.BAT: failure for Move CDCLK checks to atomic check phase
== Series Details ==
Series: Move CDCLK checks to atomic check phase
URL : https://patchwork.freedesktop.org/series/106782/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106782v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_106782v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_106782v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106782v1/index.html
Participating hosts (38 -> 36)
--
Additional (4): fi-hsw-4770 bat-adls-5 bat-jsl-1 bat-adlp-4
Missing(6): fi-tgl-dsi fi-bsw-n3050 fi-glk-dsi fi-glk-j4005 fi-bsw-kefka
fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_106782v1:
### IGT changes ###
Possible regressions
* igt@i915_module_load@load:
- fi-rkl-11600: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-rkl-11600/igt@i915_module_l...@load.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106782v1/fi-rkl-11600/igt@i915_module_l...@load.html
- fi-rkl-guc: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-rkl-guc/igt@i915_module_l...@load.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106782v1/fi-rkl-guc/igt@i915_module_l...@load.html
- fi-skl-guc: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-skl-guc/igt@i915_module_l...@load.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106782v1/fi-skl-guc/igt@i915_module_l...@load.html
- fi-skl-6700k2: [PASS][7] -> [INCOMPLETE][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-skl-6700k2/igt@i915_module_l...@load.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106782v1/fi-skl-6700k2/igt@i915_module_l...@load.html
- fi-cfl-8700k: [PASS][9] -> [INCOMPLETE][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-cfl-8700k/igt@i915_module_l...@load.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106782v1/fi-cfl-8700k/igt@i915_module_l...@load.html
- fi-adl-ddr5:[PASS][11] -> [INCOMPLETE][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-adl-ddr5/igt@i915_module_l...@load.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106782v1/fi-adl-ddr5/igt@i915_module_l...@load.html
- fi-cfl-guc: [PASS][13] -> [INCOMPLETE][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-cfl-guc/igt@i915_module_l...@load.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106782v1/fi-cfl-guc/igt@i915_module_l...@load.html
- fi-bdw-5557u: [PASS][15] -> [INCOMPLETE][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-bdw-5557u/igt@i915_module_l...@load.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106782v1/fi-bdw-5557u/igt@i915_module_l...@load.html
- fi-cfl-8109u: [PASS][17] -> [INCOMPLETE][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-cfl-8109u/igt@i915_module_l...@load.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106782v1/fi-cfl-8109u/igt@i915_module_l...@load.html
* igt@kms_busy@basic@flip:
- fi-skl-6600u: [PASS][19] -> [INCOMPLETE][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-skl-6600u/igt@kms_busy@ba...@flip.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106782v1/fi-skl-6600u/igt@kms_busy@ba...@flip.html
* igt@kms_force_connector_basic@force-connector-state:
- bat-dg1-5: [PASS][21] -> [DMESG-WARN][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-dg1-5/igt@kms_force_connector_ba...@force-connector-state.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106782v1/bat-dg1-5/igt@kms_force_connector_ba...@force-connector-state.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@load:
- {bat-jsl-1}:NOTRUN -> [INCOMPLETE][23]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106782v1/bat-jsl-1/igt@i915_module_l...@load.html
- {bat-rpls-1}: [PASS][24] -> [INCOMPLETE][25]
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-rpls-1/igt@i915_module_l...@load.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106782v1/bat-rpls-1/igt@i915_module_l...@load.html
- {bat-jsl-3}:[PASS][26] -> [INCOMPLETE][27]
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Move CDCLK checks to atomic check phase
== Series Details == Series: Move CDCLK checks to atomic check phase URL : https://patchwork.freedesktop.org/series/106782/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Move CDCLK checks to atomic check phase
== Series Details ==
Series: Move CDCLK checks to atomic check phase
URL : https://patchwork.freedesktop.org/series/106782/
State : warning
== Summary ==
Error: dim checkpatch failed
b31629d56cc7 drm/i915/display: Add CDCLK actions to intel_cdclk_state
a77796ff5290 drm/i915/display: s/intel_cdclk_can_squash/intel_cdclk_squash
-:28: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#28: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1973:
{
+
total: 0 errors, 0 warnings, 1 checks, 40 lines checked
a462b1685a1a drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl
-:25: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#25: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1948:
+static bool intel_cdclk_crawl(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_state *a,
total: 0 errors, 0 warnings, 1 checks, 42 lines checked
18d9d117a9a9 drm/i915/display: Add cdclk checks to atomic check
-:188: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#188: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:2045:
{
+
total: 0 errors, 0 warnings, 1 checks, 171 lines checked
[Intel-gfx] [PATCH 4/4] drm/i915/display: Add cdclk checks to atomic check
Checking cdclk conditions during atomic check and preparing
for commit phase so we can have atomic commit as simple
as possible. Add the specific steps to be taken during
cdclk changes, prepare for squashing, crawling and modeset
scenarios.
v2: Add intel_cdclk_modeset() similar to intel_cdclk_squash()
and intel_cdclk_crawl().
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 108 +++--
1 file changed, 77 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index cb6e419562dd..2efc1f09abab 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1693,12 +1693,23 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
+ struct intel_atomic_state *state;
+ struct intel_cdclk_state *new_cdclk_state;
+ struct cdclk_step *cdclk_steps;
+ struct intel_cdclk_state *cdclk_state;
int cdclk = cdclk_config->cdclk;
int vco = cdclk_config->vco;
+ u32 squash_ctl = 0;
u32 val;
u16 waveform;
int clock;
int ret;
+ int i;
+
+ cdclk_state = to_intel_cdclk_state(dev_priv->cdclk.obj.state);
+ state = cdclk_state->base.state;
+ new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
+ cdclk_steps = new_cdclk_state->steps;
/* Inform power controller of upcoming frequency change. */
if (DISPLAY_VER(dev_priv) >= 11)
@@ -1721,40 +1732,42 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
return;
}
- if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0)
{
- if (dev_priv->cdclk.hw.vco != vco)
+ for (i = 0; i < MAX_CDCLK_ACTIONS; i++) {
+ switch (cdclk_steps[i].action) {
+ case INTEL_CDCLK_MODESET:
+ if (DISPLAY_VER(dev_priv) >= 11) {
+ if (dev_priv->cdclk.hw.vco != 0 &&
+ dev_priv->cdclk.hw.vco != vco)
+ icl_cdclk_pll_disable(dev_priv);
+
+ if (dev_priv->cdclk.hw.vco != vco)
+ icl_cdclk_pll_enable(dev_priv, vco);
+ } else {
+ if (dev_priv->cdclk.hw.vco != 0 &&
+ dev_priv->cdclk.hw.vco != vco)
+ bxt_de_pll_disable(dev_priv);
+
+ if (dev_priv->cdclk.hw.vco != vco)
+ bxt_de_pll_enable(dev_priv, vco);
+ }
+ clock = cdclk;
+ break;
+ case INTEL_CDCLK_CRAWL:
adlp_cdclk_pll_crawl(dev_priv, vco);
- } else if (DISPLAY_VER(dev_priv) >= 11) {
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
- icl_cdclk_pll_disable(dev_priv);
-
- if (dev_priv->cdclk.hw.vco != vco)
- icl_cdclk_pll_enable(dev_priv, vco);
- } else {
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
- bxt_de_pll_disable(dev_priv);
-
- if (dev_priv->cdclk.hw.vco != vco)
- bxt_de_pll_enable(dev_priv, vco);
- }
-
- waveform = cdclk_squash_waveform(dev_priv, cdclk);
-
- if (waveform)
- clock = vco / 2;
- else
- clock = cdclk;
-
- if (has_cdclk_squasher(dev_priv)) {
- u32 squash_ctl = 0;
-
- if (waveform)
+ clock = cdclk;
+ break;
+ case INTEL_CDCLK_SQUASH:
+ waveform = cdclk_squash_waveform(dev_priv,
cdclk_steps[i].cdclk);
+ clock = vco / 2;
squash_ctl = CDCLK_SQUASH_ENABLE |
CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
-
- intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
+ intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
+ break;
+ case INTEL_CDCLK_NOOP:
+ break;
+ default:
+ break;
+ }
}
val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
@@ -1949,6 +1962,7 @@ static bool intel_cdclk_crawl(struct drm_i915_private
*dev_priv,
struct intel_cdclk_state *b)
{
int a_div, b_div;
+ struct cdclk_step *cdclk_transition = b->steps;
if
[Intel-gfx] [PATCH 3/4] drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl
Apart from checking if crawling can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4081b880a6ef..cb6e419562dd 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1944,9 +1944,9 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
skl_cdclk_uninit_hw(i915);
}
-static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *a,
- const struct intel_cdclk_config *b)
+static bool intel_cdclk_crawl(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_state *a,
+ struct intel_cdclk_state *b)
{
int a_div, b_div;
@@ -1957,13 +1957,13 @@ static bool intel_cdclk_can_crawl(struct
drm_i915_private *dev_priv,
* The vco and cd2x divider will change independently
* from each, so we disallow cd2x change when crawling.
*/
- a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
- b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
+ a_div = DIV_ROUND_CLOSEST(a->actual.vco, a->actual.cdclk);
+ b_div = DIV_ROUND_CLOSEST(b->actual.vco, b->actual.cdclk);
- return a->vco != 0 && b->vco != 0 &&
- a->vco != b->vco &&
+ return a->actual.vco != 0 && b->actual.vco != 0 &&
+ a->actual.vco != b->actual.vco &&
a_div == b_div &&
- a->ref == b->ref;
+ a->actual.ref == b->actual.ref;
}
static bool intel_cdclk_squash(struct drm_i915_private *dev_priv,
@@ -2764,9 +2764,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
new_cdclk_state)) {
drm_dbg_kms(_priv->drm,
"Can change cdclk via squasher\n");
- } else if (intel_cdclk_can_crawl(dev_priv,
-_cdclk_state->actual,
-_cdclk_state->actual)) {
+ } else if (intel_cdclk_crawl(dev_priv,
+old_cdclk_state,
+new_cdclk_state)) {
drm_dbg_kms(_priv->drm,
"Can change cdclk via crawl\n");
} else if (pipe != INVALID_PIPE) {
--
2.25.1
[Intel-gfx] [PATCH 2/4] drm/i915/display: s/intel_cdclk_can_squash/intel_cdclk_squash
Apart from checking if squashing can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 86a22c3766e5..4081b880a6ef 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1966,10 +1966,11 @@ static bool intel_cdclk_can_crawl(struct
drm_i915_private *dev_priv,
a->ref == b->ref;
}
-static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *a,
- const struct intel_cdclk_config *b)
+static bool intel_cdclk_squash(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_state *a,
+ struct intel_cdclk_state *b)
{
+
/*
* FIXME should store a bit more state in intel_cdclk_config
* to differentiate squasher vs. cd2x divider properly. For
@@ -1979,10 +1980,10 @@ static bool intel_cdclk_can_squash(struct
drm_i915_private *dev_priv,
if (!has_cdclk_squasher(dev_priv))
return false;
- return a->cdclk != b->cdclk &&
- a->vco != 0 &&
- a->vco == b->vco &&
- a->ref == b->ref;
+ return a->actual.cdclk != b->actual.cdclk &&
+ a->actual.vco != 0 &&
+ a->actual.vco == b->actual.vco &&
+ a->actual.ref == b->actual.ref;
}
/**
@@ -2758,9 +2759,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
pipe = INVALID_PIPE;
}
- if (intel_cdclk_can_squash(dev_priv,
- _cdclk_state->actual,
- _cdclk_state->actual)) {
+ if (intel_cdclk_squash(dev_priv,
+ old_cdclk_state,
+ new_cdclk_state)) {
drm_dbg_kms(_priv->drm,
"Can change cdclk via squasher\n");
} else if (intel_cdclk_can_crawl(dev_priv,
--
2.25.1
[Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to intel_cdclk_state
This is a prep patch for what the rest of the series does.
Add existing actions that change cdclk - squash, crawl, modeset to
intel_cdclk_state so we have access to the cdclk values
that are in transition.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
b/drivers/gpu/drm/i915/display/intel_cdclk.h
index b535cf6a7d9e..43835688ee02 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -15,6 +15,14 @@ struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc_state;
+enum cdclk_actions {
+ INTEL_CDCLK_MODESET = 0,
+ INTEL_CDCLK_SQUASH,
+ INTEL_CDCLK_CRAWL,
+ INTEL_CDCLK_NOOP,
+ MAX_CDCLK_ACTIONS
+};
+
struct intel_cdclk_config {
unsigned int cdclk, vco, ref, bypass;
u8 voltage_level;
@@ -51,6 +59,11 @@ struct intel_cdclk_state {
/* bitmask of active pipes */
u8 active_pipes;
+
+ struct cdclk_step {
+ enum cdclk_actions action;
+ u32 cdclk;
+ } steps[MAX_CDCLK_ACTIONS];
};
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
--
2.25.1
[Intel-gfx] [PATCH 0/4] Move CDCLK checks to atomic check phase
The intention is to check for squashing, crawling conditions at atomic check phase and prepare for commit phase. This basically means the in-flight cdclk state is available. intel_cdclk_can_squash(), intel_cdclk_can_crawl() and intel_cdclk_needs_modeset() have changes to accommodate this. Cc: Matt Roper Anusha Srivatsa (4): drm/i915/display: Add CDCLK actions to intel_cdclk_state drm/i915/display: s/intel_cdclk_can_squash/intel_cdclk_squash drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl drm/i915/display: Add cdclk checks to atomic check drivers/gpu/drm/i915/display/intel_cdclk.c | 151 ++--- drivers/gpu/drm/i915/display/intel_cdclk.h | 13 ++ 2 files changed, 112 insertions(+), 52 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH 0/4] Add CDCLK checks to atomic check phase
The intention is to check for squashing, crawling conditions at atomic check phase and prepare for commit phase. This basically means the in-flight cdclk state is available. intel_cdclk_can_squash(), intel_cdclk_can_crawl() and intel_cdclk_needs_modeset() have changes to accommodate this. Anusha Srivatsa (4): drm/i915/display: Add CDCLK actions to intel_cdclk_state drm/i915/display: s/intel_cdclk_can_squash/intel_cdclk_squash drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl drm/i915/display: Add cdclk checks to atomic check drivers/gpu/drm/i915/display/intel_cdclk.c | 151 ++--- drivers/gpu/drm/i915/display/intel_cdclk.h | 13 ++ 2 files changed, 112 insertions(+), 52 deletions(-) -- 2.25.1
Re: [Intel-gfx] [PATCH] drm/i915/ttm: don't leak the ccs state
> -Original Message-
> From: Auld, Matthew
> Sent: Wednesday, July 27, 2022 10:14 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Thomas Hellström
> ; C,
> Ramalingam
> Subject: [PATCH] drm/i915/ttm: don't leak the ccs state
>
> The kernel only manages the ccs state with lmem-only objects, however the
> kernel should still take
> care not to leak the CCS state from the previous user.
>
> Fixes: 48760ffe923a ("drm/i915/gt: Clear compress metadata for Flat-ccs
> objects")
> Signed-off-by: Matthew Auld
> Cc: Thomas Hellström
> Cc: Ramalingam C
> ---
> drivers/gpu/drm/i915/gt/intel_migrate.c | 23 ++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
> b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index a69b244f14d0..9a0814422ba4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -708,7 +708,7 @@ intel_context_migrate_copy(struct intel_context *ce,
> u8 src_access, dst_access;
> struct i915_request *rq;
> int src_sz, dst_sz;
> - bool ccs_is_src;
> + bool ccs_is_src, overwrite_ccs;
> int err;
>
> GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
> @@ -749,6 +749,8 @@ intel_context_migrate_copy(struct intel_context *ce,
> get_ccs_sg_sgt(_ccs, bytes_to_cpy);
> }
>
> + overwrite_ccs = HAS_FLAT_CCS(i915) && !ccs_bytes_to_cpy &&
> +dst_is_lmem;
> +
> src_offset = 0;
> dst_offset = CHUNK_SZ;
> if (HAS_64K_PAGES(ce->engine->i915)) { @@ -852,6 +854,25 @@
> intel_context_migrate_copy(struct intel_context *ce,
> if (err)
> goto out_rq;
> ccs_bytes_to_cpy -= ccs_sz;
> + } else if (overwrite_ccs) {
> + err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
> + if (err)
> + goto out_rq;
> +
> + /*
> + * While we can't always restore/manage the CCS state,
> + * we still need to ensure we don't leak the CCS state
> + * from the previous user, so make sure we overwrite it
> + * with something.
> + */
> + err = emit_copy_ccs(rq, dst_offset, INDIRECT_ACCESS,
> + dst_offset, DIRECT_ACCESS, len);
> + if (err)
> + goto out_rq;
> +
> + err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
> + if (err)
> + goto out_rq;
The change is looking good to the purpose. But shouldn't this be the part of
lmem allocation itself?
Ram.
> }
>
> /* Arbitration is re-enabled between requests. */
> --
> 2.37.1
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/ttm: don't leak the ccs state
== Series Details ==
Series: drm/i915/ttm: don't leak the ccs state
URL : https://patchwork.freedesktop.org/series/106765/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946_full -> Patchwork_106765v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_106765v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ctx_persistence@many-contexts:
- {shard-dg1}:NOTRUN -> [DMESG-FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/shard-dg1-13/igt@gem_ctx_persiste...@many-contexts.html
New tests
-
New tests have been introduced between CI_DRM_11946_full and
Patchwork_106765v1_full:
### New IGT tests (4) ###
* igt@kms_sequence@get-forked@hdmi-a-4-pipe-a:
- Statuses : 1 pass(s)
- Exec time: [2.35] s
* igt@kms_sequence@get-forked@hdmi-a-4-pipe-b:
- Statuses : 1 pass(s)
- Exec time: [2.23] s
* igt@kms_sequence@get-forked@hdmi-a-4-pipe-c:
- Statuses : 1 pass(s)
- Exec time: [2.22] s
* igt@kms_sequence@get-forked@hdmi-a-4-pipe-d:
- Statuses : 1 pass(s)
- Exec time: [2.24] s
Known issues
Here are the changes found in Patchwork_106765v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][2] -> [SKIP][3] ([i915#658])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/shard-iclb2/igt@feature_discov...@psr2.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/shard-iclb7/igt@feature_discov...@psr2.html
* igt@gem_create@create-massive:
- shard-glk: NOTRUN -> [DMESG-WARN][4] ([i915#4991])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/shard-glk9/igt@gem_cre...@create-massive.html
- shard-kbl: NOTRUN -> [DMESG-WARN][5] ([i915#4991])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/shard-kbl1/igt@gem_cre...@create-massive.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-kbl: [PASS][6] -> [DMESG-WARN][7] ([i915#180]) +1 similar
issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/shard-kbl1/igt@gem_ctx_isolation@preservation...@rcs0.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/shard-kbl6/igt@gem_ctx_isolation@preservation...@rcs0.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: [PASS][8] -> [TIMEOUT][9] ([i915#3063])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/shard-tglb3/igt@gem_...@in-flight-contexts-immediate.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/shard-tglb5/igt@gem_...@in-flight-contexts-immediate.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#5784])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/shard-tglb7/igt@gem_...@unwedge-stress.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/shard-tglb2/igt@gem_...@unwedge-stress.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [PASS][12] -> [SKIP][13] ([i915#4525]) +2 similar
issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/shard-iclb1/igt@gem_exec_balan...@parallel-keep-submit-fence.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/shard-iclb8/igt@gem_exec_balan...@parallel-keep-submit-fence.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-kbl: [PASS][14] -> [SKIP][15] ([fdo#109271])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/shard-kbl1/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/shard-kbl6/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][17] -> [SKIP][18] ([i915#2190])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/shard-tglb2/igt@gem_huc_c...@huc-copy.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/shard-tglb7/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +1
similar issue
[19]:
[Intel-gfx] ✓ Fi.CI.BAT: success for Bump DG2 DMC firmware to v2.07 (rev2)
== Series Details == Series: Bump DG2 DMC firmware to v2.07 (rev2) URL : https://patchwork.freedesktop.org/series/106773/ State : success == Summary == CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106773v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106773v2/index.html Participating hosts (38 -> 28) -- Missing(10): fi-rkl-11600 bat-dg1-5 bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adlp-6 bat-rplp-1 bat-rpls-1 bat-rpls-2 fi-bdw-samus Known issues Here are the changes found in Patchwork_106773v2 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gem: - fi-blb-e6850: [PASS][1] -> [DMESG-FAIL][2] ([i915#4528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-blb-e6850/igt@i915_selftest@l...@gem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106773v2/fi-blb-e6850/igt@i915_selftest@l...@gem.html * igt@i915_selftest@live@gt_heartbeat: - fi-bdw-5557u: [PASS][3] -> [DMESG-FAIL][4] ([i915#5334]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106773v2/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@requests: - fi-elk-e7500: [PASS][5] -> [DMESG-FAIL][6] ([i915#4528]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-elk-e7500/igt@i915_selftest@l...@requests.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106773v2/fi-elk-e7500/igt@i915_selftest@l...@requests.html * igt@runner@aborted: - fi-elk-e7500: NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#4312]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106773v2/fi-elk-e7500/igt@run...@aborted.html - fi-blb-e6850: NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#2403] / [i915#4312]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106773v2/fi-blb-e6850/igt@run...@aborted.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-kbl-guc: [FAIL][9] ([i915#6253]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-kbl-guc/igt@debugfs_test@read_all_entries.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106773v2/fi-kbl-guc/igt@debugfs_test@read_all_entries.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#6253]: https://gitlab.freedesktop.org/drm/intel/issues/6253 Build changes - * Linux: CI_DRM_11946 -> Patchwork_106773v2 CI-20190529: 20190529 CI_DRM_11946: 0e9c43d76a145712da46e935d429ce2a3eea80e8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6598: 97e103419021d0863db527e3f2cf39ccdd132db5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_106773v2: 0e9c43d76a145712da46e935d429ce2a3eea80e8 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 4550eef4e32b drm/i915/dmc: Update DG2 DMC firmware to v2.07 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106773v2/index.html
Re: [Intel-gfx] [PATCH] drm/i915: Suppress oom warning for shmemfs object allocation failure
Hi Nirmoy, On Wed, Jul 27, 2022 at 07:40:23PM +0200, Nirmoy Das wrote: > From: Chris Wilson > > We report object allocation failures to userspace with ENOMEM, yet we > still show the memory warning after failing to shrink device allocated > pages. While this warning is similar to other system page allocation > failures, it is superfluous to the ENOMEM provided directly to > userspace. > > v2: Add NOWARN in few more places from where we might return > ENOMEM to userspace. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4936 > Signed-off-by: Chris Wilson > Co-developed-by: Nirmoy Das > Signed-off-by: Nirmoy Das Reviewed-by: Andi Shyti Andi
Re: [Intel-gfx] [PATCH v2] drm/i915: disable pci resize on 32-bit machine
Hi Nirmoy,
On Wed, Jul 27, 2022 at 07:33:06PM +0200, Nirmoy Das wrote:
> PCI bar resize only works with 64 bit BAR so disable
> this on 32-bit machine and resolve below compilation error:
>
> drivers/gpu/drm/i915/gt/intel_region_lmem.c:94:23: error: result of
> comparison of constant 4294967296 with expression of type
> 'resource_size_t' (aka 'unsigned int') is always false
> [-Werror,-Wtautological-constant-out-of-range-compare]
> root_res->start > 0x1ull)
>
> Fixes: a91d1a17cd341 ("drm/i915: Add support for LMEM PCIe resizable bar")
> Reported-by: Linux Kernel Functional Testing
> Tested-by: Linux Kernel Functional Testing
> Acked-by: Matthew Auld
> Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
Andi
PS You forgot to CC the author of the patch you are fixing
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Suppress oom warning for shmemfs object allocation failure (rev4)
== Series Details ==
Series: drm/i915: Suppress oom warning for shmemfs object allocation failure
(rev4)
URL : https://patchwork.freedesktop.org/series/106528/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106528v4
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/index.html
Participating hosts (38 -> 40)
--
Additional (4): fi-kbl-soraka fi-hsw-4770 bat-jsl-1 bat-adlp-4
Missing(2): fi-bdw-samus bat-jsl-3
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_106528v4:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@workarounds:
- {bat-adlp-6}: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
Known issues
Here are the changes found in Patchwork_106528v4 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_gttfill@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +8 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@verify-random:
- bat-adlp-4: NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/bat-adlp-4/igt@gem_lmem_swapp...@verify-random.html
* igt@gem_tiled_pread_basic:
- bat-adlp-4: NOTRUN -> [SKIP][7] ([i915#3282])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/bat-adlp-4/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#3012])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@gem:
- fi-blb-e6850: [PASS][9] -> [DMESG-FAIL][10] ([i915#4528])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-blb-e6850/igt@i915_selftest@l...@gem.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/fi-blb-e6850/igt@i915_selftest@l...@gem.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][11] ([i915#1886])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][12] ([i915#4785])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][13] ([i915#4116])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/fi-kbl-soraka/igt@i915_selftest@l...@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-adlp-4: NOTRUN -> [SKIP][14] ([i915#5903])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/bat-adlp-4/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271]) +9 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-pnv-d510:NOTRUN -> [SKIP][16] ([fdo#109271])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +7
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
- bat-adlp-4: NOTRUN -> [SKIP][18] ([fdo#111827]) +8 similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106528v4/bat-adlp-4/igt@kms_chamel...@dp-crc-fast.html
*
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Suppress oom warning for shmemfs object allocation failure (rev4)
== Series Details == Series: drm/i915: Suppress oom warning for shmemfs object allocation failure (rev4) URL : https://patchwork.freedesktop.org/series/106528/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: disable pci resize on 32-bit machine (rev2)
== Series Details ==
Series: drm/i915: disable pci resize on 32-bit machine (rev2)
URL : https://patchwork.freedesktop.org/series/106708/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106708v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/index.html
Participating hosts (38 -> 38)
--
Additional (3): fi-hsw-4770 bat-jsl-1 bat-adlp-4
Missing(3): bat-dg2-8 fi-bdw-samus bat-jsl-3
Known issues
Here are the changes found in Patchwork_106708v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@verify-random:
- bat-adlp-4: NOTRUN -> [SKIP][1] ([i915#4613]) +3 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/bat-adlp-4/igt@gem_lmem_swapp...@verify-random.html
* igt@gem_tiled_pread_basic:
- bat-adlp-4: NOTRUN -> [SKIP][2] ([i915#3282])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/bat-adlp-4/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#3012])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][4] ([i915#4785])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-adlp-4: NOTRUN -> [SKIP][5] ([i915#5903])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/bat-adlp-4/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271]) +9 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +7
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
- bat-adlp-4: NOTRUN -> [SKIP][8] ([fdo#111827]) +8 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/bat-adlp-4/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-adlp-4: NOTRUN -> [SKIP][9] ([i915#4103])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/bat-adlp-4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-adlp-4: NOTRUN -> [SKIP][10] ([i915#4093]) +3 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/bat-adlp-4/igt@kms_force_connector_ba...@prune-stale-modes.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#1072]) +3
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-adlp-4: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#4579])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/bat-adlp-4/igt@kms_setm...@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- bat-adlp-4: NOTRUN -> [SKIP][13] ([fdo#109295] / [i915#3301] /
[i915#3708])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/bat-adlp-4/igt@prime_v...@basic-userptr.html
* igt@prime_vgem@basic-write:
- bat-adlp-4: NOTRUN -> [SKIP][14] ([fdo#109295] / [i915#3291] /
[i915#3708]) +2 similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/bat-adlp-4/igt@prime_v...@basic-write.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][15] ([i915#5594] / [i915#6246])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/fi-hsw-4770/igt@run...@aborted.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- fi-kbl-guc: [FAIL][16] ([i915#6253]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-kbl-guc/igt@debugfs_test@read_all_entries.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/fi-kbl-guc/igt@debugfs_test@read_all_entries.html
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][18] ([i915#2582]) -> [PASS][19] +4 similar
issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-rpls-2/igt@fb...@read.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106708v2/bat-rpls-2/igt@fb...@read.html
*
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: stop using swiotlb (rev6)
== Series Details == Series: drm/i915: stop using swiotlb (rev6) URL : https://patchwork.freedesktop.org/series/106589/ State : success == Summary == CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106589v6 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/index.html Participating hosts (38 -> 40) -- Additional (3): fi-hsw-4770 bat-jsl-1 bat-adlp-4 Missing(1): fi-bdw-samus Known issues Here are the changes found in Patchwork_106589v6 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@verify-random: - bat-adlp-4: NOTRUN -> [SKIP][1] ([i915#4613]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/bat-adlp-4/igt@gem_lmem_swapp...@verify-random.html * igt@gem_tiled_pread_basic: - bat-adlp-4: NOTRUN -> [SKIP][2] ([i915#3282]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/bat-adlp-4/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#3012]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rpm@module-reload: - fi-cfl-8109u: [PASS][4] -> [DMESG-FAIL][5] ([i915#62]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-cfl-8109u/igt@i915_pm_...@module-reload.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/fi-cfl-8109u/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:NOTRUN -> [INCOMPLETE][6] ([i915#4785]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@requests: - fi-blb-e6850: [PASS][7] -> [DMESG-FAIL][8] ([i915#4528]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-blb-e6850/igt@i915_selftest@l...@requests.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/fi-blb-e6850/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@ring_submission: - fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#5904]) +29 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html * igt@i915_suspend@basic-s2idle-without-i915: - fi-cfl-8109u: [PASS][11] -> [DMESG-WARN][12] ([i915#5904] / [i915#62]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html * igt@i915_suspend@basic-s3-without-i915: - bat-adlp-4: NOTRUN -> [SKIP][13] ([i915#5903]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/bat-adlp-4/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271]) +9 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-pnv-d510:NOTRUN -> [SKIP][15] ([fdo#109271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-hsw-4770:NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +7 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html - bat-adlp-4: NOTRUN -> [SKIP][17] ([fdo#111827]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/bat-adlp-4/igt@kms_chamel...@dp-crc-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - bat-adlp-4: NOTRUN -> [SKIP][18] ([i915#4103]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/bat-adlp-4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-adlp-4: NOTRUN -> [SKIP][19] ([i915#4093]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106589v6/bat-adlp-4/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_frontbuffer_tracking@basic: - fi-cfl-8109u: [PASS][20] -> [DMESG-WARN][21] ([i915#62]) +12 similar issues [20]:
Re: [Intel-gfx] [PATCH] drm/i915: Pass drm_i915_private struct instead of gt for gen11_gu_misc_irq_handler/ack()
On Tue, Jul 26, 2022 at 09:44:38AM -0700, Srivatsa, Anusha wrote:
> Thanks Tvrtko :)
> @Roper, Matthew D Did you have any other feedback on this patch?
Nope, looks fine to me. Thanks.
Reviewed-by: Matt Roper
>
> Anusha
>
> > -Original Message-
> > From: Tvrtko Ursulin
> > Sent: Tuesday, July 26, 2022 1:59 AM
> > To: Srivatsa, Anusha ; intel-
> > g...@lists.freedesktop.org; Ursulin, Tvrtko
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Pass drm_i915_private struct
> > instead of gt for gen11_gu_misc_irq_handler/ack()
> >
> >
> > On 25/07/2022 19:38, Srivatsa, Anusha wrote:
> > > @Ursulin, Tvrtko Is this wat you had in mind?
> >
> > Two functions aligned in prototype yes - but I left to you guys which
> > prototype is correct. AFAICT Matt looked and concluded i915 is correct so
> > that's good for me.
> >
> > Regards,
> >
> > Tvrtko
> >
> > >> -Original Message-
> > >> From: Srivatsa, Anusha
> > >> Sent: Thursday, July 21, 2022 3:51 PM
> > >> To: intel-gfx@lists.freedesktop.org
> > >> Cc: Srivatsa, Anusha ; Ursulin, Tvrtko
> > >> ; Roper, Matthew D
> > >>
> > >> Subject: [PATCH] drm/i915: Pass drm_i915_private struct instead of gt
> > >> for
> > >> gen11_gu_misc_irq_handler/ack()
> > >>
> > >> gen11_gu_misc_irq_handler() and gen11_gu_misc_ack() do nothing tile
> > >> specific.
> > >>
> > >> v2: gen11_gu_misc_irq_ack() tile agnostic like
> > >> gen11_gu_misc_irq_handler()
> > >> (Tvrtko)
> > >>
> > >> Cc: Tvrtko Ursulin
> > >> Cc: Matt Roper
> > >> Signed-off-by: Anusha Srivatsa
> > >> ---
> > >> drivers/gpu/drm/i915/i915_irq.c | 16
> > >> 1 file changed, 8 insertions(+), 8 deletions(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > >> b/drivers/gpu/drm/i915/i915_irq.c index 73cebc6aa650..eb37b6bacaac
> > >> 100644
> > >> --- a/drivers/gpu/drm/i915/i915_irq.c
> > >> +++ b/drivers/gpu/drm/i915/i915_irq.c
> > >> @@ -2653,9 +2653,9 @@ static irqreturn_t gen8_irq_handler(int irq,
> > >> void
> > >> *arg) }
> > >>
> > >> static u32
> > >> -gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
> > >> +gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32
> > >> +master_ctl)
> > >> {
> > >> -void __iomem * const regs = gt->uncore->regs;
> > >> +void __iomem * const regs = i915->uncore.regs;
> > >> u32 iir;
> > >>
> > >> if (!(master_ctl & GEN11_GU_MISC_IRQ)) @@ -2669,10 +2669,10
> > @@
> > >> gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl) }
> > >>
> > >> static void
> > >> -gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
> > >> +gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32
> > >> +iir)
> > >> {
> > >> if (iir & GEN11_GU_MISC_GSE)
> > >> -intel_opregion_asle_intr(gt->i915);
> > >> +intel_opregion_asle_intr(i915);
> > >> }
> > >>
> > >> static inline u32 gen11_master_intr_disable(void __iomem * const
> > >> regs) @@
> > >> -2736,11 +2736,11 @@ static irqreturn_t gen11_irq_handler(int irq,
> > >> void
> > >> *arg)
> > >> if (master_ctl & GEN11_DISPLAY_IRQ)
> > >> gen11_display_irq_handler(i915);
> > >>
> > >> -gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
> > >> +gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
> > >>
> > >> gen11_master_intr_enable(regs);
> > >>
> > >> -gen11_gu_misc_irq_handler(gt, gu_misc_iir);
> > >> +gen11_gu_misc_irq_handler(i915, gu_misc_iir);
> > >>
> > >> pmu_irq_stats(i915, IRQ_HANDLED);
> > >>
> > >> @@ -2801,11 +2801,11 @@ static irqreturn_t dg1_irq_handler(int irq,
> > >> void
> > >> *arg)
> > >> if (master_ctl & GEN11_DISPLAY_IRQ)
> > >> gen11_display_irq_handler(i915);
> > >>
> > >> -gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
> > >> +gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
> > >>
> > >> dg1_master_intr_enable(regs);
> > >>
> > >> -gen11_gu_misc_irq_handler(gt, gu_misc_iir);
> > >> +gen11_gu_misc_irq_handler(i915, gu_misc_iir);
> > >>
> > >> pmu_irq_stats(i915, IRQ_HANDLED);
> > >>
> > >> --
> > >> 2.25.1
> > >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: stop using swiotlb (rev6)
== Series Details == Series: drm/i915: stop using swiotlb (rev6) URL : https://patchwork.freedesktop.org/series/106589/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/d12+: Disable DMC handlers during loading/disabling the firmware
== Series Details ==
Series: series starting with [1/2] drm/i915/d12+: Disable DMC handlers during
loading/disabling the firmware
URL : https://patchwork.freedesktop.org/series/106767/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106767v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_106767v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_106767v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106767v1/index.html
Participating hosts (38 -> 39)
--
Additional (2): fi-kbl-soraka bat-jsl-1
Missing(1): fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_106767v1:
### IGT changes ###
Possible regressions
* igt@i915_module_load@load:
- fi-skl-6600u: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-skl-6600u/igt@i915_module_l...@load.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106767v1/fi-skl-6600u/igt@i915_module_l...@load.html
- fi-glk-j4005: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-glk-j4005/igt@i915_module_l...@load.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106767v1/fi-glk-j4005/igt@i915_module_l...@load.html
- fi-skl-guc: [PASS][5] -> [DMESG-WARN][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-skl-guc/igt@i915_module_l...@load.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106767v1/fi-skl-guc/igt@i915_module_l...@load.html
- fi-skl-6700k2: [PASS][7] -> [DMESG-WARN][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-skl-6700k2/igt@i915_module_l...@load.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106767v1/fi-skl-6700k2/igt@i915_module_l...@load.html
- fi-kbl-7567u: [PASS][9] -> [DMESG-WARN][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-kbl-7567u/igt@i915_module_l...@load.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106767v1/fi-kbl-7567u/igt@i915_module_l...@load.html
- fi-cfl-8700k: [PASS][11] -> [DMESG-WARN][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-cfl-8700k/igt@i915_module_l...@load.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106767v1/fi-cfl-8700k/igt@i915_module_l...@load.html
- fi-cfl-guc: [PASS][13] -> [DMESG-WARN][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-cfl-guc/igt@i915_module_l...@load.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106767v1/fi-cfl-guc/igt@i915_module_l...@load.html
- fi-glk-dsi: [PASS][15] -> [DMESG-WARN][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-glk-dsi/igt@i915_module_l...@load.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106767v1/fi-glk-dsi/igt@i915_module_l...@load.html
- fi-cfl-8109u: [PASS][17] -> [DMESG-WARN][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-cfl-8109u/igt@i915_module_l...@load.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106767v1/fi-cfl-8109u/igt@i915_module_l...@load.html
- fi-kbl-guc: [PASS][19] -> [DMESG-WARN][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-kbl-guc/igt@i915_module_l...@load.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106767v1/fi-kbl-guc/igt@i915_module_l...@load.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@workarounds:
- {bat-adlp-6}: [PASS][21] -> [DMESG-WARN][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106767v1/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
Known issues
Here are the changes found in Patchwork_106767v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@load:
- fi-kbl-soraka: NOTRUN -> [DMESG-WARN][23] ([i915#1982])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106767v1/fi-kbl-soraka/igt@i915_module_l...@load.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][24] -> [DMESG-FAIL][25] ([i915#4528])
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[25]:
[Intel-gfx] [PATCH 0/1] [CI] Bump DG2 DMC firmware to v2.07
The following changes since commit 150864a4d73e8c448eb1e2c68e65f07635fe1a66: amdgpu partially revert "amdgpu: update beige goby to release 22.20" (2022-07-25 14:16:04 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware dg2_dmc_2_07 for you to fetch changes up to 3ab394af47ab6b0139a3fa6a7b39564a4d18cb25: i915: Add DMC v2.07 for DG2 (2022-07-27 10:52:59 -0700) Anusha Srivatsa (1): i915: Add DMC v2.07 for DG2 WHENCE | 3 +++ i915/dg2_dmc_ver2_07.bin | Bin 0 -> 22488 bytes 2 files changed, 3 insertions(+) create mode 100644 i915/dg2_dmc_ver2_07.bin -- 2.37.1
[Intel-gfx] [PATCH 1/1] drm/i915/dmc: Update DG2 DMC firmware to v2.07
The release notes mention that DMC v2.07 has a workaround for MMIO hang issue when DC States are enabled. Signed-off-by: Madhumitha Tolakanahalli Pradeep --- drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index fa9ef591b885..ed28107cbd12 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -52,8 +52,8 @@ #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE -#define DG2_DMC_PATH DMC_PATH(dg2, 2, 06) -#define DG2_DMC_VERSION_REQUIRED DMC_VERSION(2, 06) +#define DG2_DMC_PATH DMC_PATH(dg2, 2, 07) +#define DG2_DMC_VERSION_REQUIRED DMC_VERSION(2, 07) MODULE_FIRMWARE(DG2_DMC_PATH); #define ADLP_DMC_PATH DMC_PATH(adlp, 2, 16) -- 2.37.1
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915/d12+: Disable DMC handlers during loading/disabling the firmware
== Series Details == Series: series starting with [1/2] drm/i915/d12+: Disable DMC handlers during loading/disabling the firmware URL : https://patchwork.freedesktop.org/series/106767/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/display/intel_dmc.c:441: warning: Excess function parameter 'dev_priv' description in 'intel_dmc_disable_program' ./drivers/gpu/drm/i915/display/intel_dmc.c:441: warning: Function parameter or member 'i915' not described in 'intel_dmc_disable_program' ./drivers/gpu/drm/i915/display/intel_dmc.c:441: warning: Excess function parameter 'dev_priv' description in 'intel_dmc_disable_program'
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ttm: don't leak the ccs state
== Series Details ==
Series: drm/i915/ttm: don't leak the ccs state
URL : https://patchwork.freedesktop.org/series/106765/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106765v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/index.html
Participating hosts (38 -> 39)
--
Additional (3): fi-hsw-4770 bat-jsl-1 bat-adlp-4
Missing(2): fi-bdw-samus bat-jsl-3
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_106765v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@objects:
- {bat-rpls-1}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/bat-rpls-1/igt@i915_selftest@l...@objects.html
Known issues
Here are the changes found in Patchwork_106765v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@verify-random:
- bat-adlp-4: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/bat-adlp-4/igt@gem_lmem_swapp...@verify-random.html
* igt@gem_tiled_pread_basic:
- bat-adlp-4: NOTRUN -> [SKIP][3] ([i915#3282])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/bat-adlp-4/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#3012])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][5] ([i915#4785])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- fi-ivb-3770:[PASS][6] -> [INCOMPLETE][7] ([i915#3303] /
[i915#5370])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][8] -> [DMESG-FAIL][9] ([i915#4528])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@ring_submission:
- fi-cfl-8109u: [PASS][10] -> [DMESG-WARN][11] ([i915#5904]) +29
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u: [PASS][12] -> [DMESG-WARN][13] ([i915#5904] /
[i915#62])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-adlp-4: NOTRUN -> [SKIP][14] ([i915#5903])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/bat-adlp-4/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271]) +9 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +7
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
- bat-adlp-4: NOTRUN -> [SKIP][17] ([fdo#111827]) +8 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/bat-adlp-4/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-adlp-4: NOTRUN -> [SKIP][18] ([i915#4103])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106765v1/bat-adlp-4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-adlp-4: NOTRUN -> [SKIP][19] ([i915#4093]) +3 similar issues
[19]:
[Intel-gfx] [PATCH] drm/i915: Suppress oom warning for shmemfs object allocation failure
From: Chris Wilson We report object allocation failures to userspace with ENOMEM, yet we still show the memory warning after failing to shrink device allocated pages. While this warning is similar to other system page allocation failures, it is superfluous to the ENOMEM provided directly to userspace. v2: Add NOWARN in few more places from where we might return ENOMEM to userspace. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4936 Signed-off-by: Chris Wilson Co-developed-by: Nirmoy Das Signed-off-by: Nirmoy Das --- drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c index 4eed3dd90ba8..f42ca1179f37 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c @@ -75,7 +75,7 @@ int shmem_sg_alloc_table(struct drm_i915_private *i915, struct sg_table *st, if (size > resource_size(>region)) return -ENOMEM; - if (sg_alloc_table(st, page_count, GFP_KERNEL)) + if (sg_alloc_table(st, page_count, GFP_KERNEL | __GFP_NOWARN)) return -ENOMEM; /* @@ -137,7 +137,7 @@ int shmem_sg_alloc_table(struct drm_i915_private *i915, struct sg_table *st, * trigger the out-of-memory killer and for * this we want __GFP_RETRY_MAYFAIL. */ - gfp |= __GFP_RETRY_MAYFAIL; + gfp |= __GFP_RETRY_MAYFAIL | __GFP_NOWARN; } } while (1); @@ -209,7 +209,7 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj) GEM_BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); rebuild_st: - st = kmalloc(sizeof(*st), GFP_KERNEL); + st = kmalloc(sizeof(*st), GFP_KERNEL | __GFP_NOWARN); if (!st) return -ENOMEM; -- 2.35.1
[Intel-gfx] [PATCH v2] drm/i915: disable pci resize on 32-bit machine
PCI bar resize only works with 64 bit BAR so disable
this on 32-bit machine and resolve below compilation error:
drivers/gpu/drm/i915/gt/intel_region_lmem.c:94:23: error: result of
comparison of constant 4294967296 with expression of type
'resource_size_t' (aka 'unsigned int') is always false
[-Werror,-Wtautological-constant-out-of-range-compare]
root_res->start > 0x1ull)
Fixes: a91d1a17cd341 ("drm/i915: Add support for LMEM PCIe resizable bar")
Reported-by: Linux Kernel Functional Testing
Tested-by: Linux Kernel Functional Testing
Acked-by: Matthew Auld
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 6e90032e12e9..aa6aed837194 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -15,6 +15,7 @@
#include "gt/intel_gt_mcr.h"
#include "gt/intel_gt_regs.h"
+#ifdef CONFIG_64BIT
static void _release_bars(struct pci_dev *pdev)
{
int resno;
@@ -111,6 +112,9 @@ static void i915_resize_lmem_bar(struct drm_i915_private
*i915, resource_size_t
pci_assign_unassigned_bus_resources(pdev->bus);
pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
}
+#else
+static void i915_resize_lmem_bar(struct drm_i915_private *i915,
resource_size_t lmem_size) {}
+#endif
static int
region_lmem_release(struct intel_memory_region *mem)
--
2.35.1
Re: [Intel-gfx] [PATCH] drm/i915: disable pci resize on 32-bit machine
On 7/27/2022 6:58 PM, Matthew Auld wrote:
On 26/07/2022 09:32, Nirmoy Das wrote:
PCI bar resize only works with 64 bit BAR so disable
this on 32-bit machine.
Maybe also mention somewhere that this is just to fix a compiler
warning with the 0x1ull being out-of-range with
resource_size_t on 32bit?
Yes, sounds good. I will resend with a comment.
Nirmoy
Acked-by: Matthew Auld
Fixes: a91d1a17cd341 ("drm/i915: Add support for LMEM PCIe resizable
bar")
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 6e90032e12e9..aa6aed837194 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -15,6 +15,7 @@
#include "gt/intel_gt_mcr.h"
#include "gt/intel_gt_regs.h"
+#ifdef CONFIG_64BIT
static void _release_bars(struct pci_dev *pdev)
{
int resno;
@@ -111,6 +112,9 @@ static void i915_resize_lmem_bar(struct
drm_i915_private *i915, resource_size_t
pci_assign_unassigned_bus_resources(pdev->bus);
pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
}
+#else
+static void i915_resize_lmem_bar(struct drm_i915_private *i915,
resource_size_t lmem_size) {}
+#endif
static int
region_lmem_release(struct intel_memory_region *mem)
Re: [Intel-gfx] [PATCH] drm/i915: disable pci resize on 32-bit machine
On 26/07/2022 09:32, Nirmoy Das wrote:
PCI bar resize only works with 64 bit BAR so disable
this on 32-bit machine.
Maybe also mention somewhere that this is just to fix a compiler warning
with the 0x1ull being out-of-range with resource_size_t on 32bit?
Acked-by: Matthew Auld
Fixes: a91d1a17cd341 ("drm/i915: Add support for LMEM PCIe resizable bar")
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 6e90032e12e9..aa6aed837194 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -15,6 +15,7 @@
#include "gt/intel_gt_mcr.h"
#include "gt/intel_gt_regs.h"
+#ifdef CONFIG_64BIT
static void _release_bars(struct pci_dev *pdev)
{
int resno;
@@ -111,6 +112,9 @@ static void i915_resize_lmem_bar(struct drm_i915_private
*i915, resource_size_t
pci_assign_unassigned_bus_resources(pdev->bus);
pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
}
+#else
+static void i915_resize_lmem_bar(struct drm_i915_private *i915,
resource_size_t lmem_size) {}
+#endif
static int
region_lmem_release(struct intel_memory_region *mem)
[Intel-gfx] [PATCH 2/2] drm/i915/d13: Add Wa_16015201720 disabling clock gating for PIPEDMC-A/B
Add a workaround making sure that PIPEDMC-A/B is enabled when the
firmware needs these on D13 platforms to save/restore the registers
backed by the PW_1 and PW_A power wells.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
drivers/gpu/drm/i915/i915_reg.h| 7 +++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 22f65a9968c6a..13aaa3247a5a8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1615,6 +1615,14 @@ static void icl_display_core_init(struct
drm_i915_private *dev_priv,
intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
PCH_DPMGUNIT_CLOCK_GATE_DISABLE);
+ /* Wa_16015201720:adl-p,dg2 */
+ if (DISPLAY_VER(dev_priv) == 13) {
+ intel_de_rmw(dev_priv, CLKGATE_DIS_PSL_EXT(PIPE_A),
+0, PIPEDMC_GATING_DIS);
+ intel_de_rmw(dev_priv, CLKGATE_DIS_PSL_EXT(PIPE_B),
+0, PIPEDMC_GATING_DIS);
+ }
+
/* 1. Enable PCH reset handshake. */
intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3168d7007e101..bf5c39d9f9530 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1916,6 +1916,13 @@
#define CLKGATE_DIS_PSL(pipe) \
_MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
+#define _CLKGATE_DIS_PSL_EXT_A 0x4654C
+#define _CLKGATE_DIS_PSL_EXT_B 0x46550
+#define PIPEDMC_GATING_DIS REG_BIT(12)
+
+#define CLKGATE_DIS_PSL_EXT(pipe) \
+ _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)
+
/*
* Display engine regs
*/
--
2.34.1
[Intel-gfx] [PATCH 1/2] drm/i915/d12+: Disable DMC handlers during loading/disabling the firmware
Disable the DMC event handlers before loading the firmware and after
uninitializing the display, to make sure the firmware is inactive. This
matches the Bspec "Sequences for Display C5 and C6" page for GEN12+.
Add a TODO comment for doing the same on pre-GEN12 platforms.
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_power.c| 3 ++
drivers/gpu/drm/i915/display/intel_dmc.c | 52 ---
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
3 files changed, 50 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 589af257edebc..22f65a9968c6a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1433,6 +1433,7 @@ static void skl_display_core_uninit(struct
drm_i915_private *dev_priv)
return;
gen9_disable_dc_states(dev_priv);
+ /* TODO: disable DMC program */
gen9_dbuf_disable(dev_priv);
@@ -1500,6 +1501,7 @@ static void bxt_display_core_uninit(struct
drm_i915_private *dev_priv)
return;
gen9_disable_dc_states(dev_priv);
+ /* TODO: disable DMC program */
gen9_dbuf_disable(dev_priv);
@@ -1675,6 +1677,7 @@ static void icl_display_core_uninit(struct
drm_i915_private *dev_priv)
return;
gen9_disable_dc_states(dev_priv);
+ intel_dmc_disable_program(dev_priv);
/* 1. Disable all display engine functions -> aready done */
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index fa9ef591b8853..9ae62bb1184d5 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -277,6 +277,17 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
}
+static void disable_event_handler(struct drm_i915_private *i915,
+ i915_reg_t ctl_reg, i915_reg_t htp_reg)
+{
+ intel_de_write(i915, ctl_reg,
+ REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
+ DMC_EVT_CTL_TYPE_EDGE_0_1) |
+ REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
+ DMC_EVT_CTL_EVENT_ID_FALSE));
+ intel_de_write(i915, htp_reg, 0);
+}
+
static void
disable_flip_queue_event(struct drm_i915_private *i915,
i915_reg_t ctl_reg, i915_reg_t htp_reg)
@@ -299,12 +310,7 @@ disable_flip_queue_event(struct drm_i915_private *i915,
return;
}
- intel_de_write(i915, ctl_reg,
- REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
- DMC_EVT_CTL_TYPE_EDGE_0_1) |
- REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
- DMC_EVT_CTL_EVENT_ID_FALSE));
- intel_de_write(i915, htp_reg, 0);
+ disable_event_handler(i915, ctl_reg, htp_reg);
}
static bool
@@ -356,6 +362,23 @@ disable_all_flip_queue_events(struct drm_i915_private
*i915)
}
}
+static void disable_all_event_handlers(struct drm_i915_private *i915)
+{
+ int id;
+
+ for (id = DMC_FW_MAIN; id < DMC_FW_MAX; id++) {
+ int handler;
+
+ if (!has_dmc_id_fw(i915, id))
+ continue;
+
+ for (handler = 0; handler < 8; handler++)
+ disable_event_handler(i915,
+ DMC_EVT_CTL(i915, id, handler),
+ DMC_EVT_HTP(i915, id, handler));
+ }
+}
+
/**
* intel_dmc_load_program() - write the firmware from memory to register.
* @dev_priv: i915 drm device.
@@ -372,6 +395,8 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
if (!intel_dmc_has_payload(dev_priv))
return;
+ disable_all_event_handlers(dev_priv);
+
assert_rpm_wakelock_held(_priv->runtime_pm);
preempt_disable();
@@ -405,6 +430,21 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
disable_all_flip_queue_events(dev_priv);
}
+/**
+ * intel_dmc_disable_program() - disable the firmware
+ * @dev_priv: i915 drm device
+ *
+ * Disable all event handlers in the firmware, making sure the firmware is
+ * inactive after the display is uninitialized.
+ */
+void intel_dmc_disable_program(struct drm_i915_private *i915)
+{
+ if (!intel_dmc_has_payload(i915))
+ return;
+
+ disable_all_event_handlers(i915);
+}
+
void assert_dmc_loaded(struct drm_i915_private *i915)
{
drm_WARN_ONCE(>drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
b/drivers/gpu/drm/i915/display/intel_dmc.h
index 41091aee3b47b..67e03315ef999 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++
[Intel-gfx] [PATCH] drm/i915/ttm: don't leak the ccs state
The kernel only manages the ccs state with lmem-only objects, however
the kernel should still take care not to leak the CCS state from the
previous user.
Fixes: 48760ffe923a ("drm/i915/gt: Clear compress metadata for Flat-ccs
objects")
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index a69b244f14d0..9a0814422ba4 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -708,7 +708,7 @@ intel_context_migrate_copy(struct intel_context *ce,
u8 src_access, dst_access;
struct i915_request *rq;
int src_sz, dst_sz;
- bool ccs_is_src;
+ bool ccs_is_src, overwrite_ccs;
int err;
GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
@@ -749,6 +749,8 @@ intel_context_migrate_copy(struct intel_context *ce,
get_ccs_sg_sgt(_ccs, bytes_to_cpy);
}
+ overwrite_ccs = HAS_FLAT_CCS(i915) && !ccs_bytes_to_cpy && dst_is_lmem;
+
src_offset = 0;
dst_offset = CHUNK_SZ;
if (HAS_64K_PAGES(ce->engine->i915)) {
@@ -852,6 +854,25 @@ intel_context_migrate_copy(struct intel_context *ce,
if (err)
goto out_rq;
ccs_bytes_to_cpy -= ccs_sz;
+ } else if (overwrite_ccs) {
+ err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
+ if (err)
+ goto out_rq;
+
+ /*
+* While we can't always restore/manage the CCS state,
+* we still need to ensure we don't leak the CCS state
+* from the previous user, so make sure we overwrite it
+* with something.
+*/
+ err = emit_copy_ccs(rq, dst_offset, INDIRECT_ACCESS,
+ dst_offset, DIRECT_ACCESS, len);
+ if (err)
+ goto out_rq;
+
+ err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
+ if (err)
+ goto out_rq;
}
/* Arbitration is re-enabled between requests. */
--
2.37.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: reduce TLB performance regressions
== Series Details == Series: drm/i915: reduce TLB performance regressions URL : https://patchwork.freedesktop.org/series/106758/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11946_full -> Patchwork_106758v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_106758v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_106758v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (13 -> 13) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_106758v1_full: ### IGT changes ### Possible regressions * igt@i915_pm_rpm@basic-pci-d3-state: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/shard-tglb2/igt@i915_pm_...@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/shard-tglb3/igt@i915_pm_...@basic-pci-d3-state.html New tests - New tests have been introduced between CI_DRM_11946_full and Patchwork_106758v1_full: ### New IGT tests (4) ### * igt@kms_sequence@get-forked@hdmi-a-4-pipe-a: - Statuses : 1 pass(s) - Exec time: [2.34] s * igt@kms_sequence@get-forked@hdmi-a-4-pipe-b: - Statuses : 1 pass(s) - Exec time: [2.25] s * igt@kms_sequence@get-forked@hdmi-a-4-pipe-c: - Statuses : 1 pass(s) - Exec time: [2.22] s * igt@kms_sequence@get-forked@hdmi-a-4-pipe-d: - Statuses : 1 pass(s) - Exec time: [2.23] s Known issues Here are the changes found in Patchwork_106758v1_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@psr2: - shard-iclb: [PASS][3] -> [SKIP][4] ([i915#658]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/shard-iclb2/igt@feature_discov...@psr2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/shard-iclb6/igt@feature_discov...@psr2.html * igt@gem_create@create-massive: - shard-glk: NOTRUN -> [DMESG-WARN][5] ([i915#4991]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/shard-glk2/igt@gem_cre...@create-massive.html - shard-kbl: NOTRUN -> [DMESG-WARN][6] ([i915#4991]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/shard-kbl4/igt@gem_cre...@create-massive.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#5784]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/shard-tglb7/igt@gem_...@unwedge-stress.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/shard-tglb1/igt@gem_...@unwedge-stress.html * igt@gem_exec_balancer@parallel-keep-submit-fence: - shard-iclb: [PASS][9] -> [SKIP][10] ([i915#4525]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/shard-iclb1/igt@gem_exec_balan...@parallel-keep-submit-fence.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/shard-iclb6/igt@gem_exec_balan...@parallel-keep-submit-fence.html * igt@gem_exec_fair@basic-none@rcs0: - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/shard-kbl7/igt@gem_exec_fair@basic-n...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/shard-kbl7/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: NOTRUN -> [FAIL][16] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_lmem_swapping@verify-ccs: - shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/shard-kbl4/igt@gem_lmem_swapp...@verify-ccs.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][18] ([i915#4991]) [18]:
Re: [Intel-gfx] [PATCH v2] drm/ttm: Fix dummy res NULL ptr deref bug
Hi Arunpravin, Às 02:30 de 27/07/22, Arunpravin Paneer Selvam escreveu: > Check the bo->resource value before accessing the resource > mem_type. > > v2: Fix commit description unwrapped warning > > > [ 40.191227][ T184] general protection fault, probably for non-canonical > address 0xdc02: [#1] SMP KASAN PTI > [ 40.192995][ T184] KASAN: null-ptr-deref in range > [0x0010-0x0017] > [ 40.194411][ T184] CPU: 1 PID: 184 Comm: systemd-udevd Not tainted > 5.19.0-rc4-00721-gb297c22b7070 #1 > [ 40.196063][ T184] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), > BIOS 1.16.0-debian-1.16.0-4 04/01/2014 > [ 40.199605][ T184] RIP: 0010:ttm_bo_validate+0x1b3/0x240 [ttm] > [ 40.200754][ T184] Code: e8 72 c5 ff ff 83 f8 b8 74 d4 85 c0 75 54 49 8b > 9e 58 01 00 00 48 b8 00 00 00 00 00 fc ff df 48 8d 7b 10 48 89 fa 48 c1 ea 03 > <0f> b6 04 02 84 c0 74 04 3c 03 7e 44 8b 53 10 31 c0 85 d2 0f 85 58 > [ 40.203685][ T184] RSP: 0018:c96df0c8 EFLAGS: 00010202 > [ 40.204630][ T184] RAX: dc00 RBX: RCX: > 11102f4bb71b > [ 40.205864][ T184] RDX: 0002 RSI: c96df208 RDI: > 0010 > [ 40.207102][ T184] RBP: 192dbe1a R08: c96df208 R09: > > [ 40.208394][ T184] R10: 88817a5f R11: 0001 R12: > c96df110 > [ 40.209692][ T184] R13: c96df0f0 R14: 88817a5db800 R15: > c96df208 > [ 40.210862][ T184] FS: 7f6b1d16e8c0() GS:88839d70() > knlGS: > [ 40.212250][ T184] CS: 0010 DS: ES: CR0: 80050033 > [ 40.213275][ T184] CR2: 55a1001d4ff0 CR3: 0001700f4000 CR4: > 06e0 > [ 40.214469][ T184] Call Trace: > [ 40.214974][ T184] > [ 40.215438][ T184] ? ttm_bo_bounce_temp_buffer+0x140/0x140 [ttm] > [ 40.216572][ T184] ? mutex_spin_on_owner+0x240/0x240 > [ 40.217456][ T184] ? drm_vma_offset_add+0xaa/0x100 [drm] > [ 40.218457][ T184] ttm_bo_init_reserved+0x3d6/0x540 [ttm] > [ 40.219410][ T184] ? shmem_get_inode+0x744/0x980 > [ 40.220231][ T184] ttm_bo_init_validate+0xb1/0x200 [ttm] > [ 40.221172][ T184] ? bo_driver_evict_flags+0x340/0x340 [drm_vram_helper] > [ 40.222530][ T184] ? ttm_bo_init_reserved+0x540/0x540 [ttm] > [ 40.223643][ T184] ? __do_sys_finit_module+0x11a/0x1c0 > [ 40.224654][ T184] ? __shmem_file_setup+0x102/0x280 > [ 40.234764][ T184] drm_gem_vram_create+0x305/0x480 [drm_vram_helper] > [ 40.235766][ T184] ? bo_driver_evict_flags+0x340/0x340 [drm_vram_helper] > [ 40.236846][ T184] ? __kasan_slab_free+0x108/0x180 > [ 40.237650][ T184] drm_gem_vram_fill_create_dumb+0x134/0x340 > [drm_vram_helper] > [ 40.238864][ T184] ? local_pci_probe+0xdf/0x180 > [ 40.239674][ T184] ? drmm_vram_helper_init+0x400/0x400 [drm_vram_helper] > [ 40.240826][ T184] drm_client_framebuffer_create+0x19c/0x400 [drm] > [ 40.241955][ T184] ? drm_client_buffer_delete+0x200/0x200 [drm] > [ 40.243001][ T184] ? drm_client_pick_crtcs+0x554/0xb80 [drm] > [ 40.244030][ T184] drm_fb_helper_generic_probe+0x23f/0x940 > [drm_kms_helper] > [ 40.245226][ T184] ? __cond_resched+0x1c/0xc0 > [ 40.245987][ T184] ? drm_fb_helper_memory_range_to_clip+0x180/0x180 > [drm_kms_helper] > [ 40.247316][ T184] ? mutex_unlock+0x80/0x100 > [ 40.248005][ T184] ? __mutex_unlock_slowpath+0x2c0/0x2c0 > [ 40.249083][ T184] drm_fb_helper_single_fb_probe+0x907/0xf00 > [drm_kms_helper] > [ 40.250314][ T184] ? drm_fb_helper_check_var+0x1180/0x1180 > [drm_kms_helper] > [ 40.251540][ T184] ? __cond_resched+0x1c/0xc0 > [ 40.252321][ T184] ? mutex_lock+0x9f/0x100 > [ 40.253062][ T184] __drm_fb_helper_initial_config_and_unlock+0xb9/0x2c0 > [drm_kms_helper] > [ 40.254394][ T184] drm_fbdev_client_hotplug+0x56f/0x840 [drm_kms_helper] > [ 40.255477][ T184] drm_fbdev_generic_setup+0x165/0x3c0 [drm_kms_helper] > [ 40.256607][ T184] bochs_pci_probe+0x6b7/0x900 [bochs] > [ 40.257515][ T184] ? _raw_spin_lock_irqsave+0x87/0x100 > [ 40.258312][ T184] ? bochs_hw_init+0x480/0x480 [bochs] > [ 40.259244][ T184] ? bochs_hw_init+0x480/0x480 [bochs] > [ 40.260186][ T184] local_pci_probe+0xdf/0x180 > [ 40.260928][ T184] pci_call_probe+0x15f/0x500 > [ 40.265798][ T184] ? _raw_spin_lock+0x81/0x100 > [ 40.266508][ T184] ? pci_pm_suspend_noirq+0x980/0x980 > [ 40.267322][ T184] ? pci_assign_irq+0x81/0x280 > [ 40.268096][ T184] ? pci_match_device+0x351/0x6c0 > [ 40.268883][ T184] ? kernfs_put+0x18/0x40 > [ 40.269611][ T184] pci_device_probe+0xee/0x240 > [ 40.270352][ T184] really_probe+0x435/0xa80 > [ 40.271021][ T184] __driver_probe_device+0x2ab/0x480 > [ 40.271828][ T184] driver_probe_device+0x49/0x140 > [ 40.272627][ T184] __driver_attach+0x1bd/0x4c0 > [ 40.273372][ T184] ? __device_attach_driver+0x240/0x240 >
Re: [Intel-gfx] [PATCH v3 5/6] drm/i915/gt: Batch TLB invalidations
Hi Mauro,
I think there are still some unanswered questions from Tvrtko on
this patch, am I right?
Andi
On Wed, Jul 27, 2022 at 02:29:55PM +0200, Mauro Carvalho Chehab wrote:
> From: Chris Wilson
>
> Invalidate TLB in batches, in order to reduce performance regressions.
>
> Currently, every caller performs a full barrier around a TLB
> invalidation, ignoring all other invalidations that may have already
> removed their PTEs from the cache. As this is a synchronous operation
> and can be quite slow, we cause multiple threads to contend on the TLB
> invalidate mutex blocking userspace.
>
> We only need to invalidate the TLB once after replacing our PTE to
> ensure that there is no possible continued access to the physical
> address before releasing our pages. By tracking a seqno for each full
> TLB invalidate we can quickly determine if one has been performed since
> rewriting the PTE, and only if necessary trigger one for ourselves.
>
> That helps to reduce the performance regression introduced by TLB
> invalidate logic.
>
> [mchehab: rebased to not require moving the code to a separate file]
>
> Cc: sta...@vger.kernel.org
> Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
> Suggested-by: Tvrtko Ursulin
> Signed-off-by: Chris Wilson
> Cc: Fei Yang
> Signed-off-by: Mauro Carvalho Chehab
> ---
>
> To avoid mailbombing on a large number of people, only mailing lists were C/C
> on the cover.
> See [PATCH v3 0/6] at:
> https://lore.kernel.org/all/cover.1658924372.git.mche...@kernel.org/
>
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +-
> drivers/gpu/drm/i915/gem/i915_gem_pages.c | 21 +---
> drivers/gpu/drm/i915/gt/intel_gt.c| 53 ++-
> drivers/gpu/drm/i915/gt/intel_gt.h| 12 -
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 18 ++-
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 8 ++-
> drivers/gpu/drm/i915/i915_vma.c | 33 +---
> drivers/gpu/drm/i915/i915_vma.h | 1 +
> drivers/gpu/drm/i915/i915_vma_resource.c | 5 +-
> drivers/gpu/drm/i915/i915_vma_resource.h | 6 ++-
> 10 files changed, 125 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 5cf36a130061..9f6b14ec189a 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -335,7 +335,6 @@ struct drm_i915_gem_object {
> #define I915_BO_READONLY BIT(7)
> #define I915_TILING_QUIRK_BIT 8 /* unknown swizzling; do not release! */
> #define I915_BO_PROTECTED BIT(9)
> -#define I915_BO_WAS_BOUND_BIT 10
> /**
>* @mem_flags - Mutable placement-related flags
>*
> @@ -616,6 +615,8 @@ struct drm_i915_gem_object {
>* pages were last acquired.
>*/
> bool dirty:1;
> +
> + u32 tlb;
> } mm;
>
> struct {
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> index 6835279943df..8357dbdcab5c 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> @@ -191,6 +191,18 @@ static void unmap_object(struct drm_i915_gem_object
> *obj, void *ptr)
> vunmap(ptr);
> }
>
> +static void flush_tlb_invalidate(struct drm_i915_gem_object *obj)
> +{
> + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> + struct intel_gt *gt = to_gt(i915);
> +
> + if (!obj->mm.tlb)
> + return;
> +
> + intel_gt_invalidate_tlb(gt, obj->mm.tlb);
> + obj->mm.tlb = 0;
> +}
> +
> struct sg_table *
> __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
> {
> @@ -216,14 +228,7 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object
> *obj)
> __i915_gem_object_reset_page_iter(obj);
> obj->mm.page_sizes.phys = obj->mm.page_sizes.sg = 0;
>
> - if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, >flags)) {
> - struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct intel_gt *gt = to_gt(i915);
> - intel_wakeref_t wakeref;
> -
> - with_intel_gt_pm_if_awake(gt, wakeref)
> - intel_gt_invalidate_tlbs(gt);
> - }
> + flush_tlb_invalidate(obj);
>
> return pages;
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 5c55a90672f4..f435e06125aa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -38,8 +38,6 @@ static void __intel_gt_init_early(struct intel_gt *gt)
> {
> spin_lock_init(>irq_lock);
>
> - mutex_init(>tlb_invalidate_lock);
> -
> INIT_LIST_HEAD(>closed_vma);
> spin_lock_init(>closed_lock);
>
> @@ -50,6 +48,8 @@ static void __intel_gt_init_early(struct intel_gt *gt)
>
Re: [Intel-gfx] [PATCH v3 6/6] drm/i915/gt: describe the new tlb parameter at i915_vma_resource
Hi Mauro, > TLB cache invalidation can happen on two different situations: > > 1. synchronously, at __vma_put_pages(); > 2. asynchronously. > > On the first case, TLB cache invalidation happens inside > __vma_put_pages(). So, no need to do it later on. > > However, on the second case, the pages will keep in memory > until __i915_vma_evict() is called. > > So, we need to store the TLB data at struct i915_vma_resource, > in order to do a TLB cache invalidation before allowing > userspace to re-use the same memory. > > So, i915_vma_resource_unbind() has gained a new parameter > in order to store the TLB data at the second case. > > Document it. > > Signed-off-by: Mauro Carvalho Chehab > --- > > To avoid mailbombing on a large number of people, only mailing lists were C/C > on the cover. > See [PATCH v3 0/6] at: > https://lore.kernel.org/all/cover.1658924372.git.mche...@kernel.org/ > > drivers/gpu/drm/i915/i915_vma_resource.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_vma_resource.c > b/drivers/gpu/drm/i915/i915_vma_resource.c > index 5a67995ea5fe..4fe09ea0a825 100644 > --- a/drivers/gpu/drm/i915/i915_vma_resource.c > +++ b/drivers/gpu/drm/i915/i915_vma_resource.c > @@ -216,6 +216,10 @@ i915_vma_resource_fence_notify(struct i915_sw_fence > *fence, > /** > * i915_vma_resource_unbind - Unbind a vma resource > * @vma_res: The vma resource to unbind. > + * @tlb: pointer to vma->obj->mm.tlb associated with the resource > + *to be stored at vma_res->tlb. When not-NULL, it will be used > + *to do TLB cache invalidation before freeing a VMA resource. > + *used only for async unbind. /used/Used/ With that: Reviewed-by: Andi Shyti Thanks, Andi
Re: [Intel-gfx] [PATCH v3 2/6] drm/i915/gt: document with_intel_gt_pm_if_awake()
Hi Mauro, > Add a kernel-doc markup to document this new macro. > > Reviewed-by: Tvrtko Ursulin > Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Andi Shyti Andi
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: reduce TLB performance regressions
== Series Details ==
Series: drm/i915: reduce TLB performance regressions
URL : https://patchwork.freedesktop.org/series/106758/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106758v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/index.html
Participating hosts (38 -> 39)
--
Additional (2): fi-hsw-4770 bat-jsl-1
Missing(1): fi-bdw-samus
Known issues
Here are the changes found in Patchwork_106758v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600: NOTRUN -> [FAIL][1] ([fdo#103375])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#3012])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@gem:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][3] ([i915#4528])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/fi-pnv-d510/igt@i915_selftest@l...@gem.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][4] -> [DMESG-FAIL][5] ([i915#4528])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271]) +9 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-rkl-11600: NOTRUN -> [SKIP][7] ([fdo#111827])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/fi-rkl-11600/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [PASS][9] -> [FAIL][10] ([i915#6298])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#1072]) +3
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@runner@aborted:
- fi-blb-e6850: NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#2403] /
[i915#4312])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/fi-blb-e6850/igt@run...@aborted.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- fi-kbl-guc: [FAIL][13] ([i915#6253]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-kbl-guc/igt@debugfs_test@read_all_entries.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/fi-kbl-guc/igt@debugfs_test@read_all_entries.html
* igt@i915_selftest@live@gtt:
- {bat-dg2-9}:[DMESG-WARN][15] ([i915#5763]) -> [PASS][16] +3
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/bat-dg2-9/igt@i915_selftest@l...@gtt.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/bat-dg2-9/igt@i915_selftest@l...@gtt.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][17] ([i915#4528]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [INCOMPLETE][19] ([i915#5982]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11946/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106758v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_frontbuffer_tracking@basic:
- {bat-rpls-2}: [SKIP][21] ([i915#1849]) -> [PASS][22]
[21]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: reduce TLB performance regressions
== Series Details == Series: drm/i915: reduce TLB performance regressions URL : https://patchwork.freedesktop.org/series/106758/ State : warning == Summary == Error: dim checkpatch failed 735755e9d5d5 drm/i915/gt: Ignore TLB invalidations on idle engines -:138: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'gt' - possible side-effects? #138: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm.h:58: +#define with_intel_gt_pm_if_awake(gt, wf) \ + for (wf = intel_gt_pm_get_if_awake(gt); wf; intel_gt_pm_put_async(gt), wf = 0) -:138: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'wf' - possible side-effects? #138: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm.h:58: +#define with_intel_gt_pm_if_awake(gt, wf) \ + for (wf = intel_gt_pm_get_if_awake(gt); wf; intel_gt_pm_put_async(gt), wf = 0) total: 0 errors, 0 warnings, 2 checks, 99 lines checked 225d8336f971 drm/i915/gt: document with_intel_gt_pm_if_awake() 14c4636e0625 drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations 2bbb43b7f32b drm/i915/gt: Skip TLB invalidations once wedged 0cb17ababb41 drm/i915/gt: Batch TLB invalidations 051e0bf95aa1 drm/i915/gt: describe the new tlb parameter at i915_vma_resource
Re: [Intel-gfx] [PATCH v2 06/21] drm/i915/gt: Batch TLB invalidations
On 27/07/2022 12:48, Mauro Carvalho Chehab wrote:
On Wed, 20 Jul 2022 11:49:59 +0100
Tvrtko Ursulin wrote:
On 20/07/2022 08:13, Mauro Carvalho Chehab wrote:
On Mon, 18 Jul 2022 14:52:05 +0100
Tvrtko Ursulin wrote:
On 14/07/2022 13:06, Mauro Carvalho Chehab wrote:
From: Chris Wilson
Invalidate TLB in patch, in order to reduce performance regressions.
"in batches"?
Yeah. Will fix it.
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 tlb)
+{
+ /*
+* Before we release the pages that were bound by this vma, we
+* must invalidate all the TLBs that may still have a reference
+* back to our physical address. It only needs to be done once,
+* so after updating the PTE to point away from the pages, record
+* the most recent TLB invalidation seqno, and if we have not yet
+* flushed the TLBs upon release, perform a full invalidation.
+*/
+ WRITE_ONCE(tlb, intel_gt_next_invalidate_tlb_full(vm->gt));
Shouldn't tlb be a pointer for this to make sense?
Oh, my mistake! Will fix at the next version.
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index d8b94d638559..2da6c82a8bd2 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -206,8 +206,12 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
void ppgtt_unbind_vma(struct i915_address_space *vm,
struct i915_vma_resource *vma_res)
{
- if (vma_res->allocated)
- vm->clear_range(vm, vma_res->start, vma_res->vma_size);
+ if (!vma_res->allocated)
+ return;
+
+ vm->clear_range(vm, vma_res->start, vma_res->vma_size);
+ if (vma_res->tlb)
+ vma_invalidate_tlb(vm, *vma_res->tlb);
The patch is about more than batching? If there is a security hole in
this area (unbind) with the current code?
No, I don't think there's a security hole. The rationale for this is
not due to it.
In this case obvious question is why are these changes in the patch
which declares itself to be about batching invalidations? Because...
Because vma_invalidate_tlb() basically stores a TLB seqno, but the
actual invalidation is deferred to when the pages are unset, at
__i915_gem_object_unset_pages().
So, what happens is:
- on VMA sync mode, the need to invalidate TLB is marked at
__vma_put_pages(), before VMA unbind;
- on async, this is deferred to happen at ppgtt_unbind_vma(), where
it marks the need to invalidate TLBs.
On both cases, __i915_gem_object_unset_pages() is called later,
when the driver is ready to unmap the page.
Sorry still not clear to me why is the patch moving marking of the need
to invalidate (regardless if it a bit like today, or a seqno like in
this patch) from bind to unbind?
What if the seqno was stored in i915_vma_bind, where the bit is set
today, and all the hunks which touch the unbind and evict would
disappear from the patch. What wouldn't work in that case, if anything?
Regards,
Tvrtko
I am explaining why it looks to me that the patch is doing two things.
Implementing batching _and_ adding invalidation points at VMA unbind
sites, while so far we had it at backing store release only. Maybe I am
wrong and perhaps I am too slow to pick up on the explanation here.
So if the patch is doing two things please split it up.
I am further confused by the invalidation call site in evict and in
unbind - why there can't be one logical site since the logical sequence
is evict -> unbind.
The invalidation happens only on one place: __i915_gem_object_unset_pages().
Despite its name, vma_invalidate_tlb() just marks the need of doing TLB
invalidation.
Regards,
Mauro
[Intel-gfx] [PATCH v3 1/6] drm/i915/gt: Ignore TLB invalidations on idle engines
From: Chris Wilson
Check if the device is powered down prior to any engine activity,
as, on such cases, all the TLBs were already invalidated, so an
explicit TLB invalidation is not needed, thus reducing the
performance regression impact due to it.
This becomes more significant with GuC, as it can only do so when
the connection to the GuC is awake.
Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Signed-off-by: Chris Wilson
Cc: Fei Yang
Reviewed-by: Andi Shyti
Acked-by: Thomas Hellström
Acked-by: Tvrtko Ursulin
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v3 0/6] at:
https://lore.kernel.org/all/cover.1658924372.git.mche...@kernel.org/
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 10 ++
drivers/gpu/drm/i915/gt/intel_gt.c| 17 ++---
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 3 +++
3 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 97c820eee115..6835279943df 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -6,14 +6,15 @@
#include
+#include "gt/intel_gt.h"
+#include "gt/intel_gt_pm.h"
+
#include "i915_drv.h"
#include "i915_gem_object.h"
#include "i915_scatterlist.h"
#include "i915_gem_lmem.h"
#include "i915_gem_mman.h"
-#include "gt/intel_gt.h"
-
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages,
unsigned int sg_page_sizes)
@@ -217,10 +218,11 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object
*obj)
if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, >flags)) {
struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_gt *gt = to_gt(i915);
intel_wakeref_t wakeref;
- with_intel_runtime_pm_if_active(>runtime_pm, wakeref)
- intel_gt_invalidate_tlbs(to_gt(i915));
+ with_intel_gt_pm_if_awake(gt, wakeref)
+ intel_gt_invalidate_tlbs(gt);
}
return pages;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 68c2b0d8f187..c4d43da84d8e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -12,6 +12,7 @@
#include "i915_drv.h"
#include "intel_context.h"
+#include "intel_engine_pm.h"
#include "intel_engine_regs.h"
#include "intel_ggtt_gmch.h"
#include "intel_gt.h"
@@ -924,6 +925,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore = gt->uncore;
struct intel_engine_cs *engine;
+ intel_engine_mask_t awake, tmp;
enum intel_engine_id id;
const i915_reg_t *regs;
unsigned int num = 0;
@@ -947,26 +949,31 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
GEM_TRACE("\n");
- assert_rpm_wakelock_held(>runtime_pm);
-
mutex_lock(>tlb_invalidate_lock);
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
spin_lock_irq(>lock); /* serialise invalidate with GT reset */
+ awake = 0;
for_each_engine(engine, gt, id) {
struct reg_and_bit rb;
+ if (!intel_engine_pm_is_awake(engine))
+ continue;
+
rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
if (!i915_mmio_reg_offset(rb.reg))
continue;
intel_uncore_write_fw(uncore, rb.reg, rb.bit);
+ awake |= engine->mask;
}
spin_unlock_irq(>lock);
- for_each_engine(engine, gt, id) {
+ for_each_engine_masked(engine, gt, awake, tmp) {
+ struct reg_and_bit rb;
+
/*
* HW architecture suggest typical invalidation time at 40us,
* with pessimistic cases up to 100us and a recommendation to
@@ -974,12 +981,8 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
*/
const unsigned int timeout_us = 100;
const unsigned int timeout_ms = 4;
- struct reg_and_bit rb;
rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
- if (!i915_mmio_reg_offset(rb.reg))
- continue;
-
if (__intel_wait_for_register_fw(uncore,
rb.reg, rb.bit, 0,
timeout_us, timeout_ms,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index bc898df7a48c..a334787a4939 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++
[Intel-gfx] [PATCH v3 5/6] drm/i915/gt: Batch TLB invalidations
From: Chris Wilson
Invalidate TLB in batches, in order to reduce performance regressions.
Currently, every caller performs a full barrier around a TLB
invalidation, ignoring all other invalidations that may have already
removed their PTEs from the cache. As this is a synchronous operation
and can be quite slow, we cause multiple threads to contend on the TLB
invalidate mutex blocking userspace.
We only need to invalidate the TLB once after replacing our PTE to
ensure that there is no possible continued access to the physical
address before releasing our pages. By tracking a seqno for each full
TLB invalidate we can quickly determine if one has been performed since
rewriting the PTE, and only if necessary trigger one for ourselves.
That helps to reduce the performance regression introduced by TLB
invalidate logic.
[mchehab: rebased to not require moving the code to a separate file]
Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Suggested-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Cc: Fei Yang
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v3 0/6] at:
https://lore.kernel.org/all/cover.1658924372.git.mche...@kernel.org/
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 21 +---
drivers/gpu/drm/i915/gt/intel_gt.c| 53 ++-
drivers/gpu/drm/i915/gt/intel_gt.h| 12 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 18 ++-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 8 ++-
drivers/gpu/drm/i915/i915_vma.c | 33 +---
drivers/gpu/drm/i915/i915_vma.h | 1 +
drivers/gpu/drm/i915/i915_vma_resource.c | 5 +-
drivers/gpu/drm/i915/i915_vma_resource.h | 6 ++-
10 files changed, 125 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 5cf36a130061..9f6b14ec189a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -335,7 +335,6 @@ struct drm_i915_gem_object {
#define I915_BO_READONLY BIT(7)
#define I915_TILING_QUIRK_BIT 8 /* unknown swizzling; do not release! */
#define I915_BO_PROTECTED BIT(9)
-#define I915_BO_WAS_BOUND_BIT 10
/**
* @mem_flags - Mutable placement-related flags
*
@@ -616,6 +615,8 @@ struct drm_i915_gem_object {
* pages were last acquired.
*/
bool dirty:1;
+
+ u32 tlb;
} mm;
struct {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 6835279943df..8357dbdcab5c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -191,6 +191,18 @@ static void unmap_object(struct drm_i915_gem_object *obj,
void *ptr)
vunmap(ptr);
}
+static void flush_tlb_invalidate(struct drm_i915_gem_object *obj)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_gt *gt = to_gt(i915);
+
+ if (!obj->mm.tlb)
+ return;
+
+ intel_gt_invalidate_tlb(gt, obj->mm.tlb);
+ obj->mm.tlb = 0;
+}
+
struct sg_table *
__i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
{
@@ -216,14 +228,7 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object
*obj)
__i915_gem_object_reset_page_iter(obj);
obj->mm.page_sizes.phys = obj->mm.page_sizes.sg = 0;
- if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, >flags)) {
- struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct intel_gt *gt = to_gt(i915);
- intel_wakeref_t wakeref;
-
- with_intel_gt_pm_if_awake(gt, wakeref)
- intel_gt_invalidate_tlbs(gt);
- }
+ flush_tlb_invalidate(obj);
return pages;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5c55a90672f4..f435e06125aa 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -38,8 +38,6 @@ static void __intel_gt_init_early(struct intel_gt *gt)
{
spin_lock_init(>irq_lock);
- mutex_init(>tlb_invalidate_lock);
-
INIT_LIST_HEAD(>closed_vma);
spin_lock_init(>closed_lock);
@@ -50,6 +48,8 @@ static void __intel_gt_init_early(struct intel_gt *gt)
intel_gt_init_reset(gt);
intel_gt_init_requests(gt);
intel_gt_init_timelines(gt);
+ mutex_init(>tlb.invalidate_lock);
+ seqcount_mutex_init(>tlb.seqno, >tlb.invalidate_lock);
intel_gt_pm_init_early(gt);
intel_uc_init_early(>uc);
@@ -770,6 +770,7 @@ void intel_gt_driver_late_release_all(struct
drm_i915_private
[Intel-gfx] [PATCH v3 0/6] drm/i915: reduce TLB performance regressions
Doing TLB invalidation cause performance regressions, like: [424.370996] i915 :00:02.0: [drm] *ERROR* rcs0 TLB invalidation did not complete in 4ms! As reported at: https://gitlab.freedesktop.org/drm/intel/-/issues/6424 as this is an expensive operation. So, reduce the need of it by: - checking if the engine is awake; - checking if the engine is not wedged; - batching operations. Additionally, add a workaround for a known hardware issue on some GPUs. In order to double-check that this series won't be introducing any regressions, I used this new IGT test: https://patchwork.freedesktop.org/patch/495684/?series=106757=1 Checking the results for 3 different patchsets, on Broadwell: 1) On the top of drm-tip (2022y-07m-14d-08h-35m-36) - e. g. with TLB invalidation and serialization patches: $ sudo build/tests/gem_exec_tlb|grep Subtest Subtest close-clear: SUCCESS (10.490s) Subtest madv-clear: SUCCESS (10.484s) Subtest u-unmap-clear: SUCCESS (10.527s) Subtest u-shrink-clear: SUCCESS (10.506s) Subtest close-dumb: SUCCESS (10.165s) Subtest madv-dumb: SUCCESS (10.177s) Subtest u-unmap-dumb: SUCCESS (10.172s) Subtest u-shrink-dumb: SUCCESS (10.172s) 2) With the new version of the batch TLB invalidation patches from this series: $ sudo build/tests/gem_exec_tlb|grep Subtest Subtest close-clear: SUCCESS (10.483s) Subtest madv-clear: SUCCESS (10.495s) Subtest u-unmap-clear: SUCCESS (10.545s) Subtest u-shrink-clear: SUCCESS (10.508s) Subtest close-dumb: SUCCESS (10.172s) Subtest madv-dumb: SUCCESS (10.169s) Subtest u-unmap-dumb: SUCCESS (10.174s) Subtest u-shrink-dumb: SUCCESS (10.176s) 3) Changing the TLB invalidation routine to do nothing[1]: $ sudo ~/freedesktop-igt/build/tests/gem_exec_tlb|grep Subtest (gem_exec_tlb:1958) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1958) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1958) CRITICAL: Found deadbeef in a new (clear) buffer after 3 tries! (gem_exec_tlb:1956) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1956) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1956) CRITICAL: Found deadbeef in a new (clear) buffer after 89 tries! (gem_exec_tlb:1957) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1957) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1957) CRITICAL: Found deadbeef in a new (clear) buffer after 256 tries! (gem_exec_tlb:1960) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1960) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1960) CRITICAL: Found deadbeef in a new (clear) buffer after 845 tries! (gem_exec_tlb:1961) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1961) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1961) CRITICAL: Found deadbeef in a new (clear) buffer after 1138 tries! (gem_exec_tlb:1954) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1954) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1954) CRITICAL: Found deadbeef in a new (clear) buffer after 1359 tries! (gem_exec_tlb:1955) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1955) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1955) CRITICAL: Found deadbeef in a new (clear) buffer after 1794 tries! (gem_exec_tlb:1959) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1959) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1959) CRITICAL: Found deadbeef in a new (clear) buffer after 2139 tries! Dynamic subtest smem0 failed. DEBUG (gem_exec_tlb:1944) DEBUG: 2M hole:20 contains poison:6b6b6b6b (gem_exec_tlb:1944) DEBUG: Running writer for 20 at 30 on bcs0 (gem_exec_tlb:1944) DEBUG: Closing hole:20 on rcs0, sample:deadbeef (gem_exec_tlb:1944) DEBUG: Rechecking hole:20, sample:6b6b6b6b END Subtest close-clear: FAIL (10.434s) Subtest madv-clear: SUCCESS (10.479s) Subtest u-unmap-clear: SUCCESS (10.512s) In summary, the test does properly detect fail when TLB cache invalidation doesn't happen, as shown at result (3). It also shows that both current drm-tip and drm-tip with this series applied don't have TLB invalidation cache issues. [1] I applied this patch on the top of drm-tip: diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
