Re: [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members under display.pps
On Fri, 12 Aug 2022, "Murthy, Arun R" wrote:
>> -Original Message-
>> From: Intel-gfx On Behalf Of Jani
>> Nikula
>> Sent: Thursday, August 11, 2022 8:37 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; De Marchi, Lucas
>>
>> Subject: [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members
>> under display.pps
>>
>> Move display related members under drm_i915_private display sub-struct.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> .../gpu/drm/i915/display/intel_display_core.h | 7 +++
>> drivers/gpu/drm/i915/display/intel_pps.c | 48 +--
>> drivers/gpu/drm/i915/i915_driver.c| 2 +-
>> drivers/gpu/drm/i915/i915_drv.h | 5 --
>> drivers/gpu/drm/i915/i915_reg.h | 2 +-
>> 5 files changed, 33 insertions(+), 31 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index fe19d4f9a9ab..030ced4068bb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -101,6 +101,13 @@ struct intel_display {
>>
>> wait_queue_head_t wait_queue;
>> } gmbus;
>> +
>> + struct {
>> + u32 mmio_base;
>> +
>> + /* protects panel power sequencer state */
>> + struct mutex mutex;
>> + } pps;
>> };
> Again can this power related to be moved under a substruct intel_pm ?
The pps is pretty well separated from rest of pm, so feels wrong to
shove it together with pm. And again, intel_pm makes me think intel_pm.c
which is not purely display, and needs to be reorganized.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus members under display.gmbus
On Fri, 12 Aug 2022, "Murthy, Arun R" wrote:
>> -Original Message-
>> From: Intel-gfx On Behalf Of Jani
>> Nikula
>> Sent: Thursday, August 11, 2022 8:37 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; De Marchi, Lucas
>>
>> Subject: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus
>> members under display.gmbus
>>
>> Move display related members under drm_i915_private display sub-struct.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_cdclk.c| 6 +--
>> .../gpu/drm/i915/display/intel_display_core.h | 23 ++
>> drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_gmbus.c| 46 +--
>> drivers/gpu/drm/i915/i915_drv.h | 16 ---
>> drivers/gpu/drm/i915/i915_irq.c | 4 +-
>> drivers/gpu/drm/i915/i915_reg.h | 14 +++---
>> 7 files changed, 59 insertions(+), 52 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 6095f5800a2e..ea40c75c2986 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -2098,12 +2098,12 @@ static void intel_set_cdclk(struct
>> drm_i915_private *dev_priv,
>>* functions use cdclk. Not all platforms/ports do,
>>* but we'll lock them all for simplicity.
>>*/
>> - mutex_lock(&dev_priv->gmbus_mutex);
>> + mutex_lock(&dev_priv->display.gmbus.mutex);
>> for_each_intel_dp(&dev_priv->drm, encoder) {
>> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>
>> mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
>> - &dev_priv->gmbus_mutex);
>> + &dev_priv->display.gmbus.mutex);
>> }
>>
>> intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); @@ -2113,7
>> +2113,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
>>
>> mutex_unlock(&intel_dp->aux.hw_mutex);
>> }
>> - mutex_unlock(&dev_priv->gmbus_mutex);
>> + mutex_unlock(&dev_priv->display.gmbus.mutex);
>>
>> for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
>> struct intel_dp *intel_dp = enc_to_intel_dp(encoder); diff --
>> git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index 306584c038c9..fe19d4f9a9ab 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -6,7 +6,11 @@
>> #ifndef __INTEL_DISPLAY_CORE_H__
>> #define __INTEL_DISPLAY_CORE_H__
>>
>> +#include
>> #include
>> +#include
>> +
>> +#include "intel_gmbus.h"
>>
>> struct drm_i915_private;
>> struct intel_atomic_state;
>> @@ -78,6 +82,25 @@ struct intel_display {
>> /* Display internal color functions */
>> const struct intel_color_funcs *color;
>> } funcs;
>> +
>> + /* Grouping using anonymous structs. Keep sorted. */
>> + struct {
>> + /*
>> + * Base address of where the gmbus and gpio blocks are
>> located
>> + * (either on PCH or on SoC for platforms without PCH).
>> + */
>> + u32 mmio_base;
>> +
>> + /*
>> + * gmbus.mutex protects against concurrent usage of the
>> single
>> + * hw gmbus controller on different i2c buses.
>> + */
>> + struct mutex mutex;
>> +
>> + struct intel_gmbus *bus[GMBUS_NUM_PINS];
>> +
>> + wait_queue_head_t wait_queue;
>> + } gmbus;
>> };
>
> Can this be moved to struct intel_dp?
Well, no. The data here is shared across all of them.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 06/39] drm/i915: move wm_disp funcs to display.funcs
On Fri, 12 Aug 2022, "Murthy, Arun R" wrote:
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index 98c6ccdc9100..a6843ebcca5a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -8,6 +8,7 @@
>>
>> #include
>>
>> +struct drm_i915_private;
>> struct intel_atomic_state;
>> struct intel_cdclk_funcs;
>> struct intel_clock_gating_funcs;
>> @@ -31,6 +32,23 @@ struct intel_display_funcs {
>> void (*commit_modeset_enables)(struct intel_atomic_state *state);
>> };
>>
>> +/* functions used for watermark calcs for display. */ struct
>> +intel_wm_funcs {
>> + /* update_wm is for legacy wm management */
>> + void (*update_wm)(struct drm_i915_private *dev_priv);
>> + int (*compute_pipe_wm)(struct intel_atomic_state *state,
>> +struct intel_crtc *crtc);
>> + int (*compute_intermediate_wm)(struct intel_atomic_state *state,
>> +struct intel_crtc *crtc);
>> + void (*initial_watermarks)(struct intel_atomic_state *state,
>> +struct intel_crtc *crtc);
>> + void (*atomic_update_watermarks)(struct intel_atomic_state *state,
>> + struct intel_crtc *crtc);
>> + void (*optimize_watermarks)(struct intel_atomic_state *state,
>> + struct intel_crtc *crtc);
>> + int (*compute_global_watermarks)(struct intel_atomic_state *state);
>> };
>> +
>> struct intel_display {
>> /* Display functions */
>> struct {
>> @@ -48,6 +66,9 @@ struct intel_display {
>>
>> /* pm private clock gating functions */
>> const struct intel_clock_gating_funcs *clock_gating;
>> +
>> + /* pm display functions */
>> + const struct intel_wm_funcs *wm;
>> } funcs;
>
> Can the wm, dbuf, clock related move to a struct intel_pm ? which
> makes it more meaningful else again we end up creating a struct
> intel_display a long one like i915_private.
Well, I think the display wm/dbuf stuff also needs to be split from
intel_pm.c so it's not so clear cut. And for now, I'm keeping the
functions together.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to display.funcs
On Fri, 12 Aug 2022, Jani Nikula wrote:
> On Fri, 12 Aug 2022, "Murthy, Arun R" wrote:
>>> -Original Message-
>>> From: Intel-gfx On Behalf Of Jani
>>> Nikula
>>> Sent: Thursday, August 11, 2022 8:37 PM
>>> To: intel-gfx@lists.freedesktop.org
>>> Cc: Nikula, Jani ; De Marchi, Lucas
>>>
>>> Subject: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to
>>> display.funcs
>>>
>>> Move display related members under drm_i915_private display sub-struct.
>>>
>>> Rename struct i915_clock_gating_funcs to intel_clock_gating_funcs while at
>>> it.
>>>
>>> Signed-off-by: Jani Nikula
>>> ---
>>> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
>>> drivers/gpu/drm/i915/i915_drv.h | 4 --
>>> drivers/gpu/drm/i915/intel_pm.c | 58 +--
>>> 3 files changed, 33 insertions(+), 33 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>>> index ff76bd4079e4..98c6ccdc9100 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>>> @@ -10,6 +10,7 @@
>>>
>>> struct intel_atomic_state;
>>> struct intel_cdclk_funcs;
>>> +struct intel_clock_gating_funcs;
>>> struct intel_crtc;
>>> struct intel_crtc_state;
>>> struct intel_dpll_funcs;
>>> @@ -44,6 +45,9 @@ struct intel_display {
>>>
>>> /* irq display functions */
>>> const struct intel_hotplug_funcs *hotplug;
>>> +
>>> + /* pm private clock gating functions */
>>> + const struct intel_clock_gating_funcs *clock_gating;
>> Likewise having struct intel_display and all display related structs inside
>> this, can this stuct be moved to intel_pm?
>> This is more related to a pm!
>
> I'm undecided whether it's eventually better to group the functions
> together, or spread the functions by, uh, functionality.
>
> But I'm pretty sure I want to first group them like this, see how the
> *other* named and anonymous sub-structs of intel_display shape up, and
> spread them around if that feels like the right thing to do.
Also, this series is going to be a lot of refactoring, and I'm
constantly trying to *not* incorporate too many changes, and mostly just
stick to straightforward movement. There's a lot more that should be
done wrt actually hiding this stuff within modules (using opaque
pointers etc) instead of exposing all of the data to all of the
drivers. It just can't all be done at once. This is the first step.
BR,
Jani.
>
> BR,
> Jani.
>
>
>>
>> Thanks and Regards,
>> Arun R Murthy
>>
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to display.funcs
On Fri, 12 Aug 2022, "Murthy, Arun R" wrote:
>> -Original Message-
>> From: Intel-gfx On Behalf Of Jani
>> Nikula
>> Sent: Thursday, August 11, 2022 8:37 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; De Marchi, Lucas
>>
>> Subject: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to
>> display.funcs
>>
>> Move display related members under drm_i915_private display sub-struct.
>>
>> Rename struct i915_clock_gating_funcs to intel_clock_gating_funcs while at
>> it.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
>> drivers/gpu/drm/i915/i915_drv.h | 4 --
>> drivers/gpu/drm/i915/intel_pm.c | 58 +--
>> 3 files changed, 33 insertions(+), 33 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index ff76bd4079e4..98c6ccdc9100 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -10,6 +10,7 @@
>>
>> struct intel_atomic_state;
>> struct intel_cdclk_funcs;
>> +struct intel_clock_gating_funcs;
>> struct intel_crtc;
>> struct intel_crtc_state;
>> struct intel_dpll_funcs;
>> @@ -44,6 +45,9 @@ struct intel_display {
>>
>> /* irq display functions */
>> const struct intel_hotplug_funcs *hotplug;
>> +
>> + /* pm private clock gating functions */
>> + const struct intel_clock_gating_funcs *clock_gating;
> Likewise having struct intel_display and all display related structs inside
> this, can this stuct be moved to intel_pm?
> This is more related to a pm!
I'm undecided whether it's eventually better to group the functions
together, or spread the functions by, uh, functionality.
But I'm pretty sure I want to first group them like this, see how the
*other* named and anonymous sub-structs of intel_display shape up, and
spread them around if that feels like the right thing to do.
BR,
Jani.
>
> Thanks and Regards,
> Arun R Murthy
>
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 04/39] drm/i915: move hotplug_funcs to display.funcs
On Fri, 12 Aug 2022, "Murthy, Arun R" wrote: >> -Original Message- >> From: Intel-gfx On Behalf Of Jani >> Nikula >> Sent: Thursday, August 11, 2022 8:37 PM >> To: intel-gfx@lists.freedesktop.org >> Cc: Nikula, Jani ; De Marchi, Lucas >> >> Subject: [Intel-gfx] [PATCH 04/39] drm/i915: move hotplug_funcs to >> display.funcs >> >> Move display related members under drm_i915_private display sub-struct. >> > The commit msg becomes same for the patches. Can it be more precise as > to move all hotplug related struct under display sub-struct? Yeah, just copy-pasted for now. BR, Jani. > >> Signed-off-by: Jani Nikula >> --- > Upon adding proper commit msg > Reviewed-by: Arun R Murthy > > Thanks and Regards, > Arun R Murthy > -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 02/39] drm/i915: move cdclk_funcs to display.funcs
On Fri, 12 Aug 2022, "Murthy, Arun R" wrote:
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index aafe548875cc..74e4ae0609b9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -9,6 +9,7 @@
>> #include
>>
>> struct intel_atomic_state;
>> +struct intel_cdclk_funcs;
>> struct intel_crtc;
>> struct intel_crtc_state;
>> struct intel_initial_plane_config;
>> @@ -32,6 +33,9 @@ struct intel_display {
>> struct {
>> /* Top level crtc-ish functions */
>> const struct intel_display_funcs *crtc;
>> +
>> + /* Display CDCLK functions */
>> + const struct intel_cdclk_funcs *cdclk;
>
> Like having intel_cdclk_funcs *cdclk, will intel_display_funcs
> *display makes more sense and maintaining same terminology across the
> driver.
I was considering renaming it struct intel_crtc_funcs but it's not all
crtc either. But display is both too generic (these are *all* display
functions) and has a tautology (display.funcs.display). Dunno.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to drm_i915_private
On Fri, 12 Aug 2022, "Murthy, Arun R" wrote:
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -0,0 +1,38 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +#ifndef __INTEL_DISPLAY_CORE_H__
>> +#define __INTEL_DISPLAY_CORE_H__
>> +
>> +#include
>> +
>> +struct intel_atomic_state;
>> +struct intel_crtc;
>> +struct intel_crtc_state;
>> +struct intel_initial_plane_config;
>> +
>> +struct intel_display_funcs {
>> + /* Returns the active state of the crtc, and if the crtc is active,
>> + * fills out the pipe-config with the hw state. */
> Can this be changed to multi-line commenting style.
Yeah.
> /*
> *
> */
>> + bool (*get_pipe_config)(struct intel_crtc *,
>> + struct intel_crtc_state *);
>> + void (*get_initial_plane_config)(struct intel_crtc *,
>> + struct intel_initial_plane_config *);
>> + void (*crtc_enable)(struct intel_atomic_state *state,
>> + struct intel_crtc *crtc);
>> + void (*crtc_disable)(struct intel_atomic_state *state,
>> + struct intel_crtc *crtc);
>> + void (*commit_modeset_enables)(struct intel_atomic_state *state);
>
> Can this be changed to something meaningful word, something like
> update_modeset()
It's already borderline doing too much in one patch to rename the
struct, and definitely too much to rename the hook. Maybe in another
patch.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v4 00/41] DYNDBG: opt-in class'd debug for modules, use in drm.
On Thu, Aug 11, 2022 at 06:52:40PM +0200, Daniel Vetter wrote: > On Wed, Aug 03, 2022 at 04:13:05PM -0400, Jason Baron wrote: > > > > > > On 8/3/22 15:56, jim.cro...@gmail.com wrote: > > > On Wed, Jul 20, 2022 at 9:32 AM Jim Cromie wrote: > > >> > > > > > >> Hi Jason, Greg, DRM-folk, > > >> > > >> This adds 'typed' "class FOO" support to dynamic-debug, where 'typed' > > >> means either DISJOINT (like drm debug categories), or VERBOSE (like > > >> nouveau debug-levels). Use it in DRM modules: core, helpers, and in > > >> drivers i915, amdgpu, nouveau. > > >> > > > > > > This revision fell over, on a conflict with something in drm-MUMBLE > > > > > > Error: patch > > > https://urldefense.com/v3/__https://patchwork.freedesktop.org/api/1.0/series/106427/revisions/2/mbox/__;!!GjvTz_vk!UCPl5Uf32cDVwwysMTfaLwoGLWomargFXuR8HjBA3xsUOjxXHXC5hneAkP4iWK91yc-LjjJxWW89-51Z$ > > > > > > not applied > > > Applying: dyndbg: fix static_branch manipulation > > > Applying: dyndbg: fix module.dyndbg handling > > > Applying: dyndbg: show both old and new in change-info > > > Applying: dyndbg: reverse module walk in cat control > > > Applying: dyndbg: reverse module.callsite walk in cat control > > > Applying: dyndbg: use ESCAPE_SPACE for cat control > > > Applying: dyndbg: let query-modname override actual module name > > > Applying: dyndbg: add test_dynamic_debug module > > > Applying: dyndbg: drop EXPORTed dynamic_debug_exec_queries > > > > > > Jason, > > > those above are decent maintenance patches, particularly the drop export. > > > It would be nice to trim this unused api this cycle. > > > > Hi Jim, > > > > Agreed - I was thinking the same thing. Feel free to add > > Acked-by: Jason Baron to those first 9. > > Does Greg KH usually pick up dyndbg patches or someone else or do I need > to do something? Would be great to get some movement here since -rc1 goes > out and merging will restart next week. Yes, I can take these into my tree after -rc1 is out. thanks, greg k-h
Re: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under display.audio and display.funcs
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; De Marchi, Lucas
>
> Subject: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under
> display.audio and display.funcs
>
> Move display related members under drm_i915_private display sub-struct.
>
> Split audio funcs to display.funcs to follow the same pattern as all the other
> display functions.
>
Audio is a feature as such so wouldn't intel_audio struct stand parallel to
intel_display?
Thanks and Regards,
Arun R Murthy
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_audio.c| 96 +--
> .../gpu/drm/i915/display/intel_display_core.h | 26 +
> .../gpu/drm/i915/display/intel_lpe_audio.c| 42
> drivers/gpu/drm/i915/i915_driver.c| 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 26 -
> 5 files changed, 96 insertions(+), 96 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index 6c9ee905f132..a74fc79b7910 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -393,7 +393,7 @@ hsw_dp_audio_config_update(struct intel_encoder
> *encoder,
> const struct intel_crtc_state *crtc_state) {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct i915_audio_component *acomp = dev_priv-
> >audio.component;
> + struct i915_audio_component *acomp =
> +dev_priv->display.audio.component;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> enum port port = encoder->port;
> const struct dp_aud_n_m *nm;
> @@ -441,7 +441,7 @@ hsw_hdmi_audio_config_update(struct
> intel_encoder *encoder,
>const struct intel_crtc_state *crtc_state) {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct i915_audio_component *acomp = dev_priv-
> >audio.component;
> + struct i915_audio_component *acomp =
> +dev_priv->display.audio.component;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> enum port port = encoder->port;
> int n, rate;
> @@ -496,7 +496,7 @@ static void hsw_audio_codec_disable(struct
> intel_encoder *encoder,
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> u32 tmp;
>
> - mutex_lock(&dev_priv->audio.mutex);
> + mutex_lock(&dev_priv->display.audio.mutex);
>
> /* Disable timestamps */
> tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
> @@ -514,7 +514,7 @@ static void hsw_audio_codec_disable(struct
> intel_encoder *encoder,
> tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
> intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
>
> - mutex_unlock(&dev_priv->audio.mutex);
> + mutex_unlock(&dev_priv->display.audio.mutex);
> }
>
> static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
> @@ -639,7 +639,7 @@ static void hsw_audio_codec_enable(struct
> intel_encoder *encoder,
> u32 tmp;
> int len, i;
>
> - mutex_lock(&dev_priv->audio.mutex);
> + mutex_lock(&dev_priv->display.audio.mutex);
>
> /* Enable Audio WA for 4k DSC usecases */
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) @@ -677,7
> +677,7 @@ static void hsw_audio_codec_enable(struct intel_encoder
> *encoder,
> /* Enable timestamps */
> hsw_audio_config_update(encoder, crtc_state);
>
> - mutex_unlock(&dev_priv->audio.mutex);
> + mutex_unlock(&dev_priv->display.audio.mutex);
> }
>
> static void ilk_audio_codec_disable(struct intel_encoder *encoder, @@ -
> 814,7 +814,7 @@ void intel_audio_codec_enable(struct intel_encoder
> *encoder,
> const struct drm_connector_state *conn_state) {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct i915_audio_component *acomp = dev_priv-
> >audio.component;
> + struct i915_audio_component *acomp =
> +dev_priv->display.audio.component;
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_connector *connector = conn_state->connector;
> const struct drm_display_mode *adjusted_mode = @@ -838,17
> +838,17 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
>
> connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode)
> / 2;
>
> - if (dev_priv->audio.funcs)
> - dev_priv->audio.funcs->audio_codec_enable(encoder,
> - crtc_state,
> - conn_state);
> + if (dev_priv->display.funcs.audio)
> + dev_priv->display.funcs.audio-
> >audio_codec_enable(encoder,
> +
Re: [Intel-gfx] [PATCH 11/39] drm/i915: move dmc to display.dmc
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; De Marchi, Lucas
>
> Subject: [Intel-gfx] [PATCH 11/39] drm/i915: move dmc to display.dmc
>
> Move display related members under drm_i915_private display sub-struct.
>
> FIXME: dmc really needs to be abstracted and hidden inside intel_dmc.c with
> display.dmc turned into a pointer
>
> Signed-off-by: Jani Nikula
> ---
> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
> .../drm/i915/display/intel_display_power.c| 18 +++
> .../i915/display/intel_display_power_well.c | 18 +++
> drivers/gpu/drm/i915/display/intel_dmc.c | 52 +--
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 --
> 6 files changed, 49 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 030ced4068bb..ca22706e11e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -10,6 +10,7 @@
> #include
> #include
>
> +#include "intel_dmc.h"
> #include "intel_gmbus.h"
>
> struct drm_i915_private;
> @@ -108,6 +109,9 @@ struct intel_display {
> /* protects panel power sequencer state */
> struct mutex mutex;
> } pps;
> +
> + /* Grouping using named structs. Keep sorted. */
> + struct intel_dmc dmc;
Wouldn't it be better to skip this patch for now?
Anyway the patch has a FIXME so can up with a proper patch later and avoid
double work.
Thanks and Regards,
Arun R Murthy
Re: [Intel-gfx] [PATCH 0/4] Fix HFVSDB parsing
Hi Arun, You are right, I missed to add dri-devel here :( I had send this series to dri-devel again. Thanks & Regards, Ankit On 8/12/2022 9:01 AM, Murthy, Arun R wrote: I think this series will have to be posted to dri-devel as well. Thanks and Regards, Arun R Murthy --- -Original Message- From: Intel-gfx On Behalf Of Ankit Nautiyal Sent: Thursday, August 11, 2022 10:30 AM To: intel-gfx@lists.freedesktop.org Cc: Lankhorst, Maarten Subject: [Intel-gfx] [PATCH 0/4] Fix HFVSDB parsing Fix issues in HFVSDB parsing for DSC support. Also minor refactoring in Logging. Split from original patch into a new series. https://patchwork.freedesktop.org/patch/495193/ Ankit Nautiyal (4): drm/edid: Fix minimum bpc supported with DSC1.2 for HDMI sink drm/edid: Split DSC parsing into separate function drm/edid: Refactor HFVSDB parsing for DSC1.2 drm/edid: Avoid multiple log lines for HFVSDB parsing drivers/gpu/drm/drm_edid.c | 153 + 1 file changed, 87 insertions(+), 66 deletions(-) -- 2.25.1
Re: [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members under display.pps
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; De Marchi, Lucas
>
> Subject: [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members
> under display.pps
>
> Move display related members under drm_i915_private display sub-struct.
>
> Signed-off-by: Jani Nikula
> ---
> .../gpu/drm/i915/display/intel_display_core.h | 7 +++
> drivers/gpu/drm/i915/display/intel_pps.c | 48 +--
> drivers/gpu/drm/i915/i915_driver.c| 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 5 --
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 5 files changed, 33 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index fe19d4f9a9ab..030ced4068bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -101,6 +101,13 @@ struct intel_display {
>
> wait_queue_head_t wait_queue;
> } gmbus;
> +
> + struct {
> + u32 mmio_base;
> +
> + /* protects panel power sequencer state */
> + struct mutex mutex;
> + } pps;
> };
Again can this power related to be moved under a substruct intel_pm ?
Thanks and Regards
Arun R Murthy
Re: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus members under display.gmbus
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; De Marchi, Lucas
>
> Subject: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus
> members under display.gmbus
>
> Move display related members under drm_i915_private display sub-struct.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c| 6 +--
> .../gpu/drm/i915/display/intel_display_core.h | 23 ++
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
> drivers/gpu/drm/i915/display/intel_gmbus.c| 46 +--
> drivers/gpu/drm/i915/i915_drv.h | 16 ---
> drivers/gpu/drm/i915/i915_irq.c | 4 +-
> drivers/gpu/drm/i915/i915_reg.h | 14 +++---
> 7 files changed, 59 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 6095f5800a2e..ea40c75c2986 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2098,12 +2098,12 @@ static void intel_set_cdclk(struct
> drm_i915_private *dev_priv,
>* functions use cdclk. Not all platforms/ports do,
>* but we'll lock them all for simplicity.
>*/
> - mutex_lock(&dev_priv->gmbus_mutex);
> + mutex_lock(&dev_priv->display.gmbus.mutex);
> for_each_intel_dp(&dev_priv->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
> - &dev_priv->gmbus_mutex);
> + &dev_priv->display.gmbus.mutex);
> }
>
> intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); @@ -2113,7
> +2113,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
>
> mutex_unlock(&intel_dp->aux.hw_mutex);
> }
> - mutex_unlock(&dev_priv->gmbus_mutex);
> + mutex_unlock(&dev_priv->display.gmbus.mutex);
>
> for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder); diff --
> git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 306584c038c9..fe19d4f9a9ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -6,7 +6,11 @@
> #ifndef __INTEL_DISPLAY_CORE_H__
> #define __INTEL_DISPLAY_CORE_H__
>
> +#include
> #include
> +#include
> +
> +#include "intel_gmbus.h"
>
> struct drm_i915_private;
> struct intel_atomic_state;
> @@ -78,6 +82,25 @@ struct intel_display {
> /* Display internal color functions */
> const struct intel_color_funcs *color;
> } funcs;
> +
> + /* Grouping using anonymous structs. Keep sorted. */
> + struct {
> + /*
> + * Base address of where the gmbus and gpio blocks are
> located
> + * (either on PCH or on SoC for platforms without PCH).
> + */
> + u32 mmio_base;
> +
> + /*
> + * gmbus.mutex protects against concurrent usage of the
> single
> + * hw gmbus controller on different i2c buses.
> + */
> + struct mutex mutex;
> +
> + struct intel_gmbus *bus[GMBUS_NUM_PINS];
> +
> + wait_queue_head_t wait_queue;
> + } gmbus;
> };
Can this be moved to struct intel_dp?
Thanks and Regards,
Arun R Murthy
Re: [Intel-gfx] [PATCH 08/39] drm/i915: move color_funcs to display.funcs
> -Original Message- > From: Intel-gfx On Behalf Of Jani > Nikula > Sent: Thursday, August 11, 2022 8:37 PM > To: intel-gfx@lists.freedesktop.org > Cc: Nikula, Jani ; De Marchi, Lucas > > Subject: [Intel-gfx] [PATCH 08/39] drm/i915: move color_funcs to > display.funcs > > Move display related members under drm_i915_private display sub-struct. > > Signed-off-by: Jani Nikula > --- Reviewed-by: Arun R Murthy Thanks and Regards, Arun R Murthy
Re: [Intel-gfx] [PATCH 07/39] drm/i915: move fdi_funcs to display.funcs
> -Original Message- > From: Intel-gfx On Behalf Of Jani > Nikula > Sent: Thursday, August 11, 2022 8:37 PM > To: intel-gfx@lists.freedesktop.org > Cc: Nikula, Jani ; De Marchi, Lucas > > Subject: [Intel-gfx] [PATCH 07/39] drm/i915: move fdi_funcs to display.funcs > > Move display related members under drm_i915_private display sub-struct. > > Signed-off-by: Jani Nikula > --- Reviewed-by: Arun R Murthy Thanks and Regards, Arun R Murthy
Re: [Intel-gfx] [PATCH 06/39] drm/i915: move wm_disp funcs to display.funcs
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; De Marchi, Lucas
>
> Subject: [Intel-gfx] [PATCH 06/39] drm/i915: move wm_disp funcs to
> display.funcs
>
> Move display related members under drm_i915_private display sub-struct.
>
> Rename struct drm_i915_wm_disp_funcs to intel_wm_funcs while at it.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 34 +++
> .../gpu/drm/i915/display/intel_display_core.h | 21 ++
> drivers/gpu/drm/i915/i915_drv.h | 22 --
> drivers/gpu/drm/i915/intel_pm.c | 42 +--
> 4 files changed, 59 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 24ab1501beea..7db4ac27364d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -164,16 +164,16 @@ static void ilk_pfit_enable(const struct
> intel_crtc_state *crtc_state);
> */
> void intel_update_watermarks(struct drm_i915_private *dev_priv) {
> - if (dev_priv->wm_disp->update_wm)
> - dev_priv->wm_disp->update_wm(dev_priv);
> + if (dev_priv->display.funcs.wm->update_wm)
> + dev_priv->display.funcs.wm->update_wm(dev_priv);
> }
>
> static int intel_compute_pipe_wm(struct intel_atomic_state *state,
>struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - if (dev_priv->wm_disp->compute_pipe_wm)
> - return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
> + if (dev_priv->display.funcs.wm->compute_pipe_wm)
> + return dev_priv->display.funcs.wm-
> >compute_pipe_wm(state, crtc);
> return 0;
> }
>
> @@ -181,20 +181,20 @@ static int intel_compute_intermediate_wm(struct
> intel_atomic_state *state,
>struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - if (!dev_priv->wm_disp->compute_intermediate_wm)
> + if (!dev_priv->display.funcs.wm->compute_intermediate_wm)
> return 0;
> if (drm_WARN_ON(&dev_priv->drm,
> - !dev_priv->wm_disp->compute_pipe_wm))
> + !dev_priv->display.funcs.wm->compute_pipe_wm))
> return 0;
> - return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
> + return dev_priv->display.funcs.wm-
> >compute_intermediate_wm(state,
> +crtc);
> }
>
> static bool intel_initial_watermarks(struct intel_atomic_state *state,
>struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - if (dev_priv->wm_disp->initial_watermarks) {
> - dev_priv->wm_disp->initial_watermarks(state, crtc);
> + if (dev_priv->display.funcs.wm->initial_watermarks) {
> + dev_priv->display.funcs.wm->initial_watermarks(state, crtc);
> return true;
> }
> return false;
> @@ -204,23 +204,23 @@ static void intel_atomic_update_watermarks(struct
> intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - if (dev_priv->wm_disp->atomic_update_watermarks)
> - dev_priv->wm_disp->atomic_update_watermarks(state,
> crtc);
> + if (dev_priv->display.funcs.wm->atomic_update_watermarks)
> + dev_priv->display.funcs.wm-
> >atomic_update_watermarks(state, crtc);
> }
>
> static void intel_optimize_watermarks(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - if (dev_priv->wm_disp->optimize_watermarks)
> - dev_priv->wm_disp->optimize_watermarks(state, crtc);
> + if (dev_priv->display.funcs.wm->optimize_watermarks)
> + dev_priv->display.funcs.wm->optimize_watermarks(state,
> crtc);
> }
>
> static int intel_compute_global_watermarks(struct intel_atomic_state
> *state) {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - if (dev_priv->wm_disp->compute_global_watermarks)
> - return dev_priv->wm_disp-
> >compute_global_watermarks(state);
> + if (dev_priv->display.funcs.wm->compute_global_watermarks)
> + return dev_priv->display.funcs.wm-
> >compute_global_watermarks(state);
> return 0;
> }
>
> @@ -2400,7 +2400,7 @@ static void i9xx_crtc_disable(struct
> intel_atomic_state *state,
> if (DISPLAY_VER(dev_priv) != 2)
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
> false);
>
> - if (!dev_priv->wm_disp->initial_watermarks)
> +
Re: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to display.funcs
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; De Marchi, Lucas
>
> Subject: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to
> display.funcs
>
> Move display related members under drm_i915_private display sub-struct.
>
> Rename struct i915_clock_gating_funcs to intel_clock_gating_funcs while at
> it.
>
> Signed-off-by: Jani Nikula
> ---
> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
> drivers/gpu/drm/i915/i915_drv.h | 4 --
> drivers/gpu/drm/i915/intel_pm.c | 58 +--
> 3 files changed, 33 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index ff76bd4079e4..98c6ccdc9100 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -10,6 +10,7 @@
>
> struct intel_atomic_state;
> struct intel_cdclk_funcs;
> +struct intel_clock_gating_funcs;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_dpll_funcs;
> @@ -44,6 +45,9 @@ struct intel_display {
>
> /* irq display functions */
> const struct intel_hotplug_funcs *hotplug;
> +
> + /* pm private clock gating functions */
> + const struct intel_clock_gating_funcs *clock_gating;
Likewise having struct intel_display and all display related structs inside
this, can this stuct be moved to intel_pm?
This is more related to a pm!
Thanks and Regards,
Arun R Murthy
Re: [Intel-gfx] [PATCH 04/39] drm/i915: move hotplug_funcs to display.funcs
> -Original Message- > From: Intel-gfx On Behalf Of Jani > Nikula > Sent: Thursday, August 11, 2022 8:37 PM > To: intel-gfx@lists.freedesktop.org > Cc: Nikula, Jani ; De Marchi, Lucas > > Subject: [Intel-gfx] [PATCH 04/39] drm/i915: move hotplug_funcs to > display.funcs > > Move display related members under drm_i915_private display sub-struct. > The commit msg becomes same for the patches. Can it be more precise as to move all hotplug related struct under display sub-struct? > Signed-off-by: Jani Nikula > --- Upon adding proper commit msg Reviewed-by: Arun R Murthy Thanks and Regards, Arun R Murthy
Re: [Intel-gfx] [PATCH 03/39] drm/i915: move dpll_funcs to display.funcs
> -Original Message- > From: Intel-gfx On Behalf Of Jani > Nikula > Sent: Thursday, August 11, 2022 8:37 PM > To: intel-gfx@lists.freedesktop.org > Cc: Nikula, Jani ; De Marchi, Lucas > > Subject: [Intel-gfx] [PATCH 03/39] drm/i915: move dpll_funcs to display.funcs > > Move display related members under drm_i915_private display sub-struct. > > Signed-off-by: Jani Nikula > --- Reviewed-by: Arun R Murthy Thanks and Regards, Arun R Murthy
Re: [Intel-gfx] [PATCH 02/39] drm/i915: move cdclk_funcs to display.funcs
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; De Marchi, Lucas
>
> Subject: [Intel-gfx] [PATCH 02/39] drm/i915: move cdclk_funcs to
> display.funcs
>
> Move display related members under drm_i915_private display sub-struct.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c| 70 +--
> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
> drivers/gpu/drm/i915/i915_drv.h | 4 --
> 3 files changed, 39 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 86a22c3766e5..6095f5800a2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -79,26 +79,26 @@ struct intel_cdclk_funcs { void
> intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
> struct intel_cdclk_config *cdclk_config) {
> - dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config);
> + dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config);
> }
>
> static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> {
> - dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe);
> + dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config,
> +pipe);
> }
>
> static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
> struct intel_cdclk_state
> *cdclk_config) {
> - return dev_priv->cdclk_funcs->modeset_calc_cdclk(cdclk_config);
> + return
> +dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config);
> }
>
> static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
>int cdclk)
> {
> - return dev_priv->cdclk_funcs->calc_voltage_level(cdclk);
> + return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk);
> }
>
> static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, @@
> -2080,7 +2080,7 @@ static void intel_set_cdclk(struct drm_i915_private
> *dev_priv,
> if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
> return;
>
> - if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs-
> >set_cdclk))
> + if (drm_WARN_ON_ONCE(&dev_priv->drm,
> +!dev_priv->display.funcs.cdclk->set_cdclk))
> return;
>
> intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK
> to"); @@ -3187,78 +3187,78 @@ static const struct intel_cdclk_funcs
> i830_cdclk_funcs = { void intel_init_cdclk_hooks(struct drm_i915_private
> *dev_priv) {
> if (IS_DG2(dev_priv)) {
> - dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> dev_priv->cdclk.table = dg2_cdclk_table;
> } else if (IS_ALDERLAKE_P(dev_priv)) {
> - dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> /* Wa_22011320316:adl-p[a0] */
> if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> dev_priv->cdclk.table = adlp_a_step_cdclk_table;
> else
> dev_priv->cdclk.table = adlp_cdclk_table;
> } else if (IS_ROCKETLAKE(dev_priv)) {
> - dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> dev_priv->cdclk.table = rkl_cdclk_table;
> } else if (DISPLAY_VER(dev_priv) >= 12) {
> - dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (IS_JSL_EHL(dev_priv)) {
> - dev_priv->cdclk_funcs = &ehl_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (DISPLAY_VER(dev_priv) >= 11) {
> - dev_priv->cdclk_funcs = &icl_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
> - dev_priv->cdclk_funcs = &bxt_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
> if (IS_GEMINILAKE(dev_priv))
> dev_priv->cdclk.table = glk_cdclk_table;
> else
> dev_priv->cdclk.table = bxt_cdclk_table;
> } else if (DISPLAY_VER(dev_priv) == 9) {
> - dev_priv->cdclk_funcs = &skl_cdclk_funcs;
> + dev_priv->di
Re: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to drm_i915_private
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; De Marchi, Lucas
>
> Subject: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to
> drm_i915_private
>
> In another long-overdue cleanup, add a display sub-struct to
> drm_i915_private, and start moving display related members there. Start
> with display funcs that need a rename anyway to not collide with the new
> display member.
>
> Add a new header under display/ for defining struct intel_display.
>
> Rename struct drm_i915_display_funcs to intel_display_funcs while at it.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 28 +++---
> .../gpu/drm/i915/display/intel_display_core.h | 38 +++
> .../drm/i915/display/intel_modeset_setup.c| 2 +-
> .../drm/i915/display/intel_plane_initial.c| 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 21 ++
> 5 files changed, 57 insertions(+), 34 deletions(-) create mode 100644
> drivers/gpu/drm/i915/display/intel_display_core.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f143adefdf38..24ab1501beea 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4144,7 +4144,7 @@ bool intel_crtc_get_pipe_config(struct
> intel_crtc_state *crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>
> - if (!i915->display->get_pipe_config(crtc, crtc_state))
> + if (!i915->display.funcs.crtc->get_pipe_config(crtc, crtc_state))
> return false;
>
> crtc_state->hw.active = true;
> @@ -7119,7 +7119,7 @@ static void intel_enable_crtc(struct
> intel_atomic_state *state,
>
> intel_crtc_update_active_timings(new_crtc_state);
>
> - dev_priv->display->crtc_enable(state, crtc);
> + dev_priv->display.funcs.crtc->crtc_enable(state, crtc);
>
> if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
> return;
> @@ -7198,7 +7198,7 @@ static void intel_old_crtc_state_disables(struct
> intel_atomic_state *state,
>*/
> intel_crtc_disable_pipe_crc(crtc);
>
> - dev_priv->display->crtc_disable(state, crtc);
> + dev_priv->display.funcs.crtc->crtc_disable(state, crtc);
> crtc->active = false;
> intel_fbc_disable(crtc);
> intel_disable_shared_dpll(old_crtc_state);
> @@ -7586,7 +7586,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> }
>
> /* Now enable the clocks, plane, pipe, and connectors that we set
> up. */
> - dev_priv->display->commit_modeset_enables(state);
> + dev_priv->display.funcs.crtc->commit_modeset_enables(state);
>
> intel_encoders_update_complete(state);
>
> @@ -8317,7 +8317,7 @@ static const struct drm_mode_config_funcs
> intel_mode_funcs = {
> .atomic_state_free = intel_atomic_state_free, };
>
> -static const struct drm_i915_display_funcs skl_display_funcs = {
> +static const struct intel_display_funcs skl_display_funcs = {
> .get_pipe_config = hsw_get_pipe_config,
> .crtc_enable = hsw_crtc_enable,
> .crtc_disable = hsw_crtc_disable,
> @@ -8325,7 +8325,7 @@ static const struct drm_i915_display_funcs
> skl_display_funcs = {
> .get_initial_plane_config = skl_get_initial_plane_config, };
>
> -static const struct drm_i915_display_funcs ddi_display_funcs = {
> +static const struct intel_display_funcs ddi_display_funcs = {
> .get_pipe_config = hsw_get_pipe_config,
> .crtc_enable = hsw_crtc_enable,
> .crtc_disable = hsw_crtc_disable,
> @@ -8333,7 +8333,7 @@ static const struct drm_i915_display_funcs
> ddi_display_funcs = {
> .get_initial_plane_config = i9xx_get_initial_plane_config, };
>
> -static const struct drm_i915_display_funcs pch_split_display_funcs = {
> +static const struct intel_display_funcs pch_split_display_funcs = {
> .get_pipe_config = ilk_get_pipe_config,
> .crtc_enable = ilk_crtc_enable,
> .crtc_disable = ilk_crtc_disable,
> @@ -8341,7 +8341,7 @@ static const struct drm_i915_display_funcs
> pch_split_display_funcs = {
> .get_initial_plane_config = i9xx_get_initial_plane_config, };
>
> -static const struct drm_i915_display_funcs vlv_display_funcs = {
> +static const struct intel_display_funcs vlv_display_funcs = {
> .get_pipe_config = i9xx_get_pipe_config,
> .crtc_enable = valleyview_crtc_enable,
> .crtc_disable = i9xx_crtc_disable,
> @@ -8349,7 +8349,7 @@ static const struct drm_i915_display_funcs
> vlv_display_funcs = {
> .get_initial_plane_config = i9xx_get_initial_plane_config, };
>
> -static const struct drm_i915_display_funcs i9xx_display_funcs = {
> +static const struct intel_display_funcs i9xx_display_fun
Re: [Intel-gfx] [PATCH 0/4] Fix HFVSDB parsing
I think this series will have to be posted to dri-devel as well. Thanks and Regards, Arun R Murthy --- > -Original Message- > From: Intel-gfx On Behalf Of Ankit > Nautiyal > Sent: Thursday, August 11, 2022 10:30 AM > To: intel-gfx@lists.freedesktop.org > Cc: Lankhorst, Maarten > Subject: [Intel-gfx] [PATCH 0/4] Fix HFVSDB parsing > > Fix issues in HFVSDB parsing for DSC support. > Also minor refactoring in Logging. > > Split from original patch into a new series. > https://patchwork.freedesktop.org/patch/495193/ > > Ankit Nautiyal (4): > drm/edid: Fix minimum bpc supported with DSC1.2 for HDMI sink > drm/edid: Split DSC parsing into separate function > drm/edid: Refactor HFVSDB parsing for DSC1.2 > drm/edid: Avoid multiple log lines for HFVSDB parsing > > drivers/gpu/drm/drm_edid.c | 153 + > 1 file changed, 87 insertions(+), 66 deletions(-) > > -- > 2.25.1
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: add display sub-struct to drm_i915_private
== Series Details ==
Series: drm/i915: add display sub-struct to drm_i915_private
URL : https://patchwork.freedesktop.org/series/107170/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11983_full -> Patchwork_107170v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107170v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rc6_residency@rc6-idle@vecs0:
- {shard-rkl}:[PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-2/igt@i915_pm_rc6_residency@rc6-i...@vecs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-i...@vecs0.html
Known issues
Here are the changes found in Patchwork_107170v1_full that come from known
issues:
### CI changes ###
Issues hit
* boot:
- shard-glk: ([PASS][3], [PASS][4], [PASS][5], [PASS][6],
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12],
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18],
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24],
[PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30],
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36],
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42],
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48],
[PASS][49], [FAIL][50], [PASS][51]) ([i915#4392])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk1/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk1/boot.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk1/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk1/boot.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk2/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk2/boot.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk2/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk3/boot.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk3/boot.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk3/boot.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk5/boot.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk5/boot.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk5/boot.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk6/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk6/boot.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk6/boot.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk6/boot.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk7/boot.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk7/boot.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk8/boot.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk8/boot.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk8/boot.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk9/boot.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk9/boot.html
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk9/boot.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk1/boot.html
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk1/boot.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk1/boot.html
[31]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk9/boot.html
[32]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk9/boot.html
[33]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk9/boot.html
[34]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk8/boot.html
[35]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk8/boot.html
[36]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk7/boot.html
[37]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk7/boot.html
[38]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard
[Intel-gfx] ✗ Fi.CI.IGT: failure for Fixes KW issue for NULL pointer dereference
== Series Details == Series: Fixes KW issue for NULL pointer dereference URL : https://patchwork.freedesktop.org/series/107165/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11983_full -> Patchwork_107165v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_107165v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107165v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (13 -> 13) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_107165v1_full: ### IGT changes ### Possible regressions * igt@perf_pmu@interrupts: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-skl7/igt@perf_...@interrupts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/shard-skl9/igt@perf_...@interrupts.html Known issues Here are the changes found in Patchwork_107165v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +10 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl1/igt@gem_ctx_isolation@preservation...@vcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_ctx_persistence@engines-hang: - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/shard-snb7/igt@gem_ctx_persiste...@engines-hang.html * igt@gem_eio@unwedge-stress: - shard-iclb: [PASS][6] -> [TIMEOUT][7] ([i915#3070]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb6/igt@gem_...@unwedge-stress.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/shard-iclb3/igt@gem_...@unwedge-stress.html * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb1/igt@gem_exec_balan...@parallel-bb-first.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/shard-iclb5/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_fair@basic-none@rcs0: - shard-kbl: [PASS][10] -> [SKIP][11] ([fdo#109271]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl7/igt@gem_exec_fair@basic-n...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/shard-kbl4/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2849]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][14] -> [SKIP][15] ([i915#2190]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-tglb5/igt@gem_huc_c...@huc-copy.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/shard-tglb7/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@smem-oom: - shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/shard-apl6/igt@gem_lmem_swapp...@smem-oom.html * igt@gem_lmem_swapping@verify-random: - shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/shard-kbl1/igt@gem_lmem_swapp...@verify-random.html * igt@gen7_exec_parse@oacontrol-tracking: - shard-snb: NOTRUN -> [SKIP][18] ([fdo#109271]) +63 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/shard-snb7/igt@gen7_exec_pa...@oacontrol-tracking.html * igt@i915_suspend@basic-s2idle-without-i915: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-skl1/igt@i915_susp...@basic-s2idle-without-i915.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/shard-skl10/igt@i915_susp...@basic-s2idle-without-i915.html * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3886]) +4 similar
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: clear stalled request after a reset
== Series Details ==
Series: drm/i915/guc: clear stalled request after a reset
URL : https://patchwork.freedesktop.org/series/107181/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11985 -> Patchwork_107181v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/index.html
Participating hosts (36 -> 39)
--
Additional (3): bat-dg2-8 bat-dg2-10 fi-rkl-11600
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107181v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@core_hotunplug@unbind-rebind:
- {bat-dg2-10}: NOTRUN -> [DMESG-WARN][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/bat-dg2-10/igt@core_hotunp...@unbind-rebind.html
* igt@i915_selftest@live@gt_lrc:
- {bat-dg2-8}:NOTRUN -> [INCOMPLETE][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/bat-dg2-8/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@slpc:
- {bat-rplp-1}: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11985/bat-rplp-1/igt@i915_selftest@l...@slpc.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/bat-rplp-1/igt@i915_selftest@l...@slpc.html
Known issues
Here are the changes found in Patchwork_107181v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#2190])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-rkl-11600: NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/fi-rkl-11600/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_tiled_pread_basic:
- fi-rkl-11600: NOTRUN -> [SKIP][7] ([i915#3282])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600: NOTRUN -> [SKIP][8] ([i915#3012])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u: [PASS][9] -> [DMESG-FAIL][10] ([i915#62])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11985/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@ring_submission:
- fi-cfl-8109u: [PASS][11] -> [DMESG-WARN][12] ([i915#5904]) +30
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11985/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u: [PASS][13] -> [DMESG-WARN][14] ([i915#5904] /
[i915#62])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11985/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][15] ([i915#5982])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bsw-nick:NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/fi-bsw-nick/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-4770:NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-blb-e6850: NOTRUN -> [SKIP][18] ([fdo#109271])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/fi-blb-e6850/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-pnv-d510:NOTRUN -> [SKIP][19] ([fdo#109271])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-rkl-11600: NOTRUN -> [SKIP][20] ([fdo#111827]) +7 similar issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107181v1/fi-rkl-1
[Intel-gfx] [PATCH] drm/i915/guc: clear stalled request after a reset
If the GuC CTs are full and we need to stall the request submission
while waiting for space, we save the stalled request and where the stall
occurred; when the CTs have space again we pick up the request submission
from where we left off.
If a full GT reset occurs, the state of all contexts is cleared and all
non-guilty requests are unsubmitted, therefore we need to restart the
stalled request submission from scratch. To make sure that we do so,
clear the saved request after a reset.
Fixes note: the patch that introduced the bug is in 5.15, but no
officially supported platform had GuC submission enabled by default
in that kernel, so the backport to that particular version (and only
that one) can potentially be skipped.
Fixes: 925dc1cf58ed ("drm/i915/guc: Implement GuC submission tasklet")
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matthew Brost
Cc: John Harrison
Cc: # v5.15+
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0d17da77e787..0d56b615bf78 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4002,6 +4002,13 @@ static inline void guc_init_lrc_mapping(struct intel_guc
*guc)
/* make sure all descriptors are clean... */
xa_destroy(&guc->context_lookup);
+ /*
+* A reset might have occurred while we had a pending stalled request,
+* so make sure we clean that up.
+*/
+ guc->stalled_request = NULL;
+ guc->submission_stall_reason = STALL_NONE;
+
/*
* Some contexts might have been pinned before we enabled GuC
* submission, so we need to add them to the GuC bookeeping.
--
2.25.1
[Intel-gfx] [PULL] drm-intel-next-fixes
Hi Dave and Daniel, And here is the right one. And now including all the fixes. Here goes drm-intel-next-fixes-2022-08-11: - disable pci resize on 32-bit systems (Nirmoy) - don't leak the ccs state (Matt) - TLB invalidation fixes (Chris) [now with all fixes of fixes] Thanks, Rodrigo. The following changes since commit 5493ee1919eae4f49d62276cf5986b7f7c7aa8f6: Merge tag 'amd-drm-next-5.20-2022-07-29' of https://gitlab.freedesktop.org/agd5f/linux into drm-next (2022-08-03 14:00:19 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-fixes-2022-08-11 for you to fetch changes up to 9d50bff40e3e366886ec37299fc317edf84be0c9: drm/i915: pass a pointer for tlb seqno at vma_invalidate_tlb() (2022-08-08 14:54:20 -0400) - disable pci resize on 32-bit systems (Nirmoy) - don't leak the ccs state (Matt) - TLB invalidation fixes (Chris) [now with all fixes of fixes] Chris Wilson (5): drm/i915/gt: Ignore TLB invalidations on idle engines drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations drm/i915/gt: Skip TLB invalidations once wedged drm/i915/gt: Batch TLB invalidations drm/i915/gem: Remove shared locking on freeing objects Matthew Auld (1): drm/i915/ttm: don't leak the ccs state Mauro Carvalho Chehab (1): drm/i915: pass a pointer for tlb seqno at vma_invalidate_tlb() Nirmoy Das (1): drm/i915: disable pci resize on 32-bit machine drivers/gpu/drm/i915/gem/i915_gem_object.c | 16 ++--- drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 3 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c| 25 +--- drivers/gpu/drm/i915/gt/intel_gt.c | 77 ++-- drivers/gpu/drm/i915/gt/intel_gt.h | 12 +++- drivers/gpu/drm/i915/gt/intel_gt_pm.h| 3 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 18 +- drivers/gpu/drm/i915/gt/intel_migrate.c | 23 ++- drivers/gpu/drm/i915/gt/intel_ppgtt.c| 8 ++- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 ++ drivers/gpu/drm/i915/i915_drv.h | 4 +- drivers/gpu/drm/i915/i915_vma.c | 33 +++--- drivers/gpu/drm/i915/i915_vma.h | 1 + drivers/gpu/drm/i915/i915_vma_resource.c | 5 +- drivers/gpu/drm/i915/i915_vma_resource.h | 6 +- 15 files changed, 183 insertions(+), 55 deletions(-)
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: reschedule relocations to avoid timeouts (rev2)
== Series Details == Series: drm/i915/gem: reschedule relocations to avoid timeouts (rev2) URL : https://patchwork.freedesktop.org/series/107125/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11983_full -> Patchwork_107125v2_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_107125v2_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107125v2_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (13 -> 10) -- Missing(3): shard-rkl shard-dg1 shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_107125v2_full: ### IGT changes ### Possible regressions * igt@kms_plane@plane-position-hole@pipe-b-planes: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-tglb2/igt@kms_plane@plane-position-h...@pipe-b-planes.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/shard-tglb5/igt@kms_plane@plane-position-h...@pipe-b-planes.html Known issues Here are the changes found in Patchwork_107125v2_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-hang: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/shard-snb7/igt@gem_ctx_persiste...@engines-hang.html * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb1/igt@gem_exec_balan...@parallel-bb-first.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/shard-iclb8/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2849]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_gttfill@basic: - shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271]) +14 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/shard-skl9/igt@gem_exec_gttf...@basic.html * igt@gem_lmem_swapping@smem-oom: - shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/shard-apl8/igt@gem_lmem_swapp...@smem-oom.html * igt@gem_lmem_swapping@verify-random: - shard-kbl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/shard-kbl4/igt@gem_lmem_swapp...@verify-random.html * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled: - shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271]) +64 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/shard-apl8/igt@gem_render_c...@x-tiled-to-vebox-yf-tiled.html * igt@gem_userptr_blits@input-checking: - shard-kbl: NOTRUN -> [DMESG-WARN][15] ([i915#4991]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/shard-kbl7/igt@gem_userptr_bl...@input-checking.html * igt@gem_workarounds@suspend-resume: - shard-skl: [PASS][16] -> [INCOMPLETE][17] ([i915#4939] / [i915#5129]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-skl4/igt@gem_workarou...@suspend-resume.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/shard-skl1/igt@gem_workarou...@suspend-resume.html * igt@i915_pm_rpm@dpms-lpsp: - shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271]) +106 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/shard-kbl7/igt@i915_pm_...@dpms-lpsp.html * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels: - shard-snb: NOTRUN -> [SKIP][1
Re: [Intel-gfx] [PATCH 0/2] Add DP MST DSC support to i915
On Thu, 2022-08-11 at 10:33 +0300, Lisovskiy, Stanislav wrote: > On Wed, Aug 10, 2022 at 04:02:08PM -0400, Lyude Paul wrote: > > Btw, what's the plan for this? Figured I'd ask since I noticed this on the > > ML, > > nd I'm now finishing up getting the atomic only MST patches I've been > > working > > on merged :) > > Current plan is that I need to fix this, as current implementation doesn't > seem to work because of my wrong assumption that drm_dp_mst_find_vcpi_slots > will fail if no slots are available and then we can fallback to DSC. > > In reality that function can return whatever bogus value it wants, like > 71 slots, while you have only 63 available. The real check is done in > drm_dp_mst_atomic_check, which would of course reject that configuration, > however by that moment its going to be too late for swithcing to DSC. > Yeah - the drm_dp_mst_find_vcpi_slots() bit is intentional, as we need to be able to ensure that calls to it are idempotent since it may be called multiple times. We also don't actually know whether or not we've gone past the max number of slots until atomic check since there's not necessarily a guarantee towards which order we process disabling CRTCs and process enabling them, hence why we wait towards the end to check this. The eventual plan that I'd like to see happen is to basically teach drm_dp_mst_atomic_check() to indicate when a display state needs to be recalculated in order to fit into the current bandwidth limitations. There's a number of ways we could accomplish this, one I've been thinking about in particular is maybe having drivers provide a minimum and maximum bandwidth value, so that we could also have the helpers indicate to the driver which sinks can be recalculated. Also FWIW: the reason I've been working on: https://patchwork.freedesktop.org/series/107073/ Is to make all of this easier by making sure all of the payload info is in the MST atomic state. > So looke like I will have to move that check at least partly to where DSC/no > DSC decision is done. However if there are multiple displays we get > another problem, lets say we have 2 displays requiring 40 vcpi slots each in > DSC > mode with certain input bpp. > We have now either option to reject the whole config or go back and try with > another bpp to check if we can reduce amount of slots. > Because by default we choose the first one which fits, however by the time > when > compute_config is called, we still don't have all config computed, which might > lead to that last crtc can either run our of vcpi slots or we will have to > go back and try recalculating with higher compression ratio. Having to go back and recalculate with a higher compression ratio is to be expected to some extent I'm fairly sure, as I don't really think there's any other sensible way we could figure this out besides recalculating the state multiple times. Keep in mind too - doing stuff like calling a CRTC's atomic check multiple times is totally normal and expected to work in DRM anyhow. > > My other question was that DSC was supposed to be "visually" lossless, > wondering > why we are still trying with different bpps? Could have just set highest > compression ratio right away. I think this is a misunderstanding, at least while talking to AMD the impression I've gotten is that DSC isn't actually totally loseless - which is why their driver currently tries to use the least amount of compression possible. Otherwise I would say we should just enable it at max all of the time. Also, annoyingly most of the logic for doing this is currently stuck in amdgpu's driver. but please feel free to move it out into helpers! If we want good DSC support that's definitely going to help quite a bunch since they've worked out a lot of this already, and there's probably even improvements we can make upon their logic. > > So need to sort this out first before floating new series. > > Stan > > > > > On Wed, 2022-08-10 at 11:17 +0300, Stanislav Lisovskiy wrote: > > > Currently we have only DSC support for DP SST. > > > > > > Stanislav Lisovskiy (2): > > > drm: Add missing DP DSC extended capability definitions. > > > drm/i915: Add DSC support to MST path > > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 76 +- > > > drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 145 > > > include/drm/display/drm_dp.h| 10 +- > > > 4 files changed, 203 insertions(+), 45 deletions(-) > > > > > > > -- > > Cheers, > > Lyude Paul (she/her) > > Software Engineer at Red Hat > > > -- Cheers, Lyude Paul (she/her) Software Engineer at Red Hat
[Intel-gfx] ✓ Fi.CI.IGT: success for Fix HFVSDB parsing
== Series Details == Series: Fix HFVSDB parsing URL : https://patchwork.freedesktop.org/series/107144/ State : success == Summary == CI Bug Log - changes from CI_DRM_11983_full -> Patchwork_107144v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (13 -> 9) -- Missing(4): shard-dg1 pig-kbl-iris shard-rkl shard-tglu Known issues Here are the changes found in Patchwork_107144v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@close-race: - shard-snb: [PASS][1] -> [TIMEOUT][2] ([i915#5748]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-snb6/igt@gem_b...@close-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/shard-snb6/igt@gem_b...@close-race.html * igt@gem_ctx_persistence@engines-hang: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/shard-snb2/igt@gem_ctx_persiste...@engines-hang.html * igt@gem_eio@in-flight-immediate: - shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-tglb3/igt@gem_...@in-flight-immediate.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/shard-tglb2/igt@gem_...@in-flight-immediate.html * igt@gem_exec_balancer@parallel-contexts: - shard-iclb: [PASS][6] -> [SKIP][7] ([i915#4525]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb2/igt@gem_exec_balan...@parallel-contexts.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/shard-iclb7/igt@gem_exec_balan...@parallel-contexts.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl7/igt@gem_exec_fair@basic-p...@vecs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/shard-kbl7/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2849]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_gttfill@basic: - shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271]) +16 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/shard-skl7/igt@gem_exec_gttf...@basic.html * igt@gem_lmem_swapping@smem-oom: - shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/shard-apl2/igt@gem_lmem_swapp...@smem-oom.html * igt@gem_lmem_swapping@verify-random: - shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/shard-kbl1/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap_gtt@fault-concurrent-x: - shard-snb: [PASS][15] -> [INCOMPLETE][16] ([i915#5161]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-snb2/igt@gem_mmap_...@fault-concurrent-x.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/shard-snb6/igt@gem_mmap_...@fault-concurrent-x.html * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271]) +82 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/shard-apl2/igt@gem_render_c...@x-tiled-to-vebox-yf-tiled.html * igt@gem_userptr_blits@input-checking: - shard-kbl: NOTRUN -> [DMESG-WARN][18] ([i915#4991]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/shard-kbl7/igt@gem_userptr_bl...@input-checking.html * igt@i915_pm_rpm@dpms-lpsp: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271]) +118 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/shard-kbl1/igt@i915_pm_...@dpms-lpsp.html * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels: - shard-snb: NOTRUN -> [SKIP][20] ([fdo#109271]) +63 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/shard-snb2/igt@kms_atomic_transit...@plane-all-modeset-transition-fencing-internal-panels.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [FAIL][21] ([i915#3743]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/shard-skl9/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_t
Re: [Intel-gfx] [PATCH v4 1/7] drm: Move and add a few utility macros into drm util header
On Thu, 11 Aug 2022, Daniel Vetter wrote:
> On Tue, Jul 19, 2022 at 05:04:18PM +0300, Gwan-gyeong Mun wrote:
>> It moves overflows_type utility macro into drm util header from i915_utils
>> header. The overflows_type can be used to catch the truncation between data
>> types. And it adds safe_conversion() macro which performs a type conversion
>> (cast) of an source value into a new variable, checking that the
>> destination is large enough to hold the source value.
>> And it adds exact_type and exactly_pgoff_t macro to catch type mis-match
>> while compiling.
>>
>> v3: Add is_type_unsigned() macro (Mauro)
>> Modify overflows_type() macro to consider signed data types (Mauro)
>> Fix the problem that safe_conversion() macro always returns true
>> v4: Fix kernel-doc markups
>>
>> Signed-off-by: Gwan-gyeong Mun
>> Cc: Thomas Hellström
>> Cc: Matthew Auld
>> Cc: Nirmoy Das
>> Cc: Jani Nikula
>> Reviewed-by: Mauro Carvalho Chehab
>> ---
>> drivers/gpu/drm/i915/i915_utils.h | 5 +-
>> include/drm/drm_util.h| 77 +++
>
> It's nice that there's less random piling into i915_utils.h, but pushing
> them into drm_util.h isn't really better. These should all be in
> include/linux/ somewhere, so that we have as consistent code as possible.
>
> drm_util.h should only be a fallback if we get nacks for a more general
> place and still think it's the right thing to do.
>
> i915_util.h has frankyl gone completely bonkers and should die.
Agreed [1].
BR,
Jani.
[1] https://lore.kernel.org/r/875yj9qv62@intel.com
> -Daniel
>
>> 2 files changed, 78 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_utils.h
>> b/drivers/gpu/drm/i915/i915_utils.h
>> index c10d68cdc3ca..345e5b2dc1cd 100644
>> --- a/drivers/gpu/drm/i915/i915_utils.h
>> +++ b/drivers/gpu/drm/i915/i915_utils.h
>> @@ -32,6 +32,7 @@
>> #include
>> #include
>> #include
>> +#include
>>
>> #ifdef CONFIG_X86
>> #include
>> @@ -111,10 +112,6 @@ bool i915_error_injected(void);
>> #define range_overflows_end_t(type, start, size, max) \
>> range_overflows_end((type)(start), (type)(size), (type)(max))
>>
>> -/* Note we don't consider signbits :| */
>> -#define overflows_type(x, T) \
>> -(sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T))
>> -
>> #define ptr_mask_bits(ptr, n) ({\
>> unsigned long __v = (unsigned long)(ptr); \
>> (typeof(ptr))(__v & -BIT(n)); \
>> diff --git a/include/drm/drm_util.h b/include/drm/drm_util.h
>> index 79952d8c4bba..1de9ee5704fa 100644
>> --- a/include/drm/drm_util.h
>> +++ b/include/drm/drm_util.h
>> @@ -62,6 +62,83 @@
>> */
>> #define for_each_if(condition) if (!(condition)) {} else
>>
>> +/**
>> + * is_type_unsigned - helper for checking data type which is an unsigned
>> data
>> + * type or not
>> + * @x: The data type to check
>> + *
>> + * Returns:
>> + * True if the data type is an unsigned data type, false otherwise.
>> + */
>> +#define is_type_unsigned(x) ((typeof(x))-1 >= (typeof(x))0)
>> +
>> +/**
>> + * overflows_type - helper for checking the truncation between data types
>> + * @x: Source for overflow type comparison
>> + * @T: Destination for overflow type comparison
>> + *
>> + * It compares the values and size of each data type between the first and
>> + * second argument to check whether truncation can occur when assigning the
>> + * first argument to the variable of the second argument.
>> + * Source and Destination can be used with or without sign bit.
>> + * Composite data structures such as union and structure are not considered.
>> + * Enum data types are not considered.
>> + * Floating point data types are not considered.
>> + *
>> + * Returns:
>> + * True if truncation can occur, false otherwise.
>> + */
>> +
>> +#define overflows_type(x, T) \
>> +(is_type_unsigned(x) ? \
>> +is_type_unsigned(T) ? \
>> +(sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T)) ? 1
>> : 0 \
>> +: (sizeof(x) >= sizeof(T) && (x) >> (BITS_PER_TYPE(T) -
>> 1)) ? 1 : 0 \
>> +: is_type_unsigned(T) ? \
>> +((x) < 0) ? 1 : (sizeof(x) > sizeof(T) && (x) >>
>> BITS_PER_TYPE(T)) ? 1 : 0 \
>> +: (sizeof(x) > sizeof(T)) ? \
>> +((x) < 0) ? (((x) * -1) >> BITS_PER_TYPE(T)) ? 1 : 0 \
>> +: ((x) >> BITS_PER_TYPE(T)) ? 1 : 0 \
>> +: 0)
>> +
>> +/**
>> + * exact_type - break compile if source type and destination value's type
>> are
>> + * not the same
>> + * @T: Source type
>> + * @n: Destination value
>> + *
>> + * It is a helper macro for a poor man's -Wconversion: only allow variables
>> of
>> + * an exact type. It determines whether the source type and destination
>> value's
>> + * type are the same while compiling, and it breaks compile if two types are
>> + * not the same
>> + */
>> +#de
Re: [Intel-gfx] [PATCH 0/2] Add DP MST DSC support to i915
On Thu, Aug 11, 2022 at 10:33:51AM +0300, Lisovskiy, Stanislav wrote: > On Wed, Aug 10, 2022 at 04:02:08PM -0400, Lyude Paul wrote: > > Btw, what's the plan for this? Figured I'd ask since I noticed this on the > > ML, > > nd I'm now finishing up getting the atomic only MST patches I've been > > working > > on merged :) > > Current plan is that I need to fix this, as current implementation doesn't > seem to work because of my wrong assumption that drm_dp_mst_find_vcpi_slots > will fail if no slots are available and then we can fallback to DSC. > > In reality that function can return whatever bogus value it wants, like > 71 slots, while you have only 63 available. The real check is done in > drm_dp_mst_atomic_check, which would of course reject that configuration, > however by that moment its going to be too late for swithcing to DSC. > > So looke like I will have to move that check at least partly to where DSC/no > DSC decision is done. However if there are multiple displays we get > another problem, lets say we have 2 displays requiring 40 vcpi slots each in > DSC > mode with certain input bpp. > We have now either option to reject the whole config or go back and try with > another bpp to check if we can reduce amount of slots. > Because by default we choose the first one which fits, however by the time > when > compute_config is called, we still don't have all config computed, which might > lead to that last crtc can either run our of vcpi slots or we will have to > go back and try recalculating with higher compression ratio. > > My other question was that DSC was supposed to be "visually" lossless, > wondering > why we are still trying with different bpps? Could have just set highest > compression ratio right away. We do want to still maintain as high pic quality as possible. So we try to find out the min compression ration that will make the mode fit into the available link BW. Manasi > > So need to sort this out first before floating new series. > > Stan > > > > > On Wed, 2022-08-10 at 11:17 +0300, Stanislav Lisovskiy wrote: > > > Currently we have only DSC support for DP SST. > > > > > > Stanislav Lisovskiy (2): > > > drm: Add missing DP DSC extended capability definitions. > > > drm/i915: Add DSC support to MST path > > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 76 +- > > > drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 145 > > > include/drm/display/drm_dp.h| 10 +- > > > 4 files changed, 203 insertions(+), 45 deletions(-) > > > > > > > -- > > Cheers, > > Lyude Paul (she/her) > > Software Engineer at Red Hat > >
Re: [Intel-gfx] [PATCH v2] drm/i915/dg2: Add additional HDMI pixel clock frequencies
On 01.08.2022 16:48, Taylor, Clinton A wrote:
> Using the BSPEC algorithm add addition HDMI pixel clocks to the existing
> table.
>
> v2: remove 297000 unused entry
>
> Cc: Matt Roper
> Cc: Radhakrishna Sripada
> Signed-off-by: Taylor, Clinton A
Reviewed-by: Balasubramani Vivekanandan
> ---
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 1115 +
> 1 file changed, 1115 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index 0bdbedc67d7d..f75808e0c95e 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -518,6 +518,1085 @@ static const struct intel_mpllb_state dg2_hdmi_148_5 =
> {
> };
>
> /* values in the below table are calculted using the algo */
> +static const struct intel_mpllb_state dg2_hdmi_25200 = {
> + .clock = 25200,
> + .ref_control =
> + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
> + .mpllb_cp =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
> + .mpllb_div =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
> + .mpllb_div2 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
> + .mpllb_fracn1 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
> + .mpllb_fracn2 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 41943) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2621),
> + .mpllb_sscen =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
> +};
> +
> +static const struct intel_mpllb_state dg2_hdmi_27027 = {
> + .clock = 27027,
> + .ref_control =
> + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
> + .mpllb_cp =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
> + .mpllb_div =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
> + .mpllb_div2 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
> + .mpllb_fracn1 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
> + .mpllb_fracn2 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 31876) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 46555),
> + .mpllb_sscen =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
> +};
> +
> +static const struct intel_mpllb_state dg2_hdmi_28320 = {
> + .clock = 28320,
> + .ref_control =
> + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
> + .mpllb_cp =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
> + .mpllb_div =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
> + .mpllb_div2 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 148) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
> + .mpllb_fracn1 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
> + .mpllb_fracn2 =
> + REG_FIELD_PREP(SNPS_P
Re: [Intel-gfx] [PATCH v4 00/41] DYNDBG: opt-in class'd debug for modules, use in drm.
On Wed, Aug 03, 2022 at 04:13:05PM -0400, Jason Baron wrote: > > > On 8/3/22 15:56, jim.cro...@gmail.com wrote: > > On Wed, Jul 20, 2022 at 9:32 AM Jim Cromie wrote: > >> > > > >> Hi Jason, Greg, DRM-folk, > >> > >> This adds 'typed' "class FOO" support to dynamic-debug, where 'typed' > >> means either DISJOINT (like drm debug categories), or VERBOSE (like > >> nouveau debug-levels). Use it in DRM modules: core, helpers, and in > >> drivers i915, amdgpu, nouveau. > >> > > > > This revision fell over, on a conflict with something in drm-MUMBLE > > > > Error: patch > > https://urldefense.com/v3/__https://patchwork.freedesktop.org/api/1.0/series/106427/revisions/2/mbox/__;!!GjvTz_vk!UCPl5Uf32cDVwwysMTfaLwoGLWomargFXuR8HjBA3xsUOjxXHXC5hneAkP4iWK91yc-LjjJxWW89-51Z$ > > > > not applied > > Applying: dyndbg: fix static_branch manipulation > > Applying: dyndbg: fix module.dyndbg handling > > Applying: dyndbg: show both old and new in change-info > > Applying: dyndbg: reverse module walk in cat control > > Applying: dyndbg: reverse module.callsite walk in cat control > > Applying: dyndbg: use ESCAPE_SPACE for cat control > > Applying: dyndbg: let query-modname override actual module name > > Applying: dyndbg: add test_dynamic_debug module > > Applying: dyndbg: drop EXPORTed dynamic_debug_exec_queries > > > > Jason, > > those above are decent maintenance patches, particularly the drop export. > > It would be nice to trim this unused api this cycle. > > Hi Jim, > > Agreed - I was thinking the same thing. Feel free to add > Acked-by: Jason Baron to those first 9. Does Greg KH usually pick up dyndbg patches or someone else or do I need to do something? Would be great to get some movement here since -rc1 goes out and merging will restart next week. -Daniel > > > > > > > Applying: dyndbg: add class_id to pr_debug callsites > > Applying: dyndbg: add __pr_debug_cls for testing > > Applying: dyndbg: add DECLARE_DYNDBG_CLASSMAP > > Applying: kernel/module: add __dyndbg_classes section > > Applying: dyndbg: add ddebug_attach_module_classes > > Applying: dyndbg: validate class FOO by checking with module > > Applying: dyndbg: add drm.debug style bitmap support > > Applying: dyndbg: test DECLARE_DYNDBG_CLASSMAP, sysfs nodes > > Applying: doc-dyndbg: describe "class CLASS_NAME" query support > > Applying: doc-dyndbg: edit dynamic-debug-howto for brevity, audience > > Applying: drm_print: condense enum drm_debug_category > > Applying: drm: POC drm on dyndbg - use in core, 2 helpers, 3 drivers. > > Applying: drm_print: interpose drm_*dbg with forwarding macros > > Applying: drm_print: wrap drm_*_dbg in dyndbg descriptor factory macro > > Using index info to reconstruct a base tree... > > M drivers/gpu/drm/Kconfig > > M drivers/gpu/drm/Makefile > > Falling back to patching base and 3-way merge... > > Auto-merging drivers/gpu/drm/Makefile > > Auto-merging drivers/gpu/drm/Kconfig > > CONFLICT (content): Merge conflict in drivers/gpu/drm/Kconfig > > error: Failed to merge in the changes. > > > > > > Before I resend, I should sort out that possible conflict > > which tree is patchwork applied upon ? > > > > or was it just transient ? after 5.19 I rebased a copy onto > > drm-next/drm-next, > > and there was nothing to fix - I will revisit presently.. > > > Not sure, if it's a minor conflict maybe Greg KH can sort it when > he pulls it in? If not yeah might be important to rebase first...Greg? > > Thanks, > > -Jason -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
Re: [Intel-gfx] [PATCH] Fixes KW issues for NULL pointer dereference
On 11.08.2022 13:28, Tapas Rana wrote:
I guess even for trivial patches rules should be followed - subject
should describe what has changed, commit message should describe why.
---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 9a7e50534b84..0bbf44c34cff 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -435,6 +435,9 @@ i915_ttm_memcpy_work_arm(struct i915_ttm_memcpy_work *work,
static bool i915_ttm_memcpy_allowed(struct ttm_buffer_object *bo,
struct ttm_resource *dst_mem)
{
+ if(!bo)
+ return NULL;
I guess it should be "return false"
Regards
Andrzej
+
if (i915_gem_object_needs_ccs_pages(i915_ttm_to_gem(bo)))
return false;
Re: [Intel-gfx] [PATCH v4 1/7] drm: Move and add a few utility macros into drm util header
On Tue, Jul 19, 2022 at 05:04:18PM +0300, Gwan-gyeong Mun wrote:
> It moves overflows_type utility macro into drm util header from i915_utils
> header. The overflows_type can be used to catch the truncation between data
> types. And it adds safe_conversion() macro which performs a type conversion
> (cast) of an source value into a new variable, checking that the
> destination is large enough to hold the source value.
> And it adds exact_type and exactly_pgoff_t macro to catch type mis-match
> while compiling.
>
> v3: Add is_type_unsigned() macro (Mauro)
> Modify overflows_type() macro to consider signed data types (Mauro)
> Fix the problem that safe_conversion() macro always returns true
> v4: Fix kernel-doc markups
>
> Signed-off-by: Gwan-gyeong Mun
> Cc: Thomas Hellström
> Cc: Matthew Auld
> Cc: Nirmoy Das
> Cc: Jani Nikula
> Reviewed-by: Mauro Carvalho Chehab
> ---
> drivers/gpu/drm/i915/i915_utils.h | 5 +-
> include/drm/drm_util.h| 77 +++
It's nice that there's less random piling into i915_utils.h, but pushing
them into drm_util.h isn't really better. These should all be in
include/linux/ somewhere, so that we have as consistent code as possible.
drm_util.h should only be a fallback if we get nacks for a more general
place and still think it's the right thing to do.
i915_util.h has frankyl gone completely bonkers and should die.
-Daniel
> 2 files changed, 78 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_utils.h
> b/drivers/gpu/drm/i915/i915_utils.h
> index c10d68cdc3ca..345e5b2dc1cd 100644
> --- a/drivers/gpu/drm/i915/i915_utils.h
> +++ b/drivers/gpu/drm/i915/i915_utils.h
> @@ -32,6 +32,7 @@
> #include
> #include
> #include
> +#include
>
> #ifdef CONFIG_X86
> #include
> @@ -111,10 +112,6 @@ bool i915_error_injected(void);
> #define range_overflows_end_t(type, start, size, max) \
> range_overflows_end((type)(start), (type)(size), (type)(max))
>
> -/* Note we don't consider signbits :| */
> -#define overflows_type(x, T) \
> - (sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T))
> -
> #define ptr_mask_bits(ptr, n) ({ \
> unsigned long __v = (unsigned long)(ptr); \
> (typeof(ptr))(__v & -BIT(n)); \
> diff --git a/include/drm/drm_util.h b/include/drm/drm_util.h
> index 79952d8c4bba..1de9ee5704fa 100644
> --- a/include/drm/drm_util.h
> +++ b/include/drm/drm_util.h
> @@ -62,6 +62,83 @@
> */
> #define for_each_if(condition) if (!(condition)) {} else
>
> +/**
> + * is_type_unsigned - helper for checking data type which is an unsigned data
> + * type or not
> + * @x: The data type to check
> + *
> + * Returns:
> + * True if the data type is an unsigned data type, false otherwise.
> + */
> +#define is_type_unsigned(x) ((typeof(x))-1 >= (typeof(x))0)
> +
> +/**
> + * overflows_type - helper for checking the truncation between data types
> + * @x: Source for overflow type comparison
> + * @T: Destination for overflow type comparison
> + *
> + * It compares the values and size of each data type between the first and
> + * second argument to check whether truncation can occur when assigning the
> + * first argument to the variable of the second argument.
> + * Source and Destination can be used with or without sign bit.
> + * Composite data structures such as union and structure are not considered.
> + * Enum data types are not considered.
> + * Floating point data types are not considered.
> + *
> + * Returns:
> + * True if truncation can occur, false otherwise.
> + */
> +
> +#define overflows_type(x, T) \
> + (is_type_unsigned(x) ? \
> + is_type_unsigned(T) ? \
> + (sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T)) ? 1
> : 0 \
> + : (sizeof(x) >= sizeof(T) && (x) >> (BITS_PER_TYPE(T) -
> 1)) ? 1 : 0 \
> + : is_type_unsigned(T) ? \
> + ((x) < 0) ? 1 : (sizeof(x) > sizeof(T) && (x) >>
> BITS_PER_TYPE(T)) ? 1 : 0 \
> + : (sizeof(x) > sizeof(T)) ? \
> + ((x) < 0) ? (((x) * -1) >> BITS_PER_TYPE(T)) ? 1 : 0 \
> + : ((x) >> BITS_PER_TYPE(T)) ? 1 : 0 \
> + : 0)
> +
> +/**
> + * exact_type - break compile if source type and destination value's type are
> + * not the same
> + * @T: Source type
> + * @n: Destination value
> + *
> + * It is a helper macro for a poor man's -Wconversion: only allow variables
> of
> + * an exact type. It determines whether the source type and destination
> value's
> + * type are the same while compiling, and it breaks compile if two types are
> + * not the same
> + */
> +#define exact_type(T, n) \
> + BUILD_BUG_ON(!__builtin_constant_p(n) &&
> !__builtin_types_compatible_p(T, typeof(n)))
> +
> +/**
> + * exactly_pgoff_t - helper to check if the type of a value is pgoff_t
> + * @n: value to compare pgoff_t type
> + *
Re: [Intel-gfx] [PATCH 1/3] drm: Use original src rect while initializing damage iterator
On Fri, Jul 15, 2022 at 04:49:56PM +0300, Jouni Högander wrote:
> drm_plane_state->src might be modified by the driver. This is done
> e.g. in i915 driver when there is bigger framebuffer than the plane
> and there is some offset within framebuffer. I915 driver calculates
> separate offset and adjusts src rect coords to be relative to this
> offset. Damage clips are still relative to original src coords
> provided by user-space.
>
> This patch ensures original coordinates provided by user-space are
> used when initiliazing damage iterator.
>
> Signed-off-by: Jouni Högander
Ah kunit test for this would be awesome. Iirc we have a few already for
rect/damage stuff, defo should extend/fix those.
-Daniel
> ---
> drivers/gpu/drm/drm_damage_helper.c | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_damage_helper.c
> b/drivers/gpu/drm/drm_damage_helper.c
> index 937b699ac2a8..d8b2955e88fd 100644
> --- a/drivers/gpu/drm/drm_damage_helper.c
> +++ b/drivers/gpu/drm/drm_damage_helper.c
> @@ -224,6 +224,7 @@ drm_atomic_helper_damage_iter_init(struct
> drm_atomic_helper_damage_iter *iter,
> const struct drm_plane_state *old_state,
> const struct drm_plane_state *state)
> {
> + struct drm_rect src;
> memset(iter, 0, sizeof(*iter));
>
> if (!state || !state->crtc || !state->fb || !state->visible)
> @@ -233,10 +234,12 @@ drm_atomic_helper_damage_iter_init(struct
> drm_atomic_helper_damage_iter *iter,
> iter->num_clips = drm_plane_get_damage_clips_count(state);
>
> /* Round down for x1/y1 and round up for x2/y2 to catch all pixels */
> - iter->plane_src.x1 = state->src.x1 >> 16;
> - iter->plane_src.y1 = state->src.y1 >> 16;
> - iter->plane_src.x2 = (state->src.x2 >> 16) + !!(state->src.x2 & 0x);
> - iter->plane_src.y2 = (state->src.y2 >> 16) + !!(state->src.y2 & 0x);
> + src = drm_plane_state_src(state);
> +
> + iter->plane_src.x1 = src.x1 >> 16;
> + iter->plane_src.y1 = src.y1 >> 16;
> + iter->plane_src.x2 = (src.x2 >> 16) + !!(src.x2 & 0x);
> + iter->plane_src.y2 = (src.y2 >> 16) + !!(src.y2 & 0x);
>
> if (!iter->clips || !drm_rect_equals(&state->src, &old_state->src)) {
> iter->clips = NULL;
> --
> 2.25.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add display sub-struct to drm_i915_private
== Series Details == Series: drm/i915: add display sub-struct to drm_i915_private URL : https://patchwork.freedesktop.org/series/107170/ State : success == Summary == CI Bug Log - changes from CI_DRM_11983 -> Patchwork_107170v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/index.html Participating hosts (29 -> 38) -- Additional (13): bat-dg1-6 bat-dg1-5 bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adlp-6 bat-adlp-4 bat-adln-1 fi-cfl-8109u bat-rplp-1 bat-rpls-1 bat-rpls-2 bat-jsl-1 Missing(4): fi-ctg-p8600 fi-rkl-11600 fi-hsw-4200u fi-snb-2600 Known issues Here are the changes found in Patchwork_107170v1 that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@nullptr: - bat-dg1-5: NOTRUN -> [SKIP][1] ([i915#2582]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@fb...@nullptr.html * igt@fbdev@read: - bat-adlp-4: NOTRUN -> [SKIP][2] ([i915#2582]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@fb...@read.html * igt@gem_huc_copy@huc-copy: - fi-cfl-8109u: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-apl-guc: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-adlp-4: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - fi-cfl-8109u: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg1-5: NOTRUN -> [SKIP][7] ([i915#4083]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@gem_m...@basic.html - bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#4083]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][9] ([i915#4079]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-dg1-5: NOTRUN -> [SKIP][10] ([i915#4077]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#4077]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-5: NOTRUN -> [SKIP][12] ([i915#4079]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@gem_tiled_pread_basic.html - bat-adlp-4: NOTRUN -> [SKIP][13] ([i915#3282]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-6: NOTRUN -> [SKIP][14] ([i915#1155]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html - bat-adlp-4: NOTRUN -> [SKIP][15] ([i915#1155]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@i915_pm_backli...@basic-brightness.html - bat-dg1-5: NOTRUN -> [SKIP][16] ([i915#1155]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][17] -> [INCOMPLETE][18] ([i915#5847]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_heartbeat: - fi-skl-6700k2: [PASS][19] -> [DMESG-FAIL][20] ([i915#5334]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-skl-6700k2/igt@i915_selftest@live@gt_heartbeat.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-skl-6700k2/igt@i915_selftest@live@gt_heartbeat.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: add display sub-struct to drm_i915_private
== Series Details == Series: drm/i915: add display sub-struct to drm_i915_private URL : https://patchwork.freedesktop.org/series/107170/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: add display sub-struct to drm_i915_private
== Series Details == Series: drm/i915: add display sub-struct to drm_i915_private URL : https://patchwork.freedesktop.org/series/107170/ State : warning == Summary == Error: dim checkpatch failed 81a599e0acc6 drm/i915: add display sub-struct to drm_i915_private Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in import git ModuleNotFoundError: No module named 'git' -:125: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #125: new file mode 100644 -:147: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #147: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:18: +* fills out the pipe-config with the hw state. */ -:148: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct intel_crtc *' should also have an identifier name #148: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:19: + bool (*get_pipe_config)(struct intel_crtc *, -:148: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct intel_crtc_state *' should also have an identifier name #148: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:19: + bool (*get_pipe_config)(struct intel_crtc *, -:150: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct intel_crtc *' should also have an identifier name #150: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:21: + void (*get_initial_plane_config)(struct intel_crtc *, -:150: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct intel_initial_plane_config *' should also have an identifier name #150: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:21: + void (*get_initial_plane_config)(struct intel_crtc *, total: 0 errors, 6 warnings, 0 checks, 198 lines checked 98eec48f505c drm/i915: move cdclk_funcs to display.funcs 699528783267 drm/i915: move dpll_funcs to display.funcs 22eeabd10546 drm/i915: move hotplug_funcs to display.funcs af7f4c94cba1 drm/i915: move clock_gating_funcs to display.funcs 5902bf135e5f drm/i915: move wm_disp funcs to display.funcs 763b41870eb1 drm/i915: move fdi_funcs to display.funcs d4e25a89ea42 drm/i915: move color_funcs to display.funcs 97a1a55d792b drm/i915: move and group gmbus members under display.gmbus -:347: WARNING:LONG_LINE_COMMENT: line length of 105 exceeds 100 columns #347: FILE: drivers/gpu/drm/i915/i915_reg.h:1485: +#define GMBUS0 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5100) /* clock/port select */ -:356: WARNING:LONG_LINE_COMMENT: line length of 102 exceeds 100 columns #356: FILE: drivers/gpu/drm/i915/i915_reg.h:1494: +#define GMBUS1 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5104) /* command/status */ -:375: WARNING:LONG_LINE_COMMENT: line length of 109 exceeds 100 columns #375: FILE: drivers/gpu/drm/i915/i915_reg.h:1517: +#define GMBUS3 _MMIO(dev_priv->display.gmbus.mmio_base + 0x510c) /* data buffer bytes 3-0 */ -:376: WARNING:LONG_LINE_COMMENT: line length of 114 exceeds 100 columns #376: FILE: drivers/gpu/drm/i915/i915_reg.h:1518: +#define GMBUS4 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5110) /* interrupt mask (Pineview+) */ total: 0 errors, 4 warnings, 0 checks, 320 lines checked c81231bd7491 drm/i915: move and group pps members under display.pps 9691040cd55f drm/i915: move dmc to display.dmc -:210: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #210: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:455: + !intel_de_read(i915, DMC_PROGRAM(i915->display.dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), total: 0 errors, 1 warnings, 0 checks, 339 lines checked cb5448c3b8e0 drm/i915: move and split audio under display.audio and display.funcs -:318: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "dev_priv->display.audio.lpe.platdev" #318: FILE: drivers/gpu/drm/i915/display/intel_audio.c:1406: + if (dev_priv->display.audio.lpe.platdev != NULL) -:394: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "display.audio.lpe.platdev" #394: FILE: drivers/gpu/drm/i915/display/intel_lpe_audio.c:78: +#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->display.audio.lpe.platdev != NULL) -:403: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #403: FILE: drivers/gpu/drm/i915/display/intel_lpe_audio.c:100: + rsc[0].start= rsc[0].end = dev_priv->display.audio.lpe.irq; total: 0 errors, 0 warnings, 3 checks, 501 lines checked 45cea2c0cb3f drm/i915: move dpll under display.dpll -:213: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment #213: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:89: + struct mutex lock; -:562: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() #562: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:4210: + BUG_ON(dev_priv->display.dpll.num_shared_dpll > I915_NUM_PLLS);
Re: [Intel-gfx] [PATCH] Fixes KW issue for NULL pointer dereference
The subject needs a prefix. For example "i915/drm:" or something more
specific, see git log.
Please use the imperative mood in the subject and commit message,
i.e. "fix" instead of "fixes" or "fixed".
On Thu, 11 Aug 2022, Tapas Rana wrote:
> - adds a NULL pointer check for the input parameter
Please write proper sentences. It's not a bulleted list.
This patch seems to be a v2 of an earlier patch. It's customary to add a
change history of the patch. Also, use --subject-prefix or -v
parameter to add the version in the subject like "[PATCH v2]". See
patches on the list.
>
> Signed-off-by: Tapas Rana
> ---
> drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> index 9a7e50534b84..de7c892aabc5 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> @@ -435,6 +435,9 @@ i915_ttm_memcpy_work_arm(struct i915_ttm_memcpy_work
> *work,
> static bool i915_ttm_memcpy_allowed(struct ttm_buffer_object *bo,
> struct ttm_resource *dst_mem)
> {
> + if (!bo)
> + return false;
> +
Finally, AFAICT it's not possible to reach here with NULL bo; it
would've been referenced before...
BR,
Jani.
> if (i915_gem_object_needs_ccs_pages(i915_ttm_to_gem(bo)))
> return false;
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private
On Thu, 11 Aug 2022, Jani Nikula wrote: > Add display sub-struct to drm_i915_private, and start moving display > related members there. > > This doesn't help with build dependencies yet, but adds a lot of clarity > in organizing the display data, and who accesses display data and where. > > This is a beginning, there are still stragglers, but need to start > sending the patches instead of accumulating tons more. Also pushed the lot to https://cgit.freedesktop.org/~jani/drm/log/?h=display-substruct -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH 26/39] drm/i915: move fbc to display.fbc
Move display related members under drm_i915_private display sub-struct.
Pointers and arrays of pointers to structs that we defined are fine
without a sub-struct wrapping.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
drivers/gpu/drm/i915/display/intel_fbc.c | 6 +++---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h| 3 ---
5 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 0f35f2facdfc..5afbe3e98ee8 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -125,7 +125,7 @@ static struct intel_fbc *i9xx_plane_fbc(struct
drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane)
{
if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))
- return dev_priv->fbc[INTEL_FBC_A];
+ return dev_priv->display.fbc[INTEL_FBC_A];
else
return NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 861178f969bd..066e7ee0b8df 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -18,6 +18,7 @@
#include "intel_display.h"
#include "intel_dmc.h"
#include "intel_dpll_mgr.h"
+#include "intel_fbc.h"
#include "intel_global_state.h"
#include "intel_gmbus.h"
#include "intel_opregion.h"
@@ -347,6 +348,7 @@ struct intel_display {
struct intel_audio audio;
struct intel_dmc dmc;
struct intel_dpll dpll;
+ struct intel_fbc *fbc[I915_MAX_FBCS];
struct intel_hotplug hotplug;
struct intel_opregion opregion;
struct intel_overlay *overlay;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7436b35f7ea0..5e8e29a4559f 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -59,7 +59,7 @@
#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
for_each_fbc_id((__dev_priv), (__fbc_id)) \
- for_each_if((__fbc) = (__dev_priv)->fbc[(__fbc_id)])
+ for_each_if((__fbc) = (__dev_priv)->display.fbc[(__fbc_id)])
struct intel_fbc_funcs {
void (*activate)(struct intel_fbc *fbc);
@@ -1720,7 +1720,7 @@ void intel_fbc_init(struct drm_i915_private *i915)
i915->params.enable_fbc);
for_each_fbc_id(i915, fbc_id)
- i915->fbc[fbc_id] = intel_fbc_create(i915, fbc_id);
+ i915->display.fbc[fbc_id] = intel_fbc_create(i915, fbc_id);
}
/**
@@ -1840,7 +1840,7 @@ void intel_fbc_debugfs_register(struct drm_i915_private
*i915)
struct drm_minor *minor = i915->drm.primary;
struct intel_fbc *fbc;
- fbc = i915->fbc[INTEL_FBC_A];
+ fbc = i915->display.fbc[INTEL_FBC_A];
if (fbc)
intel_fbc_debugfs_add(fbc, minor->debugfs_root);
}
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 4d6a27757065..594cda11382d 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1940,7 +1940,7 @@ static struct intel_fbc *skl_plane_fbc(struct
drm_i915_private *dev_priv,
enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe);
if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id))
- return dev_priv->fbc[fbc_id];
+ return dev_priv->display.fbc[fbc_id];
else
return NULL;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0dc3983eba84..752eeccb94eb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -40,7 +40,6 @@
#include "display/intel_display_core.h"
#include "display/intel_display_power.h"
#include "display/intel_dsb.h"
-#include "display/intel_fbc.h"
#include "display/intel_frontbuffer.h"
#include "gem/i915_gem_context_types.h"
@@ -284,8 +283,6 @@ struct drm_i915_private {
};
u32 pipestat_irq_mask[I915_MAX_PIPES];
- struct intel_fbc *fbc[I915_MAX_FBCS];
-
bool preserve_bios_swizzle;
unsigned int fsb_freq, mem_freq, is_ddr3;
--
2.34.1
[Intel-gfx] [PATCH 39/39] drm/i915: move and group properties under display.properties
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_atomic.c | 8
drivers/gpu/drm/i915/display/intel_connector.c| 8
drivers/gpu/drm/i915/display/intel_display_core.h | 6 ++
drivers/gpu/drm/i915/i915_drv.h | 3 ---
4 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index b94973b5633f..18f0a5ae3bac 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -62,9 +62,9 @@ int intel_digital_connector_atomic_get_property(struct
drm_connector *connector,
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(state);
- if (property == dev_priv->force_audio_property)
+ if (property == dev_priv->display.properties.force_audio)
*val = intel_conn_state->force_audio;
- else if (property == dev_priv->broadcast_rgb_property)
+ else if (property == dev_priv->display.properties.broadcast_rgb)
*val = intel_conn_state->broadcast_rgb;
else {
drm_dbg_atomic(&dev_priv->drm,
@@ -95,12 +95,12 @@ int intel_digital_connector_atomic_set_property(struct
drm_connector *connector,
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(state);
- if (property == dev_priv->force_audio_property) {
+ if (property == dev_priv->display.properties.force_audio) {
intel_conn_state->force_audio = val;
return 0;
}
- if (property == dev_priv->broadcast_rgb_property) {
+ if (property == dev_priv->display.properties.broadcast_rgb) {
intel_conn_state->broadcast_rgb = val;
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_connector.c
b/drivers/gpu/drm/i915/display/intel_connector.c
index 1dcc268927a2..6d5cbeb8df4d 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.c
+++ b/drivers/gpu/drm/i915/display/intel_connector.c
@@ -229,7 +229,7 @@ intel_attach_force_audio_property(struct drm_connector
*connector)
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_property *prop;
- prop = dev_priv->force_audio_property;
+ prop = dev_priv->display.properties.force_audio;
if (prop == NULL) {
prop = drm_property_create_enum(dev, 0,
"audio",
@@ -238,7 +238,7 @@ intel_attach_force_audio_property(struct drm_connector
*connector)
if (prop == NULL)
return;
- dev_priv->force_audio_property = prop;
+ dev_priv->display.properties.force_audio = prop;
}
drm_object_attach_property(&connector->base, prop, 0);
}
@@ -256,7 +256,7 @@ intel_attach_broadcast_rgb_property(struct drm_connector
*connector)
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_property *prop;
- prop = dev_priv->broadcast_rgb_property;
+ prop = dev_priv->display.properties.broadcast_rgb;
if (prop == NULL) {
prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
"Broadcast RGB",
@@ -265,7 +265,7 @@ intel_attach_broadcast_rgb_property(struct drm_connector
*connector)
if (prop == NULL)
return;
- dev_priv->broadcast_rgb_property = prop;
+ dev_priv->display.properties.broadcast_rgb = prop;
}
drm_object_attach_property(&connector->base, prop, 0);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index a753f6d66714..41ebdbd741c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -27,6 +27,7 @@
#include "intel_pm_types.h"
struct drm_i915_private;
+struct drm_property;
struct i915_audio_component;
struct i915_hdcp_comp_master;
struct intel_atomic_state;
@@ -373,6 +374,11 @@ struct intel_display {
struct mutex mutex;
} pps;
+ struct {
+ struct drm_property *broadcast_rgb;
+ struct drm_property *force_audio;
+ } properties;
+
struct {
unsigned long mask;
} quirks;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1bf7b13fdeda..ca97437f0e44 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -317,9 +317,6 @@ struct drm_i915_private {
struct i915_gpu_error gpu_error;
- struct drm_property *broadcast_rgb_property;
- struct drm_property *force_audio_property;
-
/*
* Shadows for CHV DPLL_MD regs to keep the state
* checker somewhat working
[Intel-gfx] [PATCH 17/39] drm/i915: move hotplug to display.hotplug
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/g4x_dp.c | 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +-
.../gpu/drm/i915/display/intel_display_core.h | 40 ++
.../drm/i915/display/intel_display_debugfs.c | 16 +--
drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
drivers/gpu/drm/i915/display/intel_hotplug.c | 116 +-
drivers/gpu/drm/i915/display/intel_tc.c | 4 +-
drivers/gpu/drm/i915/i915_driver.c| 6 +-
drivers/gpu/drm/i915/i915_drv.h | 40 --
drivers/gpu/drm/i915/i915_irq.c | 52
10 files changed, 144 insertions(+), 144 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
b/drivers/gpu/drm/i915/display/g4x_dp.c
index 82ad8fe7440c..e3e3d27ffb53 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -1169,7 +1169,7 @@ intel_dp_hotplug(struct intel_encoder *encoder,
static bool ibx_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
+ u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, SDEISR) & bit;
}
@@ -1223,7 +1223,7 @@ static bool gm45_digital_port_connected(struct
intel_encoder *encoder)
static bool ilk_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
+ u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, DEISR) & bit;
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 23c8287b0262..320304809ed6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4032,7 +4032,7 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
static bool lpt_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
+ u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, SDEISR) & bit;
}
@@ -4040,7 +4040,7 @@ static bool lpt_digital_port_connected(struct
intel_encoder *encoder)
static bool hsw_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
+ u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, DEISR) & bit;
}
@@ -4048,7 +4048,7 @@ static bool hsw_digital_port_connected(struct
intel_encoder *encoder)
static bool bdw_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
+ u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 8ac63352b27b..cf31ad0c9593 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -102,6 +102,45 @@ struct intel_dpll {
} ref_clks;
};
+struct intel_hotplug {
+ struct delayed_work hotplug_work;
+
+ const u32 *hpd, *pch_hpd;
+
+ struct {
+ unsigned long last_jiffies;
+ int count;
+ enum {
+ HPD_ENABLED = 0,
+ HPD_DISABLED = 1,
+ HPD_MARK_DISABLED = 2
+ } state;
+ } stats[HPD_NUM_PINS];
+ u32 event_bits;
+ u32 retry_bits;
+ struct delayed_work reenable_work;
+
+ u32 long_port_mask;
+ u32 short_port_mask;
+ struct work_struct dig_port_work;
+
+ struct work_struct poll_init_work;
+ bool poll_enabled;
+
+ unsigned int hpd_storm_threshold;
+ /* Whether or not to count short HPD IRQs in HPD storms */
+ u8 hpd_short_storm_enabled;
+
+ /*
+* if we get a HPD irq from DP and a HPD irq from non-DP
+* the non-DP HPD could block the workqueue on a mode config
+* mutex getting, that userspace may have taken. However
+* userspace is waiting on the DP workqueue to run which is
+* blocked behind the non-DP one.
+*/
+ struct workqueue_struct *dp_wq;
+};
+
struct intel_wm {
/*
* Raw watermark latency values:
@@ -213,6 +252,7 @@ struct intel_display {
struct intel_audio audio;
struct intel_
[Intel-gfx] [PATCH 31/39] drm/i915: move INTEL_FRONTBUFFER_* macros to intel_frontbuffer.h
The macros clearly don't belong in i915_drv.h. Move to
intel_frontbuffer.h.
Also split the BUILD_BUG_ON()s to intel_frontbuffer_track() to avoid
depending on some other macros in the header.
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_frontbuffer.c | 2 ++
.../gpu/drm/i915/display/intel_frontbuffer.h | 18 +
drivers/gpu/drm/i915/i915_drv.h | 20 ---
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 0d4cfbd8403e..d80e3e8a9b01 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -311,6 +311,8 @@ void intel_frontbuffer_track(struct intel_frontbuffer *old,
*/
BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
BITS_PER_TYPE(atomic_t));
+ BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32);
+ BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE);
if (old) {
drm_WARN_ON(old->obj->base.dev,
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.h
b/drivers/gpu/drm/i915/display/intel_frontbuffer.h
index ff0c37b079aa..3c474ed937fb 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.h
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.h
@@ -25,6 +25,7 @@
#define __INTEL_FRONTBUFFER_H__
#include
+#include
#include
#include "gem/i915_gem_object_types.h"
@@ -48,6 +49,23 @@ struct intel_frontbuffer {
struct rcu_head rcu;
};
+/*
+ * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
+ * considered to be the frontbuffer for the given plane interface-wise. This
+ * doesn't mean that the hw necessarily already scans it out, but that any
+ * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
+ *
+ * We have one bit per pipe and per scanout plane type.
+ */
+#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
+#define INTEL_FRONTBUFFER(pipe, plane_id) \
+ BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe));
+#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
+ BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 +
INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
+#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
+ GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
+ INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
+
void intel_frontbuffer_flip_prepare(struct drm_i915_private *i915,
unsigned frontbuffer_bits);
void intel_frontbuffer_flip_complete(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 19f41526c70a..acc04bf58be9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -483,26 +483,6 @@ static inline struct intel_gt *to_gt(struct
drm_i915_private *i915)
#define I915_GTT_OFFSET_NONE ((u32)-1)
-/*
- * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
- * considered to be the frontbuffer for the given plane interface-wise. This
- * doesn't mean that the hw necessarily already scans it out, but that any
- * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
- *
- * We have one bit per pipe and per scanout plane type.
- */
-#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
-#define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
- BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
- BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
- BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
-})
-#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
- BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 +
INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
-#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
- GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
- INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
-
#define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
--
2.34.1
[Intel-gfx] [PATCH 30/39] drm/i915: move fb_tracking under display sub-struct
Move display related members under drm_i915_private display sub-struct.
Rename struct i915_frontbuffer_tracking to intel_frontbuffer_tracking
while at it.
FIXME: fb_tracking.lock mutex init should be moved away from
i915_gem_init_early().
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_display_core.h | 12 +
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../gpu/drm/i915/display/intel_frontbuffer.c | 54 +--
drivers/gpu/drm/i915/i915_drv.h | 14 -
drivers/gpu/drm/i915/i915_gem.c | 2 +-
5 files changed, 42 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 714fb1a6bda3..f3fc69d4b7e0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -119,6 +119,17 @@ struct intel_dpll {
} ref_clks;
};
+struct intel_frontbuffer_tracking {
+ spinlock_t lock;
+
+ /*
+* Tracking bits for delayed frontbuffer flushing du to gpu activity or
+* scheduled flips.
+*/
+ unsigned busy_bits;
+ unsigned flip_bits;
+};
+
struct intel_hotplug {
struct delayed_work hotplug_work;
@@ -365,6 +376,7 @@ struct intel_display {
struct intel_dmc dmc;
struct intel_dpll dpll;
struct intel_fbc *fbc[I915_MAX_FBCS];
+ struct intel_frontbuffer_tracking fb_tracking;
struct intel_hotplug hotplug;
struct intel_opregion opregion;
struct intel_overlay *overlay;
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 619523f85a18..5dc364e9db49 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -37,10 +37,10 @@ static int i915_frontbuffer_tracking(struct seq_file *m,
void *unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
seq_printf(m, "FB tracking busy bits: 0x%08x\n",
- dev_priv->fb_tracking.busy_bits);
+ dev_priv->display.fb_tracking.busy_bits);
seq_printf(m, "FB tracking flip bits: 0x%08x\n",
- dev_priv->fb_tracking.flip_bits);
+ dev_priv->display.fb_tracking.flip_bits);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 791248f812aa..0d4cfbd8403e 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -81,9 +81,9 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
enum fb_op_origin origin)
{
/* Delay flushing when rings are still busy.*/
- spin_lock(&i915->fb_tracking.lock);
- frontbuffer_bits &= ~i915->fb_tracking.busy_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display.fb_tracking.lock);
+ frontbuffer_bits &= ~i915->display.fb_tracking.busy_bits;
+ spin_unlock(&i915->display.fb_tracking.lock);
if (!frontbuffer_bits)
return;
@@ -111,11 +111,11 @@ static void frontbuffer_flush(struct drm_i915_private
*i915,
void intel_frontbuffer_flip_prepare(struct drm_i915_private *i915,
unsigned frontbuffer_bits)
{
- spin_lock(&i915->fb_tracking.lock);
- i915->fb_tracking.flip_bits |= frontbuffer_bits;
+ spin_lock(&i915->display.fb_tracking.lock);
+ i915->display.fb_tracking.flip_bits |= frontbuffer_bits;
/* Remove stale busy bits due to the old buffer. */
- i915->fb_tracking.busy_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ i915->display.fb_tracking.busy_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display.fb_tracking.lock);
}
/**
@@ -131,11 +131,11 @@ void intel_frontbuffer_flip_prepare(struct
drm_i915_private *i915,
void intel_frontbuffer_flip_complete(struct drm_i915_private *i915,
unsigned frontbuffer_bits)
{
- spin_lock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display.fb_tracking.lock);
/* Mask any cancelled flips. */
- frontbuffer_bits &= i915->fb_tracking.flip_bits;
- i915->fb_tracking.flip_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ frontbuffer_bits &= i915->display.fb_tracking.flip_bits;
+ i915->display.fb_tracking.flip_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display.fb_tracking.lock);
if (frontbuffer_bits)
frontbuffer_flush(i915, frontbuffer_bits, ORIGIN_FLIP);
@@ -155,10 +155,10 @@ void intel_frontbuffer_flip_complete(struct
drm_i915_private *i915,
void intel_frontbuffer_flip(struct drm_i915_private *i915,
unsigned frontbuffer_bits
[Intel-gfx] [PATCH 36/39] drm/i915/quirks: abstract quirks further by making quirk ids an enum
Turn the quirk ids to enums instead of bits, and hide the masking inside
intel_quirks.c. Define the enums in intel_quirks.h to declutter
i915_drv.h while at it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_quirks.c | 21 +
drivers/gpu/drm/i915/display/intel_quirks.h | 11 ++-
drivers/gpu/drm/i915/i915_drv.h | 7 ---
3 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c
b/drivers/gpu/drm/i915/display/intel_quirks.c
index 9b5db1193a00..22e0df9d9dba 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.c
+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
@@ -9,12 +9,17 @@
#include "intel_display_types.h"
#include "intel_quirks.h"
+static void intel_set_quirk(struct drm_i915_private *i915, enum intel_quirk_id
quirk)
+{
+ i915->quirks |= BIT(quirk);
+}
+
/*
* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
*/
static void quirk_ssc_force_disable(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_LVDS_SSC_DISABLE;
+ intel_set_quirk(i915, QUIRK_LVDS_SSC_DISABLE);
drm_info(&i915->drm, "applying lvds SSC disable quirk\n");
}
@@ -24,14 +29,14 @@ static void quirk_ssc_force_disable(struct drm_i915_private
*i915)
*/
static void quirk_invert_brightness(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_INVERT_BRIGHTNESS;
+ intel_set_quirk(i915, QUIRK_INVERT_BRIGHTNESS);
drm_info(&i915->drm, "applying inverted panel brightness quirk\n");
}
/* Some VBT's incorrectly indicate no backlight is present */
static void quirk_backlight_present(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_BACKLIGHT_PRESENT;
+ intel_set_quirk(i915, QUIRK_BACKLIGHT_PRESENT);
drm_info(&i915->drm, "applying backlight present quirk\n");
}
@@ -40,7 +45,7 @@ static void quirk_backlight_present(struct drm_i915_private
*i915)
*/
static void quirk_increase_t12_delay(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_INCREASE_T12_DELAY;
+ intel_set_quirk(i915, QUIRK_INCREASE_T12_DELAY);
drm_info(&i915->drm, "Applying T12 delay quirk\n");
}
@@ -50,13 +55,13 @@ static void quirk_increase_t12_delay(struct
drm_i915_private *i915)
*/
static void quirk_increase_ddi_disabled_time(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
+ intel_set_quirk(i915, QUIRK_INCREASE_DDI_DISABLED_TIME);
drm_info(&i915->drm, "Applying Increase DDI Disabled quirk\n");
}
static void quirk_no_pps_backlight_power_hook(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK;
+ intel_set_quirk(i915, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK);
drm_info(&i915->drm, "Applying no pps backlight power quirk\n");
}
@@ -214,7 +219,7 @@ void intel_init_quirks(struct drm_i915_private *i915)
}
}
-bool intel_has_quirk(struct drm_i915_private *i915, unsigned long quirk)
+bool intel_has_quirk(struct drm_i915_private *i915, enum intel_quirk_id quirk)
{
- return i915->quirks & quirk;
+ return i915->quirks & BIT(quirk);
}
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.h
b/drivers/gpu/drm/i915/display/intel_quirks.h
index f5e399a6e7d3..10a4d163149f 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.h
+++ b/drivers/gpu/drm/i915/display/intel_quirks.h
@@ -10,7 +10,16 @@
struct drm_i915_private;
+enum intel_quirk_id {
+ QUIRK_BACKLIGHT_PRESENT,
+ QUIRK_INCREASE_DDI_DISABLED_TIME,
+ QUIRK_INCREASE_T12_DELAY,
+ QUIRK_INVERT_BRIGHTNESS,
+ QUIRK_LVDS_SSC_DISABLE,
+ QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK,
+};
+
void intel_init_quirks(struct drm_i915_private *i915);
-bool intel_has_quirk(struct drm_i915_private *i915, unsigned long quirk);
+bool intel_has_quirk(struct drm_i915_private *i915, enum intel_quirk_id quirk);
#endif /* __INTEL_QUIRKS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 22571f77dc71..60f654db7819 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -89,13 +89,6 @@ struct vlv_s0ix_state;
#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
-#define QUIRK_LVDS_SSC_DISABLE (1<<1)
-#define QUIRK_INVERT_BRIGHTNESS (1<<2)
-#define QUIRK_BACKLIGHT_PRESENT (1<<3)
-#define QUIRK_INCREASE_T12_DELAY (1<<6)
-#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
-#define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
-
struct i915_suspend_saved_registers {
u32 saveDSPARB;
u32 saveSWF0[16];
--
2.34.1
[Intel-gfx] [PATCH 38/39] drm/i915: move atomic_helper under display sub-struct
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +++---
drivers/gpu/drm/i915/display/intel_display_core.h | 6 ++
drivers/gpu/drm/i915/i915_drv.h | 5 -
3 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f80c7797176d..818f8ea52156 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7409,7 +7409,7 @@ static void intel_atomic_helper_free_state(struct
drm_i915_private *dev_priv)
struct intel_atomic_state *state, *next;
struct llist_node *freed;
- freed = llist_del_all(&dev_priv->atomic_helper.free_list);
+ freed = llist_del_all(&dev_priv->display.atomic_helper.free_list);
llist_for_each_entry_safe(state, next, freed, freed)
drm_atomic_state_put(&state->base);
}
@@ -7417,7 +7417,7 @@ static void intel_atomic_helper_free_state(struct
drm_i915_private *dev_priv)
static void intel_atomic_helper_free_state_worker(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
- container_of(work, typeof(*dev_priv), atomic_helper.free_work);
+ container_of(work, typeof(*dev_priv),
display.atomic_helper.free_work);
intel_atomic_helper_free_state(dev_priv);
}
@@ -7709,7 +7709,7 @@ intel_atomic_commit_ready(struct i915_sw_fence *fence,
case FENCE_FREE:
{
struct intel_atomic_helper *helper =
- &to_i915(state->base.dev)->atomic_helper;
+
&to_i915(state->base.dev)->display.atomic_helper;
if (llist_add(&state->freed, &helper->free_list))
schedule_work(&helper->free_work);
@@ -8699,8 +8699,8 @@ int intel_modeset_init_noirq(struct drm_i915_private
*i915)
if (ret)
goto cleanup_vga_client_pw_domain_dmc;
- init_llist_head(&i915->atomic_helper.free_list);
- INIT_WORK(&i915->atomic_helper.free_work,
+ init_llist_head(&i915->display.atomic_helper.free_list);
+ INIT_WORK(&i915->display.atomic_helper.free_work,
intel_atomic_helper_free_state_worker);
intel_init_quirks(i915);
@@ -8993,8 +8993,8 @@ void intel_modeset_driver_remove(struct drm_i915_private
*i915)
flush_workqueue(i915->display.wq.flip);
flush_workqueue(i915->display.wq.modeset);
- flush_work(&i915->atomic_helper.free_work);
- drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
+ flush_work(&i915->display.atomic_helper.free_work);
+ drm_WARN_ON(&i915->drm,
!llist_empty(&i915->display.atomic_helper.free_list));
}
/* part #2: call after irq uninstall */
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 252da61f2c6a..a753f6d66714 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -7,6 +7,7 @@
#define __INTEL_DISPLAY_CORE_H__
#include
+#include
#include
#include
#include
@@ -270,6 +271,11 @@ struct intel_display {
} funcs;
/* Grouping using anonymous structs. Keep sorted. */
+ struct intel_atomic_helper {
+ struct llist_head free_list;
+ struct work_struct free_work;
+ } atomic_helper;
+
struct {
/* backlight registers and fields in struct intel_panel */
struct mutex lock;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e529a9575a66..1bf7b13fdeda 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -297,11 +297,6 @@ struct drm_i915_private {
struct list_head global_obj_list;
- struct intel_atomic_helper {
- struct llist_head free_list;
- struct work_struct free_work;
- } atomic_helper;
-
bool mchbar_need_disable;
struct intel_l3_parity l3_parity;
--
2.34.1
[Intel-gfx] [PATCH 34/39] drm/i915: split gem quirks from display quirks
The lone gem quirk is an outlier, not even handled by the common quirk
code. Split it to a separate gem_quirks member.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gem/i915_gem_pages.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 4 ++--
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c | 2 +-
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +++-
drivers/gpu/drm/i915/i915_gem.c | 2 +-
8 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 8357dbdcab5c..e0b39463c1b0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -66,7 +66,7 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj,
shrinkable = i915_gem_object_is_shrinkable(obj);
if (i915_gem_object_is_tiled(obj) &&
- i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
+ i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) {
GEM_BUG_ON(i915_gem_object_has_tiling_quirk(obj));
i915_gem_object_set_tiling_quirk(obj);
GEM_BUG_ON(!list_empty(&obj->mm.link));
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index 85518b28cd72..fd42b89b7162 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -278,7 +278,7 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
*/
if (i915_gem_object_has_pages(obj) &&
obj->mm.madv == I915_MADV_WILLNEED &&
- i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
+ i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) {
if (tiling == I915_TILING_NONE) {
GEM_BUG_ON(!i915_gem_object_has_tiling_quirk(obj));
i915_gem_object_clear_tiling_quirk(obj);
@@ -458,7 +458,7 @@ i915_gem_get_tiling_ioctl(struct drm_device *dev, void
*data,
}
/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
- if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
+ if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
else
args->phys_swizzle_mode = args->swizzle_mode;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 3cfc621ef363..9a6a6b5b722b 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -711,7 +711,7 @@ static bool bad_swizzling(struct drm_i915_private *i915)
{
struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
- if (i915->quirks & QUIRK_PIN_SWIZZLED_PAGES)
+ if (i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
return true;
if (has_bit17_swizzle(ggtt->bit_6_swizzle_x) ||
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 3ced9948a331..25bb3bd4c3fe 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -367,7 +367,7 @@ static int igt_partial_tiling(void *arg)
unsigned int pitch;
struct tile tile;
- if (i915->quirks & QUIRK_PIN_SWIZZLED_PAGES)
+ if (i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
/*
* The swizzling pattern is actually unknown as it
* varies based on physical address of each page.
@@ -464,7 +464,7 @@ static int igt_smoke_tiling(void *arg)
* Remember to look at the st_seed if we see a flip-flop in BAT!
*/
- if (i915->quirks & QUIRK_PIN_SWIZZLED_PAGES)
+ if (i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
return 0;
obj = huge_gem_object(i915,
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index 6ebda3d65086..cf4a326f5f48 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -727,7 +727,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
* bit17 dependent, and so we need to also prevent the pages
* from being moved.
*/
- i915->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
+ i915->gem_quirks |= GEM_QUIRK_PIN_SWIZZLED_PAGES;
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
}
diff
[Intel-gfx] [PATCH 24/39] drm/i915: move mipi_mmio_base to display.dsi
Move display related members under drm_i915_private display sub-struct.
Prefer adding anonymous sub-structs even for single members that aren't
our own structs.
Abstract mmio base member access in register definitions in a macro.
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_display_core.h | 5 +
drivers/gpu/drm/i915/display/vlv_dsi.c| 4 +-
drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 188 +-
drivers/gpu/drm/i915/i915_drv.h | 3 -
4 files changed, 102 insertions(+), 98 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 533c2e3a6685..db1ba379797e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -251,6 +251,11 @@ struct intel_display {
unsigned int max_cdclk_freq;
} cdclk;
+ struct {
+ /* VLV/CHV/BXT/GLK DSI MMIO register base address */
+ u32 mmio_base;
+ } dsi;
+
struct {
/* list of fbdev register on this device */
struct intel_fbdev *fbdev;
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
b/drivers/gpu/drm/i915/display/vlv_dsi.c
index b9b1fed99874..9651a1f00587 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1872,9 +1872,9 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
return;
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
+ dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;
else
- dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
+ dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;
intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
if (!intel_dsi)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
index 356e51515346..e065b8f2ee08 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
@@ -11,6 +11,8 @@
#define VLV_MIPI_BASE VLV_DISPLAY_BASE
#define BXT_MIPI_BASE 0x6
+#define _MIPI_MMIO_BASE(__i915) ((__i915)->display.dsi.mmio_base)
+
#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c)/* ports A and
C only */
#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
@@ -96,8 +98,8 @@
/* MIPI DSI Controller and D-PHY registers */
-#define _MIPIA_DEVICE_READY(dev_priv->mipi_mmio_base + 0xb000)
-#define _MIPIC_DEVICE_READY(dev_priv->mipi_mmio_base + 0xb800)
+#define _MIPIA_DEVICE_READY(_MIPI_MMIO_BASE(dev_priv) + 0xb000)
+#define _MIPIC_DEVICE_READY(_MIPI_MMIO_BASE(dev_priv) + 0xb800)
#define MIPI_DEVICE_READY(port)_MMIO_MIPI(port,
_MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
#define BUS_POSSESSION(1 << 3) /* set
to give bus to receiver */
#define ULPS_STATE_MASK (3 << 1)
@@ -106,11 +108,11 @@
#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
#define DEVICE_READY (1 << 0)
-#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
-#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
+#define _MIPIA_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb004)
+#define _MIPIC_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb804)
#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT,
_MIPIC_INTR_STAT)
-#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
-#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
+#define _MIPIA_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb008)
+#define _MIPIC_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb808)
#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN,
_MIPIC_INTR_EN)
#define TEARING_EFFECT(1 << 31)
#define SPL_PKT_SENT_INTERRUPT(1 << 30)
@@ -145,8 +147,8 @@
#define RXSOT_SYNC_ERROR (1 << 1)
#define RXSOT_ERROR (1 << 0)
-#define _MIPIA_DSI_FUNC_PRG(dev_priv->mipi_mmio_base + 0xb00c)
-#define _MIPIC_DSI_FUNC_PRG(dev_priv->mipi_mmio_base + 0xb80c)
+#define _MIPIA_DSI_FUNC_PRG(_MIPI_MMIO_BASE(dev_priv) + 0xb00c)
+#define _MIPIC_DSI_FUNC_PRG(_MIPI_MMIO_BASE(dev_priv) + 0xb80c)
#define MIPI_DSI_FUNC_PRG(port)_MMIO_MIPI(port,
_MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
#define CMD_MODE_NOT_SUPPORTED(0 << 13)
@@ -168,76 +170,76 @@
#defi
[Intel-gfx] [PATCH 18/39] drm/i915: move overlay to display.overlay
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
drivers/gpu/drm/i915/display/intel_overlay.c | 12 ++--
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/i915_getparam.c | 2 +-
4 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index cf31ad0c9593..a5cd3a3d440e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -33,6 +33,7 @@ struct intel_fbdev;
struct intel_fdi_funcs;
struct intel_hotplug_funcs;
struct intel_initial_plane_config;
+struct intel_overlay;
struct intel_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
@@ -253,6 +254,7 @@ struct intel_display {
struct intel_dmc dmc;
struct intel_dpll dpll;
struct intel_hotplug hotplug;
+ struct intel_overlay *overlay;
struct intel_wm wm;
};
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
b/drivers/gpu/drm/i915/display/intel_overlay.c
index 79ed8bd04a07..6f26f7f91925 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -487,7 +487,7 @@ static int intel_overlay_release_old_vid(struct
intel_overlay *overlay)
void intel_overlay_reset(struct drm_i915_private *dev_priv)
{
- struct intel_overlay *overlay = dev_priv->overlay;
+ struct intel_overlay *overlay = dev_priv->display.overlay;
if (!overlay)
return;
@@ -1113,7 +1113,7 @@ int intel_overlay_put_image_ioctl(struct drm_device *dev,
void *data,
struct drm_i915_gem_object *new_bo;
int ret;
- overlay = dev_priv->overlay;
+ overlay = dev_priv->display.overlay;
if (!overlay) {
drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
return -ENODEV;
@@ -1273,7 +1273,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev,
void *data,
struct intel_overlay *overlay;
int ret;
- overlay = dev_priv->overlay;
+ overlay = dev_priv->display.overlay;
if (!overlay) {
drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
return -ENODEV;
@@ -1416,7 +1416,7 @@ void intel_overlay_setup(struct drm_i915_private
*dev_priv)
update_polyphase_filter(overlay->regs);
update_reg_attrs(overlay, overlay->regs);
- dev_priv->overlay = overlay;
+ dev_priv->display.overlay = overlay;
drm_info(&dev_priv->drm, "Initialized overlay support.\n");
return;
@@ -1428,7 +1428,7 @@ void intel_overlay_cleanup(struct drm_i915_private
*dev_priv)
{
struct intel_overlay *overlay;
- overlay = fetch_and_zero(&dev_priv->overlay);
+ overlay = fetch_and_zero(&dev_priv->display.overlay);
if (!overlay)
return;
@@ -1457,7 +1457,7 @@ struct intel_overlay_error_state {
struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
{
- struct intel_overlay *overlay = dev_priv->overlay;
+ struct intel_overlay *overlay = dev_priv->display.overlay;
struct intel_overlay_error_state *error;
if (!overlay || !overlay->active)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ef67a5322c2d..3637ee4ca088 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -82,7 +82,6 @@ struct intel_connector;
struct intel_dp;
struct intel_encoder;
struct intel_limit;
-struct intel_overlay;
struct intel_overlay_error_state;
struct vlv_s0ix_state;
@@ -342,9 +341,6 @@ struct drm_i915_private {
bool preserve_bios_swizzle;
- /* overlay */
- struct intel_overlay *overlay;
-
/* backlight registers and fields in struct intel_panel */
struct mutex backlight_lock;
diff --git a/drivers/gpu/drm/i915/i915_getparam.c
b/drivers/gpu/drm/i915/i915_getparam.c
index 6fd15b39570c..342c8ca6414e 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -36,7 +36,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = to_gt(i915)->ggtt->num_fences;
break;
case I915_PARAM_HAS_OVERLAY:
- value = !!i915->overlay;
+ value = !!i915->display.overlay;
break;
case I915_PARAM_HAS_BSD:
value = !!intel_engine_lookup_user(i915,
--
2.34.1
[Intel-gfx] [PATCH 28/39] drm/i915: move and group power related members under display.power
Move display related members under drm_i915_private display sub-struct.
Arguably chv_phy_control and chv_phy_assert could be placed in a phy
substruct, but they are only used in the power code.
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_display_core.h | 11 ++
.../drm/i915/display/intel_display_power.c| 112 +-
.../i915/display/intel_display_power_map.c| 4 +-
.../i915/display/intel_display_power_well.c | 56 -
.../i915/display/intel_display_power_well.h | 12 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 20 +---
8 files changed, 110 insertions(+), 109 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 066e7ee0b8df..19abdd05d413 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -16,6 +16,7 @@
#include "intel_cdclk.h"
#include "intel_display.h"
+#include "intel_display_power.h"
#include "intel_dmc.h"
#include "intel_dpll_mgr.h"
#include "intel_fbc.h"
@@ -326,6 +327,16 @@ struct intel_display {
struct mutex comp_mutex;
} hdcp;
+ struct {
+ struct i915_power_domains domains;
+
+ /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
+ u32 chv_phy_control;
+
+ /* perform PHY state sanity checks? */
+ bool chv_phy_assert[2];
+ } power;
+
struct {
u32 mmio_base;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index a25e632c726f..9960b7f59146 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -243,7 +243,7 @@ bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv,
struct i915_power_domains *power_domains;
bool ret;
- power_domains = &dev_priv->power_domains;
+ power_domains = &dev_priv->display.power.domains;
mutex_lock(&power_domains->lock);
ret = __intel_display_power_is_enabled(dev_priv, domain);
@@ -291,7 +291,7 @@ void intel_display_power_set_target_dc_state(struct
drm_i915_private *dev_priv,
{
struct i915_power_well *power_well;
bool dc_off_enabled;
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains =
&dev_priv->display.power.domains;
mutex_lock(&power_domains->lock);
power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF);
@@ -339,7 +339,7 @@ assert_async_put_domain_masks_disjoint(struct
i915_power_domains *power_domains)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
-power_domains);
+display.power.domains);
return !drm_WARN_ON(&i915->drm,
bitmap_intersects(power_domains->async_put_domains[0].bits,
@@ -352,7 +352,7 @@ __async_put_domains_state_ok(struct i915_power_domains
*power_domains)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
-power_domains);
+display.power.domains);
struct intel_power_domain_mask async_put_mask;
enum intel_display_power_domain domain;
bool err = false;
@@ -375,7 +375,7 @@ static void print_power_domains(struct i915_power_domains
*power_domains,
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
-power_domains);
+display.power.domains);
enum intel_display_power_domain domain;
drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits,
POWER_DOMAIN_NUM));
@@ -390,7 +390,7 @@ print_async_put_domains_state(struct i915_power_domains
*power_domains)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
-power_domains);
+display.power.domains);
drm_dbg(&i915->drm, "async_put_wakeref %u\n",
power_domains->async_put_wakeref);
@@ -445,7 +445,7 @@ static bool
intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
enum inte
[Intel-gfx] [PATCH 37/39] drm/i915: move quirks under display sub-struct
Move display related members under drm_i915_private display sub-struct.
Prefer adding anonymous sub-structs even for single members that aren't
our own structs.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_core.h | 4
drivers/gpu/drm/i915/display/intel_quirks.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 1 -
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index da76b3eecbf5..252da61f2c6a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -367,6 +367,10 @@ struct intel_display {
struct mutex mutex;
} pps;
+ struct {
+ unsigned long mask;
+ } quirks;
+
struct {
enum {
I915_SAGV_UNKNOWN = 0,
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c
b/drivers/gpu/drm/i915/display/intel_quirks.c
index 22e0df9d9dba..e74ff042a9da 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.c
+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
@@ -11,7 +11,7 @@
static void intel_set_quirk(struct drm_i915_private *i915, enum intel_quirk_id
quirk)
{
- i915->quirks |= BIT(quirk);
+ i915->display.quirks.mask |= BIT(quirk);
}
/*
@@ -221,5 +221,5 @@ void intel_init_quirks(struct drm_i915_private *i915)
bool intel_has_quirk(struct drm_i915_private *i915, enum intel_quirk_id quirk)
{
- return i915->quirks & BIT(quirk);
+ return i915->display.quirks.mask & BIT(quirk);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 60f654db7819..e529a9575a66 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -287,7 +287,6 @@ struct drm_i915_private {
unsigned short pch_id;
unsigned long gem_quirks;
- unsigned long quirks;
struct drm_atomic_state *modeset_restore_state;
struct drm_modeset_acquire_ctx reset_ctx;
--
2.34.1
[Intel-gfx] [PATCH 32/39] drm/i915: move dbuf under display sub-struct
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_core.h | 7 +++
drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
.../drm/i915/display/intel_display_power_well.c| 2 +-
drivers/gpu/drm/i915/display/intel_modeset_setup.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h| 7 ---
drivers/gpu/drm/i915/intel_pm.c| 14 +++---
drivers/gpu/drm/i915/intel_pm.h| 4 ++--
7 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index f3fc69d4b7e0..f942d156026a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -301,6 +301,13 @@ struct intel_display {
unsigned int max_cdclk_freq;
} cdclk;
+ struct {
+ /* The current hardware dbuf configuration */
+ u8 enabled_slices;
+
+ struct intel_global_obj obj;
+ } dbuf;
+
struct {
/* VLV/CHV/BXT/GLK DSI MMIO register base address */
u32 mmio_base;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 9960b7f59146..3e2f4a3d03a4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1060,14 +1060,14 @@ void gen9_dbuf_slices_update(struct drm_i915_private
*dev_priv,
for_each_dbuf_slice(dev_priv, slice)
gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice));
- dev_priv->dbuf.enabled_slices = req_slices;
+ dev_priv->display.dbuf.enabled_slices = req_slices;
mutex_unlock(&power_domains->lock);
}
static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
{
- dev_priv->dbuf.enabled_slices =
+ dev_priv->display.dbuf.enabled_slices =
intel_enabled_dbuf_slices_mask(dev_priv);
/*
@@ -1075,7 +1075,7 @@ static void gen9_dbuf_enable(struct drm_i915_private
*dev_priv)
* figure out later which slices we have and what we need.
*/
gen9_dbuf_slices_update(dev_priv, BIT(DBUF_S1) |
- dev_priv->dbuf.enabled_slices);
+ dev_priv->display.dbuf.enabled_slices);
}
static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index bc8cf0ae623b..06569fc31493 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -945,7 +945,7 @@ static bool gen9_dc_off_power_well_enabled(struct
drm_i915_private *dev_priv,
static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
{
u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv);
- u8 enabled_dbuf_slices = dev_priv->dbuf.enabled_slices;
+ u8 enabled_dbuf_slices = dev_priv->display.dbuf.enabled_slices;
drm_WARN(&dev_priv->drm,
hw_enabled_dbuf_slices != enabled_dbuf_slices,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 6efbbb85c8ed..7c75ad1b88a0 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -34,7 +34,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc
*crtc,
struct intel_cdclk_state *cdclk_state =
to_intel_cdclk_state(i915->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(i915->dbuf.obj.state);
+ to_intel_dbuf_state(i915->display.dbuf.obj.state);
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_plane *plane;
@@ -417,7 +417,7 @@ static void intel_modeset_readout_hw_state(struct
drm_i915_private *i915)
struct intel_cdclk_state *cdclk_state =
to_intel_cdclk_state(i915->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(i915->dbuf.obj.state);
+ to_intel_dbuf_state(i915->display.dbuf.obj.state);
enum pipe pipe;
struct intel_crtc *crtc;
struct intel_encoder *encoder;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index acc04bf58be9..71ed89e91e88 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -279,13 +279,6 @@ struct drm_i915_private {
unsigned int hpll_freq;
unsigned int czclk_freq;
- struct {
- /* The current hardware dbuf
[Intel-gfx] [PATCH 35/39] drm/i915/quirks: abstract checking for display quirks
Add intel_has_quirk() for checking if a display quirk is present. Avoid
accessing i915->quirks all over the place.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_backlight.c | 7 ---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
drivers/gpu/drm/i915/display/intel_dp.c| 3 ++-
drivers/gpu/drm/i915/display/intel_panel.c | 5 +++--
drivers/gpu/drm/i915/display/intel_pps.c | 3 ++-
drivers/gpu/drm/i915/display/intel_quirks.c| 5 +
drivers/gpu/drm/i915/display/intel_quirks.h| 5 -
7 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 67ecad0f9ef1..e2bbb6fc4331 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -16,6 +16,7 @@
#include "intel_dsi_dcs_backlight.h"
#include "intel_panel.h"
#include "intel_pci_config.h"
+#include "intel_quirks.h"
/**
* scale - scale values from one range to another
@@ -86,7 +87,7 @@ u32 intel_backlight_invert_pwm_level(struct intel_connector
*connector, u32 val)
return val;
if (dev_priv->params.invert_brightness > 0 ||
- dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
+ intel_has_quirk(dev_priv, QUIRK_INVERT_BRIGHTNESS)) {
return panel->backlight.pwm_level_max - val +
panel->backlight.pwm_level_min;
}
@@ -126,7 +127,7 @@ u32 intel_backlight_level_from_pwm(struct intel_connector
*connector, u32 val)
panel->backlight.max == 0 ||
panel->backlight.pwm_level_max == 0);
if (dev_priv->params.invert_brightness > 0 ||
- (dev_priv->params.invert_brightness == 0 && dev_priv->quirks &
QUIRK_INVERT_BRIGHTNESS))
+ (dev_priv->params.invert_brightness == 0 &&
intel_has_quirk(dev_priv, QUIRK_INVERT_BRIGHTNESS)))
val = panel->backlight.pwm_level_max - (val -
panel->backlight.pwm_level_min);
return scale(val, panel->backlight.pwm_level_min,
panel->backlight.pwm_level_max,
@@ -1605,7 +1606,7 @@ int intel_backlight_setup(struct intel_connector
*connector, enum pipe pipe)
int ret;
if (!connector->panel.vbt.backlight.present) {
- if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) {
+ if (intel_has_quirk(dev_priv, QUIRK_BACKLIGHT_PRESENT)) {
drm_dbg_kms(&dev_priv->drm,
"no backlight present per VBT, but present
per quirk\n");
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 320304809ed6..de04528938dc 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -57,6 +57,7 @@
#include "intel_lspcon.h"
#include "intel_pps.h"
#include "intel_psr.h"
+#include "intel_quirks.h"
#include "intel_snps_phy.h"
#include "intel_sprite.h"
#include "intel_tc.h"
@@ -631,7 +632,7 @@ void intel_ddi_disable_transcoder_func(const struct
intel_crtc_state *crtc_state
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
- if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
+ if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
drm_dbg_kms(&dev_priv->drm,
"Quirk Increase DDI disabled time\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 935ec3661aa2..2503920903a4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -72,6 +72,7 @@
#include "intel_pch_display.h"
#include "intel_pps.h"
#include "intel_psr.h"
+#include "intel_quirks.h"
#include "intel_tc.h"
#include "intel_vdsc.h"
#include "intel_vrr.h"
@@ -5293,7 +5294,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
intel_panel_init(intel_connector);
- if (!(dev_priv->quirks & QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
+ if (!intel_has_quirk(dev_priv, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
intel_connector->panel.backlight.power =
intel_pps_backlight_power;
intel_backlight_setup(intel_connector, pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gpu/drm/i915/display/intel_panel.c
index 43dbc5a3ec37..a1b4ef1ad917 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -37,13 +37,14 @@
#include "intel_display_types.h"
#include "intel_drrs.h"
#include "intel_panel.h"
+#include "intel_quirks.h"
bool intel_panel_use_ssc(struct drm_i915_private *i915)
{
if (i915->params.panel_use_ssc >= 0)
return i915->params.panel_use_ssc != 0;
- return i915->display.vbt.lvds_use_ssc
- && !(i915->quirks &
[Intel-gfx] [PATCH 33/39] drm/i915: move and group modeset_wq and flip_wq under display.wq
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 20 +--
.../gpu/drm/i915/display/intel_display_core.h | 8
drivers/gpu/drm/i915/i915_drv.h | 5 -
3 files changed, 18 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5bf062adf9ab..f80c7797176d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7812,12 +7812,12 @@ static int intel_atomic_commit(struct drm_device *dev,
i915_sw_fence_commit(&state->commit_ready);
if (nonblock && state->modeset) {
- queue_work(dev_priv->modeset_wq, &state->base.commit_work);
+ queue_work(dev_priv->display.wq.modeset,
&state->base.commit_work);
} else if (nonblock) {
- queue_work(dev_priv->flip_wq, &state->base.commit_work);
+ queue_work(dev_priv->display.wq.flip, &state->base.commit_work);
} else {
if (state->modeset)
- flush_workqueue(dev_priv->modeset_wq);
+ flush_workqueue(dev_priv->display.wq.modeset);
intel_atomic_commit_tail(state);
}
@@ -8681,9 +8681,9 @@ int intel_modeset_init_noirq(struct drm_i915_private
*i915)
intel_dmc_ucode_init(i915);
- i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
- i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
- WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
+ i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0);
+ i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI |
+ WQ_UNBOUND,
WQ_UNBOUND_MAX_ACTIVE);
intel_mode_config_init(i915);
@@ -8990,8 +8990,8 @@ void intel_modeset_driver_remove(struct drm_i915_private
*i915)
if (!HAS_DISPLAY(i915))
return;
- flush_workqueue(i915->flip_wq);
- flush_workqueue(i915->modeset_wq);
+ flush_workqueue(i915->display.wq.flip);
+ flush_workqueue(i915->display.wq.modeset);
flush_work(&i915->atomic_helper.free_work);
drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
@@ -9032,8 +9032,8 @@ void intel_modeset_driver_remove_noirq(struct
drm_i915_private *i915)
intel_gmbus_teardown(i915);
- destroy_workqueue(i915->flip_wq);
- destroy_workqueue(i915->modeset_wq);
+ destroy_workqueue(i915->display.wq.flip);
+ destroy_workqueue(i915->display.wq.modeset);
intel_fbc_cleanup(i915);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index f942d156026a..da76b3eecbf5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -378,6 +378,14 @@ struct intel_display {
u32 block_time_us;
} sagv;
+ struct {
+ /* ordered wq for modesets */
+ struct workqueue_struct *modeset;
+
+ /* unbound hipri wq for page flips/plane updates */
+ struct workqueue_struct *flip;
+ } wq;
+
/* Grouping using named structs. Keep sorted. */
struct intel_audio audio;
struct intel_dmc dmc;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 71ed89e91e88..f9170b45663f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -288,11 +288,6 @@ struct drm_i915_private {
*/
struct workqueue_struct *wq;
- /* ordered wq for modesets */
- struct workqueue_struct *modeset_wq;
- /* unbound hipri wq for page flips/plane updates */
- struct workqueue_struct *flip_wq;
-
/* PCH chipset type */
enum intel_pch pch_type;
unsigned short pch_id;
--
2.34.1
[Intel-gfx] [PATCH 20/39] drm/i915: move and group max_bw and bw_obj under display.bw
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bw.c | 42 +--
.../gpu/drm/i915/display/intel_display_core.h | 21 ++
.../drm/i915/display/intel_modeset_setup.c| 4 +-
drivers/gpu/drm/i915/i915_drv.h | 19 -
4 files changed, 44 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 4e60ad847eb0..3eb281f2cd5e 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -292,7 +292,7 @@ static int icl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
int ipqdepth, ipqdepthpch = 16;
int dclk_max;
int maxdebw;
- int num_groups = ARRAY_SIZE(dev_priv->max_bw);
+ int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
int i, ret;
ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
@@ -308,7 +308,7 @@ static int icl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
for (i = 0; i < num_groups; i++) {
- struct intel_bw_info *bi = &dev_priv->max_bw[i];
+ struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
int clpchgroup;
int j;
@@ -363,7 +363,7 @@ static int tgl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
int dclk_max;
int maxdebw, peakbw;
int clperchgroup;
- int num_groups = ARRAY_SIZE(dev_priv->max_bw);
+ int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
int i, ret;
ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
@@ -399,13 +399,13 @@ static int tgl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * qi.deinterleave;
for (i = 0; i < num_groups; i++) {
- struct intel_bw_info *bi = &dev_priv->max_bw[i];
+ struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
struct intel_bw_info *bi_next;
int clpchgroup;
int j;
if (i < num_groups - 1)
- bi_next = &dev_priv->max_bw[i + 1];
+ bi_next = &dev_priv->display.bw.max[i + 1];
clpchgroup = (sa->deburst * qi.deinterleave / num_channels) <<
i;
@@ -466,7 +466,7 @@ static int tgl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
static void dg2_get_bw_info(struct drm_i915_private *i915)
{
unsigned int deratedbw = IS_DG2_G11(i915) ? 38000 : 5;
- int num_groups = ARRAY_SIZE(i915->max_bw);
+ int num_groups = ARRAY_SIZE(i915->display.bw.max);
int i;
/*
@@ -477,7 +477,7 @@ static void dg2_get_bw_info(struct drm_i915_private *i915)
* whereas DG2-G11 platforms have 38 GB/s.
*/
for (i = 0; i < num_groups; i++) {
- struct intel_bw_info *bi = &i915->max_bw[i];
+ struct intel_bw_info *bi = &i915->display.bw.max[i];
bi->num_planes = 1;
/* Need only one dummy QGV point per group */
@@ -498,9 +498,9 @@ static unsigned int icl_max_bw(struct drm_i915_private
*dev_priv,
*/
num_planes = max(1, num_planes);
- for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
+ for (i = 0; i < ARRAY_SIZE(dev_priv->display.bw.max); i++) {
const struct intel_bw_info *bi =
- &dev_priv->max_bw[i];
+ &dev_priv->display.bw.max[i];
/*
* Pcode will not expose all QGV points when
@@ -526,9 +526,9 @@ static unsigned int tgl_max_bw(struct drm_i915_private
*dev_priv,
*/
num_planes = max(1, num_planes);
- for (i = ARRAY_SIZE(dev_priv->max_bw) - 1; i >= 0; i--) {
+ for (i = ARRAY_SIZE(dev_priv->display.bw.max) - 1; i >= 0; i--) {
const struct intel_bw_info *bi =
- &dev_priv->max_bw[i];
+ &dev_priv->display.bw.max[i];
/*
* Pcode will not expose all QGV points when
@@ -541,14 +541,14 @@ static unsigned int tgl_max_bw(struct drm_i915_private
*dev_priv,
return bi->deratedbw[qgv_point];
}
- return dev_priv->max_bw[0].deratedbw[qgv_point];
+ return dev_priv->display.bw.max[0].deratedbw[qgv_point];
}
static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
int psf_gv_point)
{
const struct intel_bw_info *bi =
- &dev_priv->max_bw[0];
+ &dev_priv->display.bw.max[0];
return bi->psf_bw[psf_gv_point];
}
@@ -667,7 +667,7 @@ intel_atomic_get_old_bw_state(struct intel_atomi
[Intel-gfx] [PATCH 29/39] drm/i915: move and group fdi members under display.fdi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_core.h | 5 +
drivers/gpu/drm/i915/display/intel_fdi.c | 10 +-
drivers/gpu/drm/i915/i915_drv.h | 3 ---
4 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index 760b5788eb43..85c2fa632c7a 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -1110,7 +1110,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
FDI_RX_LINK_REVERSAL_OVERRIDE;
- dev_priv->fdi_rx_config = intel_de_read(dev_priv,
+ dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
FDI_RX_CTL(PIPE_A)) &
fdi_config;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 19abdd05d413..714fb1a6bda3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -301,6 +301,11 @@ struct intel_display {
struct work_struct suspend_work;
} fbdev;
+ struct {
+ unsigned int pll_freq;
+ u32 rx_config;
+ } fdi;
+
struct {
/*
* Base address of where the gmbus and gpio blocks are located
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index 03ad5f5c8417..f67dd4f05bab 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -210,14 +210,14 @@ void intel_fdi_pll_freq_update(struct drm_i915_private
*i915)
u32 fdi_pll_clk =
intel_de_read(i915, FDI_PLL_BIOS_0) &
FDI_PLL_FB_CLOCK_MASK;
- i915->fdi_pll_freq = (fdi_pll_clk + 2) * 1;
+ i915->display.fdi.pll_freq = (fdi_pll_clk + 2) * 1;
} else if (IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) {
- i915->fdi_pll_freq = 27;
+ i915->display.fdi.pll_freq = 27;
} else {
return;
}
- drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->fdi_pll_freq);
+ drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->display.fdi.pll_freq);
}
int intel_fdi_link_freq(struct drm_i915_private *i915,
@@ -226,7 +226,7 @@ int intel_fdi_link_freq(struct drm_i915_private *i915,
if (HAS_DDI(i915))
return pipe_config->port_clock; /* SPLL */
else
- return i915->fdi_pll_freq;
+ return i915->display.fdi.pll_freq;
}
int ilk_fdi_compute_config(struct intel_crtc *crtc,
@@ -789,7 +789,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) |
FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
/* Enable the PCH Receiver FDI PLL */
- rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
+ rx_ctl_val = dev_priv->display.fdi.rx_config |
FDI_RX_ENHANCE_FRAME_ENABLE |
FDI_RX_PLL_ENABLE |
FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bd15bb1efac5..5833affe263d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -289,7 +289,6 @@ struct drm_i915_private {
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
- unsigned int fdi_pll_freq;
unsigned int czclk_freq;
struct {
@@ -358,8 +357,6 @@ struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
- u32 fdi_rx_config;
-
/*
* Shadows for CHV DPLL_MD regs to keep the state
* checker somewhat working in the presence hardware
--
2.34.1
[Intel-gfx] [PATCH 13/39] drm/i915: move dpll under display.dpll
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c| 12 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 24 ++--
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
.../gpu/drm/i915/display/intel_display_core.h | 21
.../drm/i915/display/intel_display_debugfs.c | 8 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 112 +-
.../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 21
9 files changed, 104 insertions(+), 104 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 5dcfa7feffa9..49357e4ed3be 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -641,13 +641,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder
*encoder)
u32 tmp;
enum phy phy;
- mutex_lock(&dev_priv->dpll.lock);
+ mutex_lock(&dev_priv->display.dpll.lock);
tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys)
tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
- mutex_unlock(&dev_priv->dpll.lock);
+ mutex_unlock(&dev_priv->display.dpll.lock);
}
static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
@@ -657,13 +657,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder
*encoder)
u32 tmp;
enum phy phy;
- mutex_lock(&dev_priv->dpll.lock);
+ mutex_lock(&dev_priv->display.dpll.lock);
tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys)
tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
- mutex_unlock(&dev_priv->dpll.lock);
+ mutex_unlock(&dev_priv->display.dpll.lock);
}
static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
@@ -693,7 +693,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
enum phy phy;
u32 val;
- mutex_lock(&dev_priv->dpll.lock);
+ mutex_lock(&dev_priv->display.dpll.lock);
val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys) {
@@ -709,7 +709,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
- mutex_unlock(&dev_priv->dpll.lock);
+ mutex_unlock(&dev_priv->display.dpll.lock);
}
static void
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index a4c8493f3ce7..23c8287b0262 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1425,7 +1425,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t
reg,
u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
{
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display.dpll.lock);
intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
@@ -1435,17 +1435,17 @@ static void _icl_ddi_enable_clock(struct
drm_i915_private *i915, i915_reg_t reg,
*/
intel_de_rmw(i915, reg, clk_off, 0);
- mutex_unlock(&i915->dpll.lock);
+ mutex_unlock(&i915->display.dpll.lock);
}
static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t
reg,
u32 clk_off)
{
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display.dpll.lock);
intel_de_rmw(i915, reg, 0, clk_off);
- mutex_unlock(&i915->dpll.lock);
+ mutex_unlock(&i915->display.dpll.lock);
}
static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915,
i915_reg_t reg,
@@ -1720,12 +1720,12 @@ static void icl_ddi_tc_enable_clock(struct
intel_encoder *encoder,
intel_de_write(i915, DDI_CLK_SEL(port),
icl_pll_to_ddi_clk_sel(encoder, crtc_state));
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display.dpll.lock);
intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
- mutex_unlock(&i915->dpll.lock);
+ mutex_unlock(&i915->display.dpll.lock);
}
static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
@@ -1734,12 +1734,12 @@ static void icl_ddi_tc_disable_clock(struct
intel_encoder *encoder)
enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
enum port port = encoder->port;
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display.dpll.lock);
intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
0, ICL_DPCLKA_CFGCR0_TC
[Intel-gfx] [PATCH 27/39] drm/i915/vrr: drop window2_delay member from i915
The window2_delay member has been functionally unused (always set to 0)
since it was added in commit bb265dbdf38d ("drm/i915/xelpd: Add VRR
guardband for VRR CTL"). Replace it with a FIXME comment.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 2 --
drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++
drivers/gpu/drm/i915/i915_drv.h | 3 ---
3 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f98ca4debcbe..5bf062adf9ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8685,8 +8685,6 @@ int intel_modeset_init_noirq(struct drm_i915_private
*i915)
i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
- i915->window2_delay = 0; /* No DSB so no window2 delay */
-
intel_mode_config_init(i915);
ret = intel_cdclk_init(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 04250a0fec3c..291374689ee7 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -142,11 +142,16 @@ intel_vrr_compute_config(struct intel_crtc_state
*crtc_state,
* For XE_LPD+, we use guardband and pipeline override
* is deprecated.
*/
- if (DISPLAY_VER(i915) >= 13)
+ if (DISPLAY_VER(i915) >= 13) {
+ /*
+* FIXME: Substract Window2 delay from below value.
+*
+* Window2 specifies time required to program DSB (Window2) in
+* number of scan lines. Assuming 0 for no DSB.
+*/
crtc_state->vrr.guardband =
- crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay -
- i915->window2_delay;
- else
+ crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;
+ } else {
/*
* FIXME: s/4/framestart_delay/ to get consistent
* earliest/latest points for register latching regardless
@@ -159,6 +164,7 @@ intel_vrr_compute_config(struct intel_crtc_state
*crtc_state,
*/
crtc_state->vrr.pipeline_full =
min(255, crtc_state->vrr.vmin -
adjusted_mode->crtc_vdisplay - 4 - 1);
+ }
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 752eeccb94eb..6fa5ab1f173f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -426,9 +426,6 @@ struct drm_i915_private {
struct file *mmap_singleton;
} gem;
- /* Window2 specifies time required to program DSB (Window2) in number
of scan lines */
- u8 window2_delay;
-
u8 pch_ssc_use;
/* For i915gm/i945gm vblank irq workaround */
--
2.34.1
[Intel-gfx] [PATCH 21/39] drm/i915: move opregion to display.opregion
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
.../gpu/drm/i915/display/intel_display_core.h | 2 +
.../drm/i915/display/intel_display_debugfs.c | 6 ++-
drivers/gpu/drm/i915/display/intel_opregion.c | 42 +--
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/i915_irq.c | 2 +-
6 files changed, 30 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 51dde5bfd956..5923cce94c11 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3078,7 +3078,7 @@ static struct vbt_header *oprom_get_vbt(struct
drm_i915_private *i915)
*/
void intel_bios_init(struct drm_i915_private *i915)
{
- const struct vbt_header *vbt = i915->opregion.vbt;
+ const struct vbt_header *vbt = i915->display.opregion.vbt;
struct vbt_header *oprom_vbt = NULL;
const struct bdb_header *bdb;
@@ -3285,7 +3285,7 @@ bool intel_bios_is_lvds_present(struct drm_i915_private
*i915, u8 *i2c_pin)
* additional data. Trust that if the VBT was written into
* the OpRegion then they have validated the LVDS's existence.
*/
- if (i915->opregion.vbt)
+ if (i915->display.opregion.vbt)
return true;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 65c3394d2e7f..948415e1a64e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -16,6 +16,7 @@
#include "intel_dpll_mgr.h"
#include "intel_global_state.h"
#include "intel_gmbus.h"
+#include "intel_opregion.h"
#include "intel_pm_types.h"
struct drm_i915_private;
@@ -286,6 +287,7 @@ struct intel_display {
struct intel_dmc dmc;
struct intel_dpll dpll;
struct intel_hotplug hotplug;
+ struct intel_opregion opregion;
struct intel_overlay *overlay;
struct intel_wm wm;
};
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 13c855b59f7d..619523f85a18 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -103,7 +103,8 @@ static int i915_sr_status(struct seq_file *m, void *unused)
static int i915_opregion(struct seq_file *m, void *unused)
{
- struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_opregion *opregion = &i915->display.opregion;
if (opregion->header)
seq_write(m, opregion->header, OPREGION_SIZE);
@@ -113,7 +114,8 @@ static int i915_opregion(struct seq_file *m, void *unused)
static int i915_vbt(struct seq_file *m, void *unused)
{
- struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_opregion *opregion = &i915->display.opregion;
if (opregion->vbt)
seq_write(m, opregion->vbt, opregion->vbt_size);
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
b/drivers/gpu/drm/i915/display/intel_opregion.c
index 1c0c745c142d..caa07ef34f21 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -252,7 +252,7 @@ struct opregion_asle_ext {
static int check_swsci_function(struct drm_i915_private *i915, u32 function)
{
- struct opregion_swsci *swsci = i915->opregion.swsci;
+ struct opregion_swsci *swsci = i915->display.opregion.swsci;
u32 main_function, sub_function;
if (!swsci)
@@ -265,11 +265,11 @@ static int check_swsci_function(struct drm_i915_private
*i915, u32 function)
/* Check if we can call the function. See swsci_setup for details. */
if (main_function == SWSCI_SBCB) {
- if ((i915->opregion.swsci_sbcb_sub_functions &
+ if ((i915->display.opregion.swsci_sbcb_sub_functions &
(1 << sub_function)) == 0)
return -EINVAL;
} else if (main_function == SWSCI_GBDA) {
- if ((i915->opregion.swsci_gbda_sub_functions &
+ if ((i915->display.opregion.swsci_gbda_sub_functions &
(1 << sub_function)) == 0)
return -EINVAL;
}
@@ -280,7 +280,7 @@ static int check_swsci_function(struct drm_i915_private
*i915, u32 function)
static int swsci(struct drm_i915_private *dev_priv,
u32 function, u32 parm, u32 *parm_out)
{
- struct opregion_swsci *swsci = dev_priv->opregion.swsci;
+ struct
[Intel-gfx] [PATCH 19/39] drm/i915: move and group sagv under display.sagv
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bw.c | 10 ++---
.../gpu/drm/i915/display/intel_display_core.h | 11 ++
drivers/gpu/drm/i915/i915_drv.h | 9 -
drivers/gpu/drm/i915/intel_pm.c | 38 +--
4 files changed, 35 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 79269d2c476b..4e60ad847eb0 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -346,9 +346,9 @@ static int icl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
* as it will fail and pointless anyway.
*/
if (qi.num_points == 1)
- dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
else
- dev_priv->sagv_status = I915_SAGV_ENABLED;
+ dev_priv->display.sagv.status = I915_SAGV_ENABLED;
return 0;
}
@@ -456,9 +456,9 @@ static int tgl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
* as it will fail and pointless anyway.
*/
if (qi.num_points == 1)
- dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
else
- dev_priv->sagv_status = I915_SAGV_ENABLED;
+ dev_priv->display.sagv.status = I915_SAGV_ENABLED;
return 0;
}
@@ -485,7 +485,7 @@ static void dg2_get_bw_info(struct drm_i915_private *i915)
bi->deratedbw[0] = deratedbw;
}
- i915->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
}
static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index a5cd3a3d440e..ab68c8799d1c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -249,6 +249,17 @@ struct intel_display {
struct mutex mutex;
} pps;
+ struct {
+ enum {
+ I915_SAGV_UNKNOWN = 0,
+ I915_SAGV_DISABLED,
+ I915_SAGV_ENABLED,
+ I915_SAGV_NOT_CONTROLLED
+ } status;
+
+ u32 block_time_us;
+ } sagv;
+
/* Grouping using named structs. Keep sorted. */
struct intel_audio audio;
struct intel_dmc dmc;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3637ee4ca088..daa6266ef127 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -447,15 +447,6 @@ struct drm_i915_private {
struct i915_suspend_saved_registers regfile;
struct vlv_s0ix_state *vlv_s0ix_state;
- enum {
- I915_SAGV_UNKNOWN = 0,
- I915_SAGV_DISABLED,
- I915_SAGV_ENABLED,
- I915_SAGV_NOT_CONTROLLED
- } sagv_status;
-
- u32 sagv_block_time_us;
-
struct dram_info {
bool wm_lv_0_adjust_needed;
u8 num_channels;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 14134e57034e..f72481e85ebd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3669,7 +3669,7 @@ static bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
return DISPLAY_VER(dev_priv) >= 9 && !IS_LP(dev_priv) &&
- dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
+ dev_priv->display.sagv.status != I915_SAGV_NOT_CONTROLLED;
}
static u32
@@ -3700,7 +3700,7 @@ intel_sagv_block_time(struct drm_i915_private *dev_priv)
static void intel_sagv_init(struct drm_i915_private *i915)
{
if (!intel_has_sagv(i915))
- i915->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
/*
* Probe to see if we have working SAGV control.
@@ -3709,21 +3709,21 @@ static void intel_sagv_init(struct drm_i915_private
*i915)
if (DISPLAY_VER(i915) < 11)
skl_sagv_disable(i915);
- drm_WARN_ON(&i915->drm, i915->sagv_status == I915_SAGV_UNKNOWN);
+ drm_WARN_ON(&i915->drm, i915->display.sagv.status == I915_SAGV_UNKNOWN);
- i915->sagv_block_time_us = intel_sagv_block_time(i915);
+ i915->display.sagv.block_time_us = intel_sagv_block_time(i915);
drm_dbg_kms(&i915->drm, "SAGV supported: %s, original SAGV block time:
%u us\n",
- str_yes_no(intel_has_sagv(i915)), i915->sagv_block_time_us);
+ str_yes_no(intel_has_sagv(i915)),
i915->display.sa
[Intel-gfx] [PATCH 25/39] drm/i915: move vbt to display.vbt
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 210 +-
drivers/gpu/drm/i915/display/intel_crt.c | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 12 +-
.../gpu/drm/i915/display/intel_display_core.h | 38
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 14 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 18 +-
drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 4 +-
drivers/gpu/drm/i915/display/intel_panel.c| 2 +-
.../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 18 +-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 37 ---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
15 files changed, 187 insertions(+), 186 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 5923cce94c11..e06c38cbeea0 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -159,7 +159,7 @@ find_section(struct drm_i915_private *i915,
{
struct bdb_block_entry *entry;
- list_for_each_entry(entry, &i915->vbt.bdb_blocks, node) {
+ list_for_each_entry(entry, &i915->display.vbt.bdb_blocks, node) {
if (entry->section_id == section_id)
return entry->data + 3;
}
@@ -501,7 +501,7 @@ init_bdb_block(struct drm_i915_private *i915,
return;
}
- list_add_tail(&entry->node, &i915->vbt.bdb_blocks);
+ list_add_tail(&entry->node, &i915->display.vbt.bdb_blocks);
}
static void init_bdb_blocks(struct drm_i915_private *i915,
@@ -878,7 +878,7 @@ parse_lfp_data(struct drm_i915_private *i915,
if (!tail)
return;
- if (i915->vbt.version >= 188) {
+ if (i915->display.vbt.version >= 188) {
panel->vbt.seamless_drrs_min_refresh_rate =
tail->seamless_drrs_min_refresh_rate[panel_type];
drm_dbg_kms(&i915->drm,
@@ -904,7 +904,7 @@ parse_generic_dtd(struct drm_i915_private *i915,
* first on VBT >= 229, but still fall back to trying the old LFP
* block if that fails.
*/
- if (i915->vbt.version < 229)
+ if (i915->display.vbt.version < 229)
return;
generic_dtd = find_section(i915, BDB_GENERIC_DTD);
@@ -1008,12 +1008,12 @@ parse_lfp_backlight(struct drm_i915_private *i915,
}
panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
- if (i915->vbt.version >= 191) {
+ if (i915->display.vbt.version >= 191) {
size_t exp_size;
- if (i915->vbt.version >= 236)
+ if (i915->display.vbt.version >= 236)
exp_size = sizeof(struct bdb_lfp_backlight_data);
- else if (i915->vbt.version >= 234)
+ else if (i915->display.vbt.version >= 234)
exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_234;
else
exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_191;
@@ -1030,14 +1030,14 @@ parse_lfp_backlight(struct drm_i915_private *i915,
panel->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
panel->vbt.backlight.active_low_pwm = entry->active_low_pwm;
- if (i915->vbt.version >= 234) {
+ if (i915->display.vbt.version >= 234) {
u16 min_level;
bool scale;
level = backlight_data->brightness_level[panel_type].level;
min_level =
backlight_data->brightness_min_level[panel_type].level;
- if (i915->vbt.version >= 236)
+ if (i915->display.vbt.version >= 236)
scale =
backlight_data->brightness_precision_bits[panel_type] == 16;
else
scale = level > 255;
@@ -1134,37 +1134,37 @@ parse_general_features(struct drm_i915_private *i915)
if (!general)
return;
- i915->vbt.int_tv_support = general->int_tv_support;
+ i915->display.vbt.int_tv_support = general->int_tv_support;
/* int_crt_support can't be trusted on earlier platforms */
- if (i915->vbt.version >= 155 &&
+ if (i915->display.vbt.version >= 155 &&
(HAS_DDI(i915) || IS_VALLEYVIEW(i915)))
- i915->vbt.int_crt_support = general->int_crt_support;
- i915->vbt.lvds_use_ssc = general->enable_ssc;
- i915->vbt.lvds_ssc_freq =
+ i915->display.vbt.int_crt_support = general->int_crt_support;
+ i915->display.vbt.lvds_use_ssc = general->enable_ssc;
+ i915->display.vbt.lvds_ssc_freq =
intel_bios_ssc_frequency(i915, general->ssc_f
[Intel-gfx] [PATCH 14/39] drm/i915: move and group fbdev under display.fbdev
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_display_core.h | 8 ++
.../drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbdev.c| 26 +--
drivers/gpu/drm/i915/i915_drv.h | 5
4 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index f12ff36fef07..71434a922695 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include "intel_display.h"
#include "intel_dmc.h"
@@ -26,6 +27,7 @@ struct intel_crtc;
struct intel_crtc_state;
struct intel_dpll_funcs;
struct intel_dpll_mgr;
+struct intel_fbdev;
struct intel_fdi_funcs;
struct intel_hotplug_funcs;
struct intel_initial_plane_config;
@@ -130,6 +132,12 @@ struct intel_display {
} funcs;
/* Grouping using anonymous structs. Keep sorted. */
+ struct {
+ /* list of fbdev register on this device */
+ struct intel_fbdev *fbdev;
+ struct work_struct suspend_work;
+ } fbdev;
+
struct {
/*
* Base address of where the gmbus and gpio blocks are located
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 7994f78b889a..e568590faa82 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -129,7 +129,7 @@ static int i915_gem_framebuffer_info(struct seq_file *m,
void *data)
struct drm_framebuffer *drm_fb;
#ifdef CONFIG_DRM_FBDEV_EMULATION
- fbdev_fb = intel_fbdev_framebuffer(dev_priv->fbdev);
+ fbdev_fb = intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev);
if (fbdev_fb) {
seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier
0x%llx, refcount %d, obj ",
fbdev_fb->base.width,
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 221336178991..c08ff6a5c2e9 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -500,7 +500,7 @@ static void intel_fbdev_suspend_worker(struct work_struct
*work)
{
intel_fbdev_set_suspend(&container_of(work,
struct drm_i915_private,
- fbdev_suspend_work)->drm,
+ display.fbdev.suspend_work)->drm,
FBINFO_STATE_RUNNING,
true);
}
@@ -530,8 +530,8 @@ int intel_fbdev_init(struct drm_device *dev)
return ret;
}
- dev_priv->fbdev = ifbdev;
- INIT_WORK(&dev_priv->fbdev_suspend_work, intel_fbdev_suspend_worker);
+ dev_priv->display.fbdev.fbdev = ifbdev;
+ INIT_WORK(&dev_priv->display.fbdev.suspend_work,
intel_fbdev_suspend_worker);
return 0;
}
@@ -548,7 +548,7 @@ static void intel_fbdev_initial_config(void *data,
async_cookie_t cookie)
void intel_fbdev_initial_config_async(struct drm_device *dev)
{
- struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
+ struct intel_fbdev *ifbdev = to_i915(dev)->display.fbdev.fbdev;
if (!ifbdev)
return;
@@ -568,12 +568,12 @@ static void intel_fbdev_sync(struct intel_fbdev *ifbdev)
void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
{
- struct intel_fbdev *ifbdev = dev_priv->fbdev;
+ struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev;
if (!ifbdev)
return;
- cancel_work_sync(&dev_priv->fbdev_suspend_work);
+ cancel_work_sync(&dev_priv->display.fbdev.suspend_work);
if (!current_is_async())
intel_fbdev_sync(ifbdev);
@@ -582,7 +582,7 @@ void intel_fbdev_unregister(struct drm_i915_private
*dev_priv)
void intel_fbdev_fini(struct drm_i915_private *dev_priv)
{
- struct intel_fbdev *ifbdev = fetch_and_zero(&dev_priv->fbdev);
+ struct intel_fbdev *ifbdev =
fetch_and_zero(&dev_priv->display.fbdev.fbdev);
if (!ifbdev)
return;
@@ -596,7 +596,7 @@ void intel_fbdev_fini(struct drm_i915_private *dev_priv)
*/
static void intel_fbdev_hpd_set_suspend(struct drm_i915_private *i915, int
state)
{
- struct intel_fbdev *ifbdev = i915->fbdev;
+ struct intel_fbdev *ifbdev = i915->display.fbdev.fbdev;
bool send_hpd = false;
mutex_lock(&ifbdev->hpd_lock);
@@ -614,7 +614,7 @@ static void intel_fbdev_hpd_set_suspend(struct
drm_i915_private *i915, int state
void intel_fbdev_set_suspend(struct drm_device *dev, int st
[Intel-gfx] [PATCH 22/39] drm/i915: move and group cdclk under display.cdclk
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/hsw_ips.c| 2 +-
drivers/gpu/drm/i915/display/intel_audio.c| 6 +-
.../gpu/drm/i915/display/intel_backlight.c| 4 +-
drivers/gpu/drm/i915/display/intel_cdclk.c| 206 +-
drivers/gpu/drm/i915/display/intel_cdclk.h| 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
.../gpu/drm/i915/display/intel_display_core.h | 14 ++
.../drm/i915/display/intel_display_power.c| 2 +-
.../i915/display/intel_display_power_well.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 +-
.../drm/i915/display/intel_modeset_setup.c| 4 +-
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 15 --
15 files changed, 141 insertions(+), 142 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c
b/drivers/gpu/drm/i915/display/hsw_ips.c
index 861dcd2eb890..a5be4af792cb 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -202,7 +202,7 @@ bool hsw_crtc_state_ips_capable(const struct
intel_crtc_state *crtc_state)
* Should measure whether using a lower cdclk w/o IPS
*/
if (IS_BROADWELL(i915) &&
- crtc_state->pixel_rate > i915->max_cdclk_freq * 95 / 100)
+ crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 /
100)
return false;
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index a74fc79b7910..aacbc6da84ef 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -532,7 +532,7 @@ static unsigned int calc_hblank_early_prog(struct
intel_encoder *encoder,
h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
vdsc_bpp = crtc_state->dsc.compressed_bpp;
- cdclk = i915->cdclk.hw.cdclk;
+ cdclk = i915->display.cdclk.hw.cdclk;
/* fec= 0.972261, using rounding multiplier of 100 */
fec_coeff = 972261;
link_clk = crtc_state->port_clock;
@@ -971,7 +971,7 @@ void intel_audio_cdclk_change_post(struct drm_i915_private
*i915)
struct aud_ts_cdclk_m_n aud_ts;
if (DISPLAY_VER(i915) >= 13) {
- get_aud_ts_cdclk_m_n(i915->cdclk.hw.ref, i915->cdclk.hw.cdclk,
&aud_ts);
+ get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref,
i915->display.cdclk.hw.cdclk, &aud_ts);
intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n);
intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m |
AUD_TS_CDCLK_M_EN);
@@ -1119,7 +1119,7 @@ static int i915_audio_component_get_cdclk_freq(struct
device *kdev)
if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv)))
return -ENODEV;
- return dev_priv->cdclk.hw.cdclk;
+ return dev_priv->display.cdclk.hw.cdclk;
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 110fc98ec280..fbe87ec458be 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1113,7 +1113,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector
*connector, u32 pwm_freq_hz)
if (IS_PINEVIEW(dev_priv))
clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq);
else
- clock = KHz(dev_priv->cdclk.hw.cdclk);
+ clock = KHz(dev_priv->display.cdclk.hw.cdclk);
return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 32);
}
@@ -1131,7 +1131,7 @@ static u32 i965_hz_to_pwm(struct intel_connector
*connector, u32 pwm_freq_hz)
if (IS_G4X(dev_priv))
clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq);
else
- clock = KHz(dev_priv->cdclk.hw.cdclk);
+ clock = KHz(dev_priv->display.cdclk.hw.cdclk);
return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 128);
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ea40c75c2986..9f8bbf9ddfa1 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -548,7 +548,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv)
else
default_credits = PFI_CREDIT(8);
- if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
+ if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) {
/* CHV suggested value is 31 or 63 */
if (IS_CHERRYVIEW(dev_priv))
credits = PFI_CREDIT_63;
@@ -1026,7 +1026,7 @@ static void skl_dpll0_enable(struct drm_i915_private
*dev_priv,
[Intel-gfx] [PATCH 23/39] drm/i915: move backlight to display.backlight
Move display related members under drm_i915_private display sub-struct. Prefer adding anonymous sub-structs even for single members that aren't our own structs. Signed-off-by: Jani Nikula --- .../gpu/drm/i915/display/intel_backlight.c| 28 +-- .../gpu/drm/i915/display/intel_display_core.h | 5 drivers/gpu/drm/i915/i915_driver.c| 2 +- drivers/gpu/drm/i915/i915_drv.h | 3 -- 4 files changed, 20 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c index fbe87ec458be..67ecad0f9ef1 100644 --- a/drivers/gpu/drm/i915/display/intel_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_backlight.c @@ -303,7 +303,7 @@ void intel_backlight_set_acpi(const struct drm_connector_state *conn_state, if (!panel->backlight.present || !conn_state->crtc) return; - mutex_lock(&dev_priv->backlight_lock); + mutex_lock(&dev_priv->display.backlight.lock); drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0); @@ -319,7 +319,7 @@ void intel_backlight_set_acpi(const struct drm_connector_state *conn_state, if (panel->backlight.enabled) intel_panel_actually_set_backlight(conn_state, hw_level); - mutex_unlock(&dev_priv->backlight_lock); + mutex_unlock(&dev_priv->display.backlight.lock); } static void lpt_disable_backlight(const struct drm_connector_state *old_conn_state, u32 level) @@ -463,14 +463,14 @@ void intel_backlight_disable(const struct drm_connector_state *old_conn_state) return; } - mutex_lock(&dev_priv->backlight_lock); + mutex_lock(&dev_priv->display.backlight.lock); if (panel->backlight.device) panel->backlight.device->props.power = FB_BLANK_POWERDOWN; panel->backlight.enabled = false; panel->backlight.funcs->disable(old_conn_state, 0); - mutex_unlock(&dev_priv->backlight_lock); + mutex_unlock(&dev_priv->display.backlight.lock); } static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state, @@ -813,11 +813,11 @@ void intel_backlight_enable(const struct intel_crtc_state *crtc_state, drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(pipe)); - mutex_lock(&dev_priv->backlight_lock); + mutex_lock(&dev_priv->display.backlight.lock); __intel_backlight_enable(crtc_state, conn_state); - mutex_unlock(&dev_priv->backlight_lock); + mutex_unlock(&dev_priv->display.backlight.lock); } #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) @@ -827,12 +827,12 @@ static u32 intel_panel_get_backlight(struct intel_connector *connector) struct intel_panel *panel = &connector->panel; u32 val = 0; - mutex_lock(&dev_priv->backlight_lock); + mutex_lock(&dev_priv->display.backlight.lock); if (panel->backlight.enabled) val = panel->backlight.funcs->get(connector, intel_connector_get_pipe(connector)); - mutex_unlock(&dev_priv->backlight_lock); + mutex_unlock(&dev_priv->display.backlight.lock); drm_dbg_kms(&dev_priv->drm, "get backlight PWM = %d\n", val); return val; @@ -860,7 +860,7 @@ static void intel_panel_set_backlight(const struct drm_connector_state *conn_sta if (!panel->backlight.present) return; - mutex_lock(&dev_priv->backlight_lock); + mutex_lock(&dev_priv->display.backlight.lock); drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0); @@ -870,7 +870,7 @@ static void intel_panel_set_backlight(const struct drm_connector_state *conn_sta if (panel->backlight.enabled) intel_panel_actually_set_backlight(conn_state, hw_level); - mutex_unlock(&dev_priv->backlight_lock); + mutex_unlock(&dev_priv->display.backlight.lock); } static int intel_backlight_device_update_status(struct backlight_device *bd) @@ -1591,11 +1591,11 @@ void intel_backlight_update(struct intel_atomic_state *state, if (!panel->backlight.present) return; - mutex_lock(&dev_priv->backlight_lock); + mutex_lock(&dev_priv->display.backlight.lock); if (!panel->backlight.enabled) __intel_backlight_enable(crtc_state, conn_state); - mutex_unlock(&dev_priv->backlight_lock); + mutex_unlock(&dev_priv->display.backlight.lock); } int intel_backlight_setup(struct intel_connector *connector, enum pipe pipe) @@ -1620,9 +1620,9 @@ int intel_backlight_setup(struct intel_connector *connector, enum pipe pipe) return -ENODEV; /* set level and max in panel struct */ - mutex_lock(&dev_priv->backlight_lock); + mutex_lock(&dev_priv->display.backlight.lock); ret = panel->backlight.funcs->setup(connector, pipe); - mutex_unlock(&dev_priv->backlight_lock); + mutex_unlock(&dev_priv->display.backlight
[Intel-gfx] [PATCH 15/39] drm/i915: move wm to display.wm
Move display related members under drm_i915_private display sub-struct.
It's a bit arbitrary when to define a named struct for grouping, but
clearly intel_wm is big enough to warrant a separate definition.
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_display_core.h | 38
.../drm/i915/display/intel_display_debugfs.c | 24 +--
drivers/gpu/drm/i915/i915_driver.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h | 37
drivers/gpu/drm/i915/intel_pm.c | 166 +-
5 files changed, 134 insertions(+), 133 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 71434a922695..c2a79e487ee9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -15,6 +15,7 @@
#include "intel_dmc.h"
#include "intel_dpll_mgr.h"
#include "intel_gmbus.h"
+#include "intel_pm_types.h"
struct drm_i915_private;
struct i915_audio_component;
@@ -100,6 +101,42 @@ struct intel_dpll {
} ref_clks;
};
+struct intel_wm {
+ /*
+* Raw watermark latency values:
+* in 0.1us units for WM0,
+* in 0.5us units for WM1+.
+*/
+ /* primary */
+ u16 pri_latency[5];
+ /* sprite */
+ u16 spr_latency[5];
+ /* cursor */
+ u16 cur_latency[5];
+ /*
+* Raw watermark memory latency values
+* for SKL for all 8 levels
+* in 1us units.
+*/
+ u16 skl_latency[8];
+
+ /* current hardware state */
+ union {
+ struct ilk_wm_values hw;
+ struct vlv_wm_values vlv;
+ struct g4x_wm_values g4x;
+ };
+
+ u8 max_level;
+
+ /*
+* Should be held around atomic WM register writing; also
+* protects * intel_crtc->wm.active and
+* crtc_state->wm.need_postvbl_update.
+*/
+ struct mutex wm_mutex;
+};
+
struct intel_display {
/* Display functions */
struct {
@@ -167,6 +204,7 @@ struct intel_display {
struct intel_audio audio;
struct intel_dmc dmc;
struct intel_dpll dpll;
+ struct intel_wm wm;
};
#endif /* __INTEL_DISPLAY_CORE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index e568590faa82..395facf6c1aa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1428,9 +1428,9 @@ static int pri_wm_latency_show(struct seq_file *m, void
*data)
const u16 *latencies;
if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->wm.skl_latency;
+ latencies = dev_priv->display.wm.skl_latency;
else
- latencies = dev_priv->wm.pri_latency;
+ latencies = dev_priv->display.wm.pri_latency;
wm_latency_show(m, latencies);
@@ -1443,9 +1443,9 @@ static int spr_wm_latency_show(struct seq_file *m, void
*data)
const u16 *latencies;
if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->wm.skl_latency;
+ latencies = dev_priv->display.wm.skl_latency;
else
- latencies = dev_priv->wm.spr_latency;
+ latencies = dev_priv->display.wm.spr_latency;
wm_latency_show(m, latencies);
@@ -1458,9 +1458,9 @@ static int cur_wm_latency_show(struct seq_file *m, void
*data)
const u16 *latencies;
if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->wm.skl_latency;
+ latencies = dev_priv->display.wm.skl_latency;
else
- latencies = dev_priv->wm.cur_latency;
+ latencies = dev_priv->display.wm.cur_latency;
wm_latency_show(m, latencies);
@@ -1551,9 +1551,9 @@ static ssize_t pri_wm_latency_write(struct file *file,
const char __user *ubuf,
u16 *latencies;
if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->wm.skl_latency;
+ latencies = dev_priv->display.wm.skl_latency;
else
- latencies = dev_priv->wm.pri_latency;
+ latencies = dev_priv->display.wm.pri_latency;
return wm_latency_write(file, ubuf, len, offp, latencies);
}
@@ -1566,9 +1566,9 @@ static ssize_t spr_wm_latency_write(struct file *file,
const char __user *ubuf,
u16 *latencies;
if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->wm.skl_latency;
+ latencies = dev_priv->display.wm.skl_latency;
else
- latencies = dev_priv->wm.spr_latency;
+ latencies = dev_priv->display.wm.spr_latency;
return wm_latency_write(file, ubuf, len, offp, latencies);
}
@@ -1581,9 +1581,9 @@ static ssize_t cur_wm_latency_write(struct file *file,
const char __user *ubuf,
[Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to display.funcs
Move display related members under drm_i915_private display sub-struct.
Rename struct i915_clock_gating_funcs to intel_clock_gating_funcs while
at it.
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_display_core.h | 4 ++
drivers/gpu/drm/i915/i915_drv.h | 4 --
drivers/gpu/drm/i915/intel_pm.c | 58 +--
3 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index ff76bd4079e4..98c6ccdc9100 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -10,6 +10,7 @@
struct intel_atomic_state;
struct intel_cdclk_funcs;
+struct intel_clock_gating_funcs;
struct intel_crtc;
struct intel_crtc_state;
struct intel_dpll_funcs;
@@ -44,6 +45,9 @@ struct intel_display {
/* irq display functions */
const struct intel_hotplug_funcs *hotplug;
+
+ /* pm private clock gating functions */
+ const struct intel_clock_gating_funcs *clock_gating;
} funcs;
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 513fae9e7a81..216298d2d677 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -78,7 +78,6 @@
#include "intel_wopcm.h"
struct dpll;
-struct drm_i915_clock_gating_funcs;
struct drm_i915_gem_object;
struct drm_i915_private;
struct intel_atomic_state;
@@ -502,9 +501,6 @@ struct drm_i915_private {
/* unbound hipri wq for page flips/plane updates */
struct workqueue_struct *flip_wq;
- /* pm private clock gating functions */
- const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
-
/* pm display functions */
const struct drm_i915_wm_disp_funcs *wm_disp;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ef7553b494ea..043094573c20 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -59,7 +59,7 @@
static void skl_sagv_disable(struct drm_i915_private *dev_priv);
-struct drm_i915_clock_gating_funcs {
+struct intel_clock_gating_funcs {
void (*init_clock_gating)(struct drm_i915_private *i915);
};
@@ -8053,7 +8053,7 @@ static void i830_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating(struct drm_i915_private *dev_priv)
{
- dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
+ dev_priv->display.funcs.clock_gating->init_clock_gating(dev_priv);
}
void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -8069,7 +8069,7 @@ static void nop_init_clock_gating(struct drm_i915_private
*dev_priv)
}
#define CG_FUNCS(platform) \
-static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs
= { \
+static const struct intel_clock_gating_funcs platform##_clock_gating_funcs = {
\
.init_clock_gating = platform##_init_clock_gating, \
}
@@ -8113,58 +8113,58 @@ CG_FUNCS(nop);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_PONTEVECCHIO(dev_priv))
- dev_priv->clock_gating_funcs = &pvc_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &pvc_clock_gating_funcs;
else if (IS_DG2(dev_priv))
- dev_priv->clock_gating_funcs = &dg2_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &dg2_clock_gating_funcs;
else if (IS_XEHPSDV(dev_priv))
- dev_priv->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating =
&xehpsdv_clock_gating_funcs;
else if (IS_ALDERLAKE_P(dev_priv))
- dev_priv->clock_gating_funcs = &adlp_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &adlp_clock_gating_funcs;
else if (IS_DG1(dev_priv))
- dev_priv->clock_gating_funcs = &dg1_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &dg1_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 12)
- dev_priv->clock_gating_funcs = &gen12lp_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating =
&gen12lp_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 11)
- dev_priv->clock_gating_funcs = &icl_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &icl_clock_gating_funcs;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
- dev_priv->clock_gating_funcs = &cfl_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &cfl_clock_gating_funcs;
else if (IS_SKYLAKE(dev_priv))
- dev_priv->clock_gating_funcs = &skl_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &skl_clock_gati
[Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus members under display.gmbus
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c| 6 +--
.../gpu/drm/i915/display/intel_display_core.h | 23 ++
drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
drivers/gpu/drm/i915/display/intel_gmbus.c| 46 +--
drivers/gpu/drm/i915/i915_drv.h | 16 ---
drivers/gpu/drm/i915/i915_irq.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 14 +++---
7 files changed, 59 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6095f5800a2e..ea40c75c2986 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2098,12 +2098,12 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
* functions use cdclk. Not all platforms/ports do,
* but we'll lock them all for simplicity.
*/
- mutex_lock(&dev_priv->gmbus_mutex);
+ mutex_lock(&dev_priv->display.gmbus.mutex);
for_each_intel_dp(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
-&dev_priv->gmbus_mutex);
+&dev_priv->display.gmbus.mutex);
}
intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
@@ -2113,7 +2113,7 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
mutex_unlock(&intel_dp->aux.hw_mutex);
}
- mutex_unlock(&dev_priv->gmbus_mutex);
+ mutex_unlock(&dev_priv->display.gmbus.mutex);
for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 306584c038c9..fe19d4f9a9ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -6,7 +6,11 @@
#ifndef __INTEL_DISPLAY_CORE_H__
#define __INTEL_DISPLAY_CORE_H__
+#include
#include
+#include
+
+#include "intel_gmbus.h"
struct drm_i915_private;
struct intel_atomic_state;
@@ -78,6 +82,25 @@ struct intel_display {
/* Display internal color functions */
const struct intel_color_funcs *color;
} funcs;
+
+ /* Grouping using anonymous structs. Keep sorted. */
+ struct {
+ /*
+* Base address of where the gmbus and gpio blocks are located
+* (either on PCH or on SoC for platforms without PCH).
+*/
+ u32 mmio_base;
+
+ /*
+* gmbus.mutex protects against concurrent usage of the single
+* hw gmbus controller on different i2c buses.
+*/
+ struct mutex mutex;
+
+ struct intel_gmbus *bus[GMBUS_NUM_PINS];
+
+ wait_queue_head_t wait_queue;
+ } gmbus;
};
#endif /* __INTEL_DISPLAY_CORE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 2bc119374555..227fbee88b89 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -42,7 +42,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
bool done;
#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) &
DP_AUX_CH_CTL_SEND_BUSY) == 0)
- done = wait_event_timeout(i915->gmbus_wait_queue, C,
+ done = wait_event_timeout(i915->display.gmbus.wait_queue, C,
msecs_to_jiffies_timeout(timeout_ms));
/* just trace the final value */
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index a6ba7fb72339..c3992b1ca842 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -369,7 +369,7 @@ static int gmbus_wait(struct drm_i915_private *dev_priv,
u32 status, u32 irq_en)
if (!has_gmbus_irq(dev_priv))
irq_en = 0;
- add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
+ add_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait);
intel_de_write_fw(dev_priv, GMBUS4, irq_en);
status |= GMBUS_SATOER;
@@ -380,7 +380,7 @@ static int gmbus_wait(struct drm_i915_private *dev_priv,
u32 status, u32 irq_en)
50);
intel_de_write_fw(dev_priv, GMBUS4, 0);
- remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
+ remove_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait);
if (gmbus2 & GMBUS_SATOER)
return -ENXIO;
@@ -400,7 +400,7 @@ gmbus_wait_idle(struct drm_i915_private
[Intel-gfx] [PATCH 16/39] drm/i915: move and group hdcp under display.hdcp
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_display_core.h | 9 ++
drivers/gpu/drm/i915/display/intel_hdcp.c | 134 +-
drivers/gpu/drm/i915/i915_driver.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h | 6 -
4 files changed, 77 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index c2a79e487ee9..8ac63352b27b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -19,6 +19,7 @@
struct drm_i915_private;
struct i915_audio_component;
+struct i915_hdcp_comp_master;
struct intel_atomic_state;
struct intel_audio_funcs;
struct intel_cdclk_funcs;
@@ -193,6 +194,14 @@ struct intel_display {
wait_queue_head_t wait_queue;
} gmbus;
+ struct {
+ struct i915_hdcp_comp_master *master;
+ bool comp_added;
+
+ /* Mutex to protect the above hdcp component related values. */
+ struct mutex comp_mutex;
+ } hdcp;
+
struct {
u32 mmio_base;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index c5e9e86bb4cb..6f04dd69087e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -188,12 +188,12 @@ bool intel_hdcp2_capable(struct intel_connector
*connector)
return false;
/* MEI interface is solid */
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- if (!dev_priv->hdcp_comp_added || !dev_priv->hdcp_master) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ if (!dev_priv->display.hdcp.comp_added ||
!dev_priv->display.hdcp.master) {
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return false;
}
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
/* Sink's capability for HDCP2.2 */
hdcp->shim->hdcp_2_2_capable(dig_port, &capable);
@@ -1124,11 +1124,11 @@ hdcp2_prepare_ake_init(struct intel_connector
*connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1136,7 +1136,7 @@ hdcp2_prepare_ake_init(struct intel_connector *connector,
if (ret)
drm_dbg_kms(&dev_priv->drm, "Prepare_ake_init failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1154,11 +1154,11 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1168,7 +1168,7 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify rx_cert failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1182,18 +1182,18 @@ static int hdcp2_verify_hprime(struct intel_connector
*connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
ret = comp->ops->verify_hprime(comp->mei_dev, data, rx_hprime);
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify hprime failed. %d\n", ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1208,11 +1208,11 @@ hdcp2_store_pairing_info(struct intel_connector
*connector,
[Intel-gfx] [PATCH 11/39] drm/i915: move dmc to display.dmc
Move display related members under drm_i915_private display sub-struct.
FIXME: dmc really needs to be abstracted and hidden inside intel_dmc.c
with display.dmc turned into a pointer
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_display_core.h | 4 ++
.../drm/i915/display/intel_display_power.c| 18 +++
.../i915/display/intel_display_power_well.c | 18 +++
drivers/gpu/drm/i915/display/intel_dmc.c | 52 +--
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 --
6 files changed, 49 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 030ced4068bb..ca22706e11e6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -10,6 +10,7 @@
#include
#include
+#include "intel_dmc.h"
#include "intel_gmbus.h"
struct drm_i915_private;
@@ -108,6 +109,9 @@ struct intel_display {
/* protects panel power sequencer state */
struct mutex mutex;
} pps;
+
+ /* Grouping using named structs. Keep sorted. */
+ struct intel_dmc dmc;
};
#endif /* __INTEL_DISPLAY_CORE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3f84af6beff3..07d083e95e37 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -268,7 +268,7 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv,
if (target_dc_state != states[i])
continue;
- if (dev_priv->dmc.allowed_dc_mask & target_dc_state)
+ if (dev_priv->display.dmc.allowed_dc_mask & target_dc_state)
break;
target_dc_state = states[i + 1];
@@ -301,7 +301,7 @@ void intel_display_power_set_target_dc_state(struct
drm_i915_private *dev_priv,
state = sanitize_target_dc_state(dev_priv, state);
- if (state == dev_priv->dmc.target_dc_state)
+ if (state == dev_priv->display.dmc.target_dc_state)
goto unlock;
dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well);
@@ -312,7 +312,7 @@ void intel_display_power_set_target_dc_state(struct
drm_i915_private *dev_priv,
if (!dc_off_enabled)
intel_power_well_enable(dev_priv, power_well);
- dev_priv->dmc.target_dc_state = state;
+ dev_priv->display.dmc.target_dc_state = state;
if (!dc_off_enabled)
intel_power_well_disable(dev_priv, power_well);
@@ -981,10 +981,10 @@ int intel_power_domains_init(struct drm_i915_private
*dev_priv)
dev_priv->params.disable_power_well =
sanitize_disable_power_well_option(dev_priv,
dev_priv->params.disable_power_well);
- dev_priv->dmc.allowed_dc_mask =
+ dev_priv->display.dmc.allowed_dc_mask =
get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
- dev_priv->dmc.target_dc_state =
+ dev_priv->display.dmc.target_dc_state =
sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
mutex_init(&power_domains->lock);
@@ -2050,7 +2050,7 @@ void intel_power_domains_suspend(struct drm_i915_private
*i915,
* resources as required and also enable deeper system power states
* that would be blocked if the firmware was inactive.
*/
- if (!(i915->dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
+ if (!(i915->display.dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
suspend_mode == I915_DRM_SUSPEND_IDLE &&
intel_dmc_has_payload(i915)) {
intel_display_power_flush_work(i915);
@@ -2243,10 +2243,10 @@ void intel_display_power_resume(struct drm_i915_private
*i915)
bxt_disable_dc9(i915);
icl_display_core_init(i915, true);
if (intel_dmc_has_payload(i915)) {
- if (i915->dmc.allowed_dc_mask &
+ if (i915->display.dmc.allowed_dc_mask &
DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(i915);
- else if (i915->dmc.allowed_dc_mask &
+ else if (i915->display.dmc.allowed_dc_mask &
DC_STATE_EN_UPTO_DC5)
gen9_enable_dc5(i915);
}
@@ -2254,7 +2254,7 @@ void intel_display_power_resume(struct drm_i915_private
*i915)
bxt_disable_dc9(i915);
bxt_display_core_init(i915, true);
if (intel_dmc_has_payload(i915) &&
- (i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
+ (i915->display.dmc.allowed_dc_mask & DC_STATE_EN_UPT
[Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members under display.pps
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_display_core.h | 7 +++
drivers/gpu/drm/i915/display/intel_pps.c | 48 +--
drivers/gpu/drm/i915/i915_driver.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h | 5 --
drivers/gpu/drm/i915/i915_reg.h | 2 +-
5 files changed, 33 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index fe19d4f9a9ab..030ced4068bb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -101,6 +101,13 @@ struct intel_display {
wait_queue_head_t wait_queue;
} gmbus;
+
+ struct {
+ u32 mmio_base;
+
+ /* protects panel power sequencer state */
+ struct mutex mutex;
+ } pps;
};
#endif /* __INTEL_DISPLAY_CORE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 1b21a341962f..9a66e03aa2d6 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -28,7 +28,7 @@ intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
* See intel_pps_reset_all() why we need a power domain reference here.
*/
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
- mutex_lock(&dev_priv->pps_mutex);
+ mutex_lock(&dev_priv->display.pps.mutex);
return wakeref;
}
@@ -38,7 +38,7 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- mutex_unlock(&dev_priv->pps_mutex);
+ mutex_unlock(&dev_priv->display.pps.mutex);
intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
return 0;
@@ -163,7 +163,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum pipe pipe;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
/* We should never land here with regular DP ports */
drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
@@ -212,7 +212,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
struct intel_connector *connector = intel_dp->attached_connector;
int backlight_controller = connector->panel.vbt.backlight.controller;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
/* We should never land here with regular DP ports */
drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
@@ -282,7 +282,7 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum port port = dig_port->base.port;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
/* try to find a pipe with this port selected */
/* first pick one where the panel is on */
@@ -407,7 +407,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
intel_dp->pps.pps_pipe == INVALID_PIPE)
@@ -420,7 +420,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
intel_dp->pps.pps_pipe == INVALID_PIPE)
@@ -463,7 +463,7 @@ static void wait_panel_status(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
i915_reg_t pp_stat_reg, pp_ctrl_reg;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
intel_pps_verify_state(intel_dp);
@@ -556,7 +556,7 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 control;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
@@ -580,7 +580,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
i915_reg_t pp_stat_reg, pp_ctrl_reg;
bool need_to_disable = !intel_dp->pps.want_panel_vdd;
- lockdep_asse
[Intel-gfx] [PATCH 07/39] drm/i915: move fdi_funcs to display.funcs
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_core.h | 4
drivers/gpu/drm/i915/display/intel_fdi.c | 8
drivers/gpu/drm/i915/i915_drv.h | 4
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index a6843ebcca5a..7dbffaebd9c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -15,6 +15,7 @@ struct intel_clock_gating_funcs;
struct intel_crtc;
struct intel_crtc_state;
struct intel_dpll_funcs;
+struct intel_fdi_funcs;
struct intel_hotplug_funcs;
struct intel_initial_plane_config;
@@ -69,6 +70,9 @@ struct intel_display {
/* pm display functions */
const struct intel_wm_funcs *wm;
+
+ /* fdi display functions */
+ const struct intel_fdi_funcs *fdi;
} funcs;
};
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index 67d2484afbaa..03ad5f5c8417 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -113,7 +113,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- dev_priv->fdi_funcs->fdi_link_train(crtc, crtc_state);
+ dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state);
}
/* units of 100MHz */
@@ -1066,11 +1066,11 @@ void
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
{
if (IS_IRONLAKE(dev_priv)) {
- dev_priv->fdi_funcs = &ilk_funcs;
+ dev_priv->display.funcs.fdi = &ilk_funcs;
} else if (IS_SANDYBRIDGE(dev_priv)) {
- dev_priv->fdi_funcs = &gen6_funcs;
+ dev_priv->display.funcs.fdi = &gen6_funcs;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
- dev_priv->fdi_funcs = &ivb_funcs;
+ dev_priv->display.funcs.fdi = &ivb_funcs;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 69a8cce48fc4..8a9f2bf24186 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -89,7 +89,6 @@ struct intel_connector;
struct intel_dp;
struct intel_encoder;
struct intel_fbdev;
-struct intel_fdi_funcs;
struct intel_gmbus;
struct intel_limit;
struct intel_overlay;
@@ -482,9 +481,6 @@ struct drm_i915_private {
/* unbound hipri wq for page flips/plane updates */
struct workqueue_struct *flip_wq;
- /* fdi display functions */
- const struct intel_fdi_funcs *fdi_funcs;
-
/* Display internal color functions */
const struct intel_color_funcs *color_funcs;
--
2.34.1
[Intel-gfx] [PATCH 02/39] drm/i915: move cdclk_funcs to display.funcs
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c| 70 +--
.../gpu/drm/i915/display/intel_display_core.h | 4 ++
drivers/gpu/drm/i915/i915_drv.h | 4 --
3 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 86a22c3766e5..6095f5800a2e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -79,26 +79,26 @@ struct intel_cdclk_funcs {
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
- dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config);
+ dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config);
}
static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe);
+ dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe);
}
static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state
*cdclk_config)
{
- return dev_priv->cdclk_funcs->modeset_calc_cdclk(cdclk_config);
+ return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config);
}
static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
int cdclk)
{
- return dev_priv->cdclk_funcs->calc_voltage_level(cdclk);
+ return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk);
}
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -2080,7 +2080,7 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
+ if (drm_WARN_ON_ONCE(&dev_priv->drm,
!dev_priv->display.funcs.cdclk->set_cdclk))
return;
intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
@@ -3187,78 +3187,78 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs
= {
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
if (IS_DG2(dev_priv)) {
- dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
- dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
else
dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
- dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->cdclk.table = rkl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 12) {
- dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_JSL_EHL(dev_priv)) {
- dev_priv->cdclk_funcs = &ehl_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
- dev_priv->cdclk_funcs = &icl_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
- dev_priv->cdclk_funcs = &bxt_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
if (IS_GEMINILAKE(dev_priv))
dev_priv->cdclk.table = glk_cdclk_table;
else
dev_priv->cdclk.table = bxt_cdclk_table;
} else if (DISPLAY_VER(dev_priv) == 9) {
- dev_priv->cdclk_funcs = &skl_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
} else if (IS_BROADWELL(dev_priv)) {
- dev_priv->cdclk_funcs = &bdw_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs;
} else if (IS_HASWELL(dev_priv)) {
- dev_priv->cdclk_funcs = &hsw_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &hs
[Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to drm_i915_private
In another long-overdue cleanup, add a display sub-struct to
drm_i915_private, and start moving display related members there. Start
with display funcs that need a rename anyway to not collide with the new
display member.
Add a new header under display/ for defining struct intel_display.
Rename struct drm_i915_display_funcs to intel_display_funcs while at it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 28 +++---
.../gpu/drm/i915/display/intel_display_core.h | 38 +++
.../drm/i915/display/intel_modeset_setup.c| 2 +-
.../drm/i915/display/intel_plane_initial.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h | 21 ++
5 files changed, 57 insertions(+), 34 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_core.h
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f143adefdf38..24ab1501beea 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4144,7 +4144,7 @@ bool intel_crtc_get_pipe_config(struct intel_crtc_state
*crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- if (!i915->display->get_pipe_config(crtc, crtc_state))
+ if (!i915->display.funcs.crtc->get_pipe_config(crtc, crtc_state))
return false;
crtc_state->hw.active = true;
@@ -7119,7 +7119,7 @@ static void intel_enable_crtc(struct intel_atomic_state
*state,
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display->crtc_enable(state, crtc);
+ dev_priv->display.funcs.crtc->crtc_enable(state, crtc);
if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
return;
@@ -7198,7 +7198,7 @@ static void intel_old_crtc_state_disables(struct
intel_atomic_state *state,
*/
intel_crtc_disable_pipe_crc(crtc);
- dev_priv->display->crtc_disable(state, crtc);
+ dev_priv->display.funcs.crtc->crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
intel_disable_shared_dpll(old_crtc_state);
@@ -7586,7 +7586,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
}
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
- dev_priv->display->commit_modeset_enables(state);
+ dev_priv->display.funcs.crtc->commit_modeset_enables(state);
intel_encoders_update_complete(state);
@@ -8317,7 +8317,7 @@ static const struct drm_mode_config_funcs
intel_mode_funcs = {
.atomic_state_free = intel_atomic_state_free,
};
-static const struct drm_i915_display_funcs skl_display_funcs = {
+static const struct intel_display_funcs skl_display_funcs = {
.get_pipe_config = hsw_get_pipe_config,
.crtc_enable = hsw_crtc_enable,
.crtc_disable = hsw_crtc_disable,
@@ -8325,7 +8325,7 @@ static const struct drm_i915_display_funcs
skl_display_funcs = {
.get_initial_plane_config = skl_get_initial_plane_config,
};
-static const struct drm_i915_display_funcs ddi_display_funcs = {
+static const struct intel_display_funcs ddi_display_funcs = {
.get_pipe_config = hsw_get_pipe_config,
.crtc_enable = hsw_crtc_enable,
.crtc_disable = hsw_crtc_disable,
@@ -8333,7 +8333,7 @@ static const struct drm_i915_display_funcs
ddi_display_funcs = {
.get_initial_plane_config = i9xx_get_initial_plane_config,
};
-static const struct drm_i915_display_funcs pch_split_display_funcs = {
+static const struct intel_display_funcs pch_split_display_funcs = {
.get_pipe_config = ilk_get_pipe_config,
.crtc_enable = ilk_crtc_enable,
.crtc_disable = ilk_crtc_disable,
@@ -8341,7 +8341,7 @@ static const struct drm_i915_display_funcs
pch_split_display_funcs = {
.get_initial_plane_config = i9xx_get_initial_plane_config,
};
-static const struct drm_i915_display_funcs vlv_display_funcs = {
+static const struct intel_display_funcs vlv_display_funcs = {
.get_pipe_config = i9xx_get_pipe_config,
.crtc_enable = valleyview_crtc_enable,
.crtc_disable = i9xx_crtc_disable,
@@ -8349,7 +8349,7 @@ static const struct drm_i915_display_funcs
vlv_display_funcs = {
.get_initial_plane_config = i9xx_get_initial_plane_config,
};
-static const struct drm_i915_display_funcs i9xx_display_funcs = {
+static const struct intel_display_funcs i9xx_display_funcs = {
.get_pipe_config = i9xx_get_pipe_config,
.crtc_enable = i9xx_crtc_enable,
.crtc_disable = i9xx_crtc_disable,
@@ -8372,16 +8372,16 @@ void intel_init_display_hooks(struct drm_i915_private
*dev_priv)
intel_dpll_init_clock_hook(dev_priv);
if (DISPLAY_VER(dev_priv) >= 9) {
- dev_priv->display = &skl_display_funcs;
+ dev_priv
[Intel-gfx] [PATCH 08/39] drm/i915: move color_funcs to display.funcs
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_color.c| 34 +--
.../gpu/drm/i915/display/intel_display_core.h | 4 +++
drivers/gpu/drm/i915/i915_drv.h | 4 ---
3 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 9583d17e858d..ed98c732b24e 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1167,22 +1167,22 @@ void intel_color_load_luts(const struct
intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->color_funcs->load_luts(crtc_state);
+ dev_priv->display.funcs.color->load_luts(crtc_state);
}
void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->color_funcs->color_commit_noarm)
- dev_priv->color_funcs->color_commit_noarm(crtc_state);
+ if (dev_priv->display.funcs.color->color_commit_noarm)
+ dev_priv->display.funcs.color->color_commit_noarm(crtc_state);
}
void intel_color_commit_arm(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->color_funcs->color_commit_arm(crtc_state);
+ dev_priv->display.funcs.color->color_commit_arm(crtc_state);
}
static bool intel_can_preload_luts(const struct intel_crtc_state
*new_crtc_state)
@@ -1238,15 +1238,15 @@ int intel_color_check(struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- return dev_priv->color_funcs->color_check(crtc_state);
+ return dev_priv->display.funcs.color->color_check(crtc_state);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->color_funcs->read_luts)
- dev_priv->color_funcs->read_luts(crtc_state);
+ if (dev_priv->display.funcs.color->read_luts)
+ dev_priv->display.funcs.color->read_luts(crtc_state);
}
static bool need_plane_update(struct intel_plane *plane,
@@ -2225,28 +2225,28 @@ void intel_color_init(struct intel_crtc *crtc)
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->color_funcs = &chv_color_funcs;
+ dev_priv->display.funcs.color = &chv_color_funcs;
} else if (DISPLAY_VER(dev_priv) >= 4) {
- dev_priv->color_funcs = &i965_color_funcs;
+ dev_priv->display.funcs.color = &i965_color_funcs;
} else {
- dev_priv->color_funcs = &i9xx_color_funcs;
+ dev_priv->display.funcs.color = &i9xx_color_funcs;
}
} else {
if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->color_funcs = &icl_color_funcs;
+ dev_priv->display.funcs.color = &icl_color_funcs;
else if (DISPLAY_VER(dev_priv) == 10)
- dev_priv->color_funcs = &glk_color_funcs;
+ dev_priv->display.funcs.color = &glk_color_funcs;
else if (DISPLAY_VER(dev_priv) == 9)
- dev_priv->color_funcs = &skl_color_funcs;
+ dev_priv->display.funcs.color = &skl_color_funcs;
else if (DISPLAY_VER(dev_priv) == 8)
- dev_priv->color_funcs = &bdw_color_funcs;
+ dev_priv->display.funcs.color = &bdw_color_funcs;
else if (DISPLAY_VER(dev_priv) == 7) {
if (IS_HASWELL(dev_priv))
- dev_priv->color_funcs = &hsw_color_funcs;
+ dev_priv->display.funcs.color =
&hsw_color_funcs;
else
- dev_priv->color_funcs = &ivb_color_funcs;
+ dev_priv->display.funcs.color =
&ivb_color_funcs;
} else
- dev_priv->color_funcs = &ilk_color_funcs;
+ dev_priv->display.funcs.color = &ilk_color_funcs;
}
drm_crtc_enable_color_mgmt(&crtc->base,
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 7dbffaebd9c0..306584c038c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -12,6 +12,7 @@ struct drm_i915_private;
struct intel_atomic_state;
struct intel_cdclk_funcs;
struct intel_clock_gating_funcs;
+struct intel_
[Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under display.audio and display.funcs
Move display related members under drm_i915_private display sub-struct.
Split audio funcs to display.funcs to follow the same pattern as all the
other display functions.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_audio.c| 96 +--
.../gpu/drm/i915/display/intel_display_core.h | 26 +
.../gpu/drm/i915/display/intel_lpe_audio.c| 42
drivers/gpu/drm/i915/i915_driver.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h | 26 -
5 files changed, 96 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 6c9ee905f132..a74fc79b7910 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -393,7 +393,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_audio_component *acomp = dev_priv->audio.component;
+ struct i915_audio_component *acomp = dev_priv->display.audio.component;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
const struct dp_aud_n_m *nm;
@@ -441,7 +441,7 @@ hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_audio_component *acomp = dev_priv->audio.component;
+ struct i915_audio_component *acomp = dev_priv->display.audio.component;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
int n, rate;
@@ -496,7 +496,7 @@ static void hsw_audio_codec_disable(struct intel_encoder
*encoder,
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
u32 tmp;
- mutex_lock(&dev_priv->audio.mutex);
+ mutex_lock(&dev_priv->display.audio.mutex);
/* Disable timestamps */
tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
@@ -514,7 +514,7 @@ static void hsw_audio_codec_disable(struct intel_encoder
*encoder,
tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
- mutex_unlock(&dev_priv->audio.mutex);
+ mutex_unlock(&dev_priv->display.audio.mutex);
}
static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
@@ -639,7 +639,7 @@ static void hsw_audio_codec_enable(struct intel_encoder
*encoder,
u32 tmp;
int len, i;
- mutex_lock(&dev_priv->audio.mutex);
+ mutex_lock(&dev_priv->display.audio.mutex);
/* Enable Audio WA for 4k DSC usecases */
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
@@ -677,7 +677,7 @@ static void hsw_audio_codec_enable(struct intel_encoder
*encoder,
/* Enable timestamps */
hsw_audio_config_update(encoder, crtc_state);
- mutex_unlock(&dev_priv->audio.mutex);
+ mutex_unlock(&dev_priv->display.audio.mutex);
}
static void ilk_audio_codec_disable(struct intel_encoder *encoder,
@@ -814,7 +814,7 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_audio_component *acomp = dev_priv->audio.component;
+ struct i915_audio_component *acomp = dev_priv->display.audio.component;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_connector *connector = conn_state->connector;
const struct drm_display_mode *adjusted_mode =
@@ -838,17 +838,17 @@ void intel_audio_codec_enable(struct intel_encoder
*encoder,
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
- if (dev_priv->audio.funcs)
- dev_priv->audio.funcs->audio_codec_enable(encoder,
- crtc_state,
- conn_state);
+ if (dev_priv->display.funcs.audio)
+ dev_priv->display.funcs.audio->audio_codec_enable(encoder,
+ crtc_state,
+ conn_state);
- mutex_lock(&dev_priv->audio.mutex);
+ mutex_lock(&dev_priv->display.audio.mutex);
encoder->audio_connector = connector;
/* referred in audio callbacks */
- dev_priv->audio.encoder_map[pipe] = encoder;
- mutex_unlock(&dev_priv->audio.mutex);
+ dev_priv->display.audio.encoder_map[pipe] = encoder;
+ mutex_unlock(&dev_priv->display.audio.mutex);
if (acomp && acomp->base.audio_ops &&
[Intel-gfx] [PATCH 04/39] drm/i915: move hotplug_funcs to display.funcs
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_display_core.h | 4
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/i915_irq.c | 20 +--
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index f09bbb7b5cc9..ff76bd4079e4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -13,6 +13,7 @@ struct intel_cdclk_funcs;
struct intel_crtc;
struct intel_crtc_state;
struct intel_dpll_funcs;
+struct intel_hotplug_funcs;
struct intel_initial_plane_config;
struct intel_display_funcs {
@@ -40,6 +41,9 @@ struct intel_display {
/* Display pll funcs */
const struct intel_dpll_funcs *dpll;
+
+ /* irq display functions */
+ const struct intel_hotplug_funcs *hotplug;
} funcs;
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 375f526215a2..513fae9e7a81 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -94,7 +94,6 @@ struct intel_encoder;
struct intel_fbdev;
struct intel_fdi_funcs;
struct intel_gmbus;
-struct intel_hotplug_funcs;
struct intel_limit;
struct intel_overlay;
struct intel_overlay_error_state;
@@ -509,9 +508,6 @@ struct drm_i915_private {
/* pm display functions */
const struct drm_i915_wm_disp_funcs *wm_disp;
- /* irq display functions */
- const struct intel_hotplug_funcs *hotplug_funcs;
-
/* fdi display functions */
const struct intel_fdi_funcs *fdi_funcs;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0389f532d926..c1b8f949c53d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4370,8 +4370,8 @@ HPD_FUNCS(ilk);
void intel_hpd_irq_setup(struct drm_i915_private *i915)
{
- if (i915->display_irqs_enabled && i915->hotplug_funcs)
- i915->hotplug_funcs->hpd_irq_setup(i915);
+ if (i915->display_irqs_enabled && i915->display.funcs.hotplug)
+ i915->display.funcs.hotplug->hpd_irq_setup(i915);
}
/**
@@ -4424,22 +4424,22 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
- dev_priv->hotplug_funcs = &i915_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &i915_hpd_funcs;
} else {
if (HAS_PCH_DG2(dev_priv))
- dev_priv->hotplug_funcs = &icp_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &icp_hpd_funcs;
else if (HAS_PCH_DG1(dev_priv))
- dev_priv->hotplug_funcs = &dg1_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &dg1_hpd_funcs;
else if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->hotplug_funcs = &gen11_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &gen11_hpd_funcs;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->hotplug_funcs = &bxt_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &bxt_hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- dev_priv->hotplug_funcs = &icp_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &icp_hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->hotplug_funcs = &spt_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &spt_hpd_funcs;
else
- dev_priv->hotplug_funcs = &ilk_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &ilk_hpd_funcs;
}
}
--
2.34.1
[Intel-gfx] [PATCH 03/39] drm/i915: move dpll_funcs to display.funcs
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_display_core.h | 4
drivers/gpu/drm/i915/display/intel_dpll.c | 24 +--
drivers/gpu/drm/i915/i915_drv.h | 4
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 74e4ae0609b9..f09bbb7b5cc9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -12,6 +12,7 @@ struct intel_atomic_state;
struct intel_cdclk_funcs;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_dpll_funcs;
struct intel_initial_plane_config;
struct intel_display_funcs {
@@ -36,6 +37,9 @@ struct intel_display {
/* Display CDCLK functions */
const struct intel_cdclk_funcs *cdclk;
+
+ /* Display pll funcs */
+ const struct intel_dpll_funcs *dpll;
} funcs;
};
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 5262f16b45ac..87899702a522 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1420,7 +1420,7 @@ int intel_dpll_crtc_compute_clock(struct
intel_atomic_state *state,
if (!crtc_state->hw.enable)
return 0;
- ret = i915->dpll_funcs->crtc_compute_clock(state, crtc);
+ ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc);
if (ret) {
drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL
settings\n",
crtc->base.base.id, crtc->base.name);
@@ -1446,10 +1446,10 @@ int intel_dpll_crtc_get_shared_dpll(struct
intel_atomic_state *state,
if (!crtc_state->hw.enable)
return 0;
- if (!i915->dpll_funcs->crtc_get_shared_dpll)
+ if (!i915->display.funcs.dpll->crtc_get_shared_dpll)
return 0;
- ret = i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
+ ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc);
if (ret) {
drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared
DPLL\n",
crtc->base.base.id, crtc->base.name);
@@ -1463,23 +1463,23 @@ void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
if (IS_DG2(dev_priv))
- dev_priv->dpll_funcs = &dg2_dpll_funcs;
+ dev_priv->display.funcs.dpll = &dg2_dpll_funcs;
else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
- dev_priv->dpll_funcs = &hsw_dpll_funcs;
+ dev_priv->display.funcs.dpll = &hsw_dpll_funcs;
else if (HAS_PCH_SPLIT(dev_priv))
- dev_priv->dpll_funcs = &ilk_dpll_funcs;
+ dev_priv->display.funcs.dpll = &ilk_dpll_funcs;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->dpll_funcs = &chv_dpll_funcs;
+ dev_priv->display.funcs.dpll = &chv_dpll_funcs;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->dpll_funcs = &vlv_dpll_funcs;
+ dev_priv->display.funcs.dpll = &vlv_dpll_funcs;
else if (IS_G4X(dev_priv))
- dev_priv->dpll_funcs = &g4x_dpll_funcs;
+ dev_priv->display.funcs.dpll = &g4x_dpll_funcs;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->dpll_funcs = &pnv_dpll_funcs;
+ dev_priv->display.funcs.dpll = &pnv_dpll_funcs;
else if (DISPLAY_VER(dev_priv) != 2)
- dev_priv->dpll_funcs = &i9xx_dpll_funcs;
+ dev_priv->display.funcs.dpll = &i9xx_dpll_funcs;
else
- dev_priv->dpll_funcs = &i8xx_dpll_funcs;
+ dev_priv->display.funcs.dpll = &i8xx_dpll_funcs;
}
static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 104095ea3738..375f526215a2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -90,7 +90,6 @@ struct intel_color_funcs;
struct intel_connector;
struct intel_crtc;
struct intel_dp;
-struct intel_dpll_funcs;
struct intel_encoder;
struct intel_fbdev;
struct intel_fdi_funcs;
@@ -516,9 +515,6 @@ struct drm_i915_private {
/* fdi display functions */
const struct intel_fdi_funcs *fdi_funcs;
- /* display pll funcs */
- const struct intel_dpll_funcs *dpll_funcs;
-
/* Display internal color functions */
const struct intel_color_funcs *color_funcs;
--
2.34.1
[Intel-gfx] [PATCH 06/39] drm/i915: move wm_disp funcs to display.funcs
Move display related members under drm_i915_private display sub-struct.
Rename struct drm_i915_wm_disp_funcs to intel_wm_funcs while at it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 34 +++
.../gpu/drm/i915/display/intel_display_core.h | 21 ++
drivers/gpu/drm/i915/i915_drv.h | 22 --
drivers/gpu/drm/i915/intel_pm.c | 42 +--
4 files changed, 59 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 24ab1501beea..7db4ac27364d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -164,16 +164,16 @@ static void ilk_pfit_enable(const struct intel_crtc_state
*crtc_state);
*/
void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
- if (dev_priv->wm_disp->update_wm)
- dev_priv->wm_disp->update_wm(dev_priv);
+ if (dev_priv->display.funcs.wm->update_wm)
+ dev_priv->display.funcs.wm->update_wm(dev_priv);
}
static int intel_compute_pipe_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp->compute_pipe_wm)
- return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
+ if (dev_priv->display.funcs.wm->compute_pipe_wm)
+ return dev_priv->display.funcs.wm->compute_pipe_wm(state, crtc);
return 0;
}
@@ -181,20 +181,20 @@ static int intel_compute_intermediate_wm(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (!dev_priv->wm_disp->compute_intermediate_wm)
+ if (!dev_priv->display.funcs.wm->compute_intermediate_wm)
return 0;
if (drm_WARN_ON(&dev_priv->drm,
- !dev_priv->wm_disp->compute_pipe_wm))
+ !dev_priv->display.funcs.wm->compute_pipe_wm))
return 0;
- return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
+ return dev_priv->display.funcs.wm->compute_intermediate_wm(state, crtc);
}
static bool intel_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp->initial_watermarks) {
- dev_priv->wm_disp->initial_watermarks(state, crtc);
+ if (dev_priv->display.funcs.wm->initial_watermarks) {
+ dev_priv->display.funcs.wm->initial_watermarks(state, crtc);
return true;
}
return false;
@@ -204,23 +204,23 @@ static void intel_atomic_update_watermarks(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp->atomic_update_watermarks)
- dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
+ if (dev_priv->display.funcs.wm->atomic_update_watermarks)
+ dev_priv->display.funcs.wm->atomic_update_watermarks(state,
crtc);
}
static void intel_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp->optimize_watermarks)
- dev_priv->wm_disp->optimize_watermarks(state, crtc);
+ if (dev_priv->display.funcs.wm->optimize_watermarks)
+ dev_priv->display.funcs.wm->optimize_watermarks(state, crtc);
}
static int intel_compute_global_watermarks(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp->compute_global_watermarks)
- return dev_priv->wm_disp->compute_global_watermarks(state);
+ if (dev_priv->display.funcs.wm->compute_global_watermarks)
+ return
dev_priv->display.funcs.wm->compute_global_watermarks(state);
return 0;
}
@@ -2400,7 +2400,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state
*state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
- if (!dev_priv->wm_disp->initial_watermarks)
+ if (!dev_priv->display.funcs.wm->initial_watermarks)
intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -8454,7 +8454,7 @@ static void sanitize_watermarks(struct drm_i915_private
*dev_priv)
int i;
/* Only supported on platforms that use atomic watermark design */
- if (!dev_priv->wm_dis
[Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private
Add display sub-struct to drm_i915_private, and start moving display related members there. This doesn't help with build dependencies yet, but adds a lot of clarity in organizing the display data, and who accesses display data and where. This is a beginning, there are still stragglers, but need to start sending the patches instead of accumulating tons more. BR, Jani. Jani Nikula (39): drm/i915: add display sub-struct to drm_i915_private drm/i915: move cdclk_funcs to display.funcs drm/i915: move dpll_funcs to display.funcs drm/i915: move hotplug_funcs to display.funcs drm/i915: move clock_gating_funcs to display.funcs drm/i915: move wm_disp funcs to display.funcs drm/i915: move fdi_funcs to display.funcs drm/i915: move color_funcs to display.funcs drm/i915: move and group gmbus members under display.gmbus drm/i915: move and group pps members under display.pps drm/i915: move dmc to display.dmc drm/i915: move and split audio under display.audio and display.funcs drm/i915: move dpll under display.dpll drm/i915: move and group fbdev under display.fbdev drm/i915: move wm to display.wm drm/i915: move and group hdcp under display.hdcp drm/i915: move hotplug to display.hotplug drm/i915: move overlay to display.overlay drm/i915: move and group sagv under display.sagv drm/i915: move and group max_bw and bw_obj under display.bw drm/i915: move opregion to display.opregion drm/i915: move and group cdclk under display.cdclk drm/i915: move backlight to display.backlight drm/i915: move mipi_mmio_base to display.dsi drm/i915: move vbt to display.vbt drm/i915: move fbc to display.fbc drm/i915/vrr: drop window2_delay member from i915 drm/i915: move and group power related members under display.power drm/i915: move and group fdi members under display.fdi drm/i915: move fb_tracking under display sub-struct drm/i915: move INTEL_FRONTBUFFER_* macros to intel_frontbuffer.h drm/i915: move dbuf under display sub-struct drm/i915: move and group modeset_wq and flip_wq under display.wq drm/i915: split gem quirks from display quirks drm/i915/quirks: abstract checking for display quirks drm/i915/quirks: abstract quirks further by making quirk ids an enum drm/i915: move quirks under display sub-struct drm/i915: move atomic_helper under display sub-struct drm/i915: move and group properties under display.properties drivers/gpu/drm/i915/display/g4x_dp.c | 4 +- drivers/gpu/drm/i915/display/hsw_ips.c| 2 +- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/icl_dsi.c| 12 +- drivers/gpu/drm/i915/display/intel_atomic.c | 8 +- drivers/gpu/drm/i915/display/intel_audio.c| 102 ++--- .../gpu/drm/i915/display/intel_backlight.c| 39 +- drivers/gpu/drm/i915/display/intel_bios.c | 214 - drivers/gpu/drm/i915/display/intel_bw.c | 52 +-- drivers/gpu/drm/i915/display/intel_cdclk.c| 282 ++-- drivers/gpu/drm/i915/display/intel_cdclk.h| 4 +- drivers/gpu/drm/i915/display/intel_color.c| 34 +- .../gpu/drm/i915/display/intel_connector.c| 8 +- drivers/gpu/drm/i915/display/intel_crt.c | 6 +- drivers/gpu/drm/i915/display/intel_ddi.c | 33 +- drivers/gpu/drm/i915/display/intel_display.c | 124 +++--- .../gpu/drm/i915/display/intel_display_core.h | 418 ++ .../drm/i915/display/intel_display_debugfs.c | 60 +-- .../drm/i915/display/intel_display_power.c| 138 +++--- .../i915/display/intel_display_power_map.c| 4 +- .../i915/display/intel_display_power_well.c | 78 ++-- .../i915/display/intel_display_power_well.h | 12 +- drivers/gpu/drm/i915/display/intel_dmc.c | 52 +-- drivers/gpu/drm/i915/display/intel_dp.c | 13 +- drivers/gpu/drm/i915/display/intel_dp_aux.c | 4 +- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll.c | 38 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 130 +++--- drivers/gpu/drm/i915/display/intel_dsi.c | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 6 +- drivers/gpu/drm/i915/display/intel_fbdev.c| 26 +- drivers/gpu/drm/i915/display/intel_fdi.c | 18 +- .../gpu/drm/i915/display/intel_frontbuffer.c | 56 +-- .../gpu/drm/i915/display/intel_frontbuffer.h | 18 + drivers/gpu/drm/i915/display/intel_gmbus.c| 46 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 134 +++--- drivers/gpu/drm/i915/display/intel_hotplug.c | 116 ++--- .../gpu/drm/i915/display/intel_lpe_audio.c| 42 +- drivers/gpu/drm/i915/display/intel_lvds.c | 4 +- .../drm/i915/display/intel_modeset_setup.c| 14 +- drivers/gpu/drm/i915/display/intel_opregion.c | 42 +- drivers/gpu/drm/i915/display/intel_overlay.c | 12 +- drivers/gpu/drm/i915/display/intel_panel.c| 5 +- .../gpu/drm/i915/display/intel_pch_refclk.c | 4 +- .../drm/i915/display/intel_plane_initial.c| 2 +- drivers/gpu
[Intel-gfx] ✓ Fi.CI.BAT: success for Fixes KW issue for NULL pointer dereference
== Series Details ==
Series: Fixes KW issue for NULL pointer dereference
URL : https://patchwork.freedesktop.org/series/107165/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11983 -> Patchwork_107165v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/index.html
Participating hosts (29 -> 39)
--
Additional (13): bat-dg1-6 bat-dg1-5 bat-adlm-1 bat-dg2-9 bat-dg2-10
bat-adlp-6 bat-adlp-4 bat-adln-1 fi-cfl-8109u bat-rplp-1 bat-rpls-1 bat-rpls-2
bat-jsl-1
Missing(3): fi-ctg-p8600 fi-hsw-4200u fi-snb-2600
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107165v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@module-reload:
- {bat-dg2-10}: NOTRUN -> [DMESG-WARN][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/bat-dg2-10/igt@i915_pm_...@module-reload.html
Known issues
Here are the changes found in Patchwork_107165v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@fbdev@nullptr:
- bat-dg1-5: NOTRUN -> [SKIP][2] ([i915#2582]) +4 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/bat-dg1-5/igt@fb...@nullptr.html
* igt@fbdev@read:
- bat-adlp-4: NOTRUN -> [SKIP][3] ([i915#2582]) +4 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/bat-adlp-4/igt@fb...@read.html
* igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlp-4: NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/bat-adlp-4/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html
* igt@gem_mmap@basic:
- bat-dg1-5: NOTRUN -> [SKIP][8] ([i915#4083])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/bat-dg1-5/igt@gem_m...@basic.html
- bat-dg1-6: NOTRUN -> [SKIP][9] ([i915#4083])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/bat-dg1-6/igt@gem_m...@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][10] ([i915#4079]) +1 similar issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html
* igt@gem_tiled_blits@basic:
- bat-dg1-5: NOTRUN -> [SKIP][11] ([i915#4077]) +2 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/bat-dg1-5/igt@gem_tiled_bl...@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][12] ([i915#4077]) +2 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-5: NOTRUN -> [SKIP][13] ([i915#4079]) +1 similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/bat-dg1-5/igt@gem_tiled_pread_basic.html
- bat-adlp-4: NOTRUN -> [SKIP][14] ([i915#3282])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/bat-adlp-4/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#1155])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html
- bat-adlp-4: NOTRUN -> [SKIP][16] ([i915#1155])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/bat-adlp-4/igt@i915_pm_backli...@basic-brightness.html
- bat-dg1-5: NOTRUN -> [SKIP][17] ([i915#1155])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@gem:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][18] ([i915#4528])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107165v1/fi-pnv-d510/igt@i915_selftest@l...@gem.html
* igt@i915_
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fixes KW issue for NULL pointer dereference
== Series Details == Series: Fixes KW issue for NULL pointer dereference URL : https://patchwork.freedesktop.org/series/107165/ State : warning == Summary == Error: dim checkpatch failed b695c16cdc66 Fixes KW issue for NULL pointer dereference -:20: ERROR:TRAILING_WHITESPACE: trailing whitespace #20: FILE: drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c:440: +^I$ total: 1 errors, 0 warnings, 0 checks, 9 lines checked
[Intel-gfx] [PATCH] Fixes KW issue for NULL pointer dereference
- adds a NULL pointer check for the input parameter
Signed-off-by: Tapas Rana
---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 9a7e50534b84..de7c892aabc5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -435,6 +435,9 @@ i915_ttm_memcpy_work_arm(struct i915_ttm_memcpy_work *work,
static bool i915_ttm_memcpy_allowed(struct ttm_buffer_object *bo,
struct ttm_resource *dst_mem)
{
+ if (!bo)
+ return false;
+
if (i915_gem_object_needs_ccs_pages(i915_ttm_to_gem(bo)))
return false;
--
2.25.1
[Intel-gfx] ✗ Fi.CI.BAT: failure for Fixes KW issues for NULL pointer dereference
== Series Details == Series: Fixes KW issues for NULL pointer dereference URL : https://patchwork.freedesktop.org/series/107160/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11983 -> Patchwork_107160v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_107160v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107160v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/index.html Participating hosts (29 -> 38) -- Additional (12): bat-dg1-6 bat-dg1-5 bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adlp-6 bat-adlp-4 fi-cfl-8109u bat-rplp-1 bat-rpls-1 bat-rpls-2 bat-jsl-1 Missing(3): fi-ctg-p8600 fi-hsw-4200u fi-snb-2600 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_107160v1: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_lrc: - bat-adlp-4: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/bat-adlp-4/igt@i915_selftest@live@gt_lrc.html Known issues Here are the changes found in Patchwork_107160v1 that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@nullptr: - bat-dg1-5: NOTRUN -> [SKIP][2] ([i915#2582]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/bat-dg1-5/igt@fb...@nullptr.html * igt@fbdev@read: - bat-adlp-4: NOTRUN -> [SKIP][3] ([i915#2582]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/bat-adlp-4/igt@fb...@read.html * igt@gem_huc_copy@huc-copy: - fi-cfl-8109u: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-apl-guc: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-adlp-4: NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/bat-adlp-4/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - fi-cfl-8109u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg1-5: NOTRUN -> [SKIP][8] ([i915#4083]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/bat-dg1-5/igt@gem_m...@basic.html - bat-dg1-6: NOTRUN -> [SKIP][9] ([i915#4083]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/bat-dg1-6/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][10] ([i915#4079]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-dg1-5: NOTRUN -> [SKIP][11] ([i915#4077]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/bat-dg1-5/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][12] ([i915#4077]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-5: NOTRUN -> [SKIP][13] ([i915#4079]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/bat-dg1-5/igt@gem_tiled_pread_basic.html - bat-adlp-4: NOTRUN -> [SKIP][14] ([i915#3282]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/bat-adlp-4/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#1155]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html - bat-adlp-4: NOTRUN -> [SKIP][16] ([i915#1155]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/bat-adlp-4/igt@i915_pm_backli...@basic-brightness.html - bat-dg1-5: NOTRUN -> [SKIP][17] ([i915#1155]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107160v1/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@hangcheck:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fixes KW issues for NULL pointer dereference
== Series Details ==
Series: Fixes KW issues for NULL pointer dereference
URL : https://patchwork.freedesktop.org/series/107160/
State : warning
== Summary ==
Error: dim checkpatch failed
639d6f6caf82 Fixes KW issues for NULL pointer dereference
-:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:15: ERROR:SPACING: space required before the open parenthesis '('
#15: FILE: drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c:438:
+ if(!bo)
-:20: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
total: 2 errors, 1 warnings, 0 checks, 9 lines checked
[Intel-gfx] [PATCH] Fixes KW issues for NULL pointer dereference
---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 9a7e50534b84..0bbf44c34cff 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -435,6 +435,9 @@ i915_ttm_memcpy_work_arm(struct i915_ttm_memcpy_work *work,
static bool i915_ttm_memcpy_allowed(struct ttm_buffer_object *bo,
struct ttm_resource *dst_mem)
{
+ if(!bo)
+ return NULL;
+
if (i915_gem_object_needs_ccs_pages(i915_ttm_to_gem(bo)))
return false;
--
2.25.1
[Intel-gfx] ✓ Fi.CI.IGT: success for i915/gvt: Fix Comet Lake
== Series Details == Series: i915/gvt: Fix Comet Lake URL : https://patchwork.freedesktop.org/series/107133/ State : success == Summary == CI Bug Log - changes from CI_DRM_11981_full -> Patchwork_107133v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_107133v1_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@psr2: - shard-iclb: [PASS][1] -> [SKIP][2] ([i915#658]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-iclb2/igt@feature_discov...@psr2.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-iclb5/igt@feature_discov...@psr2.html * igt@gem_eio@kms: - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#5784]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-tglb7/igt@gem_...@kms.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-tglb3/igt@gem_...@kms.html * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-iclb2/igt@gem_exec_balan...@parallel-bb-first.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-iclb3/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-kbl4/igt@gem_exec_fair@basic-n...@vecs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-kbl1/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-kbl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-kbl1/igt@gem_huc_c...@huc-copy.html - shard-tglb: [PASS][12] -> [SKIP][13] ([i915#2190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-tglb3/igt@gem_huc_c...@huc-copy.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-tglb7/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random: - shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-kbl4/igt@gem_lmem_swapp...@parallel-random.html * igt@gem_lmem_swapping@parallel-random-verify-ccs: - shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-apl4/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html * igt@gem_pread@exhaustion: - shard-kbl: NOTRUN -> [WARN][16] ([i915#2658]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-kbl4/igt@gem_pr...@exhaustion.html * igt@gem_pxp@protected-encrypted-src-copy-not-readible: - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-skl10/igt@gem_...@protected-encrypted-src-copy-not-readible.html * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled: - shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271]) +145 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-apl4/igt@gem_render_c...@x-tiled-to-vebox-yf-tiled.html * igt@gem_userptr_blits@dmabuf-sync: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3323]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-kbl1/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@input-checking: - shard-kbl: NOTRUN -> [DMESG-WARN][20] ([i915#4991]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-kbl7/igt@gem_userptr_bl...@input-checking.html - shard-apl: NOTRUN -> [DMESG-WARN][21] ([i915#4991]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-apl4/igt@gem_userptr_bl...@input-checking.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][22] -> [FAIL][23] ([i915#454]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-iclb2/igt@i915_pm...@dc6-dpms.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107133v1/shard-iclb3/igt@i915_pm...@dc6-dpm
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/display/dp_mst: Drop Radeon MST support, make MST atomic-only (rev3)
== Series Details == Series: drm/display/dp_mst: Drop Radeon MST support, make MST atomic-only (rev3) URL : https://patchwork.freedesktop.org/series/107073/ State : success == Summary == CI Bug Log - changes from CI_DRM_11981_full -> Patchwork_107073v3_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_107073v3_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-apl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [FAIL][50]) ([i915#4386]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl8/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl8/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl8/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl7/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl7/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl6/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl6/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl3/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl3/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl3/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl2/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl2/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl1/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl1/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-apl1/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl8/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl8/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl7/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl7/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl7/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl7/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl6/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl6/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl4/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl4/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl4/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl3/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl3/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl3/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107073v3/shard-apl3/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-t
Re: [Intel-gfx] [PATCH v6 0/4] drm/i915/display: stop HPD workers before display driver unregister
Hi Imre, Jani, Ville, Since one of CI test machines is back (bat-rpls-2) tests are regularly aborted on this machine due to bugs this patchset resolves [1], reviewing/merging these patches would allow to cure the situation on CI. [1]: https://intel-gfx-ci.01.org/tree/drm-tip/bat-rpls-2.html Regards Andrzej On 02.08.2022 14:24, Gwan-gyeong Mun wrote: Hi Jani, Ville and Imre, If there are no problems after reviewing this patch series, could you please merge it? Many thanks, G.G. On 7/22/22 3:51 PM, Andrzej Hajda wrote: Hi Jani, Ville, Arun, This patchset is replacement of patch "drm/i915/display: disable HPD workers before display driver unregister" [1]. Ive decided to split patch into two parts - fbdev and MST, there are different issues. Ive also dropped shutdown path, as it has slightly different requirements, and more importantly I am not able to test properly. v2 (thx Arun for review): - reword of commit message (Arun) - intel_fbdev_hpd_set_suspend replaced with intel_fbdev_set_suspend (Arun) v3: - new patch adding suspended flag, to handle https://gitlab.freedesktop.org/drm/intel/-/issues/5950 v4: - check suspend flag also in i915_digport_work_func v5: - added patch blocking FB creation in case HPD is supended, - added R-B from Arun to patch 3, thx v6: - finally, after getting direct access to bat-rpls-2, I have found the source of last WARN, intel_fbdev_hpd_set_suspend was not called in case of deferred setup, fixed in patch 2. [1]: https://patchwork.freedesktop.org/series/103811/ Regards Andrzej Andrzej Hajda (4): drm/i915/hpd: postpone HPD cancel work after last user suspension drm/i915/fbdev: suspend HPD before fbdev unregistration drm/i915/display: add hotplug.suspended flag drm/i915/fbdev: do not create fbdev if HPD is suspended drivers/gpu/drm/i915/display/intel_display.c | 3 +++ drivers/gpu/drm/i915/display/intel_fbdev.c | 12 ++-- drivers/gpu/drm/i915/display/intel_hotplug.c | 11 ++- drivers/gpu/drm/i915/display/intel_hotplug.h | 2 +- drivers/gpu/drm/i915/i915_driver.c | 4 ++-- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_irq.c | 1 - 7 files changed, 28 insertions(+), 7 deletions(-)
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: reschedule relocations to avoid timeouts
== Series Details == Series: drm/i915/gem: reschedule relocations to avoid timeouts URL : https://patchwork.freedesktop.org/series/107125/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11981_full -> Patchwork_107125v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_107125v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107125v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_107125v1_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_heartbeat: - shard-skl: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-skl1/igt@i915_selftest@live@gt_heartbeat.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v1/shard-skl4/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_plane_cursor@pipe-c-overlay-size-64: - shard-kbl: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-kbl1/igt@kms_plane_cur...@pipe-c-overlay-size-64.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v1/shard-kbl4/igt@kms_plane_cur...@pipe-c-overlay-size-64.html Known issues Here are the changes found in Patchwork_107125v1_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@psr2: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#658]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-iclb2/igt@feature_discov...@psr2.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v1/shard-iclb6/igt@feature_discov...@psr2.html * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-kbl4/igt@gem_ctx_isolation@preservation...@vecs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v1/shard-kbl1/igt@gem_ctx_isolation@preservation...@vecs0.html * igt@gem_exec_balancer@parallel-contexts: - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v1/shard-skl6/igt@gem_exec_balan...@parallel-contexts.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-tglb2/igt@gem_exec_fair@basic-f...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v1/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v1/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_suspend@basic-s3@smem: - shard-apl: NOTRUN -> [DMESG-WARN][14] ([i915#180]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v1/shard-apl1/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - shard-kbl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v1/shard-kbl4/igt@gem_huc_c...@huc-copy.html - shard-tglb: [PASS][16] -> [SKIP][17] ([i915#2190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11981/shard-tglb3/igt@gem_huc_c...@huc-copy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v1/shard-tglb7/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random: - shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +4 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v1/shard-kbl7/igt@gem_lmem_swapp...@parallel-random.html * igt@gem_lmem_swapping@parallel-random-verify-ccs: - shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v1/shard-apl1/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html * igt@gem_pread@exhaustion: - shard-kbl: NOTRUN -> [WARN][20] ([i915#2658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v1/shard-kbl4/igt@gem_pr...@exhaustion.html * igt@gem_render_copy@x-tiled-to-veb
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: reschedule relocations to avoid timeouts (rev2)
== Series Details == Series: drm/i915/gem: reschedule relocations to avoid timeouts (rev2) URL : https://patchwork.freedesktop.org/series/107125/ State : success == Summary == CI Bug Log - changes from CI_DRM_11983 -> Patchwork_107125v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/index.html Participating hosts (29 -> 28) -- Additional (1): fi-cfl-8109u Missing(2): fi-ctg-p8600 fi-hsw-4200u Known issues Here are the changes found in Patchwork_107125v2 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-cfl-8109u: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-apl-guc: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/fi-apl-guc/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@verify-random: - fi-cfl-8109u: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live@gt_heartbeat: - fi-bdw-5557u: [PASS][4] -> [DMESG-FAIL][5] ([i915#5334]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@requests: - fi-blb-e6850: [PASS][6] -> [DMESG-FAIL][7] ([i915#4528]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-blb-e6850/igt@i915_selftest@l...@requests.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/fi-blb-e6850/igt@i915_selftest@l...@requests.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: [PASS][8] -> [INCOMPLETE][9] ([i915#5982]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html - fi-bdw-5557u: [PASS][10] -> [INCOMPLETE][11] ([i915#146]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-snb-2600:NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/fi-snb-2600/igt@kms_chamel...@common-hpd-after-suspend.html - fi-apl-guc: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/fi-apl-guc/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-cfl-8109u: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/fi-cfl-8109u/igt@kms_chamel...@dp-crc-fast.html * igt@prime_vgem@basic-userptr: - fi-cfl-8109u: NOTRUN -> [SKIP][15] ([fdo#109271]) +10 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/fi-cfl-8109u/igt@prime_v...@basic-userptr.html Possible fixes * igt@core_hotunplug@unbind-rebind: - fi-apl-guc: [INCOMPLETE][16] ([i915#6533]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[INCOMPLETE][18] ([i915#3921]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107125v2/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#5334]: https://gitlab.freedeskto
Re: [Intel-gfx] [PATCH 0/2] Add DP MST DSC support to i915
On Wed, Aug 10, 2022 at 04:02:08PM -0400, Lyude Paul wrote: > Btw, what's the plan for this? Figured I'd ask since I noticed this on the ML, > nd I'm now finishing up getting the atomic only MST patches I've been working > on merged :) Current plan is that I need to fix this, as current implementation doesn't seem to work because of my wrong assumption that drm_dp_mst_find_vcpi_slots will fail if no slots are available and then we can fallback to DSC. In reality that function can return whatever bogus value it wants, like 71 slots, while you have only 63 available. The real check is done in drm_dp_mst_atomic_check, which would of course reject that configuration, however by that moment its going to be too late for swithcing to DSC. So looke like I will have to move that check at least partly to where DSC/no DSC decision is done. However if there are multiple displays we get another problem, lets say we have 2 displays requiring 40 vcpi slots each in DSC mode with certain input bpp. We have now either option to reject the whole config or go back and try with another bpp to check if we can reduce amount of slots. Because by default we choose the first one which fits, however by the time when compute_config is called, we still don't have all config computed, which might lead to that last crtc can either run our of vcpi slots or we will have to go back and try recalculating with higher compression ratio. My other question was that DSC was supposed to be "visually" lossless, wondering why we are still trying with different bpps? Could have just set highest compression ratio right away. So need to sort this out first before floating new series. Stan > > On Wed, 2022-08-10 at 11:17 +0300, Stanislav Lisovskiy wrote: > > Currently we have only DSC support for DP SST. > > > > Stanislav Lisovskiy (2): > > drm: Add missing DP DSC extended capability definitions. > > drm/i915: Add DSC support to MST path > > > > drivers/gpu/drm/i915/display/intel_dp.c | 76 +- > > drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 145 > > include/drm/display/drm_dp.h| 10 +- > > 4 files changed, 203 insertions(+), 45 deletions(-) > > > > -- > Cheers, > Lyude Paul (she/her) > Software Engineer at Red Hat >
[Intel-gfx] ✓ Fi.CI.BAT: success for Fix HFVSDB parsing
== Series Details == Series: Fix HFVSDB parsing URL : https://patchwork.freedesktop.org/series/107144/ State : success == Summary == CI Bug Log - changes from CI_DRM_11983 -> Patchwork_107144v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/index.html Participating hosts (29 -> 28) -- Additional (1): fi-cfl-8109u Missing(2): fi-ctg-p8600 fi-hsw-4200u Known issues Here are the changes found in Patchwork_107144v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-cfl-8109u: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-apl-guc: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@verify-random: - fi-cfl-8109u: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[PASS][4] -> [INCOMPLETE][5] ([i915#4785]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@requests: - fi-blb-e6850: [PASS][6] -> [DMESG-FAIL][7] ([i915#4528]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-blb-e6850/igt@i915_selftest@l...@requests.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: [PASS][8] -> [INCOMPLETE][9] ([i915#5982]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-snb-2600:NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/fi-snb-2600/igt@kms_chamel...@common-hpd-after-suspend.html - fi-apl-guc: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/fi-apl-guc/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-cfl-8109u: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/fi-cfl-8109u/igt@kms_chamel...@dp-crc-fast.html * igt@prime_vgem@basic-userptr: - fi-cfl-8109u: NOTRUN -> [SKIP][13] ([fdo#109271]) +10 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/fi-cfl-8109u/igt@prime_v...@basic-userptr.html Possible fixes * igt@core_hotunplug@unbind-rebind: - fi-apl-guc: [INCOMPLETE][14] ([i915#6533]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[INCOMPLETE][16] ([i915#3921]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107144v1/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785 [i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982 [i915#6533]: https://gitlab.freedesktop.org/drm/intel/issues/6533 Build changes - * Linux: CI_DRM_11983 -> Patchwork_107144v1 CI-20190529: 20190529 CI_DRM_11983: be61f160096902ab2f402179c81f6de59b016d82 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6621: 62685978a0c00bb4b874935129b9761ae10d5ca1 @ https://gitla
