[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: HuC loading for DG2
== Series Details ==
Series: drm/i915: HuC loading for DG2
URL : https://patchwork.freedesktop.org/series/107477/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12002_full -> Patchwork_107477v1_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_107477v1_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_107477v1_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (12 -> 11)
--
Missing(1): shard-rkl
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107477v1_full:
### IGT changes ###
Possible regressions
* igt@gem_eio@hibernate:
- shard-glk: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v1/shard-glk1/igt@gem_...@hibernate.html
* igt@gem_eio@suspend:
- shard-apl: NOTRUN -> [INCOMPLETE][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v1/shard-apl8/igt@gem_...@suspend.html
* igt@gem_exec_suspend@basic-s0@smem:
- shard-apl: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12002/shard-apl1/igt@gem_exec_suspend@basic...@smem.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v1/shard-apl8/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-glk: [PASS][5] -> [INCOMPLETE][6] +2 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12002/shard-glk9/igt@gem_exec_suspend@basic-s4-devi...@smem.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v1/shard-glk7/igt@gem_exec_suspend@basic-s4-devi...@smem.html
* {igt@gem_huc_copy@huc-copy-after-reset} (NEW):
- shard-iclb: NOTRUN -> [SKIP][7] +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v1/shard-iclb4/igt@gem_huc_c...@huc-copy-after-reset.html
- {shard-tglu}: NOTRUN -> [SKIP][8]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v1/shard-tglu-2/igt@gem_huc_c...@huc-copy-after-reset.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-iclb: [PASS][9] -> [INCOMPLETE][10] +4 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12002/shard-iclb5/igt@i915_susp...@basic-s3-without-i915.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v1/shard-iclb3/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-iclb: NOTRUN -> [INCOMPLETE][11] +3 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v1/shard-iclb2/igt@kms_frontbuffer_track...@fbc-suspend.html
New tests
-
New tests have been introduced between CI_DRM_12002_full and
Patchwork_107477v1_full:
### New IGT tests (2) ###
* igt@gem_huc_copy@huc-copy-after-reset:
- Statuses : 1 pass(s) 6 skip(s)
- Exec time: [0.0, 0.13] s
* igt@gem_huc_copy@huc-copy-after-suspend-resume:
- Statuses : 1 pass(s) 5 skip(s)
- Exec time: [0.0, 1.85] s
Known issues
Here are the changes found in Patchwork_107477v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@api_intel_bb@crc32:
- shard-iclb: NOTRUN -> [SKIP][12] ([i915#6230])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v1/shard-iclb5/igt@api_intel...@crc32.html
- shard-tglb: NOTRUN -> [SKIP][13] ([i915#6230])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v1/shard-tglb5/igt@api_intel...@crc32.html
* igt@feature_discovery@display-3x:
- shard-iclb: NOTRUN -> [SKIP][14] ([i915#1839])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v1/shard-iclb5/igt@feature_discov...@display-3x.html
* igt@gem_ccs@suspend-resume:
- shard-iclb: NOTRUN -> [SKIP][15] ([i915#5327])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v1/shard-iclb5/igt@gem_...@suspend-resume.html
* igt@gem_ctx_persistence@smoketest:
- shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1099]) +7
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v1/shard-snb6/igt@gem_ctx_persiste...@smoketest.html
* igt@gem_eio@hibernate:
- shard-apl: NOTRUN -> [INCOMPLETE][17] ([i915#6598]) +2 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v1/shard-apl2/igt@gem_...@hibernate.html
- shard-snb: NOTRUN -> [INCOMPLETE][18] ([i915#6598])
[18]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc/slpc: Allow SLPC to use efficient frequency (rev4)
== Series Details ==
Series: drm/i915/guc/slpc: Allow SLPC to use efficient frequency (rev4)
URL : https://patchwork.freedesktop.org/series/107101/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12004 -> Patchwork_107101v4
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_107101v4 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_107101v4, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v4/index.html
Participating hosts (38 -> 30)
--
Missing(8): fi-jsl-1 bat-dg1-5 fi-apl-guc bat-adln-1 bat-rplp-1
bat-rpls-1 bat-dg2-10 fi-ehl-2
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107101v4:
### IGT changes ###
Possible regressions
* igt@fbdev@write:
- bat-dg1-6: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/bat-dg1-6/igt@fb...@write.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v4/bat-dg1-6/igt@fb...@write.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@fbdev@read:
- {bat-dg2-9}:[PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/bat-dg2-9/igt@fb...@read.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v4/bat-dg2-9/igt@fb...@read.html
* igt@gem_basic@bad-close:
- {bat-dg2-8}:NOTRUN -> [INCOMPLETE][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v4/bat-dg2-8/igt@gem_ba...@bad-close.html
Known issues
Here are the changes found in Patchwork_107101v4 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][6] -> [INCOMPLETE][7] ([i915#4785])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v4/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-g3258: [PASS][8] -> [INCOMPLETE][9] ([i915#3303] /
[i915#4785])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v4/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [PASS][10] -> [INCOMPLETE][11] ([i915#5982])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v4/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
- fi-pnv-d510:NOTRUN -> [INCOMPLETE][12] ([i915#6598] / [i915#6601])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v4/fi-pnv-d510/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [PASS][13] -> [FAIL][14] ([i915#6298])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v4/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][15] ([fdo#109271] / [i915#4312] /
[i915#5594] / [i915#6246])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v4/fi-hsw-4770/igt@run...@aborted.html
- fi-hsw-g3258: NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#4312] /
[i915#6246])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v4/fi-hsw-g3258/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gem:
- fi-pnv-d510:[DMESG-FAIL][17] ([i915#4528]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-pnv-d510/igt@i915_selftest@l...@gem.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v4/fi-pnv-d510/igt@i915_selftest@l...@gem.html
Warnings
* igt@i915_module_load@load:
- fi-rkl-guc: [TIMEOUT][19] ([i915#6627]) -> [TIMEOUT][20]
([i915#6627] / [i915#6637])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-rkl-guc/igt@i915_module_l...@load.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v4/fi-rkl-guc/igt@i915_module_l...@load.html
- bat-dg1-6:
[Intel-gfx] ✗ Fi.CI.BAT: failure for CDCLK churn: move checks to atomic check
== Series Details == Series: CDCLK churn: move checks to atomic check URL : https://patchwork.freedesktop.org/series/107522/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12004 -> Patchwork_107522v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_107522v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107522v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107522v1/index.html Participating hosts (38 -> 36) -- Additional (1): fi-tgl-dsi Missing(3): bat-adln-1 bat-dg2-10 bat-dg1-5 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_107522v1: ### IGT changes ### Possible regressions * igt@i915_module_load@load: - fi-rkl-11600: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-rkl-11600/igt@i915_module_l...@load.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107522v1/fi-rkl-11600/igt@i915_module_l...@load.html - fi-skl-6700k2: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-skl-6700k2/igt@i915_module_l...@load.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107522v1/fi-skl-6700k2/igt@i915_module_l...@load.html - fi-cfl-8700k: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-cfl-8700k/igt@i915_module_l...@load.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107522v1/fi-cfl-8700k/igt@i915_module_l...@load.html - fi-adl-ddr5:[PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-adl-ddr5/igt@i915_module_l...@load.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107522v1/fi-adl-ddr5/igt@i915_module_l...@load.html - fi-cfl-guc: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-cfl-guc/igt@i915_module_l...@load.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107522v1/fi-cfl-guc/igt@i915_module_l...@load.html - fi-bdw-5557u: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-bdw-5557u/igt@i915_module_l...@load.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107522v1/fi-bdw-5557u/igt@i915_module_l...@load.html - fi-cfl-8109u: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-cfl-8109u/igt@i915_module_l...@load.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107522v1/fi-cfl-8109u/igt@i915_module_l...@load.html * igt@kms_busy@basic@flip: - fi-bsw-kefka: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-bsw-kefka/igt@kms_busy@ba...@flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107522v1/fi-bsw-kefka/igt@kms_busy@ba...@flip.html - fi-skl-6600u: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-skl-6600u/igt@kms_busy@ba...@flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107522v1/fi-skl-6600u/igt@kms_busy@ba...@flip.html - fi-glk-j4005: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-glk-j4005/igt@kms_busy@ba...@flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107522v1/fi-glk-j4005/igt@kms_busy@ba...@flip.html * igt@kms_force_connector_basic@force-connector-state: - fi-bdw-gvtdvm: [PASS][21] -> [DMESG-WARN][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-bdw-gvtdvm/igt@kms_force_connector_ba...@force-connector-state.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107522v1/fi-bdw-gvtdvm/igt@kms_force_connector_ba...@force-connector-state.html Warnings * igt@i915_module_load@load: - fi-rkl-guc: [TIMEOUT][23] ([i915#6627]) -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/fi-rkl-guc/igt@i915_module_l...@load.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107522v1/fi-rkl-guc/igt@i915_module_l...@load.html - bat-dg1-6: [TIMEOUT][25] ([i915#6627]) -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12004/bat-dg1-6/igt@i915_module_l...@load.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107522v1/bat-dg1-6/igt@i915_module_l...@load.html Suppressed The following results come from untrusted machines, tests, or statuses.
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for CDCLK churn: move checks to atomic check
== Series Details == Series: CDCLK churn: move checks to atomic check URL : https://patchwork.freedesktop.org/series/107522/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for CDCLK churn: move checks to atomic check
== Series Details ==
Series: CDCLK churn: move checks to atomic check
URL : https://patchwork.freedesktop.org/series/107522/
State : warning
== Summary ==
Error: dim checkpatch failed
c3061d754e21 drm/i915/display: Add CDCLK actions to intel_cdclk_state
d6438fdf45eb drm/i915/squash: s/intel_cdclk_can_squash/intel_cdclk_squash
-:43: CHECK:BRACES: braces {} should be used on all arms of this statement
#43: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1751:
+ if (waveform && has_cdclk_squasher(dev_priv)) {
[...]
+ }
[...]
-:62: CHECK:BRACES: Unbalanced braces around else statement
#62: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1769:
+ } else
-:97: ERROR:TRAILING_WHITESPACE: trailing whitespace
#97: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1994:
+^I$
total: 1 errors, 0 warnings, 2 checks, 103 lines checked
9f16f8721589 drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl
-:23: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#23: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:41:
+#define ADLP_CDCLK_CRAWL(dev_priv, vco)(HAS_CDCLK_CRAWL(dev_priv) &&
dev_priv->cdclk.hw.vco > 0 && vco > 0)
-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible
side-effects?
#23: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:41:
+#define ADLP_CDCLK_CRAWL(dev_priv, vco)(HAS_CDCLK_CRAWL(dev_priv) &&
dev_priv->cdclk.hw.vco > 0 && vco > 0)
-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'vco' - possible side-effects?
#23: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:41:
+#define ADLP_CDCLK_CRAWL(dev_priv, vco)(HAS_CDCLK_CRAWL(dev_priv) &&
dev_priv->cdclk.hw.vco > 0 && vco > 0)
-:23: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'vco' may be better as '(vco)'
to avoid precedence issues
#23: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:41:
+#define ADLP_CDCLK_CRAWL(dev_priv, vco)(HAS_CDCLK_CRAWL(dev_priv) &&
dev_priv->cdclk.hw.vco > 0 && vco > 0)
-:99: ERROR:TRAILING_WHITESPACE: trailing whitespace
#99: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1984:
+ ^I^Ia_div == b_div && $
-:99: ERROR:CODE_INDENT: code indent should use tabs where possible
#99: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1984:
+ ^I^Ia_div == b_div && $
-:99: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#99: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1984:
+ ^I^Ia_div == b_div && $
-:99: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#99: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1984:
+ ^I^Ia_div == b_div && $
total: 2 errors, 3 warnings, 3 checks, 92 lines checked
b882cdeeec1f drm/i915/display: Add cdclk checks to atomic check
[Intel-gfx] [PATCH v3] drm/i915/guc/slpc: Allow SLPC to use efficient frequency
Host Turbo operates at efficient frequency when GT is not idle unless
the user or workload has forced it to a higher level. Replicate the same
behavior in SLPC by allowing the algorithm to use efficient frequency.
We had disabled it during boot due to concerns that it might break
kernel ABI for min frequency. However, this is not the case since
SLPC will still abide by the (min,max) range limits.
With this change, min freq will be at efficient frequency level at init
instead of fused min (RPn). If user chooses to reduce min freq below the
efficient freq, we will turn off usage of efficient frequency and honor
the user request. When a higher value is written, it will get toggled
back again.
The patch also corrects the register which needs to be read for obtaining
the correct efficient frequency for Gen9+.
We see much better perf numbers with benchmarks like glmark2 with
efficient frequency usage enabled as expected.
v2: Address review comments (Rodrigo)
v3: with efficient frequency being dynamic, it is possible that the req
frequency may go beyond max freq. This will cause SLPC selftests to fail.
Add a FIXME there to start the test with [RPn, RP0] instead and restore
it afterwards.
BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/5468
Cc: Rodrigo Vivi
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/intel_rps.c | 7 ++-
drivers/gpu/drm/i915/gt/selftest_slpc.c | 9 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 66 -
drivers/gpu/drm/i915/intel_mchbar_regs.h| 3 +
4 files changed, 31 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index c7d381ad90cf..8c289a032103 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1107,7 +1107,12 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps,
struct intel_rps_freq_caps *c
caps->min_freq = (rp_state_cap >> 0) & 0xff;
} else {
caps->rp0_freq = (rp_state_cap >> 0) & 0xff;
- caps->rp1_freq = (rp_state_cap >> 8) & 0xff;
+ if (GRAPHICS_VER(i915) >= 10)
+ caps->rp1_freq = REG_FIELD_GET(RPE_MASK,
+
intel_uncore_read(to_gt(i915)->uncore,
+ GEN10_FREQ_INFO_REC));
+ else
+ caps->rp1_freq = (rp_state_cap >> 8) & 0xff;
caps->min_freq = (rp_state_cap >> 16) & 0xff;
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c
b/drivers/gpu/drm/i915/gt/selftest_slpc.c
index ac29691e0b1a..f8a1d27df272 100644
--- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
@@ -166,6 +166,15 @@ static int run_test(struct intel_gt *gt, int test_type)
return -EIO;
}
+ /*
+* FIXME: With efficient frequency enabled, GuC can request
+* frequencies higher than the SLPC max. While this is fixed
+* in GuC, we level set these tests with RPn as min.
+*/
+ err = slpc_set_min_freq(slpc, slpc->min_freq);
+ if (err)
+ return err;
+
if (slpc->min_freq == slpc->rp0_freq) {
pr_err("Min/Max are fused to the same value\n");
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index e1fa1f32f29e..9d49ccef03bb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -137,17 +137,6 @@ static int guc_action_slpc_set_param(struct intel_guc
*guc, u8 id, u32 value)
return ret > 0 ? -EPROTO : ret;
}
-static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)
-{
- u32 request[] = {
- GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
- SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1),
- id,
- };
-
- return intel_guc_send(guc, request, ARRAY_SIZE(request));
-}
-
static bool slpc_is_running(struct intel_guc_slpc *slpc)
{
return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
@@ -201,16 +190,6 @@ static int slpc_set_param(struct intel_guc_slpc *slpc, u8
id, u32 value)
return ret;
}
-static int slpc_unset_param(struct intel_guc_slpc *slpc,
- u8 id)
-{
- struct intel_guc *guc = slpc_to_guc(slpc);
-
- GEM_BUG_ON(id >= SLPC_MAX_PARAM);
-
- return guc_action_slpc_unset_param(guc, id);
-}
-
static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
{
struct drm_i915_private *i915 = slpc_to_i915(slpc);
@@ -491,6 +470,16 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc
*slpc, u32 val)
with_intel_runtime_pm(>runtime_pm, wakeref) {
+ /* Ignore efficient freq if lower min freq is requested */
+ ret = slpc_set_param(slpc,
+
[Intel-gfx] [PATCH 3/4] drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl
Apart from checking if crawling can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
v2: Move crawling steps to a switch case (anusha)
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 45 +-
1 file changed, 26 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f98fd48fe905..7bba10635c5e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -38,6 +38,7 @@
#include "intel_psr.h"
#include "vlv_sideband.h"
+#define ADLP_CDCLK_CRAWL(dev_priv, vco)(HAS_CDCLK_CRAWL(dev_priv) &&
dev_priv->cdclk.hw.vco > 0 && vco > 0)
/**
* DOC: CDCLK / RAWCLK
*
@@ -1727,10 +1728,7 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
return;
}
- if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0)
{
- if (dev_priv->cdclk.hw.vco != vco)
- adlp_cdclk_pll_crawl(dev_priv, vco);
- } else if (DISPLAY_VER(dev_priv) >= 11) {
+ if (!ADLP_CDCLK_CRAWL(dev_priv, vco) && DISPLAY_VER(dev_priv) >= 11) {
if (dev_priv->cdclk.hw.vco != 0 &&
dev_priv->cdclk.hw.vco != vco)
icl_cdclk_pll_disable(dev_priv);
@@ -1748,18 +1746,21 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
waveform = cdclk_squash_waveform(dev_priv, cdclk);
- if (waveform && has_cdclk_squasher(dev_priv)) {
- clock = vco / 2;
+ if ((waveform && has_cdclk_squasher(dev_priv)) ||
ADLP_CDCLK_CRAWL(dev_priv, vco)) {
for (i = 0; i < MAX_CDCLK_ACTIONS; i++) {
switch (cdclk_steps[i].action) {
+ case INTEL_CDCLK_CRAWL:
+ adlp_cdclk_pll_crawl(dev_priv, vco);
+ clock = cdclk;
+ break;
case INTEL_CDCLK_SQUASH:
waveform = cdclk_squash_waveform(dev_priv,
cdclk_steps[i].cdclk);
squash_ctl = CDCLK_SQUASH_ENABLE |
CDCLK_SQUASH_WINDOW_SIZE(0xf) |
waveform;
intel_de_write(dev_priv, CDCLK_SQUASH_CTL,
squash_ctl);
+ clock = vco / 2;
break;
case INTEL_CDCLK_NOOP:
- case INTEL_CDCLK_CRAWL:
case INTEL_CDCLK_MODESET:
break;
default:
@@ -1956,10 +1957,11 @@ void intel_cdclk_uninit_hw(struct drm_i915_private
*i915)
skl_cdclk_uninit_hw(i915);
}
-static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *a,
- const struct intel_cdclk_config *b)
+static bool intel_cdclk_crawl(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_state *a,
+ struct intel_cdclk_state *b)
{
+ struct cdclk_step *cdclk_transition = b->steps;
int a_div, b_div;
if (!HAS_CDCLK_CRAWL(dev_priv))
@@ -1969,13 +1971,18 @@ static bool intel_cdclk_can_crawl(struct
drm_i915_private *dev_priv,
* The vco and cd2x divider will change independently
* from each, so we disallow cd2x change when crawling.
*/
- a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
- b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
+ a_div = DIV_ROUND_CLOSEST(a->actual.vco, a->actual.cdclk);
+ b_div = DIV_ROUND_CLOSEST(b->actual.vco, b->actual.cdclk);
- return a->vco != 0 && b->vco != 0 &&
- a->vco != b->vco &&
- a_div == b_div &&
- a->ref == b->ref;
+ cdclk_transition[0].action = INTEL_CDCLK_CRAWL;
+ cdclk_transition[0].cdclk = b->actual.cdclk;
+ cdclk_transition[1].action = INTEL_CDCLK_NOOP;
+ cdclk_transition[1].cdclk = b->actual.cdclk;
+
+ return a->actual.vco != 0 && b->actual.vco != 0 &&
+ a->actual.vco != b->actual.vco &&
+ a_div == b_div &&
+ a->actual.ref == b->actual.ref;
}
static bool intel_cdclk_squash(struct drm_i915_private *dev_priv,
@@ -2781,9 +2788,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
new_cdclk_state)) {
drm_dbg_kms(_priv->drm,
"Can change cdclk via squasher\n");
- } else if (intel_cdclk_can_crawl(dev_priv,
-_cdclk_state->actual,
-_cdclk_state->actual)) {
+ } else if
[Intel-gfx] [PATCH 2/4] drm/i915/squash: s/intel_cdclk_can_squash/intel_cdclk_squash
Apart from checking if squashing can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
v2: Move squashing bits to switch case.(Anusha)
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 62 ++
1 file changed, 40 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 86a22c3766e5..f98fd48fe905 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1693,12 +1693,18 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
+ struct intel_cdclk_state *cdclk_state =
to_intel_cdclk_state(dev_priv->cdclk.obj.state);
+ struct intel_atomic_state *state = cdclk_state->base.state;
+ struct intel_cdclk_state *new_cdclk_state =
intel_atomic_get_new_cdclk_state(state);
+ struct cdclk_step *cdclk_steps = new_cdclk_state->steps;
int cdclk = cdclk_config->cdclk;
int vco = cdclk_config->vco;
+ u32 squash_ctl = 0;
u32 val;
u16 waveform;
int clock;
int ret;
+ int i;
/* Inform power controller of upcoming frequency change. */
if (DISPLAY_VER(dev_priv) >= 11)
@@ -1742,21 +1748,27 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
waveform = cdclk_squash_waveform(dev_priv, cdclk);
- if (waveform)
+ if (waveform && has_cdclk_squasher(dev_priv)) {
clock = vco / 2;
- else
+ for (i = 0; i < MAX_CDCLK_ACTIONS; i++) {
+ switch (cdclk_steps[i].action) {
+ case INTEL_CDCLK_SQUASH:
+ waveform = cdclk_squash_waveform(dev_priv,
cdclk_steps[i].cdclk);
+ squash_ctl = CDCLK_SQUASH_ENABLE |
+CDCLK_SQUASH_WINDOW_SIZE(0xf) |
waveform;
+ intel_de_write(dev_priv, CDCLK_SQUASH_CTL,
squash_ctl);
+ break;
+ case INTEL_CDCLK_NOOP:
+ case INTEL_CDCLK_CRAWL:
+ case INTEL_CDCLK_MODESET:
+ break;
+ default:
+ break;
+ }
+ }
+ } else
clock = cdclk;
- if (has_cdclk_squasher(dev_priv)) {
- u32 squash_ctl = 0;
-
- if (waveform)
- squash_ctl = CDCLK_SQUASH_ENABLE |
- CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
-
- intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
- }
-
val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
skl_cdclk_decimal(cdclk);
@@ -1966,10 +1978,11 @@ static bool intel_cdclk_can_crawl(struct
drm_i915_private *dev_priv,
a->ref == b->ref;
}
-static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *a,
- const struct intel_cdclk_config *b)
+static bool intel_cdclk_squash(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_state *a,
+ struct intel_cdclk_state *b)
{
+ struct cdclk_step *cdclk_transition = b->steps;
/*
* FIXME should store a bit more state in intel_cdclk_config
* to differentiate squasher vs. cd2x divider properly. For
@@ -1978,11 +1991,16 @@ static bool intel_cdclk_can_squash(struct
drm_i915_private *dev_priv,
*/
if (!has_cdclk_squasher(dev_priv))
return false;
+
+ cdclk_transition[0].action = INTEL_CDCLK_SQUASH;
+ cdclk_transition[0].cdclk = b->actual.cdclk;
+ cdclk_transition[1].action = INTEL_CDCLK_NOOP;
+ cdclk_transition[1].cdclk = b->actual.cdclk;
- return a->cdclk != b->cdclk &&
- a->vco != 0 &&
- a->vco == b->vco &&
- a->ref == b->ref;
+ return a->actual.cdclk != b->actual.cdclk &&
+ a->actual.vco != 0 &&
+ a->actual.vco == b->actual.vco &&
+ a->actual.ref == b->actual.ref;
}
/**
@@ -2758,9 +2776,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
pipe = INVALID_PIPE;
}
- if (intel_cdclk_can_squash(dev_priv,
- _cdclk_state->actual,
- _cdclk_state->actual)) {
+ if (intel_cdclk_squash(dev_priv,
+ old_cdclk_state,
+
[Intel-gfx] [PATCH 4/4] drm/i915/display: Add cdclk checks to atomic check
Checking cdclk conditions during atomic check and preparing
for commit phase so we can have atomic commit as simple
as possible. Add the specific steps to be taken during
cdclk changes, prepare for squashing, crawling and modeset
scenarios.
v2: Add intel_cdclk_modeset() similar to intel_cdclk_squash()
and intel_cdclk_crawl().
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 61 ++
1 file changed, 38 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 7bba10635c5e..cb58fc857484 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -38,7 +38,6 @@
#include "intel_psr.h"
#include "vlv_sideband.h"
-#define ADLP_CDCLK_CRAWL(dev_priv, vco)(HAS_CDCLK_CRAWL(dev_priv) &&
dev_priv->cdclk.hw.vco > 0 && vco > 0)
/**
* DOC: CDCLK / RAWCLK
*
@@ -1728,27 +1727,10 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
return;
}
- if (!ADLP_CDCLK_CRAWL(dev_priv, vco) && DISPLAY_VER(dev_priv) >= 11) {
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
- icl_cdclk_pll_disable(dev_priv);
-
- if (dev_priv->cdclk.hw.vco != vco)
- icl_cdclk_pll_enable(dev_priv, vco);
- } else {
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
- bxt_de_pll_disable(dev_priv);
-
- if (dev_priv->cdclk.hw.vco != vco)
- bxt_de_pll_enable(dev_priv, vco);
- }
-
waveform = cdclk_squash_waveform(dev_priv, cdclk);
- if ((waveform && has_cdclk_squasher(dev_priv)) ||
ADLP_CDCLK_CRAWL(dev_priv, vco)) {
- for (i = 0; i < MAX_CDCLK_ACTIONS; i++) {
- switch (cdclk_steps[i].action) {
+ for (i = 0; i < MAX_CDCLK_ACTIONS; i++) {
+ switch (cdclk_steps[i].action) {
case INTEL_CDCLK_CRAWL:
adlp_cdclk_pll_crawl(dev_priv, vco);
clock = cdclk;
@@ -1760,15 +1742,28 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
intel_de_write(dev_priv, CDCLK_SQUASH_CTL,
squash_ctl);
clock = vco / 2;
break;
- case INTEL_CDCLK_NOOP:
case INTEL_CDCLK_MODESET:
+ if (DISPLAY_VER(dev_priv) >= 11) {
+ if (dev_priv->cdclk.hw.vco != 0 &&
+ dev_priv->cdclk.hw.vco != vco)
+ icl_cdclk_pll_disable(dev_priv);
+ if (dev_priv->cdclk.hw.vco != vco)
+ icl_cdclk_pll_enable(dev_priv,
vco);
+ } else {
+ if (dev_priv->cdclk.hw.vco != 0 &&
+ dev_priv->cdclk.hw.vco != vco)
+ bxt_de_pll_disable(dev_priv);
+ if (dev_priv->cdclk.hw.vco != vco)
+ bxt_de_pll_enable(dev_priv,
vco);
+ }
+ clock = cdclk;
+ break;
+ case INTEL_CDCLK_NOOP:
break;
default:
break;
}
}
- } else
- clock = cdclk;
val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
@@ -2010,6 +2005,24 @@ static bool intel_cdclk_squash(struct drm_i915_private
*dev_priv,
a->actual.ref == b->actual.ref;
}
+static void intel_cdclk_modeset(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *a,
+ const struct intel_cdclk_config *b)
+{
+ struct intel_cdclk_state *new_cdclk_state;
+ struct cdclk_step *cdclk_transition;
+ struct intel_cdclk_state *cdclk_state =
to_intel_cdclk_state(i915->cdclk.obj.state);
+ struct intel_atomic_state *state = cdclk_state->base.state;
+
+ new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
+ cdclk_transition = new_cdclk_state->steps;
+
+ cdclk_transition[0].action = INTEL_CDCLK_MODESET;
+ cdclk_transition[0].cdclk = b->cdclk;
+ cdclk_transition[1].action = INTEL_CDCLK_NOOP;
+ cdclk_transition[1].cdclk = b->cdclk;
+}
+
/**
* intel_cdclk_needs_modeset - Determine if changong between the
[Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to intel_cdclk_state
This is a prep patch for what the rest of the series does.
Add existing actions that change cdclk - squash, crawl, modeset to
intel_cdclk_state so we have access to the cdclk values
that are in transition.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
b/drivers/gpu/drm/i915/display/intel_cdclk.h
index b535cf6a7d9e..43835688ee02 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -15,6 +15,14 @@ struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc_state;
+enum cdclk_actions {
+ INTEL_CDCLK_MODESET = 0,
+ INTEL_CDCLK_SQUASH,
+ INTEL_CDCLK_CRAWL,
+ INTEL_CDCLK_NOOP,
+ MAX_CDCLK_ACTIONS
+};
+
struct intel_cdclk_config {
unsigned int cdclk, vco, ref, bypass;
u8 voltage_level;
@@ -51,6 +59,11 @@ struct intel_cdclk_state {
/* bitmask of active pipes */
u8 active_pipes;
+
+ struct cdclk_step {
+ enum cdclk_actions action;
+ u32 cdclk;
+ } steps[MAX_CDCLK_ACTIONS];
};
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
--
2.25.1
[Intel-gfx] [PATCH 0/4] CDCLK churn: move checks to atomic check
The intention is to check for squashing, crawling and modeset conditions at atomic check phase and prepare for commit phase. This basically means the in-flight cdclk state is available. intel_cdclk_can_squash(), intel_cdclk_can_crawl() and intel_cdclk_needs_modeset() have changes to accommodate this. Anusha Srivatsa (4): drm/i915/display: Add CDCLK actions to intel_cdclk_state drm/i915/squash: s/intel_cdclk_can_squash/intel_cdclk_squash drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl drm/i915/display: Add cdclk checks to atomic check drivers/gpu/drm/i915/display/intel_cdclk.c | 150 + drivers/gpu/drm/i915/display/intel_cdclk.h | 13 ++ 2 files changed, 108 insertions(+), 55 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH v3 11/15] drm/i915/huc: track delayed HuC load with a fence
Given that HuC load is delayed on DG2, this patch adds support for a fence
that can be used to wait for load completion. No waiters are added in this
patch (they're coming up in the next one), to keep the focus of the
patch on the tracking logic.
The full HuC loading flow on boot DG2 is as follows:
1) i915 exports the GSC as an aux device;
2) the mei-gsc driver is loaded on the aux device;
3) the mei-pxp component is loaded;
4) mei-pxp calls back into i915 and we load the HuC.
Between steps 1 and 2 there can be several seconds of gap, mainly due to
the kernel doing other work during the boot.
The resume flow is slightly different, because we don't need to
re-expose or re-probe the aux device, so we go directly to step 3 once
i915 and mei-gsc have completed their resume flow.
Here's an example of the boot timing, captured with some logs added to
i915:
[ 17.908307] [drm] adding GSC device
[ 17.915717] [drm] i915 probe done
[ 22.282917] [drm] mei-gsc bound
[ 22.938153] [drm] HuC authenticated
Also to note is that if something goes wrong during GSC HW init the
mei-gsc driver will still bind, but steps 3 and 4 will not happen.
The status tracking is done by registering a bus_notifier to receive a
callback when the mei-gsc driver binds, with a large enough timeout to
account for delays. Once mei-gsc is bound, we switch to a smaller
timeout to wait for the mei-pxp component to load.
The fence is signalled on HuC load complete or if anything goes wrong in
any of the tracking steps. Timeout are enforced via hrtimer callbacks.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/gt/intel_gsc.c| 22 ++-
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 198 +
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 19 +++
3 files changed, 236 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c
b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 162bea57fbb5..bc9db728cdc8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -154,8 +154,14 @@ static void gsc_destroy_one(struct drm_i915_private *i915,
struct intel_gsc_intf *intf = >intf[intf_id];
if (intf->adev) {
- auxiliary_device_delete(>adev->aux_dev);
- auxiliary_device_uninit(>adev->aux_dev);
+ struct auxiliary_device *aux_dev = >adev->aux_dev;
+
+ if (intf_id == 0)
+
intel_huc_unregister_gsc_notifier(_to_gt(gsc)->uc.huc,
+ aux_dev->dev.bus);
+
+ auxiliary_device_delete(aux_dev);
+ auxiliary_device_uninit(aux_dev);
intf->adev = NULL;
}
@@ -254,14 +260,24 @@ static void gsc_init_one(struct drm_i915_private *i915,
struct intel_gsc *gsc,
goto fail;
}
+ intf->adev = adev; /* needed by the notifier */
+
+ if (intf_id == 0)
+ intel_huc_register_gsc_notifier(_to_gt(gsc)->uc.huc,
+ aux_dev->dev.bus);
+
ret = auxiliary_device_add(aux_dev);
if (ret < 0) {
drm_err(>drm, "gsc aux add failed %d\n", ret);
+ if (intf_id == 0)
+
intel_huc_unregister_gsc_notifier(_to_gt(gsc)->uc.huc,
+ aux_dev->dev.bus);
+ intf->adev = NULL;
+
/* adev will be freed with the put_device() and .release
sequence */
auxiliary_device_uninit(aux_dev);
goto fail;
}
- intf->adev = adev;
return;
fail:
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 40217fb69824..9a97b8cc90c7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -10,6 +10,8 @@
#include "intel_huc.h"
#include "i915_drv.h"
+#include
+
/**
* DOC: HuC
*
@@ -42,6 +44,164 @@
* HuC-specific commands.
*/
+/*
+ * MEI-GSC load is an async process. The probing of the exposed aux device
+ * (see intel_gsc.c) usually happens a few seconds after i915 probe, depending
+ * on when the kernel schedules it. Unless something goes terribly wrong, we're
+ * guaranteed for this to happen during boot, so the big timeout is a safety
net
+ * that we never expect to need.
+ * MEI-PXP + HuC load usually takes ~300ms, but if the GSC needs to be resumed
+ * and/or reset, this can take longer.
+ */
+#define GSC_INIT_TIMEOUT_MS 1
+#define PXP_INIT_TIMEOUT_MS 2000
+
+static int sw_fence_dummy_notify(struct i915_sw_fence *sf,
+enum i915_sw_fence_notify state)
+{
+ return NOTIFY_DONE;
+}
+
+static void __delayed_huc_load_complete(struct intel_huc *huc)
+{
+ if (!i915_sw_fence_done(>delayed_load.fence))
+ i915_sw_fence_complete(>delayed_load.fence);
+}
+
+static void
[Intel-gfx] [PATCH v3 10/15] drm/i915/dg2: setup HuC loading via GSC
The GSC will perform both the load and teh authentication, so we just
need to check the auth bit after the GSC has replied.
Since we require the PXP module to load the HuC, the earliest we can
trigger the load is during the pxp_bind operation.
Note that GSC-loaded HuC survives GT reset, so we need to just mark it
as ready when we re-init the GT HW.
v2: move setting of HuC fw error state to the failure path of the HuC
auth function, so it covers both the legacy and new auth flows
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Reviewed-by: Alan Previn #v1
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 41 +++
drivers/gpu/drm/i915/gt/uc/intel_huc.h| 2 ++
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 34 +++
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 14 +++-
5 files changed, 77 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 3bb8838e325a..40217fb69824 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -125,6 +125,28 @@ void intel_huc_fini(struct intel_huc *huc)
intel_uc_fw_fini(>fw);
}
+int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
+{
+ struct intel_gt *gt = huc_to_gt(huc);
+ int ret;
+
+ ret = __intel_wait_for_register(gt->uncore,
+ huc->status.reg,
+ huc->status.mask,
+ huc->status.value,
+ 2, 50, NULL);
+
+ if (ret) {
+ drm_err(>i915->drm,"HuC: Firmware not verified %d\n", ret);
+ intel_uc_fw_change_status(>fw,
INTEL_UC_FIRMWARE_LOAD_FAIL);
+ return ret;
+ }
+
+ intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_RUNNING);
+ drm_info(>i915->drm, "HuC authenticated\n");
+ return 0;
+}
+
/**
* intel_huc_auth() - Authenticate HuC uCode
* @huc: intel_huc structure
@@ -161,27 +183,18 @@ int intel_huc_auth(struct intel_huc *huc)
}
/* Check authentication status, it should be done by now */
- ret = __intel_wait_for_register(gt->uncore,
- huc->status.reg,
- huc->status.mask,
- huc->status.value,
- 2, 50, NULL);
- if (ret) {
- DRM_ERROR("HuC: Firmware not verified %d\n", ret);
+ ret = intel_huc_wait_for_auth_complete(huc);
+ if (ret)
goto fail;
- }
- intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_RUNNING);
- drm_info(>i915->drm, "HuC authenticated\n");
return 0;
fail:
i915_probe_error(gt->i915, "HuC: Authentication failed %d\n", ret);
- intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
return ret;
}
-static bool huc_is_authenticated(struct intel_huc *huc)
+bool intel_huc_is_authenticated(struct intel_huc *huc)
{
struct intel_gt *gt = huc_to_gt(huc);
intel_wakeref_t wakeref;
@@ -223,7 +236,7 @@ int intel_huc_check_status(struct intel_huc *huc)
break;
}
- return huc_is_authenticated(huc);
+ return intel_huc_is_authenticated(huc);
}
void intel_huc_update_auth_status(struct intel_huc *huc)
@@ -231,7 +244,7 @@ void intel_huc_update_auth_status(struct intel_huc *huc)
if (!intel_uc_fw_is_loadable(>fw))
return;
- if (huc_is_authenticated(huc))
+ if (intel_huc_is_authenticated(huc))
intel_uc_fw_change_status(>fw,
INTEL_UC_FIRMWARE_RUNNING);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index d7e25b6e879e..51f9d96a3ca3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -26,8 +26,10 @@ void intel_huc_init_early(struct intel_huc *huc);
int intel_huc_init(struct intel_huc *huc);
void intel_huc_fini(struct intel_huc *huc);
int intel_huc_auth(struct intel_huc *huc);
+int intel_huc_wait_for_auth_complete(struct intel_huc *huc);
int intel_huc_check_status(struct intel_huc *huc);
void intel_huc_update_auth_status(struct intel_huc *huc);
+bool intel_huc_is_authenticated(struct intel_huc *huc);
static inline int intel_huc_sanitize(struct intel_huc *huc)
{
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 9d6ab1e01639..4f246416db17 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -3,9 +3,43 @@
* Copyright © 2014-2019 Intel Corporation
*/
+#include "gt/intel_gsc.h"
#include "gt/intel_gt.h"
+#include "intel_huc.h"
#include
[Intel-gfx] [PATCH v3 15/15] HAX: drm/i915: force INTEL_MEI_GSC and INTEL_MEI_PXP on for CI
Both are required for HuC loading. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Kconfig.debug | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index e7fd3e76f8a2..a6576ffbc4dc 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -48,6 +48,8 @@ config DRM_I915_DEBUG select DRM_I915_DEBUG_RUNTIME_PM select DRM_I915_SW_FENCE_DEBUG_OBJECTS select DRM_I915_SELFTEST + select INTEL_MEI_GSC + select INTEL_MEI_PXP select BROKEN # for prototype uAPI default n help -- 2.37.2
[Intel-gfx] [PATCH v3 14/15] drm/i915/huc: define gsc-compatible HuC fw for DG2
The fw name is different and we need to record the fact that the blob is
gsc-loaded, so add a new macro to help.
Note: A-step DG2 G10 does not support HuC loading via GSC and would
require a separate firmware to be loaded the legacy way, but that's
not a production stepping so we're not going to bother.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Tony Ye
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 64 ++--
1 file changed, 37 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index cec6bf6bad3f..776b43d79772 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -74,35 +74,39 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
fw_def(ALDERLAKE_P, 0, guc_def(adlp, 69, 0, 3)) \
fw_def(ALDERLAKE_S, 0, guc_def(tgl, 69, 0, 3))
-#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \
- fw_def(ALDERLAKE_P, 0, huc_def(tgl, 7, 9, 3)) \
- fw_def(ALDERLAKE_S, 0, huc_def(tgl, 7, 9, 3)) \
- fw_def(DG1, 0, huc_def(dg1, 7, 9, 3)) \
- fw_def(ROCKETLAKE, 0, huc_def(tgl, 7, 9, 3)) \
- fw_def(TIGERLAKE,0, huc_def(tgl, 7, 9, 3)) \
- fw_def(JASPERLAKE, 0, huc_def(ehl, 9, 0, 0)) \
- fw_def(ELKHARTLAKE, 0, huc_def(ehl, 9, 0, 0)) \
- fw_def(ICELAKE, 0, huc_def(icl, 9, 0, 0)) \
- fw_def(COMETLAKE,5, huc_def(cml, 4, 0, 0)) \
- fw_def(COMETLAKE,0, huc_def(kbl, 4, 0, 0)) \
- fw_def(COFFEELAKE, 0, huc_def(kbl, 4, 0, 0)) \
- fw_def(GEMINILAKE, 0, huc_def(glk, 4, 0, 0)) \
- fw_def(KABYLAKE, 0, huc_def(kbl, 4, 0, 0)) \
- fw_def(BROXTON, 0, huc_def(bxt, 2, 0, 0)) \
- fw_def(SKYLAKE, 0, huc_def(skl, 2, 0, 0))
-
-#define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \
+#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_dma_def, huc_gsc_def) \
+ fw_def(DG2, 0, huc_gsc_def(dg2, 7, 10, 0)) \
+ fw_def(ALDERLAKE_P, 0, huc_dma_def(tgl, 7, 9, 3)) \
+ fw_def(ALDERLAKE_S, 0, huc_dma_def(tgl, 7, 9, 3)) \
+ fw_def(DG1, 0, huc_dma_def(dg1, 7, 9, 3)) \
+ fw_def(ROCKETLAKE, 0, huc_dma_def(tgl, 7, 9, 3)) \
+ fw_def(TIGERLAKE,0, huc_dma_def(tgl, 7, 9, 3)) \
+ fw_def(JASPERLAKE, 0, huc_dma_def(ehl, 9, 0, 0)) \
+ fw_def(ELKHARTLAKE, 0, huc_dma_def(ehl, 9, 0, 0)) \
+ fw_def(ICELAKE, 0, huc_dma_def(icl, 9, 0, 0)) \
+ fw_def(COMETLAKE,5, huc_dma_def(cml, 4, 0, 0)) \
+ fw_def(COMETLAKE,0, huc_dma_def(kbl, 4, 0, 0)) \
+ fw_def(COFFEELAKE, 0, huc_dma_def(kbl, 4, 0, 0)) \
+ fw_def(GEMINILAKE, 0, huc_dma_def(glk, 4, 0, 0)) \
+ fw_def(KABYLAKE, 0, huc_dma_def(kbl, 4, 0, 0)) \
+ fw_def(BROXTON, 0, huc_dma_def(bxt, 2, 0, 0)) \
+ fw_def(SKYLAKE, 0, huc_dma_def(skl, 2, 0, 0))
+
+#define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_, postfix_) \
"i915/" \
__stringify(prefix_) name_ \
__stringify(major_) "." \
__stringify(minor_) "." \
- __stringify(patch_) ".bin"
+ __stringify(patch_) postfix_ ".bin"
#define MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_) \
- __MAKE_UC_FW_PATH(prefix_, "_guc_", major_, minor_, patch_)
+ __MAKE_UC_FW_PATH(prefix_, "_guc_", major_, minor_, patch_, "")
#define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \
- __MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_)
+ __MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_, "")
+
+#define MAKE_HUC_GSC_FW_PATH(prefix_, major_, minor_, bld_num_) \
+ __MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_, "_gsc")
/* All blobs need to be declared via MODULE_FIRMWARE() */
#define INTEL_UC_MODULE_FW(platform_, revid_, uc_) \
@@ -110,26 +114,31 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
INTEL_GUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH)
INTEL_GUC_FIRMWARE_DEFS_FALLBACK(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH)
-INTEL_HUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_HUC_FW_PATH)
+INTEL_HUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_HUC_FW_PATH,
MAKE_HUC_GSC_FW_PATH)
/* The below structs and macros are used to iterate across the list of blobs */
struct __packed uc_fw_blob {
u8 major;
u8 minor;
+ bool loaded_via_gsc;
const char *path;
};
-#define UC_FW_BLOB(major_, minor_, path_) \
- { .major = major_, .minor = minor_, .path = path_ }
+#define UC_FW_BLOB(major_, minor_, gsc_, path_) \
+ { .major = major_, .minor = minor_, .loaded_via_gsc = gsc_, .path =
path_ }
#define GUC_FW_BLOB(prefix_, major_, minor_, patch_) \
- UC_FW_BLOB(major_, minor_, \
+ UC_FW_BLOB(major_, minor_, false, \
MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_))
#define
[Intel-gfx] [PATCH v3 01/15] HAX: mei: GSC support for XeHP SDV and DG2 platform
This is a squash of the GSC support for XeHP SDV and DG2 series, which
is being reviewed separately at:
https://patchwork.freedesktop.org/series/106638/
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 118 +---
drivers/gpu/drm/i915/gt/intel_gsc.h | 3 +
drivers/misc/mei/bus-fixup.c| 104
drivers/misc/mei/client.c | 14 ++--
drivers/misc/mei/debugfs.c | 17
drivers/misc/mei/gsc-me.c | 77 +++---
drivers/misc/mei/hbm.c | 12 +--
drivers/misc/mei/hw-me-regs.h | 7 ++
drivers/misc/mei/hw-me.c| 116 ++-
drivers/misc/mei/hw-me.h| 14 +++-
drivers/misc/mei/hw-txe.c | 2 +-
drivers/misc/mei/hw.h | 5 ++
drivers/misc/mei/init.c | 21 -
drivers/misc/mei/main.c | 2 +-
drivers/misc/mei/mei_dev.h | 26 ++
drivers/misc/mei/mkhi.h | 57 ++
drivers/misc/mei/pci-me.c | 2 +-
include/linux/mei_aux.h | 12 +++
18 files changed, 518 insertions(+), 91 deletions(-)
create mode 100644 drivers/misc/mei/mkhi.h
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c
b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 0e494028b81d..162bea57fbb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -7,6 +7,7 @@
#include
#include "i915_drv.h"
#include "i915_reg.h"
+#include "gem/i915_gem_region.h"
#include "gt/intel_gsc.h"
#include "gt/intel_gt.h"
@@ -36,10 +37,68 @@ static int gsc_irq_init(int irq)
return irq_set_chip_data(irq, NULL);
}
+static int
+gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_t
size)
+{
+ struct intel_gt *gt = gsc_to_gt(gsc);
+ struct drm_i915_gem_object *obj;
+ void *vaddr;
+ int err;
+
+ obj = i915_gem_object_create_lmem(gt->i915, size,
I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ drm_err(>i915->drm, "Failed to allocate gsc memory\n");
+ return PTR_ERR(obj);
+ }
+
+ err = i915_gem_object_pin_pages_unlocked(obj);
+ if (err) {
+ drm_err(>i915->drm, "Failed to pin pages for gsc memory\n");
+ goto out_put;
+ }
+
+ vaddr = i915_gem_object_pin_map_unlocked(obj,
i915_coherent_map_type(gt->i915, obj, true));
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ drm_err(>i915->drm, "Failed to map gsc memory\n");
+ goto out_unpin;
+ }
+
+ memset(vaddr, 0, obj->base.size);
+
+ i915_gem_object_unpin_map(obj);
+
+ intf->gem_obj = obj;
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+ return err;
+}
+
+static void gsc_ext_om_destroy(struct intel_gsc_intf *intf)
+{
+ struct drm_i915_gem_object *obj = fetch_and_zero(>gem_obj);
+
+ if (!obj)
+ return;
+
+ if (i915_gem_object_has_pinned_pages(obj))
+ i915_gem_object_unpin_pages(obj);
+
+ i915_gem_object_put(obj);
+}
+
struct gsc_def {
const char *name;
unsigned long bar;
size_t bar_size;
+ bool use_polling;
+ bool slow_firmware;
+ size_t lmem_size;
};
/* gsc resources and definitions (HECI1 and HECI2) */
@@ -54,11 +113,25 @@ static const struct gsc_def gsc_def_dg1[] = {
}
};
+static const struct gsc_def gsc_def_xehpsdv[] = {
+ {
+ /* HECI1 not enabled on the device. */
+ },
+ {
+ .name = "mei-gscfi",
+ .bar = DG1_GSC_HECI2_BASE,
+ .bar_size = GSC_BAR_LENGTH,
+ .use_polling = true,
+ .slow_firmware = true,
+ }
+};
+
static const struct gsc_def gsc_def_dg2[] = {
{
.name = "mei-gsc",
.bar = DG2_GSC_HECI1_BASE,
.bar_size = GSC_BAR_LENGTH,
+ .lmem_size = SZ_4M,
},
{
.name = "mei-gscfi",
@@ -75,26 +148,32 @@ static void gsc_release_dev(struct device *dev)
kfree(adev);
}
-static void gsc_destroy_one(struct intel_gsc_intf *intf)
+static void gsc_destroy_one(struct drm_i915_private *i915,
+ struct intel_gsc *gsc, unsigned int intf_id)
{
+ struct intel_gsc_intf *intf = >intf[intf_id];
+
if (intf->adev) {
auxiliary_device_delete(>adev->aux_dev);
auxiliary_device_uninit(>adev->aux_dev);
intf->adev = NULL;
}
+
if (intf->irq >= 0)
irq_free_desc(intf->irq);
intf->irq = -1;
+
+ gsc_ext_om_destroy(intf);
}
-static void gsc_init_one(struct drm_i915_private *i915,
-struct intel_gsc_intf *intf,
+static void gsc_init_one(struct
[Intel-gfx] [PATCH v3 13/15] drm/i915/huc: better define HuC status getparam possible return values.
The current HuC status getparam return values are a bit confusing in
regards to what happens in some scenarios. In particular, most of the
error cases cause the ioctl to return an error, but a couple of them,
INIT_FAIL and LOAD_FAIL, are not explicitly handled and neither is
their expected return value documented; these 2 error cases therefore
end up into the catch-all umbrella of the "HuC not loaded" case, with
this case therefore including both some error scenarios and the load
in progress one.
The updates included in this patch change the handling so that all
error cases behave the same way, i.e. return an errno code, and so
that the HuC load in progress case is unambiguous.
The patch also includes a small change to the FW init path to make sure
we always transition to an error state if something goes wrong.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Tony Ye
Acked-by: Tvrtko Ursulin
Acked-by: Tony Ye
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 14 +++---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 -
include/uapi/drm/i915_drm.h | 16
4 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 01f2705cb94a..10b2da810a8f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -443,6 +443,7 @@ int intel_guc_init(struct intel_guc *guc)
err_fw:
intel_uc_fw_fini(>fw);
out:
+ intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_INIT_FAIL);
i915_probe_error(gt->i915, "failed with %d\n", ret);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 9a97b8cc90c7..1a34c902d081 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -284,6 +284,7 @@ int intel_huc_init(struct intel_huc *huc)
return 0;
out:
+ intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_INIT_FAIL);
drm_info(>drm, "HuC init failed with %d\n", err);
return err;
}
@@ -403,13 +404,8 @@ bool intel_huc_is_authenticated(struct intel_huc *huc)
* This function reads status register to verify if HuC
* firmware was successfully loaded.
*
- * Returns:
- * * -ENODEV if HuC is not present on this platform,
- * * -EOPNOTSUPP if HuC firmware is disabled,
- * * -ENOPKG if HuC firmware was not installed,
- * * -ENOEXEC if HuC firmware is invalid or mismatched,
- * * 0 if HuC firmware is not running,
- * * 1 if HuC firmware is authenticated and running.
+ * The return values match what is expected for the I915_PARAM_HUC_STATUS
+ * getparam.
*/
int intel_huc_check_status(struct intel_huc *huc)
{
@@ -422,6 +418,10 @@ int intel_huc_check_status(struct intel_huc *huc)
return -ENOPKG;
case INTEL_UC_FIRMWARE_ERROR:
return -ENOEXEC;
+ case INTEL_UC_FIRMWARE_INIT_FAIL:
+ return -ENOMEM;
+ case INTEL_UC_FIRMWARE_LOAD_FAIL:
+ return -EIO;
default:
break;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 58547292efa0..cec6bf6bad3f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -749,7 +749,6 @@ int intel_uc_fw_init(struct intel_uc_fw *uc_fw)
out_unpin:
i915_gem_object_unpin_pages(uc_fw->obj);
out:
- intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_INIT_FAIL);
return err;
}
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 520ad2691a99..629198f1d8d8 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -645,6 +645,22 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
+/*
+ * Query the status of HuC load.
+ *
+ * The query can fail in the following scenarios with the listed error codes:
+ * -ENODEV if HuC is not present on this platform,
+ * -EOPNOTSUPP if HuC firmware usage is disabled,
+ * -ENOPKG if HuC firmware fetch failed,
+ * -ENOEXEC if HuC firmware is invalid or mismatched,
+ * -ENOMEM if i915 failed to prepare the FW objects for transfer to the uC,
+ * -EIO if the FW transfer or the FW authentication failed.
+ *
+ * If the IOCTL is successful, the returned parameter will be set to one of the
+ * following values:
+ * * 0 if HuC firmware load is not complete,
+ * * 1 if HuC firmware is authenticated and running.
+ */
#define I915_PARAM_HUC_STATUS 42
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
--
2.37.2
[Intel-gfx] [PATCH v3 08/15] drm/i915/pxp: implement function for sending tee stream command
From: Vitaly Lubart
Command to be sent via the stream interface are written to a local
memory page, whose address is then provided to the GSC.
The interface supports providing a full sg with multiple pages for both
input and output messages, but since for now we only aim to support short
and synchronous messages we can use a single page for both input and
output.
Note that the mei interface expects an sg of 4k pages, while our lmem pages
are 64k. If we ever need to support more than 4k we'll need to convert.
Added a TODO comment to the code to record this.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Cc: Alan Previn
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 114 -
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 6 ++
3 files changed, 124 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 2c1fc49ecec1..e0d09455a92e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -7,6 +7,7 @@
#include
#include
+#include "gem/i915_gem_region.h"
#include "i915_drv.h"
#include "intel_pxp.h"
@@ -69,6 +70,47 @@ static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
return ret;
}
+int intel_pxp_tee_stream_message(struct intel_pxp *pxp,
+u8 client_id, u32 fence_id,
+void *msg_in, size_t msg_in_len,
+void *msg_out, size_t msg_out_len)
+{
+ /* TODO: for bigger objects we need to use a sg of 4k pages */
+ const size_t max_msg_size = PAGE_SIZE;
+ struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+ struct i915_pxp_component *pxp_component = pxp->pxp_component;
+ unsigned int offset = 0;
+ struct scatterlist *sg;
+ int ret;
+
+ if (msg_in_len > max_msg_size || msg_out_len > max_msg_size)
+ return -ENOSPC;
+
+ mutex_lock(>tee_mutex);
+
+ if (unlikely(!pxp_component || !pxp_component->ops->gsc_command)) {
+ ret = -ENODEV;
+ goto unlock;
+ }
+
+ GEM_BUG_ON(!pxp->stream_cmd.obj);
+
+ sg = i915_gem_object_get_sg_dma(pxp->stream_cmd.obj, 0, );
+
+ memcpy(pxp->stream_cmd.vaddr, msg_in, msg_in_len);
+
+ ret = pxp_component->ops->gsc_command(pxp_component->tee_dev, client_id,
+ fence_id, sg, msg_in_len, sg);
+ if (ret < 0)
+ drm_err(>drm, "Failed to send PXP TEE gsc command\n");
+ else
+ memcpy(msg_out, pxp->stream_cmd.vaddr, msg_out_len);
+
+unlock:
+ mutex_unlock(>tee_mutex);
+ return ret;
+}
+
/**
* i915_pxp_tee_component_bind - bind function to pass the function pointers
to pxp_tee
* @i915_kdev: pointer to i915 kernel device
@@ -126,6 +168,66 @@ static const struct component_ops
i915_pxp_tee_component_ops = {
.unbind = i915_pxp_tee_component_unbind,
};
+static int alloc_streaming_command(struct intel_pxp *pxp)
+{
+ struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+ struct drm_i915_gem_object *obj = NULL;
+ void *cmd;
+ int err;
+
+ pxp->stream_cmd.obj = NULL;
+ pxp->stream_cmd.vaddr = NULL;
+
+ if (!IS_DGFX(i915))
+ return 0;
+
+ /* allocate lmem object of one page for PXP command memory and store it
*/
+ obj = i915_gem_object_create_lmem(i915, PAGE_SIZE,
I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ drm_err(>drm, "Failed to allocate pxp streaming
command!\n");
+ return PTR_ERR(obj);
+ }
+
+ err = i915_gem_object_pin_pages_unlocked(obj);
+ if (err) {
+ drm_err(>drm, "Failed to pin gsc message page!\n");
+ goto out_put;
+ }
+
+ /* map the lmem into the virtual memory pointer */
+ cmd = i915_gem_object_pin_map_unlocked(obj,
i915_coherent_map_type(i915, obj, true));
+ if (IS_ERR(cmd)) {
+ drm_err(>drm, "Failed to map gsc message page!\n");
+ err = PTR_ERR(cmd);
+ goto out_unpin;
+ }
+
+ memset(cmd, 0, obj->base.size);
+
+ pxp->stream_cmd.obj = obj;
+ pxp->stream_cmd.vaddr = cmd;
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+ return err;
+}
+
+static void free_streaming_command(struct intel_pxp *pxp)
+{
+ struct drm_i915_gem_object *obj = fetch_and_zero(>stream_cmd.obj);
+
+ if (!obj)
+ return;
+
+ i915_gem_object_unpin_map(obj);
+ i915_gem_object_unpin_pages(obj);
+ i915_gem_object_put(obj);
+}
+
int intel_pxp_tee_component_init(struct intel_pxp *pxp)
{
int ret;
@@ -134,16 +236,24 @@ int
[Intel-gfx] [PATCH v3 12/15] drm/i915/huc: stall media submission until HuC is loaded
Wait on the fence to be signalled to avoid the submissions finding HuC
not yet loaded.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Tony Ye
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 6 ++
drivers/gpu/drm/i915/i915_request.c| 24
2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index 49374f306a7f..209de60474a5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -77,6 +77,12 @@ static inline bool intel_huc_is_loaded_by_gsc(const struct
intel_huc *huc)
return huc->fw.loaded_via_gsc;
}
+static inline bool intel_huc_wait_required(struct intel_huc *huc)
+{
+ return intel_huc_is_used(huc) && intel_huc_is_loaded_by_gsc(huc) &&
+ !intel_huc_is_authenticated(huc);
+}
+
void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p);
#endif
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 62fad16a55e8..77f45a3cb01f 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1621,6 +1621,20 @@ i915_request_await_object(struct i915_request *to,
return ret;
}
+static void i915_request_await_huc(struct i915_request *rq)
+{
+ struct intel_huc *huc = >context->engine->gt->uc.huc;
+
+ /* don't stall kernel submissions! */
+ if (!rcu_access_pointer(rq->context->gem_context))
+ return;
+
+ if (intel_huc_wait_required(huc))
+ i915_sw_fence_await_sw_fence(>submit,
+>delayed_load.fence,
+>submitq);
+}
+
static struct i915_request *
__i915_request_ensure_parallel_ordering(struct i915_request *rq,
struct intel_timeline *timeline)
@@ -1702,6 +1716,16 @@ __i915_request_add_to_timeline(struct i915_request *rq)
struct intel_timeline *timeline = i915_request_timeline(rq);
struct i915_request *prev;
+ /*
+* Media workloads may require HuC, so stall them until HuC loading is
+* complete. Note that HuC not being loaded when a user submission
+* arrives can only happen when HuC is loaded via GSC and in that case
+* we still expect the window between us starting to accept submissions
+* and HuC loading completion to be small (a few hundred ms).
+*/
+ if (rq->engine->class == VIDEO_DECODE_CLASS)
+ i915_request_await_huc(rq);
+
/*
* Dependency tracking and request ordering along the timeline
* is special cased so that we can eliminate redundant ordering
--
2.37.2
[Intel-gfx] [PATCH v3 09/15] drm/i915/pxp: add huc authentication and loading command
From: Tomas Winkler
Add support for loading HuC via a pxp stream command.
Signed-off-by: Tomas Winkler
Signed-off-by: Vitaly Lubart
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp_huc.c | 69 +++
drivers/gpu/drm/i915/pxp/intel_pxp_huc.h | 15
.../drm/i915/pxp/intel_pxp_tee_interface.h| 21 ++
4 files changed, 107 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 589823ad62ed..5bee787d3c2a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -310,7 +310,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support. Base support is required for HuC
i915-y += \
pxp/intel_pxp.o \
- pxp/intel_pxp_tee.o
+ pxp/intel_pxp_tee.o \
+ pxp/intel_pxp_huc.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_cmd.o \
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
new file mode 100644
index ..6d25f436f329
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2021, Intel Corporation. All rights reserved.
+ */
+
+#include "drm/i915_drm.h"
+#include "i915_drv.h"
+
+#include "gem/i915_gem_region.h"
+#include "gt/intel_gt.h"
+
+#include "intel_pxp.h"
+#include "intel_pxp_huc.h"
+#include "intel_pxp_tee.h"
+#include "intel_pxp_types.h"
+#include "intel_pxp_tee_interface.h"
+
+int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ struct intel_huc *huc = >uc.huc;
+ struct pxp_tee_start_huc_auth_in huc_in = {0};
+ struct pxp_tee_start_huc_auth_out huc_out = {0};
+ dma_addr_t huc_phys_addr;
+ u8 client_id = 0;
+ u8 fence_id = 0;
+ int err;
+
+ if (!pxp->pxp_component)
+ return -ENODEV;
+
+ huc_phys_addr = i915_gem_object_get_dma_address(huc->fw.obj, 0);
+
+ /* write the PXP message into the lmem (the sg list) */
+ huc_in.header.api_version = PXP_TEE_43_APIVER;
+ huc_in.header.command_id = PXP_TEE_43_START_HUC_AUTH;
+ huc_in.header.status = 0;
+ huc_in.header.buffer_len = sizeof(huc_in.huc_base_address);
+ huc_in.huc_base_address = huc_phys_addr;
+
+ err = intel_pxp_tee_stream_message(pxp, client_id, fence_id,
+ _in, sizeof(huc_in),
+ _out, sizeof(huc_out));
+ if (err < 0) {
+ drm_err(>i915->drm,
+ "Failed to send HuC load and auth command to GSC
[%d]!\n",
+ err);
+ return err;
+ }
+
+ /*
+* HuC does sometimes survive suspend/resume (it depends on how "deep"
+* a sleep state the device reaches) so we can end up here on resume
+* with HuC already loaded, in which case the GSC will return
+* PXP_STATUS_OP_NOT_PERMITTED. We can therefore consider the GuC
+* correctly transferred in this scenario; if the same error is ever
+* returned with HuC not loaded we'll still catch it when we check the
+* authentication bit later.
+*/
+ if (huc_out.header.status != PXP_STATUS_SUCCESS &&
+ huc_out.header.status != PXP_STATUS_OP_NOT_PERMITTED) {
+ drm_err(>i915->drm,
+ "HuC load failed with GSC error = 0x%x\n",
+ huc_out.header.status);
+ return -EPROTO;
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
new file mode 100644
index ..6cf2d00548c0
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2021, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_HUC_H__
+#define __INTEL_PXP_HUC_H__
+
+#include
+
+struct intel_pxp;
+
+int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_HUC_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
index 36e9b0868f5c..1de98959a89d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
@@ -9,8 +9,20 @@
#include
#define PXP_TEE_APIVER 0x40002
+#define PXP_TEE_43_APIVER 0x00040003
#define PXP_TEE_ARB_CMDID 0x1e
#define PXP_TEE_ARB_PROTECTION_MODE 0x2
+#define PXP_TEE_43_START_HUC_AUTH 0x003A
+
+/*
+ * there are a lot of status codes for PXP, but we only define the ones we
+ * actually can handle in the
[Intel-gfx] [PATCH v3 05/15] mei: pxp: add command streamer API to the PXP driver
From: Vitaly Lubart
The discrete graphics card with GSC firmware
using command streamer API hence it requires to enhance
pxp module with the new gsc_command() handler.
The handler is implemented via mei_pxp_gsc_command() which is
just just a thin wrapper around mei_cldev_send_gsc_command()
V2:
1. More detailed commit message
2. Fix typo in the comments
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Greg Kroah-Hartman
Reviewed-by: Alan Previn
---
drivers/misc/mei/pxp/mei_pxp.c | 28
include/drm/i915_pxp_tee_interface.h | 5 +
2 files changed, 33 insertions(+)
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
index 5c39457e3f53..17c5d201603f 100644
--- a/drivers/misc/mei/pxp/mei_pxp.c
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -77,10 +77,38 @@ mei_pxp_receive_message(struct device *dev, void *buffer,
size_t size)
return byte;
}
+/**
+ * mei_pxp_gsc_command() - sends a gsc command, by sending
+ * a sgl mei message to gsc and receiving reply from gsc
+ *
+ * @dev: device corresponding to the mei_cl_device
+ * @client_id: client id to send the command to
+ * @fence_id: fence id to send the command to
+ * @sg_in: scatter gather list containing addresses for rx message buffer
+ * @total_in_len: total length of data in 'in' sg, can be less than the sum of
buffers sizes
+ * @sg_out: scatter gather list containing addresses for tx message buffer
+ *
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static ssize_t mei_pxp_gsc_command(struct device *dev, u8 client_id, u32
fence_id,
+ struct scatterlist *sg_in, size_t
total_in_len,
+ struct scatterlist *sg_out)
+{
+ struct mei_cl_device *cldev;
+
+ if (!dev || !sg_in || !sg_out)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ return mei_cldev_send_gsc_command(cldev, client_id, fence_id, sg_in,
total_in_len, sg_out);
+}
+
static const struct i915_pxp_component_ops mei_pxp_ops = {
.owner = THIS_MODULE,
.send = mei_pxp_send_message,
.recv = mei_pxp_receive_message,
+ .gsc_command = mei_pxp_gsc_command,
};
static int mei_component_master_bind(struct device *dev)
diff --git a/include/drm/i915_pxp_tee_interface.h
b/include/drm/i915_pxp_tee_interface.h
index af593ec64469..67d44a1827f9 100644
--- a/include/drm/i915_pxp_tee_interface.h
+++ b/include/drm/i915_pxp_tee_interface.h
@@ -8,6 +8,7 @@
#include
#include
+#include
/**
* struct i915_pxp_component_ops - ops for PXP services.
@@ -23,6 +24,10 @@ struct i915_pxp_component_ops {
int (*send)(struct device *dev, const void *message, size_t size);
int (*recv)(struct device *dev, void *buffer, size_t size);
+ ssize_t (*gsc_command)(struct device *dev, u8 client_id, u32 fence_id,
+ struct scatterlist *sg_in, size_t total_in_len,
+ struct scatterlist *sg_out);
+
};
/**
--
2.37.2
[Intel-gfx] [PATCH v3 06/15] mei: pxp: support matching with a gfx discrete card
From: Tomas Winkler
With on-boards graphics card, both i915 and MEI
are in the same device hierarchy with the same parent,
while for discrete gfx card the MEI is its child device.
Adjust the match function for that scenario
by matching MEI parent device with i915.
V2:
1. More detailed commit message
2. Check for dev is not null before it is accessed.
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Vitaly Lubart
Cc: Greg Kroah-Hartman
Reviewed-by: Alan Previn
---
drivers/misc/mei/pxp/mei_pxp.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
index 17c5d201603f..afc047627800 100644
--- a/drivers/misc/mei/pxp/mei_pxp.c
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -159,17 +159,24 @@ static int mei_pxp_component_match(struct device *dev,
int subcomponent,
{
struct device *base = data;
+ if (!dev)
+ return 0;
+
if (!dev->driver || strcmp(dev->driver->name, "i915") ||
subcomponent != I915_COMPONENT_PXP)
return 0;
base = base->parent;
- if (!base)
+ if (!base) /* mei device */
return 0;
- base = base->parent;
- dev = dev->parent;
+ base = base->parent; /* pci device */
+ /* for dgfx */
+ if (base && dev == base)
+ return 1;
+ /* for pch */
+ dev = dev->parent;
return (base && dev && dev == base);
}
--
2.37.2
[Intel-gfx] [PATCH v3 07/15] drm/i915/pxp: load the pxp module when we have a gsc-loaded huc
The mei_pxp module is required to send the command to load authenticate
the HuC to the GSC even if pxp is not in use for protected content
management.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile| 10 +++---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 32 +---
drivers/gpu/drm/i915/pxp/intel_pxp.h | 32
drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 8 +
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 8 -
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 11 +--
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 10 --
7 files changed, 57 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 522ef9b4aff3..589823ad62ed 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -307,15 +307,17 @@ i915-y += \
i915-y += i915_perf.o
-# Protected execution platform (PXP) support
-i915-$(CONFIG_DRM_I915_PXP) += \
+# Protected execution platform (PXP) support. Base support is required for HuC
+i915-y += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_tee.o
+
+i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_debugfs.o \
pxp/intel_pxp_irq.o \
pxp/intel_pxp_pm.o \
- pxp/intel_pxp_session.o \
- pxp/intel_pxp_tee.o
+ pxp/intel_pxp_session.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 15311eaed848..b602a51c3692 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -103,19 +103,15 @@ static int create_vcs_context(struct intel_pxp *pxp)
static void destroy_vcs_context(struct intel_pxp *pxp)
{
- intel_engine_destroy_pinned_context(fetch_and_zero(>ce));
+ if (pxp->ce)
+ intel_engine_destroy_pinned_context(fetch_and_zero(>ce));
}
-void intel_pxp_init(struct intel_pxp *pxp)
+static void pxp_init_full(struct intel_pxp *pxp)
{
struct intel_gt *gt = pxp_to_gt(pxp);
int ret;
- if (!HAS_PXP(gt->i915))
- return;
-
- mutex_init(>tee_mutex);
-
/*
* we'll use the completion to check if there is a termination pending,
* so we start it as completed and we reinit it when a termination
@@ -124,8 +120,7 @@ void intel_pxp_init(struct intel_pxp *pxp)
init_completion(>termination);
complete_all(>termination);
- mutex_init(>arb_mutex);
- INIT_WORK(>session_work, intel_pxp_session_work);
+ intel_pxp_session_management_init(pxp);
ret = create_vcs_context(pxp);
if (ret)
@@ -143,11 +138,26 @@ void intel_pxp_init(struct intel_pxp *pxp)
destroy_vcs_context(pxp);
}
-void intel_pxp_fini(struct intel_pxp *pxp)
+void intel_pxp_init(struct intel_pxp *pxp)
{
- if (!intel_pxp_is_enabled(pxp))
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
+ /* we rely on the mei PXP module */
+ if (!IS_ENABLED(CONFIG_INTEL_MEI_PXP))
return;
+ /*
+* If HuC is loaded by GSC but PXP is disabled, we can skip the init of
+* the full PXP session/object management and just init the tee channel.
+*/
+ if (HAS_PXP(gt->i915))
+ pxp_init_full(pxp);
+ else if (intel_huc_is_loaded_by_gsc(>uc.huc) &&
intel_uc_uses_huc(>uc))
+ intel_pxp_tee_component_init(pxp);
+}
+
+void intel_pxp_fini(struct intel_pxp *pxp)
+{
pxp->arb_is_valid = false;
intel_pxp_tee_component_fini(pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 73847e535cab..2da309088c6d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -12,7 +12,6 @@
struct intel_pxp;
struct drm_i915_gem_object;
-#ifdef CONFIG_DRM_I915_PXP
struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp);
bool intel_pxp_is_enabled(const struct intel_pxp *pxp);
bool intel_pxp_is_active(const struct intel_pxp *pxp);
@@ -32,36 +31,5 @@ int intel_pxp_key_check(struct intel_pxp *pxp,
bool assign);
void intel_pxp_invalidate(struct intel_pxp *pxp);
-#else
-static inline void intel_pxp_init(struct intel_pxp *pxp)
-{
-}
-
-static inline void intel_pxp_fini(struct intel_pxp *pxp)
-{
-}
-
-static inline int intel_pxp_start(struct intel_pxp *pxp)
-{
- return -ENODEV;
-}
-
-static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
-{
- return false;
-}
-
-static inline bool intel_pxp_is_active(const struct intel_pxp *pxp)
-{
- return false;
-}
-
-static inline int intel_pxp_key_check(struct intel_pxp *pxp,
- struct drm_i915_gem_object *obj,
- bool
[Intel-gfx] [PATCH v3 03/15] mei: bus: enable sending gsc commands
From: Tomas Winkler
GSC command is and extended header containing a scatter gather
list and without a data buffer. Using MEI_CL_IO_SGL flag,
the caller send the GSC command as a data and the function internally
moves it to the extended header.
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Vitaly Lubart
Cc: Greg Kroah-Hartman
---
drivers/misc/mei/bus.c | 20 ++--
drivers/misc/mei/mei_dev.h | 4
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/mei/bus.c b/drivers/misc/mei/bus.c
index 46aa3554e97b..225f0b04c021 100644
--- a/drivers/misc/mei/bus.c
+++ b/drivers/misc/mei/bus.c
@@ -100,9 +100,18 @@ ssize_t __mei_cl_send(struct mei_cl *cl, const u8 *buf,
size_t length, u8 vtag,
cb->internal = !!(mode & MEI_CL_IO_TX_INTERNAL);
cb->blocking = !!(mode & MEI_CL_IO_TX_BLOCKING);
memcpy(cb->buf.data, buf, length);
+ /* hack we point data to header */
+ if (mode & MEI_CL_IO_SGL) {
+ cb->ext_hdr = (struct mei_ext_hdr *)cb->buf.data;
+ cb->buf.data = NULL;
+ cb->buf.size = 0;
+ }
rets = mei_cl_write(cl, cb);
+ if (mode & MEI_CL_IO_SGL && rets == 0)
+ rets = length;
+
out:
mutex_unlock(>device_lock);
@@ -205,9 +214,16 @@ ssize_t __mei_cl_recv(struct mei_cl *cl, u8 *buf, size_t
length, u8 *vtag,
goto free;
}
- r_length = min_t(size_t, length, cb->buf_idx);
- memcpy(buf, cb->buf.data, r_length);
+ /* for the GSC type - copy the extended header to the buffer */
+ if (cb->ext_hdr && cb->ext_hdr->type == MEI_EXT_HDR_GSC) {
+ r_length = min_t(size_t, length, cb->ext_hdr->length *
sizeof(u32));
+ memcpy(buf, cb->ext_hdr, r_length);
+ } else {
+ r_length = min_t(size_t, length, cb->buf_idx);
+ memcpy(buf, cb->buf.data, r_length);
+ }
rets = r_length;
+
if (vtag)
*vtag = cb->vtag;
diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h
index 862190b297aa..5e28294d5dca 100644
--- a/drivers/misc/mei/mei_dev.h
+++ b/drivers/misc/mei/mei_dev.h
@@ -109,12 +109,16 @@ enum mei_cb_file_ops {
* @MEI_CL_IO_TX_INTERNAL: internal communication between driver and FW
*
* @MEI_CL_IO_RX_NONBLOCK: recv is non-blocking
+ *
+ * @MEI_CL_IO_SGL: send command with sgl list.
*/
enum mei_cl_io_mode {
MEI_CL_IO_TX_BLOCKING = BIT(0),
MEI_CL_IO_TX_INTERNAL = BIT(1),
MEI_CL_IO_RX_NONBLOCK = BIT(2),
+
+ MEI_CL_IO_SGL = BIT(3),
};
/*
--
2.37.2
[Intel-gfx] [PATCH v3 02/15] mei: add support to GSC extended header
From: Tomas Winkler
GSC extend header is of variable size and data
is provided in a sgl list inside the header
and not in the data buffers, need to enable the path.
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Vitaly Lubart
Cc: Greg Kroah-Hartman
---
drivers/misc/mei/client.c| 55 --
drivers/misc/mei/hbm.c | 13
drivers/misc/mei/hw-me.c | 5 +++-
drivers/misc/mei/hw.h| 57
drivers/misc/mei/interrupt.c | 47 -
drivers/misc/mei/mei_dev.h | 3 ++
6 files changed, 157 insertions(+), 23 deletions(-)
diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c
index e7a16d9b2241..8860a708ed19 100644
--- a/drivers/misc/mei/client.c
+++ b/drivers/misc/mei/client.c
@@ -322,6 +322,7 @@ void mei_io_cb_free(struct mei_cl_cb *cb)
list_del(>list);
kfree(cb->buf.data);
+ kfree(cb->ext_hdr);
kfree(cb);
}
@@ -401,6 +402,7 @@ static struct mei_cl_cb *mei_io_cb_init(struct mei_cl *cl,
cb->buf_idx = 0;
cb->fop_type = type;
cb->vtag = 0;
+ cb->ext_hdr = NULL;
return cb;
}
@@ -1740,6 +1742,17 @@ static inline u8 mei_ext_hdr_set_vtag(void *ext, u8 vtag)
return vtag_hdr->hdr.length;
}
+static inline bool mei_ext_hdr_is_gsc(struct mei_ext_hdr *ext)
+{
+ return ext && ext->type == MEI_EXT_HDR_GSC;
+}
+
+static inline u8 mei_ext_hdr_set_gsc(struct mei_ext_hdr *ext, struct
mei_ext_hdr *gsc_hdr)
+{
+ memcpy(ext, gsc_hdr, mei_ext_hdr_len(gsc_hdr));
+ return ext->length;
+}
+
/**
* mei_msg_hdr_init - allocate and initialize mei message header
*
@@ -1752,14 +1765,17 @@ static struct mei_msg_hdr *mei_msg_hdr_init(const
struct mei_cl_cb *cb)
size_t hdr_len;
struct mei_ext_meta_hdr *meta;
struct mei_msg_hdr *mei_hdr;
- bool is_ext, is_vtag;
+ bool is_ext, is_hbm, is_gsc, is_vtag;
+ struct mei_ext_hdr *next_ext;
if (!cb)
return ERR_PTR(-EINVAL);
/* Extended header for vtag is attached only on the first fragment */
is_vtag = (cb->vtag && cb->buf_idx == 0);
- is_ext = is_vtag;
+ is_hbm = cb->cl->me_cl->client_id == 0;
+ is_gsc = ((!is_hbm) && cb->cl->dev->hbm_f_gsc_supported &&
mei_ext_hdr_is_gsc(cb->ext_hdr));
+ is_ext = is_vtag || is_gsc;
/* Compute extended header size */
hdr_len = sizeof(*mei_hdr);
@@ -1771,6 +1787,9 @@ static struct mei_msg_hdr *mei_msg_hdr_init(const struct
mei_cl_cb *cb)
if (is_vtag)
hdr_len += sizeof(struct mei_ext_hdr_vtag);
+ if (is_gsc)
+ hdr_len += mei_ext_hdr_len(cb->ext_hdr);
+
setup_hdr:
mei_hdr = kzalloc(hdr_len, GFP_KERNEL);
if (!mei_hdr)
@@ -1785,10 +1804,20 @@ static struct mei_msg_hdr *mei_msg_hdr_init(const
struct mei_cl_cb *cb)
goto out;
meta = (struct mei_ext_meta_hdr *)mei_hdr->extension;
+ meta->size = 0;
+ next_ext = (struct mei_ext_hdr *)meta->hdrs;
if (is_vtag) {
meta->count++;
- meta->size += mei_ext_hdr_set_vtag(meta->hdrs, cb->vtag);
+ meta->size += mei_ext_hdr_set_vtag(next_ext, cb->vtag);
+ next_ext = mei_ext_next(next_ext);
+ }
+
+ if (is_gsc) {
+ meta->count++;
+ meta->size += mei_ext_hdr_set_gsc(next_ext, cb->ext_hdr);
+ next_ext = mei_ext_next(next_ext);
}
+
out:
mei_hdr->length = hdr_len - sizeof(*mei_hdr);
return mei_hdr;
@@ -1812,14 +1841,14 @@ int mei_cl_irq_write(struct mei_cl *cl, struct
mei_cl_cb *cb,
struct mei_msg_hdr *mei_hdr = NULL;
size_t hdr_len;
size_t hbuf_len, dr_len;
- size_t buf_len;
+ size_t buf_len = 0;
size_t data_len;
int hbuf_slots;
u32 dr_slots;
u32 dma_len;
int rets;
bool first_chunk;
- const void *data;
+ const void *data = NULL;
if (WARN_ON(!cl || !cl->dev))
return -ENODEV;
@@ -1839,8 +1868,10 @@ int mei_cl_irq_write(struct mei_cl *cl, struct mei_cl_cb
*cb,
return 0;
}
- buf_len = buf->size - cb->buf_idx;
- data = buf->data + cb->buf_idx;
+ if (buf->data) {
+ buf_len = buf->size - cb->buf_idx;
+ data = buf->data + cb->buf_idx;
+ }
hbuf_slots = mei_hbuf_empty_slots(dev);
if (hbuf_slots < 0) {
rets = -EOVERFLOW;
@@ -1858,9 +1889,6 @@ int mei_cl_irq_write(struct mei_cl *cl, struct mei_cl_cb
*cb,
goto err;
}
- cl_dbg(dev, cl, "Extended Header %d vtag = %d\n",
- mei_hdr->extended, cb->vtag);
-
hdr_len = sizeof(*mei_hdr) + mei_hdr->length;
/**
@@ -1889,7 +1917,7 @@ int mei_cl_irq_write(struct mei_cl *cl, struct mei_cl_cb
*cb,
[Intel-gfx] [PATCH v3 00/15] drm/i915: HuC loading for DG2
On DG2, HuC loading is performed by the GSC, via a PXP command. The load operation itself is relatively simple (just send a message to the GSC with the physical address of the HuC in LMEM), but there are timing changes that requires special attention. In particular, to send a PXP command we need to first export the GSC as an aux device and then wait for the mei-gsc and mei-pxp modules to start, which means that HuC load will complete after i915 load is complete. This means that there is a small window of time after i915 is registered and before HuC is loaded during which userspace could submit and/or check the HuC load status, although this is quite unlikely to happen (HuC is usually loaded before kernel init/resume completes). We've consulted with the media team in regards to how to handle this and they've asked us to stall all userspace VCS submission until HuC is loaded. Stalls are expected to be very rare (if any), due to the fact that HuC is usually loaded before kernel init/resume is completed. Timeouts are in place to ensure all submissions are unlocked in case something goes wrong. Since we need to monitor the status of the mei driver to know what's happening and when to time out, a notifier has been added so we get a callback when the status of the mei driver changes. Note that this series includes several mei patches that add support for sending the HuC loading command via mei-gsc. These patches depend on the GSC support for DG2 [1], which has been included squashed in a single patch to make the series apply and allow CI to run. We plan to merge those patches through the drm tree because i915 is the sole user. [1]: https://patchwork.freedesktop.org/series/106638/ v2: address review comments, Reporting HuC loading still in progress while we wait for mei-gsc init to complete, rebase on latest mei-gsc series. v3: fix cc list in mei patches. Test-with: 20220818224216.3920822-1-daniele.ceraolospu...@intel.com Cc: Alan Previn Cc: Tony Ye Cc: Alexander Usyskin Cc: Tomas Winkler Cc: Greg Kroah-Hartman Daniele Ceraolo Spurio (8): HAX: mei: GSC support for XeHP SDV and DG2 platform drm/i915/pxp: load the pxp module when we have a gsc-loaded huc drm/i915/dg2: setup HuC loading via GSC drm/i915/huc: track delayed HuC load with a fence drm/i915/huc: stall media submission until HuC is loaded drm/i915/huc: better define HuC status getparam possible return values. drm/i915/huc: define gsc-compatible HuC fw for DG2 HAX: drm/i915: force INTEL_MEI_GSC and INTEL_MEI_PXP on for CI Tomas Winkler (4): mei: add support to GSC extended header mei: bus: enable sending gsc commands mei: pxp: support matching with a gfx discrete card drm/i915/pxp: add huc authentication and loading command Vitaly Lubart (3): mei: bus: extend bus API to support command streamer API mei: pxp: add command streamer API to the PXP driver drm/i915/pxp: implement function for sending tee stream command drivers/gpu/drm/i915/Kconfig.debug| 2 + drivers/gpu/drm/i915/Makefile | 11 +- drivers/gpu/drm/i915/gt/intel_gsc.c | 140 +- drivers/gpu/drm/i915/gt/intel_gsc.h | 3 + drivers/gpu/drm/i915/gt/uc/intel_guc.c| 1 + drivers/gpu/drm/i915/gt/uc/intel_huc.c| 253 -- drivers/gpu/drm/i915/gt/uc/intel_huc.h| 27 ++ drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 34 +++ drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 1 + drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 65 +++-- drivers/gpu/drm/i915/i915_request.c | 24 ++ drivers/gpu/drm/i915/pxp/intel_pxp.c | 32 ++- drivers/gpu/drm/i915/pxp/intel_pxp.h | 32 --- drivers/gpu/drm/i915/pxp/intel_pxp_huc.c | 69 + drivers/gpu/drm/i915/pxp/intel_pxp_huc.h | 15 ++ drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 8 + drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 8 +- drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 11 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 138 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 5 + .../drm/i915/pxp/intel_pxp_tee_interface.h| 21 ++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 6 + drivers/misc/mei/bus-fixup.c | 104 --- drivers/misc/mei/bus.c| 145 +- drivers/misc/mei/client.c | 69 +++-- drivers/misc/mei/debugfs.c| 17 ++ drivers/misc/mei/gsc-me.c | 77 +- drivers/misc/mei/hbm.c| 25 +- drivers/misc/mei/hw-me-regs.h | 7 + drivers/misc/mei/hw-me.c | 121 +++-- drivers/misc/mei/hw-me.h | 14 +- drivers/misc/mei/hw-txe.c | 2 +- drivers/misc/mei/hw.h | 62 + drivers/misc/mei/init.c | 21 +- drivers/misc/mei/interrupt.c | 47 +++-
Re: [Intel-gfx] [PATCH 3/7] drm/i915/guc: Add GuC <-> kernel time stamp translation information
On 8/19/2022 03:45, Jani Nikula wrote:
On Wed, 27 Jul 2022, john.c.harri...@intel.com wrote:
From: John Harrison
It is useful to be able to match GuC events to kernel events when
looking at the GuC log. That requires being able to convert GuC
timestamps to kernel time. So, when dumping error captures and/or GuC
logs, include a stamp in both time zones plus the clock frequency.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h| 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 19 +++
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 2 ++
drivers/gpu/drm/i915/i915_gpu_error.c | 12
drivers/gpu/drm/i915/i915_gpu_error.h | 3 +++
6 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 60d6eb5f245b7..fc7979bd91db5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1007,6 +1007,8 @@
#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC(1 << 9)
#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
+#define GUCPMTIMESTAMP_MMIO(0xc3e8)
+
#define __GEN9_RCS0_MOCS0 0xc800
#define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) *
4)
#define __GEN9_VCS0_MOCS0 0xc900
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2706a8c650900..ab4aacc516aa4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -389,6 +389,25 @@ void intel_guc_write_params(struct intel_guc *guc)
intel_uncore_forcewake_put(uncore, FORCEWAKE_GT);
}
+void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p)
+{
+ struct intel_gt *gt = guc_to_gt(guc);
+ intel_wakeref_t wakeref;
+ u32 stamp = 0;
+ u64 ktime;
+
+ intel_device_info_print_runtime(RUNTIME_INFO(gt->i915), p);
Why does this function print runtime info alone? Seems kind of random,
considering what intel_device_info_print_runtime() actually
prints. Should it print both device info and runtime info, or nothing at
all?
Hmm. That was added specifically to print the rawclk value (and only for
the rawclk value) because that was the frequency that the GuC time stamp
register ticks at. I think we later worked out that the CS frequency was
more correct. Hence printing gt->clock_frequency lower down. I guess I
forgot to go back and remove the rawclk print, though.
So yeah, it can be removed.
John.
This conflicts with [1] and I don't know what to do about it. The first
instinct is to just remove it.
BR,
Jani.
[1]
https://patchwork.freedesktop.org/patch/msgid/4be86d7a0737b2c49eee460d29d42843418536fe.1660137416.git.jani.nik...@intel.com
+
+ with_intel_runtime_pm(>i915->runtime_pm, wakeref)
+ stamp = intel_uncore_read(gt->uncore, GUCPMTIMESTAMP);
+ ktime = ktime_get_boottime_ns();
+
+ drm_printf(p, "Kernel timestamp: 0x%08llX [%llu]\n", ktime, ktime);
+ drm_printf(p, "GuC timestamp: 0x%08X [%u]\n", stamp, stamp);
+ drm_printf(p, "CS timestamp frequency: %u Hz, %u ns\n",
+ gt->clock_frequency, gt->clock_period_ns);
+}
+
int intel_guc_init(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index a7acffbf15d1f..804133df1ac9b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -464,4 +464,6 @@ void intel_guc_load_status(struct intel_guc *guc, struct
drm_printer *p);
void intel_guc_write_barrier(struct intel_guc *guc);
+void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p);
+
#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 991d4a02248dc..07d31ae32f765 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -764,6 +764,8 @@ int intel_guc_log_dump(struct intel_guc_log *log, struct
drm_printer *p,
if (!obj)
return 0;
+ intel_guc_dump_time_info(guc, p);
+
map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
if (IS_ERR(map)) {
DRM_DEBUG("Failed to pin object\n");
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 32e92651ef7c2..addba75252343 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -678,6 +678,7 @@ static void err_print_uc(struct drm_i915_error_state_buf *m,
intel_uc_fw_dump(_uc->guc_fw, );
intel_uc_fw_dump(_uc->huc_fw, );
+ err_printf(m, "GuC timestamp: 0x%08x\n", error_uc->timestamp);
intel_gpu_error_print_vma(m, NULL,
Re: [Intel-gfx] [PATCH v2 21/21] drm/i915/mtl: Do not update GV point, mask value
On Thu, Aug 18, 2022 at 04:42:02PM -0700, Radhakrishna Sripada wrote:
> No need to update mask value/restrict because
> "Pcode only wants to use GV bandwidth value, not the mask value."
> for Display version greater than 14.
While the code changes might be correct, I can't decipher what the
commit message here is trying to tell us. I'm not sure what the source
or context of the quote is, but the description in the commit message
should be more focused on why it's correct for our driver to skip these
operations. I assume it has something to do with the new pm_demand
interfaces we'll be using to program this information into the hardware
in a future series? If so, maybe this patch (with a modified commit
message) is better suited for inclusion in that future series where the
context makes more sense.
>
> Bspec: 646365
This page number seems to be incorrect too.
Matt
> Cc: Matt Roper
> Original Author: Caz Yokoyama
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/intel_pm.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d09e9e5f4481..47869fe964ba 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3924,6 +3924,14 @@ void intel_sagv_pre_plane_update(struct
> intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
>
> + /*
> + * No need to update mask value/restrict because
> + * "Pcode only wants to use GV bandwidth value, not the mask value."
> + * for DISPLAY_VER() >= 14.
> + */
> + if (DISPLAY_VER(i915) >= 14)
> + return;
> +
> /*
>* Just return if we can't control SAGV or don't have it.
>* This is different from situation when we have SAGV but just can't
> @@ -3944,6 +3952,16 @@ void intel_sagv_post_plane_update(struct
> intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
>
> + /*
> + * No need to update mask value/restrict because
> + * "Pcode only wants to use GV bandwidth value, not the mask value."
> + * for DISPLAY_VER() >= 14.
> + *
> + * GV bandwidth will be set by intel_pmdemand_post_plane_update()
> + */
> + if (DISPLAY_VER(i915) >= 14)
> + return;
> +
> /*
>* Just return if we can't control SAGV or don't have it.
>* This is different from situation when we have SAGV but just can't
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v2 14/21] drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM
On Thu, Aug 18, 2022 at 04:41:55PM -0700, Radhakrishna Sripada wrote:
> Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers
> instead of GT driver mailbox.
>
> v2: Use the extracted wm latency adjustment function(Matt)
>
> Bspec: 64608
>
> Cc: Matt Roper
> Original Author: Caz Yokoyama
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 +++
> drivers/gpu/drm/i915/intel_pm.c | 21 ++---
> 2 files changed, 25 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 04a269fa8717..b2d5e1230c25 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8390,4 +8390,11 @@ enum skl_power_gate {
> #define GEN12_STATE_ACK_DEBUG_MMIO(0x20BC)
>
> #define MTL_MEDIA_GSI_BASE 0x38
> +
> +#define MTL_LATENCY_LP0_LP1 _MMIO(0x45780)
> +#define MTL_LATENCY_LP2_LP3 _MMIO(0x45784)
> +#define MTL_LATENCY_LP4_LP5 _MMIO(0x45788)
> +#define MTL_LATENCY_LEVEL0_2_4_MASK REG_GENMASK(12, 0)
> +#define MTL_LATENCY_LEVEL1_3_5_MASK REG_GENMASK(28, 16)
You might consider "_{EVEN,ODD}_LEVEL_MASK" naming here, just in case
future IP versions add additional levels beyond LP5.
Otherwise,
Reviewed-by: Matt Roper
> +
> #endif /* _I915_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 898e56d2eaf7..fac565d23d57 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2908,13 +2908,28 @@ static void intel_read_wm_latency(struct
> drm_i915_private *dev_priv,
> u16 wm[])
> {
> struct intel_uncore *uncore = _priv->uncore;
> + int max_level = ilk_wm_max_level(dev_priv);
>
> - if (DISPLAY_VER(dev_priv) >= 9) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + u32 val;
> +
> + val = intel_uncore_read(uncore, MTL_LATENCY_LP0_LP1);
> + wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val);
> + wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val);
> + val = intel_uncore_read(uncore, MTL_LATENCY_LP2_LP3);
> + wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val);
> + wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val);
> + val = intel_uncore_read(uncore, MTL_LATENCY_LP4_LP5);
> + wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val);
> + wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val);
> +
> + adjust_wm_latency(wm, max_level, 6,
> + dev_priv->dram_info.wm_lv_0_adjust_needed);
> + } else if (DISPLAY_VER(dev_priv) >= 9) {
> int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
> + int mult = IS_DG2(dev_priv) ? 2 : 1;
> u32 val;
> int ret;
> - int max_level = ilk_wm_max_level(dev_priv);
> - int mult = IS_DG2(dev_priv) ? 2 : 1;
>
> /* read the first set of memory latencies[0:3] */
> val = 0; /* data0 to be programmed to 0 for first set */
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v2 13/21] drm/i915: Extract wm latency adjustment to its own function
On Thu, Aug 18, 2022 at 04:41:54PM -0700, Radhakrishna Sripada wrote:
> Watermark latency is adjusted in cases when latency is 0us for level
> greater than 1, the subsequent levels are disabled. Extract this logic
> into its own function.
>
> Suggested-by: Matt Roper
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/intel_pm.c | 88 ++---
> 1 file changed, 48 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ef7553b494ea..898e56d2eaf7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2861,15 +2861,59 @@ static void ilk_compute_wm_level(const struct
> drm_i915_private *dev_priv,
> result->enable = true;
> }
>
> +static void
> +adjust_wm_latency(u16 wm[], int max_level, int read_latency,
> + bool wm_lv_0_adjust_needed)
> +{
> + int i, level;
> +
> + /*
> + * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
> + * need to be disabled. We make sure to sanitize the values out
> + * of the punit to satisfy this requirement.
> + */
> + for (level = 1; level <= max_level; level++) {
> + if (wm[level] == 0) {
> + for (i = level + 1; i <= max_level; i++)
> + wm[i] = 0;
> +
> + max_level = level - 1;
> + break;
> + }
> + }
> +
> + /*
> + * WaWmMemoryReadLatency
> + *
> + * punit doesn't take into account the read latency so we need
> + * to add proper adjustement to each valid level we retrieve
> + * from the punit when level 0 response data is 0us.
> + */
> + if (wm[0] == 0) {
> + for (level = 0; level <= max_level; level++)
> + wm[level] += read_latency;
> + }
> +
> + /*
> + * WA Level-0 adjustment for 16GB DIMMs: SKL+
> + * If we could not get dimm info enable this WA to prevent from
> + * any underrun. If not able to get Dimm info assume 16GB dimm
> + * to avoid any underrun.
> + */
> + if (wm_lv_0_adjust_needed)
> + wm[0] += 1;
> +}
> +
> static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
> u16 wm[])
> {
> struct intel_uncore *uncore = _priv->uncore;
>
> if (DISPLAY_VER(dev_priv) >= 9) {
> + int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
> u32 val;
> - int ret, i;
> - int level, max_level = ilk_wm_max_level(dev_priv);
> + int ret;
> + int max_level = ilk_wm_max_level(dev_priv);
> int mult = IS_DG2(dev_priv) ? 2 : 1;
>
> /* read the first set of memory latencies[0:3] */
> @@ -2909,44 +2953,8 @@ static void intel_read_wm_latency(struct
> drm_i915_private *dev_priv,
> wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
> GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
>
> - /*
> - * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
> - * need to be disabled. We make sure to sanitize the values out
> - * of the punit to satisfy this requirement.
> - */
> - for (level = 1; level <= max_level; level++) {
> - if (wm[level] == 0) {
> - for (i = level + 1; i <= max_level; i++)
> - wm[i] = 0;
> -
> - max_level = level - 1;
> -
> - break;
> - }
> - }
> -
> - /*
> - * WaWmMemoryReadLatency
> - *
> - * punit doesn't take into account the read latency so we need
> - * to add proper adjustement to each valid level we retrieve
> - * from the punit when level 0 response data is 0us.
> - */
> - if (wm[0] == 0) {
> - u8 adjust = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
> -
> - for (level = 0; level <= max_level; level++)
> - wm[level] += adjust;
> - }
> -
> - /*
> - * WA Level-0 adjustment for 16GB DIMMs: SKL+
> - * If we could not get dimm info enable this WA to prevent from
> - * any underrun. If not able to get Dimm info assume 16GB dimm
> - * to avoid any underrun.
> - */
> - if (dev_priv->dram_info.wm_lv_0_adjust_needed)
> - wm[0] += 1;
> + adjust_wm_latency(wm, max_level, read_latency,
> + dev_priv->dram_info.wm_lv_0_adjust_needed);
Would it be cleaner to just pass the dev_priv as a parameter to the
function and have it extract the structure field? As far as I can tell,
Re: [Intel-gfx] [PATCH v2 07/21] drm/i915/mtl: Add gmbus and gpio support
On Thu, Aug 18, 2022 at 04:41:48PM -0700, Radhakrishna Sripada wrote:
> Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
> From spec we have registers GPIO_CTL[1-5] mapped to native display phys and
> GPIO_CTL[9-14] are mapped to TC ports.
>
> BSpec: 49306
>
> Original Author: Brian J Lovin
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/display/intel_gmbus.c | 17 +
> drivers/gpu/drm/i915/display/intel_gmbus.h | 1 +
> 2 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
> b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index a6ba7fb72339..542b8b2654be 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -116,6 +116,20 @@ static const struct gmbus_pin gmbus_pins_dg2[] = {
> [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> };
>
> +static const struct gmbus_pin gmbus_pins_mtp[] = {
> + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> + [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> + [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> + [GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
> + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> + [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
> + [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
There's no GPIO_CTL registers for pin 13 or pin 14 on on MTP so these
last two entries shouldn't be here (and the commit message should be
fixed too).
Matt
> +};
> +
> static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
>unsigned int pin)
> {
> @@ -128,6 +142,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct
> drm_i915_private *i915,
> } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
> pins = gmbus_pins_dg1;
> size = ARRAY_SIZE(gmbus_pins_dg1);
> + } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) {
> + pins = gmbus_pins_mtp;
> + size = ARRAY_SIZE(gmbus_pins_mtp);
> } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
> pins = gmbus_pins_icp;
> size = ARRAY_SIZE(gmbus_pins_icp);
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h
> b/drivers/gpu/drm/i915/display/intel_gmbus.h
> index 8edc2e99cf53..20f704bd4e70 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.h
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
> @@ -24,6 +24,7 @@ struct i2c_adapter;
> #define GMBUS_PIN_2_BXT 2
> #define GMBUS_PIN_3_BXT 3
> #define GMBUS_PIN_4_CNP 4
> +#define GMBUS_PIN_5_MTP 5
> #define GMBUS_PIN_9_TC1_ICP 9
> #define GMBUS_PIN_10_TC2_ICP 10
> #define GMBUS_PIN_11_TC3_ICP 11
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v2 01/21] drm/i915: Read graphics/media/display arch version from hw
On Thu, Aug 18, 2022 at 04:41:42PM -0700, Radhakrishna Sripada wrote:
> From: Matt Roper
>
> Going forward, the hardware teams no longer consider new platforms to
> have a "generation" in the way we've defined it for past platforms.
> Instead, each IP block (graphics, media, display) will have their own
> architecture major.minor versions and stepping ID's which should be read
> directly from a register in the MMIO space. New hardware programming
> styles, features, and workarounds should be conditional solely on the
> architecture version, and should no longer be derived from the PCI
> device ID, revision ID, or platform-specific feature flags.
>
> v1.1: Fix build error
As Jani noted on the previous version, this patch needs to be split into
three patches (and/or be based on top of the other series that Jani has
in flight). Also the giant macro is no longer necessary on current
drm-tip now that we the version values stored consistently in
structures; we can just use a regular function and pass pointers to the
structures.
Bala also had feedback on the previous version that hasn't been
incorporated here yet either.
Matt
>
> Bspec: 63361, 64111
>
> Signed-off-by: Matt Roper
> Signed-off-by: Rodrigo Vivi
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +
> drivers/gpu/drm/i915/i915_driver.c| 80 ++-
> drivers/gpu/drm/i915/i915_drv.h | 16 ++--
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 6 ++
> drivers/gpu/drm/i915/intel_device_info.c | 32
> drivers/gpu/drm/i915/intel_device_info.h | 14
> .../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
> 8 files changed, 128 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 94f9ddcfb3a5..a053493dae24 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -39,6 +39,8 @@
> #define FORCEWAKE_ACK_RENDER_GEN9_MMIO(0xd84)
> #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)
>
> +#define GMD_ID_GRAPHICS _MMIO(0xd8c)
> +
> #define MCFG_MCR_SELECTOR_MMIO(0xfd0)
> #define SF_MCR_SELECTOR _MMIO(0xfd8)
> #define GEN8_MCR_SELECTOR_MMIO(0xfdc)
> diff --git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
> index deb8a8b76965..33566f6e9546 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -70,6 +70,7 @@
> #include "gem/i915_gem_pm.h"
> #include "gt/intel_gt.h"
> #include "gt/intel_gt_pm.h"
> +#include "gt/intel_gt_regs.h"
> #include "gt/intel_rc6.h"
>
> #include "pxp/intel_pxp_pm.h"
> @@ -306,15 +307,83 @@ static void sanitize_gpu(struct drm_i915_private *i915)
> __intel_gt_reset(to_gt(i915), ALL_ENGINES);
> }
>
> +#define IP_VER_READ(offset, ri_prefix) \
> + addr = pci_iomap_range(pdev, 0, offset, sizeof(u32)); \
> + if (drm_WARN_ON(>drm, !addr)) { \
> + /* Fall back to whatever was in the device info */ \
> + RUNTIME_INFO(i915)->ri_prefix.ver =
> INTEL_INFO(i915)->ri_prefix.ver; \
> + RUNTIME_INFO(i915)->ri_prefix.rel =
> INTEL_INFO(i915)->ri_prefix.rel; \
> + goto ri_prefix##done; \
> + } \
> + \
> + ver = ioread32(addr); \
> + pci_iounmap(pdev, addr); \
> + \
> + RUNTIME_INFO(i915)->ri_prefix.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK,
> ver); \
> + RUNTIME_INFO(i915)->ri_prefix.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK,
> ver); \
> + RUNTIME_INFO(i915)->ri_prefix.step = REG_FIELD_GET(GMD_ID_STEP, ver); \
> + \
> + /* Sanity check against expected versions from device info */ \
> + if (RUNTIME_INFO(i915)->ri_prefix.ver !=
> INTEL_INFO(i915)->ri_prefix.ver || \
> + RUNTIME_INFO(i915)->ri_prefix.rel >
> INTEL_INFO(i915)->ri_prefix.rel) \
> + drm_dbg(>drm, \
> + "Hardware reports " #ri_prefix " IP version %u.%u but
> minimum expected is %u.%u\n", \
> + RUNTIME_INFO(i915)->ri_prefix.ver, \
> + RUNTIME_INFO(i915)->ri_prefix.rel, \
> + INTEL_INFO(i915)->ri_prefix.ver, \
> + INTEL_INFO(i915)->ri_prefix.rel); \
> +ri_prefix##done:
> +
> +/**
> + * intel_ipver_early_init - setup IP version values
> + * @dev_priv: device private
> + *
> + * Setup the graphics version for the current device. This must be done
> before
> + * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this
> + * function should be called very early in the driver initialization
> sequence.
> + *
> + * Regular MMIO access is not yet setup at the point this function is called
> so
> + * we peek at the appropriate MMIO offset directly.
Re: [Intel-gfx] [PATCH] drm/i915: Switch TGL-H DP-IN to dGFX when it's supported
On Thu, Aug 18, 2022 at 2:09 PM Lukas Wunner wrote: > > On Tue, Aug 16, 2022 at 11:06:18AM +0300, Jani Nikula wrote: > > On Tue, 16 Aug 2022, Kai-Heng Feng wrote: > > > On mobile workstations like HP ZBook Fury G8, iGFX's DP-IN can switch to > > > dGFX so external monitors are routed to dGFX, and more monitors can be > > > supported as result. > > > > > > To switch the DP-IN to dGFX, the driver needs to invoke _DSM function 20 > > > on intel_dsm_guid2. This method is described in Intel document 632107. > > > > Is this the policy decision that we want to unconditionally make, > > though? > > In general, we handle switching of outputs between GPUs in vga_switcheroo.c > upon a request from user space via sysfs (well, debugfs currently). > It's up to users to decide which policy suits their needs best. > > That said, we never grew support to allow different switching policies for > the built-in panel and external outputs. Laptops supporting this are > rare. Older MacBook Pros introduced between 2008 and 2010 are among them: > They have separate muxes for the panel and external DP port. Our policy > is documented in a code comment in drivers/platform/x86/apple-gmux.c: > > * The external DP port is only fully switchable on the first two unibody > * MacBook Pro generations, MBP5 2008/09 and MBP6 2010. This is done by an > * `NXP CBTL06141`_ which is controlled by gmux. > [...] > * Our switching policy for the external port is that on those generations > * which are able to switch it fully, the port is switched together with the > * panel when IGD / DIS commands are issued to vga_switcheroo. It is thus > * possible to drive e.g. a beamer on battery power with the integrated GPU. > * The user may manually switch to the discrete GPU if more performance is > * needed. > * > * On all newer generations, the external port can only be driven by the > * discrete GPU. If a display is plugged in while the panel is switched to > * the integrated GPU, *both* GPUs will be in use for maximum performance. > * To decrease power consumption, the user may manually switch to the > * discrete GPU, thereby suspending the integrated GPU. > > In other words, on these older MacBook Pros, we switch the panel and > external DP port in unison, thus always allowing one of the two GPUs > to runtime suspend and save power. > > Thanks, > > Lukas > sure, but this is changing now. I do have a laptop with a muxable internal display. But this is considered to be a dynamic on demand switching thing not a boot time switch. Anyway, I am still not convinced that doing that unconditionally is what we want, especially as userspace has to support dynamic switching regardless.
Re: [Intel-gfx] [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
Will look into this - apologies for the trouble Matt.
...alan
-Original Message-
From: Harrison, John C
Sent: Friday, August 19, 2022 8:46 AM
To: Auld, Matthew ; intel-gfx@lists.freedesktop.org
Cc: Brost, Matthew ; Teres Alexis, Alan Previn
Subject: Re: [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling
after pin count goes to zero"
On 8/19/2022 05:39, Matthew Auld wrote:
> This reverts commit 6a079903847cce1dd06345127d2a32f26d2cd9c6.
>
> Everything in CI using GuC is now timing out[1], and killing the
> machine with this change (perhaps a deadlock?). CI was recently on
> fire due to some changes coming in from -rc1, so likely the pre-merge
> CI results for this series were invalid? For now just revert, unless
> GuC experts already have a fix in mind.
>
> [1] https://intel-gfx-ci.01.org/tree/drm-tip/index.html?
>
> Signed-off-by: Matthew Auld
> Cc: Matthew Brost
> Cc: Alan Previn
> Cc: John Harrison
Reviewed-by: John Harrison
Given that CI was claiming a pass for the original patch set, no we don't have
a fix in mind. It is most frustrating when CI says all green if the entire
universe is so broken that no tests were even running :(.
John.
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_context.h | 8 -
> drivers/gpu/drm/i915/gt/intel_context_types.h | 7 -
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 17 +-
> .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c| 60 ---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 154 +++---
> drivers/gpu/drm/i915/i915_selftest.h | 2 -
> 7 files changed, 27 insertions(+), 223 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index df7fd1b019ec..dabdfe09f5e5 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1454,7 +1454,7 @@ static void engines_idle_release(struct
> i915_gem_context *ctx,
> int err;
>
> /* serialises with execbuf */
> - intel_context_close(ce);
> + set_bit(CONTEXT_CLOSED_BIT, >flags);
> if (!intel_context_pin_if_active(ce))
> continue;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
> b/drivers/gpu/drm/i915/gt/intel_context.h
> index f96420f0b5bb..8e2d70630c49 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.h
> +++ b/drivers/gpu/drm/i915/gt/intel_context.h
> @@ -276,14 +276,6 @@ static inline bool intel_context_is_barrier(const struct
> intel_context *ce)
> return test_bit(CONTEXT_BARRIER_BIT, >flags);
> }
>
> -static inline void intel_context_close(struct intel_context *ce) -{
> - set_bit(CONTEXT_CLOSED_BIT, >flags);
> -
> - if (ce->ops->close)
> - ce->ops->close(ce);
> -}
> -
> static inline bool intel_context_is_closed(const struct intel_context *ce)
> {
> return test_bit(CONTEXT_CLOSED_BIT, >flags); diff --git
> a/drivers/gpu/drm/i915/gt/intel_context_types.h
> b/drivers/gpu/drm/i915/gt/intel_context_types.h
> index 86ac84e2edb9..04eacae1aca5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> @@ -43,8 +43,6 @@ struct intel_context_ops {
> void (*revoke)(struct intel_context *ce, struct i915_request *rq,
> unsigned int preempt_timeout_ms);
>
> - void (*close)(struct intel_context *ce);
> -
> int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww,
> void **vaddr);
> int (*pin)(struct intel_context *ce, void *vaddr);
> void (*unpin)(struct intel_context *ce); @@ -210,11 +208,6 @@
> struct intel_context {
>* each priority bucket
>*/
> u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
> - /**
> - * @sched_disable_delay: worker to disable scheduling on this
> - * context
> - */
> - struct delayed_work sched_disable_delay;
> } guc_state;
>
> struct {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index 944b549b8797..804133df1ac9 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -112,10 +112,6 @@ struct intel_guc {
>* refs
>*/
> struct list_head guc_id_list;
> - /**
> - * @guc_ids_in_use: Number single-lrc guc_ids in use
> - */
> - u16 guc_ids_in_use;
> /**
>* @destroyed_contexts: list of contexts waiting to be destroyed
>* (deregistered with the GuC)
> @@ -136,16 +132,6 @@ struct intel_guc {
>* @reset_fail_mask: mask of engines that failed to reset
>*/
> intel_engine_mask_t reset_fail_mask;
>
Re: [Intel-gfx] [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
On 8/19/2022 05:39, Matthew Auld wrote:
This reverts commit 6a079903847cce1dd06345127d2a32f26d2cd9c6.
Everything in CI using GuC is now timing out[1], and killing the machine
with this change (perhaps a deadlock?). CI was recently on fire due to
some changes coming in from -rc1, so likely the pre-merge CI results for
this series were invalid? For now just revert, unless GuC experts
already have a fix in mind.
[1] https://intel-gfx-ci.01.org/tree/drm-tip/index.html?
Signed-off-by: Matthew Auld
Cc: Matthew Brost
Cc: Alan Previn
Cc: John Harrison
Reviewed-by: John Harrison
Given that CI was claiming a pass for the original patch set, no we
don't have a fix in mind. It is most frustrating when CI says all green
if the entire universe is so broken that no tests were even running :(.
John.
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_context.h | 8 -
drivers/gpu/drm/i915/gt/intel_context_types.h | 7 -
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 17 +-
.../gpu/drm/i915/gt/uc/intel_guc_debugfs.c| 60 ---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 154 +++---
drivers/gpu/drm/i915/i915_selftest.h | 2 -
7 files changed, 27 insertions(+), 223 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index df7fd1b019ec..dabdfe09f5e5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1454,7 +1454,7 @@ static void engines_idle_release(struct i915_gem_context
*ctx,
int err;
/* serialises with execbuf */
- intel_context_close(ce);
+ set_bit(CONTEXT_CLOSED_BIT, >flags);
if (!intel_context_pin_if_active(ce))
continue;
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h
index f96420f0b5bb..8e2d70630c49 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -276,14 +276,6 @@ static inline bool intel_context_is_barrier(const struct
intel_context *ce)
return test_bit(CONTEXT_BARRIER_BIT, >flags);
}
-static inline void intel_context_close(struct intel_context *ce)
-{
- set_bit(CONTEXT_CLOSED_BIT, >flags);
-
- if (ce->ops->close)
- ce->ops->close(ce);
-}
-
static inline bool intel_context_is_closed(const struct intel_context *ce)
{
return test_bit(CONTEXT_CLOSED_BIT, >flags);
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 86ac84e2edb9..04eacae1aca5 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -43,8 +43,6 @@ struct intel_context_ops {
void (*revoke)(struct intel_context *ce, struct i915_request *rq,
unsigned int preempt_timeout_ms);
- void (*close)(struct intel_context *ce);
-
int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww,
void **vaddr);
int (*pin)(struct intel_context *ce, void *vaddr);
void (*unpin)(struct intel_context *ce);
@@ -210,11 +208,6 @@ struct intel_context {
* each priority bucket
*/
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
- /**
-* @sched_disable_delay: worker to disable scheduling on this
-* context
-*/
- struct delayed_work sched_disable_delay;
} guc_state;
struct {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 944b549b8797..804133df1ac9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -112,10 +112,6 @@ struct intel_guc {
* refs
*/
struct list_head guc_id_list;
- /**
-* @guc_ids_in_use: Number single-lrc guc_ids in use
-*/
- u16 guc_ids_in_use;
/**
* @destroyed_contexts: list of contexts waiting to be destroyed
* (deregistered with the GuC)
@@ -136,16 +132,6 @@ struct intel_guc {
* @reset_fail_mask: mask of engines that failed to reset
*/
intel_engine_mask_t reset_fail_mask;
- /**
-* @sched_disable_delay_ms: schedule disable delay, in ms, for
-* contexts
-*/
- u64 sched_disable_delay_ms;
- /**
-* @sched_disable_gucid_threshold: threshold of min remaining
available
-* guc_ids before we start bypassing the schedule disable delay
-*/
- int sched_disable_gucid_threshold;
} submission_state;
/**
@@ -475,10 +461,9 @@
Re: [Intel-gfx] [PATCH v2 00/15] drm/i915: HuC loading for DG2
On 8/19/2022 12:21 AM, Greg Kroah-Hartman wrote: On Thu, Aug 18, 2022 at 04:02:28PM -0700, Daniele Ceraolo Spurio wrote: Note that this series includes several mei patches that add support for sending the HuC loading command via mei-gsc. These patches depend on the GSC support for DG2 [1], which has been included squashed in a single patch to make the series apply and allow CI to run. We plan to merge those patches through the drm tree because i915 is the sole user. Doesn't look like you cc:ed me on any of the mei patches, which is odd, and ensure I can't review them :( My bad, will re-send the series and properly CC you on the mei patches. And why are mei changes needed only for drm? Simplifying a bit here: the GSC is on the discrete graphics card and only performs operations that are related to it; we have the mei driver take control of the GSC because its interface is mostly the same as the ME, so we can re-use the flows that are already implemented in mei with some tweaks. Daniele thanks, greg k-h
[Intel-gfx] [drm-intel:drm-intel-gt-next 2/2] drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:352:20: error: unused function 'context_has_committed_requests'
drivers/gpu/drm/i915/gem/i915_gem_context.c
drivers/gpu/drm/i915/gt/intel_context.h
drivers/gpu/drm/i915/gt/intel_context_types.h
drivers/gpu/drm/i915/gt/uc/intel_guc.h
drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
drivers/gpu/drm/i915/i915_selftest.h
tree: git://anongit.freedesktop.org/drm-intel drm-intel-gt-next
head: 6a079903847cce1dd06345127d2a32f26d2cd9c6
commit: 6a079903847cce1dd06345127d2a32f26d2cd9c6 [2/2] drm/i915/guc: Add delay
to disable scheduling after pin count goes to zero
config: x86_64-allmodconfig
(https://download.01.org/0day-ci/archive/20220819/202208192254.jhkstqcs-...@intel.com/config)
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project
0ac597f3cacf60479ffd36b03766fa7462dabd78)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
git remote add drm-intel git://anongit.freedesktop.org/drm-intel
git fetch --no-tags drm-intel drm-intel-gt-next
git checkout 6a079903847cce1dd06345127d2a32f26d2cd9c6
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1
O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:352:20: error: unused
>> function 'context_has_committed_requests' [-Werror,-Wunused-function]
static inline bool context_has_committed_requests(struct intel_context *ce)
^
1 error generated.
vim +/context_has_committed_requests +352
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
62eaf0ae217d45 Matthew Brost 2021-07-26 351
5b116c17e6babc Matthew Brost 2021-09-09 @352 static inline bool
context_has_committed_requests(struct intel_context *ce)
5b116c17e6babc Matthew Brost 2021-09-09 353 {
5b116c17e6babc Matthew Brost 2021-09-09 354return
!!ce->guc_state.number_committed_requests;
5b116c17e6babc Matthew Brost 2021-09-09 355 }
5b116c17e6babc Matthew Brost 2021-09-09 356
:: The code at line 352 was first introduced by commit
:: 5b116c17e6babc6de2e26714bc66228c74038b71 drm/i915/guc: Drop pin count
check trick between sched_disable and re-pin
:: TO: Matthew Brost
:: CC: John Harrison
--
0-DAY CI Kernel Test Service
https://01.org/lkp
[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
== Series Details ==
Series: Revert "drm/i915/guc: Add delay to disable scheduling after pin count
goes to zero"
URL : https://patchwork.freedesktop.org/series/107502/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12003 -> Patchwork_107502v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/index.html
Participating hosts (30 -> 31)
--
Additional (6): fi-rkl-11600 bat-dg2-8 bat-adlm-1 bat-adlp-6 bat-jsl-3
bat-dg2-10
Missing(5): fi-kbl-soraka bat-dg1-6 bat-dg1-5 fi-ilk-650 bat-rplp-1
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107502v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_lrc:
- {bat-dg2-9}:NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-dg2-9/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@workarounds:
- {bat-dg2-10}: NOTRUN -> [DMESG-FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-dg2-10/igt@i915_selftest@l...@workarounds.html
- {bat-dg2-9}:NOTRUN -> [DMESG-FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-dg2-9/igt@i915_selftest@l...@workarounds.html
- {bat-dg2-8}:NOTRUN -> [DMESG-FAIL][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-dg2-8/igt@i915_selftest@l...@workarounds.html
* igt@i915_suspend@basic-s3-without-i915:
- {bat-dg2-8}:NOTRUN -> [SKIP][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-dg2-8/igt@i915_susp...@basic-s3-without-i915.html
* igt@runner@aborted:
- {bat-adlm-1}: NOTRUN -> [FAIL][6]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-adlm-1/igt@run...@aborted.html
- {bat-adlp-6}: NOTRUN -> [FAIL][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-adlp-6/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_107502v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-rkl-11600: NOTRUN -> [SKIP][8] ([i915#2190])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-rkl-guc: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-rkl-11600: NOTRUN -> [SKIP][10] ([i915#4613]) +3 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_tiled_pread_basic:
- fi-rkl-11600: NOTRUN -> [SKIP][11] ([i915#3282])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html
- fi-rkl-guc: NOTRUN -> [SKIP][12] ([i915#3282])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-rkl-guc: NOTRUN -> [SKIP][13] ([i915#3012])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@i915_pm_backli...@basic-brightness.html
- fi-rkl-11600: NOTRUN -> [SKIP][14] ([i915#3012])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [PASS][15] -> [INCOMPLETE][16] ([i915#5847])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@gem:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][17] ([i915#4528])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-pnv-d510/igt@i915_selftest@l...@gem.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][18] ([i915#5982])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-rkl-guc: NOTRUN -> [SKIP][19] ([fdo#111827]) +8 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
-
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
== Series Details == Series: Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero" URL : https://patchwork.freedesktop.org/series/107502/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH 1/3] drm: Use original src rect while initializing damage iterator
On Fri, 2022-08-19 at 09:09 -0300, Maíra Canal wrote:
> Hi Jouni,
>
> On 7/15/22 10:49, Jouni Högander wrote:
> > drm_plane_state->src might be modified by the driver. This is done
> > e.g. in i915 driver when there is bigger framebuffer than the plane
> > and there is some offset within framebuffer. I915 driver calculates
> > separate offset and adjusts src rect coords to be relative to this
> > offset. Damage clips are still relative to original src coords
> > provided by user-space.
> >
> > This patch ensures original coordinates provided by user-space are
> > used when initiliazing damage iterator.
> >
>
> drm_damage_helper has some KUnit tests on drivers/gpu/drm/tests, and
> by
> applying this patch the drm_damage_helper tests started to fail.
> Could
> you also refactor the drm_damage_helper tests?
>
> To run the tests, you can run:
> $ ./tools/testing/kunit/kunit.py run \
> --kunitconfig=drivers/gpu/drm/tests \
> --kconfig_add CONFIG_UML_PCI_OVER_VIRTIO=y \
> --kconfig_add CONFIG_VIRTIO_UML=y
>
> There is also some documentation on the DRM KUnit Tests on [1].
>
> [1] https://docs.kernel.org/gpu/drm-internals.html#unit-testing
Ok, thank you for these. I will take a look.
>
> Best Regards,
> - Maíra Canal
>
> > Signed-off-by: Jouni Högander > ---
> > drivers/gpu/drm/drm_damage_helper.c | 11 +++
> > 1 file changed, 7 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_damage_helper.c
> > b/drivers/gpu/drm/drm_damage_helper.c
> > index 937b699ac2a8..d8b2955e88fd 100644
> > --- a/drivers/gpu/drm/drm_damage_helper.c
> > +++ b/drivers/gpu/drm/drm_damage_helper.c
> > @@ -224,6 +224,7 @@ drm_atomic_helper_damage_iter_init(struct
> > drm_atomic_helper_damage_iter *iter,
> >const struct drm_plane_state
> > *old_state,
> >const struct drm_plane_state *state)
> > {
> > + struct drm_rect src;
> > memset(iter, 0, sizeof(*iter));
> >
> > if (!state || !state->crtc || !state->fb || !state->visible)
> > @@ -233,10 +234,12 @@ drm_atomic_helper_damage_iter_init(struct
> > drm_atomic_helper_damage_iter *iter,
> > iter->num_clips = drm_plane_get_damage_clips_count(state);
> >
> > /* Round down for x1/y1 and round up for x2/y2 to catch all
> > pixels */
> > - iter->plane_src.x1 = state->src.x1 >> 16;
> > - iter->plane_src.y1 = state->src.y1 >> 16;
> > - iter->plane_src.x2 = (state->src.x2 >> 16) + !!(state->src.x2 &
> > 0x);
> > - iter->plane_src.y2 = (state->src.y2 >> 16) + !!(state->src.y2 &
> > 0x);
> > + src = drm_plane_state_src(state);
> > +
> > + iter->plane_src.x1 = src.x1 >> 16;
> > + iter->plane_src.y1 = src.y1 >> 16;
> > + iter->plane_src.x2 = (src.x2 >> 16) + !!(src.x2 & 0x);
> > + iter->plane_src.y2 = (src.y2 >> 16) + !!(src.y2 & 0x);
> >
> > if (!iter->clips || !drm_rect_equals(>src, _state-
> > >src)) {
> > iter->clips = NULL;
[Intel-gfx] ✗ Fi.CI.BAT: failure for gpu: move from strlcpy with unused retval to strscpy
== Series Details ==
Series: gpu: move from strlcpy with unused retval to strscpy
URL : https://patchwork.freedesktop.org/series/107501/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12003 -> Patchwork_107501v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_107501v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_107501v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/index.html
Participating hosts (30 -> 39)
--
Additional (9): fi-rkl-11600 bat-dg2-8 bat-adlm-1 bat-dg2-10 bat-adlp-6
bat-adln-1 bat-jsl-3 bat-rpls-1 bat-rpls-2
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107501v1:
### IGT changes ###
Possible regressions
* igt@gem_basic@bad-close:
- bat-dg1-5: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-dg1-5/igt@gem_ba...@bad-close.html
- bat-dg1-6: NOTRUN -> [INCOMPLETE][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-dg1-6/igt@gem_ba...@bad-close.html
Warnings
* igt@debugfs_test@read_all_entries:
- bat-dg1-6: [INCOMPLETE][3] -> [TIMEOUT][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/bat-dg1-6/igt@debugfs_test@read_all_entries.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-dg1-6/igt@debugfs_test@read_all_entries.html
- bat-dg1-5: [INCOMPLETE][5] -> [TIMEOUT][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/bat-dg1-5/igt@debugfs_test@read_all_entries.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-dg1-5/igt@debugfs_test@read_all_entries.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-elk-e7500: [INCOMPLETE][7] ([i915#6598] / [i915#6601]) ->
[INCOMPLETE][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/fi-elk-e7500/igt@i915_susp...@basic-s3-without-i915.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/fi-elk-e7500/igt@i915_susp...@basic-s3-without-i915.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@debugfs_test@read_all_entries:
- {bat-adln-1}: NOTRUN -> [TIMEOUT][9] +2 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-adln-1/igt@debugfs_test@read_all_entries.html
- {bat-dg2-8}:NOTRUN -> [TIMEOUT][10] +2 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-dg2-8/igt@debugfs_test@read_all_entries.html
- {bat-rpls-1}: NOTRUN -> [TIMEOUT][11] +1 similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-rpls-1/igt@debugfs_test@read_all_entries.html
- {bat-rpls-2}: NOTRUN -> [TIMEOUT][12] +1 similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-rpls-2/igt@debugfs_test@read_all_entries.html
- {bat-rplp-1}: [INCOMPLETE][13] -> [TIMEOUT][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/bat-rplp-1/igt@debugfs_test@read_all_entries.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-rplp-1/igt@debugfs_test@read_all_entries.html
- {bat-dg2-9}:[INCOMPLETE][15] -> [TIMEOUT][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/bat-dg2-9/igt@debugfs_test@read_all_entries.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-dg2-9/igt@debugfs_test@read_all_entries.html
* igt@gem_basic@bad-close:
- {bat-adln-1}: NOTRUN -> [INCOMPLETE][17]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-adln-1/igt@gem_ba...@bad-close.html
- {bat-dg2-8}:NOTRUN -> [INCOMPLETE][18]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-dg2-8/igt@gem_ba...@bad-close.html
- {bat-rplp-1}: NOTRUN -> [INCOMPLETE][19]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-rplp-1/igt@gem_ba...@bad-close.html
- {bat-rpls-1}: NOTRUN -> [INCOMPLETE][20]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-rpls-1/igt@gem_ba...@bad-close.html
- {bat-dg2-9}:NOTRUN -> [INCOMPLETE][21]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-dg2-9/igt@gem_ba...@bad-close.html
- {bat-rpls-2}: NOTRUN -> [INCOMPLETE][22]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107501v1/bat-rpls-2/igt@gem_ba...@bad-close.html
*
[Intel-gfx] [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
This reverts commit 6a079903847cce1dd06345127d2a32f26d2cd9c6.
Everything in CI using GuC is now timing out[1], and killing the machine
with this change (perhaps a deadlock?). CI was recently on fire due to
some changes coming in from -rc1, so likely the pre-merge CI results for
this series were invalid? For now just revert, unless GuC experts
already have a fix in mind.
[1] https://intel-gfx-ci.01.org/tree/drm-tip/index.html?
Signed-off-by: Matthew Auld
Cc: Matthew Brost
Cc: Alan Previn
Cc: John Harrison
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_context.h | 8 -
drivers/gpu/drm/i915/gt/intel_context_types.h | 7 -
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 17 +-
.../gpu/drm/i915/gt/uc/intel_guc_debugfs.c| 60 ---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 154 +++---
drivers/gpu/drm/i915/i915_selftest.h | 2 -
7 files changed, 27 insertions(+), 223 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index df7fd1b019ec..dabdfe09f5e5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1454,7 +1454,7 @@ static void engines_idle_release(struct i915_gem_context
*ctx,
int err;
/* serialises with execbuf */
- intel_context_close(ce);
+ set_bit(CONTEXT_CLOSED_BIT, >flags);
if (!intel_context_pin_if_active(ce))
continue;
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index f96420f0b5bb..8e2d70630c49 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -276,14 +276,6 @@ static inline bool intel_context_is_barrier(const struct
intel_context *ce)
return test_bit(CONTEXT_BARRIER_BIT, >flags);
}
-static inline void intel_context_close(struct intel_context *ce)
-{
- set_bit(CONTEXT_CLOSED_BIT, >flags);
-
- if (ce->ops->close)
- ce->ops->close(ce);
-}
-
static inline bool intel_context_is_closed(const struct intel_context *ce)
{
return test_bit(CONTEXT_CLOSED_BIT, >flags);
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 86ac84e2edb9..04eacae1aca5 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -43,8 +43,6 @@ struct intel_context_ops {
void (*revoke)(struct intel_context *ce, struct i915_request *rq,
unsigned int preempt_timeout_ms);
- void (*close)(struct intel_context *ce);
-
int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww,
void **vaddr);
int (*pin)(struct intel_context *ce, void *vaddr);
void (*unpin)(struct intel_context *ce);
@@ -210,11 +208,6 @@ struct intel_context {
* each priority bucket
*/
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
- /**
-* @sched_disable_delay: worker to disable scheduling on this
-* context
-*/
- struct delayed_work sched_disable_delay;
} guc_state;
struct {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 944b549b8797..804133df1ac9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -112,10 +112,6 @@ struct intel_guc {
* refs
*/
struct list_head guc_id_list;
- /**
-* @guc_ids_in_use: Number single-lrc guc_ids in use
-*/
- u16 guc_ids_in_use;
/**
* @destroyed_contexts: list of contexts waiting to be destroyed
* (deregistered with the GuC)
@@ -136,16 +132,6 @@ struct intel_guc {
* @reset_fail_mask: mask of engines that failed to reset
*/
intel_engine_mask_t reset_fail_mask;
- /**
-* @sched_disable_delay_ms: schedule disable delay, in ms, for
-* contexts
-*/
- u64 sched_disable_delay_ms;
- /**
-* @sched_disable_gucid_threshold: threshold of min remaining
available
-* guc_ids before we start bypassing the schedule disable delay
-*/
- int sched_disable_gucid_threshold;
} submission_state;
/**
@@ -475,10 +461,9 @@ void intel_guc_submission_reset_finish(struct intel_guc
*guc);
void intel_guc_submission_cancel_requests(struct intel_guc *guc);
void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p);
-void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p);
Re: [Intel-gfx] [External] Re: [PATCH] drm/i915: Switch TGL-H DP-IN to dGFX when it's supported
On 2022-08-17 13:56, Lyude Paul wrote: > Adding Mark Pearson from Lenovo to this, Mark for reference the original patch > is here: > > https://patchwork.freedesktop.org/patch/497807/?series=107312=1>> > Comments from me down below > > On Wed, 2022-08-17 at 09:02 +0800, Kai-Heng Feng wrote: >> On Wed, Aug 17, 2022 at 2:24 AM Lyude Paul wrote: >>> >>> On Tue, 2022-08-16 at 19:29 +0800, Kai-Heng Feng wrote: On Tue, Aug 16, 2022 at 4:06 PM Jani Nikula wrote: > > On Tue, 16 Aug 2022, Kai-Heng Feng wrote: >> On mobile workstations like HP ZBook Fury G8, iGFX's DP-IN can switch to >> dGFX so external monitors are routed to dGFX, and more monitors can be >> supported as result. >> >> To switch the DP-IN to dGFX, the driver needs to invoke _DSM function 20 >> on intel_dsm_guid2. This method is described in Intel document 632107. >>> >>> Is this documentation released anywhere? We've been wondering about these >>> interfaces for quite a long time, and it would be good to know if there's >>> docs >>> for this we haven't really been seeing. >>> > > Is this the policy decision that we want to unconditionally make, > though? I believes so, so more external monitors can be supported at the same time. Kai-Heng >>> >>> Is this for systems with dual Intel GPUs? I ask because if this affects >>> Intel/Nvidia hybrid systems then this is a huge no from me. Nouveau is able >>> to >>> support these systems, but at a limited capacity. This would imply that we >>> are >>> making external displays work for users of the nvidia proprietary driver, at >>> the expense making external display support for mainline kernel users >>> substantially worse for people who are using the mainline kernel. Which >>> isn't >>> a choice we should be making, because nvidia's OOT driver is not a mainline >>> kernel driver. >> >> Yes it's for Intel/NVIDIA hybrid systems. >> >> The problem is that hardware vendor design the systems to use NVIDIA >> for external displays, so using external displays on Intel are never >> tested by the vendors. >> I don't think that's any good either. >> > > Sigh, the constant forcing of nvidia hardware into laptops from vendors is > seriously something I wish they would knock it off with considering they're > basically the most difficult hardware vendor to work with. > > Anyway, if we -need- to route displays through the external GPU then we can. > But I'd like to at least get convinced first that this is an actual necessity > we should expect for multiple vendors, or the exception to the rule. Because > if these laptops are capable of driving displays through Intel, at the moment > not doing that is a huge downgrade in terms of functionality. -Especially- if > these machines were already working in the field as-is. Probably worth noting > I don't think I have yet to actually hear of any complaints about this being > the case, and I'd like to also make sure this isn't a change being done for > one or two vendors when most vendors aren't actually doing something like > this. > > Note that for a lot of systems it won't -technically- be a big difference > since the current situation in the market right now is that a lot of laptops > will have all their external displays routed through the nvidia GPU and > nowhere else. It's not great compared to just being able to use the well > supported Intel GPU for everything though. And if we're controlling display > routing through ACPI, that implies things aren't directly hooked up and > someone went through the hassle of adding a display mux - which kind of seems > like a waste of engineering effort and money if it can't actually be used for > muxing between the two GPUs. Especially considering that up until very > recently muxes had more or less been dropped from the majority of laptop > vendors (I think Dell was an exception for this fwiw). > > Mark, since you're from Lenovo can you help to confirm this as well? I'll have to do some checking for this years models and get back to you I know on last years that we had a HW mux available on the P1. There wasn't one on the P17 (and I'm not sure about the P15). My understanding is the Intel display just wasn't available at all for external display on the P17 (and I do agree with your comments on the wiseness of this!). I believe it was hardwired with no way to switch it - we lost a sale from this, and if there had been an alternative we would have pursued it. I'll confirm with the HW/FW team. We also have lots of users on Legion gaming systems - but unfortunately I don't know what happens on those platforms as they're not in our Linux program. Mark
[Intel-gfx] [PATCH] gpu: move from strlcpy with unused retval to strscpy
Follow the advice of the below link and prefer 'strscpy' in this
subsystem. Conversion is 1:1 because the return value is not used.
Generated by a coccinelle script.
Link:
https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=v6a6g1ouzcprm...@mail.gmail.com/
Signed-off-by: Wolfram Sang
---
drivers/gpu/drm/amd/amdgpu/atom.c | 2 +-
drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c | 2 +-
drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c | 6 +++---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +-
drivers/gpu/drm/display/drm_dp_helper.c | 2 +-
drivers/gpu/drm/display/drm_dp_mst_topology.c | 2 +-
drivers/gpu/drm/drm_mipi_dsi.c | 2 +-
drivers/gpu/drm/i2c/tda998x_drv.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_perf.c | 2 +-
drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c | 2 +-
drivers/gpu/drm/radeon/radeon_atombios.c| 4 ++--
drivers/gpu/drm/radeon/radeon_combios.c | 4 ++--
drivers/gpu/drm/rockchip/inno_hdmi.c| 2 +-
drivers/gpu/drm/rockchip/rk3066_hdmi.c | 2 +-
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c | 2 +-
15 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c
b/drivers/gpu/drm/amd/amdgpu/atom.c
index 1c5d9388ad0b..5f610e9a5f0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -1509,7 +1509,7 @@ struct atom_context *amdgpu_atom_parse(struct card_info
*card, void *bios)
str = CSTR(idx);
if (*str != '\0') {
pr_info("ATOM BIOS: %s\n", str);
- strlcpy(ctx->vbios_version, str, sizeof(ctx->vbios_version));
+ strscpy(ctx->vbios_version, str, sizeof(ctx->vbios_version));
}
atom_rom_header = (struct _ATOM_ROM_HEADER *)CSTR(base);
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
index d3fe149d8476..81fb4e5dd804 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
@@ -794,7 +794,7 @@ void amdgpu_add_thermal_controller(struct amdgpu_device
*adev)
struct i2c_board_info info = { };
const char *name =
pp_lib_thermal_controller_names[controller->ucType];
info.addr = controller->ucI2cAddress >> 1;
- strlcpy(info.type, name, sizeof(info.type));
+ strscpy(info.type, name, sizeof(info.type));
i2c_new_client_device(>pm.i2c_bus->adapter, );
}
} else {
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c
index 7d2ed0ed2fe2..4efb62bcdb63 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c
@@ -542,8 +542,8 @@ static int snd_dw_hdmi_probe(struct platform_device *pdev)
if (ret < 0)
return ret;
- strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
- strlcpy(card->shortname, "DW-HDMI", sizeof(card->shortname));
+ strscpy(card->driver, DRIVER_NAME, sizeof(card->driver));
+ strscpy(card->shortname, "DW-HDMI", sizeof(card->shortname));
snprintf(card->longname, sizeof(card->longname),
"%s rev 0x%02x, irq %d", card->shortname, revision,
data->irq);
@@ -561,7 +561,7 @@ static int snd_dw_hdmi_probe(struct platform_device *pdev)
dw->pcm = pcm;
pcm->private_data = dw;
- strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
+ strscpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, _dw_hdmi_ops);
/*
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 25a60eb4d67c..4f3ae976e677 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -533,7 +533,7 @@ static struct i2c_adapter *dw_hdmi_i2c_adapter(struct
dw_hdmi *hdmi)
adap->owner = THIS_MODULE;
adap->dev.parent = hdmi->dev;
adap->algo = _hdmi_algorithm;
- strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
+ strscpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
i2c_set_adapdata(adap, hdmi);
ret = i2c_add_adapter(adap);
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
b/drivers/gpu/drm/display/drm_dp_helper.c
index e5bab236b3ae..10a39b36a661 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2058,7 +2058,7 @@ int drm_dp_aux_register(struct drm_dp_aux *aux)
aux->ddc.owner = THIS_MODULE;
aux->ddc.dev.parent = aux->dev;
-
Re: [Intel-gfx] [PULL] gvt-fixes
On 17/08/2022 21:07, Vivi, Rodrigo wrote:
On Tue, 2022-08-16 at 12:43 +0800, Zhenyu Wang wrote:
On 2022.08.16 12:05:08 +0800, Zhenyu Wang wrote:
On 2022.08.15 19:32:45 -0400, Rodrigo Vivi wrote:
On Mon, Aug 15, 2022 at 10:38:55AM +0800, Zhenyu Wang wrote:
Hi,
Here's one gvt-fixes pull for 6.0-rc. Major one is Cometlake
regression
fix for mmio table rework, and others are left kernel doc fixes
not pushed yet.
Thanks
--
The following changes since commit
a7a47a5dfa9a9692a41764ee9ab4054f12924a42:
drm/i915/reset: Add additional steps for Wa_22011802037 for
execlist backend (2022-07-25 15:57:54 +0100)
are available in the Git repository at:
https://github.com/intel/gvt-linux.git tags/gvt-fixes-2022-
08-15
for you to fetch changes up to
394f0560a76298842defd1d95bd64b203a5fdcc4:
drm/i915/gvt: Fix Comet Lake (2022-08-15 10:54:03 +0800)
---
-
gvt-fixes-2022-08-15
- CometLake regression fix in mmio table rework (Alex)
- misc kernel doc and typo fixes
---
-
Alex Williamson (1):
drm/i915/gvt: Fix Comet Lake
Colin Ian King (1):
drm/i915/reg: Fix spelling mistake "Unsupport" ->
"Unsupported"
dim: d6632370536d ("drm/i915/reg: Fix spelling mistake
"Unsupport" -> "Unsupported""): committer Signed-off-by missing.
is it possible to fix this in your tree?
Sorry about that. Let me re-generate.
oh, surprise! I just found Colin's email is actually defined in
.mailmap,
so all his commits in kernel are changed for @intel.com address as in
mailmap...
Colin, would you mind to get the Sign-off-by in the patches the same
as your authorship so the tools don't get confused?
(starting with modifying in tree this already merged patch)
Since my patches are generally trivial janitorial fixed done in my spare
time I'm going to get the .mailmap changed to use my gmail email address
rather than my Intel one (since I don't do kernel work in my current role).
This should clean up the confusion. Apologies.
Colin
Thanks,
Rodrigo.
So maybe I can't change that?
Re: [Intel-gfx] [PATCH 1/3] drm: Use original src rect while initializing damage iterator
Hi Jouni,
On 7/15/22 10:49, Jouni Högander wrote:
> drm_plane_state->src might be modified by the driver. This is done
> e.g. in i915 driver when there is bigger framebuffer than the plane
> and there is some offset within framebuffer. I915 driver calculates
> separate offset and adjusts src rect coords to be relative to this
> offset. Damage clips are still relative to original src coords
> provided by user-space.
>
> This patch ensures original coordinates provided by user-space are
> used when initiliazing damage iterator.
>
drm_damage_helper has some KUnit tests on drivers/gpu/drm/tests, and by
applying this patch the drm_damage_helper tests started to fail. Could
you also refactor the drm_damage_helper tests?
To run the tests, you can run:
$ ./tools/testing/kunit/kunit.py run \
--kunitconfig=drivers/gpu/drm/tests \
--kconfig_add CONFIG_UML_PCI_OVER_VIRTIO=y \
--kconfig_add CONFIG_VIRTIO_UML=y
There is also some documentation on the DRM KUnit Tests on [1].
[1] https://docs.kernel.org/gpu/drm-internals.html#unit-testing
Best Regards,
- Maíra Canal
> Signed-off-by: Jouni Högander > ---
> drivers/gpu/drm/drm_damage_helper.c | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_damage_helper.c
> b/drivers/gpu/drm/drm_damage_helper.c
> index 937b699ac2a8..d8b2955e88fd 100644
> --- a/drivers/gpu/drm/drm_damage_helper.c
> +++ b/drivers/gpu/drm/drm_damage_helper.c
> @@ -224,6 +224,7 @@ drm_atomic_helper_damage_iter_init(struct
> drm_atomic_helper_damage_iter *iter,
> const struct drm_plane_state *old_state,
> const struct drm_plane_state *state)
> {
> + struct drm_rect src;
> memset(iter, 0, sizeof(*iter));
>
> if (!state || !state->crtc || !state->fb || !state->visible)
> @@ -233,10 +234,12 @@ drm_atomic_helper_damage_iter_init(struct
> drm_atomic_helper_damage_iter *iter,
> iter->num_clips = drm_plane_get_damage_clips_count(state);
>
> /* Round down for x1/y1 and round up for x2/y2 to catch all pixels */
> - iter->plane_src.x1 = state->src.x1 >> 16;
> - iter->plane_src.y1 = state->src.y1 >> 16;
> - iter->plane_src.x2 = (state->src.x2 >> 16) + !!(state->src.x2 & 0x);
> - iter->plane_src.y2 = (state->src.y2 >> 16) + !!(state->src.y2 & 0x);
> + src = drm_plane_state_src(state);
> +
> + iter->plane_src.x1 = src.x1 >> 16;
> + iter->plane_src.y1 = src.y1 >> 16;
> + iter->plane_src.x2 = (src.x2 >> 16) + !!(src.x2 & 0x);
> + iter->plane_src.y2 = (src.y2 >> 16) + !!(src.y2 & 0x);
>
> if (!iter->clips || !drm_rect_equals(>src, _state->src)) {
> iter->clips = NULL;
[Intel-gfx] [PATCH v3 14/14] drm/i915: move has_dsc to runtime info
If it's modified runtime, it's runtime info.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915/intel_device_info.c | 3 ++-
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
4 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 43e1bbc1e303..bb5c5fa3f157 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -344,7 +344,7 @@ bool intel_dsc_source_support(const struct intel_crtc_state
*crtc_state)
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (!INTEL_INFO(i915)->display.has_dsc)
+ if (!RUNTIME_INFO(i915)->has_dsc)
return false;
if (DISPLAY_VER(i915) >= 12)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4c7c0873b0d5..857e8bb6865c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -833,7 +833,7 @@ static const struct intel_device_info cml_gt2_info = {
ICL_COLORS, \
.display.dbuf.size = 2048, \
.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
- .display.has_dsc = 1, \
+ .__runtime.has_dsc = 1, \
.has_coherent_ggtt = false, \
.has_logical_ring_elsq = 1
@@ -955,7 +955,7 @@ static const struct intel_device_info adl_s_info = {
.__runtime.has_dmc = 1,
\
.display.has_dp_mst = 1,
\
.display.has_dsb = 1,
\
- .display.has_dsc = 1,
\
+ .__runtime.has_dsc = 1,
\
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
\
.display.has_fpga_dbg = 1,
\
.__runtime.has_hdcp = 1,
\
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index b0b37e98b112..0a1f97b35f2b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -128,6 +128,7 @@ void intel_device_info_print(const struct intel_device_info
*info,
drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
+ drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
}
@@ -408,7 +409,7 @@ void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv)
if (DISPLAY_VER(dev_priv) >= 10 &&
(dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
- info->display.has_dsc = 0;
+ runtime->has_dsc = 0;
}
if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index d94fc4ee3805..0e02b48121f5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -181,7 +181,6 @@ enum intel_ppgtt_type {
func(has_ddi); \
func(has_dp_mst); \
func(has_dsb); \
- func(has_dsc); \
func(has_fpga_dbg); \
func(has_gmch); \
func(has_hotplug); \
@@ -241,6 +240,7 @@ struct intel_runtime_info {
bool has_hdcp;
bool has_dmc;
+ bool has_dsc;
};
};
--
2.34.1
[Intel-gfx] [PATCH v3 10/14] drm/i915: move platform_engine_mask to runtime info
If it's modified runtime, it's runtime info.
mock_gem_device() is the only one that modifies it. If that could be
fixed, we wouldn't have to do this.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 58 +--
drivers/gpu/drm/i915/intel_device_info.h | 4 +-
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
5 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 37fa813af766..ca483984d780 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -736,7 +736,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt
*gt)
u16 vdbox_mask;
u16 vebox_mask;
- info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
+ info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
if (GRAPHICS_VER(i915) < 11)
return info->engine_mask;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c3b4fb00351f..8c5a155fb4ac 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -178,7 +178,7 @@
.has_3d_pipeline = 1, \
.hws_needs_physical = 1, \
.unfenced_needs_alignment = 1, \
- .platform_engine_mask = BIT(RCS0), \
+ .__runtime.platform_engine_mask = BIT(RCS0), \
.has_snoop = true, \
.has_coherent_ggtt = false, \
.dma_mask_size = 32, \
@@ -199,7 +199,7 @@
.gpu_reset_clobbers_display = true, \
.hws_needs_physical = 1, \
.unfenced_needs_alignment = 1, \
- .platform_engine_mask = BIT(RCS0), \
+ .__runtime.platform_engine_mask = BIT(RCS0), \
.has_snoop = true, \
.has_coherent_ggtt = false, \
.dma_mask_size = 32, \
@@ -237,7 +237,7 @@ static const struct intel_device_info i865g_info = {
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.display.has_gmch = 1, \
.gpu_reset_clobbers_display = true, \
- .platform_engine_mask = BIT(RCS0), \
+ .__runtime.platform_engine_mask = BIT(RCS0), \
.has_3d_pipeline = 1, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
@@ -329,7 +329,7 @@ static const struct intel_device_info pnv_m_info = {
.display.has_hotplug = 1, \
.display.has_gmch = 1, \
.gpu_reset_clobbers_display = true, \
- .platform_engine_mask = BIT(RCS0), \
+ .__runtime.platform_engine_mask = BIT(RCS0), \
.has_3d_pipeline = 1, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
@@ -362,7 +362,7 @@ static const struct intel_device_info i965gm_info = {
static const struct intel_device_info g45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_G45),
- .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
+ .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
.gpu_reset_clobbers_display = false,
};
@@ -372,7 +372,7 @@ static const struct intel_device_info gm45_info = {
.is_mobile = 1,
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
.display.supports_tv = 1,
- .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
+ .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
.gpu_reset_clobbers_display = false,
};
@@ -381,7 +381,7 @@ static const struct intel_device_info gm45_info = {
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.display.has_hotplug = 1, \
- .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
+ .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
.has_3d_pipeline = 1, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
@@ -413,7 +413,7 @@ static const struct intel_device_info ilk_m_info = {
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.display.has_hotplug = 1, \
.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
- .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
+ .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_3d_pipeline = 1, \
.has_coherent_ggtt = true, \
.has_llc = 1, \
@@ -465,7 +465,7 @@ static const struct intel_device_info snb_m_gt2_info = {
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C), \
.display.has_hotplug = 1, \
.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
- .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
+ .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_3d_pipeline = 1, \
.has_coherent_ggtt = true, \
.has_llc = 1, \
@@ -539,7 +539,7 @@
[Intel-gfx] [PATCH v3 09/14] drm/i915: move memory_regions to runtime info
If it's modified runtime, it's runtime info.
mock_gem_device() is the only one that modifies it. If that could be
fixed, we wouldn't have to do this.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 6 +++---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.h | 4 ++--
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
5 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8e63dbabb6a9..16f5e74713cf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1302,7 +1302,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
-#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
+#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
/*
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index af34a3848c43..c3b4fb00351f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -163,7 +163,7 @@
.__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K
#define GEN_DEFAULT_REGIONS \
- .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
+ .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
#define I830_FEATURES \
GEN(2), \
@@ -909,7 +909,7 @@ static const struct intel_device_info rkl_info = {
};
#define DGFX_FEATURES \
- .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
+ .__runtime.memory_regions = REGION_SMEM | REGION_LMEM |
REGION_STOLEN_LMEM, \
.has_llc = 0, \
.has_pxp = 0, \
.has_snoop = 1, \
@@ -1129,7 +1129,7 @@ static const struct intel_device_info mtl_info = {
.display.has_modular_fia = 1,
.has_flat_ccs = 0,
.has_snoop = 1,
- .memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
+ .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
.require_force_probe = 1,
};
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 21a6ccd7c407..bb16b0ec4ed2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -109,7 +109,7 @@ void intel_device_info_print(const struct intel_device_info
*info,
drm_printf(p, "display version: %u\n", info->display.ver);
drm_printf(p, "gt: %d\n", info->gt);
- drm_printf(p, "memory-regions: %x\n", info->memory_regions);
+ drm_printf(p, "memory-regions: %x\n", runtime->memory_regions);
drm_printf(p, "page-sizes: %x\n", runtime->page_sizes);
drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index fc1bee6bb185..1fd6e6e72680 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -225,6 +225,8 @@ struct intel_runtime_info {
enum intel_ppgtt_type ppgtt_type;
unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
+ u32 memory_regions; /* regions supported by the HW */
+
bool has_pooled_eu;
/* display */
@@ -245,8 +247,6 @@ struct intel_device_info {
unsigned int dma_mask_size; /* available DMA address bits */
- u32 memory_regions; /* regions supported by the HW */
-
u8 gt; /* GT number, 0 if undefined */
#define DEFINE_FLAG(name) u8 name:1
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index b23f11d24b97..2fc3472c414b 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -179,7 +179,7 @@ struct drm_i915_private *mock_gem_device(void)
I915_GTT_PAGE_SIZE_64K |
I915_GTT_PAGE_SIZE_2M;
- mkwrite_device_info(i915)->memory_regions = REGION_SMEM;
+ RUNTIME_INFO(i915)->memory_regions = REGION_SMEM;
intel_memory_regions_hw_probe(i915);
spin_lock_init(>gpu_error.lock);
--
2.34.1
[Intel-gfx] [PATCH v3 08/14] drm/i915: move has_pooled_eu to runtime info
If it's modified runtime, it's runtime info.
Curiously, the flag was never initialized statically.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 5 ++---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 3 ++-
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index c6d3050604c8..66f21c735d54 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -382,7 +382,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
static void gen9_sseu_info_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
- struct intel_device_info *info = mkwrite_device_info(i915);
struct sseu_dev_info *sseu = >info.sseu;
struct intel_uncore *uncore = gt->uncore;
u32 fuse2, eu_disable, subslice_mask;
@@ -471,10 +470,10 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
if (IS_GEN9_LP(i915)) {
#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
- info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
+ RUNTIME_INFO(i915)->has_pooled_eu =
hweight8(sseu->subslice_mask.hsw[0]) == 3;
sseu->min_eu_in_pool = 0;
- if (info->has_pooled_eu) {
+ if (HAS_POOLED_EU(i915)) {
if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
sseu->min_eu_in_pool = 3;
else if (IS_SS_DISABLED(1))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 625954276a70..8e63dbabb6a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1313,7 +1313,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
-#define HAS_POOLED_EU(dev_priv)(INTEL_INFO(dev_priv)->has_pooled_eu)
+#define HAS_POOLED_EU(dev_priv)(RUNTIME_INFO(dev_priv)->has_pooled_eu)
#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)
(INTEL_INFO(dev_priv)->has_global_mocs)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 0efbd8f5fe0e..21a6ccd7c407 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -120,6 +120,8 @@ void intel_device_info_print(const struct intel_device_info
*info,
DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
#undef PRINT_FLAG
+ drm_printf(p, "has_pooled_eu: %s\n",
str_yes_no(runtime->has_pooled_eu));
+
#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name,
str_yes_no(info->display.name))
DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
#undef PRINT_FLAG
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index d18887890e4c..fc1bee6bb185 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -164,7 +164,6 @@ enum intel_ppgtt_type {
func(has_media_ratio_mode); \
func(has_mslice_steering); \
func(has_one_eu_per_fuse_bit); \
- func(has_pooled_eu); \
func(has_pxp); \
func(has_rc6); \
func(has_rc6p); \
@@ -226,6 +225,8 @@ struct intel_runtime_info {
enum intel_ppgtt_type ppgtt_type;
unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
+ bool has_pooled_eu;
+
/* display */
struct {
u8 num_sprites[I915_MAX_PIPES];
--
2.34.1
[Intel-gfx] [PATCH v3 12/14] drm/i915: move has_hdcp to runtime info
If it's modified runtime, it's runtime info.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 4 ++--
drivers/gpu/drm/i915/i915_pci.c | 6 +++---
drivers/gpu/drm/i915/intel_device_info.c | 4 +++-
drivers/gpu/drm/i915/intel_device_info.h | 3 ++-
4 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index c5e9e86bb4cb..73b9b4c3dbe9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1110,8 +1110,8 @@ static void intel_hdcp_prop_work(struct work_struct *work)
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
{
- return INTEL_INFO(dev_priv)->display.has_hdcp &&
- (DISPLAY_VER(dev_priv) >= 12 || port < PORT_E);
+ return RUNTIME_INFO(dev_priv)->has_hdcp &&
+ (DISPLAY_VER(dev_priv) >= 12 || port < PORT_E);
}
static int
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 365cbb80975a..818c18bc0aba 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -656,7 +656,7 @@ static const struct intel_device_info chv_info = {
GEN9_DEFAULT_PAGE_SIZES, \
.display.has_dmc = 1, \
.has_gt_uc = 1, \
- .display.has_hdcp = 1, \
+ .__runtime.has_hdcp = 1, \
.display.has_ipc = 1, \
.display.has_psr = 1, \
.display.has_psr_hw_tracking = 1, \
@@ -708,7 +708,7 @@ static const struct intel_device_info skl_gt4_info = {
.display.has_ddi = 1, \
.display.has_fpga_dbg = 1, \
.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
- .display.has_hdcp = 1, \
+ .__runtime.has_hdcp = 1, \
.display.has_psr = 1, \
.display.has_psr_hw_tracking = 1, \
.has_runtime_pm = 1, \
@@ -958,7 +958,7 @@ static const struct intel_device_info adl_s_info = {
.display.has_dsc = 1,
\
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
\
.display.has_fpga_dbg = 1,
\
- .display.has_hdcp = 1,
\
+ .__runtime.has_hdcp = 1,
\
.display.has_hotplug = 1,
\
.display.has_ipc = 1,
\
.display.has_psr = 1,
\
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 91ac149ad85a..c5367b8344be 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -126,6 +126,8 @@ void intel_device_info_print(const struct intel_device_info
*info,
DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
#undef PRINT_FLAG
+ drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
+
drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
}
@@ -395,7 +397,7 @@ void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv)
}
if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
- info->display.has_hdcp = 0;
+ runtime->has_hdcp = 0;
if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
runtime->fbc_mask = 0;
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index f419848f52cb..7ac24bfbf3ea 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -185,7 +185,6 @@ enum intel_ppgtt_type {
func(has_dsc); \
func(has_fpga_dbg); \
func(has_gmch); \
- func(has_hdcp); \
func(has_hotplug); \
func(has_hti); \
func(has_ipc); \
@@ -240,6 +239,8 @@ struct intel_runtime_info {
u8 num_scalers[I915_MAX_PIPES];
u8 fbc_mask;
+
+ bool has_hdcp;
};
};
--
2.34.1
[Intel-gfx] [PATCH v3 13/14] drm/i915: move has_dmc to runtime info
If it's modified runtime, it's runtime info.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 6 +++---
drivers/gpu/drm/i915/intel_device_info.c | 3 ++-
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
4 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3f3e5ed52937..69ce6db6a7c1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1272,7 +1272,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
-#define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc)
+#define HAS_DMC(dev_priv) (RUNTIME_INFO(dev_priv)->has_dmc)
#define HAS_HECI_PXP(dev_priv) \
(INTEL_INFO(dev_priv)->has_heci_pxp)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 818c18bc0aba..4c7c0873b0d5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -654,7 +654,7 @@ static const struct intel_device_info chv_info = {
GEN8_FEATURES, \
GEN(9), \
GEN9_DEFAULT_PAGE_SIZES, \
- .display.has_dmc = 1, \
+ .__runtime.has_dmc = 1, \
.has_gt_uc = 1, \
.__runtime.has_hdcp = 1, \
.display.has_ipc = 1, \
@@ -712,7 +712,7 @@ static const struct intel_device_info skl_gt4_info = {
.display.has_psr = 1, \
.display.has_psr_hw_tracking = 1, \
.has_runtime_pm = 1, \
- .display.has_dmc = 1, \
+ .__runtime.has_dmc = 1, \
.has_rc6 = 1, \
.has_rps = true, \
.display.has_dp_mst = 1, \
@@ -952,7 +952,7 @@ static const struct intel_device_info adl_s_info = {
.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
\
BIT(DBUF_S4),
\
.display.has_ddi = 1,
\
- .display.has_dmc = 1,
\
+ .__runtime.has_dmc = 1,
\
.display.has_dp_mst = 1,
\
.display.has_dsb = 1,
\
.display.has_dsc = 1,
\
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index c5367b8344be..b0b37e98b112 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -127,6 +127,7 @@ void intel_device_info_print(const struct intel_device_info
*info,
#undef PRINT_FLAG
drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
+ drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
}
@@ -403,7 +404,7 @@ void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv)
runtime->fbc_mask = 0;
if (DISPLAY_VER(dev_priv) >= 11 && (dfsm &
ICL_DFSM_DMC_DISABLE))
- info->display.has_dmc = 0;
+ runtime->has_dmc = 0;
if (DISPLAY_VER(dev_priv) >= 10 &&
(dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 7ac24bfbf3ea..d94fc4ee3805 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -178,7 +178,6 @@ enum intel_ppgtt_type {
/* Keep in alphabetical order */ \
func(cursor_needs_physical); \
func(has_cdclk_crawl); \
- func(has_dmc); \
func(has_ddi); \
func(has_dp_mst); \
func(has_dsb); \
@@ -241,6 +240,7 @@ struct intel_runtime_info {
u8 fbc_mask;
bool has_hdcp;
+ bool has_dmc;
};
};
--
2.34.1
[Intel-gfx] [PATCH v3 07/14] drm/i915: move ppgtt_type and ppgtt_size to runtime info
If it's modified runtime, it's runtime info.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 4 +--
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 36 +--
drivers/gpu/drm/i915/intel_device_info.c | 6 ++--
drivers/gpu/drm/i915/intel_device_info.h | 6 ++--
6 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 8fcffd16bed6..c570cf780079 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1764,8 +1764,8 @@ int i915_gem_huge_page_mock_selftests(void)
return -ENOMEM;
/* Pretend to be a device which supports the 48b PPGTT */
- mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
- mkwrite_device_info(dev_priv)->ppgtt_size = 48;
+ RUNTIME_INFO(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
+ RUNTIME_INFO(dev_priv)->ppgtt_size = 48;
ppgtt = i915_ppgtt_create(to_gt(dev_priv), 0);
if (IS_ERR(ppgtt)) {
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 6ee8d1127016..7ecfa672f738 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -312,7 +312,7 @@ void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt
*gt,
ppgtt->vm.gt = gt;
ppgtt->vm.i915 = i915;
ppgtt->vm.dma = i915->drm.dev;
- ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
+ ppgtt->vm.total = BIT_ULL(RUNTIME_INFO(i915)->ppgtt_size);
ppgtt->vm.lmem_pt_obj_flags = lmem_pt_obj_flags;
dma_resv_init(>vm._resv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3c2de9babf6a..625954276a70 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1210,7 +1210,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
-#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
+#define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
#define HAS_PPGTT(dev_priv) \
(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
#define HAS_FULL_PPGTT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e34a64a247c0..af34a3848c43 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -421,8 +421,8 @@ static const struct intel_device_info ilk_m_info = {
.has_rc6p = 1, \
.has_rps = true, \
.dma_mask_size = 40, \
- .ppgtt_type = INTEL_PPGTT_ALIASING, \
- .ppgtt_size = 31, \
+ .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
+ .__runtime.ppgtt_size = 31, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
ILK_COLORS, \
@@ -474,8 +474,8 @@ static const struct intel_device_info snb_m_gt2_info = {
.has_reset_engine = true, \
.has_rps = true, \
.dma_mask_size = 40, \
- .ppgtt_type = INTEL_PPGTT_ALIASING, \
- .ppgtt_size = 31, \
+ .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
+ .__runtime.ppgtt_size = 31, \
IVB_PIPE_OFFSETS, \
IVB_CURSOR_OFFSETS, \
IVB_COLORS, \
@@ -535,8 +535,8 @@ static const struct intel_device_info vlv_info = {
.display.has_gmch = 1,
.display.has_hotplug = 1,
.dma_mask_size = 40,
- .ppgtt_type = INTEL_PPGTT_ALIASING,
- .ppgtt_size = 31,
+ .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
+ .__runtime.ppgtt_size = 31,
.has_snoop = true,
.has_coherent_ggtt = false,
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
@@ -585,8 +585,8 @@ static const struct intel_device_info hsw_gt3_info = {
GEN(8), \
.has_logical_ring_contexts = 1, \
.dma_mask_size = 39, \
- .ppgtt_type = INTEL_PPGTT_FULL, \
- .ppgtt_size = 48, \
+ .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \
+ .__runtime.ppgtt_size = 48, \
.has_64bit_reloc = 1
#define BDW_PLATFORM \
@@ -633,8 +633,8 @@ static const struct intel_device_info chv_info = {
.has_logical_ring_contexts = 1,
.display.has_gmch = 1,
.dma_mask_size = 39,
- .ppgtt_type = INTEL_PPGTT_FULL,
- .ppgtt_size = 32,
+ .__runtime.ppgtt_type = INTEL_PPGTT_FULL,
+ .__runtime.ppgtt_size = 32,
.has_reset_engine = 1,
.has_snoop = true,
.has_coherent_ggtt = false,
@@ -719,8 +719,8 @@ static const struct intel_device_info skl_gt4_info = {
.has_logical_ring_contexts = 1, \
.has_gt_uc = 1, \
.dma_mask_size = 39, \
- .ppgtt_type = INTEL_PPGTT_FULL, \
- .ppgtt_size =
[Intel-gfx] [PATCH v3 04/14] drm/i915: move graphics.ver and graphics.rel to runtime info
If it's modified runtime, it's runtime info.
mock_gem_device() is the only one that modifies them. If that could be
fixed, we wouldn't have to do this.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/i915_drv.h| 6 +++---
drivers/gpu/drm/i915/i915_pci.c| 18 +-
drivers/gpu/drm/i915/intel_device_info.c | 8
drivers/gpu/drm/i915/intel_device_info.h | 3 ++-
.../gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
5 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b4733c5a01da..02e55199b0e8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -856,9 +856,9 @@ static inline struct intel_gt *to_gt(struct
drm_i915_private *i915)
#define IP_VER(ver, rel) ((ver) << 8 | (rel))
-#define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics.ver)
-#define GRAPHICS_VER_FULL(i915)
IP_VER(INTEL_INFO(i915)->graphics.ver, \
- INTEL_INFO(i915)->graphics.rel)
+#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ver)
+#define GRAPHICS_VER_FULL(i915)
IP_VER(RUNTIME_INFO(i915)->graphics.ver, \
+ RUNTIME_INFO(i915)->graphics.rel)
#define IS_GRAPHICS_VER(i915, from, until) \
(GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d8446bb25d5e..5758438d52be 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -34,7 +34,7 @@
#define PLATFORM(x) .platform = (x)
#define GEN(x) \
- .graphics.ver = (x), \
+ .__runtime.graphics.ver = (x), \
.media.ver = (x), \
.display.ver = (x)
@@ -919,7 +919,7 @@ static const struct intel_device_info rkl_info = {
static const struct intel_device_info dg1_info = {
GEN12_FEATURES,
DGFX_FEATURES,
- .graphics.rel = 10,
+ .__runtime.graphics.rel = 10,
PLATFORM(INTEL_DG1),
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) |
BIT(PIPE_D),
.require_force_probe = 1,
@@ -1006,8 +1006,8 @@ static const struct intel_device_info adl_p_info = {
I915_GTT_PAGE_SIZE_2M
#define XE_HP_FEATURES \
- .graphics.ver = 12, \
- .graphics.rel = 50, \
+ .__runtime.graphics.ver = 12, \
+ .__runtime.graphics.rel = 50, \
XE_HP_PAGE_SIZES, \
.dma_mask_size = 46, \
.has_3d_pipeline = 1, \
@@ -1053,7 +1053,7 @@ static const struct intel_device_info xehpsdv_info = {
XE_HP_FEATURES, \
XE_HPM_FEATURES, \
DGFX_FEATURES, \
- .graphics.rel = 55, \
+ .__runtime.graphics.rel = 55, \
.media.rel = 55, \
PLATFORM(INTEL_DG2), \
.has_4tile = 1, \
@@ -1096,7 +1096,7 @@ static const struct intel_device_info pvc_info = {
XE_HPC_FEATURES,
XE_HPM_FEATURES,
DGFX_FEATURES,
- .graphics.rel = 60,
+ .__runtime.graphics.rel = 60,
.media.rel = 60,
PLATFORM(INTEL_PONTEVECCHIO),
.display = { 0 },
@@ -1122,8 +1122,8 @@ static const struct intel_device_info mtl_info = {
* Real graphics IP version will be obtained from hardware GMD_ID
* register. Value provided here is just for sanity checking.
*/
- .graphics.ver = 12,
- .graphics.rel = 70,
+ .__runtime.graphics.ver = 12,
+ .__runtime.graphics.rel = 70,
.media.ver = 13,
PLATFORM(INTEL_METEORLAKE),
.display.has_modular_fia = 1,
@@ -1280,7 +1280,7 @@ bool i915_pci_resource_valid(struct pci_dev *pdev, int
bar)
static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct
intel_device_info *intel_info)
{
- int gttmmaddr_bar = intel_info->graphics.ver == 2 ? GEN2_GTTMMADR_BAR :
GTTMMADR_BAR;
+ int gttmmaddr_bar = intel_info->__runtime.graphics.ver == 2 ?
GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
return i915_pci_resource_valid(pdev, gttmmaddr_bar);
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 7793ce243981..15f5723a140f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -92,11 +92,11 @@ void intel_device_info_print(const struct intel_device_info
*info,
const struct intel_runtime_info *runtime,
struct drm_printer *p)
{
- if (info->graphics.rel)
- drm_printf(p, "graphics version: %u.%02u\n", info->graphics.ver,
- info->graphics.rel);
+ if (runtime->graphics.rel)
+ drm_printf(p, "graphics version: %u.%02u\n",
runtime->graphics.ver,
+ runtime->graphics.rel);
[Intel-gfx] [PATCH v3 06/14] drm/i915: move page_sizes to runtime info
If it's modified runtime, it's runtime info.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c| 14 +++---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
drivers/gpu/drm/i915/i915_gem.c| 3 +--
drivers/gpu/drm/i915/i915_pci.c| 18 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.h | 4 ++--
.../gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
8 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 8357dbdcab5c..458e4f9c05f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -20,7 +20,7 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj,
unsigned int sg_page_sizes)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- unsigned long supported = INTEL_INFO(i915)->page_sizes;
+ unsigned long supported = RUNTIME_INFO(i915)->page_sizes;
bool shrinkable;
int i;
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 72ce2c9f42fd..8fcffd16bed6 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -358,7 +358,7 @@ fake_huge_pages_object(struct drm_i915_private *i915, u64
size, bool single)
static int igt_check_page_sizes(struct i915_vma *vma)
{
struct drm_i915_private *i915 = vma->vm->i915;
- unsigned int supported = INTEL_INFO(i915)->page_sizes;
+ unsigned int supported = RUNTIME_INFO(i915)->page_sizes;
struct drm_i915_gem_object *obj = vma->obj;
int err;
@@ -419,7 +419,7 @@ static int igt_mock_exhaust_device_supported_pages(void
*arg)
{
struct i915_ppgtt *ppgtt = arg;
struct drm_i915_private *i915 = ppgtt->vm.i915;
- unsigned int saved_mask = INTEL_INFO(i915)->page_sizes;
+ unsigned int saved_mask = RUNTIME_INFO(i915)->page_sizes;
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
int i, j, single;
@@ -438,7 +438,7 @@ static int igt_mock_exhaust_device_supported_pages(void
*arg)
combination |= page_sizes[j];
}
- mkwrite_device_info(i915)->page_sizes = combination;
+ RUNTIME_INFO(i915)->page_sizes = combination;
for (single = 0; single <= 1; ++single) {
obj = fake_huge_pages_object(i915, combination,
!!single);
@@ -485,7 +485,7 @@ static int igt_mock_exhaust_device_supported_pages(void
*arg)
out_put:
i915_gem_object_put(obj);
out_device:
- mkwrite_device_info(i915)->page_sizes = saved_mask;
+ RUNTIME_INFO(i915)->page_sizes = saved_mask;
return err;
}
@@ -495,7 +495,7 @@ static int igt_mock_memory_region_huge_pages(void *arg)
const unsigned int flags[] = { 0, I915_BO_ALLOC_CONTIGUOUS };
struct i915_ppgtt *ppgtt = arg;
struct drm_i915_private *i915 = ppgtt->vm.i915;
- unsigned long supported = INTEL_INFO(i915)->page_sizes;
+ unsigned long supported = RUNTIME_INFO(i915)->page_sizes;
struct intel_memory_region *mem;
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
@@ -573,7 +573,7 @@ static int igt_mock_ppgtt_misaligned_dma(void *arg)
{
struct i915_ppgtt *ppgtt = arg;
struct drm_i915_private *i915 = ppgtt->vm.i915;
- unsigned long supported = INTEL_INFO(i915)->page_sizes;
+ unsigned long supported = RUNTIME_INFO(i915)->page_sizes;
struct drm_i915_gem_object *obj;
int bit;
int err;
@@ -1390,7 +1390,7 @@ static int igt_ppgtt_smoke_huge(void *arg)
static int igt_ppgtt_sanity_check(void *arg)
{
struct drm_i915_private *i915 = arg;
- unsigned int supported = INTEL_INFO(i915)->page_sizes;
+ unsigned int supported = RUNTIME_INFO(i915)->page_sizes;
struct {
igt_create_fn fn;
unsigned int flags;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 043324fed366..3c2de9babf6a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1218,7 +1218,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
GEM_BUG_ON((sizes) == 0); \
- ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
+ ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
})
#define HAS_OVERLAY(dev_priv)
(INTEL_INFO(dev_priv)->display.has_overlay)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 702e5b89be22..4b76051312dd 100644
---
[Intel-gfx] [PATCH v3 05/14] drm/i915: move fbc_mask to runtime info
If it's modified runtime, it's runtime info.
v2: Rebase on mtl fbc_mask
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++---
.../drm/i915/display/skl_universal_plane.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 24 +--
drivers/gpu/drm/i915/intel_device_info.c | 6 ++---
drivers/gpu/drm/i915/intel_device_info.h | 12 ++
6 files changed, 28 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7436b35f7ea0..0ece995ae766 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -55,7 +55,7 @@
#define for_each_fbc_id(__dev_priv, __fbc_id) \
for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS;
(__fbc_id)++) \
- for_each_if(INTEL_INFO(__dev_priv)->display.fbc_mask &
BIT(__fbc_id))
+ for_each_if(RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
for_each_fbc_id((__dev_priv), (__fbc_id)) \
@@ -1710,10 +1710,10 @@ void intel_fbc_init(struct drm_i915_private *i915)
enum intel_fbc_id fbc_id;
if (!drm_mm_initialized(>mm.stolen))
- mkwrite_device_info(i915)->display.fbc_mask = 0;
+ RUNTIME_INFO(i915)->fbc_mask = 0;
if (need_fbc_vtd_wa(i915))
- mkwrite_device_info(i915)->display.fbc_mask = 0;
+ RUNTIME_INFO(i915)->fbc_mask = 0;
i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
drm_dbg_kms(>drm, "Sanitized enable_fbc value: %d\n",
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 4d6a27757065..bcfde81e4d08 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1928,7 +1928,7 @@ static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe
pipe)
static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
enum intel_fbc_id fbc_id, enum plane_id plane_id)
{
- if ((INTEL_INFO(dev_priv)->display.fbc_mask & BIT(fbc_id)) == 0)
+ if ((RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)
return false;
return plane_id == PLANE_PRIMARY;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 02e55199b0e8..043324fed366 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1249,7 +1249,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define I915_HAS_HOTPLUG(dev_priv)
(INTEL_INFO(dev_priv)->display.has_hotplug)
#define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2)
-#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.fbc_mask != 0)
+#define HAS_FBC(dev_priv) (RUNTIME_INFO(dev_priv)->fbc_mask != 0)
#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv)
>= 7)
#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5758438d52be..97e8ee470728 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -222,13 +222,13 @@ static const struct intel_device_info i845g_info = {
static const struct intel_device_info i85x_info = {
I830_FEATURES,
PLATFORM(INTEL_I85X),
- .display.fbc_mask = BIT(INTEL_FBC_A),
+ .__runtime.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_device_info i865g_info = {
I845_FEATURES,
PLATFORM(INTEL_I865G),
- .display.fbc_mask = BIT(INTEL_FBC_A),
+ .__runtime.fbc_mask = BIT(INTEL_FBC_A),
};
#define GEN3_FEATURES \
@@ -267,7 +267,7 @@ static const struct intel_device_info i915gm_info = {
.display.has_overlay = 1,
.display.overlay_needs_physical = 1,
.display.supports_tv = 1,
- .display.fbc_mask = BIT(INTEL_FBC_A),
+ .__runtime.fbc_mask = BIT(INTEL_FBC_A),
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -292,7 +292,7 @@ static const struct intel_device_info i945gm_info = {
.display.has_overlay = 1,
.display.overlay_needs_physical = 1,
.display.supports_tv = 1,
- .display.fbc_mask = BIT(INTEL_FBC_A),
+ .__runtime.fbc_mask = BIT(INTEL_FBC_A),
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -352,7 +352,7 @@ static const struct intel_device_info i965gm_info = {
GEN4_FEATURES,
PLATFORM(INTEL_I965GM),
.is_mobile = 1,
- .display.fbc_mask = BIT(INTEL_FBC_A),
+ .__runtime.fbc_mask = BIT(INTEL_FBC_A),
.display.has_overlay = 1,
.display.supports_tv = 1,
.hws_needs_physical = 1,
@@
[Intel-gfx] [PATCH v3 03/14] drm/i915: add initial runtime info into device info
Add initial runtime info that we can copy to runtime info at i915
creation time. This lets us define the initial values for runtime info
statically while making it possible to change them runtime. This will be
the new home for the current "const" device info members that are
modified runtime anyway.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/i915_driver.c | 7 +++-
drivers/gpu/drm/i915/intel_device_info.h | 41 +---
2 files changed, 29 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index 563797d5e6e1..1332c70370a6 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -814,6 +814,7 @@ i915_driver_create(struct pci_dev *pdev, const struct
pci_device_id *ent)
const struct intel_device_info *match_info =
(struct intel_device_info *)ent->driver_data;
struct intel_device_info *device_info;
+ struct intel_runtime_info *runtime;
struct drm_i915_private *i915;
i915 = devm_drm_dev_alloc(>dev, _drm_driver,
@@ -829,7 +830,11 @@ i915_driver_create(struct pci_dev *pdev, const struct
pci_device_id *ent)
/* Setup the write-once "constant" device info */
device_info = mkwrite_device_info(i915);
memcpy(device_info, match_info, sizeof(*device_info));
- RUNTIME_INFO(i915)->device_id = pdev->device;
+
+ /* Initialize initial runtime info from static const data and pdev. */
+ runtime = RUNTIME_INFO(i915);
+ memcpy(runtime, _INFO(i915)->__runtime, sizeof(*runtime));
+ runtime->device_id = pdev->device;
return i915;
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index b2fb9440e952..4f4d1d77925a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -202,6 +202,27 @@ struct ip_version {
u8 rel;
};
+struct intel_runtime_info {
+ /*
+* Platform mask is used for optimizing or-ed IS_PLATFORM calls into
+* into single runtime conditionals, and also to provide groundwork
+* for future per platform, or per SKU build optimizations.
+*
+* Array can be extended when necessary if the corresponding
+* BUILD_BUG_ON is hit.
+*/
+ u32 platform_mask[2];
+
+ u16 device_id;
+
+ u8 num_sprites[I915_MAX_PIPES];
+ u8 num_scalers[I915_MAX_PIPES];
+
+ u32 rawclk_freq;
+
+ struct intel_step_info step;
+};
+
struct intel_device_info {
struct ip_version graphics;
struct ip_version media;
@@ -258,27 +279,11 @@ struct intel_device_info {
u32 gamma_lut_tests;
} color;
} display;
-};
-struct intel_runtime_info {
/*
-* Platform mask is used for optimizing or-ed IS_PLATFORM calls into
-* into single runtime conditionals, and also to provide groundwork
-* for future per platform, or per SKU build optimizations.
-*
-* Array can be extended when necessary if the corresponding
-* BUILD_BUG_ON is hit.
+* Initial runtime info. Do not access outside of i915_driver_create().
*/
- u32 platform_mask[2];
-
- u16 device_id;
-
- u8 num_sprites[I915_MAX_PIPES];
- u8 num_scalers[I915_MAX_PIPES];
-
- u32 rawclk_freq;
-
- struct intel_step_info step;
+ const struct intel_runtime_info __runtime;
};
struct intel_driver_caps {
--
2.34.1
[Intel-gfx] [PATCH v3 02/14] drm/i915: combine device info printing into one
We'll be moving info between static and runtime info. Combine the
printing functions into one to keep the output sensible and (mostly)
unchanged in the process.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +--
drivers/gpu/drm/i915/i915_driver.c | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c| 3 +--
drivers/gpu/drm/i915/intel_device_info.c | 11 ---
drivers/gpu/drm/i915/intel_device_info.h | 7 +++
5 files changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 94e5c29d2ee3..d131703de3d9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -66,8 +66,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
- intel_device_info_print_static(INTEL_INFO(i915), );
- intel_device_info_print_runtime(RUNTIME_INFO(i915), );
+ intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), );
i915_print_iommu_status(i915, );
intel_gt_info_print(_gt(i915)->info, );
intel_driver_caps_print(>caps, );
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index deb8a8b76965..563797d5e6e1 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -793,8 +793,8 @@ static void i915_welcome_messages(struct drm_i915_private
*dev_priv)
INTEL_INFO(dev_priv)->platform),
GRAPHICS_VER(dev_priv));
- intel_device_info_print_static(INTEL_INFO(dev_priv), );
- intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), );
+ intel_device_info_print(INTEL_INFO(dev_priv),
+ RUNTIME_INFO(dev_priv), );
i915_print_iommu_status(dev_priv, );
intel_gt_info_print(_gt(dev_priv)->info, );
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 543ba63f958e..b5fbc2252784 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -646,8 +646,7 @@ static void err_print_capabilities(struct
drm_i915_error_state_buf *m,
{
struct drm_printer p = i915_error_printer(m);
- intel_device_info_print_static(>device_info, );
- intel_device_info_print_runtime(>runtime_info, );
+ intel_device_info_print(>device_info, >runtime_info, );
intel_driver_caps_print(>driver_caps, );
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index d98fbbd589aa..7793ce243981 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -88,8 +88,9 @@ const char *intel_platform_name(enum intel_platform platform)
return platform_names[platform];
}
-void intel_device_info_print_static(const struct intel_device_info *info,
- struct drm_printer *p)
+void intel_device_info_print(const struct intel_device_info *info,
+const struct intel_runtime_info *runtime,
+struct drm_printer *p)
{
if (info->graphics.rel)
drm_printf(p, "graphics version: %u.%02u\n", info->graphics.ver,
@@ -122,12 +123,8 @@ void intel_device_info_print_static(const struct
intel_device_info *info,
#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name,
str_yes_no(info->display.name))
DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
#undef PRINT_FLAG
-}
-void intel_device_info_print_runtime(const struct intel_runtime_info *info,
-struct drm_printer *p)
-{
- drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
+ drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
}
#undef INTEL_VGA_DEVICE
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 23bf230aa104..b2fb9440e952 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -291,10 +291,9 @@ const char *intel_platform_name(enum intel_platform
platform);
void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
-void intel_device_info_print_static(const struct intel_device_info *info,
- struct drm_printer *p);
-void intel_device_info_print_runtime(const struct intel_runtime_info *info,
-struct drm_printer *p);
+void intel_device_info_print(const struct intel_device_info *info,
+const struct intel_runtime_info *runtime,
+struct drm_printer *p);
void
[Intel-gfx] [PATCH v3 01/14] drm/i915/guc: remove runtime info printing from time stamp logging
Commit 368d179adbac ("drm/i915/guc: Add GuC <-> kernel time stamp
translation information") added intel_device_info_print_runtime() in the
time info dump for no obvious reason or explanation in the commit
message. It only logs the rawclk freq. Remove it.
Cc: John Harrison
Cc: Alan Previn
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 01f2705cb94a..24451d000a6a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -365,8 +365,6 @@ void intel_guc_dump_time_info(struct intel_guc *guc, struct
drm_printer *p)
u32 stamp = 0;
u64 ktime;
- intel_device_info_print_runtime(RUNTIME_INFO(gt->i915), p);
-
with_intel_runtime_pm(>i915->runtime_pm, wakeref)
stamp = intel_uncore_read(gt->uncore, GUCPMTIMESTAMP);
ktime = ktime_get_boottime_ns();
--
2.34.1
[Intel-gfx] [PATCH v3 00/14] drm/i915: stop modifying "const" device info
v3 of https://patchwork.freedesktop.org/series/105358/ Add a patch resolving guc time stamp logging related conflicts in the front, and remove the last two patches, for now, to avoid any potentially regressing functional changes. Leave them for later. Jani Nikula (14): drm/i915/guc: remove runtime info printing from time stamp logging drm/i915: combine device info printing into one drm/i915: add initial runtime info into device info drm/i915: move graphics.ver and graphics.rel to runtime info drm/i915: move fbc_mask to runtime info drm/i915: move page_sizes to runtime info drm/i915: move ppgtt_type and ppgtt_size to runtime info drm/i915: move has_pooled_eu to runtime info drm/i915: move memory_regions to runtime info drm/i915: move platform_engine_mask to runtime info drm/i915: move pipe_mask and cpu_transcoder_mask to runtime info drm/i915: move has_hdcp to runtime info drm/i915: move has_dmc to runtime info drm/i915: move has_dsc to runtime info drivers/gpu/drm/i915/display/intel_display.h | 4 +- drivers/gpu/drm/i915/display/intel_fbc.c | 6 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 4 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +- .../drm/i915/display/skl_universal_plane.c| 2 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 18 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_sseu.c | 5 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 - drivers/gpu/drm/i915/i915_debugfs.c | 3 +- drivers/gpu/drm/i915/i915_driver.c| 11 +- drivers/gpu/drm/i915/i915_drv.h | 24 +- drivers/gpu/drm/i915/i915_gem.c | 3 +- drivers/gpu/drm/i915/i915_gpu_error.c | 3 +- drivers/gpu/drm/i915/i915_pci.c | 242 +- drivers/gpu/drm/i915/intel_device_info.c | 71 ++--- drivers/gpu/drm/i915/intel_device_info.h | 82 +++--- drivers/gpu/drm/i915/intel_uncore.c | 2 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 8 +- 21 files changed, 256 insertions(+), 242 deletions(-) -- 2.34.1
Re: [Intel-gfx] [PATCH v3] drm/i915/pxp: don't start pxp without mei_pxp bind
On 18.08.2022 19:42, Juston Li wrote:
pxp will not start correctly until after mei_pxp bind completes and
intel_pxp_init_hw() is called.
Wait for the bind to complete before proceeding with startup.
This fixes a race condition during bootup where we observed a small
window for pxp commands to be sent, starting pxp before mei_pxp bind
completed.
Changes since v2:
- wait for pxp_component to bind instead of returning -EAGAIN (Daniele)
Changes since v1:
- check pxp_component instead of pxp_component_added (Daniele)
- pxp_component needs tee_mutex (Daniele)
- return -EAGAIN so caller knows to retry (Daniele)
Signed-off-by: Juston Li
In typical usage of component framework driver postpones initialization
till component is bound. In such case checking/waiting for component as
in this patch is not necessary and the code is more straightforward.
I wonder how it behaves on component unbind.
Anyway:
Reviewed-by: Andrzej Hajda
Regards
Andrzej
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 15311eaed848..17109c513259 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -176,6 +176,18 @@ static void pxp_queue_termination(struct intel_pxp *pxp)
spin_unlock_irq(>irq_lock);
}
+static bool pxp_component_bound(struct intel_pxp *pxp)
+{
+ bool bound = false;
+
+ mutex_lock(>tee_mutex);
+ if (pxp->pxp_component)
+ bound = true;
+ mutex_unlock(>tee_mutex);
+
+ return bound;
+}
+
/*
* the arb session is restarted from the irq work when we receive the
* termination completion interrupt
@@ -187,6 +199,9 @@ int intel_pxp_start(struct intel_pxp *pxp)
if (!intel_pxp_is_enabled(pxp))
return -ENODEV;
+ if (wait_for(pxp_component_bound(pxp), 250))
+ return -ENXIO;
+
mutex_lock(>arb_mutex);
if (pxp->arb_is_valid)
Re: [Intel-gfx] [PATCH 1/7] drm/i915/hwmon: Add HWMON infrastructure
On Fri, Aug 19, 2022 at 01:35:52PM +0300, Jani Nikula wrote:
> On Fri, 19 Aug 2022, Badal Nilawar wrote:
> > From: Dale B Stimson
> >
> > The i915 HWMON module will be used to expose voltage, power and energy
> > values for dGfx. Here we set up i915 hwmon infrastructure including i915
> > hwmon registration, basic data structures and functions.
> >
> > v2:
> > - Create HWMON infra patch (Ashutosh)
> > - Fixed review comments (Jani)
> > - Remove "select HWMON" from i915/Kconfig (Jani)
> > v3: Use hwm_ prefix for static functions (Ashutosh)
> > v4: s/#ifdef CONFIG_HWMON/#if IS_REACHABLE(CONFIG_HWMON)/ since the former
> > doesn't work if hwmon is compiled as a module (Guenter)
>
> Is this really what we want to do?
>
> In my books, it's a misconfiguration to have CONFIG_HWMON=m with
> CONFIG_DRM_I915=y. That's really the problematic combo, not just
> CONFIG_HWMON=m, right? Why do we allow it at the kconfig level, and then
> have ugly hacks around it at the code level? Especially as
> CONFIG_DRM_I915=y should really be thought of as a corner case.
>
> So why not do this in i915 Kconfig:
>
> config DRM_I915
> ...
> depends on HWMON || HWMON=n
>
Ok with me, but not my call to make. The ifdef should then use
IS_ENABLED(), though.
Guenter
> Which rejects the CONFIG_HWMON=m && CONFIG_DRM_I915=y combo.
>
> >
> > Cc: Guenter Roeck
> > Signed-off-by: Dale B Stimson
> > Signed-off-by: Ashutosh Dixit
> > Signed-off-by: Riana Tauro
> > Signed-off-by: Badal Nilawar
> > ---
> > drivers/gpu/drm/i915/Makefile | 3 +
> > drivers/gpu/drm/i915/i915_driver.c | 7 ++
> > drivers/gpu/drm/i915/i915_drv.h| 2 +
> > drivers/gpu/drm/i915/i915_hwmon.c | 135 +
> > drivers/gpu/drm/i915/i915_hwmon.h | 20 +
> > 5 files changed, 167 insertions(+)
> > create mode 100644 drivers/gpu/drm/i915/i915_hwmon.c
> > create mode 100644 drivers/gpu/drm/i915/i915_hwmon.h
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > index 522ef9b4aff3..2b235f747490 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -208,6 +208,9 @@ i915-y += gt/uc/intel_uc.o \
> > # graphics system controller (GSC) support
> > i915-y += gt/intel_gsc.o
> >
> > +# graphics hardware monitoring (HWMON) support
> > +i915-$(CONFIG_HWMON) += i915_hwmon.o
>
> Moreover, this builds i915_hwmon.o as part of i915.ko (or kernel as it's
> builtin) even if we can't use it!
>
>
> BR,
> Jani.
>
>
> > +
> > # modesetting core code
> > i915-y += \
> > display/hsw_ips.o \
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> > b/drivers/gpu/drm/i915/i915_driver.c
> > index deb8a8b76965..62340cd01dde 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -80,6 +80,7 @@
> > #include "i915_drm_client.h"
> > #include "i915_drv.h"
> > #include "i915_getparam.h"
> > +#include "i915_hwmon.h"
> > #include "i915_ioc32.h"
> > #include "i915_ioctl.h"
> > #include "i915_irq.h"
> > @@ -736,6 +737,9 @@ static void i915_driver_register(struct
> > drm_i915_private *dev_priv)
> >
> > intel_gt_driver_register(to_gt(dev_priv));
> >
> > +#if IS_REACHABLE(CONFIG_HWMON)
> > + i915_hwmon_register(dev_priv);
> > +#endif
> > intel_display_driver_register(dev_priv);
> >
> > intel_power_domains_enable(dev_priv);
> > @@ -762,6 +766,9 @@ static void i915_driver_unregister(struct
> > drm_i915_private *dev_priv)
> >
> > intel_display_driver_unregister(dev_priv);
> >
> > +#if IS_REACHABLE(CONFIG_HWMON)
> > + i915_hwmon_unregister(dev_priv);
> > +#endif
> > intel_gt_driver_unregister(to_gt(dev_priv));
> >
> > i915_perf_unregister(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 086bbe8945d6..d437d588dec9 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -705,6 +705,8 @@ struct drm_i915_private {
> >
> > struct i915_perf perf;
> >
> > + struct i915_hwmon *hwmon;
> > +
> > /* Abstract the submission mechanism (legacy ringbuffer or execlists)
> > away */
> > struct intel_gt gt0;
> >
> > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
> > b/drivers/gpu/drm/i915/i915_hwmon.c
> > new file mode 100644
> > index ..5b80a0f024f0
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> > @@ -0,0 +1,135 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2022 Intel Corporation
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +
> > +#include "i915_drv.h"
> > +#include "i915_hwmon.h"
> > +#include "intel_mchbar_regs.h"
> > +
> > +struct hwm_reg {
> > +};
> > +
> > +struct hwm_drvdata {
> > + struct i915_hwmon *hwmon;
> > + struct intel_uncore *uncore;
> > + struct device *hwmon_dev;
> > + char name[12];
> > +};
> > +
> > +struct i915_hwmon {
> > + struct hwm_drvdata ddat;
> > +
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pxp: don't start pxp without mei_pxp bind (rev3)
== Series Details == Series: drm/i915/pxp: don't start pxp without mei_pxp bind (rev3) URL : https://patchwork.freedesktop.org/series/107099/ State : success == Summary == CI Bug Log - changes from CI_DRM_11998_full -> Patchwork_107099v3_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_107099v3_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107099v3_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (13 -> 11) -- Missing(2): pig-glk-j5005 shard-dg1 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_107099v3_full: ### IGT changes ### Warnings * igt@gem_eio@in-flight-suspend: - shard-apl: [INCOMPLETE][1] ([i915#6598]) -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11998/shard-apl7/igt@gem_...@in-flight-suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107099v3/shard-apl6/igt@gem_...@in-flight-suspend.html Known issues Here are the changes found in Patchwork_107099v3_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@wait-wedge-1us: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#5904] / [i915#62]) +10 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11998/shard-apl3/igt@gem_...@wait-wedge-1us.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107099v3/shard-apl8/igt@gem_...@wait-wedge-1us.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11998/shard-apl3/igt@gem_exec_fair@basic-none-s...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107099v3/shard-apl2/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11998/shard-kbl7/igt@gem_exec_fair@basic-n...@vecs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107099v3/shard-kbl7/igt@gem_exec_fair@basic-n...@vecs0.html * igt@i915_selftest@live@hangcheck: - shard-tglb: [PASS][9] -> [DMESG-WARN][10] ([i915#5591]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11998/shard-tglb7/igt@i915_selftest@l...@hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107099v3/shard-tglb3/igt@i915_selftest@l...@hangcheck.html * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#3886]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107099v3/shard-apl2/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html * igt@kms_chamelium@dp-hpd-storm-disable: - shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107099v3/shard-apl2/igt@kms_chamel...@dp-hpd-storm-disable.html * igt@kms_color@legacy-gamma@pipe-b-dp-1: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180] / [i915#5904] / [i915#62]) +19 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11998/shard-apl3/igt@kms_color@legacy-ga...@pipe-b-dp-1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107099v3/shard-apl8/igt@kms_color@legacy-ga...@pipe-b-dp-1.html * igt@kms_cursor_crc@cursor-rapid-movement@pipe-a-dp-1-128x128: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#62]) +75 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11998/shard-apl7/igt@kms_cursor_crc@cursor-rapid-movem...@pipe-a-dp-1-128x128.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107099v3/shard-apl8/igt@kms_cursor_crc@cursor-rapid-movem...@pipe-a-dp-1-128x128.html * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-4tiled: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271]) +32 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107099v3/shard-apl2/igt@kms_draw_...@draw-method-rgb565-mmap-wc-4tiled.html * igt@kms_flip@flip-vs-wf_vblank-interruptible@a-dp1: - shard-apl: [PASS][18] -> [DMESG-WARN][19] ([i915#180] / [i915#1982] / [i915#5904] / [i915#62]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11998/shard-apl3/igt@kms_flip@flip-vs-wf_vblank-interrupti...@a-dp1.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107099v3/shard-apl8/igt@kms_flip@flip-vs-wf_vblank-interrupti...@a-dp1.html *
Re: [Intel-gfx] [PATCH 1/7] drm/i915/hwmon: Add HWMON infrastructure
On Fri, 19 Aug 2022, Badal Nilawar wrote:
> From: Dale B Stimson
>
> The i915 HWMON module will be used to expose voltage, power and energy
> values for dGfx. Here we set up i915 hwmon infrastructure including i915
> hwmon registration, basic data structures and functions.
>
> v2:
> - Create HWMON infra patch (Ashutosh)
> - Fixed review comments (Jani)
> - Remove "select HWMON" from i915/Kconfig (Jani)
> v3: Use hwm_ prefix for static functions (Ashutosh)
> v4: s/#ifdef CONFIG_HWMON/#if IS_REACHABLE(CONFIG_HWMON)/ since the former
> doesn't work if hwmon is compiled as a module (Guenter)
Is this really what we want to do?
In my books, it's a misconfiguration to have CONFIG_HWMON=m with
CONFIG_DRM_I915=y. That's really the problematic combo, not just
CONFIG_HWMON=m, right? Why do we allow it at the kconfig level, and then
have ugly hacks around it at the code level? Especially as
CONFIG_DRM_I915=y should really be thought of as a corner case.
So why not do this in i915 Kconfig:
config DRM_I915
...
depends on HWMON || HWMON=n
Which rejects the CONFIG_HWMON=m && CONFIG_DRM_I915=y combo.
>
> Cc: Guenter Roeck
> Signed-off-by: Dale B Stimson
> Signed-off-by: Ashutosh Dixit
> Signed-off-by: Riana Tauro
> Signed-off-by: Badal Nilawar
> ---
> drivers/gpu/drm/i915/Makefile | 3 +
> drivers/gpu/drm/i915/i915_driver.c | 7 ++
> drivers/gpu/drm/i915/i915_drv.h| 2 +
> drivers/gpu/drm/i915/i915_hwmon.c | 135 +
> drivers/gpu/drm/i915/i915_hwmon.h | 20 +
> 5 files changed, 167 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/i915_hwmon.c
> create mode 100644 drivers/gpu/drm/i915/i915_hwmon.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 522ef9b4aff3..2b235f747490 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -208,6 +208,9 @@ i915-y += gt/uc/intel_uc.o \
> # graphics system controller (GSC) support
> i915-y += gt/intel_gsc.o
>
> +# graphics hardware monitoring (HWMON) support
> +i915-$(CONFIG_HWMON) += i915_hwmon.o
Moreover, this builds i915_hwmon.o as part of i915.ko (or kernel as it's
builtin) even if we can't use it!
BR,
Jani.
> +
> # modesetting core code
> i915-y += \
> display/hsw_ips.o \
> diff --git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
> index deb8a8b76965..62340cd01dde 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -80,6 +80,7 @@
> #include "i915_drm_client.h"
> #include "i915_drv.h"
> #include "i915_getparam.h"
> +#include "i915_hwmon.h"
> #include "i915_ioc32.h"
> #include "i915_ioctl.h"
> #include "i915_irq.h"
> @@ -736,6 +737,9 @@ static void i915_driver_register(struct drm_i915_private
> *dev_priv)
>
> intel_gt_driver_register(to_gt(dev_priv));
>
> +#if IS_REACHABLE(CONFIG_HWMON)
> + i915_hwmon_register(dev_priv);
> +#endif
> intel_display_driver_register(dev_priv);
>
> intel_power_domains_enable(dev_priv);
> @@ -762,6 +766,9 @@ static void i915_driver_unregister(struct
> drm_i915_private *dev_priv)
>
> intel_display_driver_unregister(dev_priv);
>
> +#if IS_REACHABLE(CONFIG_HWMON)
> + i915_hwmon_unregister(dev_priv);
> +#endif
> intel_gt_driver_unregister(to_gt(dev_priv));
>
> i915_perf_unregister(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 086bbe8945d6..d437d588dec9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -705,6 +705,8 @@ struct drm_i915_private {
>
> struct i915_perf perf;
>
> + struct i915_hwmon *hwmon;
> +
> /* Abstract the submission mechanism (legacy ringbuffer or execlists)
> away */
> struct intel_gt gt0;
>
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
> b/drivers/gpu/drm/i915/i915_hwmon.c
> new file mode 100644
> index ..5b80a0f024f0
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> @@ -0,0 +1,135 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include
> +#include
> +#include
> +
> +#include "i915_drv.h"
> +#include "i915_hwmon.h"
> +#include "intel_mchbar_regs.h"
> +
> +struct hwm_reg {
> +};
> +
> +struct hwm_drvdata {
> + struct i915_hwmon *hwmon;
> + struct intel_uncore *uncore;
> + struct device *hwmon_dev;
> + char name[12];
> +};
> +
> +struct i915_hwmon {
> + struct hwm_drvdata ddat;
> + struct mutex hwmon_lock;/* counter overflow logic and
> rmw */
> + struct hwm_reg rg;
> +};
> +
> +static const struct hwmon_channel_info *hwm_info[] = {
> + NULL
> +};
> +
> +static umode_t
> +hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> +u32 attr, int channel)
> +{
> + switch (type) {
> + default:
> + return 0;
> + }
> +}
> +
> +static
Re: [Intel-gfx] [PATCH v3 15/31] platform/x86: nvidia-wmi-ec-backlight: Move fw interface definitions to a header
Hi,
On 8/18/22 21:38, Daniel Dadap wrote:
>
> On 8/18/22 1:42 PM, Hans de Goede wrote:
>> Move the WMI interface definitions to a header, so that the definitions
>> can be shared with drivers/acpi/video_detect.c .
>>
>> Suggested-by: Daniel Dadap
>> Signed-off-by: Hans de Goede
>> ---
>> MAINTAINERS | 1 +
>> .../platform/x86/nvidia-wmi-ec-backlight.c | 66 +
>> .../x86/nvidia-wmi-ec-backlight.h | 70 +++
>> 3 files changed, 72 insertions(+), 65 deletions(-)
>> create mode 100644
>> include/linux/platform_data/x86/nvidia-wmi-ec-backlight.h
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 8a5012ba6ff9..8d59c6e9b4db 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -14526,6 +14526,7 @@ M: Daniel Dadap
>> L: platform-driver-...@vger.kernel.org
>> S: Supported
>> F: drivers/platform/x86/nvidia-wmi-ec-backlight.c
>> +F: include/linux/platform_data/x86/nvidia-wmi-ec-backlight.h
>> NVM EXPRESS DRIVER
>> M: Keith Busch
>> diff --git a/drivers/platform/x86/nvidia-wmi-ec-backlight.c
>> b/drivers/platform/x86/nvidia-wmi-ec-backlight.c
>> index 61e37194df70..e84e1d629b14 100644
>> --- a/drivers/platform/x86/nvidia-wmi-ec-backlight.c
>> +++ b/drivers/platform/x86/nvidia-wmi-ec-backlight.c
>> @@ -7,74 +7,10 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include
>> -/**
>> - * enum wmi_brightness_method - WMI method IDs
>> - * @WMI_BRIGHTNESS_METHOD_LEVEL: Get/Set EC brightness level status
>> - * @WMI_BRIGHTNESS_METHOD_SOURCE: Get/Set EC Brightness Source
>> - */
>> -enum wmi_brightness_method {
>> - WMI_BRIGHTNESS_METHOD_LEVEL = 1,
>> - WMI_BRIGHTNESS_METHOD_SOURCE = 2,
>> - WMI_BRIGHTNESS_METHOD_MAX
>> -};
>> -
>> -/**
>> - * enum wmi_brightness_mode - Operation mode for WMI-wrapped method
>> - * @WMI_BRIGHTNESS_MODE_GET: Get the current brightness
>> level/source.
>> - * @WMI_BRIGHTNESS_MODE_SET: Set the brightness level.
>> - * @WMI_BRIGHTNESS_MODE_GET_MAX_LEVEL: Get the maximum brightness level.
>> This
>> - * is only valid when the WMI method is
>> - * %WMI_BRIGHTNESS_METHOD_LEVEL.
>> - */
>> -enum wmi_brightness_mode {
>> - WMI_BRIGHTNESS_MODE_GET = 0,
>> - WMI_BRIGHTNESS_MODE_SET = 1,
>> - WMI_BRIGHTNESS_MODE_GET_MAX_LEVEL = 2,
>> - WMI_BRIGHTNESS_MODE_MAX
>> -};
>> -
>> -/**
>> - * enum wmi_brightness_source - Backlight brightness control source
>> selection
>> - * @WMI_BRIGHTNESS_SOURCE_GPU: Backlight brightness is controlled by the
>> GPU.
>> - * @WMI_BRIGHTNESS_SOURCE_EC: Backlight brightness is controlled by the
>> - * system's Embedded Controller (EC).
>> - * @WMI_BRIGHTNESS_SOURCE_AUX: Backlight brightness is controlled over the
>> - * DisplayPort AUX channel.
>> - */
>> -enum wmi_brightness_source {
>> - WMI_BRIGHTNESS_SOURCE_GPU = 1,
>> - WMI_BRIGHTNESS_SOURCE_EC = 2,
>> - WMI_BRIGHTNESS_SOURCE_AUX = 3,
>> - WMI_BRIGHTNESS_SOURCE_MAX
>> -};
>> -
>> -/**
>> - * struct wmi_brightness_args - arguments for the WMI-wrapped ACPI method
>> - * @mode: Pass in an wmi_brightness_mode value to select between
>> - * getting or setting a value.
>> - * @val: In parameter for value to set when using
>> %WMI_BRIGHTNESS_MODE_SET
>> - * mode. Not used in conjunction with %WMI_BRIGHTNESS_MODE_GET or
>> - * %WMI_BRIGHTNESS_MODE_GET_MAX_LEVEL mode.
>> - * @ret: Out parameter returning retrieved value when operating in
>> - * %WMI_BRIGHTNESS_MODE_GET or %WMI_BRIGHTNESS_MODE_GET_MAX_LEVEL
>> - * mode. Not used in %WMI_BRIGHTNESS_MODE_SET mode.
>> - * @ignored: Padding; not used. The ACPI method expects a 24 byte params
>> struct.
>> - *
>> - * This is the parameters structure for the WmiBrightnessNotify ACPI method
>> as
>> - * wrapped by WMI. The value passed in to @val or returned by @ret will be a
>> - * brightness value when the WMI method ID is %WMI_BRIGHTNESS_METHOD_LEVEL,
>> or
>> - * an wmi_brightness_source value with %WMI_BRIGHTNESS_METHOD_SOURCE.
>> - */
>> -struct wmi_brightness_args {
>> - u32 mode;
>> - u32 val;
>> - u32 ret;
>> - u32 ignored[3];
>> -};
>> -
>> /**
>> * wmi_brightness_notify() - helper function for calling WMI-wrapped ACPI
>> method
>> * @w: Pointer to the struct wmi_device identified by
>> %WMI_BRIGHTNESS_GUID
>> diff --git a/include/linux/platform_data/x86/nvidia-wmi-ec-backlight.h
>> b/include/linux/platform_data/x86/nvidia-wmi-ec-backlight.h
>> new file mode 100644
>> index ..d83104c6c6cb
>> --- /dev/null
>> +++ b/include/linux/platform_data/x86/nvidia-wmi-ec-backlight.h
>> @@ -0,0 +1,70 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>
>
> Should the copyright notice from nvidia-wmi-ec-backlight be copied here as
>
Re: [Intel-gfx] [RESEND 1/3] drm/i915/dsi: filter invalid backlight and CABC ports
On Wed, 17 Aug 2022, Jani Nikula wrote: > On Wed, 17 Aug 2022, "Lisovskiy, Stanislav" > wrote: >> On Tue, Aug 16, 2022 at 06:37:20PM +0300, Jani Nikula wrote: >>> Avoid using ports that aren't initialized in case the VBT backlight or >>> CABC ports have invalid values. This fixes a NULL pointer dereference of >>> intel_dsi->dsi_hosts[port] in such cases. >>> >>> Cc: sta...@vger.kernel.org >>> Signed-off-by: Jani Nikula >> >> Would be interesting to figure out which one of those actually fixed the >> https://gitlab.freedesktop.org/drm/intel/-/issues/6476 issue, this one >> or next one. > > I asked to test with patch 1 alone first, and it lets them boot without > the oops. And it produces the warn added here. But this just filters > port C out of bl_ports, and doesn't fix the root cause. Patch 2 should > fix the root cause, get rid of the warn and give them functioning > backlight. I hope. There was no test results with patches 2&3. :) > >> Reviewed-by: Stanislav Lisovskiy > > Thanks for the review! Also, pushed the series to drm-intel-next yesterday. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915/mtl: Introduce FBC B
On Wed, 17 Aug 2022, "Kahola, Mika" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Wednesday, August 17, 2022 3:26 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; Ville Syrjälä
>> ; Kahola, Mika
>> Subject: [PATCH] drm/i915/mtl: Introduce FBC B
>>
>> From: Ville Syrjälä
>>
>> MTL introduces a second FBC engine. The two FBC engines can operate entirely
>> independently, FBC A serving pipe A and FBC B serving pipe B.
>>
>> The one place where things might go a bit wrong is the CFB allocation from
>> stolen. We might have to consider some change to the allocation strategy to
>> have a better chance of both engines being able to allocate its CFB. Maybe
>> FBC
>> A should allocate bottom up and FBC B top down, or something? For the
>> moment the allocation strategy is DRM_MM_INSERT_BEST for both.
>>
>> Cc: Mika Kahola
>> Signed-off-by: Ville Syrjälä
>> Signed-off-by: Jani Nikula
>
> Reviewed-by: Mika Kahola
Thanks for the review, pushed to drm-intel-next.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/display/intel_fbc.h | 1 +
>> drivers/gpu/drm/i915/i915_pci.c | 3 ++-
>> 2 files changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
>> b/drivers/gpu/drm/i915/display/intel_fbc.h
>> index db60143295ec..4adb98afe6ff 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
>> @@ -19,6 +19,7 @@ struct intel_plane_state;
>>
>> enum intel_fbc_id {
>> INTEL_FBC_A,
>> + INTEL_FBC_B,
>>
>> I915_MAX_FBCS,
>> };
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c
>> b/drivers/gpu/drm/i915/i915_pci.c
>> index 9fd788e147a3..d8446bb25d5e 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -,7 +,8 @@ static const struct intel_device_info pvc_info = {
>> #define XE_LPDP_FEATURES \
>> XE_LPD_FEATURES,\
>> .display.ver = 14, \
>> - .display.has_cdclk_crawl = 1
>> + .display.has_cdclk_crawl = 1, \
>> + .display.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
>>
>> __maybe_unused
>> static const struct intel_device_info mtl_info = {
>> --
>> 2.34.1
>
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915/mtl: Meteorlake and later support DP 2.0
On Wed, 17 Aug 2022, "Shankar, Uma" wrote: >> -Original Message- >> From: Nikula, Jani >> Sent: Wednesday, August 17, 2022 5:50 PM >> To: intel-gfx@lists.freedesktop.org >> Cc: Nikula, Jani ; Shankar, Uma >> >> Subject: [PATCH] drm/i915/mtl: Meteorlake and later support DP 2.0 >> >> Meteorlake and newer platforms support DP 2.0. > > Reviewed-by: Uma Shankar Thanks for the review, pushed to drm-intel-next. BR, Jani. > >> Cc: Uma Shankar >> Signed-off-by: Jani Nikula >> --- >> drivers/gpu/drm/i915/i915_drv.h | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h >> b/drivers/gpu/drm/i915/i915_drv.h >> index 086bbe8945d6..b4733c5a01da 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -1255,7 +1255,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, >> #define HAS_IPS(dev_priv)(IS_HSW_ULT(dev_priv) || >> IS_BROADWELL(dev_priv)) >> >> #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) >> -#define HAS_DP20(dev_priv) (IS_DG2(dev_priv)) >> +#define HAS_DP20(dev_priv) (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= >> 14) >> >> #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)- >> >display.has_cdclk_crawl) >> #define HAS_DDI(dev_priv) >> (INTEL_INFO(dev_priv)->display.has_ddi) >> -- >> 2.34.1 > -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915/pps: added get_pps_idx() hook as part of pps_get_register() cleanup
> -Original Message-
> From: Nikula, Jani
> Sent: Wednesday, August 3, 2022 1:44 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: ville.syrj...@linux.intel.com; Shankar, Uma ;
> Manna, Animesh
> Subject: Re: [PATCH] drm/i915/pps: added get_pps_idx() hook as part of
> pps_get_register() cleanup
>
> On Wed, 03 Aug 2022, Animesh Manna wrote:
> > To support dual LFP two instances of pps added from display gen12 onwards.
> > Few older platform like VLV also has dual pps support but handling is
> > different. So added separate hook get_pps_idx() to formulate which pps
> > instance to used for a soecific LFP on a specific platform.
> >
> > Simplified pps_get_register() which use get_pps_idx() hook to derive
> > the pps instance and get_pps_idx() will be initialized at pps_init().
> >
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_bios.c | 5
> > drivers/gpu/drm/i915/display/intel_bios.h | 1 +
> > .../drm/i915/display/intel_display_types.h| 2 ++
> > drivers/gpu/drm/i915/display/intel_pps.c | 25 ++-
> > 4 files changed, 27 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index 51dde5bfd956..42315615a728 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -611,6 +611,11 @@ static int opregion_get_panel_type(struct
> drm_i915_private *i915,
> > return intel_opregion_get_panel_type(i915);
> > }
> >
> > +bool intel_bios_is_lfp2(struct intel_encoder *encoder) {
> > + return encoder->devdata && encoder->devdata->child.handle ==
> > +DEVICE_HANDLE_LFP2; }
>
> AFAICS the encoder never really needs to know whether it's "lfp1" or "lfp2".
> It
> needs to know the pps controller number.
>
> > +
> > static int vbt_get_panel_type(struct drm_i915_private *i915,
> > const struct intel_bios_encoder_data *devdata,
> > const struct edid *edid)
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.h
> > b/drivers/gpu/drm/i915/display/intel_bios.h
> > index e47582b0de0a..aea72a87ea2c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.h
> > @@ -251,6 +251,7 @@ bool intel_bios_is_lspcon_present(const struct
> drm_i915_private *i915,
> > enum port port);
> > bool intel_bios_is_lane_reversal_needed(const struct drm_i915_private
> > *i915,
> > enum port port);
> > +bool intel_bios_is_lfp2(struct intel_encoder *encoder);
> > enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
> > enum port port); bool intel_bios_get_dsc_params(struct intel_encoder
> *encoder,
> >struct intel_crtc_state *crtc_state, diff --git
> > a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 0da9b208d56e..95f71a572b07 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1723,6 +1723,8 @@ struct intel_dp {
> >
> > /* When we last wrote the OUI for eDP */
> > unsigned long last_oui_write;
> > +
> > + int (*get_pps_idx)(struct intel_dp *intel_dp);
>
> Making this a function pointer should be a separate step. Please don't try to
> do
> too many things at once. Rule of thumb, one change per patch.
>
> Also, this should be placed near the other function pointer members in struct
> intel_dp.
>
> > };
> >
> > enum lspcon_vendor {
> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> > b/drivers/gpu/drm/i915/display/intel_pps.c
> > index 1b21a341962f..c9cdb302d318 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> > @@ -231,6 +231,17 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
> > return backlight_controller;
> > }
> >
> > +static int
> > +gen12_power_sequencer_idx(struct intel_dp *intel_dp) {
> > + struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
> > +
> > + if (intel_bios_is_lfp2(encoder))
> > + return 1;
>
> This is actually not how this works. The bxt_power_sequencer_idx() matches
> bspec 20149: "PWM and PPS are assumed to be aligned to be from same block
> and not mismatch" i.e. the backlight controller id and the pps id are the
> same.
> There are no requirements to map lfp# and pps controller like this, even if it
> might be true in the common case.
>
> The problem is we need the information *before* we call
> intel_bios_init_panel().
>
> It's a catch-22. We need the pps id to read the panel EDID, and we need the
> panel EDID to choose the correct panel type in VBT, which we need to get the
> pps id from the VBT.
>
> This is highlighted in [1]. The 2nd eDP (which is not even physically
>
Re: [Intel-gfx] [PATCH v3 09/31] ACPI: video: Make backlight class device registration a separate step (v2)
Hi,
On 8/18/22 22:07, Daniel Dadap wrote:
>
> On 8/18/22 1:42 PM, Hans de Goede wrote:
>> On x86/ACPI boards the acpi_video driver will usually initialize before
>> the kms driver (except i915). This causes /sys/class/backlight/acpi_video0
>> to show up and then the kms driver registers its own native backlight
>> device after which the drivers/acpi/video_detect.c code unregisters
>> the acpi_video0 device (when acpi_video_get_backlight_type()==native).
>>
>> This means that userspace briefly sees 2 devices and the disappearing of
>> acpi_video0 after a brief time confuses the systemd backlight level
>> save/restore code, see e.g.:
>> https://bbs.archlinux.org/viewtopic.php?id=269920
>>
>> To fix this make backlight class device registration a separate step
>> done by a new acpi_video_register_backlight() function. The intend is for
>> this to be called by the drm/kms driver *after* it is done setting up its
>> own native backlight device. So that acpi_video_get_backlight_type() knows
>> if a native backlight will be available or not at acpi_video backlight
>> registration time, avoiding the add + remove dance.
>>
>> Note the new acpi_video_register_backlight() function is also called from
>> a delayed work to ensure that the acpi_video backlight devices does get
>> registered if necessary even if there is no drm/kms driver or when it is
>> disabled.
>>
>> Changes in v2:
>> - Make register_backlight_delay a module parameter, mainly so that it can
>> be disabled by Nvidia binary driver users
>>
>> Acked-by: Rafael J. Wysocki
>> Signed-off-by: Hans de Goede
>> ---
>> drivers/acpi/acpi_video.c | 50 ---
>> include/acpi/video.h | 2 ++
>> 2 files changed, 49 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/acpi/acpi_video.c b/drivers/acpi/acpi_video.c
>> index 8545bf94866f..09dd86f86cf3 100644
>> --- a/drivers/acpi/acpi_video.c
>> +++ b/drivers/acpi/acpi_video.c
>> @@ -73,6 +73,16 @@ module_param(device_id_scheme, bool, 0444);
>> static int only_lcd = -1;
>> module_param(only_lcd, int, 0444);
>> +/*
>> + * Display probing is known to take up to 5 seconds, so delay the fallback
>> + * backlight registration by 5 seconds + 3 seconds for some extra margin.
>> + */
>> +static int register_backlight_delay = 8;
>> +module_param(register_backlight_delay, int, 0444);
>
>
> Would it make sense to make this parameter writable from userspace, e.g. so
> that it can be set by a udev rule rather than relying on a riskier kernel
> command line edit? Then again, that probably makes things more complicated,
> since you'd have to check the parameter again when the worker fires, and
> changing the parameter to a non-zero value from either zero or a different
> non-zero value would be too weird. And making a separate writable parameter
> to allow userspace to turn the worker into a noop despite it being enabled
> when the kernel was initially loaded seems wrong, too.
Right, you have pretty much described yourself why making this parameter
runtime configurable is not really feasible :)
Regards,
Hans
>
>
>> +MODULE_PARM_DESC(register_backlight_delay,
>> + "Delay in seconds before doing fallback (non GPU driver triggered) "
>> + "backlight registration, set to 0 to disable.");
>> +
>> static bool may_report_brightness_keys;
>> static int register_count;
>> static DEFINE_MUTEX(register_count_mutex);
>> @@ -81,6 +91,9 @@ static LIST_HEAD(video_bus_head);
>> static int acpi_video_bus_add(struct acpi_device *device);
>> static int acpi_video_bus_remove(struct acpi_device *device);
>> static void acpi_video_bus_notify(struct acpi_device *device, u32 event);
>> +static void acpi_video_bus_register_backlight_work(struct work_struct
>> *ignored);
>> +static DECLARE_DELAYED_WORK(video_bus_register_backlight_work,
>> + acpi_video_bus_register_backlight_work);
>> void acpi_video_detect_exit(void);
>> /*
>> @@ -1859,8 +1872,6 @@ static int acpi_video_bus_register_backlight(struct
>> acpi_video_bus *video)
>> if (video->backlight_registered)
>> return 0;
>> - acpi_video_run_bcl_for_osi(video);
>> -
>> if (acpi_video_get_backlight_type() != acpi_backlight_video)
>> return 0;
>> @@ -2086,7 +2097,11 @@ static int acpi_video_bus_add(struct acpi_device
>> *device)
>> list_add_tail(>entry, _bus_head);
>> mutex_unlock(_list_lock);
>> - acpi_video_bus_register_backlight(video);
>> + /*
>> + * The userspace visible backlight_device gets registered separately
>> + * from acpi_video_register_backlight().
>> + */
>> + acpi_video_run_bcl_for_osi(video);
>> acpi_video_bus_add_notify_handler(video);
>> return 0;
>> @@ -2125,6 +2140,11 @@ static int acpi_video_bus_remove(struct acpi_device
>> *device)
>> return 0;
>> }
>> +static void acpi_video_bus_register_backlight_work(struct work_struct
>> *ignored)
>> +{
>> +
Re: [Intel-gfx] [PATCH v2 00/15] drm/i915: HuC loading for DG2
On Thu, Aug 18, 2022 at 04:02:28PM -0700, Daniele Ceraolo Spurio wrote: > Note that this series includes several mei patches that add support for > sending the HuC loading command via mei-gsc. These patches depend on the > GSC support for DG2 [1], which has been included squashed in a single > patch to make the series apply and allow CI to run. We plan to merge > those patches through the drm tree because i915 is the sole user. Doesn't look like you cc:ed me on any of the mei patches, which is odd, and ensure I can't review them :( And why are mei changes needed only for drm? thanks, greg k-h
Re: [Intel-gfx] [PATCH 1/3] drm: Use original src rect while initializing damage iterator
On Thu, 2022-08-11 at 18:23 +0200, Daniel Vetter wrote:
> On Fri, Jul 15, 2022 at 04:49:56PM +0300, Jouni Högander wrote:
> > drm_plane_state->src might be modified by the driver. This is done
> > e.g. in i915 driver when there is bigger framebuffer than the plane
> > and there is some offset within framebuffer. I915 driver calculates
> > separate offset and adjusts src rect coords to be relative to this
> > offset. Damage clips are still relative to original src coords
> > provided by user-space.
> >
> > This patch ensures original coordinates provided by user-space are
> > used when initiliazing damage iterator.
> >
> > Signed-off-by: Jouni Högander
>
> Ah kunit test for this would be awesome. Iirc we have a few already
> for
> rect/damage stuff, defo should extend/fix those.
Can you please provide me some pointer to these tests? I have written
earlier one igt test which reveals this issue:
https://patchwork.freedesktop.org/series/103661/
https://patchwork.freedesktop.org/series/104488/
> -Daniel
>
> > ---
> > drivers/gpu/drm/drm_damage_helper.c | 11 +++
> > 1 file changed, 7 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_damage_helper.c
> > b/drivers/gpu/drm/drm_damage_helper.c
> > index 937b699ac2a8..d8b2955e88fd 100644
> > --- a/drivers/gpu/drm/drm_damage_helper.c
> > +++ b/drivers/gpu/drm/drm_damage_helper.c
> > @@ -224,6 +224,7 @@ drm_atomic_helper_damage_iter_init(struct
> > drm_atomic_helper_damage_iter *iter,
> >const struct drm_plane_state
> > *old_state,
> >const struct drm_plane_state *state)
> > {
> > + struct drm_rect src;
> > memset(iter, 0, sizeof(*iter));
> >
> > if (!state || !state->crtc || !state->fb || !state->visible)
> > @@ -233,10 +234,12 @@ drm_atomic_helper_damage_iter_init(struct
> > drm_atomic_helper_damage_iter *iter,
> > iter->num_clips = drm_plane_get_damage_clips_count(state);
> >
> > /* Round down for x1/y1 and round up for x2/y2 to catch all
> > pixels */
> > - iter->plane_src.x1 = state->src.x1 >> 16;
> > - iter->plane_src.y1 = state->src.y1 >> 16;
> > - iter->plane_src.x2 = (state->src.x2 >> 16) + !!(state->src.x2 &
> > 0x);
> > - iter->plane_src.y2 = (state->src.y2 >> 16) + !!(state->src.y2 &
> > 0x);
> > + src = drm_plane_state_src(state);
> > +
> > + iter->plane_src.x1 = src.x1 >> 16;
> > + iter->plane_src.y1 = src.y1 >> 16;
> > + iter->plane_src.x2 = (src.x2 >> 16) + !!(src.x2 & 0x);
> > + iter->plane_src.y2 = (src.y2 >> 16) + !!(src.y2 & 0x);
> >
> > if (!iter->clips || !drm_rect_equals(>src, _state-
> > >src)) {
> > iter->clips = NULL;
> > --
> > 2.25.1
> >
Re: [Intel-gfx] [PATCH i-g-t 1/3] tests/gem_exec_fence: Fix wrong engine checked for store_dword capability
On Thu, 18 Aug 2022 17:27:26 +0200 Janusz Krzysztofik wrote: > Hi Mauro, > > Thanks for reviewing this series, I've just pushed it. > > On Wednesday, 17 August 2022 14:53:48 CEST Mauro Carvalho Chehab wrote: > > Hi Janusz, > > > > On Fri, 12 Aug 2022 11:53:44 +0200 > > Janusz Krzysztofik wrote: > > > > It seems that there is a numeration issue on this series, as the patches > > on it are: > > > >[PATCH i-g-t 1/3] tests/gem_exec_fence: Fix wrong engine checked for > > store_dword capability > >[PATCH i-g-t v2 2/3] tests/gem_exec_fence: Exclude 0 from use in store > > batches > >[PATCH i-g-t v3 3/3] tests/gem_exec_fence: Restore pre-hang checks in > > *await-hang scenarios > > > > Maybe some broken script? It is also missing a cover letter. > > That was not a script, I provided version numbers of individual patches > manually, and not provided any cover letter. First patch was a small fix, > not > directly related to the two others. Second patch was a small enhancement, > also not directly related to the third one. However, the third one depended > on the two for clean apply, and that was the only reason for me sending them > in series. > > That said, let me ask, based on your huge upstream experience, what are your > preferences on patch version tagging if one is going to submit a series with > new versions of some patches while still including some other that don't need > to be changed? Should all be marked as new (and the same) versions? I guess you started without a cover letter because it was originally a single patch. Then, you realized that this was not enough, so you needed extra stuff. When I submit single fixes upstream, I usually don't add cover letters, as the patch description is usually enough, but, at the moment it becomes multiple (dependent) ones, I add it. Yet, sometimes even for simple patch submissions, I add cover letters, when I feel the need to add some explanation to help reviewers to analyze it. Basically: - the cover letter provides temporary information meant to help reviewers and maintainers to understand the series. It includes, for instance: - a short summary of the patches in the tree; - on what tree/branch the patch applies, if not on upstream (like someone's else tree, next-20220819 branch, etc). - any special instructions for the maintainers when applying it, like if the patch should be merged after some other series; - patch versions; - etc. - the patch title and the body describes: why, what and how. Those should be providing enough understanding for anyone that would later look at the git logs to understand the changes applied there. Patch version log doesn't belong here. Yet, as patch reviews could be interesting even after things get merged, you can include a link to lore, in the form of: Link: https://lore.kernel.org/$mailing_list/$msg_id (instead of $mailing list, you could just use "all") So, for instance, if I want to place a pointer to the last e-mail on this thread, I would add: Link: https://lore.kernel.org/intel-gfx/6809017.18pcnm7...@jkrzyszt-mobl1.ger.corp.intel.com or: Link: https://lore.kernel.org/all/6809017.18pcnm7...@jkrzyszt-mobl1.ger.corp.intel.com Btw, on patches generated on git, the msg_id is there after format-email. So, you can even add links to the patch you're sending. - In cases like the one you described, I would be adding a cover letter with something like: [PATCH i-g-t v3 0/3] Add some fixes to tests/gem_exec_fence some description about the series --- v3: - Added a patch to restore pre-hang checks; - patches 1 and 2 unchanged. v2: - Added a fix to exclude 0 in store batches; - patch 1 unchanged. If you need a v4, add it before v3, and so on. At the series itself, version numbers are incremented on all patches. This makes clear for reviewers that already checked your series about what changed and what remains the same. I hope that helps. Regards, Mauro
