Re: [Intel-gfx] [PATCH v2 7/9] drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state dp_dfp members
On 9/13/2022 12:26 AM, Ville Syrjälä wrote:
On Thu, Sep 01, 2022 at 11:30:59AM +0530, Ankit Nautiyal wrote:
The decision to use DFP output format conversion capabilities should be
during compute_config phase.
This patch uses the members of intel_dp->dfp to only store the
format conversion capabilities of the DP device and uses the crtc_state
dp_dfp members that are computed earlier, to program the
protocol-converter for colorspace/format conversion.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 46 +
1 file changed, 17 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f3c2aeda0c1d..409bd9cdf450 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -805,6 +805,7 @@ intel_dp_output_format(struct intel_connector *connector,
bool ycbcr_420_output)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
return INTEL_OUTPUT_FORMAT_RGB;
@@ -813,6 +814,10 @@ intel_dp_output_format(struct intel_connector *connector,
intel_dp->dfp.ycbcr_444_to_420)
return INTEL_OUTPUT_FORMAT_RGB;
+ /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
+ if (DISPLAY_VER(i915) >= 11 && intel_dp->dfp.ycbcr420_passthrough)
+ return INTEL_OUTPUT_FORMAT_YCBCR420;
+
if (intel_dp->dfp.ycbcr_444_to_420)
return INTEL_OUTPUT_FORMAT_YCBCR444;
else
@@ -2698,8 +2703,8 @@ void intel_dp_configure_protocol_converter(struct
intel_dp *intel_dp,
drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI
mode\n",
str_enable_disable(intel_dp->has_hdmi_sink));
- tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
- intel_dp->dfp.ycbcr_444_to_420 ?
DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
+ tmp = crtc_state->dp_dfp_config.ycbcr_444_to_420 ?
+ DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
if (drm_dp_dpcd_writeb(&intel_dp->aux,
DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
@@ -2707,7 +2712,7 @@ void intel_dp_configure_protocol_converter(struct
intel_dp *intel_dp,
"Failed to %s protocol converter YCbCr 4:2:0 conversion
mode\n",
str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
- tmp = intel_dp->dfp.rgb_to_ycbcr ?
+ tmp = crtc_state->dp_dfp_config.rgb_to_ycbcr ?
DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
@@ -4563,7 +4568,7 @@ intel_dp_update_420(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_connector *connector = intel_dp->attached_connector;
- bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
+ bool is_branch;
/* No YCbCr output support on gmch platforms */
if (HAS_GMCH(i915))
@@ -4577,38 +4582,21 @@ intel_dp_update_420(struct intel_dp *intel_dp)
return;
is_branch = drm_dp_is_branch(intel_dp->dpcd);
- ycbcr_420_passthrough =
+ intel_dp->dfp.ycbcr420_passthrough =
drm_dp_downstream_420_passthrough(intel_dp->dpcd,
intel_dp->downstream_ports);
/* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
- ycbcr_444_to_420 =
+ intel_dp->dfp.ycbcr_444_to_420 =
dp_to_dig_port(intel_dp)->lspcon.active ||
drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
intel_dp->downstream_ports);
- rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
-
intel_dp->downstream_ports,
-
DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
-
- if (DISPLAY_VER(i915) >= 11) {
- /* Let PCON convert from RGB->YCbCr if possible */
- if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
- intel_dp->dfp.rgb_to_ycbcr = true;
- intel_dp->dfp.ycbcr_444_to_420 = true;
- connector->base.ycbcr_420_allowed = true;
- } else {
- /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
- intel_dp->dfp.ycbcr_444_to_420 =
- ycbcr_444_to_420 && !ycbcr_420_passthrough;
+ intel_dp->dfp.rgb_to_ycbcr =
+ drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
+
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: use drm_dp_phy_name() for logging
== Series Details == Series: drm/i915/dp: use drm_dp_phy_name() for logging URL : https://patchwork.freedesktop.org/series/108436/ State : success == Summary == CI Bug Log - changes from CI_DRM_12123_full -> Patchwork_108436v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 10) -- Missing(1): shard-rkl Known issues Here are the changes found in Patchwork_108436v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglb: [PASS][1] -> [FAIL][2] ([i915#6268]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-tglb7/igt@gem_ctx_e...@basic-nohangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/shard-tglb1/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_eio@in-flight-contexts-10ms: - shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#3063]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-tglb5/igt@gem_...@in-flight-contexts-10ms.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/shard-tglb2/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_eio@kms: - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#5784]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-tglb7/igt@gem_...@kms.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/shard-tglb3/igt@gem_...@kms.html * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: [PASS][7] -> [SKIP][8] ([i915#4525]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb1/igt@gem_exec_balan...@parallel-bb-first.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/shard-iclb6/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk5/igt@gem_exec_fair@basic-throt...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/shard-glk1/igt@gem_exec_fair@basic-throt...@rcs0.html - shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/shard-iclb2/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_lmem_swapping@random-engines: - shard-tglb: NOTRUN -> [SKIP][16] ([i915#4613]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/shard-tglb3/igt@gem_lmem_swapp...@random-engines.html * igt@gem_pxp@fail-invalid-protected-context: - shard-tglb: NOTRUN -> [SKIP][17] ([i915#4270]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/shard-tglb3/igt@gem_...@fail-invalid-protected-context.html * igt@gen9_exec_parse@bb-large: - shard-tglb: NOTRUN -> [SKIP][18] ([i915#2527] / [i915#2856]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/shard-tglb3/igt@gen9_exec_pa...@bb-large.html * igt@i915_suspend@basic-s3-without-i915: - shard-iclb: [PASS][19] -> [INCOMPLETE][20] ([i915#6598]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb4/igt@i915_susp...@basic-s3-without-i915.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/shard-iclb3/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_big_fb@4-tiled-16bpp-rotate-180: - shard-tglb: NOTRUN -> [SKIP][21] ([i915#5286]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/shard-tglb3/igt@kms_big...@4-tiled-16bpp-rotate-180.html * igt@kms_big_fb@linear-64bpp-rotate-90: - shard-tglb: NOTRUN -> [SKIP][22] ([fdo#111614]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/shard-tglb3/igt@kms_big...@linear-64bpp-rotate-90.html * igt@kms_big_fb@x-tiled-32bpp-rotate-90: - shard-apl: NOTRUN -> [SKIP][23] ([fdo#109271]) +32 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/shard-apl6/igt@kms_big...@x-tiled-32bpp-rotate-90.html * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_ti
Re: [Intel-gfx] [PATCH v2 4/9] drm/i915/display: Add new members to configure PCON color conversion
On 9/13/2022 12:25 AM, Ville Syrjälä wrote:
On Thu, Sep 01, 2022 at 11:30:56AM +0530, Ankit Nautiyal wrote:
The decision to use DFP output format conversion capabilities should be
during compute_config phase.
This patch adds new members to crtc_state to help configure the DFP
output related conversions. Also adds a member to intel_dp to store
ycbcr420 pass through capability.
This will help to store only the format conversion capabilities of the
DP device in intel_dp->dfp, and use crtc_state to compute and store the
configuration for color/format conversion for a given mode.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display_types.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0da9b208d56e..065ed19a5dd3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1311,6 +1311,12 @@ struct intel_crtc_state {
/* for loading single buffered registers during vblank */
struct drm_vblank_work vblank_work;
+
+ /* DP DFP color configuration */
+ struct {
+ bool rgb_to_ycbcr;
+ bool ycbcr_444_to_420;
+ } dp_dfp_config;
Hmm. I'm thinking just something like
enum intel_output_format sink_format;
might be easier to deal with.
Thanks Ville for looking into this.
We indeed can compute the final sink_format during compute config (based
on pcon color conversion capability + platform capability)
IIUC, then during config_protocol_converter we need to compute what
conversion need to be done based on crtc->output_format and
crtc->sink_format
eg. For sink_format YCBCR420:
1. if output_format is RGB -> configure : rgb_to_ycbcr420 and
ycbcr444_to_420
2. if output_format is YCBCR444 -> configure : ycbcr444_to_420
3. if output_format is YCBCR420 -> configure : Do nothing YCBCR420
passthrough
So we store the sink_format and configuration is implicit in this case.
The idea with the dp_dfp_config was to store the conversion config to be
done by PCON with given output_format.
The sink_format in that case is implicit.
I am open to storing the sink_format too.
Can this be handy for other encoder as well, or this will be used for DP
DFPs only?
Regards,
Ankit
};
enum intel_pipe_crc_source {
@@ -1704,6 +1710,7 @@ struct intel_dp {
int pcon_max_frl_bw;
u8 max_bpc;
bool ycbcr_444_to_420;
+ bool ycbcr420_passthrough;
bool rgb_to_ycbcr;
} dfp;
--
2.25.1
[Intel-gfx] ✓ Fi.CI.BAT: success for linux-next: manual merge of the drm-intel tree with the drm tree (rev2)
== Series Details ==
Series: linux-next: manual merge of the drm-intel tree with the drm tree (rev2)
URL : https://patchwork.freedesktop.org/series/88033/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12124 -> Patchwork_88033v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/index.html
Participating hosts (41 -> 39)
--
Additional (1): fi-hsw-4770
Missing(3): fi-ctg-p8600 bat-dg2-9 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_88033v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#3012])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][2] ([i915#4785])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- bat-dg1-5: NOTRUN -> [DMESG-FAIL][3] ([i915#4494] / [i915#4957])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-bsw-kefka: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/fi-bsw-kefka/igt@kms_chamel...@common-hpd-after-suspend.html
- bat-dg1-5: NOTRUN -> [SKIP][7] ([fdo#111827])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/bat-dg1-5/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-pnv-d510:NOTRUN -> [SKIP][8] ([fdo#109271])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +7
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-dg1-5: NOTRUN -> [SKIP][10] ([i915#4078])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/bat-dg1-5/igt@kms_pipe_crc_ba...@suspend-read-crc.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#1072]) +3
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#4312] /
[i915#5594] / [i915#6246])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/fi-hsw-4770/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gem:
- fi-pnv-d510:[DMESG-FAIL][13] ([i915#4528]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-pnv-d510/igt@i915_selftest@l...@gem.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/fi-pnv-d510/igt@i915_selftest@l...@gem.html
* igt@i915_selftest@live@gem_contexts:
- {bat-dg2-8}:[INCOMPLETE][15] ([i915#6523]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-5: [INCOMPLETE][17] ([i915#4418]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@gt_pm:
- {bat-rpls-2}: [DMESG-FAIL][19] ([i915#4258]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_88033v2/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [INCOMPLETE][21] ([i915#3303] / [i915#4785]) ->
[PASS][22]
[21]:
https://intel-gf
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for linux-next: manual merge of the drm-intel tree with the drm tree (rev2)
== Series Details == Series: linux-next: manual merge of the drm-intel tree with the drm tree (rev2) URL : https://patchwork.freedesktop.org/series/88033/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2
Re: [Intel-gfx] [PATCH 01/19] drm/i915/perf: Fix OA filtering logic for GuC mode
On Fri, 09 Sep 2022 16:47:36 -0700, Dixit, Ashutosh wrote: > > On Tue, 23 Aug 2022 13:41:37 -0700, Umesh Nerlige Ramappa wrote: > > > > Hi Umesh, > > > With GuC mode of submission, GuC is in control of defining the context id > > field > > that is part of the OA reports. To filter reports, UMD and KMD must know > > what sw > > context id was chosen by GuC. There is not interface between KMD and GuC to > > determine this, so read the upper-dword of EXECLIST_STATUS to filter/squash > > OA > > reports for the specific context. > > Do you think it is worth defining an interface for GuC to return the sw > ctx_id it will be using for a ctx, say at ctx registration time? Umesh, I came across these in GuC documentation: guc_pcv1_context_parameters_set_h2g_data_t::context_id guc_pcv2_context_parameters_set_h2g_data_t::context_id Also in the code we have in prepare_context_registration_info_v70 'ctx_id = ce->guc_id.id' which seems to be assigned in new_guc_id. So wondering if this is what we need and we already have it? Thanks. -- Ashutosh
[Intel-gfx] ✓ Fi.CI.BAT: success for Fix 'remove log size module parameters'
== Series Details ==
Series: Fix 'remove log size module parameters'
URL : https://patchwork.freedesktop.org/series/108466/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12124 -> Patchwork_108466v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/index.html
Participating hosts (41 -> 39)
--
Additional (1): fi-hsw-4770
Missing(3): fi-ctg-p8600 bat-dg2-9 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_108466v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#3012])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: NOTRUN -> [DMESG-FAIL][2] ([i915#4957])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-bsw-kefka: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/fi-bsw-kefka/igt@kms_chamel...@common-hpd-after-suspend.html
- bat-dg1-5: NOTRUN -> [SKIP][8] ([fdo#111827])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/bat-dg1-5/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [PASS][10] -> [FAIL][11] ([i915#6298])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-dg1-5: NOTRUN -> [SKIP][12] ([i915#4078])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/bat-dg1-5/igt@kms_pipe_crc_ba...@suspend-read-crc.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1072]) +3
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
Possible fixes
* igt@i915_selftest@live@gem_contexts:
- {bat-dg2-8}:[INCOMPLETE][14] ([i915#6523]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-5: [INCOMPLETE][16] ([i915#4418]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@gt_pm:
- {bat-rpls-2}: [DMESG-FAIL][18] ([i915#4258]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [INCOMPLETE][20] ([i915#3303] / [i915#4785]) ->
[PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108466v1/fi-hsw-g3258/
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: HuC loading for DG2 (rev5)
== Series Details ==
Series: drm/i915: HuC loading for DG2 (rev5)
URL : https://patchwork.freedesktop.org/series/107477/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12124 -> Patchwork_107477v5
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v5/index.html
Participating hosts (41 -> 38)
--
Additional (1): fi-hsw-4770
Missing(4): fi-ctg-p8600 fi-bdw-samus fi-rkl-11600 bat-adlp-6
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107477v5:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-dg2-9}:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v5/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html
Known issues
Here are the changes found in Patchwork_107477v5 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#3012])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v5/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: NOTRUN -> [DMESG-FAIL][4] ([i915#4957])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v5/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v5/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v5/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-bsw-kefka: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v5/fi-bsw-kefka/igt@kms_chamel...@common-hpd-after-suspend.html
- bat-dg1-5: NOTRUN -> [SKIP][8] ([fdo#111827])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v5/bat-dg1-5/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v5/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [PASS][10] -> [FAIL][11] ([i915#6298])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v5/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-dg1-5: NOTRUN -> [SKIP][12] ([i915#4078])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v5/bat-dg1-5/igt@kms_pipe_crc_ba...@suspend-read-crc.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1072]) +3
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v5/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
Possible fixes
* igt@gem_huc_copy@huc-copy:
- {bat-dg2-8}:[SKIP][14] ([i915#3595]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-dg2-8/igt@gem_huc_c...@huc-copy.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v5/bat-dg2-8/igt@gem_huc_c...@huc-copy.html
- {bat-dg2-9}:[SKIP][16] ([i915#3595]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-dg2-9/igt@gem_huc_c...@huc-copy.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v5/bat-dg2-9/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@gem_contexts:
- {bat-dg2-8}:[INCOMPLETE][18] ([i915#6523]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v5/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-5: [INCOMPLETE][20] ([i915#4418]) -> [PASS][21]
[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/i915_drv.h
between commit:
3bb6a44251b4 ("drm/i915: Rename ggtt_view as gtt_view")
from the drm tree and commit:
5fd5cc73e449 ("drm/i915: split out i915_gem.c declarations to i915_gem.h")
from the drm-intel tree.
I fixed it up (I used the latter version of this file and applied the
merge fix below) and can carry the fix as necessary. This is now fixed
as far as linux-next is concerned, but any non trivial conflicts should
be mentioned to your upstream maintainer when your tree is submitted for
merging. You may also want to consider cooperating with the maintainer
of the conflicting tree to minimise any particularly complex conflicts.
From: Stephen Rothwell
Date: Tue, 13 Sep 2022 12:06:57 +1000
Subject: [PATCH] drm/i915: fix up for "drm/i915: Rename ggtt_view as gtt_view"
Signed-off-by: Stephen Rothwell
---
drivers/gpu/drm/i915/i915_gem.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index 2fccb19ed9f7..a5cdf6662d01 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -36,7 +36,7 @@ struct drm_file;
struct drm_i915_gem_object;
struct drm_i915_private;
struct i915_gem_ww_ctx;
-struct i915_ggtt_view;
+struct i915_gtt_view;
struct i915_vma;
void i915_gem_init_early(struct drm_i915_private *i915);
@@ -48,12 +48,12 @@ void i915_gem_drain_workqueue(struct drm_i915_private
*i915);
struct i915_vma * __must_check
i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
struct i915_gem_ww_ctx *ww,
- const struct i915_ggtt_view *view,
+ const struct i915_gtt_view *view,
u64 size, u64 alignment, u64 flags);
struct i915_vma * __must_check
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
-const struct i915_ggtt_view *view,
+const struct i915_gtt_view *view,
u64 size, u64 alignment, u64 flags);
int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
--
2.35.1
--
Cheers,
Stephen Rothwell
pgpBAV8rkOu2a.pgp
Description: OpenPGP digital signature
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: HuC loading for DG2 (rev5)
== Series Details == Series: drm/i915: HuC loading for DG2 (rev5) URL : https://patchwork.freedesktop.org/series/107477/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: HuC loading for DG2 (rev5)
== Series Details == Series: drm/i915: HuC loading for DG2 (rev5) URL : https://patchwork.freedesktop.org/series/107477/ State : warning == Summary == Error: dim checkpatch failed 302eb2e32f35 mei: add support to GSC extended header 2a95a5b83cba mei: bus: enable sending gsc commands c7f29caeadd2 mei: adjust extended header kdocs 11efa399db05 mei: bus: extend bus API to support command streamer API 0db9400904b7 mei: pxp: add command streamer API to the PXP driver 867598633002 mei: pxp: support matching with a gfx discrete card 2cc20805c2ef drm/i915/pxp: load the pxp module when we have a gsc-loaded huc 794fd5018fea drm/i915/pxp: implement function for sending tee stream command 1732ca11bf5d drm/i915/pxp: add huc authentication and loading command Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:33: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #33: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 131 lines checked 9f194c87f5da drm/i915/dg2: setup HuC loading via GSC 442fecfd0daa drm/i915/huc: track delayed HuC load with a fence 62443bf15658 drm/i915/huc: stall media submission until HuC is loaded 2d6e5aafb8b7 drm/i915/huc: better define HuC status getparam possible return values. 43dd36bbe2e7 drm/i915/huc: define gsc-compatible HuC fw for DG2 -:29: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #29: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:94: +#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp, huc_gsc) \ + fw_def(DG2, 0, huc_gsc(dg2)) \ fw_def(ALDERLAKE_P, 0, huc_mmp(tgl, 7, 9, 3)) \ fw_def(ALDERLAKE_S, 0, huc_mmp(tgl, 7, 9, 3)) \ fw_def(DG1, 0, huc_mmp(dg1, 7, 9, 3)) \ -:29: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fw_def' - possible side-effects? #29: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:94: +#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp, huc_gsc) \ + fw_def(DG2, 0, huc_gsc(dg2)) \ fw_def(ALDERLAKE_P, 0, huc_mmp(tgl, 7, 9, 3)) \ fw_def(ALDERLAKE_S, 0, huc_mmp(tgl, 7, 9, 3)) \ fw_def(DG1, 0, huc_mmp(dg1, 7, 9, 3)) \ -:29: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'huc_mmp' - possible side-effects? #29: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:94: +#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp, huc_gsc) \ + fw_def(DG2, 0, huc_gsc(dg2)) \ fw_def(ALDERLAKE_P, 0, huc_mmp(tgl, 7, 9, 3)) \ fw_def(ALDERLAKE_S, 0, huc_mmp(tgl, 7, 9, 3)) \ fw_def(DG1, 0, huc_mmp(dg1, 7, 9, 3)) \ -:49: WARNING:LONG_LINE: line length of 111 exceeds 100 columns #49: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:156: +INTEL_HUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_HUC_FW_PATH_BLANK, MAKE_HUC_FW_PATH_MMP, MAKE_HUC_FW_PATH_GSC) total: 1 errors, 1 warnings, 2 checks, 83 lines checked f71ce4f26857 HAX: drm/i915: force INTEL_MEI_GSC and INTEL_MEI_PXP on for CI
[Intel-gfx] ✓ Fi.CI.BAT: success for Fix bug in version reduced firmware update
== Series Details ==
Series: Fix bug in version reduced firmware update
URL : https://patchwork.freedesktop.org/series/108461/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12124 -> Patchwork_108461v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v1/index.html
Participating hosts (41 -> 40)
--
Additional (1): fi-hsw-4770
Missing(2): fi-ctg-p8600 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_108461v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#3012])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: NOTRUN -> [DMESG-FAIL][2] ([i915#4494] / [i915#4957])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v1/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v1/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-bsw-kefka: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v1/fi-bsw-kefka/igt@kms_chamel...@common-hpd-after-suspend.html
- bat-dg1-5: NOTRUN -> [SKIP][8] ([fdo#111827])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v1/bat-dg1-5/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-dg1-5: NOTRUN -> [SKIP][10] ([i915#4078])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v1/bat-dg1-5/igt@kms_pipe_crc_ba...@suspend-read-crc.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#1072]) +3
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
Possible fixes
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][12] ([i915#2867]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-5: [INCOMPLETE][14] ([i915#4418]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v1/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [INCOMPLETE][16] ([i915#3303] / [i915#4785]) ->
[PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@reset:
- fi-bsw-kefka: [INCOMPLETE][18] -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-bsw-kefka/igt@i915_selftest@l...@reset.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v1/fi-bsw-kefka/igt@i915_selftest@l...@reset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix display problems after resume
== Series Details == Series: drm/i915: Fix display problems after resume URL : https://patchwork.freedesktop.org/series/108432/ State : success == Summary == CI Bug Log - changes from CI_DRM_12123_full -> Patchwork_108432v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_108432v1_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-glk: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [FAIL][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#4392]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk1/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk1/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk2/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk2/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk2/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk2/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk3/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk3/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk5/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk5/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk5/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk6/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk6/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk7/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk7/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk7/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk8/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk8/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk8/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk8/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk9/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk9/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk1/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk1/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk1/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk2/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk2/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk2/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk3/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk3/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk3/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk3/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk5/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk5/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk5/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk6/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk6/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk6/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-glk7/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/shard-g
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: header cleanups (rev2)
== Series Details ==
Series: drm/i915: header cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/93777/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12124 -> Patchwork_93777v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/index.html
Participating hosts (41 -> 39)
--
Missing(2): fi-ctg-p8600 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_93777v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: NOTRUN -> [INCOMPLETE][1] ([i915#2940])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@gem:
- fi-blb-e6850: NOTRUN -> [DMESG-FAIL][2] ([i915#4528])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/fi-blb-e6850/igt@i915_selftest@l...@gem.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: NOTRUN -> [DMESG-FAIL][3] ([i915#4494] / [i915#4957])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][4] -> [DMESG-FAIL][5] ([i915#4528])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- bat-dg1-5: NOTRUN -> [SKIP][7] ([fdo#111827])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/bat-dg1-5/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-dg1-5: NOTRUN -> [SKIP][8] ([i915#4078])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/bat-dg1-5/igt@kms_pipe_crc_ba...@suspend-read-crc.html
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#4312])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/fi-bsw-kefka/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gem_contexts:
- {bat-dg2-8}:[INCOMPLETE][10] ([i915#6523]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-5: [INCOMPLETE][12] ([i915#4418]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@gt_pm:
- {bat-rpls-2}: [DMESG-FAIL][14] ([i915#4258]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [INCOMPLETE][16] ([i915#3303] / [i915#4785]) ->
[PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@mman:
- {bat-rpls-2}: [INCOMPLETE][18] -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-rpls-2/igt@i915_selftest@l...@mman.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/bat-rpls-2/igt@i915_selftest@l...@mman.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [DMESG-FAIL][20] ([i915#4528]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@reset:
- fi-bsw-kefka: [INCOMPLETE][22] -> [PASS][23]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-bsw-kefka/igt@i915_selftest@l...@reset.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_93777v2/fi-bsw-kefka/igt@i915_selftest@l...@reset.html
* igt@i915_suspend@basic-s3-without-i915:
- {bat-rpls-2}:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: header cleanups (rev2)
== Series Details == Series: drm/i915: header cleanups (rev2) URL : https://patchwork.freedesktop.org/series/93777/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: header cleanups (rev2)
== Series Details ==
Series: drm/i915: header cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/93777/
State : warning
== Summary ==
Error: dim checkpatch failed
5507d6540b9e drm/i915/gmbus: move GPIO enum to gmbus
855c0fd1a265 drm/i915: reduce includes in intel_connector.h
9be9ae1ddda3 drm/i915: reduce includes in intel_fifo_underrun.h
a75ba0cee8c8 drm/i915: un-inline icl_hdr_plane_mask() to simplify includes
cce28c76520c drm/i915/dpio: un-inline the vlv phy/channel mapping functions
b9c868ec648a drm/i915/dpio: move dpio_channel and dpio_phy enums to
intel_dpio_phy.h
074dd7be5839 drm/i915: reduce includes in intel_display_power.h
1b48a50fcd22 drm/i915/display: reduce the includes in intel_dvo_dev.h
899a1851365d drm/i915/display: reduce includes in intel_hdmi.h
625b062ea145 drm/i915/display: reduce includes in g4x_dp.h includes
7642f05fe510 drm/i915/irq: make gen2_irq_init()/gen2_irq_reset() static
c8f1bad1e357 drm/i915/reg: move masked field helpers to i915_reg_defs.h
-:43: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask' - possible
side-effects?
#43: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:102:
+#define _MASKED_FIELD(mask, value) ({ \
+ if (__builtin_constant_p(mask))\
+ BUILD_BUG_ON_MSG(((mask) & 0x), "Incorrect mask"); \
+ if (__builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & 0x, "Incorrect value"); \
+ if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & ~(mask),\
+"Incorrect value for mask"); \
+ __MASKED_FIELD(mask, value); })
-:43: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'value' - possible
side-effects?
#43: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:102:
+#define _MASKED_FIELD(mask, value) ({ \
+ if (__builtin_constant_p(mask))\
+ BUILD_BUG_ON_MSG(((mask) & 0x), "Incorrect mask"); \
+ if (__builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & 0x, "Incorrect value"); \
+ if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & ~(mask),\
+"Incorrect value for mask"); \
+ __MASKED_FIELD(mask, value); })
total: 0 errors, 0 warnings, 2 checks, 38 lines checked
9ac4c205c0cf drm/i915/reg: move pick even and pick to reg defs
-:50: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__a' - possible side-effects?
#50: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:120:
+#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
total: 0 errors, 0 warnings, 1 checks, 42 lines checked
211b335dbe49 drm/i915: split out intel_display_reg_defs.h
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:52: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#52:
new file mode 100644
-:102: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#102: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:46:
+#define _MMIO_TRANS2(tran, reg)
_MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
-:103: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#103: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:47:
+
INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
-:105: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#105: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:49:
+#define _MMIO_CURSOR2(pipe, reg)
_MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
-:106: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#106: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:50:
+
INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
total: 0 errors, 5 warnings, 0 checks, 176 lines checked
08bcce40276d drm/i915: stop including i915_irq.h from i915_trace.h
[Intel-gfx] [PATCH 0/1] Fix 'remove log size module parameters'
From: John Harrison The patch 'remove log size module parameters' broke loading the kernel when not compiling for debug. Fix it. Signed-off-by: John Harrison John Harrison (1): drm/i915/guc: Fix release build bug in 'remove log size module parameters' drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 25 +- 1 file changed, 1 insertion(+), 24 deletions(-) -- 2.37.3
[Intel-gfx] [PATCH 1/1] drm/i915/guc: Fix release build bug in 'remove log size module parameters'
From: John Harrison
A patch was merged to remove the GuC log size override module
parameters. That patch was broken and caused kernel error messages on
boot in non CONFIG_DEBUG_GUC|GEM builds:
[ 12.085121] i915 :00:02.0: [drm] *ERROR* Zero GuC log crash dump size!
[ 12.092035] i915 :00:02.0: [drm] *ERROR* Zero GuC log debug size!
So fit it.
Fixes: f54e515c9180 ("drm/i915/guc: Remove log size module parameters")
Cc: Joonas Lahtinen
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: Alan Previn
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Matthew Brost
Cc: Julia Lawall
Cc: Chris Wilson
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 25 +-
1 file changed, 1 insertion(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index b071973ac41c1..55d3ef93e86f8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -36,24 +36,6 @@ struct guc_log_section {
const char *name;
};
-static s32 scale_log_param(struct intel_guc_log *log, const struct
guc_log_section *section,
- s32 param)
-{
- /* -1 means default */
- if (param < 0)
- return section->default_val;
-
- /* Check for 32-bit overflow */
- if (param >= SZ_4K) {
- drm_err(&guc_to_gt(log_to_guc(log))->i915->drm, "Size too large
for GuC %s log: %dMB!",
- section->name, param);
- return section->default_val;
- }
-
- /* Param units are 1MB */
- return param * SZ_1M;
-}
-
static void _guc_log_init_sizes(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
@@ -78,15 +60,10 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
"capture",
}
};
- s32 params[GUC_LOG_SECTIONS_LIMIT] = {
- GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE / SZ_1M,
- GUC_LOG_DEFAULT_DEBUG_BUFFER_SIZE / SZ_1M,
- GUC_LOG_DEFAULT_CAPTURE_BUFFER_SIZE / SZ_1M,
- };
int i;
for (i = 0; i < GUC_LOG_SECTIONS_LIMIT; i++)
- log->sizes[i].bytes = scale_log_param(log, sections + i,
params[i]);
+ log->sizes[i].bytes = sections[i].default_val;
/* If debug size > 1MB then bump default crash size to keep the same
units */
if (log->sizes[GUC_LOG_SECTIONS_DEBUG].bytes >= SZ_1M &&
--
2.37.3
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Copy engine fuses future-proofing
== Series Details == Series: drm/i915: Copy engine fuses future-proofing URL : https://patchwork.freedesktop.org/series/108444/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12124 -> Patchwork_108444v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_108444v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_108444v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/index.html Participating hosts (41 -> 40) -- Additional (1): fi-hsw-4770 Missing(2): fi-ctg-p8600 fi-bdw-samus Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_108444v1: ### IGT changes ### Possible regressions * igt@i915_selftest@live@mman: - fi-rkl-guc: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-rkl-guc/igt@i915_selftest@l...@mman.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/fi-rkl-guc/igt@i915_selftest@l...@mman.html Known issues Here are the changes found in Patchwork_108444v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - fi-rkl-11600: NOTRUN -> [FAIL][3] ([fdo#103375]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html * igt@i915_pm_backlight@basic-brightness: - fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#3012]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@gem: - fi-blb-e6850: NOTRUN -> [DMESG-FAIL][5] ([i915#4528]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/fi-blb-e6850/igt@i915_selftest@l...@gem.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:NOTRUN -> [INCOMPLETE][6] ([i915#4785]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html - bat-dg1-5: NOTRUN -> [DMESG-FAIL][7] ([i915#4494] / [i915#4957]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick:[PASS][8] -> [DMESG-FAIL][9] ([i915#3428] / [i915#6217]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271]) +9 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-hsw-g3258: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html - fi-bsw-kefka: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/fi-bsw-kefka/igt@kms_chamel...@common-hpd-after-suspend.html - fi-rkl-11600: NOTRUN -> [SKIP][13] ([fdo#111827]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/fi-rkl-11600/igt@kms_chamel...@common-hpd-after-suspend.html - bat-dg1-5: NOTRUN -> [SKIP][14] ([fdo#111827]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/bat-dg1-5/igt@kms_chamel...@common-hpd-after-suspend.html - fi-pnv-d510:NOTRUN -> [SKIP][15] ([fdo#109271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-hsw-4770:NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +7 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html * igt@kms_pipe_crc_basic@suspend-read-crc: - bat-dg1-5: NOTRUN -> [SKIP][17] ([i915#4078]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/bat-dg1-5/igt@kms_pipe_crc_ba...@suspend-read-crc.html * igt@kms_psr@sprite_plane_onoff: - fi-hsw-4770:NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#1072]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108444v1/fi-hsw-4770/igt@kms_psr@sprite_
[Intel-gfx] ✓ Fi.CI.IGT: success for DGFX mmap with rpm (rev4)
== Series Details == Series: DGFX mmap with rpm (rev4) URL : https://patchwork.freedesktop.org/series/107400/ State : success == Summary == CI Bug Log - changes from CI_DRM_12123_full -> Patchwork_107400v4_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_107400v4_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-contexts-10ms: - shard-glk: [PASS][1] -> [TIMEOUT][2] ([i915#3063]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk9/igt@gem_...@in-flight-contexts-10ms.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/shard-glk1/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_eio@kms: - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#5784]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-tglb7/igt@gem_...@kms.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/shard-tglb1/igt@gem_...@kms.html * igt@gem_eio@unwedge-stress: - shard-iclb: [PASS][5] -> [TIMEOUT][6] ([i915#3070]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb2/igt@gem_...@unwedge-stress.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/shard-iclb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: [PASS][7] -> [SKIP][8] ([i915#4525]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb1/igt@gem_exec_balan...@parallel-bb-first.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/shard-iclb7/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk5/igt@gem_exec_fair@basic-throt...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_lmem_swapping@random-engines: - shard-tglb: NOTRUN -> [SKIP][11] ([i915#4613]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/shard-tglb1/igt@gem_lmem_swapp...@random-engines.html * igt@gem_pxp@fail-invalid-protected-context: - shard-tglb: NOTRUN -> [SKIP][12] ([i915#4270]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/shard-tglb1/igt@gem_...@fail-invalid-protected-context.html * igt@gen9_exec_parse@bb-large: - shard-tglb: NOTRUN -> [SKIP][13] ([i915#2527] / [i915#2856]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/shard-tglb1/igt@gen9_exec_pa...@bb-large.html * igt@i915_pm_dc@dc9-dpms: - shard-iclb: [PASS][14] -> [SKIP][15] ([i915#4281]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb8/igt@i915_pm...@dc9-dpms.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/shard-iclb3/igt@i915_pm...@dc9-dpms.html * igt@kms_big_fb@4-tiled-16bpp-rotate-180: - shard-tglb: NOTRUN -> [SKIP][16] ([i915#5286]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/shard-tglb1/igt@kms_big...@4-tiled-16bpp-rotate-180.html * igt@kms_big_fb@linear-64bpp-rotate-90: - shard-tglb: NOTRUN -> [SKIP][17] ([fdo#111614]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/shard-tglb1/igt@kms_big...@linear-64bpp-rotate-90.html * igt@kms_big_fb@x-tiled-32bpp-rotate-90: - shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271]) +32 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/shard-apl6/igt@kms_big...@x-tiled-32bpp-rotate-90.html * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs: - shard-tglb: NOTRUN -> [SKIP][19] ([i915#3689] / [i915#3886]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/shard-tglb1/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_rc_ccs_cc: - shard-tglb: NOTRUN -> [SKIP][20] ([i915#3689] / [i915#6095]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/shard-tglb1/igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_rc_ccs_cc.html * igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3886]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/shard-apl6/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][22] ([i915#3689]) +1 similar issue [22]: https:
[Intel-gfx] [PATCH v5 15/15] HAX: drm/i915: force INTEL_MEI_GSC and INTEL_MEI_PXP on for CI
Both are required for HuC loading. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Kconfig.debug | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index e7fd3e76f8a2..a6576ffbc4dc 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -48,6 +48,8 @@ config DRM_I915_DEBUG select DRM_I915_DEBUG_RUNTIME_PM select DRM_I915_SW_FENCE_DEBUG_OBJECTS select DRM_I915_SELFTEST + select INTEL_MEI_GSC + select INTEL_MEI_PXP select BROKEN # for prototype uAPI default n help -- 2.37.2
[Intel-gfx] [PATCH v5 13/15] drm/i915/huc: better define HuC status getparam possible return values.
The current HuC status getparam return values are a bit confusing in
regards to what happens in some scenarios. In particular, most of the
error cases cause the ioctl to return an error, but a couple of them,
INIT_FAIL and LOAD_FAIL, are not explicitly handled and neither is
their expected return value documented; these 2 error cases therefore
end up into the catch-all umbrella of the "HuC not loaded" case, with
this case therefore including both some error scenarios and the load
in progress one.
The updates included in this patch change the handling so that all
error cases behave the same way, i.e. return an errno code, and so
that the HuC load in progress case is unambiguous.
The patch also includes a small change to the FW init path to make sure
we always transition to an error state if something goes wrong.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Tony Ye
Acked-by: Tvrtko Ursulin
Acked-by: Tony Ye
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 14 +++---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 -
include/uapi/drm/i915_drm.h | 16
4 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index bac06e3d6f2c..27b09ba1d295 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -441,6 +441,7 @@ int intel_guc_init(struct intel_guc *guc)
err_fw:
intel_uc_fw_fini(&guc->fw);
out:
+ intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
i915_probe_error(gt->i915, "failed with %d\n", ret);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 5f2144c78f8a..4d1cc383b681 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -285,6 +285,7 @@ int intel_huc_init(struct intel_huc *huc)
return 0;
out:
+ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
drm_info(&i915->drm, "HuC init failed with %d\n", err);
return err;
}
@@ -404,13 +405,8 @@ bool intel_huc_is_authenticated(struct intel_huc *huc)
* This function reads status register to verify if HuC
* firmware was successfully loaded.
*
- * Returns:
- * * -ENODEV if HuC is not present on this platform,
- * * -EOPNOTSUPP if HuC firmware is disabled,
- * * -ENOPKG if HuC firmware was not installed,
- * * -ENOEXEC if HuC firmware is invalid or mismatched,
- * * 0 if HuC firmware is not running,
- * * 1 if HuC firmware is authenticated and running.
+ * The return values match what is expected for the I915_PARAM_HUC_STATUS
+ * getparam.
*/
int intel_huc_check_status(struct intel_huc *huc)
{
@@ -423,6 +419,10 @@ int intel_huc_check_status(struct intel_huc *huc)
return -ENOPKG;
case INTEL_UC_FIRMWARE_ERROR:
return -ENOEXEC;
+ case INTEL_UC_FIRMWARE_INIT_FAIL:
+ return -ENOMEM;
+ case INTEL_UC_FIRMWARE_LOAD_FAIL:
+ return -EIO;
default:
break;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index af425916cdf6..4792960d9c04 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -890,7 +890,6 @@ int intel_uc_fw_init(struct intel_uc_fw *uc_fw)
out_unpin:
i915_gem_object_unpin_pages(uc_fw->obj);
out:
- intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_INIT_FAIL);
return err;
}
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 520ad2691a99..629198f1d8d8 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -645,6 +645,22 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
+/*
+ * Query the status of HuC load.
+ *
+ * The query can fail in the following scenarios with the listed error codes:
+ * -ENODEV if HuC is not present on this platform,
+ * -EOPNOTSUPP if HuC firmware usage is disabled,
+ * -ENOPKG if HuC firmware fetch failed,
+ * -ENOEXEC if HuC firmware is invalid or mismatched,
+ * -ENOMEM if i915 failed to prepare the FW objects for transfer to the uC,
+ * -EIO if the FW transfer or the FW authentication failed.
+ *
+ * If the IOCTL is successful, the returned parameter will be set to one of the
+ * following values:
+ * * 0 if HuC firmware load is not complete,
+ * * 1 if HuC firmware is authenticated and running.
+ */
#define I915_PARAM_HUC_STATUS 42
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
--
2.37.2
[Intel-gfx] [PATCH v5 03/15] mei: adjust extended header kdocs
From: Tomas Winkler
Fix kdoc for struct mei_ext_hdr and mei_ext_begin().
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Greg Kroah-Hartman
---
V4: New in the series
V5: Rebase
drivers/misc/mei/hw.h | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/misc/mei/hw.h b/drivers/misc/mei/hw.h
index 70d405c67f0e..319418ddf4fb 100644
--- a/drivers/misc/mei/hw.h
+++ b/drivers/misc/mei/hw.h
@@ -247,8 +247,7 @@ enum mei_ext_hdr_type {
* struct mei_ext_hdr - extend header descriptor (TLV)
* @type: enum mei_ext_hdr_type
* @length: length excluding descriptor
- * @ext_payload: payload of the specific extended header
- * @hdr: place holder for actual header
+ * @data: the extended header payload
*/
struct mei_ext_hdr {
u8 type;
@@ -287,12 +286,11 @@ struct mei_ext_hdr_vtag {
* Extended header iterator functions
*/
/**
- * mei_ext_hdr - extended header iterator begin
+ * mei_ext_begin - extended header iterator begin
*
* @meta: meta header of the extended header list
*
- * Return:
- * The first extended header
+ * Return: The first extended header
*/
static inline struct mei_ext_hdr *mei_ext_begin(struct mei_ext_meta_hdr *meta)
{
--
2.37.2
[Intel-gfx] [PATCH v5 14/15] drm/i915/huc: define gsc-compatible HuC fw for DG2
The fw name is different and we need to record the fact that the blob is
gsc-loaded, so add a new macro to help.
Note: A-step DG2 G10 does not support HuC loading via GSC and would
require a separate firmware to be loaded the legacy way, but that's
not a production stepping so we're not going to bother.
v2: rebase on new fw fetch logic
Signed-off-by: Daniele Ceraolo Spurio
Cc: Tony Ye
Acked-by: Tony Ye
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 4792960d9c04..09e06ac8bcf1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -91,7 +91,8 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
fw_def(BROXTON, 0, guc_mmp(bxt, 70, 1, 1)) \
fw_def(SKYLAKE, 0, guc_mmp(skl, 70, 1, 1))
-#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp) \
+#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp, huc_gsc) \
+ fw_def(DG2, 0, huc_gsc(dg2)) \
fw_def(ALDERLAKE_P, 0, huc_mmp(tgl, 7, 9, 3)) \
fw_def(ALDERLAKE_S, 0, huc_mmp(tgl, 7, 9, 3)) \
fw_def(DG1, 0, huc_mmp(dg1, 7, 9, 3)) \
@@ -137,6 +138,9 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
#define MAKE_HUC_FW_PATH_BLANK(prefix_) \
__MAKE_UC_FW_PATH_BLANK(prefix_, "_huc")
+#define MAKE_HUC_FW_PATH_GSC(prefix_) \
+ __MAKE_UC_FW_PATH_BLANK(prefix_, "_huc_gsc")
+
#define MAKE_HUC_FW_PATH_MMP(prefix_, major_, minor_, patch_) \
__MAKE_UC_FW_PATH_MMP(prefix_, "_huc_", major_, minor_, patch_)
@@ -149,7 +153,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
MODULE_FIRMWARE(uc_);
INTEL_GUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH_MAJOR,
MAKE_GUC_FW_PATH_MMP)
-INTEL_HUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_HUC_FW_PATH_BLANK,
MAKE_HUC_FW_PATH_MMP)
+INTEL_HUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_HUC_FW_PATH_BLANK,
MAKE_HUC_FW_PATH_MMP, MAKE_HUC_FW_PATH_GSC)
/*
* The next expansion of the table macros (in __uc_fw_auto_select below)
provides
@@ -164,6 +168,7 @@ struct __packed uc_fw_blob {
u8 major;
u8 minor;
u8 patch;
+ bool loaded_via_gsc;
};
#define UC_FW_BLOB_BASE(major_, minor_, patch_, path_) \
@@ -172,16 +177,16 @@ struct __packed uc_fw_blob {
.patch = patch_, \
.path = path_,
-#define UC_FW_BLOB_NEW(major_, minor_, patch_, path_) \
+#define UC_FW_BLOB_NEW(major_, minor_, patch_, gsc_, path_) \
{ UC_FW_BLOB_BASE(major_, minor_, patch_, path_) \
- .legacy = false }
+ .legacy = false, .loaded_via_gsc = gsc_ }
#define UC_FW_BLOB_OLD(major_, minor_, patch_, path_) \
{ UC_FW_BLOB_BASE(major_, minor_, patch_, path_) \
.legacy = true }
#define GUC_FW_BLOB(prefix_, major_, minor_) \
- UC_FW_BLOB_NEW(major_, minor_, 0, \
+ UC_FW_BLOB_NEW(major_, minor_, 0, false, \
MAKE_GUC_FW_PATH_MAJOR(prefix_, major_, minor_))
#define GUC_FW_BLOB_MMP(prefix_, major_, minor_, patch_) \
@@ -189,12 +194,15 @@ struct __packed uc_fw_blob {
MAKE_GUC_FW_PATH_MMP(prefix_, major_, minor_, patch_))
#define HUC_FW_BLOB(prefix_) \
- UC_FW_BLOB_NEW(0, 0, 0, MAKE_HUC_FW_PATH_BLANK(prefix_))
+ UC_FW_BLOB_NEW(0, 0, 0, false, MAKE_HUC_FW_PATH_BLANK(prefix_))
#define HUC_FW_BLOB_MMP(prefix_, major_, minor_, patch_) \
UC_FW_BLOB_OLD(major_, minor_, patch_, \
MAKE_HUC_FW_PATH_MMP(prefix_, major_, minor_, patch_))
+#define HUC_FW_BLOB_GSC(prefix_) \
+ UC_FW_BLOB_NEW(0, 0, 0, true, MAKE_HUC_FW_PATH_GSC(prefix_))
+
struct __packed uc_fw_platform_requirement {
enum intel_platform p;
u8 rev; /* first platform rev using this FW */
@@ -220,7 +228,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct
intel_uc_fw *uc_fw)
INTEL_GUC_FIRMWARE_DEFS(MAKE_FW_LIST, GUC_FW_BLOB,
GUC_FW_BLOB_MMP)
};
static const struct uc_fw_platform_requirement blobs_huc[] = {
- INTEL_HUC_FIRMWARE_DEFS(MAKE_FW_LIST, HUC_FW_BLOB,
HUC_FW_BLOB_MMP)
+ INTEL_HUC_FIRMWARE_DEFS(MAKE_FW_LIST, HUC_FW_BLOB,
HUC_FW_BLOB_MMP, HUC_FW_BLOB_GSC)
};
static const struct fw_blobs_by_type blobs_all[INTEL_UC_FW_NUM_TYPES] =
{
[INTEL_UC_FW_TYPE_GUC] = { blobs_guc, ARRAY_SIZE(blobs_guc) },
@@ -266,6 +274,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct
intel_uc_fw *uc_fw)
uc_fw->file_wanted.path = blob->path;
uc_fw->file_wanted.major_ver = blob->major;
uc_fw->file_wanted.minor_ver = blob->minor;
+ uc_fw->loaded_via_gsc = blob->loaded_via_gsc;
break;
}
--
2.37.2
[Intel-gfx] [PATCH v5 01/15] mei: add support to GSC extended header
From: Tomas Winkler
GSC extend header is of variable size and data
is provided in a sgl list inside the header
and not in the data buffers, need to enable the path.
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Vitaly Lubart
Cc: Greg Kroah-Hartman
---
V2-3: Rebase
V4:
1. Add missing kdoc for mei_cl_cb
2. In mei_me_hbuf_write()
use dev_err() when validationg parameters instead of WARN_ON()
V5:
1. mei_ext_hdr_len: use if else instead of ?: (Greg)
2. add kdoc for gsc host to firmware interface structures
drivers/misc/mei/client.c| 55 +---
drivers/misc/mei/hbm.c | 13 ++
drivers/misc/mei/hw-me.c | 7 +++-
drivers/misc/mei/hw.h| 81
drivers/misc/mei/interrupt.c | 47 +
drivers/misc/mei/mei_dev.h | 4 ++
6 files changed, 184 insertions(+), 23 deletions(-)
diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c
index 0b2fbe1335a7..6c8b71ae32c8 100644
--- a/drivers/misc/mei/client.c
+++ b/drivers/misc/mei/client.c
@@ -322,6 +322,7 @@ void mei_io_cb_free(struct mei_cl_cb *cb)
list_del(&cb->list);
kfree(cb->buf.data);
+ kfree(cb->ext_hdr);
kfree(cb);
}
@@ -401,6 +402,7 @@ static struct mei_cl_cb *mei_io_cb_init(struct mei_cl *cl,
cb->buf_idx = 0;
cb->fop_type = type;
cb->vtag = 0;
+ cb->ext_hdr = NULL;
return cb;
}
@@ -1740,6 +1742,17 @@ static inline u8 mei_ext_hdr_set_vtag(void *ext, u8 vtag)
return vtag_hdr->hdr.length;
}
+static inline bool mei_ext_hdr_is_gsc(struct mei_ext_hdr *ext)
+{
+ return ext && ext->type == MEI_EXT_HDR_GSC;
+}
+
+static inline u8 mei_ext_hdr_set_gsc(struct mei_ext_hdr *ext, struct
mei_ext_hdr *gsc_hdr)
+{
+ memcpy(ext, gsc_hdr, mei_ext_hdr_len(gsc_hdr));
+ return ext->length;
+}
+
/**
* mei_msg_hdr_init - allocate and initialize mei message header
*
@@ -1752,14 +1765,17 @@ static struct mei_msg_hdr *mei_msg_hdr_init(const
struct mei_cl_cb *cb)
size_t hdr_len;
struct mei_ext_meta_hdr *meta;
struct mei_msg_hdr *mei_hdr;
- bool is_ext, is_vtag;
+ bool is_ext, is_hbm, is_gsc, is_vtag;
+ struct mei_ext_hdr *next_ext;
if (!cb)
return ERR_PTR(-EINVAL);
/* Extended header for vtag is attached only on the first fragment */
is_vtag = (cb->vtag && cb->buf_idx == 0);
- is_ext = is_vtag;
+ is_hbm = cb->cl->me_cl->client_id == 0;
+ is_gsc = ((!is_hbm) && cb->cl->dev->hbm_f_gsc_supported &&
mei_ext_hdr_is_gsc(cb->ext_hdr));
+ is_ext = is_vtag || is_gsc;
/* Compute extended header size */
hdr_len = sizeof(*mei_hdr);
@@ -1771,6 +1787,9 @@ static struct mei_msg_hdr *mei_msg_hdr_init(const struct
mei_cl_cb *cb)
if (is_vtag)
hdr_len += sizeof(struct mei_ext_hdr_vtag);
+ if (is_gsc)
+ hdr_len += mei_ext_hdr_len(cb->ext_hdr);
+
setup_hdr:
mei_hdr = kzalloc(hdr_len, GFP_KERNEL);
if (!mei_hdr)
@@ -1785,10 +1804,20 @@ static struct mei_msg_hdr *mei_msg_hdr_init(const
struct mei_cl_cb *cb)
goto out;
meta = (struct mei_ext_meta_hdr *)mei_hdr->extension;
+ meta->size = 0;
+ next_ext = (struct mei_ext_hdr *)meta->hdrs;
if (is_vtag) {
meta->count++;
- meta->size += mei_ext_hdr_set_vtag(meta->hdrs, cb->vtag);
+ meta->size += mei_ext_hdr_set_vtag(next_ext, cb->vtag);
+ next_ext = mei_ext_next(next_ext);
+ }
+
+ if (is_gsc) {
+ meta->count++;
+ meta->size += mei_ext_hdr_set_gsc(next_ext, cb->ext_hdr);
+ next_ext = mei_ext_next(next_ext);
}
+
out:
mei_hdr->length = hdr_len - sizeof(*mei_hdr);
return mei_hdr;
@@ -1812,14 +1841,14 @@ int mei_cl_irq_write(struct mei_cl *cl, struct
mei_cl_cb *cb,
struct mei_msg_hdr *mei_hdr = NULL;
size_t hdr_len;
size_t hbuf_len, dr_len;
- size_t buf_len;
+ size_t buf_len = 0;
size_t data_len;
int hbuf_slots;
u32 dr_slots;
u32 dma_len;
int rets;
bool first_chunk;
- const void *data;
+ const void *data = NULL;
if (WARN_ON(!cl || !cl->dev))
return -ENODEV;
@@ -1839,8 +1868,10 @@ int mei_cl_irq_write(struct mei_cl *cl, struct mei_cl_cb
*cb,
return 0;
}
- buf_len = buf->size - cb->buf_idx;
- data = buf->data + cb->buf_idx;
+ if (buf->data) {
+ buf_len = buf->size - cb->buf_idx;
+ data = buf->data + cb->buf_idx;
+ }
hbuf_slots = mei_hbuf_empty_slots(dev);
if (hbuf_slots < 0) {
rets = -EOVERFLOW;
@@ -1858,9 +1889,6 @@ int mei_cl_irq_write(struct mei_cl *cl, struct mei_cl_cb
*cb,
goto err;
}
- cl_dbg(d
[Intel-gfx] [PATCH v5 08/15] drm/i915/pxp: implement function for sending tee stream command
From: Vitaly Lubart
Command to be sent via the stream interface are written to a local
memory page, whose address is then provided to the GSC.
The interface supports providing a full sg with multiple pages for both
input and output messages, but since for now we only aim to support short
and synchronous messages we can use a single page for both input and
output.
Note that the mei interface expects an sg of 4k pages, while our lmem pages
are 64k. If we ever need to support more than 4k we'll need to convert.
Added a TODO comment to the code to record this.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Cc: Alan Previn
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 114 -
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 6 ++
3 files changed, 124 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 2c1fc49ecec1..e0d09455a92e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -7,6 +7,7 @@
#include
#include
+#include "gem/i915_gem_region.h"
#include "i915_drv.h"
#include "intel_pxp.h"
@@ -69,6 +70,47 @@ static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
return ret;
}
+int intel_pxp_tee_stream_message(struct intel_pxp *pxp,
+u8 client_id, u32 fence_id,
+void *msg_in, size_t msg_in_len,
+void *msg_out, size_t msg_out_len)
+{
+ /* TODO: for bigger objects we need to use a sg of 4k pages */
+ const size_t max_msg_size = PAGE_SIZE;
+ struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+ struct i915_pxp_component *pxp_component = pxp->pxp_component;
+ unsigned int offset = 0;
+ struct scatterlist *sg;
+ int ret;
+
+ if (msg_in_len > max_msg_size || msg_out_len > max_msg_size)
+ return -ENOSPC;
+
+ mutex_lock(&pxp->tee_mutex);
+
+ if (unlikely(!pxp_component || !pxp_component->ops->gsc_command)) {
+ ret = -ENODEV;
+ goto unlock;
+ }
+
+ GEM_BUG_ON(!pxp->stream_cmd.obj);
+
+ sg = i915_gem_object_get_sg_dma(pxp->stream_cmd.obj, 0, &offset);
+
+ memcpy(pxp->stream_cmd.vaddr, msg_in, msg_in_len);
+
+ ret = pxp_component->ops->gsc_command(pxp_component->tee_dev, client_id,
+ fence_id, sg, msg_in_len, sg);
+ if (ret < 0)
+ drm_err(&i915->drm, "Failed to send PXP TEE gsc command\n");
+ else
+ memcpy(msg_out, pxp->stream_cmd.vaddr, msg_out_len);
+
+unlock:
+ mutex_unlock(&pxp->tee_mutex);
+ return ret;
+}
+
/**
* i915_pxp_tee_component_bind - bind function to pass the function pointers
to pxp_tee
* @i915_kdev: pointer to i915 kernel device
@@ -126,6 +168,66 @@ static const struct component_ops
i915_pxp_tee_component_ops = {
.unbind = i915_pxp_tee_component_unbind,
};
+static int alloc_streaming_command(struct intel_pxp *pxp)
+{
+ struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+ struct drm_i915_gem_object *obj = NULL;
+ void *cmd;
+ int err;
+
+ pxp->stream_cmd.obj = NULL;
+ pxp->stream_cmd.vaddr = NULL;
+
+ if (!IS_DGFX(i915))
+ return 0;
+
+ /* allocate lmem object of one page for PXP command memory and store it
*/
+ obj = i915_gem_object_create_lmem(i915, PAGE_SIZE,
I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ drm_err(&i915->drm, "Failed to allocate pxp streaming
command!\n");
+ return PTR_ERR(obj);
+ }
+
+ err = i915_gem_object_pin_pages_unlocked(obj);
+ if (err) {
+ drm_err(&i915->drm, "Failed to pin gsc message page!\n");
+ goto out_put;
+ }
+
+ /* map the lmem into the virtual memory pointer */
+ cmd = i915_gem_object_pin_map_unlocked(obj,
i915_coherent_map_type(i915, obj, true));
+ if (IS_ERR(cmd)) {
+ drm_err(&i915->drm, "Failed to map gsc message page!\n");
+ err = PTR_ERR(cmd);
+ goto out_unpin;
+ }
+
+ memset(cmd, 0, obj->base.size);
+
+ pxp->stream_cmd.obj = obj;
+ pxp->stream_cmd.vaddr = cmd;
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+ return err;
+}
+
+static void free_streaming_command(struct intel_pxp *pxp)
+{
+ struct drm_i915_gem_object *obj = fetch_and_zero(&pxp->stream_cmd.obj);
+
+ if (!obj)
+ return;
+
+ i915_gem_object_unpin_map(obj);
+ i915_gem_object_unpin_pages(obj);
+ i915_gem_object_put(obj);
+}
+
int intel_pxp_tee_component_init(struct intel_pxp *pxp)
[Intel-gfx] [PATCH v5 11/15] drm/i915/huc: track delayed HuC load with a fence
Given that HuC load is delayed on DG2, this patch adds support for a fence
that can be used to wait for load completion. No waiters are added in this
patch (they're coming up in the next one), to keep the focus of the
patch on the tracking logic.
The full HuC loading flow on boot DG2 is as follows:
1) i915 exports the GSC as an aux device;
2) the mei-gsc driver is loaded on the aux device;
3) the mei-pxp component is loaded;
4) mei-pxp calls back into i915 and we load the HuC.
Between steps 1 and 2 there can be several seconds of gap, mainly due to
the kernel doing other work during the boot.
The resume flow is slightly different, because we don't need to
re-expose or re-probe the aux device, so we go directly to step 3 once
i915 and mei-gsc have completed their resume flow.
Here's an example of the boot timing, captured with some logs added to
i915:
[ 17.908307] [drm] adding GSC device
[ 17.915717] [drm] i915 probe done
[ 22.282917] [drm] mei-gsc bound
[ 22.938153] [drm] HuC authenticated
Also to note is that if something goes wrong during GSC HW init the
mei-gsc driver will still bind, but steps 3 and 4 will not happen.
The status tracking is done by registering a bus_notifier to receive a
callback when the mei-gsc driver binds, with a large enough timeout to
account for delays. Once mei-gsc is bound, we switch to a smaller
timeout to wait for the mei-pxp component to load.
The fence is signalled on HuC load complete or if anything goes wrong in
any of the tracking steps. Timeout are enforced via hrtimer callbacks.
v2: fix includes (Jani)
v5: gsc_notifier() remove unneeded ()
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/gt/intel_gsc.c| 22 ++-
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 199 +
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 +++
3 files changed, 241 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c
b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 7af6db3194dd..f544f70401f8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -142,8 +142,14 @@ static void gsc_destroy_one(struct drm_i915_private *i915,
struct intel_gsc_intf *intf = &gsc->intf[intf_id];
if (intf->adev) {
- auxiliary_device_delete(&intf->adev->aux_dev);
- auxiliary_device_uninit(&intf->adev->aux_dev);
+ struct auxiliary_device *aux_dev = &intf->adev->aux_dev;
+
+ if (intf_id == 0)
+
intel_huc_unregister_gsc_notifier(&gsc_to_gt(gsc)->uc.huc,
+ aux_dev->dev.bus);
+
+ auxiliary_device_delete(aux_dev);
+ auxiliary_device_uninit(aux_dev);
intf->adev = NULL;
}
@@ -242,14 +248,24 @@ static void gsc_init_one(struct drm_i915_private *i915,
struct intel_gsc *gsc,
goto fail;
}
+ intf->adev = adev; /* needed by the notifier */
+
+ if (intf_id == 0)
+ intel_huc_register_gsc_notifier(&gsc_to_gt(gsc)->uc.huc,
+ aux_dev->dev.bus);
+
ret = auxiliary_device_add(aux_dev);
if (ret < 0) {
drm_err(&i915->drm, "gsc aux add failed %d\n", ret);
+ if (intf_id == 0)
+
intel_huc_unregister_gsc_notifier(&gsc_to_gt(gsc)->uc.huc,
+ aux_dev->dev.bus);
+ intf->adev = NULL;
+
/* adev will be freed with the put_device() and .release
sequence */
auxiliary_device_uninit(aux_dev);
goto fail;
}
- intf->adev = adev;
return;
fail:
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index f0188931d8e4..5f2144c78f8a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -10,6 +10,9 @@
#include "intel_huc.h"
#include "i915_drv.h"
+#include
+#include
+
/**
* DOC: HuC
*
@@ -42,6 +45,164 @@
* HuC-specific commands.
*/
+/*
+ * MEI-GSC load is an async process. The probing of the exposed aux device
+ * (see intel_gsc.c) usually happens a few seconds after i915 probe, depending
+ * on when the kernel schedules it. Unless something goes terribly wrong, we're
+ * guaranteed for this to happen during boot, so the big timeout is a safety
net
+ * that we never expect to need.
+ * MEI-PXP + HuC load usually takes ~300ms, but if the GSC needs to be resumed
+ * and/or reset, this can take longer.
+ */
+#define GSC_INIT_TIMEOUT_MS 1
+#define PXP_INIT_TIMEOUT_MS 2000
+
+static int sw_fence_dummy_notify(struct i915_sw_fence *sf,
+enum i915_sw_fence_notify state)
+{
+ return NOTIFY_DONE;
+}
+
+static void __delayed_huc_load_complete(struct intel_huc *huc)
+{
+ if (!i915_sw_fenc
[Intel-gfx] [PATCH v5 12/15] drm/i915/huc: stall media submission until HuC is loaded
Wait on the fence to be signalled to avoid the submissions finding HuC
not yet loaded.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Tony Ye
Reviewed-by: Alan Previn
Acked-by: Tony Ye
---
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 6 ++
drivers/gpu/drm/i915/i915_request.c| 24
2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index 915d281c1c72..52db03620c60 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -81,6 +81,12 @@ static inline bool intel_huc_is_loaded_by_gsc(const struct
intel_huc *huc)
return huc->fw.loaded_via_gsc;
}
+static inline bool intel_huc_wait_required(struct intel_huc *huc)
+{
+ return intel_huc_is_used(huc) && intel_huc_is_loaded_by_gsc(huc) &&
+ !intel_huc_is_authenticated(huc);
+}
+
void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p);
#endif
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 62fad16a55e8..77f45a3cb01f 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1621,6 +1621,20 @@ i915_request_await_object(struct i915_request *to,
return ret;
}
+static void i915_request_await_huc(struct i915_request *rq)
+{
+ struct intel_huc *huc = &rq->context->engine->gt->uc.huc;
+
+ /* don't stall kernel submissions! */
+ if (!rcu_access_pointer(rq->context->gem_context))
+ return;
+
+ if (intel_huc_wait_required(huc))
+ i915_sw_fence_await_sw_fence(&rq->submit,
+&huc->delayed_load.fence,
+&rq->submitq);
+}
+
static struct i915_request *
__i915_request_ensure_parallel_ordering(struct i915_request *rq,
struct intel_timeline *timeline)
@@ -1702,6 +1716,16 @@ __i915_request_add_to_timeline(struct i915_request *rq)
struct intel_timeline *timeline = i915_request_timeline(rq);
struct i915_request *prev;
+ /*
+* Media workloads may require HuC, so stall them until HuC loading is
+* complete. Note that HuC not being loaded when a user submission
+* arrives can only happen when HuC is loaded via GSC and in that case
+* we still expect the window between us starting to accept submissions
+* and HuC loading completion to be small (a few hundred ms).
+*/
+ if (rq->engine->class == VIDEO_DECODE_CLASS)
+ i915_request_await_huc(rq);
+
/*
* Dependency tracking and request ordering along the timeline
* is special cased so that we can eliminate redundant ordering
--
2.37.2
[Intel-gfx] [PATCH v5 10/15] drm/i915/dg2: setup HuC loading via GSC
The GSC will perform both the load and the authentication, so we just
need to check the auth bit after the GSC has replied.
Since we require the PXP module to load the HuC, the earliest we can
trigger the load is during the pxp_bind operation.
Note that GSC-loaded HuC survives GT reset, so we need to just mark it
as ready when we re-init the GT HW.
V2: move setting of HuC fw error state to the failure path of the HuC
auth function, so it covers both the legacy and new auth flows
V4:
1. Fix typo in the commit message
2. style fix in intel_huc_wait_for_auth_complete()
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 41 +++
drivers/gpu/drm/i915/gt/uc/intel_huc.h| 2 ++
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 34 +++
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 14 +++-
5 files changed, 77 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 3bb8838e325a..f0188931d8e4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -125,6 +125,28 @@ void intel_huc_fini(struct intel_huc *huc)
intel_uc_fw_fini(&huc->fw);
}
+int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
+{
+ struct intel_gt *gt = huc_to_gt(huc);
+ int ret;
+
+ ret = __intel_wait_for_register(gt->uncore,
+ huc->status.reg,
+ huc->status.mask,
+ huc->status.value,
+ 2, 50, NULL);
+
+ if (ret) {
+ drm_err(>->i915->drm, "HuC: Firmware not verified %d\n", ret);
+ intel_uc_fw_change_status(&huc->fw,
INTEL_UC_FIRMWARE_LOAD_FAIL);
+ return ret;
+ }
+
+ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
+ drm_info(>->i915->drm, "HuC authenticated\n");
+ return 0;
+}
+
/**
* intel_huc_auth() - Authenticate HuC uCode
* @huc: intel_huc structure
@@ -161,27 +183,18 @@ int intel_huc_auth(struct intel_huc *huc)
}
/* Check authentication status, it should be done by now */
- ret = __intel_wait_for_register(gt->uncore,
- huc->status.reg,
- huc->status.mask,
- huc->status.value,
- 2, 50, NULL);
- if (ret) {
- DRM_ERROR("HuC: Firmware not verified %d\n", ret);
+ ret = intel_huc_wait_for_auth_complete(huc);
+ if (ret)
goto fail;
- }
- intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
- drm_info(>->i915->drm, "HuC authenticated\n");
return 0;
fail:
i915_probe_error(gt->i915, "HuC: Authentication failed %d\n", ret);
- intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
return ret;
}
-static bool huc_is_authenticated(struct intel_huc *huc)
+bool intel_huc_is_authenticated(struct intel_huc *huc)
{
struct intel_gt *gt = huc_to_gt(huc);
intel_wakeref_t wakeref;
@@ -223,7 +236,7 @@ int intel_huc_check_status(struct intel_huc *huc)
break;
}
- return huc_is_authenticated(huc);
+ return intel_huc_is_authenticated(huc);
}
void intel_huc_update_auth_status(struct intel_huc *huc)
@@ -231,7 +244,7 @@ void intel_huc_update_auth_status(struct intel_huc *huc)
if (!intel_uc_fw_is_loadable(&huc->fw))
return;
- if (huc_is_authenticated(huc))
+ if (intel_huc_is_authenticated(huc))
intel_uc_fw_change_status(&huc->fw,
INTEL_UC_FIRMWARE_RUNNING);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index d7e25b6e879e..51f9d96a3ca3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -26,8 +26,10 @@ void intel_huc_init_early(struct intel_huc *huc);
int intel_huc_init(struct intel_huc *huc);
void intel_huc_fini(struct intel_huc *huc);
int intel_huc_auth(struct intel_huc *huc);
+int intel_huc_wait_for_auth_complete(struct intel_huc *huc);
int intel_huc_check_status(struct intel_huc *huc);
void intel_huc_update_auth_status(struct intel_huc *huc);
+bool intel_huc_is_authenticated(struct intel_huc *huc);
static inline int intel_huc_sanitize(struct intel_huc *huc)
{
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 9d6ab1e01639..4f246416db17 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -3,9 +3,43 @@
* Copyright ©
[Intel-gfx] [PATCH v5 04/15] mei: bus: extend bus API to support command streamer API
From: Vitaly Lubart
Add mei bus API for sending gsc commands: mei_cldev_send_gsc_command()
The GSC commands are originated in the graphics stack
and are in form of SGL DMA buffers.
The GSC commands are synchronous, the response is received
in the same call on the out sg list buffers.
The function setups pointers for in and out sg lists in the
mei sgl extended header and sends it to the firmware.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Greg Kroah-Hartman
---
V2:
1. More detailed commit message
2. Fix typo in the comments
V3-4:Rebase
V5:
1. Use forward declaration instead of
#include in mei_cl_bus.h
drivers/misc/mei/bus.c | 126 +
include/linux/mei_cl_bus.h | 6 ++
2 files changed, 132 insertions(+)
diff --git a/drivers/misc/mei/bus.c b/drivers/misc/mei/bus.c
index 225f0b04c021..1fbe127ff633 100644
--- a/drivers/misc/mei/bus.c
+++ b/drivers/misc/mei/bus.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include "mei_dev.h"
@@ -838,6 +839,131 @@ int mei_cldev_disable(struct mei_cl_device *cldev)
}
EXPORT_SYMBOL_GPL(mei_cldev_disable);
+/**
+ * mei_cldev_send_gsc_command - sends a gsc command, by sending
+ * a gsl mei message to gsc and receiving reply from gsc
+ *
+ * @cldev: me client device
+ * @client_id: client id to send the command to
+ * @fence_id: fence id to send the command to
+ * @sg_in: scatter gather list containing addresses for rx message buffer
+ * @total_in_len: total length of data in 'in' sg, can be less than the sum of
buffers sizes
+ * @sg_out: scatter gather list containing addresses for tx message buffer
+ *
+ * Return:
+ * * written size in bytes
+ * * < 0 on error
+ */
+ssize_t mei_cldev_send_gsc_command(struct mei_cl_device *cldev,
+ u8 client_id, u32 fence_id,
+ struct scatterlist *sg_in,
+ size_t total_in_len,
+ struct scatterlist *sg_out)
+{
+ struct mei_cl *cl;
+ struct mei_device *bus;
+ ssize_t ret = 0;
+
+ struct mei_ext_hdr_gsc_h2f *ext_hdr;
+ size_t buf_sz = sizeof(struct mei_ext_hdr_gsc_h2f);
+ int sg_out_nents, sg_in_nents;
+ int i;
+ struct scatterlist *sg;
+ struct mei_ext_hdr_gsc_f2h rx_msg;
+ unsigned int sg_len;
+
+ if (!cldev || !sg_in || !sg_out)
+ return -EINVAL;
+
+ cl = cldev->cl;
+ bus = cldev->bus;
+
+ dev_dbg(bus->dev, "client_id %u, fence_id %u\n", client_id, fence_id);
+
+ if (!bus->hbm_f_gsc_supported)
+ return -EOPNOTSUPP;
+
+ sg_out_nents = sg_nents(sg_out);
+ sg_in_nents = sg_nents(sg_in);
+ /* at least one entry in tx and rx sgls must be present */
+ if (sg_out_nents <= 0 || sg_in_nents <= 0)
+ return -EINVAL;
+
+ buf_sz += (sg_out_nents + sg_in_nents) * sizeof(struct mei_gsc_sgl);
+ ext_hdr = kzalloc(buf_sz, GFP_KERNEL);
+ if (!ext_hdr)
+ return -ENOMEM;
+
+ /* construct the GSC message */
+ ext_hdr->hdr.type = MEI_EXT_HDR_GSC;
+ ext_hdr->hdr.length = buf_sz / sizeof(u32); /* length is in dw */
+
+ ext_hdr->client_id = client_id;
+ ext_hdr->addr_type = GSC_ADDRESS_TYPE_PHYSICAL_SGL;
+ ext_hdr->fence_id = fence_id;
+ ext_hdr->input_address_count = sg_in_nents;
+ ext_hdr->output_address_count = sg_out_nents;
+ ext_hdr->reserved[0] = 0;
+ ext_hdr->reserved[1] = 0;
+
+ /* copy in-sgl to the message */
+ for (i = 0, sg = sg_in; i < sg_in_nents; i++, sg++) {
+ ext_hdr->sgl[i].low = lower_32_bits(sg_dma_address(sg));
+ ext_hdr->sgl[i].high = upper_32_bits(sg_dma_address(sg));
+ sg_len = min_t(unsigned int, sg_dma_len(sg), PAGE_SIZE);
+ ext_hdr->sgl[i].length = (sg_len <= total_in_len) ? sg_len :
total_in_len;
+ total_in_len -= ext_hdr->sgl[i].length;
+ }
+
+ /* copy out-sgl to the message */
+ for (i = sg_in_nents, sg = sg_out; i < sg_in_nents + sg_out_nents; i++,
sg++) {
+ ext_hdr->sgl[i].low = lower_32_bits(sg_dma_address(sg));
+ ext_hdr->sgl[i].high = upper_32_bits(sg_dma_address(sg));
+ sg_len = min_t(unsigned int, sg_dma_len(sg), PAGE_SIZE);
+ ext_hdr->sgl[i].length = sg_len;
+ }
+
+ /* send the message to GSC */
+ ret = __mei_cl_send(cl, (u8 *)ext_hdr, buf_sz, 0, MEI_CL_IO_SGL);
+ if (ret < 0) {
+ dev_err(bus->dev, "__mei_cl_send failed, returned %zd\n", ret);
+ goto end;
+ }
+ if (ret != buf_sz) {
+ dev_err(bus->dev, "__mei_cl_send returned %zd instead of
expected %zd\n",
+ ret, buf_sz);
+ ret = -EIO;
+ goto end;
+ }
+
+ /* receive the
[Intel-gfx] [PATCH v5 07/15] drm/i915/pxp: load the pxp module when we have a gsc-loaded huc
The mei_pxp module is required to send the command to load authenticate
the HuC to the GSC even if pxp is not in use for protected content
management.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile| 10 +++---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 32 +---
drivers/gpu/drm/i915/pxp/intel_pxp.h | 32
drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 8 +
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 8 -
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 11 +--
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 10 --
7 files changed, 57 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a26edcdadc21..26fc2f23c4e0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -309,15 +309,17 @@ i915-y += \
i915-y += i915_perf.o
-# Protected execution platform (PXP) support
-i915-$(CONFIG_DRM_I915_PXP) += \
+# Protected execution platform (PXP) support. Base support is required for HuC
+i915-y += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_tee.o
+
+i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_debugfs.o \
pxp/intel_pxp_irq.o \
pxp/intel_pxp_pm.o \
- pxp/intel_pxp_session.o \
- pxp/intel_pxp_tee.o
+ pxp/intel_pxp_session.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 69cdaaddc4a9..5efe61f67546 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -103,19 +103,15 @@ static int create_vcs_context(struct intel_pxp *pxp)
static void destroy_vcs_context(struct intel_pxp *pxp)
{
- intel_engine_destroy_pinned_context(fetch_and_zero(&pxp->ce));
+ if (pxp->ce)
+ intel_engine_destroy_pinned_context(fetch_and_zero(&pxp->ce));
}
-void intel_pxp_init(struct intel_pxp *pxp)
+static void pxp_init_full(struct intel_pxp *pxp)
{
struct intel_gt *gt = pxp_to_gt(pxp);
int ret;
- if (!HAS_PXP(gt->i915))
- return;
-
- mutex_init(&pxp->tee_mutex);
-
/*
* we'll use the completion to check if there is a termination pending,
* so we start it as completed and we reinit it when a termination
@@ -124,8 +120,7 @@ void intel_pxp_init(struct intel_pxp *pxp)
init_completion(&pxp->termination);
complete_all(&pxp->termination);
- mutex_init(&pxp->arb_mutex);
- INIT_WORK(&pxp->session_work, intel_pxp_session_work);
+ intel_pxp_session_management_init(pxp);
ret = create_vcs_context(pxp);
if (ret)
@@ -143,11 +138,26 @@ void intel_pxp_init(struct intel_pxp *pxp)
destroy_vcs_context(pxp);
}
-void intel_pxp_fini(struct intel_pxp *pxp)
+void intel_pxp_init(struct intel_pxp *pxp)
{
- if (!intel_pxp_is_enabled(pxp))
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
+ /* we rely on the mei PXP module */
+ if (!IS_ENABLED(CONFIG_INTEL_MEI_PXP))
return;
+ /*
+* If HuC is loaded by GSC but PXP is disabled, we can skip the init of
+* the full PXP session/object management and just init the tee channel.
+*/
+ if (HAS_PXP(gt->i915))
+ pxp_init_full(pxp);
+ else if (intel_huc_is_loaded_by_gsc(>->uc.huc) &&
intel_uc_uses_huc(>->uc))
+ intel_pxp_tee_component_init(pxp);
+}
+
+void intel_pxp_fini(struct intel_pxp *pxp)
+{
pxp->arb_is_valid = false;
intel_pxp_tee_component_fini(pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 73847e535cab..2da309088c6d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -12,7 +12,6 @@
struct intel_pxp;
struct drm_i915_gem_object;
-#ifdef CONFIG_DRM_I915_PXP
struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp);
bool intel_pxp_is_enabled(const struct intel_pxp *pxp);
bool intel_pxp_is_active(const struct intel_pxp *pxp);
@@ -32,36 +31,5 @@ int intel_pxp_key_check(struct intel_pxp *pxp,
bool assign);
void intel_pxp_invalidate(struct intel_pxp *pxp);
-#else
-static inline void intel_pxp_init(struct intel_pxp *pxp)
-{
-}
-
-static inline void intel_pxp_fini(struct intel_pxp *pxp)
-{
-}
-
-static inline int intel_pxp_start(struct intel_pxp *pxp)
-{
- return -ENODEV;
-}
-
-static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
-{
- return false;
-}
-
-static inline bool intel_pxp_is_active(const struct intel_pxp *pxp)
-{
- return false;
-}
-
-static inline int intel_pxp_key_check(struct intel_pxp *pxp,
- struct drm_i915_gem_object *obj,
-
[Intel-gfx] [PATCH v5 06/15] mei: pxp: support matching with a gfx discrete card
From: Tomas Winkler
With on-boards graphics card, both i915 and MEI
are in the same device hierarchy with the same parent,
while for discrete gfx card the MEI is its child device.
Adjust the match function for that scenario
by matching MEI parent device with i915.
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Vitaly Lubart
Cc: Greg Kroah-Hartman
Reviewed-by: Alan Previn
---
V2:
1. More detailed commit message
2. Check for dev is not null before it is accessed.
V3-5: Rebase
drivers/misc/mei/pxp/mei_pxp.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
index f221464c4009..8dd09b1722eb 100644
--- a/drivers/misc/mei/pxp/mei_pxp.c
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -156,17 +156,24 @@ static int mei_pxp_component_match(struct device *dev,
int subcomponent,
{
struct device *base = data;
+ if (!dev)
+ return 0;
+
if (!dev->driver || strcmp(dev->driver->name, "i915") ||
subcomponent != I915_COMPONENT_PXP)
return 0;
base = base->parent;
- if (!base)
+ if (!base) /* mei device */
return 0;
- base = base->parent;
- dev = dev->parent;
+ base = base->parent; /* pci device */
+ /* for dgfx */
+ if (base && dev == base)
+ return 1;
+ /* for pch */
+ dev = dev->parent;
return (base && dev && dev == base);
}
--
2.37.2
[Intel-gfx] [PATCH v5 05/15] mei: pxp: add command streamer API to the PXP driver
From: Vitaly Lubart
The discrete graphics card with GSC firmware
using command streamer API hence it requires to enhance
pxp module with the new gsc_command() handler.
The handler is implemented via mei_pxp_gsc_command() which is
just a thin wrapper around mei_cldev_send_gsc_command()
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Greg Kroah-Hartman
Reviewed-by: Alan Previn
---
V2:
1. More detailed commit message
2. Fix typo in the comments
V3: Rebase
V4:
1. Use forward declaration for struct scatterlist (Jani)
2. Drop double 'just' in the commit message
V5:
1. Drop usless input params checks in mei_pxp_gsc_command (Greg)
drivers/misc/mei/pxp/mei_pxp.c | 25 +
include/drm/i915_pxp_tee_interface.h | 5 +
2 files changed, 30 insertions(+)
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
index 5c39457e3f53..f221464c4009 100644
--- a/drivers/misc/mei/pxp/mei_pxp.c
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -77,10 +77,35 @@ mei_pxp_receive_message(struct device *dev, void *buffer,
size_t size)
return byte;
}
+/**
+ * mei_pxp_gsc_command() - sends a gsc command, by sending
+ * a sgl mei message to gsc and receiving reply from gsc
+ *
+ * @dev: device corresponding to the mei_cl_device
+ * @client_id: client id to send the command to
+ * @fence_id: fence id to send the command to
+ * @sg_in: scatter gather list containing addresses for rx message buffer
+ * @total_in_len: total length of data in 'in' sg, can be less than the sum of
buffers sizes
+ * @sg_out: scatter gather list containing addresses for tx message buffer
+ *
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static ssize_t mei_pxp_gsc_command(struct device *dev, u8 client_id, u32
fence_id,
+ struct scatterlist *sg_in, size_t
total_in_len,
+ struct scatterlist *sg_out)
+{
+ struct mei_cl_device *cldev;
+
+ cldev = to_mei_cl_device(dev);
+
+ return mei_cldev_send_gsc_command(cldev, client_id, fence_id, sg_in,
total_in_len, sg_out);
+}
+
static const struct i915_pxp_component_ops mei_pxp_ops = {
.owner = THIS_MODULE,
.send = mei_pxp_send_message,
.recv = mei_pxp_receive_message,
+ .gsc_command = mei_pxp_gsc_command,
};
static int mei_component_master_bind(struct device *dev)
diff --git a/include/drm/i915_pxp_tee_interface.h
b/include/drm/i915_pxp_tee_interface.h
index af593ec64469..a702b6ec17f7 100644
--- a/include/drm/i915_pxp_tee_interface.h
+++ b/include/drm/i915_pxp_tee_interface.h
@@ -8,6 +8,7 @@
#include
#include
+struct scatterlist;
/**
* struct i915_pxp_component_ops - ops for PXP services.
@@ -23,6 +24,10 @@ struct i915_pxp_component_ops {
int (*send)(struct device *dev, const void *message, size_t size);
int (*recv)(struct device *dev, void *buffer, size_t size);
+ ssize_t (*gsc_command)(struct device *dev, u8 client_id, u32 fence_id,
+ struct scatterlist *sg_in, size_t total_in_len,
+ struct scatterlist *sg_out);
+
};
/**
--
2.37.2
[Intel-gfx] [PATCH v5 02/15] mei: bus: enable sending gsc commands
From: Tomas Winkler
GSC command is and extended header containing a scatter gather
list and without a data buffer. Using MEI_CL_IO_SGL flag,
the caller send the GSC command as a data and the function internally
moves it to the extended header.
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Vitaly Lubart
Cc: Greg Kroah-Hartman
---
V2-5: Rebase
drivers/misc/mei/bus.c | 20 ++--
drivers/misc/mei/mei_dev.h | 4
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/mei/bus.c b/drivers/misc/mei/bus.c
index 46aa3554e97b..225f0b04c021 100644
--- a/drivers/misc/mei/bus.c
+++ b/drivers/misc/mei/bus.c
@@ -100,9 +100,18 @@ ssize_t __mei_cl_send(struct mei_cl *cl, const u8 *buf,
size_t length, u8 vtag,
cb->internal = !!(mode & MEI_CL_IO_TX_INTERNAL);
cb->blocking = !!(mode & MEI_CL_IO_TX_BLOCKING);
memcpy(cb->buf.data, buf, length);
+ /* hack we point data to header */
+ if (mode & MEI_CL_IO_SGL) {
+ cb->ext_hdr = (struct mei_ext_hdr *)cb->buf.data;
+ cb->buf.data = NULL;
+ cb->buf.size = 0;
+ }
rets = mei_cl_write(cl, cb);
+ if (mode & MEI_CL_IO_SGL && rets == 0)
+ rets = length;
+
out:
mutex_unlock(&bus->device_lock);
@@ -205,9 +214,16 @@ ssize_t __mei_cl_recv(struct mei_cl *cl, u8 *buf, size_t
length, u8 *vtag,
goto free;
}
- r_length = min_t(size_t, length, cb->buf_idx);
- memcpy(buf, cb->buf.data, r_length);
+ /* for the GSC type - copy the extended header to the buffer */
+ if (cb->ext_hdr && cb->ext_hdr->type == MEI_EXT_HDR_GSC) {
+ r_length = min_t(size_t, length, cb->ext_hdr->length *
sizeof(u32));
+ memcpy(buf, cb->ext_hdr, r_length);
+ } else {
+ r_length = min_t(size_t, length, cb->buf_idx);
+ memcpy(buf, cb->buf.data, r_length);
+ }
rets = r_length;
+
if (vtag)
*vtag = cb->vtag;
diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h
index 31784bbc2d2a..8d8018428d9d 100644
--- a/drivers/misc/mei/mei_dev.h
+++ b/drivers/misc/mei/mei_dev.h
@@ -116,12 +116,16 @@ enum mei_cb_file_ops {
* @MEI_CL_IO_TX_INTERNAL: internal communication between driver and FW
*
* @MEI_CL_IO_RX_NONBLOCK: recv is non-blocking
+ *
+ * @MEI_CL_IO_SGL: send command with sgl list.
*/
enum mei_cl_io_mode {
MEI_CL_IO_TX_BLOCKING = BIT(0),
MEI_CL_IO_TX_INTERNAL = BIT(1),
MEI_CL_IO_RX_NONBLOCK = BIT(2),
+
+ MEI_CL_IO_SGL = BIT(3),
};
/*
--
2.37.2
[Intel-gfx] [PATCH v5 09/15] drm/i915/pxp: add huc authentication and loading command
From: Tomas Winkler
Add support for loading HuC via a pxp stream command.
V4:
1. Remove unnecessary include in intel_pxp_huc.h (Jani)
2. Adjust copyright year to 2022
Signed-off-by: Tomas Winkler
Signed-off-by: Vitaly Lubart
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp_huc.c | 69 +++
drivers/gpu/drm/i915/pxp/intel_pxp_huc.h | 13
.../drm/i915/pxp/intel_pxp_tee_interface.h| 23 ++-
4 files changed, 106 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 26fc2f23c4e0..f8cc1eb52626 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -312,7 +312,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support. Base support is required for HuC
i915-y += \
pxp/intel_pxp.o \
- pxp/intel_pxp_tee.o
+ pxp/intel_pxp_tee.o \
+ pxp/intel_pxp_huc.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_cmd.o \
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
new file mode 100644
index ..7ec36d94e758
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2021-2022, Intel Corporation. All rights reserved.
+ */
+
+#include "drm/i915_drm.h"
+#include "i915_drv.h"
+
+#include "gem/i915_gem_region.h"
+#include "gt/intel_gt.h"
+
+#include "intel_pxp.h"
+#include "intel_pxp_huc.h"
+#include "intel_pxp_tee.h"
+#include "intel_pxp_types.h"
+#include "intel_pxp_tee_interface.h"
+
+int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ struct intel_huc *huc = >->uc.huc;
+ struct pxp_tee_start_huc_auth_in huc_in = {0};
+ struct pxp_tee_start_huc_auth_out huc_out = {0};
+ dma_addr_t huc_phys_addr;
+ u8 client_id = 0;
+ u8 fence_id = 0;
+ int err;
+
+ if (!pxp->pxp_component)
+ return -ENODEV;
+
+ huc_phys_addr = i915_gem_object_get_dma_address(huc->fw.obj, 0);
+
+ /* write the PXP message into the lmem (the sg list) */
+ huc_in.header.api_version = PXP_TEE_43_APIVER;
+ huc_in.header.command_id = PXP_TEE_43_START_HUC_AUTH;
+ huc_in.header.status = 0;
+ huc_in.header.buffer_len = sizeof(huc_in.huc_base_address);
+ huc_in.huc_base_address = huc_phys_addr;
+
+ err = intel_pxp_tee_stream_message(pxp, client_id, fence_id,
+ &huc_in, sizeof(huc_in),
+ &huc_out, sizeof(huc_out));
+ if (err < 0) {
+ drm_err(>->i915->drm,
+ "Failed to send HuC load and auth command to GSC
[%d]!\n",
+ err);
+ return err;
+ }
+
+ /*
+* HuC does sometimes survive suspend/resume (it depends on how "deep"
+* a sleep state the device reaches) so we can end up here on resume
+* with HuC already loaded, in which case the GSC will return
+* PXP_STATUS_OP_NOT_PERMITTED. We can therefore consider the GuC
+* correctly transferred in this scenario; if the same error is ever
+* returned with HuC not loaded we'll still catch it when we check the
+* authentication bit later.
+*/
+ if (huc_out.header.status != PXP_STATUS_SUCCESS &&
+ huc_out.header.status != PXP_STATUS_OP_NOT_PERMITTED) {
+ drm_err(>->i915->drm,
+ "HuC load failed with GSC error = 0x%x\n",
+ huc_out.header.status);
+ return -EPROTO;
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
new file mode 100644
index ..e40847a91c39
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2021-2022, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_HUC_H__
+#define __INTEL_PXP_HUC_H__
+
+struct intel_pxp;
+
+int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_HUC_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
index 36e9b0868f5c..7edc1760f142 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
- * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ * Copyright(c) 2020-2022, Intel Corporation. All rights reserved.
*/
#ifndef __INTEL_PXP_TEE_INTERFACE_H__
[Intel-gfx] [PATCH v5 00/15] drm/i915: HuC loading for DG2
On DG2, HuC loading is performed by the GSC, via a PXP command. The load operation itself is relatively simple (just send a message to the GSC with the physical address of the HuC in LMEM), but there are timing changes that requires special attention. In particular, to send a PXP command we need to first export the GSC as an aux device and then wait for the mei-gsc and mei-pxp modules to start, which means that HuC load will complete after i915 load is complete. This means that there is a small window of time after i915 is registered and before HuC is loaded during which userspace could submit and/or check the HuC load status, although this is quite unlikely to happen (HuC is usually loaded before kernel init/resume completes). We've consulted with the media team in regards to how to handle this and they've asked us to stall all userspace VCS submission until HuC is loaded. Stalls are expected to be very rare (if any), due to the fact that HuC is usually loaded before kernel init/resume is completed. Timeouts are in place to ensure all submissions are unlocked in case something goes wrong. Since we need to monitor the status of the mei driver to know what's happening and when to time out, a notifier has been added so we get a callback when the status of the mei driver changes. Note that this series includes several mei patches that add support for sending the HuC loading command via mei-gsc. We plan to merge those patches through the drm tree because i915 is the sole user. v2: address review comments, Reporting HuC loading still in progress while we wait for mei-gsc init to complete, rebase on latest mei-gsc series. v3: fix cc list in mei patches. v4: update mei patches, fix includes, rebase on new FW fetch logic and merged mei-gsc support. v5: update mei patches Cc: Alan Previn Cc: Tony Ye Cc: Alexander Usyskin Cc: Tomas Winkler Cc: Greg Kroah-Hartman Daniele Ceraolo Spurio (7): drm/i915/pxp: load the pxp module when we have a gsc-loaded huc drm/i915/dg2: setup HuC loading via GSC drm/i915/huc: track delayed HuC load with a fence drm/i915/huc: stall media submission until HuC is loaded drm/i915/huc: better define HuC status getparam possible return values. drm/i915/huc: define gsc-compatible HuC fw for DG2 HAX: drm/i915: force INTEL_MEI_GSC and INTEL_MEI_PXP on for CI Tomas Winkler (5): mei: add support to GSC extended header mei: bus: enable sending gsc commands mei: adjust extended header kdocs mei: pxp: support matching with a gfx discrete card drm/i915/pxp: add huc authentication and loading command Vitaly Lubart (3): mei: bus: extend bus API to support command streamer API mei: pxp: add command streamer API to the PXP driver drm/i915/pxp: implement function for sending tee stream command drivers/gpu/drm/i915/Kconfig.debug| 2 + drivers/gpu/drm/i915/Makefile | 11 +- drivers/gpu/drm/i915/gt/intel_gsc.c | 22 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c| 1 + drivers/gpu/drm/i915/gt/uc/intel_huc.c| 254 -- drivers/gpu/drm/i915/gt/uc/intel_huc.h| 31 +++ drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 34 +++ drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 1 + drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 24 +- drivers/gpu/drm/i915/i915_request.c | 24 ++ drivers/gpu/drm/i915/pxp/intel_pxp.c | 32 ++- drivers/gpu/drm/i915/pxp/intel_pxp.h | 32 --- drivers/gpu/drm/i915/pxp/intel_pxp_huc.c | 69 + drivers/gpu/drm/i915/pxp/intel_pxp_huc.h | 13 + drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 8 + drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 8 +- drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 11 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 138 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 5 + .../drm/i915/pxp/intel_pxp_tee_interface.h| 23 +- drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 6 + drivers/misc/mei/bus.c| 146 +- drivers/misc/mei/client.c | 55 ++-- drivers/misc/mei/hbm.c| 13 + drivers/misc/mei/hw-me.c | 7 +- drivers/misc/mei/hw.h | 89 +- drivers/misc/mei/interrupt.c | 47 +++- drivers/misc/mei/mei_dev.h| 8 + drivers/misc/mei/pxp/mei_pxp.c| 38 ++- include/drm/i915_pxp_tee_interface.h | 5 + include/linux/mei_cl_bus.h| 6 + include/uapi/drm/i915_drm.h | 16 ++ 32 files changed, 1057 insertions(+), 122 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_huc.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_huc.h -- 2.37.2
Re: [Intel-gfx] [CI 1/2] drm/i915/uc: Support for version reduced and multiple firmware files
On 9/12/2022 5:23 PM, Lucas De Marchi wrote:
On Tue, Sep 06, 2022 at 04:01:46PM -0700, Daniele Ceraolo Spurio wrote:
@@ -184,49 +247,94 @@ __uc_fw_auto_select(struct drm_i915_private
*i915, struct intel_uc_fw *uc_fw)
fw_count = blobs_all[uc_fw->type].count;
for (i = 0; i < fw_count && p <= fw_blobs[i].p; i++) {
- if (p == fw_blobs[i].p && rev >= fw_blobs[i].rev) {
- const struct uc_fw_blob *blob = &fw_blobs[i].blob;
- uc_fw->path = blob->path;
- uc_fw->wanted_path = blob->path;
- uc_fw->major_ver_wanted = blob->major;
- uc_fw->minor_ver_wanted = blob->minor;
- break;
- }
- }
+ const struct uc_fw_blob *blob = &fw_blobs[i].blob;
- if (uc_fw->type == INTEL_UC_FW_TYPE_GUC) {
- const struct uc_fw_platform_requirement *blobs =
blobs_guc_fallback;
- u32 count = ARRAY_SIZE(blobs_guc_fallback);
+ if (p != fw_blobs[i].p)
+ continue;
- for (i = 0; i < count && p <= blobs[i].p; i++) {
- if (p == blobs[i].p && rev >= blobs[i].rev) {
- const struct uc_fw_blob *blob = &blobs[i].blob;
+ if (rev < fw_blobs[i].rev)
+ continue;
- uc_fw->fallback.path = blob->path;
- uc_fw->fallback.major_ver = blob->major;
- uc_fw->fallback.minor_ver = blob->minor;
- break;
- }
+ if (uc_fw->file_selected.path) {
+ if (uc_fw->file_selected.path == blob->path)
+ uc_fw->file_selected.path = NULL;
+
+ continue;
}
+
+ uc_fw->file_selected.path = blob->path;
+ uc_fw->file_wanted.path = blob->path;
+ uc_fw->file_wanted.major_ver = blob->major;
+ uc_fw->file_wanted.minor_ver = blob->minor;
+ break;
}
/* make sure the list is ordered as expected */
- if (IS_ENABLED(CONFIG_DRM_I915_SELFTEST)) {
+ if (IS_ENABLED(CONFIG_DRM_I915_SELFTEST) && !verified) {
+ verified = true;
+
for (i = 1; i < fw_count; i++) {
+ /* Next platform is good: */
if (fw_blobs[i].p < fw_blobs[i - 1].p)
continue;
+ /* Next platform revision is good: */
if (fw_blobs[i].p == fw_blobs[i - 1].p &&
fw_blobs[i].rev < fw_blobs[i - 1].rev)
continue;
- drm_err(&i915->drm, "Invalid FW blob order: %s r%u comes
before %s r%u\n",
- intel_platform_name(fw_blobs[i - 1].p),
- fw_blobs[i - 1].rev,
- intel_platform_name(fw_blobs[i].p),
- fw_blobs[i].rev);
+ /* Platform/revision must be in order: */
+ if (fw_blobs[i].p != fw_blobs[i - 1].p ||
+ fw_blobs[i].rev != fw_blobs[i - 1].rev)
+ goto bad;
+
+ /* Next major version is good: */
+ if (fw_blobs[i].blob.major < fw_blobs[i - 1].blob.major)
+ continue;
+
+ /* New must be before legacy: */
+ if (!fw_blobs[i].blob.legacy && fw_blobs[i -
1].blob.legacy)
+ goto bad;
+
+ /* New to legacy also means 0.0 to X.Y (HuC), or X.0 to
X.Y (GuC) */
+ if (fw_blobs[i].blob.legacy && !fw_blobs[i -
1].blob.legacy) {
+ if (!fw_blobs[i - 1].blob.major)
+ continue;
+
+ if (fw_blobs[i].blob.major == fw_blobs[i -
1].blob.major)
+ continue;
+ }
+
+ /* Major versions must be in order: */
+ if (fw_blobs[i].blob.major != fw_blobs[i - 1].blob.major)
+ goto bad;
+
+ /* Next minor version is good: */
+ if (fw_blobs[i].blob.minor < fw_blobs[i - 1].blob.minor)
+ continue;
- uc_fw->path = NULL;
+ /* Minor versions must be in order: */
+ if (fw_blobs[i].blob.minor != fw_blobs[i - 1].blob.minor)
+ goto bad;
+
+ /* Patch versions must be in order: */
+ if (fw_blobs[i].blob.patch <= fw_blobs[i - 1].blob.patch)
+ continue;
+
+bad:
+ drm_err(&i915->drm, "\x1B[35;1mInvalid FW blob order: %s
r%u %s%d.%d.%d comes before %s r%u %s%d.%d.%d\n",
what is this \x1B[35;1m? Probably something that went bad while
writing/pasting this?
Looks like it slipped in. Fix coming soon (John will send a v2 of "
drm/i915/uc: Fix issues with overriding firmware files" and include it
there).
Daniele
Lucas De Marchi
+ intel_platform_name(fw_blobs[i - 1].p), fw_blobs[i - 1].rev,
+ fw_blobs[i - 1].blob.legacy ? "L" : "v",
+ fw_blobs[i - 1].blob.major,
+ fw_blobs[i - 1].blob.minor,
+ fw_blobs[i - 1].blob.patch,
+ intel_platform_name(fw_blobs[i].p), fw_blobs[i].rev,
+ fw_blobs[i].blob.legacy ? "L" : "v",
+ fw_blobs[i].blob.major,
+ fw_blobs[i].bl
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: fix repeated words in comments (rev4)
== Series Details ==
Series: drm/i915: fix repeated words in comments (rev4)
URL : https://patchwork.freedesktop.org/series/107885/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12124 -> Patchwork_107885v4
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/index.html
Participating hosts (41 -> 40)
--
Additional (1): fi-hsw-4770
Missing(2): fi-ctg-p8600 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_107885v4 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#3012])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: NOTRUN -> [DMESG-FAIL][2] ([i915#4494] / [i915#4957])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-bsw-kefka: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/fi-bsw-kefka/igt@kms_chamel...@common-hpd-after-suspend.html
- bat-dg1-5: NOTRUN -> [SKIP][8] ([fdo#111827])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/bat-dg1-5/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-dg1-5: NOTRUN -> [SKIP][10] ([i915#4078])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/bat-dg1-5/igt@kms_pipe_crc_ba...@suspend-read-crc.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#1072]) +3
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
Possible fixes
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][12] ([i915#2867]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@gem_contexts:
- {bat-dg2-8}:[INCOMPLETE][14] ([i915#6523]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-5: [INCOMPLETE][16] ([i915#4418]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@gt_pm:
- {bat-rpls-2}: [DMESG-FAIL][18] ([i915#4258]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [INCOMPLETE][20] ([i915#3303] / [i915#4785]) ->
[PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12124/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107885v4/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@mman:
- {bat-rpls-2}:
Re: [Intel-gfx] [CI 1/2] drm/i915/uc: Support for version reduced and multiple firmware files
On Tue, Sep 06, 2022 at 04:01:46PM -0700, Daniele Ceraolo Spurio wrote:
@@ -184,49 +247,94 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct
intel_uc_fw *uc_fw)
fw_count = blobs_all[uc_fw->type].count;
for (i = 0; i < fw_count && p <= fw_blobs[i].p; i++) {
- if (p == fw_blobs[i].p && rev >= fw_blobs[i].rev) {
- const struct uc_fw_blob *blob = &fw_blobs[i].blob;
- uc_fw->path = blob->path;
- uc_fw->wanted_path = blob->path;
- uc_fw->major_ver_wanted = blob->major;
- uc_fw->minor_ver_wanted = blob->minor;
- break;
- }
- }
+ const struct uc_fw_blob *blob = &fw_blobs[i].blob;
- if (uc_fw->type == INTEL_UC_FW_TYPE_GUC) {
- const struct uc_fw_platform_requirement *blobs =
blobs_guc_fallback;
- u32 count = ARRAY_SIZE(blobs_guc_fallback);
+ if (p != fw_blobs[i].p)
+ continue;
- for (i = 0; i < count && p <= blobs[i].p; i++) {
- if (p == blobs[i].p && rev >= blobs[i].rev) {
- const struct uc_fw_blob *blob = &blobs[i].blob;
+ if (rev < fw_blobs[i].rev)
+ continue;
- uc_fw->fallback.path = blob->path;
- uc_fw->fallback.major_ver = blob->major;
- uc_fw->fallback.minor_ver = blob->minor;
- break;
- }
+ if (uc_fw->file_selected.path) {
+ if (uc_fw->file_selected.path == blob->path)
+ uc_fw->file_selected.path = NULL;
+
+ continue;
}
+
+ uc_fw->file_selected.path = blob->path;
+ uc_fw->file_wanted.path = blob->path;
+ uc_fw->file_wanted.major_ver = blob->major;
+ uc_fw->file_wanted.minor_ver = blob->minor;
+ break;
}
/* make sure the list is ordered as expected */
- if (IS_ENABLED(CONFIG_DRM_I915_SELFTEST)) {
+ if (IS_ENABLED(CONFIG_DRM_I915_SELFTEST) && !verified) {
+ verified = true;
+
for (i = 1; i < fw_count; i++) {
+ /* Next platform is good: */
if (fw_blobs[i].p < fw_blobs[i - 1].p)
continue;
+ /* Next platform revision is good: */
if (fw_blobs[i].p == fw_blobs[i - 1].p &&
fw_blobs[i].rev < fw_blobs[i - 1].rev)
continue;
- drm_err(&i915->drm, "Invalid FW blob order: %s r%u comes
before %s r%u\n",
- intel_platform_name(fw_blobs[i - 1].p),
- fw_blobs[i - 1].rev,
- intel_platform_name(fw_blobs[i].p),
- fw_blobs[i].rev);
+ /* Platform/revision must be in order: */
+ if (fw_blobs[i].p != fw_blobs[i - 1].p ||
+ fw_blobs[i].rev != fw_blobs[i - 1].rev)
+ goto bad;
+
+ /* Next major version is good: */
+ if (fw_blobs[i].blob.major < fw_blobs[i - 1].blob.major)
+ continue;
+
+ /* New must be before legacy: */
+ if (!fw_blobs[i].blob.legacy && fw_blobs[i -
1].blob.legacy)
+ goto bad;
+
+ /* New to legacy also means 0.0 to X.Y (HuC), or X.0 to
X.Y (GuC) */
+ if (fw_blobs[i].blob.legacy && !fw_blobs[i -
1].blob.legacy) {
+ if (!fw_blobs[i - 1].blob.major)
+ continue;
+
+ if (fw_blobs[i].blob.major == fw_blobs[i -
1].blob.major)
+ continue;
+ }
+
+ /* Major versions must be in order: */
+ if (fw_blobs[i].blob.major != fw_blobs[i -
1].blob.major)
+ goto bad;
+
+ /* Next minor version is good: */
+ if (fw_blobs[i].blob.minor < fw_blobs[i - 1].blob.minor)
+ continue;
- uc_fw->path = NULL;
+ /* Minor versions must be in order: */
+ if (fw_blobs[i].blob.minor != fw_blobs[i -
1].blob.minor)
+ goto bad;
+
+ /* Patch versions must be in order: */
+ if (fw_blobs[i].blob.patch <= fw_blobs[i -
1].blob.patch)
+
Re: [Intel-gfx] [PATCH 4/6] drm/i915: Use GEN12 RPSTAT register
On Mon, 12 Sep 2022 04:29:38 -0700, Nilawar, Badal wrote:
>
> >> diff --git a/drivers/gpu/drm/i915/i915_pmu.c
> >> b/drivers/gpu/drm/i915/i915_pmu.c
> >> index 958b37123bf1..a24704ec2c18 100644
> >> --- a/drivers/gpu/drm/i915/i915_pmu.c
> >> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> >> @@ -371,7 +371,6 @@ static void
> >> frequency_sample(struct intel_gt *gt, unsigned int period_ns)
> >> {
> >>struct drm_i915_private *i915 = gt->i915;
> >> - struct intel_uncore *uncore = gt->uncore;
> >>struct i915_pmu *pmu = &i915->pmu;
> >>struct intel_rps *rps = >->rps;
> >>
> >> @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int
> >> period_ns)
> >> * case we assume the system is running at the intended
> >> * frequency. Fortunately, the read should rarely fail!
> >> */
> >> - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
> >> + val = intel_rps_read_rpstat(rps);
> >
> > Hmm, we got rid of _fw which the comment above refers to. Maybe we need a
> > fw flag to intel_rps_read_rpstat?
>
> Above function before reading rpstat it checks if gt is awake.
Ok, so you are referring to intel_gt_pm_get_if_awake check in frequency_sample.
> So when gt is awake shouldn't matter if we read GEN6_RPSTAT1 with
> forcewake.In that case we can remove above comment. Let me know your
> thoughts on this.
I am not entirely sure about this. For example in c1c82d267ae8
intel_uncore_read_fw was introduced with the same intel_gt_pm_get_if_awake
check. So this would mean even if gt is awake not taking forcewake makes a
difference. The same code pattern was retained in b66ecd0438bf. Maybe it's
because there are no locks?
Under the circumstances I think we could do one of two things:
1. If we want to drop _fw, we should do it as a separate patch with its own
justification so it can be reviewed separately.
2. Otherwise as I mentioned we should retain the _fw and add a fw flag to
intel_rps_read_rpstat.
Thanks.
--
Ashutosh
> >>if (val)
> >>val = intel_rps_get_cagf(rps, val);
> >>else
> >> --
> >> 2.25.1
> >>
[Intel-gfx] [PATCH 1/1] drm/i915/uc: Fix issues with overriding firmware files
From: John Harrison
The earlier update to support reduced versioning of firmware files
introduced an issue with the firmware override module parameter. If an
invalid file was specified then an infinite loop could occur trying to
find a backup firmware.
The fix is that if an explicit override has been set, then don't scan
for backup options because there is no point anyway. The user wanted X
and if X is not available, that's their problem.
This patch also fixes up the scanning loop code so that if an invalid
file is passed in, it will exit rather than loop forever. So if the
impossible situation did somehow occur in the future, it wouldn't be
such a big problem.
Fixes: 665ae9c9ca79 ("drm/i915/uc: Support for version reduced and multiple
firmware files")
Cc: Daniele Ceraolo Spurio
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: Matthew Brost
Cc: Umesh Nerlige Ramappa
Cc: Matthew Auld
Cc: Alan Previn
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Vinay Belgaumkar
Cc: "Thomas Hellström"
Cc: Venkata Sandeep Dhanalakota
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index af425916cdf64..5ff98239b6c9f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -232,6 +232,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct
intel_uc_fw *uc_fw)
u32 fw_count;
u8 rev = INTEL_REVID(i915);
int i;
+ bool found;
/*
* The only difference between the ADL GuC FWs is the HWConfig support.
@@ -246,6 +247,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct
intel_uc_fw *uc_fw)
fw_blobs = blobs_all[uc_fw->type].blobs;
fw_count = blobs_all[uc_fw->type].count;
+ found = false;
for (i = 0; i < fw_count && p <= fw_blobs[i].p; i++) {
const struct uc_fw_blob *blob = &fw_blobs[i].blob;
@@ -266,9 +268,15 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct
intel_uc_fw *uc_fw)
uc_fw->file_wanted.path = blob->path;
uc_fw->file_wanted.major_ver = blob->major;
uc_fw->file_wanted.minor_ver = blob->minor;
+ found = true;
break;
}
+ if (!found && uc_fw->file_selected.path) {
+ /* Failed to find a match for the last attempt?! */
+ uc_fw->file_selected.path = NULL;
+ }
+
/* make sure the list is ordered as expected */
if (IS_ENABLED(CONFIG_DRM_I915_SELFTEST) && !verified) {
verified = true;
@@ -553,10 +561,14 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
err = firmware_request_nowarn(&fw, uc_fw->file_selected.path, dev);
memcpy(&file_ideal, &uc_fw->file_wanted, sizeof(file_ideal));
- if (!err || intel_uc_fw_is_overridden(uc_fw))
- goto done;
+
+ /* Any error is terminal if overriding. Don't bother searching for
older versions */
+ if (err && intel_uc_fw_is_overridden(uc_fw))
+ goto fail;
while (err == -ENOENT) {
+ old_ver = true;
+
__uc_fw_auto_select(i915, uc_fw);
if (!uc_fw->file_selected.path) {
/*
@@ -576,8 +588,6 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
if (err)
goto fail;
- old_ver = true;
-done:
if (uc_fw->loaded_via_gsc)
err = check_gsc_manifest(fw, uc_fw);
else
--
2.37.3
[Intel-gfx] [PATCH 0/1] Fix bug in version reduced firmware update
From: John Harrison The earlier patch to support firmware files with reduced versioning introduced an issue with the firmware override module parameter. So fix that. Signed-off-by: John Harrison John Harrison (1): drm/i915/uc: Fix issues with overriding firmware files drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 18 ++ 1 file changed, 14 insertions(+), 4 deletions(-) -- 2.37.3
Re: [Intel-gfx] [PATCH 6/7] drm/i915/guc: Make GuC log sizes runtime configurable
On 9/12/2022 00:12, Joonas Lahtinen wrote: Quoting Joonas Lahtinen (2022-08-26 09:23:08) Quoting John Harrison (2022-08-25 19:31:39) On 8/25/2022 00:15, Joonas Lahtinen wrote: Quoting John Harrison (2022-08-24 21:45:09) We also don't want to tie the GuC logging buffer size to the DRM debugging output. Enabling kernel debug output can change timings and prevent the issue that one is trying to capture in the GuC log. And it seems unlikely we could add an entire new top level DRM debug flag just for an internal i915 only log buffer size. Plus drm.debug is explicitly stated as being dynamically changeable via sysfs at any time. The GuC log buffer size cannot be changed without reloading the i915 driver. Or at least, not without reloading the GuC, but we definitely don't want to create a UAPI for arbitrarily reloading the GuC. We can make these parameters 'unsafe' so that they taint the kernel if used. But this is exactly what module parameters are for - configuration that we don't want to hardcode as CONFIG options but which must be set at module load time. It's better to have sane defaults. And if somebody wants something strange, they can have a Kconfig behind EXPERT option. But even then there should really be need for it. Define sane. I was hoping you would be the expert on that as you've suggested the patch to begin with. And as the 'expert' I suggested an approach that everyone was happy with except for yourself. Try to aim to cover >90% of the debug scenarios (that are only 0.001%) and we're already only needing to recompile kernel in 1 per million cases. We can live with that. This is not about how many instances of debug scenarios need a rebuild. It's about whether or not the person doing the repro has the ability to rebuild a custom kernel. I will push a fixup to remove the module parameters, please figure the rest out in a timely manner. Your fixup was evidently not tested because it broke non-debug builds. John, what is the status of the followup patch here to configure those reasonable defaults? We shouldn't be ignoring this and proceed to pile other GuC patches on top. Being out of office is not ignoring. And I don't see what other options we have. Setting a large default means that the vast majority of people who don't care about GuC will have their error capture logs filled with apparent gibberish in the form of a huge ASCII dump of the GuC log binary data. Which is something that people will surely complain about. Whereas setting a 'sensibly small' default means that we won't be able to use the GuC logs in many of the cases where we actually need to. So right now, it seems the only choice we have is to fix up the broken driver caused by your incomplete removal and then re-add the module parameter to our internal tree so that our internal customers can at least use it. John. Regards, Joonas
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Some house cleaning
== Series Details == Series: drm/i915: Some house cleaning URL : https://patchwork.freedesktop.org/series/108426/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12123_full -> Patchwork_108426v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_108426v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_108426v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 10) -- Missing(1): shard-rkl Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_108426v1_full: ### IGT changes ### Possible regressions * igt@gem_mmap@big-bo: - shard-glk: [PASS][1] -> [TIMEOUT][2] +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk6/igt@gem_m...@big-bo.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/shard-glk6/igt@gem_m...@big-bo.html Known issues Here are the changes found in Patchwork_108426v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@kms: - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#5784]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-tglb7/igt@gem_...@kms.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/shard-tglb1/igt@gem_...@kms.html * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb1/igt@gem_exec_balan...@parallel-bb-first.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/shard-iclb8/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][9] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk5/igt@gem_exec_fair@basic-throt...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/shard-glk1/igt@gem_exec_fair@basic-throt...@rcs0.html - shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/shard-iclb2/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_suspend@basic-s3@smem: - shard-apl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-apl2/igt@gem_exec_suspend@basic...@smem.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/shard-apl1/igt@gem_exec_suspend@basic...@smem.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][16] -> [FAIL][17] ([i915#454]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb6/igt@i915_pm...@dc6-dpms.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/shard-iclb3/igt@i915_pm...@dc6-dpms.html * igt@kms_big_fb@x-tiled-32bpp-rotate-90: - shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271]) +32 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/shard-apl1/igt@kms_big...@x-tiled-32bpp-rotate-90.html * igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3886]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/shard-apl1/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html * igt@kms_chamelium@hdmi-crc-single: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/shard-apl1/igt@kms_chamel...@hdmi-crc-single.html * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions: - shard-glk: [PASS][21] -> [FAIL][22] ([i915#2346]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk6/igt@kms_cursor_legacy@fli
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: use drm_dp_phy_name() for logging
== Series Details ==
Series: drm/i915/dp: use drm_dp_phy_name() for logging
URL : https://patchwork.freedesktop.org/series/108436/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12123 -> Patchwork_108436v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/index.html
Participating hosts (42 -> 41)
--
Additional (2): bat-jsl-1 bat-jsl-3
Missing(3): fi-ctg-p8600 fi-bdw-samus fi-snb-2520m
Known issues
Here are the changes found in Patchwork_108436v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600: NOTRUN -> [FAIL][1] ([fdo#103375])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-5: [PASS][2] -> [INCOMPLETE][3] ([i915#4418])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][4] -> [DMESG-FAIL][5] ([i915#4528])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-rkl-11600: NOTRUN -> [SKIP][6] ([fdo#111827])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/fi-rkl-11600/igt@kms_chamel...@common-hpd-after-suspend.html
*
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [PASS][7] -> [FAIL][8] ([i915#6298])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
* igt@runner@aborted:
- bat-dg1-5: NOTRUN -> [FAIL][9] ([i915#4312] / [i915#5257])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/bat-dg1-5/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_gttfill@basic:
- {bat-rpls-2}: [DMESG-WARN][10] -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/bat-rpls-2/igt@gem_exec_gttf...@basic.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/bat-rpls-2/igt@gem_exec_gttf...@basic.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [INCOMPLETE][12] ([i915#5982]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108436v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
Build changes
-
* Linux: CI_DRM_12123 -> Patchwork_108436v1
CI-20190529: 20190529
CI_DRM_12123: 5dd153b15e2e3198fca3d84db9e155f454645f91 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6650: f7aff600ab16d6405f0704b1743d2b7909715752 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108436v1: 5dd153b15e2e3198fca3d84db9e155f454645f91 @
git://anongit.freedesktop.org/gfx-
Re: [Intel-gfx] [PATCH v6 17/57] dyndbg: validate class FOO by checking with module
On Mon, Sep 12, 2022 at 2:17 PM Jason Baron wrote: > > > > On 9/9/22 16:44, jim.cro...@gmail.com wrote: > > On Wed, Sep 7, 2022 at 12:19 PM Jason Baron wrote: > >> > >> > >> > >> On 9/4/22 17:40, Jim Cromie wrote: > >>> Add module-to-class validation: > >>> > >>> #> echo class DRM_UT_KMS +p > /proc/dynamic_debug/control > >>> > >>> If a query has "class FOO", then ddebug_find_valid_class(), called > >>> from ddebug_change(), requires that FOO is known to module X, > >>> otherwize the query is skipped entirely for X. This protects each > >>> module's class-space, other than the default:31. > >>> > >>> The authors' choice of FOO is highly selective, giving isolation > >>> and/or coordinated sharing of FOOs. For example, only DRM modules > >>> should know and respond to DRM_UT_KMS. > >>> > >>> So this, combined with module's opt-in declaration of known classes, > >>> effectively privatizes the .class_id space for each module (or > >>> coordinated set of modules). > >>> > >>> Notes: > >>> > >>> For all "class FOO" queries, ddebug_find_valid_class() is called, it > >>> returns the map matching the query, and sets valid_class via an > >>> *outvar). > >>> > >>> If no "class FOO" is supplied, valid_class = _CLASS_DFLT. This > >>> insures that legacy queries do not trample on new class'd callsites, > >>> as they get added. > >> > >> > >> Hi Jim, > >> > >> I'm wondering about the case where we have a callsite which is marked > >> as 'class foo', but the query string is done by say module and file, so: > >> > >> # echo "module bar file foo.c +p" > /proc/dynamic_debug_control > >> > >> With the proposed code, I think this ends up not enabling anything right? > > > > correct - the only way to enable :pr_debug_cls(CL_FOO, " ...") > > is > >echo class CL_FOO +p > control > > > > 1st, existing dyndbg query uses, whether ad-hoc or scripted, > > were not written in anticipation of new / classified subsystems. > > > > 2nd, new class users dont want to sit in coach. no damn legroom. > > > > 3rd, consider DRM, which already has drm.debug > > ie: /sys/module/drm/parameters/debug > > and prefers it, at least by inertia. > > protecting these new class'd callsites (3-5k of them) > > from casual (unintended) manipulations of the kernel-wide > > dyndbg state seems prudent, and a usability win. > > > > Not everyone will use module bar, requiring "class foo" > > guarantees that changes are intentional. > > > > I sort of get that your trying to protect these from unintended toggling, > but I would say it's that's not really new with these statements, Whats new here is the customer - a whole new subsystem. theyre accustomed to a single point of control, /sys/module/drm/parameters/debug, and dont particularly value the infinite variety of combos under the hood. Theyre here for (Im selling them on) the JUMP_LABEL. Isolation from unintended manipulations under the hood (which is afterall a global kernel state) seems like a good guarantee. IOW class isolation from non-class, and from other INDEPENDENT classes. Only LEVEL types have any interdependence, and only with the other level classnames in the declared group. Ultimately, whats the client want ? I know my banker handles other folks money too, but I can reasonably expect isolation from their businesses. > prr_debug() come and go before and I'm not aware of this is an issue. > And in any case, a query can be modified. but youre requiring they be modified, so as not to scribble all over DRM_*, which wasnt there when they fiddled. > I think what bugs me is now query stuff works differently. Previously, > all the query strings - 'module', 'file', 'line', 'format', were > used as additional selectors, but now we have this new one 'class' > that works differently as it's requited for pr_debug_cls() statements. > theres a "when-in-rome" argument here, if DRM is Rome. > > > > > >> Because valid class is set to _DPRINTK_CLASS_DFLT and then: > >> 'dp->class_id != valid_class' is true? > >> > >> This seems confusing to me as a user as this doesn't work like the > >> other queriesso maybe we should only do the > >> 'dp->class_id != valid_class' check *if* query->class_string is set, > >> see below. > >> > > > > Could you clarify whether you think this is a logic error > > or a frame-of-reference difference as elaborated above ? > > 'frame-of-reference' I'm questioning the how 'class' works as mentioned > above not the implementation. > > Thanks, > > -Jason > > > > > ISTM theres a place for a well-worded paragraph in doc > > about the class distinction, perhaps a whole for-authors section. > > > > > > > >> > >> > >>> > >>> Also add a new column to control-file output, displaying non-default > >>> class-name (when found) or the "unknown _id:", if it has not been > >>> (correctly) declared with one of the declarator macros. > >>> > >>> Signed-off-by: Jim Cromie > >>> --- > >>> lib/dynamic_debug.c | 76 - > >>> 1 file changed, 6
Re: [Intel-gfx] [PATCH v1 1/1] drm/i915: Skip applying copy engine fuses
On Mon, Sep 12, 2022 at 10:12:57PM +0200, Andi Shyti wrote:
Hi Lucas,
On Mon, Sep 12, 2022 at 11:12:47AM -0700, Lucas De Marchi wrote:
On Mon, Sep 12, 2022 at 06:59:53PM +0200, Andi Shyti wrote:
> Hi Lucas,
>
> On Mon, Sep 12, 2022 at 09:19:38AM -0700, Lucas De Marchi wrote:
> > Support for reading the fuses to check what are the Link Copy engines
> > was added in commit ad5f74f34201 ("drm/i915/pvc: read fuses for link
> > copy engines"). However they were added unconditionally because the
> > FUSE3 register is present since graphics version 10.
> >
> > However the bitfield with meml3 fuses only exists since graphics version
> > 12. Moreover, Link Copy engines are currently only available in PVC.
> > Tying additional copy engines to the meml3 fuses is not correct for
> > other platforms.
> >
> > Make sure there is a check for `12.60 <= ver < 12.70`. Later platforms
> > may extend this function later if it's needed to fuse off copy engines.
> >
> > Currently it's harmless as the Link Copy engines are still not exported:
> > info->engine_mask only has BCS0 set and the register is only read for
> > platforms that do have it.
> >
> > Signed-off-by: Lucas De Marchi
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index 814f83b5fe59..1f7188129cd1 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -764,6 +764,10 @@ static void engine_mask_apply_copy_fuses(struct
intel_gt *gt)
> > unsigned long meml3_mask;
> > unsigned long quad;
> >
> > + if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
> > + GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
> > + return;
> > +
>
> Isn't it easier if you wrote
>
>if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 60) ||
>GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
>return;
>
> ?
>
> You save a parenthesis and a negation '!'.
but that makes it wrong. I'd really want the range
12.60 <= version < 12.70, so it applies to PVC but is then disabled
again for MTL.
But it's negated... so that if it's not in the range, it's
outside of the range... right?
NOT(12.60 <= ver < 12.70) <--- you wrote
is the same as:
ver < 12.60 or ver >= 12.70 <--- I suggested
and it would mean (just to see if I'm not getting confused by
something and the negations do always confuse me):
12.60 12.70
return | | return
ver: [--[---
But it's the same, taht's why I r-b it anyway.
yeah, when I read your reply I missed the fact you changed the
comparisons <=, >
thanks
Lucas De Marchi
Re: [Intel-gfx] [PATCH v7 2/9] drm: POC drm on dyndbg - use in core, 2 helpers, 3 drivers.
On Mon, Sep 12, 2022 at 4:29 AM Jani Nikula wrote:
>
> On Sun, 11 Sep 2022, Jim Cromie wrote:
> > Use DECLARE_DYNDBG_CLASSMAP across DRM:
> >
> > - in .c files, since macro defines/initializes a record
> >
> > - in drivers, $mod_{drv,drm,param}.c
> >ie where param setup is done, since a classmap is param related
> >
> > - in drm/drm_print.c
> >since existing __drm_debug param is defined there,
> >and we ifdef it, and provide an elaborated alternative.
> >
> > - in drm_*_helper modules:
> >dp/drm_dp - 1st item in makefile target
> >drivers/gpu/drm/drm_crtc_helper.c - random pick iirc.
> >
> > Since these modules all use identical CLASSMAP declarations (ie: names
> > and .class_id's) they will all respond together to "class DRM_UT_*"
> > query-commands:
>
> The commit message could start off by saying each module needs to define
> DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, ...). That is, IIUC.
>
Yes, I see your point.
All the explanations missing here are in preceding commits,
now in GregKHs driver-core/driver-core-next tree,
so I didnt resend them.
> Where's DECLARE_DYNDBG_CLASSMAP defined? linux-next? What's it do? What
> if multiple modules with that are actually builtin?
The commit that adds the macro is at
https://lore.kernel.org/lkml/20220904214134.408619-15-jim.cro...@gmail.com/
there are many combos of builtin, Ive done at least several:
with caveat that >98% of testing is on virtme (thanks for that tool)
- test_dynamic_debug as module, and builtin.
it has multiple macro uses, showing 1 kind of sharing
- drm as builtin, drivers as modules
that surely pulled in other drm-helpers as builtins
- all loadable modules mostly.
>
> The duplication and requirement that they're identical seems like an
> error prone combo.
I freely acknowledge(d) this is sub-optimal.
There might be a best place for a single declaration that is in-scope
across multiple modules, but I dont know the drm core/driver lifetime
well enough to just drop this into that place.
I may have complicated things by starting with a static struct holding
the classmap, that choice was driven by:
- static declaration into a section solved a problem where the class
definitions
were "registered" (term used in patchset, -v2-3?) too late to be available for
modprobe i915 dyndbg='class DRM_UT_CORE +p'
but worked afterwards
(also true for builtins and boot-time $mod.dyndbg='class notworking +p')
Another subtlety - the "sharing" is due more to: drm_dbg(DRM_UT_*, "")
Im not sure precisely how this might matter.
I also had an "incompleteness" argument circling in my head - something like;
you cant simultaneously allow a drm-wanna-be module to declare "DRM_UT_CORE"
but disallow "DRM_UT_ILL_CONSIDERED". I kind-of stopped there.
Theres also an issue where multiple declarations in a module must
avoid range overlap.
I had no idea how to put that into a BUILD_BUG_ON.
Its done manually, with commentary, in test-dynamic-debug.
Maybe both issues can be improved somewhat by changing the macro
to expect real ENUM symbols, (and stringify _VA_ARGS_ to init the classnames),
not the quoted "DRM_UT_*"s it gets now. That would also obsolete the _base,
since its the value of DRM_UT_CORE (the 1st enum val).
But that still leaves the enum vals enumerated, with possibility of
omission or mixup,
which unlike a spelling error wouldnt get caught, and would be wrong.
I fiddled with the 1st part of that for a while, I lack the macro-fu,
and punted.
Im happy to try an alternative approach, particularly with elaborated
suggestions.
>
> Finally, the choice of placement in e.g. i915_params.c seems completely
> arbitrary, and makes you wonder "what here requires this, nothing?".
acknowledged - I put it there because the access to it is via a parameter,
namely one that already affects it from a distance:
/sys/module/drm/parameters/debug - ie drm.dbg
And its not even i915's parameter.
>
> BR,
> Jani.
>
thanks,
>
> >
> > Signed-off-by: Jim Cromie
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix display problems after resume
== Series Details ==
Series: drm/i915: Fix display problems after resume
URL : https://patchwork.freedesktop.org/series/108432/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12123 -> Patchwork_108432v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/index.html
Participating hosts (42 -> 39)
--
Missing(3): fi-ctg-p8600 fi-hsw-4770 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_108432v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][1] -> [DMESG-FAIL][2] ([i915#4528])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html
Possible fixes
* igt@gem_exec_gttfill@basic:
- {bat-rpls-2}: [DMESG-WARN][3] -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/bat-rpls-2/igt@gem_exec_gttf...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/bat-rpls-2/igt@gem_exec_gttf...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
Build changes
-
* Linux: CI_DRM_12123 -> Patchwork_108432v1
CI-20190529: 20190529
CI_DRM_12123: 5dd153b15e2e3198fca3d84db9e155f454645f91 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6650: f7aff600ab16d6405f0704b1743d2b7909715752 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108432v1: 5dd153b15e2e3198fca3d84db9e155f454645f91 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
a6309c422ba4 drm/i915: Fix display problems after resume
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108432v1/index.html
Re: [Intel-gfx] [PATCH v1 1/1] drm/i915: Skip applying copy engine fuses
Hi Lucas,
On Mon, Sep 12, 2022 at 11:12:47AM -0700, Lucas De Marchi wrote:
> On Mon, Sep 12, 2022 at 06:59:53PM +0200, Andi Shyti wrote:
> > Hi Lucas,
> >
> > On Mon, Sep 12, 2022 at 09:19:38AM -0700, Lucas De Marchi wrote:
> > > Support for reading the fuses to check what are the Link Copy engines
> > > was added in commit ad5f74f34201 ("drm/i915/pvc: read fuses for link
> > > copy engines"). However they were added unconditionally because the
> > > FUSE3 register is present since graphics version 10.
> > >
> > > However the bitfield with meml3 fuses only exists since graphics version
> > > 12. Moreover, Link Copy engines are currently only available in PVC.
> > > Tying additional copy engines to the meml3 fuses is not correct for
> > > other platforms.
> > >
> > > Make sure there is a check for `12.60 <= ver < 12.70`. Later platforms
> > > may extend this function later if it's needed to fuse off copy engines.
> > >
> > > Currently it's harmless as the Link Copy engines are still not exported:
> > > info->engine_mask only has BCS0 set and the register is only read for
> > > platforms that do have it.
> > >
> > > Signed-off-by: Lucas De Marchi
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > index 814f83b5fe59..1f7188129cd1 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > @@ -764,6 +764,10 @@ static void engine_mask_apply_copy_fuses(struct
> > > intel_gt *gt)
> > > unsigned long meml3_mask;
> > > unsigned long quad;
> > >
> > > + if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
> > > + GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
> > > + return;
> > > +
> >
> > Isn't it easier if you wrote
> >
> > if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 60) ||
> > GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> > return;
> >
> > ?
> >
> > You save a parenthesis and a negation '!'.
>
> but that makes it wrong. I'd really want the range
> 12.60 <= version < 12.70, so it applies to PVC but is then disabled
> again for MTL.
But it's negated... so that if it's not in the range, it's
outside of the range... right?
NOT(12.60 <= ver < 12.70) <--- you wrote
is the same as:
ver < 12.60 or ver >= 12.70 <--- I suggested
and it would mean (just to see if I'm not getting confused by
something and the negations do always confuse me):
12.60 12.70
return | | return
ver: [--[---
But it's the same, taht's why I r-b it anyway.
> Depending on how this evolves for future platforms, we
> may change it to a feature flag or just check by platform
> name. For now I think this is the most future-proof option.
yes, I got the point and I think it's fine.
Andi
> Lucas De Marchi
>
> >
> > Anyway, looks good:
> >
> > Reviewed-by: Andi Shyti
> >
> > Andi
> >
> > > meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
> > > meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
> > >
> > >
> > > --
> > > b4 0.10.0-dev-df873
[Intel-gfx] ✓ Fi.CI.BAT: success for DGFX mmap with rpm (rev4)
== Series Details ==
Series: DGFX mmap with rpm (rev4)
URL : https://patchwork.freedesktop.org/series/107400/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12123 -> Patchwork_107400v4
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/index.html
Participating hosts (42 -> 40)
--
Missing(2): fi-ctg-p8600 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_107400v4 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gem:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][1] ([i915#4528])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/fi-pnv-d510/igt@i915_selftest@l...@gem.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][2] -> [INCOMPLETE][3] ([i915#4785])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][4] -> [DMESG-FAIL][5] ([i915#4528])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-rkl-11600: NOTRUN -> [SKIP][6] ([fdo#111827])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/fi-rkl-11600/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#4312] /
[i915#5594] / [i915#6246])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/fi-hsw-4770/igt@run...@aborted.html
Possible fixes
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][8] ([i915#2582]) -> [PASS][9] +4 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/bat-rpls-2/igt@fb...@read.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/bat-rpls-2/igt@fb...@read.html
* igt@gem_exec_gttfill@basic:
- {bat-rpls-2}: [DMESG-WARN][10] -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/bat-rpls-2/igt@gem_exec_gttf...@basic.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/bat-rpls-2/igt@gem_exec_gttf...@basic.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][12] ([i915#4528]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [INCOMPLETE][14] ([i915#5982]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v4/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
[i915#5828]: https://gitlab.freedesktop.org/drm/intel/issues/5828
[i915#5886]: https://gitlab.freedesktop.org/drm/intel/issues/5886
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#6246]: https://gitlab.freedesktop.org/drm/intel/issues/6246
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6670]: https://gitlab.freedesktop.org/drm/intel/issues/6670
Build changes
-
* Linux: CI_DRM_12123 -> Patchwork_107400v4
CI-20190529: 20190529
CI_DRM_12123: 5dd153b15e2e3198fca3d84db9e155f454645f91 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6650: f7aff600ab16d6405f0704b1743d2b7909715752 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107400v4: 5dd153b15e2e3198fca3d84db9e155f454645f91 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
ca780df60316 drm/i915/dgfx: Release mmap on rpm suspend
9187cc9627d4 drm/i915:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DGFX mmap with rpm (rev4)
== Series Details == Series: DGFX mmap with rpm (rev4) URL : https://patchwork.freedesktop.org/series/107400/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [RESEND] drm/i915/dp: use drm_dp_phy_name() for logging
On 12.09.2022 15:23, Jani Nikula wrote:
Drop the local intel_dp_phy_name() function, and replace with
drm_dp_phy_name(). This lets us drop a number of local buffers.
v2: Rebase
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä # v1
Signed-off-by: Jani Nikula
Reviewed-by: Andrzej Hajda
Regards
Andrzej
---
.../drm/i915/display/intel_dp_link_training.c | 83 ---
1 file changed, 36 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index d213d8ad1ea5..3d3efcf02011 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -37,17 +37,6 @@ static void intel_dp_reset_lttpr_count(struct intel_dp
*intel_dp)
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0;
}
-static const char *intel_dp_phy_name(enum drm_dp_phy dp_phy,
-char *buf, size_t buf_size)
-{
- if (dp_phy == DP_PHY_DPRX)
- snprintf(buf, buf_size, "DPRX");
- else
- snprintf(buf, buf_size, "LTTPR %d", dp_phy - DP_PHY_LTTPR1 + 1);
-
- return buf;
-}
-
static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
enum drm_dp_phy dp_phy)
{
@@ -60,20 +49,19 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp
*intel_dp,
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
- char phy_name[10];
-
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) {
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
"[ENCODER:%d:%s][%s] failed to read the PHY caps\n",
- encoder->base.base.id, encoder->base.name,
phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return;
}
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
"[ENCODER:%d:%s][%s] PHY capabilities: %*ph\n",
- encoder->base.base.id, encoder->base.name, phy_name,
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy),
(int)sizeof(intel_dp->lttpr_phy_caps[0]),
phy_caps);
}
@@ -423,14 +411,13 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- char phy_name[10];
int lane;
if (intel_dp_is_uhbr(crtc_state)) {
drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] 128b/132b, lanes: %d,
"
"TX FFE request: " TRAIN_REQ_FMT "\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name,
sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
crtc_state->lane_count,
TRAIN_REQ_TX_FFE_ARGS(link_status));
} else {
@@ -438,7 +425,7 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
"vswing request: " TRAIN_REQ_FMT ", "
"pre-emphasis request: " TRAIN_REQ_FMT "\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name,
sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
crtc_state->lane_count,
TRAIN_REQ_VSWING_ARGS(link_status),
TRAIN_REQ_PREEMPH_ARGS(link_status));
@@ -503,13 +490,12 @@ intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp,
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
- char phy_name[10];
if (train_pat != DP_TRAINING_PATTERN_DISABLE)
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Using DP training pattern
TPS%c\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name,
sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
dp_training_pattern_name(train_pat));
intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
@@ -546,13 +532,12 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_privat
Re: [Intel-gfx] [PATCH v2 7/9] drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state dp_dfp members
On Thu, Sep 01, 2022 at 11:30:59AM +0530, Ankit Nautiyal wrote:
> The decision to use DFP output format conversion capabilities should be
> during compute_config phase.
>
> This patch uses the members of intel_dp->dfp to only store the
> format conversion capabilities of the DP device and uses the crtc_state
> dp_dfp members that are computed earlier, to program the
> protocol-converter for colorspace/format conversion.
>
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 46 +
> 1 file changed, 17 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index f3c2aeda0c1d..409bd9cdf450 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -805,6 +805,7 @@ intel_dp_output_format(struct intel_connector *connector,
> bool ycbcr_420_output)
> {
> struct intel_dp *intel_dp = intel_attached_dp(connector);
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
> return INTEL_OUTPUT_FORMAT_RGB;
> @@ -813,6 +814,10 @@ intel_dp_output_format(struct intel_connector *connector,
> intel_dp->dfp.ycbcr_444_to_420)
> return INTEL_OUTPUT_FORMAT_RGB;
>
> + /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
> + if (DISPLAY_VER(i915) >= 11 && intel_dp->dfp.ycbcr420_passthrough)
> + return INTEL_OUTPUT_FORMAT_YCBCR420;
> +
> if (intel_dp->dfp.ycbcr_444_to_420)
> return INTEL_OUTPUT_FORMAT_YCBCR444;
> else
> @@ -2698,8 +2703,8 @@ void intel_dp_configure_protocol_converter(struct
> intel_dp *intel_dp,
> drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI
> mode\n",
> str_enable_disable(intel_dp->has_hdmi_sink));
>
> - tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
> - intel_dp->dfp.ycbcr_444_to_420 ?
> DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
> + tmp = crtc_state->dp_dfp_config.ycbcr_444_to_420 ?
> + DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
>
> if (drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
> @@ -2707,7 +2712,7 @@ void intel_dp_configure_protocol_converter(struct
> intel_dp *intel_dp,
> "Failed to %s protocol converter YCbCr 4:2:0
> conversion mode\n",
> str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
>
> - tmp = intel_dp->dfp.rgb_to_ycbcr ?
> + tmp = crtc_state->dp_dfp_config.rgb_to_ycbcr ?
> DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
>
> if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
> @@ -4563,7 +4568,7 @@ intel_dp_update_420(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> struct intel_connector *connector = intel_dp->attached_connector;
> - bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
> + bool is_branch;
>
> /* No YCbCr output support on gmch platforms */
> if (HAS_GMCH(i915))
> @@ -4577,38 +4582,21 @@ intel_dp_update_420(struct intel_dp *intel_dp)
> return;
>
> is_branch = drm_dp_is_branch(intel_dp->dpcd);
> - ycbcr_420_passthrough =
> + intel_dp->dfp.ycbcr420_passthrough =
> drm_dp_downstream_420_passthrough(intel_dp->dpcd,
> intel_dp->downstream_ports);
> /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
> - ycbcr_444_to_420 =
> + intel_dp->dfp.ycbcr_444_to_420 =
> dp_to_dig_port(intel_dp)->lspcon.active ||
> drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
>
> intel_dp->downstream_ports);
> - rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
> -
> intel_dp->downstream_ports,
> -
> DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
> -
> - if (DISPLAY_VER(i915) >= 11) {
> - /* Let PCON convert from RGB->YCbCr if possible */
> - if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
> - intel_dp->dfp.rgb_to_ycbcr = true;
> - intel_dp->dfp.ycbcr_444_to_420 = true;
> - connector->base.ycbcr_420_allowed = true;
> - } else {
> - /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
> - intel_dp->dfp.ycbcr_444_to_420 =
> - ycbcr_444_to_420 && !ycbcr_420_passthrough;
> + intel_dp->dfp.rgb_to_ycbcr =
> + drm_dp_downstream_rgb_to_ycbcr_conversi
Re: [Intel-gfx] [PATCH v2 4/9] drm/i915/display: Add new members to configure PCON color conversion
On Thu, Sep 01, 2022 at 11:30:56AM +0530, Ankit Nautiyal wrote:
> The decision to use DFP output format conversion capabilities should be
> during compute_config phase.
>
> This patch adds new members to crtc_state to help configure the DFP
> output related conversions. Also adds a member to intel_dp to store
> ycbcr420 pass through capability.
>
> This will help to store only the format conversion capabilities of the
> DP device in intel_dp->dfp, and use crtc_state to compute and store the
> configuration for color/format conversion for a given mode.
>
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 0da9b208d56e..065ed19a5dd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1311,6 +1311,12 @@ struct intel_crtc_state {
>
> /* for loading single buffered registers during vblank */
> struct drm_vblank_work vblank_work;
> +
> + /* DP DFP color configuration */
> + struct {
> + bool rgb_to_ycbcr;
> + bool ycbcr_444_to_420;
> + } dp_dfp_config;
Hmm. I'm thinking just something like
enum intel_output_format sink_format;
might be easier to deal with.
> };
>
> enum intel_pipe_crc_source {
> @@ -1704,6 +1710,7 @@ struct intel_dp {
> int pcon_max_frl_bw;
> u8 max_bpc;
> bool ycbcr_444_to_420;
> + bool ycbcr420_passthrough;
> bool rgb_to_ycbcr;
> } dfp;
>
> --
> 2.25.1
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v1 1/1] drm/i915: Skip applying copy engine fuses
On 12.09.2022 18:19, Lucas De Marchi wrote:
Support for reading the fuses to check what are the Link Copy engines
was added in commit ad5f74f34201 ("drm/i915/pvc: read fuses for link
copy engines"). However they were added unconditionally because the
FUSE3 register is present since graphics version 10.
However the bitfield with meml3 fuses only exists since graphics version
12. Moreover, Link Copy engines are currently only available in PVC.
Tying additional copy engines to the meml3 fuses is not correct for
other platforms.
Make sure there is a check for `12.60 <= ver < 12.70`. Later platforms
may extend this function later if it's needed to fuse off copy engines.
Currently it's harmless as the Link Copy engines are still not exported:
info->engine_mask only has BCS0 set and the register is only read for
platforms that do have it.
Signed-off-by: Lucas De Marchi
Reviewed-by: Andrzej Hajda
Regards
Andrzej
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 814f83b5fe59..1f7188129cd1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -764,6 +764,10 @@ static void engine_mask_apply_copy_fuses(struct intel_gt
*gt)
unsigned long meml3_mask;
unsigned long quad;
+ if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
+ GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
+ return;
+
meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/ipc: ipc and sub-struct refactoring, take 2
== Series Details ==
Series: drm/i915/ipc: ipc and sub-struct refactoring, take 2
URL : https://patchwork.freedesktop.org/series/108428/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12123 -> Patchwork_108428v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_108428v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108428v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108428v1/index.html
Participating hosts (42 -> 41)
--
Additional (1): bat-jsl-1
Missing(2): fi-ctg-p8600 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_108428v1:
### IGT changes ###
Possible regressions
* igt@i915_pm_rps@basic-api:
- fi-adl-ddr5:[PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/fi-adl-ddr5/igt@i915_pm_...@basic-api.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108428v1/fi-adl-ddr5/igt@i915_pm_...@basic-api.html
Known issues
Here are the changes found in Patchwork_108428v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-rkl-11600: NOTRUN -> [SKIP][3] ([fdo#111827])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108428v1/fi-rkl-11600/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-pnv-d510:NOTRUN -> [SKIP][4] ([fdo#109271])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108428v1/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html
Possible fixes
* igt@gem_exec_gttfill@basic:
- {bat-rpls-2}: [DMESG-WARN][5] -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/bat-rpls-2/igt@gem_exec_gttf...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108428v1/bat-rpls-2/igt@gem_exec_gttf...@basic.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][7] ([i915#4528]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108428v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [INCOMPLETE][9] ([i915#5982]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108428v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
Build changes
-
* Linux: CI_DRM_12123 -> Patchwork_108428v1
CI-20190529: 20190529
CI_DRM_12123: 5dd153b15e2e3198fca3d84db9e155f454645f91 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6650: f7aff600ab16d6405f0704b1743d2b7909715752 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108428v1: 5dd153b15e2e3198fca3d84db9e155f454645f91 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4976f897758f drm/i915/ipc: use intel_uncore_rmw() to enable/disable
7593b78e3d53 drm/i915/display: move IPC under display wm sub-struct
d5d89a2be0f9 drm/i915/ipc: register debugfs only if IPC available
dfdced37801b drm/i915/ipc: move IPC debugfs to skl_watermark.c
d75ccc652171 drm/i915/ipc: refactor and rename IPC functions
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patc
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/ipc: ipc and sub-struct refactoring, take 2
== Series Details == Series: drm/i915/ipc: ipc and sub-struct refactoring, take 2 URL : https://patchwork.freedesktop.org/series/108428/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Some house cleaning
== Series Details ==
Series: drm/i915: Some house cleaning
URL : https://patchwork.freedesktop.org/series/108426/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12123 -> Patchwork_108426v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/index.html
Participating hosts (42 -> 39)
--
Missing(3): fi-ctg-p8600 fi-rkl-11600 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_108426v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [PASS][1] -> [INCOMPLETE][2] ([i915#3303] /
[i915#4785])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@runner@aborted:
- fi-hsw-g3258: NOTRUN -> [FAIL][5] ([fdo#109271] / [i915#4312] /
[i915#6246])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/fi-hsw-g3258/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_gttfill@basic:
- {bat-rpls-2}: [DMESG-WARN][6] -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/bat-rpls-2/igt@gem_exec_gttf...@basic.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/bat-rpls-2/igt@gem_exec_gttf...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5828]: https://gitlab.freedesktop.org/drm/intel/issues/5828
[i915#6246]: https://gitlab.freedesktop.org/drm/intel/issues/6246
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6670]: https://gitlab.freedesktop.org/drm/intel/issues/6670
Build changes
-
* Linux: CI_DRM_12123 -> Patchwork_108426v1
CI-20190529: 20190529
CI_DRM_12123: 5dd153b15e2e3198fca3d84db9e155f454645f91 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6650: f7aff600ab16d6405f0704b1743d2b7909715752 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108426v1: 5dd153b15e2e3198fca3d84db9e155f454645f91 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
d6f67a484e7a drm/i915: s/intel_connector/connector/ in init code
16cb14b5 drm/i915: Finish s/intel_encoder/encoder/ rename
9558b8e1e3a0 drm/i915: Don't init eDP if we can't find a fixed mode
9c722f39880b drm/i915: Clean up connector->*_allowed setup
88f07fd6ec57 drm/i915: Extract intel_attach_scaling_mode_property()
f387bee2c7e3 drm/i915: Move eDP scaling_mode prop setup to the proper place
70470ea4c46b drm/i915: Extract intel_lvds_add_properties()
dc026855af76 drm/i915: Extract intel_dp_mst_add_properties()
d16db10af4d1 drm/i915: Extract intel_tv_add_properties()
4f08aa24180b drm/i915: Extract intel_edp_backlight_setup()
95df3fdc7b5e drm/i915: Pass intel_encoder to to_lvds_encoder()
72980db31b2c drm/i915: Use BIT() when dealing with output types
4a382d2e7ed5 drm/i915: Drop pointless 'budget' variable
1380e82d92b8 drm/i915: Clean up transcoder_to_stream_enc_status()
4943cf293b98 drm/i915: Drop pointless middle man variable
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108426v1/index.html
Re: [Intel-gfx] [PATCH v1 1/1] drm/i915: Skip applying copy engine fuses
On Mon, Sep 12, 2022 at 06:59:53PM +0200, Andi Shyti wrote:
Hi Lucas,
On Mon, Sep 12, 2022 at 09:19:38AM -0700, Lucas De Marchi wrote:
Support for reading the fuses to check what are the Link Copy engines
was added in commit ad5f74f34201 ("drm/i915/pvc: read fuses for link
copy engines"). However they were added unconditionally because the
FUSE3 register is present since graphics version 10.
However the bitfield with meml3 fuses only exists since graphics version
12. Moreover, Link Copy engines are currently only available in PVC.
Tying additional copy engines to the meml3 fuses is not correct for
other platforms.
Make sure there is a check for `12.60 <= ver < 12.70`. Later platforms
may extend this function later if it's needed to fuse off copy engines.
Currently it's harmless as the Link Copy engines are still not exported:
info->engine_mask only has BCS0 set and the register is only read for
platforms that do have it.
Signed-off-by: Lucas De Marchi
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 814f83b5fe59..1f7188129cd1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -764,6 +764,10 @@ static void engine_mask_apply_copy_fuses(struct intel_gt
*gt)
unsigned long meml3_mask;
unsigned long quad;
+ if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
+ GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
+ return;
+
Isn't it easier if you wrote
if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 60) ||
GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
return;
?
You save a parenthesis and a negation '!'.
but that makes it wrong. I'd really want the range
12.60 <= version < 12.70, so it applies to PVC but is then disabled
again for MTL. Depending on how this evolves for future platforms, we
may change it to a feature flag or just check by platform
name. For now I think this is the most future-proof option.
Lucas De Marchi
Anyway, looks good:
Reviewed-by: Andi Shyti
Andi
meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
--
b4 0.10.0-dev-df873
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Some house cleaning
== Series Details == Series: drm/i915: Some house cleaning URL : https://patchwork.freedesktop.org/series/108426/ State : warning == Summary == Error: dim checkpatch failed bb92496cbf75 drm/i915: Drop pointless middle man variable 24106901ef3f drm/i915: Clean up transcoder_to_stream_enc_status() f812b8d2b903 drm/i915: Drop pointless 'budget' variable 585c200640cf drm/i915: Use BIT() when dealing with output types 56b56ed7479a drm/i915: Pass intel_encoder to to_lvds_encoder() 9d3269780500 drm/i915: Extract intel_edp_backlight_setup() 50ef7f176f11 drm/i915: Extract intel_tv_add_properties() a28c6ad5cd02 drm/i915: Extract intel_dp_mst_add_properties() 1f08af6be780 drm/i915: Extract intel_lvds_add_properties() d4b0e18948d1 drm/i915: Move eDP scaling_mode prop setup to the proper place 534fed13623a drm/i915: Extract intel_attach_scaling_mode_property() 7103e1ac93ff drm/i915: Clean up connector->*_allowed setup ee13198e6f5a drm/i915: Don't init eDP if we can't find a fixed mode 46944f8a5aa8 drm/i915: Finish s/intel_encoder/encoder/ rename -:347: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "encoder->audio_connector" #347: FILE: drivers/gpu/drm/i915/display/intel_audio.c:1234: + *enabled = encoder->audio_connector != NULL; total: 0 errors, 0 warnings, 1 checks, 1523 lines checked d0565df6f72d drm/i915: s/intel_connector/connector/ in init code -:62: CHECK:CAMELCASE: Avoid CamelCase: #62: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:2035: + connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; total: 0 errors, 0 warnings, 1 checks, 1083 lines checked
Re: [Intel-gfx] [PATCH 13/15] drm/i915: Don't init eDP if we can't find a fixed mode
On Mon, Sep 12, 2022 at 03:02:36PM +0300, Jani Nikula wrote:
> On Mon, 12 Sep 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > In the unlikely case of not finding a fixed mode don't register
> > the eDP connector. I think there are some places where we'd oops
> > if we didn't have a fixed mode for eDP so presumable this doesn't
> > typically happen. But better safe than sorry.
>
> I think this is fine as the first step. ISTR there are provisions in the
> DP spec for adding some default mode if all else fails, maybe we should
> look into adding something like that?
I have no idea if eDP panels would support even the 640x480
fallback mode. My hunch is no, but might be interesting to
test if someone is willing to risk their eDP panel...
I have a feeling we should also just remove the current VBT
fixed mode fallback. I think the Windows driver has no such
thing, though should probably double check that.
>
> Guaranteeing we always have a fixed mode for eDP opens up possibilities
> for some further cleanup if we want. We have some "is edp and fixed
> mode" style conditions.
Yeah. Though I'm not sure if we'd want to go with
if (edp) or if (fixed_mode) in those cases. I have
occasionally pondered about exposing a user configurable
fixed_mode for external displays as well. Would let users
run their external display with a specific mode and
use the pfit to scale things instead of relying on the
display having a decent scaler.
>
> Up to and including this patch in the series,
I think I'll skip it for now.
>
> Reviewed-by: Jani Nikula
Thanks.
>
>
> >
> > Also pimp the debugs with the encoder id+name. I think dumping
> > the encoder rather than the connector provides more information
> > here (eg. to match again the port information in the VBT).
> >
> > We can also drop the extra check from intel_edp_add_properties().
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 13 +
> > 1 file changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 7b4ffb74c94c..8fe48634eb9d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5197,9 +5197,6 @@ intel_edp_add_properties(struct intel_dp *intel_dp)
> >
> > intel_attach_scaling_mode_property(&connector->base);
> >
> > - if (!fixed_mode)
> > - return;
> > -
> > drm_connector_set_panel_orientation_with_quirk(&connector->base,
> >
> > i915->display.vbt.orientation,
> >fixed_mode->hdisplay,
> > @@ -5272,7 +5269,8 @@ static bool intel_edp_init_connector(struct intel_dp
> > *intel_dp,
> > if (!has_dpcd) {
> > /* if this fails, presume the device is a ghost */
> > drm_info(&dev_priv->drm,
> > -"failed to retrieve link info, disabling eDP\n");
> > +"[ENCODER:%d:%s] failed to retrieve link info,
> > disabling eDP\n",
> > +encoder->base.base.id, encoder->base.name);
> > goto out_vdd_off;
> > }
> >
> > @@ -5318,6 +5316,13 @@ static bool intel_edp_init_connector(struct intel_dp
> > *intel_dp,
> >
> > mutex_unlock(&dev->mode_config.mutex);
> >
> > + if (!intel_panel_preferred_fixed_mode(intel_connector)) {
> > + drm_info(&dev_priv->drm,
> > +"[ENCODER:%d:%s] failed to find fixed mode for the
> > panel, disabling eDP\n",
> > +encoder->base.base.id, encoder->base.name);
> > + goto out_vdd_off;
> > + }
> > +
> > intel_panel_init(intel_connector);
> >
> > intel_edp_backlight_setup(intel_dp, intel_connector);
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v3 19/37] drm/i915: stop using kernel-doc markups for something else
On Mon, Sep 12, 2022 at 06:47:56PM +0200, Mauro Carvalho Chehab wrote:
> Hi Matt,
>
> Em Mon, 12 Sep 2022 08:09:57 -0700
> Matt Roper escreveu:
>
> > > --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> >
> > Several of the comments in this file do appear to be kerneldoc (in fact
> > kerneldoc that was specifically requested during code review at
> > https://patchwork.freedesktop.org/patch/448456/#comment_804252) and this
> > file is included from Documentation/gpu/i915.rst, so I think some of
> > these changes might be moving in the wrong direction. Should we instead
> > focus on fixing up the comments that aren't quite formatted properly?
>
> Those *appear* to be kernel-doc markups, but they aren't, because
> the structs themselves are not properly marked. See, for instance
> struct intel_context.
>
> scripts/kerneldoc will *only* consider what's there as a proper
> comment if you add:
>
> /**
>* struct intel_context - describes an i915 context
>*
>*/
> struct intel_context {
> union {
> /** @ref: a kernel object reference */
> struct kref ref; /* no kref_get_unless_zero()! */
> /** @rcu: a rcu header */
> struct rcu_head rcu;
> };
> ...
> }
>
> Describing all fields inside the struct. Just placing
> /** something */
> on some random places in the middle doesn't make it a kernel-doc.
Right, what we have today is incomplete/incorrect. But I think we
should be fixing that by adding the missing documentation on the
structure, rather than giving up and removing the kerneldoc. The end
goal should be to have proper generated documentation, not just silence
the warnings while leaving the actual output incomplete.
Matt
>
> If you actually run kernel-doc in Werror mode:
>
> ./scripts/kernel-doc -Werror -sphinx-version 2.4.4
> drivers/gpu/drm/i915/gt/intel_context_types.h | echo "ERROR!"
> ERROR!
> drivers/gpu/drm/i915/gt/intel_context_types.h:1: warning: no structured
> comments found
> 1 warnings as Errors
>
> you'll see that this is currently broken.
>
> Thanks,
> Mauro
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL
Hi Badal, On Mon, Sep 12, 2022 at 05:42:57PM +0530, Nilawar, Badal wrote: > I added Cc: in individual patches. So I thought it will pick automatically. > But anyway I have to fix some of the comments. So I will fix those and > resend the series. I will Cc relevant people. yes... it depends on your git-send-email command. I think no one has received the e-mail other than the mailing list. If you have the '--suppress-cc=all' flag then you need to explicitly add the --to/--cc recipients (this is how I do it in order avoid sending patches to unwanted people). If you don't have the '--suppress-cc=all' then git-send-email figures out by itself whom to send the patch by checking the commit tags. In both the cases, though, before sending the patches individually, git-send-email displays the people that have been added to the 'cc' list. Please make sure not to forget the dri-devel mailing list () and to check if the patches are actually sent to everyone. Thanks, Andi > Regards, > Badal > > On 12-09-2022 17:37, Jani Nikula wrote: > > On Mon, 12 Sep 2022, Andi Shyti wrote: > > > Hi Badal, > > > > > > you haven't Cc'ed anyone here... Please do CC the people > > > interested in the patches and dri-devel mailing list. > > > > > > If you don't mind, could you please resend the series either as a > > > V2, if you are going to change something, or as a RESEND, if you > > > will not change anything? > > > > Anyway some of the patches have been merged already so a rebase is in > > order. > > > > BR, > > Jani. > > > > > > > > Thanks, > > > Andi > > > > > > On Fri, Sep 09, 2022 at 08:26:40AM +0530, Badal Nilawar wrote: > > > > This series includes the code changes to get CAGF, RC State and > > > > C6 Residency of MTL. The series depends on: > > > > > > > > https://patchwork.freedesktop.org/series/107908/ > > > > > > > > We have included 3 patches from from the above series as part of this > > > > series in order for this series to compile. These are the first 3 > > > > patches > > > > authored by Matt Roper. Please do not review these first 3 patches. Only > > > > patch 4 and 6 needs review. > > > > > > > > v2: Included "Use GEN12 RPSTAT register" patch > > > > > > > > Cc: Ashutosh Dixit > > > > > > > > Badal Nilawar (2): > > > >drm/i915/mtl: Modify CAGF functions for MTL > > > >drm/i915/mtl: Add C6 residency support for MTL SAMedia > > > > > > > > Don Hiatt (1): > > > >drm/i915: Use GEN12 RPSTAT register > > > > > > > > Matt Roper (3): > > > >drm/i915: Prepare more multi-GT initialization > > > >drm/i915: Rename and expose common GT early init routine > > > >drm/i915/xelpmp: Expose media as another GT > > > > > > > > drivers/gpu/drm/i915/Makefile | 1 + > > > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- > > > > drivers/gpu/drm/i915/gt/intel_gt.c| 70 +++ > > > > drivers/gpu/drm/i915/gt/intel_gt.h| 2 +- > > > > drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 58 ++- > > > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 31 > > > > drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++- > > > > drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + > > > > drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +- > > > > drivers/gpu/drm/i915/gt/intel_rps.c | 22 +- > > > > drivers/gpu/drm/i915/gt/intel_rps.h | 1 + > > > > drivers/gpu/drm/i915/gt/intel_sa_media.c | 39 +++ > > > > drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 > > > > drivers/gpu/drm/i915/gt/selftest_rc6.c| 9 ++- > > > > drivers/gpu/drm/i915/i915_drv.h | 2 + > > > > drivers/gpu/drm/i915/i915_pci.c | 15 > > > > drivers/gpu/drm/i915/i915_pmu.c | 11 ++- > > > > drivers/gpu/drm/i915/intel_device_info.h | 19 + > > > > drivers/gpu/drm/i915/intel_uncore.c | 16 - > > > > drivers/gpu/drm/i915/intel_uncore.h | 20 +- > > > > .../gpu/drm/i915/selftests/mock_gem_device.c | 1 + > > > > 21 files changed, 325 insertions(+), 26 deletions(-) > > > > create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c > > > > create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h > > > > > > > > -- > > > > 2.25.1 > >
Re: [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL
Hi Jani, On Mon, Sep 12, 2022 at 03:07:01PM +0300, Jani Nikula wrote: > On Mon, 12 Sep 2022, Andi Shyti wrote: > > Hi Badal, > > > > you haven't Cc'ed anyone here... Please do CC the people > > interested in the patches and dri-devel mailing list. > > > > If you don't mind, could you please resend the series either as a > > V2, if you are going to change something, or as a RESEND, if you > > will not change anything? > > Anyway some of the patches have been merged already so a rebase is in > order. thanks... I see that some of the patches have been reviewed previously, I missed that. Thank you, Andi
Re: [Intel-gfx] [PATCH v1 1/1] drm/i915: Skip applying copy engine fuses
Hi Lucas,
On Mon, Sep 12, 2022 at 09:19:38AM -0700, Lucas De Marchi wrote:
> Support for reading the fuses to check what are the Link Copy engines
> was added in commit ad5f74f34201 ("drm/i915/pvc: read fuses for link
> copy engines"). However they were added unconditionally because the
> FUSE3 register is present since graphics version 10.
>
> However the bitfield with meml3 fuses only exists since graphics version
> 12. Moreover, Link Copy engines are currently only available in PVC.
> Tying additional copy engines to the meml3 fuses is not correct for
> other platforms.
>
> Make sure there is a check for `12.60 <= ver < 12.70`. Later platforms
> may extend this function later if it's needed to fuse off copy engines.
>
> Currently it's harmless as the Link Copy engines are still not exported:
> info->engine_mask only has BCS0 set and the register is only read for
> platforms that do have it.
>
> Signed-off-by: Lucas De Marchi
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 814f83b5fe59..1f7188129cd1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -764,6 +764,10 @@ static void engine_mask_apply_copy_fuses(struct intel_gt
> *gt)
> unsigned long meml3_mask;
> unsigned long quad;
>
> + if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
> + GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
> + return;
> +
Isn't it easier if you wrote
if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 60) ||
GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
return;
?
You save a parenthesis and a negation '!'.
Anyway, looks good:
Reviewed-by: Andi Shyti
Andi
> meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
> meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
>
>
> --
> b4 0.10.0-dev-df873
[Intel-gfx] [PATCH 12/15] drm/i915/reg: move masked field helpers to i915_reg_defs.h
This is a more logical place for generic helpers.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 13 -
drivers/gpu/drm/i915/i915_reg_defs.h | 13 +
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52462cbfdc66..3727fc1d5d61 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -171,19 +171,6 @@
INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
DISPLAY_MMIO_BASE(dev_priv) +
(reg))
-#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
-#define _MASKED_FIELD(mask, value) ({ \
- if (__builtin_constant_p(mask))\
- BUILD_BUG_ON_MSG(((mask) & 0x), "Incorrect mask"); \
- if (__builtin_constant_p(value)) \
- BUILD_BUG_ON_MSG((value) & 0x, "Incorrect value"); \
- if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
- BUILD_BUG_ON_MSG((value) & ~(mask),\
-"Incorrect value for mask"); \
- __MASKED_FIELD(mask, value); })
-#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
-#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
-
#define GU_CNTL_MMIO(0x101010)
#define LMEM_INITREG_BIT(7)
diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
b/drivers/gpu/drm/i915/i915_reg_defs.h
index 8f486f77609f..7536f1b72778 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -98,6 +98,19 @@
*/
#define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val))
+#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
+#define _MASKED_FIELD(mask, value) ({ \
+ if (__builtin_constant_p(mask))\
+ BUILD_BUG_ON_MSG(((mask) & 0x), "Incorrect mask"); \
+ if (__builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & 0x, "Incorrect value"); \
+ if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & ~(mask),\
+"Incorrect value for mask"); \
+ __MASKED_FIELD(mask, value); })
+#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
+#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
+
typedef struct {
u32 reg;
} i915_reg_t;
--
2.34.1
[Intel-gfx] [PATCH 09/15] drm/i915/display: reduce includes in intel_hdmi.h
Only include what's needed. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_hdmi.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h index 93f65a917c36..774dda2376ed 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.h +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h @@ -6,20 +6,20 @@ #ifndef __INTEL_HDMI_H__ #define __INTEL_HDMI_H__ -#include #include +enum hdmi_infoframe_type; +enum port; struct drm_connector; +struct drm_connector_state; struct drm_encoder; struct drm_i915_private; struct intel_connector; +struct intel_crtc_state; struct intel_digital_port; struct intel_encoder; -struct intel_crtc_state; struct intel_hdmi; -struct drm_connector_state; union hdmi_infoframe; -enum port; void intel_hdmi_init_connector(struct intel_digital_port *dig_port, struct intel_connector *intel_connector); -- 2.34.1
[Intel-gfx] [PATCH 15/15] drm/i915: stop including i915_irq.h from i915_trace.h
Turns out most of the files that need i915_reg.h get it implicitly via
{display/intel_de.h, gt/intel_context.h} -> i915_trace.h -> i915_irq.h
-> i915_reg.h. Since i915_trace.h doesn't actually need i915_irq.h,
makes sense to drop it, but that requires adding quite a few new
includes all over the place.
Prefer actually including i915_reg.h where needed instead of adding
another implicit include, because eventually we'll want to split up
i915_reg.h and only include the specific registers at each place.
Also some places actually needed i915_irq.h too.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/g4x_dp.c| 1 +
drivers/gpu/drm/i915/display/g4x_hdmi.c | 1 +
drivers/gpu/drm/i915/display/i9xx_plane.c| 4 +++-
drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
drivers/gpu/drm/i915/display/intel_backlight.c | 1 +
drivers/gpu/drm/i915/display/intel_cdclk.c | 1 +
drivers/gpu/drm/i915/display/intel_color.c | 1 +
drivers/gpu/drm/i915/display/intel_combo_phy.c | 1 +
drivers/gpu/drm/i915/display/intel_crt.c | 2 ++
drivers/gpu/drm/i915/display/intel_cursor.c | 3 ++-
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 ++
drivers/gpu/drm/i915/display/intel_dp.c | 1 +
drivers/gpu/drm/i915/display/intel_dp_aux.c | 1 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
drivers/gpu/drm/i915/display/intel_dpio_phy.c| 1 +
drivers/gpu/drm/i915/display/intel_dpll.c| 1 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c| 1 +
drivers/gpu/drm/i915/display/intel_drrs.c| 1 +
drivers/gpu/drm/i915/display/intel_dsb.c | 1 +
drivers/gpu/drm/i915/display/intel_dvo.c | 1 +
drivers/gpu/drm/i915/display/intel_fdi.c | 1 +
drivers/gpu/drm/i915/display/intel_gmbus.c | 2 ++
drivers/gpu/drm/i915/display/intel_hdmi.c| 1 +
drivers/gpu/drm/i915/display/intel_lpe_audio.c | 2 ++
drivers/gpu/drm/i915/display/intel_lspcon.c | 1 +
drivers/gpu/drm/i915/display/intel_lvds.c| 1 +
drivers/gpu/drm/i915/display/intel_modeset_setup.c | 1 +
drivers/gpu/drm/i915/display/intel_panel.c | 1 +
drivers/gpu/drm/i915/display/intel_pch_display.c | 1 +
drivers/gpu/drm/i915/display/intel_pch_refclk.c | 1 +
drivers/gpu/drm/i915/display/intel_pipe_crc.c| 2 ++
drivers/gpu/drm/i915/display/intel_pps.c | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 1 +
drivers/gpu/drm/i915/display/intel_sdvo.c| 1 +
drivers/gpu/drm/i915/display/intel_snps_phy.c| 1 +
drivers/gpu/drm/i915/display/intel_sprite.c | 1 +
drivers/gpu/drm/i915/display/intel_tv.c | 2 ++
drivers/gpu/drm/i915/display/intel_vdsc.c| 1 +
drivers/gpu/drm/i915/display/intel_vga.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/skl_scaler.c| 2 ++
drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 ++
drivers/gpu/drm/i915/display/vlv_dsi.c | 1 +
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 1 +
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 1 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 ++
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 1 +
drivers/gpu/drm/i915/gt/intel_gtt.c | 1 +
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c| 1 +
drivers/gpu/drm/i915/gvt/cmd_parser.c| 1 +
drivers/gpu/drm/i915/gvt/mmio_context.c | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c| 1 +
drivers/gpu/drm/i915/i915_perf.c | 1 +
drivers/gpu/drm/i915/i915_trace.h| 1 -
drivers/gpu/drm/i915/intel_device_info.c | 3 ++-
drivers/gpu/drm/i915/intel_uncore.c | 1 +
63 files changed, 76 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
b/drivers/gpu/drm/i915/display/g4x_dp.c
index e3e3d27ffb53..3593938dcd87 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -8,6 +8,7 @@
#include
#include "g4x_dp.h"
+#include "i915_reg.h"
#include "intel_audio.h"
#include "intel_backlight.h"
#include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 5fbd2ae95869..ab5cc4a90591 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.
[Intel-gfx] [PATCH 08/15] drm/i915/display: reduce the includes in intel_dvo_dev.h
Only include what's needed.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dvo_dev.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dvo_dev.h
b/drivers/gpu/drm/i915/display/intel_dvo_dev.h
index d96c3cc46e50..f446a04a1052 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo_dev.h
+++ b/drivers/gpu/drm/i915/display/intel_dvo_dev.h
@@ -23,12 +23,12 @@
#ifndef __INTEL_DVO_DEV_H__
#define __INTEL_DVO_DEV_H__
-#include
-
-#include
-
#include "i915_reg_defs.h"
+enum drm_connector_status;
+struct drm_display_mode;
+struct i2c_adapter;
+
struct intel_dvo_device {
const char *name;
int type;
--
2.34.1
[Intel-gfx] [PATCH 14/15] drm/i915: split out intel_display_reg_defs.h
Split out the display register helper macros to a separate file. For now, include it from i915_reg.h, but note that there are already files that don't need i915_reg.h, such as intel_audio.c. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi_regs.h | 2 +- .../gpu/drm/i915/display/intel_audio_regs.h | 2 +- .../drm/i915/display/intel_backlight_regs.h | 2 +- .../drm/i915/display/intel_display_reg_defs.h | 53 +++ .../gpu/drm/i915/display/intel_hdcp_regs.h| 2 +- .../drm/i915/display/intel_snps_phy_regs.h| 2 +- .../gpu/drm/i915/display/intel_tc_phy_regs.h | 2 +- drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 2 +- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 42 +-- drivers/gpu/drm/i915/i915_reg_defs.h | 2 - 11 files changed, 62 insertions(+), 50 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_display_reg_defs.h diff --git a/drivers/gpu/drm/i915/display/icl_dsi_regs.h b/drivers/gpu/drm/i915/display/icl_dsi_regs.h index f78f28b8dd94..d4845ac65acc 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi_regs.h +++ b/drivers/gpu/drm/i915/display/icl_dsi_regs.h @@ -6,7 +6,7 @@ #ifndef __ICL_DSI_REGS_H__ #define __ICL_DSI_REGS_H__ -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" /* Gen11 DSI */ #define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \ diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h b/drivers/gpu/drm/i915/display/intel_audio_regs.h index d1e5844e3484..21919f9da5fc 100644 --- a/drivers/gpu/drm/i915/display/intel_audio_regs.h +++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h @@ -6,7 +6,7 @@ #ifndef __INTEL_AUDIO_REGS_H__ #define __INTEL_AUDIO_REGS_H__ -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) #define INTEL_AUDIO_DEVCL0x808629FB diff --git a/drivers/gpu/drm/i915/display/intel_backlight_regs.h b/drivers/gpu/drm/i915/display/intel_backlight_regs.h index 50c1210f6d5d..344eb8096bd2 100644 --- a/drivers/gpu/drm/i915/display/intel_backlight_regs.h +++ b/drivers/gpu/drm/i915/display/intel_backlight_regs.h @@ -6,7 +6,7 @@ #ifndef __INTEL_BACKLIGHT_REGS_H__ #define __INTEL_BACKLIGHT_REGS_H__ -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250) #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350) diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h new file mode 100644 index ..02605418ff08 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef __INTEL_DISPLAY_REG_DEFS_H__ +#define __INTEL_DISPLAY_REG_DEFS_H__ + +#include "i915_reg_defs.h" + +#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display.mmio_offset) + +#define VLV_DISPLAY_BASE 0x18 + +/* + * Named helper wrappers around _PICK_EVEN() and _PICK(). + */ +#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) +#define _PLANE(plane, a, b)_PICK_EVEN(plane, a, b) +#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) +#define _PORT(port, a, b) _PICK_EVEN(port, a, b) +#define _PLL(pll, a, b)_PICK_EVEN(pll, a, b) +#define _PHY(phy, a, b)_PICK_EVEN(phy, a, b) + +#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) +#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) +#define _MMIO_TRANS(tran, a, b)_MMIO(_TRANS(tran, a, b)) +#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) +#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) +#define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) + +#define _PHY3(phy, ...)_PICK(phy, __VA_ARGS__) + +#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) +#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) +#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) +#define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__)) + +/* + * Device info offset array based helpers for groups of registers with unevenly + * spaced base offsets. + */ +#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \ + INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \ + DISPLAY_MMIO_BASE(dev_priv) + (reg)) +#define _MMIO_TRANS2(tran, reg) _MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \ + INTEL_INFO(dev_priv)->display.tran
[Intel-gfx] [PATCH 13/15] drm/i915/reg: move pick even and pick to reg defs
This is a more logical place for generic helpers.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 15 ---
drivers/gpu/drm/i915/i915_reg_defs.h | 15 +++
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3727fc1d5d61..03ff6039b27f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -117,21 +117,6 @@
#define DISPLAY_MMIO_BASE(dev_priv)
(INTEL_INFO(dev_priv)->display.mmio_offset)
-/*
- * Given the first two numbers __a and __b of arbitrarily many evenly spaced
- * numbers, pick the 0-based __index'th value.
- *
- * Always prefer this over _PICK() if the numbers are evenly spaced.
- */
-#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
-
-/*
- * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
- *
- * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
- */
-#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
-
/*
* Named helper wrappers around _PICK_EVEN() and _PICK().
*/
diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
b/drivers/gpu/drm/i915/i915_reg_defs.h
index 7536f1b72778..344e5006650e 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -111,6 +111,21 @@
#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
+/*
+ * Given the first two numbers __a and __b of arbitrarily many evenly spaced
+ * numbers, pick the 0-based __index'th value.
+ *
+ * Always prefer this over _PICK() if the numbers are evenly spaced.
+ */
+#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
+
+/*
+ * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
+ *
+ * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
+ */
+#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
+
typedef struct {
u32 reg;
} i915_reg_t;
--
2.34.1
[Intel-gfx] [PATCH 06/15] drm/i915/dpio: move dpio_channel and dpio_phy enums to intel_dpio_phy.h
Reduce the size of intel_display.h by moving out the dpio_channel and
dpio_phy enums.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.h| 11 ---
.../gpu/drm/i915/display/intel_display_power_well.h | 2 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.h | 13 +++--
drivers/gpu/drm/i915/gvt/display.c | 2 ++
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/gvt/mmio.c | 1 +
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
drivers/gpu/drm/i915/vlv_sideband.c | 2 ++
8 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 85395c8e58f9..63ca58c5636b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -261,17 +261,6 @@ enum tc_port_mode {
TC_PORT_LEGACY,
};
-enum dpio_channel {
- DPIO_CH0,
- DPIO_CH1
-};
-
-enum dpio_phy {
- DPIO_PHY0,
- DPIO_PHY1,
- DPIO_PHY2,
-};
-
enum aux_ch {
AUX_CH_A,
AUX_CH_B,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h
b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index 31a898176ebb..cef36f27755f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -7,8 +7,8 @@
#include
-#include "intel_display.h"
#include "intel_display_power.h"
+#include "intel_dpio_phy.h"
struct drm_i915_private;
struct i915_power_well;
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
index 828ad58624d8..9c7725dacb47 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
@@ -8,8 +8,6 @@
#include
-enum dpio_channel;
-enum dpio_phy;
enum pipe;
enum port;
struct drm_i915_private;
@@ -17,6 +15,17 @@ struct intel_crtc_state;
struct intel_digital_port;
struct intel_encoder;
+enum dpio_channel {
+ DPIO_CH0,
+ DPIO_CH1,
+};
+
+enum dpio_phy {
+ DPIO_PHY0,
+ DPIO_PHY1,
+ DPIO_PHY2,
+};
+
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch);
void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/gvt/display.c
b/drivers/gpu/drm/i915/gvt/display.c
index c7722c818b4d..c033249e73f4 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -36,6 +36,8 @@
#include "i915_reg.h"
#include "gvt.h"
+#include "display/intel_dpio_phy.h"
+
static int get_edp_pipe(struct intel_vgpu *vgpu)
{
u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index daac2050d77d..08beaeadadb7 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -43,6 +43,7 @@
#include "intel_mchbar_regs.h"
#include "display/intel_display_types.h"
#include "display/intel_dmc_regs.h"
+#include "display/intel_dpio_phy.h"
#include "display/intel_fbc.h"
#include "display/vlv_dsi_pll_regs.h"
#include "gt/intel_gt_regs.h"
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index 9acc00505fde..5b5def6ddef7 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -37,6 +37,7 @@
#include "i915_reg.h"
#include "gvt.h"
+#include "display/intel_dpio_phy.h"
#include "gt/intel_gt_regs.h"
/**
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 8279dc580a3e..33a65d1a82b5 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -6,6 +6,7 @@
#include "display/intel_audio_regs.h"
#include "display/intel_backlight_regs.h"
#include "display/intel_dmc_regs.h"
+#include "display/intel_dpio_phy.h"
#include "display/vlv_dsi_pll_regs.h"
#include "gt/intel_gt_regs.h"
#include "gvt/gvt.h"
diff --git a/drivers/gpu/drm/i915/vlv_sideband.c
b/drivers/gpu/drm/i915/vlv_sideband.c
index c26001300ebd..6eea6e1a99c0 100644
--- a/drivers/gpu/drm/i915/vlv_sideband.c
+++ b/drivers/gpu/drm/i915/vlv_sideband.c
@@ -8,6 +8,8 @@
#include "i915_reg.h"
#include "vlv_sideband.h"
+#include "display/intel_dpio_phy.h"
+
/*
* IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
* VLV_VLV2_PUNIT_HAS_0.8.docx
--
2.34.1
[Intel-gfx] [PATCH 10/15] drm/i915/display: reduce includes in g4x_dp.h includes
Only include what's needed. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/g4x_dp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.h b/drivers/gpu/drm/i915/display/g4x_dp.h index e1f50263a725..a38b3e1e01d3 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.h +++ b/drivers/gpu/drm/i915/display/g4x_dp.h @@ -8,7 +8,7 @@ #include -#include "i915_reg.h" +#include "i915_reg_defs.h" enum pipe; enum port; -- 2.34.1
[Intel-gfx] [PATCH 03/15] drm/i915: reduce includes in intel_fifo_underrun.h
Only include what's needed. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_fifo_underrun.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.h b/drivers/gpu/drm/i915/display/intel_fifo_underrun.h index e04f22ac1f49..2e47d7d3c101 100644 --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.h +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.h @@ -8,9 +8,8 @@ #include -#include "intel_display.h" - struct drm_i915_private; +enum pipe; bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable); -- 2.34.1
[Intel-gfx] [PATCH 07/15] drm/i915: reduce includes in intel_display_power.h
Only include what's needed. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_power.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 7136ea3f233e..1e77e52c87fe 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -6,11 +6,12 @@ #ifndef __INTEL_DISPLAY_POWER_H__ #define __INTEL_DISPLAY_POWER_H__ -#include "intel_runtime_pm.h" +#include "intel_wakeref.h" enum aux_ch; enum dpio_channel; enum dpio_phy; +enum i915_drm_suspend_mode; enum port; struct drm_i915_private; struct i915_power_well; -- 2.34.1
[Intel-gfx] [PATCH 11/15] drm/i915/irq: make gen2_irq_init()/gen2_irq_reset() static
The gen2 irq functions aren't used outside of i915_irq.h. Make them
static, and remove the useless macro wrappers.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_irq.c | 10 +-
drivers/gpu/drm/i915/i915_irq.h | 9 -
2 files changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 86a42d9e8041..65038750b6f6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -248,7 +248,7 @@ void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t
imr,
intel_uncore_posting_read(uncore, iir);
}
-void gen2_irq_reset(struct intel_uncore *uncore)
+static void gen2_irq_reset(struct intel_uncore *uncore)
{
intel_uncore_write16(uncore, GEN2_IMR, 0x);
intel_uncore_posting_read16(uncore, GEN2_IMR);
@@ -309,8 +309,8 @@ void gen3_irq_init(struct intel_uncore *uncore,
intel_uncore_posting_read(uncore, imr);
}
-void gen2_irq_init(struct intel_uncore *uncore,
- u32 imr_val, u32 ier_val)
+static void gen2_irq_init(struct intel_uncore *uncore,
+ u32 imr_val, u32 ier_val)
{
gen2_assert_iir_is_zero(uncore);
@@ -3928,7 +3928,7 @@ static void i8xx_irq_reset(struct drm_i915_private
*dev_priv)
i9xx_pipestat_irq_reset(dev_priv);
- GEN2_IRQ_RESET(uncore);
+ gen2_irq_reset(uncore);
dev_priv->irq_mask = ~0u;
}
@@ -3954,7 +3954,7 @@ static void i8xx_irq_postinstall(struct drm_i915_private
*dev_priv)
I915_MASTER_ERROR_INTERRUPT |
I915_USER_INTERRUPT;
- GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
+ gen2_irq_init(uncore, dev_priv->irq_mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index 82639d9d7e82..9b004fc3444e 100644
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -90,12 +90,9 @@ void i965_disable_vblank(struct drm_crtc *crtc);
void ilk_disable_vblank(struct drm_crtc *crtc);
void bdw_disable_vblank(struct drm_crtc *crtc);
-void gen2_irq_reset(struct intel_uncore *uncore);
void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
i915_reg_t iir, i915_reg_t ier);
-void gen2_irq_init(struct intel_uncore *uncore,
- u32 imr_val, u32 ier_val);
void gen3_irq_init(struct intel_uncore *uncore,
i915_reg_t imr, u32 imr_val,
i915_reg_t ier, u32 ier_val,
@@ -111,9 +108,6 @@ void gen3_irq_init(struct intel_uncore *uncore,
#define GEN3_IRQ_RESET(uncore, type) \
gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
-#define GEN2_IRQ_RESET(uncore) \
- gen2_irq_reset(uncore)
-
#define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
({ \
unsigned int which_ = which; \
@@ -129,7 +123,4 @@ void gen3_irq_init(struct intel_uncore *uncore,
type##IER, ier_val, \
type##IIR)
-#define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \
- gen2_irq_init((uncore), imr_val, ier_val)
-
#endif /* __I915_IRQ_H__ */
--
2.34.1
[Intel-gfx] [PATCH 04/15] drm/i915: un-inline icl_hdr_plane_mask() to simplify includes
This lets us drop the heavy intel_display.h include from intel_sprite.h.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_sprite.h| 9 +
drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 +
drivers/gpu/drm/i915/display/skl_universal_plane.h | 1 +
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h
b/drivers/gpu/drm/i915/display/intel_sprite.h
index 4f63e4967731..4635c7ad23f9 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.h
+++ b/drivers/gpu/drm/i915/display/intel_sprite.h
@@ -8,14 +8,13 @@
#include
-#include "intel_display.h"
-
struct drm_device;
struct drm_display_mode;
struct drm_file;
struct drm_i915_private;
struct intel_crtc_state;
struct intel_plane_state;
+enum pipe;
/*
* FIXME: We should instead only take spinlocks once for the entire update
@@ -34,12 +33,6 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev,
void *data,
int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
-static inline u8 icl_hdr_plane_mask(void)
-{
- return BIT(PLANE_PRIMARY) |
- BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
-}
-
int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 7cb713043408..46e10b369a3d 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -246,6 +246,11 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id);
}
+u8 icl_hdr_plane_mask(void)
+{
+ return BIT(PLANE_PRIMARY) | BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
+}
+
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id
plane_id)
{
return DISPLAY_VER(dev_priv) >= 11 &&
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h
b/drivers/gpu/drm/i915/display/skl_universal_plane.h
index 351040b64dc7..be64c201f9b3 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h
@@ -30,6 +30,7 @@ int skl_calc_main_surface_offset(const struct
intel_plane_state *plane_state,
bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
enum plane_id plane_id);
+u8 icl_hdr_plane_mask(void);
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id
plane_id);
#endif
--
2.34.1
[Intel-gfx] [PATCH 02/15] drm/i915: reduce includes in intel_connector.h
Only include what's needed. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_connector.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_connector.h b/drivers/gpu/drm/i915/display/intel_connector.h index 661a37a3c6d8..c75890dc23e9 100644 --- a/drivers/gpu/drm/i915/display/intel_connector.h +++ b/drivers/gpu/drm/i915/display/intel_connector.h @@ -6,7 +6,7 @@ #ifndef __INTEL_CONNECTOR_H__ #define __INTEL_CONNECTOR_H__ -#include "intel_display.h" +#include struct drm_connector; struct edid; -- 2.34.1
[Intel-gfx] [PATCH 05/15] drm/i915/dpio: un-inline the vlv phy/channel mapping functions
Simplify the heavy intel_display_types.h header.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_types.h| 45 ---
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 42 +
drivers/gpu/drm/i915/display/intel_dpio_phy.h | 6 +++
drivers/gpu/drm/i915/display/intel_dpll.c | 1 +
drivers/gpu/drm/i915/display/intel_pps.c | 1 +
6 files changed, 51 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 2d0018ae34b1..407706448e9c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -90,6 +90,7 @@
#include "intel_display_types.h"
#include "intel_dmc.h"
#include "intel_dp_link_training.h"
+#include "intel_dpio_phy.h"
#include "intel_dpt.h"
#include "intel_dsb.h"
#include "intel_fbc.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3b7945aad22a..b683b8f90bcd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1799,51 +1799,6 @@ struct intel_dp_mst_encoder {
struct intel_connector *connector;
};
-static inline enum dpio_channel
-vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
-{
- switch (dig_port->base.port) {
- default:
- MISSING_CASE(dig_port->base.port);
- fallthrough;
- case PORT_B:
- case PORT_D:
- return DPIO_CH0;
- case PORT_C:
- return DPIO_CH1;
- }
-}
-
-static inline enum dpio_phy
-vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
-{
- switch (dig_port->base.port) {
- default:
- MISSING_CASE(dig_port->base.port);
- fallthrough;
- case PORT_B:
- case PORT_C:
- return DPIO_PHY0;
- case PORT_D:
- return DPIO_PHY1;
- }
-}
-
-static inline enum dpio_channel
-vlv_pipe_to_channel(enum pipe pipe)
-{
- switch (pipe) {
- default:
- MISSING_CASE(pipe);
- fallthrough;
- case PIPE_A:
- case PIPE_C:
- return DPIO_CH0;
- case PIPE_B:
- return DPIO_CH1;
- }
-}
-
struct intel_load_detect_pipe {
struct drm_atomic_state *restore_state;
};
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 8732b8722ed7..6fc5b9e58152 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -655,6 +655,48 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder)
return mask;
}
+enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
+{
+ switch (dig_port->base.port) {
+ default:
+ MISSING_CASE(dig_port->base.port);
+ fallthrough;
+ case PORT_B:
+ case PORT_D:
+ return DPIO_CH0;
+ case PORT_C:
+ return DPIO_CH1;
+ }
+}
+
+enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
+{
+ switch (dig_port->base.port) {
+ default:
+ MISSING_CASE(dig_port->base.port);
+ fallthrough;
+ case PORT_B:
+ case PORT_C:
+ return DPIO_PHY0;
+ case PORT_D:
+ return DPIO_PHY1;
+ }
+}
+
+enum dpio_channel vlv_pipe_to_channel(enum pipe pipe)
+{
+ switch (pipe) {
+ default:
+ MISSING_CASE(pipe);
+ fallthrough;
+ case PIPE_A:
+ case PIPE_C:
+ return DPIO_CH0;
+ case PIPE_B:
+ return DPIO_CH1;
+ }
+}
+
void chv_set_phy_signal_level(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
u32 deemph_reg_value, u32 margin_reg_value,
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
index 9c3d008e8e1a..828ad58624d8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
@@ -10,9 +10,11 @@
enum dpio_channel;
enum dpio_phy;
+enum pipe;
enum port;
struct drm_i915_private;
struct intel_crtc_state;
+struct intel_digital_port;
struct intel_encoder;
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
@@ -30,6 +32,10 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder
*encoder,
u8 lane_lat_optim_mask);
u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
+enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port);
+enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port);
+enum dpi
[Intel-gfx] [PATCH 01/15] drm/i915/gmbus: move GPIO enum to gmbus
The GPIO enum is only used in intel_gmbus.c, hide it there.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.h | 18 --
drivers/gpu/drm/i915/display/intel_gmbus.c | 20 +++-
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 884e8e67b17c..85395c8e58f9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -61,24 +61,6 @@ struct intel_remapped_info;
struct intel_rotation_info;
struct pci_dev;
-enum i915_gpio {
- GPIOA,
- GPIOB,
- GPIOC,
- GPIOD,
- GPIOE,
- GPIOF,
- GPIOG,
- GPIOH,
- __GPIOI_UNUSED,
- GPIOJ,
- GPIOK,
- GPIOL,
- GPIOM,
- GPION,
- GPIOO,
-};
-
/*
* Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
* rest have consecutive values and match the enum values of transcoders
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 6f6cfccad477..86817b56095e 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -49,9 +49,27 @@ struct intel_gmbus {
struct drm_i915_private *i915;
};
+enum gmbus_gpio {
+ GPIOA,
+ GPIOB,
+ GPIOC,
+ GPIOD,
+ GPIOE,
+ GPIOF,
+ GPIOG,
+ GPIOH,
+ __GPIOI_UNUSED,
+ GPIOJ,
+ GPIOK,
+ GPIOL,
+ GPIOM,
+ GPION,
+ GPIOO,
+};
+
struct gmbus_pin {
const char *name;
- enum i915_gpio gpio;
+ enum gmbus_gpio gpio;
};
/* Map gmbus pin pairs to names and registers. */
--
2.34.1
[Intel-gfx] [PATCH 00/15] drm/i915: header cleanups
Some header cleanups to reduce our interdependencies. Here are some stats for i915, and part of the reason I keep doing this and nagging about casual addition of includes, especially in headers. We currently have 348 .c files and 353 .h files. 28% (98/353) of the header files, when modified, cause the rebuild of at least 83% (289+/348) .c files, virtually the entire driver. For reference, a random data point v5.10, we had 282 .c files, 240 .h files, and 33% (80/240) of the header files, when modified, caused the rebuild of at least 81% (228+/282) .c files. We have more files, but proportionally fewer headers cause the rebuild of the entire driver. The cutoff above for 83% (and 81% for v5.10) is clear by looking at the list below; there's a steep drop in dependencies at that point. Basically all roads lead to and from i915_drv.h. Reducing the amount of stuff in i915_drv.h, and especially the headers it includes recursively, help incremental builds the most. "If you modify this header, how many .c files get rebuilt?" drivers/gpu/drm/i915/selftests/i915_perf_selftests.h: 324 drivers/gpu/drm/i915/selftests/i915_mock_selftests.h: 324 drivers/gpu/drm/i915/selftests/i915_live_selftests.h: 324 drivers/gpu/drm/i915/i915_utils.h: 324 drivers/gpu/drm/i915/i915_selftest.h: 324 drivers/gpu/drm/i915/i915_gem.h: 319 drivers/gpu/drm/i915/i915_sw_fence.h: 315 drivers/gpu/drm/i915/i915_reg_defs.h: 314 drivers/gpu/drm/i915/intel_wakeref.h: 313 drivers/gpu/drm/i915/intel_runtime_pm.h: 313 drivers/gpu/drm/i915/i915_scatterlist.h: 313 drivers/gpu/drm/i915/i915_gem_ww.h: 313 drivers/gpu/drm/i915/intel_uncore.h: 312 drivers/gpu/drm/i915/i915_vma_resource.h: 312 drivers/gpu/drm/i915/i915_tasklet.h: 312 drivers/gpu/drm/i915/i915_scheduler_types.h: 312 drivers/gpu/drm/i915/i915_scheduler.h: 312 drivers/gpu/drm/i915/i915_request.h: 312 drivers/gpu/drm/i915/i915_priolist_types.h: 312 drivers/gpu/drm/i915/i915_pmu.h: 312 drivers/gpu/drm/i915/i915_active_types.h: 312 drivers/gpu/drm/i915/i915_active.h: 312 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h: 312 drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h: 312 drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h: 312 drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h: 312 drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h: 312 drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h: 312 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h: 312 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h: 312 drivers/gpu/drm/i915/gt/intel_workarounds_types.h: 312 drivers/gpu/drm/i915/gt/intel_timeline_types.h: 312 drivers/gpu/drm/i915/gt/intel_sseu.h: 312 drivers/gpu/drm/i915/gt/intel_engine_types.h: 312 drivers/gpu/drm/i915/gt/intel_context_types.h: 312 drivers/gpu/drm/i915/gem/i915_gem_context_types.h: 312 drivers/gpu/drm/i915/gem/i915_gem_object_types.h: 311 drivers/gpu/drm/i915/intel_memory_region.h: 310 drivers/gpu/drm/i915/i915_vma_types.h: 309 drivers/gpu/drm/i915/i915_params.h: 309 drivers/gpu/drm/i915/i915_gem_gtt.h: 309 drivers/gpu/drm/i915/gt/intel_reset_types.h: 309 drivers/gpu/drm/i915/gt/intel_reset.h: 309 drivers/gpu/drm/i915/gt/intel_gtt.h: 309 drivers/gpu/drm/i915/gem/i915_gem_object.h: 309 drivers/gpu/drm/i915/display/intel_frontbuffer.h: 309 drivers/gpu/drm/i915/i915_vma.h: 307 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h: 307 drivers/gpu/drm/i915/display/intel_display.h: 307 drivers/gpu/drm/i915/intel_step.h: 302 drivers/gpu/drm/i915/intel_device_info.h: 302 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h: 302 drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h: 302 drivers/gpu/drm/i915/gt/uc/intel_huc.h: 301 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h: 301 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h: 301 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h: 301 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h: 301 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h: 301 drivers/gpu/drm/i915/gt/uc/intel_guc_log.h: 301 drivers/gpu/drm/i915/gt/uc/intel_guc.h: 301 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h: 301 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h: 301 drivers/gpu/drm/i915/gt/uc/intel_uc.h: 300 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h: 300 drivers/gpu/drm/i915/gt/intel_rps_types.h: 299 drivers/gpu/drm/i915/pxp/intel_pxp_types.h: 298 drivers/gpu/drm/i915/gt/intel_rc6_types.h: 298 drivers/gpu/drm/i915/gt/intel_migrate_types.h: 298 drivers/gpu/drm/i915/gt/intel_llc_types.h: 298 drivers/gpu/drm/i915/gt/intel_hwconfig.h: 298 drivers/gpu/drm/i915/gt/intel_gt_types.h: 298 drivers/gpu/drm/i915/gt/intel_gt_buffer_pool_types.h: 298 drivers/gpu/drm/i915/gt/intel_gsc.h: 298 drivers/gpu/drm/i915/i915_syncmap.h: 296 drivers/gpu/drm/i915/gt/intel_timeline.h: 295 drivers/gpu/drm/i915/intel_pm_types.h: 294 drivers/gpu/drm/i915/gt/intel_workarounds.h: 294 drivers/gpu/drm/i915/gt/intel_engine.h: 294 drivers/gpu/drm/i915/display/intel_dpll_mgr.h: 294 drivers/gpu/drm/i915/display/intel_display_power.h: 294 drivers/gpu/drm/i915/gem/i915_gem_lmem.h: 290 drivers/gpu/drm/i915/intel_wopcm.h: 289 drivers/gpu/drm/i915/inte
Re: [Intel-gfx] [PATCH] drm/i915: Fix display problems after resume
On Mon, Sep 12, 2022 at 02:48:54PM +0200, Thomas Hellström wrote:
> On Mon, 2022-09-12 at 15:43 +0300, Ville Syrjälä wrote:
> > On Mon, Sep 12, 2022 at 02:19:57PM +0200, Thomas Hellström wrote:
> > > Commit 39a2bd34c933 ("drm/i915: Use the vma resource as argument
> > > for gtt
> > > binding / unbinding") introduced a regression that due to the vma
> > > resource
> > > tracking of the binding state, dpt ptes were not correctly
> > > repopulated.
> >
> > Doesn't this mean all ggtt ptes weren't repopulated? So I'm
> > wondering how anything at all has been working?
>
> ggtt ptes had a different check that was copy-pasted from the pre-vma-
> resource code and that wasn't that strict. Hence why it worked.
The ggtt one seems to want to skip if the vma is already bound
with the other flag than what we're using this time, but doesn't
skip if it's already bound with the same flag(s). I have no idea
what it's trying to achieve there.
The dpt case skips if it's a bound at all, which seems much more
obvious but the fact that ggtt code never did that makes me
suspect it's not that clear cut.
So seems to me that the two checks are trying to do achieve
different goals, but at least I can't tell why that is.
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v3 19/37] drm/i915: stop using kernel-doc markups for something else
Hi Matt,
Em Mon, 12 Sep 2022 08:09:57 -0700
Matt Roper escreveu:
> > --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
>
> Several of the comments in this file do appear to be kerneldoc (in fact
> kerneldoc that was specifically requested during code review at
> https://patchwork.freedesktop.org/patch/448456/#comment_804252) and this
> file is included from Documentation/gpu/i915.rst, so I think some of
> these changes might be moving in the wrong direction. Should we instead
> focus on fixing up the comments that aren't quite formatted properly?
Those *appear* to be kernel-doc markups, but they aren't, because
the structs themselves are not properly marked. See, for instance
struct intel_context.
scripts/kerneldoc will *only* consider what's there as a proper
comment if you add:
/**
* struct intel_context - describes an i915 context
*
*/
struct intel_context {
union {
/** @ref: a kernel object reference */
struct kref ref; /* no kref_get_unless_zero()! */
/** @rcu: a rcu header */
struct rcu_head rcu;
};
...
}
Describing all fields inside the struct. Just placing
/** something */
on some random places in the middle doesn't make it a kernel-doc.
If you actually run kernel-doc in Werror mode:
./scripts/kernel-doc -Werror -sphinx-version 2.4.4
drivers/gpu/drm/i915/gt/intel_context_types.h | echo "ERROR!"
ERROR!
drivers/gpu/drm/i915/gt/intel_context_types.h:1: warning: no structured
comments found
1 warnings as Errors
you'll see that this is currently broken.
Thanks,
Mauro
Re: [Intel-gfx] [PATCH 2/7] drm/i915/hwmon: Add HWMON current voltage support
On Mon, 12 Sep 2022 07:09:28 -0700, Gupta, Anshuman wrote:
>
> > +static int
> > +hwm_in_read(struct hwm_drvdata *ddat, u32 attr, long *val) {
> > + struct i915_hwmon *hwmon = ddat->hwmon;
> > + intel_wakeref_t wakeref;
> > + u32 reg_value;
> > +
> > + switch (attr) {
> > + case hwmon_in_input:
>
> Other attributes in this series take hwmon->lock before accessing i915
> registers , So do we need lock here as well ?
The lock is being taken only for RMW and for making sure energy counter
updates happen atomically. We are not taking the lock for just reads so IMO
no lock is needed here.
> > + with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
> > + reg_value = intel_uncore_read(ddat->uncore, hwmon-
> > >rg.gt_perf_status);
> > + /* In units of 2.5 millivolt */
> > + *val =
> > DIV_ROUND_CLOSEST(REG_FIELD_GET(GEN12_VOLTAGE_MASK, reg_value) *
> > 25, 10);
> > + return 0;
> > + default:
> > + return -EOPNOTSUPP;
> > + }
> > +}
Thanks.
--
Ashutosh
[Intel-gfx] [PATCH v1 0/1] drm/i915: Copy engine fuses future-proofing
Fix missing IP version when applying copy engine fuses. Signed-off-by: Lucas De Marchi --- Lucas De Marchi (1): drm/i915: Skip applying copy engine fuses drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 1 file changed, 4 insertions(+) --- base-commit: 088771790e5d121c70c358468abbebb4710eb02f change-id: 20220912-copy-engine-526db816b088 Best regards, -- Lucas De Marchi
[Intel-gfx] [PATCH v1 1/1] drm/i915: Skip applying copy engine fuses
Support for reading the fuses to check what are the Link Copy engines
was added in commit ad5f74f34201 ("drm/i915/pvc: read fuses for link
copy engines"). However they were added unconditionally because the
FUSE3 register is present since graphics version 10.
However the bitfield with meml3 fuses only exists since graphics version
12. Moreover, Link Copy engines are currently only available in PVC.
Tying additional copy engines to the meml3 fuses is not correct for
other platforms.
Make sure there is a check for `12.60 <= ver < 12.70`. Later platforms
may extend this function later if it's needed to fuse off copy engines.
Currently it's harmless as the Link Copy engines are still not exported:
info->engine_mask only has BCS0 set and the register is only read for
platforms that do have it.
Signed-off-by: Lucas De Marchi
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 814f83b5fe59..1f7188129cd1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -764,6 +764,10 @@ static void engine_mask_apply_copy_fuses(struct intel_gt
*gt)
unsigned long meml3_mask;
unsigned long quad;
+ if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
+ GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
+ return;
+
meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
--
b4 0.10.0-dev-df873
Re: [Intel-gfx] [PATCH v2 0/2] drm/i915: Media fuses future-proofing
On Fri, Sep 09, 2022 at 04:18:14PM -0700, Lucas De Marchi wrote: Update fuse handling for media to future-proof it. Signed-off-by: Lucas De Marchi Thanks Matt Roper and Andrzej for the review. Applied. Lucas De Marchi
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Extract function to apply media fuses
On Mon, Sep 12, 2022 at 10:56:16AM +0200, Andrzej Hajda wrote:
On 10.09.2022 01:18, Lucas De Marchi wrote:
Just like is done for compute and copy engines, extract a function to
handle media engines. While at it, be consistent on using or not the
uncore/gt/info variable aliases.
Reviewed-by: Matt Roper
Signed-off-by: Lucas De Marchi
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index b6602439224d..814f83b5fe59 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -663,6 +663,74 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
return false;
}
+static void engine_mask_apply_media_fuses(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ unsigned int logical_vdbox = 0;
+ unsigned int i;
+ u32 media_fuse, fuse1;
+ u16 vdbox_mask;
+ u16 vebox_mask;
+
+ if (MEDIA_VER(gt->i915) < 11)
+ return;
+
+ /*
+* On newer platforms the fusing register is called 'enable' and has
+* enable semantics, while on older platforms it is called 'disable'
+* and bits have disable semantices.
+*/
+ media_fuse = intel_uncore_read(gt->uncore,
GEN11_GT_VEBOX_VDBOX_DISABLE);
+ if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
+ media_fuse = ~media_fuse;
+
+ vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
+ vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
+ GEN11_GT_VEBOX_DISABLE_SHIFT;
+
+ if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
+ fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
+ gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
+ } else {
+ gt->info.sfc_mask = ~0;
+ }
+
+ for (i = 0; i < I915_MAX_VCS; i++) {
+ if (!HAS_ENGINE(gt, _VCS(i))) {
+ vdbox_mask &= ~BIT(i);
+ continue;
+ }
+
+ if (!(BIT(i) & vdbox_mask)) {
+ gt->info.engine_mask &= ~BIT(_VCS(i));
+ drm_dbg(&i915->drm, "vcs%u fused off\n", i);
+ continue;
+ }
+
+ if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
+ gt->info.vdbox_sfc_access |= BIT(i);
+ logical_vdbox++;
+ }
+ drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
+ vdbox_mask, VDBOX_MASK(gt));
+ GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
+
+ for (i = 0; i < I915_MAX_VECS; i++) {
+ if (!HAS_ENGINE(gt, _VECS(i))) {
+ vebox_mask &= ~BIT(i);
+ continue;
+ }
+
+ if (!(BIT(i) & vebox_mask)) {
+ gt->info.engine_mask &= ~BIT(_VECS(i));
+ drm_dbg(&i915->drm, "vecs%u fused off\n", i);
+ }
+ }
+ drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
+ vebox_mask, VEBOX_MASK(gt));
+ GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
+}
+
static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -671,6 +739,9 @@ static void engine_mask_apply_compute_fuses(struct intel_gt
*gt)
unsigned long ccs_mask;
unsigned int i;
+ if (GRAPHICS_VER(i915) < 11)
+ return;
+
Why there is no similar sentinel in case of engine_mask_apply_copy_fuses?
Beside this:
Reviewed-by: Andrzej Hajda
I noticed it too while doing these patches. I have a pending one for
that, but it seems I failed to send it on Friday.
drm/i915: Skip applying copy engine fuses
Support for reading the fuses to check what are the Link Copy engines
was added in commit ad5f74f34201 ("drm/i915/pvc: read fuses for link
copy engines"). However they were added unconditionally because the
FUSE3 register is present since graphics version 10.
However the bitfield with meml3 fuses only exists since graphics version
12. Moreover, Link Copy engines are currently only available in PVC.
Tying additional copy engines to the meml3 fuses is not correct for
other platforms.
Make sure there is a check for `12.60 <= ver < 12.70`. Later platforms
may extend this function later if it's needed to fuse off copy engines.
Currently it's harmless as the Link Copy engines are still not exported:
info->engine_mask only has BCS0 set and the register is only read for
platforms that do have it.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 6e0122b3dca2..ac5ff17888cd 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -694,6 +694,10 @@ static voi
Re: [Intel-gfx] [PATCH v3 19/37] drm/i915: stop using kernel-doc markups for something else
On Fri, Sep 09, 2022 at 09:34:26AM +0200, Mauro Carvalho Chehab wrote: > There are some occurrences of "/**" that aren't actually part of > a kernel-doc markup. Replace them by "/*", in order to make easier > to identify what i915 files contain kernel-doc markups. > > Reviewed-by: Rodrigo Vivi > Signed-off-by: Mauro Carvalho Chehab > --- > > To avoid mailbombing on a large number of people, only mailing lists were C/C > on the cover. > See [PATCH v3 00/37] at: > https://lore.kernel.org/all/cover.1662708705.git.mche...@kernel.org/ > > drivers/gpu/drm/i915/display/dvo_ch7017.c | 26 +++ > drivers/gpu/drm/i915/display/dvo_ch7xxx.c | 6 +- > .../drm/i915/display/intel_display_types.h| 2 +- > drivers/gpu/drm/i915/display/intel_dvo_dev.h | 6 +- > drivers/gpu/drm/i915/display/intel_sdvo.c | 4 +- > drivers/gpu/drm/i915/display/intel_tv.c | 2 +- > drivers/gpu/drm/i915/gt/intel_context_types.h | 69 +-- > drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h | 2 +- > drivers/gpu/drm/i915/gt/intel_gt_types.h | 12 ++-- > drivers/gpu/drm/i915/gt/intel_reset_types.h | 4 +- > .../gpu/drm/i915/gt/intel_timeline_types.h| 6 +- > .../drm/i915/gt/shaders/clear_kernel/hsw.asm | 4 +- > .../drm/i915/gt/shaders/clear_kernel/ivb.asm | 4 +- > drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 10 +-- > drivers/gpu/drm/i915/i915_drm_client.h| 2 +- > drivers/gpu/drm/i915/i915_drv.h | 24 +++ > drivers/gpu/drm/i915/i915_file_private.h | 8 +-- > drivers/gpu/drm/i915/i915_gpu_error.h | 4 +- > drivers/gpu/drm/i915/i915_pmu.h | 32 - > drivers/gpu/drm/i915/intel_uncore.h | 4 +- > 20 files changed, 115 insertions(+), 116 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/dvo_ch7017.c > b/drivers/gpu/drm/i915/display/dvo_ch7017.c > index 0589994dde11..581e29ab77e4 100644 > --- a/drivers/gpu/drm/i915/display/dvo_ch7017.c > +++ b/drivers/gpu/drm/i915/display/dvo_ch7017.c > @@ -55,13 +55,13 @@ > #define CH7017_TEST_PATTERN 0x48 > > #define CH7017_POWER_MANAGEMENT 0x49 > -/** Enables the TV output path. */ > +/* Enables the TV output path. */ > #define CH7017_TV_EN (1 << 0) > #define CH7017_DAC0_POWER_DOWN (1 << 1) > #define CH7017_DAC1_POWER_DOWN (1 << 2) > #define CH7017_DAC2_POWER_DOWN (1 << 3) > #define CH7017_DAC3_POWER_DOWN (1 << 4) > -/** Powers down the TV out block, and DAC0-3 */ > +/* Powers down the TV out block, and DAC0-3 */ > #define CH7017_TV_POWER_DOWN_EN (1 << 5) > > #define CH7017_VERSION_ID0x4a > @@ -84,26 +84,26 @@ > #define CH7017_UP_SCALER_HORIZONTAL_INC_10x5e > > #define CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT 0x5f > -/**< Low bits of horizontal active pixel input */ > +/* Low bits of horizontal active pixel input */ > > #define CH7017_ACTIVE_INPUT_LINE_OUTPUT 0x60 > -/** High bits of horizontal active pixel input */ > +/* High bits of horizontal active pixel input */ > #define CH7017_LVDS_HAP_INPUT_MASK (0x7 << 0) > -/** High bits of vertical active line output */ > +/* High bits of vertical active line output */ > #define CH7017_LVDS_VAL_HIGH_MASK(0x7 << 3) > > #define CH7017_VERTICAL_ACTIVE_LINE_OUTPUT 0x61 > -/**< Low bits of vertical active line output */ > +/* Low bits of vertical active line output */ > > #define CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT0x62 > -/**< Low bits of horizontal active pixel output */ > +/* Low bits of horizontal active pixel output */ > > #define CH7017_LVDS_POWER_DOWN 0x63 > -/** High bits of horizontal active pixel output */ > +/* High bits of horizontal active pixel output */ > #define CH7017_LVDS_HAP_HIGH_MASK(0x7 << 0) > -/** Enables the LVDS power down state transition */ > +/* Enables the LVDS power down state transition */ > #define CH7017_LVDS_POWER_DOWN_EN(1 << 6) > -/** Enables the LVDS upscaler */ > +/* Enables the LVDS upscaler */ > #define CH7017_LVDS_UPSCALER_EN (1 << 7) > #define CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED 0x08 > > @@ -116,9 +116,9 @@ > #define CH7017_LVDS_ENCODING_2 0x65 > > #define CH7017_LVDS_PLL_CONTROL 0x66 > -/** Enables the LVDS panel output path */ > +/* Enables the LVDS panel output path */ > #define CH7017_LVDS_PANEN(1 << 0) > -/** Enables the LVDS panel backlight */ > +/* Enables the LVDS panel backlight */ > #define CH7017_LVDS_BKLEN(1 << 3) > > #define CH7017_POWER_SEQUENCING_T1 0x67 > @@ -197,7 +197,7 @@ static bool ch7017_write(struct intel_dvo_device *dvo, u8 > addr, u8 val) > return i2c_transfer(dvo->i2c_bus, &msg, 1) == 1; > } > > -/** Probes for a CH7017 on the given bus and slave address. */ > +/* Probes for a CH7017 on the given bus and slave address. */ > static bool ch7017_init(struct intel_dvo_device
Re: [Intel-gfx] [PATCH v4 05/15] mei: pxp: add command streamer API to the PXP driver
On Mon, Sep 12, 2022 at 09:59:45AM +, Winkler, Tomas wrote:
> >
> > On Fri, Sep 09, 2022 at 06:38:33AM +, Winkler, Tomas wrote:
> > > >
> > > > On Thu, Sep 08, 2022 at 05:16:02PM -0700, Daniele Ceraolo Spurio wrote:
> > > > > +static ssize_t mei_pxp_gsc_command(struct device *dev, u8
> > > > > +client_id,
> > > > u32 fence_id,
> > > > > +struct scatterlist *sg_in, size_t
> > > > > total_in_len,
> > > > > +struct scatterlist *sg_out) {
> > > > > + struct mei_cl_device *cldev;
> > > > > +
> > > > > + if (!dev || !sg_in || !sg_out)
> > > > > + return -EINVAL;
> > > >
> > > > How can these ever be NULL? Doesn't the core control this, so why
> > > > would that happen?
> > > This is any interface function between modules, I think it is not
> > > healthy to take assumptions here about how caller behaves, this is not an
> > inner functions. This is important even for catching programmatical
> > mistakes.
> >
> > It is a static function being called from a framework. Enforce this in the
> > framework, don't sprinkle this stuff everywhere, the kernel is NOT defensive
> > about internal users like this otherwise it will overwhelm every function
> > call.
>
> I'm not sure, this is the case here. The function is passed to i915 (other
> driver) driver via struct i915_pxp_component_op.
> This is outside of the component framework.
Then pass in the real mei structure please. Don't force someone else to
"find" it in the device tree like you are currently trying to do.
thanks,
greg k-h
Re: [Intel-gfx] [PATCH 2/7] drm/i915/hwmon: Add HWMON current voltage support
> -Original Message-
> From: Nilawar, Badal
> Sent: Thursday, August 25, 2022 6:51 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Dixit, Ashutosh ; Tauro, Riana
> ; Gupta, Anshuman ;
> Ewins, Jon ; linux-hw...@vger.kernel.org
> Subject: [PATCH 2/7] drm/i915/hwmon: Add HWMON current voltage support
>
> From: Riana Tauro
>
> Use i915 HWMON subsystem to display current input voltage.
>
> v2:
> - Updated date and kernel version in feature description
> - Fixed review comments (Ashutosh)
> v3: Use macro HWMON_CHANNEL_INFO to define hwmon channel (Guenter)
> v4:
> - Fixed review comments (Ashutosh)
> - Use hwm_ prefix for static functions (Ashutosh)
>
> Cc: Guenter Roeck
> Cc: Anshuman Gupta
> Signed-off-by: Riana Tauro
> Signed-off-by: Badal Nilawar
> Acked-by: Guenter Roeck
> ---
> .../ABI/testing/sysfs-driver-intel-i915-hwmon | 7 +++
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++
> drivers/gpu/drm/i915/i915_hwmon.c | 47 +++
> 3 files changed, 57 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> new file mode 100644
> index ..24c4b7477d51
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> @@ -0,0 +1,7 @@
> +What:/sys/devices/.../hwmon/hwmon/in0_input
> +Date:June 2022
> +KernelVersion: 5.19
> +Contact: dri-de...@lists.freedesktop.org
> +Description: RO. Current Voltage in millivolt.
> +
> + Only supported for particular Intel i915 graphics platforms.
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 94f9ddcfb3a5..5d4fbda4d326 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1508,6 +1508,9 @@
> #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
> #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)
>
> +#define GEN12_RPSTAT1_MMIO(0x1381b4)
> +#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
> +
> #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 +
> ((x) * 4))
> #define GEN11_CSME (31)
> #define GEN11_GUNIT(28)
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
> b/drivers/gpu/drm/i915/i915_hwmon.c
> index 103dd543a214..2192d0fd4c66 100644
> --- a/drivers/gpu/drm/i915/i915_hwmon.c
> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> @@ -11,8 +11,10 @@
> #include "i915_hwmon.h"
> #include "i915_reg.h"
> #include "intel_mchbar_regs.h"
> +#include "gt/intel_gt_regs.h"
>
> struct hwm_reg {
> + i915_reg_t gt_perf_status;
> };
>
> struct hwm_drvdata {
> @@ -29,14 +31,49 @@ struct i915_hwmon {
> };
>
> static const struct hwmon_channel_info *hwm_info[] = {
> + HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
> NULL
> };
>
> +static umode_t
> +hwm_in_is_visible(const struct hwm_drvdata *ddat, u32 attr) {
> + switch (attr) {
> + case hwmon_in_input:
> + return i915_mmio_reg_valid(ddat->hwmon->rg.gt_perf_status)
> ? 0444 : 0;
> + default:
> + return 0;
> + }
> +}
> +
> +static int
> +hwm_in_read(struct hwm_drvdata *ddat, u32 attr, long *val) {
> + struct i915_hwmon *hwmon = ddat->hwmon;
> + intel_wakeref_t wakeref;
> + u32 reg_value;
> +
> + switch (attr) {
> + case hwmon_in_input:
Other attributes in this series take hwmon->lock before accessing i915
registers ,
So do we need lock here as well ?
Thanks,
Anshuman Gupta.
> + with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
> + reg_value = intel_uncore_read(ddat->uncore, hwmon-
> >rg.gt_perf_status);
> + /* In units of 2.5 millivolt */
> + *val =
> DIV_ROUND_CLOSEST(REG_FIELD_GET(GEN12_VOLTAGE_MASK, reg_value) *
> 25, 10);
> + return 0;
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> static umode_t
> hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> u32 attr, int channel)
> {
> + struct hwm_drvdata *ddat = (struct hwm_drvdata *)drvdata;
> +
> switch (type) {
> + case hwmon_in:
> + return hwm_in_is_visible(ddat, attr);
> default:
> return 0;
> }
> @@ -46,7 +83,11 @@ static int
> hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
>int channel, long *val)
> {
> + struct hwm_drvdata *ddat = dev_get_drvdata(dev);
> +
> switch (type) {
> + case hwmon_in:
> + return hwm_in_read(ddat, attr, val);
> default:
> return -EOPNOTSUPP;
> }
> @@ -76,6 +117,12 @@ static const struct hwmon_chip_info hwm_chip_info = {
> static void hwm_get_preregistration_info(struct drm_i91
Re: [Intel-gfx] [PULL] drm-intel-fixes
On Sun, 2022-09-11 at 19:22 +0200, Jason A. Donenfeld wrote:
> Hi Rodrigo,
>
> On Thu, Sep 08, 2022 at 09:59:54AM -0400, Rodrigo Vivi wrote:
> > Hi Dave and Daniel,
> >
> > A few fixes, but most targeting stable.
> >
> > [...]
> >
> > Ville Syrjälä (2):
> > drm/i915: Implement WaEdpLinkRateDataReload
>
> Don't you need to revert d5929835080a60f9119d024fa42f315913942f76 in
> order for "drm/i915: Implement WaEdpLinkRateDataReload" to actually
> be
> useful/interesting? Otherwise, what's the point?
Unfortunately there was no clear indication on the revert patch for
the tool to pick, and I hadn't followed that front myself closely.
Should
483e3d87a37e ("Revert "drm/i915/display: Re-add check for low voltage
sku for max dp source rate"")
have a Fixes tag?
Or should dim consider all reverts as Fixes?
Anyway, I will cherry pick this to our fixes branch for propagation
this week.
Thanks for the heads up,
Rodrigo.
>
> Regards,
> Jason
[Intel-gfx] NULL pointer dereference in i915 in i915_gem_do_execbuffer, eb_lookup_vmas
Hi all, I experience periodic crashes on HP Elite Dragonfly G2 (i7-1165G7) which, I believe, are related to a bug in the i915 driver. I collected a stacktrace and a kdump on 5.19.8 compiled with KASAN. This time the screen was frozen, but I could SSH into the machine. Sometimes a kernel panic happens. I will appreciate it if this can be fixed. Please find the decoded stack trace below: [ +13,386280] general protection fault, probably for non-canonical address 0xdcec: [#1] PREEMPT SMP DEBUG_PAGEALLOC KASAN NOPTI [ +0,24] KASAN: null-ptr-deref in range [0x0760-0x0767] [ +0,17] Hardware name: HP HP Elite Dragonfly G2 Notebook PC/8716, BIOS T90 Ver. 01.01.04 01/03/2021 [ +0,06] RIP: 0010:i915_gem_do_execbuffer (./drivers/gpu/drm/i915/gem/i915_gem_object.h:632 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:921 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:3391) i915 [ +0,000207] Code: b8 00 00 00 48 89 f8 48 c1 e8 03 80 3c 28 00 0f 85 5d 3f 00 00 4d 8b af b8 00 00 00 49 8d bd 60 07 00 00 48 89 f8 48 c1 e8 03 <80> 3c 28 00 0f 85 34 3f 00 00 49 83 bd 60 07 00 00 00 74 6c 4c 89 All code 0:b8 00 00 00 48 mov$0x4800,%eax 5:89 f8mov%edi,%eax 7:48 c1 e8 03 shr$0x3,%rax b:80 3c 28 00 cmpb $0x0,(%rax,%rbp,1) f:0f 85 5d 3f 00 00jne0x3f72 15:4d 8b af b8 00 00 00 mov0xb8(%r15),%r13 1c:49 8d bd 60 07 00 00 lea0x760(%r13),%rdi 23:48 89 f8 mov%rdi,%rax 26:48 c1 e8 03 shr$0x3,%rax 2a:*80 3c 28 00 cmpb $0x0,(%rax,%rbp,1) <-- trapping instruction 2e:0f 85 34 3f 00 00jne0x3f68 34:49 83 bd 60 07 00 00 cmpq $0x0,0x760(%r13) 3b:00 3c:74 6cje 0xaa 3e:4c rex.WR 3f:89 .byte 0x89 Code starting with the faulting instruction === 0:80 3c 28 00 cmpb $0x0,(%rax,%rbp,1) 4:0f 85 34 3f 00 00jne0x3f3e a:49 83 bd 60 07 00 00 cmpq $0x0,0x760(%r13) 11:00 12:74 6cje 0x80 14:4c rex.WR 15:89 .byte 0x89 [ +0,08] RSP: 0018:c9000a74f7e8 EFLAGS: 00010202 [ +0,09] RAX: 00ec RBX: 0008 RCX: [ +0,06] RDX: 0001 RSI: c9000a74f880 RDI: 0760 [ +0,05] RBP: dc00 R08: 888135ae8000 R09: [ +0,05] R10: fbfff5b2f5a4 R11: c16145cb R12: 0008 [ +0,05] R13: R14: 001c R15: 88813513d640 [ +0,05] FS: 7f1329fced00() GS:1000() knlGS: [ +0,07] CS: 0010 DS: ES: CR0: 80050033 [ +0,05] CR2: 7f5c6ff8f80c CR3: 00011493e005 CR4: 00f70ef0 [ +0,06] PKRU: 5554 [ +0,04] Call Trace: [ +0,05] [ +0,10] ? parse_timeline_fences (drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:3292) i915 [ +0,000193] ? kernel_text_address (kernel/extable.c:125 kernel/extable.c:94) [ +0,39] ? reacquire_held_locks (kernel/locking/lockdep.c:5674) [ +0,09] ? __schedule_bug (kernel/sched/core.c:9820) [ +0,14] i915_gem_execbuffer2_ioctl (drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:3543) i915 [ +0,000184] ? i915_gem_do_execbuffer (drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:3503) i915 [ +0,000177] drm_ioctl_kernel (drivers/gpu/drm/drm_ioctl.c:782) [ +0,09] ? drm_version (drivers/gpu/drm/drm_ioctl.c:767) [ +0,11] drm_ioctl (drivers/gpu/drm/drm_ioctl.c:886) [ +0,08] ? i915_gem_do_execbuffer (drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:3503) i915 [ +0,000174] ? drm_ioctl_kernel (drivers/gpu/drm/drm_ioctl.c:807) [ +0,06] ? lock_release (./include/trace/events/lock.h:69 kernel/locking/lockdep.c:5677) [ +0,08] ? lock_downgrade (kernel/locking/lockdep.c:5634) [ +0,07] ? ktime_get_coarse_real_ts64 (./include/linux/seqlock.h:274 kernel/time/timekeeping.c:2261) [ +0,19] __x64_sys_ioctl (fs/ioctl.c:51 fs/ioctl.c:870 fs/ioctl.c:856 fs/ioctl.c:856) [ +0,09] do_syscall_64 (arch/x86/entry/common.c:50 arch/x86/entry/common.c:80) [ +0,08] ? do_syscall_64 (arch/x86/entry/common.c:87) [ +0,07] entry_SYSCALL_64_after_hwframe (arch/x86/entry/entry_64.S:120) [ +0,08] RIP: 0033:0x7f132a9579ef [ +0,06] Code: 00 48 89 44 24 18 31 c0 48 8d 44 24 60 c7 04 24 10 00 00 00 48 89 44 24 08 48 8d 44 24 20 48 89 44 24 10 b8 10 00 00 00 0f 05 <89> c2 3d 00 f0 ff ff 77 18 48 8b 44 24 18 64 48 2b 04 25 28 00 00 All code 0:00 48 89 add%cl,-0x77(%rax) 3:44 24 18 rex.R and $0x18,%al 6:31 c0
Re: [Intel-gfx] [PATCH v2 10/41] drm/modes: Add a function to generate analog display modes
Hi Maxime, W dniu 9.09.2022 o 16:00, Maxime Ripard pisze: > On Wed, Sep 07, 2022 at 11:31:21PM +0200, Mateusz Kwiatkowski wrote: >> The "canonical" modelines (at least for vc4's VEC, see the notes below): >> >> - (vfp==4, vsync==6, vbp==39) for 576i >> - (vfp==7, vsync==6, vbp==32) for 480i >> - (vfp==5, vsync==6, vbp==28) for 486i (full frame NTSC as originally >> specified) > > It's not clear to me either how you come up with those timings? Well, experimentally ;) The values for 480i and 576i are the values currently used by the downstream kernel, and those in turn has been copied from the firmware (or more precisely, I chose them so that the PV registers end up the same as the values set by the firmware). I also checked with an oscilloscope that the waveforms look as they should. VEC doesn't exactly handle the half-lines at the start and end of the odd field right, but otherwise, the blanking and sync pulses are where they should be. The 486i values has been constructed from the 480i ones according to the calculations from cross-referencing SMPTE documents, see my previous e-mail. I know this is perhaps unsatisfactory ;) I don't have access to the VC4 documentation, so this was _almost_ reverse engineering for me. Best regards, Mateusz Kwiatkowski
Re: [Intel-gfx] [PATCH] drm/i915/gvt: fix double-free bug in split_2MB_gtt_entry.
Hi Greg, I got it, Greg. Mid-Autumn Festival is coming and I will have a couple of days off. I'll see what I can do after holiday :) Regards, Zheng Wang 在 2022年9月8日星期四，Greg KH 写道： > On Thu, Sep 08, 2022 at 05:09:40PM +0800, Zheng Hacker wrote: > > Hi Zhenyu, > > > > This issue has been open for a few days. Could you plz write a patch > > for that :) I'm not familiar with the logical code here. > > As this is only able to be hit in a theoretical system, it isn't that > high of a priority, if any priority at all. Why not try to write a > patch for it yourself to help resolve the issue faster? > > thanks, > > greg k-h >
Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gvt: fix double-free bug in split_2MB_gtt_entry.
>From 18fc95d6a73f0af7e8947a1cb01a3a39f2e61c00 Mon Sep 17 00:00:00 2001
From: xmzyshypnc <1002992...@qq.com>
Date: Sun, 4 Sep 2022 20:20:56 +0800
Subject: [PATCH] drm/i915/gvt: fix double-free bug in split_2MB_gtt_entry.
There is a double-free security bug in split_2MB_gtt_entry.
Here is a calling chain :
ppgtt_populate_spt->ppgtt_populate_shadow_entry->split_2MB_gtt_entry.
If intel_gvt_dma_map_guest_page failed, it will call
ppgtt_invalidate_spt, which will finally call ppgtt_free_spt and
kfree(spt). But the caller does not notice that, and it will call
ppgtt_free_spt again in error path.
Fix this by returning the result of ppgtt_invalidate_spt to split_2MB_gtt_entry.
Signed-off-by: Zheng Wang <1002992...@qq.com>
---
drivers/gpu/drm/i915/gvt/gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index ce0eb03709c3..9f14fded8c0c 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1215,7 +1215,7 @@ static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
ret = intel_gvt_dma_map_guest_page(vgpu, start_gfn + sub_index,
PAGE_SIZE, &dma_addr);
if (ret) {
- ppgtt_invalidate_spt(spt);
+ ret = ppgtt_invalidate_spt(spt);
return ret;
}
sub_se.val64 = se->val64;
--
2.25.1
Re: [Intel-gfx] [PATCH v2 37/41] drm/sun4i: tv: Remove useless function
Dne ponedeljek, 29. avgust 2022 ob 15:11:51 CEST je Maxime Ripard napisal(a): > The drm_connector_to_sun4i_tv() function isn't used anywhere in the driver, > so let's remove it. > > Signed-off-by: Maxime Ripard Acked-by: Jernej Skrabec Best regards, Jernej
Re: [Intel-gfx] [PATCH v2 32/41] drm/vc4: vec: Convert to the new TV mode property
Hi Maxime,
W dniu 08.09.2022 o 13:23, Maxime Ripard pisze:
> Hi Noralf,
>
> On Tue, Aug 30, 2022 at 09:01:08PM +0200, Noralf Trønnes wrote:
>>> +static const struct drm_prop_enum_list tv_mode_names[] = {
>>
>> Maybe call it legacy_tv_mode_enums?
>>
>>>
>>> + { VC4_VEC_TV_MODE_NTSC, "NTSC", },
>>>
>>> + { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", },
>>>
>>> + { VC4_VEC_TV_MODE_PAL, "PAL", },
>>>
>>> + { VC4_VEC_TV_MODE_PAL_M, "PAL-M", },
>>
>> If you use DRM_MODE_TV_MODE_* here you don't need to translate the value
>> using the switch statement in get/set property, you can use the value
>> directly to get/set tv.mode.
>
> I'm sorry, I'm not quite sure what you mean by that. If we expose the
> DRM_MODE_TV_MODE_* properties there, won't that change the values the
> userspace will need to use to set that property?
I'd just like to point out that if numerical values of these enums are your
concern, then you're (or perhaps I am ;) already breaking this by adding new
modes in patch 33/41 in this series.
And the values (and names!) added by that patch (33/41) don't match those
currently used by the downstream version
(https://github.com/raspberrypi/linux/blob/rpi-5.15.y/drivers/gpu/drm/vc4/vc4_vec.c).
If any userspace software is manipulating this property, it's most likely
targeting the downstream code. But since you're not aiming for consistency with
that, I was under the impression that compatibility isn't a concern.
Best regards,
Mateusz Kwiatkowski
Re: [Intel-gfx] [PATCH v6 17/57] dyndbg: validate class FOO by checking with module
On 9/4/22 17:40, Jim Cromie wrote:
> Add module-to-class validation:
>
> #> echo class DRM_UT_KMS +p > /proc/dynamic_debug/control
>
> If a query has "class FOO", then ddebug_find_valid_class(), called
> from ddebug_change(), requires that FOO is known to module X,
> otherwize the query is skipped entirely for X. This protects each
> module's class-space, other than the default:31.
>
> The authors' choice of FOO is highly selective, giving isolation
> and/or coordinated sharing of FOOs. For example, only DRM modules
> should know and respond to DRM_UT_KMS.
>
> So this, combined with module's opt-in declaration of known classes,
> effectively privatizes the .class_id space for each module (or
> coordinated set of modules).
>
> Notes:
>
> For all "class FOO" queries, ddebug_find_valid_class() is called, it
> returns the map matching the query, and sets valid_class via an
> *outvar).
>
> If no "class FOO" is supplied, valid_class = _CLASS_DFLT. This
> insures that legacy queries do not trample on new class'd callsites,
> as they get added.
Hi Jim,
I'm wondering about the case where we have a callsite which is marked
as 'class foo', but the query string is done by say module and file, so:
# echo "module bar file foo.c +p" > /proc/dynamic_debug_control
With the proposed code, I think this ends up not enabling anything right?
Because valid class is set to _DPRINTK_CLASS_DFLT and then:
'dp->class_id != valid_class' is true?
This seems confusing to me as a user as this doesn't work like the
other queriesso maybe we should only do the
'dp->class_id != valid_class' check *if* query->class_string is set,
see below.
>
> Also add a new column to control-file output, displaying non-default
> class-name (when found) or the "unknown _id:", if it has not been
> (correctly) declared with one of the declarator macros.
>
> Signed-off-by: Jim Cromie
> ---
> lib/dynamic_debug.c | 76 -
> 1 file changed, 68 insertions(+), 8 deletions(-)
>
> diff --git a/lib/dynamic_debug.c b/lib/dynamic_debug.c
> index b71efd0b491d..db96ded78c3f 100644
> --- a/lib/dynamic_debug.c
> +++ b/lib/dynamic_debug.c
> @@ -56,6 +56,7 @@ struct ddebug_query {
> const char *module;
> const char *function;
> const char *format;
> + const char *class_string;
> unsigned int first_lineno, last_lineno;
> };
>
> @@ -136,15 +137,33 @@ static void vpr_info_dq(const struct ddebug_query
> *query, const char *msg)
> fmtlen--;
> }
>
> - v3pr_info("%s: func=\"%s\" file=\"%s\" module=\"%s\" format=\"%.*s\"
> lineno=%u-%u\n",
> - msg,
> - query->function ?: "",
> - query->filename ?: "",
> - query->module ?: "",
> - fmtlen, query->format ?: "",
> - query->first_lineno, query->last_lineno);
> + v3pr_info("%s: func=\"%s\" file=\"%s\" module=\"%s\" format=\"%.*s\"
> lineno=%u-%u class=%s\n",
> + msg,
> + query->function ?: "",
> + query->filename ?: "",
> + query->module ?: "",
> + fmtlen, query->format ?: "",
> + query->first_lineno, query->last_lineno, query->class_string);
> }
>
> +static struct ddebug_class_map *ddebug_find_valid_class(struct ddebug_table
> const *dt,
> + const char
> *class_string, int *class_id)
> +{
> + struct ddebug_class_map *map;
> + int idx;
> +
> + list_for_each_entry(map, &dt->maps, link) {
> + idx = match_string(map->class_names, map->length, class_string);
> + if (idx >= 0) {
> + *class_id = idx + map->base;
> + return map;
> + }
> + }
> + *class_id = -ENOENT;
> + return NULL;
> +}
> +
> +#define __outvar /* filled by callee */
> /*
> * Search the tables for _ddebug's which match the given `query' and
> * apply the `flags' and `mask' to them. Returns number of matching
> @@ -159,6 +178,8 @@ static int ddebug_change(const struct ddebug_query *query,
> unsigned int newflags;
> unsigned int nfound = 0;
> struct flagsbuf fbuf, nbuf;
> + struct ddebug_class_map *map = NULL;
> + int __outvar valid_class;
>
> /* search for matching ddebugs */
> mutex_lock(&ddebug_lock);
> @@ -169,9 +190,22 @@ static int ddebug_change(const struct ddebug_query
> *query,
> !match_wildcard(query->module, dt->mod_name))
> continue;
>
> + if (query->class_string) {
> + map = ddebug_find_valid_class(dt, query->class_string,
> &valid_class);
> + if (!map)
> + continue;
So remove the else here.
> + } else {
> + /* constrain query, do not touch class'd callsites */
> + valid_class = _DPRINTK_CLA
