Re: [Intel-gfx] v5.19 & v6.0 stable backport request

[Greg Kroah-Hartman]

On Tue, Oct 18, 2022 at 02:02:08PM +0300, Jani Nikula wrote:
> 
> Hello stable team, please backport these two commits to stable kernels
> v5.19 and v6.0:
> 
> 4e78d6023c15 ("drm/i915/bios: Validate fp_timing terminator presence")

Does not apply to 5.19.y, can you provide a working backport?

> d3a7051841f0 ("drm/i915/bios: Use hardcoded fp_timing size for generating LFP 
> data pointers")

Queued up to both trees now, thanks.

greg k-h

[Intel-gfx] ✓ Fi.CI.BAT: success for Add hwmon support for dgfx selftests

[Patchwork]

== Series Details ==

Series: Add hwmon support for dgfx selftests
URL   : https://patchwork.freedesktop.org/series/109850/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12258 -> Patchwork_109850v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109850v1/index.html

Participating hosts (39 -> 39)
--

  Additional (1): fi-hsw-4770 
  Missing(1): bat-adlm-1 

Known issues


  Here are the changes found in Patchwork_109850v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109850v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#3012])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109850v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rpm@module-reload:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][3] ([i915#7221])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109850v1/fi-hsw-4770/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@sanitycheck:
- fi-apl-guc: NOTRUN -> [INCOMPLETE][4] ([i915#7222])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109850v1/fi-apl-guc/igt@i915_selftest@l...@sanitycheck.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109850v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109850v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1072]) +3 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109850v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#4312] / 
[i915#5594])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109850v1/fi-hsw-4770/igt@run...@aborted.html
- fi-apl-guc: NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#4312])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109850v1/fi-apl-guc/igt@run...@aborted.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [INCOMPLETE][10] ([i915#7073]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109850v1/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html

  * igt@debugfs_test@read_all_entries:
- {fi-tgl-mst}:   [DMESG-WARN][12] ([i915#6434]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/fi-tgl-mst/igt@debugfs_test@read_all_entries.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109850v1/fi-tgl-mst/igt@debugfs_test@read_all_entries.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
  [i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
  [i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
  [i915#7073]: https://gitlab.freedesktop.org/drm/intel/issues/7073
  [i915#7221]: https://gitlab.freedesktop.org/drm/intel/issues/7221
  [i915#7222]: https://gitlab.freedesktop.org/drm/intel/issues/7222


Build changes
-

  * Linux: CI_DRM_12258 -> Patchwork_109850v1

  CI-20190529: 20190529
  CI_DRM_12258: 46aaaf749a4300985a8415b327a96a2bffb63018 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7019: fdbafce2b74e84739bb1d81223ae6f01fb442980 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_109850v1: 46aaaf749a4300985a8415b327a96a2bffb63018 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

e4c51f4587d3 drm/i915/selftests: Add hwmon support in libpower for dgfx
4d2c780d73b

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add hwmon support for dgfx selftests

[Patchwork]

== Series Details ==

Series: Add hwmon support for dgfx selftests
URL   : https://patchwork.freedesktop.org/series/109850/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced 
symbol 'old'
+./include/asm-g

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add hwmon support for dgfx selftests

[Patchwork]

== Series Details ==

Series: Add hwmon support for dgfx selftests
URL   : https://patchwork.freedesktop.org/series/109850/
State : warning

== Summary ==

Error: dim checkpatch failed
9cbba6841433 drm/i915/selftests: Rename librapl library to libpower
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
-:119: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#119: 
rename from drivers/gpu/drm/i915/selftests/librapl.c

total: 0 errors, 1 warnings, 0 checks, 126 lines checked
560c8fdc95e8 drm/i915/hwmon: Add helper function to obtain energy values
b3bf39f91aea drm/i915/selftests: Add hwmon support in libpower for dgfx

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/guc: Add GuC-Error-Capture-Init coverage of new engine types (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Add GuC-Error-Capture-Init coverage of new engine types 
(rev2)
URL   : https://patchwork.freedesktop.org/series/109737/
State : failure

== Summary ==

Error: make failed
  CALLscripts/checksyscalls.sh
  DESCEND objtool
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c: In function ‘__stringify_type’:
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:436:2: error: label at end of 
compound statement
  default:
  ^~~
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c: In function 
‘__stringify_engclass’:
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:456:2: error: label at end of 
compound statement
  default:
  ^~~
scripts/Makefile.build:250: recipe for target 
'drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o' failed
make[5]: *** [drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o] Error 1
scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm/i915' failed
make[4]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm' failed
make[3]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:500: recipe for target 'drivers/gpu' failed
make[2]: *** [drivers/gpu] Error 2
scripts/Makefile.build:500: recipe for target 'drivers' failed
make[1]: *** [drivers] Error 2
Makefile:1992: recipe for target '.' failed
make: *** [.] Error 2

[Intel-gfx] ✓ Fi.CI.BAT: success for i915: CAGF and RC6 changes for MTL (rev6)

[Patchwork]

== Series Details ==

Series: i915: CAGF and RC6 changes for MTL (rev6)
URL   : https://patchwork.freedesktop.org/series/108156/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12258 -> Patchwork_108156v6


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/index.html

Participating hosts (39 -> 39)
--

  Additional (1): fi-hsw-4770 
  Missing(1): fi-adl-ddr5 

Known issues


  Here are the changes found in Patchwork_108156v6 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[PASS][1] -> [FAIL][2] ([i915#7229])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@gem_tiled_blits@basic:
- fi-pnv-d510:[PASS][4] -> [SKIP][5] ([fdo#109271])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-pnv-d510/igt@gem_tiled_bl...@basic.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3012])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rpm@module-reload:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][7] ([i915#7221])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-hsw-4770/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@sanitycheck:
- fi-apl-guc: NOTRUN -> [INCOMPLETE][8] ([i915#7222])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-apl-guc/igt@i915_selftest@l...@sanitycheck.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271]) +9 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#1072]) +3 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#4312] / 
[i915#5594])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-hsw-4770/igt@run...@aborted.html
- fi-apl-guc: NOTRUN -> [FAIL][13] ([fdo#109271] / [i915#4312])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-apl-guc/igt@run...@aborted.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [INCOMPLETE][14] ([i915#7073]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html

  
 Warnings 

  * igt@i915_suspend@basic-s3-without-i915:
- fi-bdw-gvtdvm:  [FAIL][16] ([fdo#103375]) -> [INCOMPLETE][17] 
([i915#146])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/fi-bdw-gvtdvm/igt@i915_susp...@basic-s3-without-i915.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-bdw-gvtdvm/igt@i915_susp...@basic-s3-without-i915.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
  [i915#5594]: https://gitlab.

[Intel-gfx] [PATCH 3/3] drm/i915/selftests: Add hwmon support in libpower for dgfx

[Riana Tauro]

From: Tilak Tangudu 

hwmon provides an interface to read energy values for discrete graphics.
add hwmon support to the existing libpower library so that it can verify
power consumption values in different selftests.

Changed prototype of libpower_get_energy_uJ

Signed-off-by: Tilak Tangudu 
Signed-off-by: Riana Tauro 
---
 drivers/gpu/drm/i915/gt/selftest_rc6.c|  8 +++---
 drivers/gpu/drm/i915/gt/selftest_rps.c| 22 +++
 drivers/gpu/drm/i915/gt/selftest_slpc.c   |  2 +-
 drivers/gpu/drm/i915/selftests/libpower.c | 33 ---
 drivers/gpu/drm/i915/selftests/libpower.h |  8 +++---
 5 files changed, 38 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c 
b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index aacff50dfa89..585915f7c988 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -61,9 +61,9 @@ int live_rc6_manual(void *arg)
res[0] = rc6_residency(rc6);
 
dt = ktime_get();
-   rc0_power = libpower_get_energy_uJ();
+   rc0_power = libpower_get_energy_uJ(gt->i915);
msleep(250);
-   rc0_power = libpower_get_energy_uJ() - rc0_power;
+   rc0_power = libpower_get_energy_uJ(gt->i915) - rc0_power;
dt = ktime_sub(ktime_get(), dt);
res[1] = rc6_residency(rc6);
if ((res[1] - res[0]) >> 10) {
@@ -89,9 +89,9 @@ int live_rc6_manual(void *arg)
res[0] = rc6_residency(rc6);
intel_uncore_forcewake_flush(rc6_to_uncore(rc6), FORCEWAKE_ALL);
dt = ktime_get();
-   rc6_power = libpower_get_energy_uJ();
+   rc6_power = libpower_get_energy_uJ(gt->i915);
msleep(100);
-   rc6_power = libpower_get_energy_uJ() - rc6_power;
+   rc6_power = libpower_get_energy_uJ(gt->i915) - rc6_power;
dt = ktime_sub(ktime_get(), dt);
res[1] = rc6_residency(rc6);
if (res[1] == res[0]) {
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c 
b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 3287698c655b..e88bd774a862 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -1094,38 +1094,38 @@ int live_rps_interrupt(void *arg)
return err;
 }
 
-static u64 __measure_power(int duration_ms)
+static u64 __measure_power(struct intel_gt *gt, int duration_ms)
 {
u64 dE, dt;
 
dt = ktime_get();
-   dE = libpower_get_energy_uJ();
+   dE = libpower_get_energy_uJ(gt->i915);
usleep_range(1000 * duration_ms, 2000 * duration_ms);
-   dE = libpower_get_energy_uJ() - dE;
+   dE = libpower_get_energy_uJ(gt->i915) - dE;
dt = ktime_get() - dt;
 
return div64_u64(1000 * 1000 * dE, dt);
 }
 
-static u64 measure_power(struct intel_rps *rps, int *freq)
+static u64 measure_power(struct intel_gt *gt, int *freq)
 {
u64 x[5];
int i;
 
for (i = 0; i < 5; i++)
-   x[i] = __measure_power(5);
+   x[i] = __measure_power(gt, 5);
 
-   *freq = (*freq + intel_rps_read_actual_frequency(rps)) / 2;
+   *freq = (*freq + intel_rps_read_actual_frequency(>->rps)) / 2;
 
/* A simple triangle filter for better result stability */
sort(x, 5, sizeof(*x), cmp_u64, NULL);
return div_u64(x[1] + 2 * x[2] + x[3], 4);
 }
 
-static u64 measure_power_at(struct intel_rps *rps, int *freq)
+static u64 measure_power_at(struct intel_gt *gt, int *freq)
 {
-   *freq = rps_set_check(rps, *freq);
-   return measure_power(rps, freq);
+   *freq = rps_set_check(>->rps, *freq);
+   return measure_power(gt, freq);
 }
 
 int live_rps_power(void *arg)
@@ -1191,10 +1191,10 @@ int live_rps_power(void *arg)
}
 
max.freq = rps->max_freq;
-   max.power = measure_power_at(rps, &max.freq);
+   max.power = measure_power_at(gt, &max.freq);
 
min.freq = rps->min_freq;
-   min.power = measure_power_at(rps, &min.freq);
+   min.power = measure_power_at(gt, &min.freq);
 
igt_spinner_end(&spin);
st_engine_heartbeat_enable(engine);
diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c 
b/drivers/gpu/drm/i915/gt/selftest_slpc.c
index 494e7a486b07..bca15cfad8a1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
@@ -70,7 +70,7 @@ static u64 measure_power_at_freq(struct intel_gt *gt, int 
*freq, u64 *power)
if (err)
return err;
*freq = intel_rps_read_actual_frequency(>->rps);
-   *power = measure_power(>->rps, freq);
+   *power = measure_power(gt, freq);
 
return err;
 }
diff --git a/drivers/gpu/drm/i915/selftests/libpower.c 
b/drivers/gpu/drm/i915/selftests/libpower.c
index c66e993c5f85..b0dfcdf0f20b 100644
--- a/drivers/gpu/drm/i915/selftests/libpower.c
+++ b/drivers/gpu/drm/i915/selftests/libpower.c
@@ -6,29 +6,30 @@
 #include 
 
 #include "i915_drv.h"
+#include "i915_hwmon.h"
 #inclu

[Intel-gfx] [PATCH 2/3] drm/i915/hwmon: Add helper function to obtain energy values

[Riana Tauro]

Add an interface to obtain hwmon energy values. This is used
by selftest to verify power consumption

Signed-off-by: Riana Tauro 
---
 drivers/gpu/drm/i915/i915_hwmon.c | 23 ---
 drivers/gpu/drm/i915/i915_hwmon.h |  1 +
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_hwmon.c 
b/drivers/gpu/drm/i915/i915_hwmon.c
index 9e9781493025..1eb85cd96171 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -138,7 +138,7 @@ hwm_field_scale_and_write(struct hwm_drvdata *ddat, 
i915_reg_t rgadr,
  * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before
  * energy1_input overflows. This at 1000 W is an overflow duration of 278 
years.
  */
-static void
+static int
 hwm_energy(struct hwm_drvdata *ddat, long *energy)
 {
struct intel_uncore *uncore = ddat->uncore;
@@ -153,6 +153,9 @@ hwm_energy(struct hwm_drvdata *ddat, long *energy)
else
rgaddr = hwmon->rg.energy_status_all;
 
+   if (!i915_mmio_reg_valid(rgaddr))
+   return -EOPNOTSUPP;
+
mutex_lock(&hwmon->hwmon_lock);
 
with_intel_runtime_pm(uncore->rpm, wakeref)
@@ -167,6 +170,21 @@ hwm_energy(struct hwm_drvdata *ddat, long *energy)
*energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY,
  hwmon->scl_shift_energy);
mutex_unlock(&hwmon->hwmon_lock);
+
+   return 0;
+}
+
+/*
+ * i915_hwm_get_energy - obtains energy value
+ * Returns: 0 on success or a negative error code
+ */
+int
+i915_hwm_get_energy(struct drm_i915_private *i915, long *energy)
+{
+   struct i915_hwmon *hwmon = i915->hwmon;
+   struct hwm_drvdata *ddat = &hwmon->ddat;
+
+   return hwm_energy(ddat, energy);
 }
 
 static ssize_t
@@ -441,8 +459,7 @@ hwm_energy_read(struct hwm_drvdata *ddat, u32 attr, long 
*val)
 {
switch (attr) {
case hwmon_energy_input:
-   hwm_energy(ddat, val);
-   return 0;
+   return hwm_energy(ddat, val);
default:
return -EOPNOTSUPP;
}
diff --git a/drivers/gpu/drm/i915/i915_hwmon.h 
b/drivers/gpu/drm/i915/i915_hwmon.h
index 7ca9cf2c34c9..fa3b13568b37 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.h
+++ b/drivers/gpu/drm/i915/i915_hwmon.h
@@ -12,6 +12,7 @@ struct drm_i915_private;
 #if IS_REACHABLE(CONFIG_HWMON)
 void i915_hwmon_register(struct drm_i915_private *i915);
 void i915_hwmon_unregister(struct drm_i915_private *i915);
+int i915_hwm_get_energy(struct drm_i915_private *i915, long *energy);
 #else
 static inline void i915_hwmon_register(struct drm_i915_private *i915) { };
 static inline void i915_hwmon_unregister(struct drm_i915_private *i915) { };
-- 
2.25.1

[Intel-gfx] [PATCH 1/3] drm/i915/selftests: Rename librapl library to libpower

[Riana Tauro]

Rename functions in librapl library to libpower.
No functional changes.

Signed-off-by: Riana Tauro 
---
 drivers/gpu/drm/i915/Makefile   |  2 +-
 drivers/gpu/drm/i915/gt/selftest_rc6.c  | 12 ++--
 drivers/gpu/drm/i915/gt/selftest_rps.c  |  8 
 drivers/gpu/drm/i915/gt/selftest_slpc.c |  2 +-
 .../i915/selftests/{librapl.c => libpower.c}| 10 +-
 drivers/gpu/drm/i915/selftests/libpower.h   | 17 +
 drivers/gpu/drm/i915/selftests/librapl.h| 17 -
 7 files changed, 34 insertions(+), 34 deletions(-)
 rename drivers/gpu/drm/i915/selftests/{librapl.c => libpower.c} (69%)
 create mode 100644 drivers/gpu/drm/i915/selftests/libpower.h
 delete mode 100644 drivers/gpu/drm/i915/selftests/librapl.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2535593ab379..6bb291312c84 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -339,7 +339,7 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
selftests/igt_mmap.o \
selftests/igt_reset.o \
selftests/igt_spinner.o \
-   selftests/librapl.o
+   selftests/libpower.o
 
 # virtual gpu code
 i915-y += i915_vgpu.o
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c 
b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 8c70b7e12074..aacff50dfa89 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -11,7 +11,7 @@
 #include "selftest_rc6.h"
 
 #include "selftests/i915_random.h"
-#include "selftests/librapl.h"
+#include "selftests/libpower.h"
 
 static u64 rc6_residency(struct intel_rc6 *rc6)
 {
@@ -51,7 +51,7 @@ int live_rc6_manual(void *arg)
if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915))
return 0;
 
-   has_power = librapl_supported(gt->i915);
+   has_power = libpower_supported(gt->i915);
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
 
/* Force RC6 off for starters */
@@ -61,9 +61,9 @@ int live_rc6_manual(void *arg)
res[0] = rc6_residency(rc6);
 
dt = ktime_get();
-   rc0_power = librapl_energy_uJ();
+   rc0_power = libpower_get_energy_uJ();
msleep(250);
-   rc0_power = librapl_energy_uJ() - rc0_power;
+   rc0_power = libpower_get_energy_uJ() - rc0_power;
dt = ktime_sub(ktime_get(), dt);
res[1] = rc6_residency(rc6);
if ((res[1] - res[0]) >> 10) {
@@ -89,9 +89,9 @@ int live_rc6_manual(void *arg)
res[0] = rc6_residency(rc6);
intel_uncore_forcewake_flush(rc6_to_uncore(rc6), FORCEWAKE_ALL);
dt = ktime_get();
-   rc6_power = librapl_energy_uJ();
+   rc6_power = libpower_get_energy_uJ();
msleep(100);
-   rc6_power = librapl_energy_uJ() - rc6_power;
+   rc6_power = libpower_get_energy_uJ() - rc6_power;
dt = ktime_sub(ktime_get(), dt);
res[1] = rc6_residency(rc6);
if (res[1] == res[0]) {
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c 
b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 99a372486fb7..3287698c655b 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -19,7 +19,7 @@
 #include "selftest_rps.h"
 #include "selftests/igt_flush_test.h"
 #include "selftests/igt_spinner.h"
-#include "selftests/librapl.h"
+#include "selftests/libpower.h"
 
 /* Try to isolate the impact of cstates from determing frequency response */
 #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */
@@ -1099,9 +1099,9 @@ static u64 __measure_power(int duration_ms)
u64 dE, dt;
 
dt = ktime_get();
-   dE = librapl_energy_uJ();
+   dE = libpower_get_energy_uJ();
usleep_range(1000 * duration_ms, 2000 * duration_ms);
-   dE = librapl_energy_uJ() - dE;
+   dE = libpower_get_energy_uJ() - dE;
dt = ktime_get() - dt;
 
return div64_u64(1000 * 1000 * dE, dt);
@@ -1147,7 +1147,7 @@ int live_rps_power(void *arg)
if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
return 0;
 
-   if (!librapl_supported(gt->i915))
+   if (!libpower_supported(gt->i915))
return 0;
 
if (igt_spinner_init(&spin, gt))
diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c 
b/drivers/gpu/drm/i915/gt/selftest_slpc.c
index 4c6e9257e593..494e7a486b07 100644
--- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
@@ -161,7 +161,7 @@ static int slpc_power(struct intel_gt *gt, struct 
intel_engine_cs *engine)
 * actually saves power. Let's see if our RAPL measurement supports
 * that theory.
 */
-   if (!librapl_supported(gt->i915))
+   if (!libpower_supported(gt->i915))
return 0;
 
min.freq = slpc->min_freq;
diff --git a/drivers/gpu/drm/i915/selftests/librapl.c 
b/drivers/gpu/drm/i915/selftests/libpower.c
similarity index 69%
rename from drivers/gpu/drm/i915/selft

[Intel-gfx] [PATCH 0/3] Add hwmon support for dgfx selftests

[Riana Tauro]

Rename librapl library to libpower. Add hwmon support in libpower for
dgfx.

Riana Tauro (2):
  drm/i915/selftests: Rename librapl library to libpower
  drm/i915/hwmon: Add helper function to obtain energy values

Tilak Tangudu (1):
  drm/i915/selftests: Add hwmon support in libpower for dgfx

 drivers/gpu/drm/i915/Makefile |  2 +-
 drivers/gpu/drm/i915/gt/selftest_rc6.c| 12 
 drivers/gpu/drm/i915/gt/selftest_rps.c| 26 -
 drivers/gpu/drm/i915/gt/selftest_slpc.c   |  4 +--
 drivers/gpu/drm/i915/i915_hwmon.c | 23 +--
 drivers/gpu/drm/i915/i915_hwmon.h |  1 +
 drivers/gpu/drm/i915/selftests/libpower.c | 35 +++
 drivers/gpu/drm/i915/selftests/libpower.h | 19 
 drivers/gpu/drm/i915/selftests/librapl.c  | 34 --
 drivers/gpu/drm/i915/selftests/librapl.h  | 17 ---
 10 files changed, 97 insertions(+), 76 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/selftests/libpower.c
 create mode 100644 drivers/gpu/drm/i915/selftests/libpower.h
 delete mode 100644 drivers/gpu/drm/i915/selftests/librapl.c
 delete mode 100644 drivers/gpu/drm/i915/selftests/librapl.h

-- 
2.25.1

[Intel-gfx] [PATCH v2 2/2] drm/i915/guc: Add compute reglist for guc err capture

[Alan Previn]

We missed this at initial upstream because at that time
none of the GuC enabled platforms had a compute engine.
Add this now.

Signed-off-by: Alan Previn 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 47f74aa16ab5..bebb88ba712d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -169,6 +169,8 @@ static struct __guc_mmio_reg_descr_group default_lists[] = {
MAKE_REGLIST(default_global_regs, PF, GLOBAL, 0),
MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS),
MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, 
GUC_RENDER_CLASS),
+   MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, 
GUC_COMPUTE_CLASS),
+   MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, 
GUC_COMPUTE_CLASS),
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS),
MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS),
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS),
@@ -182,6 +184,8 @@ static const struct __guc_mmio_reg_descr_group 
xe_lpd_lists[] = {
MAKE_REGLIST(xe_lpd_global_regs, PF, GLOBAL, 0),
MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS),
MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, 
GUC_RENDER_CLASS),
+   MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS),
+   MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, 
GUC_COMPUTE_CLASS),
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS),
MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS),
MAKE_REGLIST(xe_lpd_vec_class_regs, PF, ENGINE_CLASS, 
GUC_VIDEOENHANCE_CLASS),
-- 
2.34.1

[Intel-gfx] [PATCH V2 0/2] drm/i915/guc: Add GuC-Error-Capture-Init coverage of new engine types

[Alan Previn]

After initial upstream merge of GuC error-capture feature, we eventually
decided to remove a lot of unnecessary warning messages when we couldn't
retrieve register lists for ADS-error-state-capture initialization. It was
a justified decision because the majority of that noise was being repeated
three times per GT reset and included list-types that are not supported
upstream. However after that change, we are not able to catch cases of
missing register lists for new engines that hadn't been added.

This series introduces new selective checks and warnings (such as skipping
if its a VF or if its an empty register list). This series also adds register
list for compute engine which is merely a duplicate of render class list.

Alan Previn (2):
  drm/i915/guc: Add error-capture init warnings when needed
  drm/i915/guc: Add compute reglist for guc err capture

 .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 80 ---
 1 file changed, 71 insertions(+), 9 deletions(-)


base-commit: b249abef9f86f788e6bacc657ae8eb7743948200
-- 
2.34.1

[Intel-gfx] [PATCH v2 1/2] drm/i915/guc: Add error-capture init warnings when needed

[Alan Previn]

If GuC is being used and we initialized GuC-error-capture,
we need to be warning if we don't provide an error-capture
register list in the firmware ADS, for valid GT engines.
A warning makes sense as this would impact debugability
without realizing why a reglist wasn't retrieved and reported
by GuC.

However, depending on the platform, we might have certain
engines that have a register list for engine instance error state
but not for engine class. Thus, add a check only to warn if the
register list was non existent vs an empty list (use the
empty lists to skip the warning).

NOTE: if a future platform were to introduce new registers
in place of what was an empty list on existing / legacy hardware
engines no warning is provided as the empty list is meant
to be used intentionally. As an example, if a future hardware
were to add blitter engine-class-registers (new) on top
of the legacy blitter engine-instance-register (HEAD, TAIL, etc.),
no warning is generated.

Signed-off-by: Alan Previn 
---
 .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 76 ---
 1 file changed, 67 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index d5c03e7a7843..47f74aa16ab5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -419,6 +419,42 @@ guc_capture_get_device_reglist(struct intel_guc *guc)
return default_lists;
 }
 
+static const char *
+__stringify_type(u32 type)
+{
+   switch (type) {
+   case GUC_CAPTURE_LIST_TYPE_GLOBAL:
+   return "Global";
+   case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS:
+   return "Class";
+   case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE:
+   return "Instance";
+   default:
+   }
+
+   return "unknown";
+}
+
+static const char *
+__stringify_engclass(u32 class)
+{
+   switch (class) {
+   case GUC_RENDER_CLASS:
+   return "Render";
+   case GUC_VIDEO_CLASS:
+   return "Video";
+   case GUC_VIDEOENHANCE_CLASS:
+   return "VideoEnhance";
+   case GUC_BLITTER_CLASS:
+   return "Blitter";
+   case GUC_COMPUTE_CLASS:
+   return "Compute";
+   default:
+   }
+
+   return "unknown";
+}
+
 static int
 guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
  struct guc_mmio_reg *ptr, u16 num_entries)
@@ -482,23 +518,38 @@ guc_cap_list_num_regs(struct intel_guc_state_capture *gc, 
u32 owner, u32 type, u
return num_regs;
 }
 
-int
-intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 
classid,
- size_t *size)
+static int
+guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 
classid,
+   size_t *size, bool is_purpose_est)
 {
struct intel_guc_state_capture *gc = guc->capture;
+   struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct __guc_capture_ads_cache *cache = 
&gc->ads_cache[owner][type][classid];
int num_regs;
 
-   if (!gc->reglists)
+   if (!gc->reglists) {
+   drm_warn(&i915->drm, "GuC-capture: No reglist on this 
device\n");
return -ENODEV;
+   }
 
if (cache->is_valid) {
*size = cache->size;
return cache->status;
}
 
+   if (!is_purpose_est && owner == GUC_CAPTURE_LIST_INDEX_PF &&
+   !guc_capture_get_one_list(gc->reglists, owner, type, classid)) {
+   if (type == GUC_CAPTURE_LIST_TYPE_GLOBAL)
+   drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist 
Global!\n");
+   else
+   drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist 
%s(%u):%s(%u)!\n",
+__stringify_type(type), type,
+__stringify_engclass(classid), classid);
+   return -ENODATA;
+   }
+
num_regs = guc_cap_list_num_regs(gc, owner, type, classid);
+   /* intentional empty lists can exist depending on hw config */
if (!num_regs)
return -ENODATA;
 
@@ -508,6 +559,13 @@ intel_guc_capture_getlistsize(struct intel_guc *guc, u32 
owner, u32 type, u32 cl
return 0;
 }
 
+int
+intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 
classid,
+ size_t *size)
+{
+   return guc_capture_getlistsize(guc, owner, type, classid, size, false);
+}
+
 static void guc_capture_create_prealloc_nodes(struct intel_guc *guc);
 
 int
@@ -627,15 +685,15 @@ guc_capture_output_min_size_est(struct intel_guc *guc)
worst_min_size += sizeof(struct 
guc_state_capture_group_header_t) +
 (3 * sizeof(struct 
guc_state_capture_header_t));
 
-   if (!intel_guc_capture_getlistsize(guc, 0

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: CAGF and RC6 changes for MTL (rev6)

[Patchwork]

== Series Details ==

Series: i915: CAGF and RC6 changes for MTL (rev6)
URL   : https://patchwork.freedesktop.org/series/108156/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Add error-capture init warnings when needed

[Teres Alexis, Alan Previn]

> > > Also commit message you can aim to wrap at 75 chars as per 
> > > submitting-patches.rst.
> > > 
> > > > +   return -ENODATA;
> > > 
> > > Is this a new exit condition or the thing would exit on the !num_regs 
> > > check below anyway? Just wondering if the series is only about logging 
> > > changes or there is more to it.
> > Its no different from previous behavior - and yes its about logging the 
> > missing reg lists for hw that needs it as we are
> > missing this for DG2 we we didn't notice (we did a previous revert to 
> > remove these warnings but that time the warnings
> > was too verbose - even complaining for the intentional empty lists and for 
> > VF cases that isnt supported).
> 
> Okay think I get it, thanks. If the "positive match" logging of empty 
> list is more future proof than "negative - don't log these" you will 
> know better.

NOTE: John and I had an offline conversation and we are aware that there will 
still be a case where
we can miss new-platform updates for guc-error-capture without being alerted by 
a warning:
Let's take the example of the empty blitter's engine-class-register-list. We 
dont have such a thing on
today's hardware.. we only have blitter's engine-register-list ... i.e. HEAD, 
TAIL etc. But if a future
platform were to introduce a blitter engine-class-register-list, we wont get a 
warning since the empty
list is there to prevent unnecessary warning for today's hardware. But we know 
this is better than
having to explain unnecessary warnings (which was the reason why a more verbose 
version of this code
was removed in the past).

I believe we are good with this solution here for now.

Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Change RC6 residency functions to accept register ID's

[Dixit, Ashutosh]

On Mon, 17 Oct 2022 01:27:35 -0700, Jani Nikula wrote:

Hi Jani,

Thanks for reviewing, great suggestions overall. I have taken care of most
of them in series version v6. Please see below.

> On Fri, 14 Oct 2022, Ashutosh Dixit  wrote:
> > @@ -811,9 +809,23 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, 
> > const i915_reg_t reg)
> > return mul_u64_u32_div(time_hw, mul, div);
> >  }
> >
> > -u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg)
> > +u64 intel_rc6_residency_us(struct intel_rc6 *rc6, const enum rc6_res_reg 
> > id)
> > +{
> > +   return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, id), 1000);
> > +}
> > +
> > +void intel_rc6_print_rc6_res(struct seq_file *m,
> > +const char *title,
> > +const enum rc6_res_reg id)
>
> intel_rc6_print_rc5_res is unnecessary duplication.
>
> intel_rc6_print_residency() maybe?

Done.

>
> >  {
> > -   return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000);
> > +   struct intel_gt *gt = m->private;
> > +   i915_reg_t reg = gt->rc6.res_reg[id];
> > +   intel_wakeref_t wakeref;
> > +
> > +   with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> > +   seq_printf(m, "%s %u (%llu us)\n", title,
> > +  intel_uncore_read(gt->uncore, reg),
> > +  intel_rc6_residency_us(>->rc6, id));
> >  }
> >
> >  #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h 
> > b/drivers/gpu/drm/i915/gt/intel_rc6.h
> > index b6fea71afc223..584d2d3b2ec3f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rc6.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.h
> > @@ -6,7 +6,7 @@
> >  #ifndef INTEL_RC6_H
> >  #define INTEL_RC6_H
> >
> > -#include "i915_reg_defs.h"
> > +#include "intel_rc6_types.h"
>
> You can forward declare enums as a gcc extension.
>
> enum rc6_res_reg;

Tried but was seeing compile errors so left as is.

> >  struct intel_engine_cs;
> >  struct intel_rc6;
> > @@ -21,7 +21,10 @@ void intel_rc6_sanitize(struct intel_rc6 *rc6);
> >  void intel_rc6_enable(struct intel_rc6 *rc6);
> >  void intel_rc6_disable(struct intel_rc6 *rc6);
> >
> > -u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, i915_reg_t reg);
> > -u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg);
> > +u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const enum rc6_res_reg 
> > id);
> > +u64 intel_rc6_residency_us(struct intel_rc6 *rc6, const enum rc6_res_reg 
> > id);
> > +void intel_rc6_print_rc6_res(struct seq_file *m,
> > +const char *title,
> > +const enum rc6_res_reg id);
>
> "const enum" makes no sense.

Removed. Probably const for pass-by-value function arguments never makes
sense, I had left the const thinking it would indicate that the function
won't modify that argument, but is probably not worth it so removed all
"const enum"s.

>
> >
> >  #endif /* INTEL_RC6_H */
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6_types.h 
> > b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
> > index e747492b2f46e..0386a3f6e4dc6 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rc6_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
> > @@ -13,7 +13,17 @@
> >
> >  struct drm_i915_gem_object;
> >
> > +enum rc6_res_reg {
> > +   RC6_RES_REG_RC6_LOCKED,
> > +   RC6_RES_REG_RC6,
> > +   RC6_RES_REG_RC6p,
> > +   RC6_RES_REG_RC6pp
> > +};
>
> Naming: intel_rc6_* for all.

Done.

> I think you need to take the abstraction further away from
> registers. You don't need the *register* part here for anything. Stop
> thinking in terms of registers in the interface.
>
> The callers care about things like "RC6+ residency since boot", and the
> callers don't care about where or how this information originates
> from. They just want the info, and the register is an implementation
> detail hidden behind the interface.
>
> I.e. use the enum to identify the data you want, not which register it
> comes from.

Done, please take a look at the new patch.

>
> > +
> > +#define VLV_RC6_RES_REG_MEDIA_RC6 RC6_RES_REG_RC6p
>
> Please handle this in the enum.

Done.

>
> > +
> >  struct intel_rc6 {
> > +   i915_reg_t res_reg[4];
>
> Maybe the id enum should have _MAX as last value, used for size here.

Done.

Thanks.
--
Ashutosh


>
> > u64 prev_hw_residency[4];
> > u64 cur_residency[4];
> >
> > diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c 
> > b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> > index 8c70b7e120749..a236e3f8f3183 100644
> > --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> > +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> > @@ -19,11 +19,11 @@ static u64 rc6_residency(struct intel_rc6 *rc6)
> >
> > /* XXX VLV_GT_MEDIA_RC6? */
> >
> > -   result = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6);
> > +   result = intel_rc6_residency_ns(rc6, RC6_RES_REG_RC6);
> > if (HAS_RC6p(rc6_to_i915(rc6)))
> > -   result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6p);
> > +   result += intel_rc6_residenc

[Intel-gfx] [PATCH 4/4] drm/i915/mtl: C6 residency and C state type for MTL SAMedia

[Ashutosh Dixit]

From: Badal Nilawar 

Add support for C6 residency and C state type for MTL SAMedia. Also add
mtl_drpc.

v2: Fixed review comments (Ashutosh)
v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R)
Remove MTL_CC_SHIFT (Ashutosh)
Adapt to RC6 residency register code refactor (Jani N)
v4: Move MTL branch to top in drpc_show

Signed-off-by: Ashutosh Dixit 
Signed-off-by: Badal Nilawar 
---
 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 60 ++-
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   |  5 ++
 drivers/gpu/drm/i915/gt/intel_rc6.c   | 17 --
 3 files changed, 77 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c 
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 235d593cfaeba..c88d8ec62b692 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -256,6 +256,62 @@ static int ilk_drpc(struct seq_file *m)
return 0;
 }
 
+static int mtl_drpc(struct seq_file *m)
+{
+   struct intel_gt *gt = m->private;
+   struct intel_uncore *uncore = gt->uncore;
+   u32 gt_core_status, rcctl1, global_forcewake;
+   u32 mtl_powergate_enable = 0, mtl_powergate_status = 0;
+
+   gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
+
+   global_forcewake = intel_uncore_read(uncore, FORCEWAKE_GT_GEN9);
+
+   rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
+   mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
+   mtl_powergate_status = intel_uncore_read(uncore,
+GEN9_PWRGT_DOMAIN_STATUS);
+
+   seq_printf(m, "RC6 Enabled: %s\n",
+  str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
+   if (gt->type == GT_MEDIA) {
+   seq_printf(m, "Media Well Gating Enabled: %s\n",
+  str_yes_no(mtl_powergate_enable & 
GEN9_MEDIA_PG_ENABLE));
+   } else {
+   seq_printf(m, "Render Well Gating Enabled: %s\n",
+  str_yes_no(mtl_powergate_enable & 
GEN9_RENDER_PG_ENABLE));
+   }
+
+   seq_puts(m, "Current RC state: ");
+   switch (REG_FIELD_GET(MTL_CC_MASK, gt_core_status)) {
+   case MTL_CC0:
+   seq_puts(m, "on\n");
+   break;
+   case MTL_CC6:
+   seq_puts(m, "RC6\n");
+   break;
+   default:
+   seq_puts(m, "Unknown\n");
+   break;
+   }
+
+   if (gt->type == GT_MEDIA)
+   seq_printf(m, "Media Power Well: %s\n",
+  (mtl_powergate_status &
+   GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
+   else
+   seq_printf(m, "Render Power Well: %s\n",
+  (mtl_powergate_status &
+   GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
+
+   /* Works for both render and media gt's */
+   intel_rc6_print_residency(m, "RC6 residency since boot:", 
INTEL_RC6_RES_RC6);
+
+   seq_printf(m, "Global Forcewake Requests: 0x%x\n", global_forcewake);
+
+   return fw_domains_show(m, NULL);
+}
+
 static int drpc_show(struct seq_file *m, void *unused)
 {
struct intel_gt *gt = m->private;
@@ -264,7 +320,9 @@ static int drpc_show(struct seq_file *m, void *unused)
int err = -ENODEV;
 
with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
-   if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+   if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+   err = mtl_drpc(m);
+   else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
err = vlv_drpc(m);
else if (GRAPHICS_VER(i915) >= 6)
err = gen6_drpc(m);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index b4b1b54ad738f..9f168867eb8ae 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -24,6 +24,9 @@
 /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
 #define MTL_MIRROR_TARGET_WP1  _MMIO(0xc60)
 #define   MTL_CAGF_MASKREG_GENMASK(8, 0)
+#define   MTL_CC0  0x0
+#define   MTL_CC6  0x3
+#define   MTL_CC_MASK  REG_GENMASK(12, 9)
 
 /* RPM unit config (Gen8+) */
 #define RPM_CONFIG0_MMIO(0xd00)
@@ -1516,6 +1519,8 @@
 #define FORCEWAKE_MEDIA_VLV_MMIO(0x1300b8)
 #define FORCEWAKE_ACK_MEDIA_VLV_MMIO(0x1300bc)
 
+#define MTL_MEDIA_MC6  _MMIO(0x138048)
+
 #define GEN6_GT_THREAD_STATUS_REG  _MMIO(0x13805c)
 #define   GEN6_GT_THREAD_STATUS_CORE_MASK  0x7
 
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c 
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 6db4e

[Intel-gfx] [PATCH 0/4] i915: CAGF and RC6 changes for MTL

[Ashutosh Dixit]

This series includes the code changes to get CAGF, RC State and C6
Residency of MTL.

v3: Included "Use GEN12 RPSTAT register" patch

v4:
  - Rebased
  - Dropped "Use GEN12 RPSTAT register" patch from this series
going to send separate series for it

v5:
- Included "drm/i915/gt: Change RC6 residency functions to accept register
  ID's" based on code review feedback

v6:
- Addressed Jani N's review comments on "drm/i915/gt: Change RC6 residency
  functions to accept register ID's"
- Minor changes to other patches, please see individual patches for changelogs

Ashutosh Dixit (1):
  drm/i915/gt: Use RC6 residency types as arguments to residency
functions

Badal Nilawar (2):
  drm/i915/mtl: Modify CAGF functions for MTL
  drm/i915/mtl: C6 residency and C state type for MTL SAMedia

Don Hiatt (1):
  drm/i915: Use GEN12_RPSTAT register for GT freq

 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 87 ++-
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 11 +++
 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c   | 12 +--
 drivers/gpu/drm/i915/gt/intel_rc6.c   | 64 +-
 drivers/gpu/drm/i915/gt/intel_rc6.h   |  8 +-
 drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 +++-
 drivers/gpu/drm/i915/gt/intel_rps.c   | 40 -
 drivers/gpu/drm/i915/gt/intel_rps.h   |  2 +
 drivers/gpu/drm/i915/gt/selftest_rc6.c|  6 +-
 drivers/gpu/drm/i915/i915_pmu.c   |  9 +-
 10 files changed, 188 insertions(+), 66 deletions(-)

-- 
2.38.0

[Intel-gfx] [PATCH 1/4] drm/i915: Use GEN12_RPSTAT register for GT freq

[Ashutosh Dixit]

From: Don Hiatt 

On GEN12+ use GEN12_RPSTAT register to get actual resolved GT
freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if
GT is in RC6.

v2:
  - Fixed review comments(Ashutosh)
  - Added function intel_rps_read_rpstat_fw to read RPSTAT without
forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko)
v3:
  - Updated commit title and message for more clarity (Ashutosh)
  - Replaced intel_rps_read_rpstat with direct read to GEN12_RPSTAT1 in
read_cagf (Ashutosh)

Cc: Don Hiatt 
Cc: Andi Shyti 
Signed-off-by: Don Hiatt 
Signed-off-by: Badal Nilawar 
Signed-off-by: Ashutosh Dixit 
Reviewed-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h |  2 ++
 drivers/gpu/drm/i915/gt/intel_rps.c | 32 +
 drivers/gpu/drm/i915/gt/intel_rps.h |  2 ++
 drivers/gpu/drm/i915/i915_pmu.c |  3 +--
 4 files changed, 33 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 36d95b79022c0..a7a0129d0e3fc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1543,6 +1543,8 @@
 
 #define GEN12_RPSTAT1  _MMIO(0x1381b4)
 #define   GEN12_VOLTAGE_MASK   REG_GENMASK(10, 0)
+#define   GEN12_CAGF_SHIFT 11
+#define   GEN12_CAGF_MASK  REG_GENMASK(19, 11)
 
 #define GEN11_GT_INTR_DW(x)_MMIO(0x190018 + ((x) * 4))
 #define   GEN11_CSME   (31)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index fc23c562d9b2a..df21258976d86 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2068,12 +2068,34 @@ void intel_rps_sanitize(struct intel_rps *rps)
rps_disable_interrupts(rps);
 }
 
+u32 intel_rps_read_rpstat_fw(struct intel_rps *rps)
+{
+   struct drm_i915_private *i915 = rps_to_i915(rps);
+   i915_reg_t rpstat;
+
+   rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1;
+
+   return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat);
+}
+
+u32 intel_rps_read_rpstat(struct intel_rps *rps)
+{
+   struct drm_i915_private *i915 = rps_to_i915(rps);
+   i915_reg_t rpstat;
+
+   rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1;
+
+   return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat);
+}
+
 u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
 {
struct drm_i915_private *i915 = rps_to_i915(rps);
u32 cagf;
 
-   if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+   if (GRAPHICS_VER(i915) >= 12)
+   cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT;
+   else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
cagf = (rpstat >> 8) & 0xff;
else if (GRAPHICS_VER(i915) >= 9)
cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
@@ -2094,7 +2116,9 @@ static u32 read_cagf(struct intel_rps *rps)
struct intel_uncore *uncore = rps_to_uncore(rps);
u32 freq;
 
-   if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+   if (GRAPHICS_VER(i915) >= 12) {
+   freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
+   } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
vlv_punit_get(i915);
freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
vlv_punit_put(i915);
@@ -2260,7 +2284,7 @@ static void rps_frequency_dump(struct intel_rps *rps, 
struct drm_printer *p)
rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
 
-   rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
+   rpstat = intel_rps_read_rpstat(rps);
rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & 
GEN6_CURICONT_MASK;
rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & 
GEN6_CURBSYTAVG_MASK;
rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & 
GEN6_CURBSYTAVG_MASK;
@@ -2395,7 +2419,7 @@ static void slpc_frequency_dump(struct intel_rps *rps, 
struct drm_printer *p)
drm_printf(p, "PM MASK=0x%08x\n", pm_mask);
drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
   rps->pm_intrmsk_mbz);
-   drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, 
GEN6_RPSTAT1));
+   drm_printf(p, "RPSTAT1: 0x%08x\n", intel_rps_read_rpstat(rps));
drm_printf(p, "RPNSWREQ: %dMHz\n", 
intel_rps_get_requested_frequency(rps));
drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
   intel_gpu_freq(rps, caps.min_freq));
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h 
b/drivers/gpu/drm/i915/gt/intel_rps.h
index 110300dfd4383..9e1cad9ba0e9c 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -48,6 +48,8 @@ u32 intel_rps_get_rp1_frequency(stru

[Intel-gfx] [PATCH 2/4] drm/i915/mtl: Modify CAGF functions for MTL

[Ashutosh Dixit]

From: Badal Nilawar 

Update CAGF functions for MTL to get actual resolved frequency of 3D and
SAMedia.

v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
Move MTL branches in cagf functions to top (MattR)
Fix commit message (Andi)
v3: Added comment about registers not needing forcewake for Gen12+ and
returning 0 freq in RC6

Bspec: 66300

Signed-off-by: Ashutosh Dixit 
Signed-off-by: Badal Nilawar 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h |  4 
 drivers/gpu/drm/i915/gt/intel_rps.c | 12 ++--
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index a7a0129d0e3fc..b4b1b54ad738f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -21,6 +21,10 @@
  */
 #define PERF_REG(offset)   _MMIO(offset)
 
+/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
+#define MTL_MIRROR_TARGET_WP1  _MMIO(0xc60)
+#define   MTL_CAGF_MASKREG_GENMASK(8, 0)
+
 /* RPM unit config (Gen8+) */
 #define RPM_CONFIG0_MMIO(0xd00)
 #define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT3
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index df21258976d86..5a743ae4dd11e 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
struct drm_i915_private *i915 = rps_to_i915(rps);
u32 cagf;
 
-   if (GRAPHICS_VER(i915) >= 12)
+   if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+   cagf = rpstat & MTL_CAGF_MASK;
+   else if (GRAPHICS_VER(i915) >= 12)
cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT;
else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
cagf = (rpstat >> 8) & 0xff;
@@ -2116,7 +2118,13 @@ static u32 read_cagf(struct intel_rps *rps)
struct intel_uncore *uncore = rps_to_uncore(rps);
u32 freq;
 
-   if (GRAPHICS_VER(i915) >= 12) {
+   /*
+* For Gen12+ reading freq from HW does not need a forcewake and
+* registers will return 0 freq when GT is in RC6
+*/
+   if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
+   freq = intel_uncore_read(rps_to_gt(rps)->uncore, 
MTL_MIRROR_TARGET_WP1);
+   } else if (GRAPHICS_VER(i915) >= 12) {
freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
vlv_punit_get(i915);
-- 
2.38.0

[Intel-gfx] [PATCH 3/4] drm/i915/gt: Use RC6 residency types as arguments to residency functions

[Ashutosh Dixit]

Previously RC6 residency functions directly accepted RC6 residency register
MMIO offsets (there are four RC6 residency registers). This worked but
required an assumption on the residency register layout so was not future
proof.

Therefore change RC6 residency functions to accept RC6 residency types
instead of register MMIO offsets. The knowledge of register offsets as well
as ID to offset mapping is now maintained solely in intel_rc6 and can be
tailored for different platforms and different register layouts as need
arises.

v2: Address review comments by Jani N
- Change residency functions to accept RC6 residency types instead of
  register ID's
- s/intel_rc6_print_rc5_res/intel_rc6_print_residency/
- Remove "const enum" in function arguments
- Naming: intel_rc6_* for enum
- Use INTEL_RC6_RES_MAX and other minor changes

Suggested-by: Rodrigo Vivi 
Suggested-by: Jani Nikula 
Reported-by: Jani Nikula 
Signed-off-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 27 +++--
 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c   | 12 ++--
 drivers/gpu/drm/i915/gt/intel_rc6.c   | 55 +++
 drivers/gpu/drm/i915/gt/intel_rc6.h   |  8 ++-
 drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 -
 drivers/gpu/drm/i915/gt/selftest_rc6.c|  6 +-
 drivers/gpu/drm/i915/i915_pmu.c   |  6 +-
 7 files changed, 70 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c 
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 40d0a3be42acf..235d593cfaeba 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -83,19 +83,6 @@ static int fw_domains_show(struct seq_file *m, void *data)
 }
 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains);
 
-static void print_rc6_res(struct seq_file *m,
- const char *title,
- const i915_reg_t reg)
-{
-   struct intel_gt *gt = m->private;
-   intel_wakeref_t wakeref;
-
-   with_intel_runtime_pm(gt->uncore->rpm, wakeref)
-   seq_printf(m, "%s %u (%llu us)\n", title,
-  intel_uncore_read(gt->uncore, reg),
-  intel_rc6_residency_us(>->rc6, reg));
-}
-
 static int vlv_drpc(struct seq_file *m)
 {
struct intel_gt *gt = m->private;
@@ -115,8 +102,8 @@ static int vlv_drpc(struct seq_file *m)
seq_printf(m, "Media Power Well: %s\n",
   (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
 
-   print_rc6_res(m, "Render RC6 residency since boot:", GEN6_GT_GFX_RC6);
-   print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
+   intel_rc6_print_residency(m, "Render RC6 residency since boot:", 
INTEL_RC6_RES_RC6);
+   intel_rc6_print_residency(m, "Media RC6 residency since boot:", 
INTEL_RC6_RES_VLV_MEDIA);
 
return fw_domains_show(m, NULL);
 }
@@ -192,11 +179,11 @@ static int gen6_drpc(struct seq_file *m)
}
 
/* Not exactly sure what this is */
-   print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
- GEN6_GT_GFX_RC6_LOCKED);
-   print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
-   print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
-   print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
+   intel_rc6_print_residency(m, "RC6 \"Locked to RPn\" residency since 
boot:",
+ INTEL_RC6_RES_RC6_LOCKED);
+   intel_rc6_print_residency(m, "RC6 residency since boot:", 
INTEL_RC6_RES_RC6);
+   intel_rc6_print_residency(m, "RC6+ residency since boot:", 
INTEL_RC6_RES_RC6p);
+   intel_rc6_print_residency(m, "RC6++ residency since boot:", 
INTEL_RC6_RES_RC6pp);
 
if (GRAPHICS_VER(i915) <= 7) {
seq_printf(m, "RC6   voltage: %dmV\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c 
b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 9041609523697..19a6e052c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -93,13 +93,13 @@ sysfs_gt_attribute_r_func(struct device *dev, struct 
device_attribute *attr,
sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
 
 #ifdef CONFIG_PM
-static u32 get_residency(struct intel_gt *gt, i915_reg_t reg)
+static u32 get_residency(struct intel_gt *gt, enum intel_rc6_res_type id)
 {
intel_wakeref_t wakeref;
u64 res = 0;
 
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
-   res = intel_rc6_residency_us(>->rc6, reg);
+   res = intel_rc6_residency_us(>->rc6, id);
 
return DIV_ROUND_CLOSEST_ULL(res, 1000);
 }
@@ -123,7 +123,7 @@ static ssize_t rc6_enable_show(struct device *dev,
 
 static u32 __rc6_residency_ms_show(struct intel_gt *gt)
 {
-   return get_residency(gt, GEN6_GT_GFX_RC6);
+   return get_r

Re: [Intel-gfx] [PATCH v4 15/17] drm/i915/vm_bind: Handle persistent vmas in execbuf3

[Niranjana Vishwanathapura]

On Tue, Oct 18, 2022 at 01:20:06PM -0700, Niranjana Vishwanathapura wrote:

On Tue, Oct 18, 2022 at 07:01:57PM +0100, Matthew Auld wrote:

On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:

Handle persistent (VM_BIND) mappings during the request submission
in the execbuf3 path.

v2: Ensure requests wait for bindings to complete.
v3: Remove short term pinning with PIN_VALIDATE flag.
   Individualize fences before adding to dma_resv obj.

Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
.../gpu/drm/i915/gem/i915_gem_execbuffer3.c   | 208 +-
1 file changed, 207 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
index a9b4cc44bf66..8120e4c6b7da 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
@@ -3,6 +3,7 @@
 * Copyright © 2022 Intel Corporation
 */
+#include 
#include 
#include 
@@ -19,6 +20,7 @@
#include "i915_gem_vm_bind.h"
#include "i915_trace.h"
+#define __EXEC3_HAS_PINBIT_ULL(33)
#define __EXEC3_ENGINE_PINNED   BIT_ULL(32)
#define __EXEC3_INTERNAL_FLAGS  (~0ull << 32)
@@ -42,7 +44,9 @@
 * execlist. Hence, no support for implicit sync.
 *
 * The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only
- * works with execbuf3 ioctl for submission.
+ * works with execbuf3 ioctl for submission. All BOs mapped on that VM (through
+ * VM_BIND call) at the time of execbuf3 call are deemed required for that
+ * submission.
 *
 * The execbuf3 ioctl directly specifies the batch addresses instead of as
 * object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not
@@ -58,6 +62,13 @@
 * So, a lot of code supporting execbuf2 ioctl, like relocations, VA evictions,
 * vma lookup table, implicit sync, vma active reference tracking etc., are not
 * applicable for execbuf3 ioctl.
+ *
+ * During each execbuf submission, request fence is added to all VM_BIND mapped
+ * objects with DMA_RESV_USAGE_BOOKKEEP. The DMA_RESV_USAGE_BOOKKEEP usage will
+ * prevent over sync (See enum dma_resv_usage). Note that DRM_I915_GEM_WAIT and
+ * DRM_I915_GEM_BUSY ioctls do not check for DMA_RESV_USAGE_BOOKKEEP usage and
+ * hence should not be used for end of batch check. Instead, the execbuf3
+ * timeline out fence should be used for end of batch check.
 */
/**
@@ -127,6 +138,23 @@ eb_find_vma(struct i915_address_space *vm, u64 addr)
return i915_gem_vm_bind_lookup_vma(vm, va);
}
+static void eb_scoop_unbound_vma_all(struct i915_address_space *vm)
+{
+   struct i915_vma *vma, *vn;
+
+   /**
+* Move all unbound vmas back into vm_bind_list so that they are
+* revalidated.
+*/
+   spin_lock(&vm->vm_rebind_lock);
+   list_for_each_entry_safe(vma, vn, &vm->vm_rebind_list, vm_rebind_link) {
+   list_del_init(&vma->vm_rebind_link);
+   if (!list_empty(&vma->vm_bind_link))
+   list_move_tail(&vma->vm_bind_link, &vm->vm_bind_list);
+   }
+   spin_unlock(&vm->vm_rebind_lock);
+}
+
static int eb_lookup_vma_all(struct i915_execbuffer *eb)
{
unsigned int i, current_batch = 0;
@@ -141,14 +169,108 @@ static int eb_lookup_vma_all(struct i915_execbuffer *eb)
++current_batch;
}
+   eb_scoop_unbound_vma_all(eb->context->vm);
+
+   return 0;
+}
+
+static int eb_lock_vma_all(struct i915_execbuffer *eb)
+{
+   struct i915_address_space *vm = eb->context->vm;
+   struct i915_vma *vma;
+   int err;
+
+   err = i915_gem_object_lock(eb->context->vm->root_obj, &eb->ww);
+   if (err)
+   return err;
+
+   list_for_each_entry(vma, &vm->non_priv_vm_bind_list,
+   non_priv_vm_bind_link) {
+   err = i915_gem_object_lock(vma->obj, &eb->ww);
+   if (err)
+   return err;
+   }
+
return 0;
}
+static void eb_release_persistent_vma_all(struct i915_execbuffer *eb)
+{
+   struct i915_address_space *vm = eb->context->vm;
+   struct i915_vma *vma, *vn;
+
+   lockdep_assert_held(&vm->vm_bind_lock);
+
+   if (!(eb->args->flags & __EXEC3_HAS_PIN))
+   return;
+
+   assert_object_held(vm->root_obj);
+
+   list_for_each_entry_safe(vma, vn, &vm->vm_bind_list, vm_bind_link)
+   if (i915_vma_verify_bind_complete(vma))
+   list_move_tail(&vma->vm_bind_link, &vm->vm_bound_list);
+
+   eb->args->flags &= ~__EXEC3_HAS_PIN;
+}
+
static void eb_release_vma_all(struct i915_execbuffer *eb)
{
+   eb_release_persistent_vma_all(eb);
eb_unpin_engine(eb);
}
+static int eb_reserve_fence_for_persistent_vma_all(struct i915_execbuffer *eb)
+{
+   struct i915_address_space *vm = eb->context->vm;
+   u64 num_fences = 1;
+   struct i915_vma *vma;
+   int ret;
+
+   /* Reserve enough slots to acc

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Add error-capture init warnings when needed

[Teres Alexis, Alan Previn]

Update: One additional change needed... after more testing i have come to 
realize that
intel_guc_capture_getlistsize is also being triggered before 
ADS-guc-error-capture
register-list population during initialization of the guc-error-capture module 
itself 
(intel_guc_capture_init). Its getting called as part of a check on the size of 
the
guc-log-buffer-error-capture-region to verify its big enough for the current 
platform
(assuming all engine masks + all steered-register permutations). So at that 
early
point, we do encounter the "OTHER ENGINE" showing up as a possible engine but in
fact none of the current hardware has that (yet). So to ensure this warning is 
not printed
during this early size estimation check:

i shall make "intel_guc_capture_getlistsize" a wrapper around a new function
"static int guc_capture_getlistsize(...[same-params]..., bool 
is_purpose_estimation)"
which contains all the original logic and uses new boolean for the additional 
check
on whether to print the warning or not.

current code:
if (!guc_capture_get_one_list(gc->reglists, owner, type, 
classid)) {
if (owner == GUC_CAPTURE_LIST_INDEX_PF && type == 
GUC_CAPTURE_LIST_TYPE_GLOBAL)
drm_warn(&i915->drm, "Missing GuC reglist 
Global\n");
... ...
...
new code: 
if (!is_purpose_estimation && owner == 
GUC_CAPTURE_LIST_INDEX_PF &&
!guc_capture_get_one_list(gc->reglists, owner, type, 
classid)) {
if (tpe == GUC_CAPTURE_LIST_TYPE_GLOBAL)
drm_warn(&i915->drm, "Missing GuC reglist 
Global\n");
...
...


On Tue, 2022-10-18 at 09:00 +0100, Tvrtko Ursulin wrote:
> > > > +   if (!guc_capture_get_one_list(gc->reglists, owner, type, 
> > > > classid)) {
> > > > +   if (owner == GUC_CAPTURE_LIST_INDEX_PF && type == 
> > > > GUC_CAPTURE_LIST_TYPE_GLOBAL)
> > > > +   drm_warn(&i915->drm, "GuC-capture: missing 
> > > > reglist type-Global\n");
> > > > +   if (owner == GUC_CAPTURE_LIST_INDEX_PF)
> > > 
> > > GUC_CAPTURE_LIST_INDEX_PF could be made once on the enclosing if 
> > > statement?
> > Sure - will do.
> > > 
> > > Btw what's with the PF and VF (cover letter) references while SRIOV does 
> > > not exists upstream?
> > To maintain a scalable code flow across both the ADS code and 
> > guc-error-capture code, we do have to skip over this enum
> > else we'll encounter lots of warnings about missing VF-reglist support 
> > (which we cant check for since we dont even have
> > support - i.e we dont even have a "is not supported" check) but the GuC 
> > firmware ADS buffer allocation includes an entry
> > for VFs so we have to skip over it. This is the cleanest way i can think of 
> > without impacting other code areas and also
> > while adding the ability to warn when its important.
> > > > +   drm_warn(&i915->drm, "GuC-capture: missing 
> > > > regiist type(%d)-%s : "
> > > 
> > > reglist
> > thanks - will fix
> > > 
> > > > +"%s(%d)-Engine\n", type, 
> > > > __stringify_type(type),
> > > > +__stringify_engclass(classid), 
> > > > classid);
> > > 
> > > One details to consider from Documentation/process/coding-style.rst
> > > """
> > > However, never break user-visible strings such as printk messages because 
> > > that breaks the ability to grep for them.
> > > """
> > > 
> > I totally agree with you but i cant find a way to keep totally grep-able 
> > way without creating a whole set of error
> > strings for the various list-types, list-owners and class-types. However i 
> > did ensure the first part of the message
> > is grep-able : "GuC-capture: missing reglist type". Do you an alternative 
> > proposal?
> 
> Yeah it is not very greppable being largely constructed at runtime, but 
> just don't break the string. IMO no gain to diverge from coding style here.
> 
> Or maybe with one level of indentation less as discussed, and maybe 
> remove "GuC-capture" if it can be implied (are there other reglists not 
> relating to error capture?), maybe it becomes short enough?
> 
> "Missing GuC reglist %s(%u):%s(%u)!", ...
> 
> ?
> 
Yes. this will work well - will use this.

> Type will never be unknown I suspect since it should always be added 
> very early during development. So type and engine suffixes may be 
> redundant? Or keep it verbose if that fits better with existing GuC 
> error capture logging, I don't know.
> 
above is good. :)
> > 
> > > Also commit message you can aim to wrap at 75 chars as per 
> > > submitting-patches.rst.
> > > 
> > > > +   return -ENODATA;
> > > 
> > > Is this a new exit condition or the thing would exit on the !num_regs 
> > > check below anyway? Just wondering if the series 

Re: [Intel-gfx] [PATCH v4 12/17] drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl

[Niranjana Vishwanathapura]

On Tue, Oct 18, 2022 at 06:30:58PM +0100, Matthew Auld wrote:

On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:

Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
works in vm_bind mode. The vm_bind mode only works with
this new execbuf3 ioctl.

The new execbuf3 ioctl will not have any list of objects to validate
bind as all required objects binding would have been requested by the
userspace before submitting the execbuf3.

Legacy features like relocations etc are not supported by execbuf3.

v2: Add more input validity checks.
v3: batch_address is a VA (not an array) if num_batches=1,
minor cleanup
v4: replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode()

Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/Makefile |   1 +
 .../gpu/drm/i915/gem/i915_gem_execbuffer3.c   | 580 ++
 drivers/gpu/drm/i915/gem/i915_gem_ioctls.h|   2 +
 drivers/gpu/drm/i915/i915_driver.c|   1 +
 include/uapi/drm/i915_drm.h   |  61 ++
 5 files changed, 645 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8d76bb888dc3..6a801684d569 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -150,6 +150,7 @@ gem-y += \
gem/i915_gem_domain.o \
gem/i915_gem_execbuffer_common.o \
gem/i915_gem_execbuffer.o \
+   gem/i915_gem_execbuffer3.o \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
gem/i915_gem_lmem.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
new file mode 100644
index ..a9b4cc44bf66
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
@@ -0,0 +1,580 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include 
+#include 
+
+#include 
+
+#include "gt/intel_context.h"
+#include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt.h"
+
+#include "i915_drv.h"
+#include "i915_gem_context.h"
+#include "i915_gem_execbuffer_common.h"
+#include "i915_gem_ioctls.h"
+#include "i915_gem_vm_bind.h"
+#include "i915_trace.h"
+
+#define __EXEC3_ENGINE_PINNED  BIT_ULL(32)
+#define __EXEC3_INTERNAL_FLAGS (~0ull << 32)
+
+/* Catch emission of unexpected errors for CI! */
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
+#undef EINVAL
+#define EINVAL ({ \
+   DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
+   22; \
+})
+#endif
+
+/**
+ * DOC: User command execution with execbuf3 ioctl
+ *
+ * A VM in VM_BIND mode will not support older execbuf mode of binding.
+ * The execbuf ioctl handling in VM_BIND mode differs significantly from the
+ * older execbuf2 ioctl (See struct drm_i915_gem_execbuffer2).
+ * Hence, a new execbuf3 ioctl has been added to support VM_BIND mode. (See
+ * struct drm_i915_gem_execbuffer3). The execbuf3 ioctl will not accept any
+ * execlist. Hence, no support for implicit sync.
+ *
+ * The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only
+ * works with execbuf3 ioctl for submission.
+ *
+ * The execbuf3 ioctl directly specifies the batch addresses instead of as
+ * object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not
+ * support many of the older features like in/out/submit fences, fence array,
+ * default gem context etc. (See struct drm_i915_gem_execbuffer3).
+ *
+ * In VM_BIND mode, VA allocation is completely managed by the user instead of
+ * the i915 driver. Hence all VA assignment, eviction are not applicable in
+ * VM_BIND mode. Also, for determining object activeness, VM_BIND mode will not
+ * be using the i915_vma active reference tracking. It will instead check the
+ * dma-resv object's fence list for that.
+ *
+ * So, a lot of code supporting execbuf2 ioctl, like relocations, VA evictions,
+ * vma lookup table, implicit sync, vma active reference tracking etc., are not
+ * applicable for execbuf3 ioctl.
+ */
+
+/**
+ * struct i915_execbuffer - execbuf struct for execbuf3
+ * @i915: reference to the i915 instance we run on
+ * @file: drm file reference
+ * args: execbuf3 ioctl structure
+ * @gt: reference to the gt instance ioctl submitted for
+ * @context: logical state for the request
+ * @gem_context: callers context
+ * @requests: requests to be build
+ * @composite_fence: used for excl fence in dma_resv objects when > 1 BB 
submitted
+ * @ww: i915_gem_ww_ctx instance
+ * @num_batches: number of batches submitted
+ * @batch_addresses: addresses corresponds to the submitted batches
+ * @batches: references to the i915_vmas corresponding to the batches
+ */
+struct i915_execbuffer {
+   struct drm_i915_private *i915;
+   struct drm_file *file;
+   struct drm_i915_gem_execbuffer3 *args;
+
+   struct intel_gt *gt;
+   struct intel_context *context;
+   struct i915_gem_

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part 
of pps_get_register() cleanup
URL   : https://patchwork.freedesktop.org/series/109820/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12254_full -> Patchwork_109820v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_109820v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gen9_exec_parse@allowed-single:
- shard-tglb: NOTRUN -> [SKIP][1] ([i915#2527] / [i915#2856])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/shard-tglb1/igt@gen9_exec_pa...@allowed-single.html

  * igt@i915_selftest@live@workarounds:
- shard-tglb: NOTRUN -> [INCOMPLETE][2] ([i915#7222])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/shard-tglb1/igt@i915_selftest@l...@workarounds.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][3] ([i915#6095])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/shard-tglb1/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][4] ([i915#3689] / [i915#3886])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/shard-tglb1/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_content_protection@content_type_change:
- shard-tglb: NOTRUN -> [SKIP][5] ([i915#7118])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/shard-tglb1/igt@kms_content_protection@content_type_change.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-tglb: NOTRUN -> [SKIP][6] ([i915#3555]) +1 similar issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/shard-tglb1/igt@kms_cursor_...@cursor-sliding-32x10.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-tglb: NOTRUN -> [SKIP][7] ([fdo#109274] / [fdo#111825] / 
[i915#3637])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/shard-tglb1/igt@kms_f...@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt:
- shard-tglb: NOTRUN -> [SKIP][8] ([fdo#109280] / [fdo#111825]) +2 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/shard-tglb1/igt@kms_frontbuffer_track...@fbcpsr-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-c-edp-1:
- shard-tglb: NOTRUN -> [SKIP][9] ([i915#5176]) +3 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/shard-tglb1/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0...@pipe-c-edp-1.html

  
 Possible fixes 

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][10] ([i915#2842]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12254/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][12] ([i915#2190]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12254/shard-tglb7/igt@gem_huc_c...@huc-copy.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/shard-tglb1/igt@gem_huc_c...@huc-copy.html

  
 Warnings 

  * igt@gem_pwrite@basic-exhaustion:
- shard-apl:  [INCOMPLETE][14] ([i915#7248]) -> [INCOMPLETE][15] 
([i915#7227] / [i915#7248])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12254/shard-apl7/igt@gem_pwr...@basic-exhaustion.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/shard-apl7/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_workarounds@suspend-resume:
- shard-apl:  [INCOMPLETE][16] ([i915#7231] / [i915#7259]) -> 
[INCOMPLETE][17] ([i915#7259])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12254/shard-apl3/igt@gem_workarou...@suspend-resume.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/shard-apl6/igt@gem_workarou...@suspend-resume.html

  
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i9

Re: [Intel-gfx] [PATCH v2 5/7] drm/i915/mtl: Handle wopcm per-GT and limit calculations.

[Matt Roper]

On Tue, Oct 18, 2022 at 05:44:38PM -0700, John Harrison wrote:
> On 10/12/2022 17:03, Daniele Ceraolo Spurio wrote:
> > From: Aravind Iddamsetty 
> > 
...
> > diff --git a/drivers/gpu/drm/i915/intel_wopcm.c 
> > b/drivers/gpu/drm/i915/gt/intel_wopcm.c
> > similarity index 86%
> > rename from drivers/gpu/drm/i915/intel_wopcm.c
> > rename to drivers/gpu/drm/i915/gt/intel_wopcm.c
> > index 322fb9eeb880..487fbbbdf3d6 100644
> > --- a/drivers/gpu/drm/i915/intel_wopcm.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_wopcm.c
> > @@ -43,6 +43,7 @@
> >   /* Default WOPCM size is 2MB from Gen11, 1MB on previous platforms */
> >   #define GEN11_WOPCM_SIZE  SZ_2M
> >   #define GEN9_WOPCM_SIZE   SZ_1M
> > +#define XELPM_SAMEDIA_WOPCM_SIZE   SZ_2M
> XELPM? Isn't it just XELP?

Xe_LP is the older TGL-ADL gfx IP name.  MTL's media IP is called
Xe_LPM+ (which we should label as XELPMP in code, so it looks like the
final "P" is missing here).


Matt

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v4 09/17] drm/i915/vm_bind: Add out fence support

[Niranjana Vishwanathapura]

On Tue, Oct 18, 2022 at 04:28:07PM +0100, Matthew Auld wrote:

On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:

Add support for handling out fence for vm_bind call.

v2: Reset vma->vm_bind_fence.syncobj to NULL at the end
of vm_bind call.
v3: Remove vm_unbind out fence uapi which is not supported yet.

Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h   |  4 +
 .../drm/i915/gem/i915_gem_vm_bind_object.c| 82 +++
 drivers/gpu/drm/i915/i915_vma.c   |  7 +-
 drivers/gpu/drm/i915/i915_vma_types.h |  7 ++
 include/uapi/drm/i915_drm.h   | 49 ++-
 5 files changed, 146 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
index 36262a6357b5..b70e900e35ab 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
@@ -8,6 +8,7 @@
 #include 
+struct dma_fence;
 struct drm_device;
 struct drm_file;
 struct i915_address_space;
@@ -23,4 +24,7 @@ int i915_gem_vm_unbind_ioctl(struct drm_device *dev, void 
*data,
 void i915_gem_vm_unbind_all(struct i915_address_space *vm);
+void i915_vm_bind_signal_fence(struct i915_vma *vma,
+  struct dma_fence * const fence);
+
 #endif /* __I915_GEM_VM_BIND_H */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
index 3ea3cb3ed97e..63889ba00183 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
@@ -7,6 +7,8 @@
 #include 
+#include 
+
 #include "gem/i915_gem_context.h"
 #include "gem/i915_gem_vm_bind.h"
@@ -100,6 +102,76 @@ static void i915_gem_vm_bind_remove(struct i915_vma *vma, 
bool release_obj)
i915_gem_object_put(vma->obj);
 }
+static int i915_vm_bind_add_fence(struct drm_file *file, struct i915_vma *vma,
+ u32 handle, u64 point)
+{
+   struct drm_syncobj *syncobj;
+
+   syncobj = drm_syncobj_find(file, handle);
+   if (!syncobj) {
+   DRM_DEBUG("Invalid syncobj handle provided\n");
+   return -ENOENT;
+   }
+
+   /*
+* For timeline syncobjs we need to preallocate chains for
+* later signaling.
+*/
+   if (point) {
+   vma->vm_bind_fence.chain_fence = dma_fence_chain_alloc();
+   if (!vma->vm_bind_fence.chain_fence) {
+   drm_syncobj_put(syncobj);
+   return -ENOMEM;
+   }
+   } else {
+   vma->vm_bind_fence.chain_fence = NULL;
+   }
+   vma->vm_bind_fence.syncobj = syncobj;
+   vma->vm_bind_fence.value = point;
+
+   return 0;
+}
+
+static void i915_vm_bind_put_fence(struct i915_vma *vma)
+{
+   if (!vma->vm_bind_fence.syncobj)
+   return;
+
+   drm_syncobj_put(vma->vm_bind_fence.syncobj);
+   dma_fence_chain_free(vma->vm_bind_fence.chain_fence);
+   vma->vm_bind_fence.syncobj = NULL;
+}
+
+/**
+ * i915_vm_bind_signal_fence() - Add fence to vm_bind syncobj
+ * @vma: vma mapping requiring signaling
+ * @fence: fence to be added
+ *
+ * Associate specified @fence with the @vma's syncobj to be
+ * signaled after the @fence work completes.
+ */
+void i915_vm_bind_signal_fence(struct i915_vma *vma,
+  struct dma_fence * const fence)
+{
+   struct drm_syncobj *syncobj = vma->vm_bind_fence.syncobj;
+
+   if (!syncobj)
+   return;
+
+   if (vma->vm_bind_fence.chain_fence) {
+   drm_syncobj_add_point(syncobj,
+ vma->vm_bind_fence.chain_fence,
+ fence, vma->vm_bind_fence.value);
+   /*
+* The chain's ownership is transferred to the
+* timeline.
+*/
+   vma->vm_bind_fence.chain_fence = NULL;
+   } else {
+   drm_syncobj_replace_fence(syncobj, fence);
+   }
+}
+
 static int i915_gem_vm_unbind_vma(struct i915_address_space *vm,
  struct drm_i915_gem_vm_unbind *va)
 {
@@ -237,6 +309,13 @@ static int i915_gem_vm_bind_obj(struct i915_address_space 
*vm,
goto unlock_vm;
}
+   if (va->fence.flags & I915_TIMELINE_FENCE_SIGNAL) {
+   ret = i915_vm_bind_add_fence(file, vma, va->fence.handle,
+va->fence.value);
+   if (ret)
+   goto put_vma;
+   }
+
pin_flags = va->start | PIN_OFFSET_FIXED | PIN_USER | PIN_VALIDATE;
for_i915_gem_ww(&ww, ret, true) {
@@ -258,6 +337,9 @@ static int i915_gem_vm_bind_obj(struct i915_address_space 
*vm,
i915_gem_object_get(vma->obj);
}
+   if (va->fence.flags & I915_TIMELINE_FENCE

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/vm_bind: Add VM_BIND functionality (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915/vm_bind: Add VM_BIND functionality (rev7)
URL   : https://patchwork.freedesktop.org/series/105879/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12254_full -> Patchwork_105879v7_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_105879v7_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_mmap_gtt@fault-concurrent-y:
- shard-snb:  [PASS][1] -> [INCOMPLETE][2] ([i915#5161])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12254/shard-snb2/igt@gem_mmap_...@fault-concurrent-y.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v7/shard-snb5/igt@gem_mmap_...@fault-concurrent-y.html

  * igt@gen9_exec_parse@allowed-single:
- shard-tglb: NOTRUN -> [SKIP][3] ([i915#2527] / [i915#2856])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v7/shard-tglb1/igt@gen9_exec_pa...@allowed-single.html

  * igt@i915_selftest@live@workarounds:
- shard-tglb: NOTRUN -> [INCOMPLETE][4] ([i915#7222])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v7/shard-tglb1/igt@i915_selftest@l...@workarounds.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#3743])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12254/shard-tglb7/igt@kms_big...@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v7/shard-tglb1/igt@kms_big...@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][7] ([i915#6095])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v7/shard-tglb1/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][8] ([i915#3689] / [i915#3886])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v7/shard-tglb1/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_content_protection@content_type_change:
- shard-tglb: NOTRUN -> [SKIP][9] ([i915#7118])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v7/shard-tglb1/igt@kms_content_protection@content_type_change.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-tglb: NOTRUN -> [SKIP][10] ([i915#3555]) +1 similar issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v7/shard-tglb1/igt@kms_cursor_...@cursor-sliding-32x10.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-tglb: NOTRUN -> [SKIP][11] ([fdo#109274] / [fdo#111825] / 
[i915#3637])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v7/shard-tglb1/igt@kms_f...@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt:
- shard-tglb: NOTRUN -> [SKIP][12] ([fdo#109280] / [fdo#111825]) +2 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v7/shard-tglb1/igt@kms_frontbuffer_track...@fbcpsr-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-c-edp-1:
- shard-tglb: NOTRUN -> [SKIP][13] ([i915#5176]) +3 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v7/shard-tglb1/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0...@pipe-c-edp-1.html

  
 Possible fixes 

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-tglb: [FAIL][14] ([i915#3743]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12254/shard-tglb1/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v7/shard-tglb1/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  
 Warnings 

  * igt@gem_pread@exhaustion:
- shard-tglb: [INCOMPLETE][16] ([i915#7244]) -> [WARN][17] 
([i915#2658])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12254/shard-tglb1/igt@gem_pr...@exhaustion.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v7/shard-tglb1/igt@gem_pr...@exhaustion.html

  * igt@gem_workarounds@suspend-resume:
- shard-apl:  [INCOMPLETE][18] ([i915#7231] / [i915#7259]) -> 
[INCOMPLETE][19] ([i915#7259])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12254/shard-apl3/igt@gem_workarou...@suspend-resume.html
   [19]: 
https://intel-gfx-ci.01.org/

Re: [Intel-gfx] [PATCH v2 5/7] drm/i915/mtl: Handle wopcm per-GT and limit calculations.

[John Harrison]

On 10/12/2022 17:03, Daniele Ceraolo Spurio wrote:

From: Aravind Iddamsetty 

With MTL standalone media architecture the wopcm layout has changed with
separate partitioning in WOPCM for GCD/GT GuC and SA Media GuC. The size

What is GCD?


of WOPCM is 4MB with lower 2MB for SA Media and upper 2MB for GCD/GT.

 +=+===> ++ <== WOPCM TOP
 ^ ^ ||
 | | ||
 |GCD|   GCD RC6 Image|
 |GuC|Power Context   |
 |WOPCM  ||
 |Size   ++
 | | |   GCD GuC Image|
 | | ||
 | v ||
 | +===> ++ <== SA Media GuC WOPCM Top
 | ^ ||
 |   SA Media||
 |GuC| SA Media RC6 Image |
 |   WOPCM   |Power Context   |
 |Size   ||
   WOPCM   | ++
 | | ||
 | | | SA Media GuC Image |
 | v ||
 | +===> ++ <== GuC WOPCM base
 |   | WOPCM RSVD |
 |   +--- + <== HuC Firmware Top
 v   |  HuC FW|
 +=> ++ <== WOPCM Base

Given that MTL has GuC deprivilege, the WOPCM registers are pre-locked
by the bios. Therefore, we can skip all the math for the partitioning
and just limit ourselves to sanity checking the values.

v2: fix makefile file ordering (Jani)

Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Daniele Ceraolo Spurio 
Cc: Matt Roper 
Cc: John Harrison 
Cc: Alan Previn 
Cc: Jani Nikula 
---
  drivers/gpu/drm/i915/Makefile   |  5 ++-
  drivers/gpu/drm/i915/gt/intel_ggtt.c|  2 +-
  drivers/gpu/drm/i915/gt/intel_gt.c  |  1 +
  drivers/gpu/drm/i915/gt/intel_gt_types.h|  2 +
  drivers/gpu/drm/i915/{ => gt}/intel_wopcm.c | 48 +++--
  drivers/gpu/drm/i915/{ => gt}/intel_wopcm.h |  0
  drivers/gpu/drm/i915/gt/uc/intel_uc.c   |  4 +-
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c| 14 +++---
  drivers/gpu/drm/i915/i915_driver.c  |  2 -
  drivers/gpu/drm/i915/i915_drv.h |  3 --
  drivers/gpu/drm/i915/i915_gem.c |  5 ++-
  11 files changed, 55 insertions(+), 31 deletions(-)
  rename drivers/gpu/drm/i915/{ => gt}/intel_wopcm.c (86%)
  rename drivers/gpu/drm/i915/{ => gt}/intel_wopcm.h (100%)

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f8cc1eb52626..4101b3507346 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -127,9 +127,11 @@ gt-y += \
gt/intel_sseu.o \
gt/intel_sseu_debugfs.o \
gt/intel_timeline.o \
+   gt/intel_wopcm.o \
gt/intel_workarounds.o \
gt/shmem_utils.o \
gt/sysfs_engines.o
+
  # x86 intel-gtt module support
  gt-$(CONFIG_X86) += gt/intel_ggtt_gmch.o
  # autogenerated null render state
@@ -183,8 +185,7 @@ i915-y += \
  i915_trace_points.o \
  i915_ttm_buddy_manager.o \
  i915_vma.o \
- i915_vma_resource.o \
- intel_wopcm.o
+ i915_vma_resource.o
  
  # general-purpose microcontroller (GuC) support

  i915-y += gt/uc/intel_uc.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 5c67e49aacf6..b30560ab1c1b 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -560,7 +560,7 @@ static int init_ggtt(struct i915_ggtt *ggtt)
 * why.
 */
ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
-  intel_wopcm_guc_size(&ggtt->vm.i915->wopcm));
+  intel_wopcm_guc_size(&ggtt->vm.gt->wopcm));
  
  	ret = intel_vgt_balloon(ggtt);

if (ret)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index b367cfff48d5..a95eb0b656d2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -56,6 +56,7 @@ void intel_gt_common_init_early(struct intel_gt *gt)
seqcount_mutex_init(>->tlb.seqno, >->tlb.invalidate_lock);
intel_gt_pm_init_early(gt);
  
+	intel_wopcm_init_early(>->wopcm);

intel_uc_init_early(>->uc);
intel_rps_init_early(>->rps);
  }
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 30003d68fd51..a23cd3af5bf2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -30,6 +30,7 @@
  #include "intel_migrate_types.h"
  #include "intel_wakeref.h"
  #include "pxp/intel_pxp_types.h"
+#include "intel_wopcm.h"
  
  struct drm_i915_private;

  struct i915_ggtt;
@@ -98,6 +99,7 @@ struct intel_gt {
  
  	struct intel_uc uc;

struct intel_gsc g

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add DG2 OA support (rev8)

[Patchwork]

== Series Details ==

Series: Add DG2 OA support (rev8)
URL   : https://patchwork.freedesktop.org/series/107584/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DG2 OA support (rev8)

[Patchwork]

== Series Details ==

Series: Add DG2 OA support (rev8)
URL   : https://patchwork.freedesktop.org/series/107584/
State : warning

== Summary ==

Error: dim checkpatch failed
0bf14cf6597e drm/i915/perf: Fix OA filtering logic for GuC mode
dfe2d19762a0 drm/i915/perf: Add 32-bit OAG and OAR formats for DG2
d315bb1f4f02 drm/i915/perf: Fix noa wait predication for DG2
909fd2f2dbb4 drm/i915/perf: Determine gen12 oa ctx offset at runtime
212e98fbb19e drm/i915/perf: Enable bytes per clock reporting in OA
6c1e44b8ee86 drm/i915/perf: Simply use stream->ctx
d6ad777f12c6 drm/i915/perf: Move gt-specific data from i915->perf to gt->perf
4f2b61f0f0c5 drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops
341cd0a92c2d drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers
01cbb5248b04 drm/i915/perf: Store a pointer to oa_format in oa_buffer
1ba7b62c013d drm/i915/perf: Add Wa_1508761755:dg2
-:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#50: FILE: drivers/gpu/drm/i915/i915_perf.c:2786:
+   intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
+  
_MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));

-:68: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#68: FILE: drivers/gpu/drm/i915/i915_perf.c:2875:
+   intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
+  
_MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));

total: 0 errors, 0 warnings, 2 checks, 49 lines checked
21597a2d5558 drm/i915/perf: Apply Wa_18013179988
c27db74ba252 drm/i915/perf: Save/restore EU flex counters across reset
c016fd4fd563 drm/i915/guc: Support OA when Wa_16011777198 is enabled
-:72: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#72: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:208:
+   GEM_BUG_ON(id >= SLPC_MAX_PARAM);

total: 0 errors, 1 warnings, 0 checks, 151 lines checked
8620f1d6a324 drm/i915/perf: complete programming whitelisting for XEHPSDV
c26a47fd0a86 drm/i915/perf: Enable OA for DG2

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/slpc: Optmize waitboost for SLPC

[Patchwork]

== Series Details ==

Series: drm/i915/slpc: Optmize waitboost for SLPC
URL   : https://patchwork.freedesktop.org/series/109840/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12258 -> Patchwork_109840v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v1/index.html

Participating hosts (39 -> 38)
--

  Additional (1): fi-hsw-4770 
  Missing(2): bat-adlm-1 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_109840v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[PASS][1] -> [FAIL][2] ([i915#7229])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#3012])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rpm@module-reload:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][4] ([i915#7221])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v1/fi-hsw-4770/igt@i915_pm_...@module-reload.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1072]) +3 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#4312] / 
[i915#5594])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v1/fi-hsw-4770/igt@run...@aborted.html

  
 Warnings 

  * igt@i915_suspend@basic-s3-without-i915:
- fi-bdw-gvtdvm:  [FAIL][9] ([fdo#103375]) -> [INCOMPLETE][10] 
([i915#146])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/fi-bdw-gvtdvm/igt@i915_susp...@basic-s3-without-i915.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v1/fi-bdw-gvtdvm/igt@i915_susp...@basic-s3-without-i915.html

  
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
  [i915#7221]: https://gitlab.freedesktop.org/drm/intel/issues/7221
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229


Build changes
-

  * Linux: CI_DRM_12258 -> Patchwork_109840v1

  CI-20190529: 20190529
  CI_DRM_12258: 46aaaf749a4300985a8415b327a96a2bffb63018 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7019: fdbafce2b74e84739bb1d81223ae6f01fb442980 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_109840v1: 46aaaf749a4300985a8415b327a96a2bffb63018 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

5c0801b811a7 drm/i915/slpc: Optmize waitboost for SLPC

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v1/index.html

Re: [Intel-gfx] [PATCH 3/3] drm/i915/tgl+: Sanitize DKL PHY register definitions

[kernel test robot]

Hi Imre,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-tip/drm-tip]

url:
https://github.com/intel-lab-lkp/linux/commits/Imre-Deak/drm-i915-tgl-Add-locking-around-DKL-PHY-register-accesses/20221019-012209
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:
https://lore.kernel.org/r/20221018172042.1449885-3-imre.deak%40intel.com
patch subject: [Intel-gfx] [PATCH 3/3] drm/i915/tgl+: Sanitize DKL PHY register 
definitions
config: x86_64-randconfig-a005
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project 
f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# 
https://github.com/intel-lab-lkp/linux/commit/7829cf13e91885a6fca2628c8164adf7e16c8c39
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review 
Imre-Deak/drm-i915-tgl-Add-locking-around-DKL-PHY-register-accesses/20221019-012209
git checkout 7829cf13e91885a6fca2628c8164adf7e16c8c39
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 
O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot 

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/display/intel_tc.c:837: warning: Function parameter or 
member 'work' not described in 'intel_tc_port_disconnect_phy_work'
   drivers/gpu/drm/i915/display/intel_tc.c:837: warning: Excess function 
parameter 'dig_port' description in 'intel_tc_port_disconnect_phy_work'
>> drivers/gpu/drm/i915/display/intel_tc.c:978: warning: expecting prototype 
>> for intel_tc_dkl_posting_read(). Prototype was for 
>> intel_tc_dkl_phy_posting_read() instead


vim +978 drivers/gpu/drm/i915/display/intel_tc.c

1e6345b5b55c373 Imre Deak 2022-10-18  969  
1e6345b5b55c373 Imre Deak 2022-10-18  970  /**
1e6345b5b55c373 Imre Deak 2022-10-18  971   * intel_tc_dkl_posting_read - do a 
posting read from a Dekel PHY register
1e6345b5b55c373 Imre Deak 2022-10-18  972   * @i915: i915 device instance
1e6345b5b55c373 Imre Deak 2022-10-18  973   * @reg: Dekel PHY register
1e6345b5b55c373 Imre Deak 2022-10-18  974   *
1e6345b5b55c373 Imre Deak 2022-10-18  975   * Read the @reg Dekel PHY register 
without returning the read value.
1e6345b5b55c373 Imre Deak 2022-10-18  976   */
7829cf13e91885a Imre Deak 2022-10-18  977  void 
intel_tc_dkl_phy_posting_read(struct drm_i915_private *i915, struct 
intel_tc_dkl_reg reg)
1e6345b5b55c373 Imre Deak 2022-10-18 @978  {
1e6345b5b55c373 Imre Deak 2022-10-18  979   
spin_lock(&i915->display.tc.dkl_lock);
1e6345b5b55c373 Imre Deak 2022-10-18  980  
7829cf13e91885a Imre Deak 2022-10-18  981   dkl_set_hip_idx(i915, reg);
7829cf13e91885a Imre Deak 2022-10-18  982   intel_de_posting_read(i915, 
DKL_REG_MMIO(reg));
1e6345b5b55c373 Imre Deak 2022-10-18  983  
1e6345b5b55c373 Imre Deak 2022-10-18  984   
spin_unlock(&i915->display.tc.dkl_lock);
1e6345b5b55c373 Imre Deak 2022-10-18  985  }
1e6345b5b55c373 Imre Deak 2022-10-18  986  

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp
#
# Automatically generated file; DO NOT EDIT.
# Linux/x86_64 6.1.0-rc1 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="clang version 14.0.6 (git://gitmirror/llvm_project 
f28c006a5895fc0e329fe15fead81e37457cb1d1)"
CONFIG_GCC_VERSION=0
CONFIG_CC_IS_CLANG=y
CONFIG_CLANG_VERSION=140006
CONFIG_AS_IS_LLVM=y
CONFIG_AS_VERSION=140006
CONFIG_LD_VERSION=0
CONFIG_LD_IS_LLD=y
CONFIG_LLD_VERSION=140006
CONFIG_RUST_IS_AVAILABLE=y
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_TOOLS_SUPPORT_RELR=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_PAHOLE_VERSION=123
CONFIG_CONSTRUCTORS=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
# CONFIG_UAPI_HEADER_TEST is not set
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_BUILD_SALT=""
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_LZ4=y
CONFIG_HAVE_KERNEL_ZSTD=y
# CONFIG_KERNEL_GZIP is not set
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
CONFIG_KERNEL_LZO=y
# CONFIG_KERNEL_LZ4 is not set
# CONFIG_KERNEL_ZSTD is not set
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
# CONFIG_WATCH_QUEUE is not set
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_USELIB=y
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

[Intel-gfx] [PATCH v5 05/16] drm/i915/perf: Enable bytes per clock reporting in OA

[Umesh Nerlige Ramappa]

XEHPSDV and DG2 provide a way to configure bytes per clock vs commands
per clock reporting. Enable bytes per clock setting on enabling OA.

Bspec: 51762
Bspec: 52201

v2:
- Fix commit msg (Ashutosh)
- Fix checkpatch issues

v3:
- s/commands/bytes/ in code comment and commmit msg

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_drv.h  |  3 +++
 drivers/gpu/drm/i915/i915_pci.c  |  1 +
 drivers/gpu/drm/i915/i915_perf.c | 20 
 drivers/gpu/drm/i915/i915_perf_oa_regs.h |  4 
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 5 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7c64f8a17493..438aebeea103 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -898,6 +898,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
 
+#define HAS_OA_BPC_REPORTING(dev_priv) \
+   (INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
+
 /*
  * Set this flag, when platform requires 64K GTT page sizes or larger for
  * device local memory access.
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 496df0f547f4..cbced3f3db17 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1023,6 +1023,7 @@ static const struct intel_device_info adl_p_info = {
.has_logical_ring_contexts = 1, \
.has_logical_ring_elsq = 1, \
.has_mslice_steering = 1, \
+   .has_oa_bpc_reporting = 1, \
.has_rc6 = 1, \
.has_reset_engine = 1, \
.has_rps = 1, \
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index b71b5cf21176..d11cc949c9be 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2748,10 +2748,12 @@ static int
 gen12_enable_metric_set(struct i915_perf_stream *stream,
struct i915_active *active)
 {
+   struct drm_i915_private *i915 = stream->perf->i915;
struct intel_uncore *uncore = stream->uncore;
struct i915_oa_config *oa_config = stream->oa_config;
bool periodic = stream->periodic;
u32 period_exponent = stream->period_exponent;
+   u32 sqcnt1;
int ret;
 
intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,
@@ -2770,6 +2772,16 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
(period_exponent << 
GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
: 0);
 
+   /*
+* Initialize Super Queue Internal Cnt Register
+* Set PMON Enable in order to collect valid metrics.
+* Enable byets per clock reporting in OA for XEHPSDV onward.
+*/
+   sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
+(HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
+
+   intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, sqcnt1);
+
/*
 * Update all contexts prior writing the mux configurations as we need
 * to make sure all slices/subslices are ON before writing to NOA
@@ -2819,6 +2831,8 @@ static void gen11_disable_metric_set(struct 
i915_perf_stream *stream)
 static void gen12_disable_metric_set(struct i915_perf_stream *stream)
 {
struct intel_uncore *uncore = stream->uncore;
+   struct drm_i915_private *i915 = stream->perf->i915;
+   u32 sqcnt1;
 
/* Reset all contexts' slices/subslices configurations. */
gen12_configure_all_contexts(stream, NULL, NULL);
@@ -2829,6 +2843,12 @@ static void gen12_disable_metric_set(struct 
i915_perf_stream *stream)
 
/* Make sure we disable noa to save power. */
intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
+
+   sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
+(HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
+
+   /* Reset PMON Enable to save power. */
+   intel_uncore_rmw(uncore, GEN12_SQCNT1, sqcnt1, 0);
 }
 
 static void gen7_oa_enable(struct i915_perf_stream *stream)
diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h 
b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
index 0ef3562ff4aa..381d94101610 100644
--- a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
+++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
@@ -134,4 +134,8 @@
 #define GDT_CHICKEN_BITS_MMIO(0x9840)
 #define   GT_NOA_ENABLE0x0080
 
+#define GEN12_SQCNT1   _MMIO(0x8718)
+#define   GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
+#define   GEN12_SQCNT1_OABPC   REG_BIT(29)
+
 #endif /* __INTEL_PERF_OA_REGS__ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index cdf78728dcad..42218c8d85f2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.

[Intel-gfx] [PATCH v5 10/16] drm/i915/perf: Store a pointer to oa_format in oa_buffer

[Umesh Nerlige Ramappa]

DG2 introduces OA reports with 64 bit report header fields. Perf OA
would need more information about the OA format in order to process such
reports. Store all OA format info in oa_buffer instead of just the size
and format-id.

v2: Drop format_size variable (Ashutosh)

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Lionel Landwerlin 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_perf.c   | 30 +++---
 drivers/gpu/drm/i915/i915_perf_types.h |  3 +--
 2 files changed, 13 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2c8727253f0d..585079ae5f03 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -465,7 +465,7 @@ static u32 gen7_oa_hw_tail_read(struct i915_perf_stream 
*stream)
 static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
 {
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
-   int report_size = stream->oa_buffer.format_size;
+   int report_size = stream->oa_buffer.format->size;
unsigned long flags;
bool pollin;
u32 hw_tail;
@@ -602,7 +602,7 @@ static int append_oa_sample(struct i915_perf_stream *stream,
size_t *offset,
const u8 *report)
 {
-   int report_size = stream->oa_buffer.format_size;
+   int report_size = stream->oa_buffer.format->size;
struct drm_i915_perf_record_header header;
 
header.type = DRM_I915_PERF_RECORD_SAMPLE;
@@ -652,7 +652,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream 
*stream,
  size_t *offset)
 {
struct intel_uncore *uncore = stream->uncore;
-   int report_size = stream->oa_buffer.format_size;
+   int report_size = stream->oa_buffer.format->size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
u32 mask = (OA_BUFFER_SIZE - 1);
@@ -945,7 +945,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream 
*stream,
  size_t *offset)
 {
struct intel_uncore *uncore = stream->uncore;
-   int report_size = stream->oa_buffer.format_size;
+   int report_size = stream->oa_buffer.format->size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
u32 mask = (OA_BUFFER_SIZE - 1);
@@ -2506,7 +2506,7 @@ static int gen12_configure_oar_context(struct 
i915_perf_stream *stream,
 {
int err;
struct intel_context *ce = stream->pinned_ctx;
-   u32 format = stream->oa_buffer.format;
+   u32 format = stream->oa_buffer.format->format;
u32 offset = stream->perf->ctx_oactxctrl_offset;
struct flex regs_context[] = {
{
@@ -2877,7 +2877,7 @@ static void gen7_oa_enable(struct i915_perf_stream 
*stream)
u32 ctx_id = stream->specific_ctx_id;
bool periodic = stream->periodic;
u32 period_exponent = stream->period_exponent;
-   u32 report_format = stream->oa_buffer.format;
+   u32 report_format = stream->oa_buffer.format->format;
 
/*
 * Reset buf pointers so we don't forward reports from before now.
@@ -2903,7 +2903,7 @@ static void gen7_oa_enable(struct i915_perf_stream 
*stream)
 static void gen8_oa_enable(struct i915_perf_stream *stream)
 {
struct intel_uncore *uncore = stream->uncore;
-   u32 report_format = stream->oa_buffer.format;
+   u32 report_format = stream->oa_buffer.format->format;
 
/*
 * Reset buf pointers so we don't forward reports from before now.
@@ -2929,7 +2929,7 @@ static void gen8_oa_enable(struct i915_perf_stream 
*stream)
 static void gen12_oa_enable(struct i915_perf_stream *stream)
 {
struct intel_uncore *uncore = stream->uncore;
-   u32 report_format = stream->oa_buffer.format;
+   u32 report_format = stream->oa_buffer.format->format;
 
/*
 * If we don't want OA reports from the OA buffer, then we don't even
@@ -3110,7 +3110,6 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
struct drm_i915_private *i915 = stream->perf->i915;
struct i915_perf *perf = stream->perf;
struct intel_gt *gt;
-   int format_size;
int ret;
 
if (!props->engine) {
@@ -3166,20 +3165,15 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 
stream->sample_size = sizeof(struct drm_i915_perf_record_header);
 
-   format_size = perf->oa_formats[props->oa_format].size;
+   stream->oa_buffer.format = &perf->oa_formats[props->oa_format];
+   if (drm_WARN_ON(&i915->drm, stream->oa_buffer.format->size == 0))
+   return -EINVAL;
 
stream->sample_flags = props->sample_flags;
-   stream->sample_size += format_size;
-
-   stream->oa_buffer.format_size = format_size;
-   if (drm_WARN_ON

[Intel-gfx] [PATCH v5 08/16] drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops

[Umesh Nerlige Ramappa]

With multi-gt, user can access multiple OA buffers concurrently. Use
stream->lock instead of gt->perf.lock to serialize file operations.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_perf.c   | 31 --
 drivers/gpu/drm/i915/i915_perf_types.h |  5 +
 2 files changed, 19 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 83c5dc043261..9a00398ae25f 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3231,6 +3231,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
stream->poll_check_timer.function = oa_poll_check_timer_cb;
init_waitqueue_head(&stream->poll_wq);
spin_lock_init(&stream->oa_buffer.ptr_lock);
+   mutex_init(&stream->lock);
 
return 0;
 
@@ -3294,7 +3295,6 @@ static ssize_t i915_perf_read(struct file *file,
  loff_t *ppos)
 {
struct i915_perf_stream *stream = file->private_data;
-   struct intel_gt *gt = stream->engine->gt;
size_t offset = 0;
int ret;
 
@@ -3318,14 +3318,14 @@ static ssize_t i915_perf_read(struct file *file,
if (ret)
return ret;
 
-   mutex_lock(>->perf.lock);
+   mutex_lock(&stream->lock);
ret = stream->ops->read(stream, buf, count, &offset);
-   mutex_unlock(>->perf.lock);
+   mutex_unlock(&stream->lock);
} while (!offset && !ret);
} else {
-   mutex_lock(>->perf.lock);
+   mutex_lock(&stream->lock);
ret = stream->ops->read(stream, buf, count, &offset);
-   mutex_unlock(>->perf.lock);
+   mutex_unlock(&stream->lock);
}
 
/* We allow the poll checking to sometimes report false positive EPOLLIN
@@ -3372,9 +3372,6 @@ static enum hrtimer_restart oa_poll_check_timer_cb(struct 
hrtimer *hrtimer)
  * &i915_perf_stream_ops->poll_wait to call poll_wait() with a wait queue that
  * will be woken for new stream data.
  *
- * Note: The >->perf.lock mutex has been taken to serialize
- * with any non-file-operation driver hooks.
- *
  * Returns: any poll events that are ready without sleeping
  */
 static __poll_t i915_perf_poll_locked(struct i915_perf_stream *stream,
@@ -3413,12 +3410,11 @@ static __poll_t i915_perf_poll_locked(struct 
i915_perf_stream *stream,
 static __poll_t i915_perf_poll(struct file *file, poll_table *wait)
 {
struct i915_perf_stream *stream = file->private_data;
-   struct intel_gt *gt = stream->engine->gt;
__poll_t ret;
 
-   mutex_lock(>->perf.lock);
+   mutex_lock(&stream->lock);
ret = i915_perf_poll_locked(stream, file, wait);
-   mutex_unlock(>->perf.lock);
+   mutex_unlock(&stream->lock);
 
return ret;
 }
@@ -3517,9 +3513,6 @@ static long i915_perf_config_locked(struct 
i915_perf_stream *stream,
  * @cmd: the ioctl request
  * @arg: the ioctl data
  *
- * Note: The >->perf.lock mutex has been taken to serialize
- * with any non-file-operation driver hooks.
- *
  * Returns: zero on success or a negative error code. Returns -EINVAL for
  * an unknown ioctl request.
  */
@@ -3557,12 +3550,11 @@ static long i915_perf_ioctl(struct file *file,
unsigned long arg)
 {
struct i915_perf_stream *stream = file->private_data;
-   struct intel_gt *gt = stream->engine->gt;
long ret;
 
-   mutex_lock(>->perf.lock);
+   mutex_lock(&stream->lock);
ret = i915_perf_ioctl_locked(stream, cmd, arg);
-   mutex_unlock(>->perf.lock);
+   mutex_unlock(&stream->lock);
 
return ret;
 }
@@ -3608,6 +3600,11 @@ static int i915_perf_release(struct inode *inode, struct 
file *file)
struct i915_perf *perf = stream->perf;
struct intel_gt *gt = stream->engine->gt;
 
+   /*
+* Within this call, we know that the fd is being closed and we have no
+* other user of stream->lock. Use the perf lock to destroy the stream
+* here.
+*/
mutex_lock(>->perf.lock);
i915_perf_destroy_locked(stream);
mutex_unlock(>->perf.lock);
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h 
b/drivers/gpu/drm/i915/i915_perf_types.h
index e888bfab478f..dc9bfd8086cf 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -146,6 +146,11 @@ struct i915_perf_stream {
 */
struct intel_engine_cs *engine;
 
+   /*
+* Lock associated with operations on stream
+*/
+   struct mutex lock;
+
/**
 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
 * properties given when opening a stream, representing the contents
-- 
2.25.1

[Intel-gfx] [PATCH v5 06/16] drm/i915/perf: Simply use stream->ctx

[Umesh Nerlige Ramappa]

Earlier code used exclusive_stream to check for user passed context.
Simplify this by accessing stream->ctx.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_perf.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index d11cc949c9be..75d320b2c1f8 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -776,7 +776,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream 
*stream,
 * switches since it's not-uncommon for periodic samples to
 * identify a switch before any 'context switch' report.
 */
-   if (!stream->perf->exclusive_stream->ctx ||
+   if (!stream->ctx ||
stream->specific_ctx_id == ctx_id ||
stream->oa_buffer.last_ctx_id == stream->specific_ctx_id ||
reason & OAREPORT_REASON_CTX_SWITCH) {
@@ -785,7 +785,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream 
*stream,
 * While filtering for a single context we avoid
 * leaking the IDs of other contexts.
 */
-   if (stream->perf->exclusive_stream->ctx &&
+   if (stream->ctx &&
stream->specific_ctx_id != ctx_id) {
report32[2] = INVALID_CTX_ID;
}
-- 
2.25.1

[Intel-gfx] [PATCH v5 03/16] drm/i915/perf: Fix noa wait predication for DG2

[Umesh Nerlige Ramappa]

Predication for batch buffer commands changed in XEHPSDV.
MI_BATCH_BUFFER_START predicates based on MI_SET_PREDICATE_RESULT
register. The MI_SET_PREDICATE_RESULT register can only be modified
with MI_SET_PREDICATE command. When configured, the MI_SET_PREDICATE
command sets MI_SET_PREDICATE_RESULT based on bit 0 of
MI_PREDICATE_RESULT_2. Use this to configure predication in noa_wait.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_engine_regs.h |  1 +
 drivers/gpu/drm/i915/i915_perf.c| 24 +
 2 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h 
b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index fe1a0d5fd4b1..ee3efd06ee54 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -201,6 +201,7 @@
 #define RING_CONTEXT_STATUS_PTR(base)  _MMIO((base) + 0x3a0)
 #define RING_CTX_TIMESTAMP(base)   _MMIO((base) + 0x3a8) /* gen8+ 
*/
 #define RING_PREDICATE_RESULT(base)_MMIO((base) + 0x3b8)
+#define MI_PREDICATE_RESULT_2_ENGINE(base) _MMIO((base) + 0x3bc)
 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 
4)
 #define   RING_FORCE_TO_NONPRIV_DENY   REG_BIT(30)
 #define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK   REG_GENMASK(25, 2)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2b772a6b1cd6..e68666b44a72 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -286,6 +286,7 @@ static u32 i915_perf_stream_paranoid = true;
 #define OAREPORT_REASON_CTX_SWITCH (1<<3)
 #define OAREPORT_REASON_CLK_RATIO  (1<<5)
 
+#define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
 
 /* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
  *
@@ -1760,6 +1761,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
DELTA_TARGET,
N_CS_GPR
};
+   i915_reg_t mi_predicate_result = HAS_MI_SET_PREDICATE(i915) ?
+ MI_PREDICATE_RESULT_2_ENGINE(base) :
+ 
MI_PREDICATE_RESULT_1(RENDER_RING_BASE);
 
bo = i915_gem_object_create_internal(i915, 4096);
if (IS_ERR(bo)) {
@@ -1797,7 +1801,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
stream, cs, true /* save */, CS_GPR(i),
INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
cs = save_restore_register(
-   stream, cs, true /* save */, 
MI_PREDICATE_RESULT_1(RENDER_RING_BASE),
+   stream, cs, true /* save */, mi_predicate_result,
INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
 
/* First timestamp snapshot location. */
@@ -1851,7 +1855,10 @@ static int alloc_noa_wait(struct i915_perf_stream 
*stream)
 */
*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
-   *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));
+   *cs++ = i915_mmio_reg_offset(mi_predicate_result);
+
+   if (HAS_MI_SET_PREDICATE(i915))
+   *cs++ = MI_SET_PREDICATE | 1;
 
/* Restart from the beginning if we had timestamps roll over. */
*cs++ = (GRAPHICS_VER(i915) < 8 ?
@@ -1861,6 +1868,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
*cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
*cs++ = 0;
 
+   if (HAS_MI_SET_PREDICATE(i915))
+   *cs++ = MI_SET_PREDICATE;
+
/*
 * Now add the diff between to previous timestamps and add it to :
 *  (((1 * << 64) - 1) - delay_ns)
@@ -1888,7 +1898,10 @@ static int alloc_noa_wait(struct i915_perf_stream 
*stream)
 */
*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
-   *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));
+   *cs++ = i915_mmio_reg_offset(mi_predicate_result);
+
+   if (HAS_MI_SET_PREDICATE(i915))
+   *cs++ = MI_SET_PREDICATE | 1;
 
/* Predicate the jump.  */
*cs++ = (GRAPHICS_VER(i915) < 8 ?
@@ -1898,13 +1911,16 @@ static int alloc_noa_wait(struct i915_perf_stream 
*stream)
*cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
*cs++ = 0;
 
+   if (HAS_MI_SET_PREDICATE(i915))
+   *cs++ = MI_SET_PREDICATE;
+
/* Restore registers. */
for (i = 0; i < N_CS_GPR; i++)
cs = save_restore_register(
stream, cs, false /* restore */, CS_GPR(i),
INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
cs = save_restore_register(
-   stream, cs, false /* restore */, 
MI_PREDICATE_RESULT_1(RENDER_RING_BASE),
+   stream, cs, fa

[Intel-gfx] [PATCH v5 14/16] drm/i915/guc: Support OA when Wa_16011777198 is enabled

[Umesh Nerlige Ramappa]

From: Vinay Belgaumkar 

On DG2, a w/a resets RCS/CCS before it goes into RC6. This breaks OA
since OA does not expect engine resets during its use. Fix it by
disabling RC6.

v2: (Ashutosh)
- Bring back slpc_unset_param helper
- Update commit msg
- Use with_intel_runtime_pm helper for set/unset

v3: (Ashutosh)
- Just use intel_uc_uses_guc_rc

Signed-off-by: Vinay Belgaumkar 
Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h |  9 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 66 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h   |  2 +
 drivers/gpu/drm/i915/i915_perf.c  | 27 
 4 files changed, 104 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
index 4c840a2639dc..811add10c30d 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
@@ -128,6 +128,15 @@ enum slpc_media_ratio_mode {
SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO = 2,
 };
 
+enum slpc_gucrc_mode {
+   SLPC_GUCRC_MODE_HW = 0,
+   SLPC_GUCRC_MODE_GUCRC_NO_RC6 = 1,
+   SLPC_GUCRC_MODE_GUCRC_STATIC_TIMEOUT = 2,
+   SLPC_GUCRC_MODE_GUCRC_DYNAMIC_HYSTERESIS = 3,
+
+   SLPC_GUCRC_MODE_MAX,
+};
+
 enum slpc_event_id {
SLPC_EVENT_RESET = 0,
SLPC_EVENT_SHUTDOWN = 1,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index fdd895f73f9f..b3a4fb9e021f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -137,6 +137,17 @@ static int guc_action_slpc_set_param(struct intel_guc 
*guc, u8 id, u32 value)
return ret > 0 ? -EPROTO : ret;
 }
 
+static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)
+{
+   u32 request[] = {
+   GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
+   SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1),
+   id,
+   };
+
+   return intel_guc_send(guc, request, ARRAY_SIZE(request));
+}
+
 static bool slpc_is_running(struct intel_guc_slpc *slpc)
 {
return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
@@ -190,6 +201,15 @@ static int slpc_set_param(struct intel_guc_slpc *slpc, u8 
id, u32 value)
return ret;
 }
 
+static int slpc_unset_param(struct intel_guc_slpc *slpc, u8 id)
+{
+   struct intel_guc *guc = slpc_to_guc(slpc);
+
+   GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+
+   return guc_action_slpc_unset_param(guc, id);
+}
+
 static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
 {
struct drm_i915_private *i915 = slpc_to_i915(slpc);
@@ -610,6 +630,52 @@ static void slpc_get_rp_values(struct intel_guc_slpc *slpc)
slpc->boost_freq = slpc->rp0_freq;
 }
 
+/**
+ * intel_guc_slpc_override_gucrc_mode() - override GUCRC mode
+ * @slpc: pointer to intel_guc_slpc.
+ * @mode: new value of the mode.
+ *
+ * This function will override the GUCRC mode.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode)
+{
+   int ret;
+   struct drm_i915_private *i915 = slpc_to_i915(slpc);
+   intel_wakeref_t wakeref;
+
+   if (mode >= SLPC_GUCRC_MODE_MAX)
+   return -EINVAL;
+
+   with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+   ret = slpc_set_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
+   if (ret)
+   drm_err(&i915->drm,
+   "Override gucrc mode %d failed %d\n",
+   mode, ret);
+   }
+
+   return ret;
+}
+
+int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
+{
+   struct drm_i915_private *i915 = slpc_to_i915(slpc);
+   intel_wakeref_t wakeref;
+   int ret = 0;
+
+   with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+   ret = slpc_unset_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE);
+   if (ret)
+   drm_err(&i915->drm,
+   "Unsetting gucrc mode failed %d\n",
+   ret);
+   }
+
+   return ret;
+}
+
 /*
  * intel_guc_slpc_enable() - Start SLPC
  * @slpc: pointer to intel_guc_slpc.
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index 82a98f78f96c..ccf483730d9d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -42,5 +42,7 @@ int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc 
*slpc, u32 val);
 void intel_guc_pm_intrmsk_enable(struct intel_gt *gt);
 void intel_guc_slpc_boost(struct intel_guc_slpc *slpc);
 void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc);
+int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc);
+int intel_guc_slpc_over

[Intel-gfx] [PATCH v5 15/16] drm/i915/perf: complete programming whitelisting for XEHPSDV

[Umesh Nerlige Ramappa]

From: Lionel Landwerlin 

We have an additional register to select which slices contribute to
OAG/OAG counter increments.

Signed-off-by: Lionel Landwerlin 
Signed-off-by: Matt Roper 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_drv.h  |  2 ++
 drivers/gpu/drm/i915/i915_pci.c  |  1 +
 drivers/gpu/drm/i915/i915_perf.c | 13 +
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 4 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 438aebeea103..3bbcd726c2da 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -900,6 +900,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_OA_BPC_REPORTING(dev_priv) \
(INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
+#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
+   (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
 
 /*
  * Set this flag, when platform requires 64K GTT page sizes or larger for
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index cbced3f3db17..3f505ee15d66 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1024,6 +1024,7 @@ static const struct intel_device_info adl_p_info = {
.has_logical_ring_elsq = 1, \
.has_mslice_steering = 1, \
.has_oa_bpc_reporting = 1, \
+   .has_oa_slice_contrib_limits = 1, \
.has_rc6 = 1, \
.has_reset_engine = 1, \
.has_rps = 1, \
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index bc0c486cf7d4..176442d5e57e 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4261,6 +4261,11 @@ static const struct i915_range gen12_oa_b_counters[] = {
{}
 };
 
+static const struct i915_range xehp_oa_b_counters[] = {
+   { .start = 0xdc48, .end = 0xdc48 }, /* OAA_ENABLE_REG */
+   { .start = 0xdd00, .end = 0xdd48 }, /* OAG_LCE0_0 - OAA_LENABLE_REG 
*/
+};
+
 static const struct i915_range gen7_oa_mux_regs[] = {
{ .start = 0x91b8, .end = 0x91cc }, /* OA_PERFCNT[1-2], 
OA_PERFMATRIX */
{ .start = 0x9800, .end = 0x9888 }, /* MICRO_BP0_0 - NOA_WRITE */
@@ -4335,6 +4340,12 @@ static bool gen12_is_valid_b_counter_addr(struct 
i915_perf *perf, u32 addr)
return reg_in_range_table(addr, gen12_oa_b_counters);
 }
 
+static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
+{
+   return reg_in_range_table(addr, xehp_oa_b_counters) ||
+   reg_in_range_table(addr, gen12_oa_b_counters);
+}
+
 static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
 {
return reg_in_range_table(addr, gen12_oa_mux_regs);
@@ -4847,6 +4858,8 @@ void i915_perf_init(struct drm_i915_private *i915)
perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
} else if (GRAPHICS_VER(i915) == 12) {
perf->ops.is_valid_b_counter_reg =
+   HAS_OA_SLICE_CONTRIB_LIMITS(i915) ?
+   xehp_is_valid_b_counter_addr :
gen12_is_valid_b_counter_addr;
perf->ops.is_valid_mux_reg =
gen12_is_valid_mux_addr;
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 42218c8d85f2..e292c1ee7c93 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -165,6 +165,7 @@ enum intel_ppgtt_type {
func(has_media_ratio_mode); \
func(has_mslice_steering); \
func(has_oa_bpc_reporting); \
+   func(has_oa_slice_contrib_limits); \
func(has_one_eu_per_fuse_bit); \
func(has_pxp); \
func(has_rc6); \
-- 
2.25.1

[Intel-gfx] [PATCH v5 11/16] drm/i915/perf: Add Wa_1508761755:dg2

[Umesh Nerlige Ramappa]

Disable Clock gating in EU when gathering the events so that EU events
are not lost.

v2: Fix checkpatch issues
v3: User MCR helpers to write to MC reg

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h |  1 +
 drivers/gpu/drm/i915/i915_perf.c| 24 
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 36d95b79022c..b101e31df61c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1164,6 +1164,7 @@
 #define   GEN12_DISABLE_EARLY_READ REG_BIT(14)
 #define   GEN12_ENABLE_LARGE_GRF_MODE  REG_BIT(12)
 #define   GEN12_PUSH_CONST_DEREF_HOLD_DIS  REG_BIT(8)
+#define   GEN12_DISABLE_DOP_GATING  REG_BIT(0)
 
 #define RT_CTRLMCR_REG(0xe530)
 #define   DIS_NULL_QUERY   REG_BIT(10)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 585079ae5f03..18619eb19769 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -204,6 +204,7 @@
 #include "gt/intel_gpu_commands.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_clock_utils.h"
+#include "gt/intel_gt_mcr.h"
 #include "gt/intel_gt_regs.h"
 #include "gt/intel_lrc.h"
 #include "gt/intel_lrc_reg.h"
@@ -2775,6 +2776,18 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
u32 sqcnt1;
int ret;
 
+   /*
+* Wa_1508761755:xehpsdv, dg2
+* EU NOA signals behave incorrectly if EU clock gating is enabled.
+* Disable thread stall DOP gating and EU DOP gating.
+*/
+   if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
+   intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
+  
_MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
+   intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
+  
_MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING));
+   }
+
intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,
   /* Disable clk ratio reports, like previous Gens. */
   
_MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
@@ -2853,6 +2866,17 @@ static void gen12_disable_metric_set(struct 
i915_perf_stream *stream)
struct drm_i915_private *i915 = stream->perf->i915;
u32 sqcnt1;
 
+   /*
+* Wa_1508761755:xehpsdv, dg2
+* Enable thread stall DOP gating and EU DOP gating.
+*/
+   if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
+   intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
+  
_MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
+   intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
+  
_MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING));
+   }
+
/* Reset all contexts' slices/subslices configurations. */
gen12_configure_all_contexts(stream, NULL, NULL);
 
-- 
2.25.1

[Intel-gfx] [PATCH v5 12/16] drm/i915/perf: Apply Wa_18013179988

[Umesh Nerlige Ramappa]

OA reports in the OA buffer contain an OA timestamp field that helps
user calculate delta between 2 OA reports. The calculation relies on the
CS timestamp frequency to convert the timestamp value to nanoseconds.
The CS timestamp frequency is a function of the CTC_SHIFT value in
RPM_CONFIG0.

In DG2, OA unit assumes that the CTC_SHIFT is 3, instead of using the
actual value from RPM_CONFIG0. At the user level, this results in an
error in calculating delta between 2 OA reports since the OA timestamp
is not shifted in the same manner as CS timestamp. Also the periodicity
of the reports is different from what the user configured because of
mismatch in the CS and OA frequencies.

The issue also affects MI_REPORT_PERF_COUNT command.

To resolve this, return actual OA timestamp frequency to the user in
i915_getparam_ioctl, so that user can calculate the right OA exponent as
well as interpret the reports correctly.

MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893

v2:
- Use REG_FIELD_GET (Ashutosh)
- Update commit msg

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_getparam.c |  3 +++
 drivers/gpu/drm/i915/i915_perf.c | 30 ++--
 drivers/gpu/drm/i915/i915_perf.h |  2 ++
 include/uapi/drm/i915_drm.h  |  6 ++
 4 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_getparam.c 
b/drivers/gpu/drm/i915/i915_getparam.c
index 342c8ca6414e..3047e80e1163 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -175,6 +175,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_PERF_REVISION:
value = i915_perf_ioctl_version();
break;
+   case I915_PARAM_OA_TIMESTAMP_FREQUENCY:
+   value = i915_perf_oa_timestamp_frequency(i915);
+   break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 18619eb19769..8540eb6156e4 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3109,6 +3109,30 @@ get_sseu_config(struct intel_sseu *out_sseu,
return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu);
 }
 
+/*
+ * OA timestamp frequency = CS timestamp frequency in most platforms. On some
+ * platforms OA unit ignores the CTC_SHIFT and the 2 timestamps differ. In such
+ * cases, return the adjusted CS timestamp frequency to the user.
+ */
+u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
+{
+   /* Wa_18013179988:dg2 */
+   if (IS_DG2(i915)) {
+   intel_wakeref_t wakeref;
+   u32 reg, shift;
+
+   with_intel_runtime_pm(to_gt(i915)->uncore->rpm, wakeref)
+   reg = intel_uncore_read(to_gt(i915)->uncore, 
RPM_CONFIG0);
+
+   shift = 
REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK,
+ reg);
+
+   return to_gt(i915)->clock_frequency << (3 - shift);
+   }
+
+   return to_gt(i915)->clock_frequency;
+}
+
 /**
  * i915_oa_stream_init - validate combined props for OA stream and init
  * @stream: An i915 perf stream
@@ -3830,8 +3854,10 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
 
 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
 {
-   return intel_gt_clock_interval_to_ns(to_gt(perf->i915),
-2ULL << exponent);
+   u64 nom = (2ULL << exponent) * NSEC_PER_SEC;
+   u32 den = i915_perf_oa_timestamp_frequency(perf->i915);
+
+   return div_u64(nom + den - 1, den);
 }
 
 static __always_inline bool
diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
index 1d1329e5af3a..f96e09a4af04 100644
--- a/drivers/gpu/drm/i915/i915_perf.h
+++ b/drivers/gpu/drm/i915/i915_perf.h
@@ -57,4 +57,6 @@ static inline void i915_oa_config_put(struct i915_oa_config 
*oa_config)
kref_put(&oa_config->ref, i915_oa_config_release);
 }
 
+u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915);
+
 #endif /* __I915_PERF_H__ */
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 158b35fb28f3..c346b1923d11 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -765,6 +765,12 @@ typedef struct drm_i915_irq_wait {
 /* Query if the kernel supports the I915_USERPTR_PROBE flag. */
 #define I915_PARAM_HAS_USERPTR_PROBE 56
 
+/*
+ * Frequency of the timestamps in OA reports. This used to be the same as the 
CS
+ * timestamp frequency, but differs on some platforms.
+ */
+#define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57
+
 /* Must be kept compact -- no holes and well documented */
 
 /**
-- 
2.25.1

[Intel-gfx] [PATCH v5 04/16] drm/i915/perf: Determine gen12 oa ctx offset at runtime

[Umesh Nerlige Ramappa]

Some SKUs of same gen12 platform may have different oactxctrl
offsets. For gen12, determine oactxctrl offsets at runtime.

v2: (Lionel)
- Move MI definitions to intel_gpu_commands.h
- Ensure __find_reg_in_lri does read past context image size

v3: (Ashutosh)
- Drop unnecessary use of double underscores
- fix find_reg_in_lri
- Return error if oa context offset is U32_MAX
- Error out if oa_ctx_ctrl_offset does not find offset

v4: (Ashutosh)
- Warn on odd MI LRI_LEN
- Remove unnecessary check for valid_oactxctrl_offset
- Drop valid_oactxctrl_offset macro

v5: Drop unrelated comment

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h |   4 +
 drivers/gpu/drm/i915/i915_perf.c | 146 ---
 drivers/gpu/drm/i915/i915_perf_oa_regs.h |   2 +-
 3 files changed, 127 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h 
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index d4e9702d3c8e..f50ea92910d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -187,6 +187,10 @@
 #define   MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
 #define   MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/
 
+#define MI_OPCODE(x)   (((x) >> 23) & 0x3f)
+#define IS_MI_LRI_CMD(x)   (MI_OPCODE(x) == MI_OPCODE(MI_INSTR(0x22, 0)))
+#define MI_LRI_LEN(x)  (((x) & 0xff) + 1)
+
 /*
  * 3D instructions used by the kernel
  */
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e68666b44a72..b71b5cf21176 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1356,6 +1356,74 @@ static int gen12_get_render_context_id(struct 
i915_perf_stream *stream)
return 0;
 }
 
+static bool oa_find_reg_in_lri(u32 *state, u32 reg, u32 *offset, u32 end)
+{
+   u32 idx = *offset;
+   u32 len = min(MI_LRI_LEN(state[idx]) + idx, end);
+   bool found = false;
+
+   idx++;
+   for (; idx < len; idx += 2) {
+   if (state[idx] == reg) {
+   found = true;
+   break;
+   }
+   }
+
+   *offset = idx;
+   return found;
+}
+
+static u32 oa_context_image_offset(struct intel_context *ce, u32 reg)
+{
+   u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
+   u32 *state = ce->lrc_reg_state;
+
+   for (offset = 0; offset < len; ) {
+   if (IS_MI_LRI_CMD(state[offset])) {
+   /*
+* We expect reg-value pairs in MI_LRI command, so
+* MI_LRI_LEN() should be even, if not, issue a warning.
+*/
+   drm_WARN_ON(&ce->engine->i915->drm,
+   MI_LRI_LEN(state[offset]) & 0x1);
+
+   if (oa_find_reg_in_lri(state, reg, &offset, len))
+   break;
+   } else {
+   offset++;
+   }
+   }
+
+   return offset < len ? offset : U32_MAX;
+}
+
+static int set_oa_ctx_ctrl_offset(struct intel_context *ce)
+{
+   i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);
+   struct i915_perf *perf = &ce->engine->i915->perf;
+   u32 offset = perf->ctx_oactxctrl_offset;
+
+   /* Do this only once. Failure is stored as offset of U32_MAX */
+   if (offset)
+   goto exit;
+
+   offset = oa_context_image_offset(ce, i915_mmio_reg_offset(reg));
+   perf->ctx_oactxctrl_offset = offset;
+
+   drm_dbg(&ce->engine->i915->drm,
+   "%s oa ctx control at 0x%08x dword offset\n",
+   ce->engine->name, offset);
+
+exit:
+   return offset && offset != U32_MAX ? 0 : -ENODEV;
+}
+
+static bool engine_supports_mi_query(struct intel_engine_cs *engine)
+{
+   return engine->class == RENDER_CLASS;
+}
+
 /**
  * oa_get_render_ctx_id - determine and hold ctx hw id
  * @stream: An i915-perf stream opened for OA metrics
@@ -1375,6 +1443,21 @@ static int oa_get_render_ctx_id(struct i915_perf_stream 
*stream)
if (IS_ERR(ce))
return PTR_ERR(ce);
 
+   if (engine_supports_mi_query(stream->engine)) {
+   /*
+* We are enabling perf query here. If we don't find the context
+* offset here, just return an error.
+*/
+   ret = set_oa_ctx_ctrl_offset(ce);
+   if (ret) {
+   intel_context_unpin(ce);
+   drm_err(&stream->perf->i915->drm,
+   "Enabling perf query failed for %s\n",
+   stream->engine->name);
+   return ret;
+   }
+   }
+
switch (GRAPHICS_VER(ce->engine->i915)) {
case 7: {
/*
@@ -2406,10 +2489,11 @@ static int gen12_configure_oar_context(

[Intel-gfx] [PATCH v5 09/16] drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers

[Umesh Nerlige Ramappa]

User passes uabi engine class and instance to the perf OA interface. Use
gt corresponding to the engine to pin the buffers to the right ggtt.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_perf.c | 21 +++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 9a00398ae25f..2c8727253f0d 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1754,6 +1754,7 @@ static void gen12_init_oa_buffer(struct i915_perf_stream 
*stream)
 static int alloc_oa_buffer(struct i915_perf_stream *stream)
 {
struct drm_i915_private *i915 = stream->perf->i915;
+   struct intel_gt *gt = stream->engine->gt;
struct drm_i915_gem_object *bo;
struct i915_vma *vma;
int ret;
@@ -1773,11 +1774,22 @@ static int alloc_oa_buffer(struct i915_perf_stream 
*stream)
i915_gem_object_set_cache_coherency(bo, I915_CACHE_LLC);
 
/* PreHSW required 512K alignment, HSW requires 16M */
-   vma = i915_gem_object_ggtt_pin(bo, NULL, 0, SZ_16M, 0);
+   vma = i915_vma_instance(bo, >->ggtt->vm, NULL);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
goto err_unref;
}
+
+   /*
+* PreHSW required 512K alignment.
+* HSW and onwards, align to requested size of OA buffer.
+*/
+   ret = i915_vma_pin(vma, 0, SZ_16M, PIN_GLOBAL | PIN_HIGH);
+   if (ret) {
+   drm_err(>->i915->drm, "Failed to pin OA buffer %d\n", ret);
+   goto err_unref;
+   }
+
stream->oa_buffer.vma = vma;
 
stream->oa_buffer.vaddr =
@@ -1827,6 +1839,7 @@ static u32 *save_restore_register(struct i915_perf_stream 
*stream, u32 *cs,
 static int alloc_noa_wait(struct i915_perf_stream *stream)
 {
struct drm_i915_private *i915 = stream->perf->i915;
+   struct intel_gt *gt = stream->engine->gt;
struct drm_i915_gem_object *bo;
struct i915_vma *vma;
const u64 delay_ticks = 0x -
@@ -1867,12 +1880,16 @@ static int alloc_noa_wait(struct i915_perf_stream 
*stream)
 * multiple OA config BOs will have a jump to this address and it
 * needs to be fixed during the lifetime of the i915/perf stream.
 */
-   vma = i915_gem_object_ggtt_pin_ww(bo, &ww, NULL, 0, 0, PIN_HIGH);
+   vma = i915_vma_instance(bo, >->ggtt->vm, NULL);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
goto out_ww;
}
 
+   ret = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
+   if (ret)
+   goto out_ww;
+
batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
if (IS_ERR(batch)) {
ret = PTR_ERR(batch);
-- 
2.25.1

[Intel-gfx] [PATCH v5 01/16] drm/i915/perf: Fix OA filtering logic for GuC mode

[Umesh Nerlige Ramappa]

With GuC mode of submission, GuC is in control of defining the context
id field that is part of the OA reports. To filter reports, UMD and KMD
must know what sw context id was chosen by GuC. There is not interface
between KMD and GuC to determine this, so read the upper-dword of
EXECLIST_STATUS to filter/squash OA reports for the specific context.

v2: Explain guc id stealing w.r.t OA use case

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_lrc.h |   2 +
 drivers/gpu/drm/i915/i915_perf.c| 144 
 2 files changed, 127 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h 
b/drivers/gpu/drm/i915/gt/intel_lrc.h
index a390f0813c8b..7111bae759f3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -110,6 +110,8 @@ enum {
 #define XEHP_SW_CTX_ID_WIDTH   16
 #define XEHP_SW_COUNTER_SHIFT  58
 #define XEHP_SW_COUNTER_WIDTH  6
+#define GEN12_GUC_SW_CTX_ID_SHIFT  39
+#define GEN12_GUC_SW_CTX_ID_WIDTH  16
 
 static inline void lrc_runtime_start(struct intel_context *ce)
 {
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 15816df916c7..255335868b6a 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1231,6 +1231,128 @@ static struct intel_context *oa_pin_context(struct 
i915_perf_stream *stream)
return stream->pinned_ctx;
 }
 
+static int
+__store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
+{
+   u32 *cs, cmd;
+
+   cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
+   if (GRAPHICS_VER(rq->engine->i915) >= 8)
+   cmd++;
+
+   cs = intel_ring_begin(rq, 4);
+   if (IS_ERR(cs))
+   return PTR_ERR(cs);
+
+   *cs++ = cmd;
+   *cs++ = i915_mmio_reg_offset(reg);
+   *cs++ = ggtt_offset;
+   *cs++ = 0;
+
+   intel_ring_advance(rq, cs);
+
+   return 0;
+}
+
+static int
+__read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset)
+{
+   struct i915_request *rq;
+   int err;
+
+   rq = i915_request_create(ce);
+   if (IS_ERR(rq))
+   return PTR_ERR(rq);
+
+   i915_request_get(rq);
+
+   err = __store_reg_to_mem(rq, reg, ggtt_offset);
+
+   i915_request_add(rq);
+   if (!err && i915_request_wait(rq, 0, HZ / 2) < 0)
+   err = -ETIME;
+
+   i915_request_put(rq);
+
+   return err;
+}
+
+static int
+gen12_guc_sw_ctx_id(struct intel_context *ce, u32 *ctx_id)
+{
+   struct i915_vma *scratch;
+   u32 *val;
+   int err;
+
+   scratch = 
__vm_create_scratch_for_read_pinned(&ce->engine->gt->ggtt->vm, 4);
+   if (IS_ERR(scratch))
+   return PTR_ERR(scratch);
+
+   err = i915_vma_sync(scratch);
+   if (err)
+   goto err_scratch;
+
+   err = __read_reg(ce, RING_EXECLIST_STATUS_HI(ce->engine->mmio_base),
+i915_ggtt_offset(scratch));
+   if (err)
+   goto err_scratch;
+
+   val = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);
+   if (IS_ERR(val)) {
+   err = PTR_ERR(val);
+   goto err_scratch;
+   }
+
+   *ctx_id = *val;
+   i915_gem_object_unpin_map(scratch->obj);
+
+err_scratch:
+   i915_vma_unpin_and_release(&scratch, 0);
+   return err;
+}
+
+/*
+ * For execlist mode of submission, pick an unused context id
+ * 0 - (NUM_CONTEXT_TAG -1) are used by other contexts
+ * XXX_MAX_CONTEXT_HW_ID is used by idle context
+ *
+ * For GuC mode of submission read context id from the upper dword of the
+ * EXECLIST_STATUS register. Note that we read this value only once and expect
+ * that the value stays fixed for the entire OA use case. There are cases where
+ * GuC KMD implementation may deregister a context to reuse it's context id, 
but
+ * we prevent that from happening to the OA context by pinning it.
+ */
+static int gen12_get_render_context_id(struct i915_perf_stream *stream)
+{
+   u32 ctx_id, mask;
+   int ret;
+
+   if (intel_engine_uses_guc(stream->engine)) {
+   ret = gen12_guc_sw_ctx_id(stream->pinned_ctx, &ctx_id);
+   if (ret)
+   return ret;
+
+   mask = ((1U << GEN12_GUC_SW_CTX_ID_WIDTH) - 1) <<
+   (GEN12_GUC_SW_CTX_ID_SHIFT - 32);
+   } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 50)) {
+   ctx_id = (XEHP_MAX_CONTEXT_HW_ID - 1) <<
+   (XEHP_SW_CTX_ID_SHIFT - 32);
+
+   mask = ((1U << XEHP_SW_CTX_ID_WIDTH) - 1) <<
+   (XEHP_SW_CTX_ID_SHIFT - 32);
+   } else {
+   ctx_id = (GEN12_MAX_CONTEXT_HW_ID - 1) <<
+(GEN11_SW_CTX_ID_SHIFT - 32);
+
+   mask = ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) 

[Intel-gfx] [PATCH v5 07/16] drm/i915/perf: Move gt-specific data from i915->perf to gt->perf

[Umesh Nerlige Ramappa]

Make perf part of gt as the OAG buffer is specific to a gt. The refactor
eventually simplifies programming the right OA buffer and the right HW
registers when supporting multiple gts.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Lionel Landwerlin 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_gt_types.h   |  3 +
 drivers/gpu/drm/i915/gt/intel_sseu.c   |  4 +-
 drivers/gpu/drm/i915/i915_perf.c   | 75 +-
 drivers/gpu/drm/i915/i915_perf_types.h | 39 +--
 drivers/gpu/drm/i915/selftests/i915_perf.c | 16 +++--
 5 files changed, 80 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 64aa2ba624fc..6f686a4244f0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -20,6 +20,7 @@
 #include "intel_gsc.h"
 
 #include "i915_vma.h"
+#include "i915_perf_types.h"
 #include "intel_engine_types.h"
 #include "intel_gt_buffer_pool_types.h"
 #include "intel_hwconfig.h"
@@ -289,6 +290,8 @@ struct intel_gt {
/* sysfs defaults per gt */
struct gt_defaults defaults;
struct kobject *sysfs_defaults;
+
+   struct i915_perf_gt perf;
 };
 
 struct intel_gt_definition {
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c 
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 66f21c735d54..6c6198a257ac 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -677,8 +677,8 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
 * If i915/perf is active, we want a stable powergating configuration
 * on the system. Use the configuration pinned by i915/perf.
 */
-   if (i915->perf.exclusive_stream)
-   req_sseu = &i915->perf.sseu;
+   if (gt->perf.exclusive_stream)
+   req_sseu = >->perf.sseu;
 
slices = hweight8(req_sseu->slice_mask);
subslices = hweight8(req_sseu->subslice_mask);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 75d320b2c1f8..83c5dc043261 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1565,8 +1565,9 @@ free_noa_wait(struct i915_perf_stream *stream)
 static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
 {
struct i915_perf *perf = stream->perf;
+   struct intel_gt *gt = stream->engine->gt;
 
-   if (WARN_ON(stream != perf->exclusive_stream))
+   if (WARN_ON(stream != gt->perf.exclusive_stream))
return;
 
/*
@@ -1575,7 +1576,7 @@ static void i915_oa_stream_destroy(struct 
i915_perf_stream *stream)
 *
 * See i915_oa_init_reg_state() and lrc_configure_all_contexts()
 */
-   WRITE_ONCE(perf->exclusive_stream, NULL);
+   WRITE_ONCE(gt->perf.exclusive_stream, NULL);
perf->ops.disable_metric_set(stream);
 
free_oa_buffer(stream);
@@ -2566,10 +2567,11 @@ oa_configure_all_contexts(struct i915_perf_stream 
*stream,
 {
struct drm_i915_private *i915 = stream->perf->i915;
struct intel_engine_cs *engine;
+   struct intel_gt *gt = stream->engine->gt;
struct i915_gem_context *ctx, *cn;
int err;
 
-   lockdep_assert_held(&stream->perf->lock);
+   lockdep_assert_held(>->perf.lock);
 
/*
 * The OA register config is setup through the context image. This image
@@ -3090,6 +3092,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 {
struct drm_i915_private *i915 = stream->perf->i915;
struct i915_perf *perf = stream->perf;
+   struct intel_gt *gt;
int format_size;
int ret;
 
@@ -3098,6 +3101,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
"OA engine not specified\n");
return -EINVAL;
}
+   gt = props->engine->gt;
 
/*
 * If the sysfs metrics/ directory wasn't registered for some
@@ -3128,7 +3132,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 * counter reports and marshal to the appropriate client
 * we currently only allow exclusive access
 */
-   if (perf->exclusive_stream) {
+   if (gt->perf.exclusive_stream) {
drm_dbg(&stream->perf->i915->drm,
"OA unit already in use\n");
return -EBUSY;
@@ -3208,8 +3212,8 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 
stream->ops = &i915_oa_stream_ops;
 
-   perf->sseu = props->sseu;
-   WRITE_ONCE(perf->exclusive_stream, stream);
+   stream->engine->gt->perf.sseu = props->sseu;
+   WRITE_ONCE(gt->perf.exclusive_stream, stream);
 
ret = i915_perf_stream_enable_sync(stream);
if (ret) {
@@ -3231,7 +3235,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
return 0;
 
 err_enable:
-   WRITE_ONCE(perf->exclusive_s

[Intel-gfx] [PATCH v5 13/16] drm/i915/perf: Save/restore EU flex counters across reset

[Umesh Nerlige Ramappa]

If a drm client is killed, then hw contexts used by the client are reset
immediately. This reset clears the EU flex counter configuration. If an
OA use case is running in parallel, it would start seeing zeroed eu
counter values following the reset even if the drm client is restarted.
Save/restore the EU flex counter config so that the EU counters can be
monitored continuously across resets.

v2:
- Save/restore eu flex config only for gen12, as for pre-gen12, these
  are saved and restored in the context image.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 34ef4f36e660..a419d60166c8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -392,6 +392,16 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
else
ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), 
false);
 
+   if (GRAPHICS_VER(engine->i915) >= 12) {
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL0, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL1, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL2, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL3, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL4, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL5, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL6, false);
+   }
+
return ret ? -1 : 0;
 }
 
-- 
2.25.1

[Intel-gfx] [PATCH v5 02/16] drm/i915/perf: Add 32-bit OAG and OAR formats for DG2

[Umesh Nerlige Ramappa]

Add new OA formats for DG2.

MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893

v2:
- Update commit title (Ashutosh)
- Coding style fixes (Lionel)
- 64 bit OA formats need UMD changes in GPUvis, drop for now and send in a
  separate series with UMD changes

v3:
- Update commit message to drop 64 bit related description

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Lionel Landwerlin  #1
---
 drivers/gpu/drm/i915/i915_perf.c | 7 +++
 include/uapi/drm/i915_drm.h  | 4 
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 255335868b6a..2b772a6b1cd6 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -320,6 +320,8 @@ static const struct i915_oa_format 
oa_formats[I915_OA_FORMAT_MAX] = {
[I915_OA_FORMAT_A12]= { 0, 64 },
[I915_OA_FORMAT_A12_B8_C8]  = { 2, 128 },
[I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
+   [I915_OAR_FORMAT_A32u40_A4u32_B8_C8]= { 5, 256 },
+   [I915_OA_FORMAT_A24u40_A14u32_B8_C8]= { 5, 256 },
 };
 
 #define SAMPLE_OA_REPORT  (1<<0)
@@ -4515,6 +4517,11 @@ static void oa_init_supported_formats(struct i915_perf 
*perf)
oa_format_add(perf, I915_OA_FORMAT_C4_B8);
break;
 
+   case INTEL_DG2:
+   oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
+   oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
+   break;
+
default:
MISSING_CASE(platform);
}
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 2e613109356b..158b35fb28f3 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2666,6 +2666,10 @@ enum drm_i915_oa_format {
I915_OA_FORMAT_A12_B8_C8,
I915_OA_FORMAT_A32u40_A4u32_B8_C8,
 
+   /* DG2 */
+   I915_OAR_FORMAT_A32u40_A4u32_B8_C8,
+   I915_OA_FORMAT_A24u40_A14u32_B8_C8,
+
I915_OA_FORMAT_MAX  /* non-ABI */
 };
 
-- 
2.25.1

[Intel-gfx] [PATCH v5 16/16] drm/i915/perf: Enable OA for DG2

[Umesh Nerlige Ramappa]

OA was disabled for DG2 as support was missing. Enable it back now.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_perf.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 176442d5e57e..3438cff13f38 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4798,12 +4798,6 @@ void i915_perf_init(struct drm_i915_private *i915)
 {
struct i915_perf *perf = &i915->perf;
 
-   /* XXX const struct i915_perf_ops! */
-
-   /* i915_perf is not enabled for DG2 yet */
-   if (IS_DG2(i915))
-   return;
-
perf->oa_formats = oa_formats;
if (IS_HASWELL(i915)) {
perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;
-- 
2.25.1

[Intel-gfx] [PATCH v5 00/16] Add DG2 OA support

[Umesh Nerlige Ramappa]

Add OA format support for DG2 and various fixes for DG2.

This series has 2 uapi changes listed below:

1) drm/i915/perf: Add OAG and OAR formats for DG2

DG2 has new OA formats defined that can be selected by the
user. The UMD changes that are consumed by GPUvis are:
https://patchwork.freedesktop.org/patch/504456/?series=107633&rev=5

Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893

2) drm/i915/perf: Apply Wa_18013179988

DG2 has a bug where the OA timestamp does not tick at the CS timestamp
frequency. Instead it ticks at a multiple that is determined from the
CTC_SHIFT value in RPM_CONFIG. Since the timestamp is used by UMD to
make sense of all the counters in the report, expose the OA timestamp
frequency to the user. The interface is generic and applies to all
platforms. On platforms where the bug is not present, this returns the
CS timestamp frequency. UMD specific changes consumed by GPUvis are:
https://patchwork.freedesktop.org/patch/504464/?series=107633&rev=5

Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893

v2:
- Add review comments
- Update uapi changes in cover letter
- Drop patches for non-production platforms
drm/i915/perf: Use helpers to process reports w.r.t. OA buffer size
drm/i915/perf: Add Wa_16010703925:dg2

- Drop 64-bit OA format changes for now
drm/i915/perf: Parse 64bit report header formats correctly
drm/i915/perf: Add Wa_1608133521:dg2

v3:
- Add review comments to patches 02, 04, 05, 14
- Drop Acks

v4:
- Add review comments to patch 04
- Update R-bs
- Add MR links to patches 02 and 12

v5:
- Drop unrelated comment
- Rebase and fix MCR reg write
- On pre-gen12, EU flex config is saved/restored in the context image, so
  save/restore EU flex config only for gen12.

Test-with: 20220923195224.283045-1-umesh.nerlige.rama...@intel.com
Signed-off-by: Umesh Nerlige Ramappa 

Lionel Landwerlin (1):
  drm/i915/perf: complete programming whitelisting for XEHPSDV

Umesh Nerlige Ramappa (14):
  drm/i915/perf: Fix OA filtering logic for GuC mode
  drm/i915/perf: Add 32-bit OAG and OAR formats for DG2
  drm/i915/perf: Fix noa wait predication for DG2
  drm/i915/perf: Determine gen12 oa ctx offset at runtime
  drm/i915/perf: Enable bytes per clock reporting in OA
  drm/i915/perf: Simply use stream->ctx
  drm/i915/perf: Move gt-specific data from i915->perf to gt->perf
  drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops
  drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers
  drm/i915/perf: Store a pointer to oa_format in oa_buffer
  drm/i915/perf: Add Wa_1508761755:dg2
  drm/i915/perf: Apply Wa_18013179988
  drm/i915/perf: Save/restore EU flex counters across reset
  drm/i915/perf: Enable OA for DG2

Vinay Belgaumkar (1):
  drm/i915/guc: Support OA when Wa_16011777198 is enabled

 drivers/gpu/drm/i915/gt/intel_engine_regs.h   |   1 +
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h  |   4 +
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   |   1 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h  |   3 +
 drivers/gpu/drm/i915/gt/intel_lrc.h   |   2 +
 drivers/gpu/drm/i915/gt/intel_sseu.c  |   4 +-
 .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h |   9 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c|  10 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   |  66 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h   |   2 +
 drivers/gpu/drm/i915/i915_drv.h   |   5 +
 drivers/gpu/drm/i915/i915_getparam.c  |   3 +
 drivers/gpu/drm/i915/i915_pci.c   |   2 +
 drivers/gpu/drm/i915/i915_perf.c  | 576 ++
 drivers/gpu/drm/i915/i915_perf.h  |   2 +
 drivers/gpu/drm/i915/i915_perf_oa_regs.h  |   6 +-
 drivers/gpu/drm/i915/i915_perf_types.h|  47 +-
 drivers/gpu/drm/i915/intel_device_info.h  |   2 +
 drivers/gpu/drm/i915/selftests/i915_perf.c|  16 +-
 include/uapi/drm/i915_drm.h   |  10 +
 20 files changed, 630 insertions(+), 141 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH] drm/i915/slpc: Optmize waitboost for SLPC

[Vinay Belgaumkar]

Waitboost (when SLPC is enabled) results in a H2G message. This can result
in thousands of messages during a stress test and fill up an already full
CTB. There is no need to request for RP0 if GuC is already requesting the
same.

Signed-off-by: Vinay Belgaumkar 
---
 drivers/gpu/drm/i915/gt/intel_rps.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index fc23c562d9b2..a20ae4fceac8 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1005,13 +1005,20 @@ void intel_rps_dec_waiters(struct intel_rps *rps)
 void intel_rps_boost(struct i915_request *rq)
 {
struct intel_guc_slpc *slpc;
+   struct intel_rps *rps = &READ_ONCE(rq->engine)->gt->rps;
 
if (i915_request_signaled(rq) || i915_request_has_waitboost(rq))
return;
 
+   /* If GuC is already requesting RP0, skip */
+   if (rps_uses_slpc(rps)) {
+   slpc = rps_to_slpc(rps);
+   if (intel_rps_get_requested_frequency(rps) == slpc->rp0_freq)
+   return;
+   }
+
/* Serializes with i915_request_retire() */
if (!test_and_set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags)) {
-   struct intel_rps *rps = &READ_ONCE(rq->engine)->gt->rps;
 
if (rps_uses_slpc(rps)) {
slpc = rps_to_slpc(rps);
-- 
2.35.1

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pvc: Update forcewake domain for CCS register ranges

[Matt Roper]

On Sat, Oct 15, 2022 at 02:01:50AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/pvc: Update forcewake domain for CCS register ranges
> URL   : https://patchwork.freedesktop.org/series/109734/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_12242_full -> Patchwork_109734v1_full
> 
> 
> Summary
> ---
> 
>   **WARNING**
> 
>   Minor unknown changes coming with Patchwork_109734v1_full need to be 
> verified
>   manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_109734v1_full, please notify your bug team to allow 
> them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (9 -> 11)
> --
> 
>   Additional (2): shard-rkl shard-dg1 
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_109734v1_full:
> 
> ### IGT changes ###
> 
>  Warnings 
> 
>   * igt@runner@aborted:
> - shard-skl:  ([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4]) 
> ([i915#3002] / [i915#4312] / [i915#6949]) -> ([FAIL][5], [FAIL][6], 
> [FAIL][7], [FAIL][8]) ([i915#3002] / [i915#4312])
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl6/igt@run...@aborted.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl6/igt@run...@aborted.html
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl4/igt@run...@aborted.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl10/igt@run...@aborted.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109734v1/shard-skl3/igt@run...@aborted.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109734v1/shard-skl6/igt@run...@aborted.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109734v1/shard-skl4/igt@run...@aborted.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109734v1/shard-skl6/igt@run...@aborted.html

The PVC forcewake changes would not impact SKL behavior.  Patch applied
to drm-intel-gt-next.  Thanks Harish for the review.


Matt

> 
>   
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * igt@gem_busy@close-race:
> - {shard-rkl}:NOTRUN -> [INCOMPLETE][9]
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109734v1/shard-rkl-5/igt@gem_b...@close-race.html
> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_109734v1_full that come from known 
> issues:
> 
> ### CI changes ###
> 
>  Possible fixes 
> 
>   * boot:
> - shard-skl:  ([PASS][10], [PASS][11], [PASS][12], [PASS][13], 
> [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], 
> [PASS][20], [FAIL][21], [PASS][22], [FAIL][23], [PASS][24], [PASS][25], 
> [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], 
> [PASS][32], [PASS][33], [PASS][34]) ([i915#5032]) -> ([PASS][35], [PASS][36], 
> [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
> [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], 
> [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53])
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl9/boot.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl9/boot.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl9/boot.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl9/boot.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl7/boot.html
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl7/boot.html
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl7/boot.html
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl6/boot.html
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl6/boot.html
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl6/boot.html
>[20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl5/boot.html
>[21]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl5/boot.html
>[22]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl5/boot.html
>[23]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl5/boot.html
>[24]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl4/boot.html
>[25]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl4/boot.html
>[26]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl4/boot.html
>[27]: 
> https://intel-gfx-ci.01.org/tree

Re: [Intel-gfx] [PATCH] drm/i915/pvc: Update forcewake domain for CCS register ranges

[Chegondi, Harish]

On Fri, 2022-10-14 at 16:30 -0700, Matt Roper wrote:
> The bspec was just updated with a correction to the forcewake domain
> required when accessing registers in the CCS engine ranges (0x1a000 -
> 0x1 and 0x26000 - 0x27fff) on PVC; these ranges require a wake on
> the RENDER domain, not the GT domain.
> 
> Bspec: 67609
> Signed-off-by: Matt Roper 

Reviewed-by: Harish Chegondi 

>  drivers/gpu/drm/i915/intel_uncore.c | 22 --
>  1 file changed, 12 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index c058cdc6d8a0..2a3e2869fe71 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1682,25 +1682,27 @@ static const struct intel_forcewake_range
> __pvc_fw_ranges[] = {
> GEN_FW_RANGE(0x12000, 0x12fff, 0), /*
> 0x12000 - 0x127ff: always on
> 0x12800 - 0x12fff: reserved */
> -   GEN_FW_RANGE(0x13000, 0x23fff, FORCEWAKE_GT), /*
> +   GEN_FW_RANGE(0x13000, 0x19fff, FORCEWAKE_GT), /*
> 0x13000 - 0x135ff: gt
> 0x13600 - 0x147ff: reserved
> 0x14800 - 0x153ff: gt
> -   0x15400 - 0x19fff: reserved
> -   0x1a000 - 0x1: gt
> -   0x2 - 0x21fff: reserved
> -   0x22000 - 0x23fff: gt */
> +   0x15400 - 0x19fff: reserved */
> +   GEN_FW_RANGE(0x1a000, 0x21fff, FORCEWAKE_RENDER), /*
> +   0x1a000 - 0x1: render
> +   0x2 - 0x21fff: reserved */
> +   GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
> GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
> 24000 - 0x2407f: always on
> 24080 - 0x2417f: reserved */
> -   GEN_FW_RANGE(0x24180, 0x3, FORCEWAKE_GT), /*
> +   GEN_FW_RANGE(0x24180, 0x25fff, FORCEWAKE_GT), /*
> 0x24180 - 0x241ff: gt
> 0x24200 - 0x251ff: reserved
> 0x25200 - 0x252ff: gt
> -   0x25300 - 0x25fff: reserved
> -   0x26000 - 0x27fff: gt
> -   0x28000 - 0x2: reserved
> -   0x3 - 0x3: gt */
> +   0x25300 - 0x25fff: reserved */
> +   GEN_FW_RANGE(0x26000, 0x2, FORCEWAKE_RENDER), /*
> +   0x26000 - 0x27fff: render
> +   0x28000 - 0x2: reserved */
> +   GEN_FW_RANGE(0x3, 0x3, FORCEWAKE_GT),
> GEN_FW_RANGE(0x4, 0x1b, 0),
> GEN_FW_RANGE(0x1c, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
> 0x1c - 0x1c2bff: VD0

Re: [Intel-gfx] [PATCH v5 20/22] drm/vc4: vec: Convert to the new TV mode property

[Mateusz Kwiatkowski]

Hi Maxime,

W dniu 18.10.2022 o 12:00, Maxime Ripard pisze:
> On Mon, Oct 17, 2022 at 12:31:31PM +0200, Noralf Trønnes wrote:
>> Den 16.10.2022 20.52, skrev Mateusz Kwiatkowski:
  static int vc4_vec_connector_get_modes(struct drm_connector *connector)
  {
 -  struct drm_connector_state *state = connector->state;
struct drm_display_mode *mode;
  
 -  mode = drm_mode_duplicate(connector->dev,
 -vc4_vec_tv_modes[state->tv.legacy_mode].mode);
 +  mode = drm_mode_analog_ntsc_480i(connector->dev);
if (!mode) {
DRM_ERROR("Failed to create a new display mode\n");
return -ENOMEM;
}
  
 +  mode->type |= DRM_MODE_TYPE_PREFERRED;
drm_mode_probed_add(connector, mode);
  
 -  return 1;
 +  mode = drm_mode_analog_pal_576i(connector->dev);
 +  if (!mode) {
 +  DRM_ERROR("Failed to create a new display mode\n");
 +  return -ENOMEM;
 +  }
 +
 +  drm_mode_probed_add(connector, mode);
 +
 +  return 2;
 +}
>>>
>>> Referencing those previous discussions:
>>> - 
>>> https://lore.kernel.org/dri-devel/0255f7c6-0484-6456-350d-cf24f3fee...@tronnes.org/
>>> - 
>>> https://lore.kernel.org/dri-devel/c8f8015a-75da-afa8-ca7f-b2b134cac...@gmail.com/
>>>
>>> Unconditionally setting the 480i mode as DRM_MODE_TYPE_PREFERRED causes Xorg
>>> (at least on current Raspberry Pi OS) to display garbage when
>>> video=Composite1:PAL is specified on the command line, so I'm afraid this 
>>> won't
>>> do.
>>>
>>> As I see it, there are three viable solutions for this issue:
>>>
>>> a) Somehow query the video= command line option from this function, and set
>>>DRM_MODE_TYPE_PREFERRED appropriately. This would break the abstraction
>>>provided by global DRM code, but should work fine.
>>>
>>> b) Modify drm_helper_probe_add_cmdline_mode() so that it sets
>>>DRM_MODE_TYPE_PREFERRED in addition to DRM_MODE_TYPE_USERDEF. This seems
>>>pretty robust, but affects the entire DRM subsystem, which may break
>>>userspace in different ways.
>>>
>>>- Maybe this could be mitigated by adding some additional conditions, 
>>> e.g.
>>>  setting the PREFERRED flag only if no modes are already flagged as such
>>>  and/or only if the cmdline mode is a named one (~= analog TV mode)
>>>
>>> c) Forcing userspace (Xorg / Raspberry Pi OS) to get fixed and honor the 
>>> USERDEF
>>>flag.
>>>
>>> Either way, hardcoding 480i as PREFERRED does not seem right.
>>>
>>
>> My solution for this is to look at tv.mode to know which mode to mark as
>> preferred. Maxime didn't like this since it changes things behind
>> userspace's back. I don't see how that can cause any problems for userspace.
>>
>> If userspace uses atomic and sets tv_mode, it has to know which mode to
>> use before hand, so it doesn't look at the preferreded flag.
>>
>> If it uses legacy and sets tv_mode, it can end up with a stale preferred
>> flag, but no worse than not having the flag or that ntsc is always
>> preferred.
>>
>> If it doesn't change tv_mode, there's no problem, the preferred flag
>> doesn't change.
>
> I don't like it because I just see no way to make this reliable. When we
> set tv_mode, we're not only going to change the preferred flag, but also
> the order of the modes to make the preferred mode first.
>
> Since we just changed the mode lists, we also want to send a hotplug
> event to userspace so that it gets notified of it. It will pick up the
> new preferred mode, great.
>
> But what if it doesn't? There's no requirement for userspace to handle
> hotplug events, and Kodi won't for example. So we just changed the TV
> mode but not the actual mode, and that's it. It's just as broken for
> Kodi as it is for X11 right now.
>
> If we can't get a bullet-proof solution, then I'm not convinced it's
> worth addressing. Especially since it's already the current state, and
> it doesn't seem to bother a lot of people.

I wouldn't rely on the "doesn't seem to bother a lot of people" bit too much.
Here's why:

- Analog TV output is a relatively obscure feature in this day and age in the
  first place.

- Out of the people interested in using it with VC4/VEC, many are actually using
  the downstream kernel from https://github.com/raspberrypi/linux instead of the
  upstream kernel, and/or firmware mode-switching instead of proper KMS.

  - The downstream kernel only reports modes that match the TV mode set at boot
either via vc4.tv_norm=, or implied by the resolution set via video=; note
that video= is also set appropriately at boot by Pi firmware, based on the
value of sdtv_mode set in config.txt. See also the
vc4_vec_connector_get_modes() and vc4_vec_get_default_mode() functions in

https://github.com/raspberrypi/linux/blob/dbd073e4028580a09b6ee507e0c137441cb52650/drivers/gpu/drm/vc4/vc4_vec.c

  - When firmware mode-switching is used, it sets the appropriate TV mode

Re: [Intel-gfx] [PATCH] drm/vc4: vec: Add support for PAL-60

[Mateusz Kwiatkowski]

Hi Maxime,

W dniu 18.10.2022 o 10:31, Maxime Ripard pisze:
> Hi,
>
> On Sun, Oct 16, 2022 at 09:46:49PM +0200, Mateusz Kwiatkowski wrote:
>> @@ -308,14 +324,15 @@ static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] 
>> = {
>>  };
>>  
>>  static inline const struct vc4_vec_tv_mode *
>> -vc4_vec_tv_mode_lookup(unsigned int mode)
>> +vc4_vec_tv_mode_lookup(unsigned int mode, u16 htotal)
>>  {
>>  unsigned int i;
>>  
>>  for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) {
>>  const struct vc4_vec_tv_mode *tv_mode = &vc4_vec_tv_modes[i];
>>  
>> -if (tv_mode->mode == mode)
>> +if (tv_mode->mode == mode &&
>> +tv_mode->expected_htotal == htotal)
>>  return tv_mode;
>
> Is there any reason we're not using the refresh rate to filter this? It
> seems more natural to me.

Let me give you an example first.

There are actually two ways to configure PAL-60-ish mode on VC4/VEC:

a) Modeline 13.5 720 734 798 858 480 487 493 525 Interlace, standard registers
   set to VEC_CONFIG0_PAL_M_STD, custom frequency enabled and set to 0x2a098acb;
   Setting the standard registers to "PAL-M" puts the VEC in true 59.94 Hz mode,
   so the video timings are identical as for NTSC (or PAL-M), and the custom
   frequency makes the color subcarrier compatible with regular PAL receivers.
   This is the "true" PAL-60, thanks to the true System M timings.

a) Modeline 13.5 720 740 804 864 480 486 492 525 Interlace, standards registers
   set to VEC_CONFIG0_PAL with standard frequency; This is a "fake" PAL-60 mode,
   the refresh rate is actually ~59.524 Hz. Most "NTSC" sets will be able to
   sync with this mode no problem, but the VEC is actually operating in its
   50 Hz mode - it's just the "premature" vertical sync signal causes it to
   output something that is similar to the 525-line system, however strictly
   speaking non-standard due to lower horizontal sync frequency.

This comes down to the fact that:

- When VEC's standard registers are set to VEC_CONFIG0_NTSC_STD or
  VEC_CONFIG0_PAL_M_STD, it operates in the "CCIR System M" mode, expects htotal
  to be exactly 858 pixels (and it will generate horizontal sync pulse every 858
  pixels on its own regardless of what comes out of the PV - so there will be
  garbage on screen if you set it to anything else), and vtotal to be 525 lines.
  It will not accept vtotal that's any higher (it will generate its own vertical
  sync as demanded by System M if not triggered by the PV), but it can be lower
  - resulting in modes that are non-standard, but otherwise valid.

- Likewise, when the registers are set to VEC_CONFIG0_PAL_BDGHI_STD,
  VEC_CONFIG0_PAL_N_STD or VEC_CONFIG0_SECAM_STD (SECAM is a bit special, but
  that's irrelevant here), it operates in the "CCIR System B/D/G/H/I/N" mode,
  and likewise, expects htotal to be exactly 864 pixels (garbage on screen
  otherwise), vtotal limit is 625 lines, etc.

Checking for the refresh rate would only work for standard-compliant modes and
have the potential of completely breaking on any custom modes. Conversely,
checking for htotal aligns perfectly with the limitations of the hardware, and
allows the user to set any modeline that the hardware is able to output with
any level of sanity.

Footnote: all this information on VEC's behavior comes from my own
experimentation, messing around with its registers and seeing what happens
(both on screen and on an oscilloscope). I've never seen any Broadcom docs on
this chip, so it's by no means official.

Best regards,
Mateusz Kwiatkowski

Re: [Intel-gfx] [PATCH v2 3/7] drm/i915/uc: use different ggtt pin offsets for uc loads

[Ceraolo Spurio, Daniele]

On 10/17/2022 4:44 PM, John Harrison wrote:

On 10/12/2022 17:03, Daniele Ceraolo Spurio wrote:

Our current FW loading process is the same for all FWs:

- Pin FW to GGTT at the start of the ggtt->uc_fw node
- Load the FW
- Unpin

This worked because we didn't have a case where 2 FWs would be loaded on
the same GGTT at the same time. On MTL, however, this can happend if 
both

GTs are reset at the same time, so we can't pin everything in the same
spot and we need to use separate offset. For simplicity, instead of
calculating the exact required size, we reserve a 2MB slot for each fw.

v2: fail fetch if FW is > 2MBs, improve comments (John)

Signed-off-by: Daniele Ceraolo Spurio 
Cc: John Harrison 
Cc: Alan Previn 
---
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 30 +---
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 13 ++
  2 files changed, 40 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c

index de2843dc1307..021290a26195 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -575,6 +575,17 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
  err = firmware_request_nowarn(&fw, uc_fw->file_selected.path, 
dev);

  memcpy(&file_ideal, &uc_fw->file_wanted, sizeof(file_ideal));
  +    if (!err && fw->size > INTEL_UC_RSVD_GGTT_PER_FW) {
+    drm_err(&i915->drm,
+    "%s firmware %s: size (%zuKB) exceeds max supported size 
(%uKB)\n",
+    intel_uc_fw_type_repr(uc_fw->type), 
uc_fw->file_selected.path,

+    fw->size / SZ_1K, INTEL_UC_RSVD_GGTT_PER_FW / SZ_1K);
+
+    /* try to find another blob to load */
+    release_firmware(fw);
+    err = -ENOENT;
+    }
+
  /* Any error is terminal if overriding. Don't bother searching 
for older versions */

  if (err && intel_uc_fw_is_overridden(uc_fw))
  goto fail;
@@ -677,14 +688,28 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
    static u32 uc_fw_ggtt_offset(struct intel_uc_fw *uc_fw)
  {
-    struct i915_ggtt *ggtt = __uc_fw_to_gt(uc_fw)->ggtt;
+    struct intel_gt *gt = __uc_fw_to_gt(uc_fw);
+    struct i915_ggtt *ggtt = gt->ggtt;
  struct drm_mm_node *node = &ggtt->uc_fw;
+    u32 offset = uc_fw->type * INTEL_UC_RSVD_GGTT_PER_FW;
+
+    /*
+ * To keep the math simple, we use 8MB for the root tile and 8MB 
for

+ * the media one. This will need to be updated if we ever have more
+ * than 1 media GT
+ */
+    BUILD_BUG_ON(INTEL_UC_FW_NUM_TYPES * INTEL_UC_RSVD_GGTT_PER_FW > 
SZ_8M);

+    GEM_BUG_ON(gt->type == GT_MEDIA && gt->info.id > 1);
+    if (gt->type == GT_MEDIA)
+    offset += SZ_8M;
This is all because render/media GTs share the same page tables? 
Regular multi-tile is completely separate address spaces and can use a 
single common address? Otherwise, it seems like 'offset = gt->info.id 
* 2M' would be the generic solution and no reference to GT_MEDIA 
required. So maybe add a quick comment to that effect?


Yup this is only because of the GGTT sharing. There is already a comment 
somewhere else, but I'll add one here as well.






GEM_BUG_ON(!drm_mm_node_allocated(node));
  GEM_BUG_ON(upper_32_bits(node->start));
  GEM_BUG_ON(upper_32_bits(node->start + node->size - 1));
+    GEM_BUG_ON(offset + uc_fw->obj->base.size > node->size);
+    GEM_BUG_ON(uc_fw->obj->base.size > INTEL_UC_RSVD_GGTT_PER_FW);
  -    return lower_32_bits(node->start);
+    return lower_32_bits(node->start + offset);
  }
    static void uc_fw_bind_ggtt(struct intel_uc_fw *uc_fw)
@@ -699,7 +724,6 @@ static void uc_fw_bind_ggtt(struct intel_uc_fw 
*uc_fw)

  dummy->bi.pages = obj->mm.pages;
    GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
-    GEM_BUG_ON(dummy->node_size > ggtt->uc_fw.size);
    /* uc_fw->obj cache domains were not controlled across 
suspend */

  if (i915_gem_object_has_struct_page(obj))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h

index cb586f7df270..7b3db41efa6e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
@@ -6,6 +6,7 @@
  #ifndef _INTEL_UC_FW_H_
  #define _INTEL_UC_FW_H_
  +#include 
  #include 
  #include "intel_uc_fw_abi.h"
  #include "intel_device_info.h"
@@ -114,6 +115,18 @@ struct intel_uc_fw {
(uc)->fw.file_selected.minor_ver, \
(uc)->fw.file_selected.patch_ver))
  +/*
+ * When we load the uC binaries, we pin them in a reserved section 
at the top of
+ * the GGTT, which is ~18 MBs. On multi-GT systems where the GTs 
share the GGTT,
^^^ meaning only systems with a render GT + media GT as opposed to 
regular multi-GT systems? Would be good to make that explicit either 
here or above (or both).


I'll add a comment above where we reference the media gt.

Daniele



John.

+ * we also need to make sure that each binary is pinned to a unique 
location
+ * during load, becau

Re: [Intel-gfx] [PATCH v4 15/17] drm/i915/vm_bind: Handle persistent vmas in execbuf3

[Niranjana Vishwanathapura]

On Tue, Oct 18, 2022 at 07:01:57PM +0100, Matthew Auld wrote:

On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:

Handle persistent (VM_BIND) mappings during the request submission
in the execbuf3 path.

v2: Ensure requests wait for bindings to complete.
v3: Remove short term pinning with PIN_VALIDATE flag.
Individualize fences before adding to dma_resv obj.

Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 .../gpu/drm/i915/gem/i915_gem_execbuffer3.c   | 208 +-
 1 file changed, 207 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
index a9b4cc44bf66..8120e4c6b7da 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
@@ -3,6 +3,7 @@
  * Copyright © 2022 Intel Corporation
  */
+#include 
 #include 
 #include 
@@ -19,6 +20,7 @@
 #include "i915_gem_vm_bind.h"
 #include "i915_trace.h"
+#define __EXEC3_HAS_PINBIT_ULL(33)
 #define __EXEC3_ENGINE_PINNED  BIT_ULL(32)
 #define __EXEC3_INTERNAL_FLAGS (~0ull << 32)
@@ -42,7 +44,9 @@
  * execlist. Hence, no support for implicit sync.
  *
  * The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only
- * works with execbuf3 ioctl for submission.
+ * works with execbuf3 ioctl for submission. All BOs mapped on that VM (through
+ * VM_BIND call) at the time of execbuf3 call are deemed required for that
+ * submission.
  *
  * The execbuf3 ioctl directly specifies the batch addresses instead of as
  * object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not
@@ -58,6 +62,13 @@
  * So, a lot of code supporting execbuf2 ioctl, like relocations, VA evictions,
  * vma lookup table, implicit sync, vma active reference tracking etc., are not
  * applicable for execbuf3 ioctl.
+ *
+ * During each execbuf submission, request fence is added to all VM_BIND mapped
+ * objects with DMA_RESV_USAGE_BOOKKEEP. The DMA_RESV_USAGE_BOOKKEEP usage will
+ * prevent over sync (See enum dma_resv_usage). Note that DRM_I915_GEM_WAIT and
+ * DRM_I915_GEM_BUSY ioctls do not check for DMA_RESV_USAGE_BOOKKEEP usage and
+ * hence should not be used for end of batch check. Instead, the execbuf3
+ * timeline out fence should be used for end of batch check.
  */
 /**
@@ -127,6 +138,23 @@ eb_find_vma(struct i915_address_space *vm, u64 addr)
return i915_gem_vm_bind_lookup_vma(vm, va);
 }
+static void eb_scoop_unbound_vma_all(struct i915_address_space *vm)
+{
+   struct i915_vma *vma, *vn;
+
+   /**
+* Move all unbound vmas back into vm_bind_list so that they are
+* revalidated.
+*/
+   spin_lock(&vm->vm_rebind_lock);
+   list_for_each_entry_safe(vma, vn, &vm->vm_rebind_list, vm_rebind_link) {
+   list_del_init(&vma->vm_rebind_link);
+   if (!list_empty(&vma->vm_bind_link))
+   list_move_tail(&vma->vm_bind_link, &vm->vm_bind_list);
+   }
+   spin_unlock(&vm->vm_rebind_lock);
+}
+
 static int eb_lookup_vma_all(struct i915_execbuffer *eb)
 {
unsigned int i, current_batch = 0;
@@ -141,14 +169,108 @@ static int eb_lookup_vma_all(struct i915_execbuffer *eb)
++current_batch;
}
+   eb_scoop_unbound_vma_all(eb->context->vm);
+
+   return 0;
+}
+
+static int eb_lock_vma_all(struct i915_execbuffer *eb)
+{
+   struct i915_address_space *vm = eb->context->vm;
+   struct i915_vma *vma;
+   int err;
+
+   err = i915_gem_object_lock(eb->context->vm->root_obj, &eb->ww);
+   if (err)
+   return err;
+
+   list_for_each_entry(vma, &vm->non_priv_vm_bind_list,
+   non_priv_vm_bind_link) {
+   err = i915_gem_object_lock(vma->obj, &eb->ww);
+   if (err)
+   return err;
+   }
+
return 0;
 }
+static void eb_release_persistent_vma_all(struct i915_execbuffer *eb)
+{
+   struct i915_address_space *vm = eb->context->vm;
+   struct i915_vma *vma, *vn;
+
+   lockdep_assert_held(&vm->vm_bind_lock);
+
+   if (!(eb->args->flags & __EXEC3_HAS_PIN))
+   return;
+
+   assert_object_held(vm->root_obj);
+
+   list_for_each_entry_safe(vma, vn, &vm->vm_bind_list, vm_bind_link)
+   if (i915_vma_verify_bind_complete(vma))
+   list_move_tail(&vma->vm_bind_link, &vm->vm_bound_list);
+
+   eb->args->flags &= ~__EXEC3_HAS_PIN;
+}
+
 static void eb_release_vma_all(struct i915_execbuffer *eb)
 {
+   eb_release_persistent_vma_all(eb);
eb_unpin_engine(eb);
 }
+static int eb_reserve_fence_for_persistent_vma_all(struct i915_execbuffer *eb)
+{
+   struct i915_address_space *vm = eb->context->vm;
+   u64 num_fences = 1;
+   struct i915_vma *vma;
+   int ret;
+
+   /* Reserve enough slots to accommodate composite fences */
+   if (intel_co

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/edid: Parse VRR cap fields from HFVSDB block

[Patchwork]

== Series Details ==

Series: drm/edid: Parse VRR cap fields from HFVSDB block
URL   : https://patchwork.freedesktop.org/series/109801/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12254_full -> Patchwork_109801v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_109801v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gen9_exec_parse@allowed-single:
- shard-tglb: NOTRUN -> [SKIP][1] ([i915#2527] / [i915#2856])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109801v1/shard-tglb7/igt@gen9_exec_pa...@allowed-single.html

  * igt@i915_selftest@live@workarounds:
- shard-tglb: NOTRUN -> [INCOMPLETE][2] ([i915#7222])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109801v1/shard-tglb7/igt@i915_selftest@l...@workarounds.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#3743])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12254/shard-tglb7/igt@kms_big...@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109801v1/shard-tglb1/igt@kms_big...@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][5] ([i915#6095])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109801v1/shard-tglb7/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][6] ([i915#3689] / [i915#3886])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109801v1/shard-tglb7/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_content_protection@content_type_change:
- shard-tglb: NOTRUN -> [SKIP][7] ([i915#7118])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109801v1/shard-tglb7/igt@kms_content_protection@content_type_change.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-tglb: NOTRUN -> [SKIP][8] ([i915#3555]) +1 similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109801v1/shard-tglb7/igt@kms_cursor_...@cursor-sliding-32x10.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-tglb: NOTRUN -> [SKIP][9] ([fdo#109274] / [fdo#111825] / 
[i915#3637])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109801v1/shard-tglb7/igt@kms_f...@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt:
- shard-tglb: NOTRUN -> [SKIP][10] ([fdo#109280] / [fdo#111825]) +2 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109801v1/shard-tglb7/igt@kms_frontbuffer_track...@fbcpsr-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-c-edp-1:
- shard-tglb: NOTRUN -> [SKIP][11] ([i915#5176]) +3 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109801v1/shard-tglb7/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0...@pipe-c-edp-1.html

  
 Possible fixes 

  * igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [FAIL][12] ([i915#6268]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12254/shard-tglb1/igt@gem_ctx_e...@basic-nohangcheck.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109801v1/shard-tglb1/igt@gem_ctx_e...@basic-nohangcheck.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][14] ([i915#2190]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12254/shard-tglb7/igt@gem_huc_c...@huc-copy.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109801v1/shard-tglb1/igt@gem_huc_c...@huc-copy.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-tglb: [FAIL][16] ([i915#3743]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12254/shard-tglb1/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109801v1/shard-tglb7/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i91

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/slpc: Use platform limits for min/max frequency (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/slpc: Use platform limits for min/max frequency (rev3)
URL   : https://patchwork.freedesktop.org/series/109632/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12257 -> Patchwork_109632v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v3/index.html

Participating hosts (41 -> 40)
--

  Additional (1): bat-adlm-1 
  Missing(2): bat-atsm-1 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_109632v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_tiled_blits@basic:
- fi-pnv-d510:[PASS][1] -> [SKIP][2] ([fdo#109271]) +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12257/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v3/fi-pnv-d510/igt@gem_tiled_bl...@basic.html

  
 Possible fixes 

  * igt@i915_module_load@reload:
- {bat-rpls-2}:   [DMESG-WARN][3] ([i915#5537]) -> [PASS][4] +1 similar 
issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12257/bat-rpls-2/igt@i915_module_l...@reload.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v3/bat-rpls-2/igt@i915_module_l...@reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#7221]: https://gitlab.freedesktop.org/drm/intel/issues/7221


Build changes
-

  * Linux: CI_DRM_12257 -> Patchwork_109632v3

  CI-20190529: 20190529
  CI_DRM_12257: b249abef9f86f788e6bacc657ae8eb7743948200 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7018: 8312a2fe3f3287ba4ac4bc8d100de0734480f482 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_109632v3: b249abef9f86f788e6bacc657ae8eb7743948200 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

e3a77a884651 drm/i915/slpc: Use platform limits for min/max frequency

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v3/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/slpc: Use platform limits for min/max frequency (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/slpc: Use platform limits for min/max frequency (rev3)
URL   : https://patchwork.freedesktop.org/series/109632/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH] drm/edid: Parse VRR cap fields from HFVSDB block

[Navare, Manasi]

On Tue, Oct 18, 2022 at 11:01:48AM +0530, Ankit Nautiyal wrote:
> This patch parses HFVSDB fields for VRR capabilities of an
> HDMI2.1 sink and stores the VRR caps in a new structure in
> drm_hdmi_info.
> 
> Signed-off-by: Ankit Nautiyal 

Makes sense to add this VRR info to drm_hdmi_info struct and not combine
with DP VRR info struct in display info since hdmi info has other HDMI
cap info stored here.

Reviewed-by: Manasi Navare 

Manasi

> ---
>  drivers/gpu/drm/drm_edid.c  | 26 --
>  include/drm/drm_connector.h | 27 +++
>  2 files changed, 51 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 47465b9765f1..bb1f7d899580 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -5823,6 +5823,21 @@ static void drm_parse_ycbcr420_deep_color_info(struct 
> drm_connector *connector,
>   hdmi->y420_dc_modes = dc_mask;
>  }
>  
> +static void drm_parse_vrr_info(struct drm_hdmi_vrr_cap *hdmi_vrr,
> +const u8 *hf_scds)
> +{
> + if (hf_scds[8] & DRM_EDID_CNMVRR)
> + hdmi_vrr->cnm_vrr = true;
> + if (hf_scds[8] & DRM_EDID_CINEMA_VRR)
> + hdmi_vrr->cinema_vrr = true;
> + if (hf_scds[8] & DRM_EDID_MDELTA)
> + hdmi_vrr->m_delta = true;
> +
> + hdmi_vrr->vrr_min = hf_scds[9] & DRM_EDID_VRR_MIN_MASK;
> + hdmi_vrr->vrr_max = (hf_scds[9] & DRM_EDID_VRR_MAX_UPPER_MASK) << 2;
> + hdmi_vrr->vrr_max |= hf_scds[10] & DRM_EDID_VRR_MAX_LOWER_MASK;
> +}
> +
>  static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
>  const u8 *hf_scds)
>  {
> @@ -5901,9 +5916,11 @@ static void drm_parse_hdmi_forum_scds(struct 
> drm_connector *connector,
>   struct drm_display_info *display = &connector->display_info;
>   struct drm_hdmi_info *hdmi = &display->hdmi;
>   struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
> + struct drm_hdmi_vrr_cap *hdmi_vrr = &hdmi->vrr_cap;
>   int max_tmds_clock = 0;
>   u8 max_frl_rate = 0;
>   bool dsc_support = false;
> + bool vrr_support = false;
>  
>   display->has_hdmi_infoframe = true;
>  
> @@ -5949,14 +5966,19 @@ static void drm_parse_hdmi_forum_scds(struct 
> drm_connector *connector,
>  
>   drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
>  
> + if (cea_db_payload_len(hf_scds) >= 8 && hf_scds[8]) {
> + drm_parse_vrr_info(hdmi_vrr, hf_scds);
> + vrr_support = true;
> + }
> +
>   if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
>   drm_parse_dsc_info(hdmi_dsc, hf_scds);
>   dsc_support = true;
>   }
>  
>   drm_dbg_kms(connector->dev,
> - "HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 
> 1.2 support: %s\n",
> - max_tmds_clock, str_yes_no(max_frl_rate), 
> str_yes_no(dsc_support));
> + "HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, VRR 
> support: %s, DSC 1.2 support: %s\n",
> + max_tmds_clock, str_yes_no(max_frl_rate), 
> str_yes_no(vrr_support), str_yes_no(dsc_support));
>  }
>  
>  static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index b1b2df48d42c..ec6ef71ab5cd 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -219,6 +219,30 @@ struct drm_hdmi_dsc_cap {
>   u8 total_chunk_kbytes;
>  };
>  
> +
> +/**
> + * struct drm_hdmi_vrr_cap - VRR capabilities of HDMI sink
> + * Describes the VRR support provided by HDMI 2.1 sink.
> + * The information is fetched fom additional HFVSDB blocks defined
> + * for HDMI 2.1.
> + */
> +struct drm_hdmi_vrr_cap {
> + /** @cnm_vrr: sink supports negative Mvrr values*/
> + bool cnm_vrr;
> +
> + /** @cinema_vrr: sink supports fractional and integer media rates < 
> VRRmin*/
> + bool cinema_vrr;
> +
> + /** @m_delta: sink can anticipate and compensate for frame-to-frame 
> variation in Mvrr */
> + bool m_delta;
> +
> + /** @vrr_min: VRRmin - lowest framerate in Hz that sink can support in 
> VRR */
> + u8 vrr_min;
> +
> + /** @vrr_max: VRRmax - highest framerate in Hz that sink can support in 
> VRR */
> + u16 vrr_max;
> +};
> +
>  /**
>   * struct drm_hdmi_info - runtime information about the connected HDMI sink
>   *
> @@ -259,6 +283,9 @@ struct drm_hdmi_info {
>  
>   /** @dsc_cap: DSC capabilities of the sink */
>   struct drm_hdmi_dsc_cap dsc_cap;
> +
> + /** @vrr_cap: VRR capabilities of the sink */
> + struct drm_hdmi_vrr_cap vrr_cap;
>  };
>  
>  /**
> -- 
> 2.25.1
> 

[Intel-gfx] [PATCH v3] drm/i915/slpc: Use platform limits for min/max frequency

[Vinay Belgaumkar]

GuC will set the min/max frequencies to theoretical max on
ATS-M. This will break kernel ABI, so limit min/max frequency
to RP0(platform max) instead.

Also modify the SLPC selftest to update the min frequency
when we have a server part so that we can iterate between
platform min and max.

v2: Check softlimits instead of platform limits (Riana)
v3: More review comments (Ashutosh)

Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7030

Acked-by: Nirmoy Das 
Reviewed-by: Riana Tauro 
Signed-off-by: Vinay Belgaumkar 
---
 drivers/gpu/drm/i915/gt/selftest_slpc.c   | 40 +--
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 30 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h   |  2 +
 .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h |  3 ++
 4 files changed, 63 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c 
b/drivers/gpu/drm/i915/gt/selftest_slpc.c
index 4c6e9257e593..e42bc215e54d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
@@ -234,6 +234,7 @@ static int run_test(struct intel_gt *gt, int test_type)
enum intel_engine_id id;
struct igt_spinner spin;
u32 slpc_min_freq, slpc_max_freq;
+   u32 saved_min_freq;
int err = 0;
 
if (!intel_uc_uses_guc_slpc(>->uc))
@@ -252,20 +253,35 @@ static int run_test(struct intel_gt *gt, int test_type)
return -EIO;
}
 
-   /*
-* FIXME: With efficient frequency enabled, GuC can request
-* frequencies higher than the SLPC max. While this is fixed
-* in GuC, we level set these tests with RPn as min.
-*/
-   err = slpc_set_min_freq(slpc, slpc->min_freq);
-   if (err)
-   return err;
+   if (slpc_min_freq == slpc_max_freq) {
+   /* Server parts will have min/max clamped to RP0 */
+   if (slpc->min_is_rpmax) {
+   err = slpc_set_min_freq(slpc, slpc->min_freq);
+   if (err) {
+   pr_err("Unable to update min freq on server 
part");
+   return err;
+   }
 
-   if (slpc->min_freq == slpc->rp0_freq) {
-   pr_err("Min/Max are fused to the same value\n");
-   return -EINVAL;
+   } else {
+   pr_err("Min/Max are fused to the same value\n");
+   return -EINVAL;
+   }
+   } else {
+   /*
+* FIXME: With efficient frequency enabled, GuC can request
+* frequencies higher than the SLPC max. While this is fixed
+* in GuC, we level set these tests with RPn as min.
+*/
+   err = slpc_set_min_freq(slpc, slpc->min_freq);
+   if (err)
+   return err;
}
 
+   saved_min_freq = slpc_min_freq;
+
+   /* New temp min freq = RPn */
+   slpc_min_freq = slpc->min_freq;
+
intel_gt_pm_wait_for_idle(gt);
intel_gt_pm_get(gt);
for_each_engine(engine, gt, id) {
@@ -347,7 +363,7 @@ static int run_test(struct intel_gt *gt, int test_type)
 
/* Restore min/max frequencies */
slpc_set_max_freq(slpc, slpc_max_freq);
-   slpc_set_min_freq(slpc, slpc_min_freq);
+   slpc_set_min_freq(slpc, saved_min_freq);
 
if (igt_flush_test(gt->i915))
err = -EIO;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index fdd895f73f9f..b7cdeec44bd3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -263,6 +263,7 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
 
slpc->max_freq_softlimit = 0;
slpc->min_freq_softlimit = 0;
+   slpc->min_is_rpmax = false;
 
slpc->boost_freq = 0;
atomic_set(&slpc->num_waiters, 0);
@@ -588,6 +589,32 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
return 0;
 }
 
+static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
+{
+   int slpc_min_freq;
+
+   if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq))
+   return false;
+
+   if (slpc_min_freq == SLPC_MAX_FREQ_MHZ)
+   return true;
+   else
+   return false;
+}
+
+static void update_server_min_softlimit(struct intel_guc_slpc *slpc)
+{
+   /* For server parts, SLPC min will be at RPMax.
+* Use min softlimit to clamp it to RP0 instead.
+*/
+   if (is_slpc_min_freq_rpmax(slpc) &&
+   !slpc->min_freq_softlimit) {
+   slpc->min_is_rpmax = true;
+   slpc->min_freq_softlimit = slpc->rp0_freq;
+   (slpc_to_gt(slpc))->defaults.min_freq = 
slpc->min_freq_softlimit;
+   }
+}
+
 static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
 {
/* Force SLPC to used platform rp0 */
@@ 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fix CFI violations in gt_sysfs (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix CFI violations in gt_sysfs (rev4)
URL   : https://patchwork.freedesktop.org/series/108917/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12257 -> Patchwork_108917v4


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_108917v4 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_108917v4, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v4/index.html

Participating hosts (41 -> 39)
--

  Additional (1): fi-icl-u2 
  Missing(3): bat-atsm-1 fi-bdw-samus fi-bsw-nick 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_108917v4:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rpm@basic-pci-d3-state:
- bat-adlp-4: [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12257/bat-adlp-4/igt@i915_pm_...@basic-pci-d3-state.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v4/bat-adlp-4/igt@i915_pm_...@basic-pci-d3-state.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_module_load@reload:
- {bat-rpls-2}:   [DMESG-WARN][3] ([i915#5537]) -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12257/bat-rpls-2/igt@i915_module_l...@reload.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v4/bat-rpls-2/igt@i915_module_l...@reload.html

  
Known issues


  Here are the changes found in Patchwork_108917v4 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v4/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v4/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_selftest@live@sanitycheck:
- fi-icl-u2:  NOTRUN -> [INCOMPLETE][7] ([i915#7222])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v4/fi-icl-u2/igt@i915_selftest@l...@sanitycheck.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][8] ([fdo#111827]) +7 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v4/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-icl-u2:  NOTRUN -> [SKIP][9] ([i915#4103])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v4/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([fdo#109285])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v4/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][11] ([i915#3555])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v4/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][12] ([fdo#109295] / [i915#3301])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v4/fi-icl-u2/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- fi-icl-u2:  NOTRUN -> [FAIL][13] ([i915#4312])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v4/fi-icl-u2/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[SKIP][14] ([fdo#109271]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12257/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v4/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: htt

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix CFI violations in gt_sysfs (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix CFI violations in gt_sysfs (rev4)
URL   : https://patchwork.freedesktop.org/series/108917/
State : warning

== Summary ==

Error: dim checkpatch failed
33f051ef3eac drm/i915: Fix CFI violations in gt_sysfs
-:123: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#123: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs.c:61:
 }
+static struct kobj_attribute attr_id = __ATTR_RO(id);

-:266: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_name' - possible 
side-effects?
#266: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:155:
+#define INTEL_GT_DUAL_ATTR_RW(_name) \
+   static struct device_attribute dev_attr_##_name = __ATTR(_name, 0644,   
\
+
_name##_dev_show,  \
+
_name##_dev_store);\
+   INTEL_GT_ATTR_RW(_name)

-:272: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_name' - possible 
side-effects?
#272: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:161:
+#define INTEL_GT_DUAL_ATTR_RO(_name) \
+   static struct device_attribute dev_attr_##_name = __ATTR(_name, 0444,   
\
+
_name##_dev_show,  \
+NULL); 
\
+   INTEL_GT_ATTR_RO(_name)

-:654: CHECK:CAMELCASE: Avoid CamelCase: 
#654: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:405:
+INTEL_GT_SYSFS_SHOW_MAX(RPn_freq_mhz);

-:662: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_mode' - possible 
side-effects?
#662: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:413:
+#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store, _show_dev, 
_store_dev)\
+   static struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, 
_mode,  \
+   _show_dev, 
_store_dev); \
+   static struct kobj_attribute attr_rps_##_name = __ATTR(rps_##_name, 
_mode,  \
+  _show, _store)

-:703: CHECK:CAMELCASE: Avoid CamelCase: 
#703: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:445:
+   &p##attr_##s##_RPn_freq_mhz.attr, \

-:840: CHECK:CAMELCASE: Avoid CamelCase: 
#840: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:675:
+INTEL_GT_ATTR_RO(media_RPn_freq_mhz);

-:850: CHECK:CAMELCASE: Avoid CamelCase: 
#850: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:681:
+   &attr_media_RPn_freq_mhz.attr,

total: 0 errors, 0 warnings, 8 checks, 785 lines checked

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/tgl+: Add locking around DKL PHY register accesses

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/tgl+: Add locking around DKL PHY 
register accesses
URL   : https://patchwork.freedesktop.org/series/109834/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12257 -> Patchwork_109834v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_109834v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109834v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109834v1/index.html

Participating hosts (41 -> 41)
--

  Additional (2): bat-adlm-1 fi-icl-u2 
  Missing(2): bat-atsm-1 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109834v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rpm@module-reload:
- fi-bdw-5557u:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12257/fi-bdw-5557u/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109834v1/fi-bdw-5557u/igt@i915_pm_...@module-reload.html

  
Known issues


  Here are the changes found in Patchwork_109834v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#7073])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12257/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109834v1/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109834v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109834v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_selftest@live@sanitycheck:
- fi-icl-u2:  NOTRUN -> [INCOMPLETE][7] ([i915#7222])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109834v1/fi-icl-u2/igt@i915_selftest@l...@sanitycheck.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][8] ([fdo#111827]) +7 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109834v1/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-icl-u2:  NOTRUN -> [SKIP][9] ([i915#4103])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109834v1/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([fdo#109285])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109834v1/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][11] ([i915#3555])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109834v1/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][12] ([fdo#109295] / [i915#3301])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109834v1/fi-icl-u2/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- fi-icl-u2:  NOTRUN -> [FAIL][13] ([i915#4312])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109834v1/fi-icl-u2/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[SKIP][14] ([fdo#109271]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12257/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109834v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}:   [DMESG-WARN][16] ([i915#5537]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12257/bat-rpls-2/igt@i915_pm_...@module-reload.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109834v1/bat-rpls-2/igt@i915_pm_...@module-reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=

Re: [Intel-gfx] [PATCH v4 15/17] drm/i915/vm_bind: Handle persistent vmas in execbuf3

[Matthew Auld]

On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:

Handle persistent (VM_BIND) mappings during the request submission
in the execbuf3 path.

v2: Ensure requests wait for bindings to complete.
v3: Remove short term pinning with PIN_VALIDATE flag.
 Individualize fences before adding to dma_resv obj.

Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
  .../gpu/drm/i915/gem/i915_gem_execbuffer3.c   | 208 +-
  1 file changed, 207 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
index a9b4cc44bf66..8120e4c6b7da 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
@@ -3,6 +3,7 @@
   * Copyright © 2022 Intel Corporation
   */
  
+#include 

  #include 
  #include 
  
@@ -19,6 +20,7 @@

  #include "i915_gem_vm_bind.h"
  #include "i915_trace.h"
  
+#define __EXEC3_HAS_PIN			BIT_ULL(33)

  #define __EXEC3_ENGINE_PINNED BIT_ULL(32)
  #define __EXEC3_INTERNAL_FLAGS(~0ull << 32)
  
@@ -42,7 +44,9 @@

   * execlist. Hence, no support for implicit sync.
   *
   * The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only
- * works with execbuf3 ioctl for submission.
+ * works with execbuf3 ioctl for submission. All BOs mapped on that VM (through
+ * VM_BIND call) at the time of execbuf3 call are deemed required for that
+ * submission.
   *
   * The execbuf3 ioctl directly specifies the batch addresses instead of as
   * object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not
@@ -58,6 +62,13 @@
   * So, a lot of code supporting execbuf2 ioctl, like relocations, VA 
evictions,
   * vma lookup table, implicit sync, vma active reference tracking etc., are 
not
   * applicable for execbuf3 ioctl.
+ *
+ * During each execbuf submission, request fence is added to all VM_BIND mapped
+ * objects with DMA_RESV_USAGE_BOOKKEEP. The DMA_RESV_USAGE_BOOKKEEP usage will
+ * prevent over sync (See enum dma_resv_usage). Note that DRM_I915_GEM_WAIT and
+ * DRM_I915_GEM_BUSY ioctls do not check for DMA_RESV_USAGE_BOOKKEEP usage and
+ * hence should not be used for end of batch check. Instead, the execbuf3
+ * timeline out fence should be used for end of batch check.
   */
  
  /**

@@ -127,6 +138,23 @@ eb_find_vma(struct i915_address_space *vm, u64 addr)
return i915_gem_vm_bind_lookup_vma(vm, va);
  }
  
+static void eb_scoop_unbound_vma_all(struct i915_address_space *vm)

+{
+   struct i915_vma *vma, *vn;
+
+   /**
+* Move all unbound vmas back into vm_bind_list so that they are
+* revalidated.
+*/
+   spin_lock(&vm->vm_rebind_lock);
+   list_for_each_entry_safe(vma, vn, &vm->vm_rebind_list, vm_rebind_link) {
+   list_del_init(&vma->vm_rebind_link);
+   if (!list_empty(&vma->vm_bind_link))
+   list_move_tail(&vma->vm_bind_link, &vm->vm_bind_list);
+   }
+   spin_unlock(&vm->vm_rebind_lock);
+}
+
  static int eb_lookup_vma_all(struct i915_execbuffer *eb)
  {
unsigned int i, current_batch = 0;
@@ -141,14 +169,108 @@ static int eb_lookup_vma_all(struct i915_execbuffer *eb)
++current_batch;
}
  
+	eb_scoop_unbound_vma_all(eb->context->vm);

+
+   return 0;
+}
+
+static int eb_lock_vma_all(struct i915_execbuffer *eb)
+{
+   struct i915_address_space *vm = eb->context->vm;
+   struct i915_vma *vma;
+   int err;
+
+   err = i915_gem_object_lock(eb->context->vm->root_obj, &eb->ww);
+   if (err)
+   return err;
+
+   list_for_each_entry(vma, &vm->non_priv_vm_bind_list,
+   non_priv_vm_bind_link) {
+   err = i915_gem_object_lock(vma->obj, &eb->ww);
+   if (err)
+   return err;
+   }
+
return 0;
  }
  
+static void eb_release_persistent_vma_all(struct i915_execbuffer *eb)

+{
+   struct i915_address_space *vm = eb->context->vm;
+   struct i915_vma *vma, *vn;
+
+   lockdep_assert_held(&vm->vm_bind_lock);
+
+   if (!(eb->args->flags & __EXEC3_HAS_PIN))
+   return;
+
+   assert_object_held(vm->root_obj);
+
+   list_for_each_entry_safe(vma, vn, &vm->vm_bind_list, vm_bind_link)
+   if (i915_vma_verify_bind_complete(vma))
+   list_move_tail(&vma->vm_bind_link, &vm->vm_bound_list);
+
+   eb->args->flags &= ~__EXEC3_HAS_PIN;
+}
+
  static void eb_release_vma_all(struct i915_execbuffer *eb)
  {
+   eb_release_persistent_vma_all(eb);
eb_unpin_engine(eb);
  }
  
+static int eb_reserve_fence_for_persistent_vma_all(struct i915_execbuffer *eb)

+{
+   struct i915_address_space *vm = eb->context->vm;
+   u64 num_fences = 1;
+   struct i915_vma *vma;
+   int ret;
+
+   /* Reserve enough slots to accommodate composite fences */
+   if (intel_context_is_parallel

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/tgl+: Add locking around DKL PHY register accesses

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/tgl+: Add locking around DKL PHY 
register accesses
URL   : https://patchwork.freedesktop.org/series/109834/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/tgl+: Add locking around DKL PHY register accesses

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/tgl+: Add locking around DKL PHY 
register accesses
URL   : https://patchwork.freedesktop.org/series/109834/
State : warning

== Summary ==

Error: dim checkpatch failed
3b99286d8d78 drm/i915/tgl+: Add locking around DKL PHY register accesses
-:160: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#160: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:398:
+   spinlock_t dkl_lock;

-:473: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'reg' - possible 
side-effects?
#473: FILE: drivers/gpu/drm/i915/i915_reg.h:7446:
+#define DKL_REG_TC_PORT(reg)   (((reg).reg - _DKL_PHY1_BASE) >> 
_DKL_BANK_SHIFT)

total: 0 errors, 0 warnings, 2 checks, 405 lines checked
a96e4b0b1cb6 drm/i915/tgl+: Move DKL PHY register definitions to 
intel_tc_phy_regs.h
-:51: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#51: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:290:
+#define DKL_REG_TC_PORT(reg)   (((reg).reg - 
_DKL_PHY1_BASE) >> _DKL_BANK_SHIFT)

-:51: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'reg' - possible side-effects?
#51: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:290:
+#define DKL_REG_TC_PORT(reg)   (((reg).reg - 
_DKL_PHY1_BASE) >> _DKL_BANK_SHIFT)

-:67: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#67: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:306:
+#define   DKL_PLL_DIV0_AFC_STARTUP(val)
REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val))

-:172: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#172: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:411:
+#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) 
REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))

-:174: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#174: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:413:
+#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) 
REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))

total: 0 errors, 4 warnings, 1 checks, 388 lines checked
003469f884e8 drm/i915/tgl+: Sanitize DKL PHY register definitions
-:317: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#317: FILE: drivers/gpu/drm/i915/display/intel_tc.c:960:
+void intel_tc_dkl_rmw(struct drm_i915_private *i915, struct intel_tc_dkl_reg 
reg, u32 clear, u32 set)

-:371: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#371: FILE: drivers/gpu/drm/i915/display/intel_tc.h:43:
+void intel_tc_dkl_rmw(struct drm_i915_private *i915, struct intel_tc_dkl_reg 
reg, u32 clear, u32 set);

-:403: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'reg' - possible 
side-effects?
#403: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:298:
+#define DKL_REG_MMIO(reg)  _MMIO(reg.reg)

-:409: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#409: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:304:
+#define _DKL_REG_BANK_OFFSET(phy_offset)   ((phy_offset) & ((1 << 
_DKL_BANK_SHIFT) - 1))

-:412: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy_offset' - possible 
side-effects?
#412: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:307:
+#define _DKL_REG(tc_port, phy_offset)  \
+   ((const struct intel_tc_dkl_reg) { \
+   .reg = _DKL_REG_PHY_BASE(tc_port) + \
+  _DKL_REG_BANK_OFFSET(phy_offset), \
+   .bank_idx = _DKL_REG_BANK_IDX(phy_offset), \
+   })

-:419: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ln0_offs' - possible 
side-effects?
#419: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:314:
+#define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \
+   _DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs)))

total: 0 errors, 3 warnings, 3 checks, 578 lines checked

Re: [Intel-gfx] [PATCH v4 12/17] drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl

[Matthew Auld]

On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:

Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
works in vm_bind mode. The vm_bind mode only works with
this new execbuf3 ioctl.

The new execbuf3 ioctl will not have any list of objects to validate
bind as all required objects binding would have been requested by the
userspace before submitting the execbuf3.

Legacy features like relocations etc are not supported by execbuf3.

v2: Add more input validity checks.
v3: batch_address is a VA (not an array) if num_batches=1,
 minor cleanup
v4: replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode()

Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
  drivers/gpu/drm/i915/Makefile |   1 +
  .../gpu/drm/i915/gem/i915_gem_execbuffer3.c   | 580 ++
  drivers/gpu/drm/i915/gem/i915_gem_ioctls.h|   2 +
  drivers/gpu/drm/i915/i915_driver.c|   1 +
  include/uapi/drm/i915_drm.h   |  61 ++
  5 files changed, 645 insertions(+)
  create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8d76bb888dc3..6a801684d569 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -150,6 +150,7 @@ gem-y += \
gem/i915_gem_domain.o \
gem/i915_gem_execbuffer_common.o \
gem/i915_gem_execbuffer.o \
+   gem/i915_gem_execbuffer3.o \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
gem/i915_gem_lmem.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
new file mode 100644
index ..a9b4cc44bf66
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
@@ -0,0 +1,580 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include 
+#include 
+
+#include 
+
+#include "gt/intel_context.h"
+#include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt.h"
+
+#include "i915_drv.h"
+#include "i915_gem_context.h"
+#include "i915_gem_execbuffer_common.h"
+#include "i915_gem_ioctls.h"
+#include "i915_gem_vm_bind.h"
+#include "i915_trace.h"
+
+#define __EXEC3_ENGINE_PINNED  BIT_ULL(32)
+#define __EXEC3_INTERNAL_FLAGS (~0ull << 32)
+
+/* Catch emission of unexpected errors for CI! */
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
+#undef EINVAL
+#define EINVAL ({ \
+   DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
+   22; \
+})
+#endif
+
+/**
+ * DOC: User command execution with execbuf3 ioctl
+ *
+ * A VM in VM_BIND mode will not support older execbuf mode of binding.
+ * The execbuf ioctl handling in VM_BIND mode differs significantly from the
+ * older execbuf2 ioctl (See struct drm_i915_gem_execbuffer2).
+ * Hence, a new execbuf3 ioctl has been added to support VM_BIND mode. (See
+ * struct drm_i915_gem_execbuffer3). The execbuf3 ioctl will not accept any
+ * execlist. Hence, no support for implicit sync.
+ *
+ * The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only
+ * works with execbuf3 ioctl for submission.
+ *
+ * The execbuf3 ioctl directly specifies the batch addresses instead of as
+ * object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not
+ * support many of the older features like in/out/submit fences, fence array,
+ * default gem context etc. (See struct drm_i915_gem_execbuffer3).
+ *
+ * In VM_BIND mode, VA allocation is completely managed by the user instead of
+ * the i915 driver. Hence all VA assignment, eviction are not applicable in
+ * VM_BIND mode. Also, for determining object activeness, VM_BIND mode will not
+ * be using the i915_vma active reference tracking. It will instead check the
+ * dma-resv object's fence list for that.
+ *
+ * So, a lot of code supporting execbuf2 ioctl, like relocations, VA evictions,
+ * vma lookup table, implicit sync, vma active reference tracking etc., are not
+ * applicable for execbuf3 ioctl.
+ */
+
+/**
+ * struct i915_execbuffer - execbuf struct for execbuf3
+ * @i915: reference to the i915 instance we run on
+ * @file: drm file reference
+ * args: execbuf3 ioctl structure
+ * @gt: reference to the gt instance ioctl submitted for
+ * @context: logical state for the request
+ * @gem_context: callers context
+ * @requests: requests to be build
+ * @composite_fence: used for excl fence in dma_resv objects when > 1 BB 
submitted
+ * @ww: i915_gem_ww_ctx instance
+ * @num_batches: number of batches submitted
+ * @batch_addresses: addresses corresponds to the submitted batches
+ * @batches: references to the i915_vmas corresponding to the batches
+ */
+struct i915_execbuffer {
+   struct drm_i915_private *i915;
+   struct drm_file *file;
+   struct drm_i915_gem_execbuffer3 *args;
+
+   struct intel_gt *gt;
+   struct intel_context *context;
+   struct i915_gem_context *gem_context;
+
+   struct i915_request *re

[Intel-gfx] [PATCH 3/3] drm/i915/tgl+: Sanitize DKL PHY register definitions

[Imre Deak]

Not all Dekel PHY registers have a lane instance, so having to specify
this when using them is awkward. It makes more sense to define each PHY
register with its full internal PHY offset where bits 15:12 is the lane
for lane-instanced PHY registers and just a register bank index for other
PHY registers. This way lane-instanced registers can be referred to with
the (tc_port, lane) parameters, while other registers just with a tc_port
parameter.

An additional benefit of this change is to prevent passing a Dekel
register to a generic MMIO access function or vice versa.

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_ddi.c  |  20 +-
 .../i915/display/intel_display_power_well.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  48 ++---
 drivers/gpu/drm/i915/display/intel_tc.c   |  32 ++-
 drivers/gpu/drm/i915/display/intel_tc.h   |  10 +-
 .../gpu/drm/i915/display/intel_tc_phy_regs.h  | 188 +-
 6 files changed, 151 insertions(+), 149 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8e2b338883858..4a4824480 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1262,11 +1262,11 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
for (ln = 0; ln < 2; ln++) {
int level;
 
-   intel_tc_dkl_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), ln, 
0);
+   intel_tc_dkl_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 
0);
 
level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 
-   intel_tc_dkl_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), ln,
+   intel_tc_dkl_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
 DKL_TX_PRESHOOT_COEFF_MASK |
 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
 DKL_TX_VSWING_CONTROL_MASK,
@@ -1276,7 +1276,7 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
 
level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 
-   intel_tc_dkl_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), ln,
+   intel_tc_dkl_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
 DKL_TX_PRESHOOT_COEFF_MASK |
 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
 DKL_TX_VSWING_CONTROL_MASK,
@@ -1284,7 +1284,7 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
 
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
 
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
 
-   intel_tc_dkl_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln,
+   intel_tc_dkl_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
 DKL_TX_DP20BITMODE, 0);
 
if (IS_ALDERLAKE_P(dev_priv)) {
@@ -1303,7 +1303,7 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
}
 
-   intel_tc_dkl_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln,
+   intel_tc_dkl_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
 
DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
 
DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
 val);
@@ -2016,8 +2016,8 @@ icl_program_mg_dp_mode(struct intel_digital_port 
*dig_port,
return;
 
if (DISPLAY_VER(dev_priv) >= 12) {
-   ln0 = intel_tc_dkl_read(dev_priv, DKL_DP_MODE(tc_port), 0);
-   ln1 = intel_tc_dkl_read(dev_priv, DKL_DP_MODE(tc_port), 1);
+   ln0 = intel_tc_dkl_read(dev_priv, DKL_DP_MODE(tc_port, 0));
+   ln1 = intel_tc_dkl_read(dev_priv, DKL_DP_MODE(tc_port, 1));
} else {
ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
@@ -2078,8 +2078,8 @@ icl_program_mg_dp_mode(struct intel_digital_port 
*dig_port,
}
 
if (DISPLAY_VER(dev_priv) >= 12) {
-   intel_tc_dkl_write(dev_priv, DKL_DP_MODE(tc_port), 0, ln0);
-   intel_tc_dkl_write(dev_priv, DKL_DP_MODE(tc_port), 1, ln1);
+   intel_tc_dkl_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
+   intel_tc_dkl_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
} else {
intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
@@ -3084,7 +3084,7 @@ static void adlp_tbt_to_dp_alt_switch_wa(struct 
intel_encoder *encoder)
int ln;
 
for (ln = 0; ln < 2; ln++)
-   intel_t

[Intel-gfx] [PATCH 2/3] drm/i915/tgl+: Move DKL PHY register definitions to intel_tc_phy_regs.h

[Imre Deak]

Move the TypeC DKL PHY register definitions to intel_tc_phy_regs.h next
to the TypeC MG PHY registers.

No functional changes.

Signed-off-by: Imre Deak 
---
 .../i915/display/intel_display_power_well.c   |   1 +
 .../gpu/drm/i915/display/intel_tc_phy_regs.h  | 186 ++
 drivers/gpu/drm/i915/i915_reg.h   | 179 -
 3 files changed, 187 insertions(+), 179 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c 
b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index c37d2d5bbd983..3cc7c5722cd5b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -19,6 +19,7 @@
 #include "intel_pcode.h"
 #include "intel_pps.h"
 #include "intel_tc.h"
+#include "intel_tc_phy_regs.h"
 #include "intel_vga.h"
 #include "skl_watermark.h"
 #include "vlv_sideband.h"
diff --git a/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h 
b/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
index 5a545086f9599..29cc06c31e0cc 100644
--- a/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
@@ -8,6 +8,7 @@
 
 #include "i915_reg_defs.h"
 
+/* MG PHY registers */
 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
_MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
 
@@ -277,4 +278,189 @@
   
_MG_PLL_TDC_COLDST_BIAS_PORT1, \
   
_MG_PLL_TDC_COLDST_BIAS_PORT2)
 
+/* DEKEL PHY registers */
+#define _DKL_PHY1_BASE 0x168000
+#define _DKL_PHY2_BASE 0x169000
+#define _DKL_PHY3_BASE 0x16A000
+#define _DKL_PHY4_BASE 0x16B000
+#define _DKL_PHY5_BASE 0x16C000
+#define _DKL_PHY6_BASE 0x16D000
+
+#define _DKL_BANK_SHIFT12
+#define DKL_REG_TC_PORT(reg)   (((reg).reg - 
_DKL_PHY1_BASE) >> _DKL_BANK_SHIFT)
+
+/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
+#define _DKL_PCS_DW5   0x14
+#define DKL_PCS_DW5(tc_port)   _MMIO(_PORT(tc_port, \
+   
_DKL_PHY1_BASE, \
+   
_DKL_PHY2_BASE) + \
+ _DKL_PCS_DW5)
+#define   DKL_PCS_DW5_CORE_SOFTRESET   REG_BIT(11)
+
+#define _DKL_PLL_DIV0  0x200
+#define DKL_PLL_DIV0(tc_port)  _MMIO(_PORT(tc_port, \
+   
_DKL_PHY1_BASE, \
+   
_DKL_PHY2_BASE) + \
+ _DKL_PLL_DIV0)
+#define   DKL_PLL_DIV0_AFC_STARTUP_MASKREG_GENMASK(27, 
25)
+#define   DKL_PLL_DIV0_AFC_STARTUP(val)
REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val))
+#define   DKL_PLL_DIV0_INTEG_COEFF(x)  ((x) << 16)
+#define   DKL_PLL_DIV0_INTEG_COEFF_MASK(0x1F << 16)
+#define   DKL_PLL_DIV0_PROP_COEFF(x)   ((x) << 12)
+#define   DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
+#define   DKL_PLL_DIV0_FBPREDIV_SHIFT  (8)
+#define   DKL_PLL_DIV0_FBPREDIV(x) ((x) << 
DKL_PLL_DIV0_FBPREDIV_SHIFT)
+#define   DKL_PLL_DIV0_FBPREDIV_MASK   (0xF << 
DKL_PLL_DIV0_FBPREDIV_SHIFT)
+#define   DKL_PLL_DIV0_FBDIV_INT(x)((x) << 0)
+#define   DKL_PLL_DIV0_FBDIV_INT_MASK  (0xFF << 0)
+#define   DKL_PLL_DIV0_MASK
(DKL_PLL_DIV0_INTEG_COEFF_MASK | \
+
DKL_PLL_DIV0_PROP_COEFF_MASK | \
+
DKL_PLL_DIV0_FBPREDIV_MASK | \
+
DKL_PLL_DIV0_FBDIV_INT_MASK)
+
+#define _DKL_PLL_DIV1  0x204
+#define DKL_PLL_DIV1(tc_port)  _MMIO(_PORT(tc_port, \
+   
_DKL_PHY1_BASE, \
+   
_DKL_PHY2_BASE) + \
+ _DKL_PLL_DIV1)
+#define   DKL_PLL_DIV1_IREF_TRIM(x)((x) << 16)
+#define   DKL_PLL_DIV1_IREF_TRIM_MASK  (0x1F << 16)
+#define   DKL_PLL_DIV1_TDC_TARGET_CNT(x)   ((x) << 0)
+#define   DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
+
+#de

[Intel-gfx] [PATCH 1/3] drm/i915/tgl+: Add locking around DKL PHY register accesses

[Imre Deak]

Accessing the TypeC DKL PHY registers during modeset-commit,
-verification, DP link-retraining and AUX power well toggling is racy
due to these code paths being concurrent and the PHY register bank
selection register (HIP_INDEX_REG) being shared between PHY instances
(aka TC ports) and the bank selection being not atomic wrt. the actual
PHY register access.

Add the required locking around each PHY register bank selection->
register access sequence.

Kudos to Ville for noticing the race conditions.

Cc: Ville Syrjälä 
Cc:  # v5.5+
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_ddi.c  | 67 ++---
 drivers/gpu/drm/i915/display/intel_display.c  |  2 +
 .../gpu/drm/i915/display/intel_display_core.h |  4 +
 .../i915/display/intel_display_power_well.c   |  6 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 58 +---
 drivers/gpu/drm/i915/display/intel_tc.c   | 94 +++
 drivers/gpu/drm/i915/display/intel_tc.h   |  9 ++
 drivers/gpu/drm/i915/i915_reg.h   |  3 +
 8 files changed, 167 insertions(+), 76 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 971356237eca3..8e2b338883858 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1262,33 +1262,30 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
for (ln = 0; ln < 2; ln++) {
int level;
 
-   intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
-  HIP_INDEX_VAL(tc_port, ln));
-
-   intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
+   intel_tc_dkl_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), ln, 
0);
 
level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 
-   intel_de_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port),
-DKL_TX_PRESHOOT_COEFF_MASK |
-DKL_TX_DE_EMPAHSIS_COEFF_MASK |
-DKL_TX_VSWING_CONTROL_MASK,
-
DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
-
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
-
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
+   intel_tc_dkl_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), ln,
+DKL_TX_PRESHOOT_COEFF_MASK |
+DKL_TX_DE_EMPAHSIS_COEFF_MASK |
+DKL_TX_VSWING_CONTROL_MASK,
+
DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
+
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
+
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
 
level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 
-   intel_de_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port),
-DKL_TX_PRESHOOT_COEFF_MASK |
-DKL_TX_DE_EMPAHSIS_COEFF_MASK |
-DKL_TX_VSWING_CONTROL_MASK,
-
DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
-
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
-
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
+   intel_tc_dkl_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), ln,
+DKL_TX_PRESHOOT_COEFF_MASK |
+DKL_TX_DE_EMPAHSIS_COEFF_MASK |
+DKL_TX_VSWING_CONTROL_MASK,
+
DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
+
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
+
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
 
-   intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
-DKL_TX_DP20BITMODE, 0);
+   intel_tc_dkl_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln,
+DKL_TX_DP20BITMODE, 0);
 
if (IS_ALDERLAKE_P(dev_priv)) {
u32 val;
@@ -1306,10 +1303,10 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
}
 
-   intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
-DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
-DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
-val);
+   intel_tc_dkl_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln,
+
DKL_TX_DPCNTL2_C

Re: [Intel-gfx] [PATCH v4 17/17] drm/i915/vm_bind: Add uapi for user to enable vm_bind_mode

[Niranjana Vishwanathapura]

On Tue, Oct 18, 2022 at 05:03:16PM +0100, Matthew Auld wrote:

On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:

Add getparam support for VM_BIND capability version.
Add VM creation time flag to enable vm_bind_mode for the VM.

v2: update kernel-doc
v3: create vm->root_obj only upon I915_VM_CREATE_FLAGS_USE_VM_BIND
v4: replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode()

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 25 +++--
 drivers/gpu/drm/i915/gem/i915_gem_context.h |  3 +--
 drivers/gpu/drm/i915/gt/intel_gtt.c |  2 ++
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/i915_getparam.c|  3 +++
 include/uapi/drm/i915_drm.h | 22 +-
 6 files changed, 52 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 76c6419b7ae0..0376adbbeecc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1803,9 +1803,13 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, 
void *data,
if (!HAS_FULL_PPGTT(i915))
return -ENODEV;
-   if (args->flags)
+   if (args->flags & I915_VM_CREATE_FLAGS_UNKNOWN)
return -EINVAL;
+   if ((args->flags & I915_VM_CREATE_FLAGS_USE_VM_BIND) &&
+   !HAS_VM_BIND(i915))
+   return -EOPNOTSUPP;
+
ppgtt = i915_ppgtt_create(to_gt(i915), 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
@@ -1818,15 +1822,32 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, 
void *data,
goto err_put;
}
+   if (args->flags & I915_VM_CREATE_FLAGS_USE_VM_BIND) {
+   struct drm_i915_gem_object *obj;
+
+   obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+   if (IS_ERR(obj)) {
+   err = PTR_ERR(obj);
+   goto err_put;
+   }
+
+   ppgtt->vm.root_obj = obj;
+   }
+
err = xa_alloc(&file_priv->vm_xa, &id, &ppgtt->vm,
   xa_limit_32b, GFP_KERNEL);
if (err)
-   goto err_put;
+   goto err_root_obj_put;
GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */
args->vm_id = id;
return 0;
+err_root_obj_put:
+   if (ppgtt->vm.root_obj) {
+   i915_gem_object_put(ppgtt->vm.root_obj);
+   ppgtt->vm.root_obj = NULL;
+   }
 err_put:
i915_vm_put(&ppgtt->vm);
return err;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h 
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index e8b41aa8f8c4..b53aef2853cb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -150,8 +150,7 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device 
*dev, void *data,
  */
 static inline bool i915_gem_vm_is_vm_bind_mode(struct i915_address_space *vm)
 {
-   /* No support to enable vm_bind mode yet */
-   return false;
+   return !!vm->root_obj;
 }
 struct i915_address_space *
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 50648ab9214a..ae66fdd4bce9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -178,6 +178,8 @@ int i915_vm_lock_objects(struct i915_address_space *vm,
 void i915_address_space_fini(struct i915_address_space *vm)
 {
drm_mm_takedown(&vm->mm);
+   if (vm->root_obj)
+   i915_gem_object_put(vm->root_obj);
GEM_BUG_ON(!RB_EMPTY_ROOT(&vm->va.rb_root));
mutex_destroy(&vm->vm_bind_lock);
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7c64f8a17493..f4e7f3d4aff9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -972,6 +972,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_BAR2_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+#define HAS_VM_BIND(i915) (GRAPHICS_VER(i915) >= 12)
+
 /* intel_device_info.c */
 static inline struct intel_device_info *
 mkwrite_device_info(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c 
b/drivers/gpu/drm/i915/i915_getparam.c
index 342c8ca6414e..f45b3c684bcf 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -175,6 +175,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_PERF_REVISION:
value = i915_perf_ioctl_version();
break;
+   case I915_PARAM_VM_BIND_VERSION:
+   value = HAS_VM_BIND(i915);
+   break;
default:
DRM_DEBUG("Unknown para

Re: [Intel-gfx] [PATCH v4 17/17] drm/i915/vm_bind: Add uapi for user to enable vm_bind_mode

[Matthew Auld]

On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:

Add getparam support for VM_BIND capability version.
Add VM creation time flag to enable vm_bind_mode for the VM.

v2: update kernel-doc
v3: create vm->root_obj only upon I915_VM_CREATE_FLAGS_USE_VM_BIND
v4: replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode()

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
  drivers/gpu/drm/i915/gem/i915_gem_context.c | 25 +++--
  drivers/gpu/drm/i915/gem/i915_gem_context.h |  3 +--
  drivers/gpu/drm/i915/gt/intel_gtt.c |  2 ++
  drivers/gpu/drm/i915/i915_drv.h |  2 ++
  drivers/gpu/drm/i915/i915_getparam.c|  3 +++
  include/uapi/drm/i915_drm.h | 22 +-
  6 files changed, 52 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 76c6419b7ae0..0376adbbeecc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1803,9 +1803,13 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, 
void *data,
if (!HAS_FULL_PPGTT(i915))
return -ENODEV;
  
-	if (args->flags)

+   if (args->flags & I915_VM_CREATE_FLAGS_UNKNOWN)
return -EINVAL;
  
+	if ((args->flags & I915_VM_CREATE_FLAGS_USE_VM_BIND) &&

+   !HAS_VM_BIND(i915))
+   return -EOPNOTSUPP;
+
ppgtt = i915_ppgtt_create(to_gt(i915), 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
@@ -1818,15 +1822,32 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, 
void *data,
goto err_put;
}
  
+	if (args->flags & I915_VM_CREATE_FLAGS_USE_VM_BIND) {

+   struct drm_i915_gem_object *obj;
+
+   obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+   if (IS_ERR(obj)) {
+   err = PTR_ERR(obj);
+   goto err_put;
+   }
+
+   ppgtt->vm.root_obj = obj;
+   }
+
err = xa_alloc(&file_priv->vm_xa, &id, &ppgtt->vm,
   xa_limit_32b, GFP_KERNEL);
if (err)
-   goto err_put;
+   goto err_root_obj_put;
  
  	GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */

args->vm_id = id;
return 0;
  
+err_root_obj_put:

+   if (ppgtt->vm.root_obj) {
+   i915_gem_object_put(ppgtt->vm.root_obj);
+   ppgtt->vm.root_obj = NULL;
+   }
  err_put:
i915_vm_put(&ppgtt->vm);
return err;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h 
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index e8b41aa8f8c4..b53aef2853cb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -150,8 +150,7 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device 
*dev, void *data,
   */
  static inline bool i915_gem_vm_is_vm_bind_mode(struct i915_address_space *vm)
  {
-   /* No support to enable vm_bind mode yet */
-   return false;
+   return !!vm->root_obj;
  }
  
  struct i915_address_space *

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 50648ab9214a..ae66fdd4bce9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -178,6 +178,8 @@ int i915_vm_lock_objects(struct i915_address_space *vm,
  void i915_address_space_fini(struct i915_address_space *vm)
  {
drm_mm_takedown(&vm->mm);
+   if (vm->root_obj)
+   i915_gem_object_put(vm->root_obj);
GEM_BUG_ON(!RB_EMPTY_ROOT(&vm->va.rb_root));
mutex_destroy(&vm->vm_bind_lock);
  }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7c64f8a17493..f4e7f3d4aff9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -972,6 +972,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
  #define HAS_BAR2_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
  
+#define HAS_VM_BIND(i915) (GRAPHICS_VER(i915) >= 12)

+
  /* intel_device_info.c */
  static inline struct intel_device_info *
  mkwrite_device_info(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c 
b/drivers/gpu/drm/i915/i915_getparam.c
index 342c8ca6414e..f45b3c684bcf 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -175,6 +175,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_PERF_REVISION:
value = i915_perf_ioctl_version();
break;
+   case I915_PARAM_VM_BIND_VERSION:
+   value = HAS_VM_BIND(i915);
+   break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
  

Re: [Intel-gfx] [PATCH] drm/i915: fix clear mask in GEN7_MISCCPCTL update

[Matt Roper]

On Mon, Oct 17, 2022 at 10:55:25AM +0200, Andrzej Hajda wrote:
> GEN7_DOP_CLOCK_GATE_ENABLE bit should be cleared, not inverse.
> The bug was introduced during conversion to intel_uncore_rmw helper.
> 
> Suggested-by: Matt Roper 
> Fixes: 8cee664d3eb6f8 ("drm/i915: use proper helper for register updates")
> Signed-off-by: Andrzej Hajda 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 4 ++--
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2b75ca5e6e618b..d68859866bf238 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1052,8 +1052,8 @@ static void ivb_parity_work(struct work_struct *work)
>   if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
>   goto out;
>  
> - misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, 
> ~GEN7_DOP_CLOCK_GATE_ENABLE,
> -  0);
> + misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL,
> +  GEN7_DOP_CLOCK_GATE_ENABLE, 0);
>   intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL);
>  
>   while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9f6c58ad8bdb06..19d4a88184d7a1 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4321,8 +4321,8 @@ static void gen8_set_l3sqc_credits(struct 
> drm_i915_private *dev_priv,
>   u32 val;
>  
>   /* WaTempDisableDOPClkGating:bdw */
> - misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, 
> ~GEN7_DOP_CLOCK_GATE_ENABLE,
> -  0);
> + misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL,
> +  GEN7_DOP_CLOCK_GATE_ENABLE, 0);
>  
>   val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
>   val &= ~L3_PRIO_CREDITS_MASK;
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v4 09/17] drm/i915/vm_bind: Add out fence support

[Matthew Auld]

On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:

Add support for handling out fence for vm_bind call.

v2: Reset vma->vm_bind_fence.syncobj to NULL at the end
 of vm_bind call.
v3: Remove vm_unbind out fence uapi which is not supported yet.

Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
  drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h   |  4 +
  .../drm/i915/gem/i915_gem_vm_bind_object.c| 82 +++
  drivers/gpu/drm/i915/i915_vma.c   |  7 +-
  drivers/gpu/drm/i915/i915_vma_types.h |  7 ++
  include/uapi/drm/i915_drm.h   | 49 ++-
  5 files changed, 146 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
index 36262a6357b5..b70e900e35ab 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
@@ -8,6 +8,7 @@
  
  #include 
  
+struct dma_fence;

  struct drm_device;
  struct drm_file;
  struct i915_address_space;
@@ -23,4 +24,7 @@ int i915_gem_vm_unbind_ioctl(struct drm_device *dev, void 
*data,
  
  void i915_gem_vm_unbind_all(struct i915_address_space *vm);
  
+void i915_vm_bind_signal_fence(struct i915_vma *vma,

+  struct dma_fence * const fence);
+
  #endif /* __I915_GEM_VM_BIND_H */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
index 3ea3cb3ed97e..63889ba00183 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
@@ -7,6 +7,8 @@
  
  #include 
  
+#include 

+
  #include "gem/i915_gem_context.h"
  #include "gem/i915_gem_vm_bind.h"
  
@@ -100,6 +102,76 @@ static void i915_gem_vm_bind_remove(struct i915_vma *vma, bool release_obj)

i915_gem_object_put(vma->obj);
  }
  
+static int i915_vm_bind_add_fence(struct drm_file *file, struct i915_vma *vma,

+ u32 handle, u64 point)
+{
+   struct drm_syncobj *syncobj;
+
+   syncobj = drm_syncobj_find(file, handle);
+   if (!syncobj) {
+   DRM_DEBUG("Invalid syncobj handle provided\n");
+   return -ENOENT;
+   }
+
+   /*
+* For timeline syncobjs we need to preallocate chains for
+* later signaling.
+*/
+   if (point) {
+   vma->vm_bind_fence.chain_fence = dma_fence_chain_alloc();
+   if (!vma->vm_bind_fence.chain_fence) {
+   drm_syncobj_put(syncobj);
+   return -ENOMEM;
+   }
+   } else {
+   vma->vm_bind_fence.chain_fence = NULL;
+   }
+   vma->vm_bind_fence.syncobj = syncobj;
+   vma->vm_bind_fence.value = point;
+
+   return 0;
+}
+
+static void i915_vm_bind_put_fence(struct i915_vma *vma)
+{
+   if (!vma->vm_bind_fence.syncobj)
+   return;
+
+   drm_syncobj_put(vma->vm_bind_fence.syncobj);
+   dma_fence_chain_free(vma->vm_bind_fence.chain_fence);
+   vma->vm_bind_fence.syncobj = NULL;
+}
+
+/**
+ * i915_vm_bind_signal_fence() - Add fence to vm_bind syncobj
+ * @vma: vma mapping requiring signaling
+ * @fence: fence to be added
+ *
+ * Associate specified @fence with the @vma's syncobj to be
+ * signaled after the @fence work completes.
+ */
+void i915_vm_bind_signal_fence(struct i915_vma *vma,
+  struct dma_fence * const fence)
+{
+   struct drm_syncobj *syncobj = vma->vm_bind_fence.syncobj;
+
+   if (!syncobj)
+   return;
+
+   if (vma->vm_bind_fence.chain_fence) {
+   drm_syncobj_add_point(syncobj,
+ vma->vm_bind_fence.chain_fence,
+ fence, vma->vm_bind_fence.value);
+   /*
+* The chain's ownership is transferred to the
+* timeline.
+*/
+   vma->vm_bind_fence.chain_fence = NULL;
+   } else {
+   drm_syncobj_replace_fence(syncobj, fence);
+   }
+}
+
  static int i915_gem_vm_unbind_vma(struct i915_address_space *vm,
  struct drm_i915_gem_vm_unbind *va)
  {
@@ -237,6 +309,13 @@ static int i915_gem_vm_bind_obj(struct i915_address_space 
*vm,
goto unlock_vm;
}
  
+	if (va->fence.flags & I915_TIMELINE_FENCE_SIGNAL) {

+   ret = i915_vm_bind_add_fence(file, vma, va->fence.handle,
+va->fence.value);
+   if (ret)
+   goto put_vma;
+   }
+
pin_flags = va->start | PIN_OFFSET_FIXED | PIN_USER | PIN_VALIDATE;
  
  	for_i915_gem_ww(&ww, ret, true) {

@@ -258,6 +337,9 @@ static int i915_gem_vm_bind_obj(struct i915_address_space 
*vm,
i915_gem_object_get(vma->obj);
}
  
+	if (va->fence.flags & I915_TIMELINE_FENCE_SIGNAL)

+   

[Intel-gfx] PR for HuC 7.10.3

[Daniele Ceraolo Spurio]

The following changes since commit 48407ffd7adb9511701547068b1e6f0956bd1c94:

  cnm: update chips&media wave521c firmware. (2022-10-17 10:20:43 -0400)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-firmware dg2_huc_7.10.3_pr

for you to fetch changes up to 8f86b5ab3e051170ea240fc409d457e16e24bc21:

  i915: Add HuC 7.10.3 for DG2 (2022-10-18 08:18:19 -0700)


Daniele Ceraolo Spurio (1):
  i915: Add HuC 7.10.3 for DG2

 WHENCE   |   3 +++
 i915/dg2_huc_gsc.bin | Bin 0 -> 622592 bytes
 2 files changed, 3 insertions(+)
 create mode 100755 i915/dg2_huc_gsc.bin

Re: [Intel-gfx] [PATCH v3 09/17] drm/i915/vm_bind: Add out fence support

[Matthew Auld]

On 14/10/2022 07:48, Niranjana Vishwanathapura wrote:

On Sun, Oct 09, 2022 at 11:58:18PM -0700, Niranjana Vishwanathapura wrote:

Add support for handling out fence for vm_bind call.

v2: Reset vma->vm_bind_fence.syncobj to NULL at the end
   of vm_bind call.

Signed-off-by: Niranjana Vishwanathapura 


Signed-off-by: Andi Shyti 
---
drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h   |  4 +
.../drm/i915/gem/i915_gem_vm_bind_object.c    | 82 +++
drivers/gpu/drm/i915/i915_vma.c   |  7 +-
drivers/gpu/drm/i915/i915_vma_types.h |  7 ++
include/uapi/drm/i915_drm.h   | 63 +-
5 files changed, 158 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h

index 36262a6357b5..b70e900e35ab 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
@@ -8,6 +8,7 @@

#include 

+struct dma_fence;
struct drm_device;
struct drm_file;
struct i915_address_space;
@@ -23,4 +24,7 @@ int i915_gem_vm_unbind_ioctl(struct drm_device *dev, 
void *data,


void i915_gem_vm_unbind_all(struct i915_address_space *vm);

+void i915_vm_bind_signal_fence(struct i915_vma *vma,
+   struct dma_fence * const fence);
+
#endif /* __I915_GEM_VM_BIND_H */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c

index c435d49af2c8..526d3a6bf671 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
@@ -7,6 +7,8 @@

#include 

+#include 
+
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_vm_bind.h"

@@ -100,6 +102,76 @@ static void i915_gem_vm_bind_remove(struct 
i915_vma *vma, bool release_obj)

    i915_gem_object_put(vma->obj);
}

+static int i915_vm_bind_add_fence(struct drm_file *file, struct 
i915_vma *vma,

+  u32 handle, u64 point)
+{
+    struct drm_syncobj *syncobj;
+
+    syncobj = drm_syncobj_find(file, handle);
+    if (!syncobj) {
+    DRM_DEBUG("Invalid syncobj handle provided\n");
+    return -ENOENT;
+    }
+
+    /*
+ * For timeline syncobjs we need to preallocate chains for
+ * later signaling.
+ */
+    if (point) {
+    vma->vm_bind_fence.chain_fence = dma_fence_chain_alloc();
+    if (!vma->vm_bind_fence.chain_fence) {
+    drm_syncobj_put(syncobj);
+    return -ENOMEM;
+    }
+    } else {
+    vma->vm_bind_fence.chain_fence = NULL;
+    }
+    vma->vm_bind_fence.syncobj = syncobj;
+    vma->vm_bind_fence.value = point;
+
+    return 0;
+}
+
+static void i915_vm_bind_put_fence(struct i915_vma *vma)
+{
+    if (!vma->vm_bind_fence.syncobj)
+    return;
+
+    drm_syncobj_put(vma->vm_bind_fence.syncobj);
+    dma_fence_chain_free(vma->vm_bind_fence.chain_fence);
+    vma->vm_bind_fence.syncobj = NULL;
+}
+
+/**
+ * i915_vm_bind_signal_fence() - Add fence to vm_bind syncobj
+ * @vma: vma mapping requiring signaling
+ * @fence: fence to be added
+ *
+ * Associate specified @fence with the @vma's syncobj to be
+ * signaled after the @fence work completes.
+ */
+void i915_vm_bind_signal_fence(struct i915_vma *vma,
+   struct dma_fence * const fence)
+{
+    struct drm_syncobj *syncobj = vma->vm_bind_fence.syncobj;
+
+    if (!syncobj)
+    return;
+
+    if (vma->vm_bind_fence.chain_fence) {
+    drm_syncobj_add_point(syncobj,
+  vma->vm_bind_fence.chain_fence,
+  fence, vma->vm_bind_fence.value);
+    /*
+ * The chain's ownership is transferred to the
+ * timeline.
+ */
+    vma->vm_bind_fence.chain_fence = NULL;
+    } else {
+    drm_syncobj_replace_fence(syncobj, fence);
+    }
+}
+
static int i915_gem_vm_unbind_vma(struct i915_address_space *vm,
  struct drm_i915_gem_vm_unbind *va)
{
@@ -237,6 +309,13 @@ static int i915_gem_vm_bind_obj(struct 
i915_address_space *vm,

    goto unlock_vm;
}

+    if (va->fence.flags & I915_TIMELINE_FENCE_SIGNAL) {
+    ret = i915_vm_bind_add_fence(file, vma, va->fence.handle,
+ va->fence.value);
+    if (ret)
+    goto put_vma;
+    }
+
pin_flags = va->start | PIN_OFFSET_FIXED | PIN_USER | PIN_VALIDATE;

for_i915_gem_ww(&ww, ret, true) {
@@ -258,6 +337,9 @@ static int i915_gem_vm_bind_obj(struct 
i915_address_space *vm,

    i915_gem_object_get(vma->obj);
}

+    if (va->fence.flags & I915_TIMELINE_FENCE_SIGNAL)
+    i915_vm_bind_put_fence(vma);
+put_vma:
if (ret)
    i915_vma_destroy(vma);
unlock_vm:
diff --git a/drivers/gpu/drm/i915/i915_vma.c 
b/drivers/gpu/drm/i915/i915_vma.c

index 88c09e885fec..cb8e718ec46e 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -29,6 +29,7 @@
#include "display/intel_frontbuffer.h"
#include "gem/i915_gem_lmem.h"
#include "gem/i915_ge

Re: [Intel-gfx] i915 "GPU HANG", bisected to a2daa27c0c61 "swiotlb: simplify swiotlb_max_segment"

[Christoph Hellwig]

On Tue, Oct 18, 2022 at 04:53:50PM +0200, Juergen Gross wrote:
>> If we don't need the IS_ENABLED is not needed I'm all for dropping it.
>> But unless I misread the code, on arm/arm64 even PV guests are 1:1
>> mapped so that all Linux physically contigous memory also is Xen
>> contigous, so we don't need the hack.
>
> There are no PV guests on arm/arm64.

Ok, that's the part I was missing.  In that case we should be fine
without the IS_ENABLED indeed.

Re: [Intel-gfx] i915 "GPU HANG", bisected to a2daa27c0c61 "swiotlb: simplify swiotlb_max_segment"

[Juergen Gross]

On 18.10.22 16:33, Christoph Hellwig wrote:

On Tue, Oct 18, 2022 at 04:21:43PM +0200, Jan Beulich wrote:

Leaving the "i915 abuses" part aside (because I can't tell what exactly the
abuse is), but assuming that "can't cope with bounce buffering" means they
don't actually use the allocated buffers, I'd suggest this:


Except for one odd place i915 never uses dma_alloc_* but always allocates
memory itself and then maps it, but then treats it as if it was a
dma_alloc_coherent allocations, that is never does ownership changes.


I've dropped the TDX related remark because I don't think it's meaningful
for PV guests.


This remark is for TDX in general, not Xen related.  With TDX and other
confidentatial computing schemes, all DMA must be bounce buffered, and
all drivers skipping dma_sync* calls are broken.


Otoh I've left the "abuses ignores" word sequence as is, no
matter that it reads odd to me. Plus, as hinted at before, I'm not
convinced the IS_ENABLED() use is actually necessary or warranted here.


If we don't need the IS_ENABLED is not needed I'm all for dropping it.
But unless I misread the code, on arm/arm64 even PV guests are 1:1
mapped so that all Linux physically contigous memory also is Xen
contigous, so we don't need the hack.


There are no PV guests on arm/arm64.


Juergen


OpenPGP_0xB0DE9DD628BF132F.asc
Description: OpenPGP public key


OpenPGP_signature
Description: OpenPGP digital signature

Re: [Intel-gfx] i915 "GPU HANG", bisected to a2daa27c0c61 "swiotlb: simplify swiotlb_max_segment"

[Christoph Hellwig]

On Tue, Oct 18, 2022 at 04:21:43PM +0200, Jan Beulich wrote:
> Leaving the "i915 abuses" part aside (because I can't tell what exactly the
> abuse is), but assuming that "can't cope with bounce buffering" means they
> don't actually use the allocated buffers, I'd suggest this:

Except for one odd place i915 never uses dma_alloc_* but always allocates
memory itself and then maps it, but then treats it as if it was a
dma_alloc_coherent allocations, that is never does ownership changes.

> I've dropped the TDX related remark because I don't think it's meaningful
> for PV guests.

This remark is for TDX in general, not Xen related.  With TDX and other
confidentatial computing schemes, all DMA must be bounce buffered, and
all drivers skipping dma_sync* calls are broken.

> Otoh I've left the "abuses ignores" word sequence as is, no
> matter that it reads odd to me. Plus, as hinted at before, I'm not
> convinced the IS_ENABLED() use is actually necessary or warranted here.

If we don't need the IS_ENABLED is not needed I'm all for dropping it.
But unless I misread the code, on arm/arm64 even PV guests are 1:1
mapped so that all Linux physically contigous memory also is Xen
contigous, so we don't need the hack.

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Extend Wa_1607297627 to Alderlake-P

[Souza, Jose]

On Mon, 2022-10-17 at 20:05 +, Patchwork wrote:
Patch Details
Series: drm/i915: Extend Wa_1607297627 to Alderlake-P
URL:https://patchwork.freedesktop.org/series/109772/
State:  failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109772v1/index.html
CI Bug Log - changes from CI_DRM_12251_full -> Patchwork_109772v1_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_109772v1_full absolutely need to 
be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_109772v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Participating hosts (12 -> 12)

No changes in participating hosts

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_109772v1_full:

IGT changes
Possible regressions

  *   igt@i915_module_load@reload-with-fault-injection:

 *   shard-tglb: 
PASS
 -> 
INCOMPLETE
  *   igt@i915_suspend@debugfs-reader:

 *   shard-apl: NOTRUN -> 
INCOMPLETE

Failures are not related, patch was pushed.

Thanks for the review Lucas and Tvrtko.

Warnings

  *   igt@gem_eio@in-flight-suspend:
 *   shard-apl: 
INCOMPLETE
 (i915#7112) -> 
INCOMPLETE

Known issues

Here are the changes found in Patchwork_109772v1_full that come from known 
issues:

CI changes
Issues hit

  *   boot:
 *   shard-apl: 
(PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS)
 -> 
(PASS,
 
PASS,
 
PASS,
 
FAIL,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dgfx: Temporary hammer to keep autosuspend control 'on' (rev2)

[Gupta, Anshuman]

Pushed to drm-intel-next.
Thanks for Review.
Br,
Anshuman Gupta.

From: Patchwork  
Sent: Friday, October 14, 2022 7:01 PM
To: Gupta, Anshuman 
Cc: intel-gfx@lists.freedesktop.org
Subject: ✓ Fi.CI.IGT: success for drm/i915/dgfx: Temporary hammer to keep 
autosuspend control 'on' (rev2)

Patch Details 
Series:
drm/i915/dgfx: Temporary hammer to keep autosuspend control 'on' (rev2)
URL:
https://patchwork.freedesktop.org/series/109612/
State:
success
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/index.html
CI Bug Log - changes from CI_DRM_12242_full -> Patchwork_109612v2_full
Summary
SUCCESS
No regressions found.
Participating hosts (9 -> 11)
Additional (2): shard-rkl shard-dg1 
Known issues
Here are the changes found in Patchwork_109612v2_full that come from known 
issues:
CI changes
Possible fixes
• boot:
o shard-skl: 
(https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl10/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl9/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl9/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl9/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl10/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl9/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl7/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl7/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl7/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl6/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl6/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl6/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl5/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl5/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl10/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl10/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl1/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl5/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl5/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl4/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl4/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl4/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl4/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl1/boot.html, 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl1/boot.html) 
(https://gitlab.freedesktop.org/drm/intel/issues/5032) -> 
(https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl1/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl9/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl9/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl9/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl7/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl7/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl6/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl6/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl6/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl5/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl5/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl4/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl4/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl4/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl2/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl2/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl1/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl1/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl10/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl10/boot.html,
 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-skl10/boot.html)
IGT changes
Issues hit
• igt@gem_exec_balancer@parallel-out-fence:
o shard-iclb: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-iclb1/igt@gem_exec_balan...@parallel-out-fence.html
 -> 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109612v2/shard-iclb8/igt@gem_exec_balan...@parallel-out-fence.html
 (https://gitlab.freedesktop.org/drm/intel/issues/4525)
• igt@gem_exec_fai

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Print return value on error (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Print return value on error (rev3)
URL   : https://patchwork.freedesktop.org/series/109722/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12255 -> Patchwork_109722v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109722v3/index.html

Participating hosts (41 -> 40)
--

  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_109722v3 that come from known issues:

### IGT changes ###

 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- fi-bdw-5557u:   [INCOMPLETE][1] -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12255/fi-bdw-5557u/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109722v3/fi-bdw-5557u/igt@i915_pm_...@module-reload.html

  


Build changes
-

  * Linux: CI_DRM_12255 -> Patchwork_109722v3

  CI-20190529: 20190529
  CI_DRM_12255: a236605e800c4f71899730d9343834b2df2a5908 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7018: 8312a2fe3f3287ba4ac4bc8d100de0734480f482 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_109722v3: a236605e800c4f71899730d9343834b2df2a5908 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

b103860c9240 drm/i915: Print return value on error

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109722v3/index.html

Re: [Intel-gfx] [PATCH v7 00/21] Move all drivers to a common dma-buf locking convention

[Dmitry Osipenko]

On 10/18/22 14:34, Christian König wrote:
> Am 18.10.22 um 01:07 schrieb Dmitry Osipenko:
>> On 10/17/22 20:22, Dmitry Osipenko wrote:
>>> Hello,
>>>
>>> This series moves all drivers to a dynamic dma-buf locking
>>> specification.
>>>  From now on all dma-buf importers are made responsible for holding
>>> dma-buf's reservation lock around all operations performed over dma-bufs
>>> in accordance to the locking specification. This allows us to utilize
>>> reservation lock more broadly around kernel without fearing of a
>>> potential
>>> deadlocks.
>>>
>>> This patchset passes all i915 selftests. It was also tested using
>>> VirtIO,
>>> Panfrost, Lima, Tegra, udmabuf, AMDGPU and Nouveau drivers. I tested
>>> cases
>>> of display+GPU, display+V4L and GPU+V4L dma-buf sharing (where
>>> appropriate),
>>> which covers majority of kernel drivers since rest of the drivers share
>>> same or similar code paths.
>>>
>>> Changelog:
>>>
>>> v7: - Rebased on top of recent drm-misc-next.
>>>
>>>  - Added ack from Jason Gunthorpe to the RDMA patch.
>>>
>>>  - Added iosys_map_clear() to dma_buf_vmap_unlocked(), making it
>>> fully
>>>    consistent with dma_buf_vmap().
>>>
>>> v6: - Added r-b from Michael Ruhl to the i915 patch.
>>>
>>>  - Added acks from Sumit Semwal and updated commit message of the
>>>    "Move dma_buf_vmap() to dynamic locking specification" patch like
>>>    was suggested by Sumit.
>>>
>>>  - Added "!dmabuf" check to dma_buf_vmap_unlocked() to match the
>>> locked
>>>    variant of the function, for consistency.
>>>
>>> v5: - Added acks and r-bs that were given to v4.
>>>
>>>  - Changed i915 preparation patch like was suggested by Michael
>>> Ruhl.
>>>    The scope of reservation locking is smaller now.
>>>
>>> v4: - Added dma_buf_mmap() to the "locking convention" documentation,
>>>    which was missed by accident in v3.
>>>
>>>  - Added acks from Christian König, Tomasz Figa and Hans Verkuil
>>> that
>>>    they gave to couple v3 patches.
>>>
>>>  - Dropped the "_unlocked" postfix from function names that don't
>>> have
>>>    the locked variant, as was requested by Christian König.
>>>
>>>  - Factored out the per-driver preparations into separate patches
>>>    to ease reviewing of the changes, which is now doable without the
>>>    global dma-buf functions renaming.
>>>
>>>  - Factored out the dynamic locking convention enforcements into
>>> separate
>>>    patches which add the final dma_resv_assert_held(dmabuf->resv)
>>> to the
>>>    dma-buf API functions.
>>>
>>> v3: - Factored out dma_buf_mmap_unlocked() and attachment functions
>>>    into aseparate patches, like was suggested by Christian König.
>>>
>>>  - Corrected and factored out dma-buf locking documentation into
>>>    a separate patch, like was suggested by Christian König.
>>>
>>>  - Intel driver dropped the reservation locking fews days ago from
>>>    its BO-release code path, but we need that locking for the
>>> imported
>>>    GEMs because in the end that code path unmaps the imported GEM.
>>>    So I added back the locking needed by the imported GEMs, updating
>>>    the "dma-buf attachment locking specification" patch
>>> appropriately.
>>>
>>>  - Tested Nouveau+Intel dma-buf import/export combo.
>>>
>>>  - Tested udmabuf import to i915/Nouveau/AMDGPU.
>>>
>>>  - Fixed few places in Etnaviv, Panfrost and Lima drivers that I
>>> missed
>>>    to switch to locked dma-buf vmapping in the drm/gem: Take
>>> reservation
>>>    lock for vmap/vunmap operations" patch. In a result
>>> invalidated the
>>>    Christian's r-b that he gave to v2.
>>>
>>>  - Added locked dma-buf vmap/vunmap functions that are needed for
>>> fixing
>>>    vmappping of Etnaviv, Panfrost and Lima drivers mentioned above.
>>>    I actually had this change stashed for the drm-shmem shrinker
>>> patchset,
>>>    but then realized that it's already needed by the dma-buf
>>> patches.
>>>    Also improved my tests to better cover these code paths.
>>>
>>> v2: - Changed locking specification to avoid problems with a
>>> cross-driver
>>>    ww locking, like was suggested by Christian König. Now the
>>> attach/detach
>>>    callbacks are invoked without the held lock and exporter
>>> should take the
>>>    lock.
>>>
>>>  - Added "locking convention" documentation that explains which
>>> dma-buf
>>>    functions and callbacks are locked/unlocked for importers and
>>> exporters,
>>>    which was requested by Christian König.
>>>
>>>  - Added ack from Tomasz Figa to the V4L patches that he gave to v1.
>>>
>>> Dmitry Osipenko (21):
>>>    dma-buf: Add unlocked variant of vmapping functions
>>>    dma-buf: Add unlocked variant of attachment-mapping functions
>>>    drm/gem: Take reservation lock for vmap/vunmap operations
>>>    drm/prime: Prepare to dynamic dma-buf locking specification
>>

Re: [Intel-gfx] [PATCH v5 12/22] drm/connector: Add a function to lookup a TV mode by its name

[Noralf Trønnes]

Den 18.10.2022 11.33, skrev Maxime Ripard:
> On Mon, Oct 17, 2022 at 12:44:45PM +0200, Noralf Trønnes wrote:
>> Den 13.10.2022 15.18, skrev Maxime Ripard:
>>> As part of the command line parsing rework coming in the next patches,
>>> we'll need to lookup drm_connector_tv_mode values by their name, already
>>> defined in drm_tv_mode_enum_list.
>>>
>>> In order to avoid any code duplication, let's do a function that will
>>> perform a lookup of a TV mode name and return its value.
>>>
>>> Signed-off-by: Maxime Ripard 
>>> ---
>>>  drivers/gpu/drm/drm_connector.c | 24 
>>>  include/drm/drm_connector.h |  2 ++
>>>  2 files changed, 26 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/drm_connector.c 
>>> b/drivers/gpu/drm/drm_connector.c
>>> index 820f4c730b38..30611c616435 100644
>>> --- a/drivers/gpu/drm/drm_connector.c
>>> +++ b/drivers/gpu/drm/drm_connector.c
>>> @@ -991,6 +991,30 @@ static const struct drm_prop_enum_list 
>>> drm_tv_mode_enum_list[] = {
>>>  };
>>>  DRM_ENUM_NAME_FN(drm_get_tv_mode_name, drm_tv_mode_enum_list)
>>>  
>>> +/**
>>> + * drm_get_tv_mode_from_name - Translates a TV mode name into its enum 
>>> value
>>> + * @name: TV Mode name we want to convert
>>> + * @len: Length of @name
>>> + *
>>> + * Translates @name into an enum drm_connector_tv_mode.
>>> + *
>>> + * Returns: the enum value on success, a negative errno otherwise.
>>> + */
>>> +int drm_get_tv_mode_from_name(const char *name, size_t len)
>>
>> Do we really need to pass in length here? item->name has to always be
>> NUL terminated otherwise things would break elsewhere, so it shouldn't
>> be necessary AFAICS.
> 
> The only user so far is the command-line parsing code, and we might very
> well have an option after the tv_mode, something like
> 720x480i,tv_mode=NTSC,rotate=180
> 
> In this case, we won't get a NULL-terminated name.
> 

My point is that item->name will always be NUL terminated so strcmp()
will never look past that.

Noralf.

Re: [Intel-gfx] [PATCH v7 00/21] Move all drivers to a common dma-buf locking convention

[Christian König]

Am 18.10.22 um 01:07 schrieb Dmitry Osipenko:

On 10/17/22 20:22, Dmitry Osipenko wrote:

Hello,

This series moves all drivers to a dynamic dma-buf locking specification.
 From now on all dma-buf importers are made responsible for holding
dma-buf's reservation lock around all operations performed over dma-bufs
in accordance to the locking specification. This allows us to utilize
reservation lock more broadly around kernel without fearing of a potential
deadlocks.

This patchset passes all i915 selftests. It was also tested using VirtIO,
Panfrost, Lima, Tegra, udmabuf, AMDGPU and Nouveau drivers. I tested cases
of display+GPU, display+V4L and GPU+V4L dma-buf sharing (where appropriate),
which covers majority of kernel drivers since rest of the drivers share
same or similar code paths.

Changelog:

v7: - Rebased on top of recent drm-misc-next.

 - Added ack from Jason Gunthorpe to the RDMA patch.

 - Added iosys_map_clear() to dma_buf_vmap_unlocked(), making it fully
   consistent with dma_buf_vmap().

v6: - Added r-b from Michael Ruhl to the i915 patch.

 - Added acks from Sumit Semwal and updated commit message of the
   "Move dma_buf_vmap() to dynamic locking specification" patch like
   was suggested by Sumit.

 - Added "!dmabuf" check to dma_buf_vmap_unlocked() to match the locked
   variant of the function, for consistency.

v5: - Added acks and r-bs that were given to v4.

 - Changed i915 preparation patch like was suggested by Michael Ruhl.
   The scope of reservation locking is smaller now.

v4: - Added dma_buf_mmap() to the "locking convention" documentation,
   which was missed by accident in v3.

 - Added acks from Christian König, Tomasz Figa and Hans Verkuil that
   they gave to couple v3 patches.

 - Dropped the "_unlocked" postfix from function names that don't have
   the locked variant, as was requested by Christian König.

 - Factored out the per-driver preparations into separate patches
   to ease reviewing of the changes, which is now doable without the
   global dma-buf functions renaming.

 - Factored out the dynamic locking convention enforcements into separate
   patches which add the final dma_resv_assert_held(dmabuf->resv) to the
   dma-buf API functions.

v3: - Factored out dma_buf_mmap_unlocked() and attachment functions
   into aseparate patches, like was suggested by Christian König.

 - Corrected and factored out dma-buf locking documentation into
   a separate patch, like was suggested by Christian König.

 - Intel driver dropped the reservation locking fews days ago from
   its BO-release code path, but we need that locking for the imported
   GEMs because in the end that code path unmaps the imported GEM.
   So I added back the locking needed by the imported GEMs, updating
   the "dma-buf attachment locking specification" patch appropriately.

 - Tested Nouveau+Intel dma-buf import/export combo.

 - Tested udmabuf import to i915/Nouveau/AMDGPU.

 - Fixed few places in Etnaviv, Panfrost and Lima drivers that I missed
   to switch to locked dma-buf vmapping in the drm/gem: Take reservation
   lock for vmap/vunmap operations" patch. In a result invalidated the
   Christian's r-b that he gave to v2.

 - Added locked dma-buf vmap/vunmap functions that are needed for fixing
   vmappping of Etnaviv, Panfrost and Lima drivers mentioned above.
   I actually had this change stashed for the drm-shmem shrinker patchset,
   but then realized that it's already needed by the dma-buf patches.
   Also improved my tests to better cover these code paths.

v2: - Changed locking specification to avoid problems with a cross-driver
   ww locking, like was suggested by Christian König. Now the attach/detach
   callbacks are invoked without the held lock and exporter should take the
   lock.

 - Added "locking convention" documentation that explains which dma-buf
   functions and callbacks are locked/unlocked for importers and exporters,
   which was requested by Christian König.

 - Added ack from Tomasz Figa to the V4L patches that he gave to v1.

Dmitry Osipenko (21):
   dma-buf: Add unlocked variant of vmapping functions
   dma-buf: Add unlocked variant of attachment-mapping functions
   drm/gem: Take reservation lock for vmap/vunmap operations
   drm/prime: Prepare to dynamic dma-buf locking specification
   drm/armada: Prepare to dynamic dma-buf locking specification
   drm/i915: Prepare to dynamic dma-buf locking specification
   drm/omapdrm: Prepare to dynamic dma-buf locking specification
   drm/tegra: Prepare to dynamic dma-buf locking specification
   drm/etnaviv: Prepare to dynamic dma-buf locking specification
   RDMA/umem: Prepare to dynamic dma-buf locking specification
   misc: fastrpc: Prepare to dynamic dma-buf locking specification
   xen/gntdev: Prepare to dynamic dma-buf locking specificatio

Re: [Intel-gfx] i915 "GPU HANG", bisected to a2daa27c0c61 "swiotlb: simplify swiotlb_max_segment"

[Christoph Hellwig]

On Tue, Oct 18, 2022 at 10:57:37AM +0200, Jan Beulich wrote:
> Shouldn't this then be xen_pv_domain() that you use here, and - if you
> really want IS_ENABLED() in addition - CONFIG_XEN_PV?

I'll need help from people that understand Xen better than me what
the exact conditions (and maybe also comments are).

[Intel-gfx] v5.19 & v6.0 stable backport request

[Jani Nikula]

Hello stable team, please backport these two commits to stable kernels
v5.19 and v6.0:

4e78d6023c15 ("drm/i915/bios: Validate fp_timing terminator presence")
d3a7051841f0 ("drm/i915/bios: Use hardcoded fp_timing size for generating LFP 
data pointers")

References: 
https://lore.kernel.org/r/fac9a564-edff-db25-20d4-7146ae2a7...@redhat.com

Thanks,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 3/5] drm/i915/mtl: Add support for C10 phy programming

[Jani Nikula]

On Fri, 14 Oct 2022, "Kahola, Mika"  wrote:
> Maybe these could be moved into intel_cx0_reg_defs.h file?

Register definitions to intel_cx0_regs.h. See

$ find drivers/gpu/drm/i915/ -name "*_regs.h"

Any common helpers such as REG_FIELD_GET8() and friends to
i915_reg_defs.h where we already have some other sized helpers.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] alderlake crashes (random memory corruption?) with 6.0 i915 / ucode related

[Ville Syrjälä]

On Mon, Oct 17, 2022 at 04:32:28PM +0200, Hans de Goede wrote:
> Hi,
> 
> On 10/17/22 15:35, Jani Nikula wrote:
> > On Mon, 17 Oct 2022, Hans de Goede  wrote:
> >> Hi,
> >>
> >> On 10/17/22 13:19, Thorsten Leemhuis wrote:
> >>> CCing the regression mailing list, as it should be in the loop for all
> >>> regressions, as explained here:
> >>> https://www.kernel.org/doc/html/latest/admin-guide/reporting-issues.html
> >>
> >> Yes sorry about that I meant to Cc the regressions list, not you 
> >> personally,
> >> but the auto-completion picked the wrong address-book entry
> >> (and I did not notice this).
> >>
> >>> On 17.10.22 12:48, Hans de Goede wrote:
>  On 10/17/22 10:39, Jani Nikula wrote:
> > On Mon, 17 Oct 2022, Jani Nikula  wrote:
> >> On Thu, 13 Oct 2022, Hans de Goede  wrote:
> >>> With 6.0 the following WARN triggers:
> >>> drivers/gpu/drm/i915/display/intel_bios.c:477:
> >>>
> >>> drm_WARN(&i915->drm, min_size == 0,
> >>>  "Block %d min_size is zero\n", section_id);
> >>
> >> What's the value of section_id that gets printed?
> >
> > I'm guessing this is [1] fixed by commit d3a7051841f0 ("drm/i915/bios:
> > Use hardcoded fp_timing size for generating LFP data pointers") in
> > v6.1-rc1.
> >
> > I don't think this is the root cause for your issues, but I wonder if
> > you could try v6.1-rc1 or drm-tip and see if we've fixed the other stuff
> > already too?
> 
>  6.1-rc1 indeed does not trigger the drm_WARN and for now (couple of
>  reboots, running for 5 minutes now) it seems stable. 6.0.0 usually
>  crashed during boot (but not always).
> 
>  Do you think it would be worthwhile to try 6.0.0 with d3a7051841f0 ?
> >>
> >> So I have been trying 6.0.0 with d3a7051841f0 doing a whole bunch of
> >> reboots + general use and that seems stable, then I reverted it and
> >> the very first boot of the kernel with that broke again, so I'm
> >> pretty sure that d3a7051841f0 fixes things.
> >>
> >> So d3a7051841f0 seems to do more then just fix the WARN().
> > 
> > Wow, so I guess we do screw up the parsing royally then. :o
> 
> I'm running the kernel with lockdep + list-debugging enabled and
> I could not reproduce this (not easily at least) on a standard
> Fedora 6.0.0 build without that. So maybe the parsing just manages
> to write out of binds a tiny bit which just happens to hit a list_head
> somewhere ... ?

We don't parse any of the LFP data stuff if we didn't manage
to generate the data ptrs. So can't really see how that would
happen. Another theory might be that something else gets
screwed up if we fail to parse anything, but can't really
think how that would lead to list corruption either.

> 
> Either way things look stable with d3a7051841f0 and it turns out
> that Fedora already had that cherry-picked downstream in the
> 5.19.13 kernel which was stable for me too.
> 
> >> So lets try to get d3a7051841f0 added to the official stable series
> >> ASAP (I just noticed that Mark Pearson from Lenovo has already added it
> >> to Fedora's 6.0.2 build.
> > 
> > I think I'd also pick d3a7051841f0^ i.e. both commits:
> > 
> > d3a7051841f0 ("drm/i915/bios: Use hardcoded fp_timing size for generating 
> > LFP data pointers")
> > 4e78d6023c15 ("drm/i915/bios: Validate fp_timing terminator presence")
> > 
> > for stable.

Ack from me.

> 
> That sounds good, can you take care of submitting these to gkh ?
> 
> Regards,
> 
> Hans

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v5 20/22] drm/vc4: vec: Convert to the new TV mode property

[Maxime Ripard]

On Mon, Oct 17, 2022 at 12:31:31PM +0200, Noralf Trønnes wrote:
> Den 16.10.2022 20.52, skrev Mateusz Kwiatkowski:
> >>  static int vc4_vec_connector_get_modes(struct drm_connector *connector)
> >>  {
> >> -  struct drm_connector_state *state = connector->state;
> >>struct drm_display_mode *mode;
> >>  
> >> -  mode = drm_mode_duplicate(connector->dev,
> >> -vc4_vec_tv_modes[state->tv.legacy_mode].mode);
> >> +  mode = drm_mode_analog_ntsc_480i(connector->dev);
> >>if (!mode) {
> >>DRM_ERROR("Failed to create a new display mode\n");
> >>return -ENOMEM;
> >>}
> >>  
> >> +  mode->type |= DRM_MODE_TYPE_PREFERRED;
> >>drm_mode_probed_add(connector, mode);
> >>  
> >> -  return 1;
> >> +  mode = drm_mode_analog_pal_576i(connector->dev);
> >> +  if (!mode) {
> >> +  DRM_ERROR("Failed to create a new display mode\n");
> >> +  return -ENOMEM;
> >> +  }
> >> +
> >> +  drm_mode_probed_add(connector, mode);
> >> +
> >> +  return 2;
> >> +}
> > 
> > Referencing those previous discussions:
> > - 
> > https://lore.kernel.org/dri-devel/0255f7c6-0484-6456-350d-cf24f3fee...@tronnes.org/
> > - 
> > https://lore.kernel.org/dri-devel/c8f8015a-75da-afa8-ca7f-b2b134cac...@gmail.com/
> > 
> > Unconditionally setting the 480i mode as DRM_MODE_TYPE_PREFERRED causes Xorg
> > (at least on current Raspberry Pi OS) to display garbage when
> > video=Composite1:PAL is specified on the command line, so I'm afraid this 
> > won't
> > do.
> > 
> > As I see it, there are three viable solutions for this issue:
> > 
> > a) Somehow query the video= command line option from this function, and set
> >DRM_MODE_TYPE_PREFERRED appropriately. This would break the abstraction
> >provided by global DRM code, but should work fine.
> > 
> > b) Modify drm_helper_probe_add_cmdline_mode() so that it sets
> >DRM_MODE_TYPE_PREFERRED in addition to DRM_MODE_TYPE_USERDEF. This seems
> >pretty robust, but affects the entire DRM subsystem, which may break
> >userspace in different ways.
> > 
> >- Maybe this could be mitigated by adding some additional conditions, 
> > e.g.
> >  setting the PREFERRED flag only if no modes are already flagged as such
> >  and/or only if the cmdline mode is a named one (~= analog TV mode)
> > 
> > c) Forcing userspace (Xorg / Raspberry Pi OS) to get fixed and honor the 
> > USERDEF
> >flag.
> > 
> > Either way, hardcoding 480i as PREFERRED does not seem right.
> > 
> 
> My solution for this is to look at tv.mode to know which mode to mark as
> preferred. Maxime didn't like this since it changes things behind
> userspace's back. I don't see how that can cause any problems for userspace.
> 
> If userspace uses atomic and sets tv_mode, it has to know which mode to
> use before hand, so it doesn't look at the preferreded flag.
> 
> If it uses legacy and sets tv_mode, it can end up with a stale preferred
> flag, but no worse than not having the flag or that ntsc is always
> preferred.
> 
> If it doesn't change tv_mode, there's no problem, the preferred flag
> doesn't change.

I don't like it because I just see no way to make this reliable. When we
set tv_mode, we're not only going to change the preferred flag, but also
the order of the modes to make the preferred mode first.

Since we just changed the mode lists, we also want to send a hotplug
event to userspace so that it gets notified of it. It will pick up the
new preferred mode, great.

But what if it doesn't? There's no requirement for userspace to handle
hotplug events, and Kodi won't for example. So we just changed the TV
mode but not the actual mode, and that's it. It's just as broken for
Kodi as it is for X11 right now.

If we can't get a bullet-proof solution, then I'm not convinced it's
worth addressing. Especially since it's already the current state, and
it doesn't seem to bother a lot of people.

Maxime


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Re: [Intel-gfx] [PATCH v5 12/22] drm/connector: Add a function to lookup a TV mode by its name

[Maxime Ripard]

On Mon, Oct 17, 2022 at 12:44:45PM +0200, Noralf Trønnes wrote:
> Den 13.10.2022 15.18, skrev Maxime Ripard:
> > As part of the command line parsing rework coming in the next patches,
> > we'll need to lookup drm_connector_tv_mode values by their name, already
> > defined in drm_tv_mode_enum_list.
> > 
> > In order to avoid any code duplication, let's do a function that will
> > perform a lookup of a TV mode name and return its value.
> > 
> > Signed-off-by: Maxime Ripard 
> > ---
> >  drivers/gpu/drm/drm_connector.c | 24 
> >  include/drm/drm_connector.h |  2 ++
> >  2 files changed, 26 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/drm_connector.c 
> > b/drivers/gpu/drm/drm_connector.c
> > index 820f4c730b38..30611c616435 100644
> > --- a/drivers/gpu/drm/drm_connector.c
> > +++ b/drivers/gpu/drm/drm_connector.c
> > @@ -991,6 +991,30 @@ static const struct drm_prop_enum_list 
> > drm_tv_mode_enum_list[] = {
> >  };
> >  DRM_ENUM_NAME_FN(drm_get_tv_mode_name, drm_tv_mode_enum_list)
> >  
> > +/**
> > + * drm_get_tv_mode_from_name - Translates a TV mode name into its enum 
> > value
> > + * @name: TV Mode name we want to convert
> > + * @len: Length of @name
> > + *
> > + * Translates @name into an enum drm_connector_tv_mode.
> > + *
> > + * Returns: the enum value on success, a negative errno otherwise.
> > + */
> > +int drm_get_tv_mode_from_name(const char *name, size_t len)
> 
> Do we really need to pass in length here? item->name has to always be
> NUL terminated otherwise things would break elsewhere, so it shouldn't
> be necessary AFAICS.

The only user so far is the command-line parsing code, and we might very
well have an option after the tv_mode, something like
720x480i,tv_mode=NTSC,rotate=180

In this case, we won't get a NULL-terminated name.

Maxime

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part 
of pps_get_register() cleanup
URL   : https://patchwork.freedesktop.org/series/109820/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12254 -> Patchwork_109820v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/index.html

Participating hosts (45 -> 43)
--

  Additional (2): fi-hsw-4770 bat-atsm-1 
  Missing(4): fi-kbl-soraka fi-bdw-samus fi-icl-u2 fi-kbl-guc 

Known issues


  Here are the changes found in Patchwork_109820v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-gvtdvm:  NOTRUN -> [FAIL][1] ([fdo#103375])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/fi-bdw-gvtdvm/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#3012])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rpm@module-reload:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][3] ([i915#7221])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/fi-hsw-4770/igt@i915_pm_...@module-reload.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-bdw-gvtdvm:  NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/fi-bdw-gvtdvm/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-bdw-gvtdvm:  NOTRUN -> [SKIP][7] ([fdo#109271])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/fi-bdw-gvtdvm/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1072]) +3 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#4312] / 
[i915#5594])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/fi-hsw-4770/igt@run...@aborted.html

  
 Warnings 

  * igt@i915_suspend@basic-s3-without-i915:
- fi-bdw-gvtdvm:  [INCOMPLETE][10] ([i915#146]) -> [FAIL][11] 
([fdo#103375])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12254/fi-bdw-gvtdvm/igt@i915_susp...@basic-s3-without-i915.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/fi-bdw-gvtdvm/igt@i915_susp...@basic-s3-without-i915.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
  [i915#7220]: https://gitlab.freedesktop.org/drm/intel/issues/7220
  [i915#7221]: https://gitlab.freedesktop.org/drm/intel/issues/7221


Build changes
-

  * Linux: CI_DRM_12254 -> Patchwork_109820v1

  CI-20190529: 20190529
  CI_DRM_12254: 2e6cdde56f896add665edb8d2f6d3dfce8b1b3b6 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7018: 8312a2fe3f3287ba4ac4bc8d100de0734480f482 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_109820v1: 2e6cdde56f896add665edb8d2f6d3dfce8b1b3b6 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

d30c74ae83d9 drm/i915/pps: Enable 2nd pps for dual EDP scenario
9826402fcca7 drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() 
cleanup

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109820v1/index.html

Re: [Intel-gfx] [PATCH] drm/i915: use intel_uncore_rmw when appropriate

[Ville Syrjälä]

On Mon, Oct 17, 2022 at 12:37:56PM +0200, Andrzej Hajda wrote:
> This patch replaces all occurences of the form
> intel_uncore_write(reg, intel_uncore_read(reg) OP val)
> with intel_uncore_rmw.
> 
> Signed-off-by: Andrzej Hajda 
> ---
> Apparently I have missed this pattern during refactoring.
> 
> Regards
> Andrzej
> ---
>  drivers/gpu/drm/i915/gt/intel_rps.c |   4 +-
>  drivers/gpu/drm/i915/intel_pm.c | 190 ++--
>  2 files changed, 68 insertions(+), 126 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index fc23c562d9b2a7..070005dd0da476 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -625,9 +625,7 @@ static void gen5_rps_disable(struct intel_rps *rps)
>   rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
>  
>   /* Ack interrupts, disable EFC interrupt */
> - intel_uncore_write(uncore, MEMINTREN,
> -intel_uncore_read(uncore, MEMINTREN) &
> -~MEMINT_EVAL_CHG_EN);
> + intel_uncore_rmw(uncore, MEMINTREN, MEMINT_EVAL_CHG_EN, 0);
>   intel_uncore_write(uncore, MEMINTRSTS, MEMINT_EVAL_CHG);
>  
>   /* Go back to the starting frequency */

Maybe split the gt stuff to a separate patch?

> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 19d4a88184d7a1..4d264147ada94b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c

> @@ -4293,14 +4272,12 @@ static void lpt_init_clock_gating(struct 
> drm_i915_private *dev_priv)
>* disabled when not needed anymore in order to save power.
>*/
>   if (HAS_PCH_LPT_LP(dev_priv))
> - intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D,
> -intel_uncore_read(&dev_priv->uncore, 
> SOUTH_DSPCLK_GATE_D) |
> -PCH_LP_PARTITION_LEVEL_DISABLE);
> + intel_uncore_rmw(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, 0,
^

I'd put the newline there in these cases. That way everything we're
doing to the register value would be neatly on the same line instead
of spread around like this.

> +  PCH_LP_PARTITION_LEVEL_DISABLE);
>  
>   /* WADPOClockGatingDisable:hsw */
> - intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A),
> -intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A)) 
> |
> -TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> + intel_uncore_rmw(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A), 0,
> +  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
>  }
>  
>  static void lpt_suspend_hw(struct drm_i915_private *dev_priv)

> @@ -4532,43 +4494,37 @@ static void bdw_init_clock_gating(struct 
> drm_i915_private *dev_priv)
>   enum pipe pipe;
>  
>   /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
> - intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A),
> -intel_uncore_read(&dev_priv->uncore, 
> CHICKEN_PIPESL_1(PIPE_A)) |
> -HSW_FBCQ_DIS);
> + intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, 
> HSW_FBCQ_DIS);
>  
>   /* WaSwitchSolVfFArbitrationPriority:bdw */
> - intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, 
> intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
> + intel_uncore_rmw(&dev_priv->uncore, GAM_ECOCHK, 0, 
> HSW_ECOCHK_ARB_PRIO_SOL);
>  
>   /* WaPsrDPAMaskVBlankInSRD:bdw */
> - intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
> -intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | 
> DPA_MASK_VBLANK_SRD);
> + intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PAR1_1, 0, 
> DPA_MASK_VBLANK_SRD);
>  
>   for_each_pipe(dev_priv, pipe) {
>   /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
> - intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
> -intel_uncore_read(&dev_priv->uncore, 
> CHICKEN_PIPESL_1(pipe)) |
> -BDW_DPRS_MASK_VBLANK_SRD);
> + intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe), 0,
> +  BDW_DPRS_MASK_VBLANK_SRD);
>   }
>  
>   /* WaVSRefCountFullforceMissDisable:bdw */
>   /* WaDSRefCountFullforceMissDisable:bdw */
> - intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
> -intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
> -~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
> + intel_uncore_rmw(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
> +  (GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME), 
> 0);

Useless parens there. Ditto in the other copy.

This stuff really doesn't belong here anyway. I thought someone would have
hoisted all the gt stuff into a more appropriate place by now. But I guess
not.

Re: [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario

[Manna, Animesh]

Thanks Jani for review.
Floated a new version after addressing the review comments in this series.
https://patchwork.freedesktop.org/series/109820/

Regards,
Animesh

> -Original Message-
> From: Nikula, Jani 
> Sent: Monday, October 17, 2022 6:39 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Manna, Animesh ; Ville Syrjälä
> ; Shankar, Uma 
> Subject: Re: [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario
> 
> On Mon, 10 Oct 2022, Animesh Manna  wrote:
> > From display gen12 onwards to support dual EDP two instances of pps added.
> > Currently backlight controller and pps instance can be mapped together
> > for a specific panel. Currently dual PPS support is broken. This patch
> > fixes it and enables for display 12+.
> >
> > v1: Iniital revision.
> > v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init.
> > [Jani]
> > v3: Set pps_id to -1 for pnpid type of panel which will be used by
> > bxt_power_sequencer_idx() to set 2nd pps instance as default for 2nd
> > EDP panel. [Jani]
> > v4: Early return for PANEL_TYPE_FALLBACK. [Jani]
> >
> > Cc: Jani Nikula 
> > Cc: Ville Syrjälä 
> > Cc: Uma Shankar 
> > Signed-off-by: Animesh Manna 
> > ---
> >  drivers/gpu/drm/i915/display/intel_bios.c  | 13 +++--
> >  drivers/gpu/drm/i915/display/intel_bios.h  |  2 +-
> >  drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
> >  drivers/gpu/drm/i915/display/intel_dp.c| 10 +++---
> >  drivers/gpu/drm/i915/display/intel_pps.c   | 12 +++-
> >  5 files changed, 31 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index c2987f2c2b2e..dd3cd2ca815d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -3183,15 +3183,22 @@ void intel_bios_init(struct drm_i915_private
> *i915)
> > kfree(oprom_vbt);
> >  }
> >
> > -void intel_bios_init_panel(struct drm_i915_private *i915,
> > +bool intel_bios_init_panel(struct drm_i915_private *i915,
> >struct intel_panel *panel,
> >const struct intel_bios_encoder_data *devdata,
> >const struct edid *edid)
> >  {
> > init_vbt_panel_defaults(panel);
> > -
> 
> Please don't do superfluous whitespace changes.
> 
> > panel->vbt.panel_type = get_panel_type(i915, devdata, edid);
> >
> > +   if (panel->vbt.panel_type == PANEL_TYPE_PNPID ||
> > +   panel->vbt.panel_type == PANEL_TYPE_FALLBACK) {
> > +   panel->vbt.edp.pps_id = -1;
> > +
> > +   if (!edid && intel_bios_encoder_supports_edp(devdata))
> > +   return true;
> > +   }
> > +
> 
>   if (panel->vbt.panel_type == PANEL_TYPE_FALLBACK && !edid) {
>   panel->vbt.backlight.controller = -1;
>   return true;
>   }
> 
> > parse_panel_options(i915, panel);
> > parse_generic_dtd(i915, panel);
> > parse_lfp_data(i915, panel);
> > @@ -3203,6 +3210,8 @@ void intel_bios_init_panel(struct drm_i915_private
> *i915,
> > parse_psr(i915, panel);
> > parse_mipi_config(i915, panel);
> > parse_mipi_sequence(i915, panel);
> > +
> > +   return false;
> >  }
> >
> >  /**
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.h
> > b/drivers/gpu/drm/i915/display/intel_bios.h
> > index e375405a7828..f8ef0274f3ee 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.h
> > @@ -232,7 +232,7 @@ struct mipi_pps_data {  } __packed;
> >
> >  void intel_bios_init(struct drm_i915_private *dev_priv); -void
> > intel_bios_init_panel(struct drm_i915_private *dev_priv,
> > +bool intel_bios_init_panel(struct drm_i915_private *dev_priv,
> >struct intel_panel *panel,
> >const struct intel_bios_encoder_data *devdata,
> >const struct edid *edid);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 44ab296c1f04..37e8309207bf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -307,6 +307,7 @@ struct intel_vbt_panel_data {
> > int preemphasis;
> > int vswing;
> > int bpp;
> > +   int pps_id;
> 
> Unnecessary.
> 
> > struct edp_power_seq pps;
> > u8 drrs_msa_timing_delay;
> > bool low_vswing;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 70b06806ec0d..50d9223562e2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5235,6 +5235,7 @@ static bool intel_edp_init_connector(struct intel_dp
> *intel_dp,
> > struct intel_encoder *encoder = &dp_to_dig_port(intel

[Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup

[Animesh Manna]

Simplified pps_get_register() which use get_pps_idx() hook to derive the
pps instance and get_pps_idx() will be initialized at pps_init().

v1: Initial version. Got r-b from Jani.
v2: Corrected unintentional change around memset() call. [Jani]

Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Uma Shankar 
Signed-off-by: Animesh Manna 
---
 drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
 drivers/gpu/drm/i915/display/intel_pps.c   | 14 +-
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index e2b853e9e51d..44ab296c1f04 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1694,6 +1694,7 @@ struct intel_dp {
u8 (*preemph_max)(struct intel_dp *intel_dp);
u8 (*voltage_max)(struct intel_dp *intel_dp,
  const struct intel_crtc_state *crtc_state);
+   int (*get_pps_idx)(struct intel_dp *intel_dp);
 
/* Displayport compliance testing */
struct intel_dp_compliance compliance;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c 
b/drivers/gpu/drm/i915/display/intel_pps.c
index 21944f5bf3a8..9ed62c891b8c 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -365,11 +365,8 @@ static void intel_pps_get_registers(struct intel_dp 
*intel_dp,
int pps_idx = 0;
 
memset(regs, 0, sizeof(*regs));
-
-   if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
-   pps_idx = bxt_power_sequencer_idx(intel_dp);
-   else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-   pps_idx = vlv_power_sequencer_pipe(intel_dp);
+   if (intel_dp->get_pps_idx)
+   pps_idx = intel_dp->get_pps_idx(intel_dp);
 
regs->pp_ctrl = PP_CONTROL(pps_idx);
regs->pp_stat = PP_STATUS(pps_idx);
@@ -1432,6 +1429,13 @@ void intel_pps_init(struct intel_dp *intel_dp)
intel_dp->pps.initializing = true;
INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
 
+   if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+   intel_dp->get_pps_idx = bxt_power_sequencer_idx;
+   else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+   intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
+   else
+   intel_dp->get_pps_idx = NULL;
+
pps_init_timestamps(intel_dp);
 
with_intel_pps_lock(intel_dp, wakeref) {
-- 
2.29.0

[Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario

[Animesh Manna]

>From display gen12 onwards to support dual EDP two instances of pps added.
Currently backlight controller and pps instance can be mapped together
for a specific panel. Currently dual PPS support is broken. This patch
fixes it and enables for display 12+.

v1: Iniital revision.
v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. [Jani]
v3: Set pps_id to -1 for pnpid type of panel which will be used by
bxt_power_sequencer_idx() to set 2nd pps instance as default for
2nd EDP panel. [Jani]
v4: Early return for PANEL_TYPE_FALLBACK. [Jani]
v5: Removed additional pps_id variable and reused backlight
controller. [Jani]

Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Uma Shankar 
Signed-off-by: Animesh Manna 
---
 drivers/gpu/drm/i915/display/intel_bios.c |  9 -
 drivers/gpu/drm/i915/display/intel_bios.h |  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c   | 10 +++---
 drivers/gpu/drm/i915/display/intel_pps.c  | 12 +++-
 4 files changed, 27 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index c2987f2c2b2e..1c1eea061fbb 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3183,7 +3183,7 @@ void intel_bios_init(struct drm_i915_private *i915)
kfree(oprom_vbt);
 }
 
-void intel_bios_init_panel(struct drm_i915_private *i915,
+bool intel_bios_init_panel(struct drm_i915_private *i915,
   struct intel_panel *panel,
   const struct intel_bios_encoder_data *devdata,
   const struct edid *edid)
@@ -3192,6 +3192,11 @@ void intel_bios_init_panel(struct drm_i915_private *i915,
 
panel->vbt.panel_type = get_panel_type(i915, devdata, edid);
 
+   if (panel->vbt.panel_type == PANEL_TYPE_FALLBACK && !edid) {
+   panel->vbt.backlight.controller = -1;
+   return true;
+   }
+
parse_panel_options(i915, panel);
parse_generic_dtd(i915, panel);
parse_lfp_data(i915, panel);
@@ -3203,6 +3208,8 @@ void intel_bios_init_panel(struct drm_i915_private *i915,
parse_psr(i915, panel);
parse_mipi_config(i915, panel);
parse_mipi_sequence(i915, panel);
+
+   return false;
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h 
b/drivers/gpu/drm/i915/display/intel_bios.h
index e375405a7828..f8ef0274f3ee 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -232,7 +232,7 @@ struct mipi_pps_data {
 } __packed;
 
 void intel_bios_init(struct drm_i915_private *dev_priv);
-void intel_bios_init_panel(struct drm_i915_private *dev_priv,
+bool intel_bios_init_panel(struct drm_i915_private *dev_priv,
   struct intel_panel *panel,
   const struct intel_bios_encoder_data *devdata,
   const struct edid *edid);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index a060903891b2..6d3a0fe06359 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5234,6 +5234,7 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
bool has_dpcd;
struct edid *edid;
+   bool retry;
 
if (!intel_dp_is_edp(intel_dp))
return true;
@@ -5253,6 +5254,9 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
return false;
}
 
+   retry = intel_bios_init_panel(dev_priv, &intel_connector->panel,
+ encoder->devdata, NULL);
+
intel_pps_init(intel_dp);
 
/* Cache DPCD and EDID for edp. */
@@ -5287,9 +5291,9 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
edid = ERR_PTR(-ENOENT);
}
intel_connector->edid = edid;
-
-   intel_bios_init_panel(dev_priv, &intel_connector->panel,
- encoder->devdata, IS_ERR(edid) ? NULL : edid);
+   if (retry)
+   intel_bios_init_panel(dev_priv, &intel_connector->panel,
+ encoder->devdata, IS_ERR(edid) ? NULL : 
edid);
 
intel_panel_add_edid_fixed_modes(intel_connector, true);
 
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c 
b/drivers/gpu/drm/i915/display/intel_pps.c
index 9ed62c891b8c..f9899305d6e0 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -218,6 +218,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
/* We should never land here with regular DP ports */
drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
 
+   if (backlight_controller == -1) {
+   /*
+* Use 2nd PPS instance as default for 2nd EDP panel.
+*/
+  

Re: [Intel-gfx] [PATCH] drm/vc4: vec: Add support for PAL-60

[Maxime Ripard]

Hi,

On Sun, Oct 16, 2022 at 09:46:49PM +0200, Mateusz Kwiatkowski wrote:
> @@ -308,14 +324,15 @@ static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] 
> = {
>  };
>  
>  static inline const struct vc4_vec_tv_mode *
> -vc4_vec_tv_mode_lookup(unsigned int mode)
> +vc4_vec_tv_mode_lookup(unsigned int mode, u16 htotal)
>  {
>   unsigned int i;
>  
>   for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) {
>   const struct vc4_vec_tv_mode *tv_mode = &vc4_vec_tv_modes[i];
>  
> - if (tv_mode->mode == mode)
> + if (tv_mode->mode == mode &&
> + tv_mode->expected_htotal == htotal)
>   return tv_mode;

Is there any reason we're not using the refresh rate to filter this? It
seems more natural to me.

Maxime


signature.asc
Description: PGP signature

[Intel-gfx] ✗ Fi.CI.BUILD: failure for i915 "GPU HANG", bisected to a2daa27c0c61 "swiotlb: simplify swiotlb_max_segment"

[Patchwork]

== Series Details ==

Series: i915 "GPU HANG", bisected to a2daa27c0c61 "swiotlb: simplify 
swiotlb_max_segment"
URL   : https://patchwork.freedesktop.org/series/109817/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/109817/revisions/1/mbox/ not 
applied
Applying: i915 "GPU HANG", bisected to a2daa27c0c61 "swiotlb: simplify 
swiotlb_max_segment"
error: No valid patches in input (allow with "--allow-empty")
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 i915 "GPU HANG", bisected to a2daa27c0c61 "swiotlb: 
simplify swiotlb_max_segment"
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".