Re: [Intel-gfx] [PATCH v3 6/6] freezer, sched: Rewrite core freezer logic

[Chen Yu]

On 2022-10-26 at 13:43:00 +0200, Peter Zijlstra wrote:
> On Wed, Oct 26, 2022 at 01:32:31PM +0300, Ville Syrjälä wrote:
> > Short form looks to be this:
> > <4>[  355.437846] 1 lock held by rs:main Q:Reg/359:
> > <4>[  355.438418]  #0: 88844693b758 (>__lock){-.-.}-{2:2}, at: 
> > raw_spin_rq_lock_nested+0x1b/0x30
> > <4>[  355.438432] rs:main Q:Reg/359 holding locks while freezing
> 
> > <4>[  355.438429] [ cut here ]
> > <4>[  355.438432] rs:main Q:Reg/359 holding locks while freezing
> > <4>[  355.438439] WARNING: CPU: 0 PID: 6211 at kernel/freezer.c:134 
> > __set_task_frozen+0x86/0xb0
> > <4>[  355.438447] Modules linked in: snd_hda_intel i915 mei_hdcp mei_pxp 
> > drm_display_helper drm_kms_helper vgem drm_shmem_helper snd_hda_codec_hdmi 
> > snd_hda_codec_realtek snd_hda_codec_generic ledtrig_audio snd_intel_dspcfg 
> > snd_hda_codec snd_hwdep snd_hda_core snd_pcm prime_numbers ttm drm_buddy 
> > syscopyarea sysfillrect sysimgblt fb_sys_fops fuse x86_pkg_temp_thermal 
> > coretemp kvm_intel btusb btrtl btbcm btintel kvm irqbypass bluetooth 
> > crct10dif_pclmul crc32_pclmul ecdh_generic ghash_clmulni_intel ecc e1000e 
> > mei_me i2c_i801 ptp mei i2c_smbus pps_core lpc_ich video wmi [last 
> > unloaded: drm_kms_helper]
> > <4>[  355.438521] CPU: 0 PID: 6211 Comm: rtcwake Tainted: G U   
> >   6.1.0-rc2-CI_DRM_12295-g3844a56a0922+ #1
> > <4>[  355.438526] Hardware name:  /NUC5i7RYB, BIOS 
> > RYBDWi35.86A.0385.2020.0519.1558 05/19/2020
> > <4>[  355.438530] RIP: 0010:__set_task_frozen+0x86/0xb0
> > <4>[  355.438536] Code: 83 60 09 00 00 85 c0 74 2a 48 89 df e8 ac 02 9b 00 
> > 8b 93 38 05 00 00 48 8d b3 48 07 00 00 48 c7 c7 a0 62 2b 82 e8 ee c1 9a 00 
> > <0f> 0b c6 05 51 75 e3 02 01 c7 43 18 00 80 00 00 b8 00 80 00 00 5b
> > <4>[  355.438541] RSP: 0018:c900012cbcf0 EFLAGS: 00010086
> > <4>[  355.438546] RAX:  RBX: 88810d090040 RCX: 
> > 0004
> > <4>[  355.438550] RDX: 0004 RSI: f5de RDI: 
> > 
> > <4>[  355.438553] RBP:  R08:  R09: 
> > c000f5de
> > <4>[  355.438557] R10: 002335f8 R11: c900012cbb88 R12: 
> > 0246
> > <4>[  355.438561] R13: 81165430 R14:  R15: 
> > 88810d090040
> > <4>[  355.438565] FS:  7fcfa43c7740() GS:88844680() 
> > knlGS:
> > <4>[  355.438569] CS:  0010 DS:  ES:  CR0: 80050033
> > <4>[  355.438582] CR2: 7fceb380f6b8 CR3: 000117c5c004 CR4: 
> > 003706f0
> > <4>[  355.438586] Call Trace:
> > <4>[  355.438589]  
> > <4>[  355.438592]  task_call_func+0xc4/0xe0
> > <4>[  355.438600]  freeze_task+0x84/0xe0
> > <4>[  355.438607]  try_to_freeze_tasks+0xac/0x260
> > <4>[  355.438616]  freeze_processes+0x56/0xb0
> > <4>[  355.438622]  pm_suspend.cold.7+0x1d9/0x31c
> > <4>[  355.438629]  state_store+0x7b/0xe0
> > <4>[  355.438637]  kernfs_fop_write_iter+0x124/0x1c0
> > <4>[  355.438644]  vfs_write+0x34f/0x4e0
> > <4>[  355.438655]  ksys_write+0x57/0xd0
> > <4>[  355.438663]  do_syscall_64+0x3a/0x90
> > <4>[  355.438670]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
> 
> Oh I think I see what's going on.
> 
> It's a very narrow race between schedule() and task_call_func().
> 
>   CPU0CPU1
> 
>   __schedule()
> rq_lock();
> prev_state = READ_ONCE(prev->__state);
> if (... && prev_state) {
>   deactivate_tasl(rq, prev, ...)
> prev->on_rq = 0;
> 
>   task_call_func()
> 
> raw_spin_lock_irqsave(p->pi_lock);
> state = READ_ONCE(p->__state);
> smp_rmb();
> if (... || p->on_rq) // 
> false!!!
>   rq = __task_rq_lock()
> 
> ret = func();
> 
> next = pick_next_task();
> rq = context_switch(prev, next)
>   prepare_lock_switch()
> spin_release(&__rq_lockp(rq)->dep_map...)
> 
> 
> 
> So while the task is on it's way out, it still holds rq->lock for a
> little while, and right then task_call_func() comes in and figures it
> doesn't need rq->lock anymore (because the task is already dequeued --
> but still running there) and then the __set_task_frozen() thing observes
> it's holding rq->lock and yells murder.
> 
> Could you please give the below a spin?
> 
> ---
> diff --git a/kernel/sched/core.c b/kernel/sched/core.c
> index cb2aa2b54c7a..f519f44cd4c7 100644
> --- a/kernel/sched/core.c
> +++ b/kernel/sched/core.c
> @@ -4200,6 +4200,37 @@ try_to_wake_up(struct task_struct *p, unsigned int 
> state, int wake_flags)
>   return success;
>  }
>  
> +static bool __task_needs_rq_lock(struct task_struct *p)
> +{
> + 

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: CAGF and RC6 changes for MTL (rev11)

[Vudum, Lakshminarayana]

Re-reported.

-Original Message-
From: Dixit, Ashutosh  
Sent: Tuesday, October 25, 2022 10:26 AM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana 
Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: CAGF and RC6 changes 
for MTL (rev11)

On Mon, 24 Oct 2022 18:25:06 -0700, Patchwork wrote:
>

Hi Lakshmi,

The below failures are unrelated to this series.

Thanks.
--
Ashutosh

> Patch Details
>
> Series:  i915: CAGF and RC6 changes for MTL (rev11)
> URL: https://patchwork.freedesktop.org/series/108156/
> State:   failure
> Details: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.htm
> l
>
> CI Bug Log - changes from CI_DRM_12288 -> Patchwork_108156v11
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with Patchwork_108156v11 absolutely 
> need to be verified manually.
>
> If you think the reported changes have nothing to do with the changes 
> introduced in Patchwork_108156v11, please notify your bug team to 
> allow them to document this new failure mode, which will reduce false 
> positives in CI.
>
> External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.htm
> l
>
> Participating hosts (41 -> 40)
>
> Additional (1): bat-atsm-1
> Missing (2): fi-ctg-p8600 fi-icl-u2
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in 
> Patchwork_108156v11:
>
> IGT changes
>
> Possible regressions
>
>   • igt@gem_exec_parallel@engines@contexts:
>
>   □ fi-bsw-nick: PASS -> INCOMPLETE
>   • igt@i915_selftest@live@hugepages:
>
>   □ fi-cfl-8109u: PASS -> DMESG-FAIL
>
>   □ fi-skl-guc: PASS -> DMESG-FAIL
>
>   • igt@i915_suspend@basic-s3-without-i915:
>
>   □ fi-rkl-11600: NOTRUN -> INCOMPLETE
>
> Suppressed

Re: [Intel-gfx] [PATCH v3] drm/i915/gvt: fix double free bug in split_2MB_gtt_entry

[Dave Airlie]

On Thu, 27 Oct 2022 at 13:26, Zheng Hacker  wrote:
>
> Dave Airlie  于2022年10月27日周四 08:01写道：
> >
> > On Fri, 7 Oct 2022 at 11:38, Zheng Wang  wrote:
> > >
> > > If intel_gvt_dma_map_guest_page failed, it will call
> > > ppgtt_invalidate_spt, which will finally free the spt.
> > > But the caller does not notice that, it will free spt again in error path.
> > >
> > > Fix this by spliting invalidate and free in ppgtt_invalidate_spt.
> > > Only free spt when in good case.
> > >
> > > Reported-by: Zheng Wang 
> > > Signed-off-by: Zheng Wang 
> >
> > Has this landed in a tree yet, since it's a possible CVE, might be
> > good to merge it somewhere.
> >
> > Dave.
> >
>
> Hi Dave,
>
> This patched hasn't been merged yet. Could you please help with this?

I'll add some more people who can probably look at it.

Dave.

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/display: Do both crawl and squash 
when changing cdclk
URL   : https://patchwork.freedesktop.org/series/110199/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12304 -> Patchwork_110199v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/index.html

Participating hosts (39 -> 38)
--

  Additional (2): fi-rkl-11600 fi-icl-u2 
  Missing(3): fi-ctg-p8600 fi-hsw-4770 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110199v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}:   [DMESG-WARN][1] ([i915#5537]) -> [WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/bat-rpls-2/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/bat-rpls-2/igt@i915_pm_...@module-reload.html

  
Known issues


  Here are the changes found in Patchwork_110199v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-rkl-11600:   NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html
- fi-icl-u2:  NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-rkl-11600:   NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_tiled_pread_basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][7] ([i915#3282])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600:   NOTRUN -> [SKIP][8] ([i915#3012])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [PASS][9] -> [INCOMPLETE][10] ([i915#3303] / 
[i915#4785])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   NOTRUN -> [INCOMPLETE][11] ([i915#4817])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-rkl-guc: NOTRUN -> [SKIP][12] ([fdo#111827])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-guc/igt@kms_chamel...@common-hpd-after-suspend.html
- bat-adlp-4: NOTRUN -> [SKIP][13] ([fdo#111827])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/bat-adlp-4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-rkl-11600:   NOTRUN -> [SKIP][14] ([fdo#111827]) +7 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@kms_chamel...@hdmi-hpd-fast.html
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([fdo#111827]) +8 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-rkl-11600:   NOTRUN -> [SKIP][16] ([i915#4103])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
- fi-icl-u2:  NOTRUN -> [SKIP][17] ([i915#4103])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-rkl-11600:   NOTRUN -> [SKIP][18] ([fdo#109285] / [i915#4098])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@kms_force_connector_ba...@force-load-detect.html
- fi-icl-u2:  NOTRUN -> [SKIP][19] ([fdo#109285])
   [19]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for i915: CAGF and RC6 changes for MTL (rev11)

[Patchwork]

== Series Details ==

Series: i915: CAGF and RC6 changes for MTL (rev11)
URL   : https://patchwork.freedesktop.org/series/108156/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12288 -> Patchwork_108156v11


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.html

Participating hosts (41 -> 41)
--

  Additional (2): fi-kbl-soraka bat-atsm-1 
  Missing(2): fi-ctg-p8600 fi-icl-u2 

Known issues


  Here are the changes found in Patchwork_108156v11 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271]) +9 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html

  * igt@gem_exec_parallel@engines@contexts:
- fi-bsw-nick:[PASS][2] -> [INCOMPLETE][3] ([i915#7311])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-bsw-nick/igt@gem_exec_parallel@engi...@contexts.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-bsw-nick/igt@gem_exec_parallel@engi...@contexts.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][6] ([i915#5334])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [PASS][7] -> [INCOMPLETE][8] ([i915#4983])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][9] ([i915#1886])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@gtt:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][10] ([i915#7319])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@i915_selftest@l...@gtt.html

  * igt@i915_selftest@live@hugepages:
- fi-cfl-8109u:   [PASS][11] -> [DMESG-FAIL][12] ([i915#7311])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-cfl-8109u/igt@i915_selftest@l...@hugepages.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-cfl-8109u/igt@i915_selftest@l...@hugepages.html
- fi-skl-guc: [PASS][13] -> [DMESG-FAIL][14] ([i915#7311])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-skl-guc/igt@i915_selftest@l...@hugepages.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-skl-guc/igt@i915_selftest@l...@hugepages.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   NOTRUN -> [INCOMPLETE][15] ([i915#4817])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-soraka:  NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@runner@aborted:
- fi-cfl-8109u:   NOTRUN -> [FAIL][18] ([i915#4312])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-cfl-8109u/igt@run...@aborted.html
- fi-skl-guc: NOTRUN -> [FAIL][19] ([i915#4312])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-skl-guc/igt@run...@aborted.html
- fi-bsw-nick:NOTRUN -> [FAIL][20] ([i915#4312])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-bsw-nick/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_huc_copy@huc-copy:
- {bat-dg2-8}:[FAIL][21] ([i915#7029]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/bat-dg2-8/igt@gem_huc_c...@huc-copy.html
   [22]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for Add DG2 OA support (rev11)

[Patchwork]

== Series Details ==

Series: Add DG2 OA support (rev11)
URL   : https://patchwork.freedesktop.org/series/107584/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12304 -> Patchwork_107584v11


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/index.html

Participating hosts (39 -> 38)
--

  Additional (1): fi-tgl-dsi 
  Missing(2): fi-ctg-p8600 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_107584v11:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}:   [DMESG-WARN][1] ([i915#5537]) -> [WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/bat-rpls-2/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/bat-rpls-2/igt@i915_pm_...@module-reload.html

  
Known issues


  Here are the changes found in Patchwork_107584v11 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][3] -> [INCOMPLETE][4] ([i915#7120])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/fi-bsw-nick/igt@i915_selftest@l...@execlists.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-rkl-guc: NOTRUN -> [SKIP][5] ([fdo#111827])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/fi-rkl-guc/igt@kms_chamel...@common-hpd-after-suspend.html
- bat-adlp-4: NOTRUN -> [SKIP][6] ([fdo#111827])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/bat-adlp-4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlp-4: NOTRUN -> [SKIP][7] ([i915#3546])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/bat-adlp-4/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  * igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#4312])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/fi-bsw-nick/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}:   [DMESG-WARN][9] ([i915#2867]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-adlm-1}:   [DMESG-WARN][11] ([i915#2867]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html
- {bat-rpls-1}:   [DMESG-WARN][13] ([i915#6687]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [INCOMPLETE][15] ([i915#4983]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@hangcheck:
- {bat-dg2-9}:[INCOMPLETE][17] -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/bat-dg2-9/igt@i915_selftest@l...@hangcheck.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/bat-dg2-9/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@hugepages:
- {bat-rpls-2}:   [DMESG-WARN][19] ([i915#5278]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/bat-rpls-2/igt@i915_selftest@l...@hugepages.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/bat-rpls-2/igt@i915_selftest@l...@hugepages.html

  * igt@i915_selftest@live@migrate:
- bat-adlp-4: [INCOMPLETE][21] ([i915#7308]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/bat-adlp-4/igt@i915_selftest@l...@migrate.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/bat-adlp-4/igt@i915_selftest@l...@migrate.html

  * igt@i915_suspend@basic-s3-without-i915:
- {bat-rpls-2}:   [FAIL][23] ([i915#6559]) 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DG2 OA support (rev11)

[Patchwork]

== Series Details ==

Series: Add DG2 OA support (rev11)
URL   : https://patchwork.freedesktop.org/series/107584/
State : warning

== Summary ==

Error: dim checkpatch failed
c780bcbe9c6f drm/i915/perf: Fix OA filtering logic for GuC mode
2401ac2c7fc1 drm/i915/perf: Add 32-bit OAG and OAR formats for DG2
5d610536496e drm/i915/perf: Fix noa wait predication for DG2
8150f38baaf3 drm/i915/perf: Determine gen12 oa ctx offset at runtime
f8424d7d4682 drm/i915/perf: Enable bytes per clock reporting in OA
332119d05b01 drm/i915/perf: Simply use stream->ctx
9973045e0a8a drm/i915/perf: Move gt-specific data from i915->perf to gt->perf
68ee20b88b7c drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops
93a32bbfa186 drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers
a4ad0fa8da87 drm/i915/perf: Store a pointer to oa_format in oa_buffer
4d0cdc933cfc drm/i915/perf: Add Wa_1508761755:dg2
2369dd487b2d drm/i915/perf: Apply Wa_18013179988
b3ae6a1bea90 drm/i915/perf: Save/restore EU flex counters across reset
11e115088bfc drm/i915/guc: Support OA when Wa_16011777198 is enabled
-:72: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#72: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:208:
+   GEM_BUG_ON(id >= SLPC_MAX_PARAM);

total: 0 errors, 1 warnings, 0 checks, 151 lines checked
304e1330b825 drm/i915/perf: complete programming whitelisting for XEHPSDV
dca80a1d9ead drm/i915/perf: Enable OA for DG2

Re: [Intel-gfx] [PATCH v3] drm/i915/gvt: fix double free bug in split_2MB_gtt_entry

[Zheng Hacker]

Dave Airlie  于2022年10月27日周四 08:01写道：
>
> On Fri, 7 Oct 2022 at 11:38, Zheng Wang  wrote:
> >
> > If intel_gvt_dma_map_guest_page failed, it will call
> > ppgtt_invalidate_spt, which will finally free the spt.
> > But the caller does not notice that, it will free spt again in error path.
> >
> > Fix this by spliting invalidate and free in ppgtt_invalidate_spt.
> > Only free spt when in good case.
> >
> > Reported-by: Zheng Wang 
> > Signed-off-by: Zheng Wang 
>
> Has this landed in a tree yet, since it's a possible CVE, might be
> good to merge it somewhere.
>
> Dave.
>

Hi Dave,

This patched hasn't been merged yet. Could you please help with this?

Best Regards,
Zheng Wang

[Intel-gfx] ✗ Fi.CI.IGT: failure for freezer, sched: Rewrite core freezer logic fix (rev3)

[Patchwork]

== Series Details ==

Series: freezer, sched: Rewrite core freezer logic fix (rev3)
URL   : https://patchwork.freedesktop.org/series/110173/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12298_full -> Patchwork_110173v3_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110173v3_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110173v3_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110173v3_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-skl:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/shard-skl7/igt@i915_pm_...@modeset-non-lpsp-stress-no-wait.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_pread@exhaustion:
- {shard-rkl}:NOTRUN -> [INCOMPLETE][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/shard-rkl-5/igt@gem_pr...@exhaustion.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-rkl}:NOTRUN -> [WARN][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_110173v3_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-skl:  NOTRUN -> [DMESG-WARN][4] ([i915#4991])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/shard-skl7/igt@gem_cre...@create-massive.html

  * igt@gem_eio@reset-stress:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#5784])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12298/shard-tglb6/igt@gem_...@reset-stress.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/shard-tglb5/igt@gem_...@reset-stress.html

  * igt@gem_exec_fair@basic-deadline:
- shard-skl:  NOTRUN -> [FAIL][7] ([i915#2846])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/shard-skl7/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12298/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/shard-tglb8/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-none@bcs0:
- shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12298/shard-iclb8/igt@gem_exec_fair@basic-n...@bcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/shard-iclb5/igt@gem_exec_fair@basic-n...@bcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12298/shard-glk5/igt@gem_exec_fair@basic-throt...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/shard-glk1/igt@gem_exec_fair@basic-throt...@rcs0.html
- shard-iclb: NOTRUN -> [FAIL][14] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_lmem_swapping@parallel-random-verify:
- shard-skl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/shard-skl2/igt@gem_lmem_swapp...@parallel-random-verify.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-apl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/shard-apl2/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html
- shard-glk:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/shard-glk3/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@random-engines:
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/shard-iclb1/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-skl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3323])
   

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Audio stuff (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Audio stuff (rev2)
URL   : https://patchwork.freedesktop.org/series/110188/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12302 -> Patchwork_110188v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/index.html

Participating hosts (41 -> 40)
--

  Additional (2): fi-cml-u2 fi-icl-u2 
  Missing(3): fi-ctg-p8600 fi-bdw-samus fi-kbl-8809g 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110188v2:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}:   [WARN][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12302/bat-rpls-2/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/bat-rpls-2/igt@i915_pm_...@module-reload.html

  
Known issues


  Here are the changes found in Patchwork_110188v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][3] ([i915#1208]) +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
- fi-cml-u2:  NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/fi-cml-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-cml-u2:  NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/fi-cml-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2:  NOTRUN -> [SKIP][8] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-cml-u2:  NOTRUN -> [SKIP][10] ([i915#4213])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/fi-cml-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
- fi-icl-u2:  NOTRUN -> [SKIP][11] ([i915#4103])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2:  NOTRUN -> [SKIP][12] ([fdo#109285])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/fi-cml-u2/igt@kms_force_connector_ba...@force-load-detect.html
- fi-icl-u2:  NOTRUN -> [SKIP][13] ([fdo#109285])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][14] ([i915#3555])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html
- fi-cml-u2:  NOTRUN -> [SKIP][15] ([i915#3555])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/fi-cml-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][16] ([fdo#109295] / [i915#3301])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/fi-icl-u2/igt@prime_v...@basic-userptr.html
- fi-cml-u2:  NOTRUN -> [SKIP][17] ([fdo#109295] / [i915#3301])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/fi-cml-u2/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@gem_huc_copy@huc-copy:
- {bat-dg2-11}:   [FAIL][18] ([i915#7029]) -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12302/bat-dg2-11/igt@gem_huc_c...@huc-copy.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v2/bat-dg2-11/igt@gem_huc_c...@huc-copy.html

  * 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Audio stuff (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Audio stuff (rev2)
URL   : https://patchwork.freedesktop.org/series/110188/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+drivers/gpu/drm/i915/display/intel_display_types.h:1936:24: warning: trying to 
copy expression type 31
+drivers/gpu/drm/i915/display/intel_display_types.h:1936:24: 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Audio stuff (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Audio stuff (rev2)
URL   : https://patchwork.freedesktop.org/series/110188/
State : warning

== Summary ==

Error: dim checkpatch failed
d5e981d3cb31 drm/i915/audio: s/dev_priv/i915/
-:1033: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written 
"i915->display.audio.lpe.platdev"
#1033: FILE: drivers/gpu/drm/i915/display/intel_audio.c:1405:
+   if (i915->display.audio.lpe.platdev != NULL)

total: 0 errors, 0 warnings, 1 checks, 980 lines checked
c41db3f96f70 drm/i915/audio: Nuke leftover ROUNDING_FACTOR
93827d906e6a drm/i915/audio: Remove CL/BLC audio stuff
aaa8398a5432 drm/i915/audio: Extract struct ilk_audio_regs
d31d04e641ca drm/i915/audio: Use REG_BIT() & co.
-:159: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#159: FILE: drivers/gpu/drm/i915/display/intel_audio_regs.h:64:
+#define   AUD_CONFIG_N(n)  
(REG_FIELD_PREP(AUD_CONFIG_UPPER_N_MASK, (n) >> 12) | \

-:159: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects?
#159: FILE: drivers/gpu/drm/i915/display/intel_audio_regs.h:64:
+#define   AUD_CONFIG_N(n)  
(REG_FIELD_PREP(AUD_CONFIG_UPPER_N_MASK, (n) >> 12) | \
+
REG_FIELD_PREP(AUD_CONFIG_LOWER_N_MASK, (n) & 0xfff))

-:160: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#160: FILE: drivers/gpu/drm/i915/display/intel_audio_regs.h:65:
+
REG_FIELD_PREP(AUD_CONFIG_LOWER_N_MASK, (n) & 0xfff))

total: 0 errors, 2 warnings, 1 checks, 171 lines checked
4b5a7ea8120e drm/i915/audio: Unify register bit naming
cb9af05dabb5 drm/i915/audio: Protect singleton register with a lock
3baeed6a6bf0 drm/i915/audio: Nuke intel_eld_uptodate()
dee866fe1f99 drm/i915/audio: Read ELD buffer size from hardware
b8dc3881149e drm/i915/audio: Make sure we write the whole ELD buffer
957ecb1cee1f drm/i915/audio: Use u32* for ELD
e5c74315831c drm/i915/audio: Use intel_de_rmw() for most audio registers
672dae67c4e6 drm/i915/audio: Split "ELD valid" vs. audio PD on hsw+
62ae6a195cbd drm/i915/audio: Do the vblank waits
23299d1dbf96 drm/i915/sdvo: Extract intel_sdvo_has_audio()

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: prepare for uC loading on MTL (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: prepare for uC loading on MTL (rev5)
URL   : https://patchwork.freedesktop.org/series/108925/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12302 -> Patchwork_108925v5


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108925v5/index.html

Participating hosts (41 -> 40)
--

  Additional (1): fi-icl-u2 
  Missing(2): fi-ctg-p8600 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_108925v5:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@migrate:
- {bat-adlp-6}:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12302/bat-adlp-6/igt@i915_selftest@l...@migrate.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108925v5/bat-adlp-6/igt@i915_selftest@l...@migrate.html

  
Known issues


  Here are the changes found in Patchwork_108925v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108925v5/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_tiled_blits@basic:
- fi-pnv-d510:[PASS][4] -> [SKIP][5] ([fdo#109271]) +2 similar 
issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12302/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108925v5/fi-pnv-d510/igt@gem_tiled_bl...@basic.html

  * igt@i915_selftest@live@hangcheck:
- fi-adl-ddr5:[PASS][6] -> [DMESG-WARN][7] ([i915#5591])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12302/fi-adl-ddr5/igt@i915_selftest@l...@hangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108925v5/fi-adl-ddr5/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][8] ([fdo#111827]) +7 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108925v5/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-icl-u2:  NOTRUN -> [SKIP][9] ([i915#4103])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108925v5/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@runner@aborted:
- fi-icl-u2:  NOTRUN -> [FAIL][10] ([i915#4312])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108925v5/fi-icl-u2/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_huc_copy@huc-copy:
- {bat-dg2-11}:   [FAIL][11] ([i915#7029]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12302/bat-dg2-11/igt@gem_huc_c...@huc-copy.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108925v5/bat-dg2-11/igt@gem_huc_c...@huc-copy.html

  * igt@i915_pm_rpm@module-reload:
- fi-skl-6600u:   [FAIL][13] -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12302/fi-skl-6600u/igt@i915_pm_...@module-reload.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108925v5/fi-skl-6600u/igt@i915_pm_...@module-reload.html

  * 
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka:   [FAIL][15] ([i915#6298]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12302/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108925v5/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u:   [DMESG-WARN][17] ([i915#62]) -> [PASS][18] +15 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12302/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108925v5/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4983]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: prepare for uC loading on MTL (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: prepare for uC loading on MTL (rev5)
URL   : https://patchwork.freedesktop.org/series/108925/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: prepare for uC loading on MTL (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: prepare for uC loading on MTL (rev5)
URL   : https://patchwork.freedesktop.org/series/108925/
State : warning

== Summary ==

Error: dim checkpatch failed
0ab6f91e91d1 drm/i915/huc: only load HuC on GTs that have VCS engines
-:44: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#44: FILE: drivers/gpu/drm/i915/gt/uc/intel_huc.c:227:
+   GEM_BUG_ON(!gt_is_root(gt) && !gt->info.engine_mask);

total: 0 errors, 1 warnings, 0 checks, 59 lines checked
bd5154948513 drm/i915/uc: fetch uc firmwares for each GT
c44a395804cc drm/i915/uc: use different ggtt pin offsets for uc loads
-:66: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#66: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:704:
+   GEM_BUG_ON(gt->type == GT_MEDIA && gt->info.id > 1);

-:73: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#73: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:711:
+   GEM_BUG_ON(offset + uc_fw->obj->base.size > node->size);

-:74: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#74: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:712:
+   GEM_BUG_ON(uc_fw->obj->base.size > INTEL_UC_RSVD_GGTT_PER_FW);

total: 0 errors, 3 warnings, 0 checks, 82 lines checked
e84d57a6dbf1 drm/i915/guc: Add GuC deprivilege feature to MTL
a52cad6a8c62 drm/i915/mtl: Handle wopcm per-GT and limit calculations.
-:113: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#113: 
rename from drivers/gpu/drm/i915/intel_wopcm.c

-:278: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#278: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:567:
+   GEM_BUG_ON(!gt->wopcm.size);

total: 0 errors, 2 warnings, 0 checks, 240 lines checked
3f38b7223791 drm/i915/guc: define media GT GuC send regs
1aa6d0faac94 drm/i915/guc: handle interrupts from media GuC

Re: [Intel-gfx] [PATCH v3] drm/i915/gvt: fix double free bug in split_2MB_gtt_entry

[Dave Airlie]

On Fri, 7 Oct 2022 at 11:38, Zheng Wang  wrote:
>
> If intel_gvt_dma_map_guest_page failed, it will call
> ppgtt_invalidate_spt, which will finally free the spt.
> But the caller does not notice that, it will free spt again in error path.
>
> Fix this by spliting invalidate and free in ppgtt_invalidate_spt.
> Only free spt when in good case.
>
> Reported-by: Zheng Wang 
> Signed-off-by: Zheng Wang 

Has this landed in a tree yet, since it's a possible CVE, might be
good to merge it somewhere.

Dave.

> ---
> v3:
> - correct spelling mistake and remove unused variable suggested by Greg
>
> v2: https://lore.kernel.org/all/20221006165845.1735393-1-zyytlz...@163.com/
>
> v1: https://lore.kernel.org/all/20220928033340.1063949-1-zyytlz...@163.com/
> ---
>  drivers/gpu/drm/i915/gvt/gtt.c | 32 +---
>  1 file changed, 21 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index ce0eb03709c3..865d33762e45 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -959,6 +959,7 @@ static inline int ppgtt_put_spt(struct 
> intel_vgpu_ppgtt_spt *spt)
> return atomic_dec_return(>refcount);
>  }
>
> +static int ppgtt_invalidate_and_free_spt(struct intel_vgpu_ppgtt_spt *spt);
>  static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
>
>  static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
> @@ -995,7 +996,7 @@ static int ppgtt_invalidate_spt_by_shadow_entry(struct 
> intel_vgpu *vgpu,
> ops->get_pfn(e));
> return -ENXIO;
> }
> -   return ppgtt_invalidate_spt(s);
> +   return ppgtt_invalidate_and_free_spt(s);
>  }
>
>  static inline void ppgtt_invalidate_pte(struct intel_vgpu_ppgtt_spt *spt,
> @@ -1016,18 +1017,30 @@ static inline void ppgtt_invalidate_pte(struct 
> intel_vgpu_ppgtt_spt *spt,
> intel_gvt_dma_unmap_guest_page(vgpu, pfn << PAGE_SHIFT);
>  }
>
> -static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
> +static int ppgtt_invalidate_and_free_spt(struct intel_vgpu_ppgtt_spt *spt)
>  {
> -   struct intel_vgpu *vgpu = spt->vgpu;
> -   struct intel_gvt_gtt_entry e;
> -   unsigned long index;
> int ret;
>
> trace_spt_change(spt->vgpu->id, "die", spt,
> -   spt->guest_page.gfn, spt->shadow_page.type);
> -
> +   spt->guest_page.gfn, spt->shadow_page.type);
> if (ppgtt_put_spt(spt) > 0)
> return 0;
> +   ret = ppgtt_invalidate_spt(spt);
> +   if (!ret) {
> +   trace_spt_change(spt->vgpu->id, "release", spt,
> +spt->guest_page.gfn, spt->shadow_page.type);
> +   ppgtt_free_spt(spt);
> +   }
> +
> +   return ret;
> +}
> +
> +static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
> +{
> +   struct intel_vgpu *vgpu = spt->vgpu;
> +   struct intel_gvt_gtt_entry e;
> +   unsigned long index;
> +   int ret;
>
> for_each_present_shadow_entry(spt, , index) {
> switch (e.type) {
> @@ -1059,9 +1072,6 @@ static int ppgtt_invalidate_spt(struct 
> intel_vgpu_ppgtt_spt *spt)
> }
> }
>
> -   trace_spt_change(spt->vgpu->id, "release", spt,
> -spt->guest_page.gfn, spt->shadow_page.type);
> -   ppgtt_free_spt(spt);
> return 0;
>  fail:
> gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
> @@ -1393,7 +1403,7 @@ static int ppgtt_handle_guest_entry_removal(struct 
> intel_vgpu_ppgtt_spt *spt,
> ret = -ENXIO;
> goto fail;
> }
> -   ret = ppgtt_invalidate_spt(s);
> +   ret = ppgtt_invalidate_and_free_spt(s);
> if (ret)
> goto fail;
> } else {
> --
> 2.25.1
>

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: More gamma work

[Patchwork]

== Series Details ==

Series: drm/i915: More gamma work
URL   : https://patchwork.freedesktop.org/series/110168/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12296_full -> Patchwork_110168v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110168v1_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_suspend@basic-s3-without-i915:
- {shard-rkl}:NOTRUN -> [INCOMPLETE][1] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-rkl-5/igt@i915_susp...@basic-s3-without-i915.html

  * igt@sysfs_timeslice_duration@idempotent@vcs0:
- {shard-dg1}:NOTRUN -> [FAIL][2] +9 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-dg1-18/igt@sysfs_timeslice_duration@idempot...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_110168v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_mm@all:
- shard-iclb: NOTRUN -> [SKIP][3] ([i915#6433])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@drm...@all.html

  * igt@feature_discovery@display-3x:
- shard-iclb: NOTRUN -> [SKIP][4] ([i915#1839])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@feature_discov...@display-3x.html

  * igt@gem_ccs@suspend-resume:
- shard-tglb: NOTRUN -> [SKIP][5] ([i915#5325])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@gem_...@suspend-resume.html

  * igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#6268])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb6/igt@gem_ctx_e...@basic-nohangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb2/igt@gem_ctx_e...@basic-nohangcheck.html

  * igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2410])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb6/igt@gem_ctx_persiste...@many-contexts.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar 
issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb6/igt@gem_exec_fair@basic-p...@bcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb2/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][13] ([fdo#109283])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@gem_exec_par...@no-vebox.html

  * igt@gem_exec_whisper@basic-fds-priority:
- shard-skl:  [PASS][14] -> [DMESG-WARN][15] ([i915#1982])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl1/igt@gem_exec_whis...@basic-fds-priority.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl6/igt@gem_exec_whis...@basic-fds-priority.html

  * igt@gem_pxp@create-regular-context-1:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#4270])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@gem_...@create-regular-context-1.html

  * igt@gem_userptr_blits@input-checking:
- shard-skl:  NOTRUN -> [DMESG-WARN][17] ([i915#4991])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl10/igt@gem_userptr_bl...@input-checking.html

  * igt@gen7_exec_parse@load-register-reg:
- shard-iclb: NOTRUN -> [SKIP][18] ([fdo#109289])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@gen7_exec_pa...@load-register-reg.html

  * igt@gen7_exec_parse@oacontrol-tracking:
- shard-apl:  NOTRUN -> [SKIP][19] ([fdo#109271]) +36 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl8/igt@gen7_exec_pa...@oacontrol-tracking.html

  * igt@gen9_exec_parse@allowed-single:
- shard-apl:  [PASS][20] -> [DMESG-WARN][21] ([i915#5566] / 
[i915#716])
   [20]: 

[Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL

[Anusha Srivatsa]

As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.

v2: Revert to using bxt_get_cdclk()

BSpec: 65243

Cc: Clint Taylor 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6a775367f02a..28253cb310ca 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1345,6 +1345,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = 
{
{}
 };
 
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+   { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, 
.waveform = 0xad5a },
+   { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, 
.waveform = 0xb6b6 },
+   { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, 
.waveform = 0x },
+   { .refclk = 38400, .cdclk = 48, .divider = 2, .ratio = 25, 
.waveform = 0x },
+   { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, 
.waveform = 0x },
+   { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, 
.waveform = 0x },
+   {}
+};
+
 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 {
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3160,6 +3170,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
 }
 
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+   .get_cdclk = bxt_get_cdclk,
+   .set_cdclk = bxt_set_cdclk,
+   .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+   .calc_voltage_level = tgl_calc_voltage_level,
+};
+
 static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3295,7 +3312,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = 
{
  */
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
-   if (IS_DG2(dev_priv)) {
+   if (IS_METEORLAKE(dev_priv)) {
+   dev_priv->display.funcs.cdclk = _cdclk_funcs;
+   dev_priv->display.cdclk.table = mtl_cdclk_table;
+   } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
-- 
2.25.1

[Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk

[Anusha Srivatsa]

From: Ville Syrjälä 

For MTL, changing cdclk from between certain frequencies has
both squash and crawl. Use the current cdclk config and
the new(desired) cdclk config to construtc a mid cdclk config.
Set the cdclk twice:
- Current cdclk -> mid cdclk
- mid cdclk -> desired cdclk

v2: Add check in intel_modeset_calc_cdclk() to avoid cdclk
change via modeset for platforms that support squash_crawl sequences(Ville)

v3: Add checks for:
- scenario where only slow clock is used and
cdclk is actually 0 (bringing up display).
- PLLs are on before looking up the waveform.
- Squash and crawl capability checks.(Ville)

v4: Rebase
- Move checks to be more consistent (Ville)
- Add comments (Bala)

Cc: Balasubramani Vivekanandan 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 157 +
 1 file changed, 129 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index eada931cb1c8..6a775367f02a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1716,37 +1716,74 @@ static void dg2_cdclk_squash_program(struct 
drm_i915_private *i915,
intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
 }
 
-static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *cdclk_config,
- enum pipe pipe)
+static int cdclk_squash_divider(u16 waveform)
+{
+   return hweight16(waveform ?: 0x);
+}
+
+static bool cdclk_crawl_and_squash(struct drm_i915_private *i915,
+  const struct intel_cdclk_config 
*old_cdclk_config,
+  const struct intel_cdclk_config 
*new_cdclk_config,
+  struct intel_cdclk_config *mid_cdclk_config)
+{
+   u16 old_waveform, new_waveform, mid_waveform;
+   int size = 16;
+   int div = 2;
+
+   /* Return if both Squash and Crawl are not present */
+   if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
+   return false;
+
+   /* Return if Squash only or Crawl only is the desired action */
+   if (old_cdclk_config->vco <= 0 || new_cdclk_config->vco <= 0 ||
+   old_cdclk_config->vco == new_cdclk_config->vco ||
+   old_waveform == new_waveform)
+   return false;
+
+   old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
+   new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
+
+   *mid_cdclk_config = *new_cdclk_config;
+
+   /* Populate the mid_cdclk_config accordingly.
+* - If moving to a higher cdclk, the desired action is squashing.
+* The mid cdclk config should have the new (squash) waveform.
+* - If moving to a lower cdclk, the desired action is crawling.
+* The mid cdclk config should have the new vco.
+*/
+
+   if (cdclk_squash_divider(new_waveform) > 
cdclk_squash_divider(old_waveform)) {
+   mid_cdclk_config->vco = old_cdclk_config->vco;
+   mid_waveform = new_waveform;
+   } else {
+   mid_cdclk_config->vco = new_cdclk_config->vco;
+   mid_waveform = old_waveform;
+   }
+
+   mid_cdclk_config->cdclk = 
DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
+   mid_cdclk_config->vco, size 
* div);
+
+   /* make sure the mid clock came out sane */
+
+   drm_WARN_ON(>drm, mid_cdclk_config->cdclk <
+   min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
+   drm_WARN_ON(>drm, mid_cdclk_config->cdclk >
+   i915->display.cdclk.max_cdclk_freq);
+   drm_WARN_ON(>drm, cdclk_squash_waveform(i915, 
mid_cdclk_config->cdclk) !=
+   mid_waveform);
+
+   return true;
+}
+
+static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
+  const struct intel_cdclk_config *cdclk_config,
+  enum pipe pipe)
 {
int cdclk = cdclk_config->cdclk;
int vco = cdclk_config->vco;
u32 val;
u16 waveform;
int clock;
-   int ret;
-
-   /* Inform power controller of upcoming frequency change. */
-   if (DISPLAY_VER(dev_priv) >= 11)
-   ret = skl_pcode_request(_priv->uncore, 
SKL_PCODE_CDCLK_CONTROL,
-   SKL_CDCLK_PREPARE_FOR_CHANGE,
-   SKL_CDCLK_READY_FOR_CHANGE,
-   SKL_CDCLK_READY_FOR_CHANGE, 3);
-   else
-   /*
-* BSpec requires us to wait up to 150usec, but that leads to
-* timeouts; the 2ms used here is based on experiment.
-*/
-   ret = snb_pcode_write_timeout(_priv->uncore,
-  

[Intel-gfx] ✗ Fi.CI.BAT: failure for i915: CAGF and RC6 changes for MTL (rev11)

[Patchwork]

== Series Details ==

Series: i915: CAGF and RC6 changes for MTL (rev11)
URL   : https://patchwork.freedesktop.org/series/108156/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12288 -> Patchwork_108156v11


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_108156v11 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_108156v11, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.html

Participating hosts (41 -> 41)
--

  Additional (2): fi-kbl-soraka bat-atsm-1 
  Missing(2): fi-ctg-p8600 fi-icl-u2 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_108156v11:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gtt:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@i915_selftest@l...@gtt.html

  
Known issues


  Here are the changes found in Patchwork_108156v11 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271]) +9 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html

  * igt@gem_exec_parallel@engines@contexts:
- fi-bsw-nick:[PASS][3] -> [INCOMPLETE][4] ([i915#7311])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-bsw-nick/igt@gem_exec_parallel@engi...@contexts.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-bsw-nick/igt@gem_exec_parallel@engi...@contexts.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][7] ([i915#5334])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [PASS][8] -> [INCOMPLETE][9] ([i915#4983])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][10] ([i915#1886])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hugepages:
- fi-cfl-8109u:   [PASS][11] -> [DMESG-FAIL][12] ([i915#7311])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-cfl-8109u/igt@i915_selftest@l...@hugepages.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-cfl-8109u/igt@i915_selftest@l...@hugepages.html
- fi-skl-guc: [PASS][13] -> [DMESG-FAIL][14] ([i915#7311])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-skl-guc/igt@i915_selftest@l...@hugepages.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-skl-guc/igt@i915_selftest@l...@hugepages.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   NOTRUN -> [INCOMPLETE][15] ([i915#4817])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-soraka:  NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@runner@aborted:
- fi-cfl-8109u:   NOTRUN -> [FAIL][18] ([i915#4312])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-cfl-8109u/igt@run...@aborted.html
- fi-skl-guc: NOTRUN -> [FAIL][19] ([i915#4312])
   [19]: 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Fix Guc-Err-Capture sizing warning

[Teres Alexis, Alan Previn]

AS per the other rev, below regressions are, once again, unrelated to this 
series because this series patch modified code that only get executed if GuC 
ADS is being initialized whereas the regressions are on platforms that do not 
have GuC enabled (which i further verified in the full dmesg).

On Wed, 2022-10-26 at 18:52 +, Patchwork wrote:
Patch Details
Series: Fix Guc-Err-Capture sizing warning
URL:https://patchwork.freedesktop.org/series/110155/
State:  failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110155v1/index.html
CI Bug Log - changes from CI_DRM_12295_full -> Patchwork_110155v1_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_110155v1_full absolutely need to 
be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_110155v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Participating hosts (9 -> 11)

Additional (2): shard-rkl shard-dg1

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_110155v1_full:

IGT changes
Possible regressions

  *   igt@i915_selftest@live@execlists:

 *   shard-skl: NOTRUN -> 
INCOMPLETE
  *   igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:

 *   shard-iclb: 
PASS
 -> 
FAIL
  *   igt@kms_sequence@queue-idle@edp-1-pipe-a:

 *   shard-skl: NOTRUN -> 
FAIL
  *   igt@syncobj_timeline@wait-all-for-submit-snapshot:

 *   shard-skl: 
PASS
 -> 
FAIL

Warnings

  *   igt@runner@aborted:
 *   shard-skl: 
(FAIL,
 
FAIL,
 
FAIL)
 (i915#3002 / 
i915#4312 / 
i915#6949) -> 
(FAIL,
 
FAIL,
 
FAIL,
 
FAIL,
 
FAIL,
 
FAIL,
 
FAIL)
 (i915#3002 / 
i915#4312)

Re: [Intel-gfx] [PATCH v6 22/23] drm/vc4: vec: Add support for more analog TV standards

[Mateusz Kwiatkowski]

Hi Maxime,

I've seen that you've incorporated my PAL60 patch. Thanks!

I still yet need to test your v6 changes, but looking at this code with just my
mental static analysis, it seems to me that the vc4_vec_encoder_atomic_check()
should have the tv_mode validation. I should've added it to the PAL60 patch,
but it somehow slipped my mind then.

Anyway, I mentioned it previously here:
https://lore.kernel.org/dri-devel/0f2beec2-ae8e-5579-f0b6-a73d9dae1...@gmail.com/

It would look something like this, inside vc4_vec_encoder_atomic_check():

+   const struct vc4_vec_tv_mode *tv_mode =
+   vc4_vec_tv_mode_lookup(conn_state->tv.mode);
+
+   if (!tv_mode)
+   return -EINVAL;

Without this, it's possible to set e.g. 480i mode and SECAM, which will fail -
but with the current version it will only fail in vc4_vec_encoder_enable(),
which cannot return an error, and in my experience that causes a rather lengthy
lockup.

But, like I said, I still need to actually test that with this version.

Anyway, I was also thinking about adding support for the more "exotic"
non-standard modes. NTSC-50 is, unfortunately, impossible with VEC, but
PAL-N-60 and PAL-M-50 should work. The necessary vc4_vec_tv_modes entries would
look something like:

@@ -325,12 +325,28 @@ static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
.config0 = VEC_CONFIG0_PAL_M_STD,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
+   {
+   /* PAL-M-50 */
+   .mode = DRM_MODE_TV_MODE_PAL,
+   .expected_htotal = 864,
+   .config0 = VEC_CONFIG0_PAL_BDGHI_STD,
+   .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
+   .custom_freq = 0x21e6efe3,
+   },
{
.mode = DRM_MODE_TV_MODE_PAL_N,
.expected_htotal = 864,
.config0 = VEC_CONFIG0_PAL_N_STD,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
+   {
+   /* PAL-N-60 */
+   .mode = DRM_MODE_TV_MODE_PAL_N,
+   .expected_htotal = 858,
+   .config0 = VEC_CONFIG0_PAL_M_STD,
+   .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
+   .custom_freq = 0x21f69446,
+   },
{
.mode = DRM_MODE_TV_MODE_SECAM,
.expected_htotal = 864,

I'm not sure if we actually want to add that. The two arguments for doing so
I can think of is 1. it should work, so "why not", 2. it means that more modes
will result in _some_ kind of a valid signal, rather than erroring out, which
is always a plus in my book. I can also think of a hypothetical use case, like
someone in South America with an old PAL-N-only set that would nevertheless
still sync at 60 Hz (perhaps with the help of messing with vertical hold knob),
who would like to play retro games at 60 Hz in color.

But on the other hand, I admit that this scenario is likely a stretch and the
number of people who would actually use it is probably close to the proverbial
two ;) So it's your call, I'm just leaving those settings here just in case.

I'll get back in a couple of days when I do some testing of this v6 patchset.

Best regards,
Mateusz Kwiatkowski

W dniu 26.10.2022 o 17:33, max...@cerno.tech pisze:
> From: Mateusz Kwiatkowski 
>
> Add support for the following composite output modes (all of them are
> somewhat more obscure than the previously defined ones):
>
> - NTSC_443 - NTSC-style signal with the chroma subcarrier shifted to
>   4.43361875 MHz (the PAL subcarrier frequency). Never used for
>   broadcasting, but sometimes used as a hack to play NTSC content in PAL
>   regions (e.g. on VCRs).
> - PAL_N - PAL with alternative chroma subcarrier frequency,
>   3.58205625 MHz. Used as a broadcast standard in Argentina, Paraguay
>   and Uruguay to fit 576i50 with colour in 6 MHz channel raster.
> - PAL60 - 480i60 signal with PAL-style color at normal European PAL
>   frequency. Another non-standard, non-broadcast mode, used in similar
>   contexts as NTSC_443. Some displays support one but not the other.
> - SECAM - French frequency-modulated analog color standard; also have
>   been broadcast in Eastern Europe and various parts of Africa and Asia.
>   Uses the same 576i50 timings as PAL.
>
> Also added some comments explaining color subcarrier frequency
> registers.
>
> Acked-by: Noralf Trønnes 
> Signed-off-by: Mateusz Kwiatkowski 
> Signed-off-by: Maxime Ripard 
>
> ---
> Changes in v6:
> - Support PAL60 again
> ---
>  drivers/gpu/drm/vc4/vc4_vec.c | 111 
> --
>  1 file changed, 107 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c
> index 1dda451c8def..d82aef168075 100644
> --- a/drivers/gpu/drm/vc4/vc4_vec.c
> +++ b/drivers/gpu/drm/vc4/vc4_vec.c
> @@ -46,6 +46,7 @@
>  #define VEC_CONFIG0_YDEL(x)  ((x) << 26)
>  #define 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: stop abusing swiotlb_max_segment (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915: stop abusing swiotlb_max_segment (rev7)
URL   : https://patchwork.freedesktop.org/series/109946/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12296_full -> Patchwork_109946v7_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_109946v7_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109946v7_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109946v7_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@perf:
- shard-skl:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v7/shard-skl9/igt@i915_selftest@l...@perf.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][2] -> [FAIL][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-iclb1/igt@kms_frontbuffer_track...@psr-1p-primscrn-cur-indfb-draw-render.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v7/shard-iclb1/igt@kms_frontbuffer_track...@psr-1p-primscrn-cur-indfb-draw-render.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@sysfs_timeslice_duration@idempotent@vcs0:
- {shard-dg1}:NOTRUN -> [FAIL][4] +9 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v7/shard-dg1-15/igt@sysfs_timeslice_duration@idempot...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_109946v7_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ccs@suspend-resume:
- shard-tglb: NOTRUN -> [SKIP][5] ([i915#5325])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v7/shard-tglb7/igt@gem_...@suspend-resume.html

  * igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#6268])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb6/igt@gem_ctx_e...@basic-nohangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v7/shard-tglb6/igt@gem_ctx_e...@basic-nohangcheck.html

  * igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2410])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb6/igt@gem_ctx_persiste...@many-contexts.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v7/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v7/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb6/igt@gem_exec_fair@basic-throt...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v7/shard-tglb1/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][14] -> [SKIP][15] ([i915#2190])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb1/igt@gem_huc_c...@huc-copy.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v7/shard-tglb6/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random-ccs:
- shard-skl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v7/shard-skl7/igt@gem_lmem_swapp...@verify-random-ccs.html

  * igt@gem_softpin@evict-single-offset:
- shard-tglb: [PASS][17] -> [FAIL][18] ([i915#4171])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb6/igt@gem_soft...@evict-single-offset.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v7/shard-tglb1/igt@gem_soft...@evict-single-offset.html

  * igt@gem_userptr_blits@input-checking:
- shard-skl:  NOTRUN -> [DMESG-WARN][19] ([i915#4991])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v7/shard-skl4/igt@gem_userptr_bl...@input-checking.html

  * igt@gen7_exec_parse@oacontrol-tracking:
- shard-apl:  NOTRUN -> [SKIP][20] 

[Intel-gfx] [PATCH v6 10/16] drm/i915/perf: Store a pointer to oa_format in oa_buffer

[Umesh Nerlige Ramappa]

DG2 introduces OA reports with 64 bit report header fields. Perf OA
would need more information about the OA format in order to process such
reports. Store all OA format info in oa_buffer instead of just the size
and format-id.

v2: Drop format_size variable (Ashutosh)

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Lionel Landwerlin 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_perf.c   | 30 +++---
 drivers/gpu/drm/i915/i915_perf_types.h |  3 +--
 2 files changed, 13 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2c8727253f0d..585079ae5f03 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -465,7 +465,7 @@ static u32 gen7_oa_hw_tail_read(struct i915_perf_stream 
*stream)
 static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
 {
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
-   int report_size = stream->oa_buffer.format_size;
+   int report_size = stream->oa_buffer.format->size;
unsigned long flags;
bool pollin;
u32 hw_tail;
@@ -602,7 +602,7 @@ static int append_oa_sample(struct i915_perf_stream *stream,
size_t *offset,
const u8 *report)
 {
-   int report_size = stream->oa_buffer.format_size;
+   int report_size = stream->oa_buffer.format->size;
struct drm_i915_perf_record_header header;
 
header.type = DRM_I915_PERF_RECORD_SAMPLE;
@@ -652,7 +652,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream 
*stream,
  size_t *offset)
 {
struct intel_uncore *uncore = stream->uncore;
-   int report_size = stream->oa_buffer.format_size;
+   int report_size = stream->oa_buffer.format->size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
u32 mask = (OA_BUFFER_SIZE - 1);
@@ -945,7 +945,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream 
*stream,
  size_t *offset)
 {
struct intel_uncore *uncore = stream->uncore;
-   int report_size = stream->oa_buffer.format_size;
+   int report_size = stream->oa_buffer.format->size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
u32 mask = (OA_BUFFER_SIZE - 1);
@@ -2506,7 +2506,7 @@ static int gen12_configure_oar_context(struct 
i915_perf_stream *stream,
 {
int err;
struct intel_context *ce = stream->pinned_ctx;
-   u32 format = stream->oa_buffer.format;
+   u32 format = stream->oa_buffer.format->format;
u32 offset = stream->perf->ctx_oactxctrl_offset;
struct flex regs_context[] = {
{
@@ -2877,7 +2877,7 @@ static void gen7_oa_enable(struct i915_perf_stream 
*stream)
u32 ctx_id = stream->specific_ctx_id;
bool periodic = stream->periodic;
u32 period_exponent = stream->period_exponent;
-   u32 report_format = stream->oa_buffer.format;
+   u32 report_format = stream->oa_buffer.format->format;
 
/*
 * Reset buf pointers so we don't forward reports from before now.
@@ -2903,7 +2903,7 @@ static void gen7_oa_enable(struct i915_perf_stream 
*stream)
 static void gen8_oa_enable(struct i915_perf_stream *stream)
 {
struct intel_uncore *uncore = stream->uncore;
-   u32 report_format = stream->oa_buffer.format;
+   u32 report_format = stream->oa_buffer.format->format;
 
/*
 * Reset buf pointers so we don't forward reports from before now.
@@ -2929,7 +2929,7 @@ static void gen8_oa_enable(struct i915_perf_stream 
*stream)
 static void gen12_oa_enable(struct i915_perf_stream *stream)
 {
struct intel_uncore *uncore = stream->uncore;
-   u32 report_format = stream->oa_buffer.format;
+   u32 report_format = stream->oa_buffer.format->format;
 
/*
 * If we don't want OA reports from the OA buffer, then we don't even
@@ -3110,7 +3110,6 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
struct drm_i915_private *i915 = stream->perf->i915;
struct i915_perf *perf = stream->perf;
struct intel_gt *gt;
-   int format_size;
int ret;
 
if (!props->engine) {
@@ -3166,20 +3165,15 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 
stream->sample_size = sizeof(struct drm_i915_perf_record_header);
 
-   format_size = perf->oa_formats[props->oa_format].size;
+   stream->oa_buffer.format = >oa_formats[props->oa_format];
+   if (drm_WARN_ON(>drm, stream->oa_buffer.format->size == 0))
+   return -EINVAL;
 
stream->sample_flags = props->sample_flags;
-   stream->sample_size += format_size;
-
-   stream->oa_buffer.format_size = format_size;
-   if (drm_WARN_ON(>drm, 

[Intel-gfx] [PATCH v6 04/16] drm/i915/perf: Determine gen12 oa ctx offset at runtime

[Umesh Nerlige Ramappa]

Some SKUs of same gen12 platform may have different oactxctrl
offsets. For gen12, determine oactxctrl offsets at runtime.

v2: (Lionel)
- Move MI definitions to intel_gpu_commands.h
- Ensure __find_reg_in_lri does read past context image size

v3: (Ashutosh)
- Drop unnecessary use of double underscores
- fix find_reg_in_lri
- Return error if oa context offset is U32_MAX
- Error out if oa_ctx_ctrl_offset does not find offset

v4: (Ashutosh)
- Warn on odd MI LRI_LEN
- Remove unnecessary check for valid_oactxctrl_offset
- Drop valid_oactxctrl_offset macro

v5: Drop unrelated comment

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h |   4 +
 drivers/gpu/drm/i915/i915_perf.c | 146 ---
 drivers/gpu/drm/i915/i915_perf_oa_regs.h |   2 +-
 3 files changed, 127 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h 
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index d4e9702d3c8e..f50ea92910d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -187,6 +187,10 @@
 #define   MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
 #define   MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/
 
+#define MI_OPCODE(x)   (((x) >> 23) & 0x3f)
+#define IS_MI_LRI_CMD(x)   (MI_OPCODE(x) == MI_OPCODE(MI_INSTR(0x22, 0)))
+#define MI_LRI_LEN(x)  (((x) & 0xff) + 1)
+
 /*
  * 3D instructions used by the kernel
  */
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e68666b44a72..b71b5cf21176 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1356,6 +1356,74 @@ static int gen12_get_render_context_id(struct 
i915_perf_stream *stream)
return 0;
 }
 
+static bool oa_find_reg_in_lri(u32 *state, u32 reg, u32 *offset, u32 end)
+{
+   u32 idx = *offset;
+   u32 len = min(MI_LRI_LEN(state[idx]) + idx, end);
+   bool found = false;
+
+   idx++;
+   for (; idx < len; idx += 2) {
+   if (state[idx] == reg) {
+   found = true;
+   break;
+   }
+   }
+
+   *offset = idx;
+   return found;
+}
+
+static u32 oa_context_image_offset(struct intel_context *ce, u32 reg)
+{
+   u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
+   u32 *state = ce->lrc_reg_state;
+
+   for (offset = 0; offset < len; ) {
+   if (IS_MI_LRI_CMD(state[offset])) {
+   /*
+* We expect reg-value pairs in MI_LRI command, so
+* MI_LRI_LEN() should be even, if not, issue a warning.
+*/
+   drm_WARN_ON(>engine->i915->drm,
+   MI_LRI_LEN(state[offset]) & 0x1);
+
+   if (oa_find_reg_in_lri(state, reg, , len))
+   break;
+   } else {
+   offset++;
+   }
+   }
+
+   return offset < len ? offset : U32_MAX;
+}
+
+static int set_oa_ctx_ctrl_offset(struct intel_context *ce)
+{
+   i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);
+   struct i915_perf *perf = >engine->i915->perf;
+   u32 offset = perf->ctx_oactxctrl_offset;
+
+   /* Do this only once. Failure is stored as offset of U32_MAX */
+   if (offset)
+   goto exit;
+
+   offset = oa_context_image_offset(ce, i915_mmio_reg_offset(reg));
+   perf->ctx_oactxctrl_offset = offset;
+
+   drm_dbg(>engine->i915->drm,
+   "%s oa ctx control at 0x%08x dword offset\n",
+   ce->engine->name, offset);
+
+exit:
+   return offset && offset != U32_MAX ? 0 : -ENODEV;
+}
+
+static bool engine_supports_mi_query(struct intel_engine_cs *engine)
+{
+   return engine->class == RENDER_CLASS;
+}
+
 /**
  * oa_get_render_ctx_id - determine and hold ctx hw id
  * @stream: An i915-perf stream opened for OA metrics
@@ -1375,6 +1443,21 @@ static int oa_get_render_ctx_id(struct i915_perf_stream 
*stream)
if (IS_ERR(ce))
return PTR_ERR(ce);
 
+   if (engine_supports_mi_query(stream->engine)) {
+   /*
+* We are enabling perf query here. If we don't find the context
+* offset here, just return an error.
+*/
+   ret = set_oa_ctx_ctrl_offset(ce);
+   if (ret) {
+   intel_context_unpin(ce);
+   drm_err(>perf->i915->drm,
+   "Enabling perf query failed for %s\n",
+   stream->engine->name);
+   return ret;
+   }
+   }
+
switch (GRAPHICS_VER(ce->engine->i915)) {
case 7: {
/*
@@ -2406,10 +2489,11 @@ static int gen12_configure_oar_context(struct 
i915_perf_stream 

[Intel-gfx] [PATCH v6 09/16] drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers

[Umesh Nerlige Ramappa]

User passes uabi engine class and instance to the perf OA interface. Use
gt corresponding to the engine to pin the buffers to the right ggtt.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_perf.c | 21 +++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 9a00398ae25f..2c8727253f0d 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1754,6 +1754,7 @@ static void gen12_init_oa_buffer(struct i915_perf_stream 
*stream)
 static int alloc_oa_buffer(struct i915_perf_stream *stream)
 {
struct drm_i915_private *i915 = stream->perf->i915;
+   struct intel_gt *gt = stream->engine->gt;
struct drm_i915_gem_object *bo;
struct i915_vma *vma;
int ret;
@@ -1773,11 +1774,22 @@ static int alloc_oa_buffer(struct i915_perf_stream 
*stream)
i915_gem_object_set_cache_coherency(bo, I915_CACHE_LLC);
 
/* PreHSW required 512K alignment, HSW requires 16M */
-   vma = i915_gem_object_ggtt_pin(bo, NULL, 0, SZ_16M, 0);
+   vma = i915_vma_instance(bo, >ggtt->vm, NULL);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
goto err_unref;
}
+
+   /*
+* PreHSW required 512K alignment.
+* HSW and onwards, align to requested size of OA buffer.
+*/
+   ret = i915_vma_pin(vma, 0, SZ_16M, PIN_GLOBAL | PIN_HIGH);
+   if (ret) {
+   drm_err(>i915->drm, "Failed to pin OA buffer %d\n", ret);
+   goto err_unref;
+   }
+
stream->oa_buffer.vma = vma;
 
stream->oa_buffer.vaddr =
@@ -1827,6 +1839,7 @@ static u32 *save_restore_register(struct i915_perf_stream 
*stream, u32 *cs,
 static int alloc_noa_wait(struct i915_perf_stream *stream)
 {
struct drm_i915_private *i915 = stream->perf->i915;
+   struct intel_gt *gt = stream->engine->gt;
struct drm_i915_gem_object *bo;
struct i915_vma *vma;
const u64 delay_ticks = 0x -
@@ -1867,12 +1880,16 @@ static int alloc_noa_wait(struct i915_perf_stream 
*stream)
 * multiple OA config BOs will have a jump to this address and it
 * needs to be fixed during the lifetime of the i915/perf stream.
 */
-   vma = i915_gem_object_ggtt_pin_ww(bo, , NULL, 0, 0, PIN_HIGH);
+   vma = i915_vma_instance(bo, >ggtt->vm, NULL);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
goto out_ww;
}
 
+   ret = i915_vma_pin_ww(vma, , 0, 0, PIN_GLOBAL | PIN_HIGH);
+   if (ret)
+   goto out_ww;
+
batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
if (IS_ERR(batch)) {
ret = PTR_ERR(batch);
-- 
2.25.1

[Intel-gfx] [PATCH v6 13/16] drm/i915/perf: Save/restore EU flex counters across reset

[Umesh Nerlige Ramappa]

If a drm client is killed, then hw contexts used by the client are reset
immediately. This reset clears the EU flex counter configuration. If an
OA use case is running in parallel, it would start seeing zeroed eu
counter values following the reset even if the drm client is restarted.
Save/restore the EU flex counter config so that the EU counters can be
monitored continuously across resets.

v2:
- Save/restore eu flex config only for gen12, as for pre-gen12, these
  are saved and restored in the context image.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 34ef4f36e660..a419d60166c8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -392,6 +392,16 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
else
ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), 
false);
 
+   if (GRAPHICS_VER(engine->i915) >= 12) {
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL0, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL1, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL2, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL3, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL4, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL5, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL6, false);
+   }
+
return ret ? -1 : 0;
 }
 
-- 
2.25.1

[Intel-gfx] [PATCH v6 11/16] drm/i915/perf: Add Wa_1508761755:dg2

[Umesh Nerlige Ramappa]

Disable Clock gating in EU when gathering the events so that EU events
are not lost.

v2: Fix checkpatch issues
v3: User MCR helpers to write to MC reg
v4: Indent correctly (checkpatch)

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h |  1 +
 drivers/gpu/drm/i915/i915_perf.c| 24 
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 36d95b79022c..b101e31df61c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1164,6 +1164,7 @@
 #define   GEN12_DISABLE_EARLY_READ REG_BIT(14)
 #define   GEN12_ENABLE_LARGE_GRF_MODE  REG_BIT(12)
 #define   GEN12_PUSH_CONST_DEREF_HOLD_DIS  REG_BIT(8)
+#define   GEN12_DISABLE_DOP_GATING  REG_BIT(0)
 
 #define RT_CTRLMCR_REG(0xe530)
 #define   DIS_NULL_QUERY   REG_BIT(10)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 585079ae5f03..e14d16ac47de 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -204,6 +204,7 @@
 #include "gt/intel_gpu_commands.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_clock_utils.h"
+#include "gt/intel_gt_mcr.h"
 #include "gt/intel_gt_regs.h"
 #include "gt/intel_lrc.h"
 #include "gt/intel_lrc_reg.h"
@@ -2775,6 +2776,18 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
u32 sqcnt1;
int ret;
 
+   /*
+* Wa_1508761755:xehpsdv, dg2
+* EU NOA signals behave incorrectly if EU clock gating is enabled.
+* Disable thread stall DOP gating and EU DOP gating.
+*/
+   if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
+   intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
+
_MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
+   intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
+  
_MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING));
+   }
+
intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,
   /* Disable clk ratio reports, like previous Gens. */
   
_MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
@@ -2853,6 +2866,17 @@ static void gen12_disable_metric_set(struct 
i915_perf_stream *stream)
struct drm_i915_private *i915 = stream->perf->i915;
u32 sqcnt1;
 
+   /*
+* Wa_1508761755:xehpsdv, dg2
+* Enable thread stall DOP gating and EU DOP gating.
+*/
+   if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
+   intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
+
_MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
+   intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
+  
_MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING));
+   }
+
/* Reset all contexts' slices/subslices configurations. */
gen12_configure_all_contexts(stream, NULL, NULL);
 
-- 
2.25.1

[Intel-gfx] [PATCH v6 16/16] drm/i915/perf: Enable OA for DG2

[Umesh Nerlige Ramappa]

OA was disabled for DG2 as support was missing. Enable it back now.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_perf.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2db74b5a54cd..0dd597a7a11f 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4798,12 +4798,6 @@ void i915_perf_init(struct drm_i915_private *i915)
 {
struct i915_perf *perf = >perf;
 
-   /* XXX const struct i915_perf_ops! */
-
-   /* i915_perf is not enabled for DG2 yet */
-   if (IS_DG2(i915))
-   return;
-
perf->oa_formats = oa_formats;
if (IS_HASWELL(i915)) {
perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;
-- 
2.25.1

[Intel-gfx] [PATCH v6 05/16] drm/i915/perf: Enable bytes per clock reporting in OA

[Umesh Nerlige Ramappa]

XEHPSDV and DG2 provide a way to configure bytes per clock vs commands
per clock reporting. Enable bytes per clock setting on enabling OA.

Bspec: 51762
Bspec: 52201

v2:
- Fix commit msg (Ashutosh)
- Fix checkpatch issues

v3:
- s/commands/bytes/ in code comment and commmit msg

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_drv.h  |  3 +++
 drivers/gpu/drm/i915/i915_pci.c  |  1 +
 drivers/gpu/drm/i915/i915_perf.c | 20 
 drivers/gpu/drm/i915/i915_perf_oa_regs.h |  4 
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 5 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d7b8eb9d4117..866edee7d5eb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -898,6 +898,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
 
+#define HAS_OA_BPC_REPORTING(dev_priv) \
+   (INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
+
 /*
  * Set this flag, when platform requires 64K GTT page sizes or larger for
  * device local memory access.
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 19bf5ef6a20d..449aa2421891 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1023,6 +1023,7 @@ static const struct intel_device_info adl_p_info = {
.has_logical_ring_contexts = 1, \
.has_logical_ring_elsq = 1, \
.has_mslice_steering = 1, \
+   .has_oa_bpc_reporting = 1, \
.has_rc6 = 1, \
.has_reset_engine = 1, \
.has_rps = 1, \
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index b71b5cf21176..d11cc949c9be 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2748,10 +2748,12 @@ static int
 gen12_enable_metric_set(struct i915_perf_stream *stream,
struct i915_active *active)
 {
+   struct drm_i915_private *i915 = stream->perf->i915;
struct intel_uncore *uncore = stream->uncore;
struct i915_oa_config *oa_config = stream->oa_config;
bool periodic = stream->periodic;
u32 period_exponent = stream->period_exponent;
+   u32 sqcnt1;
int ret;
 
intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,
@@ -2770,6 +2772,16 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
(period_exponent << 
GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
: 0);
 
+   /*
+* Initialize Super Queue Internal Cnt Register
+* Set PMON Enable in order to collect valid metrics.
+* Enable byets per clock reporting in OA for XEHPSDV onward.
+*/
+   sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
+(HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
+
+   intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, sqcnt1);
+
/*
 * Update all contexts prior writing the mux configurations as we need
 * to make sure all slices/subslices are ON before writing to NOA
@@ -2819,6 +2831,8 @@ static void gen11_disable_metric_set(struct 
i915_perf_stream *stream)
 static void gen12_disable_metric_set(struct i915_perf_stream *stream)
 {
struct intel_uncore *uncore = stream->uncore;
+   struct drm_i915_private *i915 = stream->perf->i915;
+   u32 sqcnt1;
 
/* Reset all contexts' slices/subslices configurations. */
gen12_configure_all_contexts(stream, NULL, NULL);
@@ -2829,6 +2843,12 @@ static void gen12_disable_metric_set(struct 
i915_perf_stream *stream)
 
/* Make sure we disable noa to save power. */
intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
+
+   sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
+(HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
+
+   /* Reset PMON Enable to save power. */
+   intel_uncore_rmw(uncore, GEN12_SQCNT1, sqcnt1, 0);
 }
 
 static void gen7_oa_enable(struct i915_perf_stream *stream)
diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h 
b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
index 0ef3562ff4aa..381d94101610 100644
--- a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
+++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
@@ -134,4 +134,8 @@
 #define GDT_CHICKEN_BITS_MMIO(0x9840)
 #define   GT_NOA_ENABLE0x0080
 
+#define GEN12_SQCNT1   _MMIO(0x8718)
+#define   GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
+#define   GEN12_SQCNT1_OABPC   REG_BIT(29)
+
 #endif /* __INTEL_PERF_OA_REGS__ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index cdf78728dcad..42218c8d85f2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ 

[Intel-gfx] [PATCH v6 12/16] drm/i915/perf: Apply Wa_18013179988

[Umesh Nerlige Ramappa]

OA reports in the OA buffer contain an OA timestamp field that helps
user calculate delta between 2 OA reports. The calculation relies on the
CS timestamp frequency to convert the timestamp value to nanoseconds.
The CS timestamp frequency is a function of the CTC_SHIFT value in
RPM_CONFIG0.

In DG2, OA unit assumes that the CTC_SHIFT is 3, instead of using the
actual value from RPM_CONFIG0. At the user level, this results in an
error in calculating delta between 2 OA reports since the OA timestamp
is not shifted in the same manner as CS timestamp. Also the periodicity
of the reports is different from what the user configured because of
mismatch in the CS and OA frequencies.

The issue also affects MI_REPORT_PERF_COUNT command.

To resolve this, return actual OA timestamp frequency to the user in
i915_getparam_ioctl, so that user can calculate the right OA exponent as
well as interpret the reports correctly.

MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893

v2:
- Use REG_FIELD_GET (Ashutosh)
- Update commit msg

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_getparam.c |  3 +++
 drivers/gpu/drm/i915/i915_perf.c | 30 ++--
 drivers/gpu/drm/i915/i915_perf.h |  2 ++
 include/uapi/drm/i915_drm.h  |  6 ++
 4 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_getparam.c 
b/drivers/gpu/drm/i915/i915_getparam.c
index 342c8ca6414e..3047e80e1163 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -175,6 +175,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_PERF_REVISION:
value = i915_perf_ioctl_version();
break;
+   case I915_PARAM_OA_TIMESTAMP_FREQUENCY:
+   value = i915_perf_oa_timestamp_frequency(i915);
+   break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e14d16ac47de..b73d91b792df 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3109,6 +3109,30 @@ get_sseu_config(struct intel_sseu *out_sseu,
return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu);
 }
 
+/*
+ * OA timestamp frequency = CS timestamp frequency in most platforms. On some
+ * platforms OA unit ignores the CTC_SHIFT and the 2 timestamps differ. In such
+ * cases, return the adjusted CS timestamp frequency to the user.
+ */
+u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
+{
+   /* Wa_18013179988:dg2 */
+   if (IS_DG2(i915)) {
+   intel_wakeref_t wakeref;
+   u32 reg, shift;
+
+   with_intel_runtime_pm(to_gt(i915)->uncore->rpm, wakeref)
+   reg = intel_uncore_read(to_gt(i915)->uncore, 
RPM_CONFIG0);
+
+   shift = 
REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK,
+ reg);
+
+   return to_gt(i915)->clock_frequency << (3 - shift);
+   }
+
+   return to_gt(i915)->clock_frequency;
+}
+
 /**
  * i915_oa_stream_init - validate combined props for OA stream and init
  * @stream: An i915 perf stream
@@ -3830,8 +3854,10 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
 
 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
 {
-   return intel_gt_clock_interval_to_ns(to_gt(perf->i915),
-2ULL << exponent);
+   u64 nom = (2ULL << exponent) * NSEC_PER_SEC;
+   u32 den = i915_perf_oa_timestamp_frequency(perf->i915);
+
+   return div_u64(nom + den - 1, den);
 }
 
 static __always_inline bool
diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
index 1d1329e5af3a..f96e09a4af04 100644
--- a/drivers/gpu/drm/i915/i915_perf.h
+++ b/drivers/gpu/drm/i915/i915_perf.h
@@ -57,4 +57,6 @@ static inline void i915_oa_config_put(struct i915_oa_config 
*oa_config)
kref_put(_config->ref, i915_oa_config_release);
 }
 
+u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915);
+
 #endif /* __I915_PERF_H__ */
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 158b35fb28f3..c346b1923d11 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -765,6 +765,12 @@ typedef struct drm_i915_irq_wait {
 /* Query if the kernel supports the I915_USERPTR_PROBE flag. */
 #define I915_PARAM_HAS_USERPTR_PROBE 56
 
+/*
+ * Frequency of the timestamps in OA reports. This used to be the same as the 
CS
+ * timestamp frequency, but differs on some platforms.
+ */
+#define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57
+
 /* Must be kept compact -- no holes and well documented */
 
 /**
-- 
2.25.1

[Intel-gfx] [PATCH v6 06/16] drm/i915/perf: Simply use stream->ctx

[Umesh Nerlige Ramappa]

Earlier code used exclusive_stream to check for user passed context.
Simplify this by accessing stream->ctx.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_perf.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index d11cc949c9be..75d320b2c1f8 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -776,7 +776,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream 
*stream,
 * switches since it's not-uncommon for periodic samples to
 * identify a switch before any 'context switch' report.
 */
-   if (!stream->perf->exclusive_stream->ctx ||
+   if (!stream->ctx ||
stream->specific_ctx_id == ctx_id ||
stream->oa_buffer.last_ctx_id == stream->specific_ctx_id ||
reason & OAREPORT_REASON_CTX_SWITCH) {
@@ -785,7 +785,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream 
*stream,
 * While filtering for a single context we avoid
 * leaking the IDs of other contexts.
 */
-   if (stream->perf->exclusive_stream->ctx &&
+   if (stream->ctx &&
stream->specific_ctx_id != ctx_id) {
report32[2] = INVALID_CTX_ID;
}
-- 
2.25.1

[Intel-gfx] [PATCH v6 15/16] drm/i915/perf: complete programming whitelisting for XEHPSDV

[Umesh Nerlige Ramappa]

From: Lionel Landwerlin 

We have an additional register to select which slices contribute to
OAG/OAG counter increments.

Signed-off-by: Lionel Landwerlin 
Signed-off-by: Matt Roper 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_drv.h  |  2 ++
 drivers/gpu/drm/i915/i915_pci.c  |  1 +
 drivers/gpu/drm/i915/i915_perf.c | 13 +
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 4 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 866edee7d5eb..36a09719b682 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -900,6 +900,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_OA_BPC_REPORTING(dev_priv) \
(INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
+#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
+   (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
 
 /*
  * Set this flag, when platform requires 64K GTT page sizes or larger for
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 449aa2421891..dcb2fcb4dd7c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1024,6 +1024,7 @@ static const struct intel_device_info adl_p_info = {
.has_logical_ring_elsq = 1, \
.has_mslice_steering = 1, \
.has_oa_bpc_reporting = 1, \
+   .has_oa_slice_contrib_limits = 1, \
.has_rc6 = 1, \
.has_reset_engine = 1, \
.has_rps = 1, \
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index b2766485888f..2db74b5a54cd 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4261,6 +4261,11 @@ static const struct i915_range gen12_oa_b_counters[] = {
{}
 };
 
+static const struct i915_range xehp_oa_b_counters[] = {
+   { .start = 0xdc48, .end = 0xdc48 }, /* OAA_ENABLE_REG */
+   { .start = 0xdd00, .end = 0xdd48 }, /* OAG_LCE0_0 - OAA_LENABLE_REG 
*/
+};
+
 static const struct i915_range gen7_oa_mux_regs[] = {
{ .start = 0x91b8, .end = 0x91cc }, /* OA_PERFCNT[1-2], 
OA_PERFMATRIX */
{ .start = 0x9800, .end = 0x9888 }, /* MICRO_BP0_0 - NOA_WRITE */
@@ -4335,6 +4340,12 @@ static bool gen12_is_valid_b_counter_addr(struct 
i915_perf *perf, u32 addr)
return reg_in_range_table(addr, gen12_oa_b_counters);
 }
 
+static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
+{
+   return reg_in_range_table(addr, xehp_oa_b_counters) ||
+   reg_in_range_table(addr, gen12_oa_b_counters);
+}
+
 static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
 {
return reg_in_range_table(addr, gen12_oa_mux_regs);
@@ -4847,6 +4858,8 @@ void i915_perf_init(struct drm_i915_private *i915)
perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
} else if (GRAPHICS_VER(i915) == 12) {
perf->ops.is_valid_b_counter_reg =
+   HAS_OA_SLICE_CONTRIB_LIMITS(i915) ?
+   xehp_is_valid_b_counter_addr :
gen12_is_valid_b_counter_addr;
perf->ops.is_valid_mux_reg =
gen12_is_valid_mux_addr;
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 42218c8d85f2..e292c1ee7c93 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -165,6 +165,7 @@ enum intel_ppgtt_type {
func(has_media_ratio_mode); \
func(has_mslice_steering); \
func(has_oa_bpc_reporting); \
+   func(has_oa_slice_contrib_limits); \
func(has_one_eu_per_fuse_bit); \
func(has_pxp); \
func(has_rc6); \
-- 
2.25.1

[Intel-gfx] [PATCH v6 01/16] drm/i915/perf: Fix OA filtering logic for GuC mode

[Umesh Nerlige Ramappa]

With GuC mode of submission, GuC is in control of defining the context
id field that is part of the OA reports. To filter reports, UMD and KMD
must know what sw context id was chosen by GuC. There is not interface
between KMD and GuC to determine this, so read the upper-dword of
EXECLIST_STATUS to filter/squash OA reports for the specific context.

v2: Explain guc id stealing w.r.t OA use case

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_lrc.h |   2 +
 drivers/gpu/drm/i915/i915_perf.c| 144 
 2 files changed, 127 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h 
b/drivers/gpu/drm/i915/gt/intel_lrc.h
index a390f0813c8b..7111bae759f3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -110,6 +110,8 @@ enum {
 #define XEHP_SW_CTX_ID_WIDTH   16
 #define XEHP_SW_COUNTER_SHIFT  58
 #define XEHP_SW_COUNTER_WIDTH  6
+#define GEN12_GUC_SW_CTX_ID_SHIFT  39
+#define GEN12_GUC_SW_CTX_ID_WIDTH  16
 
 static inline void lrc_runtime_start(struct intel_context *ce)
 {
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 15816df916c7..255335868b6a 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1231,6 +1231,128 @@ static struct intel_context *oa_pin_context(struct 
i915_perf_stream *stream)
return stream->pinned_ctx;
 }
 
+static int
+__store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
+{
+   u32 *cs, cmd;
+
+   cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
+   if (GRAPHICS_VER(rq->engine->i915) >= 8)
+   cmd++;
+
+   cs = intel_ring_begin(rq, 4);
+   if (IS_ERR(cs))
+   return PTR_ERR(cs);
+
+   *cs++ = cmd;
+   *cs++ = i915_mmio_reg_offset(reg);
+   *cs++ = ggtt_offset;
+   *cs++ = 0;
+
+   intel_ring_advance(rq, cs);
+
+   return 0;
+}
+
+static int
+__read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset)
+{
+   struct i915_request *rq;
+   int err;
+
+   rq = i915_request_create(ce);
+   if (IS_ERR(rq))
+   return PTR_ERR(rq);
+
+   i915_request_get(rq);
+
+   err = __store_reg_to_mem(rq, reg, ggtt_offset);
+
+   i915_request_add(rq);
+   if (!err && i915_request_wait(rq, 0, HZ / 2) < 0)
+   err = -ETIME;
+
+   i915_request_put(rq);
+
+   return err;
+}
+
+static int
+gen12_guc_sw_ctx_id(struct intel_context *ce, u32 *ctx_id)
+{
+   struct i915_vma *scratch;
+   u32 *val;
+   int err;
+
+   scratch = 
__vm_create_scratch_for_read_pinned(>engine->gt->ggtt->vm, 4);
+   if (IS_ERR(scratch))
+   return PTR_ERR(scratch);
+
+   err = i915_vma_sync(scratch);
+   if (err)
+   goto err_scratch;
+
+   err = __read_reg(ce, RING_EXECLIST_STATUS_HI(ce->engine->mmio_base),
+i915_ggtt_offset(scratch));
+   if (err)
+   goto err_scratch;
+
+   val = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);
+   if (IS_ERR(val)) {
+   err = PTR_ERR(val);
+   goto err_scratch;
+   }
+
+   *ctx_id = *val;
+   i915_gem_object_unpin_map(scratch->obj);
+
+err_scratch:
+   i915_vma_unpin_and_release(, 0);
+   return err;
+}
+
+/*
+ * For execlist mode of submission, pick an unused context id
+ * 0 - (NUM_CONTEXT_TAG -1) are used by other contexts
+ * XXX_MAX_CONTEXT_HW_ID is used by idle context
+ *
+ * For GuC mode of submission read context id from the upper dword of the
+ * EXECLIST_STATUS register. Note that we read this value only once and expect
+ * that the value stays fixed for the entire OA use case. There are cases where
+ * GuC KMD implementation may deregister a context to reuse it's context id, 
but
+ * we prevent that from happening to the OA context by pinning it.
+ */
+static int gen12_get_render_context_id(struct i915_perf_stream *stream)
+{
+   u32 ctx_id, mask;
+   int ret;
+
+   if (intel_engine_uses_guc(stream->engine)) {
+   ret = gen12_guc_sw_ctx_id(stream->pinned_ctx, _id);
+   if (ret)
+   return ret;
+
+   mask = ((1U << GEN12_GUC_SW_CTX_ID_WIDTH) - 1) <<
+   (GEN12_GUC_SW_CTX_ID_SHIFT - 32);
+   } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 50)) {
+   ctx_id = (XEHP_MAX_CONTEXT_HW_ID - 1) <<
+   (XEHP_SW_CTX_ID_SHIFT - 32);
+
+   mask = ((1U << XEHP_SW_CTX_ID_WIDTH) - 1) <<
+   (XEHP_SW_CTX_ID_SHIFT - 32);
+   } else {
+   ctx_id = (GEN12_MAX_CONTEXT_HW_ID - 1) <<
+(GEN11_SW_CTX_ID_SHIFT - 32);
+
+   mask = ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) <<
+

[Intel-gfx] [PATCH v6 07/16] drm/i915/perf: Move gt-specific data from i915->perf to gt->perf

[Umesh Nerlige Ramappa]

Make perf part of gt as the OAG buffer is specific to a gt. The refactor
eventually simplifies programming the right OA buffer and the right HW
registers when supporting multiple gts.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Lionel Landwerlin 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_gt_types.h   |  3 +
 drivers/gpu/drm/i915/gt/intel_sseu.c   |  4 +-
 drivers/gpu/drm/i915/i915_perf.c   | 75 +-
 drivers/gpu/drm/i915/i915_perf_types.h | 39 +--
 drivers/gpu/drm/i915/selftests/i915_perf.c | 16 +++--
 5 files changed, 80 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 64aa2ba624fc..6f686a4244f0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -20,6 +20,7 @@
 #include "intel_gsc.h"
 
 #include "i915_vma.h"
+#include "i915_perf_types.h"
 #include "intel_engine_types.h"
 #include "intel_gt_buffer_pool_types.h"
 #include "intel_hwconfig.h"
@@ -289,6 +290,8 @@ struct intel_gt {
/* sysfs defaults per gt */
struct gt_defaults defaults;
struct kobject *sysfs_defaults;
+
+   struct i915_perf_gt perf;
 };
 
 struct intel_gt_definition {
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c 
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 66f21c735d54..6c6198a257ac 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -677,8 +677,8 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
 * If i915/perf is active, we want a stable powergating configuration
 * on the system. Use the configuration pinned by i915/perf.
 */
-   if (i915->perf.exclusive_stream)
-   req_sseu = >perf.sseu;
+   if (gt->perf.exclusive_stream)
+   req_sseu = >perf.sseu;
 
slices = hweight8(req_sseu->slice_mask);
subslices = hweight8(req_sseu->subslice_mask);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 75d320b2c1f8..83c5dc043261 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1565,8 +1565,9 @@ free_noa_wait(struct i915_perf_stream *stream)
 static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
 {
struct i915_perf *perf = stream->perf;
+   struct intel_gt *gt = stream->engine->gt;
 
-   if (WARN_ON(stream != perf->exclusive_stream))
+   if (WARN_ON(stream != gt->perf.exclusive_stream))
return;
 
/*
@@ -1575,7 +1576,7 @@ static void i915_oa_stream_destroy(struct 
i915_perf_stream *stream)
 *
 * See i915_oa_init_reg_state() and lrc_configure_all_contexts()
 */
-   WRITE_ONCE(perf->exclusive_stream, NULL);
+   WRITE_ONCE(gt->perf.exclusive_stream, NULL);
perf->ops.disable_metric_set(stream);
 
free_oa_buffer(stream);
@@ -2566,10 +2567,11 @@ oa_configure_all_contexts(struct i915_perf_stream 
*stream,
 {
struct drm_i915_private *i915 = stream->perf->i915;
struct intel_engine_cs *engine;
+   struct intel_gt *gt = stream->engine->gt;
struct i915_gem_context *ctx, *cn;
int err;
 
-   lockdep_assert_held(>perf->lock);
+   lockdep_assert_held(>perf.lock);
 
/*
 * The OA register config is setup through the context image. This image
@@ -3090,6 +3092,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 {
struct drm_i915_private *i915 = stream->perf->i915;
struct i915_perf *perf = stream->perf;
+   struct intel_gt *gt;
int format_size;
int ret;
 
@@ -3098,6 +3101,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
"OA engine not specified\n");
return -EINVAL;
}
+   gt = props->engine->gt;
 
/*
 * If the sysfs metrics/ directory wasn't registered for some
@@ -3128,7 +3132,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 * counter reports and marshal to the appropriate client
 * we currently only allow exclusive access
 */
-   if (perf->exclusive_stream) {
+   if (gt->perf.exclusive_stream) {
drm_dbg(>perf->i915->drm,
"OA unit already in use\n");
return -EBUSY;
@@ -3208,8 +3212,8 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 
stream->ops = _oa_stream_ops;
 
-   perf->sseu = props->sseu;
-   WRITE_ONCE(perf->exclusive_stream, stream);
+   stream->engine->gt->perf.sseu = props->sseu;
+   WRITE_ONCE(gt->perf.exclusive_stream, stream);
 
ret = i915_perf_stream_enable_sync(stream);
if (ret) {
@@ -3231,7 +3235,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
return 0;
 
 err_enable:
-   WRITE_ONCE(perf->exclusive_stream, NULL);
+   

[Intel-gfx] [PATCH v6 03/16] drm/i915/perf: Fix noa wait predication for DG2

[Umesh Nerlige Ramappa]

Predication for batch buffer commands changed in XEHPSDV.
MI_BATCH_BUFFER_START predicates based on MI_SET_PREDICATE_RESULT
register. The MI_SET_PREDICATE_RESULT register can only be modified
with MI_SET_PREDICATE command. When configured, the MI_SET_PREDICATE
command sets MI_SET_PREDICATE_RESULT based on bit 0 of
MI_PREDICATE_RESULT_2. Use this to configure predication in noa_wait.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_engine_regs.h |  1 +
 drivers/gpu/drm/i915/i915_perf.c| 24 +
 2 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h 
b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index fe1a0d5fd4b1..ee3efd06ee54 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -201,6 +201,7 @@
 #define RING_CONTEXT_STATUS_PTR(base)  _MMIO((base) + 0x3a0)
 #define RING_CTX_TIMESTAMP(base)   _MMIO((base) + 0x3a8) /* gen8+ 
*/
 #define RING_PREDICATE_RESULT(base)_MMIO((base) + 0x3b8)
+#define MI_PREDICATE_RESULT_2_ENGINE(base) _MMIO((base) + 0x3bc)
 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 
4)
 #define   RING_FORCE_TO_NONPRIV_DENY   REG_BIT(30)
 #define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK   REG_GENMASK(25, 2)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2b772a6b1cd6..e68666b44a72 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -286,6 +286,7 @@ static u32 i915_perf_stream_paranoid = true;
 #define OAREPORT_REASON_CTX_SWITCH (1<<3)
 #define OAREPORT_REASON_CLK_RATIO  (1<<5)
 
+#define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
 
 /* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
  *
@@ -1760,6 +1761,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
DELTA_TARGET,
N_CS_GPR
};
+   i915_reg_t mi_predicate_result = HAS_MI_SET_PREDICATE(i915) ?
+ MI_PREDICATE_RESULT_2_ENGINE(base) :
+ 
MI_PREDICATE_RESULT_1(RENDER_RING_BASE);
 
bo = i915_gem_object_create_internal(i915, 4096);
if (IS_ERR(bo)) {
@@ -1797,7 +1801,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
stream, cs, true /* save */, CS_GPR(i),
INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
cs = save_restore_register(
-   stream, cs, true /* save */, 
MI_PREDICATE_RESULT_1(RENDER_RING_BASE),
+   stream, cs, true /* save */, mi_predicate_result,
INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
 
/* First timestamp snapshot location. */
@@ -1851,7 +1855,10 @@ static int alloc_noa_wait(struct i915_perf_stream 
*stream)
 */
*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
-   *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));
+   *cs++ = i915_mmio_reg_offset(mi_predicate_result);
+
+   if (HAS_MI_SET_PREDICATE(i915))
+   *cs++ = MI_SET_PREDICATE | 1;
 
/* Restart from the beginning if we had timestamps roll over. */
*cs++ = (GRAPHICS_VER(i915) < 8 ?
@@ -1861,6 +1868,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
*cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
*cs++ = 0;
 
+   if (HAS_MI_SET_PREDICATE(i915))
+   *cs++ = MI_SET_PREDICATE;
+
/*
 * Now add the diff between to previous timestamps and add it to :
 *  (((1 * << 64) - 1) - delay_ns)
@@ -1888,7 +1898,10 @@ static int alloc_noa_wait(struct i915_perf_stream 
*stream)
 */
*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
-   *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));
+   *cs++ = i915_mmio_reg_offset(mi_predicate_result);
+
+   if (HAS_MI_SET_PREDICATE(i915))
+   *cs++ = MI_SET_PREDICATE | 1;
 
/* Predicate the jump.  */
*cs++ = (GRAPHICS_VER(i915) < 8 ?
@@ -1898,13 +1911,16 @@ static int alloc_noa_wait(struct i915_perf_stream 
*stream)
*cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
*cs++ = 0;
 
+   if (HAS_MI_SET_PREDICATE(i915))
+   *cs++ = MI_SET_PREDICATE;
+
/* Restore registers. */
for (i = 0; i < N_CS_GPR; i++)
cs = save_restore_register(
stream, cs, false /* restore */, CS_GPR(i),
INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
cs = save_restore_register(
-   stream, cs, false /* restore */, 
MI_PREDICATE_RESULT_1(RENDER_RING_BASE),
+   stream, cs, 

[Intel-gfx] [PATCH v6 08/16] drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops

[Umesh Nerlige Ramappa]

With multi-gt, user can access multiple OA buffers concurrently. Use
stream->lock instead of gt->perf.lock to serialize file operations.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_perf.c   | 31 --
 drivers/gpu/drm/i915/i915_perf_types.h |  5 +
 2 files changed, 19 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 83c5dc043261..9a00398ae25f 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3231,6 +3231,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
stream->poll_check_timer.function = oa_poll_check_timer_cb;
init_waitqueue_head(>poll_wq);
spin_lock_init(>oa_buffer.ptr_lock);
+   mutex_init(>lock);
 
return 0;
 
@@ -3294,7 +3295,6 @@ static ssize_t i915_perf_read(struct file *file,
  loff_t *ppos)
 {
struct i915_perf_stream *stream = file->private_data;
-   struct intel_gt *gt = stream->engine->gt;
size_t offset = 0;
int ret;
 
@@ -3318,14 +3318,14 @@ static ssize_t i915_perf_read(struct file *file,
if (ret)
return ret;
 
-   mutex_lock(>perf.lock);
+   mutex_lock(>lock);
ret = stream->ops->read(stream, buf, count, );
-   mutex_unlock(>perf.lock);
+   mutex_unlock(>lock);
} while (!offset && !ret);
} else {
-   mutex_lock(>perf.lock);
+   mutex_lock(>lock);
ret = stream->ops->read(stream, buf, count, );
-   mutex_unlock(>perf.lock);
+   mutex_unlock(>lock);
}
 
/* We allow the poll checking to sometimes report false positive EPOLLIN
@@ -3372,9 +3372,6 @@ static enum hrtimer_restart oa_poll_check_timer_cb(struct 
hrtimer *hrtimer)
  * _perf_stream_ops->poll_wait to call poll_wait() with a wait queue that
  * will be woken for new stream data.
  *
- * Note: The >perf.lock mutex has been taken to serialize
- * with any non-file-operation driver hooks.
- *
  * Returns: any poll events that are ready without sleeping
  */
 static __poll_t i915_perf_poll_locked(struct i915_perf_stream *stream,
@@ -3413,12 +3410,11 @@ static __poll_t i915_perf_poll_locked(struct 
i915_perf_stream *stream,
 static __poll_t i915_perf_poll(struct file *file, poll_table *wait)
 {
struct i915_perf_stream *stream = file->private_data;
-   struct intel_gt *gt = stream->engine->gt;
__poll_t ret;
 
-   mutex_lock(>perf.lock);
+   mutex_lock(>lock);
ret = i915_perf_poll_locked(stream, file, wait);
-   mutex_unlock(>perf.lock);
+   mutex_unlock(>lock);
 
return ret;
 }
@@ -3517,9 +3513,6 @@ static long i915_perf_config_locked(struct 
i915_perf_stream *stream,
  * @cmd: the ioctl request
  * @arg: the ioctl data
  *
- * Note: The >perf.lock mutex has been taken to serialize
- * with any non-file-operation driver hooks.
- *
  * Returns: zero on success or a negative error code. Returns -EINVAL for
  * an unknown ioctl request.
  */
@@ -3557,12 +3550,11 @@ static long i915_perf_ioctl(struct file *file,
unsigned long arg)
 {
struct i915_perf_stream *stream = file->private_data;
-   struct intel_gt *gt = stream->engine->gt;
long ret;
 
-   mutex_lock(>perf.lock);
+   mutex_lock(>lock);
ret = i915_perf_ioctl_locked(stream, cmd, arg);
-   mutex_unlock(>perf.lock);
+   mutex_unlock(>lock);
 
return ret;
 }
@@ -3608,6 +3600,11 @@ static int i915_perf_release(struct inode *inode, struct 
file *file)
struct i915_perf *perf = stream->perf;
struct intel_gt *gt = stream->engine->gt;
 
+   /*
+* Within this call, we know that the fd is being closed and we have no
+* other user of stream->lock. Use the perf lock to destroy the stream
+* here.
+*/
mutex_lock(>perf.lock);
i915_perf_destroy_locked(stream);
mutex_unlock(>perf.lock);
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h 
b/drivers/gpu/drm/i915/i915_perf_types.h
index e888bfab478f..dc9bfd8086cf 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -146,6 +146,11 @@ struct i915_perf_stream {
 */
struct intel_engine_cs *engine;
 
+   /*
+* Lock associated with operations on stream
+*/
+   struct mutex lock;
+
/**
 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
 * properties given when opening a stream, representing the contents
-- 
2.25.1

[Intel-gfx] [PATCH v6 14/16] drm/i915/guc: Support OA when Wa_16011777198 is enabled

[Umesh Nerlige Ramappa]

From: Vinay Belgaumkar 

On DG2, a w/a resets RCS/CCS before it goes into RC6. This breaks OA
since OA does not expect engine resets during its use. Fix it by
disabling RC6.

v2: (Ashutosh)
- Bring back slpc_unset_param helper
- Update commit msg
- Use with_intel_runtime_pm helper for set/unset

v3: (Ashutosh)
- Just use intel_uc_uses_guc_rc

Signed-off-by: Vinay Belgaumkar 
Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h |  9 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 66 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h   |  2 +
 drivers/gpu/drm/i915/i915_perf.c  | 27 
 4 files changed, 104 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
index 4c840a2639dc..811add10c30d 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
@@ -128,6 +128,15 @@ enum slpc_media_ratio_mode {
SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO = 2,
 };
 
+enum slpc_gucrc_mode {
+   SLPC_GUCRC_MODE_HW = 0,
+   SLPC_GUCRC_MODE_GUCRC_NO_RC6 = 1,
+   SLPC_GUCRC_MODE_GUCRC_STATIC_TIMEOUT = 2,
+   SLPC_GUCRC_MODE_GUCRC_DYNAMIC_HYSTERESIS = 3,
+
+   SLPC_GUCRC_MODE_MAX,
+};
+
 enum slpc_event_id {
SLPC_EVENT_RESET = 0,
SLPC_EVENT_SHUTDOWN = 1,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index fdd895f73f9f..b3a4fb9e021f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -137,6 +137,17 @@ static int guc_action_slpc_set_param(struct intel_guc 
*guc, u8 id, u32 value)
return ret > 0 ? -EPROTO : ret;
 }
 
+static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)
+{
+   u32 request[] = {
+   GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
+   SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1),
+   id,
+   };
+
+   return intel_guc_send(guc, request, ARRAY_SIZE(request));
+}
+
 static bool slpc_is_running(struct intel_guc_slpc *slpc)
 {
return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
@@ -190,6 +201,15 @@ static int slpc_set_param(struct intel_guc_slpc *slpc, u8 
id, u32 value)
return ret;
 }
 
+static int slpc_unset_param(struct intel_guc_slpc *slpc, u8 id)
+{
+   struct intel_guc *guc = slpc_to_guc(slpc);
+
+   GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+
+   return guc_action_slpc_unset_param(guc, id);
+}
+
 static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
 {
struct drm_i915_private *i915 = slpc_to_i915(slpc);
@@ -610,6 +630,52 @@ static void slpc_get_rp_values(struct intel_guc_slpc *slpc)
slpc->boost_freq = slpc->rp0_freq;
 }
 
+/**
+ * intel_guc_slpc_override_gucrc_mode() - override GUCRC mode
+ * @slpc: pointer to intel_guc_slpc.
+ * @mode: new value of the mode.
+ *
+ * This function will override the GUCRC mode.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode)
+{
+   int ret;
+   struct drm_i915_private *i915 = slpc_to_i915(slpc);
+   intel_wakeref_t wakeref;
+
+   if (mode >= SLPC_GUCRC_MODE_MAX)
+   return -EINVAL;
+
+   with_intel_runtime_pm(>runtime_pm, wakeref) {
+   ret = slpc_set_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
+   if (ret)
+   drm_err(>drm,
+   "Override gucrc mode %d failed %d\n",
+   mode, ret);
+   }
+
+   return ret;
+}
+
+int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
+{
+   struct drm_i915_private *i915 = slpc_to_i915(slpc);
+   intel_wakeref_t wakeref;
+   int ret = 0;
+
+   with_intel_runtime_pm(>runtime_pm, wakeref) {
+   ret = slpc_unset_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE);
+   if (ret)
+   drm_err(>drm,
+   "Unsetting gucrc mode failed %d\n",
+   ret);
+   }
+
+   return ret;
+}
+
 /*
  * intel_guc_slpc_enable() - Start SLPC
  * @slpc: pointer to intel_guc_slpc.
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index 82a98f78f96c..ccf483730d9d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -42,5 +42,7 @@ int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc 
*slpc, u32 val);
 void intel_guc_pm_intrmsk_enable(struct intel_gt *gt);
 void intel_guc_slpc_boost(struct intel_guc_slpc *slpc);
 void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc);
+int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc);
+int intel_guc_slpc_override_gucrc_mode(struct 

[Intel-gfx] [PATCH v6 02/16] drm/i915/perf: Add 32-bit OAG and OAR formats for DG2

[Umesh Nerlige Ramappa]

Add new OA formats for DG2.

MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893

v2:
- Update commit title (Ashutosh)
- Coding style fixes (Lionel)
- 64 bit OA formats need UMD changes in GPUvis, drop for now and send in a
  separate series with UMD changes

v3:
- Update commit message to drop 64 bit related description

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Lionel Landwerlin  #1
---
 drivers/gpu/drm/i915/i915_perf.c | 7 +++
 include/uapi/drm/i915_drm.h  | 4 
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 255335868b6a..2b772a6b1cd6 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -320,6 +320,8 @@ static const struct i915_oa_format 
oa_formats[I915_OA_FORMAT_MAX] = {
[I915_OA_FORMAT_A12]= { 0, 64 },
[I915_OA_FORMAT_A12_B8_C8]  = { 2, 128 },
[I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
+   [I915_OAR_FORMAT_A32u40_A4u32_B8_C8]= { 5, 256 },
+   [I915_OA_FORMAT_A24u40_A14u32_B8_C8]= { 5, 256 },
 };
 
 #define SAMPLE_OA_REPORT  (1<<0)
@@ -4515,6 +4517,11 @@ static void oa_init_supported_formats(struct i915_perf 
*perf)
oa_format_add(perf, I915_OA_FORMAT_C4_B8);
break;
 
+   case INTEL_DG2:
+   oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
+   oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
+   break;
+
default:
MISSING_CASE(platform);
}
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 2e613109356b..158b35fb28f3 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2666,6 +2666,10 @@ enum drm_i915_oa_format {
I915_OA_FORMAT_A12_B8_C8,
I915_OA_FORMAT_A32u40_A4u32_B8_C8,
 
+   /* DG2 */
+   I915_OAR_FORMAT_A32u40_A4u32_B8_C8,
+   I915_OA_FORMAT_A24u40_A14u32_B8_C8,
+
I915_OA_FORMAT_MAX  /* non-ABI */
 };
 
-- 
2.25.1

[Intel-gfx] [PATCH v6 00/16] Add DG2 OA support

[Umesh Nerlige Ramappa]

Add OA format support for DG2 and various fixes for DG2.

This series has 2 uapi changes listed below:

1) drm/i915/perf: Add OAG and OAR formats for DG2

DG2 has new OA formats defined that can be selected by the
user. The UMD changes that are consumed by GPUvis are:
https://patchwork.freedesktop.org/patch/504456/?series=107633=5

Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893

2) drm/i915/perf: Apply Wa_18013179988

DG2 has a bug where the OA timestamp does not tick at the CS timestamp
frequency. Instead it ticks at a multiple that is determined from the
CTC_SHIFT value in RPM_CONFIG. Since the timestamp is used by UMD to
make sense of all the counters in the report, expose the OA timestamp
frequency to the user. The interface is generic and applies to all
platforms. On platforms where the bug is not present, this returns the
CS timestamp frequency. UMD specific changes consumed by GPUvis are:
https://patchwork.freedesktop.org/patch/504464/?series=107633=5

Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893

v2:
- Add review comments
- Update uapi changes in cover letter
- Drop patches for non-production platforms
drm/i915/perf: Use helpers to process reports w.r.t. OA buffer size
drm/i915/perf: Add Wa_16010703925:dg2

- Drop 64-bit OA format changes for now
drm/i915/perf: Parse 64bit report header formats correctly
drm/i915/perf: Add Wa_1608133521:dg2

v3:
- Add review comments to patches 02, 04, 05, 14
- Drop Acks

v4:
- Add review comments to patch 04
- Update R-bs
- Add MR links to patches 02 and 12

v5:
- Drop unrelated comment
- Rebase and fix MCR reg write
- On pre-gen12, EU flex config is saved/restored in the context image, so
  save/restore EU flex config only for gen12.

v6:
- Fix checkpatch issues

Test-with: 20221025200709.83314-1-umesh.nerlige.rama...@intel.com
Signed-off-by: Umesh Nerlige Ramappa 

Lionel Landwerlin (1):
  drm/i915/perf: complete programming whitelisting for XEHPSDV

Umesh Nerlige Ramappa (14):
  drm/i915/perf: Fix OA filtering logic for GuC mode
  drm/i915/perf: Add 32-bit OAG and OAR formats for DG2
  drm/i915/perf: Fix noa wait predication for DG2
  drm/i915/perf: Determine gen12 oa ctx offset at runtime
  drm/i915/perf: Enable bytes per clock reporting in OA
  drm/i915/perf: Simply use stream->ctx
  drm/i915/perf: Move gt-specific data from i915->perf to gt->perf
  drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops
  drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers
  drm/i915/perf: Store a pointer to oa_format in oa_buffer
  drm/i915/perf: Add Wa_1508761755:dg2
  drm/i915/perf: Apply Wa_18013179988
  drm/i915/perf: Save/restore EU flex counters across reset
  drm/i915/perf: Enable OA for DG2

Vinay Belgaumkar (1):
  drm/i915/guc: Support OA when Wa_16011777198 is enabled

 drivers/gpu/drm/i915/gt/intel_engine_regs.h   |   1 +
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h  |   4 +
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   |   1 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h  |   3 +
 drivers/gpu/drm/i915/gt/intel_lrc.h   |   2 +
 drivers/gpu/drm/i915/gt/intel_sseu.c  |   4 +-
 .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h |   9 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c|  10 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   |  66 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h   |   2 +
 drivers/gpu/drm/i915/i915_drv.h   |   5 +
 drivers/gpu/drm/i915/i915_getparam.c  |   3 +
 drivers/gpu/drm/i915/i915_pci.c   |   2 +
 drivers/gpu/drm/i915/i915_perf.c  | 576 ++
 drivers/gpu/drm/i915/i915_perf.h  |   2 +
 drivers/gpu/drm/i915/i915_perf_oa_regs.h  |   6 +-
 drivers/gpu/drm/i915/i915_perf_types.h|  47 +-
 drivers/gpu/drm/i915/intel_device_info.h  |   2 +
 drivers/gpu/drm/i915/selftests/i915_perf.c|  16 +-
 include/uapi/drm/i915_drm.h   |  10 +
 20 files changed, 630 insertions(+), 141 deletions(-)

-- 
2.25.1

Re: [Intel-gfx] [PATCH v6 16/23] drm/probe-helper: Provide a TV get_modes helper

[Mateusz Kwiatkowski]

Hi Maxime,

First of all, nice idea with the helper function that can be reused by different
drivers. This is neat!

But looking at this function, it feels a bit overcomplicated. You're creating
the two modes, then checking which one is the default, then set the preferred
one and possibly reorder them. Maybe it can be simplified somehow?

Although when I tried to refactor it myself, I ended up with something that's
not better at all. Maybe it needs to be complicated, after all :(

Anyway, the current version seems to have a couple of bugs:

> + if (tv_mode_supported(connector, DRM_MODE_TV_MODE_PAL) ||
> + tv_mode_supported(connector, DRM_MODE_TV_MODE_PAL_N) ||
> + tv_mode_supported(connector, DRM_MODE_TV_MODE_SECAM)) {
> + mode = drm_mode_analog_pal_576i(connector->dev);
> + if (!mode)
> + return 0;
> +
> + tv_modes[count++] = mode;
> + }

If the 480i mode has been created properly, but there's an error creating the
576i one (we enter the if (!mode) clause), the 480i mode will leak.

> + if (count == 1) {

You're handling the count == 1 case specially, but if count == 0, the rest of
the code will assume that two modes exist and probably segfault in the process.

> + ret = drm_object_property_get_default_value(>base,
> + 
> dev->mode_config.tv_mode_property,
> + _mode);
> + if (ret)
> + return 0;
> +
> + if (cmdline->tv_mode_specified)
> + default_mode = cmdline->tv_mode;

In case of an error (ret != 0), the modes created so far in the tv_modes array
will leak.

Also, I wonder if maybe the if (cmdline->tv_mode_specified) clause should go
first? If we're going to use the default from cmdline, there's no point in even
querying the property default value.

Best regards,
Mateusz Kwiatkowski

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/sdvo: Fix LVDS fixed mode setup and clean up output setup

[Patchwork]

== Series Details ==

Series: drm/i915/sdvo: Fix LVDS fixed mode setup and clean up output setup
URL   : https://patchwork.freedesktop.org/series/110167/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12296_full -> Patchwork_110167v1_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_110167v1_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110167v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110167v1_full:

### IGT changes ###

 Warnings 

  * igt@runner@aborted:
- shard-skl:  ([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4], 
[FAIL][5], [FAIL][6]) ([i915#3002] / [i915#4312] / [i915#6949]) -> ([FAIL][7], 
[FAIL][8], [FAIL][9], [FAIL][10], [FAIL][11]) ([i915#3002] / [i915#4312])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl3/igt@run...@aborted.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl2/igt@run...@aborted.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl4/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl6/igt@run...@aborted.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl6/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl9/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110167v1/shard-skl6/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110167v1/shard-skl1/igt@run...@aborted.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110167v1/shard-skl3/igt@run...@aborted.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110167v1/shard-skl10/igt@run...@aborted.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110167v1/shard-skl6/igt@run...@aborted.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_pwrite@basic-exhaustion:
- {shard-rkl}:NOTRUN -> [INCOMPLETE][12]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110167v1/shard-rkl-5/igt@gem_pwr...@basic-exhaustion.html

  * igt@kms_vblank@pipe-d-ts-continuation-dpms-rpm:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][13]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110167v1/shard-dg1-15/igt@kms_vbl...@pipe-d-ts-continuation-dpms-rpm.html

  * igt@sysfs_timeslice_duration@idempotent@vcs0:
- {shard-dg1}:NOTRUN -> [FAIL][14] +9 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110167v1/shard-dg1-18/igt@sysfs_timeslice_duration@idempot...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_110167v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-skl:  ([PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
[PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
[PASS][37]) -> ([PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], 
[PASS][49], [FAIL][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], 
[PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59]) ([i915#5032])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl9/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl9/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl9/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl7/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl7/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl7/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl6/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl6/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl6/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl6/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl5/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl4/boot.html
   [27]: 

Re: [Intel-gfx] [PATCH 10/10] iommufd: Allow iommufd to supply /dev/vfio/vfio

[Alex Williamson]

On Tue, 25 Oct 2022 15:50:45 -0300
Jason Gunthorpe  wrote:

> If the VFIO container is compiled out, give a kconfig option for iommufd
> to provide the miscdev node with the same name and permissions as vfio
> uses.
> 
> The compatibility node supports the same ioctls as VFIO and automatically
> enables the VFIO compatible pinned page accounting mode.

I think I'd like to see some sort of breadcrumb when /dev/vfio/vfio is
provided by something other than the vfio container code.  If we intend
to include this before P2P is resolved, that breadcrumb (dmesg I'm
guessing) might also list any known limitations of the compatibility to
save time with debugging.  Thanks,

Alex

> Signed-off-by: Jason Gunthorpe 
> ---
>  drivers/iommu/iommufd/Kconfig | 12 
>  drivers/iommu/iommufd/main.c  | 35 ---
>  2 files changed, 44 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/iommu/iommufd/Kconfig b/drivers/iommu/iommufd/Kconfig
> index f0a2012234fa09..afc83b7575cce6 100644
> --- a/drivers/iommu/iommufd/Kconfig
> +++ b/drivers/iommu/iommufd/Kconfig
> @@ -14,6 +14,18 @@ config IOMMUFD
> If you don't know what to do here, say N.
>  
>  if IOMMUFD
> +config IOMMUFD_VFIO_CONTAINER
> + bool "IOMMUFD provides the VFIO container /dev/vfio/vfio"
> + depends on VFIO && !VFIO_CONTAINER
> + default VFIO && !VFIO_CONTAINER
> + help
> +   IOMMUFD will provide /dev/vfio/vfio instead of VFIO. This relies on
> +   IOMMUFD providing compatibility emulation to give the same ioctls.
> +   It provides an option to build a kernel with legacy VFIO components
> +   removed.
> +
> +   Unless testing IOMMUFD say N here.
> +
>  config IOMMUFD_TEST
>   bool "IOMMU Userspace API Test support"
>   depends on RUNTIME_TESTING_MENU
> diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c
> index 8a31c1a14cdd53..19db81fbf7f08f 100644
> --- a/drivers/iommu/iommufd/main.c
> +++ b/drivers/iommu/iommufd/main.c
> @@ -24,6 +24,7 @@
>  #include 
>  #include 
>  
> +#include "io_pagetable.h"
>  #include "iommufd_private.h"
>  #include "iommufd_test.h"
>  
> @@ -31,6 +32,7 @@ struct iommufd_object_ops {
>   void (*destroy)(struct iommufd_object *obj);
>  };
>  static struct iommufd_object_ops iommufd_object_ops[];
> +static struct miscdevice vfio_misc_dev;
>  
>  struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx,
>size_t size,
> @@ -167,6 +169,13 @@ static int iommufd_fops_open(struct inode *inode, struct 
> file *filp)
>   if (!ictx)
>   return -ENOMEM;
>  
> + /*
> +  * For compatibility with VFIO when /dev/vfio/vfio is opened we default
> +  * to the same rlimit accounting as vfio uses.
> +  */
> + if (filp->private_data == _misc_dev)
> + ictx->account_mode = IOPT_PAGES_ACCOUNT_MM;
> +
>   xa_init_flags(>objects, XA_FLAGS_ALLOC1 | XA_FLAGS_ACCOUNT);
>   ictx->file = filp;
>   filp->private_data = ictx;
> @@ -392,26 +401,46 @@ static struct miscdevice iommu_misc_dev = {
>   .mode = 0660,
>  };
>  
> +
> +static struct miscdevice vfio_misc_dev = {
> + .minor = VFIO_MINOR,
> + .name = "vfio",
> + .fops = _fops,
> + .nodename = "vfio/vfio",
> + .mode = 0666,
> +};
> +
>  static int __init iommufd_init(void)
>  {
>   int ret;
>  
>   ret = misc_register(_misc_dev);
> - if (ret) {
> - pr_err("Failed to register misc device\n");
> + if (ret)
>   return ret;
> - }
>  
> + if (IS_ENABLED(CONFIG_IOMMUFD_VFIO_CONTAINER)) {
> + ret = misc_register(_misc_dev);
> + if (ret)
> + goto err_misc;
> + }
>   return 0;
> +err_misc:
> + misc_deregister(_misc_dev);
> + return ret;
>  }
>  
>  static void __exit iommufd_exit(void)
>  {
> + if (IS_ENABLED(CONFIG_IOMMUFD_VFIO_CONTAINER))
> + misc_deregister(_misc_dev);
>   misc_deregister(_misc_dev);
>  }
>  
>  module_init(iommufd_init);
>  module_exit(iommufd_exit);
>  
> +#if IS_ENABLED(CONFIG_IOMMUFD_VFIO_CONTAINER)
> +MODULE_ALIAS_MISCDEV(VFIO_MINOR);
> +#endif
>  MODULE_DESCRIPTION("I/O Address Space Management for passthrough devices");
>  MODULE_LICENSE("GPL");

Re: [Intel-gfx] [PATCH v6 14/23] drm/modes: Properly generate a drm_display_mode from a named mode

[Mateusz Kwiatkowski]

Hi Maxime,


+static struct drm_display_mode *drm_named_mode(struct drm_device *dev,
+  struct drm_cmdline_mode *cmd)
+{
+   struct drm_display_mode *mode;
+   unsigned int i;
+
+   for (i = 0; i < ARRAY_SIZE(drm_named_modes); i++) {
+   const struct drm_named_mode *named_mode = _named_modes[i];
+
+   if (strcmp(cmd->name, named_mode->name))
+   continue;
+
+   if (!named_mode->tv_mode)
+   continue;
+
+   mode = drm_analog_tv_mode(dev,
+ named_mode->tv_mode,
+ named_mode->pixel_clock_khz * 1000,
+ named_mode->xres,
+ named_mode->yres,
+ named_mode->flags & 
DRM_MODE_FLAG_INTERLACE);
+   if (!mode)
+   return NULL;
+
+   return mode;
+   }
+
+   return NULL;
+}
+


You didn't add tv_mode_specified to struct drm_named_mode, and left the
if (!named_mode->tv_mode) condition here. This will break on NTSC.

Best regards,
Mateusz Kwiatkowski

Re: [Intel-gfx] [PATCH 04/10] vfio: Move storage of allow_unsafe_interrupts to vfio_main.c

[Alex Williamson]

On Tue, 25 Oct 2022 15:17:10 -0300
Jason Gunthorpe  wrote:

> This legacy module knob has become uAPI, when set on the vfio_iommu_type1
> it disables some security protections in the iommu drivers. Move the
> storage for this knob to vfio_main.c so that iommufd can access it too.

I don't really understand this, we're changing the behavior of the
iommufd_device_attach() operation based on the modules options of
vfio_iommu_type1, which may not be loaded or even compiled into the
kernel.  Our compatibility story falls apart when VFIO_CONTAINER is not
set, iommufd sneaks in to usurp /dev/vfio/vfio, and the user's module
options for type1 go unprocessed.

I hate to suggest that type1 becomes a module that does nothing more
than maintain consistency of this variable when the full type1 isn't
available, but is that what we need to do?  Thanks,

Alex

> Signed-off-by: Jason Gunthorpe 
> ---
>  drivers/vfio/vfio.h | 2 ++
>  drivers/vfio/vfio_iommu_type1.c | 5 ++---
>  drivers/vfio/vfio_main.c| 3 +++
>  3 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
> index f95f4925b83bbd..54e5a8e0834ccb 100644
> --- a/drivers/vfio/vfio.h
> +++ b/drivers/vfio/vfio.h
> @@ -130,4 +130,6 @@ extern bool vfio_noiommu __read_mostly;
>  enum { vfio_noiommu = false };
>  #endif
>  
> +extern bool vfio_allow_unsafe_interrupts;
> +
>  #endif
> diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
> index 23c24fe98c00d4..186e33a006d314 100644
> --- a/drivers/vfio/vfio_iommu_type1.c
> +++ b/drivers/vfio/vfio_iommu_type1.c
> @@ -44,9 +44,8 @@
>  #define DRIVER_AUTHOR   "Alex Williamson "
>  #define DRIVER_DESC "Type1 IOMMU driver for VFIO"
>  
> -static bool allow_unsafe_interrupts;
>  module_param_named(allow_unsafe_interrupts,
> -allow_unsafe_interrupts, bool, S_IRUGO | S_IWUSR);
> +vfio_allow_unsafe_interrupts, bool, S_IRUGO | S_IWUSR);
>  MODULE_PARM_DESC(allow_unsafe_interrupts,
>"Enable VFIO IOMMU support for on platforms without interrupt 
> remapping support.");
>  
> @@ -2282,7 +2281,7 @@ static int vfio_iommu_type1_attach_group(void 
> *iommu_data,
>   iommu_group_for_each_dev(iommu_group, (void 
> *)IOMMU_CAP_INTR_REMAP,
>vfio_iommu_device_capable);
>  
> - if (!allow_unsafe_interrupts && !msi_remap) {
> + if (!vfio_allow_unsafe_interrupts && !msi_remap) {
>   pr_warn("%s: No interrupt remapping support.  Use the module 
> param \"allow_unsafe_interrupts\" to enable VFIO IOMMU support on this 
> platform\n",
>  __func__);
>   ret = -EPERM;
> diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
> index 8d809ecd982b39..1e414b2c48a511 100644
> --- a/drivers/vfio/vfio_main.c
> +++ b/drivers/vfio/vfio_main.c
> @@ -51,6 +51,9 @@ static struct vfio {
>   struct ida  device_ida;
>  } vfio;
>  
> +bool vfio_allow_unsafe_interrupts;
> +EXPORT_SYMBOL_GPL(vfio_allow_unsafe_interrupts);
> +
>  static DEFINE_XARRAY(vfio_device_set_xa);
>  static const struct file_operations vfio_group_fops;
>  

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/1] drm/i915/pxp: Separate PXP FW interface structures for both v42 and 43

[Teres Alexis, Alan Previn]

The issues reported below are unrelated to the patch because:
1. SKL and ICL do not even support PXP and none of the code path of this series 
will get executed.
2. RKL supports PXP but the code paths only get executed when PXP is enabled by 
the component binding and activated (via IGT PXP) whereas the failure was on 
"[IGT] i915_selftest: starting dynamic subtest hugepages" and no PXP code paths 
executed.

Thus these failures are unrelated.


On Tue, 2022-10-25 at 00:21 +, Patchwork wrote:
Patch Details
Series: series starting with [1/1] drm/i915/pxp: Separate PXP FW interface 
structures for both v42 and 43
URL:https://patchwork.freedesktop.org/series/110084/
State:  failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110084v1/index.html
CI Bug Log - changes from CI_DRM_12288 -> Patchwork_110084v1
Summary

FAILURE

Serious unknown changes coming with Patchwork_110084v1 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_110084v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110084v1/index.html

Participating hosts (41 -> 41)

Additional (1): bat-atsm-1
Missing (1): fi-ctg-p8600

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_110084v1:

IGT changes
Possible regressions

  *   igt@i915_selftest@live@hugepages:

 *   fi-rkl-guc: 
PASS
 -> 
DMESG-FAIL

 *   fi-skl-guc: 
PASS
 -> 
DMESG-FAIL

 *   fi-icl-u2: 
PASS
 -> 
DMESG-FAIL

Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  *   igt@i915_selftest@live@hugepages:
 *   {fi-tgl-dsi}: NOTRUN -> 
DMESG-FAIL

Known issues

Here are the changes found in Patchwork_110084v1 that come from known issues:

I

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

[Matthew Garrett]

On Wed, Oct 26, 2022 at 11:59:28AM +0200, Hans de Goede wrote:

> Ok, so this is a local customization to what is already a custom BIOS
> for a custom motherboard. There is a lot of custom in that sentence and
> TBH at some point things might become too custom for them to be expected
> to work OOTB.

But it *did* work OOTB before. You broke it. I accept that I'm a 
ludicrously weird corner case here, but there are going to be other 
systems that are also affected by this.

> I'm afraid things are not that simple. I assume that with
> "if ACPI backlight control is expected to work" you mean don't
> use ACPI backlight control when (acpi_osi_is_win8() && native_available)
> evaluates to true because it is known to be broken on some of
> those systems because Windows 8 stopped using it ?

Correct.

> Unfortunately something similar applies to vendor interfaces,
> When Windows XP started using (and mandating for certification
> IIRC) ACPI backlight control, vendors still kept their own
> vendor specific EC/smbios/ACPI/WMI backlight interfaces around for
> a long long time, except they were often no longer tested.

The current situation (both before your patchset and with its current 
implementation) is that vendor is preferred to native, so if the vendor 
interface is present then we're already using it.

> > The 
> > problem you're dealing with is that the knowledge of whether or not 
> > there's a vendor interface isn't something the core kernel code knows 
> > about. What you're proposing here is effectively for us to expose 
> > additional information about whether or not there's a vendor interface 
> > in the system firmware, but since we're talking in some cases about 
> > hardware that's almost 20 years old, we're not realistically going to 
> > get those old machines fixed.
> 
> I don't understand why you keep talking about the old vendor interfaces,
> at least for the chromebook part of this thread the issue is that
> the i915 driver no longer registers the intel_backlight device which
> is a native device type, which is caused by the patch this email
> thread is about (and old vendor interfaces do not come into play
> at all here). So AFAICT this is a native vs acpi backlight control
> issue ?

I'm referring to your proposed patch that changed the default from 
backlight_vendor to backlight_native, which would fix my machine and 
Chromebooks but break anything that relies on the vendor interfaces.

> I really want to resolve your bug, but I still lack a lot of info,
> like what backlight interface you were actually using in 6.0 ?

Native.

> {
>  .callback = video_detect_force_video,
>  /* ThinkPad X201s */
>  .matches = {
> DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
> DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X201s"),
> },
> },
> 
> will trigger.

In this case you'd break anyone else running the system who isn't using 
the hacked EC and different ACPI tables - obviously there's ways round 
this, but realistically since I'm (as far as I know) the only person in 
this situation it makes more sense for me to add a kernel parameter than 
carry around an exceedingly niche DMI quirk. I'm fine with that. But the 
point I'm trying to make is that the machines *are* telling you whether 
they'd prefer vendor or native, and you're not taking that into account 
in the video_detect code.

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/userptr: restore probe_range behaviour (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/userptr: restore probe_range behaviour (rev2)
URL   : https://patchwork.freedesktop.org/series/110083/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12296_full -> Patchwork_110083v2_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110083v2_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-rkl}:NOTRUN -> [WARN][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v2/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html

  * igt@sysfs_timeslice_duration@idempotent@vcs0:
- {shard-dg1}:NOTRUN -> [FAIL][2] +9 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v2/shard-dg1-16/igt@sysfs_timeslice_duration@idempot...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_110083v2_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_mm@all:
- shard-iclb: NOTRUN -> [SKIP][3] ([i915#6433])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v2/shard-iclb6/igt@drm...@all.html

  * igt@feature_discovery@display-3x:
- shard-iclb: NOTRUN -> [SKIP][4] ([i915#1839])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v2/shard-iclb6/igt@feature_discov...@display-3x.html

  * igt@gem_ccs@suspend-resume:
- shard-tglb: NOTRUN -> [SKIP][5] ([i915#5325])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v2/shard-tglb7/igt@gem_...@suspend-resume.html

  * igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2410])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb6/igt@gem_ctx_persiste...@many-contexts.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v2/shard-tglb2/igt@gem_ctx_persiste...@many-contexts.html

  * igt@gem_eio@in-flight-contexts-1us:
- shard-snb:  [PASS][8] -> [FAIL][9] ([i915#4409])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-snb6/igt@gem_...@in-flight-contexts-1us.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v2/shard-snb4/igt@gem_...@in-flight-contexts-1us.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar 
issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb6/igt@gem_exec_fair@basic-p...@bcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v2/shard-tglb6/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v2/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][13] ([fdo#109283])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v2/shard-iclb6/igt@gem_exec_par...@no-vebox.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][14] -> [SKIP][15] ([i915#2190])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb1/igt@gem_huc_c...@huc-copy.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v2/shard-tglb6/igt@gem_huc_c...@huc-copy.html

  * igt@gem_pxp@create-regular-context-1:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#4270])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v2/shard-iclb6/igt@gem_...@create-regular-context-1.html

  * igt@gen7_exec_parse@load-register-reg:
- shard-iclb: NOTRUN -> [SKIP][17] ([fdo#109289])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v2/shard-iclb6/igt@gen7_exec_pa...@load-register-reg.html

  * igt@gen7_exec_parse@oacontrol-tracking:
- shard-apl:  NOTRUN -> [SKIP][18] ([fdo#109271]) +36 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v2/shard-apl2/igt@gen7_exec_pa...@oacontrol-tracking.html

  * igt@gen9_exec_parse@bb-large:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#2856])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v2/shard-iclb6/igt@gen9_exec_pa...@bb-large.html

  * igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][20] -> [FAIL][21] ([i915#3989] / [i915#454])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-iclb7/igt@i915_pm...@dc6-dpms.html
   [21]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for freezer, sched: Rewrite core freezer logic fix (rev3)

[Patchwork]

== Series Details ==

Series: freezer, sched: Rewrite core freezer logic fix (rev3)
URL   : https://patchwork.freedesktop.org/series/110173/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12298 -> Patchwork_110173v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/index.html

Participating hosts (41 -> 39)
--

  Missing(2): fi-ctg-p8600 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_110173v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#7073])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12298/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][3] -> [INCOMPLETE][4] ([i915#4785])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12298/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-cfl-8109u:   NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/fi-cfl-8109u/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][6] ([fdo#109271] / [i915#4312] / 
[i915#5594])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/fi-hsw-4770/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[FAIL][7] ([i915#7229]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12298/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-bxt-dsi: [DMESG-FAIL][9] ([i915#5334]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12298/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_pm:
- {bat-adln-1}:   [DMESG-FAIL][11] ([i915#4258]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12298/bat-adln-1/igt@i915_selftest@live@gt_pm.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/bat-adln-1/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hugepages:
- {bat-rpls-1}:   [DMESG-WARN][13] ([i915#5278]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12298/bat-rpls-1/igt@i915_selftest@l...@hugepages.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/bat-rpls-1/igt@i915_selftest@l...@hugepages.html

  * igt@i915_selftest@live@reset:
- {bat-rpls-1}:   [DMESG-FAIL][15] ([i915#4983]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12298/bat-rpls-1/igt@i915_selftest@l...@reset.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/bat-rpls-1/igt@i915_selftest@l...@reset.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-cfl-8109u:   [DMESG-WARN][17] -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12298/fi-cfl-8109u/igt@i915_susp...@basic-s3-without-i915.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v3/fi-cfl-8109u/igt@i915_susp...@basic-s3-without-i915.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7073]: https://gitlab.freedesktop.org/drm/intel/issues/7073
 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)
URL   : https://patchwork.freedesktop.org/series/109963/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109963v5_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109963v5_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@sysfs_preempt_timeout@idempotent@rcs0:
- {shard-dg1}:NOTRUN -> [FAIL][1] +4 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-dg1-15/igt@sysfs_preempt_timeout@idempot...@rcs0.html

  
Known issues


  Here are the changes found in Patchwork_109963v5_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [PASS][2] -> [TIMEOUT][3] ([i915#3063])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb5/igt@gem_...@in-flight-contexts-10ms.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-tglb6/igt@gem_...@in-flight-contexts-10ms.html

  * igt@gem_eio@in-flight-suspend:
- shard-skl:  [PASS][4] -> [INCOMPLETE][5] ([i915#7112])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@gem_...@in-flight-suspend.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl6/igt@gem_...@in-flight-suspend.html

  * igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][6] -> [SKIP][7] ([i915#4525])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb1/igt@gem_exec_balan...@parallel.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@gem_exec_balan...@parallel.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@gem_lmem_swapp...@parallel-random.html

  * igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][13] -> [FAIL][14] ([i915#3989] / [i915#454])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb5/igt@i915_pm...@dc6-dpms.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@i915_pm...@dc6-dpms.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl:  NOTRUN -> [SKIP][15] ([fdo#109271]) +43 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_big...@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_color_chamelium@ctm-limited-range:
- shard-skl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +2 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_color_chamel...@ctm-limited-range.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1:
- shard-skl:  [PASS][17] -> [INCOMPLETE][18] ([i915#6951])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl7/igt@kms_cursor_crc@cursor-susp...@pipe-b-edp-1.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl9/igt@kms_cursor_crc@cursor-susp...@pipe-b-edp-1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl:  [PASS][19] -> [FAIL][20] ([i915#79]) +1 similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html

  * 
igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#3555]) +2 similar issues
  

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/slpc: Use platform limits for min/max frequency (rev5)

[Belgaumkar, Vinay]

On 10/26/2022 12:13 PM, Belgaumkar, Vinay wrote:

Project List - Patchwork

*From:* Patchwork 
*Sent:* Tuesday, October 25, 2022 7:39 PM
*To:* Belgaumkar, Vinay 
*Cc:* intel-gfx@lists.freedesktop.org
*Subject:* ✗ Fi.CI.IGT: failure for drm/i915/slpc: Use platform limits 
for min/max frequency (rev5)


*Patch Details*

*Series:*



drm/i915/slpc: Use platform limits for min/max frequency (rev5)

*URL:*



https://patchwork.freedesktop.org/series/109632/

*State:*



failure

*Details:*



https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/index.html


  CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109632v5_full


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_109632v5_full absolutely 
need to be

verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_109632v5_full, please notify your bug team to 
allow them
to document this new failure mode, which will reduce false positives 
in CI.



Participating hosts (9 -> 11)

Additional (2): shard-rkl shard-dg1


Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_109632v5_full:



  IGT changes


Possible regressions

  * igt@gem_exec_capture@pi@vecs0:
  o shard-iclb: PASS


-> INCOMPLETE



Not related to this change as it is not a server part.

To clarify, this patch affects the guc path, ICL does not use that. So 
failure is not related to this patch.


Thanks,

Vinay.


Thanks,

Vinay.


Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  * igt@gem_create@create-clear@smem0:
  o {shard-rkl}: NOTRUN -> INCOMPLETE


  * igt@sysfs_preempt_timeout@idempotent@rcs0:
  o {shard-dg1}: NOTRUN -> FAIL


+4 similar issues


Known issues

Here are the changes found in Patchwork_109632v5_full that come from 
known issues:



  IGT changes


Issues hit

  * igt@gem_ctx_exec@basic-nohangcheck:
  o shard-tglb: PASS


-> FAIL


(i915#6268 )
  * igt@gem_exec_balancer@parallel:
  o shard-iclb: PASS


-> SKIP


(i915#4525 )
  * igt@gem_exec_fair@basic-pace-share@rcs0:
  o shard-glk: PASS


-> FAIL


(i915#2842 )
  * igt@gem_huc_copy@huc-copy:
  o shard-tglb: PASS


-> SKIP


(i915#2190 )
  * igt@gem_lmem_swapping@parallel-random:
  o shard-skl: NOTRUN -> SKIP


(fdo#109271
 /
i915#4613 )
  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
  o shard-skl: PASS


-> FAIL


(i915#2521 )
  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
  o shard-skl: NOTRUN -> 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for freezer, sched: Rewrite core freezer logic fix (rev3)

[Patchwork]

== Series Details ==

Series: freezer, sched: Rewrite core freezer logic fix (rev3)
URL   : https://patchwork.freedesktop.org/series/110173/
State : warning

== Summary ==

Error: dim checkpatch failed
c9af43324598 freezer, sched: Rewrite core freezer logic fix
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#12: 
> <4>[  355.438418]  #0: 88844693b758 (>__lock){-.-.}-{2:2}, at: 
> raw_spin_rq_lock_nested+0x1b/0x30

-:112: WARNING:MEMORY_BARRIER: memory barrier without comment
#112: FILE: kernel/sched/core.c:4226:
+   smp_rmb();

-:152: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 2 warnings, 0 checks, 66 lines checked

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Revert "drm/i915/uapi: expose GTT alignment"

[Vudum, Lakshminarayana]

Filed a new issue and re-reported.
https://gitlab.freedesktop.org/drm/intel/-/issues/7323
igt@i915_selftest@mock@requests - incomplete - GEM_BUG_ON(ce->timeline->seqno 
!= ({ do { __attribute__((__noreturn__)) extern void __compiletime_assert, 
kernel BUG at drivers/gpu/drm/i915/gt/intel_engine_pm.c:72!

Lakshmi.

-Original Message-
From: Auld, Matthew  
Sent: Wednesday, October 26, 2022 11:01 AM
To: Vudum, Lakshminarayana ; 
intel-gfx@lists.freedesktop.org
Subject: Re: ✗ Fi.CI.IGT: failure for Revert "drm/i915/uapi: expose GTT 
alignment"

On 26/10/2022 18:53, Vudum, Lakshminarayana wrote:
> @Auld, Matthew Can you check if this is related to your patch? Looks new to 
> me.
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-skl9/igt@i915_selftest@m...@requests.html#dmesg-warnings16

For sure unrelated to this series.

> 
> Lakshmi.
> -Original Message-
> From: Auld, Matthew 
> Sent: Wednesday, October 26, 2022 1:53 AM
> To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 
> 
> Subject: Re: ✗ Fi.CI.IGT: failure for Revert "drm/i915/uapi: expose GTT 
> alignment"
> 
> On 26/10/2022 08:47, Patchwork wrote:
>> *Patch Details*
>> *Series:*Revert "drm/i915/uapi: expose GTT alignment"
>> *URL:*   https://patchwork.freedesktop.org/series/110041/
>> 
>> *State:* failure
>> *Details:*
>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html
>> 
>>
>>
>>CI Bug Log - changes from CI_DRM_12284_full -> Patchwork_110041v1_full
>>
>>
>>  Summary
>>
>> *FAILURE*
>>
>> Serious unknown changes coming with Patchwork_110041v1_full absolutely
>> need to be
>> verified manually.
>>
>> If you think the reported changes have nothing to do with the changes
>> introduced in Patchwork_110041v1_full, please notify your bug team to
>> allow them
>> to document this new failure mode, which will reduce false positives in CI.
>>
>>
>>  Participating hosts (11 -> 11)
>>
>> No changes in participating hosts
>>
>>
>>  Possible new issues
>>
>> Here are the unknown changes that may have been introduced in
>> Patchwork_110041v1_full:
>>
>>
>>IGT changes
>>
>>
>>  Possible regressions
>>
>>*
>>
>>  igt@i915_pm_rpm@drm-resources-equal:
>>
>>o shard-iclb: PASS
>>  
>> 
>>  -> FAIL 
>> 
>>*
>>
>>  igt@i915_selftest@live@guc_hang:
>>
>>o shard-skl: PASS
>>  
>> 
>>  -> INCOMPLETE 
>> 
>>*
>>
>>  igt@i915_suspend@forcewake:
>>
>>o shard-skl: NOTRUN -> INCOMPLETE
>>  
>> 
>>  +1 similar issue
>>
>>
> 
> 
> All look to be unrelated.
> 
>>  Warnings
>>
>>*
>>
>>  igt@kms_color@ctm-0-75@pipe-d-edp-1:
>>
>>o shard-tglb: FAIL
>>  
>> 
>>  (i915#315  / i915#6946 
>> ) -> INCOMPLETE 
>> 
>>*
>>
>>  igt@kms_cursor_legacy@flip-vs-cursor@atomic:
>>
>>o shard-skl: FAIL
>>  
>> 
>>  (i915#2346 ) -> 
>> INCOMPLETE 
>> 
>>
>>
>>  Suppressed
>>
>> The following results come from untrusted machines, tests, or statuses.
>> They do not affect the overall result.
>>
>>*
>>
>>  igt@gem_mmap_offset@clear@smem0:
>>
>>o {shard-rkl}: PASS
>>  
>> 
>>  -> INCOMPLETE 
>> 
>>*
>>
>>  igt@i915_pm_rc6_residency@rc6-idle@vcs0:
>>
>>o {shard-rkl}: PASS
>>  
>> 
>>  -> WARN 
>> 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/slpc: Use platform limits for min/max frequency (rev5)

[Belgaumkar, Vinay]

From: Patchwork 
Sent: Tuesday, October 25, 2022 7:39 PM
To: Belgaumkar, Vinay 
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for drm/i915/slpc: Use platform limits for 
min/max frequency (rev5)

Patch Details
Series:
drm/i915/slpc: Use platform limits for min/max frequency (rev5)
URL:
https://patchwork.freedesktop.org/series/109632/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/index.html
CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109632v5_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_109632v5_full absolutely need to 
be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_109632v5_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Participating hosts (9 -> 11)

Additional (2): shard-rkl shard-dg1

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_109632v5_full:

IGT changes
Possible regressions

  *   igt@gem_exec_capture@pi@vecs0:
 *   shard-iclb: 
PASS
 -> 
INCOMPLETE
Not related to this change as it is not a server part.
Thanks,
Vinay.
Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  *   igt@gem_create@create-clear@smem0:
 *   {shard-rkl}: NOTRUN -> 
INCOMPLETE
  *   igt@sysfs_preempt_timeout@idempotent@rcs0:
 *   {shard-dg1}: NOTRUN -> 
FAIL
 +4 similar issues

Known issues

Here are the changes found in Patchwork_109632v5_full that come from known 
issues:

IGT changes
Issues hit

  *   igt@gem_ctx_exec@basic-nohangcheck:
 *   shard-tglb: 
PASS
 -> 
FAIL
 (i915#6268)
  *   igt@gem_exec_balancer@parallel:
 *   shard-iclb: 
PASS
 -> 
SKIP
 (i915#4525)
  *   igt@gem_exec_fair@basic-pace-share@rcs0:
 *   shard-glk: 
PASS
 -> 
FAIL
 (i915#2842)
  *   igt@gem_huc_copy@huc-copy:
 *   shard-tglb: 
PASS
 -> 
SKIP
 (i915#2190)
  *   igt@gem_lmem_swapping@parallel-random:
 *   shard-skl: NOTRUN -> 
SKIP
 (fdo#109271 / 
i915#4613)
  *   igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
 *   shard-skl: 
PASS
 -> 
FAIL
 (i915#2521)
  *   igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
 *   shard-skl: NOTRUN -> 
SKIP
 (fdo#109271) +44 similar 
issues
  *   igt@kms_big_fb@y-tiled-32bpp-rotate-180:
 *   shard-glk: 
PASS
 -> 
DMESG-FAIL
 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)
URL   : https://patchwork.freedesktop.org/series/109963/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109963v5_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_109963v5_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109963v5_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109963v5_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1:
- shard-skl:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl7/igt@kms_cursor_crc@cursor-susp...@pipe-b-edp-1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl9/igt@kms_cursor_crc@cursor-susp...@pipe-b-edp-1.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@sysfs_preempt_timeout@idempotent@rcs0:
- {shard-dg1}:NOTRUN -> [FAIL][3] +4 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-dg1-15/igt@sysfs_preempt_timeout@idempot...@rcs0.html

  
Known issues


  Here are the changes found in Patchwork_109963v5_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb5/igt@gem_...@in-flight-contexts-10ms.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-tglb6/igt@gem_...@in-flight-contexts-10ms.html

  * igt@gem_eio@in-flight-suspend:
- shard-skl:  [PASS][6] -> [INCOMPLETE][7] ([i915#7112])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@gem_...@in-flight-suspend.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl6/igt@gem_...@in-flight-suspend.html

  * igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb1/igt@gem_exec_balan...@parallel.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@gem_exec_balan...@parallel.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl:  [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@gem_lmem_swapp...@parallel-random.html

  * igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][15] -> [FAIL][16] ([i915#3989] / [i915#454])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb5/igt@i915_pm...@dc6-dpms.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@i915_pm...@dc6-dpms.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl:  NOTRUN -> [SKIP][17] ([fdo#109271]) +43 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_big...@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_color_chamelium@ctm-limited-range:
- shard-skl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +2 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_color_chamel...@ctm-limited-range.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl:  [PASS][19] -> [FAIL][20] ([i915#79]) +1 similar issue
   [19]: 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Add DG2 OA support (rev10)

[Umesh Nerlige Ramappa]

On Wed, Oct 26, 2022 at 02:33:50PM +, Patchwork wrote:

  Patch Details

Series:  Add DG2 OA support (rev10)
URL: [1]https://patchwork.freedesktop.org/series/107584/
State:   failure
Details: 
[2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/index.html

   CI Bug Log - changes from CI_DRM_12294_full -> Patchwork_107584v10_full

Summary

  FAILURE

  Serious unknown changes coming with Patchwork_107584v10_full absolutely
  need to be
  verified manually.

  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_107584v10_full, please notify your bug team to
  allow them
  to document this new failure mode, which will reduce false positives in
  CI.

Participating hosts (11 -> 11)

  No changes in participating hosts

Possible new issues

  Here are the unknown changes that may have been introduced in
  Patchwork_107584v10_full:

 IGT changes

   Possible regressions

* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-edp-1:

 * shard-skl: [3]PASS -> [4]FAIL


unrelated to this series.



* igt@perf@global-sseu-config:

 * shard-tglb: [5]PASS -> [6]SKIP

   Suppressed

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

* igt@perf@global-sseu-config:

 * {shard-rkl}: NOTRUN -> [7]SKIP

 * {shard-dg1}: [8]PASS -> [9]SKIP


global-sseu-config is supposed to skip for all non-gen11 platforms.

Thanks
Umesh

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Delay disabling GuC scheduling of an idle context (rev2)

[Teres Alexis, Alan Previn]

I verified that 2 of the 3 the errors reported below are on platforms that 
don't support GuC and the dmesgs confirm guc was disabled.
The remaining ICL one, we know ICL doesnt support GuC .. also, additionally, 
the error was on a display IGT where CRCs were failing.
That said these errors I believe are unrelated.
...alan


On Wed, 2022-10-26 at 18:02 +, Patchwork wrote:
Patch Details
Series: Delay disabling GuC scheduling of an idle context (rev2)
URL:https://patchwork.freedesktop.org/series/109466/
State:  failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/index.html
CI Bug Log - changes from CI_DRM_12295_full -> Patchwork_109466v2_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_109466v2_full absolutely need to 
be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_109466v2_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Participating hosts (9 -> 11)

Additional (2): shard-rkl shard-dg1

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_109466v2_full:

IGT changes
Possible regressions

  *   igt@i915_selftest@live@hangcheck:

 *   shard-skl: NOTRUN -> 
INCOMPLETE
 +1 similar issue
  *   igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:

 *   shard-skl: 
PASS
 -> 
INCOMPLETE
  *   igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:

 *   shard-iclb: 
PASS
 -> 
FAIL

Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  *   igt@sysfs_preempt_timeout@idempotent@rcs0:
 *   {shard-dg1}: NOTRUN -> 
FAIL
 +4 similar issues

Known issues

Re: [Intel-gfx] [PATCH v5 09/19] drm/i915/vm_bind: Add out fence support

[Niranjana Vishwanathapura]

On Wed, Oct 26, 2022 at 06:15:09PM +0100, Matthew Auld wrote:

On 25/10/2022 07:58, Niranjana Vishwanathapura wrote:

Add support for handling out fence for vm_bind call.

v2: Reset vma->vm_bind_fence.syncobj to NULL at the end
of vm_bind call.
v3: Remove vm_unbind out fence uapi which is not supported yet.
v4: Return error if I915_TIMELINE_FENCE_WAIT fence flag is set.
Wait for bind to complete iff I915_TIMELINE_FENCE_SIGNAL is
not specified.

Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h   |  4 +
 .../drm/i915/gem/i915_gem_vm_bind_object.c| 93 +++
 drivers/gpu/drm/i915/i915_vma.c   |  7 +-
 drivers/gpu/drm/i915/i915_vma_types.h |  7 ++
 include/uapi/drm/i915_drm.h   | 49 +-
 5 files changed, 157 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
index 36262a6357b5..b70e900e35ab 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
@@ -8,6 +8,7 @@
 #include 
+struct dma_fence;
 struct drm_device;
 struct drm_file;
 struct i915_address_space;
@@ -23,4 +24,7 @@ int i915_gem_vm_unbind_ioctl(struct drm_device *dev, void 
*data,
 void i915_gem_vm_unbind_all(struct i915_address_space *vm);
+void i915_vm_bind_signal_fence(struct i915_vma *vma,
+  struct dma_fence * const fence);
+
 #endif /* __I915_GEM_VM_BIND_H */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
index 863bd17c9253..fca6d6eb9ef8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
@@ -7,6 +7,8 @@
 #include 
+#include 
+
 #include "gem/i915_gem_context.h"
 #include "gem/i915_gem_vm_bind.h"
@@ -100,6 +102,76 @@ static void i915_gem_vm_bind_remove(struct i915_vma *vma, 
bool release_obj)
i915_gem_object_put(vma->obj);
 }
+static int i915_vm_bind_add_fence(struct drm_file *file, struct i915_vma *vma,
+ u32 handle, u64 point)
+{
+   struct drm_syncobj *syncobj;
+
+   syncobj = drm_syncobj_find(file, handle);
+   if (!syncobj) {
+   DRM_DEBUG("Invalid syncobj handle provided\n");


AFAIK drm_dbg() is preferred, if possible.


ok, will fix.




+   return -ENOENT;
+   }
+
+   /*
+* For timeline syncobjs we need to preallocate chains for
+* later signaling.
+*/
+   if (point) {
+   vma->vm_bind_fence.chain_fence = dma_fence_chain_alloc();
+   if (!vma->vm_bind_fence.chain_fence) {
+   drm_syncobj_put(syncobj);
+   return -ENOMEM;
+   }
+   } else {
+   vma->vm_bind_fence.chain_fence = NULL;
+   }
+   vma->vm_bind_fence.syncobj = syncobj;
+   vma->vm_bind_fence.value = point;
+
+   return 0;
+}
+
+static void i915_vm_bind_put_fence(struct i915_vma *vma)
+{
+   if (!vma->vm_bind_fence.syncobj)
+   return;
+
+   drm_syncobj_put(vma->vm_bind_fence.syncobj);
+   dma_fence_chain_free(vma->vm_bind_fence.chain_fence);
+   vma->vm_bind_fence.syncobj = NULL;
+}
+
+/**
+ * i915_vm_bind_signal_fence() - Add fence to vm_bind syncobj
+ * @vma: vma mapping requiring signaling
+ * @fence: fence to be added
+ *
+ * Associate specified @fence with the @vma's syncobj to be
+ * signaled after the @fence work completes.
+ */
+void i915_vm_bind_signal_fence(struct i915_vma *vma,
+  struct dma_fence * const fence)
+{
+   struct drm_syncobj *syncobj = vma->vm_bind_fence.syncobj;
+
+   if (!syncobj)
+   return;
+
+   if (vma->vm_bind_fence.chain_fence) {
+   drm_syncobj_add_point(syncobj,
+ vma->vm_bind_fence.chain_fence,
+ fence, vma->vm_bind_fence.value);
+   /*
+* The chain's ownership is transferred to the
+* timeline.
+*/
+   vma->vm_bind_fence.chain_fence = NULL;
+   } else {
+   drm_syncobj_replace_fence(syncobj, fence);
+   }
+}
+
 static int i915_gem_vm_unbind_vma(struct i915_address_space *vm,
  struct drm_i915_gem_vm_unbind *va)
 {
@@ -205,6 +277,10 @@ static int i915_gem_vm_bind_obj(struct i915_address_space 
*vm,
if (!va->length || !IS_ALIGNED(va->start, I915_GTT_PAGE_SIZE))
ret = -EINVAL;
+   /* In fences are not supported */
+   if (va->fence.flags & I915_TIMELINE_FENCE_WAIT)
+   ret = -EINVAL;


I guess also:

if (flags & __I915_TIMELINE_FENCE_UNKNOWN_FLAGS)



ok, will add


Reviewed-by: Matthew Auld 



Thanks,
Niranjana


+
obj = i915_gem_object_lookup(file, 

[Intel-gfx] ✓ Fi.CI.IGT: success for Revert "drm/i915/uapi: expose GTT alignment"

[Patchwork]

== Series Details ==

Series: Revert "drm/i915/uapi: expose GTT alignment"
URL   : https://patchwork.freedesktop.org/series/110041/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12284_full -> Patchwork_110041v1_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_110041v1_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110041v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110041v1_full:

### IGT changes ###

 Warnings 

  * igt@kms_color@ctm-0-75@pipe-d-edp-1:
- shard-tglb: [FAIL][1] ([i915#315] / [i915#6946]) -> 
[INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-tglb6/igt@kms_color@ctm-0...@pipe-d-edp-1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-tglb8/igt@kms_color@ctm-0...@pipe-d-edp-1.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic:
- shard-skl:  [FAIL][3] ([i915#2346]) -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-skl6/igt@kms_cursor_legacy@flip-vs-cur...@atomic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-skl9/igt@kms_cursor_legacy@flip-vs-cur...@atomic.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_mmap_offset@clear@smem0:
- {shard-rkl}:[PASS][5] -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-rkl-4/igt@gem_mmap_offset@cl...@smem0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-rkl-5/igt@gem_mmap_offset@cl...@smem0.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-rkl}:[PASS][7] -> [WARN][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-rkl-4/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html

  * igt@i915_pm_rc6_residency@rc6-idle@vecs0:
- {shard-rkl}:[PASS][9] -> [FAIL][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-rkl-4/igt@i915_pm_rc6_residency@rc6-i...@vecs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-i...@vecs0.html

  
Known issues


  Here are the changes found in Patchwork_110041v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-glk:  ([PASS][11], [PASS][12], [PASS][13], [PASS][14], 
[PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], 
[PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], 
[PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], 
[PASS][33], [PASS][34], [PASS][35]) -> ([PASS][36], [PASS][37], [PASS][38], 
[PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], 
[PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], 
[PASS][51], [PASS][52], [PASS][53], [FAIL][54], [PASS][55], [PASS][56], 
[PASS][57], [PASS][58], [PASS][59], [PASS][60]) ([i915#4392])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk9/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk9/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk9/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk8/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk8/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk8/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk7/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk7/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk7/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk6/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk6/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk6/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk5/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk5/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk5/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk3/boot.html
   

[Intel-gfx] ✗ Fi.CI.IGT: failure for Fix Guc-Err-Capture sizing warning

[Patchwork]

== Series Details ==

Series: Fix Guc-Err-Capture sizing warning
URL   : https://patchwork.freedesktop.org/series/110155/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12295_full -> Patchwork_110155v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110155v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110155v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110155v1_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@execlists:
- shard-skl:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110155v1/shard-skl5/igt@i915_selftest@l...@execlists.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][2] -> [FAIL][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-iclb6/igt@kms_frontbuffer_track...@psr-1p-primscrn-cur-indfb-draw-render.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110155v1/shard-iclb1/igt@kms_frontbuffer_track...@psr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_sequence@queue-idle@edp-1-pipe-a:
- shard-skl:  NOTRUN -> [FAIL][4]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110155v1/shard-skl2/igt@kms_sequence@queue-i...@edp-1-pipe-a.html

  * igt@syncobj_timeline@wait-all-for-submit-snapshot:
- shard-skl:  [PASS][5] -> [FAIL][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-skl2/igt@syncobj_timel...@wait-all-for-submit-snapshot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110155v1/shard-skl1/igt@syncobj_timel...@wait-all-for-submit-snapshot.html

  
 Warnings 

  * igt@runner@aborted:
- shard-skl:  ([FAIL][7], [FAIL][8], [FAIL][9]) ([i915#3002] / 
[i915#4312] / [i915#6949]) -> ([FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13], 
[FAIL][14], [FAIL][15], [FAIL][16]) ([i915#3002] / [i915#4312])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-skl4/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-skl10/igt@run...@aborted.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-skl7/igt@run...@aborted.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110155v1/shard-skl9/igt@run...@aborted.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110155v1/shard-skl2/igt@run...@aborted.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110155v1/shard-skl2/igt@run...@aborted.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110155v1/shard-skl3/igt@run...@aborted.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110155v1/shard-skl5/igt@run...@aborted.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110155v1/shard-skl3/igt@run...@aborted.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110155v1/shard-skl6/igt@run...@aborted.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-rkl}:NOTRUN -> [WARN][17]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110155v1/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html

  * igt@perf@polling-parameterized:
- {shard-rkl}:NOTRUN -> [INCOMPLETE][18]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110155v1/shard-rkl-3/igt@p...@polling-parameterized.html

  * igt@sysfs_timeslice_duration@idempotent@vcs0:
- {shard-dg1}:NOTRUN -> [FAIL][19] +9 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110155v1/shard-dg1-16/igt@sysfs_timeslice_duration@idempot...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_110155v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-apl:  ([PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44]) -> ([PASS][45], [PASS][46], [PASS][47], 
[PASS][48], [PASS][49], [FAIL][50], [PASS][51], [PASS][52], [PASS][53], 
[PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], 
[PASS][60], [PASS][61], 

Re: [Intel-gfx] [PATCH v4 1/1] drm/i915/guc: Fix GuC error capture sizing estimation and reporting

[John Harrison]

On 10/25/2022 23:05, Alan Previn wrote:

During GuC error capture initialization, we estimate the amount of size
we need for the error-capture-region of the shared GuC-log-buffer.
This calculation was incorrect so fix that. With the fixed calculation
we can reduce the allocation of error-capture region from 4MB to 1MB
(see note2 below for reasoning). Additionally, switch from drm_notice to
drm_debug for the 3X spare size check since that would be impossible to
hit without redesigning gpu_coredump framework to hold multiple captures.

NOTE1: Even for 1x the min size estimation case, actually running out
of space is a corner case because it can only occur if all engine
instances get reset all at once and i915 isn't able extract the capture
data fast enough within G2H handler worker.

NOTE2: With the corrected calculation, a DG2 part required ~77K and a PVC
required ~115K (1X min-est-size that is calculated as one-shot all-engine-
reset scenario).

Fixes d7c15d76a5547: drm/i915/guc: Check sizing of guc_capture output

Signed-off-by: Alan Previn 
The fixes tag is not correct. You should use 'dim fixes ' to create 
it automatically (it also adds a whole bunch of CC tags). I can fix that 
when merging, though.


Reviewed-by: John Harrison 


---
  .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 29 ---
  drivers/gpu/drm/i915/gt/uc/intel_guc_log.c|  6 ++--
  2 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index c4bee3bc15a9..4e6dca707d94 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -559,8 +559,9 @@ guc_capture_getlistsize(struct intel_guc *guc, u32 owner, 
u32 type, u32 classid,
if (!num_regs)
return -ENODATA;
  
-	*size = PAGE_ALIGN((sizeof(struct guc_debug_capture_list)) +

-  (num_regs * sizeof(struct guc_mmio_reg)));
+   if (size)
+   *size = PAGE_ALIGN((sizeof(struct guc_debug_capture_list)) +
+  (num_regs * sizeof(struct guc_mmio_reg)));
  
  	return 0;

  }
@@ -670,7 +671,7 @@ guc_capture_output_min_size_est(struct intel_guc *guc)
struct intel_gt *gt = guc_to_gt(guc);
struct intel_engine_cs *engine;
enum intel_engine_id id;
-   int worst_min_size = 0, num_regs = 0;
+   int worst_min_size = 0;
size_t tmp = 0;
  
  	if (!guc->capture)

@@ -692,20 +693,18 @@ guc_capture_output_min_size_est(struct intel_guc *guc)
 (3 * sizeof(struct 
guc_state_capture_header_t));
  
  		if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, , true))

-   num_regs += tmp;
+   worst_min_size += tmp;
  
  		if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS,

 engine->class, , true)) {
-   num_regs += tmp;
+   worst_min_size += tmp;
}
if (!guc_capture_getlistsize(guc, 0, 
GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE,
 engine->class, , true)) {
-   num_regs += tmp;
+   worst_min_size += tmp;
}
}
  
-	worst_min_size += (num_regs * sizeof(struct guc_mmio_reg));

-
return worst_min_size;
  }
  
@@ -722,15 +721,23 @@ static void check_guc_capture_size(struct intel_guc *guc)

int spare_size = min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER;
u32 buffer_size = intel_guc_log_section_size_capture(>log);
  
+	/*

+* NOTE: min_size is much smaller than the capture region allocation (DG2: 
<80K vs 1MB)
+* Additionally, its based on space needed to fit all engines getting 
reset at once
+* within the same G2H handler task slot. This is very unlikely. 
However, if GuC really
+* does run out of space for whatever reason, we will see an separate 
warning message
+* when processing the G2H event capture-notification, search for:
+* INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE.
+*/
if (min_size < 0)
drm_warn(>drm, "Failed to calculate GuC error state capture 
buffer minimum size: %d!\n",
 min_size);
else if (min_size > buffer_size)
-   drm_warn(>drm, "GuC error state capture buffer is too small: %d 
< %d\n",
+   drm_warn(>drm, "GuC error state capture buffer maybe small: %d 
< %d\n",
 buffer_size, min_size);
else if (spare_size > buffer_size)
-   drm_notice(>drm, "GuC error state capture buffer maybe too small: 
%d < %d (min = %d)\n",
-  buffer_size, spare_size, min_size);
+   drm_dbg(>drm, "GuC error state capture buffer lacks spare size: 
%d < %d (min 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Audio stuff

[Patchwork]

== Series Details ==

Series: drm/i915: Audio stuff
URL   : https://patchwork.freedesktop.org/series/110188/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12297 -> Patchwork_110188v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110188v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110188v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v1/index.html

Participating hosts (40 -> 39)
--

  Additional (2): fi-bdw-gvtdvm fi-bxt-dsi 
  Missing(3): fi-ctg-p8600 fi-hsw-4770 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110188v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-bdw-gvtdvm:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v1/fi-bdw-gvtdvm/igt@i915_susp...@basic-s2idle-without-i915.html

  
 Warnings 

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [INCOMPLETE][2] ([i915#4817]) -> [INCOMPLETE][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12297/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  
Known issues


  Here are the changes found in Patchwork_110188v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-bxt-dsi: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v1/fi-bxt-dsi/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html
- fi-bdw-gvtdvm:  NOTRUN -> [SKIP][6] ([fdo#109271]) +37 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v1/fi-bdw-gvtdvm/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-bxt-dsi: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v1/fi-bxt-dsi/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_tiled_blits@basic:
- fi-bxt-dsi: NOTRUN -> [SKIP][8] ([fdo#109271]) +12 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v1/fi-bxt-dsi/igt@gem_tiled_bl...@basic.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-7567u:   [PASS][9] -> [DMESG-FAIL][10] ([i915#5334])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12297/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v1/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v1/fi-apl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
- fi-bxt-dsi: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v1/fi-bxt-dsi/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-bdw-gvtdvm:  NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v1/fi-bdw-gvtdvm/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-apl-guc: NOTRUN -> [SKIP][14] ([fdo#109271]) +11 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v1/fi-apl-guc/igt@kms_psr@sprite_plane_onoff.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][15] ([i915#2867]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12297/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110188v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [INCOMPLETE][17] ([i915#7056]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12297/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [18]: 

[Intel-gfx] ✗ Fi.CI.IGT: failure for Delay disabling GuC scheduling of an idle context (rev2)

[Patchwork]

== Series Details ==

Series: Delay disabling GuC scheduling of an idle context (rev2)
URL   : https://patchwork.freedesktop.org/series/109466/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12295_full -> Patchwork_109466v2_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_109466v2_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109466v2_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109466v2_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@hangcheck:
- shard-skl:  NOTRUN -> [INCOMPLETE][1] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/shard-skl7/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:
- shard-skl:  [PASS][2] -> [INCOMPLETE][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-skl1/igt@kms_flip@flip-vs-suspend-interrupti...@c-edp1.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/shard-skl3/igt@kms_flip@flip-vs-suspend-interrupti...@c-edp1.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][4] -> [FAIL][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-iclb6/igt@kms_frontbuffer_track...@psr-1p-primscrn-cur-indfb-draw-render.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/shard-iclb1/igt@kms_frontbuffer_track...@psr-1p-primscrn-cur-indfb-draw-render.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@sysfs_preempt_timeout@idempotent@rcs0:
- {shard-dg1}:NOTRUN -> [FAIL][6] +4 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/shard-dg1-18/igt@sysfs_preempt_timeout@idempot...@rcs0.html

  
Known issues


  Here are the changes found in Patchwork_109466v2_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-glk:  ([PASS][7], [PASS][8], [PASS][9], [PASS][10], 
[PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], 
[PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], 
[PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], 
[PASS][29], [PASS][30], [PASS][31]) -> ([PASS][32], [PASS][33], [PASS][34], 
[PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], 
[PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], 
[PASS][47], [PASS][48], [PASS][49], [FAIL][50], [PASS][51], [PASS][52], 
[PASS][53], [PASS][54], [PASS][55]) ([i915#4392])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk2/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk9/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk9/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk9/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk9/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk8/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk8/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk8/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk7/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk7/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk7/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk6/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk6/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk6/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk5/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk5/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk5/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk3/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk3/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk3/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk2/boot.html
   [28]: 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Revert "drm/i915/uapi: expose GTT alignment"

[Matthew Auld]

On 26/10/2022 18:53, Vudum, Lakshminarayana wrote:

@Auld, Matthew Can you check if this is related to your patch? Looks new to me.
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-skl9/igt@i915_selftest@m...@requests.html#dmesg-warnings16


For sure unrelated to this series.



Lakshmi.
-Original Message-
From: Auld, Matthew 
Sent: Wednesday, October 26, 2022 1:53 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Subject: Re: ✗ Fi.CI.IGT: failure for Revert "drm/i915/uapi: expose GTT 
alignment"

On 26/10/2022 08:47, Patchwork wrote:

*Patch Details*
*Series:*   Revert "drm/i915/uapi: expose GTT alignment"
*URL:*  https://patchwork.freedesktop.org/series/110041/

*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html



   CI Bug Log - changes from CI_DRM_12284_full -> Patchwork_110041v1_full


 Summary

*FAILURE*

Serious unknown changes coming with Patchwork_110041v1_full absolutely
need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_110041v1_full, please notify your bug team to
allow them
to document this new failure mode, which will reduce false positives in CI.


 Participating hosts (11 -> 11)

No changes in participating hosts


 Possible new issues

Here are the unknown changes that may have been introduced in
Patchwork_110041v1_full:


   IGT changes


 Possible regressions

   *

 igt@i915_pm_rpm@drm-resources-equal:

   o shard-iclb: PASS
 

 -> FAIL 

   *

 igt@i915_selftest@live@guc_hang:

   o shard-skl: PASS
 

 -> INCOMPLETE 

   *

 igt@i915_suspend@forcewake:

   o shard-skl: NOTRUN -> INCOMPLETE
 

 +1 similar issue





All look to be unrelated.


 Warnings

   *

 igt@kms_color@ctm-0-75@pipe-d-edp-1:

   o shard-tglb: FAIL
 

 (i915#315  / i915#6946 
) -> INCOMPLETE 

   *

 igt@kms_cursor_legacy@flip-vs-cursor@atomic:

   o shard-skl: FAIL
 

 (i915#2346 ) -> INCOMPLETE 



 Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

   *

 igt@gem_mmap_offset@clear@smem0:

   o {shard-rkl}: PASS
 

 -> INCOMPLETE 

   *

 igt@i915_pm_rc6_residency@rc6-idle@vcs0:

   o {shard-rkl}: PASS
 

 -> WARN 

   *

 igt@i915_pm_rc6_residency@rc6-idle@vecs0:

   o {shard-rkl}: PASS
 

 -> FAIL 



 Known issues

Here are the changes found in Patchwork_110041v1_full that come from
known issues:


   CI changes


 Issues hit

   * boot:
   o shard-glk: (PASS
 , PASS , PASS , PASS 

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/xelp: Add Wa_1806527549 (rev2)

[Matt Roper]

On Wed, Oct 26, 2022 at 06:04:08AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/xelp: Add Wa_1806527549 (rev2)
> URL   : https://patchwork.freedesktop.org/series/109885/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_12261_full -> Patchwork_109885v2_full
> 
> 
> Summary
> ---
> 
>   **SUCCESS**
> 
>   No regressions found.

Applied to drm-intel-gt-next.  Thanks for the patch and review.


Matt

> 
>   
> 
> Participating hosts (9 -> 12)
> --
> 
>   Additional (3): shard-rkl shard-dg1 shard-tglu 
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_109885v2_full:
> 
> ### IGT changes ###
> 
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * igt@gem_pwrite@basic-exhaustion:
> - {shard-rkl}:NOTRUN -> [INCOMPLETE][1]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-rkl-5/igt@gem_pwr...@basic-exhaustion.html
> 
>   * igt@kms_big_fb@linear-64bpp-rotate-0:
> - {shard-dg1}:NOTRUN -> [FAIL][2]
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-dg1-13/igt@kms_big...@linear-64bpp-rotate-0.html
> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_109885v2_full that come from known 
> issues:
> 
> ### CI changes ###
> 
>  Issues hit 
> 
>   * boot:
> - shard-glk:  ([PASS][3], [PASS][4], [PASS][5], [PASS][6], 
> [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
> [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
> [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
> [PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], 
> [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
> [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
> [PASS][43], [FAIL][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], 
> [PASS][49], [PASS][50], [PASS][51], [PASS][52]) ([i915#4392])
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk3/boot.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk9/boot.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk9/boot.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk9/boot.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk9/boot.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk8/boot.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk8/boot.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk8/boot.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk7/boot.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk7/boot.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk6/boot.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk6/boot.html
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk6/boot.html
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk5/boot.html
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk5/boot.html
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk1/boot.html
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk1/boot.html
>[20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk1/boot.html
>[21]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk2/boot.html
>[22]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk2/boot.html
>[23]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk5/boot.html
>[24]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk3/boot.html
>[25]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk3/boot.html
>[26]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk2/boot.html
>[27]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk2/boot.html
>[28]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-glk9/boot.html
>[29]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-glk9/boot.html
>[30]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-glk8/boot.html
>[31]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-glk8/boot.html
>[32]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-glk8/boot.html
>[33]: 
> 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/4] drm/i915/display: Change terminology for cdclk actions

[Srivatsa, Anusha]

From: Patchwork 
Sent: Wednesday, October 26, 2022 10:07 AM
To: Srivatsa, Anusha 
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for series starting with [CI,1/4] 
drm/i915/display: Change terminology for cdclk actions

Patch Details
Series:
series starting with [CI,1/4] drm/i915/display: Change terminology for cdclk 
actions
URL:
https://patchwork.freedesktop.org/series/110145/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110145v1/index.html
CI Bug Log - changes from CI_DRM_12295_full -> Patchwork_110145v1_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_110145v1_full absolutely need to 
be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_110145v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Participating hosts (9 -> 11)

Additional (2): shard-rkl shard-dg1

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_110145v1_full:

IGT changes
Possible regressions

  *   igt@i915_pm_rpm@system-suspend-execbuf:

 *   shard-iclb: 
PASS
 -> 
FAIL

  *   igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-edp-1:

 *   shard-skl: 
PASS
 -> 
FAIL

Checked the igt-runner and dmesg logs for both the above failures. It shows all 
129/129 tests to be passing. Dmesg looks clean as well.

Anusha
Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  *   igt@sysfs_timeslice_duration@idempotent@vcs0:

 *   {shard-dg1}: NOTRUN -> 
FAIL
 +9 similar issues

Known issues

Here are the changes found in Patchwork_110145v1_full that come from known 
issues:

CI changes
Issues hit

  *   boot:

 *   shard-glk: 
(PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS)
 -> 
(PASS,
 
PASS,
 
PASS,
 
PASS,
 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Revert "drm/i915/uapi: expose GTT alignment"

[Vudum, Lakshminarayana]

@Auld, Matthew Can you check if this is related to your patch? Looks new to me.
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-skl9/igt@i915_selftest@m...@requests.html#dmesg-warnings16

Lakshmi.
-Original Message-
From: Auld, Matthew  
Sent: Wednesday, October 26, 2022 1:53 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Subject: Re: ✗ Fi.CI.IGT: failure for Revert "drm/i915/uapi: expose GTT 
alignment"

On 26/10/2022 08:47, Patchwork wrote:
> *Patch Details*
> *Series:* Revert "drm/i915/uapi: expose GTT alignment"
> *URL:*https://patchwork.freedesktop.org/series/110041/ 
> 
> *State:*  failure
> *Details:* 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html 
> 
> 
> 
>   CI Bug Log - changes from CI_DRM_12284_full -> Patchwork_110041v1_full
> 
> 
> Summary
> 
> *FAILURE*
> 
> Serious unknown changes coming with Patchwork_110041v1_full absolutely 
> need to be
> verified manually.
> 
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_110041v1_full, please notify your bug team to 
> allow them
> to document this new failure mode, which will reduce false positives in CI.
> 
> 
> Participating hosts (11 -> 11)
> 
> No changes in participating hosts
> 
> 
> Possible new issues
> 
> Here are the unknown changes that may have been introduced in 
> Patchwork_110041v1_full:
> 
> 
>   IGT changes
> 
> 
> Possible regressions
> 
>   *
> 
> igt@i915_pm_rpm@drm-resources-equal:
> 
>   o shard-iclb: PASS
> 
> 
>  -> FAIL 
> 
>   *
> 
> igt@i915_selftest@live@guc_hang:
> 
>   o shard-skl: PASS
> 
> 
>  -> INCOMPLETE 
> 
>   *
> 
> igt@i915_suspend@forcewake:
> 
>   o shard-skl: NOTRUN -> INCOMPLETE
> 
> 
>  +1 similar issue
> 
> 


All look to be unrelated.

> Warnings
> 
>   *
> 
> igt@kms_color@ctm-0-75@pipe-d-edp-1:
> 
>   o shard-tglb: FAIL
> 
> 
>  (i915#315  / i915#6946 
> ) -> INCOMPLETE 
> 
>   *
> 
> igt@kms_cursor_legacy@flip-vs-cursor@atomic:
> 
>   o shard-skl: FAIL
> 
> 
>  (i915#2346 ) -> 
> INCOMPLETE 
> 
> 
> 
> Suppressed
> 
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
> 
>   *
> 
> igt@gem_mmap_offset@clear@smem0:
> 
>   o {shard-rkl}: PASS
> 
> 
>  -> INCOMPLETE 
> 
>   *
> 
> igt@i915_pm_rc6_residency@rc6-idle@vcs0:
> 
>   o {shard-rkl}: PASS
> 
> 
>  -> WARN 
> 
>   *
> 
> igt@i915_pm_rc6_residency@rc6-idle@vecs0:
> 
>   o {shard-rkl}: PASS
> 
> 
>  -> FAIL 
> 
> 
> 
> Known issues
> 
> Here are the changes found in Patchwork_110041v1_full that come from 
> known issues:
> 
> 
>   CI changes
> 
> 
> Issues hit
> 
>   * boot:
>   o shard-glk: (PASS
> 
> , 
> PASS 
> 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Audio stuff

[Patchwork]

== Series Details ==

Series: drm/i915: Audio stuff
URL   : https://patchwork.freedesktop.org/series/110188/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+drivers/gpu/drm/i915/display/intel_display_types.h:1936:24: warning: trying to 
copy expression type 31
+drivers/gpu/drm/i915/display/intel_display_types.h:1936:24: warning: 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Audio stuff

[Patchwork]

== Series Details ==

Series: drm/i915: Audio stuff
URL   : https://patchwork.freedesktop.org/series/110188/
State : warning

== Summary ==

Error: dim checkpatch failed
89816a330d11 drm/i915/audio: s/dev_priv/i915/
-:1033: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written 
"i915->display.audio.lpe.platdev"
#1033: FILE: drivers/gpu/drm/i915/display/intel_audio.c:1405:
+   if (i915->display.audio.lpe.platdev != NULL)

total: 0 errors, 0 warnings, 1 checks, 980 lines checked
8325b0ad65e4 drm/i915/audio: Nuke leftover ROUNDING_FACTOR
d094a7c24e7b drm/i915/audio: Remove CL/BLC audio stuff
54d4a3711cf8 drm/i915/audio: Extract struct ilk_audio_regs
4f45f3bb14c8 drm/i915/audio: Use REG_BIT() & co.
-:159: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#159: FILE: drivers/gpu/drm/i915/display/intel_audio_regs.h:64:
+#define   AUD_CONFIG_N(n)  
(REG_FIELD_PREP(AUD_CONFIG_UPPER_N_MASK, (n) >> 12) | \

-:159: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects?
#159: FILE: drivers/gpu/drm/i915/display/intel_audio_regs.h:64:
+#define   AUD_CONFIG_N(n)  
(REG_FIELD_PREP(AUD_CONFIG_UPPER_N_MASK, (n) >> 12) | \
+
REG_FIELD_PREP(AUD_CONFIG_LOWER_N_MASK, (n) & 0xfff))

-:160: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#160: FILE: drivers/gpu/drm/i915/display/intel_audio_regs.h:65:
+
REG_FIELD_PREP(AUD_CONFIG_LOWER_N_MASK, (n) & 0xfff))

total: 0 errors, 2 warnings, 1 checks, 171 lines checked
06c9bf190dac drm/i915/audio: Unify register bit naming
6d602f53455a drm/i915/audio: Protect singleton register with a lock
1073b7c305e4 drm/i915/audio: Nuke intel_eld_uptodate()
697922c27a1f drm/i915/audio: Read ELD buffer size from hardware
8cbdd1858525 drm/i915/audio: Make sure we write the whole ELD buffer
c1c46ff8ff02 drm/i915/audio: Use u32* for ELD
0b75f88aab20 drm/i915/audio: Use intel_de_rmw() for most audio registers
5f2b90c200c2 drm/i915/audio: Split "ELD valid" vs. audio PD on hsw+
1ec9053b637e drm/i915/audio: Do the vblank waits
672420cdf531 drm/i915/sdvo: Extract intel_sdvo_has_audio()

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: add over-fetch padding to store_dw batchbuffer

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: add over-fetch padding to store_dw batchbuffer
URL   : https://patchwork.freedesktop.org/series/110186/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12297 -> Patchwork_110186v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110186v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110186v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/index.html

Participating hosts (40 -> 41)
--

  Additional (3): fi-bdw-gvtdvm fi-bxt-dsi fi-tgl-dsi 
  Missing(2): fi-ctg-p8600 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110186v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-bdw-gvtdvm:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/fi-bdw-gvtdvm/igt@i915_susp...@basic-s2idle-without-i915.html

  
Known issues


  Here are the changes found in Patchwork_110186v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-bxt-dsi: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/fi-bxt-dsi/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html
- fi-bdw-gvtdvm:  NOTRUN -> [SKIP][4] ([fdo#109271]) +37 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/fi-bdw-gvtdvm/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-bxt-dsi: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/fi-bxt-dsi/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_tiled_blits@basic:
- fi-bxt-dsi: NOTRUN -> [SKIP][6] ([fdo#109271]) +12 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/fi-bxt-dsi/igt@gem_tiled_bl...@basic.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: NOTRUN -> [DMESG-FAIL][7] ([i915#5334])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
- fi-bxt-dsi: NOTRUN -> [DMESG-FAIL][8] ([i915#5334])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][9] -> [INCOMPLETE][10] ([i915#4785])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12297/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/fi-apl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
- fi-bxt-dsi: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/fi-bxt-dsi/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-bdw-gvtdvm:  NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/fi-bdw-gvtdvm/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-apl-guc: NOTRUN -> [SKIP][14] ([fdo#109271]) +11 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/fi-apl-guc/igt@kms_psr@sprite_plane_onoff.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][15] ([fdo#109271] / [i915#4312] / 
[i915#5594])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/fi-hsw-4770/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][16] ([i915#2867]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12297/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110186v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * 

Re: [Intel-gfx] [CI 1/4] drm/i915/display: Change terminology for cdclk actions

[Srivatsa, Anusha]

> -Original Message-
> From: Jani Nikula 
> Sent: Wednesday, October 26, 2022 12:52 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [CI 1/4] drm/i915/display: Change terminology for
> cdclk actions
> 
> On Tue, 25 Oct 2022, Anusha Srivatsa  wrote:
> > No functional changes. Changing terminology in some print statements.
> > s/has_cdclk_squasher/has_cdclk_squash,
> > s/crawler/crawl and s/squasher/squash.
> 
> Any particular reason you re-sent this for CI? You know you can re-run tests
> from the patchwork page if the patches remain unchanged?

Checkpatch return some errors on the previous series: 
https://patchwork.freedesktop.org/series/110135/

Had to rectify them and send it again.

Anusha 
> BR,
> Jani.
> 
> 
> >
> > Cc: Balasubramani Vivekanandan
> 
> > Cc: Ville Syrjälä 
> > Signed-off-by: Anusha Srivatsa 
> > Reviewed-by: Balasubramani Vivekanandan
> > 
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 16 
> >  1 file changed, 8 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index ad401357ab66..0f5add2fc51b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1220,7 +1220,7 @@ static void skl_cdclk_uninit_hw(struct
> drm_i915_private *dev_priv)
> > skl_set_cdclk(dev_priv, _config, INVALID_PIPE);  }
> >
> > -static bool has_cdclk_squasher(struct drm_i915_private *i915)
> > +static bool has_cdclk_squash(struct drm_i915_private *i915)
> >  {
> > return IS_DG2(i915);
> >  }
> > @@ -1520,7 +1520,7 @@ static void bxt_get_cdclk(struct drm_i915_private
> *dev_priv,
> > return;
> > }
> >
> > -   if (has_cdclk_squasher(dev_priv))
> > +   if (has_cdclk_squash(dev_priv))
> > squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
> >
> > if (squash_ctl & CDCLK_SQUASH_ENABLE) { @@ -1747,7 +1747,7 @@
> static
> > void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> > else
> > clock = cdclk;
> >
> > -   if (has_cdclk_squasher(dev_priv)) {
> > +   if (has_cdclk_squash(dev_priv)) {
> > u32 squash_ctl = 0;
> >
> > if (waveform)
> > @@ -1845,7 +1845,7 @@ static void bxt_sanitize_cdclk(struct
> drm_i915_private *dev_priv)
> > expected = skl_cdclk_decimal(cdclk);
> >
> > /* Figure out what CD2X divider we should be using for this cdclk */
> > -   if (has_cdclk_squasher(dev_priv))
> > +   if (has_cdclk_squash(dev_priv))
> > clock = dev_priv->display.cdclk.hw.vco / 2;
> > else
> > clock = dev_priv->display.cdclk.hw.cdclk; @@ -1976,7
> +1976,7 @@
> > static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
> >  * the moment all platforms with squasher use a fixed cd2x
> >  * divider.
> >  */
> > -   if (!has_cdclk_squasher(dev_priv))
> > +   if (!has_cdclk_squash(dev_priv))
> > return false;
> >
> > return a->cdclk != b->cdclk &&
> > @@ -2028,7 +2028,7 @@ static bool intel_cdclk_can_cd2x_update(struct
> drm_i915_private *dev_priv,
> >  * the moment all platforms with squasher use a fixed cd2x
> >  * divider.
> >  */
> > -   if (has_cdclk_squasher(dev_priv))
> > +   if (has_cdclk_squash(dev_priv))
> > return false;
> >
> > return a->cdclk != b->cdclk &&
> > @@ -2754,12 +2754,12 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> >_cdclk_state->actual,
> >_cdclk_state->actual)) {
> > drm_dbg_kms(_priv->drm,
> > -   "Can change cdclk via squasher\n");
> > +   "Can change cdclk via squashing\n");
> > } else if (intel_cdclk_can_crawl(dev_priv,
> >  _cdclk_state->actual,
> >  _cdclk_state->actual)) {
> > drm_dbg_kms(_priv->drm,
> > -   "Can change cdclk via crawl\n");
> > +   "Can change cdclk via crawling\n");
> > } else if (pipe != INVALID_PIPE) {
> > new_cdclk_state->pipe = pipe;
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v5 19/19] drm/i915/vm_bind: Render VM_BIND documentation

[Matthew Auld]

On 25/10/2022 07:59, Niranjana Vishwanathapura wrote:

Update i915 documentation to include VM_BIND changes
and render all VM_BIND related documentation.

Signed-off-by: Niranjana Vishwanathapura 


Thanks for adding this,
Reviewed-by: Matthew Auld 

Re: [Intel-gfx] [PATCH v5 09/19] drm/i915/vm_bind: Add out fence support

[Matthew Auld]

On 25/10/2022 07:58, Niranjana Vishwanathapura wrote:

Add support for handling out fence for vm_bind call.

v2: Reset vma->vm_bind_fence.syncobj to NULL at the end
 of vm_bind call.
v3: Remove vm_unbind out fence uapi which is not supported yet.
v4: Return error if I915_TIMELINE_FENCE_WAIT fence flag is set.
 Wait for bind to complete iff I915_TIMELINE_FENCE_SIGNAL is
 not specified.

Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
  drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h   |  4 +
  .../drm/i915/gem/i915_gem_vm_bind_object.c| 93 +++
  drivers/gpu/drm/i915/i915_vma.c   |  7 +-
  drivers/gpu/drm/i915/i915_vma_types.h |  7 ++
  include/uapi/drm/i915_drm.h   | 49 +-
  5 files changed, 157 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
index 36262a6357b5..b70e900e35ab 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
@@ -8,6 +8,7 @@
  
  #include 
  
+struct dma_fence;

  struct drm_device;
  struct drm_file;
  struct i915_address_space;
@@ -23,4 +24,7 @@ int i915_gem_vm_unbind_ioctl(struct drm_device *dev, void 
*data,
  
  void i915_gem_vm_unbind_all(struct i915_address_space *vm);
  
+void i915_vm_bind_signal_fence(struct i915_vma *vma,

+  struct dma_fence * const fence);
+
  #endif /* __I915_GEM_VM_BIND_H */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
index 863bd17c9253..fca6d6eb9ef8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
@@ -7,6 +7,8 @@
  
  #include 
  
+#include 

+
  #include "gem/i915_gem_context.h"
  #include "gem/i915_gem_vm_bind.h"
  
@@ -100,6 +102,76 @@ static void i915_gem_vm_bind_remove(struct i915_vma *vma, bool release_obj)

i915_gem_object_put(vma->obj);
  }
  
+static int i915_vm_bind_add_fence(struct drm_file *file, struct i915_vma *vma,

+ u32 handle, u64 point)
+{
+   struct drm_syncobj *syncobj;
+
+   syncobj = drm_syncobj_find(file, handle);
+   if (!syncobj) {
+   DRM_DEBUG("Invalid syncobj handle provided\n");


AFAIK drm_dbg() is preferred, if possible.


+   return -ENOENT;
+   }
+
+   /*
+* For timeline syncobjs we need to preallocate chains for
+* later signaling.
+*/
+   if (point) {
+   vma->vm_bind_fence.chain_fence = dma_fence_chain_alloc();
+   if (!vma->vm_bind_fence.chain_fence) {
+   drm_syncobj_put(syncobj);
+   return -ENOMEM;
+   }
+   } else {
+   vma->vm_bind_fence.chain_fence = NULL;
+   }
+   vma->vm_bind_fence.syncobj = syncobj;
+   vma->vm_bind_fence.value = point;
+
+   return 0;
+}
+
+static void i915_vm_bind_put_fence(struct i915_vma *vma)
+{
+   if (!vma->vm_bind_fence.syncobj)
+   return;
+
+   drm_syncobj_put(vma->vm_bind_fence.syncobj);
+   dma_fence_chain_free(vma->vm_bind_fence.chain_fence);
+   vma->vm_bind_fence.syncobj = NULL;
+}
+
+/**
+ * i915_vm_bind_signal_fence() - Add fence to vm_bind syncobj
+ * @vma: vma mapping requiring signaling
+ * @fence: fence to be added
+ *
+ * Associate specified @fence with the @vma's syncobj to be
+ * signaled after the @fence work completes.
+ */
+void i915_vm_bind_signal_fence(struct i915_vma *vma,
+  struct dma_fence * const fence)
+{
+   struct drm_syncobj *syncobj = vma->vm_bind_fence.syncobj;
+
+   if (!syncobj)
+   return;
+
+   if (vma->vm_bind_fence.chain_fence) {
+   drm_syncobj_add_point(syncobj,
+ vma->vm_bind_fence.chain_fence,
+ fence, vma->vm_bind_fence.value);
+   /*
+* The chain's ownership is transferred to the
+* timeline.
+*/
+   vma->vm_bind_fence.chain_fence = NULL;
+   } else {
+   drm_syncobj_replace_fence(syncobj, fence);
+   }
+}
+
  static int i915_gem_vm_unbind_vma(struct i915_address_space *vm,
  struct drm_i915_gem_vm_unbind *va)
  {
@@ -205,6 +277,10 @@ static int i915_gem_vm_bind_obj(struct i915_address_space 
*vm,
if (!va->length || !IS_ALIGNED(va->start, I915_GTT_PAGE_SIZE))
ret = -EINVAL;
  
+	/* In fences are not supported */

+   if (va->fence.flags & I915_TIMELINE_FENCE_WAIT)
+   ret = -EINVAL;


I guess also:

if (flags & __I915_TIMELINE_FENCE_UNKNOWN_FLAGS)

Reviewed-by: Matthew Auld 


+
obj = i915_gem_object_lookup(file, va->handle);
if (!obj)
return -ENOENT;
@@ -237,6 

Re: [Intel-gfx] [PATCH v5 16/19] drm/i915/vm_bind: userptr dma-resv changes

[Matthew Auld]

On 25/10/2022 07:59, Niranjana Vishwanathapura wrote:

For persistent (vm_bind) vmas of userptr BOs, handle the user
page pinning by using the i915_gem_object_userptr_submit_init()
/done() functions

v2: Do not double add vma to vm->userptr_invalidated_list

Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 

Reviewed-by: Matthew Auld 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: add over-fetch padding to store_dw batchbuffer

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: add over-fetch padding to store_dw batchbuffer
URL   : https://patchwork.freedesktop.org/series/110186/
State : warning

== Summary ==

Error: dim checkpatch failed
9a15ae121ad3 drm/i915/selftests: add over-fetch padding to store_dw batchbuffer
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#13: 
(memory is unmapped and TLB is invalidated during memory access, not fully).

total: 0 errors, 1 warnings, 0 checks, 15 lines checked

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)
URL   : https://patchwork.freedesktop.org/series/109963/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109963v5_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_109963v5_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109963v5_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109963v5_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1:
- shard-skl:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl7/igt@kms_cursor_crc@cursor-susp...@pipe-b-edp-1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl9/igt@kms_cursor_crc@cursor-susp...@pipe-b-edp-1.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@sysfs_preempt_timeout@idempotent@rcs0:
- {shard-dg1}:NOTRUN -> [FAIL][3] +4 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-dg1-15/igt@sysfs_preempt_timeout@idempot...@rcs0.html

  
Known issues


  Here are the changes found in Patchwork_109963v5_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb5/igt@gem_...@in-flight-contexts-10ms.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-tglb6/igt@gem_...@in-flight-contexts-10ms.html

  * igt@gem_eio@in-flight-suspend:
- shard-skl:  [PASS][6] -> [INCOMPLETE][7] ([i915#7112])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@gem_...@in-flight-suspend.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl6/igt@gem_...@in-flight-suspend.html

  * igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb1/igt@gem_exec_balan...@parallel.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@gem_exec_balan...@parallel.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl:  [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@gem_lmem_swapp...@parallel-random.html

  * igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][15] -> [FAIL][16] ([i915#3989] / [i915#454])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb5/igt@i915_pm...@dc6-dpms.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@i915_pm...@dc6-dpms.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl:  NOTRUN -> [SKIP][17] ([fdo#109271]) +43 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_big...@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_color_chamelium@ctm-limited-range:
- shard-skl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +2 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_color_chamel...@ctm-limited-range.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl:  [PASS][19] -> [FAIL][20] ([i915#79]) +1 similar issue
   [19]: 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Remove unwanted ghost obj check (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Remove unwanted ghost obj check (rev2)
URL   : https://patchwork.freedesktop.org/series/110065/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12297 -> Patchwork_110065v2


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110065v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110065v2, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110065v2/index.html

Participating hosts (40 -> 41)
--

  Additional (3): fi-bdw-gvtdvm fi-bxt-dsi fi-tgl-dsi 
  Missing(2): fi-ctg-p8600 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110065v2:

### IGT changes ###

 Possible regressions 

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-bdw-gvtdvm:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110065v2/fi-bdw-gvtdvm/igt@i915_susp...@basic-s2idle-without-i915.html

  
Known issues


  Here are the changes found in Patchwork_110065v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-bxt-dsi: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110065v2/fi-bxt-dsi/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110065v2/fi-apl-guc/igt@gem_lmem_swapp...@basic.html
- fi-bdw-gvtdvm:  NOTRUN -> [SKIP][4] ([fdo#109271]) +37 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110065v2/fi-bdw-gvtdvm/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-bxt-dsi: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110065v2/fi-bxt-dsi/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_tiled_blits@basic:
- fi-bxt-dsi: NOTRUN -> [SKIP][6] ([fdo#109271]) +12 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110065v2/fi-bxt-dsi/igt@gem_tiled_bl...@basic.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110065v2/fi-apl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
- fi-bxt-dsi: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110065v2/fi-bxt-dsi/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-bdw-gvtdvm:  NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110065v2/fi-bdw-gvtdvm/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [PASS][10] -> [FAIL][11] ([i915#6298])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12297/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110065v2/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-apl-guc: NOTRUN -> [SKIP][12] ([fdo#109271]) +11 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110065v2/fi-apl-guc/igt@kms_psr@sprite_plane_onoff.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][13] ([i915#2867]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12297/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110065v2/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
- {bat-adlm-1}:   [DMESG-WARN][15] ([i915#2867]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12297/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110065v2/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [INCOMPLETE][17] ([i915#7056]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12297/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [18]: 

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/4] drm/i915/display: Change terminology for cdclk actions

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/4] drm/i915/display: Change terminology for 
cdclk actions
URL   : https://patchwork.freedesktop.org/series/110145/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12295_full -> Patchwork_110145v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110145v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110145v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110145v1_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rpm@system-suspend-execbuf:
- shard-iclb: [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-iclb6/igt@i915_pm_...@system-suspend-execbuf.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110145v1/shard-iclb8/igt@i915_pm_...@system-suspend-execbuf.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-edp-1:
- shard-skl:  [PASS][3] -> [FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-skl1/igt@kms_async_flips@async-flip-with-page-flip-eve...@pipe-b-edp-1.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110145v1/shard-skl3/igt@kms_async_flips@async-flip-with-page-flip-eve...@pipe-b-edp-1.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@sysfs_timeslice_duration@idempotent@vcs0:
- {shard-dg1}:NOTRUN -> [FAIL][5] +9 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110145v1/shard-dg1-19/igt@sysfs_timeslice_duration@idempot...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_110145v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-glk:  ([PASS][6], [PASS][7], [PASS][8], [PASS][9], 
[PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], 
[PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], 
[PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], 
[PASS][28], [PASS][29], [PASS][30]) -> ([PASS][31], [PASS][32], [PASS][33], 
[PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], 
[PASS][40], [FAIL][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], 
[PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], 
[PASS][52], [PASS][53], [PASS][54], [PASS][55]) ([i915#4392])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk9/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk9/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk9/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk9/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk8/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk8/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk8/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk7/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk7/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk7/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk6/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk6/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk6/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk5/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk5/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk5/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk3/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk3/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk3/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk2/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk2/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk2/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk1/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/shard-glk1/boot.html
   

[Intel-gfx] [PATCH 07/15] drm/i915/audio: Protect singleton register with a lock

[Ville Syrjala]

From: Ville Syrjälä 

On the "ilk" platforms AUD_CNTL_ST2 is a singleton. Protect
it with the audio mutex in case we ever want to do parallel
RMW access to it.

Currently that should not happen since we only do audio
enable/disable from full modesets, and those are fully
serialized. But we probably want to think about toggling
audio on/off from fastsets too.

The hsw codepaths already have the same locking.
g4x should not need it since it can only do audio to a
single port at a time, which means it's actually broken
in more ways than this atm.

Cc: Chaitanya Kumar Borah 
Cc: Kai Vehmanen 
Cc: Takashi Iwai 
Reviewed-by: Jani Nikula 
Reviewed-by: Kai Vehmanen 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_audio.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index 5d545d2ffb33..093283fd1c28 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -707,6 +707,8 @@ static void ilk_audio_codec_disable(struct intel_encoder 
*encoder,
 
ilk_audio_regs_init(i915, pipe, );
 
+   mutex_lock(>display.audio.mutex);
+
/* Disable timestamps */
tmp = intel_de_read(i915, regs.aud_config);
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
@@ -721,6 +723,8 @@ static void ilk_audio_codec_disable(struct intel_encoder 
*encoder,
tmp = intel_de_read(i915, regs.aud_cntrl_st2);
tmp &= ~IBX_ELD_VALID(port);
intel_de_write(i915, regs.aud_cntrl_st2, tmp);
+
+   mutex_unlock(>display.audio.mutex);
 }
 
 static void ilk_audio_codec_enable(struct intel_encoder *encoder,
@@ -749,6 +753,7 @@ static void ilk_audio_codec_enable(struct intel_encoder 
*encoder,
 
ilk_audio_regs_init(i915, pipe, );
 
+   mutex_lock(>display.audio.mutex);
 
/* Invalidate ELD */
tmp = intel_de_read(i915, regs.aud_cntrl_st2);
@@ -781,6 +786,8 @@ static void ilk_audio_codec_enable(struct intel_encoder 
*encoder,
else
tmp |= audio_config_hdmi_pixel_clock(crtc_state);
intel_de_write(i915, regs.aud_config, tmp);
+
+   mutex_unlock(>display.audio.mutex);
 }
 
 /**
-- 
2.37.4

[Intel-gfx] [PATCH 13/15] drm/i915/audio: Split "ELD valid" vs. audio PD on hsw+

[Ville Syrjala]

From: Ville Syrjälä 

On the older platforms the audio presence detect bit is in
the port register, so it gets written outside audio codec hooks
and is this separate from the ELD valid toggling. Split the
operations into two steps on hsw+ to be more consistent with
both the other platforms and the spec. Also according to the
spec we might need some vblank waits between the two which
definitely needs them done separately.

Cc: Chaitanya Kumar Borah 
Cc: Kai Vehmanen 
Cc: Takashi Iwai 
Reviewed-by: Jani Nikula 
Reviewed-by: Kai Vehmanen 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_audio.c | 16 +++-
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index 9ba1351f2c6d..cbc5615f43bf 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -481,9 +481,12 @@ static void hsw_audio_codec_disable(struct intel_encoder 
*encoder,
 (intel_crtc_has_dp_encoder(old_crtc_state) ?
  AUD_CONFIG_N_VALUE_INDEX : 0));
 
-   /* Disable audio presence detect, invalidate ELD */
+   /* Invalidate ELD */
+   intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
+AUDIO_ELD_VALID(cpu_transcoder), 0);
+
+   /* Disable audio presence detect */
intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
-AUDIO_ELD_VALID(cpu_transcoder) |
 AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0);
 
mutex_unlock(>display.audio.mutex);
@@ -614,10 +617,13 @@ static void hsw_audio_codec_enable(struct intel_encoder 
*encoder,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
enable_audio_dsc_wa(encoder, crtc_state);
 
-   /* Enable audio presence detect, invalidate ELD */
+   /* Enable audio presence detect */
intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
-AUDIO_ELD_VALID(cpu_transcoder),
-AUDIO_OUTPUT_ENABLE(cpu_transcoder));
+0, AUDIO_OUTPUT_ENABLE(cpu_transcoder));
+
+   /* Invalidate ELD */
+   intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
+AUDIO_ELD_VALID(cpu_transcoder), 0);
 
/*
 * FIXME: We're supposed to wait for vblank here, but we have vblanks
-- 
2.37.4

[Intel-gfx] [PATCH 10/15] drm/i915/audio: Make sure we write the whole ELD buffer

[Ville Syrjala]

From: Ville Syrjälä 

Currently we only write as many dwords into the hardware
ELD buffers as drm_eld_size() tells us. That could mean the
remainder of the hardware buffer is left with whatever
stale garbage it had before, which doesn't seem entirely
great. Let's zero out the remainder of the buffer in case
the provided ELD doesn't fill it fully.

We can also sanity check out idea of the hardware ELD buffer's
size by making sure the address wrapped back to zero once
we wrote the entire buffer.

Cc: Chaitanya Kumar Borah 
Cc: Kai Vehmanen 
Cc: Takashi Iwai 
Reviewed-by: Jani Nikula 
Reviewed-by: Kai Vehmanen 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_audio.c | 34 --
 1 file changed, 25 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index 60b44bcaa0e4..56f0d8af313e 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -334,19 +334,24 @@ static void g4x_audio_codec_enable(struct intel_encoder 
*encoder,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct drm_connector *connector = conn_state->connector;
const u8 *eld = connector->eld;
+   int eld_buffer_size, len, i;
u32 tmp;
-   int len, i;
 
tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
tmp &= ~(G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK);
intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
 
-   len = g4x_eld_buffer_size(i915);
-   len = min(drm_eld_size(eld) / 4, len);
+   eld_buffer_size = g4x_eld_buffer_size(i915);
+   len = min(drm_eld_size(eld) / 4, eld_buffer_size);
 
for (i = 0; i < len; i++)
intel_de_write(i915, G4X_HDMIW_HDMIEDID,
   *((const u32 *)eld + i));
+   for (; i < eld_buffer_size; i++)
+   intel_de_write(i915, G4X_HDMIW_HDMIEDID, 0);
+
+   drm_WARN_ON(>drm,
+   (intel_de_read(i915, G4X_AUD_CNTL_ST) & 
G4X_ELD_ADDRESS_MASK) != 0);
 
tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
tmp |= G4X_ELD_VALID;
@@ -610,8 +615,8 @@ static void hsw_audio_codec_enable(struct intel_encoder 
*encoder,
struct drm_connector *connector = conn_state->connector;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
const u8 *eld = connector->eld;
+   int eld_buffer_size, len, i;
u32 tmp;
-   int len, i;
 
mutex_lock(>display.audio.mutex);
 
@@ -637,12 +642,18 @@ static void hsw_audio_codec_enable(struct intel_encoder 
*encoder,
tmp &= ~IBX_ELD_ADDRESS_MASK;
intel_de_write(i915, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp);
 
-   len = hsw_eld_buffer_size(i915, cpu_transcoder);
-   len = min(drm_eld_size(eld) / 4, len);
+   eld_buffer_size = hsw_eld_buffer_size(i915, cpu_transcoder);
+   len = min(drm_eld_size(eld) / 4, eld_buffer_size);
 
for (i = 0; i < len; i++)
intel_de_write(i915, HSW_AUD_EDID_DATA(cpu_transcoder),
   *((const u32 *)eld + i));
+   for (; i < eld_buffer_size; i++)
+   intel_de_write(i915, HSW_AUD_EDID_DATA(cpu_transcoder), 0);
+
+   drm_WARN_ON(>drm,
+   (intel_de_read(i915, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder)) &
+IBX_ELD_ADDRESS_MASK) != 0);
 
/* ELD valid */
tmp = intel_de_read(i915, HSW_AUD_PIN_ELD_CP_VLD);
@@ -741,8 +752,8 @@ static void ilk_audio_codec_enable(struct intel_encoder 
*encoder,
enum pipe pipe = crtc->pipe;
enum port port = encoder->port;
const u8 *eld = connector->eld;
+   int eld_buffer_size, len, i;
struct ilk_audio_regs regs;
-   int len, i;
u32 tmp;
 
if (drm_WARN_ON(>drm, port == PORT_A))
@@ -769,12 +780,17 @@ static void ilk_audio_codec_enable(struct intel_encoder 
*encoder,
tmp &= ~IBX_ELD_ADDRESS_MASK;
intel_de_write(i915, regs.aud_cntl_st, tmp);
 
-   len = ilk_eld_buffer_size(i915, pipe);
-   len = min(drm_eld_size(eld) / 4, len);
+   eld_buffer_size = ilk_eld_buffer_size(i915, pipe);
+   len = min(drm_eld_size(eld) / 4, eld_buffer_size);
 
for (i = 0; i < len; i++)
intel_de_write(i915, regs.hdmiw_hdmiedid,
   *((const u32 *)eld + i));
+   for (; i < eld_buffer_size; i++)
+   intel_de_write(i915, regs.hdmiw_hdmiedid, 0);
+
+   drm_WARN_ON(>drm,
+   (intel_de_read(i915, regs.aud_cntl_st) & 
IBX_ELD_ADDRESS_MASK) != 0);
 
/* ELD valid */
tmp = intel_de_read(i915, regs.aud_cntrl_st2);
-- 
2.37.4

[Intel-gfx] [PATCH 09/15] drm/i915/audio: Read ELD buffer size from hardware

[Ville Syrjala]

From: Ville Syrjälä 

We currently read the ELD buffer size from hardware on g4x,
but on ilk+ we just hardcode it to 84 bytes. Let's unify
this and just do the hardware readout on all platforms,
in case the size changes in the future or something.

TODO: should perhaps do the readout during driver init and
stash the results somewhere so that we could check that the
connector's ELD actually fits and not even try to enable audio
in that case...

v2: Document the size is in dwords (Jani)

Cc: Chaitanya Kumar Borah 
Cc: Kai Vehmanen 
Cc: Takashi Iwai 
Reviewed-by: Jani Nikula 
Reviewed-by: Kai Vehmanen 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_audio.c | 52 +++---
 1 file changed, 45 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index 7867eb670560..60b44bcaa0e4 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -304,6 +304,16 @@ static int audio_config_hdmi_get_n(const struct 
intel_crtc_state *crtc_state,
return 0;
 }
 
+/* ELD buffer size in dwords */
+static int g4x_eld_buffer_size(struct drm_i915_private *i915)
+{
+   u32 tmp;
+
+   tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
+
+   return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp);
+}
+
 static void g4x_audio_codec_disable(struct intel_encoder *encoder,
const struct intel_crtc_state 
*old_crtc_state,
const struct drm_connector_state 
*old_conn_state)
@@ -329,10 +339,11 @@ static void g4x_audio_codec_enable(struct intel_encoder 
*encoder,
 
tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
tmp &= ~(G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK);
-   len = REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp);
intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
 
+   len = g4x_eld_buffer_size(i915);
len = min(drm_eld_size(eld) / 4, len);
+
for (i = 0; i < len; i++)
intel_de_write(i915, G4X_HDMIW_HDMIEDID,
   *((const u32 *)eld + i));
@@ -442,6 +453,17 @@ hsw_audio_config_update(struct intel_encoder *encoder,
hsw_hdmi_audio_config_update(encoder, crtc_state);
 }
 
+/* ELD buffer size in dwords */
+static int hsw_eld_buffer_size(struct drm_i915_private *i915,
+  enum transcoder cpu_transcoder)
+{
+   u32 tmp;
+
+   tmp = intel_de_read(i915, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder));
+
+   return REG_FIELD_GET(IBX_ELD_BUFFER_SIZE_MASK, tmp);
+}
+
 static void hsw_audio_codec_disable(struct intel_encoder *encoder,
const struct intel_crtc_state 
*old_crtc_state,
const struct drm_connector_state 
*old_conn_state)
@@ -615,9 +637,10 @@ static void hsw_audio_codec_enable(struct intel_encoder 
*encoder,
tmp &= ~IBX_ELD_ADDRESS_MASK;
intel_de_write(i915, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp);
 
-   /* Up to 84 bytes of hw ELD buffer */
-   len = min(drm_eld_size(eld), 84);
-   for (i = 0; i < len / 4; i++)
+   len = hsw_eld_buffer_size(i915, cpu_transcoder);
+   len = min(drm_eld_size(eld) / 4, len);
+
+   for (i = 0; i < len; i++)
intel_de_write(i915, HSW_AUD_EDID_DATA(cpu_transcoder),
   *((const u32 *)eld + i));
 
@@ -658,6 +681,20 @@ static void ilk_audio_regs_init(struct drm_i915_private 
*i915,
}
 }
 
+/* ELD buffer size in dwords */
+static int ilk_eld_buffer_size(struct drm_i915_private *i915,
+  enum pipe pipe)
+{
+   struct ilk_audio_regs regs;
+   u32 tmp;
+
+   ilk_audio_regs_init(i915, pipe, );
+
+   tmp = intel_de_read(i915, regs.aud_cntl_st);
+
+   return REG_FIELD_GET(IBX_ELD_BUFFER_SIZE_MASK, tmp);
+}
+
 static void ilk_audio_codec_disable(struct intel_encoder *encoder,
const struct intel_crtc_state 
*old_crtc_state,
const struct drm_connector_state 
*old_conn_state)
@@ -732,9 +769,10 @@ static void ilk_audio_codec_enable(struct intel_encoder 
*encoder,
tmp &= ~IBX_ELD_ADDRESS_MASK;
intel_de_write(i915, regs.aud_cntl_st, tmp);
 
-   /* Up to 84 bytes of hw ELD buffer */
-   len = min(drm_eld_size(eld), 84);
-   for (i = 0; i < len / 4; i++)
+   len = ilk_eld_buffer_size(i915, pipe);
+   len = min(drm_eld_size(eld) / 4, len);
+
+   for (i = 0; i < len; i++)
intel_de_write(i915, regs.hdmiw_hdmiedid,
   *((const u32 *)eld + i));
 
-- 
2.37.4

[Intel-gfx] [PATCH 12/15] drm/i915/audio: Use intel_de_rmw() for most audio registers

[Ville Syrjala]

From: Ville Syrjälä 

The audio code does a lot of RMW accesses. Utilize
intel_de_rmw() to make that a bit less tedious.

There are still some hand rolled RMW left, but those have
a lot of code in between the read and write to calculate
the new value, so would need some refactoring first.

v2: Add parens around the ?: to satisfy the robot

Cc: Chaitanya Kumar Borah 
Cc: Kai Vehmanen 
Cc: Takashi Iwai 
Reviewed-by: Jani Nikula 
Reviewed-by: Kai Vehmanen 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_audio.c | 136 +
 1 file changed, 56 insertions(+), 80 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index f4c319a3003b..9ba1351f2c6d 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -319,12 +319,10 @@ static void g4x_audio_codec_disable(struct intel_encoder 
*encoder,
const struct drm_connector_state 
*old_conn_state)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-   u32 tmp;
 
/* Invalidate ELD */
-   tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
-   tmp &= ~G4X_ELD_VALID;
-   intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
+   intel_de_rmw(i915, G4X_AUD_CNTL_ST,
+G4X_ELD_VALID, 0);
 }
 
 static void g4x_audio_codec_enable(struct intel_encoder *encoder,
@@ -335,11 +333,9 @@ static void g4x_audio_codec_enable(struct intel_encoder 
*encoder,
struct drm_connector *connector = conn_state->connector;
const u32 *eld = (const u32 *)connector->eld;
int eld_buffer_size, len, i;
-   u32 tmp;
 
-   tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
-   tmp &= ~(G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK);
-   intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
+   intel_de_rmw(i915, G4X_AUD_CNTL_ST,
+G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0);
 
eld_buffer_size = g4x_eld_buffer_size(i915);
len = min(drm_eld_size(connector->eld) / 4, eld_buffer_size);
@@ -352,9 +348,8 @@ static void g4x_audio_codec_enable(struct intel_encoder 
*encoder,
drm_WARN_ON(>drm,
(intel_de_read(i915, G4X_AUD_CNTL_ST) & 
G4X_ELD_ADDRESS_MASK) != 0);
 
-   tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
-   tmp |= G4X_ELD_VALID;
-   intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
+   intel_de_rmw(i915, G4X_AUD_CNTL_ST,
+0, G4X_ELD_VALID);
 }
 
 static void
@@ -474,25 +469,22 @@ static void hsw_audio_codec_disable(struct intel_encoder 
*encoder,
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
-   u32 tmp;
 
mutex_lock(>display.audio.mutex);
 
/* Disable timestamps */
-   tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder));
-   tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
-   tmp |= AUD_CONFIG_N_PROG_ENABLE;
-   tmp &= ~AUD_CONFIG_UPPER_N_MASK;
-   tmp &= ~AUD_CONFIG_LOWER_N_MASK;
-   if (intel_crtc_has_dp_encoder(old_crtc_state))
-   tmp |= AUD_CONFIG_N_VALUE_INDEX;
-   intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp);
+   intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder),
+AUD_CONFIG_N_VALUE_INDEX |
+AUD_CONFIG_UPPER_N_MASK |
+AUD_CONFIG_LOWER_N_MASK,
+AUD_CONFIG_N_PROG_ENABLE |
+(intel_crtc_has_dp_encoder(old_crtc_state) ?
+ AUD_CONFIG_N_VALUE_INDEX : 0));
 
-   /* Invalidate ELD */
-   tmp = intel_de_read(i915, HSW_AUD_PIN_ELD_CP_VLD);
-   tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
-   tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
-   intel_de_write(i915, HSW_AUD_PIN_ELD_CP_VLD, tmp);
+   /* Disable audio presence detect, invalidate ELD */
+   intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
+AUDIO_ELD_VALID(cpu_transcoder) |
+AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0);
 
mutex_unlock(>display.audio.mutex);
 }
@@ -615,7 +607,6 @@ static void hsw_audio_codec_enable(struct intel_encoder 
*encoder,
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
const u32 *eld = (const u32 *)connector->eld;
int eld_buffer_size, len, i;
-   u32 tmp;
 
mutex_lock(>display.audio.mutex);
 
@@ -624,10 +615,9 @@ static void hsw_audio_codec_enable(struct intel_encoder 
*encoder,
enable_audio_dsc_wa(encoder, crtc_state);
 
/* Enable audio presence detect, invalidate ELD */
-   tmp = intel_de_read(i915, HSW_AUD_PIN_ELD_CP_VLD);
-   tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder);
-   tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
-   intel_de_write(i915, HSW_AUD_PIN_ELD_CP_VLD, tmp);
+   intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
+

[Intel-gfx] [PATCH 11/15] drm/i915/audio: Use u32* for ELD

[Ville Syrjala]

From: Ville Syrjälä 

Make the eld pointer u32* so we don't have to do super
ugly casting in the code itself.

Cc: Chaitanya Kumar Borah 
Cc: Kai Vehmanen 
Cc: Takashi Iwai 
Reviewed-by: Jani Nikula 
Reviewed-by: Kai Vehmanen 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_audio.c | 21 +
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index 56f0d8af313e..f4c319a3003b 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -333,7 +333,7 @@ static void g4x_audio_codec_enable(struct intel_encoder 
*encoder,
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct drm_connector *connector = conn_state->connector;
-   const u8 *eld = connector->eld;
+   const u32 *eld = (const u32 *)connector->eld;
int eld_buffer_size, len, i;
u32 tmp;
 
@@ -342,11 +342,10 @@ static void g4x_audio_codec_enable(struct intel_encoder 
*encoder,
intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
 
eld_buffer_size = g4x_eld_buffer_size(i915);
-   len = min(drm_eld_size(eld) / 4, eld_buffer_size);
+   len = min(drm_eld_size(connector->eld) / 4, eld_buffer_size);
 
for (i = 0; i < len; i++)
-   intel_de_write(i915, G4X_HDMIW_HDMIEDID,
-  *((const u32 *)eld + i));
+   intel_de_write(i915, G4X_HDMIW_HDMIEDID, eld[i]);
for (; i < eld_buffer_size; i++)
intel_de_write(i915, G4X_HDMIW_HDMIEDID, 0);
 
@@ -614,7 +613,7 @@ static void hsw_audio_codec_enable(struct intel_encoder 
*encoder,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct drm_connector *connector = conn_state->connector;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-   const u8 *eld = connector->eld;
+   const u32 *eld = (const u32 *)connector->eld;
int eld_buffer_size, len, i;
u32 tmp;
 
@@ -643,11 +642,10 @@ static void hsw_audio_codec_enable(struct intel_encoder 
*encoder,
intel_de_write(i915, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp);
 
eld_buffer_size = hsw_eld_buffer_size(i915, cpu_transcoder);
-   len = min(drm_eld_size(eld) / 4, eld_buffer_size);
+   len = min(drm_eld_size(connector->eld) / 4, eld_buffer_size);
 
for (i = 0; i < len; i++)
-   intel_de_write(i915, HSW_AUD_EDID_DATA(cpu_transcoder),
-  *((const u32 *)eld + i));
+   intel_de_write(i915, HSW_AUD_EDID_DATA(cpu_transcoder), eld[i]);
for (; i < eld_buffer_size; i++)
intel_de_write(i915, HSW_AUD_EDID_DATA(cpu_transcoder), 0);
 
@@ -749,9 +747,9 @@ static void ilk_audio_codec_enable(struct intel_encoder 
*encoder,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_connector *connector = conn_state->connector;
+   const u32 *eld = (const u32 *)connector->eld;
enum pipe pipe = crtc->pipe;
enum port port = encoder->port;
-   const u8 *eld = connector->eld;
int eld_buffer_size, len, i;
struct ilk_audio_regs regs;
u32 tmp;
@@ -781,11 +779,10 @@ static void ilk_audio_codec_enable(struct intel_encoder 
*encoder,
intel_de_write(i915, regs.aud_cntl_st, tmp);
 
eld_buffer_size = ilk_eld_buffer_size(i915, pipe);
-   len = min(drm_eld_size(eld) / 4, eld_buffer_size);
+   len = min(drm_eld_size(connector->eld) / 4, eld_buffer_size);
 
for (i = 0; i < len; i++)
-   intel_de_write(i915, regs.hdmiw_hdmiedid,
-  *((const u32 *)eld + i));
+   intel_de_write(i915, regs.hdmiw_hdmiedid, eld[i]);
for (; i < eld_buffer_size; i++)
intel_de_write(i915, regs.hdmiw_hdmiedid, 0);
 
-- 
2.37.4

[Intel-gfx] [PATCH 14/15] drm/i915/audio: Do the vblank waits

[Ville Syrjala]

From: Ville Syrjälä 

The spec tells us to do a bunch of vblank waits in the audio
enable/disable sequences. Make it so.

The FIXMEs are nonsense since we do the audio disable very
early and enable very late, so vblank interrupts are in fact
enabled when we do this.

TODO not sure we actually want these since we don't even rely
on the hw ELD buffer, and these might be there just to give
the audio side a bit of time to respond to the unsol events.
OTOH they might be really needed for some other reason.

Cc: Chaitanya Kumar Borah 
Cc: Kai Vehmanen 
Cc: Takashi Iwai 
Acked-by: Jani Nikula 
Reviewed-by: Kai Vehmanen 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_audio.c | 31 +-
 1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index cbc5615f43bf..c3176c9c89a6 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -319,10 +319,14 @@ static void g4x_audio_codec_disable(struct intel_encoder 
*encoder,
const struct drm_connector_state 
*old_conn_state)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 
/* Invalidate ELD */
intel_de_rmw(i915, G4X_AUD_CNTL_ST,
 G4X_ELD_VALID, 0);
+
+   intel_crtc_wait_for_next_vblank(crtc);
+   intel_crtc_wait_for_next_vblank(crtc);
 }
 
 static void g4x_audio_codec_enable(struct intel_encoder *encoder,
@@ -330,10 +334,13 @@ static void g4x_audio_codec_enable(struct intel_encoder 
*encoder,
   const struct drm_connector_state *conn_state)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_connector *connector = conn_state->connector;
const u32 *eld = (const u32 *)connector->eld;
int eld_buffer_size, len, i;
 
+   intel_crtc_wait_for_next_vblank(crtc);
+
intel_de_rmw(i915, G4X_AUD_CNTL_ST,
 G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0);
 
@@ -468,6 +475,7 @@ static void hsw_audio_codec_disable(struct intel_encoder 
*encoder,
const struct drm_connector_state 
*old_conn_state)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 
mutex_lock(>display.audio.mutex);
@@ -485,6 +493,9 @@ static void hsw_audio_codec_disable(struct intel_encoder 
*encoder,
intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
 AUDIO_ELD_VALID(cpu_transcoder), 0);
 
+   intel_crtc_wait_for_next_vblank(crtc);
+   intel_crtc_wait_for_next_vblank(crtc);
+
/* Disable audio presence detect */
intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
 AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0);
@@ -606,6 +617,7 @@ static void hsw_audio_codec_enable(struct intel_encoder 
*encoder,
   const struct drm_connector_state *conn_state)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_connector *connector = conn_state->connector;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
const u32 *eld = (const u32 *)connector->eld;
@@ -621,17 +633,12 @@ static void hsw_audio_codec_enable(struct intel_encoder 
*encoder,
intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder));
 
+   intel_crtc_wait_for_next_vblank(crtc);
+
/* Invalidate ELD */
intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
 AUDIO_ELD_VALID(cpu_transcoder), 0);
 
-   /*
-* FIXME: We're supposed to wait for vblank here, but we have vblanks
-* disabled during the mode set. The proper fix would be to push the
-* rest of the setup into a vblank work item, queued here, but the
-* infrastructure is not there yet.
-*/
-
/* Reset ELD address */
intel_de_rmw(i915, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder),
 IBX_ELD_ADDRESS_MASK, 0);
@@ -729,6 +736,9 @@ static void ilk_audio_codec_disable(struct intel_encoder 
*encoder,
 IBX_ELD_VALID(port), 0);
 
mutex_unlock(>display.audio.mutex);
+
+   intel_crtc_wait_for_next_vblank(crtc);
+   intel_crtc_wait_for_next_vblank(crtc);
 }
 
 static void ilk_audio_codec_enable(struct intel_encoder *encoder,
@@ -747,12 +757,7 @@ static void ilk_audio_codec_enable(struct intel_encoder 
*encoder,
if (drm_WARN_ON(>drm, port == PORT_A))
return;
 
-   

[Intel-gfx] [PATCH 15/15] drm/i915/sdvo: Extract intel_sdvo_has_audio()

[Ville Syrjala]

From: Ville Syrjälä 

Pull the SDVO audio state computation into a helper.

This is almost identical to intel_hdmi_has_audio(),
except the sink capabilities are stored under intel_sdvo
rather than intel_hdmi. Might be nice to get rid of
this duplication eventually...

Cc: Chaitanya Kumar Borah 
Cc: Kai Vehmanen 
Cc: Takashi Iwai 
Reviewed-by: Jani Nikula 
Reviewed-by: Kai Vehmanen 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_sdvo.c | 27 +++
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c 
b/drivers/gpu/drm/i915/display/intel_sdvo.c
index cf8e80936d8e..8852564b5fbf 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -1297,13 +1297,28 @@ static bool intel_sdvo_limited_color_range(struct 
intel_encoder *encoder,
return intel_hdmi_limited_color_range(crtc_state, conn_state);
 }
 
+static bool intel_sdvo_has_audio(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+const struct drm_connector_state *conn_state)
+{
+   struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
+   const struct intel_digital_connector_state *intel_conn_state =
+   to_intel_digital_connector_state(conn_state);
+
+   if (!crtc_state->has_hdmi_sink)
+   return false;
+
+   if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
+   return intel_sdvo->has_hdmi_audio;
+   else
+   return intel_conn_state->force_audio == HDMI_AUDIO_ON;
+}
+
 static int intel_sdvo_compute_config(struct intel_encoder *encoder,
 struct intel_crtc_state *pipe_config,
 struct drm_connector_state *conn_state)
 {
struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
-   struct intel_sdvo_connector_state *intel_sdvo_state =
-   to_intel_sdvo_connector_state(conn_state);
struct intel_sdvo_connector *intel_sdvo_connector =
to_intel_sdvo_connector(conn_state->connector);
struct drm_display_mode *adjusted_mode = _config->hw.adjusted_mode;
@@ -1362,13 +1377,7 @@ static int intel_sdvo_compute_config(struct 
intel_encoder *encoder,
 
pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, 
conn_state);
 
-   if (pipe_config->has_hdmi_sink) {
-   if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO)
-   pipe_config->has_audio = intel_sdvo->has_hdmi_audio;
-   else
-   pipe_config->has_audio =
-   intel_sdvo_state->base.force_audio == 
HDMI_AUDIO_ON;
-   }
+   pipe_config->has_audio = intel_sdvo_has_audio(encoder, pipe_config, 
conn_state);
 
pipe_config->limited_color_range =
intel_sdvo_limited_color_range(encoder, pipe_config,
-- 
2.37.4

[Intel-gfx] [PATCH 02/15] drm/i915/audio: Nuke leftover ROUNDING_FACTOR

[Ville Syrjala]

From: Ville Syrjälä 

Remove some leftovers I missed in commit
2dd43144e824 ("drm/i915: Streamline the artihmetic")

Cc: Chaitanya Kumar Borah 
Cc: Kai Vehmanen 
Cc: Takashi Iwai 
Reviewed-by: Jani Nikula 
Reviewed-by: Kai Vehmanen 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_audio.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index aa70b3f075c3..c6e7cecc6690 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -626,8 +626,6 @@ static void enable_audio_dsc_wa(struct intel_encoder 
*encoder,
intel_de_write(i915, AUD_CONFIG_BE, val);
 }
 
-#undef ROUNDING_FACTOR
-
 static void hsw_audio_codec_enable(struct intel_encoder *encoder,
   const struct intel_crtc_state *crtc_state,
   const struct drm_connector_state *conn_state)
-- 
2.37.4

[Intel-gfx] [PATCH 04/15] drm/i915/audio: Extract struct ilk_audio_regs

[Ville Syrjala]

From: Ville Syrjälä 

The "ilk" audio codec codepaths have some duplicated code
to figure out the correct registers to use on each platform.
Extrat that into a single place.

Cc: Chaitanya Kumar Borah 
Cc: Kai Vehmanen 
Cc: Takashi Iwai 
Reviewed-by: Jani Nikula 
Reviewed-by: Kai Vehmanen 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_audio.c | 101 +++--
 1 file changed, 51 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index b91167eaf71f..e35fabf8d86e 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -665,47 +665,64 @@ static void hsw_audio_codec_enable(struct intel_encoder 
*encoder,
mutex_unlock(>display.audio.mutex);
 }
 
-static void ilk_audio_codec_disable(struct intel_encoder *encoder,
-   const struct intel_crtc_state 
*old_crtc_state,
-   const struct drm_connector_state 
*old_conn_state)
+struct ilk_audio_regs {
+   i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
+};
+
+static void ilk_audio_regs_init(struct drm_i915_private *i915,
+   enum pipe pipe,
+   struct ilk_audio_regs *regs)
 {
-   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-   struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
-   enum pipe pipe = crtc->pipe;
-   enum port port = encoder->port;
-   u32 tmp, eldv;
-   i915_reg_t aud_config, aud_cntrl_st2;
-
-   if (drm_WARN_ON(>drm, port == PORT_A))
-   return;
-
if (HAS_PCH_IBX(i915)) {
-   aud_config = IBX_AUD_CFG(pipe);
-   aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
+   regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
+   regs->aud_config = IBX_AUD_CFG(pipe);
+   regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
+   regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
-   aud_config = VLV_AUD_CFG(pipe);
-   aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
+   regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
+   regs->aud_config = VLV_AUD_CFG(pipe);
+   regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
+   regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
} else {
-   aud_config = CPT_AUD_CFG(pipe);
-   aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
+   regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
+   regs->aud_config = CPT_AUD_CFG(pipe);
+   regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
+   regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
}
+}
+
+static void ilk_audio_codec_disable(struct intel_encoder *encoder,
+   const struct intel_crtc_state 
*old_crtc_state,
+   const struct drm_connector_state 
*old_conn_state)
+{
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+   enum pipe pipe = crtc->pipe;
+   enum port port = encoder->port;
+   struct ilk_audio_regs regs;
+   u32 tmp, eldv;
+
+   if (drm_WARN_ON(>drm, port == PORT_A))
+   return;
+
+   ilk_audio_regs_init(i915, pipe, );
 
/* Disable timestamps */
-   tmp = intel_de_read(i915, aud_config);
+   tmp = intel_de_read(i915, regs.aud_config);
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
tmp |= AUD_CONFIG_N_PROG_ENABLE;
tmp &= ~AUD_CONFIG_UPPER_N_MASK;
tmp &= ~AUD_CONFIG_LOWER_N_MASK;
if (intel_crtc_has_dp_encoder(old_crtc_state))
tmp |= AUD_CONFIG_N_VALUE_INDEX;
-   intel_de_write(i915, aud_config, tmp);
+   intel_de_write(i915, regs.aud_config, tmp);
 
eldv = IBX_ELD_VALID(port);
 
/* Invalidate ELD */
-   tmp = intel_de_read(i915, aud_cntrl_st2);
+   tmp = intel_de_read(i915, regs.aud_cntrl_st2);
tmp &= ~eldv;
-   intel_de_write(i915, aud_cntrl_st2, tmp);
+   intel_de_write(i915, regs.aud_cntrl_st2, tmp);
 }
 
 static void ilk_audio_codec_enable(struct intel_encoder *encoder,
@@ -718,9 +735,9 @@ static void ilk_audio_codec_enable(struct intel_encoder 
*encoder,
enum pipe pipe = crtc->pipe;
enum port port = encoder->port;
const u8 *eld = connector->eld;
+   struct ilk_audio_regs regs;
u32 tmp, eldv;
int len, i;
-   i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
 
if (drm_WARN_ON(>drm, port == PORT_A))
return;
@@ -732,49 +749,33 @@ static void ilk_audio_codec_enable(struct intel_encoder 
*encoder,
 * infrastructure is not there yet.
 */
 
-   if (HAS_PCH_IBX(i915)) {
-   hdmiw_hdmiedid 

[Intel-gfx] [PATCH 05/15] drm/i915/audio: Use REG_BIT() & co.

[Ville Syrjala]

From: Ville Syrjälä 

Switch the audio registers to REG_BIT() & co.

Cc: Chaitanya Kumar Borah 
Cc: Kai Vehmanen 
Cc: Takashi Iwai 
Reviewed-by: Jani Nikula 
Reviewed-by: Kai Vehmanen 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_audio.c| 15 ++--
 .../gpu/drm/i915/display/intel_audio_regs.h   | 81 +--
 2 files changed, 45 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index e35fabf8d86e..29f2820c94c3 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -362,7 +362,7 @@ static void g4x_audio_codec_enable(struct intel_encoder 
*encoder,
 
tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
tmp &= ~(G4X_ELDV | G4X_ELD_ADDR_MASK);
-   len = (tmp >> 9) & 0x1f;/* ELD buffer size */
+   len = REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp);
intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
 
len = min(drm_eld_size(eld) / 4, len);
@@ -700,7 +700,7 @@ static void ilk_audio_codec_disable(struct intel_encoder 
*encoder,
enum pipe pipe = crtc->pipe;
enum port port = encoder->port;
struct ilk_audio_regs regs;
-   u32 tmp, eldv;
+   u32 tmp;
 
if (drm_WARN_ON(>drm, port == PORT_A))
return;
@@ -717,11 +717,9 @@ static void ilk_audio_codec_disable(struct intel_encoder 
*encoder,
tmp |= AUD_CONFIG_N_VALUE_INDEX;
intel_de_write(i915, regs.aud_config, tmp);
 
-   eldv = IBX_ELD_VALID(port);
-
/* Invalidate ELD */
tmp = intel_de_read(i915, regs.aud_cntrl_st2);
-   tmp &= ~eldv;
+   tmp &= ~IBX_ELD_VALID(port);
intel_de_write(i915, regs.aud_cntrl_st2, tmp);
 }
 
@@ -736,8 +734,8 @@ static void ilk_audio_codec_enable(struct intel_encoder 
*encoder,
enum port port = encoder->port;
const u8 *eld = connector->eld;
struct ilk_audio_regs regs;
-   u32 tmp, eldv;
int len, i;
+   u32 tmp;
 
if (drm_WARN_ON(>drm, port == PORT_A))
return;
@@ -751,11 +749,10 @@ static void ilk_audio_codec_enable(struct intel_encoder 
*encoder,
 
ilk_audio_regs_init(i915, pipe, );
 
-   eldv = IBX_ELD_VALID(port);
 
/* Invalidate ELD */
tmp = intel_de_read(i915, regs.aud_cntrl_st2);
-   tmp &= ~eldv;
+   tmp &= ~IBX_ELD_VALID(port);
intel_de_write(i915, regs.aud_cntrl_st2, tmp);
 
/* Reset ELD write address */
@@ -771,7 +768,7 @@ static void ilk_audio_codec_enable(struct intel_encoder 
*encoder,
 
/* ELD valid */
tmp = intel_de_read(i915, regs.aud_cntrl_st2);
-   tmp |= eldv;
+   tmp |= IBX_ELD_VALID(port);
intel_de_write(i915, regs.aud_cntrl_st2, tmp);
 
/* Enable timestamps */
diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h 
b/drivers/gpu/drm/i915/display/intel_audio_regs.h
index ebbdd0654919..b5684ed839be 100644
--- a/drivers/gpu/drm/i915/display/intel_audio_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h
@@ -9,9 +9,10 @@
 #include "i915_reg_defs.h"
 
 #define G4X_AUD_CNTL_ST_MMIO(0x620B4)
-#define   G4X_ELDV (1 << 14)
-#define   G4X_ELD_ADDR_MASK(0xf << 5)
-#define   G4X_ELD_ACK  (1 << 4)
+#define   G4X_ELDV REG_BIT(14)
+#define   G4X_ELD_BUFFER_SIZE_MASK REG_GENMASK(13, 9)
+#define   G4X_ELD_ADDR_MASKREG_GENMASK(8, 5)
+#define   G4X_ELD_ACK  REG_BIT(4)
 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
 
 #define _IBX_HDMIW_HDMIEDID_A  0xE2050
@@ -22,12 +23,12 @@
 #define _IBX_AUD_CNTL_ST_B 0xE21B4
 #define IBX_AUD_CNTL_ST(pipe)  _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
  _IBX_AUD_CNTL_ST_B)
-#define   IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
-#define   IBX_ELD_ADDRESS_MASK (0x1f << 5)
-#define   IBX_ELD_ACK  (1 << 4)
+#define   IBX_ELD_BUFFER_SIZE_MASK REG_GENMASK(14, 10)
+#define   IBX_ELD_ADDRESS_MASK REG_GENMASK(9, 5)
+#define   IBX_ELD_ACK  REG_BIT(4)
 #define IBX_AUD_CNTL_ST2   _MMIO(0xE20C0)
-#define   IBX_CP_READY(port)   ((1 << 1) << (((port) - 1) * 4))
-#define   IBX_ELD_VALID(port)  ((1 << 0) << (((port) - 1) * 4))
+#define   IBX_CP_READY(port)   REG_BIT(((port) - 1) * 4 + 1)
+#define   IBX_ELD_VALID(port)  REG_BIT(((port) - 1) * 4 + 0)
 
 #define _CPT_HDMIW_HDMIEDID_A  0xE5050
 #define _CPT_HDMIW_HDMIEDID_B  0xE5150
@@ -54,34 +55,30 @@
 #define _VLV_AUD_CONFIG_A  (VLV_DISPLAY_BASE + 0x62000)
 #define _VLV_AUD_CONFIG_B  (VLV_DISPLAY_BASE + 0x62100)
 #define VLV_AUD_CFG(pipe)  _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, 
_VLV_AUD_CONFIG_B)
-
-#define   AUD_CONFIG_N_VALUE_INDEX 

[Intel-gfx] [PATCH 08/15] drm/i915/audio: Nuke intel_eld_uptodate()

[Ville Syrjala]

From: Ville Syrjälä 

No idea why we do this ELD comparions on g4x before loading
the new ELD. Seems entirely pointless so just get rid of it.

Cc: Chaitanya Kumar Borah 
Cc: Kai Vehmanen 
Cc: Takashi Iwai 
Reviewed-by: Jani Nikula 
Reviewed-by: Kai Vehmanen 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_audio.c | 33 --
 1 file changed, 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index 093283fd1c28..7867eb670560 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -304,33 +304,6 @@ static int audio_config_hdmi_get_n(const struct 
intel_crtc_state *crtc_state,
return 0;
 }
 
-static bool intel_eld_uptodate(struct drm_connector *connector,
-  i915_reg_t reg_eldv, u32 bits_eldv,
-  i915_reg_t reg_elda, u32 bits_elda,
-  i915_reg_t reg_edid)
-{
-   struct drm_i915_private *i915 = to_i915(connector->dev);
-   const u8 *eld = connector->eld;
-   u32 tmp;
-   int i;
-
-   tmp = intel_de_read(i915, reg_eldv);
-   tmp &= bits_eldv;
-
-   if (!tmp)
-   return false;
-
-   tmp = intel_de_read(i915, reg_elda);
-   tmp &= ~bits_elda;
-   intel_de_write(i915, reg_elda, tmp);
-
-   for (i = 0; i < drm_eld_size(eld) / 4; i++)
-   if (intel_de_read(i915, reg_edid) != *((const u32 *)eld + i))
-   return false;
-
-   return true;
-}
-
 static void g4x_audio_codec_disable(struct intel_encoder *encoder,
const struct intel_crtc_state 
*old_crtc_state,
const struct drm_connector_state 
*old_conn_state)
@@ -354,12 +327,6 @@ static void g4x_audio_codec_enable(struct intel_encoder 
*encoder,
u32 tmp;
int len, i;
 
-   if (intel_eld_uptodate(connector,
-  G4X_AUD_CNTL_ST, G4X_ELD_VALID,
-  G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK,
-  G4X_HDMIW_HDMIEDID))
-   return;
-
tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
tmp &= ~(G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK);
len = REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp);
-- 
2.37.4

[Intel-gfx] [PATCH 01/15] drm/i915/audio: s/dev_priv/i915/

[Ville Syrjala]

From: Ville Syrjälä 

Rename the 'dev_priv' variables to 'i915' in the audio code
to match modern style conventions.

v2: Drop some needless braces in intel_audio_hooks_init()

Cc: Chaitanya Kumar Borah 
Cc: Kai Vehmanen 
Cc: Takashi Iwai 
Reviewed-by: Jani Nikula 
Reviewed-by: Kai Vehmanen 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_audio.c| 391 +-
 .../gpu/drm/i915/display/intel_audio_regs.h   |   2 +-
 2 files changed, 196 insertions(+), 197 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index aacbc6da84ef..aa70b3f075c3 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -250,7 +250,7 @@ static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state 
*crtc_state)
 {
-   struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+   struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
const struct drm_display_mode *adjusted_mode =
_state->hw.adjusted_mode;
int i;
@@ -260,17 +260,17 @@ static u32 audio_config_hdmi_pixel_clock(const struct 
intel_crtc_state *crtc_sta
break;
}
 
-   if (DISPLAY_VER(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500)
+   if (DISPLAY_VER(i915) < 12 && adjusted_mode->crtc_clock > 148500)
i = ARRAY_SIZE(hdmi_audio_clock);
 
if (i == ARRAY_SIZE(hdmi_audio_clock)) {
-   drm_dbg_kms(_priv->drm,
+   drm_dbg_kms(>drm,
"HDMI audio pixel clock setting for %d not found, 
falling back to defaults\n",
adjusted_mode->crtc_clock);
i = 1;
}
 
-   drm_dbg_kms(_priv->drm,
+   drm_dbg_kms(>drm,
"Configuring HDMI audio for pixel clock %d (0x%08x)\n",
hdmi_audio_clock[i].clock,
hdmi_audio_clock[i].config);
@@ -309,23 +309,23 @@ static bool intel_eld_uptodate(struct drm_connector 
*connector,
   i915_reg_t reg_elda, u32 bits_elda,
   i915_reg_t reg_edid)
 {
-   struct drm_i915_private *dev_priv = to_i915(connector->dev);
+   struct drm_i915_private *i915 = to_i915(connector->dev);
const u8 *eld = connector->eld;
u32 tmp;
int i;
 
-   tmp = intel_de_read(dev_priv, reg_eldv);
+   tmp = intel_de_read(i915, reg_eldv);
tmp &= bits_eldv;
 
if (!tmp)
return false;
 
-   tmp = intel_de_read(dev_priv, reg_elda);
+   tmp = intel_de_read(i915, reg_elda);
tmp &= ~bits_elda;
-   intel_de_write(dev_priv, reg_elda, tmp);
+   intel_de_write(i915, reg_elda, tmp);
 
for (i = 0; i < drm_eld_size(eld) / 4; i++)
-   if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld + 
i))
+   if (intel_de_read(i915, reg_edid) != *((const u32 *)eld + i))
return false;
 
return true;
@@ -335,33 +335,33 @@ static void g4x_audio_codec_disable(struct intel_encoder 
*encoder,
const struct intel_crtc_state 
*old_crtc_state,
const struct drm_connector_state 
*old_conn_state)
 {
-   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u32 eldv, tmp;
 
-   tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
+   tmp = intel_de_read(i915, G4X_AUD_VID_DID);
if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
eldv = G4X_ELDV_DEVCL_DEVBLC;
else
eldv = G4X_ELDV_DEVCTG;
 
/* Invalidate ELD */
-   tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
+   tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
tmp &= ~eldv;
-   intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
+   intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
 }
 
 static void g4x_audio_codec_enable(struct intel_encoder *encoder,
   const struct intel_crtc_state *crtc_state,
   const struct drm_connector_state *conn_state)
 {
-   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct drm_connector *connector = conn_state->connector;
const u8 *eld = connector->eld;
u32 eldv;
u32 tmp;
int len, i;
 
-   tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
+   tmp = intel_de_read(i915, G4X_AUD_VID_DID);
if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
eldv = G4X_ELDV_DEVCL_DEVBLC;
else
@@ -373,27 +373,27 @@ static 

[Intel-gfx] [PATCH 06/15] drm/i915/audio: Unify register bit naming

[Ville Syrjala]

From: Ville Syrjälä 

Rename a few g4x bits to match the ibx+ bits.

Cc: Chaitanya Kumar Borah 
Cc: Kai Vehmanen 
Cc: Takashi Iwai 
Reviewed-by: Jani Nikula 
Reviewed-by: Kai Vehmanen 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_audio.c  | 10 +-
 drivers/gpu/drm/i915/display/intel_audio_regs.h |  4 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index 29f2820c94c3..5d545d2ffb33 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -340,7 +340,7 @@ static void g4x_audio_codec_disable(struct intel_encoder 
*encoder,
 
/* Invalidate ELD */
tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
-   tmp &= ~G4X_ELDV;
+   tmp &= ~G4X_ELD_VALID;
intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
 }
 
@@ -355,13 +355,13 @@ static void g4x_audio_codec_enable(struct intel_encoder 
*encoder,
int len, i;
 
if (intel_eld_uptodate(connector,
-  G4X_AUD_CNTL_ST, G4X_ELDV,
-  G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
+  G4X_AUD_CNTL_ST, G4X_ELD_VALID,
+  G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK,
   G4X_HDMIW_HDMIEDID))
return;
 
tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
-   tmp &= ~(G4X_ELDV | G4X_ELD_ADDR_MASK);
+   tmp &= ~(G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK);
len = REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp);
intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
 
@@ -371,7 +371,7 @@ static void g4x_audio_codec_enable(struct intel_encoder 
*encoder,
   *((const u32 *)eld + i));
 
tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
-   tmp |= G4X_ELDV;
+   tmp |= G4X_ELD_VALID;
intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h 
b/drivers/gpu/drm/i915/display/intel_audio_regs.h
index b5684ed839be..4f432c2eb543 100644
--- a/drivers/gpu/drm/i915/display/intel_audio_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h
@@ -9,9 +9,9 @@
 #include "i915_reg_defs.h"
 
 #define G4X_AUD_CNTL_ST_MMIO(0x620B4)
-#define   G4X_ELDV REG_BIT(14)
+#define   G4X_ELD_VALIDREG_BIT(14)
 #define   G4X_ELD_BUFFER_SIZE_MASK REG_GENMASK(13, 9)
-#define   G4X_ELD_ADDR_MASKREG_GENMASK(8, 5)
+#define   G4X_ELD_ADDRESS_MASK REG_GENMASK(8, 5)
 #define   G4X_ELD_ACK  REG_BIT(4)
 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
 
-- 
2.37.4

[Intel-gfx] [PATCH 03/15] drm/i915/audio: Remove CL/BLC audio stuff

[Ville Syrjala]

From: Ville Syrjälä 

We don't use the audio code on crestline (CL) since it doesn't
support native HDMI output, and SDVO has it's own way of doing
audio.

And Bearlake-C (BLC) doesn't even exist in the real world, so
no point it trying to deal with it.

Cc: Chaitanya Kumar Borah 
Cc: Kai Vehmanen 
Cc: Takashi Iwai 
Reviewed-by: Jani Nikula 
Reviewed-by: Kai Vehmanen 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_audio.c| 23 ---
 .../gpu/drm/i915/display/intel_audio_regs.h   |  8 +--
 2 files changed, 6 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index c6e7cecc6690..b91167eaf71f 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -336,17 +336,11 @@ static void g4x_audio_codec_disable(struct intel_encoder 
*encoder,
const struct drm_connector_state 
*old_conn_state)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-   u32 eldv, tmp;
-
-   tmp = intel_de_read(i915, G4X_AUD_VID_DID);
-   if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
-   eldv = G4X_ELDV_DEVCL_DEVBLC;
-   else
-   eldv = G4X_ELDV_DEVCTG;
+   u32 tmp;
 
/* Invalidate ELD */
tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
-   tmp &= ~eldv;
+   tmp &= ~G4X_ELDV;
intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
 }
 
@@ -357,24 +351,17 @@ static void g4x_audio_codec_enable(struct intel_encoder 
*encoder,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct drm_connector *connector = conn_state->connector;
const u8 *eld = connector->eld;
-   u32 eldv;
u32 tmp;
int len, i;
 
-   tmp = intel_de_read(i915, G4X_AUD_VID_DID);
-   if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
-   eldv = G4X_ELDV_DEVCL_DEVBLC;
-   else
-   eldv = G4X_ELDV_DEVCTG;
-
if (intel_eld_uptodate(connector,
-  G4X_AUD_CNTL_ST, eldv,
+  G4X_AUD_CNTL_ST, G4X_ELDV,
   G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
   G4X_HDMIW_HDMIEDID))
return;
 
tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
-   tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
+   tmp &= ~(G4X_ELDV | G4X_ELD_ADDR_MASK);
len = (tmp >> 9) & 0x1f;/* ELD buffer size */
intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
 
@@ -384,7 +371,7 @@ static void g4x_audio_codec_enable(struct intel_encoder 
*encoder,
   *((const u32 *)eld + i));
 
tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
-   tmp |= eldv;
+   tmp |= G4X_ELDV;
intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h 
b/drivers/gpu/drm/i915/display/intel_audio_regs.h
index e25248cdac51..ebbdd0654919 100644
--- a/drivers/gpu/drm/i915/display/intel_audio_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h
@@ -8,14 +8,8 @@
 
 #include "i915_reg_defs.h"
 
-#define G4X_AUD_VID_DID_MMIO(DISPLAY_MMIO_BASE(i915) + 
0x62020)
-#define   INTEL_AUDIO_DEVCL0x808629FB
-#define   INTEL_AUDIO_DEVBLC   0x80862801
-#define   INTEL_AUDIO_DEVCTG   0x80862802
-
 #define G4X_AUD_CNTL_ST_MMIO(0x620B4)
-#define   G4X_ELDV_DEVCL_DEVBLC(1 << 13)
-#define   G4X_ELDV_DEVCTG  (1 << 14)
+#define   G4X_ELDV (1 << 14)
 #define   G4X_ELD_ADDR_MASK(0xf << 5)
 #define   G4X_ELD_ACK  (1 << 4)
 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
-- 
2.37.4

[Intel-gfx] [PATCH 00/15] drm/i915: Audio stuff

[Ville Syrjala]

From: Ville Syrjälä 

All the less controversional cleanups/fixes/etc. from the
earlier ELD precompute+state check series. So no actual
ELD precompute+state check here yet.

Ville Syrjälä (15):
  drm/i915/audio: s/dev_priv/i915/
  drm/i915/audio: Nuke leftover ROUNDING_FACTOR
  drm/i915/audio: Remove CL/BLC audio stuff
  drm/i915/audio: Extract struct ilk_audio_regs
  drm/i915/audio: Use REG_BIT() & co.
  drm/i915/audio: Unify register bit naming
  drm/i915/audio: Protect singleton register with a lock
  drm/i915/audio: Nuke intel_eld_uptodate()
  drm/i915/audio: Read ELD buffer size from hardware
  drm/i915/audio: Make sure we write the whole ELD buffer
  drm/i915/audio: Use u32* for ELD
  drm/i915/audio: Use intel_de_rmw() for most audio registers
  drm/i915/audio: Split "ELD valid" vs. audio PD on hsw+
  drm/i915/audio: Do the vblank waits
  drm/i915/sdvo: Extract intel_sdvo_has_audio()

 drivers/gpu/drm/i915/display/intel_audio.c| 660 +-
 .../gpu/drm/i915/display/intel_audio_regs.h   |  87 ++-
 drivers/gpu/drm/i915/display/intel_sdvo.c |  27 +-
 3 files changed, 384 insertions(+), 390 deletions(-)

-- 
2.37.4

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm: Analog TV Improvements (rev6)

[Patchwork]

== Series Details ==

Series: drm: Analog TV Improvements (rev6)
URL   : https://patchwork.freedesktop.org/series/107892/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/107892/revisions/6/mbox/ not 
applied
Applying: drm/tests: Add Kunit Helpers
Applying: drm/connector: Rename legacy TV property
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/drm_connector.c
M   drivers/gpu/drm/i915/display/intel_tv.c
M   include/drm/drm_connector.h
Falling back to patching base and 3-way merge...
Auto-merging include/drm/drm_connector.h
Auto-merging drivers/gpu/drm/i915/display/intel_tv.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_tv.c
Auto-merging drivers/gpu/drm/drm_connector.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0002 drm/connector: Rename legacy TV property
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

[Intel-gfx] ✗ Fi.CI.IGT: failure for Revert "drm/i915/uapi: expose GTT alignment"

[Patchwork]

== Series Details ==

Series: Revert "drm/i915/uapi: expose GTT alignment"
URL   : https://patchwork.freedesktop.org/series/110041/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12284_full -> Patchwork_110041v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110041v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110041v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110041v1_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@mock@requests:
- shard-skl:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-skl9/igt@i915_selftest@m...@requests.html

  
 Warnings 

  * igt@kms_color@ctm-0-75@pipe-d-edp-1:
- shard-tglb: [FAIL][2] ([i915#315] / [i915#6946]) -> 
[INCOMPLETE][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-tglb6/igt@kms_color@ctm-0...@pipe-d-edp-1.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-tglb8/igt@kms_color@ctm-0...@pipe-d-edp-1.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic:
- shard-skl:  [FAIL][4] ([i915#2346]) -> [INCOMPLETE][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-skl6/igt@kms_cursor_legacy@flip-vs-cur...@atomic.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-skl9/igt@kms_cursor_legacy@flip-vs-cur...@atomic.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_mmap_offset@clear@smem0:
- {shard-rkl}:[PASS][6] -> [INCOMPLETE][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-rkl-4/igt@gem_mmap_offset@cl...@smem0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-rkl-5/igt@gem_mmap_offset@cl...@smem0.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-rkl}:[PASS][8] -> [WARN][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-rkl-4/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html

  * igt@i915_pm_rc6_residency@rc6-idle@vecs0:
- {shard-rkl}:[PASS][10] -> [FAIL][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-rkl-4/igt@i915_pm_rc6_residency@rc6-i...@vecs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-i...@vecs0.html

  
Known issues


  Here are the changes found in Patchwork_110041v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-glk:  ([PASS][12], [PASS][13], [PASS][14], [PASS][15], 
[PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], 
[PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], 
[PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], 
[PASS][34], [PASS][35], [PASS][36]) -> ([PASS][37], [PASS][38], [PASS][39], 
[PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], 
[PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], 
[PASS][52], [PASS][53], [PASS][54], [FAIL][55], [PASS][56], [PASS][57], 
[PASS][58], [PASS][59], [PASS][60], [PASS][61]) ([i915#4392])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk9/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk9/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk9/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk8/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk8/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk8/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk7/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk7/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk7/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk6/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk6/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk6/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/shard-glk5/boot.html
 

[Intel-gfx] ✗ Fi.CI.BAT: failure for freezer, sched: Rewrite core freezer logic fix (rev2)

[Patchwork]

== Series Details ==

Series: freezer, sched: Rewrite core freezer logic fix (rev2)
URL   : https://patchwork.freedesktop.org/series/110173/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12297 -> Patchwork_110173v2


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110173v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110173v2, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/index.html

Participating hosts (40 -> 40)
--

  Additional (3): fi-cml-u2 fi-bdw-gvtdvm fi-bxt-dsi 
  Missing(3): fi-ctg-p8600 fi-hsw-4770 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110173v2:

### IGT changes ###

 Possible regressions 

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-bdw-gvtdvm:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-bdw-gvtdvm/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-cml-u2:  NOTRUN -> [INCOMPLETE][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-cml-u2/igt@i915_susp...@basic-s3-without-i915.html

  
Known issues


  Here are the changes found in Patchwork_110173v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][3] ([i915#1208]) +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-cml-u2:  NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-cml-u2/igt@gem_huc_c...@huc-copy.html
- fi-bxt-dsi: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-bxt-dsi/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-apl-guc/igt@gem_lmem_swapp...@basic.html
- fi-bdw-gvtdvm:  NOTRUN -> [SKIP][7] ([fdo#109271]) +37 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-bdw-gvtdvm/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-cml-u2:  NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-cml-u2/igt@gem_lmem_swapp...@parallel-random-engines.html
- fi-bxt-dsi: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-bxt-dsi/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_tiled_blits@basic:
- fi-bxt-dsi: NOTRUN -> [SKIP][10] ([fdo#109271]) +12 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-bxt-dsi/igt@gem_tiled_bl...@basic.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-cml-u2:  NOTRUN -> [DMESG-FAIL][11] ([i915#5334])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-cml-u2/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2:  NOTRUN -> [SKIP][12] ([fdo#109284] / [fdo#111827]) +7 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-apl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
- fi-bxt-dsi: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-bxt-dsi/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-bdw-gvtdvm:  NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-bdw-gvtdvm/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-cml-u2:  NOTRUN -> [SKIP][16] ([i915#4213])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110173v2/fi-cml-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * 

[Intel-gfx] [PATCH] drm/i915/selftests: add over-fetch padding to store_dw batchbuffer

[Andrzej Hajda]

Due to batch buffer over-fetch mechanism up to 4KB beyond the last
command in the buffer can be read by engine executing the buffer.
On the other side if memory is accessed during TLB invalidation proper
TLB invalidation is not guaranteed. Both conditions can occur when two
buffers are bound to adjacent PTEs and during execution of the 1st buffer
(overfetch tries to access PTE of the 2nd buffer) 2nd buffer is removed
(memory is unmapped and TLB is invalidated during memory access, not fully).
As a result engine tries to access unmapped memory and causes DMAR faults
and catastrophic errors.
The simplest solution of this issue is to allocate buffers big enough, to
avoid over-fetch crossing buffer boundary.

BSpec: 45718, 44393

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5278
Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c 
b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
index 3c55e77b0f1b00..42966e3855a5a5 100644
--- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
+++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
@@ -44,13 +44,14 @@ igt_emit_store_dw(struct i915_vma *vma,
  unsigned long count,
  u32 val)
 {
+#define BB_OVERFETCH_SIZE (PAGE_SIZE)
struct drm_i915_gem_object *obj;
const int ver = GRAPHICS_VER(vma->vm->i915);
unsigned long n, size;
u32 *cmd;
int err;
 
-   size = (4 * count + 1) * sizeof(u32);
+   size = (4 * count + 1) * sizeof(u32) + BB_OVERFETCH_SIZE;
size = round_up(size, PAGE_SIZE);
obj = i915_gem_object_create_internal(vma->vm->i915, size);
if (IS_ERR(obj))
-- 
2.34.1

[Intel-gfx] [PATCH v6 22/23] drm/vc4: vec: Add support for more analog TV standards

[maxime]

From: Mateusz Kwiatkowski 

Add support for the following composite output modes (all of them are
somewhat more obscure than the previously defined ones):

- NTSC_443 - NTSC-style signal with the chroma subcarrier shifted to
  4.43361875 MHz (the PAL subcarrier frequency). Never used for
  broadcasting, but sometimes used as a hack to play NTSC content in PAL
  regions (e.g. on VCRs).
- PAL_N - PAL with alternative chroma subcarrier frequency,
  3.58205625 MHz. Used as a broadcast standard in Argentina, Paraguay
  and Uruguay to fit 576i50 with colour in 6 MHz channel raster.
- PAL60 - 480i60 signal with PAL-style color at normal European PAL
  frequency. Another non-standard, non-broadcast mode, used in similar
  contexts as NTSC_443. Some displays support one but not the other.
- SECAM - French frequency-modulated analog color standard; also have
  been broadcast in Eastern Europe and various parts of Africa and Asia.
  Uses the same 576i50 timings as PAL.

Also added some comments explaining color subcarrier frequency
registers.

Acked-by: Noralf Trønnes 
Signed-off-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 

---
Changes in v6:
- Support PAL60 again
---
 drivers/gpu/drm/vc4/vc4_vec.c | 111 --
 1 file changed, 107 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c
index 1dda451c8def..d82aef168075 100644
--- a/drivers/gpu/drm/vc4/vc4_vec.c
+++ b/drivers/gpu/drm/vc4/vc4_vec.c
@@ -46,6 +46,7 @@
 #define VEC_CONFIG0_YDEL(x)((x) << 26)
 #define VEC_CONFIG0_CDEL_MASK  GENMASK(25, 24)
 #define VEC_CONFIG0_CDEL(x)((x) << 24)
+#define VEC_CONFIG0_SECAM_STD  BIT(21)
 #define VEC_CONFIG0_PBPR_FIL   BIT(18)
 #define VEC_CONFIG0_CHROMA_GAIN_MASK   GENMASK(17, 16)
 #define VEC_CONFIG0_CHROMA_GAIN_UNITY  (0 << 16)
@@ -76,6 +77,27 @@
 #define VEC_SOFT_RESET 0x10c
 #define VEC_CLMP0_START0x144
 #define VEC_CLMP0_END  0x148
+
+/*
+ * These set the color subcarrier frequency
+ * if VEC_CONFIG1_CUSTOM_FREQ is enabled.
+ *
+ * VEC_FREQ1_0 contains the most significant 16-bit half-word,
+ * VEC_FREQ3_2 contains the least significant 16-bit half-word.
+ * 0x8000 seems to be equivalent to the pixel clock
+ * (which itself is the VEC clock divided by 8).
+ *
+ * Reference values (with the default pixel clock of 13.5 MHz):
+ *
+ * NTSC  (3579545.[45] Hz) - 0x21F07C1F
+ * PAL   (4433618.75 Hz)   - 0x2A098ACB
+ * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3
+ * PAL-N (3582056.25 Hz)   - 0x21F69446
+ *
+ * NOTE: For SECAM, it is used as the Dr center frequency,
+ * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not;
+ * that is specified as 4406250 Hz, which corresponds to 0x29C71C72.
+ */
 #define VEC_FREQ3_20x180
 #define VEC_FREQ1_00x184
 
@@ -118,6 +140,14 @@
 
 #define VEC_INTERRUPT_CONTROL  0x190
 #define VEC_INTERRUPT_STATUS   0x194
+
+/*
+ * Db center frequency for SECAM; the clock for this is the same as for
+ * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency.
+ *
+ * This is specified as 425 Hz, which corresponds to 0x284BDA13.
+ * That is also the default value, so no need to set it explicitly.
+ */
 #define VEC_FCW_SECAM_B0x198
 #define VEC_SECAM_GAIN_VAL 0x19c
 
@@ -197,10 +227,15 @@ enum vc4_vec_tv_mode_id {
VC4_VEC_TV_MODE_NTSC_J,
VC4_VEC_TV_MODE_PAL,
VC4_VEC_TV_MODE_PAL_M,
+   VC4_VEC_TV_MODE_NTSC_443,
+   VC4_VEC_TV_MODE_PAL_60,
+   VC4_VEC_TV_MODE_PAL_N,
+   VC4_VEC_TV_MODE_SECAM,
 };
 
 struct vc4_vec_tv_mode {
unsigned int mode;
+   u16 expected_htotal;
u32 config0;
u32 config1;
u32 custom_freq;
@@ -236,35 +271,68 @@ static const struct debugfs_reg32 vec_regs[] = {
 static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
{
.mode = DRM_MODE_TV_MODE_NTSC,
+   .expected_htotal = 858,
.config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
+   {
+   .mode = DRM_MODE_TV_MODE_NTSC_443,
+   .expected_htotal = 858,
+   .config0 = VEC_CONFIG0_NTSC_STD,
+   .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
+   .custom_freq = 0x2a098acb,
+   },
{
.mode = DRM_MODE_TV_MODE_NTSC_J,
+   .expected_htotal = 858,
.config0 = VEC_CONFIG0_NTSC_STD,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
{
.mode = DRM_MODE_TV_MODE_PAL,
+   .expected_htotal = 864,
.config0 = VEC_CONFIG0_PAL_BDGHI_STD,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
+   {
+   /* PAL-60 */
+   

[Intel-gfx] [PATCH v6 21/23] drm/vc4: vec: Convert to the new TV mode property

[maxime]

Now that the core can deal fine with analog TV modes, let's convert the vc4
VEC driver to leverage those new features.

We've added some backward compatibility to support the old TV mode property
and translate it into the new TV norm property. We're also making use of
the new analog TV atomic_check helper to make sure we trigger a modeset
whenever the TV mode is updated.

Acked-by: Noralf Trønnes 
Signed-off-by: Maxime Ripard 

---
Changes in v6:
- Use new get_modes helper

Changes in v5:
- Renamed tv_mode_names into legacy_tv_mode_names

Changes in v4:
- Removed the count variable in .get_modes
---
 drivers/gpu/drm/vc4/vc4_vec.c | 185 +-
 1 file changed, 129 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c
index bfa8a58dba30..1dda451c8def 100644
--- a/drivers/gpu/drm/vc4/vc4_vec.c
+++ b/drivers/gpu/drm/vc4/vc4_vec.c
@@ -172,6 +172,8 @@ struct vc4_vec {
 
struct clk *clock;
 
+   struct drm_property *legacy_tv_mode_property;
+
struct debugfs_regset32 regset;
 };
 
@@ -184,6 +186,12 @@ encoder_to_vc4_vec(struct drm_encoder *encoder)
return container_of(encoder, struct vc4_vec, encoder.base);
 }
 
+static inline struct vc4_vec *
+connector_to_vc4_vec(struct drm_connector *connector)
+{
+   return container_of(connector, struct vc4_vec, connector);
+}
+
 enum vc4_vec_tv_mode_id {
VC4_VEC_TV_MODE_NTSC,
VC4_VEC_TV_MODE_NTSC_J,
@@ -192,7 +200,7 @@ enum vc4_vec_tv_mode_id {
 };
 
 struct vc4_vec_tv_mode {
-   const struct drm_display_mode *mode;
+   unsigned int mode;
u32 config0;
u32 config1;
u32 custom_freq;
@@ -225,43 +233,51 @@ static const struct debugfs_reg32 vec_regs[] = {
VC4_REG32(VEC_DAC_MISC),
 };
 
-static const struct drm_display_mode ntsc_mode = {
-   DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 13500,
-720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,
-480, 480 + 7, 480 + 7 + 6, 525, 0,
-DRM_MODE_FLAG_INTERLACE)
-};
-
-static const struct drm_display_mode pal_mode = {
-   DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 13500,
-720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
-576, 576 + 4, 576 + 4 + 6, 625, 0,
-DRM_MODE_FLAG_INTERLACE)
-};
-
 static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
-   [VC4_VEC_TV_MODE_NTSC] = {
-   .mode = _mode,
+   {
+   .mode = DRM_MODE_TV_MODE_NTSC,
.config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
-   [VC4_VEC_TV_MODE_NTSC_J] = {
-   .mode = _mode,
+   {
+   .mode = DRM_MODE_TV_MODE_NTSC_J,
.config0 = VEC_CONFIG0_NTSC_STD,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
-   [VC4_VEC_TV_MODE_PAL] = {
-   .mode = _mode,
+   {
+   .mode = DRM_MODE_TV_MODE_PAL,
.config0 = VEC_CONFIG0_PAL_BDGHI_STD,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
-   [VC4_VEC_TV_MODE_PAL_M] = {
-   .mode = _mode,
+   {
+   .mode = DRM_MODE_TV_MODE_PAL_M,
.config0 = VEC_CONFIG0_PAL_M_STD,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
 };
 
+static inline const struct vc4_vec_tv_mode *
+vc4_vec_tv_mode_lookup(unsigned int mode)
+{
+   unsigned int i;
+
+   for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) {
+   const struct vc4_vec_tv_mode *tv_mode = _vec_tv_modes[i];
+
+   if (tv_mode->mode == mode)
+   return tv_mode;
+   }
+
+   return NULL;
+}
+
+static const struct drm_prop_enum_list legacy_tv_mode_names[] = {
+   { VC4_VEC_TV_MODE_NTSC, "NTSC", },
+   { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", },
+   { VC4_VEC_TV_MODE_PAL, "PAL", },
+   { VC4_VEC_TV_MODE_PAL_M, "PAL-M", },
+};
+
 static enum drm_connector_status
 vc4_vec_connector_detect(struct drm_connector *connector, bool force)
 {
@@ -274,21 +290,74 @@ static void vc4_vec_connector_reset(struct drm_connector 
*connector)
drm_atomic_helper_connector_tv_reset(connector);
 }
 
-static int vc4_vec_connector_get_modes(struct drm_connector *connector)
+static int
+vc4_vec_connector_set_property(struct drm_connector *connector,
+  struct drm_connector_state *state,
+  struct drm_property *property,
+  uint64_t val)
 {
-   struct drm_connector_state *state = connector->state;
-   struct drm_display_mode *mode;
-
-   mode = drm_mode_duplicate(connector->dev,
- vc4_vec_tv_modes[state->tv.legacy_mode].mode);
-   if (!mode) {
-   DRM_ERROR("Failed to create a new display mode\n");
-   return -ENOMEM;
+   struct