Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: Enable Idle Messaging for GSC CS

[Nilawar, Badal]

On 18-11-2022 03:44, Rodrigo Vivi wrote:

On Tue, Nov 15, 2022 at 07:14:40PM +0530, Badal Nilawar wrote:

From: Vinay Belgaumkar 

By defaut idle mesaging is disabled for GSC CS so to unblock RC6
entry on media tile idle messaging need to be enabled.

v2:
  - Fix review comments (Vinay)
  - Set GSC idle hysterisis to 5 us (Badal)

Bspec: 71496

Cc: Daniele Ceraolo Spurio 
Signed-off-by: Vinay Belgaumkar 
Signed-off-by: Badal Nilawar 
---
  drivers/gpu/drm/i915/gt/intel_engine_pm.c | 18 ++
  drivers/gpu/drm/i915/gt/intel_gt_regs.h   |  4 
  2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c 
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index b0a4a2dbe3ee..5522885b2db0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -15,6 +15,22 @@
  #include "intel_rc6.h"
  #include "intel_ring.h"
  #include "shmem_utils.h"
+#include "intel_gt_regs.h"
+
+static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)
+{
+   struct drm_i915_private *i915 = engine->i915;
+
+   if (IS_METEORLAKE(i915) && engine->id == GSC0) {
+   intel_uncore_write(engine->gt->uncore,
+  RC_PSMI_CTRL_GSCCS,
+  _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));


disable the disable? shouldn't be enable the disable?
1 = disable, no?


+   /* 5 us hysterisis */


could you please mention here in the comment that 0xA = 5 us per spec?
I got confused again even though you had explained already...

Sure I will add the comment "0xA=5 us as per spec"


BTW, how reliable that spec is? Because according to that same line
we should be setting the bit 16, not the bit 0 in the previous reg!

Bit 16 is mask bit. Bit 0 need to be cleared to enable Idle messaging.
Bit[0] = 1 Disable Idle Messaging / 0 Enable Idle Messaging.

Regards,
Badal



+   intel_uncore_write(engine->gt->uncore,
+  PWRCTX_MAXCNT_GSCCS,
+  0xA);
+   }
+}
  
  static void dbg_poison_ce(struct intel_context *ce)

  {
@@ -275,6 +291,8 @@ void intel_engine_init__pm(struct intel_engine_cs *engine)
  
  	intel_wakeref_init(>wakeref, rpm, _ops);

intel_engine_init_heartbeat(engine);
+
+   intel_gsc_idle_msg_enable(engine);
  }
  
  /**

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 07031e03f80c..20472eb15364 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -913,6 +913,10 @@
  #define  MSG_IDLE_FW_MASK REG_GENMASK(13, 9)
  #define  MSG_IDLE_FW_SHIFT9
  
+#define	RC_PSMI_CTRL_GSCCS	_MMIO(0x11a050)

+#define  IDLE_MSG_DISABLE  BIT(0)
+#define PWRCTX_MAXCNT_GSCCS_MMIO(0x11a054)
+
  #define FORCEWAKE_MEDIA_GEN9  _MMIO(0xa270)
  #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
  
--

2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for Add module oriented dmesg output

[Patchwork]

== Series Details ==

Series: Add module oriented dmesg output
URL   : https://patchwork.freedesktop.org/series/111050/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12397 -> Patchwork_111050v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/index.html

Participating hosts (31 -> 37)
--

  Additional (11): bat-dg1-7 bat-dg1-6 bat-dg2-8 bat-adlm-1 bat-dg2-9 
bat-adlp-6 bat-adln-1 bat-rplp-1 bat-rpls-2 bat-dg2-11 bat-jsl-1 
  Missing(5): fi-kbl-soraka fi-ilk-m540 fi-ctg-p8600 fi-hsw-4770 
fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_111050v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@hugepages:
- {bat-rpls-2}:   NOTRUN -> [DMESG-WARN][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-rpls-2/igt@i915_selftest@l...@hugepages.html

  * igt@i915_selftest@live@slpc:
- {bat-rpls-2}:   NOTRUN -> [DMESG-FAIL][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html

  
Known issues


  Here are the changes found in Patchwork_111050v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_mmap@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][3] ([i915#4083])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@gem_m...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][4] ([i915#4079]) +1 similar issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html
- fi-apl-guc: [PASS][5] -> [INCOMPLETE][6] ([i915#7056])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][7] ([i915#4077]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6:  NOTRUN -> [SKIP][8] ([i915#1155])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
- bat-dg1-6:  NOTRUN -> [SKIP][9] ([i915#6621])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@i915_pm_...@basic-api.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6:  NOTRUN -> [SKIP][10] ([i915#4215])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6:  NOTRUN -> [SKIP][11] ([i915#4212]) +7 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_chamelium@hdmi-crc-fast:
- bat-dg1-6:  NOTRUN -> [SKIP][12] ([fdo#111827]) +8 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-dg1-6:  NOTRUN -> [SKIP][13] ([i915#4103] / [i915#4213])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-6:  NOTRUN -> [SKIP][14] ([fdo#109285])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_psr@sprite_plane_onoff:
- bat-dg1-6:  NOTRUN -> [SKIP][15] ([i915#1072] / [i915#4078]) +3 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-6:  NOTRUN -> [SKIP][16] ([i915#3555])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-gtt:
- bat-dg1-6:  NOTRUN -> [SKIP][17] ([i915#3708] / [i915#4077]) +1 
similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@prime_v...@basic-gtt.html

  * igt@prime_vgem@basic-userptr:
- bat-dg1-6:  NOTRUN -> [SKIP][18] ([i915#3708] / [i915#4873])
   [18]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add module oriented dmesg output

[Patchwork]

== Series Details ==

Series: Add module oriented dmesg output
URL   : https://patchwork.freedesktop.org/series/111050/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add module oriented dmesg output

[Patchwork]

== Series Details ==

Series: Add module oriented dmesg output
URL   : https://patchwork.freedesktop.org/series/111050/
State : warning

== Summary ==

Error: dim checkpatch failed
910945e13c6a drm/i915/gt: Start adding module oriented dmesg output
-:229: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible 
side-effects?
#229: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:16:
+#define gt_err(_gt, _fmt, ...) \
+   drm_err(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)

-:232: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible 
side-effects?
#232: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:19:
+#define gt_warn(_gt, _fmt, ...) \
+   drm_warn(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, 
##__VA_ARGS__)

-:235: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible 
side-effects?
#235: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:22:
+#define gt_notice(_gt, _fmt, ...) \
+   drm_notice(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, 
##__VA_ARGS__)

-:238: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible 
side-effects?
#238: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:25:
+#define gt_info(_gt, _fmt, ...) \
+   drm_info(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, 
##__VA_ARGS__)

-:241: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible 
side-effects?
#241: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:28:
+#define gt_dbg(_gt, _fmt, ...) \
+   drm_dbg(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)

-:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible 
side-effects?
#244: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:31:
+#define gt_probe_error(_gt, _fmt, ...) \
+   do { \
+   if (i915_error_injected()) \
+   gt_dbg(_gt, _fmt, ##__VA_ARGS__); \
+   else \
+   gt_err(_gt, _fmt, ##__VA_ARGS__); \
+   } while (0)

-:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_fmt' - possible 
side-effects?
#244: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:31:
+#define gt_probe_error(_gt, _fmt, ...) \
+   do { \
+   if (i915_error_injected()) \
+   gt_dbg(_gt, _fmt, ##__VA_ARGS__); \
+   else \
+   gt_err(_gt, _fmt, ##__VA_ARGS__); \
+   } while (0)

-:258: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible 
side-effects?
#258: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:45:
+#define gt_WARN(_gt, _condition, _fmt, ...) \
+   drm_WARN(&(_gt)->i915->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, 
##__VA_ARGS__)

-:261: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible 
side-effects?
#261: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:48:
+#define gt_WARN_ONCE(_gt, _condition, _fmt, ...) \
+   drm_WARN_ONCE(&(_gt)->i915->drm, _condition, "GT%u: " _fmt, 
(_gt)->info.id, ##__VA_ARGS__)

total: 0 errors, 0 warnings, 9 checks, 227 lines checked
0824d2802a9d drm/i915/huc: Add HuC specific debug print wrappers
-:146: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_huc' - possible 
side-effects?
#146: FILE: drivers/gpu/drm/i915/gt/uc/intel_huc.h:34:
+#define huc_probe_error(_huc, _fmt, ...) \
+   do { \
+   if (i915_error_injected()) \
+   huc_dbg(_huc, _fmt, ##__VA_ARGS__); \
+   else \
+   huc_err(_huc, _fmt, ##__VA_ARGS__); \
+   } while (0)

-:146: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_fmt' - possible 
side-effects?
#146: FILE: drivers/gpu/drm/i915/gt/uc/intel_huc.h:34:
+#define huc_probe_error(_huc, _fmt, ...) \
+   do { \
+   if (i915_error_injected()) \
+   huc_dbg(_huc, _fmt, ##__VA_ARGS__); \
+   else \
+   huc_err(_huc, _fmt, ##__VA_ARGS__); \
+   } while (0)

total: 0 errors, 0 warnings, 2 checks, 129 lines checked
d0ae6abfafaa drm/i915/guc: Add GuC specific debug print wrappers
-:149: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_guc' - possible 
side-effects?
#149: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc.h:42:
+#define guc_probe_error(_guc, _fmt, ...) \
+   do { \
+   if (i915_error_injected()) \
+   guc_dbg(_guc, _fmt, ##__VA_ARGS__); \
+   else \
+   guc_err(_guc, _fmt, ##__VA_ARGS__); \
+   } while (0)

-:149: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_fmt' - possible 
side-effects?
#149: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc.h:42:
+#define guc_probe_error(_guc, _fmt, ...) \
+   do { \
+   if (i915_error_injected()) \
+   guc_dbg(_guc, _fmt, ##__VA_ARGS__); \
+   else \
+   guc_err(_guc, _fmt, ##__VA_ARGS__); \
+   } while (0)

-:290: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#290: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:621:
if (!caplist) {
+   guc_dbg(guc, "capture: Failed to alloc cached 

[Intel-gfx] [PATCH v2 2/5] drm/i915/huc: Add HuC specific debug print wrappers

[John . C . Harrison]

From: John Harrison 

Create a set of HuC printers and start using them.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_huc.c | 31 ++
 drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 +++
 2 files changed, 35 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index be855811d85df..0bbbc7192da63 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -107,11 +107,9 @@ static enum hrtimer_restart 
huc_delayed_load_timer_callback(struct hrtimer *hrti
 
if (!intel_huc_is_authenticated(huc)) {
if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_GSC)
-   drm_notice(_to_gt(huc)->i915->drm,
-  "timed out waiting for MEI GSC init to load 
HuC\n");
+   huc_notice(huc, "Timed out waiting for MEI GSC init to 
load FW\n");
else if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_PXP)
-   drm_notice(_to_gt(huc)->i915->drm,
-  "timed out waiting for MEI PXP init to load 
HuC\n");
+   huc_notice(huc, "Timed out waiting for MEI PXP init to 
load FW\n");
else
MISSING_CASE(huc->delayed_load.status);
 
@@ -174,8 +172,7 @@ static int gsc_notifier(struct notifier_block *nb, unsigned 
long action, void *d
 
case BUS_NOTIFY_DRIVER_NOT_BOUND: /* mei driver fails to be bound */
case BUS_NOTIFY_UNBIND_DRIVER: /* mei driver about to be unbound */
-   drm_info(_to_gt(huc)->i915->drm,
-"mei driver not bound, disabling HuC load\n");
+   huc_info(huc, "- mei driver not bound, disabling HuC load\n");
gsc_init_error(huc);
break;
}
@@ -193,8 +190,7 @@ void intel_huc_register_gsc_notifier(struct intel_huc *huc, 
struct bus_type *bus
huc->delayed_load.nb.notifier_call = gsc_notifier;
ret = bus_register_notifier(bus, >delayed_load.nb);
if (ret) {
-   drm_err(_to_gt(huc)->i915->drm,
-   "failed to register GSC notifier\n");
+   huc_err(huc, "Failed to register GSC notifier\n");
huc->delayed_load.nb.notifier_call = NULL;
gsc_init_error(huc);
}
@@ -284,8 +280,7 @@ static int check_huc_loading_mode(struct intel_huc *huc)
  GSC_LOADS_HUC;
 
if (fw_needs_gsc != hw_uses_gsc) {
-   drm_err(>i915->drm,
-   "mismatch between HuC FW (%s) and HW (%s) load modes\n",
+   huc_err(huc, "Mismatch between FW (%s) and HW (%s) load 
modes\n",
HUC_LOAD_MODE_STRING(fw_needs_gsc),
HUC_LOAD_MODE_STRING(hw_uses_gsc));
return -ENOEXEC;
@@ -294,19 +289,17 @@ static int check_huc_loading_mode(struct intel_huc *huc)
/* make sure we can access the GSC via the mei driver if we need it */
if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) && 
IS_ENABLED(CONFIG_INTEL_MEI_GSC)) &&
fw_needs_gsc) {
-   drm_info(>i915->drm,
-"Can't load HuC due to missing MEI modules\n");
+   huc_info(huc, "Can't load due to missing MEI modules\n");
return -EIO;
}
 
-   drm_dbg(>i915->drm, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
+   huc_dbg(huc, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
 
return 0;
 }
 
 int intel_huc_init(struct intel_huc *huc)
 {
-   struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
int err;
 
err = check_huc_loading_mode(huc);
@@ -323,7 +316,7 @@ int intel_huc_init(struct intel_huc *huc)
 
 out:
intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_INIT_FAIL);
-   drm_info(>drm, "HuC init failed with %d\n", err);
+   huc_info(huc, "init failed with %d\n", err);
return err;
 }
 
@@ -366,13 +359,13 @@ int intel_huc_wait_for_auth_complete(struct intel_huc 
*huc)
delayed_huc_load_complete(huc);
 
if (ret) {
-   drm_err(>i915->drm, "HuC: Firmware not verified %d\n", ret);
+   huc_err(huc, "firmware not verified %d\n", ret);
intel_uc_fw_change_status(>fw, 
INTEL_UC_FIRMWARE_LOAD_FAIL);
return ret;
}
 
intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_RUNNING);
-   drm_info(>i915->drm, "HuC authenticated\n");
+   huc_info(huc, "authenticated\n");
return 0;
 }
 
@@ -407,7 +400,7 @@ int intel_huc_auth(struct intel_huc *huc)
 
ret = intel_guc_auth_huc(guc, intel_guc_ggtt_offset(guc, 
huc->fw.rsa_data));
if (ret) {
-   DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
+   huc_err(huc, "auth request not acked by GuC: %d\n", ret);

[Intel-gfx] [PATCH v2 3/5] drm/i915/guc: Add GuC specific debug print wrappers

[John . C . Harrison]

From: John Harrison 

Create a set of GuC printers and start using them.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.c| 32 --
 drivers/gpu/drm/i915/gt/uc/intel_guc.h| 35 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c|  8 +--
 .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 48 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +++---
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 37 ++-
 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c |  7 +--
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 55 +++-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +--
 drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +-
 .../drm/i915/gt/uc/selftest_guc_hangcheck.c   | 22 +++
 .../drm/i915/gt/uc/selftest_guc_multi_lrc.c   | 10 +--
 12 files changed, 179 insertions(+), 190 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 52aede324788e..d9972510ee29b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -94,8 +94,8 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc)
assert_rpm_wakelock_held(>i915->runtime_pm);
 
spin_lock_irq(gt->irq_lock);
-   WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
-gt->pm_guc_events);
+   guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
+gt->pm_guc_events);
gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
spin_unlock_irq(gt->irq_lock);
 
@@ -339,7 +339,7 @@ static void guc_init_params(struct intel_guc *guc)
params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
 
for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
-   DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
+   guc_dbg(guc, "init param[%2d] = %#x\n", i, params[i]);
 }
 
 /*
@@ -451,7 +451,7 @@ int intel_guc_init(struct intel_guc *guc)
intel_uc_fw_fini(>fw);
 out:
intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_INIT_FAIL);
-   i915_probe_error(gt->i915, "failed with %d\n", ret);
+   guc_probe_error(guc, "init failed with %d\n", ret);
return ret;
 }
 
@@ -484,7 +484,6 @@ void intel_guc_fini(struct intel_guc *guc)
 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
u32 *response_buf, u32 response_buf_size)
 {
-   struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
u32 header;
int i;
@@ -519,8 +518,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 
*request, u32 len,
   10, 10, );
if (unlikely(ret)) {
 timeout:
-   drm_err(>drm, "mmio request %#x: no reply %x\n",
-   request[0], header);
+   guc_err(guc, "mmio request %#x: no reply %x\n", request[0], 
header);
goto out;
}
 
@@ -541,8 +539,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 
*request, u32 len,
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 
GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
 
-   drm_dbg(>drm, "mmio request %#x: retrying, reason %u\n",
-   request[0], reason);
+   guc_dbg(guc, "mmio request %#x: retrying, reason %u\n", 
request[0], reason);
goto retry;
}
 
@@ -550,16 +547,14 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 
*request, u32 len,
u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
 
-   drm_err(>drm, "mmio request %#x: failure %x/%u\n",
-   request[0], error, hint);
+   guc_err(guc, "mmio request %#x: failure %x/%u\n", request[0], 
error, hint);
ret = -ENXIO;
goto out;
}
 
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 
GUC_HXG_TYPE_RESPONSE_SUCCESS) {
 proto:
-   drm_err(>drm, "mmio request %#x: unexpected reply %#x\n",
-   request[0], header);
+   guc_err(guc, "mmio request %#x: unexpected reply %#x\n", 
request[0], header);
ret = -EPROTO;
goto out;
}
@@ -601,9 +596,9 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc 
*guc,
msg = payload[0] & guc->msg_enabled_mask;
 
if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)
-   drm_err(_to_gt(guc)->i915->drm, "Received early GuC crash 
dump notification!\n");
+   guc_err(guc, "early notification: Crash dump!\n");
if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)
-   drm_err(_to_gt(guc)->i915->drm, "Received early GuC 
exception notification!\n");
+  

[Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers

[John . C . Harrison]

From: John Harrison 

Re-work the existing GuC CT printers and extend as required to match
the new wrapping scheme.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++---
 1 file changed, 113 insertions(+), 109 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 2b22065e87bf9..9d404fb377637 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -18,31 +18,49 @@ static inline struct intel_guc *ct_to_guc(struct 
intel_guc_ct *ct)
return container_of(ct, struct intel_guc, ct);
 }
 
-static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
-{
-   return guc_to_gt(ct_to_guc(ct));
-}
-
 static inline struct drm_i915_private *ct_to_i915(struct intel_guc_ct *ct)
 {
-   return ct_to_gt(ct)->i915;
-}
+   struct intel_guc *guc = ct_to_guc(ct);
+   struct intel_gt *gt = guc_to_gt(guc);
 
-static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
-{
-   return _to_i915(ct)->drm;
+   return gt->i915;
 }
 
-#define CT_ERROR(_ct, _fmt, ...) \
-   drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+#define ct_err(_ct, _fmt, ...) \
+   guc_err(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_warn(_ct, _fmt, ...) \
+   guc_warn(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_notice(_ct, _fmt, ...) \
+   guc_notice(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_info(_ct, _fmt, ...) \
+   guc_info(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
 #ifdef CONFIG_DRM_I915_DEBUG_GUC
-#define CT_DEBUG(_ct, _fmt, ...) \
-   drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+#define ct_dbg(_ct, _fmt, ...) \
+   guc_dbg(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
 #else
-#define CT_DEBUG(...)  do { } while (0)
+#define ct_dbg(...)do { } while (0)
 #endif
-#define CT_PROBE_ERROR(_ct, _fmt, ...) \
-   i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+
+#define ct_probe_error(_ct, _fmt, ...) \
+   do { \
+   if (i915_error_injected()) \
+   ct_dbg(_ct, _fmt, ##__VA_ARGS__); \
+   else \
+   ct_err(_ct, _fmt, ##__VA_ARGS__); \
+   } while (0)
+
+#define ct_WARN_ON(_ct, _condition) \
+   ct_WARN(_ct, _condition, "%s", "ct_WARN_ON(" __stringify(_condition) 
")")
+
+#define ct_WARN(_ct, _condition, _fmt, ...) \
+   guc_WARN(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_WARN_ONCE(_ct, _condition, _fmt, ...) \
+   guc_WARN_ONCE(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
 
 /**
  * DOC: CTB Blob
@@ -170,7 +188,7 @@ static int ct_control_enable(struct intel_guc_ct *ct, bool 
enable)
err = guc_action_control_ctb(ct_to_guc(ct), enable ?
 GUC_CTB_CONTROL_ENABLE : 
GUC_CTB_CONTROL_DISABLE);
if (unlikely(err))
-   CT_PROBE_ERROR(ct, "Failed to control/%s CTB (%pe)\n",
+   ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
   str_enable_disable(enable), ERR_PTR(err));
 
return err;
@@ -201,7 +219,7 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool 
send,
   size);
if (unlikely(err))
 failed:
-   CT_PROBE_ERROR(ct, "Failed to register %s buffer (%pe)\n",
+   ct_probe_error(ct, "Failed to register %s buffer (%pe)\n",
   send ? "SEND" : "RECV", ERR_PTR(err));
 
return err;
@@ -235,21 +253,21 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE + 
CTB_G2H_BUFFER_SIZE;
err = intel_guc_allocate_and_map_vma(guc, blob_size, >vma, );
if (unlikely(err)) {
-   CT_PROBE_ERROR(ct, "Failed to allocate %u for CTB data (%pe)\n",
+   ct_probe_error(ct, "Failed to allocate %u for CTB data (%pe)\n",
   blob_size, ERR_PTR(err));
return err;
}
 
-   CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), 
blob_size);
+   ct_dbg(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), 
blob_size);
 
/* store pointers to desc and cmds for send ctb */
desc = blob;
cmds = blob + 2 * CTB_DESC_SIZE;
cmds_size = CTB_H2G_BUFFER_SIZE;
resv_space = 0;
-   CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
-ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
-resv_space);
+   ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
+  ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
+  resv_space);
 
guc_ct_buffer_init(>ctbs.send, desc, cmds, cmds_size, resv_space);
 
@@ -258,9 +276,9 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
cmds = 

[Intel-gfx] [PATCH v2 5/5] drm/i915/uc: Update the gt/uc code to use gt_err and friends

[John . C . Harrison]

From: John Harrison 

Use the new module oriented output message helpers where possible.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc.c| 108 +++
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c |  98 ++--
 2 files changed, 99 insertions(+), 107 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 1d28286e6f066..269be95625342 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -65,29 +65,29 @@ static int __intel_uc_reset_hw(struct intel_uc *uc)
 
ret = intel_reset_guc(gt);
if (ret) {
-   DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
+   gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
return ret;
}
 
guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
-   WARN(!(guc_status & GS_MIA_IN_RESET),
-"GuC status: 0x%x, MIA core expected to be in reset\n",
-guc_status);
+   gt_WARN(gt, !(guc_status & GS_MIA_IN_RESET),
+   "GuC status: 0x%x, MIA core expected to be in reset\n",
+   guc_status);
 
return ret;
 }
 
 static void __confirm_options(struct intel_uc *uc)
 {
-   struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
+   struct intel_gt *gt = uc_to_gt(uc);
+   struct drm_i915_private *i915 = gt->i915;
 
-   drm_dbg(>drm,
-   "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
-   i915->params.enable_guc,
-   str_yes_no(intel_uc_wants_guc(uc)),
-   str_yes_no(intel_uc_wants_guc_submission(uc)),
-   str_yes_no(intel_uc_wants_huc(uc)),
-   str_yes_no(intel_uc_wants_guc_slpc(uc)));
+   gt_dbg(gt, "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
+  i915->params.enable_guc,
+  str_yes_no(intel_uc_wants_guc(uc)),
+  str_yes_no(intel_uc_wants_guc_submission(uc)),
+  str_yes_no(intel_uc_wants_huc(uc)),
+  str_yes_no(intel_uc_wants_guc_slpc(uc)));
 
if (i915->params.enable_guc == 0) {
GEM_BUG_ON(intel_uc_wants_guc(uc));
@@ -98,26 +98,22 @@ static void __confirm_options(struct intel_uc *uc)
}
 
if (!intel_uc_supports_guc(uc))
-   drm_info(>drm,
-"Incompatible option enable_guc=%d - %s\n",
-i915->params.enable_guc, "GuC is not supported!");
+   gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+   i915->params.enable_guc, "GuC is not supported!");
 
if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC &&
!intel_uc_supports_huc(uc))
-   drm_info(>drm,
-"Incompatible option enable_guc=%d - %s\n",
-i915->params.enable_guc, "HuC is not supported!");
+   gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+   i915->params.enable_guc, "HuC is not supported!");
 
if (i915->params.enable_guc & ENABLE_GUC_SUBMISSION &&
!intel_uc_supports_guc_submission(uc))
-   drm_info(>drm,
-"Incompatible option enable_guc=%d - %s\n",
-i915->params.enable_guc, "GuC submission is N/A");
+   gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+   i915->params.enable_guc, "GuC submission is N/A");
 
if (i915->params.enable_guc & ~ENABLE_GUC_MASK)
-   drm_info(>drm,
-"Incompatible option enable_guc=%d - %s\n",
-i915->params.enable_guc, "undocumented flag");
+   gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+   i915->params.enable_guc, "undocumented flag");
 }
 
 void intel_uc_init_early(struct intel_uc *uc)
@@ -249,15 +245,13 @@ static int guc_enable_communication(struct intel_guc *guc)
intel_guc_ct_event_handler(>ct);
spin_unlock_irq(gt->irq_lock);
 
-   drm_dbg(>drm, "GuC communication enabled\n");
+   guc_dbg(guc, "communication enabled\n");
 
return 0;
 }
 
 static void guc_disable_communication(struct intel_guc *guc)
 {
-   struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
-
/*
 * Events generated during or after CT disable are logged by guc in
 * via mmio. Make sure the register is clear before disabling CT since
@@ -277,7 +271,7 @@ static void guc_disable_communication(struct intel_guc *guc)
 */
guc_get_mmio_msg(guc);
 
-   drm_dbg(>drm, "GuC communication disabled\n");
+   guc_dbg(guc, "communication disabled\n");
 }
 
 static void __uc_fetch_firmwares(struct intel_uc *uc)
@@ -290,8 +284,8 @@ static void __uc_fetch_firmwares(struct intel_uc *uc)
if (err) {
/* Make sure we transition out of 

[Intel-gfx] [PATCH v2 1/5] drm/i915/gt: Start adding module oriented dmesg output

[John . C . Harrison]

From: John Harrison 

When trying to analyse bug reports from CI, customers, etc. it can be
difficult to work out exactly what is happening on which GT in a
multi-GT system. So add GT oriented debug/error message wrappers. If
used instead of the drm_ equivalents, you get the same output but with
a GT# prefix on it.

v2: Go back to using lower case names (combined review feedback).
Convert intel_gt.c as a first step.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 96 ++
 drivers/gpu/drm/i915/gt/intel_gt.h | 35 +++
 2 files changed, 81 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 0325f071046ca..349fcfdd14a6d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -90,9 +90,8 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
if (err == -ENODEV)
return 0;
 
-   drm_err(>drm,
-   "Failed to setup region(%d) type=%d\n",
-   err, INTEL_MEMORY_LOCAL);
+   gt_err(gt, "Failed to setup region(%d) type=%d\n",
+  err, INTEL_MEMORY_LOCAL);
return err;
}
 
@@ -192,14 +191,14 @@ int intel_gt_init_hw(struct intel_gt *gt)
 
ret = i915_ppgtt_init_hw(gt);
if (ret) {
-   drm_err(>drm, "Enabling PPGTT failed (%d)\n", ret);
+   gt_err(gt, "Enabling PPGTT failed (%d)\n", ret);
goto out;
}
 
/* We can't enable contexts until all firmware is loaded */
ret = intel_uc_init_hw(>uc);
if (ret) {
-   i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
+   gt_probe_error(gt, "Enabling uc failed (%d)\n", ret);
goto out;
}
 
@@ -264,7 +263,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
 * some errors might have become stuck,
 * mask them.
 */
-   drm_dbg(>i915->drm, "EIR stuck: 0x%08x, masking\n", eir);
+   gt_dbg(gt, "EIR stuck: 0x%08x, masking\n", eir);
rmw_set(uncore, EMR, eir);
intel_uncore_write(uncore, GEN2_IIR,
   I915_MASTER_ERROR_INTERRUPT);
@@ -298,16 +297,16 @@ static void gen6_check_faults(struct intel_gt *gt)
for_each_engine(engine, gt, id) {
fault = GEN6_RING_FAULT_REG_READ(engine);
if (fault & RING_FAULT_VALID) {
-   drm_dbg(>i915->drm, "Unexpected fault\n"
-   "\tAddr: 0x%08lx\n"
-   "\tAddress space: %s\n"
-   "\tSource ID: %d\n"
-   "\tType: %d\n",
-   fault & PAGE_MASK,
-   fault & RING_FAULT_GTTSEL_MASK ?
-   "GGTT" : "PPGTT",
-   RING_FAULT_SRCID(fault),
-   RING_FAULT_FAULT_TYPE(fault));
+   gt_dbg(gt, "Unexpected fault\n"
+  "\tAddr: 0x%08lx\n"
+  "\tAddress space: %s\n"
+  "\tSource ID: %d\n"
+  "\tType: %d\n",
+  fault & PAGE_MASK,
+  fault & RING_FAULT_GTTSEL_MASK ?
+  "GGTT" : "PPGTT",
+  RING_FAULT_SRCID(fault),
+  RING_FAULT_FAULT_TYPE(fault));
}
}
 }
@@ -334,17 +333,17 @@ static void xehp_check_faults(struct intel_gt *gt)
fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
 ((u64)fault_data0 << 12);
 
-   drm_dbg(>i915->drm, "Unexpected fault\n"
-   "\tAddr: 0x%08x_%08x\n"
-   "\tAddress space: %s\n"
-   "\tEngine ID: %d\n"
-   "\tSource ID: %d\n"
-   "\tType: %d\n",
-   upper_32_bits(fault_addr), lower_32_bits(fault_addr),
-   fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
-   GEN8_RING_FAULT_ENGINE_ID(fault),
-   RING_FAULT_SRCID(fault),
-   RING_FAULT_FAULT_TYPE(fault));
+   gt_dbg(gt, "Unexpected fault\n"
+  "\tAddr: 0x%08x_%08x\n"
+  "\tAddress space: %s\n"
+  "\tEngine ID: %d\n"
+  "\tSource ID: %d\n"
+  "\tType: %d\n",
+  upper_32_bits(fault_addr), lower_32_bits(fault_addr),
+  fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
+  GEN8_RING_FAULT_ENGINE_ID(fault),
+ 

[Intel-gfx] [PATCH v2 0/5] Add module oriented dmesg output

[John . C . Harrison]

From: John Harrison 

When trying to analyse bug reports from CI, customers, etc. it can be
difficult to work out exactly what is happening on which GT in a
multi-GT system. So add GT oriented debug/error message wrappers. If
used instead of the drm_ equivalents, you get the same output but with
a GT# prefix on it.

It was also requested to extend this further to submodules in order to
factor out the repeated structure accessing constructs and common
string prefixes. So, add versions for GuC, HuC and GuC CTB as well.

This patch set updates all the gt/uc files to use the new helpers as a
first step. The intention would be to convert all output messages that
have access to a GT structure.

v2: Go back to using lower case names, add more wrapper sets (combined
review feedback). Also, wrap up probe injection and WARN entries.

Signed-off-by: John Harrison 


John Harrison (5):
  drm/i915/gt: Start adding module oriented dmesg output
  drm/i915/huc: Add HuC specific debug print wrappers
  drm/i915/guc: Add GuC specific debug print wrappers
  drm/i915/guc: Add GuC CT specific debug print wrappers
  drm/i915/uc: Update the gt/uc code to use gt_err and friends

 drivers/gpu/drm/i915/gt/intel_gt.c|  96 
 drivers/gpu/drm/i915/gt/intel_gt.h|  35 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc.c|  32 +--
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  35 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c|   8 +-
 .../gpu/drm/i915/gt/uc/intel_guc_capture.c|  48 ++--
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |  19 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c|  37 ++-
 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c |   7 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   |  55 ++---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  62 +++--
 drivers/gpu/drm/i915/gt/uc/intel_huc.c|  31 +--
 drivers/gpu/drm/i915/gt/uc/intel_huc.h|  23 ++
 drivers/gpu/drm/i915/gt/uc/intel_uc.c | 108 -
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  |  98 
 drivers/gpu/drm/i915/gt/uc/selftest_guc.c |  34 +--
 .../drm/i915/gt/uc/selftest_guc_hangcheck.c   |  22 +-
 .../drm/i915/gt/uc/selftest_guc_multi_lrc.c   |  10 +-
 19 files changed, 507 insertions(+), 475 deletions(-)

-- 
2.37.3

Re: [Intel-gfx] [PATCH 2/3] drm/i915/display: Do both crawl and squash when changing cdclk

[Matt Roper]

On Thu, Nov 17, 2022 at 03:00:01PM -0800, Anusha Srivatsa wrote:
> From: Ville Syrjälä 
> 
> For MTL, changing cdclk from between certain frequencies has
> both squash and crawl. Use the current cdclk config and
> the new(desired) cdclk config to construtc a mid cdclk config.

s/construtc/construct/

> Set the cdclk twice:
> - Current cdclk -> mid cdclk
> - mid cdclk -> desired cdclk
> 
> Driver should not take some Pcode mailbox communication
> in the cdclk path for platforms that are Display version 14 and later.
> 
> v2: Add check in intel_modeset_calc_cdclk() to avoid cdclk
> change via modeset for platforms that support squash_crawl sequences(Ville)
> 
> v3: Add checks for:
> - scenario where only slow clock is used and
> cdclk is actually 0 (bringing up display).
> - PLLs are on before looking up the waveform.
> - Squash and crawl capability checks.(Ville)
> 
> v4: Rebase
> - Move checks to be more consistent (Ville)
> - Add comments (Bala)
> v5:
> - Further small changes. Move checks around.
> - Make if-else better looking (Ville)
> 
> v6: MTl should not follow PUnit mailbox communication as the rest of
> gen11+ platforms.(Anusha)
> 
> Cc: Clint Taylor 
> Cc: Balasubramani Vivekanandan 
> Signed-off-by: Anusha Srivatsa 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 181 +
>  1 file changed, 150 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 25d01271dc09..1280a08b9c72 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1727,37 +1727,79 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
>   return vco == ~0;
>  }
>  
> -static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> -   const struct intel_cdclk_config *cdclk_config,
> -   enum pipe pipe)
> +static int cdclk_squash_divider(u16 waveform)
> +{
> + return hweight16(waveform ?: 0x);
> +}
> +
> +static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private 
> *i915,
> + const struct 
> intel_cdclk_config *old_cdclk_config,
> + const struct 
> intel_cdclk_config *new_cdclk_config,
> + struct intel_cdclk_config 
> *mid_cdclk_config)
> +{
> + u16 old_waveform, new_waveform, mid_waveform;
> + int size = 16;
> + int div = 2;
> +
> + /* Return for vco ~0 (-1) and follow complete PLL disable and enable */

I don't think the mention of ~0 / -1 here is helpful; we added the
helper function to hide those low-level implementation details.  Just
say something high-level about what you're actually trying to do like
"If the PLL is in an unknown state, force a complete disable and
re-enable."

Aside from that (and the typo in the commit message),

Reviewed-by: Matt Roper 

> + if (cdclk_pll_is_unknown(old_cdclk_config->vco))
> + return false;
> +
> + /* Return if both Squash and Crawl are not present */
> + if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
> + return false;
> +
> + old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
> + new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
> +
> + /* Return if Squash only or Crawl only is the desired action */
> + if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
> + old_cdclk_config->vco == new_cdclk_config->vco ||
> + old_waveform == new_waveform)
> + return false;
> +
> + *mid_cdclk_config = *new_cdclk_config;
> +
> + /*
> +  * Populate the mid_cdclk_config accordingly.
> +  * - If moving to a higher cdclk, the desired action is squashing.
> +  * The mid cdclk config should have the new (squash) waveform.
> +  * - If moving to a lower cdclk, the desired action is crawling.
> +  * The mid cdclk config should have the new vco.
> +  */
> +
> + if (cdclk_squash_divider(new_waveform) > 
> cdclk_squash_divider(old_waveform)) {
> + mid_cdclk_config->vco = old_cdclk_config->vco;
> + mid_waveform = new_waveform;
> + } else {
> + mid_cdclk_config->vco = new_cdclk_config->vco;
> + mid_waveform = old_waveform;
> + }
> +
> + mid_cdclk_config->cdclk = 
> DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
> + mid_cdclk_config->vco, size 
> * div);
> +
> + /* make sure the mid clock came out sane */
> +
> + drm_WARN_ON(>drm, mid_cdclk_config->cdclk <
> + min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
> + drm_WARN_ON(>drm, mid_cdclk_config->cdclk >
> + i915->display.cdclk.max_cdclk_freq);
> + drm_WARN_ON(>drm, cdclk_squash_waveform(i915, 
> 

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/pxp: Add missing cleanup steps for PXP global-teardown

[Patchwork]

== Series Details ==

Series: drm/i915/pxp: Add missing cleanup steps for PXP global-teardown
URL   : https://patchwork.freedesktop.org/series/111047/
State : failure

== Summary ==

Error: make failed
  CALLscripts/checksyscalls.sh
  DESCEND objtool
  MODPOST Module.symvers
ERROR: modpost: "intel_pxp_terminate" [drivers/gpu/drm/i915/i915.ko] undefined!
scripts/Makefile.modpost:126: recipe for target 'Module.symvers' failed
make[1]: *** [Module.symvers] Error 1
Makefile:1944: recipe for target 'modpost' failed
make: *** [modpost] Error 2

Re: [Intel-gfx] [PATCH 2/2] drm/i915/pxp: Trigger the global teardown for before suspending

[Teres Alexis, Alan Previn]

On Thu, 2022-11-17 at 16:36 -0800, Alan Previn wrote:
> A driver bug was recently discovered where the security firmware was
> receiving internal HW signals indicating that session key expirations
> had occurred. Architecturally, the firmware was expecting a response
> from the GuC to acknowledge the event with the firmware side.
> However the OS was in a suspended state and GuC had been reset.
> Internal specifications actually required the driver to ensure
> that all active sessions be properly cleaned up in such cases where
> the system is suspended and the GuC potentially unable to respond.
> 
> This patch adds the global teardown code in i915's suspend_prepare
> code path.
> 
> Signed-off-by: Alan Previn 
> ---
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> @@ -14,7 +14,7 @@ void intel_pxp_suspend_prepare(struct intel_pxp *pxp)
>   if (!intel_pxp_is_enabled(pxp))
>   return;
>  
> - pxp->arb_is_valid = false;
> + intel_pxp_end(pxp);
>  
>   intel_pxp_invalidate(pxp);
>  }
We discovered that depending on the runtime-pm behavior of the platform, this 
patch uncovers a hang on the mei component
driver (when calling the mei-pxp's interface for sending messages to the 
firmware from within the suspend-prepare
callstack).

As soon as that mei patch is fit for publication we shall either merge the 
patches into a single series or provide a
link from here.

...alan

[Intel-gfx] [PATCH 1/2] drm/i915/pxp: Invalidate all PXP fw sessions during teardown

[Alan Previn]

A gap was recently discovered where if an application did not
invalidate all of the stream keys (intentionally or not), and the
driver did a full PXP global teardown on the GT subsystem, we
find that future session creation would fail on the security
firmware's side of the equation. i915 is the entity that needs
ensure the sessions' state across both iGT and security firmware
are at a known clean point when performing a full global teardown.

That said, the i915 should inspect all active sessions and submit
the invalidate-stream-key PXP command to the security firmware for
each of them.

Signed-off-by: Alan Previn 
---
 drivers/gpu/drm/i915/pxp/intel_pxp.h  |  1 +
 .../drm/i915/pxp/intel_pxp_cmd_interface_42.h | 15 +++
 .../i915/pxp/intel_pxp_cmd_interface_cmn.h|  3 ++
 drivers/gpu/drm/i915/pxp/intel_pxp_session.c  |  5 +++
 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c  | 45 +++
 drivers/gpu/drm/i915/pxp/intel_pxp_types.h|  2 +
 6 files changed, 71 insertions(+)

diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h 
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 2da309088c6d..6ba8fa5bfea0 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -23,6 +23,7 @@ void intel_pxp_init_hw(struct intel_pxp *pxp);
 void intel_pxp_fini_hw(struct intel_pxp *pxp);
 
 void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
+void intel_pxp_tee_end_all_fw_sessions(struct intel_pxp *pxp, u32 
sessions_mask);
 
 int intel_pxp_start(struct intel_pxp *pxp);
 
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_42.h 
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_42.h
index 739f9072fa5f..26f7d9f01bf3 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_42.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_42.h
@@ -12,6 +12,9 @@
 /* PXP-Opcode for Init Session */
 #define PXP42_CMDID_INIT_SESSION 0x1e
 
+/* PXP-Opcode for Invalidate Stream Key */
+#define PXP42_CMDID_INVALIDATE_STREAM_KEY 0x0007
+
 /* PXP-Input-Packet: Init Session (Arb-Session) */
 struct pxp42_create_arb_in {
struct pxp_cmd_header header;
@@ -25,4 +28,16 @@ struct pxp42_create_arb_out {
struct pxp_cmd_header header;
 } __packed;
 
+/* PXP-Input-Packet: Invalidate Stream Key */
+struct pxp42_inv_stream_key_in {
+   struct pxp_cmd_header header;
+   u32 rsvd[3];
+} __packed;
+
+/* PXP-Output-Packet: Invalidate Stream Key */
+struct pxp42_inv_stream_key_out {
+   struct pxp_cmd_header header;
+   u32 rsvd;
+} __packed;
+
 #endif /* __INTEL_PXP_FW_INTERFACE_42_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h 
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h
index c2f23394f9b8..69e34ec49e78 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h
@@ -27,6 +27,9 @@ struct pxp_cmd_header {
union {
u32 status; /* out */
u32 stream_id; /* in */
+#define PXP_CMDHDR_EXTDATA_SESSION_VALID GENMASK(0, 0)
+#define PXP_CMDHDR_EXTDATA_APP_TYPE GENMASK(1, 1)
+#define PXP_CMDHDR_EXTDATA_SESSION_ID GENMASK(17, 2)
};
/* Length of the message (excluding the header) */
u32 buffer_len;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c 
b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
index 85572360c71a..85e404b5ad0e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -91,10 +91,13 @@ static int pxp_terminate_arb_session_and_global(struct 
intel_pxp *pxp)
 {
int ret;
struct intel_gt *gt = pxp_to_gt(pxp);
+   u32 active_sip_slots;
 
/* must mark termination in progress calling this function */
GEM_WARN_ON(pxp->arb_is_valid);
 
+   active_sip_slots = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+
/* terminate the hw sessions */
ret = intel_pxp_terminate_session(pxp, ARB_SESSION);
if (ret) {
@@ -110,6 +113,8 @@ static int pxp_terminate_arb_session_and_global(struct 
intel_pxp *pxp)
 
intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1);
 
+   intel_pxp_tee_end_all_fw_sessions(pxp, active_sip_slots);
+
return ret;
 }
 
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c 
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index b0c9170b1395..9260a7013191 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -309,3 +309,48 @@ int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp 
*pxp,
 
return ret;
 }
+
+static void intel_pxp_tee_end_one_fw_session(struct intel_pxp *pxp, u32 
session_id, bool is_alive)
+{
+   struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+   struct pxp42_inv_stream_key_in msg_in = {0};
+   struct pxp42_inv_stream_key_out msg_out = {0};
+   int ret, trials = 0;
+
+try_again:
+   memset(_in, 0, sizeof(msg_in));
+   

[Intel-gfx] [PATCH 2/2] drm/i915/pxp: Trigger the global teardown for before suspending

[Alan Previn]

A driver bug was recently discovered where the security firmware was
receiving internal HW signals indicating that session key expirations
had occurred. Architecturally, the firmware was expecting a response
from the GuC to acknowledge the event with the firmware side.
However the OS was in a suspended state and GuC had been reset.
Internal specifications actually required the driver to ensure
that all active sessions be properly cleaned up in such cases where
the system is suspended and the GuC potentially unable to respond.

This patch adds the global teardown code in i915's suspend_prepare
code path.

Signed-off-by: Alan Previn 
---
 drivers/gpu/drm/i915/pxp/intel_pxp.c | 60 +---
 drivers/gpu/drm/i915/pxp/intel_pxp.h |  2 +
 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c  |  2 +-
 drivers/gpu/drm/i915/pxp/intel_pxp_session.c |  9 ++-
 4 files changed, 60 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c 
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 5efe61f67546..659410ae1b89 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -198,6 +198,55 @@ static bool pxp_component_bound(struct intel_pxp *pxp)
return bound;
 }
 
+static int __pxp_global_teardown_locked(struct intel_pxp *pxp, bool 
terminate_for_cleanup)
+{
+   if (terminate_for_cleanup) {
+   if (!pxp->arb_is_valid)
+   return 0;
+   /*
+* To ensure synchronous and coherent session teardown 
completion
+* in response to suspend or shutdown triggers, don't user a 
worker.
+*/
+   intel_pxp_mark_termination_in_progress(pxp);
+   intel_pxp_terminate(pxp, false);
+   } else {
+   if (pxp->arb_is_valid)
+   return 0;
+   /*
+* If we are not in final termination, and the arb-session is 
currently
+* inactive, we are doing a reset and restart due to some 
runtime event.
+* Use the worker that was designed for this.
+*/
+   pxp_queue_termination(pxp);
+   }
+
+   if (!wait_for_completion_timeout(>termination, 
msecs_to_jiffies(250)))
+   return -ETIMEDOUT;
+
+   return 0;
+}
+
+void intel_pxp_end(struct intel_pxp *pxp)
+{
+   struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+   intel_wakeref_t wakeref;
+
+   if (!intel_pxp_is_enabled(pxp))
+   return;
+
+   wakeref = intel_runtime_pm_get(>runtime_pm);
+
+   mutex_lock(>arb_mutex);
+
+   if (__pxp_global_teardown_locked(pxp, true))
+   drm_dbg(&(pxp_to_gt(pxp))->i915->drm, "PXP end timed out\n");
+
+   mutex_unlock(>arb_mutex);
+
+   intel_pxp_fini_hw(pxp);
+   intel_runtime_pm_put(>runtime_pm, wakeref);
+}
+
 /*
  * the arb session is restarted from the irq work when we receive the
  * termination completion interrupt
@@ -214,16 +263,9 @@ int intel_pxp_start(struct intel_pxp *pxp)
 
mutex_lock(>arb_mutex);
 
-   if (pxp->arb_is_valid)
-   goto unlock;
-
-   pxp_queue_termination(pxp);
-
-   if (!wait_for_completion_timeout(>termination,
-   msecs_to_jiffies(250))) {
-   ret = -ETIMEDOUT;
+   ret = __pxp_global_teardown_locked(pxp, false);
+   if (ret)
goto unlock;
-   }
 
/* make sure the compiler doesn't optimize the double access */
barrier();
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h 
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 6ba8fa5bfea0..d001828b3372 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -26,6 +26,8 @@ void intel_pxp_mark_termination_in_progress(struct intel_pxp 
*pxp);
 void intel_pxp_tee_end_all_fw_sessions(struct intel_pxp *pxp, u32 
sessions_mask);
 
 int intel_pxp_start(struct intel_pxp *pxp);
+void intel_pxp_end(struct intel_pxp *pxp);
+void intel_pxp_terminate(struct intel_pxp *pxp, bool restart_arb);
 
 int intel_pxp_key_check(struct intel_pxp *pxp,
struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c 
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
index 6a7d4e2ee138..36af52c28e63 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -14,7 +14,7 @@ void intel_pxp_suspend_prepare(struct intel_pxp *pxp)
if (!intel_pxp_is_enabled(pxp))
return;
 
-   pxp->arb_is_valid = false;
+   intel_pxp_end(pxp);
 
intel_pxp_invalidate(pxp);
 }
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c 
b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
index 85e404b5ad0e..fdf30554d80f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -118,11 +118,14 @@ static int 

[Intel-gfx] [PATCH 0/2] drm/i915/pxp: Add missing cleanup steps for PXP global-teardown

[Alan Previn]

A customer issue was recently discovered and in the process a
gap in i915's PXP interaction with HW+FW architecure was also
realized. This series adds those missing pieces.
The patches explain the details.

Alan Previn (2):
  drm/i915/pxp: Invalidate all PXP fw sessions during teardown
  drm/i915/pxp: Trigger the global teardown for before suspending

 drivers/gpu/drm/i915/pxp/intel_pxp.c  | 60 ---
 drivers/gpu/drm/i915/pxp/intel_pxp.h  |  3 +
 .../drm/i915/pxp/intel_pxp_cmd_interface_42.h | 15 +
 .../i915/pxp/intel_pxp_cmd_interface_cmn.h|  3 +
 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c   |  2 +-
 drivers/gpu/drm/i915/pxp/intel_pxp_session.c  | 14 -
 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c  | 45 ++
 drivers/gpu/drm/i915/pxp/intel_pxp_types.h|  2 +
 8 files changed, 131 insertions(+), 13 deletions(-)


base-commit: 75ed1f4f7835f178647e3f73910ed4af0944d9ec
-- 
2.34.1

Re: [Intel-gfx] linux-next: manual merge of the drm-misc tree with the origin tree

[Nathan Chancellor]

On Fri, Nov 18, 2022 at 09:06:36AM +1100, Stephen Rothwell wrote:
> Hi Nathan,
> 
> On Thu, 17 Nov 2022 10:29:33 -0700 Nathan Chancellor  
> wrote:
> >
> > This resolution is not quite right, as pointed out by clang:
> > 
> > drivers/gpu/drm/vc4/vc4_hdmi.c:351:14: error: variable 'vc4_hdmi' is 
> > uninitialized when used here [-Werror,-Wuninitialized]
> > mutex_lock(_hdmi->mutex);
> > ^~~~
> > ./include/linux/mutex.h:187:44: note: expanded from macro 'mutex_lock'
> > #define mutex_lock(lock) mutex_lock_nested(lock, 0)
> >^~~~
> > drivers/gpu/drm/vc4/vc4_hdmi.c:322:27: note: initialize the variable 
> > 'vc4_hdmi' to silence this warning
> > struct vc4_hdmi *vc4_hdmi;
> >  ^
> >   = NULL
> > 1 error generated.
> > 
> > Obviously, the assignment of vc4_hdmi should be before mutex_lock().
> 
> Thanks for pointing that out (silly me :-) ).  I have fixed up the
> resolution for today.

Great, thank you so much! One less warning to worry about :)

Cheers,
Nathan

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/display: Add missing checks for 
cdclk crawling
URL   : https://patchwork.freedesktop.org/series/111045/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12396 -> Patchwork_111045v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/index.html

Participating hosts (40 -> 38)
--

  Additional (2): fi-rkl-11600 bat-dg1-6 
  Missing(4): fi-ctg-p8600 fi-hsw-4770 fi-ilk-m540 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_111045v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- fi-rkl-11600:   NOTRUN -> [SKIP][1] ([i915#7456])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/fi-rkl-11600/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[PASS][2] -> [FAIL][3] ([i915#7229])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_huc_copy@huc-copy:
- fi-rkl-11600:   NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html

  * igt@gem_linear_blits@basic:
- fi-pnv-d510:[PASS][5] -> [SKIP][6] ([fdo#109271])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/fi-pnv-d510/igt@gem_linear_bl...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/fi-pnv-d510/igt@gem_linear_bl...@basic.html

  * igt@gem_lmem_swapping@basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/fi-rkl-11600/igt@gem_lmem_swapp...@basic.html

  * igt@gem_mmap@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][8] ([i915#4083])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/bat-dg1-6/igt@gem_m...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][9] ([i915#4079]) +1 similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][10] ([i915#4077]) +2 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][11] ([i915#3282])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6:  NOTRUN -> [SKIP][12] ([i915#1155])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html
- fi-rkl-11600:   NOTRUN -> [SKIP][13] ([i915#3012])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
- bat-dg1-6:  NOTRUN -> [SKIP][14] ([i915#6621])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/bat-dg1-6/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hangcheck:
- fi-rkl-guc: [PASS][15] -> [INCOMPLETE][16] ([i915#4983])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/fi-rkl-guc/igt@i915_selftest@l...@hangcheck.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/fi-rkl-guc/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@migrate:
- bat-adlp-4: [PASS][17] -> [INCOMPLETE][18] ([i915#7308] / 
[i915#7348])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/bat-adlp-4/igt@i915_selftest@l...@migrate.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/bat-adlp-4/igt@i915_selftest@l...@migrate.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   NOTRUN -> [INCOMPLETE][19] ([i915#4817])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6:  NOTRUN -> [SKIP][20] ([i915#4215])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6:  NOTRUN -> [SKIP][21] ([i915#4212]) +7 similar issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/display: Add missing checks for 
cdclk crawling
URL   : https://patchwork.freedesktop.org/series/111045/
State : warning

== Summary ==

Error: dim checkpatch failed
c105abf14fde drm/i915/display: Add missing checks for cdclk crawling
f6927d8d6e84 drm/i915/display: Do both crawl and squash when changing cdclk
-:61: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#61: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1736:
+   const struct 
intel_cdclk_config *old_cdclk_config,

-:62: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#62: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1737:
+   const struct 
intel_cdclk_config *new_cdclk_config,

-:173: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional 
statements (8, 26)
#173: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1854:
+   if (DISPLAY_VER(dev_priv) >= 14)
+   /* NOOP */;

-:205: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional 
statements (8, 19)
#205: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1885:
+   if (DISPLAY_VER(dev_priv) >= 14)
[...]
+*/;

total: 0 errors, 4 warnings, 0 checks, 220 lines checked
58eebe208394 drm/i915/display: Add CDCLK Support for MTL

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/dg2: Introduce Wa_18018764978

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/dg2: Introduce Wa_18018764978
URL   : https://patchwork.freedesktop.org/series/111042/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12396 -> Patchwork_111042v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/index.html

Participating hosts (40 -> 39)
--

  Additional (2): fi-rkl-11600 bat-dg1-6 
  Missing(3): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_111042v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- fi-rkl-11600:   NOTRUN -> [SKIP][1] ([i915#7456])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/fi-rkl-11600/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_huc_copy@huc-copy:
- fi-rkl-11600:   NOTRUN -> [SKIP][2] ([i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/fi-rkl-11600/igt@gem_lmem_swapp...@basic.html

  * igt@gem_mmap@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][4] ([i915#4083])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/bat-dg1-6/igt@gem_m...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][5] ([i915#4079]) +1 similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][7] ([i915#3282])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6:  NOTRUN -> [SKIP][8] ([i915#1155])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html
- fi-rkl-11600:   NOTRUN -> [SKIP][9] ([i915#3012])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
- bat-dg1-6:  NOTRUN -> [SKIP][10] ([i915#6621])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/bat-dg1-6/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][11] -> [INCOMPLETE][12] ([i915#4785])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   NOTRUN -> [INCOMPLETE][13] ([i915#4817])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6:  NOTRUN -> [SKIP][14] ([i915#4215])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6:  NOTRUN -> [SKIP][15] ([i915#4212]) +7 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_chamelium@hdmi-crc-fast:
- bat-dg1-6:  NOTRUN -> [SKIP][16] ([fdo#111827]) +8 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
- fi-rkl-11600:   NOTRUN -> [SKIP][17] ([fdo#111827]) +7 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/fi-rkl-11600/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-rkl-11600:   NOTRUN -> [SKIP][18] ([i915#4103])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
- bat-dg1-6:  NOTRUN -> [SKIP][19] ([i915#4103] / [i915#4213])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/bat-dg1-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-rkl-11600:   NOTRUN -> [SKIP][20] 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dmc: Add MTL DMC firmware v2.10

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Add MTL DMC firmware v2.10
URL   : https://patchwork.freedesktop.org/series/111020/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12392_full -> Patchwork_111020v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_111020v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-glk:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25]) -> ([FAIL][26], [PASS][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], 
[PASS][48], [PASS][49]) ([i915#4392])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk1/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk1/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk1/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk2/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk2/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk2/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk3/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk3/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk3/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk5/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk5/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk5/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk5/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk6/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk6/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk6/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk7/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk7/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk7/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk8/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk8/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk8/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk9/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk9/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-glk9/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk1/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk1/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk1/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk1/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk2/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk2/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk2/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk3/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk3/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk3/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk5/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk5/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk6/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk6/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk6/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk7/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk7/boot.html
   [43]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/shard-glk7/boot.html
   

Re: [Intel-gfx] [PATCH v4 2/6] drm/i915/pxp: Make intel_pxp_is_enabled implicitly sort PXP-owning-GT

[Teres Alexis, Alan Previn]

On Thu, 2022-11-17 at 11:04 -0500, Vivi, Rodrigo wrote:
> On Wed, Nov 16, 2022 at 04:30:14PM -0800, Alan Previn wrote:
> > Make intel_pxp_is_enabled a global check and implicitly find the
> > PXP-owning-GT.
> > 
> > PXP feature support is a device-config flag. In preparation for MTL
> > PXP control-context shall reside on of the two GT's. That said,
> > update intel_pxp_is_enabled to take in i915 as its input and internally
> > find the right gt to check if PXP is enabled so its transparent to
> > callers of this functions.
> > 
> > However we also need to expose the per-gt variation of this internal
> > pxp files to use (like what intel_pxp_enabled was prior) so also expose
> > a new intel_gtpxp_is_enabled function for replacement.
> > 
> > Signed-off-by: Alan Previn 
> > ---
> >  drivers/gpu/drm/i915/gem/i915_gem_context.c  |  2 +-
> >  drivers/gpu/drm/i915/gem/i915_gem_create.c   |  2 +-
> >  drivers/gpu/drm/i915/pxp/intel_pxp.c | 28 ++--
> >  drivers/gpu/drm/i915/pxp/intel_pxp.h |  4 ++-
> >  drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c |  2 +-
> >  drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c |  2 +-
> >  drivers/gpu/drm/i915/pxp/intel_pxp_irq.c |  2 +-
> >  drivers/gpu/drm/i915/pxp/intel_pxp_pm.c  |  8 +++---
> >  drivers/gpu/drm/i915/pxp/intel_pxp_tee.c |  4 +--
> >  9 files changed, 40 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
> > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index 7f2831efc798..c123f4847b19 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -257,7 +257,7 @@ static int proto_context_set_protected(struct 
> > drm_i915_private *i915,
> >  
> > if (!protected) {
> > pc->uses_protected_content = false;
> > -   } else if (!intel_pxp_is_enabled(_gt(i915)->pxp)) {
> > +   } else if (!intel_pxp_is_enabled(i915)) {
> 
> if we are asking about pxp we should pass pxp, not i915...
> 
> 
The function is being called by gem-exec / gem-context / gem-create about the 
availibility of this feature globally.
I had previously discussed this with Daniele with the goal to have 2 versions 
(one a wrapper over the other) where u can
query "is the pxp feature available on this hw?" vs "does this gt have the 
enabled pxp controls"? where the latter is
more for internal PXP usage while the former is for external (gem-exec, 
gem-context, etc). So the naming above was
decided by Daniele. Or perhaps this might work better?

Another direction is to have the external callers not change at all (so 
gem-exec would continue call with either the
render-gt-pxp or the media-gt-pxp and have the internal subsystem sort out 
which is the correct subsystem. Internally in
our display code, when we have shared functions like clocks, buffers and such 
where i've seen code that takes in the
caller's crtc the top level and then internally parse across all crtcs to take 
the proper global actions (where
sometimes the control unit might reside on only 1 crtc). Actually, this was 
where rev1 was originally heading but
Daniele said that was convoluted (the internal rerouting from callers gt-pxp to 
the correct gt-pxp).

Respectfully and humbly, i would like to request where is the coding guideline 
for function naming when u have 2nd level
subsystem IPs owning control over global hw features so that we dont need to 
have this back and forth of conflicting
direction from different reviewers especially so long after initial reviews 
have started. (internally reworking future
MTL PXP series end up getting impacted here).

...alan

[Intel-gfx] [PATCH 3/3] drm/i915/display: Add CDCLK Support for MTL

[Anusha Srivatsa]

As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.

v2: Revert to using bxt_get_cdclk()

BSpec: 65243

Cc: Clint Taylor 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Clint Taylor 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 1280a08b9c72..32fbabf531fe 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1346,6 +1346,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = 
{
{}
 };
 
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+   { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, 
.waveform = 0xad5a },
+   { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, 
.waveform = 0xb6b6 },
+   { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, 
.waveform = 0x },
+   { .refclk = 38400, .cdclk = 48, .divider = 2, .ratio = 25, 
.waveform = 0x },
+   { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, 
.waveform = 0x },
+   { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, 
.waveform = 0x },
+   {}
+};
+
 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 {
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3190,6 +3200,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
 }
 
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+   .get_cdclk = bxt_get_cdclk,
+   .set_cdclk = bxt_set_cdclk,
+   .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+   .calc_voltage_level = tgl_calc_voltage_level,
+};
+
 static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3325,7 +3342,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = 
{
  */
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
-   if (IS_DG2(dev_priv)) {
+   if (IS_METEORLAKE(dev_priv)) {
+   dev_priv->display.funcs.cdclk = _cdclk_funcs;
+   dev_priv->display.cdclk.table = mtl_cdclk_table;
+   } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
-- 
2.25.1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/dg2: Introduce Wa_18018764978

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/dg2: Introduce Wa_18018764978
URL   : https://patchwork.freedesktop.org/series/111042/
State : warning

== Summary ==

Error: dim checkpatch failed
7b856027caa8 drm/i915/dg2: Introduce Wa_18018764978
-:37: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#37: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:779:
+   if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) ||
+   IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))

total: 0 errors, 0 warnings, 1 checks, 20 lines checked
f33eea50286e drm/i915/dg2: Introduce Wa_18019271663

[Intel-gfx] [PATCH 1/3] drm/i915/display: Add missing checks for cdclk crawling

[Anusha Srivatsa]

cdclk_sanitize() function was written assuming vco was a signed integer.
vco gets assigned to -1 (essentially ~0) for the case where PLL
might be enabled and vco is not a frequency that will ever
get used. In such a scenario the right thing to do is disable the
PLL and re-enable it again with a valid frequency.
However the vco is declared as a unsigned variable.
With the above assumption, driver takes crawl path when not needed.
Add explicit check to not crawl in the case of an invalid PLL.

v2: Move the check from .h to .c (MattR)
- Move check to bxt_set_cdclk() instead of
intel_modeset_calc_cdclk() which is directly in
the path of the sanitize() function (Ville)

v3: remove unwanted parenthesis(Ville)

Cc: Ville Syrjälä 
Cc: Matt Roper 
Suggested-by: Ville Syrjälä 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index b74e36d76013..25d01271dc09 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1717,6 +1717,16 @@ static void dg2_cdclk_squash_program(struct 
drm_i915_private *i915,
intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
 }
 
+static bool cdclk_pll_is_unknown(unsigned int vco)
+{
+   /*
+* Ensure driver does not take the crawl path for the
+* case when the vco is set to ~0 in the
+* sanitize path.
+*/
+   return vco == ~0;
+}
+
 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
  const struct intel_cdclk_config *cdclk_config,
  enum pipe pipe)
@@ -1749,7 +1759,8 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
return;
}
 
-   if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && 
vco > 0) {
+   if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && 
vco > 0 &&
+   !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
if (dev_priv->display.cdclk.hw.vco != vco)
adlp_cdclk_pll_crawl(dev_priv, vco);
} else if (DISPLAY_VER(dev_priv) >= 11)
-- 
2.25.1

[Intel-gfx] [PATCH 2/3] drm/i915/display: Do both crawl and squash when changing cdclk

[Anusha Srivatsa]

From: Ville Syrjälä 

For MTL, changing cdclk from between certain frequencies has
both squash and crawl. Use the current cdclk config and
the new(desired) cdclk config to construtc a mid cdclk config.
Set the cdclk twice:
- Current cdclk -> mid cdclk
- mid cdclk -> desired cdclk

Driver should not take some Pcode mailbox communication
in the cdclk path for platforms that are Display version 14 and later.

v2: Add check in intel_modeset_calc_cdclk() to avoid cdclk
change via modeset for platforms that support squash_crawl sequences(Ville)

v3: Add checks for:
- scenario where only slow clock is used and
cdclk is actually 0 (bringing up display).
- PLLs are on before looking up the waveform.
- Squash and crawl capability checks.(Ville)

v4: Rebase
- Move checks to be more consistent (Ville)
- Add comments (Bala)
v5:
- Further small changes. Move checks around.
- Make if-else better looking (Ville)

v6: MTl should not follow PUnit mailbox communication as the rest of
gen11+ platforms.(Anusha)

Cc: Clint Taylor 
Cc: Balasubramani Vivekanandan 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 181 +
 1 file changed, 150 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 25d01271dc09..1280a08b9c72 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1727,37 +1727,79 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
return vco == ~0;
 }
 
-static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *cdclk_config,
- enum pipe pipe)
+static int cdclk_squash_divider(u16 waveform)
+{
+   return hweight16(waveform ?: 0x);
+}
+
+static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private 
*i915,
+   const struct 
intel_cdclk_config *old_cdclk_config,
+   const struct 
intel_cdclk_config *new_cdclk_config,
+   struct intel_cdclk_config 
*mid_cdclk_config)
+{
+   u16 old_waveform, new_waveform, mid_waveform;
+   int size = 16;
+   int div = 2;
+
+   /* Return for vco ~0 (-1) and follow complete PLL disable and enable */
+   if (cdclk_pll_is_unknown(old_cdclk_config->vco))
+   return false;
+
+   /* Return if both Squash and Crawl are not present */
+   if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
+   return false;
+
+   old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
+   new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
+
+   /* Return if Squash only or Crawl only is the desired action */
+   if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
+   old_cdclk_config->vco == new_cdclk_config->vco ||
+   old_waveform == new_waveform)
+   return false;
+
+   *mid_cdclk_config = *new_cdclk_config;
+
+   /*
+* Populate the mid_cdclk_config accordingly.
+* - If moving to a higher cdclk, the desired action is squashing.
+* The mid cdclk config should have the new (squash) waveform.
+* - If moving to a lower cdclk, the desired action is crawling.
+* The mid cdclk config should have the new vco.
+*/
+
+   if (cdclk_squash_divider(new_waveform) > 
cdclk_squash_divider(old_waveform)) {
+   mid_cdclk_config->vco = old_cdclk_config->vco;
+   mid_waveform = new_waveform;
+   } else {
+   mid_cdclk_config->vco = new_cdclk_config->vco;
+   mid_waveform = old_waveform;
+   }
+
+   mid_cdclk_config->cdclk = 
DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
+   mid_cdclk_config->vco, size 
* div);
+
+   /* make sure the mid clock came out sane */
+
+   drm_WARN_ON(>drm, mid_cdclk_config->cdclk <
+   min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
+   drm_WARN_ON(>drm, mid_cdclk_config->cdclk >
+   i915->display.cdclk.max_cdclk_freq);
+   drm_WARN_ON(>drm, cdclk_squash_waveform(i915, 
mid_cdclk_config->cdclk) !=
+   mid_waveform);
+
+   return true;
+}
+
+static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
+  const struct intel_cdclk_config *cdclk_config,
+  enum pipe pipe)
 {
int cdclk = cdclk_config->cdclk;
int vco = cdclk_config->vco;
u32 val;
u16 waveform;
int clock;
-   int ret;
-
-   /* Inform power controller of upcoming frequency change. */
-   if (DISPLAY_VER(dev_priv) >= 11)
-   ret = skl_pcode_request(_priv->uncore, 

Re: [Intel-gfx] [PATCH] drm/i915: rename intel_gsc to intel_heci_gsc

[Ceraolo Spurio, Daniele]

On 11/3/2022 3:41 AM, Winkler, Tomas wrote:

Starting on MTL, the GSC FW is loaded at runtime and will be managed
directly by i915. This means we now have a naming clash around the GSC, as
we have 2 different aspects of it that we need to handle: the HECI interfaces
we export pre-mtl and the new full FW loading and support we have to
introduce starting from MTL. To avoid confusion, rename the existing
intel_gsc structure to intel_heci_gsc, to make it clear it contains the data
related to the HECI interfaces.


Are you sure you want to take this path, it will make backporting quite 
difficult.


The diff is relatively small (< 50 lines), so it shouldn't be too bad. 
Otherwise, do you have any suggestion on how to avoid name clashing in a 
different way? I really want to avoid confusion around legacy heci gsc 
and new runtime-loaded gsc. My plan was to name them intel_heci_gsc and 
intel_gsc_uc respectively, to make it super clear which is which, but 
I'm open to alternatives.


Daniele




Signed-off-by: Daniele Ceraolo Spurio 
Cc: Tomas Winkler 
Cc: Alexander Usyskin 
---
  drivers/gpu/drm/i915/Makefile |  4 +-
  drivers/gpu/drm/i915/gt/intel_gt.c|  4 +-
  drivers/gpu/drm/i915/gt/intel_gt.h|  4 +-
  drivers/gpu/drm/i915/gt/intel_gt_irq.c|  2 +-
  drivers/gpu/drm/i915/gt/intel_gt_types.h  |  4 +-
  .../i915/gt/{intel_gsc.c => intel_heci_gsc.c} | 43 ++-
.../i915/gt/{intel_gsc.h => intel_heci_gsc.h} | 22 +-
  drivers/gpu/drm/i915/gt/uc/intel_huc.c| 10 ++---
  drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c |  2 +-
  9 files changed, 48 insertions(+), 47 deletions(-)  rename
drivers/gpu/drm/i915/gt/{intel_gsc.c => intel_heci_gsc.c} (84%)  rename
drivers/gpu/drm/i915/gt/{intel_gsc.h => intel_heci_gsc.h} (52%)

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 51704b54317c..2fa401dcf087 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -206,8 +206,8 @@ i915-y += gt/uc/intel_uc.o \
  gt/uc/intel_huc_debugfs.o \
  gt/uc/intel_huc_fw.o

-# graphics system controller (GSC) support -i915-y += gt/intel_gsc.o
+# graphics system controller (GSC) HECI support i915-y +=
+gt/intel_heci_gsc.o

  # graphics hardware monitoring (HWMON) support
  i915-$(CONFIG_HWMON) += i915_hwmon.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 8e914c4066ed..6ca72479c943 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -454,7 +454,7 @@ void intel_gt_chipset_flush(struct intel_gt *gt)

  void intel_gt_driver_register(struct intel_gt *gt)  {
-   intel_gsc_init(>gsc, gt->i915);
+   intel_heci_gsc_init(>heci_gsc, gt->i915);

intel_rps_driver_register(>rps);

@@ -785,7 +785,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt)

intel_gt_sysfs_unregister(gt);
intel_rps_driver_unregister(>rps);
-   intel_gsc_fini(>gsc);
+   intel_heci_gsc_fini(>heci_gsc);

intel_pxp_fini(>pxp);

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index e0365d556248..43f73239a363 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -39,9 +39,9 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc
*huc)
return container_of(huc, struct intel_gt, uc.huc);  }

-static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc)
+static inline struct intel_gt *heci_gsc_to_gt(struct intel_heci_gsc
+*heci_gsc)
  {
-   return container_of(gsc, struct intel_gt, gsc);
+   return container_of(heci_gsc, struct intel_gt, heci_gsc);
  }

  void intel_gt_common_init_early(struct intel_gt *gt); diff --git
a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f26882fdc24c..3b4bd237659a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -75,7 +75,7 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
return intel_pxp_irq_handler(>pxp, iir);

if (instance == OTHER_GSC_INSTANCE)
-   return intel_gsc_irq_handler(gt, iir);
+   return intel_heci_gsc_irq_handler(gt, iir);

WARN_ONCE(1, "unhandled other interrupt instance=0x%x,
iir=0x%x\n",
  instance, iir);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index a0cc73b401ef..80a0163dcc01 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -17,7 +17,7 @@
  #include 

  #include "uc/intel_uc.h"
-#include "intel_gsc.h"
+#include "intel_heci_gsc.h"

  #include "i915_vma.h"
  #include "i915_perf_types.h"
@@ -100,7 +100,7 @@ struct intel_gt {
struct i915_ggtt *ggtt;

struct intel_uc uc;
-   struct intel_gsc gsc;
+   struct intel_heci_gsc heci_gsc;

struct {
  

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/rpl-p: Add stepping info

[Patchwork]

== Series Details ==

Series: drm/i915/rpl-p: Add stepping info
URL   : https://patchwork.freedesktop.org/series/111041/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12396 -> Patchwork_111041v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/index.html

Participating hosts (40 -> 38)
--

  Additional (1): bat-dg1-6 
  Missing(3): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_111041v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_mmap@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][1] ([i915#4083])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-dg1-6/igt@gem_m...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][2] ([i915#4079]) +1 similar issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html
- fi-apl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#7056])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][5] ([i915#4077]) +2 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6:  NOTRUN -> [SKIP][6] ([i915#1155])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
- bat-dg1-6:  NOTRUN -> [SKIP][7] ([i915#6621])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-dg1-6/igt@i915_pm_...@basic-api.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6:  NOTRUN -> [SKIP][8] ([i915#4215])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6:  NOTRUN -> [SKIP][9] ([i915#4212]) +7 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_chamelium@hdmi-crc-fast:
- bat-dg1-6:  NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-dg1-6:  NOTRUN -> [SKIP][11] ([i915#4103] / [i915#4213])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-dg1-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-6:  NOTRUN -> [SKIP][12] ([fdo#109285])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-dg1-6/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_psr@sprite_plane_onoff:
- bat-dg1-6:  NOTRUN -> [SKIP][13] ([i915#1072] / [i915#4078]) +3 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-dg1-6/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-6:  NOTRUN -> [SKIP][14] ([i915#3555])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-dg1-6/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-gtt:
- bat-dg1-6:  NOTRUN -> [SKIP][15] ([i915#3708] / [i915#4077]) +1 
similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-dg1-6/igt@prime_v...@basic-gtt.html

  * igt@prime_vgem@basic-userptr:
- bat-dg1-6:  NOTRUN -> [SKIP][16] ([i915#3708] / [i915#4873])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-dg1-6/igt@prime_v...@basic-userptr.html

  * igt@prime_vgem@basic-write:
- bat-dg1-6:  NOTRUN -> [SKIP][17] ([i915#3708]) +3 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-dg1-6/igt@prime_v...@basic-write.html

  
 Possible fixes 

  * igt@fbdev@read:
- {bat-rpls-2}:   [SKIP][18] ([i915#2582]) -> [PASS][19] +4 similar 
issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/bat-rpls-2/igt@fb...@read.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/bat-rpls-2/igt@fb...@read.html

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][20] ([i915#2867]) -> [PASS][21]
   [20]: 

Re: [Intel-gfx] [PATCH v4 1/6] drm/i915/pxp: Make gt and pxp init/fini aware of PXP-owning-GT

[Teres Alexis, Alan Previn]

On Thu, 2022-11-17 at 11:02 -0500, Vivi, Rodrigo wrote:
> On Wed, Nov 16, 2022 at 04:30:13PM -0800, Alan Previn wrote:
> > In preparation for future MTL-PXP feature support, PXP control
> > context should only valid on the correct gt tile. Depending on the
> > device-info this depends on which tile owns the VEBOX and KCR.
> > PXP is still a global feature though (despite its control-context
> > located in the owning GT structure). Additionally, we find
> > that the HAS_PXP macro is only used within the pxp module,
> > 
> > That said, lets drop that HAS_PXP macro altogether and replace it
> > with a more fitting named intel_gtpxp_is_supported and helpers
> > so that PXP init/fini can use to verify if the referenced gt supports
> > PXP or teelink.
> 
> Yep, I understand you as I'm not fan of these macros, specially
> single usage. But we need to consider that we have multiple dependencies
> there and other cases like this in the driver... Well, but I'm not
> opposing, but probably better to first get rid of the macro,
> then change the behavior of the function on the next patch.
> 
> > 
> > Add TODO for Meteorlake that will come in future series.
> 
> This refactor patch should be standalone, without poputing it with
> the changes that didn't came yet to this point.
> 
Sure i can follow this rule, but it would then raise the question of "nothign 
is really changing anywhere for MTL, why
are we doing this" thats why i wanted to add that placeholder. I see "TODO"s 
are a common thing in the driver for larger
features that cant all be enabled at once. Respectfully and humbly, is there 
some documented rule? Can you show it to
me?

> > 
> > Signed-off-by: Alan Previn 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h  |  4 
> >  drivers/gpu/drm/i915/pxp/intel_pxp.c | 22 ++--
> >  drivers/gpu/drm/i915/pxp/intel_pxp.h |  3 +++
> >  drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c |  2 +-
> >  4 files changed, 20 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 7e3820d2c404..0616e5f0bd31 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -933,10 +933,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >  
> >  #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)
> > (INTEL_INFO(dev_priv)->has_global_mocs)
> >  
> > -#define HAS_PXP(dev_priv)  ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \
> > -   INTEL_INFO(dev_priv)->has_pxp) && \
> > -   VDBOX_MASK(to_gt(dev_priv)))
> > -
> >  #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
> >  
> >  #define HAS_GMD_ID(i915)   (INTEL_INFO(i915)->has_gmd_id)
> > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c 
> > b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > index 5efe61f67546..d993e752bd36 100644
> > --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > @@ -44,6 +44,20 @@ struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
> > return container_of(pxp, struct intel_gt, pxp);
> >  }
> >  
> > +static bool _gt_needs_teelink(struct intel_gt *gt)
> > +{
> > +   /* TODO: MTL won't rely on CONFIG_INTEL_MEI_PXP but on GSC engine */
> > +   return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && 
> > intel_huc_is_loaded_by_gsc(>uc.huc) &&
> > +   intel_uc_uses_huc(>uc));
> > +}
> > +
> > +bool intel_pxp_supported_on_gt(const struct intel_pxp *pxp)
> 
> If we are asking if it is supported on gt, then the argument must be a gt 
> struct.
> 
I agree with you but Daniele said above is more consistent with existing ways 
that is considered the standard.
Respectfully and humbly I would like to request both yourself and Daniele to 
show me the coding guidelines somewhere.

Honestly, this is one of the first few hunks of the first patch of the first 
series in a very large complex design to
enable PXP on MTL and it only a helper utility function. Respecfully and 
humbly, I rather we focus our energy for review
+ redo  on more critical things like the e2e usage and top-to-bottom design or 
coding logic flows or find actual bugs
instead of debating about coding styles for internal only helper functions.


> > +{
> > +   /* TODO: MTL won't rely on CONFIG_INTEL_MEI_PXP but on GSC engine */
> > +   return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && 
> > IS_ENABLED(CONFIG_DRM_I915_PXP) &&
> > +   INTEL_INFO((pxp_to_gt(pxp))->i915)->has_pxp && 
> > VDBOX_MASK(pxp_to_gt(pxp)));
> > +}
> > +
> >  bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
> >  {
> > return pxp->ce;
> > @@ -142,17 +156,13 @@ void intel_pxp_init(struct intel_pxp *pxp)
> >  {
> > struct intel_gt *gt = pxp_to_gt(pxp);
> >  
> > -   /* we rely on the mei PXP module */
> > -   if (!IS_ENABLED(CONFIG_INTEL_MEI_PXP))
> > -   return;
> 
> I took a time to understand this movement based on the commit description.
> I have the feeling that this 

[Intel-gfx] [PATCH v2 2/2] drm/i915/dg2: Introduce Wa_18019271663

[Matt Atwood]

Wa_18019271663 applies to all DG2 steppings and skus.

Bspec: 66622

Signed-off-by: Matt Atwood 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 ---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 1711dbf9dd462..62a17baacf03e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -429,9 +429,10 @@
 #define   RC_OP_FLUSH_ENABLE   (1 << 0)
 #define   HIZ_RAW_STALL_OPT_DISABLE(1 << 2)
 #define CACHE_MODE_1   _MMIO(0x7004) /* IVB+ */
-#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE(1 << 6)
-#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE(1 << 6)
-#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   (1 << 1)
+#define   MSAA_OPTIMIZATION_REDUC_DISABLE  REG_BIT(11)
+#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLEREG_BIT(6)
+#define   GEN8_4x4_STC_OPTIMIZATION_DISABLEREG_BIT(6)
+#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   REG_BIT(1)
 
 #define GEN7_GT_MODE   _MMIO(0x7008)
 #define   GEN9_IZ_HASHING_MASK(slice)  (0x3 << ((slice) * 2))
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 483fd2a83ca19..452e423233207 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -781,6 +781,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs 
*engine,
 
/* Wa_15010599737:dg2 */
wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
+
+   /*Wa_18019271663:dg2 */
+   wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
 }
 
 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
-- 
2.38.1

[Intel-gfx] [PATCH v2 1/2] drm/i915/dg2: Introduce Wa_18018764978

[Matt Atwood]

Wa_18018764978 applies to specific steppings of DG2 (G10 C0+,
G11 and G12 A0+).

Bspec: 66622

Signed-off-by: Matt Atwood 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index c3cd926917957..1711dbf9dd462 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -457,6 +457,9 @@
 #define GEN8_L3CNTLREG _MMIO(0x7034)
 #define   GEN8_ERRDETBCTRL (1 << 9)
 
+#define PSS_MODE2  _MMIO(0x703c)
+#define   SCOREBOARD_STALL_FLUSH_CONTROL   REG_BIT(5)
+
 #define GEN7_SC_INSTDONE   _MMIO(0x7100)
 #define GEN12_SC_INSTDONE_EXTRA_MMIO(0x7104)
 #define GEN12_SC_INSTDONE_EXTRA2   _MMIO(0x7108)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1bd8d63ad4f3f..483fd2a83ca19 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -774,6 +774,11 @@ static void dg2_ctx_workarounds_init(struct 
intel_engine_cs *engine,
IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
wa_masked_field_set(wal, VF_PREEMPTION, 
PREEMPTION_VERTEX_COUNT, 0x4000);
 
+   /* Wa_18018764978:dg2 */
+   if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) ||
+   IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
+   wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
+
/* Wa_15010599737:dg2 */
wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
 }
-- 
2.38.1

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/mtl: Fix dram info readout

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/mtl: Fix dram info readout
URL   : https://patchwork.freedesktop.org/series/111039/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12396 -> Patchwork_111039v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/index.html

Participating hosts (40 -> 37)
--

  Additional (1): bat-dg1-6 
  Missing(4): fi-ctg-p8600 fi-hsw-4770 fi-ilk-m540 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_111039v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@basic-rte:
- {bat-adln-1}:   [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/bat-adln-1/igt@i915_pm_...@basic-rte.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-adln-1/igt@i915_pm_...@basic-rte.html

  
Known issues


  Here are the changes found in Patchwork_111039v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_mmap@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][3] ([i915#4083])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-dg1-6/igt@gem_m...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][4] ([i915#4079]) +1 similar issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][5] ([i915#4077]) +2 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6:  NOTRUN -> [SKIP][6] ([i915#1155])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
- bat-dg1-6:  NOTRUN -> [SKIP][7] ([i915#6621])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-dg1-6/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-6:  NOTRUN -> [INCOMPLETE][8] ([i915#4418])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-dg1-6/igt@i915_selftest@live@gt_engines.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6:  NOTRUN -> [SKIP][9] ([i915#4215])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6:  NOTRUN -> [SKIP][10] ([i915#4212]) +7 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_chamelium@hdmi-crc-fast:
- bat-dg1-6:  NOTRUN -> [SKIP][11] ([fdo#111827]) +7 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-dg1-6:  NOTRUN -> [SKIP][12] ([i915#4103] / [i915#4213])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-dg1-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-6:  NOTRUN -> [SKIP][13] ([fdo#109285])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-dg1-6/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_psr@sprite_plane_onoff:
- bat-dg1-6:  NOTRUN -> [SKIP][14] ([i915#1072] / [i915#4078]) +3 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-dg1-6/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-6:  NOTRUN -> [SKIP][15] ([i915#3555])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-dg1-6/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-gtt:
- bat-dg1-6:  NOTRUN -> [SKIP][16] ([i915#3708] / [i915#4077]) +1 
similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-dg1-6/igt@prime_v...@basic-gtt.html

  * igt@prime_vgem@basic-read:
- bat-dg1-6:  NOTRUN -> [SKIP][17] ([i915#3708]) +3 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/bat-dg1-6/igt@prime_v...@basic-read.html

  * igt@prime_vgem@basic-userptr:
- bat-dg1-6:  NOTRUN -> [SKIP][18] ([i915#3708] / [i915#4873])
   [18]: 

Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: Enable Idle Messaging for GSC CS

[Rodrigo Vivi]

On Tue, Nov 15, 2022 at 07:14:40PM +0530, Badal Nilawar wrote:
> From: Vinay Belgaumkar 
> 
> By defaut idle mesaging is disabled for GSC CS so to unblock RC6
> entry on media tile idle messaging need to be enabled.
> 
> v2:
>  - Fix review comments (Vinay)
>  - Set GSC idle hysterisis to 5 us (Badal)
> 
> Bspec: 71496
> 
> Cc: Daniele Ceraolo Spurio 
> Signed-off-by: Vinay Belgaumkar 
> Signed-off-by: Badal Nilawar 
> ---
>  drivers/gpu/drm/i915/gt/intel_engine_pm.c | 18 ++
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h   |  4 
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c 
> b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> index b0a4a2dbe3ee..5522885b2db0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> @@ -15,6 +15,22 @@
>  #include "intel_rc6.h"
>  #include "intel_ring.h"
>  #include "shmem_utils.h"
> +#include "intel_gt_regs.h"
> +
> +static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)
> +{
> + struct drm_i915_private *i915 = engine->i915;
> +
> + if (IS_METEORLAKE(i915) && engine->id == GSC0) {
> + intel_uncore_write(engine->gt->uncore,
> +RC_PSMI_CTRL_GSCCS,
> +_MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));

disable the disable? shouldn't be enable the disable?
1 = disable, no?

> + /* 5 us hysterisis */

could you please mention here in the comment that 0xA = 5 us per spec?
I got confused again even though you had explained already...

BTW, how reliable that spec is? Because according to that same line
we should be setting the bit 16, not the bit 0 in the previous reg!

> + intel_uncore_write(engine->gt->uncore,
> +PWRCTX_MAXCNT_GSCCS,
> +0xA);
> + }
> +}
>  
>  static void dbg_poison_ce(struct intel_context *ce)
>  {
> @@ -275,6 +291,8 @@ void intel_engine_init__pm(struct intel_engine_cs *engine)
>  
>   intel_wakeref_init(>wakeref, rpm, _ops);
>   intel_engine_init_heartbeat(engine);
> +
> + intel_gsc_idle_msg_enable(engine);
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 07031e03f80c..20472eb15364 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -913,6 +913,10 @@
>  #define  MSG_IDLE_FW_MASKREG_GENMASK(13, 9)
>  #define  MSG_IDLE_FW_SHIFT   9
>  
> +#define  RC_PSMI_CTRL_GSCCS  _MMIO(0x11a050)
> +#defineIDLE_MSG_DISABLE  BIT(0)
> +#define PWRCTX_MAXCNT_GSCCS  _MMIO(0x11a054)
> +
>  #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
>  #define FORCEWAKE_RENDER_GEN9_MMIO(0xa278)
>  
> -- 
> 2.25.1
> 

Re: [Intel-gfx] linux-next: manual merge of the drm-misc tree with the origin tree

[Stephen Rothwell]

Hi Nathan,

On Thu, 17 Nov 2022 10:29:33 -0700 Nathan Chancellor  wrote:
>
> This resolution is not quite right, as pointed out by clang:
> 
> drivers/gpu/drm/vc4/vc4_hdmi.c:351:14: error: variable 'vc4_hdmi' is 
> uninitialized when used here [-Werror,-Wuninitialized]
> mutex_lock(_hdmi->mutex);
> ^~~~
> ./include/linux/mutex.h:187:44: note: expanded from macro 'mutex_lock'
> #define mutex_lock(lock) mutex_lock_nested(lock, 0)
>^~~~
> drivers/gpu/drm/vc4/vc4_hdmi.c:322:27: note: initialize the variable 
> 'vc4_hdmi' to silence this warning
> struct vc4_hdmi *vc4_hdmi;
>  ^
>   = NULL
> 1 error generated.
> 
> Obviously, the assignment of vc4_hdmi should be before mutex_lock().

Thanks for pointing that out (silly me :-) ).  I have fixed up the
resolution for today.

-- 
Cheers,
Stephen Rothwell


pgpcqRpmGR2ff.pgp
Description: OpenPGP digital signature

Re: [Intel-gfx] [PATCH 0/5] i915: CAGF and RC6 changes for MTL

[Rodrigo Vivi]

On Mon, Nov 14, 2022 at 06:03:43PM +0530, Badal Nilawar wrote:
> This series includes the code changes to get CAGF, RC State and C6
> Residency of MTL.
> 
> v3: Included "Use GEN12 RPSTAT register" patch
> 
> v4:
>   - Rebased
>   - Dropped "Use GEN12 RPSTAT register" patch from this series
> going to send separate series for it
> 
> v5:
>   - Included "drm/i915/gt: Change RC6 residency functions to accept register
> ID's" based on code review feedback
> 
> v6:
>   - Addressed Jani N's review comments on "drm/i915/gt: Change RC6 residency
> functions to accept register ID's"
>   - Re-add "drm/i915: Use GEN12_RPSTAT register for GT freq" to this series
> 
> v7: Rebuild, identical to v6
> 
> v8:
>   - Add "drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf" to the 
> series
> (based on Rodrigo's review) to consistently use REG_FIELD_GET
>   - Minor changes to other patches, please see individual patches for 
> changelogs
> 
> v9: Rebuild, identical to v8
> 
> v10: Address review comments from Rodrigo on Patch 5
> 
> v11: Change state name for MTL_CC0 to RC0 in Patch 5
> 
> v12: Rebased to latest upstream. Identical to v11.

Thanks for the patches and for addressing all the requests.

Just for the record:
With your authorization, while merging them, I have added your missed
Signed-off-by to the couple patches, as we had discussed offline.

> 
> Ashutosh Dixit (2):
>   drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
>   drm/i915/gt: Use RC6 residency types as arguments to residency
> functions
> 
> Badal Nilawar (2):
>   drm/i915/mtl: Modify CAGF functions for MTL
>   drm/i915/mtl: C6 residency and C state type for MTL SAMedia
> 
> Don Hiatt (1):
>   drm/i915: Use GEN12_RPSTAT register for GT freq
> 
>  drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 88 ++-
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 22 +++--
>  drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c   | 12 +--
>  drivers/gpu/drm/i915/gt/intel_rc6.c   | 64 +-
>  drivers/gpu/drm/i915/gt/intel_rc6.h   | 11 ++-
>  drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 +++-
>  drivers/gpu/drm/i915/gt/intel_rps.c   | 51 ---
>  drivers/gpu/drm/i915/gt/intel_rps.h   |  2 +
>  drivers/gpu/drm/i915/gt/selftest_rc6.c|  6 +-
>  drivers/gpu/drm/i915/i915_pmu.c   |  9 +-
>  10 files changed, 198 insertions(+), 82 deletions(-)
> 
> -- 
> 2.25.1
> 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm: Analog TV Improvements (rev11)

[Patchwork]

== Series Details ==

Series: drm: Analog TV Improvements (rev11)
URL   : https://patchwork.freedesktop.org/series/107892/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12392_full -> Patchwork_107892v11_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_107892v11_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_107892v11_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_107892v11_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_suspend@sysfs-reader:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-tglb6/igt@i915_susp...@sysfs-reader.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/shard-tglb1/igt@i915_susp...@sysfs-reader.html

  
Known issues


  Here are the changes found in Patchwork_107892v11_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@psr2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#658])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-iclb2/igt@feature_discov...@psr2.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/shard-iclb8/igt@feature_discov...@psr2.html

  * igt@gem_create@create-massive:
- shard-skl:  NOTRUN -> [DMESG-WARN][5] ([i915#4991]) +1 similar 
issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/shard-skl6/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_persistence@hang:
- shard-skl:  NOTRUN -> [SKIP][6] ([fdo#109271]) +226 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/shard-skl7/igt@gem_ctx_persiste...@hang.html

  * igt@gem_eio@in-flight-contexts-immediate:
- shard-apl:  [PASS][7] -> [TIMEOUT][8] ([i915#3063])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-apl7/igt@gem_...@in-flight-contexts-immediate.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/shard-apl7/igt@gem_...@in-flight-contexts-immediate.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][9] ([i915#7557])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/shard-skl3/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-apl1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/shard-apl3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_lmem_swapping@basic:
- shard-skl:  NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +5 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/shard-skl7/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-apl:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/shard-apl6/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@verify-random:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#4613])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/shard-tglb1/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_pxp@create-regular-buffer:
- shard-tglb: NOTRUN -> [SKIP][15] ([i915#4270])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/shard-tglb1/igt@gem_...@create-regular-buffer.html

  * igt@gen9_exec_parse@unaligned-jump:
- shard-tglb: NOTRUN -> [SKIP][16] ([i915#2527] / [i915#2856])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/shard-tglb1/igt@gen9_exec_pa...@unaligned-jump.html

  * igt@i915_pm_dc@dc6-dpms:
- shard-skl:  NOTRUN -> [FAIL][17] ([i915#3989] / [i915#454])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/shard-skl3/igt@i915_pm...@dc6-dpms.html

  * igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][18] -> [FAIL][19] ([i915#3989] / [i915#454])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-iclb6/igt@i915_pm...@dc6-psr.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/shard-iclb2/igt@i915_pm...@dc6-psr.html

  * igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- shard-tglb: NOTRUN -> [WARN][20] ([i915#2681]) +3 similar issues
   [20]: 

Re: [Intel-gfx] [PATCH] drm/i915/rpl-p: Add stepping info

[Matt Roper]

On Thu, Nov 17, 2022 at 01:41:32PM -0800, Matt Atwood wrote:
> Add stepping-substepping info in accordance to bpsec changes.
> 
> Bspec: 55376
> 
> Cc: Anusha Srivatsa 
> Signed-off-by: Matt Atwood 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/intel_step.c | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_step.c 
> b/drivers/gpu/drm/i915/intel_step.c
> index 75d7a86c60c07..84a6fe736a3b5 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -131,6 +131,10 @@ static const struct intel_step_info adls_rpls_revids[] = 
> {
>   [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
>  };
>  
> +static const struct intel_step_info adlp_rplp_revids[] = {
> + [0x4] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_E0 },
> +};
> +
>  static const struct intel_step_info adlp_n_revids[] = {
>   [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
>  };
> @@ -187,6 +191,9 @@ void intel_step_init(struct drm_i915_private *i915)
>   } else if (IS_ADLP_N(i915)) {
>   revids = adlp_n_revids;
>   size = ARRAY_SIZE(adlp_n_revids);
> + } else if (IS_ADLP_RPLP(i915)) {
> + revids = adlp_rplp_revids;
> + size = ARRAY_SIZE(adlp_rplp_revids);
>   } else if (IS_ALDERLAKE_P(i915)) {
>   revids = adlp_revids;
>   size = ARRAY_SIZE(adlp_revids);
> -- 
> 2.38.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/mtl: Skip doubling channel numbers for LPDDR4/LPDDDR5

[Matt Roper]

On Thu, Nov 17, 2022 at 01:30:15PM -0800, Radhakrishna Sripada wrote:
> MTL LPDDR5 reported 16b with 8 channels. Previous platforms
> reported 32b with 4 channels and hence needed a multiplication
> by a factor of 2. Skip increasing the channels for MTL.
> 
> v2: Use version check instead of platform check(MattR)
> 
> Bspec: 64631
> Cc: Matt Roper 
> Signed-off-by: Radhakrishna Sripada 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 4ace026b29bd..1c236f02b380 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -439,7 +439,8 @@ static int tgl_get_bw_info(struct drm_i915_private 
> *dev_priv, const struct intel
>   return ret;
>   }
>  
> - if (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == 
> INTEL_DRAM_LPDDR5)
> + if (DISPLAY_VER(dev_priv) < 14 &&
> + (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == 
> INTEL_DRAM_LPDDR5))
>   num_channels *= 2;
>  
>   qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, 
> is_y_tile ? 4 : 2);
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

[Intel-gfx] ✓ Fi.CI.BAT: success for Fix live busy stats selftest failure (rev3)

[Patchwork]

== Series Details ==

Series: Fix live busy stats selftest failure (rev3)
URL   : https://patchwork.freedesktop.org/series/110557/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12396 -> Patchwork_110557v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/index.html

Participating hosts (40 -> 39)
--

  Additional (2): fi-rkl-11600 bat-dg1-6 
  Missing(3): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_110557v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- fi-rkl-11600:   NOTRUN -> [SKIP][1] ([i915#7456])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/fi-rkl-11600/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600:   NOTRUN -> [INCOMPLETE][2] ([i915#6179])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-rkl-11600:   NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/fi-rkl-11600/igt@gem_lmem_swapp...@basic.html

  * igt@gem_mmap@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/bat-dg1-6/igt@gem_m...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][6] ([i915#4079]) +1 similar issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][7] ([i915#4077]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][8] ([i915#3282])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6:  NOTRUN -> [SKIP][9] ([i915#1155])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html
- fi-rkl-11600:   NOTRUN -> [SKIP][10] ([i915#3012])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
- bat-dg1-6:  NOTRUN -> [SKIP][11] ([i915#6621])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/bat-dg1-6/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][12] -> [INCOMPLETE][13] ([i915#4785])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   NOTRUN -> [FAIL][14] ([fdo#103375])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6:  NOTRUN -> [SKIP][15] ([i915#4215])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6:  NOTRUN -> [SKIP][16] ([i915#4212]) +7 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_chamelium@hdmi-crc-fast:
- bat-dg1-6:  NOTRUN -> [SKIP][17] ([fdo#111827]) +8 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
- fi-rkl-11600:   NOTRUN -> [SKIP][18] ([fdo#111827]) +7 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/fi-rkl-11600/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-rkl-11600:   NOTRUN -> [SKIP][19] ([i915#4103])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
- bat-dg1-6:  NOTRUN -> [SKIP][20] ([i915#4103] / [i915#4213])
   [20]: 

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/mtl: Fix dram info readout

[Matt Roper]

On Thu, Nov 17, 2022 at 01:30:14PM -0800, Radhakrishna Sripada wrote:
> Register info read from the hardware is being cleared out. Preserve
> the register value and use extracted fields in the logic.

This description is kind of hard to understand if you don't already know
what the problem is (and the context in the diff itself doesn't show
enough of the function to make it clear either).  You might want to
clarify that we were overwriting the 'val' variable that code later in
the function still expects to contain the full register value.

With a reworded commit message,

Reviewed-by: Matt Roper 

> 
> Fixes: 825477e77912 ("drm/i915/mtl: Obtain SAGV values from MMIO instead of 
> GT pcode mailbox")
> Cc: Matt Roper 
> Signed-off-by: Radhakrishna Sripada 
> ---
>  drivers/gpu/drm/i915/intel_dram.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dram.c 
> b/drivers/gpu/drm/i915/intel_dram.c
> index 2403ccd52c74..bba8cb6e8ae4 100644
> --- a/drivers/gpu/drm/i915/intel_dram.c
> +++ b/drivers/gpu/drm/i915/intel_dram.c
> @@ -471,8 +471,7 @@ static int xelpdp_get_dram_info(struct drm_i915_private 
> *i915)
>   u32 val = intel_uncore_read(>uncore, MTL_MEM_SS_INFO_GLOBAL);
>   struct dram_info *dram_info = >dram_info;
>  
> - val = REG_FIELD_GET(MTL_DDR_TYPE_MASK, val);
> - switch (val) {
> + switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
>   case 0:
>   dram_info->type = INTEL_DRAM_DDR4;
>   break;
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

[Intel-gfx] [PATCH] drm/i915/rpl-p: Add stepping info

[Matt Atwood]

Add stepping-substepping info in accordance to bpsec changes.

Bspec: 55376

Cc: Anusha Srivatsa 
Signed-off-by: Matt Atwood 
---
 drivers/gpu/drm/i915/intel_step.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_step.c 
b/drivers/gpu/drm/i915/intel_step.c
index 75d7a86c60c07..84a6fe736a3b5 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -131,6 +131,10 @@ static const struct intel_step_info adls_rpls_revids[] = {
[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
 };
 
+static const struct intel_step_info adlp_rplp_revids[] = {
+   [0x4] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_E0 },
+};
+
 static const struct intel_step_info adlp_n_revids[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
 };
@@ -187,6 +191,9 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ADLP_N(i915)) {
revids = adlp_n_revids;
size = ARRAY_SIZE(adlp_n_revids);
+   } else if (IS_ADLP_RPLP(i915)) {
+   revids = adlp_rplp_revids;
+   size = ARRAY_SIZE(adlp_rplp_revids);
} else if (IS_ALDERLAKE_P(i915)) {
revids = adlp_revids;
size = ARRAY_SIZE(adlp_revids);
-- 
2.38.1

[Intel-gfx] [PATCH v2 2/2] drm/i915/mtl: Skip doubling channel numbers for LPDDR4/LPDDDR5

[Radhakrishna Sripada]

MTL LPDDR5 reported 16b with 8 channels. Previous platforms
reported 32b with 4 channels and hence needed a multiplication
by a factor of 2. Skip increasing the channels for MTL.

v2: Use version check instead of platform check(MattR)

Bspec: 64631
Cc: Matt Roper 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/display/intel_bw.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index 4ace026b29bd..1c236f02b380 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -439,7 +439,8 @@ static int tgl_get_bw_info(struct drm_i915_private 
*dev_priv, const struct intel
return ret;
}
 
-   if (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == 
INTEL_DRAM_LPDDR5)
+   if (DISPLAY_VER(dev_priv) < 14 &&
+   (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == 
INTEL_DRAM_LPDDR5))
num_channels *= 2;
 
qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, 
is_y_tile ? 4 : 2);
-- 
2.34.1

[Intel-gfx] [PATCH v2 1/2] drm/i915/mtl: Fix dram info readout

[Radhakrishna Sripada]

Register info read from the hardware is being cleared out. Preserve
the register value and use extracted fields in the logic.

Fixes: 825477e77912 ("drm/i915/mtl: Obtain SAGV values from MMIO instead of GT 
pcode mailbox")
Cc: Matt Roper 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/intel_dram.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dram.c 
b/drivers/gpu/drm/i915/intel_dram.c
index 2403ccd52c74..bba8cb6e8ae4 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -471,8 +471,7 @@ static int xelpdp_get_dram_info(struct drm_i915_private 
*i915)
u32 val = intel_uncore_read(>uncore, MTL_MEM_SS_INFO_GLOBAL);
struct dram_info *dram_info = >dram_info;
 
-   val = REG_FIELD_GET(MTL_DDR_TYPE_MASK, val);
-   switch (val) {
+   switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
case 0:
dram_info->type = INTEL_DRAM_DDR4;
break;
-- 
2.34.1

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mtl: Enable Idle Messaging for GSC CS

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: Enable Idle Messaging for GSC CS
URL   : https://patchwork.freedesktop.org/series/111011/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12392_full -> Patchwork_111011v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_111011v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-snb:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [FAIL][33], [FAIL][34], [PASS][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], 
[PASS][48], [PASS][49]) ([i915#4338])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb2/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb2/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb2/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb2/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb2/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb4/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb4/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb4/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb4/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb4/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb5/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb5/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb5/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb5/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb5/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb6/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb6/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb6/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb6/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb6/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb7/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb7/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb7/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb7/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/shard-snb7/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb7/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb7/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb7/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb7/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb6/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb6/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb6/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb6/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb6/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb6/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb5/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb5/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb5/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb5/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb5/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb4/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/shard-snb4/boot.html
   [43]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Skip doubling channel numbers for LPDDR4/LPDDDR5

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: Skip doubling channel numbers for LPDDR4/LPDDDR5
URL   : https://patchwork.freedesktop.org/series/111036/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12396 -> Patchwork_111036v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/index.html

Participating hosts (40 -> 37)
--

  Additional (2): fi-rkl-11600 bat-dg1-6 
  Missing(5): fi-ilk-m540 fi-cfl-8700k fi-ctg-p8600 fi-hsw-4770 
fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_111036v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- fi-rkl-11600:   NOTRUN -> [SKIP][1] ([i915#7456])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/fi-rkl-11600/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_huc_copy@huc-copy:
- fi-rkl-11600:   NOTRUN -> [SKIP][2] ([i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-rkl-11600:   NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/fi-rkl-11600/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_mmap@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][4] ([i915#4083])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/bat-dg1-6/igt@gem_m...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][5] ([i915#4079]) +1 similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][7] ([i915#3282])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6:  NOTRUN -> [SKIP][8] ([i915#1155])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html
- fi-rkl-11600:   NOTRUN -> [SKIP][9] ([i915#3012])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
- bat-dg1-6:  NOTRUN -> [SKIP][10] ([i915#6621])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/bat-dg1-6/igt@i915_pm_...@basic-api.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   NOTRUN -> [INCOMPLETE][11] ([i915#4817])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6:  NOTRUN -> [SKIP][12] ([i915#4215])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6:  NOTRUN -> [SKIP][13] ([i915#4212]) +7 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_chamelium@hdmi-crc-fast:
- bat-dg1-6:  NOTRUN -> [SKIP][14] ([fdo#111827]) +8 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-rkl-11600:   NOTRUN -> [SKIP][15] ([fdo#111827]) +7 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/fi-rkl-11600/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-rkl-11600:   NOTRUN -> [SKIP][16] ([i915#4103])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
- bat-dg1-6:  NOTRUN -> [SKIP][17] ([i915#4103] / [i915#4213])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/bat-dg1-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [PASS][18] -> [FAIL][19] ([i915#6298])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [19]: 

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Skip doubling channel numbers for LPDDR4/LPDDDR5

[Matt Roper]

On Thu, Nov 17, 2022 at 11:22:04AM -0800, Radhakrishna Sripada wrote:
> MTL LPDDR5 reported 16b with 8 channels. Previous platforms
> reported 32b with 4 channels and hence needed a mulitplication
> by a factor of 2. Skip increasing the channels for MTL.

Looks like the bspec was just updated a couple weeks ago with this
change.

> 
> While at it fix the logic while reading dram info num channels.

It's probably better to break this out into its own patch since it's an
independent bugfix, not related to the last month's bspec update.

> 
> Bspec: 64631
> Fixes: 825477e77912 ("drm/i915/mtl: Obtain SAGV values from MMIO instead of 
> GT pcode mailbox")
> Signed-off-by: Radhakrishna Sripada 
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 3 ++-
>  drivers/gpu/drm/i915/intel_dram.c   | 3 +--
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 4ace026b29bd..7601e1061bca 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -439,7 +439,8 @@ static int tgl_get_bw_info(struct drm_i915_private 
> *dev_priv, const struct intel
>   return ret;
>   }
>  
> - if (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == 
> INTEL_DRAM_LPDDR5)
> + if (!IS_METEORLAKE(dev_priv) &&

Unless we have a reason to believe otherwise, we should assume that this
change will carry forward to future platforms as well, so this should be
a version check rather than specifically checking IS_METEORLAKE.


Matt

> + (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == 
> INTEL_DRAM_LPDDR5))
>   num_channels *= 2;
>  
>   qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, 
> is_y_tile ? 4 : 2);
> diff --git a/drivers/gpu/drm/i915/intel_dram.c 
> b/drivers/gpu/drm/i915/intel_dram.c
> index 2403ccd52c74..bba8cb6e8ae4 100644
> --- a/drivers/gpu/drm/i915/intel_dram.c
> +++ b/drivers/gpu/drm/i915/intel_dram.c
> @@ -471,8 +471,7 @@ static int xelpdp_get_dram_info(struct drm_i915_private 
> *i915)
>   u32 val = intel_uncore_read(>uncore, MTL_MEM_SS_INFO_GLOBAL);
>   struct dram_info *dram_info = >dram_info;
>  
> - val = REG_FIELD_GET(MTL_DDR_TYPE_MASK, val);
> - switch (val) {
> + switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
>   case 0:
>   dram_info->type = INTEL_DRAM_DDR4;
>   break;
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Manage uncore->lock while waiting on MCR register

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Manage uncore->lock while waiting on MCR register
URL   : https://patchwork.freedesktop.org/series/111033/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12396 -> Patchwork_111033v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/index.html

Participating hosts (40 -> 38)
--

  Additional (1): bat-dg1-6 
  Missing(3): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_111033v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[PASS][1] -> [FAIL][2] ([i915#7229])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_mmap@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][3] ([i915#4083])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/bat-dg1-6/igt@gem_m...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][4] ([i915#4079]) +1 similar issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_blits@basic:
- fi-pnv-d510:[PASS][5] -> [SKIP][6] ([fdo#109271]) +1 similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/fi-pnv-d510/igt@gem_tiled_bl...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][7] ([i915#4077]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6:  NOTRUN -> [SKIP][8] ([i915#1155])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
- bat-dg1-6:  NOTRUN -> [SKIP][9] ([i915#6621])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/bat-dg1-6/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][10] -> [INCOMPLETE][11] ([i915#4785])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6:  NOTRUN -> [SKIP][12] ([i915#4215])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6:  NOTRUN -> [SKIP][13] ([i915#4212]) +7 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_chamelium@hdmi-crc-fast:
- bat-dg1-6:  NOTRUN -> [SKIP][14] ([fdo#111827]) +8 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-dg1-6:  NOTRUN -> [SKIP][15] ([i915#4103] / [i915#4213])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/bat-dg1-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-6:  NOTRUN -> [SKIP][16] ([fdo#109285])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/bat-dg1-6/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_psr@sprite_plane_onoff:
- bat-dg1-6:  NOTRUN -> [SKIP][17] ([i915#1072] / [i915#4078]) +3 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/bat-dg1-6/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-6:  NOTRUN -> [SKIP][18] ([i915#3555])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/bat-dg1-6/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-gtt:
- bat-dg1-6:  NOTRUN -> [SKIP][19] ([i915#3708] / [i915#4077]) +1 
similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/bat-dg1-6/igt@prime_v...@basic-gtt.html

  * igt@prime_vgem@basic-userptr:
- bat-dg1-6:  NOTRUN -> [SKIP][20] ([i915#3708] / [i915#4873])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/bat-dg1-6/igt@prime_v...@basic-userptr.html

  * 

[Intel-gfx] [PATCH] drm/i915/mtl: Skip doubling channel numbers for LPDDR4/LPDDDR5

[Radhakrishna Sripada]

MTL LPDDR5 reported 16b with 8 channels. Previous platforms
reported 32b with 4 channels and hence needed a mulitplication
by a factor of 2. Skip increasing the channels for MTL.

While at it fix the logic while reading dram info num channels.

Bspec: 64631
Fixes: 825477e77912 ("drm/i915/mtl: Obtain SAGV values from MMIO instead of GT 
pcode mailbox")
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/display/intel_bw.c | 3 ++-
 drivers/gpu/drm/i915/intel_dram.c   | 3 +--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index 4ace026b29bd..7601e1061bca 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -439,7 +439,8 @@ static int tgl_get_bw_info(struct drm_i915_private 
*dev_priv, const struct intel
return ret;
}
 
-   if (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == 
INTEL_DRAM_LPDDR5)
+   if (!IS_METEORLAKE(dev_priv) &&
+   (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == 
INTEL_DRAM_LPDDR5))
num_channels *= 2;
 
qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, 
is_y_tile ? 4 : 2);
diff --git a/drivers/gpu/drm/i915/intel_dram.c 
b/drivers/gpu/drm/i915/intel_dram.c
index 2403ccd52c74..bba8cb6e8ae4 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -471,8 +471,7 @@ static int xelpdp_get_dram_info(struct drm_i915_private 
*i915)
u32 val = intel_uncore_read(>uncore, MTL_MEM_SS_INFO_GLOBAL);
struct dram_info *dram_info = >dram_info;
 
-   val = REG_FIELD_GET(MTL_DDR_TYPE_MASK, val);
-   switch (val) {
+   switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
case 0:
dram_info->type = INTEL_DRAM_DDR4;
break;
-- 
2.34.1

[Intel-gfx] [PULL] drm-misc-fixes

[Maarten Lankhorst]

Hi Dave, Daniel,

A few fixes for v6.1-rc6.

Most important one apears to be reverting a change that breaks DP-MST.

drm-misc-fixes-2022-11-17:
drm-misc-fixes for v6.1-rc6:
- Fix error handling in vc4_atomic_commit_tail()
- Set bpc for logictechno panels.
- Fix potential memory leak in drm_dev_init()
- Fix potential null-ptr-deref in drm_vblank_destroy_worker()
- Set lima's clkname corrrectly when regulator is missing.
- Small amdgpu fix to gang submission.
- Revert hiding unregistered connectors from userspace, as it breaks on DP-MST.
- Add workaround for DP++ dual mode adaptors that don't support
  i2c subaddressing.
The following changes since commit f352262f727215553879705bacbcb208979f3eff:

  drm/panfrost: Split io-pgtable requests properly (2022-11-09 14:17:39 +)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2022-11-17

for you to fetch changes up to 5954acbacbd1946b96ce8ee799d309cb0cd3cb9d:

  drm/display: Don't assume dual mode adaptors support i2c sub-addressing 
(2022-11-15 23:31:02 +0200)


drm-misc-fixes for v6.1-rc6:
- Fix error handling in vc4_atomic_commit_tail()
- Set bpc for logictechno panels.
- Fix potential memory leak in drm_dev_init()
- Fix potential null-ptr-deref in drm_vblank_destroy_worker()
- Set lima's clkname corrrectly when regulator is missing.
- Small amdgpu fix to gang submission.
- Revert hiding unregistered connectors from userspace, as it breaks on DP-MST.
- Add workaround for DP++ dual mode adaptors that don't support
  i2c subaddressing.


Aishwarya Kothari (1):
  drm/panel: simple: set bpc field for logic technologies displays

Christian König (1):
  drm/amdgpu: use the last IB as gang leader v2

Erico Nunes (1):
  drm/lima: Fix opp clkname setting in case of missing regulator

Gaosheng Cui (1):
  drm/vc4: kms: Fix IS_ERR() vs NULL check for vc4_kms

Shang XiaoJing (2):
  drm/drv: Fix potential memory leak in drm_dev_init()
  drm: Fix potential null-ptr-deref in drm_vblank_destroy_worker()

Simon Rettberg (1):
  drm/display: Don't assume dual mode adaptors support i2c sub-addressing

Simon Ser (1):
  Revert "drm: hide unregistered connectors from GETCONNECTOR IOCTL"

 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 23 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.h|  1 +
 drivers/gpu/drm/display/drm_dp_dual_mode_helper.c | 51 +--
 drivers/gpu/drm/drm_drv.c |  2 +-
 drivers/gpu/drm/drm_internal.h|  3 +-
 drivers/gpu/drm/drm_mode_config.c |  3 --
 drivers/gpu/drm/lima/lima_devfreq.c   | 15 ---
 drivers/gpu/drm/panel/panel-simple.c  |  2 +
 drivers/gpu/drm/vc4/vc4_kms.c |  8 ++--
 9 files changed, 64 insertions(+), 44 deletions(-)

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Don't disable DDI/Transcoder when setting phy test pattern (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Don't disable DDI/Transcoder when setting phy test 
pattern (rev4)
URL   : https://patchwork.freedesktop.org/series/108636/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12391_full -> Patchwork_108636v4_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_108636v4_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_108636v4_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_108636v4_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_eio@in-flight-suspend:
- shard-skl:  NOTRUN -> [INCOMPLETE][1] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v4/shard-skl1/igt@gem_...@in-flight-suspend.html

  
Known issues


  Here are the changes found in Patchwork_108636v4_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_buddy@all:
- shard-tglb: NOTRUN -> [SKIP][2] ([i915#6433])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v4/shard-tglb5/igt@drm_bu...@all.html

  * igt@gem_ctx_persistence@engines-hang@bcs0:
- shard-skl:  NOTRUN -> [SKIP][3] ([fdo#109271]) +84 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v4/shard-skl9/igt@gem_ctx_persistence@engines-h...@bcs0.html

  * igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12391/shard-iclb1/igt@gem_exec_balan...@parallel-bb-first.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v4/shard-iclb5/igt@gem_exec_balan...@parallel-bb-first.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12391/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v4/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl:  [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12391/shard-apl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v4/shard-apl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v4/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12391/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v4/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_lmem_swapping@verify:
- shard-apl:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v4/shard-apl6/igt@gem_lmem_swapp...@verify.html

  * igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#4270])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v4/shard-tglb5/igt@gem_...@regular-baseline-src-copy-readible.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-tglb: NOTRUN -> [SKIP][15] ([i915#3297]) +1 similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v4/shard-tglb5/igt@gem_userptr_bl...@invalid-mmap-offset-unsync.html

  * igt@gen9_exec_parse@bb-start-far:
- shard-tglb: NOTRUN -> [SKIP][16] ([i915#2527] / [i915#2856])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v4/shard-tglb5/igt@gen9_exec_pa...@bb-start-far.html

  * igt@i915_pm_dc@dc6-psr:
- shard-skl:  NOTRUN -> [FAIL][17] ([i915#3989] / [i915#454])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v4/shard-skl7/igt@i915_pm...@dc6-psr.html
- shard-iclb: [PASS][18] -> [FAIL][19] ([i915#3989] / [i915#454])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12391/shard-iclb8/igt@i915_pm...@dc6-psr.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v4/shard-iclb7/igt@i915_pm...@dc6-psr.html

  * igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- shard-tglb:

[Intel-gfx] [PATCH] drm/i915/gt: Manage uncore->lock while waiting on MCR register

[Matt Roper]

The GT MCR code currently relies on uncore->lock to avoid race
conditions on the steering control register during MCR operations.  The
*_fw() versions of MCR operations expect the caller to already hold
uncore->lock, while the non-fw variants manage the lock internally.
However the sole callsite of intel_gt_mcr_wait_for_reg_fw() does not
currently obtain the forcewake lock, allowing a potential race condition
(and triggering an assertion on lockdep builds).  Furthermore, since
'wait for register value' requests may not return immediately, it is
undesirable to hold a fundamental lock like uncore->lock for the entire
wait and block all other MMIO for the duration; rather the lock is only
needed around the MCR read operations and can be released during the
delays.

Convert intel_gt_mcr_wait_for_reg_fw() to a non-fw variant that will
manage uncore->lock internally.  This does have the side effect of
causing an unnecessary lookup in the forcewake table on each read
operation, but since the caller is still holding the relevant forcewake
domain, this will ultimately just incremenent the reference count and
won't actually cause any additional MMIO traffic.

In the future we plan to switch to a dedicated MCR lock to protect the
steering critical section rather than using the overloaded and
high-traffic uncore->lock; on MTL and beyond the new lock can be
implemented on top of the hardware-provided synchonization mechanism for
steering.

Fixes: 3068bec83eea ("drm/i915/gt: Add intel_gt_mcr_wait_for_reg_fw()")
Cc: Lucas De Marchi 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_gt.c |  6 +++---
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 18 ++
 drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 12 ++--
 3 files changed, 19 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 0325f071046c..b5ad9caa5537 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1035,9 +1035,9 @@ get_reg_and_bit(const struct intel_engine_cs *engine, 
const bool gen8,
 static int wait_for_invalidate(struct intel_gt *gt, struct reg_and_bit rb)
 {
if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
-   return intel_gt_mcr_wait_for_reg_fw(gt, rb.mcr_reg, rb.bit, 0,
-   TLB_INVAL_TIMEOUT_US,
-   TLB_INVAL_TIMEOUT_MS);
+   return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bit, 0,
+TLB_INVAL_TIMEOUT_US,
+TLB_INVAL_TIMEOUT_MS);
else
return __intel_wait_for_register_fw(gt->uncore, rb.reg, rb.bit, 
0,
TLB_INVAL_TIMEOUT_US,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c 
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 830edffe88cc..d9a8ff9e5e57 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -730,17 +730,19 @@ void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, 
unsigned int dss,
  *
  * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
  */
-int intel_gt_mcr_wait_for_reg_fw(struct intel_gt *gt,
-i915_mcr_reg_t reg,
-u32 mask,
-u32 value,
-unsigned int fast_timeout_us,
-unsigned int slow_timeout_ms)
+int intel_gt_mcr_wait_for_reg(struct intel_gt *gt,
+ i915_mcr_reg_t reg,
+ u32 mask,
+ u32 value,
+ unsigned int fast_timeout_us,
+ unsigned int slow_timeout_ms)
 {
-   u32 reg_value = 0;
-#define done (((reg_value = intel_gt_mcr_read_any_fw(gt, reg)) & mask) == 
value)
int ret;
 
+   lockdep_assert_not_held(>uncore->lock);
+
+#define done ((intel_gt_mcr_read_any(gt, reg) & mask) == value)
+
/* Catch any overuse of this function */
might_sleep_if(slow_timeout_ms);
GEM_BUG_ON(fast_timeout_us > 2);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h 
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
index 3fb0502bff22..ae93b20e1c17 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
@@ -37,12 +37,12 @@ void intel_gt_mcr_report_steering(struct drm_printer *p, 
struct intel_gt *gt,
 void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
  unsigned int *group, unsigned int *instance);
 
-int intel_gt_mcr_wait_for_reg_fw(struct intel_gt *gt,
-i915_mcr_reg_t reg,
-u32 mask,
-u32 value,
-unsigned int 

Re: [Intel-gfx] linux-next: manual merge of the drm-misc tree with the origin tree

[Nathan Chancellor]

Hi Stephen,

On Wed, Nov 16, 2022 at 10:57:02AM +1100, Stephen Rothwell wrote:
> Hi all,
> 
> Today's linux-next merge of the drm-misc tree got a conflict in:
> 
>   drivers/gpu/drm/vc4/vc4_hdmi.c
> 
> between commit:
> 
>   682f99b8ae88 ("drm/vc4: hdmi: Take our lock to reset the link")
> 
> from the origin tree and commits:
> 
>   d218750805a3 ("drm/vc4: hdmi: Pass vc4_hdmi to 
> vc4_hdmi_supports_scrambling()")
>   0a99962c0dbf ("drm/vc4: hdmi: Fix pointer dereference before check")
> 
> from the drm-misc tree.
> 
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging.  You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.
> 
> -- 
> Cheers,
> Stephen Rothwell
> 
> diff --cc drivers/gpu/drm/vc4/vc4_hdmi.c
> index d7fcc7a4c082,6b223a5fcf6f..
> --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
> +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
> @@@ -349,12 -348,9 +348,13 @@@ static int vc4_hdmi_reset_link(struct d
>   if (!crtc_state->active)
>   return 0;
>   
>  +mutex_lock(_hdmi->mutex);
>  +
> - if (!vc4_hdmi_supports_scrambling(encoder)) {
> + vc4_hdmi = connector_to_vc4_hdmi(connector);
>  -if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
> ++if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
>  +mutex_unlock(_hdmi->mutex);
>   return 0;
>  +}
>   
>   scrambling_needed = 
> vc4_hdmi_mode_needs_scrambling(_hdmi->saved_adjusted_mode,
>  vc4_hdmi->output_bpc,

This resolution is not quite right, as pointed out by clang:

drivers/gpu/drm/vc4/vc4_hdmi.c:351:14: error: variable 'vc4_hdmi' is 
uninitialized when used here [-Werror,-Wuninitialized]
mutex_lock(_hdmi->mutex);
^~~~
./include/linux/mutex.h:187:44: note: expanded from macro 'mutex_lock'
#define mutex_lock(lock) mutex_lock_nested(lock, 0)
   ^~~~
drivers/gpu/drm/vc4/vc4_hdmi.c:322:27: note: initialize the variable 
'vc4_hdmi' to silence this warning
struct vc4_hdmi *vc4_hdmi;
 ^
  = NULL
1 error generated.

Obviously, the assignment of vc4_hdmi should be before mutex_lock().

Cheers,
Nathan

Re: [Intel-gfx] [PATCH v10 18/19] drm/vc4: vec: Add support for more analog TV standards

[Maxime Ripard]

On Thu, Nov 17, 2022 at 04:49:28PM +0100, Mauro Carvalho Chehab wrote:
> On Thu, 17 Nov 2022 10:29:01 +0100
> Maxime Ripard  wrote:
> 
> > From: Mateusz Kwiatkowski 
> > 
> > Add support for the following composite output modes (all of them are
> > somewhat more obscure than the previously defined ones):
> > 
> > - NTSC_443 - NTSC-style signal with the chroma subcarrier shifted to
> >   4.43361875 MHz (the PAL subcarrier frequency). Never used for
> >   broadcasting, but sometimes used as a hack to play NTSC content in PAL
> >   regions (e.g. on VCRs).
> 
> > - PAL_N - PAL with alternative chroma subcarrier frequency,
> >   3.58205625 MHz. Used as a broadcast standard in Argentina, Paraguay
> >   and Uruguay to fit 576i50 with colour in 6 MHz channel raster.
> 
> That's not right. Argentina uses a different standard than Paraguay and
> Uruguai.
> 
> See, there are two variants of PAL/N. The original one and PAL/N' - also
> called PAL/NC or PAL/CN (Combination N). Some of the timings are 
> different on /NC variant.
> 
> As far as I'm aware, PAL/Nc is used in Argentina, while
> PAL/N is used in Paraguai and Uruguai, but I may be wrong on that,
> as it has been a long time since had to touch on this.
> 
> > - PAL60 - 480i60 signal with PAL-style color at normal European PAL
> >   frequency. Another non-standard, non-broadcast mode, used in similar
> >   contexts as NTSC_443. Some displays support one but not the other.
> 
> > - SECAM - French frequency-modulated analog color standard; also have
> >   been broadcast in Eastern Europe and various parts of Africa and Asia.
> >   Uses the same 576i50 timings as PAL.
> 
> This is also wrong. just like PAL, there are several variants of SECAM,
> one used in France, and a different one in France overseas and on
> previous France colonies in Africa and Asia. Eastern Europe also used
> different variants of SECAM.

And that's fine? Everything I did is supposed to be easy to extend if
and when needed, so if someone has some interest in providing support
for more standards, they are very welcome to do so.

I won't do it in this series though.

Maxime


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Re: [Intel-gfx] [PATCH v4 4/6] drm/i915/pxp: Make PXP tee component bind/unbind aware of PXP-owning-GT

[Rodrigo Vivi]

On Wed, Nov 16, 2022 at 04:30:16PM -0800, Alan Previn wrote:
> Ensure i915_pxp_tee_component_bind / unbind implicitly sorts out
> getting the correct per-GT PXP control-context from the PXP-owning-GT
> when establishing or ending connection. Thus, replace _i915_to_pxp_gt
> with intel_pxp_get_owning_gt (also takes in i915).
> 
> Signed-off-by: Alan Previn 
> Reviewed-by: Daniele Ceraolo Spurio 
> ---
>  drivers/gpu/drm/i915/pxp/intel_pxp.c |  6 +++---
>  drivers/gpu/drm/i915/pxp/intel_pxp.h |  2 ++
>  drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 14 --
>  3 files changed, 17 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c 
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 76a924587543..6a78b6ef0235 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -64,7 +64,7 @@ bool intel_pxp_is_enabled_on_gt(const struct intel_pxp *pxp)
>   return pxp->ce;
>  }
>  
> -static struct intel_gt *i915_to_pxp_gt(struct drm_i915_private *i915)
> +struct intel_gt *intel_pxp_get_owning_gt(struct drm_i915_private *i915)
>  {
>   struct intel_gt *gt = NULL;
>   int i = 0;
> @@ -79,7 +79,7 @@ static struct intel_gt *i915_to_pxp_gt(struct 
> drm_i915_private *i915)
>  
>  bool intel_pxp_is_enabled(struct drm_i915_private *i915)
>  {
> - struct intel_gt *gt = i915_to_pxp_gt(i915);
> + struct intel_gt *gt = intel_pxp_get_owning_gt(i915);
>  
>   if (!gt)
>   return false;
> @@ -94,7 +94,7 @@ bool intel_pxp_is_active_on_gt(const struct intel_pxp *pxp)
>  
>  bool intel_pxp_is_active(struct drm_i915_private *i915)
>  {
> - struct intel_gt *gt = i915_to_pxp_gt(i915);
> + struct intel_gt *gt = intel_pxp_get_owning_gt(i915);
>  
>   if (!gt)
>   return false;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h 
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index fe981eebf0ec..c798c3bde957 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -13,6 +13,8 @@ struct intel_pxp;
>  struct drm_i915_gem_object;
>  struct drm_i915_private;
>  
> +struct intel_gt *intel_pxp_get_owning_gt(struct drm_i915_private *i915);
> +
>  struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp);
>  
>  bool intel_pxp_supported_on_gt(const struct intel_pxp *pxp);
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c 
> b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> index a5c9c692c20d..b9198e961cb6 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -20,8 +20,12 @@
>  static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
>  {
>   struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
> + struct intel_gt *gt = intel_pxp_get_owning_gt(i915);
>  
> - return _gt(i915)->pxp;
> + if (!gt)
> + return NULL;
> +
> + return >pxp;

or pxp is part of gt, what it looks like, then we use per gt and avoid on the 
others...

>  }
>  
>  static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
> @@ -128,10 +132,16 @@ static int i915_pxp_tee_component_bind(struct device 
> *i915_kdev,
>  {
>   struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
>   struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
> - struct intel_uc *uc = _to_gt(pxp)->uc;
> + struct intel_uc *uc;
>   intel_wakeref_t wakeref;
>   int ret = 0;
>  
> + if (!pxp) {
> + drm_warn(>drm, "tee comp binding without a PXP-owner 
> GT\n");

or we have a single pxp component under i915 and we associate with the gt0 only
and save the gt inside the pxp...

but this whole owning thing seems so convoluted...

> + return -ENODEV;
> + }
> + uc = _to_gt(pxp)->uc;
> +
>   mutex_lock(>tee_mutex);
>   pxp->pxp_component = data;
>   pxp->pxp_component->tee_dev = tee_kdev;
> -- 
> 2.34.1
> 

Re: [Intel-gfx] [PATCH v4 3/6] drm/i915/pxp: Make intel_pxp_is_active implicitly sort PXP-owning-GT

[Rodrigo Vivi]

On Wed, Nov 16, 2022 at 04:30:15PM -0800, Alan Previn wrote:
> Make intel_pxp_is_active a global check and implicitly find
> the PXP-owning-GT.
> 
> As per prior two patches, callers of this function shall now
> pass in i915 since PXP is a global GPU feature. Make
> intel_pxp_is_active implicitly find the right gt so it's transparent
> for global view callers (like display or gem-exec).
> 
> However we also need to expose the per-gt variation of this for internal
> pxp files to use (like what intel_pxp_is_active was prior) so also expose
> a new intel_gtpxp_is_active function for replacement.
> 
> Signed-off-by: Alan Previn 
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_context.c  |  2 +-
>  drivers/gpu/drm/i915/pxp/intel_pxp.c | 14 --
>  drivers/gpu/drm/i915/pxp/intel_pxp.h |  3 ++-
>  drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c |  4 ++--
>  drivers/gpu/drm/i915/pxp/intel_pxp_irq.c |  2 +-
>  5 files changed, 18 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index c123f4847b19..165be45a3c13 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -271,7 +271,7 @@ static int proto_context_set_protected(struct 
> drm_i915_private *i915,
>*/
>   pc->pxp_wakeref = intel_runtime_pm_get(>runtime_pm);
>  
> - if (!intel_pxp_is_active(_gt(i915)->pxp))
> + if (!intel_pxp_is_active(i915))
>   ret = intel_pxp_start(_gt(i915)->pxp);
>   }
>  
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c 
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 88105101af79..76a924587543 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -87,11 +87,21 @@ bool intel_pxp_is_enabled(struct drm_i915_private *i915)
>   return intel_pxp_is_enabled_on_gt(>pxp);
>  }
>  
> -bool intel_pxp_is_active(const struct intel_pxp *pxp)
> +bool intel_pxp_is_active_on_gt(const struct intel_pxp *pxp)

if we are asking about the gt we should pass gt

>  {
>   return pxp->arb_is_valid;
>  }
>  
> +bool intel_pxp_is_active(struct drm_i915_private *i915)
> +{
> + struct intel_gt *gt = i915_to_pxp_gt(i915);
> +
> + if (!gt)
> + return false;
> +
> + return intel_pxp_is_active_on_gt(>pxp);

> +}
> +
>  /* KCR register definitions */
>  #define KCR_INIT _MMIO(0x320f0)
>  /* Setting KCR Init bit is required after system boot */
> @@ -287,7 +297,7 @@ int intel_pxp_key_check(struct intel_pxp *pxp,
>   struct drm_i915_gem_object *obj,
>   bool assign)
>  {
> - if (!intel_pxp_is_active(pxp))
> + if (!intel_pxp_is_active_on_gt(pxp))
>   return -ENODEV;
>  
>   if (!i915_gem_object_is_protected(obj))
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h 
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 3f71b1653f74..fe981eebf0ec 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -19,7 +19,8 @@ bool intel_pxp_supported_on_gt(const struct intel_pxp *pxp);
>  
>  bool intel_pxp_is_enabled_on_gt(const struct intel_pxp *pxp);
>  bool intel_pxp_is_enabled(struct drm_i915_private *i915);
> -bool intel_pxp_is_active(const struct intel_pxp *pxp);
> +bool intel_pxp_is_active_on_gt(const struct intel_pxp *pxp);
> +bool intel_pxp_is_active(struct drm_i915_private *i915);
>  
>  void intel_pxp_init(struct intel_pxp *pxp);
>  void intel_pxp_fini(struct intel_pxp *pxp);
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c 
> b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
> index 4d257055434b..52a808fd4704 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
> @@ -25,7 +25,7 @@ static int pxp_info_show(struct seq_file *m, void *data)
>   return 0;
>   }
>  
> - drm_printf(, "active: %s\n", str_yes_no(intel_pxp_is_active(pxp)));
> + drm_printf(, "active: %s\n", 
> str_yes_no(intel_pxp_is_active_on_gt(pxp)));
>   drm_printf(, "instance counter: %u\n", pxp->key_instance);
>  
>   return 0;
> @@ -43,7 +43,7 @@ static int pxp_terminate_set(void *data, u64 val)
>   struct intel_pxp *pxp = data;
>   struct intel_gt *gt = pxp_to_gt(pxp);
>  
> - if (!intel_pxp_is_active(pxp))
> + if (!intel_pxp_is_active_on_gt(pxp))
>   return -ENODEV;
>  
>   /* simulate a termination interrupt */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c 
> b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> index d3c697bf9aab..c25c1979 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> @@ -86,7 +86,7 @@ void intel_pxp_irq_disable(struct intel_pxp *pxp)
>* called in a path were the driver consider the session as valid and
>* doesn't call a termination on restart.
> 

Re: [Intel-gfx] [PATCH v4 2/6] drm/i915/pxp: Make intel_pxp_is_enabled implicitly sort PXP-owning-GT

[Rodrigo Vivi]

On Wed, Nov 16, 2022 at 04:30:14PM -0800, Alan Previn wrote:
> Make intel_pxp_is_enabled a global check and implicitly find the
> PXP-owning-GT.
> 
> PXP feature support is a device-config flag. In preparation for MTL
> PXP control-context shall reside on of the two GT's. That said,
> update intel_pxp_is_enabled to take in i915 as its input and internally
> find the right gt to check if PXP is enabled so its transparent to
> callers of this functions.
> 
> However we also need to expose the per-gt variation of this internal
> pxp files to use (like what intel_pxp_enabled was prior) so also expose
> a new intel_gtpxp_is_enabled function for replacement.
> 
> Signed-off-by: Alan Previn 
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_context.c  |  2 +-
>  drivers/gpu/drm/i915/gem/i915_gem_create.c   |  2 +-
>  drivers/gpu/drm/i915/pxp/intel_pxp.c | 28 ++--
>  drivers/gpu/drm/i915/pxp/intel_pxp.h |  4 ++-
>  drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c |  2 +-
>  drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c |  2 +-
>  drivers/gpu/drm/i915/pxp/intel_pxp_irq.c |  2 +-
>  drivers/gpu/drm/i915/pxp/intel_pxp_pm.c  |  8 +++---
>  drivers/gpu/drm/i915/pxp/intel_pxp_tee.c |  4 +--
>  9 files changed, 40 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 7f2831efc798..c123f4847b19 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -257,7 +257,7 @@ static int proto_context_set_protected(struct 
> drm_i915_private *i915,
>  
>   if (!protected) {
>   pc->uses_protected_content = false;
> - } else if (!intel_pxp_is_enabled(_gt(i915)->pxp)) {
> + } else if (!intel_pxp_is_enabled(i915)) {

if we are asking about pxp we should pass pxp, not i915...

>   ret = -ENODEV;
>   } else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) ||
>  !(pc->user_flags & BIT(UCONTEXT_BANNABLE))) {
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> index 33673fe7ee0a..e44803f9bec4 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> @@ -384,7 +384,7 @@ static int ext_set_protected(struct i915_user_extension 
> __user *base, void *data
>   if (ext.flags)
>   return -EINVAL;
>  
> - if (!intel_pxp_is_enabled(_gt(ext_data->i915)->pxp))
> + if (!intel_pxp_is_enabled(ext_data->i915))
>   return -ENODEV;
>  
>   ext_data->flags |= I915_BO_PROTECTED;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c 
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index d993e752bd36..88105101af79 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -9,6 +9,7 @@
>  #include "intel_pxp_tee.h"
>  #include "gem/i915_gem_context.h"
>  #include "gt/intel_context.h"
> +#include "gt/intel_gt.h"
>  #include "i915_drv.h"
>  
>  /**
> @@ -58,11 +59,34 @@ bool intel_pxp_supported_on_gt(const struct intel_pxp 
> *pxp)
>   INTEL_INFO((pxp_to_gt(pxp))->i915)->has_pxp && 
> VDBOX_MASK(pxp_to_gt(pxp)));
>  }
>  
> -bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
> +bool intel_pxp_is_enabled_on_gt(const struct intel_pxp *pxp)
>  {
>   return pxp->ce;
>  }
>  
> +static struct intel_gt *i915_to_pxp_gt(struct drm_i915_private *i915)
> +{
> + struct intel_gt *gt = NULL;
> + int i = 0;
> +
> + for_each_gt(gt, i915, i) {
> + /* There can be only one GT that supports PXP */
> + if (intel_pxp_supported_on_gt(>pxp))
> + return gt;
> + }
> + return NULL;
> +}
> +
> +bool intel_pxp_is_enabled(struct drm_i915_private *i915)
> +{
> + struct intel_gt *gt = i915_to_pxp_gt(i915);
> +
> + if (!gt)
> + return false;
> +
> + return intel_pxp_is_enabled_on_gt(>pxp);
> +}
> +
>  bool intel_pxp_is_active(const struct intel_pxp *pxp)
>  {
>   return pxp->arb_is_valid;
> @@ -216,7 +240,7 @@ int intel_pxp_start(struct intel_pxp *pxp)
>  {
>   int ret = 0;
>  
> - if (!intel_pxp_is_enabled(pxp))
> + if (!intel_pxp_is_enabled_on_gt(pxp))
>   return -ENODEV;
>  
>   if (wait_for(pxp_component_bound(pxp), 250))
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h 
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index efa83f9d5e24..3f71b1653f74 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -11,12 +11,14 @@
>  
>  struct intel_pxp;
>  struct drm_i915_gem_object;
> +struct drm_i915_private;
>  
>  struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp);
>  
>  bool intel_pxp_supported_on_gt(const struct intel_pxp *pxp);
>  
> -bool intel_pxp_is_enabled(const struct intel_pxp *pxp);
> +bool intel_pxp_is_enabled_on_gt(const struct intel_pxp *pxp);
> +bool 

Re: [Intel-gfx] [PATCH v4 1/6] drm/i915/pxp: Make gt and pxp init/fini aware of PXP-owning-GT

[Rodrigo Vivi]

On Wed, Nov 16, 2022 at 04:30:13PM -0800, Alan Previn wrote:
> In preparation for future MTL-PXP feature support, PXP control
> context should only valid on the correct gt tile. Depending on the
> device-info this depends on which tile owns the VEBOX and KCR.
> PXP is still a global feature though (despite its control-context
> located in the owning GT structure). Additionally, we find
> that the HAS_PXP macro is only used within the pxp module,
> 
> That said, lets drop that HAS_PXP macro altogether and replace it
> with a more fitting named intel_gtpxp_is_supported and helpers
> so that PXP init/fini can use to verify if the referenced gt supports
> PXP or teelink.

Yep, I understand you as I'm not fan of these macros, specially
single usage. But we need to consider that we have multiple dependencies
there and other cases like this in the driver... Well, but I'm not
opposing, but probably better to first get rid of the macro,
then change the behavior of the function on the next patch.

> 
> Add TODO for Meteorlake that will come in future series.

This refactor patch should be standalone, without poputing it with
the changes that didn't came yet to this point.

> 
> Signed-off-by: Alan Previn 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  4 
>  drivers/gpu/drm/i915/pxp/intel_pxp.c | 22 ++--
>  drivers/gpu/drm/i915/pxp/intel_pxp.h |  3 +++
>  drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c |  2 +-
>  4 files changed, 20 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7e3820d2c404..0616e5f0bd31 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -933,10 +933,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  
>  #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)  
> (INTEL_INFO(dev_priv)->has_global_mocs)
>  
> -#define HAS_PXP(dev_priv)  ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \
> - INTEL_INFO(dev_priv)->has_pxp) && \
> - VDBOX_MASK(to_gt(dev_priv)))
> -
>  #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
>  
>  #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c 
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 5efe61f67546..d993e752bd36 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -44,6 +44,20 @@ struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
>   return container_of(pxp, struct intel_gt, pxp);
>  }
>  
> +static bool _gt_needs_teelink(struct intel_gt *gt)
> +{
> + /* TODO: MTL won't rely on CONFIG_INTEL_MEI_PXP but on GSC engine */
> + return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && 
> intel_huc_is_loaded_by_gsc(>uc.huc) &&
> + intel_uc_uses_huc(>uc));
> +}
> +
> +bool intel_pxp_supported_on_gt(const struct intel_pxp *pxp)

If we are asking if it is supported on gt, then the argument must be a gt 
struct.

> +{
> + /* TODO: MTL won't rely on CONFIG_INTEL_MEI_PXP but on GSC engine */
> + return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && 
> IS_ENABLED(CONFIG_DRM_I915_PXP) &&
> + INTEL_INFO((pxp_to_gt(pxp))->i915)->has_pxp && 
> VDBOX_MASK(pxp_to_gt(pxp)));
> +}
> +
>  bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
>  {
>   return pxp->ce;
> @@ -142,17 +156,13 @@ void intel_pxp_init(struct intel_pxp *pxp)
>  {
>   struct intel_gt *gt = pxp_to_gt(pxp);
>  
> - /* we rely on the mei PXP module */
> - if (!IS_ENABLED(CONFIG_INTEL_MEI_PXP))
> - return;

I took a time to understand this movement based on the commit description.
I have the feeling that this patch deserves further split in different patches.

But also, looking a few lines above pxp_to_gt(pxp), I believe we
have further refactor to do sooner. is is one pxp per gt, then we
need to only enable in the gt0?

> -
>   /*
>* If HuC is loaded by GSC but PXP is disabled, we can skip the init of
>* the full PXP session/object management and just init the tee channel.
>*/
> - if (HAS_PXP(gt->i915))
> + if (intel_pxp_supported_on_gt(pxp))
>   pxp_init_full(pxp);
> - else if (intel_huc_is_loaded_by_gsc(>uc.huc) && 
> intel_uc_uses_huc(>uc))
> + else if (_gt_needs_teelink(gt))
>   intel_pxp_tee_component_init(pxp);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h 
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 2da309088c6d..efa83f9d5e24 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -13,6 +13,9 @@ struct intel_pxp;
>  struct drm_i915_gem_object;
>  
>  struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp);
> +
> +bool intel_pxp_supported_on_gt(const struct intel_pxp *pxp);
> +
>  bool intel_pxp_is_enabled(const struct intel_pxp *pxp);
>  bool intel_pxp_is_active(const struct intel_pxp *pxp);
>  
> diff --git 

Re: [Intel-gfx] [PATCH] drm/i915/huc: fix leak of debug object in huc load fence on driver unload

[Ceraolo Spurio, Daniele]

On 11/16/2022 5:29 PM, Brian Norris wrote:

Hi Daniele,

On Thu, Nov 10, 2022 at 04:56:51PM -0800, Daniele Ceraolo Spurio wrote:

The fence is always initialized in huc_init_early, but the cleanup in
huc_fini is only being run if HuC is enabled. This causes a leaking of
the debug object when HuC is disabled/not supported, which can in turn
trigger a warning if we try to register a new debug offset at the same
address on driver reload.

To fix the issue, make sure to always run the cleanup code.

Reported-by: Tvrtko Ursulin 
Reported-by: Brian Norris 
Fixes: 27536e03271d ("drm/i915/huc: track delayed HuC load with a fence")
Signed-off-by: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Brian Norris 
Cc: Alan Previn 
Cc: John Harrison 
---

Note: I didn't manage to repro the reported warning, but I did confirm
that we weren't correctly calling i915_sw_fence_fini and that this patch
fixes that.

I *did* reproduce, and with this patch, I no longer reproduce. So:

Tested-by: Brian Norris 

I see this differs very slightly from the draft version (which didn't
work for me):

https://lore.kernel.org/all/ac5fde11-c17d-8574-c938-c2278d53c...@intel.com/

so presumably that diff is the fix.


The extra diff makes the driver call the cleanup function even if HuC is 
disabled, while the draft version just fixed the cleanup function 
without making sure it was being called.




Thanks a bunch!


Thanks for testing!

Daniele



Brian


  drivers/gpu/drm/i915/gt/uc/intel_huc.c | 12 +++-
  drivers/gpu/drm/i915/gt/uc/intel_uc.c  |  1 +
  2 files changed, 8 insertions(+), 5 deletions(-)

Re: [Intel-gfx] [PATCH v10 18/19] drm/vc4: vec: Add support for more analog TV standards

[Mauro Carvalho Chehab]

On Thu, 17 Nov 2022 10:29:01 +0100
Maxime Ripard  wrote:

> From: Mateusz Kwiatkowski 
> 
> Add support for the following composite output modes (all of them are
> somewhat more obscure than the previously defined ones):
> 
> - NTSC_443 - NTSC-style signal with the chroma subcarrier shifted to
>   4.43361875 MHz (the PAL subcarrier frequency). Never used for
>   broadcasting, but sometimes used as a hack to play NTSC content in PAL
>   regions (e.g. on VCRs).

> - PAL_N - PAL with alternative chroma subcarrier frequency,
>   3.58205625 MHz. Used as a broadcast standard in Argentina, Paraguay
>   and Uruguay to fit 576i50 with colour in 6 MHz channel raster.

That's not right. Argentina uses a different standard than Paraguay and
Uruguai.

See, there are two variants of PAL/N. The original one and PAL/N' - also
called PAL/NC or PAL/CN (Combination N). Some of the timings are 
different on /NC variant.

As far as I'm aware, PAL/Nc is used in Argentina, while
PAL/N is used in Paraguai and Uruguai, but I may be wrong on that,
as it has been a long time since had to touch on this.

> - PAL60 - 480i60 signal with PAL-style color at normal European PAL
>   frequency. Another non-standard, non-broadcast mode, used in similar
>   contexts as NTSC_443. Some displays support one but not the other.

> - SECAM - French frequency-modulated analog color standard; also have
>   been broadcast in Eastern Europe and various parts of Africa and Asia.
>   Uses the same 576i50 timings as PAL.

This is also wrong. just like PAL, there are several variants of SECAM,
one used in France, and a different one in France overseas and on
previous France colonies in Africa and Asia. Eastern Europe also used
different variants of SECAM.

> 
> Also added some comments explaining color subcarrier frequency
> registers.
> 
> Acked-by: Noralf Trønnes 
> Signed-off-by: Mateusz Kwiatkowski 
> Tested-by: Mateusz Kwiatkowski 
> Signed-off-by: Maxime Ripard 
> 
> ---
> Changes in v6:
> - Support PAL60 again
> ---
>  drivers/gpu/drm/vc4/vc4_vec.c | 111 
> --
>  1 file changed, 107 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c
> index a828fc6fb776..d23dbad3cbf6 100644
> --- a/drivers/gpu/drm/vc4/vc4_vec.c
> +++ b/drivers/gpu/drm/vc4/vc4_vec.c
> @@ -46,6 +46,7 @@
>  #define VEC_CONFIG0_YDEL(x)  ((x) << 26)
>  #define VEC_CONFIG0_CDEL_MASKGENMASK(25, 24)
>  #define VEC_CONFIG0_CDEL(x)  ((x) << 24)
> +#define VEC_CONFIG0_SECAM_STDBIT(21)
>  #define VEC_CONFIG0_PBPR_FIL BIT(18)
>  #define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16)
>  #define VEC_CONFIG0_CHROMA_GAIN_UNITY(0 << 16)
> @@ -76,6 +77,27 @@
>  #define VEC_SOFT_RESET   0x10c
>  #define VEC_CLMP0_START  0x144
>  #define VEC_CLMP0_END0x148
> +
> +/*
> + * These set the color subcarrier frequency
> + * if VEC_CONFIG1_CUSTOM_FREQ is enabled.
> + *
> + * VEC_FREQ1_0 contains the most significant 16-bit half-word,
> + * VEC_FREQ3_2 contains the least significant 16-bit half-word.
> + * 0x8000 seems to be equivalent to the pixel clock
> + * (which itself is the VEC clock divided by 8).
> + *
> + * Reference values (with the default pixel clock of 13.5 MHz):
> + *
> + * NTSC  (3579545.[45] Hz) - 0x21F07C1F
> + * PAL   (4433618.75 Hz)   - 0x2A098ACB
> + * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3
> + * PAL-N (3582056.25 Hz)   - 0x21F69446
> + *
> + * NOTE: For SECAM, it is used as the Dr center frequency,
> + * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not;
> + * that is specified as 4406250 Hz, which corresponds to 0x29C71C72.
> + */
>  #define VEC_FREQ3_2  0x180
>  #define VEC_FREQ1_0  0x184
>  
> @@ -118,6 +140,14 @@
>  
>  #define VEC_INTERRUPT_CONTROL0x190
>  #define VEC_INTERRUPT_STATUS 0x194
> +
> +/*
> + * Db center frequency for SECAM; the clock for this is the same as for
> + * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency.
> + *
> + * This is specified as 425 Hz, which corresponds to 0x284BDA13.
> + * That is also the default value, so no need to set it explicitly.
> + */
>  #define VEC_FCW_SECAM_B  0x198
>  #define VEC_SECAM_GAIN_VAL   0x19c
>  
> @@ -197,10 +227,15 @@ enum vc4_vec_tv_mode_id {
>   VC4_VEC_TV_MODE_NTSC_J,
>   VC4_VEC_TV_MODE_PAL,
>   VC4_VEC_TV_MODE_PAL_M,
> + VC4_VEC_TV_MODE_NTSC_443,
> + VC4_VEC_TV_MODE_PAL_60,
> + VC4_VEC_TV_MODE_PAL_N,
> + VC4_VEC_TV_MODE_SECAM,
>  };
>  
>  struct vc4_vec_tv_mode {
>   unsigned int mode;
> + u16 expected_htotal;
>   u32 config0;
>   u32 config1;
>   u32 custom_freq;
> @@ -236,35 +271,68 @@ static const struct debugfs_reg32 vec_regs[] = {
>  static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
>   {
>  

Re: [Intel-gfx] [PATCH v10 05/19] drm/connector: Add TV standard property

[Maxime Ripard]

On Thu, Nov 17, 2022 at 03:35:57PM +0100, Mauro Carvalho Chehab wrote:
> On Thu, 17 Nov 2022 10:28:48 +0100
> Maxime Ripard  wrote:
> 
> > The TV mode property has been around for a while now to select and get the
> > current TV mode output on an analog TV connector.
> > 
> > Despite that property name being generic, its content isn't and has been
> > driver-specific which makes it hard to build any generic behaviour on top
> > of it, both in kernel and user-space.
> > 
> > Let's create a new enum tv norm property, that can contain any of the
> > analog TV standards currently supported by kernel drivers. Each driver can
> > then pass in a bitmask of the modes it supports, and the property
> > creation function will filter out the modes not supported.
> > 
> > We'll then be able to phase out the older tv mode property.
> > 
> > Tested-by: Mateusz Kwiatkowski 
> > Signed-off-by: Maxime Ripard 
> > 
> > ---
> > Changes in v10:
> > - Fix checkpatch warning
> > 
> > Changes in v5:
> > - Create an analog TV properties documentation section, and document TV
> >   Mode there instead of the csv file
> > 
> > Changes in v4:
> > - Add property documentation to kms-properties.csv
> > - Fix documentation
> > ---
> >  Documentation/gpu/drm-kms.rst |   6 ++
> >  drivers/gpu/drm/drm_atomic_uapi.c |   4 ++
> >  drivers/gpu/drm/drm_connector.c   | 122 
> > +-
> >  include/drm/drm_connector.h   |  64 
> >  include/drm/drm_mode_config.h |   8 +++
> >  5 files changed, 203 insertions(+), 1 deletion(-)
> > 
> > diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
> > index b4377a545425..321f2f582c64 100644
> > --- a/Documentation/gpu/drm-kms.rst
> > +++ b/Documentation/gpu/drm-kms.rst
> > @@ -520,6 +520,12 @@ HDMI Specific Connector Properties
> >  .. kernel-doc:: drivers/gpu/drm/drm_connector.c
> > :doc: HDMI connector properties
> >  
> > +Analog TV Specific Connector Properties
> > +--
> > +
> > +.. kernel-doc:: drivers/gpu/drm/drm_connector.c
> > +   :doc: Analog TV Connector Properties
> > +
> >  Standard CRTC Properties
> >  
> >  
> > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c 
> > b/drivers/gpu/drm/drm_atomic_uapi.c
> > index 7f2b9a07fbdf..d867e7f9f2cd 100644
> > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > @@ -700,6 +700,8 @@ static int drm_atomic_connector_set_property(struct 
> > drm_connector *connector,
> > state->tv.margins.bottom = val;
> > } else if (property == config->legacy_tv_mode_property) {
> > state->tv.legacy_mode = val;
> > +   } else if (property == config->tv_mode_property) {
> > +   state->tv.mode = val;
> > } else if (property == config->tv_brightness_property) {
> > state->tv.brightness = val;
> > } else if (property == config->tv_contrast_property) {
> > @@ -810,6 +812,8 @@ drm_atomic_connector_get_property(struct drm_connector 
> > *connector,
> > *val = state->tv.margins.bottom;
> > } else if (property == config->legacy_tv_mode_property) {
> > *val = state->tv.legacy_mode;
> > +   } else if (property == config->tv_mode_property) {
> > +   *val = state->tv.mode;
> > } else if (property == config->tv_brightness_property) {
> > *val = state->tv.brightness;
> > } else if (property == config->tv_contrast_property) {
> > diff --git a/drivers/gpu/drm/drm_connector.c 
> > b/drivers/gpu/drm/drm_connector.c
> > index 06e737ed15f5..07d449736956 100644
> > --- a/drivers/gpu/drm/drm_connector.c
> > +++ b/drivers/gpu/drm/drm_connector.c
> > @@ -984,6 +984,17 @@ static const struct drm_prop_enum_list 
> > drm_dvi_i_subconnector_enum_list[] = {
> >  DRM_ENUM_NAME_FN(drm_get_dvi_i_subconnector_name,
> >  drm_dvi_i_subconnector_enum_list)
> >  
> > +static const struct drm_prop_enum_list drm_tv_mode_enum_list[] = {
> > +   { DRM_MODE_TV_MODE_NTSC, "NTSC" },
> > +   { DRM_MODE_TV_MODE_NTSC_443, "NTSC-443" },
> > +   { DRM_MODE_TV_MODE_NTSC_J, "NTSC-J" },
> > +   { DRM_MODE_TV_MODE_PAL, "PAL" },
> > +   { DRM_MODE_TV_MODE_PAL_M, "PAL-M" },
> > +   { DRM_MODE_TV_MODE_PAL_N, "PAL-N" },
> > +   { DRM_MODE_TV_MODE_SECAM, "SECAM" },
> > +};
> 
> Nack. It sounds a very bad idea to have standards as generic as 
> NTSC, PAL, SECAM. 
> 
> If you take a look at the CCIR/ITU-R specs that define video standards, 
> you'll see that the standard has actually two components:
> 
> 1. the composite color TV signal: PAL, NTSC, SECAM, defined in ITU-R BT1700[1]
> 
> 2. and the conventional analogue TV (the "monochromatic" part),
> as defined in ITU-R BT.1701[2], which is, basically, a letter from A to N
> (with some country-specific variants, like Nc). Two of those standards
> (M and J) are used on Countries with a power grid of 60Hz, as they have
> a frame rate of either 30fps or 29.997fps.
> 
> [1] 

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/1] drm/i915: use the original Wa_14010685332 for PCH_ADP

[Patchwork]

== Series Details ==

Series: series starting with [1/1] drm/i915: use the original Wa_14010685332 
for PCH_ADP
URL   : https://patchwork.freedesktop.org/series/110988/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12391_full -> Patchwork_110988v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_110988v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_buddy@all:
- shard-tglb: NOTRUN -> [SKIP][1] ([i915#6433])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110988v1/shard-tglb3/igt@drm_bu...@all.html

  * igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][2] -> [FAIL][3] ([i915#6268])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12391/shard-tglb3/igt@gem_ctx_e...@basic-nohangcheck.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110988v1/shard-tglb6/igt@gem_ctx_e...@basic-nohangcheck.html

  * igt@gem_ctx_persistence@engines-hang@bcs0:
- shard-skl:  NOTRUN -> [SKIP][4] ([fdo#109271]) +82 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110988v1/shard-skl5/igt@gem_ctx_persistence@engines-h...@bcs0.html

  * igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12391/shard-iclb1/igt@gem_exec_balan...@parallel-bb-first.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110988v1/shard-iclb5/igt@gem_exec_balan...@parallel-bb-first.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-glk:  [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12391/shard-glk5/igt@gem_exec_fair@basic-n...@vcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110988v1/shard-glk9/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12391/shard-apl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110988v1/shard-apl8/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110988v1/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12391/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110988v1/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_fenced_exec_thrash@2-spare-fences:
- shard-skl:  [PASS][14] -> [DMESG-WARN][15] ([i915#1982])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12391/shard-skl7/igt@gem_fenced_exec_thr...@2-spare-fences.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110988v1/shard-skl6/igt@gem_fenced_exec_thr...@2-spare-fences.html

  * igt@gem_lmem_swapping@verify-random:
- shard-skl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110988v1/shard-skl1/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#4270])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110988v1/shard-tglb3/igt@gem_...@regular-baseline-src-copy-readible.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-tglb: NOTRUN -> [SKIP][18] ([i915#3297]) +1 similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110988v1/shard-tglb3/igt@gem_userptr_bl...@invalid-mmap-offset-unsync.html

  * igt@gen9_exec_parse@bb-start-far:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#2527] / [i915#2856])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110988v1/shard-tglb3/igt@gen9_exec_pa...@bb-start-far.html

  * igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][20] -> [FAIL][21] ([i915#3989] / [i915#454])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12391/shard-iclb8/igt@i915_pm...@dc6-psr.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110988v1/shard-iclb7/igt@i915_pm...@dc6-psr.html

  * igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- shard-tglb: NOTRUN -> [WARN][22] ([i915#2681]) +3 similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110988v1/shard-tglb3/igt@i915_pm_rc6_residency@rc6-i...@rcs0.html

  * 

Re: [Intel-gfx] [PATCH v10 05/19] drm/connector: Add TV standard property

[Mauro Carvalho Chehab]

On Thu, 17 Nov 2022 10:28:48 +0100
Maxime Ripard  wrote:

> The TV mode property has been around for a while now to select and get the
> current TV mode output on an analog TV connector.
> 
> Despite that property name being generic, its content isn't and has been
> driver-specific which makes it hard to build any generic behaviour on top
> of it, both in kernel and user-space.
> 
> Let's create a new enum tv norm property, that can contain any of the
> analog TV standards currently supported by kernel drivers. Each driver can
> then pass in a bitmask of the modes it supports, and the property
> creation function will filter out the modes not supported.
> 
> We'll then be able to phase out the older tv mode property.
> 
> Tested-by: Mateusz Kwiatkowski 
> Signed-off-by: Maxime Ripard 
> 
> ---
> Changes in v10:
> - Fix checkpatch warning
> 
> Changes in v5:
> - Create an analog TV properties documentation section, and document TV
>   Mode there instead of the csv file
> 
> Changes in v4:
> - Add property documentation to kms-properties.csv
> - Fix documentation
> ---
>  Documentation/gpu/drm-kms.rst |   6 ++
>  drivers/gpu/drm/drm_atomic_uapi.c |   4 ++
>  drivers/gpu/drm/drm_connector.c   | 122 
> +-
>  include/drm/drm_connector.h   |  64 
>  include/drm/drm_mode_config.h |   8 +++
>  5 files changed, 203 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
> index b4377a545425..321f2f582c64 100644
> --- a/Documentation/gpu/drm-kms.rst
> +++ b/Documentation/gpu/drm-kms.rst
> @@ -520,6 +520,12 @@ HDMI Specific Connector Properties
>  .. kernel-doc:: drivers/gpu/drm/drm_connector.c
> :doc: HDMI connector properties
>  
> +Analog TV Specific Connector Properties
> +--
> +
> +.. kernel-doc:: drivers/gpu/drm/drm_connector.c
> +   :doc: Analog TV Connector Properties
> +
>  Standard CRTC Properties
>  
>  
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c 
> b/drivers/gpu/drm/drm_atomic_uapi.c
> index 7f2b9a07fbdf..d867e7f9f2cd 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -700,6 +700,8 @@ static int drm_atomic_connector_set_property(struct 
> drm_connector *connector,
>   state->tv.margins.bottom = val;
>   } else if (property == config->legacy_tv_mode_property) {
>   state->tv.legacy_mode = val;
> + } else if (property == config->tv_mode_property) {
> + state->tv.mode = val;
>   } else if (property == config->tv_brightness_property) {
>   state->tv.brightness = val;
>   } else if (property == config->tv_contrast_property) {
> @@ -810,6 +812,8 @@ drm_atomic_connector_get_property(struct drm_connector 
> *connector,
>   *val = state->tv.margins.bottom;
>   } else if (property == config->legacy_tv_mode_property) {
>   *val = state->tv.legacy_mode;
> + } else if (property == config->tv_mode_property) {
> + *val = state->tv.mode;
>   } else if (property == config->tv_brightness_property) {
>   *val = state->tv.brightness;
>   } else if (property == config->tv_contrast_property) {
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 06e737ed15f5..07d449736956 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -984,6 +984,17 @@ static const struct drm_prop_enum_list 
> drm_dvi_i_subconnector_enum_list[] = {
>  DRM_ENUM_NAME_FN(drm_get_dvi_i_subconnector_name,
>drm_dvi_i_subconnector_enum_list)
>  
> +static const struct drm_prop_enum_list drm_tv_mode_enum_list[] = {
> + { DRM_MODE_TV_MODE_NTSC, "NTSC" },
> + { DRM_MODE_TV_MODE_NTSC_443, "NTSC-443" },
> + { DRM_MODE_TV_MODE_NTSC_J, "NTSC-J" },
> + { DRM_MODE_TV_MODE_PAL, "PAL" },
> + { DRM_MODE_TV_MODE_PAL_M, "PAL-M" },
> + { DRM_MODE_TV_MODE_PAL_N, "PAL-N" },
> + { DRM_MODE_TV_MODE_SECAM, "SECAM" },
> +};

Nack. It sounds a very bad idea to have standards as generic as 
NTSC, PAL, SECAM. 

If you take a look at the CCIR/ITU-R specs that define video standards, 
you'll see that the standard has actually two components:

1. the composite color TV signal: PAL, NTSC, SECAM, defined in ITU-R BT1700[1]

2. and the conventional analogue TV (the "monochromatic" part),
as defined in ITU-R BT.1701[2], which is, basically, a letter from A to N
(with some country-specific variants, like Nc). Two of those standards
(M and J) are used on Countries with a power grid of 60Hz, as they have
a frame rate of either 30fps or 29.997fps.

[1] https://www.itu.int/rec/R-REC-BT.1700-0-200502-I/en
[2] https://www.itu.int/rec/R-REC-BT.1701-1-200508-I/en

The actual combination is defined within Country-specific laws, which
selects a conventional analogue signal with a composite color one.

So, for instance, US uses 

Re: [Intel-gfx] [PATCH 1/4] drm/i915/hti: abstract hti handling

[Jani Nikula]

On Thu, 17 Nov 2022, Ville Syrjälä  wrote:
> On Wed, Nov 09, 2022 at 04:42:06PM +0200, Jani Nikula wrote:
>> The HTI or HDPORT handling is sprinkled around. Centralize to one place.
>> 
>> Add a note about how subtle the mapping from HDPORT_STATE register to
>> dpll mask actually is.
>> 
>> Signed-off-by: Jani Nikula 
>> ---
>>  drivers/gpu/drm/i915/Makefile |  1 +
>>  drivers/gpu/drm/i915/display/intel_ddi.c  |  9 +
>>  drivers/gpu/drm/i915/display/intel_display.c  |  8 +---
>>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 +-
>>  drivers/gpu/drm/i915/display/intel_hti.c  | 39 +++
>>  drivers/gpu/drm/i915/display/intel_hti.h  | 18 +
>>  drivers/gpu/drm/i915/display/intel_hti_regs.h | 16 
>>  drivers/gpu/drm/i915/i915_reg.h   |  5 ---
>>  8 files changed, 80 insertions(+), 27 deletions(-)
>>  create mode 100644 drivers/gpu/drm/i915/display/intel_hti.c
>>  create mode 100644 drivers/gpu/drm/i915/display/intel_hti.h
>>  create mode 100644 drivers/gpu/drm/i915/display/intel_hti_regs.h
>> 
>> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>> index 51704b54317c..cb8232bd315b 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -247,6 +247,7 @@ i915-y += \
>>  display/intel_global_state.o \
>>  display/intel_hdcp.o \
>>  display/intel_hotplug.o \
>> +display/intel_hti.o \
>>  display/intel_lpe_audio.o \
>>  display/intel_modeset_verify.o \
>>  display/intel_modeset_setup.o \
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
>> b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index e95bde5cf060..5be9573bf65c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -56,6 +56,7 @@
>>  #include "intel_hdcp.h"
>>  #include "intel_hdmi.h"
>>  #include "intel_hotplug.h"
>> +#include "intel_hti.h"
>>  #include "intel_lspcon.h"
>>  #include "intel_mg_phy_regs.h"
>>  #include "intel_pps.h"
>> @@ -4113,12 +4114,6 @@ intel_ddi_max_lanes(struct intel_digital_port 
>> *dig_port)
>>  return max_lanes;
>>  }
>>  
>> -static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
>> -{
>> -return i915->hti_state & HDPORT_ENABLED &&
>> -   i915->hti_state & HDPORT_DDI_USED(phy);
>> -}
>> -
>>  static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
>>enum port port)
>>  {
>> @@ -4247,7 +4242,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
>> enum port port)
>>   * driver.  In that case we should skip initializing the corresponding
>>   * outputs.
>>   */
>> -if (hti_uses_phy(dev_priv, phy)) {
>> +if (intel_hti_uses_phy(dev_priv, phy)) {
>>  drm_dbg_kms(_priv->drm, "PORT %c / PHY %c reserved by 
>> HTI\n",
>>  port_name(port), phy_name(phy));
>>  return;
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index 0d3353c403af..90219e7abc7c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -100,6 +100,7 @@
>>  #include "intel_frontbuffer.h"
>>  #include "intel_hdcp.h"
>>  #include "intel_hotplug.h"
>> +#include "intel_hti.h"
>>  #include "intel_modeset_verify.h"
>>  #include "intel_modeset_setup.h"
>>  #include "intel_overlay.h"
>> @@ -8735,12 +8736,7 @@ int intel_modeset_init_nogem(struct drm_i915_private 
>> *i915)
>>  if (i915->display.cdclk.max_cdclk_freq == 0)
>>  intel_update_max_cdclk(i915);
>>  
>> -/*
>> - * If the platform has HTI, we need to find out whether it has reserved
>> - * any display resources before we create our display outputs.
>> - */
>> -if (INTEL_INFO(i915)->display.has_hti)
>> -i915->hti_state = intel_de_read(i915, HDPORT_STATE);
>> +intel_hti_init(i915);
>>  
>>  /* Just disable it once at startup */
>>  intel_vga_disable(i915);
>> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
>> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> index 7c6c094a0a01..28f7dcb170c7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> @@ -30,6 +30,7 @@
>>  #include "intel_dpio_phy.h"
>>  #include "intel_dpll.h"
>>  #include "intel_dpll_mgr.h"
>> +#include "intel_hti.h"
>>  #include "intel_mg_phy_regs.h"
>>  #include "intel_pch_refclk.h"
>>  #include "intel_tc.h"
>> @@ -3163,14 +3164,6 @@ static void icl_update_active_dpll(struct 
>> intel_atomic_state *state,
>>  icl_set_active_port_dpll(crtc_state, port_dpll_id);
>>  }
>>  
>> -static u32 intel_get_hti_plls(struct drm_i915_private *i915)
>> -{
>> -if (!(i915->hti_state & HDPORT_ENABLED))
>> -return 0;
>> -
>> -return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state);
>> -}
>> -
>>  static int 

Re: [Intel-gfx] [PATCH v4 9/9] drm/i915/mtl+: Don't enable the AUX_IO power for non-eDP port main links

[Imre Deak]

On Thu, Nov 17, 2022 at 03:24:51PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 14, 2022 at 02:22:51PM +0200, Imre Deak wrote:
> > MTL+ requires the AUX_IO power for the main link only on eDP, so don't
> > enable it in other cases.
> > 
> > v2:
> > - Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr.
> > 
> > Cc: Ville Syrjälä 
> > Signed-off-by: Imre Deak 
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 0231b273e1673..9bf303e166e1a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -868,8 +868,9 @@ intel_ddi_main_link_aux_domain(struct 
> > intel_digital_port *dig_port,
> >  */
> > if (intel_encoder_can_psr(_port->base))
> > return intel_display_power_aux_io_domain(i915, 
> > dig_port->aux_ch);
> > -   else if (intel_crtc_has_dp_encoder(crtc_state) ||
> > -intel_phy_is_tc(i915, phy))
> > +   else if (DISPLAY_VER(i915) < 14 &&
> > +(intel_crtc_has_dp_encoder(crtc_state) ||
> 
> You want to keep that for now, and maybe remove later I guess?

Yes, according to
https://lore.kernel.org/intel-gfx/20221107170917.3566758-5-imre.d...@intel.com/T/#m49ef1ce586700e1

> Series looks OK to me.
> Reviewed-by: Ville Syrjälä 

Thanks.

> 
> > + intel_phy_is_tc(i915, phy)))
> > return intel_aux_power_domain(dig_port);
> > else
> > return POWER_DOMAIN_INVALID;
> > -- 
> > 2.37.1
> 
> -- 
> Ville Syrjälä
> Intel

Re: [Intel-gfx] [PULL] gvt-next

[Rodrigo Vivi]

On Thu, Nov 17, 2022 at 02:41:06PM +0800, Zhenyu Wang wrote:
> On 2022.11.17 03:37:17 +, Vivi, Rodrigo wrote:
> > On Thu, 2022-11-17 at 11:02 +0800, Zhenyu Wang wrote:
> > > On 2022.11.15 10:36:59 -0500, Rodrigo Vivi wrote:
> > > > On Fri, Nov 11, 2022 at 04:59:03PM +0800, Zhenyu Wang wrote:
> > > > > Hi,
> > > > > 
> > > > > Here's current accumulated changes in gvt-next. Sorry that I
> > > > > delayed
> > > > > to refresh them on time for upstream...It contains mostly kernel
> > > > > doc,
> > > > > typo fixes and small code cleanups, as details below.
> > > > > 
> > > > > btw, one gvt change for next
> > > > > https://patchwork.freedesktop.org/patch/58/
> > > > > is still pending, I need a backmerge from linus tree e.g with
> > > > > recent vfio/mdev
> > > > > consolidate change with gvt and Jason's fix for destroy device,
> > > > > to apply Zhi's
> > > > > change cleanly. Pls help on that.
> > > > > 
> 
> > 
> > Based on what I could verify the commiter signature is really not
> > there. It looks like you later forced a rebase and while
> > rebasing you forgot to re-sign everything.
> > 
> 
> Hi, pls re-pull this one.

This one worked out. Pulled, thanks!

> 
> thanks!
> ---
> The following changes since commit a6ebd538364b1e9e6048faaafbc0188172ed50c3:
> 
>   drm/i915/sdvo: Fix debug print (2022-10-28 14:46:21 +0300)
> 
> are available in the Git repository at:
> 
>   https://github.com/intel/gvt-linux.git tags/gvt-next-2022-11-17
> 
> for you to fetch changes up to 04ec334e1a0381c3305da4d277cef9250769ca43:
> 
>   drm/i915/gvt: Remove the unused function get_pt_type() (2022-11-17 14:07:09 
> +0800)
> 
> 
> gvt-next-2022-11-17
> 
> - kernel doc fixes
> - remove vgpu->released sanity check
> - small clean up
> 
> 
> Colin Ian King (1):
>   drm/i915/reg: Fix spelling mistake "Unsupport" -> "Unsupported"
> 
> Jiapeng Chong (4):
>   drm/i915/gvt: Fix kernel-doc
>   drm/i915/gvt: Fix kernel-doc
>   drm/i915/gvt: Fix kernel-doc
>   drm/i915/gvt: Remove the unused function get_pt_type()
> 
> Julia Lawall (1):
>   drm/i915/gvt: fix typo in comment
> 
> Mauro Carvalho Chehab (1):
>   drm/i915: gvt: fix kernel-doc trivial warnings
> 
> Paulo Miguel Almeida (1):
>   i915/gvt: remove hardcoded value on crc32_start calculation
> 
> Zhi Wang (1):
>   drm/i915/gvt: remove the vgpu->released and its sanity check
> 
> wangjianli (1):
>   drm/i915: fix repeated words in comments
> 
>  drivers/gpu/drm/i915/gvt/aperture_gm.c  | 4 ++--
>  drivers/gpu/drm/i915/gvt/cfg_space.c| 2 +-
>  drivers/gpu/drm/i915/gvt/dmabuf.h   | 2 +-
>  drivers/gpu/drm/i915/gvt/firmware.c | 2 +-
>  drivers/gpu/drm/i915/gvt/gtt.c  | 9 ++---
>  drivers/gpu/drm/i915/gvt/gvt.h  | 2 --
>  drivers/gpu/drm/i915/gvt/handlers.c | 4 ++--
>  drivers/gpu/drm/i915/gvt/kvmgt.c| 4 
>  drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
>  drivers/gpu/drm/i915/gvt/page_track.c   | 2 +-
>  drivers/gpu/drm/i915/gvt/vgpu.c | 6 +++---
>  11 files changed, 14 insertions(+), 25 deletions(-)

Re: [Intel-gfx] [PATCH v4 9/9] drm/i915/mtl+: Don't enable the AUX_IO power for non-eDP port main links

[Ville Syrjälä]

On Mon, Nov 14, 2022 at 02:22:51PM +0200, Imre Deak wrote:
> MTL+ requires the AUX_IO power for the main link only on eDP, so don't
> enable it in other cases.
> 
> v2:
> - Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr.
> 
> Cc: Ville Syrjälä 
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 0231b273e1673..9bf303e166e1a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -868,8 +868,9 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port 
> *dig_port,
>*/
>   if (intel_encoder_can_psr(_port->base))
>   return intel_display_power_aux_io_domain(i915, 
> dig_port->aux_ch);
> - else if (intel_crtc_has_dp_encoder(crtc_state) ||
> -  intel_phy_is_tc(i915, phy))
> + else if (DISPLAY_VER(i915) < 14 &&
> +  (intel_crtc_has_dp_encoder(crtc_state) ||

You want to keep that for now, and maybe remove later I guess?

Series looks OK to me.
Reviewed-by: Ville Syrjälä 

> +   intel_phy_is_tc(i915, phy)))
>   return intel_aux_power_domain(dig_port);
>   else
>   return POWER_DOMAIN_INVALID;
> -- 
> 2.37.1

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 1/4] drm/i915/hti: abstract hti handling

[Ville Syrjälä]

On Wed, Nov 09, 2022 at 04:42:06PM +0200, Jani Nikula wrote:
> The HTI or HDPORT handling is sprinkled around. Centralize to one place.
> 
> Add a note about how subtle the mapping from HDPORT_STATE register to
> dpll mask actually is.
> 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/Makefile |  1 +
>  drivers/gpu/drm/i915/display/intel_ddi.c  |  9 +
>  drivers/gpu/drm/i915/display/intel_display.c  |  8 +---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 +-
>  drivers/gpu/drm/i915/display/intel_hti.c  | 39 +++
>  drivers/gpu/drm/i915/display/intel_hti.h  | 18 +
>  drivers/gpu/drm/i915/display/intel_hti_regs.h | 16 
>  drivers/gpu/drm/i915/i915_reg.h   |  5 ---
>  8 files changed, 80 insertions(+), 27 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_hti.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_hti.h
>  create mode 100644 drivers/gpu/drm/i915/display/intel_hti_regs.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 51704b54317c..cb8232bd315b 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -247,6 +247,7 @@ i915-y += \
>   display/intel_global_state.o \
>   display/intel_hdcp.o \
>   display/intel_hotplug.o \
> + display/intel_hti.o \
>   display/intel_lpe_audio.o \
>   display/intel_modeset_verify.o \
>   display/intel_modeset_setup.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index e95bde5cf060..5be9573bf65c 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -56,6 +56,7 @@
>  #include "intel_hdcp.h"
>  #include "intel_hdmi.h"
>  #include "intel_hotplug.h"
> +#include "intel_hti.h"
>  #include "intel_lspcon.h"
>  #include "intel_mg_phy_regs.h"
>  #include "intel_pps.h"
> @@ -4113,12 +4114,6 @@ intel_ddi_max_lanes(struct intel_digital_port 
> *dig_port)
>   return max_lanes;
>  }
>  
> -static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
> -{
> - return i915->hti_state & HDPORT_ENABLED &&
> -i915->hti_state & HDPORT_DDI_USED(phy);
> -}
> -
>  static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
> enum port port)
>  {
> @@ -4247,7 +4242,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
> enum port port)
>* driver.  In that case we should skip initializing the corresponding
>* outputs.
>*/
> - if (hti_uses_phy(dev_priv, phy)) {
> + if (intel_hti_uses_phy(dev_priv, phy)) {
>   drm_dbg_kms(_priv->drm, "PORT %c / PHY %c reserved by 
> HTI\n",
>   port_name(port), phy_name(phy));
>   return;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0d3353c403af..90219e7abc7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -100,6 +100,7 @@
>  #include "intel_frontbuffer.h"
>  #include "intel_hdcp.h"
>  #include "intel_hotplug.h"
> +#include "intel_hti.h"
>  #include "intel_modeset_verify.h"
>  #include "intel_modeset_setup.h"
>  #include "intel_overlay.h"
> @@ -8735,12 +8736,7 @@ int intel_modeset_init_nogem(struct drm_i915_private 
> *i915)
>   if (i915->display.cdclk.max_cdclk_freq == 0)
>   intel_update_max_cdclk(i915);
>  
> - /*
> -  * If the platform has HTI, we need to find out whether it has reserved
> -  * any display resources before we create our display outputs.
> -  */
> - if (INTEL_INFO(i915)->display.has_hti)
> - i915->hti_state = intel_de_read(i915, HDPORT_STATE);
> + intel_hti_init(i915);
>  
>   /* Just disable it once at startup */
>   intel_vga_disable(i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 7c6c094a0a01..28f7dcb170c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -30,6 +30,7 @@
>  #include "intel_dpio_phy.h"
>  #include "intel_dpll.h"
>  #include "intel_dpll_mgr.h"
> +#include "intel_hti.h"
>  #include "intel_mg_phy_regs.h"
>  #include "intel_pch_refclk.h"
>  #include "intel_tc.h"
> @@ -3163,14 +3164,6 @@ static void icl_update_active_dpll(struct 
> intel_atomic_state *state,
>   icl_set_active_port_dpll(crtc_state, port_dpll_id);
>  }
>  
> -static u32 intel_get_hti_plls(struct drm_i915_private *i915)
> -{
> - if (!(i915->hti_state & HDPORT_ENABLED))
> - return 0;
> -
> - return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state);
> -}
> -
>  static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
>  {
> @@ 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/pxp: Prepare intel_pxp entry points for MTL (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/pxp: Prepare intel_pxp entry points for MTL (rev4)
URL   : https://patchwork.freedesktop.org/series/109429/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12390_full -> Patchwork_109429v4_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_109429v4_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109429v4_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109429v4_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_fence@syncobj-backward-timeline-chain-engines:
- shard-skl:  [PASS][1] -> [WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl3/igt@gem_exec_fe...@syncobj-backward-timeline-chain-engines.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109429v4/shard-skl5/igt@gem_exec_fe...@syncobj-backward-timeline-chain-engines.html

  * igt@kms_vblank@pipe-c-accuracy-idle:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-tglb7/igt@kms_vbl...@pipe-c-accuracy-idle.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109429v4/shard-tglb8/igt@kms_vbl...@pipe-c-accuracy-idle.html

  
Known issues


  Here are the changes found in Patchwork_109429v4_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-skl:  ([PASS][5], [PASS][6], [PASS][7], [PASS][8], 
[PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], 
[PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], 
[PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) -> 
([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], 
[PASS][33], [PASS][34], [FAIL][35], [PASS][36], [PASS][37], [PASS][38], 
[PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], 
[PASS][45], [PASS][46], [PASS][47], [PASS][48]) ([i915#5032])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl9/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl9/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl7/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl6/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl6/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl6/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl5/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl5/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl4/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl3/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl3/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl2/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl1/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl1/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl1/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl10/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl10/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl10/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109429v4/shard-skl10/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109429v4/shard-skl10/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109429v4/shard-skl10/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109429v4/shard-skl1/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109429v4/shard-skl1/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109429v4/shard-skl1/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109429v4/shard-skl2/boot.html
   [34]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dmc: Add MTL DMC firmware v2.10

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Add MTL DMC firmware v2.10
URL   : https://patchwork.freedesktop.org/series/111020/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12392 -> Patchwork_111020v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/index.html

Participating hosts (27 -> 38)
--

  Additional (14): bat-dg1-7 bat-dg1-6 bat-dg1-5 bat-dg2-8 bat-adlm-1 bat-dg2-9 
bat-adlp-6 bat-adlp-4 bat-adln-1 bat-rplp-1 bat-rpls-2 bat-dg2-11 fi-bsw-kefka 
bat-jsl-1 
  Missing(3): fi-kbl-soraka bat-kbl-2 bat-jsl-3 

Known issues


  Here are the changes found in Patchwork_111020v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-adlp-4: NOTRUN -> [SKIP][1] ([i915#7456])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-adlp-4/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_lmem_swapping@verify-random:
- bat-adlp-4: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-adlp-4/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-dg1-5:  NOTRUN -> [SKIP][3] ([i915#4083])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-dg1-5/igt@gem_m...@basic.html
- bat-dg1-6:  NOTRUN -> [SKIP][4] ([i915#4083])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-dg1-6/igt@gem_m...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][5] ([i915#4079]) +1 similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html
- bat-dg1-5:  NOTRUN -> [SKIP][7] ([i915#4077]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg1-5:  NOTRUN -> [SKIP][8] ([i915#4079]) +1 similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-dg1-5/igt@gem_tiled_pread_basic.html
- bat-adlp-4: NOTRUN -> [SKIP][9] ([i915#3282])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-adlp-4/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6:  NOTRUN -> [SKIP][10] ([i915#1155])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html
- bat-dg1-5:  NOTRUN -> [SKIP][11] ([i915#1155])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
- bat-dg1-6:  NOTRUN -> [SKIP][12] ([i915#6621])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-dg1-6/igt@i915_pm_...@basic-api.html
- bat-dg1-5:  NOTRUN -> [SKIP][13] ([i915#6621])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-dg1-5/igt@i915_pm_...@basic-api.html
- bat-adlp-4: NOTRUN -> [SKIP][14] ([i915#6621])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-adlp-4/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-5:  NOTRUN -> [INCOMPLETE][15] ([i915#4418])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-dg1-5/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@mman:
- fi-rkl-guc: [PASS][16] -> [TIMEOUT][17] ([i915#6794])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/fi-rkl-guc/igt@i915_selftest@l...@mman.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/fi-rkl-guc/igt@i915_selftest@l...@mman.html

  * igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-dg1-5:  NOTRUN -> [SKIP][18] ([i915#4212]) +7 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-dg1-5/igt@kms_addfb_ba...@basic-x-tiled-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-5:  NOTRUN -> [SKIP][19] ([i915#4215])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-dg1-5/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
- bat-dg1-6:  NOTRUN -> [SKIP][20] ([i915#4215])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111020v1/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6:  NOTRUN -> [SKIP][21] 

Re: [Intel-gfx] [PATCH v10 01/19] drm/tests: client: Mention that we can't use MODULE_ macros

[Noralf Trønnes]

Den 17.11.2022 10.28, skrev Maxime Ripard:
> That file is included directly, so we can't use any MODULE macro. Let's
> leave a comment to avoid any future mistake.
> 
> Signed-off-by: Maxime Ripard 
> ---

Reviewed-by: Noralf Trønnes 

Re: [Intel-gfx] [PATCH 1/2] drm/print: Add drm_dbg_ratelimited

[Matthew Auld]

On Thu, 13 Oct 2022 at 09:40, Nirmoy Das  wrote:
>
> Add a function for ratelimitted debug print.
>
> Cc: Maarten Lankhorst 
> Cc: Maxime Ripard 
> Cc: Thomas Zimmermann 
> Cc: David Airlie 
> Cc: Daniel Vetter 
> Signed-off-by: Nirmoy Das 
Reviewed-by: Matthew Auld 

> ---
>  include/drm/drm_print.h | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
> index 22fabdeed297..1e2e26378570 100644
> --- a/include/drm/drm_print.h
> +++ b/include/drm/drm_print.h
> @@ -562,6 +562,9 @@ void __drm_err(const char *format, ...);
> drm_dev_printk(drm_ ? drm_->dev : NULL, KERN_DEBUG, fmt, ## 
> __VA_ARGS__);   \
>  })
>
> +#define drm_dbg_ratelimited(drm, fmt, ...) \
> +   __DRM_DEFINE_DBG_RATELIMITED(DRIVER, drm, fmt, ## __VA_ARGS__)
> +
>  #define drm_dbg_kms_ratelimited(drm, fmt, ...) \
> __DRM_DEFINE_DBG_RATELIMITED(KMS, drm, fmt, ## __VA_ARGS__)
>
> --
> 2.37.3
>

[Intel-gfx] ✓ Fi.CI.IGT: success for i915: CAGF and RC6 changes for MTL (rev14)

[Patchwork]

== Series Details ==

Series: i915: CAGF and RC6 changes for MTL (rev14)
URL   : https://patchwork.freedesktop.org/series/108156/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12390_full -> Patchwork_108156v14_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_108156v14_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-skl:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22]) -> ([PASS][23], 
[PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [FAIL][35], 
[FAIL][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42]) ([i915#5032])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl9/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl9/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl7/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl7/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl7/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl6/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl6/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl6/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl5/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl5/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl4/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl4/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl4/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl3/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl3/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl2/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl1/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl1/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl1/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl10/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl10/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl10/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl1/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl1/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl10/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl10/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl9/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl9/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl9/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl7/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl7/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl6/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl6/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl5/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl5/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl5/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl5/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl4/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl4/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl3/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl2/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v14/shard-skl2/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@display-2x:
- shard-tglb: NOTRUN -> 

Re: [Intel-gfx] [PATCH] drm/i915/edp: wait power off delay at driver remove to optimize probe

[Jani Nikula]

On Wed, 16 Nov 2022, Ville Syrjälä  wrote:
> On Wed, Nov 16, 2022 at 05:06:57PM +0200, Jani Nikula wrote:
>> Panel power off delay is the time the panel power needs to remain off
>> after being switched off, before it can be switched on again.
>> 
>> For the purpose of respecting panel power off delay at driver probe,
>> assuming the panel was last switched off at driver probe is overly
>> pessimistic. If the panel was never on, we'd end up waiting for no
>> reason.
>> 
>> We don't know what has happened before kernel boot, but we can make some
>> assumptions:
>> 
>> - The panel may have been switched off right before kernel boot by some
>>   pre-os environment.
>> 
>> - After kernel boot, the panel may only be switched off by i915.
>> 
>> - At i915 driver probe, only a previously loaded and removed i915 may
>>   have switched the panel power off.
>> 
>> With these assumptions, we can initialize the last power off time to
>> kernel boot time, if we also ensure i915 driver remove waits for the
>> panel power off delay after switching panel power off.
>> 
>> This shaves off the time it takes from kernel boot to i915 probe from
>> the first panel enable, if (and only if) the panel was not already
>> enabled at boot.
>> 
>> The encoder destroy hook is pretty much the last place where we can
>> wait, right after we've ensured the panel power has been switched off,
>> and before the whole encode is destroyed.
>
> Yeah, the fact that we have the vdd_off_sync() in there at least
> theoretically means the vdd might be on at any point before that.
>
> I was also pondering about doing this for all encoder types.
> Though the benefits are slightly less pronounced I guess:
> a) we don't need to power the panel for the output probe on those,
>so a bit more time will have elapsed anyway before we have to
>power the panel on during the first modeset
> b) for LVDS we rely 100% on the pps state machine so the initial
>boot case is already as optimal as possible. Adding the explicit
>wait into the unload path could thus only help the speed of
>of the first modeset during module reload
>
> But maybe we'd stil want to do that, for consistency if nothing else?
>
> Either way, this patch is
> Reviewed-by: Ville Syrjälä 

Thanks for the review and testing, pushed to drm-intel-next.

BR,
Jani.

>
>> 
>> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7417
>> Cc: Lee Shawn C 
>> Cc: Ville Syrjälä 
>> Signed-off-by: Jani Nikula 
>> ---
>>  drivers/gpu/drm/i915/display/intel_dp.c  | 6 ++
>>  drivers/gpu/drm/i915/display/intel_pps.c | 8 +++-
>>  2 files changed, 13 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 914161d7d122..67089711d9e2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -4877,6 +4877,12 @@ void intel_dp_encoder_flush_work(struct drm_encoder 
>> *encoder)
>>  
>>  intel_pps_vdd_off_sync(intel_dp);
>>  
>> +/*
>> + * Ensure power off delay is respected on module remove, so that we can
>> + * reduce delays at driver probe. See pps_init_timestamps().
>> + */
>> +intel_pps_wait_power_cycle(intel_dp);
>> +
>>  intel_dp_aux_fini(intel_dp);
>>  }
>>  
>> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c 
>> b/drivers/gpu/drm/i915/display/intel_pps.c
>> index 81ee7f3aadf6..9bbf41a076f7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> @@ -1100,7 +1100,13 @@ bool intel_pps_have_panel_power_or_vdd(struct 
>> intel_dp *intel_dp)
>>  
>>  static void pps_init_timestamps(struct intel_dp *intel_dp)
>>  {
>> -intel_dp->pps.panel_power_off_time = ktime_get_boottime();
>> +/*
>> + * Initialize panel power off time to 0, assuming panel power could have
>> + * been toggled between kernel boot and now only by a previously loaded
>> + * and removed i915, which has already ensured sufficient power off
>> + * delay at module remove.
>> + */
>> +intel_dp->pps.panel_power_off_time = 0;
>>  intel_dp->pps.last_power_on = jiffies;
>>  intel_dp->pps.last_backlight_off = jiffies;
>>  }
>> -- 
>> 2.34.1

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Analog TV Improvements (rev11)

[Patchwork]

== Series Details ==

Series: drm: Analog TV Improvements (rev11)
URL   : https://patchwork.freedesktop.org/series/107892/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12392 -> Patchwork_107892v11


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/index.html

Participating hosts (27 -> 36)
--

  Additional (12): bat-dg1-7 bat-dg1-5 bat-dg2-8 bat-adlm-1 bat-dg2-9 
bat-adlp-6 bat-adlp-4 bat-adln-1 bat-rplp-1 bat-dg2-11 fi-bsw-kefka bat-jsl-1 
  Missing(3): fi-kbl-soraka bat-kbl-2 bat-jsl-3 

Known issues


  Here are the changes found in Patchwork_107892v11 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-adlp-4: NOTRUN -> [SKIP][1] ([i915#7456])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/bat-adlp-4/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_lmem_swapping@verify-random:
- bat-adlp-4: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/bat-adlp-4/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-dg1-5:  NOTRUN -> [SKIP][3] ([i915#4083])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/bat-dg1-5/igt@gem_m...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg1-5:  NOTRUN -> [SKIP][4] ([i915#4077]) +2 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg1-5:  NOTRUN -> [SKIP][5] ([i915#4079]) +1 similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/bat-dg1-5/igt@gem_tiled_pread_basic.html
- bat-adlp-4: NOTRUN -> [SKIP][6] ([i915#3282])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/bat-adlp-4/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-5:  NOTRUN -> [SKIP][7] ([i915#1155])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
- bat-dg1-5:  NOTRUN -> [SKIP][8] ([i915#6621])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/bat-dg1-5/igt@i915_pm_...@basic-api.html
- bat-adlp-4: NOTRUN -> [SKIP][9] ([i915#6621])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/bat-adlp-4/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [PASS][10] -> [INCOMPLETE][11] ([i915#4983])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html

  * igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-dg1-5:  NOTRUN -> [SKIP][12] ([i915#4212]) +7 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/bat-dg1-5/igt@kms_addfb_ba...@basic-x-tiled-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-5:  NOTRUN -> [SKIP][13] ([i915#4215])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/bat-dg1-5/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- bat-adlp-4: NOTRUN -> [SKIP][15] ([fdo#111827]) +8 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/bat-adlp-4/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@dp-edid-read:
- fi-bsw-kefka:   NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/fi-bsw-kefka/igt@kms_chamel...@dp-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- bat-dg1-5:  NOTRUN -> [SKIP][17] ([fdo#111827]) +8 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/bat-dg1-5/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-adlp-4: NOTRUN -> [SKIP][18] ([i915#4103])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/bat-adlp-4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
- bat-dg1-5:  NOTRUN -> [SKIP][19] ([i915#4103] / [i915#4213])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107892v11/bat-dg1-5/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * 

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Ratelimit debug log in vm_fault_ttm

[Matthew Auld]

On 13/10/2022 09:40, Nirmoy Das wrote:

Test like i915_gem_mman_live_selftests/igt_mmap_migrate can cause
dmesg spamming. Use ratelimit api to reduce log rate.

References: https://gitlab.freedesktop.org/drm/intel/-/issues/7038
Cc: Matthew Auld 
Signed-off-by: Nirmoy Das 

Reviewed-by: Matthew Auld 



---
  drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index d63f30efd631..6b60b99461e2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -1080,8 +1080,9 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
}
  
  		if (err) {

-   drm_dbg(dev, "Unable to make resource CPU accessible(err = 
%pe)\n",
-   ERR_PTR(err));
+   drm_dbg_ratelimited(dev,
+   "Unable to make resource CPU 
accessible(err = %pe)\n",
+   ERR_PTR(err));
dma_resv_unlock(bo->base.resv);
ret = VM_FAULT_SIGBUS;
goto out_rpm;

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm: Analog TV Improvements (rev11)

[Patchwork]

== Series Details ==

Series: drm: Analog TV Improvements (rev11)
URL   : https://patchwork.freedesktop.org/series/107892/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Enable Idle Messaging for GSC CS

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: Enable Idle Messaging for GSC CS
URL   : https://patchwork.freedesktop.org/series/111011/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12392 -> Patchwork_111011v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/index.html

Participating hosts (27 -> 36)
--

  Additional (12): bat-dg1-7 bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adlp-6 
bat-adlp-4 bat-adln-1 bat-rplp-1 bat-rpls-2 bat-dg2-11 fi-bsw-kefka bat-jsl-1 
  Missing(3): fi-kbl-soraka bat-kbl-2 bat-jsl-3 

Known issues


  Here are the changes found in Patchwork_111011v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-adlp-4: NOTRUN -> [SKIP][1] ([i915#7456])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/bat-adlp-4/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_lmem_swapping@verify-random:
- bat-adlp-4: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/bat-adlp-4/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_tiled_pread_basic:
- bat-adlp-4: NOTRUN -> [SKIP][3] ([i915#3282])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/bat-adlp-4/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-adlp-4: NOTRUN -> [SKIP][4] ([i915#6621])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/bat-adlp-4/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][5] -> [INCOMPLETE][6] ([i915#7120])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12392/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-rkl-guc: NOTRUN -> [SKIP][8] ([fdo#111827])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/fi-rkl-guc/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- bat-adlp-4: NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/bat-adlp-4/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@dp-edid-read:
- fi-bsw-kefka:   NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/fi-bsw-kefka/igt@kms_chamel...@dp-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-adlp-4: NOTRUN -> [SKIP][11] ([i915#4103])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/bat-adlp-4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * 
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka:   NOTRUN -> [FAIL][12] ([i915#6298])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-adlp-4: NOTRUN -> [SKIP][13] ([i915#4093]) +3 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/bat-adlp-4/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlp-4: NOTRUN -> [SKIP][14] ([i915#3546])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/bat-adlp-4/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-adlp-4: NOTRUN -> [SKIP][15] ([i915#3555] / [i915#4579])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/bat-adlp-4/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
- fi-bsw-kefka:   NOTRUN -> [SKIP][16] ([fdo#109271]) +17 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/fi-bsw-kefka/igt@prime_v...@basic-fence-flip.html

  * igt@prime_vgem@basic-userptr:
- bat-adlp-4: NOTRUN -> [SKIP][17] ([fdo#109295] / [i915#3301] / 
[i915#3708])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v1/bat-adlp-4/igt@prime_v...@basic-userptr.html

  * igt@prime_vgem@basic-write:
- bat-adlp-4: NOTRUN -> [SKIP][18] ([fdo#109295] / [i915#3291] / 
[i915#3708]) +2 similar issues
   [18]: 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Finish (de)gamma readout (rev9)

[Patchwork]

== Series Details ==

Series: drm/i915: Finish (de)gamma readout (rev9)
URL   : https://patchwork.freedesktop.org/series/79614/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12390_full -> Patchwork_79614v9_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_79614v9_full absolutely need to 
be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_79614v9_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_79614v9_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_fence@syncobj-invalid-flags:
- shard-skl:  [PASS][1] -> [WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl7/igt@gem_exec_fe...@syncobj-invalid-flags.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_79614v9/shard-skl9/igt@gem_exec_fe...@syncobj-invalid-flags.html

  
Known issues


  Here are the changes found in Patchwork_79614v9_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-skl:  ([PASS][3], [PASS][4], [PASS][5], [PASS][6], 
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24]) -> 
([PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [FAIL][33], [PASS][34], [PASS][35], [PASS][36], 
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44], [PASS][45]) ([i915#5032])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl9/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl9/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl7/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl7/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl6/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl6/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl6/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl5/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl5/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl4/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl4/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl3/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl3/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl2/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl1/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl1/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl1/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl10/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl10/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl10/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_79614v9/shard-skl9/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_79614v9/shard-skl9/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_79614v9/shard-skl7/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_79614v9/shard-skl7/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_79614v9/shard-skl6/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_79614v9/shard-skl6/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_79614v9/shard-skl6/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_79614v9/shard-skl5/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_79614v9/shard-skl5/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_79614v9/shard-skl5/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_79614v9/shard-skl4/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_79614v9/shard-skl4/boot.html
   [37]: 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/edp: wait power off delay at driver remove to optimize probe

[Patchwork]

== Series Details ==

Series: drm/i915/edp: wait power off delay at driver remove to optimize probe
URL   : https://patchwork.freedesktop.org/series/110971/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12390_full -> Patchwork_110971v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110971v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110971v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110971v1_full:

### IGT changes ###

 Possible regressions 

  * igt@device_reset@unbind-reset-rebind:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-tglb7/igt@device_re...@unbind-reset-rebind.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110971v1/shard-tglb6/igt@device_re...@unbind-reset-rebind.html

  
Known issues


  Here are the changes found in Patchwork_110971v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-skl:  ([PASS][3], [PASS][4], [PASS][5], [PASS][6], 
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24]) -> 
([PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [FAIL][33], [FAIL][34], [FAIL][35], [FAIL][36], 
[FAIL][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44]) ([i915#5032])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl9/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl9/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl7/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl7/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl6/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl6/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl6/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl5/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl5/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl4/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl4/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl3/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl3/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl2/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl1/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl1/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl1/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl10/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl10/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl10/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110971v1/shard-skl10/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110971v1/shard-skl10/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110971v1/shard-skl1/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110971v1/shard-skl1/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110971v1/shard-skl2/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110971v1/shard-skl3/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110971v1/shard-skl4/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110971v1/shard-skl4/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110971v1/shard-skl5/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110971v1/shard-skl5/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110971v1/shard-skl5/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110971v1/shard-skl5/boot.html
   

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fix negative remaining time after retire requests

[Das, Nirmoy]

On 11/16/2022 12:25 PM, Janusz Krzysztofik wrote:


Commit b97060a99b01 ("drm/i915/guc: Update intel_gt_wait_for_idle to work
with GuC") extended the API of intel_gt_retire_requests_timeout() with an
extra argument 'remaining_timeout', intended for passing back unconsumed
portion of requested timeout when 0 (success) is returned.  However, when
request retirement happens to succeed despite an error returned by
dma_fence_wait_timeout(), the error code (a negative value) is passed back
instead of remaining time.  If a user then passes that negative value
forward as requested timeout to another wait, an explicit WARN or BUG can
be triggered.

Instead of copying the value of timeout variable to *remaining_timeout
before return, update the *remaining_timeout after each DMA fence wait.



Thanks for the detailed comment, indeed we were not accounting for the 
return value of dma_fence_wait_timeout()


Acked-by: Nirmoy Das 


Thanks,

Nirmoy



Set it to 0 on -ETIME, -EINTR or -ERESTARTSYS, and assume no time has been
consumed on other errors returned from the wait.

Fixes: b97060a99b01 ("drm/i915/guc: Update intel_gt_wait_for_idle to work with 
GuC")
Signed-off-by: Janusz Krzysztofik 
Cc: sta...@vger.kernel.org # v5.15+
---
  drivers/gpu/drm/i915/gt/intel_gt_requests.c | 23 ++---
  1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c 
b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
index edb881d756309..ccaf2fd80625b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
@@ -138,6 +138,9 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, 
long timeout,
unsigned long active_count = 0;
LIST_HEAD(free);
  
+	if (remaining_timeout)

+   *remaining_timeout = timeout;
+
flush_submission(gt, timeout); /* kick the ksoftirqd tasklets */
spin_lock(>lock);
list_for_each_entry_safe(tl, tn, >active_list, link) {
@@ -163,6 +166,23 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, 
long timeout,
 timeout);
dma_fence_put(fence);
  
+if (remaining_timeout) {

+   /*
+* If we get an error here but request
+* retirement succeeds anyway
+* (!active_count) and we return 0, the
+* caller may want to spend remaining
+* time on waiting for other events.
+*/
+   if (timeout == -ETIME ||
+   timeout == -EINTR ||
+   timeout == -ERESTARTSYS)
+   *remaining_timeout = 0;
+   else if (timeout >= 0)
+   *remaining_timeout = timeout;
+   /* else assume no time consumed */
+   }
+
/* Retirement is best effort */
if (!mutex_trylock(>mutex)) {
active_count++;
@@ -196,9 +216,6 @@ out_active: spin_lock(>lock);
if (flush_submission(gt, timeout)) /* Wait, there's more! */
active_count++;
  
-	if (remaining_timeout)

-   *remaining_timeout = timeout;
-
return active_count ? timeout : 0;
  }
  

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Never return 0 on timeout when retiring requests

[Das, Nirmoy]

Looks very relevant to  our recent hangcheck failures.


Acked-by: Nirmoy Das 

On 11/16/2022 12:25 PM, Janusz Krzysztofik wrote:

Users of intel_gt_retire_requests_timeout() expect 0 return value on
success.  However, we have no protection from passing back 0 potentially
returned by dma_fence_wait_timeout() on timeout.

Replace 0 with -ETIME before using timeout as return value.

Fixes: f33a8a51602c ("drm/i915: Merge wait_for_timelines with retire_request")
Signed-off-by: Janusz Krzysztofik 
Cc: sta...@vger.kernel.org # v5.5+
---
  drivers/gpu/drm/i915/gt/intel_gt_requests.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c 
b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
index ccaf2fd80625b..ac6b2b1861397 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
@@ -213,6 +213,9 @@ out_active: spin_lock(>lock);
list_for_each_entry_safe(tl, tn, , link)
__intel_timeline_free(>kref);
  
+	if (!timeout)

+   timeout = -ETIME;
+
if (flush_submission(gt, timeout)) /* Wait, there's more! */
active_count++;
  

[Intel-gfx] [PATCH] drm/i915/dmc: Add MTL DMC firmware v2.10

[Madhumitha Tolakanahalli Pradeep]

This patch adds DMC firmware v2.10 for Meteorlake.

Release Notes:
1.DCstate residency counter
2.Traphit fix
3.LM TONEFACT fix
4.Ramp up timer fix(PFET)

Signed-off-by: Madhumitha Tolakanahalli Pradeep 

---
 drivers/gpu/drm/i915/display/intel_dmc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c 
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 081a4d0083b1..bebc80aca44c 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -52,6 +52,10 @@
 
 #define DISPLAY_VER12_DMC_MAX_FW_SIZE  ICL_DMC_MAX_FW_SIZE
 
+#define MTL_DMC_PATH   DMC_PATH(mtl, 2, 10)
+#define MTL_DMC_VERSION_REQUIRED   DMC_VERSION(2, 10)
+MODULE_FIRMWARE(MTL_DMC_PATH);
+
 #define DG2_DMC_PATH   DMC_PATH(dg2, 2, 07)
 #define DG2_DMC_VERSION_REQUIRED   DMC_VERSION(2, 07)
 MODULE_FIRMWARE(DG2_DMC_PATH);
-- 
2.38.1

[Intel-gfx] [CI] PR for MTL DMC v2.10

[Tolakanahalli Pradeep, Madhumitha]

The following changes since commit daff40492bd0cd071c7f5521b339e12e4de718c1:

  linux-firmware: update firmware for MT7986 (2022-11-16 08:53:28 -0500)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-firmware mtl_dmc_v2.10

for you to fetch changes up to de854c96df66be4a13f8bfbb1e78bd5d0cea2e8e:

  i915: Add DMC v2.10 for MTL (2022-11-16 14:26:06 -0800)


Madhumitha Tolakanahalli Pradeep (1):
  i915: Add DMC v2.10 for MTL

 WHENCE   |   3 +++
 i915/mtl_dmc_ver2_10.bin | Bin 0 -> 48112 bytes
 2 files changed, 3 insertions(+)
 create mode 100644 i915/mtl_dmc_ver2_10.bin

[Intel-gfx] [PATCH v10 19/19] drm/sun4i: tv: Convert to the new TV mode property

[Maxime Ripard]

Now that the core can deal fine with analog TV modes, let's convert the
sun4i TV driver to leverage those new features.

Acked-by: Noralf Trønnes 
Reviewed-by: Jernej Skrabec 
Signed-off-by: Maxime Ripard 

---
Changes in v6:
- Convert to new get_modes helper

Changes in v5:
- Removed the count variable in get_modes
- Removed spurious vc4 change
---
 drivers/gpu/drm/sun4i/sun4i_tv.c | 141 ++-
 1 file changed, 34 insertions(+), 107 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index c65f0a89b6b0..9625a00a48ba 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -141,23 +141,14 @@ struct resync_parameters {
 struct tv_mode {
char*name;
 
+   unsigned inttv_mode;
+
u32 mode;
u32 chroma_freq;
u16 back_porch;
u16 front_porch;
-   u16 line_number;
u16 vblank_level;
 
-   u32 hdisplay;
-   u16 hfront_porch;
-   u16 hsync_len;
-   u16 hback_porch;
-
-   u32 vdisplay;
-   u16 vfront_porch;
-   u16 vsync_len;
-   u16 vback_porch;
-
boolyc_en;
booldac3_en;
booldac_bit25_en;
@@ -213,7 +204,7 @@ static const struct resync_parameters pal_resync_parameters 
= {
 
 static const struct tv_mode tv_modes[] = {
{
-   .name   = "NTSC",
+   .tv_mode= DRM_MODE_TV_MODE_NTSC,
.mode   = SUN4I_TVE_CFG0_RES_480i,
.chroma_freq= 0x21f07c1f,
.yc_en  = true,
@@ -222,17 +213,6 @@ static const struct tv_mode tv_modes[] = {
 
.back_porch = 118,
.front_porch= 32,
-   .line_number= 525,
-
-   .hdisplay   = 720,
-   .hfront_porch   = 18,
-   .hsync_len  = 2,
-   .hback_porch= 118,
-
-   .vdisplay   = 480,
-   .vfront_porch   = 26,
-   .vsync_len  = 2,
-   .vback_porch= 17,
 
.vblank_level   = 240,
 
@@ -242,23 +222,12 @@ static const struct tv_mode tv_modes[] = {
.resync_params  = _resync_parameters,
},
{
-   .name   = "PAL",
+   .tv_mode= DRM_MODE_TV_MODE_PAL,
.mode   = SUN4I_TVE_CFG0_RES_576i,
.chroma_freq= 0x2a098acb,
 
.back_porch = 138,
.front_porch= 24,
-   .line_number= 625,
-
-   .hdisplay   = 720,
-   .hfront_porch   = 3,
-   .hsync_len  = 2,
-   .hback_porch= 139,
-
-   .vdisplay   = 576,
-   .vfront_porch   = 28,
-   .vsync_len  = 2,
-   .vback_porch= 19,
 
.vblank_level   = 252,
 
@@ -276,63 +245,21 @@ drm_encoder_to_sun4i_tv(struct drm_encoder *encoder)
encoder);
 }
 
-/*
- * FIXME: If only the drm_display_mode private field was usable, this
- * could go away...
- *
- * So far, it doesn't seem to be preserved when the mode is passed by
- * to mode_set for some reason.
- */
-static const struct tv_mode *sun4i_tv_find_tv_by_mode(const struct 
drm_display_mode *mode)
+static const struct tv_mode *
+sun4i_tv_find_tv_by_mode(unsigned int mode)
 {
int i;
 
-   /* First try to identify the mode by name */
for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
const struct tv_mode *tv_mode = _modes[i];
 
-   DRM_DEBUG_DRIVER("Comparing mode %s vs %s",
-mode->name, tv_mode->name);
-
-   if (!strcmp(mode->name, tv_mode->name))
-   return tv_mode;
-   }
-
-   /* Then by number of lines */
-   for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
-   const struct tv_mode *tv_mode = _modes[i];
-
-   DRM_DEBUG_DRIVER("Comparing mode %s vs %s (X: %d vs %d)",
-mode->name, tv_mode->name,
-mode->vdisplay, tv_mode->vdisplay);
-
-   if (mode->vdisplay == tv_mode->vdisplay)
+   if (tv_mode->tv_mode == mode)
return tv_mode;
}
 
return NULL;
 }
 
-static void sun4i_tv_mode_to_drm_mode(const struct tv_mode *tv_mode,
- struct drm_display_mode *mode)
-{
-   DRM_DEBUG_DRIVER("Creating mode %s\n", mode->name);
-
-   mode->type = DRM_MODE_TYPE_DRIVER;
-   mode->clock = 13500;
-   mode->flags = DRM_MODE_FLAG_INTERLACE;
-
-   mode->hdisplay = tv_mode->hdisplay;
-   

[Intel-gfx] [PATCH v10 17/19] drm/vc4: vec: Convert to the new TV mode property

[Maxime Ripard]

Now that the core can deal fine with analog TV modes, let's convert the vc4
VEC driver to leverage those new features.

We've added some backward compatibility to support the old TV mode property
and translate it into the new TV norm property. We're also making use of
the new analog TV atomic_check helper to make sure we trigger a modeset
whenever the TV mode is updated.

Acked-by: Noralf Trønnes 
Tested-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 

---
Changes in v7:
- Lookup the tv mode in atomic_check to make sure it's supported

Changes in v6:
- Use new get_modes helper

Changes in v5:
- Renamed tv_mode_names into legacy_tv_mode_names

Changes in v4:
- Removed the count variable in .get_modes
---
 drivers/gpu/drm/vc4/vc4_vec.c | 186 ++
 1 file changed, 132 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c
index bfa8a58dba30..a828fc6fb776 100644
--- a/drivers/gpu/drm/vc4/vc4_vec.c
+++ b/drivers/gpu/drm/vc4/vc4_vec.c
@@ -172,6 +172,8 @@ struct vc4_vec {
 
struct clk *clock;
 
+   struct drm_property *legacy_tv_mode_property;
+
struct debugfs_regset32 regset;
 };
 
@@ -184,6 +186,12 @@ encoder_to_vc4_vec(struct drm_encoder *encoder)
return container_of(encoder, struct vc4_vec, encoder.base);
 }
 
+static inline struct vc4_vec *
+connector_to_vc4_vec(struct drm_connector *connector)
+{
+   return container_of(connector, struct vc4_vec, connector);
+}
+
 enum vc4_vec_tv_mode_id {
VC4_VEC_TV_MODE_NTSC,
VC4_VEC_TV_MODE_NTSC_J,
@@ -192,7 +200,7 @@ enum vc4_vec_tv_mode_id {
 };
 
 struct vc4_vec_tv_mode {
-   const struct drm_display_mode *mode;
+   unsigned int mode;
u32 config0;
u32 config1;
u32 custom_freq;
@@ -225,43 +233,51 @@ static const struct debugfs_reg32 vec_regs[] = {
VC4_REG32(VEC_DAC_MISC),
 };
 
-static const struct drm_display_mode ntsc_mode = {
-   DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 13500,
-720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,
-480, 480 + 7, 480 + 7 + 6, 525, 0,
-DRM_MODE_FLAG_INTERLACE)
-};
-
-static const struct drm_display_mode pal_mode = {
-   DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 13500,
-720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
-576, 576 + 4, 576 + 4 + 6, 625, 0,
-DRM_MODE_FLAG_INTERLACE)
-};
-
 static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
-   [VC4_VEC_TV_MODE_NTSC] = {
-   .mode = _mode,
+   {
+   .mode = DRM_MODE_TV_MODE_NTSC,
.config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
-   [VC4_VEC_TV_MODE_NTSC_J] = {
-   .mode = _mode,
+   {
+   .mode = DRM_MODE_TV_MODE_NTSC_J,
.config0 = VEC_CONFIG0_NTSC_STD,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
-   [VC4_VEC_TV_MODE_PAL] = {
-   .mode = _mode,
+   {
+   .mode = DRM_MODE_TV_MODE_PAL,
.config0 = VEC_CONFIG0_PAL_BDGHI_STD,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
-   [VC4_VEC_TV_MODE_PAL_M] = {
-   .mode = _mode,
+   {
+   .mode = DRM_MODE_TV_MODE_PAL_M,
.config0 = VEC_CONFIG0_PAL_M_STD,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
 };
 
+static inline const struct vc4_vec_tv_mode *
+vc4_vec_tv_mode_lookup(unsigned int mode)
+{
+   unsigned int i;
+
+   for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) {
+   const struct vc4_vec_tv_mode *tv_mode = _vec_tv_modes[i];
+
+   if (tv_mode->mode == mode)
+   return tv_mode;
+   }
+
+   return NULL;
+}
+
+static const struct drm_prop_enum_list legacy_tv_mode_names[] = {
+   { VC4_VEC_TV_MODE_NTSC, "NTSC", },
+   { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", },
+   { VC4_VEC_TV_MODE_PAL, "PAL", },
+   { VC4_VEC_TV_MODE_PAL_M, "PAL-M", },
+};
+
 static enum drm_connector_status
 vc4_vec_connector_detect(struct drm_connector *connector, bool force)
 {
@@ -274,21 +290,74 @@ static void vc4_vec_connector_reset(struct drm_connector 
*connector)
drm_atomic_helper_connector_tv_reset(connector);
 }
 
-static int vc4_vec_connector_get_modes(struct drm_connector *connector)
+static int
+vc4_vec_connector_set_property(struct drm_connector *connector,
+  struct drm_connector_state *state,
+  struct drm_property *property,
+  uint64_t val)
 {
-   struct drm_connector_state *state = connector->state;
-   struct drm_display_mode *mode;
-
-   mode = drm_mode_duplicate(connector->dev,
- vc4_vec_tv_modes[state->tv.legacy_mode].mode);
-   if (!mode) {
-

[Intel-gfx] [PATCH v10 18/19] drm/vc4: vec: Add support for more analog TV standards

[Maxime Ripard]

From: Mateusz Kwiatkowski 

Add support for the following composite output modes (all of them are
somewhat more obscure than the previously defined ones):

- NTSC_443 - NTSC-style signal with the chroma subcarrier shifted to
  4.43361875 MHz (the PAL subcarrier frequency). Never used for
  broadcasting, but sometimes used as a hack to play NTSC content in PAL
  regions (e.g. on VCRs).
- PAL_N - PAL with alternative chroma subcarrier frequency,
  3.58205625 MHz. Used as a broadcast standard in Argentina, Paraguay
  and Uruguay to fit 576i50 with colour in 6 MHz channel raster.
- PAL60 - 480i60 signal with PAL-style color at normal European PAL
  frequency. Another non-standard, non-broadcast mode, used in similar
  contexts as NTSC_443. Some displays support one but not the other.
- SECAM - French frequency-modulated analog color standard; also have
  been broadcast in Eastern Europe and various parts of Africa and Asia.
  Uses the same 576i50 timings as PAL.

Also added some comments explaining color subcarrier frequency
registers.

Acked-by: Noralf Trønnes 
Signed-off-by: Mateusz Kwiatkowski 
Tested-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 

---
Changes in v6:
- Support PAL60 again
---
 drivers/gpu/drm/vc4/vc4_vec.c | 111 --
 1 file changed, 107 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c
index a828fc6fb776..d23dbad3cbf6 100644
--- a/drivers/gpu/drm/vc4/vc4_vec.c
+++ b/drivers/gpu/drm/vc4/vc4_vec.c
@@ -46,6 +46,7 @@
 #define VEC_CONFIG0_YDEL(x)((x) << 26)
 #define VEC_CONFIG0_CDEL_MASK  GENMASK(25, 24)
 #define VEC_CONFIG0_CDEL(x)((x) << 24)
+#define VEC_CONFIG0_SECAM_STD  BIT(21)
 #define VEC_CONFIG0_PBPR_FIL   BIT(18)
 #define VEC_CONFIG0_CHROMA_GAIN_MASK   GENMASK(17, 16)
 #define VEC_CONFIG0_CHROMA_GAIN_UNITY  (0 << 16)
@@ -76,6 +77,27 @@
 #define VEC_SOFT_RESET 0x10c
 #define VEC_CLMP0_START0x144
 #define VEC_CLMP0_END  0x148
+
+/*
+ * These set the color subcarrier frequency
+ * if VEC_CONFIG1_CUSTOM_FREQ is enabled.
+ *
+ * VEC_FREQ1_0 contains the most significant 16-bit half-word,
+ * VEC_FREQ3_2 contains the least significant 16-bit half-word.
+ * 0x8000 seems to be equivalent to the pixel clock
+ * (which itself is the VEC clock divided by 8).
+ *
+ * Reference values (with the default pixel clock of 13.5 MHz):
+ *
+ * NTSC  (3579545.[45] Hz) - 0x21F07C1F
+ * PAL   (4433618.75 Hz)   - 0x2A098ACB
+ * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3
+ * PAL-N (3582056.25 Hz)   - 0x21F69446
+ *
+ * NOTE: For SECAM, it is used as the Dr center frequency,
+ * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not;
+ * that is specified as 4406250 Hz, which corresponds to 0x29C71C72.
+ */
 #define VEC_FREQ3_20x180
 #define VEC_FREQ1_00x184
 
@@ -118,6 +140,14 @@
 
 #define VEC_INTERRUPT_CONTROL  0x190
 #define VEC_INTERRUPT_STATUS   0x194
+
+/*
+ * Db center frequency for SECAM; the clock for this is the same as for
+ * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency.
+ *
+ * This is specified as 425 Hz, which corresponds to 0x284BDA13.
+ * That is also the default value, so no need to set it explicitly.
+ */
 #define VEC_FCW_SECAM_B0x198
 #define VEC_SECAM_GAIN_VAL 0x19c
 
@@ -197,10 +227,15 @@ enum vc4_vec_tv_mode_id {
VC4_VEC_TV_MODE_NTSC_J,
VC4_VEC_TV_MODE_PAL,
VC4_VEC_TV_MODE_PAL_M,
+   VC4_VEC_TV_MODE_NTSC_443,
+   VC4_VEC_TV_MODE_PAL_60,
+   VC4_VEC_TV_MODE_PAL_N,
+   VC4_VEC_TV_MODE_SECAM,
 };
 
 struct vc4_vec_tv_mode {
unsigned int mode;
+   u16 expected_htotal;
u32 config0;
u32 config1;
u32 custom_freq;
@@ -236,35 +271,68 @@ static const struct debugfs_reg32 vec_regs[] = {
 static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
{
.mode = DRM_MODE_TV_MODE_NTSC,
+   .expected_htotal = 858,
.config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
+   {
+   .mode = DRM_MODE_TV_MODE_NTSC_443,
+   .expected_htotal = 858,
+   .config0 = VEC_CONFIG0_NTSC_STD,
+   .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
+   .custom_freq = 0x2a098acb,
+   },
{
.mode = DRM_MODE_TV_MODE_NTSC_J,
+   .expected_htotal = 858,
.config0 = VEC_CONFIG0_NTSC_STD,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
{
.mode = DRM_MODE_TV_MODE_PAL,
+   .expected_htotal = 864,
.config0 = VEC_CONFIG0_PAL_BDGHI_STD,
.config1 = VEC_CONFIG1_C_CVBS_CVBS,
},
+   {
+   

[Intel-gfx] [PATCH v10 14/19] drm/atomic-helper: Add an analog TV atomic_check implementation

[Maxime Ripard]

The analog TV connector drivers share some atomic_check logic, and the new
TV standard property have created some boilerplate that can be shared
across drivers too.

Let's create an atomic_check helper for those use cases.

Reviewed-by: Noralf Trønnes 
Tested-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 

---
Changes in v10:
- Fix checkpatch warning
---
 drivers/gpu/drm/drm_atomic_state_helper.c | 49 +++
 include/drm/drm_atomic_state_helper.h |  3 ++
 2 files changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c 
b/drivers/gpu/drm/drm_atomic_state_helper.c
index e1fc3f26340a..22251c5f6a8a 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -556,6 +556,55 @@ void drm_atomic_helper_connector_tv_reset(struct 
drm_connector *connector)
 }
 EXPORT_SYMBOL(drm_atomic_helper_connector_tv_reset);
 
+/**
+ * @drm_atomic_helper_connector_tv_check: Validate an analog TV connector state
+ * @connector: DRM Connector
+ * @state: the DRM State object
+ *
+ * Checks the state object to see if the requested state is valid for an
+ * analog TV connector.
+ *
+ * Returns:
+ * Zero for success, a negative error code on error.
+ */
+int drm_atomic_helper_connector_tv_check(struct drm_connector *connector,
+struct drm_atomic_state *state)
+{
+   struct drm_connector_state *old_conn_state =
+   drm_atomic_get_old_connector_state(state, connector);
+   struct drm_connector_state *new_conn_state =
+   drm_atomic_get_new_connector_state(state, connector);
+   struct drm_crtc_state *crtc_state;
+   struct drm_crtc *crtc;
+
+   crtc = new_conn_state->crtc;
+   if (!crtc)
+   return 0;
+
+   crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+   if (!crtc_state)
+   return -EINVAL;
+
+   if (old_conn_state->tv.mode != new_conn_state->tv.mode)
+   crtc_state->mode_changed = true;
+
+   if (old_conn_state->tv.margins.left != new_conn_state->tv.margins.left 
||
+   old_conn_state->tv.margins.right != 
new_conn_state->tv.margins.right ||
+   old_conn_state->tv.margins.top != new_conn_state->tv.margins.top ||
+   old_conn_state->tv.margins.bottom != 
new_conn_state->tv.margins.bottom ||
+   old_conn_state->tv.mode != new_conn_state->tv.mode ||
+   old_conn_state->tv.brightness != new_conn_state->tv.brightness ||
+   old_conn_state->tv.contrast != new_conn_state->tv.contrast ||
+   old_conn_state->tv.flicker_reduction != 
new_conn_state->tv.flicker_reduction ||
+   old_conn_state->tv.overscan != new_conn_state->tv.overscan ||
+   old_conn_state->tv.saturation != new_conn_state->tv.saturation ||
+   old_conn_state->tv.hue != new_conn_state->tv.hue)
+   crtc_state->connectors_changed = true;
+
+   return 0;
+}
+EXPORT_SYMBOL(drm_atomic_helper_connector_tv_check);
+
 /**
  * __drm_atomic_helper_connector_duplicate_state - copy atomic connector state
  * @connector: connector object
diff --git a/include/drm/drm_atomic_state_helper.h 
b/include/drm/drm_atomic_state_helper.h
index c8fbce795ee7..b9740edb2658 100644
--- a/include/drm/drm_atomic_state_helper.h
+++ b/include/drm/drm_atomic_state_helper.h
@@ -26,6 +26,7 @@
 
 #include 
 
+struct drm_atomic_state;
 struct drm_bridge;
 struct drm_bridge_state;
 struct drm_crtc;
@@ -71,6 +72,8 @@ void __drm_atomic_helper_connector_reset(struct drm_connector 
*connector,
 struct drm_connector_state 
*conn_state);
 void drm_atomic_helper_connector_reset(struct drm_connector *connector);
 void drm_atomic_helper_connector_tv_reset(struct drm_connector *connector);
+int drm_atomic_helper_connector_tv_check(struct drm_connector *connector,
+struct drm_atomic_state *state);
 void drm_atomic_helper_connector_tv_margins_reset(struct drm_connector 
*connector);
 void
 __drm_atomic_helper_connector_duplicate_state(struct drm_connector *connector,

-- 
b4 0.11.0-dev-99e3a

[Intel-gfx] [PATCH v10 15/19] drm/vc4: vec: Use TV Reset implementation

[Maxime Ripard]

The analog TV properties created by the drm_mode_create_tv_properties() are
not properly initialised at reset. Let's switch our implementation to call
drm_atomic_helper_connector_tv_reset().

Reviewed-by: Noralf Trønnes 
Tested-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/vc4/vc4_vec.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c
index adc9bf99e3fd..90e375a8a8f9 100644
--- a/drivers/gpu/drm/vc4/vc4_vec.c
+++ b/drivers/gpu/drm/vc4/vc4_vec.c
@@ -268,6 +268,12 @@ vc4_vec_connector_detect(struct drm_connector *connector, 
bool force)
return connector_status_unknown;
 }
 
+static void vc4_vec_connector_reset(struct drm_connector *connector)
+{
+   drm_atomic_helper_connector_reset(connector);
+   drm_atomic_helper_connector_tv_reset(connector);
+}
+
 static int vc4_vec_connector_get_modes(struct drm_connector *connector)
 {
struct drm_connector_state *state = connector->state;
@@ -288,7 +294,7 @@ static int vc4_vec_connector_get_modes(struct drm_connector 
*connector)
 static const struct drm_connector_funcs vc4_vec_connector_funcs = {
.detect = vc4_vec_connector_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
-   .reset = drm_atomic_helper_connector_reset,
+   .reset = vc4_vec_connector_reset,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 };

-- 
b4 0.11.0-dev-99e3a

[Intel-gfx] [PATCH v10 13/19] drm/atomic-helper: Add a TV properties reset helper

[Maxime Ripard]

The drm_tv_create_properties() function will create a bunch of properties,
but it's up to each and every driver using that function to properly reset
the state of these properties leading to inconsistent behaviours.

Let's create a helper that will take care of it.

Reviewed-by: Noralf Trønnes 
Tested-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 

---
Changes in v6:
- Use tv_mode_specified instead of a !0 tv_mode to set the default
---
 drivers/gpu/drm/drm_atomic_state_helper.c | 75 +++
 include/drm/drm_atomic_state_helper.h |  1 +
 2 files changed, 76 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c 
b/drivers/gpu/drm/drm_atomic_state_helper.c
index dfb57217253b..e1fc3f26340a 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -481,6 +481,81 @@ void drm_atomic_helper_connector_tv_margins_reset(struct 
drm_connector *connecto
 }
 EXPORT_SYMBOL(drm_atomic_helper_connector_tv_margins_reset);
 
+/**
+ * drm_atomic_helper_connector_tv_reset - Resets Analog TV connector properties
+ * @connector: DRM connector
+ *
+ * Resets the analog TV properties attached to a connector
+ */
+void drm_atomic_helper_connector_tv_reset(struct drm_connector *connector)
+{
+   struct drm_device *dev = connector->dev;
+   struct drm_cmdline_mode *cmdline = >cmdline_mode;
+   struct drm_connector_state *state = connector->state;
+   struct drm_property *prop;
+   uint64_t val;
+
+   prop = dev->mode_config.tv_mode_property;
+   if (prop)
+   if (!drm_object_property_get_default_value(>base,
+  prop, ))
+   state->tv.mode = val;
+
+   if (cmdline->tv_mode_specified)
+   state->tv.mode = cmdline->tv_mode;
+
+   prop = dev->mode_config.tv_select_subconnector_property;
+   if (prop)
+   if (!drm_object_property_get_default_value(>base,
+  prop, ))
+   state->tv.select_subconnector = val;
+
+   prop = dev->mode_config.tv_subconnector_property;
+   if (prop)
+   if (!drm_object_property_get_default_value(>base,
+  prop, ))
+   state->tv.subconnector = val;
+
+   prop = dev->mode_config.tv_brightness_property;
+   if (prop)
+   if (!drm_object_property_get_default_value(>base,
+  prop, ))
+   state->tv.brightness = val;
+
+   prop = dev->mode_config.tv_contrast_property;
+   if (prop)
+   if (!drm_object_property_get_default_value(>base,
+  prop, ))
+   state->tv.contrast = val;
+
+   prop = dev->mode_config.tv_flicker_reduction_property;
+   if (prop)
+   if (!drm_object_property_get_default_value(>base,
+  prop, ))
+   state->tv.flicker_reduction = val;
+
+   prop = dev->mode_config.tv_overscan_property;
+   if (prop)
+   if (!drm_object_property_get_default_value(>base,
+  prop, ))
+   state->tv.overscan = val;
+
+   prop = dev->mode_config.tv_saturation_property;
+   if (prop)
+   if (!drm_object_property_get_default_value(>base,
+  prop, ))
+   state->tv.saturation = val;
+
+   prop = dev->mode_config.tv_hue_property;
+   if (prop)
+   if (!drm_object_property_get_default_value(>base,
+  prop, ))
+   state->tv.hue = val;
+
+   drm_atomic_helper_connector_tv_margins_reset(connector);
+}
+EXPORT_SYMBOL(drm_atomic_helper_connector_tv_reset);
+
 /**
  * __drm_atomic_helper_connector_duplicate_state - copy atomic connector state
  * @connector: connector object
diff --git a/include/drm/drm_atomic_state_helper.h 
b/include/drm/drm_atomic_state_helper.h
index 192766656b88..c8fbce795ee7 100644
--- a/include/drm/drm_atomic_state_helper.h
+++ b/include/drm/drm_atomic_state_helper.h
@@ -70,6 +70,7 @@ void __drm_atomic_helper_connector_state_reset(struct 
drm_connector_state *conn_
 void __drm_atomic_helper_connector_reset(struct drm_connector *connector,
 struct drm_connector_state 
*conn_state);
 void drm_atomic_helper_connector_reset(struct drm_connector *connector);
+void drm_atomic_helper_connector_tv_reset(struct drm_connector *connector);
 void drm_atomic_helper_connector_tv_margins_reset(struct drm_connector 
*connector);
 void
 __drm_atomic_helper_connector_duplicate_state(struct drm_connector 

[Intel-gfx] [PATCH v10 09/19] drm/modes: Properly generate a drm_display_mode from a named mode

[Maxime Ripard]

The framework will get the drm_display_mode from the drm_cmdline_mode it
got by parsing the video command line argument by calling
drm_connector_pick_cmdline_mode().

The heavy lifting will then be done by the
drm_mode_create_from_cmdline_mode() function.

In the case of the named modes though, there's no real code to make that
translation and we rely on the drivers to guess which actual display mode
we meant.

Let's modify drm_mode_create_from_cmdline_mode() to properly generate the
drm_display_mode we mean when passing a named mode.

Reviewed-by: Noralf Trønnes 
Tested-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 

---
Changes in v10:
- Fix checkpatch warning

Changes in v9:
- Switch to parameterized tests for named modes

Changes in v8:
- Return the result of drm_analog_tv_mode directly

Changes in v7:
- Use tv_mode_specified in drm_mode_parse_command_line_for_connector

Changes in v6:
- Fix get_modes to return 0 instead of an error code
- Rename the tests to follow the DRM test naming convention

Changes in v5:
- Switched to KUNIT_ASSERT_NOT_NULL
---
 drivers/gpu/drm/drm_modes.c | 29 -
 drivers/gpu/drm/tests/drm_client_modeset_test.c | 84 -
 2 files changed, 111 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index f9fe065f189b..3d410be8db69 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -2499,6 +2499,31 @@ bool drm_mode_parse_command_line_for_connector(const 
char *mode_option,
 }
 EXPORT_SYMBOL(drm_mode_parse_command_line_for_connector);
 
+static struct drm_display_mode *drm_named_mode(struct drm_device *dev,
+  struct drm_cmdline_mode *cmd)
+{
+   unsigned int i;
+
+   for (i = 0; i < ARRAY_SIZE(drm_named_modes); i++) {
+   const struct drm_named_mode *named_mode = _named_modes[i];
+
+   if (strcmp(cmd->name, named_mode->name))
+   continue;
+
+   if (!cmd->tv_mode_specified)
+   continue;
+
+   return drm_analog_tv_mode(dev,
+ named_mode->tv_mode,
+ named_mode->pixel_clock_khz * 1000,
+ named_mode->xres,
+ named_mode->yres,
+ named_mode->flags & 
DRM_MODE_FLAG_INTERLACE);
+   }
+
+   return NULL;
+}
+
 /**
  * drm_mode_create_from_cmdline_mode - convert a command line modeline into a 
DRM display mode
  * @dev: DRM device to create the new mode for
@@ -2516,7 +2541,9 @@ drm_mode_create_from_cmdline_mode(struct drm_device *dev,
if (cmd->xres == 0 || cmd->yres == 0)
return NULL;
 
-   if (cmd->cvt)
+   if (strlen(cmd->name))
+   mode = drm_named_mode(dev, cmd);
+   else if (cmd->cvt)
mode = drm_cvt_mode(dev,
cmd->xres, cmd->yres,
cmd->refresh_specified ? cmd->refresh : 60,
diff --git a/drivers/gpu/drm/tests/drm_client_modeset_test.c 
b/drivers/gpu/drm/tests/drm_client_modeset_test.c
index cdae1e4c762a..fe1f6be097a2 100644
--- a/drivers/gpu/drm/tests/drm_client_modeset_test.c
+++ b/drivers/gpu/drm/tests/drm_client_modeset_test.c
@@ -21,7 +21,26 @@ struct drm_client_modeset_test_priv {
 
 static int drm_client_modeset_connector_get_modes(struct drm_connector 
*connector)
 {
-   return drm_add_modes_noedid(connector, 1920, 1200);
+   struct drm_display_mode *mode;
+   int count;
+
+   count = drm_add_modes_noedid(connector, 1920, 1200);
+
+   mode = drm_mode_analog_ntsc_480i(connector->dev);
+   if (!mode)
+   return count;
+
+   drm_mode_probed_add(connector, mode);
+   count += 1;
+
+   mode = drm_mode_analog_pal_576i(connector->dev);
+   if (!mode)
+   return count;
+
+   drm_mode_probed_add(connector, mode);
+   count += 1;
+
+   return count;
 }
 
 static const struct drm_connector_helper_funcs 
drm_client_modeset_connector_helper_funcs = {
@@ -52,6 +71,9 @@ static int drm_client_modeset_test_init(struct kunit *test)
 
drm_connector_helper_add(>connector, 
_client_modeset_connector_helper_funcs);
 
+   priv->connector.interlace_allowed = true;
+   priv->connector.doublescan_allowed = true;
+
return 0;
 }
 
@@ -84,8 +106,68 @@ static void drm_test_pick_cmdline_res_1920_1080_60(struct 
kunit *test)
KUNIT_EXPECT_TRUE(test, drm_mode_equal(expected_mode, mode));
 }
 
+struct drm_connector_pick_cmdline_mode_test {
+   const char *cmdline;
+   struct drm_display_mode *(*func)(struct drm_device *drm);
+};
+
+#define TEST_CMDLINE(_cmdline, _fn)\
+   {   \
+   .cmdline = _cmdline,\
+   

[Intel-gfx] [PATCH v10 16/19] drm/vc4: vec: Check for VEC output constraints

[Maxime Ripard]

From: Mateusz Kwiatkowski 

The VEC can accept pretty much any relatively reasonable mode, but still
has a bunch of constraints to meet.

Let's create an atomic_check() implementation that will make sure we
don't end up accepting a non-functional mode.

Acked-by: Noralf Trønnes 
Signed-off-by: Mateusz Kwiatkowski 
Tested-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 

---

Changes in v6:
- Used htotal instead of vtotal to discriminate PAL against NTSC
---
 drivers/gpu/drm/vc4/vc4_vec.c | 50 +++
 1 file changed, 50 insertions(+)

diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c
index 90e375a8a8f9..bfa8a58dba30 100644
--- a/drivers/gpu/drm/vc4/vc4_vec.c
+++ b/drivers/gpu/drm/vc4/vc4_vec.c
@@ -453,6 +453,7 @@ static int vc4_vec_encoder_atomic_check(struct drm_encoder 
*encoder,
struct drm_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
 {
+   const struct drm_display_mode *mode = _state->adjusted_mode;
const struct vc4_vec_tv_mode *vec_mode;
 
vec_mode = _vec_tv_modes[conn_state->tv.legacy_mode];
@@ -461,6 +462,55 @@ static int vc4_vec_encoder_atomic_check(struct drm_encoder 
*encoder,
!drm_mode_equal(vec_mode->mode, _state->adjusted_mode))
return -EINVAL;
 
+   if (mode->crtc_hdisplay % 4)
+   return -EINVAL;
+
+   if (!(mode->crtc_hsync_end - mode->crtc_hsync_start))
+   return -EINVAL;
+
+   switch (mode->htotal) {
+   /* NTSC */
+   case 858:
+   if (mode->crtc_vtotal > 262)
+   return -EINVAL;
+
+   if (mode->crtc_vdisplay < 1 || mode->crtc_vdisplay > 253)
+   return -EINVAL;
+
+   if (!(mode->crtc_vsync_start - mode->crtc_vdisplay))
+   return -EINVAL;
+
+   if ((mode->crtc_vsync_end - mode->crtc_vsync_start) != 3)
+   return -EINVAL;
+
+   if ((mode->crtc_vtotal - mode->crtc_vsync_end) < 4)
+   return -EINVAL;
+
+   break;
+
+   /* PAL/SECAM */
+   case 864:
+   if (mode->crtc_vtotal > 312)
+   return -EINVAL;
+
+   if (mode->crtc_vdisplay < 1 || mode->crtc_vdisplay > 305)
+   return -EINVAL;
+
+   if (!(mode->crtc_vsync_start - mode->crtc_vdisplay))
+   return -EINVAL;
+
+   if ((mode->crtc_vsync_end - mode->crtc_vsync_start) != 3)
+   return -EINVAL;
+
+   if ((mode->crtc_vtotal - mode->crtc_vsync_end) < 2)
+   return -EINVAL;
+
+   break;
+
+   default:
+   return -EINVAL;
+   }
+
return 0;
 }
 

-- 
b4 0.11.0-dev-99e3a

[Intel-gfx] [PATCH v10 12/19] drm/probe-helper: Provide a TV get_modes helper

[Maxime Ripard]

From: Noralf Trønnes 

Most of the TV connectors will need a similar get_modes implementation
that will, depending on the drivers' capabilities, register the 480i and
576i modes.

That implementation will also need to set the preferred flag and order
the modes based on the driver and users preferrence.

This is especially important to guarantee that a userspace stack such as
Xorg can start and pick up the preferred mode while maintaining a
working output.

Signed-off-by: Noralf Trønnes 
Tested-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 

---
Changes in v10:
- Fix checkpatch warning
- Add missing MODULE_* macros

Changes in v9:
- Store a function pointer instead of duplicating the expected mode
- Switch to kunit_test_suite

Changes in v8:
- Remove unused tv_mode_support function
- Add unit tests

Changes in v7:
- Used Noralf's implementation

Changes in v6:
- New patch
---
 drivers/gpu/drm/drm_probe_helper.c|  82 +++
 drivers/gpu/drm/tests/Makefile|   1 +
 drivers/gpu/drm/tests/drm_probe_helper_test.c | 205 ++
 include/drm/drm_probe_helper.h|   1 +
 4 files changed, 289 insertions(+)

diff --git a/drivers/gpu/drm/drm_probe_helper.c 
b/drivers/gpu/drm/drm_probe_helper.c
index bcd9611dabfd..1ea053cef557 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -1146,3 +1146,85 @@ int drm_connector_helper_get_modes(struct drm_connector 
*connector)
return count;
 }
 EXPORT_SYMBOL(drm_connector_helper_get_modes);
+
+/**
+ * drm_connector_helper_tv_get_modes - Fills the modes availables to a TV 
connector
+ * @connector: The connector
+ *
+ * Fills the available modes for a TV connector based on the supported
+ * TV modes, and the default mode expressed by the kernel command line.
+ *
+ * This can be used as the default TV connector helper .get_modes() hook
+ * if the driver does not need any special processing.
+ *
+ * Returns:
+ * The number of modes added to the connector.
+ */
+int drm_connector_helper_tv_get_modes(struct drm_connector *connector)
+{
+   struct drm_device *dev = connector->dev;
+   struct drm_property *tv_mode_property =
+   dev->mode_config.tv_mode_property;
+   struct drm_cmdline_mode *cmdline = >cmdline_mode;
+   unsigned int ntsc_modes = BIT(DRM_MODE_TV_MODE_NTSC) |
+   BIT(DRM_MODE_TV_MODE_NTSC_443) |
+   BIT(DRM_MODE_TV_MODE_NTSC_J) |
+   BIT(DRM_MODE_TV_MODE_PAL_M);
+   unsigned int pal_modes = BIT(DRM_MODE_TV_MODE_PAL) |
+   BIT(DRM_MODE_TV_MODE_PAL_N) |
+   BIT(DRM_MODE_TV_MODE_SECAM);
+   unsigned int tv_modes[2] = { UINT_MAX, UINT_MAX };
+   unsigned int i, supported_tv_modes = 0;
+
+   if (!tv_mode_property)
+   return 0;
+
+   for (i = 0; i < tv_mode_property->num_values; i++)
+   supported_tv_modes |= BIT(tv_mode_property->values[i]);
+
+   if ((supported_tv_modes & ntsc_modes) &&
+   (supported_tv_modes & pal_modes)) {
+   uint64_t default_mode;
+
+   if (drm_object_property_get_default_value(>base,
+ tv_mode_property,
+ _mode))
+   return 0;
+
+   if (cmdline->tv_mode_specified)
+   default_mode = cmdline->tv_mode;
+
+   if (BIT(default_mode) & ntsc_modes) {
+   tv_modes[0] = DRM_MODE_TV_MODE_NTSC;
+   tv_modes[1] = DRM_MODE_TV_MODE_PAL;
+   } else {
+   tv_modes[0] = DRM_MODE_TV_MODE_PAL;
+   tv_modes[1] = DRM_MODE_TV_MODE_NTSC;
+   }
+   } else if (supported_tv_modes & ntsc_modes) {
+   tv_modes[0] = DRM_MODE_TV_MODE_NTSC;
+   } else if (supported_tv_modes & pal_modes) {
+   tv_modes[0] = DRM_MODE_TV_MODE_PAL;
+   } else {
+   return 0;
+   }
+
+   for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
+   struct drm_display_mode *mode;
+
+   if (tv_modes[i] == DRM_MODE_TV_MODE_NTSC)
+   mode = drm_mode_analog_ntsc_480i(dev);
+   else if (tv_modes[i] == DRM_MODE_TV_MODE_PAL)
+   mode = drm_mode_analog_pal_576i(dev);
+   else
+   break;
+   if (!mode)
+   return i;
+   if (!i)
+   mode->type |= DRM_MODE_TYPE_PREFERRED;
+   drm_mode_probed_add(connector, mode);
+   }
+
+   return i;
+}
+EXPORT_SYMBOL(drm_connector_helper_tv_get_modes);
diff --git a/drivers/gpu/drm/tests/Makefile b/drivers/gpu/drm/tests/Makefile
index c7903c112c65..94fe546d937d 100644
--- a/drivers/gpu/drm/tests/Makefile
+++ b/drivers/gpu/drm/tests/Makefile
@@ -13,4 +13,5 @@ obj-$(CONFIG_DRM_KUNIT_TEST) += \
  

[Intel-gfx] [PATCH v10 10/19] drm/client: Remove match on mode name

[Maxime Ripard]

Commit 3aeeb13d8996 ("drm/modes: Support modes names on the command
line") initially introduced the named modes support by essentially
matching the name passed on the command-line to the mode names defined
by the drivers.

This proved to be difficult to work with, since all drivers had to
provide properly named modes. This was also needed because we weren't
passing a full blown-mode to the drivers, but were only filling its
name.

Thanks to the previous patches, we now generate a proper mode, and we
thus can use the usual matching algo on timings, and can simply drop the
name match.

Reviewed-by: Noralf Trønnes 
Suggested-by: Noralf Trønnes 
Signed-off-by: Maxime Ripard 

---
Changes in v8:
- New patch
---
 drivers/gpu/drm/drm_client_modeset.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/drm_client_modeset.c 
b/drivers/gpu/drm/drm_client_modeset.c
index d553e793e673..1b12a3c201a3 100644
--- a/drivers/gpu/drm/drm_client_modeset.c
+++ b/drivers/gpu/drm/drm_client_modeset.c
@@ -188,10 +188,6 @@ static struct drm_display_mode 
*drm_connector_pick_cmdline_mode(struct drm_conne
prefer_non_interlace = !cmdline_mode->interlace;
 again:
list_for_each_entry(mode, >modes, head) {
-   /* Check (optional) mode name first */
-   if (!strcmp(mode->name, cmdline_mode->name))
-   return mode;
-
/* check width/height */
if (mode->hdisplay != cmdline_mode->xres ||
mode->vdisplay != cmdline_mode->yres)

-- 
b4 0.11.0-dev-99e3a

[Intel-gfx] [PATCH v10 11/19] drm/modes: Introduce more named modes

[Maxime Ripard]

Now that we can easily extend the named modes list, let's add a few more
analog TV modes that were used in the wild, and some unit tests to make
sure it works as intended.

Reviewed-by: Noralf Trønnes 
Tested-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 

---
Changes in v9:
- Document the new supported names

Changes in v6:
- Renamed the tests to follow DRM test naming convention

Changes in v5:
- Switched to KUNIT_ASSERT_NOT_NULL
---
 Documentation/fb/modedb.rst | 3 +++
 drivers/gpu/drm/drm_modes.c | 2 ++
 drivers/gpu/drm/tests/drm_client_modeset_test.c | 2 ++
 3 files changed, 7 insertions(+)

diff --git a/Documentation/fb/modedb.rst b/Documentation/fb/modedb.rst
index bebfe61caa77..bb2889c6ea27 100644
--- a/Documentation/fb/modedb.rst
+++ b/Documentation/fb/modedb.rst
@@ -29,7 +29,10 @@ Things between square brackets are optional.
 Valid names are::
 
   - NSTC: 480i output, with the CCIR System-M TV mode and NTSC color encoding
+  - NTSC-J: 480i output, with the CCIR System-M TV mode, the NTSC color
+encoding, and a black level equal to the blanking level.
   - PAL: 576i output, with the CCIR System-B TV mode and PAL color encoding
+  - PAL-M: 480i output, with the CCIR System-M TV mode and PAL color encoding
 
 If 'M' is specified in the mode_option argument (after  and before
  and , if specified) the timings will be calculated using
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 3d410be8db69..699c66e54668 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -2274,7 +2274,9 @@ struct drm_named_mode {
 
 static const struct drm_named_mode drm_named_modes[] = {
NAMED_MODE("NTSC", 13500, 720, 480, DRM_MODE_FLAG_INTERLACE, 
DRM_MODE_TV_MODE_NTSC),
+   NAMED_MODE("NTSC-J", 13500, 720, 480, DRM_MODE_FLAG_INTERLACE, 
DRM_MODE_TV_MODE_NTSC_J),
NAMED_MODE("PAL", 13500, 720, 576, DRM_MODE_FLAG_INTERLACE, 
DRM_MODE_TV_MODE_PAL),
+   NAMED_MODE("PAL-M", 13500, 720, 480, DRM_MODE_FLAG_INTERLACE, 
DRM_MODE_TV_MODE_PAL_M),
 };
 
 static int drm_mode_parse_cmdline_named_mode(const char *name,
diff --git a/drivers/gpu/drm/tests/drm_client_modeset_test.c 
b/drivers/gpu/drm/tests/drm_client_modeset_test.c
index fe1f6be097a2..52929536a158 100644
--- a/drivers/gpu/drm/tests/drm_client_modeset_test.c
+++ b/drivers/gpu/drm/tests/drm_client_modeset_test.c
@@ -150,7 +150,9 @@ static void drm_test_pick_cmdline_named(struct kunit *test)
 static const
 struct drm_connector_pick_cmdline_mode_test 
drm_connector_pick_cmdline_mode_tests[] = {
TEST_CMDLINE("NTSC", drm_mode_analog_ntsc_480i),
+   TEST_CMDLINE("NTSC-J", drm_mode_analog_ntsc_480i),
TEST_CMDLINE("PAL", drm_mode_analog_pal_576i),
+   TEST_CMDLINE("PAL-M", drm_mode_analog_ntsc_480i),
 };
 
 static void

-- 
b4 0.11.0-dev-99e3a

[Intel-gfx] [PATCH v10 07/19] drm/connector: Add a function to lookup a TV mode by its name

[Maxime Ripard]

As part of the command line parsing rework coming in the next patches,
we'll need to lookup drm_connector_tv_mode values by their name, already
defined in drm_tv_mode_enum_list.

In order to avoid any code duplication, let's do a function that will
perform a lookup of a TV mode name and return its value.

Reviewed-by: Noralf Trønnes 
Tested-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 

---
Changes in v10:
- Add missing MODULE_* macros

Changes in v9:
- Switch the single invalid parameterized test to a regular test
- Switch to kunit_test_suite

Changes in v7:
- Add kunit tests
---
 drivers/gpu/drm/drm_connector.c| 24 ++
 drivers/gpu/drm/tests/Makefile |  1 +
 drivers/gpu/drm/tests/drm_connector_test.c | 76 ++
 include/drm/drm_connector.h|  2 +
 4 files changed, 103 insertions(+)

diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 07d449736956..8d92777e57dd 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -995,6 +995,30 @@ static const struct drm_prop_enum_list 
drm_tv_mode_enum_list[] = {
 };
 DRM_ENUM_NAME_FN(drm_get_tv_mode_name, drm_tv_mode_enum_list)
 
+/**
+ * drm_get_tv_mode_from_name - Translates a TV mode name into its enum value
+ * @name: TV Mode name we want to convert
+ * @len: Length of @name
+ *
+ * Translates @name into an enum drm_connector_tv_mode.
+ *
+ * Returns: the enum value on success, a negative errno otherwise.
+ */
+int drm_get_tv_mode_from_name(const char *name, size_t len)
+{
+   unsigned int i;
+
+   for (i = 0; i < ARRAY_SIZE(drm_tv_mode_enum_list); i++) {
+   const struct drm_prop_enum_list *item = 
_tv_mode_enum_list[i];
+
+   if (strlen(item->name) == len && !strncmp(item->name, name, 
len))
+   return item->type;
+   }
+
+   return -EINVAL;
+}
+EXPORT_SYMBOL(drm_get_tv_mode_from_name);
+
 static const struct drm_prop_enum_list drm_tv_select_enum_list[] = {
{ DRM_MODE_SUBCONNECTOR_Automatic, "Automatic" }, /* DVI-I and TV-out */
{ DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */
diff --git a/drivers/gpu/drm/tests/Makefile b/drivers/gpu/drm/tests/Makefile
index b22ac96fdd65..c7903c112c65 100644
--- a/drivers/gpu/drm/tests/Makefile
+++ b/drivers/gpu/drm/tests/Makefile
@@ -3,6 +3,7 @@
 obj-$(CONFIG_DRM_KUNIT_TEST) += \
drm_buddy_test.o \
drm_cmdline_parser_test.o \
+   drm_connector_test.o \
drm_damage_helper_test.o \
drm_dp_mst_helper_test.o \
drm_format_helper_test.o \
diff --git a/drivers/gpu/drm/tests/drm_connector_test.c 
b/drivers/gpu/drm/tests/drm_connector_test.c
new file mode 100644
index ..c66aa2dc8d9d
--- /dev/null
+++ b/drivers/gpu/drm/tests/drm_connector_test.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Kunit test for drm_modes functions
+ */
+
+#include 
+
+#include 
+
+struct drm_get_tv_mode_from_name_test {
+   const char *name;
+   enum drm_connector_tv_mode expected_mode;
+};
+
+#define TV_MODE_NAME(_name, _mode) \
+   {   \
+   .name = _name,  \
+   .expected_mode = _mode, \
+   }
+
+static void drm_test_get_tv_mode_from_name_valid(struct kunit *test)
+{
+   const struct drm_get_tv_mode_from_name_test *params = test->param_value;
+
+   KUNIT_EXPECT_EQ(test,
+   drm_get_tv_mode_from_name(params->name, 
strlen(params->name)),
+   params->expected_mode);
+}
+
+static const
+struct drm_get_tv_mode_from_name_test drm_get_tv_mode_from_name_valid_tests[] 
= {
+   TV_MODE_NAME("NTSC", DRM_MODE_TV_MODE_NTSC),
+   TV_MODE_NAME("NTSC-443", DRM_MODE_TV_MODE_NTSC_443),
+   TV_MODE_NAME("NTSC-J", DRM_MODE_TV_MODE_NTSC_J),
+   TV_MODE_NAME("PAL", DRM_MODE_TV_MODE_PAL),
+   TV_MODE_NAME("PAL-M", DRM_MODE_TV_MODE_PAL_M),
+   TV_MODE_NAME("PAL-N", DRM_MODE_TV_MODE_PAL_N),
+   TV_MODE_NAME("SECAM", DRM_MODE_TV_MODE_SECAM),
+};
+
+static void
+drm_get_tv_mode_from_name_valid_desc(const struct 
drm_get_tv_mode_from_name_test *t,
+char *desc)
+{
+   sprintf(desc, "%s", t->name);
+}
+
+KUNIT_ARRAY_PARAM(drm_get_tv_mode_from_name_valid,
+ drm_get_tv_mode_from_name_valid_tests,
+ drm_get_tv_mode_from_name_valid_desc);
+
+static void drm_test_get_tv_mode_from_name_truncated(struct kunit *test)
+{
+   const char *name = "NTS";
+   int ret;
+
+   ret = drm_get_tv_mode_from_name(name, strlen(name));
+   KUNIT_EXPECT_LT(test, ret, 0);
+};
+
+static struct kunit_case drm_get_tv_mode_from_name_tests[] = {
+   KUNIT_CASE_PARAM(drm_test_get_tv_mode_from_name_valid,
+drm_get_tv_mode_from_name_valid_gen_params),
+   KUNIT_CASE(drm_test_get_tv_mode_from_name_truncated),
+   

[Intel-gfx] [PATCH v10 03/19] drm/connector: Only register TV mode property if present

[Maxime Ripard]

The drm_create_tv_properties() will create the TV mode property
unconditionally.

However, since we'll gradually phase it out, let's register it only if we
have a list passed as an argument. This will make the transition easier.

Acked-by: Noralf Trønnes 
Tested-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/drm_connector.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 05edff79d312..78fcffae100b 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1690,15 +1690,18 @@ int drm_mode_create_tv_properties(struct drm_device 
*dev,
if (drm_mode_create_tv_margin_properties(dev))
goto nomem;
 
-   dev->mode_config.legacy_tv_mode_property =
-   drm_property_create(dev, DRM_MODE_PROP_ENUM,
-   "mode", num_modes);
-   if (!dev->mode_config.legacy_tv_mode_property)
-   goto nomem;
 
-   for (i = 0; i < num_modes; i++)
-   drm_property_add_enum(dev->mode_config.legacy_tv_mode_property,
- i, modes[i]);
+   if (num_modes) {
+   dev->mode_config.legacy_tv_mode_property =
+   drm_property_create(dev, DRM_MODE_PROP_ENUM,
+   "mode", num_modes);
+   if (!dev->mode_config.legacy_tv_mode_property)
+   goto nomem;
+
+   for (i = 0; i < num_modes; i++)
+   
drm_property_add_enum(dev->mode_config.legacy_tv_mode_property,
+ i, modes[i]);
+   }
 
dev->mode_config.tv_brightness_property =
drm_property_create_range(dev, 0, "brightness", 0, 100);

-- 
b4 0.11.0-dev-99e3a

[Intel-gfx] [PATCH v10 08/19] drm/modes: Introduce the tv_mode property as a command-line option

[Maxime Ripard]

Our new tv mode option allows to specify the TV mode from a property.
However, it can still be useful, for example to avoid any boot time
artifact, to set that property directly from the kernel command line.

Let's add some code to allow it, and some unit tests to exercise that code.

Reviewed-by: Noralf Trønnes 
Tested-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 

---
Changes in v10:
- Fix checkpatch warning

Changes in v7:
- Add Noralf Reviewed-by

Changes in v6:
- Add a tv_mode_specified field

Changes in v4:
- Add Documentation of the command-line option to modedb.rst
---
 Documentation/fb/modedb.rst |  2 +
 drivers/gpu/drm/drm_modes.c | 37 --
 drivers/gpu/drm/tests/drm_cmdline_parser_test.c | 68 +
 include/drm/drm_connector.h | 12 +
 4 files changed, 116 insertions(+), 3 deletions(-)

diff --git a/Documentation/fb/modedb.rst b/Documentation/fb/modedb.rst
index e53375033146..bebfe61caa77 100644
--- a/Documentation/fb/modedb.rst
+++ b/Documentation/fb/modedb.rst
@@ -70,6 +70,8 @@ Valid options are::
   - reflect_y (boolean): Perform an axial symmetry on the Y axis
   - rotate (integer): Rotate the initial framebuffer by x
 degrees. Valid values are 0, 90, 180 and 270.
+  - tv_mode: Analog TV mode. One of "NTSC", "NTSC-443", "NTSC-J", "PAL",
+"PAL-M", "PAL-N", or "SECAM".
   - panel_orientation, one of "normal", "upside_down", "left_side_up", or
 "right_side_up". For KMS drivers only, this sets the "panel orientation"
 property on the kms connector as hint for kms users.
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 9426c87df623..f9fe065f189b 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -2135,6 +2135,30 @@ static int drm_mode_parse_panel_orientation(const char 
*delim,
return 0;
 }
 
+static int drm_mode_parse_tv_mode(const char *delim,
+ struct drm_cmdline_mode *mode)
+{
+   const char *value;
+   int ret;
+
+   if (*delim != '=')
+   return -EINVAL;
+
+   value = delim + 1;
+   delim = strchr(value, ',');
+   if (!delim)
+   delim = value + strlen(value);
+
+   ret = drm_get_tv_mode_from_name(value, delim - value);
+   if (ret < 0)
+   return ret;
+
+   mode->tv_mode_specified = true;
+   mode->tv_mode = ret;
+
+   return 0;
+}
+
 static int drm_mode_parse_cmdline_options(const char *str,
  bool freestanding,
  const struct drm_connector *connector,
@@ -2204,6 +2228,9 @@ static int drm_mode_parse_cmdline_options(const char *str,
} else if (!strncmp(option, "panel_orientation", delim - 
option)) {
if (drm_mode_parse_panel_orientation(delim, mode))
return -EINVAL;
+   } else if (!strncmp(option, "tv_mode", delim - option)) {
+   if (drm_mode_parse_tv_mode(delim, mode))
+   return -EINVAL;
} else {
return -EINVAL;
}
@@ -2232,20 +2259,22 @@ struct drm_named_mode {
unsigned int xres;
unsigned int yres;
unsigned int flags;
+   unsigned int tv_mode;
 };
 
-#define NAMED_MODE(_name, _pclk, _x, _y, _flags)   \
+#define NAMED_MODE(_name, _pclk, _x, _y, _flags, _mode)\
{   \
.name = _name,  \
.pixel_clock_khz = _pclk,   \
.xres = _x, \
.yres = _y, \
.flags = _flags,\
+   .tv_mode = _mode,   \
}
 
 static const struct drm_named_mode drm_named_modes[] = {
-   NAMED_MODE("NTSC", 13500, 720, 480, DRM_MODE_FLAG_INTERLACE),
-   NAMED_MODE("PAL", 13500, 720, 576, DRM_MODE_FLAG_INTERLACE),
+   NAMED_MODE("NTSC", 13500, 720, 480, DRM_MODE_FLAG_INTERLACE, 
DRM_MODE_TV_MODE_NTSC),
+   NAMED_MODE("PAL", 13500, 720, 576, DRM_MODE_FLAG_INTERLACE, 
DRM_MODE_TV_MODE_PAL),
 };
 
 static int drm_mode_parse_cmdline_named_mode(const char *name,
@@ -2290,6 +2319,8 @@ static int drm_mode_parse_cmdline_named_mode(const char 
*name,
cmdline_mode->xres = mode->xres;
cmdline_mode->yres = mode->yres;
cmdline_mode->interlace = !!(mode->flags & 
DRM_MODE_FLAG_INTERLACE);
+   cmdline_mode->tv_mode = mode->tv_mode;
+   cmdline_mode->tv_mode_specified = true;
cmdline_mode->specified = true;
 
return 1;
diff --git a/drivers/gpu/drm/tests/drm_cmdline_parser_test.c 
b/drivers/gpu/drm/tests/drm_cmdline_parser_test.c
index 

[Intel-gfx] [PATCH v10 06/19] drm/modes: Add a function to generate analog display modes

[Maxime Ripard]

Multiple drivers (meson, vc4, sun4i) define analog TV 525-lines and
625-lines modes in their drivers.

Since those modes are fairly standard, and that we'll need to use them
in more places in the future, it makes sense to move their definition
into the core framework.

However, analog display usually have fairly loose timings requirements,
the only discrete parameters being the total number of lines and pixel
clock frequency. Thus, we created a function that will create a display
mode from the standard, the pixel frequency and the active area.

Tested-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 

---
Changes in v10:
- Fix checkpatch warning
- Add missing MODULE_* macros

Changes in v9:
- Rename the tests
- Switch to kunit_test_suite

Changes in v6:
- Fix typo

Changes in v4:
- Reworded the line length check comment
- Switch to HZ_PER_KHZ in tests
- Use previous timing to fill our mode
- Move the number of lines check earlier
---
 drivers/gpu/drm/drm_modes.c| 476 +
 drivers/gpu/drm/tests/Makefile |   1 +
 drivers/gpu/drm/tests/drm_modes_test.c | 145 ++
 include/drm/drm_modes.h|  17 ++
 4 files changed, 639 insertions(+)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 3c8034a8c27b..9426c87df623 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -116,6 +116,482 @@ void drm_mode_probed_add(struct drm_connector *connector,
 }
 EXPORT_SYMBOL(drm_mode_probed_add);
 
+enum drm_mode_analog {
+   DRM_MODE_ANALOG_NTSC, /* 525 lines, 60Hz */
+   DRM_MODE_ANALOG_PAL, /* 625 lines, 50Hz */
+};
+
+/*
+ * The timings come from:
+ * - 
https://web.archive.org/web/20220406232708/http://www.kolumbus.fi/pami1/video/pal_ntsc.html
+ * - 
https://web.archive.org/web/20220406124914/http://martin.hinner.info/vga/pal.html
+ * - 
https://web.archive.org/web/20220609202433/http://www.batsocks.co.uk/readme/video_timing.htm
+ */
+#define NTSC_LINE_DURATION_NS  63556U
+#define NTSC_LINES_NUMBER  525
+
+#define NTSC_HBLK_DURATION_TYP_NS  10900U
+#define NTSC_HBLK_DURATION_MIN_NS  (NTSC_HBLK_DURATION_TYP_NS - 200)
+#define NTSC_HBLK_DURATION_MAX_NS  (NTSC_HBLK_DURATION_TYP_NS + 200)
+
+#define NTSC_HACT_DURATION_TYP_NS  (NTSC_LINE_DURATION_NS - 
NTSC_HBLK_DURATION_TYP_NS)
+#define NTSC_HACT_DURATION_MIN_NS  (NTSC_LINE_DURATION_NS - 
NTSC_HBLK_DURATION_MAX_NS)
+#define NTSC_HACT_DURATION_MAX_NS  (NTSC_LINE_DURATION_NS - 
NTSC_HBLK_DURATION_MIN_NS)
+
+#define NTSC_HFP_DURATION_TYP_NS   1500
+#define NTSC_HFP_DURATION_MIN_NS   1270
+#define NTSC_HFP_DURATION_MAX_NS   2220
+
+#define NTSC_HSLEN_DURATION_TYP_NS 4700
+#define NTSC_HSLEN_DURATION_MIN_NS (NTSC_HSLEN_DURATION_TYP_NS - 100)
+#define NTSC_HSLEN_DURATION_MAX_NS (NTSC_HSLEN_DURATION_TYP_NS + 100)
+
+#define NTSC_HBP_DURATION_TYP_NS   4700
+
+/*
+ * I couldn't find the actual tolerance for the back porch, so let's
+ * just reuse the sync length ones.
+ */
+#define NTSC_HBP_DURATION_MIN_NS   (NTSC_HBP_DURATION_TYP_NS - 100)
+#define NTSC_HBP_DURATION_MAX_NS   (NTSC_HBP_DURATION_TYP_NS + 100)
+
+#define PAL_LINE_DURATION_NS   64000U
+#define PAL_LINES_NUMBER   625
+
+#define PAL_HACT_DURATION_TYP_NS   51950U
+#define PAL_HACT_DURATION_MIN_NS   (PAL_HACT_DURATION_TYP_NS - 100)
+#define PAL_HACT_DURATION_MAX_NS   (PAL_HACT_DURATION_TYP_NS + 400)
+
+#define PAL_HBLK_DURATION_TYP_NS   (PAL_LINE_DURATION_NS - 
PAL_HACT_DURATION_TYP_NS)
+#define PAL_HBLK_DURATION_MIN_NS   (PAL_LINE_DURATION_NS - 
PAL_HACT_DURATION_MAX_NS)
+#define PAL_HBLK_DURATION_MAX_NS   (PAL_LINE_DURATION_NS - 
PAL_HACT_DURATION_MIN_NS)
+
+#define PAL_HFP_DURATION_TYP_NS1650
+#define PAL_HFP_DURATION_MIN_NS(PAL_HFP_DURATION_TYP_NS - 100)
+#define PAL_HFP_DURATION_MAX_NS(PAL_HFP_DURATION_TYP_NS + 400)
+
+#define PAL_HSLEN_DURATION_TYP_NS  4700
+#define PAL_HSLEN_DURATION_MIN_NS  (PAL_HSLEN_DURATION_TYP_NS - 200)
+#define PAL_HSLEN_DURATION_MAX_NS  (PAL_HSLEN_DURATION_TYP_NS + 200)
+
+#define PAL_HBP_DURATION_TYP_NS5700
+#define PAL_HBP_DURATION_MIN_NS(PAL_HBP_DURATION_TYP_NS - 200)
+#define PAL_HBP_DURATION_MAX_NS(PAL_HBP_DURATION_TYP_NS + 200)
+
+struct analog_param_field {
+   unsigned int even, odd;
+};
+
+#define PARAM_FIELD(_odd, _even)   \
+   { .even = _even, .odd = _odd }
+
+struct analog_param_range {
+   unsigned intmin, typ, max;
+};
+
+#define PARAM_RANGE(_min, _typ, _max)  \
+   { .min = _min, .typ = _typ, .max = _max }
+
+struct analog_parameters {
+   unsigned intnum_lines;
+   unsigned intline_duration_ns;
+
+   struct analog_param_range   hact_ns;
+   struct analog_param_range   hfp_ns;
+   struct analog_param_range   

[Intel-gfx] [PATCH v10 05/19] drm/connector: Add TV standard property

[Maxime Ripard]

The TV mode property has been around for a while now to select and get the
current TV mode output on an analog TV connector.

Despite that property name being generic, its content isn't and has been
driver-specific which makes it hard to build any generic behaviour on top
of it, both in kernel and user-space.

Let's create a new enum tv norm property, that can contain any of the
analog TV standards currently supported by kernel drivers. Each driver can
then pass in a bitmask of the modes it supports, and the property
creation function will filter out the modes not supported.

We'll then be able to phase out the older tv mode property.

Tested-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 

---
Changes in v10:
- Fix checkpatch warning

Changes in v5:
- Create an analog TV properties documentation section, and document TV
  Mode there instead of the csv file

Changes in v4:
- Add property documentation to kms-properties.csv
- Fix documentation
---
 Documentation/gpu/drm-kms.rst |   6 ++
 drivers/gpu/drm/drm_atomic_uapi.c |   4 ++
 drivers/gpu/drm/drm_connector.c   | 122 +-
 include/drm/drm_connector.h   |  64 
 include/drm/drm_mode_config.h |   8 +++
 5 files changed, 203 insertions(+), 1 deletion(-)

diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index b4377a545425..321f2f582c64 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -520,6 +520,12 @@ HDMI Specific Connector Properties
 .. kernel-doc:: drivers/gpu/drm/drm_connector.c
:doc: HDMI connector properties
 
+Analog TV Specific Connector Properties
+--
+
+.. kernel-doc:: drivers/gpu/drm/drm_connector.c
+   :doc: Analog TV Connector Properties
+
 Standard CRTC Properties
 
 
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c 
b/drivers/gpu/drm/drm_atomic_uapi.c
index 7f2b9a07fbdf..d867e7f9f2cd 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -700,6 +700,8 @@ static int drm_atomic_connector_set_property(struct 
drm_connector *connector,
state->tv.margins.bottom = val;
} else if (property == config->legacy_tv_mode_property) {
state->tv.legacy_mode = val;
+   } else if (property == config->tv_mode_property) {
+   state->tv.mode = val;
} else if (property == config->tv_brightness_property) {
state->tv.brightness = val;
} else if (property == config->tv_contrast_property) {
@@ -810,6 +812,8 @@ drm_atomic_connector_get_property(struct drm_connector 
*connector,
*val = state->tv.margins.bottom;
} else if (property == config->legacy_tv_mode_property) {
*val = state->tv.legacy_mode;
+   } else if (property == config->tv_mode_property) {
+   *val = state->tv.mode;
} else if (property == config->tv_brightness_property) {
*val = state->tv.brightness;
} else if (property == config->tv_contrast_property) {
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 06e737ed15f5..07d449736956 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -984,6 +984,17 @@ static const struct drm_prop_enum_list 
drm_dvi_i_subconnector_enum_list[] = {
 DRM_ENUM_NAME_FN(drm_get_dvi_i_subconnector_name,
 drm_dvi_i_subconnector_enum_list)
 
+static const struct drm_prop_enum_list drm_tv_mode_enum_list[] = {
+   { DRM_MODE_TV_MODE_NTSC, "NTSC" },
+   { DRM_MODE_TV_MODE_NTSC_443, "NTSC-443" },
+   { DRM_MODE_TV_MODE_NTSC_J, "NTSC-J" },
+   { DRM_MODE_TV_MODE_PAL, "PAL" },
+   { DRM_MODE_TV_MODE_PAL_M, "PAL-M" },
+   { DRM_MODE_TV_MODE_PAL_N, "PAL-N" },
+   { DRM_MODE_TV_MODE_SECAM, "SECAM" },
+};
+DRM_ENUM_NAME_FN(drm_get_tv_mode_name, drm_tv_mode_enum_list)
+
 static const struct drm_prop_enum_list drm_tv_select_enum_list[] = {
{ DRM_MODE_SUBCONNECTOR_Automatic, "Automatic" }, /* DVI-I and TV-out */
{ DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */
@@ -1552,6 +1563,71 @@ 
EXPORT_SYMBOL(drm_connector_attach_dp_subconnector_property);
  * infoframe values is done through drm_hdmi_avi_infoframe_content_type().
  */
 
+/*
+ * TODO: Document the properties:
+ *   - left margin
+ *   - right margin
+ *   - top margin
+ *   - bottom margin
+ *   - brightness
+ *   - contrast
+ *   - flicker reduction
+ *   - hue
+ *   - mode
+ *   - overscan
+ *   - saturation
+ *   - select subconnector
+ *   - subconnector
+ */
+/**
+ * DOC: Analog TV Connector Properties
+ *
+ * TV Mode:
+ * Indicates the TV Mode used on an analog TV connector. The value
+ * of this property can be one of the following:
+ *
+ * NTSC:
+ * TV Mode is CCIR System M (aka 525-lines) together with
+ * the NTSC Color Encoding.
+ *
+ * NTSC-443:
+ *
+ * 

[Intel-gfx] [PATCH v10 04/19] drm/connector: Rename drm_mode_create_tv_properties

[Maxime Ripard]

drm_mode_create_tv_properties(), among other things, will create the
"mode" property that stores the analog TV mode that connector is
supposed to output.

However, that property is getting deprecated, so let's rename that
function to mention it's deprecated. We'll introduce a new variant of
that function creating the property superseeding it in a later patch.

Reviewed-by: Lyude Paul  # nouveau
Reviewed-by: Noralf Trønnes 
Tested-by: Mateusz Kwiatkowski 
Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/drm_connector.c   | 12 ++--
 drivers/gpu/drm/gud/gud_connector.c   |  4 ++--
 drivers/gpu/drm/i2c/ch7006_drv.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_tv.c   |  2 +-
 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c |  2 +-
 drivers/gpu/drm/vc4/vc4_vec.c |  5 +++--
 include/drm/drm_connector.h   |  6 +++---
 7 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 78fcffae100b..06e737ed15f5 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1604,7 +1604,7 @@ EXPORT_SYMBOL(drm_connector_attach_tv_margin_properties);
  * Called by a driver's HDMI connector initialization routine, this function
  * creates the TV margin properties for a given device. No need to call this
  * function for an SDTV connector, it's already called from
- * drm_mode_create_tv_properties().
+ * drm_mode_create_tv_properties_legacy().
  *
  * Returns:
  * 0 on success or a negative error code on failure.
@@ -1639,7 +1639,7 @@ int drm_mode_create_tv_margin_properties(struct 
drm_device *dev)
 EXPORT_SYMBOL(drm_mode_create_tv_margin_properties);
 
 /**
- * drm_mode_create_tv_properties - create TV specific connector properties
+ * drm_mode_create_tv_properties_legacy - create TV specific connector 
properties
  * @dev: DRM device
  * @num_modes: number of different TV formats (modes) supported
  * @modes: array of pointers to strings containing name of each format
@@ -1652,9 +1652,9 @@ EXPORT_SYMBOL(drm_mode_create_tv_margin_properties);
  * Returns:
  * 0 on success or a negative error code on failure.
  */
-int drm_mode_create_tv_properties(struct drm_device *dev,
- unsigned int num_modes,
- const char * const modes[])
+int drm_mode_create_tv_properties_legacy(struct drm_device *dev,
+unsigned int num_modes,
+const char * const modes[])
 {
struct drm_property *tv_selector;
struct drm_property *tv_subconnector;
@@ -1737,7 +1737,7 @@ int drm_mode_create_tv_properties(struct drm_device *dev,
 nomem:
return -ENOMEM;
 }
-EXPORT_SYMBOL(drm_mode_create_tv_properties);
+EXPORT_SYMBOL(drm_mode_create_tv_properties_legacy);
 
 /**
  * drm_mode_create_scaling_mode_property - create scaling mode property
diff --git a/drivers/gpu/drm/gud/gud_connector.c 
b/drivers/gpu/drm/gud/gud_connector.c
index 86e992b2108b..034e78360d4f 100644
--- a/drivers/gpu/drm/gud/gud_connector.c
+++ b/drivers/gpu/drm/gud/gud_connector.c
@@ -400,7 +400,7 @@ static int gud_connector_add_tv_mode(struct gud_device 
*gdrm, struct drm_connect
for (i = 0; i < num_modes; i++)
modes[i] = [i * GUD_CONNECTOR_TV_MODE_NAME_LEN];
 
-   ret = drm_mode_create_tv_properties(connector->dev, num_modes, modes);
+   ret = drm_mode_create_tv_properties_legacy(connector->dev, num_modes, 
modes);
 free:
kfree(buf);
if (ret < 0)
@@ -539,7 +539,7 @@ static int gud_connector_add_properties(struct gud_device 
*gdrm, struct gud_conn
fallthrough;
case GUD_PROPERTY_TV_HUE:
/* This is a no-op if already added. */
-   ret = drm_mode_create_tv_properties(drm, 0, NULL);
+   ret = drm_mode_create_tv_properties_legacy(drm, 0, 
NULL);
if (ret)
goto out;
break;
diff --git a/drivers/gpu/drm/i2c/ch7006_drv.c b/drivers/gpu/drm/i2c/ch7006_drv.c
index 9aff24e8e3b2..b9788218b2ec 100644
--- a/drivers/gpu/drm/i2c/ch7006_drv.c
+++ b/drivers/gpu/drm/i2c/ch7006_drv.c
@@ -250,7 +250,7 @@ static int ch7006_encoder_create_resources(struct 
drm_encoder *encoder,
struct drm_device *dev = encoder->dev;
struct drm_mode_config *conf = >mode_config;
 
-   drm_mode_create_tv_properties(dev, NUM_TV_NORMS, ch7006_tv_norm_names);
+   drm_mode_create_tv_properties_legacy(dev, NUM_TV_NORMS, 
ch7006_tv_norm_names);
 
priv->scale_property = drm_property_create_range(dev, 0, "scale", 0, 2);
if (!priv->scale_property)
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c 
b/drivers/gpu/drm/i915/display/intel_tv.c
index 95b021da5a11..0affbc80ba89 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c