[Intel-gfx] [PULL] drm-misc-next
Hi Daniel, Dave, We might be fairly late for a drm-misc-next PR by now, but I chose to send it anyway because we might have an -rc8, and this is almost exclusively fixes that should go in anyway. This will be the last drm-misc-next PR for this cycle Maxime drm-misc-next-2022-11-24: drm-misc-next for 6.2: UAPI Changes: Cross-subsystem Changes: - fbdev: Make fb_modesetting_disabled() static - udmabuf: Add vmap and vunmap methods to udmabuf_ops Core Changes: - doc: make drm-uapi igt-tests more readable - fb-helper: Revert of the damage worker removal - fourcc: Add missing big-endian XRGB1555 and RGB565 formats - gem-shmem: Fix for resource leakage in __drm_gem_shmem_create() - scheduler: Fix lockup in drm_sched_entity_kill() Driver Changes: The following changes since commit 35c3a2d02f0dc153a5f2f304ba33e1436b6a8d8f: drm/tests: helpers: Add SPDX header (2022-11-17 09:25:38 +0100) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2022-11-24 for you to fetch changes up to 6fb6c979ca628583d4d0c59a0f8ff977e581ecc0: drm/fourcc: Add missing big-endian XRGB1555 and RGB565 formats (2022-11-23 20:34:46 +0100) drm-misc-next for 6.2: UAPI Changes: Cross-subsystem Changes: - fbdev: Make fb_modesetting_disabled() static - udmabuf: Add vmap and vunmap methods to udmabuf_ops Core Changes: - doc: make drm-uapi igt-tests more readable - fb-helper: Revert of the damage worker removal - fourcc: Add missing big-endian XRGB1555 and RGB565 formats - gem-shmem: Fix for resource leakage in __drm_gem_shmem_create() - scheduler: Fix lockup in drm_sched_entity_kill() Driver Changes: ChunyouTang (1): drm/gem-shmem: When drm_gem_object_init failed, should release object Dmitry Osipenko (1): drm/scheduler: Fix lockup in drm_sched_entity_kill() Geert Uytterhoeven (1): drm/fourcc: Add missing big-endian XRGB1555 and RGB565 formats Lukasz Wiecaszek (1): udmabuf: add vmap and vunmap methods to udmabuf_ops Randy Dunlap (1): drm/doc: make drm-uapi igt-tests more readable Shang XiaoJing (1): drm: Fix potential null-ptr-deref due to drmm_mode_config_init() Thomas Zimmermann (4): fbdev: Make fb_modesetting_disabled() static inline Revert "drm/fb-helper: Remove damage worker" Revert "drm/fb-helper: Schedule deferred-I/O worker after writing to framebuffer" Revert "drm/fb-helper: Perform damage handling in deferred-I/O helper" Documentation/gpu/drm-uapi.rst | 12 ++-- drivers/dma-buf/udmabuf.c| 28 drivers/gpu/drm/drm_fb_helper.c | 30 +- drivers/gpu/drm/drm_fourcc.c | 4 drivers/gpu/drm/drm_gem.c| 19 --- drivers/gpu/drm/drm_gem_shmem_helper.c | 4 +++- drivers/gpu/drm/drm_mode_config.c| 8 +++- drivers/gpu/drm/scheduler/sched_entity.c | 2 +- drivers/gpu/drm/scheduler/sched_main.c | 4 ++-- drivers/video/fbdev/core/fb_defio.c | 16 include/drm/drm_fb_helper.h | 2 ++ include/drm/drm_gem.h| 1 + include/linux/fb.h | 3 +-- 13 files changed, 84 insertions(+), 49 deletions(-) signature.asc Description: PGP signature
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dp: wait on timeout before retry include sw delay
== Series Details == Series: drm/i915/dp: wait on timeout before retry include sw delay URL : https://patchwork.freedesktop.org/series/111303/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead
[Intel-gfx] [PATCH] drm/i915/dp: wait on timeout before retry include sw delay
AUX HW timeout is being set to max(4000ms), consider AUX SW timeout to
be 200ms more to avoid AUX boundary read//write.
HSDES: 1409498780
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 664bebdecea7..6c1c9602518b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -293,14 +293,13 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
DP_AUX_CH_CTL_RECEIVE_ERROR);
/*
-* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
-* 400us delay required for errors and timeouts
-* Timeout errors from the HW already meet this
-* requirement so skip to next iteration
+* Once the hw timeouts, before next try
+* need to add a sw timeout of 200usec(HSD: 1409498780).
*/
- if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
+ if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
+ usleep_range(200, 300);
continue;
-
+ }
if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
usleep_range(400, 500);
continue;
--
2.25.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: Do not parse context image for HSW (rev3)
== Series Details == Series: drm/i915/perf: Do not parse context image for HSW (rev3) URL : https://patchwork.freedesktop.org/series/111231/ State : success == Summary == CI Bug Log - changes from CI_DRM_12426 -> Patchwork_111231v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/index.html Participating hosts (37 -> 38) -- Additional (2): fi-tgl-dsi bat-dg1-6 Missing(1): fi-ctg-p8600 Known issues Here are the changes found in Patchwork_111231v3 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap@basic: - bat-dg1-6: NOTRUN -> [SKIP][1] ([i915#4083]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-dg1-6/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][2] ([i915#4079]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][3] ([i915#4077]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-6: NOTRUN -> [SKIP][4] ([i915#7561]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-dg1-6: NOTRUN -> [SKIP][5] ([i915#6621]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-dg1-6/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#4215]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@tile-pitch-mismatch: - bat-dg1-6: NOTRUN -> [SKIP][7] ([i915#4212]) +7 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html - bat-adlp-4: NOTRUN -> [SKIP][9] ([fdo#111827]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-adlp-4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-crc-fast: - bat-dg1-6: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#4103] / [i915#4213]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-dg1-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg1-6: NOTRUN -> [SKIP][12] ([fdo#109285]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-dg1-6/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@suspend-read-crc: - bat-adlp-4: NOTRUN -> [SKIP][13] ([i915#3546]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-adlp-4/igt@kms_pipe_crc_ba...@suspend-read-crc.html * igt@kms_psr@sprite_plane_onoff: - bat-dg1-6: NOTRUN -> [SKIP][14] ([i915#1072] / [i915#4078]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-dg1-6/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#3555]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-dg1-6/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-gtt: - bat-dg1-6: NOTRUN -> [SKIP][16] ([i915#3708] / [i915#4077]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-dg1-6/igt@prime_v...@basic-gtt.html * igt@prime_vgem@basic-read: - bat-dg1-6: NOTRUN -> [SKIP][17] ([i915#3708]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-dg1-6/igt@prime_v...@basic-read.html * igt@prime_vgem@basic-userptr: - bat-dg1-6: NOTRUN -> [SKIP][18] ([i915#3708] / [i915#4873]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v3/bat-dg1-6/igt@prime_v...@basic-userptr.html Possible fixes * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[INCOMPLETE][19]
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/perf: Do not parse context image for HSW (rev3)
== Series Details == Series: drm/i915/perf: Do not parse context image for HSW (rev3) URL : https://patchwork.freedesktop.org/series/111231/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/huc: always init the delayed load fence
== Series Details ==
Series: drm/i915/huc: always init the delayed load fence
URL : https://patchwork.freedesktop.org/series/111288/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12425 -> Patchwork_111288v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v1/index.html
Participating hosts (38 -> 37)
--
Missing(1): fi-ctg-p8600
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111288v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-dg2-11}: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-dg2-11/igt@gem_exec_suspend@basic...@smem.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v1/bat-dg2-11/igt@gem_exec_suspend@basic...@smem.html
Known issues
Here are the changes found in Patchwork_111288v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@basic:
- fi-pnv-d510:NOTRUN -> [SKIP][3] ([fdo#109271]) +5 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v1/fi-pnv-d510/igt@gem_lmem_swapp...@basic.html
* igt@i915_pm_rpm@module-reload:
- fi-blb-e6850: NOTRUN -> [SKIP][4] ([fdo#109271]) +5 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v1/fi-blb-e6850/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-blb-e6850: [INCOMPLETE][6] -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v1/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
- fi-pnv-d510:[INCOMPLETE][8] -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-pnv-d510/igt@core_hotunp...@unbind-rebind.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v1/fi-pnv-d510/igt@core_hotunp...@unbind-rebind.html
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][10] ([i915#2582]) -> [PASS][11] +4 similar
issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-rpls-2/igt@fb...@read.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v1/bat-rpls-2/igt@fb...@read.html
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[FAIL][12] ([i915#7229]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][14] ([i915#4785]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#6818]: https://gitlab.freedesktop.org/drm/intel/issues/6818
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
[i915#7346]: https://gitlab.freedesktop.org/drm/intel/issues/7346
Build changes
-
* Linux: CI_DRM_12425 -> Patchwork_111288v1
CI-20190529: 20190529
CI_DRM_12425: 66e5d8e0cdb991feba4fde2c851e700f993d240a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7072: 69ba7163475925cdc69aebbdfa0e87453ae165c7 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111288v1: 66e5d8e0cdb991feba4fde2c851e700f993d240a @
[Intel-gfx] [PATCH v2 0/3] drm/i915/pxp: Add missing cleanup steps for PXP global-teardown
A customer issue was recently discovered and in the process a gap in i915's PXP interaction with HW+FW architecure was also realized. This series adds those missing pieces. The patches explain the details. Changes from prior revs: v1: - Dont need to teardown non arbitration sessions (Juston). - Fix builds when PXP is enabled in config (Alan/CI-build) - Fix the broken pm-suspend-resume symmetry when we do this pxp-session-teardown during i915s pm_suspend_prepare by ensuring the init is done during i915s pm_resume_complete. Alan Previn (3): drm/i915/pxp: Invalidate all PXP fw sessions during teardown drm/i915/pxp: Trigger the global teardown for before suspending drm/i915/pxp: Pxp hw init should be in resume_complete drivers/gpu/drm/i915/gem/i915_gem_pm.c| 11 drivers/gpu/drm/i915/gem/i915_gem_pm.h| 2 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 7 ++- drivers/gpu/drm/i915/gt/intel_gt_pm.h | 2 + drivers/gpu/drm/i915/i915_driver.c| 16 + drivers/gpu/drm/i915/pxp/intel_pxp.c | 60 --- drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 + .../drm/i915/pxp/intel_pxp_cmd_interface_42.h | 15 + .../i915/pxp/intel_pxp_cmd_interface_cmn.h| 3 + drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 4 +- drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 6 +- drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 14 - drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 4 ++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 35 +++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 2 + 15 files changed, 164 insertions(+), 19 deletions(-) base-commit: 66e5d8e0cdb991feba4fde2c851e700f993d240a -- 2.34.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pxp: Create a backend abstraction layer for pxp-tee-link
== Series Details ==
Series: drm/i915/pxp: Create a backend abstraction layer for pxp-tee-link
URL : https://patchwork.freedesktop.org/series/111287/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12425 -> Patchwork_111287v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111287v1/index.html
Participating hosts (38 -> 36)
--
Additional (1): bat-atsm-1
Missing(3): fi-ctg-p8600 fi-rkl-11600 fi-cfl-8700k
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111287v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@core_hotunplug@unbind-rebind:
- {bat-dg2-9}:[PASS][1] -> [DMESG-WARN][2] +3 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-dg2-9/igt@core_hotunp...@unbind-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111287v1/bat-dg2-9/igt@core_hotunp...@unbind-rebind.html
* igt@gem_lmem_swapping@parallel-random-engines@lmem0:
- {bat-dg2-11}: [PASS][3] -> [DMESG-WARN][4] +7 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-dg2-11/igt@gem_lmem_swapping@parallel-random-engi...@lmem0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111287v1/bat-dg2-11/igt@gem_lmem_swapping@parallel-random-engi...@lmem0.html
- {bat-dg2-8}:[PASS][5] -> [DMESG-WARN][6] +8 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-dg2-8/igt@gem_lmem_swapping@parallel-random-engi...@lmem0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111287v1/bat-dg2-8/igt@gem_lmem_swapping@parallel-random-engi...@lmem0.html
* igt@gem_lmem_swapping@random-engines@lmem0:
- {bat-atsm-1}: NOTRUN -> [DMESG-WARN][7] +8 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111287v1/bat-atsm-1/igt@gem_lmem_swapping@random-engi...@lmem0.html
* igt@i915_selftest@live@workarounds:
- {bat-dg2-11}: [PASS][8] -> [INCOMPLETE][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-dg2-11/igt@i915_selftest@l...@workarounds.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111287v1/bat-dg2-11/igt@i915_selftest@l...@workarounds.html
- {bat-atsm-1}: NOTRUN -> [INCOMPLETE][10]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111287v1/bat-atsm-1/igt@i915_selftest@l...@workarounds.html
- {bat-dg2-9}:[PASS][11] -> [INCOMPLETE][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-dg2-9/igt@i915_selftest@l...@workarounds.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111287v1/bat-dg2-9/igt@i915_selftest@l...@workarounds.html
- {bat-dg2-8}:[PASS][13] -> [INCOMPLETE][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-dg2-8/igt@i915_selftest@l...@workarounds.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111287v1/bat-dg2-8/igt@i915_selftest@l...@workarounds.html
Known issues
Here are the changes found in Patchwork_111287v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111287v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
Possible fixes
* igt@i915_module_load@reload:
- {bat-rpls-2}: [DMESG-WARN][16] ([i915#6434]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-rpls-2/igt@i915_module_l...@reload.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111287v1/bat-rpls-2/igt@i915_module_l...@reload.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][18] ([i915#4785]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111287v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][20] ([i915#4983]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-rpls-1/igt@i915_selftest@l...@reset.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111287v1/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@i915_selftest@live@slpc:
- {bat-adln-1}: [DMESG-FAIL][22] ([i915#6997]) -> [PASS][23]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-adln-1/igt@i915_selftest@l...@slpc.html
[23]:
[Intel-gfx] ✓ Fi.CI.BAT: success for More GuC firmware version improvements (rev2)
== Series Details ==
Series: More GuC firmware version improvements (rev2)
URL : https://patchwork.freedesktop.org/series/111218/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12425 -> Patchwork_111218v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111218v2/index.html
Participating hosts (38 -> 37)
--
Additional (1): bat-atsm-1
Missing(2): fi-ctg-p8600 fi-rkl-11600
Known issues
Here are the changes found in Patchwork_111218v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#7073])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111218v2/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
* igt@gem_tiled_blits@basic:
- fi-pnv-d510:[PASS][3] -> [SKIP][4] ([fdo#109271]) +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111218v2/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-glk-j4005: [PASS][5] -> [DMESG-FAIL][6] ([i915#5334])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111218v2/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111218v2/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
Possible fixes
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][8] ([i915#2582]) -> [PASS][9] +4 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-rpls-2/igt@fb...@read.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111218v2/bat-rpls-2/igt@fb...@read.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][10] ([i915#4785]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111218v2/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][12] ([i915#4983]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-rpls-1/igt@i915_selftest@l...@reset.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111218v2/bat-rpls-1/igt@i915_selftest@l...@reset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6077]: https://gitlab.freedesktop.org/drm/intel/issues/6077
[i915#6078]: https://gitlab.freedesktop.org/drm/intel/issues/6078
[i915#6093]: https://gitlab.freedesktop.org/drm/intel/issues/6093
[i915#6094]: https://gitlab.freedesktop.org/drm/intel/issues/6094
[i915#6166]: https://gitlab.freedesktop.org/drm/intel/issues/6166
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7073]: https://gitlab.freedesktop.org/drm/intel/issues/7073
[i915#7357]: https://gitlab.freedesktop.org/drm/intel/issues/7357
[i915#7535]: https://gitlab.freedesktop.org/drm/intel/issues/7535
[i915#7554]: https://gitlab.freedesktop.org/drm/intel/issues/7554
Build changes
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/huc: always init the delayed load fence
== Series Details == Series: drm/i915/huc: always init the delayed load fence URL : https://patchwork.freedesktop.org/series/111288/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/pxp: Create a backend abstraction layer for pxp-tee-link
== Series Details == Series: drm/i915/pxp: Create a backend abstraction layer for pxp-tee-link URL : https://patchwork.freedesktop.org/series/111287/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead ./drivers/gpu/drm/i915/pxp/intel_pxp_types.h:1: warning: no structured comments found
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pxp: Create a backend abstraction layer for pxp-tee-link
== Series Details == Series: drm/i915/pxp: Create a backend abstraction layer for pxp-tee-link URL : https://patchwork.freedesktop.org/series/111287/ State : warning == Summary == Error: dim checkpatch failed 11ceb24c80fb HAX: drm/i915/pxp: Prepare intel_pxp entry points for MTL 362d4558aeaa drm/i915/pxp: Refactor mei-teelink checks at init/fini f76d384f0eaf drm/i915/pxp: Abstract mei-teelink function access via backend ptrs 0e1aed6ffa27 drm/i915/pxp: Separate tee-link front end interfaces from backend implementation Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in import git ModuleNotFoundError: No module named 'git' Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in import git ModuleNotFoundError: No module named 'git' -:415: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #415: new file mode 100644 -:521: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #521: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c:102: + GEM_BUG_ON(!pxp->stream_cmd.obj); total: 0 errors, 2 warnings, 0 checks, 730 lines checked 6f79db582769 drm/i915/pxp: move mei-pxp and mei-gsc resources to be backend-private -:206: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #206: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c:132: + GEM_BUG_ON(!mei->stream_cmd.obj); total: 0 errors, 1 warnings, 0 checks, 430 lines checked f90c8b2d8f09 drm/i915/pxp: Add PXP gsccs tee-link backend stubs Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in import git ModuleNotFoundError: No module named 'git' Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in import git ModuleNotFoundError: No module named 'git' -:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #25: new file mode 100644 -:113: ERROR:RETURN_PARENTHESES: return is not a function, parentheses are not required #113: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_tee.c:57: + return (HAS_ENGINE(gt, GSC0)); total: 1 errors, 1 warnings, 0 checks, 102 lines checked 03ebd40d438b drm/i915/pxp: Better hierarchy readibility - move backends to a backend folder -:8: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #8: This would provide clearer readibility of file hiearchy with regards to this -:50: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #50: rename from drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c total: 0 errors, 2 warnings, 0 checks, 53 lines checked
Re: [Intel-gfx] [PATCH] drm/i915/gt: Manage uncore->lock while waiting on MCR register
On Wed, Nov 23, 2022 at 02:46:18PM -0800, John Harrison wrote: > On 11/17/2022 09:33, Matt Roper wrote: > > ... > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c > > b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c > > index 830edffe88cc..d9a8ff9e5e57 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c > > @@ -730,17 +730,19 @@ void intel_gt_mcr_get_ss_steering(struct intel_gt > > *gt, unsigned int dss, > >* > >* Return: 0 if the register matches the desired condition, or -ETIMEDOUT. > >*/ > > -int intel_gt_mcr_wait_for_reg_fw(struct intel_gt *gt, > > -i915_mcr_reg_t reg, > > -u32 mask, > > -u32 value, > > -unsigned int fast_timeout_us, > > -unsigned int slow_timeout_ms) > > +int intel_gt_mcr_wait_for_reg(struct intel_gt *gt, > This change missed the comment above and so is causing errors from the > documentation build: Yeah, I already sent a fix for that here: https://patchwork.freedesktop.org/patch/512602/?series=111220=1 Matt > > Error: make htmldocs had i915 warnings > ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype > for intel_gt_mcr_wait_for_reg_fw(). Prototype was for > intel_gt_mcr_wait_for_reg() instead > ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype > for intel_gt_mcr_wait_for_reg_fw(). Prototype was for > intel_gt_mcr_wait_for_reg() instead > > John. > > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
Re: [Intel-gfx] [PATCH 2/2] drm/i915/pxp: Trigger the global teardown for before suspending
On Mon, 2022-11-21 at 14:14 -0800, Juston Li wrote:
> > Alan:[snip]
> >
> > > > +void intel_pxp_end(struct intel_pxp *pxp)
> > > > +{
> > > > + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
> > > > + intel_wakeref_t wakeref;
> > > > +
> > > > + if (!intel_pxp_is_enabled(pxp))
> > > > + return;
> > > > +
> > > > + wakeref = intel_runtime_pm_get(>runtime_pm);
> > > > +
> > > > + mutex_lock(>arb_mutex);
> > > > +
> > > > + if (__pxp_global_teardown_locked(pxp, true))
> > > > + drm_dbg(&(pxp_to_gt(pxp))->i915->drm, "PXP end
> > > > timed
> > > > out\n");
> > > > +
> > > > + mutex_unlock(>arb_mutex);
> > > > +
> > > > + intel_pxp_fini_hw(pxp);
> > >
> > > Is intel_pxp_suspend() still needed then if we already fini_hw()
> > > here
> > > and mark invalidation in intel_pxp_terminate()?
> > >
> >
> > Good catch - looks like we might not need intel_pxp_suspend. But I'll
> > verify that for you.
>
> Actually, might need to be careful here. If system aborts suspend or
> fails to suspend for any reason, suspend_prepare()->intel_pxp_fini_hw()
> might have been called but not suspend().
>
> Correct me if I'm wrong, but in that case I don't think resume() will
> be called and thus intel_pxp_init_hw().
>
> For some background, there were some issues with PXP ending up in a bad
> state when some other driver caused suspend to fail or user
> closed/opened lid quickly and aborted suspend.
>
>
Yeah, i only now notice that we although we define an i915 callback for 'struct
dev_pm_ops.prepare' we don't provide one
for 'struct dev_pm_ops.complete' which are the two opposing sides of
suspend-vs-resume phases - meaning we really should
be doing the intel_pxp_init_hw() in the "complete" callback. I will go ahead
and propose this change (considering this
is the last part of resume, I'm hoping it will not cause any regression) and
should address this concern and fix a "lack
of symmetry"
> > Also, looks like i forgot to include a non-CONFIG_DRM_I915_PXP
> > version of intel_pxp_end which was causing the build
> > failure. Will resend.
> >
> > Btw, thanks for reviewing this Juston, i had cc'd you because of the
> > impact to suspend-resume flows and I believe you
> > have had prior experience debugging issues with that and runtime-
> > suspend/resume. Do you any other issues with this
> > change?
>
> Np, thanks for the patches!
>
> The only other concern I had that's more of a downstream issue is we
> ended up using hw_state_invalidated to block PXP ioctl ops during
> teardown to prevent further PXP ioctls triggering pxp_start and another
> termination queued.
> I don't recall if I sent you this patch on our tree:
> https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3207105
> I think this could happen in suspend now too, if app sends PXP ops
> while suspend termination is in progress.
>
> Juston
Yes we did receive this patch.
[Intel-gfx] [PATCH v3] drm/i915/perf: Do not parse context image for HSW
An earlier commit introduced a mechanism to parse the context image to
find the OA context control offset. This resulted in an NPD on haswell
when gem_context was passed into i915_perf_open_ioctl params. Haswell
does not support logical ring contexts, so ensure that the context image
is parsed only for platforms with logical ring contexts and also
validate lrc_reg_state.
v2: Fix build failure
v3: Fix checkpatch error
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7432
Fixes: a5c3a3cbf029 ("drm/i915/perf: Determine gen12 oa ctx offset at runtime")
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 00e09bb18b13..125b6ca25a75 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1383,6 +1383,9 @@ static u32 oa_context_image_offset(struct intel_context
*ce, u32 reg)
u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
u32 *state = ce->lrc_reg_state;
+ if (drm_WARN_ON(>engine->i915->drm, !state))
+ return U32_MAX;
+
for (offset = 0; offset < len; ) {
if (IS_MI_LRI_CMD(state[offset])) {
/*
@@ -1447,7 +1450,8 @@ static int oa_get_render_ctx_id(struct i915_perf_stream
*stream)
if (IS_ERR(ce))
return PTR_ERR(ce);
- if (engine_supports_mi_query(stream->engine)) {
+ if (engine_supports_mi_query(stream->engine) &&
+ HAS_LOGICAL_RING_CONTEXTS(stream->perf->i915)) {
/*
* We are enabling perf query here. If we don't find the context
* offset here, just return an error.
--
2.36.1
[Intel-gfx] [PATCH] drm/i915/huc: always init the delayed load fence
The fence is only tracking if the HuC load is in progress or not and
doesn't distinguish between already loaded, not supported or disabled,
so we can always initialize it to completed, no matter the actual
support. We already do that for most platforms, but we skip it on
GTs that lack VCS engines (i.e. MTL root GT), so fix that. Note that the
cleanup is already unconditional.
While at it, move the init/fini to helper functions.
Fixes: 02224691cb0f ("drm/i915/huc: fix leak of debug object in huc load fence
on driver unload")
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 47 +++---
1 file changed, 34 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 0976e9101346..5f393f8e8b2e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -211,6 +211,30 @@ void intel_huc_unregister_gsc_notifier(struct intel_huc
*huc, struct bus_type *b
huc->delayed_load.nb.notifier_call = NULL;
}
+static void delayed_huc_load_init(struct intel_huc *huc)
+{
+ /*
+* Initialize fence to be complete as this is expected to be complete
+* unless there is a delayed HuC reload in progress.
+*/
+ i915_sw_fence_init(>delayed_load.fence,
+ sw_fence_dummy_notify);
+ i915_sw_fence_commit(>delayed_load.fence);
+
+ hrtimer_init(>delayed_load.timer, CLOCK_MONOTONIC,
HRTIMER_MODE_REL);
+ huc->delayed_load.timer.function = huc_delayed_load_timer_callback;
+}
+
+static void delayed_huc_load_fini(struct intel_huc *huc)
+{
+ /*
+* the fence is initialized in init_early, so we need to clean it up
+* even if HuC loading is off.
+*/
+ delayed_huc_load_complete(huc);
+ i915_sw_fence_fini(>delayed_load.fence);
+}
+
static bool vcs_supported(struct intel_gt *gt)
{
intel_engine_mask_t mask = gt->info.engine_mask;
@@ -241,6 +265,15 @@ void intel_huc_init_early(struct intel_huc *huc)
intel_uc_fw_init_early(>fw, INTEL_UC_FW_TYPE_HUC);
+ /*
+* we always init the fence as already completed, even if HuC is not
+* supported. This way we don't have to distinguish between HuC not
+* supported/disabled or already loaded, band can focus on if the load
+* is currently in progress (fence not complete) or not, which is what
+* we care about for stalling userspace submissions.
+*/
+ delayed_huc_load_init(huc);
+
if (!vcs_supported(gt)) {
intel_uc_fw_change_status(>fw,
INTEL_UC_FIRMWARE_NOT_SUPPORTED);
return;
@@ -255,17 +288,6 @@ void intel_huc_init_early(struct intel_huc *huc)
huc->status.mask = HUC_FW_VERIFIED;
huc->status.value = HUC_FW_VERIFIED;
}
-
- /*
-* Initialize fence to be complete as this is expected to be complete
-* unless there is a delayed HuC reload in progress.
-*/
- i915_sw_fence_init(>delayed_load.fence,
- sw_fence_dummy_notify);
- i915_sw_fence_commit(>delayed_load.fence);
-
- hrtimer_init(>delayed_load.timer, CLOCK_MONOTONIC,
HRTIMER_MODE_REL);
- huc->delayed_load.timer.function = huc_delayed_load_timer_callback;
}
#define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy")
@@ -333,8 +355,7 @@ void intel_huc_fini(struct intel_huc *huc)
* the fence is initialized in init_early, so we need to clean it up
* even if HuC loading is off.
*/
- delayed_huc_load_complete(huc);
- i915_sw_fence_fini(>delayed_load.fence);
+ delayed_huc_load_fini(huc);
if (intel_uc_fw_is_loadable(>fw))
intel_uc_fw_fini(>fw);
--
2.37.3
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for More GuC firmware version improvements (rev2)
== Series Details == Series: More GuC firmware version improvements (rev2) URL : https://patchwork.freedesktop.org/series/111218/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More GuC firmware version improvements (rev2)
== Series Details == Series: More GuC firmware version improvements (rev2) URL : https://patchwork.freedesktop.org/series/111218/ State : warning == Summary == Error: dim checkpatch failed 230524ea4d08 drm/i915/uc: Rationalise delimiters in filename macros 1a05b91ce526 drm/i915/uc: More refactoring of UC version numbers -:221: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ver' - possible side-effects? #221: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h:118: +#define MAKE_UC_VER_STRUCT(ver)MAKE_UC_VER((ver).major, (ver).minor, (ver).patch) total: 0 errors, 0 warnings, 1 checks, 190 lines checked 4439471aa4f5 drm/i915/guc: Use GuC submission API version number -:40: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ver' - possible side-effects? #40: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc.h:279: +#define MAKE_GUC_VER_STRUCT(ver) MAKE_GUC_VER((ver).major, (ver).minor, (ver).patch) total: 0 errors, 0 warnings, 1 checks, 271 lines checked
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Don't disable DDI/Transcoder when setting phy test pattern (rev5)
== Series Details ==
Series: drm/i915/display: Don't disable DDI/Transcoder when setting phy test
pattern (rev5)
URL : https://patchwork.freedesktop.org/series/108636/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12425 -> Patchwork_108636v5
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_108636v5 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108636v5, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v5/index.html
Participating hosts (38 -> 36)
--
Missing(2): fi-ctg-p8600 fi-hsw-4770
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_108636v5:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gt_lrc:
- bat-dg1-5: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-dg1-5/igt@i915_selftest@live@gt_lrc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v5/bat-dg1-5/igt@i915_selftest@live@gt_lrc.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@hangcheck:
- {fi-ehl-2}: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v5/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
Known issues
Here are the changes found in Patchwork_108636v5 that come from known issues:
### IGT changes ###
Issues hit
* igt@runner@aborted:
- bat-dg1-5: NOTRUN -> [FAIL][5] ([i915#4312])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v5/bat-dg1-5/igt@run...@aborted.html
Possible fixes
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][6] ([i915#2582]) -> [PASS][7] +4 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-rpls-2/igt@fb...@read.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v5/bat-rpls-2/igt@fb...@read.html
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[FAIL][8] ([i915#7229]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v5/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
* igt@i915_module_load@reload:
- {bat-rpls-2}: [DMESG-WARN][10] ([i915#6434]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-rpls-2/igt@i915_module_l...@reload.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v5/bat-rpls-2/igt@i915_module_l...@reload.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][12] ([i915#4983]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-rpls-1/igt@i915_selftest@l...@reset.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v5/bat-rpls-1/igt@i915_selftest@l...@reset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
[i915#7346]: https://gitlab.freedesktop.org/drm/intel/issues/7346
Build changes
-
* Linux: CI_DRM_12425 -> Patchwork_108636v5
CI-20190529: 20190529
CI_DRM_12425: 66e5d8e0cdb991feba4fde2c851e700f993d240a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7072: 69ba7163475925cdc69aebbdfa0e87453ae165c7 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108636v5: 66e5d8e0cdb991feba4fde2c851e700f993d240a @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1795ce34eab6 drm/i915/display: Don't disable DDI/Transcoder when setting phy
test pattern
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108636v5/index.html
Re: [Intel-gfx] [PATCH 1/2] drm/i915/pxp: Invalidate all PXP fw sessions during teardown
On Mon, 2022-11-21 at 16:14 -0800, Juston Li wrote:
> On Thu, 2022-11-17 at 16:36 -0800, Alan Previn wrote:
> >
Alan: [snip]
> > +void intel_pxp_tee_end_all_fw_sessions(struct intel_pxp *pxp, u32
> > sessions_mask)
> > +{
> > + int n;
> > +
> > + for (n = 0; n < INTEL_PXP_MAX_HWDRM_SESSIONS; ++n) {
> > + intel_pxp_tee_end_one_fw_session(pxp, n,
> > (sessions_mask & 0x1) ? true : false);
>
> What's the reason for the is_alive bool here? Instead of only sending
> the invalidate cmd for the alive sessions?
>
> Although... for upstream we really only need to invalidate the ARB
> session right?
>
> Juston
>
Yes - will fix that - only the downstream code would need that behavior.
> > + sessions_mask = (sessions_mask >> 1);
> > + }
> > +}
Re: [Intel-gfx] [PATCH v4 1/6] drm/i915/pxp: Make gt and pxp init/fini aware of PXP-owning-GT
typo correction... On Tue, 2022-11-22 at 12:13 -0800, Alan Previn Teres Alexis wrote: > After a more comprehensive offline discussion with Daniele and Rodrigo, > design direction was made to go with Option2 > where we elevate pxp to a global subsystem and within it it establish a > pointer to the correct gt for pxp-controls. This > also reflects the current HW architectures where the PXP feature (when viewed > as a service for contexts and buffers) is > global to all subsystems including any workload on any tile, despite its > single control-knobs being only in the media > tile (because PXP controls needs to be global to the GPU to avoid any races). > > This would mean we move 'struct intel_pxp' to be under i915 so that all > subsystems that need to call into PXP would now > pass in i915 as its parameter. PXP internally would have a pointer to the > correct GT (media-tile for MTL and gt0 for typo: "pass in i915->pxp as its parameter" > prior). > > It would also mean that certain code will still look a little kludgy or needs > attention: > - power-related operations like init/fini and suspend/resume would now need > to called either before or after all-gt > equivalents to ensure proper flow. > - KCR IRQ will although being a gt level IRQ will now require passing i915 > into the pxp subsystem. > > *NOTE: above list, even if i missed any, would still be nowhere near the > amount of other external facing interfaces that > would be called by global subsystems that would now look clean with i915->pxp > as its param. > > ...alan
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/display: Don't disable DDI/Transcoder when setting phy test pattern (rev5)
== Series Details == Series: drm/i915/display: Don't disable DDI/Transcoder when setting phy test pattern (rev5) URL : https://patchwork.freedesktop.org/series/108636/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: switch to intel_de_* register accessors
== Series Details ==
Series: drm/i915/display: switch to intel_de_* register accessors
URL : https://patchwork.freedesktop.org/series/111281/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12425 -> Patchwork_111281v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111281v1/index.html
Participating hosts (38 -> 38)
--
Additional (1): fi-tgl-dsi
Missing(1): fi-ctg-p8600
Known issues
Here are the changes found in Patchwork_111281v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][1] ([i915#6179])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111281v1/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
Possible fixes
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][2] ([i915#2582]) -> [PASS][3] +4 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-rpls-2/igt@fb...@read.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111281v1/bat-rpls-2/igt@fb...@read.html
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[FAIL][4] ([i915#7229]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111281v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
Warnings
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [INCOMPLETE][6] ([i915#4817]) -> [FAIL][7]
([fdo#103375])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111281v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6179]: https://gitlab.freedesktop.org/drm/intel/issues/6179
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6856]: https://gitlab.freedesktop.org/drm/intel/issues/6856
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7125]: https://gitlab.freedesktop.org/drm/intel/issues/7125
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
[i915#7355]: https://gitlab.freedesktop.org/drm/intel/issues/7355
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7554]: https://gitlab.freedesktop.org/drm/intel/issues/7554
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
Build changes
-
* Linux: CI_DRM_12425 -> Patchwork_111281v1
CI-20190529: 20190529
CI_DRM_12425: 66e5d8e0cdb991feba4fde2c851e700f993d240a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7072: 69ba7163475925cdc69aebbdfa0e87453ae165c7 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111281v1: 66e5d8e0cdb991feba4fde2c851e700f993d240a @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
809345841230 drm/i915/fbc: switch to intel_de_* register accessors in display
code
3ca275f5c581 drm/i915/tc: switch to intel_de_* register accessors in display
code
d33fc04bc8af drm/i915/snps: switch to intel_de_* register accessors in display
code
dc68f8eeddfc drm/i915/wm: switch to intel_de_* register accessors in display
code
5bc60163fcd3 drm/i915/gmbus: switch to intel_de_* register accessors in display
code
0ebad48a3c8f drm/i915/dp-aux: switch to intel_de_* register accessors in
display code
f109f92c4648 drm/i915/dmc: switch to intel_de_* register accessors in
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/perf: Do not parse context image for HSW (rev2)
On Wed, Nov 23, 2022 at 07:22:56PM +, Patchwork wrote: Patch Details Series: drm/i915/perf: Do not parse context image for HSW (rev2) URL: [1]https://patchwork.freedesktop.org/series/111231/ State: failure Details: [2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v2/index.html CI Bug Log - changes from CI_DRM_12419_full -> Patchwork_111231v2_full Summary FAILURE Serious unknown changes coming with Patchwork_111231v2_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_111231v2_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) No changes in participating hosts Possible new issues Here are the unknown changes that may have been introduced in Patchwork_111231v2_full: IGT changes Possible regressions * igt@gem_exec_schedule@deep@vecs0: * shard-skl: NOTRUN -> [3]INCOMPLETE +1 similar issue * igt@kms_vblank@pipe-d-ts-continuation-modeset-hang: * shard-tglb: [4]PASS -> [5]INCOMPLETE This patch only touches OA code and affects only OA use cases, so the above failures are not related. Thanks, Umesh Known issues
Re: [Intel-gfx] [PATCH] drm/i915/gt: Manage uncore->lock while waiting on MCR register
On 11/17/2022 09:33, Matt Roper wrote: ... diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c index 830edffe88cc..d9a8ff9e5e57 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c @@ -730,17 +730,19 @@ void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss, * * Return: 0 if the register matches the desired condition, or -ETIMEDOUT. */ -int intel_gt_mcr_wait_for_reg_fw(struct intel_gt *gt, -i915_mcr_reg_t reg, -u32 mask, -u32 value, -unsigned int fast_timeout_us, -unsigned int slow_timeout_ms) +int intel_gt_mcr_wait_for_reg(struct intel_gt *gt, This change missed the comment above and so is causing errors from the documentation build: Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead John.
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: A check on mode->clock, if it exceeds max_dot_clock
== Series Details == Series: drm/i915/display: A check on mode->clock, if it exceeds max_dot_clock URL : https://patchwork.freedesktop.org/series/111240/ State : success == Summary == CI Bug Log - changes from CI_DRM_12419_full -> Patchwork_111240v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_111240v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ccs@block-copy-compressed: - shard-iclb: NOTRUN -> [SKIP][1] ([i915#5327]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-iclb1/igt@gem_...@block-copy-compressed.html * igt@gem_ctx_persistence@hang: - shard-skl: NOTRUN -> [SKIP][2] ([fdo#109271]) +183 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-skl1/igt@gem_ctx_persiste...@hang.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2842]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-tglb5/igt@gem_exec_fair@basic-f...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_params@larger-than-life-batch: - shard-glk: NOTRUN -> [SKIP][5] ([fdo#109271]) +45 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-glk9/igt@gem_exec_par...@larger-than-life-batch.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][6] -> [SKIP][7] ([i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-tglb5/igt@gem_huc_c...@huc-copy.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-tglb7/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-random: - shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-glk9/igt@gem_lmem_swapp...@heavy-random.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-skl10/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_userptr_blits@input-checking: - shard-skl: NOTRUN -> [DMESG-WARN][10] ([i915#4991]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-skl10/igt@gem_userptr_bl...@input-checking.html * igt@gen9_exec_parse@cmd-crossing-page: - shard-iclb: NOTRUN -> [SKIP][11] ([i915#2856]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-iclb1/igt@gen9_exec_pa...@cmd-crossing-page.html * igt@i915_pipe_stress@stress-xrgb-ytiled: - shard-skl: NOTRUN -> [FAIL][12] ([i915#7036]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-skl9/igt@i915_pipe_str...@stress-xrgb-ytiled.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#3989] / [i915#454]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-iclb7/igt@i915_pm...@dc6-psr.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-iclb3/igt@i915_pm...@dc6-psr.html * igt@i915_pm_rc6_residency@rc6-idle@vcs0: - shard-skl: NOTRUN -> [WARN][15] ([i915#1804]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-skl1/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html * igt@i915_pm_rpm@modeset-lpsp: - shard-skl: NOTRUN -> [DMESG-WARN][16] ([i915#1982]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-skl9/igt@i915_pm_...@modeset-lpsp.html * igt@i915_selftest@live@hangcheck: - shard-tglb: [PASS][17] -> [DMESG-WARN][18] ([i915#5591]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-tglb3/igt@i915_selftest@l...@hangcheck.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-tglb1/igt@i915_selftest@l...@hangcheck.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1: - shard-skl: NOTRUN -> [FAIL][19] ([i915#2521]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-skl10/igt@kms_async_flips@alternate-sync-async-f...@pipe-b-edp-1.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip: - shard-iclb: NOTRUN -> [SKIP][20] ([i915#5286]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111240v1/shard-iclb1/igt@kms_big...@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html * igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc:
[Intel-gfx] [RFC 4/7] drm/i915/pxp: Separate tee-link front end interfaces from backend implementation
Separate tee-link front end interfaces from backend implementation.
Duplicate intel_pxp_tee to intel_pxp_tee_mei keep the front end side
(like populating the backend hooks) in the former while keeping the
mei backend (like send_message) in the _mei variant.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 329 +-
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 16 +-
drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c | 334 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.h | 13 +
5 files changed, 359 insertions(+), 334 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 01974b82d205..6ed45d9145e8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -319,6 +319,7 @@ i915-y += i915_perf.o
i915-y += \
pxp/intel_pxp.o \
pxp/intel_pxp_tee.o \
+ pxp/intel_pxp_tee_mei.o \
pxp/intel_pxp_huc.o
i915-$(CONFIG_DRM_I915_PXP) += \
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index fa41f4224333..034e2eee5075 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -3,322 +3,10 @@
* Copyright(c) 2020 Intel Corporation.
*/
-#include
-
-#include
-#include
-
-#include "gem/i915_gem_lmem.h"
-
#include "i915_drv.h"
#include "intel_pxp.h"
-#include "intel_pxp_session.h"
#include "intel_pxp_tee.h"
-#include "intel_pxp_cmd_interface_42.h"
-#include "intel_pxp_huc.h"
-
-static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
-{
- struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
- struct intel_gt *gt = intel_pxp_get_owning_gt(i915);
-
- if (!gt)
- return NULL;
-
- return >pxp;
-}
-
-static int mei_tee_io_message(struct intel_pxp *pxp,
- void *msg_in, size_t msg_in_size,
- void *msg_out, size_t msg_out_max_size,
- size_t *msg_out_size)
-{
- struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
- struct i915_pxp_component *pxp_component = pxp->pxp_component;
- int ret = 0;
-
- mutex_lock(>tee_mutex);
-
- /*
-* The binding of the component is asynchronous from i915 probe, so we
-* can't be sure it has happened.
-*/
- if (!pxp_component) {
- ret = -ENODEV;
- goto unlock;
- }
-
- ret = pxp_component->ops->send(pxp_component->tee_dev, msg_in,
msg_in_size);
- if (ret) {
- drm_err(>drm, "Failed to send PXP TEE message\n");
- goto unlock;
- }
-
- ret = pxp_component->ops->recv(pxp_component->tee_dev, msg_out,
msg_out_max_size);
- if (ret < 0) {
- drm_err(>drm, "Failed to receive PXP TEE message\n");
- goto unlock;
- }
-
- if (ret > msg_out_max_size) {
- drm_err(>drm,
- "Failed to receive PXP TEE message due to unexpected
output size\n");
- ret = -ENOSPC;
- goto unlock;
- }
-
- if (msg_out_size)
- *msg_out_size = ret;
-
- ret = 0;
-unlock:
- mutex_unlock(>tee_mutex);
- return ret;
-}
-
-static int mei_tee_gsc_stream_message(struct intel_pxp *pxp,
- void *msg_in, size_t msg_in_size,
- void *msg_out, size_t msg_out_max_size,
- size_t *msg_out_size)
-{
- /* TODO: for bigger objects we need to use a sg of 4k pages */
- const size_t max_msg_size = PAGE_SIZE;
- struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
- struct i915_pxp_component *pxp_component = pxp->pxp_component;
- unsigned int offset = 0;
- struct scatterlist *sg;
- int ret;
-
- if (msg_in_size > max_msg_size || msg_out_max_size > max_msg_size)
- return -ENOSPC;
-
- mutex_lock(>tee_mutex);
-
- if (unlikely(!pxp_component || !pxp_component->ops->gsc_command)) {
- ret = -ENODEV;
- goto unlock;
- }
-
- GEM_BUG_ON(!pxp->stream_cmd.obj);
-
- sg = i915_gem_object_get_sg_dma(pxp->stream_cmd.obj, 0, );
-
- memcpy(pxp->stream_cmd.vaddr, msg_in, msg_in_size);
-
- ret = pxp_component->ops->gsc_command(pxp_component->tee_dev, 0, 0,
- sg, msg_in_size, sg);
- if (ret < 0)
- drm_err(>drm, "Failed to send PXP TEE gsc command\n");
- else
- memcpy(msg_out, pxp->stream_cmd.vaddr, msg_out_max_size);
-
-unlock:
- mutex_unlock(>tee_mutex);
- return ret;
-}
-
-/**
- *
[Intel-gfx] [RFC 7/7] drm/i915/pxp: Better hierarchy readibility - move backends to a backend folder
Move the mei and gsccs backend implementation files into a backend folder
This would provide clearer readibility of file hiearchy with regards to this
backend vs front end thus encouraging better code location selcection for
future changes.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile | 6 +++---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 4 ++--
.../drm/i915/pxp/{ => tee_backends}/intel_pxp_gsccs.c | 6 --
.../drm/i915/pxp/{ => tee_backends}/intel_pxp_gsccs.h | 0
.../i915/pxp/{ => tee_backends}/intel_pxp_tee_mei.c | 11 ++-
.../i915/pxp/{ => tee_backends}/intel_pxp_tee_mei.h | 0
6 files changed, 15 insertions(+), 12 deletions(-)
rename drivers/gpu/drm/i915/pxp/{ => tee_backends}/intel_pxp_gsccs.c (92%)
rename drivers/gpu/drm/i915/pxp/{ => tee_backends}/intel_pxp_gsccs.h (100%)
rename drivers/gpu/drm/i915/pxp/{ => tee_backends}/intel_pxp_tee_mei.c (98%)
rename drivers/gpu/drm/i915/pxp/{ => tee_backends}/intel_pxp_tee_mei.h (100%)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 05072d7a4ba4..10e252192b3f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -318,10 +318,10 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support. Base support is required for HuC
i915-y += \
pxp/intel_pxp.o \
- pxp/intel_pxp_tee.o \
- pxp/intel_pxp_tee_mei.o \
pxp/intel_pxp_huc.o \
- pxp/intel_pxp_gsccs.o
+ pxp/intel_pxp_tee.o \
+ pxp/tee_backends/intel_pxp_tee_mei.o \
+ pxp/tee_backends/intel_pxp_gsccs.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_cmd.o \
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index a4b7f6c7bc54..9b6e48929e6c 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -5,9 +5,9 @@
#include "i915_drv.h"
#include "intel_pxp.h"
-#include "intel_pxp_gsccs.h"
#include "intel_pxp_tee.h"
-#include "intel_pxp_tee_mei.h"
+#include "tee_backends/intel_pxp_gsccs.h"
+#include "tee_backends/intel_pxp_tee_mei.h"
int intel_pxp_teelink_create_session(struct intel_pxp *pxp,
int arb_session_id)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
b/drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_gsccs.c
similarity index 92%
rename from drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
rename to drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_gsccs.c
index a4243272ca73..6441018f5207 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
+++ b/drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_gsccs.c
@@ -4,8 +4,10 @@
*/
#include "i915_drv.h"
-#include "intel_pxp.h"
-#include "intel_pxp_gsccs.h"
+
+#include "pxp/intel_pxp.h"
+
+#include "pxp/tee_backends/intel_pxp_gsccs.h"
static int gsccs_tee_send_message(struct intel_pxp *pxp,
void *msg_in, size_t msg_in_size,
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
b/drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_gsccs.h
similarity index 100%
rename from drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
rename to drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_gsccs.h
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c
b/drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_tee_mei.c
similarity index 98%
rename from drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c
rename to drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_tee_mei.c
index a81e8859335e..881fc93b1cb0 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c
+++ b/drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_tee_mei.c
@@ -11,11 +11,12 @@
#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
-#include "intel_pxp.h"
-#include "intel_pxp_cmd_interface_42.h"
-#include "intel_pxp_huc.h"
-#include "intel_pxp_session.h"
-#include "intel_pxp_tee_mei.h"
+
+#include "pxp/intel_pxp.h"
+#include "pxp/intel_pxp_cmd_interface_42.h"
+#include "pxp/intel_pxp_huc.h"
+#include "pxp/intel_pxp_session.h"
+#include "pxp/tee_backends/intel_pxp_tee_mei.h"
struct mei_teelink_priv {
/**
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.h
b/drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_tee_mei.h
similarity index 100%
rename from drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.h
rename to drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_tee_mei.h
--
2.34.1
[Intel-gfx] [RFC 6/7] drm/i915/pxp: Add PXP gsccs tee-link backend stubs
Add PXP gsccs tee-link backend using empty stubs for now.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c | 46 ++
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h | 13 ++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 14 +--
4 files changed, 72 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6ed45d9145e8..05072d7a4ba4 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -320,7 +320,8 @@ i915-y += \
pxp/intel_pxp.o \
pxp/intel_pxp_tee.o \
pxp/intel_pxp_tee_mei.o \
- pxp/intel_pxp_huc.o
+ pxp/intel_pxp_huc.o \
+ pxp/intel_pxp_gsccs.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_cmd.o \
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
new file mode 100644
index ..a4243272ca73
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2022 Intel Corporation.
+ */
+
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_gsccs.h"
+
+static int gsccs_tee_send_message(struct intel_pxp *pxp,
+ void *msg_in, size_t msg_in_size,
+ void *msg_out, size_t msg_out_size_max,
+ size_t *msg_out_len)
+{
+ return -ENODEV;
+}
+
+static int
+gsccs_tee_create_session(struct intel_pxp *pxp,
+int session_id)
+{
+ return -ENODEV;
+}
+
+static bool gsccs_tee_is_ready(struct intel_pxp *pxp)
+{
+ return false;
+}
+
+static void gsccs_tee_fini(struct intel_pxp *pxp)
+{
+}
+
+static int gsccs_tee_init(struct intel_pxp *pxp)
+{
+ return -ENODEV;
+}
+
+void intel_pxp_init_gsccs_tee_hooks(struct intel_pxp *pxp)
+{
+ pxp->tee_link.init = gsccs_tee_init;
+ pxp->tee_link.fini = gsccs_tee_fini;
+ pxp->tee_link.is_ready = gsccs_tee_is_ready;
+ pxp->tee_link.create_session = gsccs_tee_create_session;
+ pxp->tee_link.send_message = gsccs_tee_send_message;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
new file mode 100644
index ..5fb9f2c042ff
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2022, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_TEE_GSCCS_H__
+#define __INTEL_PXP_TEE_GSCCS_H__
+
+struct intel_pxp;
+
+void intel_pxp_init_gsccs_tee_hooks(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_TEE_GSCCS_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 1171f339643c..a4b7f6c7bc54 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
+#include "intel_pxp_gsccs.h"
#include "intel_pxp_tee.h"
#include "intel_pxp_tee_mei.h"
@@ -51,6 +52,11 @@ bool intel_pxp_teelink_is_ready(struct intel_pxp *pxp)
return false;
}
+static bool gt_supports_teelink_via_gsccs(struct intel_gt *gt)
+{
+ return (HAS_ENGINE(gt, GSC0));
+}
+
static bool gt_supports_teelink_via_mei(struct intel_gt *gt)
{
return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && !HAS_ENGINE(gt, GSC0));
@@ -61,11 +67,13 @@ int intel_pxp_teelink_init(struct intel_pxp *pxp)
struct intel_gt *gt = pxp_to_gt(pxp);
int ret = -ENOLINK;
- if (!gt_supports_teelink_via_mei(gt))
+ if (gt_supports_teelink_via_mei(gt))
+ intel_pxp_init_mei_tee_hooks(pxp);
+ else if (gt_supports_teelink_via_gsccs(gt))
+ intel_pxp_init_gsccs_tee_hooks(pxp);
+ else
return -ENODEV;
- intel_pxp_init_mei_tee_hooks(pxp);
-
if (pxp->tee_link.init)
ret = pxp->tee_link.init(pxp);
if (ret)
--
2.34.1
[Intel-gfx] [RFC 5/7] drm/i915/pxp: move mei-pxp and mei-gsc resources to be backend-private
drm/i915/pxp: move mei-pxp and mei-gsc resources to be backend-private
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 14 +-
drivers/gpu/drm/i915/pxp/intel_pxp_huc.c | 4 +-
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 8 ++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c | 143 +--
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 38 ++---
7 files changed, 132 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 33f86bb05148..49105bb1d694 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -230,18 +230,6 @@ static void pxp_queue_termination(struct intel_pxp *pxp)
spin_unlock_irq(gt->irq_lock);
}
-static bool pxp_component_bound(struct intel_pxp *pxp)
-{
- bool bound = false;
-
- mutex_lock(>tee_mutex);
- if (pxp->pxp_component)
- bound = true;
- mutex_unlock(>tee_mutex);
-
- return bound;
-}
-
/*
* the arb session is restarted from the irq work when we receive the
* termination completion interrupt
@@ -260,7 +248,7 @@ int intel_pxp_start(struct drm_i915_private *i915)
if (!intel_pxp_is_enabled_on_gt(pxp))
return -ENODEV;
- if (wait_for(pxp_component_bound(pxp), 250))
+ if (wait_for(intel_pxp_teelink_is_ready(pxp), 250))
return -ENXIO;
mutex_lock(>arb_mutex);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
index 043344dbf566..69ee261a1f7e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
@@ -11,10 +11,10 @@
#include "gt/intel_gt.h"
#include "intel_pxp.h"
+#include "intel_pxp_cmd_interface_43.h"
#include "intel_pxp_huc.h"
#include "intel_pxp_tee.h"
#include "intel_pxp_types.h"
-#include "intel_pxp_cmd_interface_43.h"
int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp)
{
@@ -25,7 +25,7 @@ int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp)
dma_addr_t huc_phys_addr;
int err;
- if (!pxp->pxp_component)
+ if (!intel_pxp_teelink_is_ready(pxp))
return -ENODEV;
huc_phys_addr = i915_gem_object_get_dma_address(huc->fw.obj, 0);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
index 19ac8828cbde..dc907a338fdb 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -7,6 +7,7 @@
#include "intel_pxp_irq.h"
#include "intel_pxp_pm.h"
#include "intel_pxp_session.h"
+#include "intel_pxp_tee.h"
#include "i915_drv.h"
void intel_pxp_suspend_prepare(struct intel_pxp *pxp)
@@ -42,7 +43,7 @@ void intel_pxp_resume(struct intel_pxp *pxp)
* re-bound after we come out, so in that scenario we can defer the
* hw init to the bind call.
*/
- if (!pxp->pxp_component)
+ if (!intel_pxp_teelink_is_ready(pxp))
return;
intel_pxp_init_hw(pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 034e2eee5075..1171f339643c 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -43,6 +43,14 @@ int intel_pxp_teelink_send_message(struct intel_pxp *pxp,
msg_out_max_size);
}
+bool intel_pxp_teelink_is_ready(struct intel_pxp *pxp)
+{
+ if (pxp->tee_link.is_ready)
+ return pxp->tee_link.is_ready(pxp);
+
+ return false;
+}
+
static bool gt_supports_teelink_via_mei(struct intel_gt *gt)
{
return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && !HAS_ENGINE(gt, GSC0));
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
index 6c09fa11bcca..46852f164e36 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -13,6 +13,8 @@ struct intel_pxp;
int intel_pxp_teelink_init(struct intel_pxp *pxp);
void intel_pxp_teelink_fini(struct intel_pxp *pxp);
+bool intel_pxp_teelink_is_ready(struct intel_pxp *pxp);
+
int intel_pxp_teelink_create_session(struct intel_pxp *pxp,
int arb_session_id);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c
index cd54219ced06..a81e8859335e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c
@@ -17,6 +17,34 @@
#include "intel_pxp_session.h"
#include "intel_pxp_tee_mei.h"
+struct mei_teelink_priv {
+ /**
+* @pxp_component: i915_pxp_component struct of the bound mei_pxp
+* module. Only set and cleared inside component bind/unbind functions,
+* which are
[Intel-gfx] [RFC 3/7] drm/i915/pxp: Abstract mei-teelink function access via backend ptrs
Abstract mei-teelink function access via backend ptrs
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp_huc.c | 9 +-
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 2 +-
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 107 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 15 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 22
5 files changed, 112 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
index 2e1165522950..043344dbf566 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
@@ -23,8 +23,6 @@ int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp)
struct pxp43_start_huc_auth_in huc_in = {0};
struct pxp43_start_huc_auth_out huc_out = {0};
dma_addr_t huc_phys_addr;
- u8 client_id = 0;
- u8 fence_id = 0;
int err;
if (!pxp->pxp_component)
@@ -39,9 +37,10 @@ int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp)
huc_in.header.buffer_len = sizeof(huc_in.huc_base_address);
huc_in.huc_base_address = huc_phys_addr;
- err = intel_pxp_tee_stream_message(pxp, client_id, fence_id,
- _in, sizeof(huc_in),
- _out, sizeof(huc_out));
+ err = intel_pxp_teelink_send_message(pxp,
+_in, sizeof(huc_in),
+_out, sizeof(huc_out),
+NULL);
if (err < 0) {
drm_err(>i915->drm,
"Failed to send HuC load and auth command to GSC
[%d]!\n",
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
index 85572360c71a..dec209e57596 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -66,7 +66,7 @@ static int pxp_create_arb_session(struct intel_pxp *pxp)
return -EEXIST;
}
- ret = intel_pxp_tee_cmd_create_arb_session(pxp, ARB_SESSION);
+ ret = intel_pxp_teelink_create_session(pxp, ARB_SESSION);
if (ret) {
drm_err(>i915->drm, "tee cmd for arb session creation
failed\n");
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 23a848b52c75..fa41f4224333 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -28,10 +28,10 @@ static inline struct intel_pxp *i915_dev_to_pxp(struct
device *i915_kdev)
return >pxp;
}
-static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
- void *msg_in, u32 msg_in_size,
- void *msg_out, u32 msg_out_max_size,
- u32 *msg_out_rcv_size)
+static int mei_tee_io_message(struct intel_pxp *pxp,
+ void *msg_in, size_t msg_in_size,
+ void *msg_out, size_t msg_out_max_size,
+ size_t *msg_out_size)
{
struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
struct i915_pxp_component *pxp_component = pxp->pxp_component;
@@ -67,8 +67,8 @@ static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
goto unlock;
}
- if (msg_out_rcv_size)
- *msg_out_rcv_size = ret;
+ if (msg_out_size)
+ *msg_out_size = ret;
ret = 0;
unlock:
@@ -76,10 +76,10 @@ static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
return ret;
}
-int intel_pxp_tee_stream_message(struct intel_pxp *pxp,
-u8 client_id, u32 fence_id,
-void *msg_in, size_t msg_in_len,
-void *msg_out, size_t msg_out_len)
+static int mei_tee_gsc_stream_message(struct intel_pxp *pxp,
+ void *msg_in, size_t msg_in_size,
+ void *msg_out, size_t msg_out_max_size,
+ size_t *msg_out_size)
{
/* TODO: for bigger objects we need to use a sg of 4k pages */
const size_t max_msg_size = PAGE_SIZE;
@@ -89,7 +89,7 @@ int intel_pxp_tee_stream_message(struct intel_pxp *pxp,
struct scatterlist *sg;
int ret;
- if (msg_in_len > max_msg_size || msg_out_len > max_msg_size)
+ if (msg_in_size > max_msg_size || msg_out_max_size > max_msg_size)
return -ENOSPC;
mutex_lock(>tee_mutex);
@@ -103,14 +103,14 @@ int intel_pxp_tee_stream_message(struct intel_pxp *pxp,
sg = i915_gem_object_get_sg_dma(pxp->stream_cmd.obj, 0, );
- memcpy(pxp->stream_cmd.vaddr, msg_in, msg_in_len);
+ memcpy(pxp->stream_cmd.vaddr,
[Intel-gfx] [RFC 0/7] drm/i915/pxp: Create a backend abstraction layer for pxp-tee-link
PXP is a feature allowing workloads executing on engines to operate with encrypted buffers (via specific state instructions). On the other hand, PXP controls for operations like arbitration session creation and global teardown of PXP sessions require communicating with the security firmware. The transport layer to establish, execute and shutdown communication with the security firmware is different between TGL/ADL vs MTL. The former uses the mei component driver interfaces while the latter depends on the media-tile's GSC-command-streamer. Both cases have very different code flow and assets. This series aims to create a clean partition between the front end of the PXP subsystem and the backend-tee transport layer. The goal here is to present an intuitive layering using backend function pointers that will scale for future hardware backends while keeping the front end agnostic to the backend details. Alan Previn (7): HAX: drm/i915/pxp: Prepare intel_pxp entry points for MTL drm/i915/pxp: Refactor mei-teelink checks at init/fini drm/i915/pxp: Abstract mei-teelink function access via backend ptrs drm/i915/pxp: Separate tee-link front end interfaces from backend implementation drm/i915/pxp: move mei-pxp and mei-gsc resources to be backend-private drm/i915/pxp: Add PXP gsccs tee-link backend stubs drm/i915/pxp: Better hierarchy readibility - move backends to a backend folder drivers/gpu/drm/i915/Makefile | 4 +- .../drm/i915/display/skl_universal_plane.c| 2 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +- drivers/gpu/drm/i915/gem/i915_gem_create.c| 2 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +- drivers/gpu/drm/i915/i915_drv.h | 4 - drivers/gpu/drm/i915/pxp/intel_pxp.c | 103 +++-- drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 +- drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 8 +- drivers/gpu/drm/i915/pxp/intel_pxp_huc.c | 13 +- drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 4 +- drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 11 +- drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 310 ++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 22 +- drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 52 ++- .../i915/pxp/tee_backends/intel_pxp_gsccs.c | 48 +++ .../i915/pxp/tee_backends/intel_pxp_gsccs.h | 13 + .../i915/pxp/tee_backends/intel_pxp_tee_mei.c | 398 ++ .../i915/pxp/tee_backends/intel_pxp_tee_mei.h | 13 + 21 files changed, 677 insertions(+), 358 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_gsccs.c create mode 100644 drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_gsccs.h create mode 100644 drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_tee_mei.c create mode 100644 drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_tee_mei.h base-commit: c8b2ce6e20662ef30130e65f473b1ff5362765e3 -- 2.34.1
[Intel-gfx] [RFC 2/7] drm/i915/pxp: Refactor mei-teelink checks at init/fini
In preparation of MTL-pxp support, add helper functions to
determine if teelink is required and to determine the type
of teelink for the current gt-pxp subsystem.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 6 +++---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 26
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +++
3 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 58219beecfa4..33f86bb05148 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -174,7 +174,7 @@ static void pxp_init_full(struct intel_pxp *pxp)
if (ret)
return;
- ret = intel_pxp_tee_component_init(pxp);
+ ret = intel_pxp_teelink_init(pxp);
if (ret)
goto out_context;
@@ -197,14 +197,14 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (intel_pxp_supported_on_gt(pxp))
pxp_init_full(pxp);
else if (_gt_needs_teelink(gt))
- intel_pxp_tee_component_init(pxp);
+ intel_pxp_teelink_init(pxp);
}
void intel_pxp_fini(struct intel_pxp *pxp)
{
pxp->arb_is_valid = false;
- intel_pxp_tee_component_fini(pxp);
+ intel_pxp_teelink_fini(pxp);
destroy_vcs_context(pxp);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index b9198e961cb6..23a848b52c75 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -319,3 +319,29 @@ int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp
*pxp,
return ret;
}
+
+static bool gt_supports_teelink_via_mei(struct intel_gt *gt)
+{
+ return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && !HAS_ENGINE(gt, GSC0));
+}
+
+int intel_pxp_teelink_init(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ int ret = -ENOLINK;
+
+ if (!gt_supports_teelink_via_mei(gt))
+ return -ENODEV;
+
+ ret = intel_pxp_tee_component_init(pxp);
+ if (ret)
+ drm_warn(>i915->drm, "Teelink initialization failed with
%d\n", ret);
+
+ return ret;
+}
+
+void intel_pxp_teelink_fini(struct intel_pxp *pxp)
+{
+ intel_pxp_tee_component_fini(pxp);
+}
+
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
index aeb3dfe7ce96..62995e95773f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -19,4 +19,7 @@ int intel_pxp_tee_stream_message(struct intel_pxp *pxp,
void *msg_in, size_t msg_in_len,
void *msg_out, size_t msg_out_len);
+int intel_pxp_teelink_init(struct intel_pxp *pxp);
+void intel_pxp_teelink_fini(struct intel_pxp *pxp);
+
#endif /* __INTEL_PXP_TEE_H__ */
--
2.34.1
[Intel-gfx] [RFC 1/7] HAX: drm/i915/pxp: Prepare intel_pxp entry points for MTL
Squash of all the patches from the series:
https://patchwork.freedesktop.org/series/109429/
Above series is not a prerequisite to showcase the design changes
being proposed in the next set of patches but will be in the same
order dependency as here. NOTE: that series will be going through a
major redesign based on the latest review comments.
Signed-off-by: Alan Previn
---
.../drm/i915/display/skl_universal_plane.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +-
drivers/gpu/drm/i915/gem/i915_gem_create.c| 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 -
drivers/gpu/drm/i915/pxp/intel_pxp.c | 83 ---
drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 +++-
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 2 +-
drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 8 +-
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 4 +-
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 8 +-
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 18 +++-
12 files changed, 114 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 76490cc59d8f..3436bf433c10 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1848,7 +1848,7 @@ static bool bo_has_valid_encryption(struct
drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- return intel_pxp_key_check(_gt(i915)->pxp, obj, false) == 0;
+ return intel_pxp_key_check(i915, obj, false) == 0;
}
static bool pxp_is_borked(struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 7f2831efc798..15c3d435093a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -257,7 +257,7 @@ static int proto_context_set_protected(struct
drm_i915_private *i915,
if (!protected) {
pc->uses_protected_content = false;
- } else if (!intel_pxp_is_enabled(_gt(i915)->pxp)) {
+ } else if (!intel_pxp_is_enabled(i915)) {
ret = -ENODEV;
} else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) ||
!(pc->user_flags & BIT(UCONTEXT_BANNABLE))) {
@@ -271,8 +271,8 @@ static int proto_context_set_protected(struct
drm_i915_private *i915,
*/
pc->pxp_wakeref = intel_runtime_pm_get(>runtime_pm);
- if (!intel_pxp_is_active(_gt(i915)->pxp))
- ret = intel_pxp_start(_gt(i915)->pxp);
+ if (!intel_pxp_is_active(i915))
+ ret = intel_pxp_start(i915);
}
return ret;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 33673fe7ee0a..e44803f9bec4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -384,7 +384,7 @@ static int ext_set_protected(struct i915_user_extension
__user *base, void *data
if (ext.flags)
return -EINVAL;
- if (!intel_pxp_is_enabled(_gt(ext_data->i915)->pxp))
+ if (!intel_pxp_is_enabled(ext_data->i915))
return -ENODEV;
ext_data->flags |= I915_BO_PROTECTED;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 29e9e8d5b6fe..9943d5827300 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -869,7 +869,7 @@ static struct i915_vma *eb_lookup_vma(struct
i915_execbuffer *eb, u32 handle)
*/
if (i915_gem_context_uses_protected_content(eb->gem_context) &&
i915_gem_object_is_protected(obj)) {
- err = intel_pxp_key_check(>gt->pxp, obj, true);
+ err = intel_pxp_key_check(vm->gt->i915, obj, true);
if (err) {
i915_gem_object_put(obj);
return ERR_PTR(err);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a380db36d52c..a171ad57fe73 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -918,10 +918,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)
(INTEL_INFO(dev_priv)->has_global_mocs)
-#define HAS_PXP(dev_priv) ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \
- INTEL_INFO(dev_priv)->has_pxp) && \
- VDBOX_MASK(to_gt(dev_priv)))
-
#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
[Intel-gfx] [PATCH v2 2/3] drm/i915/uc: More refactoring of UC version numbers
From: John Harrison
As a precursor to a coming change (for adding a GuC submission API
version), abstract the UC version number into its own private
structure separate to the firmware filename.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c| 6 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 76 +++-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 15 +++--
3 files changed, 48 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 1d28286e6f066..e6edad6f8f9dd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -437,9 +437,9 @@ static void print_fw_ver(struct intel_uc *uc, struct
intel_uc_fw *fw)
drm_info(>drm, "%s firmware %s version %u.%u.%u\n",
intel_uc_fw_type_repr(fw->type), fw->file_selected.path,
-fw->file_selected.major_ver,
-fw->file_selected.minor_ver,
-fw->file_selected.patch_ver);
+fw->file_selected.ver.major,
+fw->file_selected.ver.minor,
+fw->file_selected.ver.patch);
}
static int __uc_init_hw(struct intel_uc *uc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 774c3d84a4243..5e2ee1ac89514 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -278,8 +278,8 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct
intel_uc_fw *uc_fw)
uc_fw->file_selected.path = blob->path;
uc_fw->file_wanted.path = blob->path;
- uc_fw->file_wanted.major_ver = blob->major;
- uc_fw->file_wanted.minor_ver = blob->minor;
+ uc_fw->file_wanted.ver.major = blob->major;
+ uc_fw->file_wanted.ver.minor = blob->minor;
uc_fw->loaded_via_gsc = blob->loaded_via_gsc;
found = true;
break;
@@ -438,28 +438,28 @@ static void __force_fw_fetch_failures(struct intel_uc_fw
*uc_fw, int e)
uc_fw->user_overridden = user;
} else if (i915_inject_probe_error(i915, e)) {
/* require next major version */
- uc_fw->file_wanted.major_ver += 1;
- uc_fw->file_wanted.minor_ver = 0;
+ uc_fw->file_wanted.ver.major += 1;
+ uc_fw->file_wanted.ver.minor = 0;
uc_fw->user_overridden = user;
} else if (i915_inject_probe_error(i915, e)) {
/* require next minor version */
- uc_fw->file_wanted.minor_ver += 1;
+ uc_fw->file_wanted.ver.minor += 1;
uc_fw->user_overridden = user;
- } else if (uc_fw->file_wanted.major_ver &&
+ } else if (uc_fw->file_wanted.ver.major &&
i915_inject_probe_error(i915, e)) {
/* require prev major version */
- uc_fw->file_wanted.major_ver -= 1;
- uc_fw->file_wanted.minor_ver = 0;
+ uc_fw->file_wanted.ver.major -= 1;
+ uc_fw->file_wanted.ver.minor = 0;
uc_fw->user_overridden = user;
- } else if (uc_fw->file_wanted.minor_ver &&
+ } else if (uc_fw->file_wanted.ver.minor &&
i915_inject_probe_error(i915, e)) {
/* require prev minor version - hey, this should work! */
- uc_fw->file_wanted.minor_ver -= 1;
+ uc_fw->file_wanted.ver.minor -= 1;
uc_fw->user_overridden = user;
} else if (user && i915_inject_probe_error(i915, e)) {
/* officially unsupported platform */
- uc_fw->file_wanted.major_ver = 0;
- uc_fw->file_wanted.minor_ver = 0;
+ uc_fw->file_wanted.ver.major = 0;
+ uc_fw->file_wanted.ver.minor = 0;
uc_fw->user_overridden = true;
}
}
@@ -471,9 +471,9 @@ static int check_gsc_manifest(const struct firmware *fw,
u32 version_hi = dw[HUC_GSC_VERSION_HI_DW];
u32 version_lo = dw[HUC_GSC_VERSION_LO_DW];
- uc_fw->file_selected.major_ver = FIELD_GET(HUC_GSC_MAJOR_VER_HI_MASK,
version_hi);
- uc_fw->file_selected.minor_ver = FIELD_GET(HUC_GSC_MINOR_VER_HI_MASK,
version_hi);
- uc_fw->file_selected.patch_ver = FIELD_GET(HUC_GSC_PATCH_VER_LO_MASK,
version_lo);
+ uc_fw->file_selected.ver.major = FIELD_GET(HUC_GSC_MAJOR_VER_HI_MASK,
version_hi);
+ uc_fw->file_selected.ver.minor = FIELD_GET(HUC_GSC_MINOR_VER_HI_MASK,
version_hi);
+ uc_fw->file_selected.ver.patch = FIELD_GET(HUC_GSC_PATCH_VER_LO_MASK,
version_lo);
return 0;
}
@@ -532,11 +532,11 @@ static int check_ccs_header(struct intel_gt *gt,
}
/* Get version numbers from the CSS header */
- uc_fw->file_selected.major_ver =
[Intel-gfx] [PATCH v2 0/3] More GuC firmware version improvements
From: John Harrison Start using the 'submission API version' for deciding which GuC API to use in the submission code. Correct version number manipulation code to support full 32bit major/minor/patch components, except for GuC which is guaranteed to be 8bit safe. Other minor code clean ups around version number handling. v2: Fix some typos, better naming, an extra comment and a bunch of refactoring of the GuC version number handling (review feedback by Daniele) Signed-off-by: John Harrison John Harrison (3): drm/i915/uc: Rationalise delimiters in filename macros drm/i915/uc: More refactoring of UC version numbers drm/i915/guc: Use GuC submission API version number drivers/gpu/drm/i915/gt/uc/intel_guc.h| 11 + .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 15 +- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 206 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 15 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 3 +- 6 files changed, 183 insertions(+), 73 deletions(-) -- 2.37.3
[Intel-gfx] [PATCH v2 3/3] drm/i915/guc: Use GuC submission API version number
From: John Harrison
The GuC firmware includes an extra version number to specify the
submission API level. So use that rather than the main firmware
version number for submission related checks.
Also, while it is guaranteed that GuC version number components are
only 8-bits in size, other firmwares do not have that restriction. So
stop making assumptions about them generically fitting in a u16
individually, or in a u32 as a combined 8.8.8.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 11 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 15 ++-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 124 --
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 10 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 3 +-
5 files changed, 137 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 1bb3f98292866..bb4dfe707a7d0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -158,6 +158,9 @@ struct intel_guc {
bool submission_selected;
/** @submission_initialized: tracks whether GuC submission has been
initialised */
bool submission_initialized;
+ /** @submission_version: Submission API version of the currently loaded
firmware */
+ struct intel_uc_fw_ver submission_version;
+
/**
* @rc_supported: tracks whether we support GuC rc on the current
platform
*/
@@ -268,6 +271,14 @@ struct intel_guc {
#endif
};
+/*
+ * GuC version number components are only 8-bit, so converting to a 32bit 8.8.8
+ * integer works.
+ */
+#define MAKE_GUC_VER(maj, min, pat)(((maj) << 16) | ((min) << 8) | (pat))
+#define MAKE_GUC_VER_STRUCT(ver) MAKE_GUC_VER((ver).major, (ver).minor,
(ver).patch)
+#define GUC_SUBMIT_VER(guc)
MAKE_GUC_VER_STRUCT((guc)->submission_version)
+
static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
{
return container_of(log, struct intel_guc, log);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0a42f1807f52c..53f7f599cde3a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1890,7 +1890,7 @@ int intel_guc_submission_init(struct intel_guc *guc)
if (guc->submission_initialized)
return 0;
- if (GET_UC_VER(guc) < MAKE_UC_VER(70, 0, 0)) {
+ if (GUC_SUBMIT_VER(guc) < MAKE_GUC_VER(1, 0, 0)) {
ret = guc_lrc_desc_pool_create_v69(guc);
if (ret)
return ret;
@@ -2330,7 +2330,7 @@ static int register_context(struct intel_context *ce,
bool loop)
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_register(ce);
- if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0))
+ if (GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 0, 0))
ret = register_context_v70(guc, ce, loop);
else
ret = register_context_v69(guc, ce, loop);
@@ -2342,7 +2342,7 @@ static int register_context(struct intel_context *ce,
bool loop)
set_context_registered(ce);
spin_unlock_irqrestore(>guc_state.lock, flags);
- if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0))
+ if (GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 0, 0))
guc_context_policy_init_v70(ce, loop);
}
@@ -2956,7 +2956,7 @@ static void __guc_context_set_preemption_timeout(struct
intel_guc *guc,
u16 guc_id,
u32 preemption_timeout)
{
- if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0)) {
+ if (GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 0, 0)) {
struct context_policy policy;
__guc_context_policy_start_klv(, guc_id);
@@ -3283,7 +3283,7 @@ static int guc_context_alloc(struct intel_context *ce)
static void __guc_context_set_prio(struct intel_guc *guc,
struct intel_context *ce)
{
- if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0)) {
+ if (GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 0, 0)) {
struct context_policy policy;
__guc_context_policy_start_klv(, ce->guc_id.id);
@@ -4366,7 +4366,7 @@ static int guc_init_global_schedule_policy(struct
intel_guc *guc)
intel_wakeref_t wakeref;
int ret = 0;
- if (GET_UC_VER(guc) < MAKE_UC_VER(70, 3, 0))
+ if (GUC_SUBMIT_VER(guc) < MAKE_GUC_VER(1, 1, 0))
return 0;
__guc_scheduling_policy_start_klv();
@@ -4905,6 +4905,9 @@ void intel_guc_submission_print_info(struct intel_guc
*guc,
if (!sched_engine)
return;
+ drm_printf(p, "GuC Submission API Version: %d.%d.%d\n",
+
[Intel-gfx] [PATCH v2 1/3] drm/i915/uc: Rationalise delimiters in filename macros
From: John Harrison The way delimiters (underscores and dots) were added to the UC filenames was different for different types of delimiter. Rationalise them to all be done the same way - implicitly in the concatenation macro rather than explicitly in the file name prefix. Signed-off-by: John Harrison Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 0c80ba51a4bdc..774c3d84a4243 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -118,35 +118,35 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, */ #define __MAKE_UC_FW_PATH_BLANK(prefix_, name_) \ "i915/" \ - __stringify(prefix_) name_ ".bin" + __stringify(prefix_) "_" name_ ".bin" #define __MAKE_UC_FW_PATH_MAJOR(prefix_, name_, major_) \ "i915/" \ - __stringify(prefix_) name_ \ + __stringify(prefix_) "_" name_ "_" \ __stringify(major_) ".bin" #define __MAKE_UC_FW_PATH_MMP(prefix_, name_, major_, minor_, patch_) \ "i915/" \ - __stringify(prefix_) name_ \ + __stringify(prefix_) "_" name_ "_" \ __stringify(major_) "." \ __stringify(minor_) "." \ __stringify(patch_) ".bin" /* Minor for internal driver use, not part of file name */ #define MAKE_GUC_FW_PATH_MAJOR(prefix_, major_, minor_) \ - __MAKE_UC_FW_PATH_MAJOR(prefix_, "_guc_", major_) + __MAKE_UC_FW_PATH_MAJOR(prefix_, "guc", major_) #define MAKE_GUC_FW_PATH_MMP(prefix_, major_, minor_, patch_) \ - __MAKE_UC_FW_PATH_MMP(prefix_, "_guc_", major_, minor_, patch_) + __MAKE_UC_FW_PATH_MMP(prefix_, "guc", major_, minor_, patch_) #define MAKE_HUC_FW_PATH_BLANK(prefix_) \ - __MAKE_UC_FW_PATH_BLANK(prefix_, "_huc") + __MAKE_UC_FW_PATH_BLANK(prefix_, "huc") #define MAKE_HUC_FW_PATH_GSC(prefix_) \ - __MAKE_UC_FW_PATH_BLANK(prefix_, "_huc_gsc") + __MAKE_UC_FW_PATH_BLANK(prefix_, "huc_gsc") #define MAKE_HUC_FW_PATH_MMP(prefix_, major_, minor_, patch_) \ - __MAKE_UC_FW_PATH_MMP(prefix_, "_huc_", major_, minor_, patch_) + __MAKE_UC_FW_PATH_MMP(prefix_, "huc", major_, minor_, patch_) /* * All blobs need to be declared via MODULE_FIRMWARE(). -- 2.37.3
[Intel-gfx] ✓ Fi.CI.BAT: success for Add module oriented dmesg output (rev2)
== Series Details ==
Series: Add module oriented dmesg output (rev2)
URL : https://patchwork.freedesktop.org/series/111050/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12425 -> Patchwork_111050v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v2/index.html
Participating hosts (38 -> 36)
--
Missing(2): fi-ctg-p8600 fi-hsw-4770
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111050v2:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@requests:
- {bat-rpls-1}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-rpls-1/igt@i915_selftest@l...@requests.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v2/bat-rpls-1/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@slpc:
- {bat-rpls-2}: [DMESG-FAIL][3] ([i915#6367]) -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-rpls-2/igt@i915_selftest@l...@slpc.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v2/bat-rpls-2/igt@i915_selftest@l...@slpc.html
Known issues
Here are the changes found in Patchwork_111050v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_tiled_blits@basic:
- fi-pnv-d510:[PASS][5] -> [SKIP][6] ([fdo#109271]) +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v2/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-rkl-11600: NOTRUN -> [SKIP][7] ([fdo#111827])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v2/fi-rkl-11600/igt@kms_chamel...@common-hpd-after-suspend.html
Possible fixes
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][8] ([i915#2582]) -> [PASS][9] +4 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-rpls-2/igt@fb...@read.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v2/bat-rpls-2/igt@fb...@read.html
* igt@i915_module_load@reload:
- {bat-rpls-2}: [DMESG-WARN][10] ([i915#6434]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/bat-rpls-2/igt@i915_module_l...@reload.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v2/bat-rpls-2/igt@i915_module_l...@reload.html
Warnings
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[FAIL][12] ([i915#7229]) -> [SKIP][13] ([fdo#109271])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v2/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [INCOMPLETE][14] ([i915#4817]) -> [FAIL][15]
([fdo#103375])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v2/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
Build changes
-
* Linux: CI_DRM_12425 -> Patchwork_111050v2
CI-20190529: 20190529
CI_DRM_12425: 66e5d8e0cdb991feba4fde2c851e700f993d240a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7072: 69ba7163475925cdc69aebbdfa0e87453ae165c7 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111050v2: 66e5d8e0cdb991feba4fde2c851e700f993d240a @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
a579176c4d7d drm/i915/uc: Update the gt/uc code to use gt_err and friends
fda9c48751ad drm/i915/guc: Add GuC CT specific debug print wrappers
[Intel-gfx] [PATCH v4] drm/i915/display: Don't disable DDI/Transcoder when setting phy test pattern
Bspecs has updated recently to remove the restriction to disable
DDI/Transcoder before setting PHY test pattern. This update is to
address PHY compliance test failures observed on a port with LTTPR.
The issue is that when Transc. is disabled, the main link signals fed
to LTTPR will be dropped invalidating link training, which will affect
the quality of the phy test pattern when the transcoder is enabled again.
v2: Update commit message (Clint)
v3: Add missing Signed-off in v2
v4: Update Bspec and commit message for pre-gen12 (Jani)
Bspec: 50482, 7555
Cc: Imre Deak
Cc: Clint Taylor
CC: Jani Nikula
Tested-by: Khaled Almahallawy
Signed-off-by: Khaled Almahallawy
Reviewed-by: Clint Taylor
Signed-off-by: Khaled Almahallawy
---
drivers/gpu/drm/i915/display/intel_dp.c | 59 -
1 file changed, 59 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index cf8a2f644bab..9ce3562d027d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3698,61 +3698,6 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp,
}
}
-static void
-intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
-{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_device *dev = dig_port->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
- enum pipe pipe = crtc->pipe;
- u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
-
- trans_ddi_func_ctl_value = intel_de_read(dev_priv,
-TRANS_DDI_FUNC_CTL(pipe));
- trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
- dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
-
- trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
- TGL_TRANS_DDI_PORT_MASK);
- trans_conf_value &= ~PIPECONF_ENABLE;
- dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
-
- intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
- intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
- trans_ddi_func_ctl_value);
- intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
-}
-
-static void
-intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
-const struct intel_crtc_state *crtc_state)
-{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_device *dev = dig_port->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- enum port port = dig_port->base.port;
- struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
- enum pipe pipe = crtc->pipe;
- u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
-
- trans_ddi_func_ctl_value = intel_de_read(dev_priv,
-TRANS_DDI_FUNC_CTL(pipe));
- trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
- dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
-
- trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
- TGL_TRANS_DDI_SELECT_PORT(port);
- trans_conf_value |= PIPECONF_ENABLE;
- dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
-
- intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
- intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
- intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
- trans_ddi_func_ctl_value);
-}
-
static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
const struct intel_crtc_state
*crtc_state)
{
@@ -3771,14 +3716,10 @@ static void intel_dp_process_phy_request(struct
intel_dp *intel_dp,
intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
link_status);
- intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
-
intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
intel_dp_phy_pattern_update(intel_dp, crtc_state);
- intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
-
drm_dp_dpcd_write(_dp->aux, DP_TRAINING_LANE0_SET,
intel_dp->train_set, crtc_state->lane_count);
--
2.25.1
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add module oriented dmesg output (rev2)
== Series Details == Series: Add module oriented dmesg output (rev2) URL : https://patchwork.freedesktop.org/series/111050/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
[Intel-gfx] ✗ Fi.CI.DOCS: warning for Add module oriented dmesg output (rev2)
== Series Details == Series: Add module oriented dmesg output (rev2) URL : https://patchwork.freedesktop.org/series/111050/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add module oriented dmesg output (rev2)
== Series Details ==
Series: Add module oriented dmesg output (rev2)
URL : https://patchwork.freedesktop.org/series/111050/
State : warning
== Summary ==
Error: dim checkpatch failed
60fd35ea849f drm/i915/gt: Start adding module oriented dmesg output
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 11, in
import git
ModuleNotFoundError: No module named 'git'
-:225: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#225:
new file mode 100644
-:242: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible
side-effects?
#242: FILE: drivers/gpu/drm/i915/gt/intel_gt_print.h:13:
+#define gt_err(_gt, _fmt, ...) \
+ drm_err(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
-:245: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible
side-effects?
#245: FILE: drivers/gpu/drm/i915/gt/intel_gt_print.h:16:
+#define gt_warn(_gt, _fmt, ...) \
+ drm_warn(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id,
##__VA_ARGS__)
-:248: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible
side-effects?
#248: FILE: drivers/gpu/drm/i915/gt/intel_gt_print.h:19:
+#define gt_notice(_gt, _fmt, ...) \
+ drm_notice(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id,
##__VA_ARGS__)
-:251: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible
side-effects?
#251: FILE: drivers/gpu/drm/i915/gt/intel_gt_print.h:22:
+#define gt_info(_gt, _fmt, ...) \
+ drm_info(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id,
##__VA_ARGS__)
-:254: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible
side-effects?
#254: FILE: drivers/gpu/drm/i915/gt/intel_gt_print.h:25:
+#define gt_dbg(_gt, _fmt, ...) \
+ drm_dbg(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
-:257: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible
side-effects?
#257: FILE: drivers/gpu/drm/i915/gt/intel_gt_print.h:28:
+#define gt_err_ratelimited(_gt, _fmt, ...) \
+ drm_err_ratelimited(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id,
##__VA_ARGS__)
-:260: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible
side-effects?
#260: FILE: drivers/gpu/drm/i915/gt/intel_gt_print.h:31:
+#define gt_probe_error(_gt, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ gt_dbg(_gt, _fmt, ##__VA_ARGS__); \
+ else \
+ gt_err(_gt, _fmt, ##__VA_ARGS__); \
+ } while (0)
-:260: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_fmt' - possible
side-effects?
#260: FILE: drivers/gpu/drm/i915/gt/intel_gt_print.h:31:
+#define gt_probe_error(_gt, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ gt_dbg(_gt, _fmt, ##__VA_ARGS__); \
+ else \
+ gt_err(_gt, _fmt, ##__VA_ARGS__); \
+ } while (0)
-:274: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible
side-effects?
#274: FILE: drivers/gpu/drm/i915/gt/intel_gt_print.h:45:
+#define gt_WARN(_gt, _condition, _fmt, ...) \
+ drm_WARN(&(_gt)->i915->drm, _condition, "GT%u: " _fmt, (_gt)->info.id,
##__VA_ARGS__)
-:277: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible
side-effects?
#277: FILE: drivers/gpu/drm/i915/gt/intel_gt_print.h:48:
+#define gt_WARN_ONCE(_gt, _condition, _fmt, ...) \
+ drm_WARN_ONCE(&(_gt)->i915->drm, _condition, "GT%u: " _fmt,
(_gt)->info.id, ##__VA_ARGS__)
total: 0 errors, 1 warnings, 10 checks, 237 lines checked
ea27dc23d9fd drm/i915/huc: Add HuC specific debug print wrappers
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 11, in
import git
ModuleNotFoundError: No module named 'git'
-:135: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#135:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 137 lines checked
2dc865e6be6d drm/i915/guc: Add GuC specific debug print wrappers
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 11, in
import git
ModuleNotFoundError: No module named 'git'
-:271: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#271: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:622:
if (!caplist) {
+ guc_dbg(guc, "capture: Failed to alloc cached caplist\n");
-:288: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#288: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:663:
if (!null_header) {
+ guc_dbg(guc, "capture: Failed to alloc cached null list\n");
-:635: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#635:
new file mode 100644
-:1169: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#1169: FILE: drivers/gpu/drm/i915/gt/uc/selftest_guc.c:156:
if (!ce) {
+ guc_err(guc, "Context array allocation failed\n");
total: 0 errors, 4 warnings, 0
[Intel-gfx] [PATCH 09/12] drm/i915/wm: switch to intel_de_* register accessors in display code
Avoid direct uncore use in display code.
Cc: Maarten Lankhorst
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/skl_watermark.c | 42 +---
1 file changed, 18 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index e0766d1be966..ae4e9e680c2e 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -45,8 +45,7 @@ u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private
*i915)
enum dbuf_slice slice;
for_each_dbuf_slice(i915, slice) {
- if (intel_uncore_read(>uncore,
- DBUF_CTL_S(slice)) & DBUF_POWER_STATE)
+ if (intel_de_read(i915, DBUF_CTL_S(slice)) & DBUF_POWER_STATE)
enabled_slices |= BIT(slice);
}
@@ -75,7 +74,7 @@ intel_sagv_block_time(struct drm_i915_private *i915)
if (DISPLAY_VER(i915) >= 14) {
u32 val;
- val = intel_uncore_read(>uncore, MTL_LATENCY_SAGV);
+ val = intel_de_read(i915, MTL_LATENCY_SAGV);
return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val);
} else if (DISPLAY_VER(i915) >= 12) {
@@ -756,18 +755,18 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *i915,
/* Cursor doesn't support NV12/planar, so no extra calculation needed */
if (plane_id == PLANE_CURSOR) {
- val = intel_uncore_read(>uncore, CUR_BUF_CFG(pipe));
+ val = intel_de_read(i915, CUR_BUF_CFG(pipe));
skl_ddb_entry_init_from_hw(ddb, val);
return;
}
- val = intel_uncore_read(>uncore, PLANE_BUF_CFG(pipe, plane_id));
+ val = intel_de_read(i915, PLANE_BUF_CFG(pipe, plane_id));
skl_ddb_entry_init_from_hw(ddb, val);
if (DISPLAY_VER(i915) >= 11)
return;
- val = intel_uncore_read(>uncore, PLANE_NV12_BUF_CFG(pipe,
plane_id));
+ val = intel_de_read(i915, PLANE_NV12_BUF_CFG(pipe, plane_id));
skl_ddb_entry_init_from_hw(ddb_y, val);
}
@@ -2821,36 +2820,32 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc
*crtc,
for (level = 0; level <= max_level; level++) {
if (plane_id != PLANE_CURSOR)
- val = intel_uncore_read(>uncore,
PLANE_WM(pipe, plane_id, level));
+ val = intel_de_read(i915, PLANE_WM(pipe,
plane_id, level));
else
- val = intel_uncore_read(>uncore,
CUR_WM(pipe, level));
+ val = intel_de_read(i915, CUR_WM(pipe, level));
skl_wm_level_from_reg_val(val, >wm[level]);
}
if (plane_id != PLANE_CURSOR)
- val = intel_uncore_read(>uncore,
PLANE_WM_TRANS(pipe, plane_id));
+ val = intel_de_read(i915, PLANE_WM_TRANS(pipe,
plane_id));
else
- val = intel_uncore_read(>uncore,
CUR_WM_TRANS(pipe));
+ val = intel_de_read(i915, CUR_WM_TRANS(pipe));
skl_wm_level_from_reg_val(val, >trans_wm);
if (HAS_HW_SAGV_WM(i915)) {
if (plane_id != PLANE_CURSOR)
- val = intel_uncore_read(>uncore,
- PLANE_WM_SAGV(pipe,
plane_id));
+ val = intel_de_read(i915, PLANE_WM_SAGV(pipe,
plane_id));
else
- val = intel_uncore_read(>uncore,
- CUR_WM_SAGV(pipe));
+ val = intel_de_read(i915, CUR_WM_SAGV(pipe));
skl_wm_level_from_reg_val(val, >sagv.wm0);
if (plane_id != PLANE_CURSOR)
- val = intel_uncore_read(>uncore,
-
PLANE_WM_SAGV_TRANS(pipe, plane_id));
+ val = intel_de_read(i915,
PLANE_WM_SAGV_TRANS(pipe, plane_id));
else
- val = intel_uncore_read(>uncore,
-
CUR_WM_SAGV_TRANS(pipe));
+ val = intel_de_read(i915,
CUR_WM_SAGV_TRANS(pipe));
skl_wm_level_from_reg_val(val, >sagv.trans_wm);
} else if (DISPLAY_VER(i915) >= 12) {
@@ -3126,8 +3121,8 @@ void skl_watermark_ipc_update(struct drm_i915_private
*i915)
if (!HAS_IPC(i915))
return;
- intel_uncore_rmw(>uncore, DISP_ARB_CTL2, DISP_IPC_ENABLE,
-skl_watermark_ipc_enabled(i915) ? DISP_IPC_ENABLE : 0);
+ intel_de_rmw(i915, DISP_ARB_CTL2,
[Intel-gfx] [PATCH 10/12] drm/i915/snps: switch to intel_de_* register accessors in display code
Avoid direct uncore use in display code.
Cc: Maarten Lankhorst
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index c799e891f8b5..9494cfd45519 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -44,18 +44,18 @@ void intel_snps_phy_wait_for_calibration(struct
drm_i915_private *i915)
}
}
-void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv,
+void intel_snps_phy_update_psr_power_state(struct drm_i915_private *i915,
enum phy phy, bool enable)
{
u32 val;
- if (!intel_phy_is_snps(dev_priv, phy))
+ if (!intel_phy_is_snps(i915, phy))
return;
val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR,
enable ? 2 : 3);
- intel_uncore_rmw(_priv->uncore, SNPS_PHY_TX_REQ(phy),
-SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val);
+ intel_de_rmw(i915, SNPS_PHY_TX_REQ(phy),
+SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val);
}
void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
@@ -1785,7 +1785,7 @@ void intel_mpllb_enable(struct intel_encoder *encoder,
*/
/* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */
- intel_uncore_rmw(_priv->uncore, enable_reg, 0, PLL_ENABLE);
+ intel_de_rmw(dev_priv, enable_reg, 0, PLL_ENABLE);
/*
* 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This
@@ -1830,14 +1830,13 @@ void intel_mpllb_disable(struct intel_encoder *encoder)
*/
/* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */
- intel_uncore_rmw(>uncore, enable_reg, PLL_ENABLE, 0);
+ intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0);
/*
* 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0".
* This will allow the PLL to stop running.
*/
- intel_uncore_rmw(>uncore, SNPS_PHY_MPLLB_DIV(phy),
-SNPS_PHY_MPLLB_FORCE_EN, 0);
+ intel_de_rmw(i915, SNPS_PHY_MPLLB_DIV(phy), SNPS_PHY_MPLLB_FORCE_EN, 0);
/*
* 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment
--
2.34.1
[Intel-gfx] [PATCH 12/12] drm/i915/fbc: switch to intel_de_* register accessors in display code
Avoid direct uncore use in display code. Use the new
intel_de_rewrite_fw().
Cc: Maarten Lankhorst
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_fbc.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index b5ee5ea0d010..6066ac412e6f 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -323,10 +323,7 @@ static void i8xx_fbc_nuke(struct intel_fbc *fbc)
enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
struct drm_i915_private *dev_priv = fbc->i915;
- spin_lock_irq(_priv->uncore.lock);
- intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
- intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
- spin_unlock_irq(_priv->uncore.lock);
+ intel_de_rewrite_fw(dev_priv, DSPADDR(i9xx_plane));
}
static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
@@ -359,10 +356,7 @@ static void i965_fbc_nuke(struct intel_fbc *fbc)
enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
struct drm_i915_private *dev_priv = fbc->i915;
- spin_lock_irq(_priv->uncore.lock);
- intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
- intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
- spin_unlock_irq(_priv->uncore.lock);
+ intel_de_rewrite_fw(dev_priv, DSPSURF(i9xx_plane));
}
static const struct intel_fbc_funcs i965_fbc_funcs = {
--
2.34.1
[Intel-gfx] [PATCH 08/12] drm/i915/gmbus: switch to intel_de_* register accessors in display code
Avoid direct uncore use in display code.
Cc: Maarten Lankhorst
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_gmbus.c | 46 --
1 file changed, 17 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index a5840a28a69d..0bc4f6b48e80 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -255,14 +255,12 @@ static void bxt_gmbus_clock_gating(struct
drm_i915_private *i915,
static u32 get_reserved(struct intel_gmbus *bus)
{
struct drm_i915_private *i915 = bus->i915;
- struct intel_uncore *uncore = >uncore;
u32 reserved = 0;
/* On most chips, these bits must be preserved in software. */
if (!IS_I830(i915) && !IS_I845G(i915))
- reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) &
- (GPIO_DATA_PULLUP_DISABLE |
- GPIO_CLOCK_PULLUP_DISABLE);
+ reserved = intel_de_read_notrace(i915, bus->gpio_reg) &
+ (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE);
return reserved;
}
@@ -270,37 +268,31 @@ static u32 get_reserved(struct intel_gmbus *bus)
static int get_clock(void *data)
{
struct intel_gmbus *bus = data;
- struct intel_uncore *uncore = >i915->uncore;
+ struct drm_i915_private *i915 = bus->i915;
u32 reserved = get_reserved(bus);
- intel_uncore_write_notrace(uncore,
- bus->gpio_reg,
- reserved | GPIO_CLOCK_DIR_MASK);
- intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
+ intel_de_write_notrace(i915, bus->gpio_reg, reserved |
GPIO_CLOCK_DIR_MASK);
+ intel_de_write_notrace(i915, bus->gpio_reg, reserved);
- return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
- GPIO_CLOCK_VAL_IN) != 0;
+ return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_CLOCK_VAL_IN)
!= 0;
}
static int get_data(void *data)
{
struct intel_gmbus *bus = data;
- struct intel_uncore *uncore = >i915->uncore;
+ struct drm_i915_private *i915 = bus->i915;
u32 reserved = get_reserved(bus);
- intel_uncore_write_notrace(uncore,
- bus->gpio_reg,
- reserved | GPIO_DATA_DIR_MASK);
- intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
+ intel_de_write_notrace(i915, bus->gpio_reg, reserved |
GPIO_DATA_DIR_MASK);
+ intel_de_write_notrace(i915, bus->gpio_reg, reserved);
- return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
- GPIO_DATA_VAL_IN) != 0;
+ return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_DATA_VAL_IN)
!= 0;
}
static void set_clock(void *data, int state_high)
{
struct intel_gmbus *bus = data;
- struct intel_uncore *uncore = >i915->uncore;
+ struct drm_i915_private *i915 = bus->i915;
u32 reserved = get_reserved(bus);
u32 clock_bits;
@@ -310,16 +302,14 @@ static void set_clock(void *data, int state_high)
clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
GPIO_CLOCK_VAL_MASK;
- intel_uncore_write_notrace(uncore,
- bus->gpio_reg,
- reserved | clock_bits);
- intel_uncore_posting_read(uncore, bus->gpio_reg);
+ intel_de_write_notrace(i915, bus->gpio_reg, reserved | clock_bits);
+ intel_de_posting_read(i915, bus->gpio_reg);
}
static void set_data(void *data, int state_high)
{
struct intel_gmbus *bus = data;
- struct intel_uncore *uncore = >i915->uncore;
+ struct drm_i915_private *i915 = bus->i915;
u32 reserved = get_reserved(bus);
u32 data_bits;
@@ -329,8 +319,8 @@ static void set_data(void *data, int state_high)
data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
GPIO_DATA_VAL_MASK;
- intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits);
- intel_uncore_posting_read(uncore, bus->gpio_reg);
+ intel_de_write_notrace(i915, bus->gpio_reg, reserved | data_bits);
+ intel_de_posting_read(i915, bus->gpio_reg);
}
static int
@@ -439,9 +429,7 @@ gmbus_wait_idle(struct drm_i915_private *i915)
add_wait_queue(>display.gmbus.wait_queue, );
intel_de_write_fw(i915, GMBUS4(i915), irq_enable);
- ret = intel_wait_for_register_fw(>uncore,
-GMBUS2(i915), GMBUS_ACTIVE, 0,
-10);
+ ret = intel_de_wait_for_register_fw(i915, GMBUS2(i915), GMBUS_ACTIVE,
0, 10);
intel_de_write_fw(i915, GMBUS4(i915), 0);
remove_wait_queue(>display.gmbus.wait_queue, );
--
2.34.1
[Intel-gfx] [PATCH 06/12] drm/i915/dmc: switch to intel_de_* register accessors in display code
Avoid direct uncore use in display code.
Cc: Maarten Lankhorst
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dmc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 081a4d0083b1..2580ccf4d6b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -433,9 +433,9 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
for (id = 0; id < DMC_FW_MAX; id++) {
for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) {
- intel_uncore_write_fw(_priv->uncore,
-
DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i),
- dmc->dmc_info[id].payload[i]);
+ intel_de_write_fw(dev_priv,
+
DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i),
+ dmc->dmc_info[id].payload[i]);
}
}
--
2.34.1
[Intel-gfx] [PATCH 07/12] drm/i915/dp-aux: switch to intel_de_* register accessors in display code
Avoid direct uncore use in display code.
Cc: Maarten Lankhorst
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 29 +
1 file changed, 13 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 664bebdecea7..91c93c93e5fc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_trace.h"
+#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp_aux.h"
#include "intel_pps.h"
@@ -42,7 +43,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
u32 status;
bool done;
-#define C (((status = intel_uncore_read_notrace(>uncore, ch_ctl)) &
DP_AUX_CH_CTL_SEND_BUSY) == 0)
+#define C (((status = intel_de_read_notrace(i915, ch_ctl)) &
DP_AUX_CH_CTL_SEND_BUSY) == 0)
done = wait_event_timeout(i915->display.gmbus.wait_queue, C,
msecs_to_jiffies_timeout(timeout_ms));
@@ -191,7 +192,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *i915 =
to_i915(dig_port->base.base.dev);
- struct intel_uncore *uncore = >uncore;
enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
bool is_tc_port = intel_phy_is_tc(i915, phy);
i915_reg_t ch_ctl, ch_data[5];
@@ -235,7 +235,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
/* Try to wait for any previous AUX channel activity */
for (try = 0; try < 3; try++) {
- status = intel_uncore_read_notrace(uncore, ch_ctl);
+ status = intel_de_read_notrace(i915, ch_ctl);
if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
break;
msleep(1);
@@ -244,7 +244,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
if (try == 3) {
- const u32 status = intel_uncore_read(uncore, ch_ctl);
+ const u32 status = intel_de_read(i915, ch_ctl);
if (status != intel_dp->aux_busy_last_status) {
drm_WARN(>drm, 1,
@@ -274,23 +274,20 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
for (try = 0; try < 5; try++) {
/* Load the send data into the aux channel data
registers */
for (i = 0; i < send_bytes; i += 4)
- intel_uncore_write(uncore,
- ch_data[i >> 2],
- intel_dp_aux_pack(send + i,
-send_bytes
- i));
+ intel_de_write(i915, ch_data[i >> 2],
+ intel_dp_aux_pack(send + i,
+send_bytes -
i));
/* Send the command and wait for it to complete */
- intel_uncore_write(uncore, ch_ctl, send_ctl);
+ intel_de_write(i915, ch_ctl, send_ctl);
status = intel_dp_aux_wait_done(intel_dp);
/* Clear done status and any errors */
- intel_uncore_write(uncore,
- ch_ctl,
- status |
- DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_RECEIVE_ERROR);
+ intel_de_write(i915, ch_ctl,
+ status | DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ DP_AUX_CH_CTL_RECEIVE_ERROR);
/*
* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
@@ -361,7 +358,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
recv_bytes = recv_size;
for (i = 0; i < recv_bytes; i += 4)
- intel_dp_aux_unpack(intel_uncore_read(uncore, ch_data[i >> 2]),
+ intel_dp_aux_unpack(intel_de_read(i915, ch_data[i >> 2]),
recv + i, recv_bytes - i);
ret = recv_bytes;
--
2.34.1
[Intel-gfx] [PATCH 11/12] drm/i915/tc: switch to intel_de_* register accessors in display code
Avoid direct uncore use in display code.
Cc: Maarten Lankhorst
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_tc.c | 55 -
1 file changed, 18 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index 70624b4b2d38..f45328712bff 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "i915_reg.h"
+#include "intel_de.h"
#include "intel_display.h"
#include "intel_display_power_map.h"
#include "intel_display_types.h"
@@ -120,11 +121,9 @@ assert_tc_cold_blocked(struct intel_digital_port *dig_port)
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct intel_uncore *uncore = >uncore;
u32 lane_mask;
- lane_mask = intel_uncore_read(uncore,
- PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
+ lane_mask = intel_de_read(i915,
PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
drm_WARN_ON(>drm, lane_mask == 0x);
assert_tc_cold_blocked(dig_port);
@@ -136,11 +135,9 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port
*dig_port)
u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct intel_uncore *uncore = >uncore;
u32 pin_mask;
- pin_mask = intel_uncore_read(uncore,
-PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
+ pin_mask = intel_de_read(i915, PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
drm_WARN_ON(>drm, pin_mask == 0x);
assert_tc_cold_blocked(dig_port);
@@ -186,7 +183,6 @@ void intel_tc_port_set_fia_lane_count(struct
intel_digital_port *dig_port,
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
- struct intel_uncore *uncore = >uncore;
u32 val;
drm_WARN_ON(>drm,
@@ -194,8 +190,7 @@ void intel_tc_port_set_fia_lane_count(struct
intel_digital_port *dig_port,
assert_tc_cold_blocked(dig_port);
- val = intel_uncore_read(uncore,
- PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
+ val = intel_de_read(i915, PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx);
switch (required_lanes) {
@@ -216,8 +211,7 @@ void intel_tc_port_set_fia_lane_count(struct
intel_digital_port *dig_port,
MISSING_CASE(required_lanes);
}
- intel_uncore_write(uncore,
- PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
+ intel_de_write(i915, PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
}
static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
@@ -246,13 +240,11 @@ static void tc_port_fixup_legacy_flag(struct
intel_digital_port *dig_port,
static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct intel_uncore *uncore = >uncore;
u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
u32 mask = 0;
u32 val;
- val = intel_uncore_read(uncore,
- PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
+ val = intel_de_read(i915, PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
if (val == 0x) {
drm_dbg_kms(>drm,
@@ -266,7 +258,7 @@ static u32 icl_tc_port_live_status_mask(struct
intel_digital_port *dig_port)
if (val & TC_LIVE_STATE_TC(dig_port->tc_phy_fia_idx))
mask |= BIT(TC_PORT_DP_ALT);
- if (intel_uncore_read(uncore, SDEISR) & isr_bit)
+ if (intel_de_read(i915, SDEISR) & isr_bit)
mask |= BIT(TC_PORT_LEGACY);
/* The sink can be connected only in a single mode. */
@@ -281,7 +273,6 @@ static u32 adl_tc_port_live_status_mask(struct
intel_digital_port *dig_port)
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
- struct intel_uncore *uncore = >uncore;
u32 val, mask = 0;
/*
@@ -289,13 +280,13 @@ static u32 adl_tc_port_live_status_mask(struct
intel_digital_port *dig_port)
* registers in IOM. Note that this doesn't apply to PHY and FIA
* registers.
*/
- val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port));
+ val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT)
mask |=
[Intel-gfx] [PATCH 05/12] drm/i915/power: switch to intel_de_* register accessors in display code
Avoid direct uncore use in display code.
Cc: Maarten Lankhorst
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3adba64937de..1a23ecd4623a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1673,7 +1673,7 @@ static void icl_display_core_init(struct drm_i915_private
*dev_priv,
if (DISPLAY_VER(dev_priv) >= 12) {
val = DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR;
- intel_uncore_rmw(_priv->uncore, GEN11_CHICKEN_DCPR_2, 0,
val);
+ intel_de_rmw(dev_priv, GEN11_CHICKEN_DCPR_2, 0, val);
}
/* Wa_14011503030:xelpd */
--
2.34.1
[Intel-gfx] [PATCH 04/12] drm/i915/crt: switch to intel_de_* register accessors in display code
Avoid direct uncore use in display code.
Cc: Maarten Lankhorst
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_crt.c | 42 +++-
1 file changed, 19 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index ed94ba5c0302..7267ffc7f539 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -682,7 +682,6 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
{
struct drm_device *dev = crt->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = _priv->uncore;
u32 save_bclrpat;
u32 save_vtotal;
u32 vtotal, vactive;
@@ -694,9 +693,9 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
drm_dbg_kms(_priv->drm, "starting load-detect on CRT\n");
- save_bclrpat = intel_uncore_read(uncore, BCLRPAT(pipe));
- save_vtotal = intel_uncore_read(uncore, VTOTAL(pipe));
- vblank = intel_uncore_read(uncore, VBLANK(pipe));
+ save_bclrpat = intel_de_read(dev_priv, BCLRPAT(pipe));
+ save_vtotal = intel_de_read(dev_priv, VTOTAL(pipe));
+ vblank = intel_de_read(dev_priv, VBLANK(pipe));
vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
vactive = (save_vtotal & 0x7ff) + 1;
@@ -705,23 +704,23 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
vblank_end = ((vblank >> 16) & 0xfff) + 1;
/* Set the border color to purple. */
- intel_uncore_write(uncore, BCLRPAT(pipe), 0x500050);
+ intel_de_write(dev_priv, BCLRPAT(pipe), 0x500050);
if (DISPLAY_VER(dev_priv) != 2) {
- u32 pipeconf = intel_uncore_read(uncore, PIPECONF(pipe));
- intel_uncore_write(uncore,
- PIPECONF(pipe),
- pipeconf | PIPECONF_FORCE_BORDER);
- intel_uncore_posting_read(uncore, PIPECONF(pipe));
+ u32 pipeconf = intel_de_read(dev_priv, PIPECONF(pipe));
+
+ intel_de_write(dev_priv, PIPECONF(pipe),
+ pipeconf | PIPECONF_FORCE_BORDER);
+ intel_de_posting_read(dev_priv, PIPECONF(pipe));
/* Wait for next Vblank to substitue
* border color for Color info */
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv,
pipe));
- st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
+ st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
status = ((st00 & (1 << 4)) != 0) ?
connector_status_connected :
connector_status_disconnected;
- intel_uncore_write(uncore, PIPECONF(pipe), pipeconf);
+ intel_de_write(dev_priv, PIPECONF(pipe), pipeconf);
} else {
bool restore_vblank = false;
int count, detect;
@@ -735,10 +734,8 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
u32 vsync_start = (vsync & 0x) + 1;
vblank_start = vsync_start;
- intel_uncore_write(uncore,
- VBLANK(pipe),
- (vblank_start - 1) |
- ((vblank_end - 1) << 16));
+ intel_de_write(dev_priv, VBLANK(pipe),
+ (vblank_start - 1) | ((vblank_end - 1)
<< 16));
restore_vblank = true;
}
/* sample in the vertical border, selecting the larger one */
@@ -750,10 +747,9 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
/*
* Wait for the border to be displayed
*/
- while (intel_uncore_read(uncore, PIPEDSL(pipe)) >= vactive)
+ while (intel_de_read(dev_priv, PIPEDSL(pipe)) >= vactive)
;
- while ((dsl = intel_uncore_read(uncore, PIPEDSL(pipe))) <=
- vsample)
+ while ((dsl = intel_de_read(dev_priv, PIPEDSL(pipe))) <=
vsample)
;
/*
* Watch ST00 for an entire scanline
@@ -763,14 +759,14 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
do {
count++;
/* Read the ST00 VGA status register */
- st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
+ st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
if (st00 & (1 << 4))
detect++;
- } while ((intel_uncore_read(uncore, PIPEDSL(pipe)) == dsl));
+ } while ((intel_de_read(dev_priv, PIPEDSL(pipe)) == dsl));
/* restore vblank if
[Intel-gfx] [PATCH 01/12] drm/i915/de: Add more macros to remove all direct calls to uncore
From: Maarten Lankhorst
Add more de helpers to be able to avoid direct calls to uncore.
v2 by Jani:
- drop pcode stuff for now
- rename intel_de_write_samevalue -> intel_de_rewrite_fw
Signed-off-by: Maarten Lankhorst
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_de.h | 43 +
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_de.h
b/drivers/gpu/drm/i915/display/intel_de.h
index 9c104f65e4c8..7fd74eda89fc 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -16,6 +16,12 @@ intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
return intel_uncore_read(>uncore, reg);
}
+static inline u8
+intel_de_read8(struct drm_i915_private *i915, i915_reg_t reg)
+{
+ return intel_uncore_read8(>uncore, reg);
+}
+
static inline void
intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
{
@@ -41,6 +47,23 @@ intel_de_wait_for_register(struct drm_i915_private *i915,
i915_reg_t reg,
return intel_wait_for_register(>uncore, reg, mask, value,
timeout);
}
+static inline int
+intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg,
+ u32 mask, u32 value, unsigned int timeout)
+{
+ return intel_wait_for_register_fw(>uncore, reg, mask, value,
timeout);
+}
+
+static inline int
+__intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
+u32 mask, u32 value,
+unsigned int fast_timeout_us,
+unsigned int slow_timeout_ms, u32 *out_value)
+{
+ return __intel_wait_for_register(>uncore, reg, mask, value,
+fast_timeout_us, slow_timeout_ms,
out_value);
+}
+
static inline int
intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
u32 mask, unsigned int timeout)
@@ -81,4 +104,24 @@ intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t
reg, u32 val)
intel_uncore_write_fw(>uncore, reg, val);
}
+static inline void
+intel_de_rewrite_fw(struct drm_i915_private *i915, i915_reg_t reg)
+{
+ spin_lock_irq(>uncore.lock);
+ intel_de_write_fw(i915, reg, intel_de_read_fw(i915, reg));
+ spin_unlock_irq(>uncore.lock);
+}
+
+static inline u32
+intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t reg)
+{
+ return intel_uncore_read_notrace(>uncore, reg);
+}
+
+static inline void
+intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
+{
+ intel_uncore_write_notrace(>uncore, reg, val);
+}
+
#endif /* __INTEL_DE_H__ */
--
2.34.1
[Intel-gfx] [PATCH 03/12] drm/i915/crt: drop a bunch of unnecessary register variables
There's no need to save the register offsets. Drop the variables.
Cc: Maarten Lankhorst
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_crt.c | 39 +---
1 file changed, 15 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index 797ad9489f7e..ed94ba5c0302 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -689,23 +689,14 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
u32 vsample;
u32 vblank, vblank_start, vblank_end;
u32 dsl;
- i915_reg_t bclrpat_reg, vtotal_reg,
- vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
u8 st00;
enum drm_connector_status status;
drm_dbg_kms(_priv->drm, "starting load-detect on CRT\n");
- bclrpat_reg = BCLRPAT(pipe);
- vtotal_reg = VTOTAL(pipe);
- vblank_reg = VBLANK(pipe);
- vsync_reg = VSYNC(pipe);
- pipeconf_reg = PIPECONF(pipe);
- pipe_dsl_reg = PIPEDSL(pipe);
-
- save_bclrpat = intel_uncore_read(uncore, bclrpat_reg);
- save_vtotal = intel_uncore_read(uncore, vtotal_reg);
- vblank = intel_uncore_read(uncore, vblank_reg);
+ save_bclrpat = intel_uncore_read(uncore, BCLRPAT(pipe));
+ save_vtotal = intel_uncore_read(uncore, VTOTAL(pipe));
+ vblank = intel_uncore_read(uncore, VBLANK(pipe));
vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
vactive = (save_vtotal & 0x7ff) + 1;
@@ -714,14 +705,14 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
vblank_end = ((vblank >> 16) & 0xfff) + 1;
/* Set the border color to purple. */
- intel_uncore_write(uncore, bclrpat_reg, 0x500050);
+ intel_uncore_write(uncore, BCLRPAT(pipe), 0x500050);
if (DISPLAY_VER(dev_priv) != 2) {
- u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg);
+ u32 pipeconf = intel_uncore_read(uncore, PIPECONF(pipe));
intel_uncore_write(uncore,
- pipeconf_reg,
+ PIPECONF(pipe),
pipeconf | PIPECONF_FORCE_BORDER);
- intel_uncore_posting_read(uncore, pipeconf_reg);
+ intel_uncore_posting_read(uncore, PIPECONF(pipe));
/* Wait for next Vblank to substitue
* border color for Color info */
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv,
pipe));
@@ -730,7 +721,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
connector_status_connected :
connector_status_disconnected;
- intel_uncore_write(uncore, pipeconf_reg, pipeconf);
+ intel_uncore_write(uncore, PIPECONF(pipe), pipeconf);
} else {
bool restore_vblank = false;
int count, detect;
@@ -740,12 +731,12 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
* Yes, this will flicker
*/
if (vblank_start <= vactive && vblank_end >= vtotal) {
- u32 vsync = intel_de_read(dev_priv, vsync_reg);
+ u32 vsync = intel_de_read(dev_priv, VSYNC(pipe));
u32 vsync_start = (vsync & 0x) + 1;
vblank_start = vsync_start;
intel_uncore_write(uncore,
- vblank_reg,
+ VBLANK(pipe),
(vblank_start - 1) |
((vblank_end - 1) << 16));
restore_vblank = true;
@@ -759,9 +750,9 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
/*
* Wait for the border to be displayed
*/
- while (intel_uncore_read(uncore, pipe_dsl_reg) >= vactive)
+ while (intel_uncore_read(uncore, PIPEDSL(pipe)) >= vactive)
;
- while ((dsl = intel_uncore_read(uncore, pipe_dsl_reg)) <=
+ while ((dsl = intel_uncore_read(uncore, PIPEDSL(pipe))) <=
vsample)
;
/*
@@ -775,11 +766,11 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
if (st00 & (1 << 4))
detect++;
- } while ((intel_uncore_read(uncore, pipe_dsl_reg) == dsl));
+ } while ((intel_uncore_read(uncore, PIPEDSL(pipe)) == dsl));
/* restore vblank if necessary */
if (restore_vblank)
- intel_uncore_write(uncore, vblank_reg, vblank);
+ intel_uncore_write(uncore,
[Intel-gfx] [PATCH 02/12] drm/i915/de: return the old register value from intel_de_rmw()
A similar thing was added in intel_uncore_rmw(). Make it available for
display too.
Cc: Maarten Lankhorst
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_de.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_de.h
b/drivers/gpu/drm/i915/display/intel_de.h
index 7fd74eda89fc..d8f046af5bdf 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -34,10 +34,10 @@ intel_de_write(struct drm_i915_private *i915, i915_reg_t
reg, u32 val)
intel_uncore_write(>uncore, reg, val);
}
-static inline void
+static inline u32
intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
{
- intel_uncore_rmw(>uncore, reg, clear, set);
+ return intel_uncore_rmw(>uncore, reg, clear, set);
}
static inline int
--
2.34.1
[Intel-gfx] [PATCH 00/12] drm/i915/display: switch to intel_de_* register accessors
Based on earlier work by Maarten, switch to intel_de_* register accessors in display for display registers, and avoid direct i915->uncore access in general. For now, leave the non-display registers be, as well as pcode. Jani Nikula (11): drm/i915/de: return the old register value from intel_de_rmw() drm/i915/crt: drop a bunch of unnecessary register variables drm/i915/crt: switch to intel_de_* register accessors in display code drm/i915/power: switch to intel_de_* register accessors in display code drm/i915/dmc: switch to intel_de_* register accessors in display code drm/i915/dp-aux: switch to intel_de_* register accessors in display code drm/i915/gmbus: switch to intel_de_* register accessors in display code drm/i915/wm: switch to intel_de_* register accessors in display code drm/i915/snps: switch to intel_de_* register accessors in display code drm/i915/tc: switch to intel_de_* register accessors in display code drm/i915/fbc: switch to intel_de_* register accessors in display code Maarten Lankhorst (1): drm/i915/de: Add more macros to remove all direct calls to uncore drivers/gpu/drm/i915/display/intel_crt.c | 53 +++--- drivers/gpu/drm/i915/display/intel_de.h | 47 +++- .../drm/i915/display/intel_display_power.c| 2 +- drivers/gpu/drm/i915/display/intel_dmc.c | 6 +- drivers/gpu/drm/i915/display/intel_dp_aux.c | 29 +- drivers/gpu/drm/i915/display/intel_fbc.c | 10 +--- drivers/gpu/drm/i915/display/intel_gmbus.c| 46 ++-- drivers/gpu/drm/i915/display/intel_snps_phy.c | 15 +++-- drivers/gpu/drm/i915/display/intel_tc.c | 55 ++- drivers/gpu/drm/i915/display/skl_watermark.c | 42 ++ 10 files changed, 144 insertions(+), 161 deletions(-) -- 2.34.1
Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
On 23.11.2022 02:25, John Harrison wrote:
> On 11/22/2022 09:54, Michal Wajdeczko wrote:
>> On 18.11.2022 02:58, john.c.harri...@intel.com wrote:
>>> From: John Harrison
>>>
>>> Re-work the existing GuC CT printers and extend as required to match
>>> the new wrapping scheme.
>>>
>>> Signed-off-by: John Harrison
>>> ---
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++---
>>> 1 file changed, 113 insertions(+), 109 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> index 2b22065e87bf9..9d404fb377637 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> @@ -18,31 +18,49 @@ static inline struct intel_guc *ct_to_guc(struct
>>> intel_guc_ct *ct)
>>> return container_of(ct, struct intel_guc, ct);
>>> }
>>> -static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
>>> -{
>>> - return guc_to_gt(ct_to_guc(ct));
>>> -}
>>> -
>>> static inline struct drm_i915_private *ct_to_i915(struct
>>> intel_guc_ct *ct)
>>> {
>>> - return ct_to_gt(ct)->i915;
>>> -}
>>> + struct intel_guc *guc = ct_to_guc(ct);
>>> + struct intel_gt *gt = guc_to_gt(guc);
>>> -static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
>>> -{
>>> - return _to_i915(ct)->drm;
>>> + return gt->i915;
>>> }
>>> -#define CT_ERROR(_ct, _fmt, ...) \
>>> - drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>> +#define ct_err(_ct, _fmt, ...) \
>>> + guc_err(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>> +
>>> +#define ct_warn(_ct, _fmt, ...) \
>>> + guc_warn(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>> +
>>> +#define ct_notice(_ct, _fmt, ...) \
>>> + guc_notice(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>> +
>>> +#define ct_info(_ct, _fmt, ...) \
>>> + guc_info(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>> +
>>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>> -#define CT_DEBUG(_ct, _fmt, ...) \
>>> - drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>> +#define ct_dbg(_ct, _fmt, ...) \
>>> + guc_dbg(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>> #else
>>> -#define CT_DEBUG(...) do { } while (0)
>>> +#define ct_dbg(...) do { } while (0)
>>> #endif
>>> -#define CT_PROBE_ERROR(_ct, _fmt, ...) \
>>> - i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
>>> +
>>> +#define ct_probe_error(_ct, _fmt, ...) \
>>> + do { \
>>> + if (i915_error_injected()) \
>>> + ct_dbg(_ct, _fmt, ##__VA_ARGS__); \
>>> + else \
>>> + ct_err(_ct, _fmt, ##__VA_ARGS__); \
>>> + } while (0)
>> guc_probe_error ?
>>
>>> +
>>> +#define ct_WARN_ON(_ct, _condition) \
>>> + ct_WARN(_ct, _condition, "%s", "ct_WARN_ON("
>>> __stringify(_condition) ")")
>>> +
>>> +#define ct_WARN(_ct, _condition, _fmt, ...) \
>>> + guc_WARN(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
>>> +
>>> +#define ct_WARN_ONCE(_ct, _condition, _fmt, ...) \
>>> + guc_WARN_ONCE(ct_to_guc(_ct), _condition, "CT " _fmt,
>>> ##__VA_ARGS__)
>>> /**
>>> * DOC: CTB Blob
>>> @@ -170,7 +188,7 @@ static int ct_control_enable(struct intel_guc_ct
>>> *ct, bool enable)
>>> err = guc_action_control_ctb(ct_to_guc(ct), enable ?
>>> GUC_CTB_CONTROL_ENABLE :
>>> GUC_CTB_CONTROL_DISABLE);
>>> if (unlikely(err))
>>> - CT_PROBE_ERROR(ct, "Failed to control/%s CTB (%pe)\n",
>>> + ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
>>> str_enable_disable(enable), ERR_PTR(err));
>> btw, shouldn't we change all messages to start with lowercase ?
>>
>> was:
>> "CT0: Failed to control/%s CTB (%pe)"
>> is:
>> "GT0: GuC CT Failed to control/%s CTB (%pe)"
>>
>> unless we keep colon (as suggested by Tvrtko) as then:
>>
>> "GT0: GuC CT: Failed to control/%s CTB (%pe)"
> Blanket added the colon makes it messy when a string actually wants to
> start with the prefix. The rule I've been using is lower case word when
> the prefix was part of the string, upper case word when the prefix is
Hmm, I'm not sure that we should attempt to have such a flexible rule as
we shouldn't rely too much on actual format of the prefix as it could be
changed any time. All we should know about final log message is that it
_will_ properly identify the "GT" or "GuC" that this log is related to.
So I would suggest to be just consistent and probably always start with
upper case, as that seems to be mostly used in kernel error logs, and
just make sure that any prefix will honor that (by including colon, or
braces), so this will always work like:
"[drm] *ERROR* GT0: Failed to foo (-EIO)"
"[drm] *ERROR* GT0: GUC: Failed to foo (-EIO)"
"[drm] *ERROR* GT0: GUC: CT: Failed to foo (-EIO)"
or
"[drm] *ERROR* GT0: Failed to foo (-EIO)"
"[drm] *ERROR* GT0: [GUC] Failed to foo (-EIO)"
"[drm] *ERROR* GT0: [GUC] CT: Failed to foo (-EIO)"
and even for:
"[drm] *ERROR* GT(root) Failed to
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/2] drm/i915/dg2: Introduce Wa_18018764978
== Series Details == Series: series starting with [v4,1/2] drm/i915/dg2: Introduce Wa_18018764978 URL : https://patchwork.freedesktop.org/series/111270/ State : success == Summary == CI Bug Log - changes from CI_DRM_12424 -> Patchwork_111270v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/index.html Participating hosts (37 -> 37) -- Additional (2): fi-icl-u2 bat-dg1-6 Missing(2): fi-ctg-p8600 fi-ilk-m540 Known issues Here are the changes found in Patchwork_111270v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - fi-icl-u2: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-icl-u2/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-icl-u2: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@random-engines: - fi-icl-u2: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html * igt@gem_mmap@basic: - bat-dg1-6: NOTRUN -> [SKIP][4] ([i915#4083]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][5] ([i915#4079]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-6: NOTRUN -> [SKIP][7] ([i915#7561]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#6621]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@i915_pm_...@basic-api.html * igt@i915_suspend@basic-s2idle-without-i915: - fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][9] ([i915#146]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-bdw-gvtdvm/igt@i915_susp...@basic-s2idle-without-i915.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: [PASS][10] -> [INCOMPLETE][11] ([i915#4817]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12424/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-6: NOTRUN -> [SKIP][12] ([i915#4215]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@tile-pitch-mismatch: - bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#4212]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html * igt@kms_chamelium@common-hpd-after-suspend: - bat-dg1-5: NOTRUN -> [SKIP][14] ([fdo#111827]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-5/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-crc-fast: - bat-dg1-6: NOTRUN -> [SKIP][15] ([fdo#111827]) +8 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][16] ([fdo#111827]) +8 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html - fi-bdw-gvtdvm: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +7 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-bdw-gvtdvm/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - fi-icl-u2: NOTRUN -> [SKIP][18] ([i915#4103]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html - bat-dg1-6: NOTRUN -> [SKIP][19] ([i915#4103] / [i915#4213]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html *
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: remove some limited use register access wrappers
== Series Details ==
Series: drm/i915/gt: remove some limited use register access wrappers
URL : https://patchwork.freedesktop.org/series/111265/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12424 -> Patchwork_111265v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/index.html
Participating hosts (37 -> 37)
--
Additional (2): fi-icl-u2 bat-dg1-6
Missing(2): fi-ctg-p8600 fi-ilk-m540
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111265v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@migrate:
- {bat-rpls-2}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12424/bat-rpls-2/igt@i915_selftest@l...@migrate.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/bat-rpls-2/igt@i915_selftest@l...@migrate.html
Known issues
Here are the changes found in Patchwork_111265v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- fi-icl-u2: NOTRUN -> [SKIP][3] ([i915#7456])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/fi-icl-u2/igt@debugfs_t...@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][4] ([i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html
* igt@gem_mmap@basic:
- bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#4083])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/bat-dg1-6/igt@gem_m...@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][7] ([i915#4079]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#4077]) +2 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6: NOTRUN -> [SKIP][9] ([i915#7561])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-6: NOTRUN -> [SKIP][10] ([i915#6621])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/bat-dg1-6/igt@i915_pm_...@basic-api.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][11] ([i915#146])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/fi-bdw-gvtdvm/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [PASS][12] -> [INCOMPLETE][13] ([i915#4817])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12424/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6: NOTRUN -> [SKIP][14] ([i915#4215])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#4212]) +7 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html
* igt@kms_chamelium@common-hpd-after-suspend:
- bat-dg1-5: NOTRUN -> [SKIP][16] ([fdo#111827])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/bat-dg1-5/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-crc-fast:
- bat-dg1-6: NOTRUN -> [SKIP][17] ([fdo#111827]) +8 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][18] ([fdo#111827]) +8 similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111265v1/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
- fi-bdw-gvtdvm: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +7
similar issues
[19]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/fbc: Disable FBC when VT-d is enabled
== Series Details == Series: drm/i915/fbc: Disable FBC when VT-d is enabled URL : https://patchwork.freedesktop.org/series/111239/ State : success == Summary == CI Bug Log - changes from CI_DRM_12419_full -> Patchwork_111239v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts New tests - New tests have been introduced between CI_DRM_12419_full and Patchwork_111239v1_full: ### New IGT tests (1) ### * igt@i915_pm_rpm: - Statuses : - Exec time: [None] s Known issues Here are the changes found in Patchwork_111239v1_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-snb: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [FAIL][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#4338]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb7/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb7/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb7/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb7/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb7/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb7/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb5/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb5/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb5/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb5/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb5/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb4/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb4/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb2/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb2/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb2/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-snb2/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111239v1/shard-snb7/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111239v1/shard-snb7/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111239v1/shard-snb7/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111239v1/shard-snb7/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111239v1/shard-snb7/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111239v1/shard-snb7/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111239v1/shard-snb5/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111239v1/shard-snb5/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111239v1/shard-snb5/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111239v1/shard-snb5/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111239v1/shard-snb5/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111239v1/shard-snb5/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111239v1/shard-snb5/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111239v1/shard-snb4/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111239v1/shard-snb4/boot.html [41]:
Re: [Intel-gfx] [PATCH v2] drm/i915/perf: Do not parse context image for HSW
On Tue, Nov 22, 2022 at 07:25:36PM -0800, Dixit, Ashutosh wrote:
On Tue, 22 Nov 2022 18:07:00 -0800, Umesh Nerlige Ramappa wrote:
Hi Umesh,
An earlier commit introduced a mechanism to parse the context image to
find the OA context control offset. This resulted in an NPD on haswell
when gem_context was passed into i915_perf_open_ioctl params. Haswell
does not support logical ring contexts, so ensure that the context image
is parsed only for platforms with logical ring contexts and also
validate lrc_reg_state.
v2: Fix build failure
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7432
Fixes: a5c3a3cbf029 ("drm/i915/perf: Determine gen12 oa ctx offset at runtime")
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 00e09bb18b13..dbd785974f20 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1383,6 +1383,9 @@ static u32 oa_context_image_offset(struct intel_context
*ce, u32 reg)
u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
u32 *state = ce->lrc_reg_state;
+ if (drm_WARN_ON(>engine->i915->drm, state == NULL))
+ return U32_MAX;
+
So if we didn't add the HAS_LOGICAL_RING_CONTEXTS check below state would
be NULL correct? I couldn't figure out how it is NULL on HSW looking at the
code (with the context image pin/unpin).
Ref: intel_engines_init()
Haswell is using ring submission. While it does have a context image or
ce->state, there is no lrc state offset here. I think lrc is an execlist
concept (used only for execlist and guc submission).
/*
@@ -1447,7 +1450,8 @@ static int oa_get_render_ctx_id(struct i915_perf_stream
*stream)
if (IS_ERR(ce))
return PTR_ERR(ce);
- if (engine_supports_mi_query(stream->engine)) {
+ if (engine_supports_mi_query(stream->engine) &&
+ HAS_LOGICAL_RING_CONTEXTS(stream->perf->i915)) {
This check looks fine since we seem to be looking inside ce->lrc_reg_state
for oactxctrl.
The earlier code also does not define perf->ctx_oactxctrl_offset for
haswell. Ref: i915_perf_init().
Overall looks fine so this is:
Reviewed-by: Ashutosh Dixit
Thanks,
Umesh
/*
* We are enabling perf query here. If we don't find the context
* offset here, just return an error.
--
2.36.1
[Intel-gfx] [PATCH v3 2/5] drm/i915/huc: Add HuC specific debug print wrappers
From: John Harrison
Create a set of HuC printers and start using them.
v2: Minor tweaks (review feedback from MichalW).
Split definitions into separate header (review feedback from Jani).
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 32
drivers/gpu/drm/i915/gt/uc/intel_huc_print.h | 30 ++
2 files changed, 43 insertions(+), 19 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_print.h
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index be855811d85df..7656c6c423154 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -8,6 +8,7 @@
#include "gt/intel_gt.h"
#include "intel_guc_reg.h"
#include "intel_huc.h"
+#include "intel_huc_print.h"
#include "i915_drv.h"
#include
@@ -107,11 +108,9 @@ static enum hrtimer_restart
huc_delayed_load_timer_callback(struct hrtimer *hrti
if (!intel_huc_is_authenticated(huc)) {
if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_GSC)
- drm_notice(_to_gt(huc)->i915->drm,
- "timed out waiting for MEI GSC init to load
HuC\n");
+ huc_notice(huc, "Timed out waiting for MEI GSC init to
load FW\n");
else if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_PXP)
- drm_notice(_to_gt(huc)->i915->drm,
- "timed out waiting for MEI PXP init to load
HuC\n");
+ huc_notice(huc, "Timed out waiting for MEI PXP init to
load FW\n");
else
MISSING_CASE(huc->delayed_load.status);
@@ -174,8 +173,7 @@ static int gsc_notifier(struct notifier_block *nb, unsigned
long action, void *d
case BUS_NOTIFY_DRIVER_NOT_BOUND: /* mei driver fails to be bound */
case BUS_NOTIFY_UNBIND_DRIVER: /* mei driver about to be unbound */
- drm_info(_to_gt(huc)->i915->drm,
-"mei driver not bound, disabling HuC load\n");
+ huc_info(huc, "- mei driver not bound, disabling HuC load\n");
gsc_init_error(huc);
break;
}
@@ -193,8 +191,7 @@ void intel_huc_register_gsc_notifier(struct intel_huc *huc,
struct bus_type *bus
huc->delayed_load.nb.notifier_call = gsc_notifier;
ret = bus_register_notifier(bus, >delayed_load.nb);
if (ret) {
- drm_err(_to_gt(huc)->i915->drm,
- "failed to register GSC notifier\n");
+ huc_err(huc, "Failed to register GSC notifier\n");
huc->delayed_load.nb.notifier_call = NULL;
gsc_init_error(huc);
}
@@ -284,8 +281,7 @@ static int check_huc_loading_mode(struct intel_huc *huc)
GSC_LOADS_HUC;
if (fw_needs_gsc != hw_uses_gsc) {
- drm_err(>i915->drm,
- "mismatch between HuC FW (%s) and HW (%s) load modes\n",
+ huc_err(huc, "Mismatch between FW (%s) and HW (%s) load
modes\n",
HUC_LOAD_MODE_STRING(fw_needs_gsc),
HUC_LOAD_MODE_STRING(hw_uses_gsc));
return -ENOEXEC;
@@ -294,19 +290,17 @@ static int check_huc_loading_mode(struct intel_huc *huc)
/* make sure we can access the GSC via the mei driver if we need it */
if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) &&
IS_ENABLED(CONFIG_INTEL_MEI_GSC)) &&
fw_needs_gsc) {
- drm_info(>i915->drm,
-"Can't load HuC due to missing MEI modules\n");
+ huc_info(huc, "Can't load due to missing MEI modules\n");
return -EIO;
}
- drm_dbg(>i915->drm, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
+ huc_dbg(huc, "load by GSC: %s\n", str_yes_no(fw_needs_gsc));
return 0;
}
int intel_huc_init(struct intel_huc *huc)
{
- struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
int err;
err = check_huc_loading_mode(huc);
@@ -323,7 +317,7 @@ int intel_huc_init(struct intel_huc *huc)
out:
intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_INIT_FAIL);
- drm_info(>drm, "HuC init failed with %d\n", err);
+ huc_info(huc, "init failed with %d\n", err);
return err;
}
@@ -366,13 +360,13 @@ int intel_huc_wait_for_auth_complete(struct intel_huc
*huc)
delayed_huc_load_complete(huc);
if (ret) {
- drm_err(>i915->drm, "HuC: Firmware not verified %d\n", ret);
+ huc_err(huc, "firmware not verified %d\n", ret);
intel_uc_fw_change_status(>fw,
INTEL_UC_FIRMWARE_LOAD_FAIL);
return ret;
}
intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_RUNNING);
- drm_info(>i915->drm, "HuC authenticated\n");
+ huc_info(huc, "authenticated\n");
[Intel-gfx] [PATCH v3 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
From: John Harrison
Re-work the existing GuC CT printers and extend as required to match
the new wrapping scheme.
v2: Improve probe_error definition (review feedback from MichalW).
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 218 +++---
1 file changed, 109 insertions(+), 109 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 2b22065e87bf9..8800fe3c96caf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -11,6 +11,7 @@
#include "i915_drv.h"
#include "intel_guc_ct.h"
+#include "intel_guc_print.h"
#include "gt/intel_gt.h"
static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
@@ -18,31 +19,44 @@ static inline struct intel_guc *ct_to_guc(struct
intel_guc_ct *ct)
return container_of(ct, struct intel_guc, ct);
}
-static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
-{
- return guc_to_gt(ct_to_guc(ct));
-}
-
static inline struct drm_i915_private *ct_to_i915(struct intel_guc_ct *ct)
{
- return ct_to_gt(ct)->i915;
-}
+ struct intel_guc *guc = ct_to_guc(ct);
+ struct intel_gt *gt = guc_to_gt(guc);
-static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
-{
- return _to_i915(ct)->drm;
+ return gt->i915;
}
-#define CT_ERROR(_ct, _fmt, ...) \
- drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+#define ct_err(_ct, _fmt, ...) \
+ guc_err(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_warn(_ct, _fmt, ...) \
+ guc_warn(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_notice(_ct, _fmt, ...) \
+ guc_notice(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_info(_ct, _fmt, ...) \
+ guc_info(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
#ifdef CONFIG_DRM_I915_DEBUG_GUC
-#define CT_DEBUG(_ct, _fmt, ...) \
- drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+#define ct_dbg(_ct, _fmt, ...) \
+ guc_dbg(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
#else
-#define CT_DEBUG(...) do { } while (0)
+#define ct_dbg(...)do { } while (0)
#endif
-#define CT_PROBE_ERROR(_ct, _fmt, ...) \
- i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+
+#define ct_probe_error(_ct, _fmt, ...) \
+ guc_probe_error(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_WARN_ON(_ct, _condition) \
+ ct_WARN(_ct, _condition, "%s", "ct_WARN_ON(" __stringify(_condition)
")")
+
+#define ct_WARN(_ct, _condition, _fmt, ...) \
+ guc_WARN(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_WARN_ONCE(_ct, _condition, _fmt, ...) \
+ guc_WARN_ONCE(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
/**
* DOC: CTB Blob
@@ -170,7 +184,7 @@ static int ct_control_enable(struct intel_guc_ct *ct, bool
enable)
err = guc_action_control_ctb(ct_to_guc(ct), enable ?
GUC_CTB_CONTROL_ENABLE :
GUC_CTB_CONTROL_DISABLE);
if (unlikely(err))
- CT_PROBE_ERROR(ct, "Failed to control/%s CTB (%pe)\n",
+ ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
str_enable_disable(enable), ERR_PTR(err));
return err;
@@ -201,7 +215,7 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool
send,
size);
if (unlikely(err))
failed:
- CT_PROBE_ERROR(ct, "Failed to register %s buffer (%pe)\n",
+ ct_probe_error(ct, "Failed to register %s buffer (%pe)\n",
send ? "SEND" : "RECV", ERR_PTR(err));
return err;
@@ -235,21 +249,21 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE +
CTB_G2H_BUFFER_SIZE;
err = intel_guc_allocate_and_map_vma(guc, blob_size, >vma, );
if (unlikely(err)) {
- CT_PROBE_ERROR(ct, "Failed to allocate %u for CTB data (%pe)\n",
+ ct_probe_error(ct, "Failed to allocate %u for CTB data (%pe)\n",
blob_size, ERR_PTR(err));
return err;
}
- CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma),
blob_size);
+ ct_dbg(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma),
blob_size);
/* store pointers to desc and cmds for send ctb */
desc = blob;
cmds = blob + 2 * CTB_DESC_SIZE;
cmds_size = CTB_H2G_BUFFER_SIZE;
resv_space = 0;
- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
-ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
-resv_space);
+ ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
+ ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
+ resv_space);
guc_ct_buffer_init(>ctbs.send, desc, cmds,
[Intel-gfx] [PATCH v3 5/5] drm/i915/uc: Update the gt/uc code to use gt_err and friends
From: John Harrison
Use the new module oriented output message helpers where possible.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c| 110 +++
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 99 ++--
2 files changed, 102 insertions(+), 107 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 1d28286e6f066..f56fa0ff0f969 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -6,9 +6,11 @@
#include
#include "gt/intel_gt.h"
+#include "gt/intel_gt_print.h"
#include "gt/intel_reset.h"
#include "intel_guc.h"
#include "intel_guc_ads.h"
+#include "intel_guc_print.h"
#include "intel_guc_submission.h"
#include "gt/intel_rps.h"
#include "intel_uc.h"
@@ -65,29 +67,29 @@ static int __intel_uc_reset_hw(struct intel_uc *uc)
ret = intel_reset_guc(gt);
if (ret) {
- DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
+ gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
return ret;
}
guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
- WARN(!(guc_status & GS_MIA_IN_RESET),
-"GuC status: 0x%x, MIA core expected to be in reset\n",
-guc_status);
+ gt_WARN(gt, !(guc_status & GS_MIA_IN_RESET),
+ "GuC status: 0x%x, MIA core expected to be in reset\n",
+ guc_status);
return ret;
}
static void __confirm_options(struct intel_uc *uc)
{
- struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
+ struct intel_gt *gt = uc_to_gt(uc);
+ struct drm_i915_private *i915 = gt->i915;
- drm_dbg(>drm,
- "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
- i915->params.enable_guc,
- str_yes_no(intel_uc_wants_guc(uc)),
- str_yes_no(intel_uc_wants_guc_submission(uc)),
- str_yes_no(intel_uc_wants_huc(uc)),
- str_yes_no(intel_uc_wants_guc_slpc(uc)));
+ gt_dbg(gt, "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
+ i915->params.enable_guc,
+ str_yes_no(intel_uc_wants_guc(uc)),
+ str_yes_no(intel_uc_wants_guc_submission(uc)),
+ str_yes_no(intel_uc_wants_huc(uc)),
+ str_yes_no(intel_uc_wants_guc_slpc(uc)));
if (i915->params.enable_guc == 0) {
GEM_BUG_ON(intel_uc_wants_guc(uc));
@@ -98,26 +100,22 @@ static void __confirm_options(struct intel_uc *uc)
}
if (!intel_uc_supports_guc(uc))
- drm_info(>drm,
-"Incompatible option enable_guc=%d - %s\n",
-i915->params.enable_guc, "GuC is not supported!");
+ gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+ i915->params.enable_guc, "GuC is not supported!");
if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC &&
!intel_uc_supports_huc(uc))
- drm_info(>drm,
-"Incompatible option enable_guc=%d - %s\n",
-i915->params.enable_guc, "HuC is not supported!");
+ gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+ i915->params.enable_guc, "HuC is not supported!");
if (i915->params.enable_guc & ENABLE_GUC_SUBMISSION &&
!intel_uc_supports_guc_submission(uc))
- drm_info(>drm,
-"Incompatible option enable_guc=%d - %s\n",
-i915->params.enable_guc, "GuC submission is N/A");
+ gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+ i915->params.enable_guc, "GuC submission is N/A");
if (i915->params.enable_guc & ~ENABLE_GUC_MASK)
- drm_info(>drm,
-"Incompatible option enable_guc=%d - %s\n",
-i915->params.enable_guc, "undocumented flag");
+ gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+ i915->params.enable_guc, "undocumented flag");
}
void intel_uc_init_early(struct intel_uc *uc)
@@ -249,15 +247,13 @@ static int guc_enable_communication(struct intel_guc *guc)
intel_guc_ct_event_handler(>ct);
spin_unlock_irq(gt->irq_lock);
- drm_dbg(>drm, "GuC communication enabled\n");
+ guc_dbg(guc, "communication enabled\n");
return 0;
}
static void guc_disable_communication(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
-
/*
* Events generated during or after CT disable are logged by guc in
* via mmio. Make sure the register is clear before disabling CT since
@@ -277,7 +273,7 @@ static void guc_disable_communication(struct intel_guc *guc)
*/
guc_get_mmio_msg(guc);
- drm_dbg(>drm, "GuC
[Intel-gfx] [PATCH v3 1/5] drm/i915/gt: Start adding module oriented dmesg output
From: John Harrison
When trying to analyse bug reports from CI, customers, etc. it can be
difficult to work out exactly what is happening on which GT in a
multi-GT system. So add GT oriented debug/error message wrappers. If
used instead of the drm_ equivalents, you get the same output but with
a GT# prefix on it.
v2: Go back to using lower case names (combined review feedback).
Convert intel_gt.c as a first step.
v3: Add gt_err_ratelimited() as well, undo one conversation that might
not have a GT pointer in some scenarios (review feedback from Michal W).
Split definitions into separate header (review feedback from Jani).
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_gt.c | 96
drivers/gpu/drm/i915/gt/intel_gt_print.h | 51 +
2 files changed, 97 insertions(+), 50 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_print.h
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index b5ad9caa55372..f153003120997 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -23,6 +23,7 @@
#include "intel_gt_debugfs.h"
#include "intel_gt_mcr.h"
#include "intel_gt_pm.h"
+#include "intel_gt_print.h"
#include "intel_gt_regs.h"
#include "intel_gt_requests.h"
#include "intel_migrate.h"
@@ -90,9 +91,8 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
if (err == -ENODEV)
return 0;
- drm_err(>drm,
- "Failed to setup region(%d) type=%d\n",
- err, INTEL_MEMORY_LOCAL);
+ gt_err(gt, "Failed to setup region(%d) type=%d\n",
+ err, INTEL_MEMORY_LOCAL);
return err;
}
@@ -192,14 +192,14 @@ int intel_gt_init_hw(struct intel_gt *gt)
ret = i915_ppgtt_init_hw(gt);
if (ret) {
- drm_err(>drm, "Enabling PPGTT failed (%d)\n", ret);
+ gt_err(gt, "Enabling PPGTT failed (%d)\n", ret);
goto out;
}
/* We can't enable contexts until all firmware is loaded */
ret = intel_uc_init_hw(>uc);
if (ret) {
- i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
+ gt_probe_error(gt, "Enabling uc failed (%d)\n", ret);
goto out;
}
@@ -264,7 +264,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
* some errors might have become stuck,
* mask them.
*/
- drm_dbg(>i915->drm, "EIR stuck: 0x%08x, masking\n", eir);
+ gt_dbg(gt, "EIR stuck: 0x%08x, masking\n", eir);
rmw_set(uncore, EMR, eir);
intel_uncore_write(uncore, GEN2_IIR,
I915_MASTER_ERROR_INTERRUPT);
@@ -298,16 +298,16 @@ static void gen6_check_faults(struct intel_gt *gt)
for_each_engine(engine, gt, id) {
fault = GEN6_RING_FAULT_REG_READ(engine);
if (fault & RING_FAULT_VALID) {
- drm_dbg(>i915->drm, "Unexpected fault\n"
- "\tAddr: 0x%08lx\n"
- "\tAddress space: %s\n"
- "\tSource ID: %d\n"
- "\tType: %d\n",
- fault & PAGE_MASK,
- fault & RING_FAULT_GTTSEL_MASK ?
- "GGTT" : "PPGTT",
- RING_FAULT_SRCID(fault),
- RING_FAULT_FAULT_TYPE(fault));
+ gt_dbg(gt, "Unexpected fault\n"
+ "\tAddr: 0x%08lx\n"
+ "\tAddress space: %s\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ fault & PAGE_MASK,
+ fault & RING_FAULT_GTTSEL_MASK ?
+ "GGTT" : "PPGTT",
+ RING_FAULT_SRCID(fault),
+ RING_FAULT_FAULT_TYPE(fault));
}
}
}
@@ -334,17 +334,17 @@ static void xehp_check_faults(struct intel_gt *gt)
fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
((u64)fault_data0 << 12);
- drm_dbg(>i915->drm, "Unexpected fault\n"
- "\tAddr: 0x%08x_%08x\n"
- "\tAddress space: %s\n"
- "\tEngine ID: %d\n"
- "\tSource ID: %d\n"
- "\tType: %d\n",
- upper_32_bits(fault_addr), lower_32_bits(fault_addr),
- fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
- GEN8_RING_FAULT_ENGINE_ID(fault),
- RING_FAULT_SRCID(fault),
-
[Intel-gfx] [PATCH v3 3/5] drm/i915/guc: Add GuC specific debug print wrappers
From: John Harrison
Create a set of GuC printers and start using them.
v2: Tweaks to output messages. (review feedback from Michal W).
Split definitions to separate header (review feedback from Jani).
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 33 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 9 ++-
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 49 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 28 -
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 38 +--
drivers/gpu/drm/i915/gt/uc/intel_guc_print.h | 42 +
drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 8 +--
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 56 +++--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 63 +--
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +-
.../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +++
.../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +--
12 files changed, 198 insertions(+), 194 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_print.h
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 52aede324788e..19a632a3e4b03 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -11,6 +11,7 @@
#include "intel_guc.h"
#include "intel_guc_ads.h"
#include "intel_guc_capture.h"
+#include "intel_guc_print.h"
#include "intel_guc_slpc.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -94,8 +95,8 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc)
assert_rpm_wakelock_held(>i915->runtime_pm);
spin_lock_irq(gt->irq_lock);
- WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
-gt->pm_guc_events);
+ guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
+gt->pm_guc_events);
gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
spin_unlock_irq(gt->irq_lock);
@@ -339,7 +340,7 @@ static void guc_init_params(struct intel_guc *guc)
params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
- DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
+ guc_dbg(guc, "init param[%2d] = %#x\n", i, params[i]);
}
/*
@@ -451,7 +452,7 @@ int intel_guc_init(struct intel_guc *guc)
intel_uc_fw_fini(>fw);
out:
intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_INIT_FAIL);
- i915_probe_error(gt->i915, "failed with %d\n", ret);
+ guc_probe_error(guc, "init failed with %d\n", ret);
return ret;
}
@@ -484,7 +485,6 @@ void intel_guc_fini(struct intel_guc *guc)
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
u32 *response_buf, u32 response_buf_size)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
u32 header;
int i;
@@ -519,8 +519,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
10, 10, );
if (unlikely(ret)) {
timeout:
- drm_err(>drm, "mmio request %#x: no reply %x\n",
- request[0], header);
+ guc_err(guc, "mmio request %#x: no reply %x\n", request[0],
header);
goto out;
}
@@ -541,8 +540,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) ==
GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
- drm_dbg(>drm, "mmio request %#x: retrying, reason %u\n",
- request[0], reason);
+ guc_dbg(guc, "mmio request %#x: retrying, reason %u\n",
request[0], reason);
goto retry;
}
@@ -550,16 +548,14 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
- drm_err(>drm, "mmio request %#x: failure %x/%u\n",
- request[0], error, hint);
+ guc_err(guc, "mmio request %#x: failure %x/%u\n", request[0],
error, hint);
ret = -ENXIO;
goto out;
}
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) !=
GUC_HXG_TYPE_RESPONSE_SUCCESS) {
proto:
- drm_err(>drm, "mmio request %#x: unexpected reply %#x\n",
- request[0], header);
+ guc_err(guc, "mmio request %#x: unexpected reply %#x\n",
request[0], header);
ret = -EPROTO;
goto out;
}
@@ -601,9 +597,9 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc
*guc,
[Intel-gfx] [PATCH v3 0/5] Add module oriented dmesg output
From: John Harrison When trying to analyse bug reports from CI, customers, etc. it can be difficult to work out exactly what is happening on which GT in a multi-GT system. So add GT oriented debug/error message wrappers. If used instead of the drm_ equivalents, you get the same output but with a GT# prefix on it. It was also requested to extend this further to submodules in order to factor out the repeated structure accessing constructs and common string prefixes. So, add versions for GuC, HuC and GuC CTB as well. This patch set updates all the gt/uc files to use the new helpers as a first step. The intention would be to convert all output messages that have access to a GT structure. v2: Go back to using lower case names, add more wrapper sets (combined review feedback). Also, wrap up probe injection and WARN entries. v3: Split definitions out to separate header files. Tweak some messages. Wrap a couple more functions. (review feedback from Jani and Michal W). Signed-off-by: John Harrison John Harrison (5): drm/i915/gt: Start adding module oriented dmesg output drm/i915/huc: Add HuC specific debug print wrappers drm/i915/guc: Add GuC specific debug print wrappers drm/i915/guc: Add GuC CT specific debug print wrappers drm/i915/uc: Update the gt/uc code to use gt_err and friends drivers/gpu/drm/i915/gt/intel_gt.c| 96 drivers/gpu/drm/i915/gt/intel_gt_print.h | 51 drivers/gpu/drm/i915/gt/uc/intel_guc.c| 33 ++- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 9 +- .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 49 ++-- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 218 +- drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 28 ++- drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 38 +-- drivers/gpu/drm/i915/gt/uc/intel_guc_print.h | 42 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 8 +- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 56 ++--- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 63 +++-- drivers/gpu/drm/i915/gt/uc/intel_huc.c| 32 ++- drivers/gpu/drm/i915/gt/uc/intel_huc_print.h | 30 +++ drivers/gpu/drm/i915/gt/uc/intel_uc.c | 110 + drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 99 drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +-- .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +- .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +- 19 files changed, 549 insertions(+), 479 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_print.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_print.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_print.h -- 2.37.3
Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/dg2: Introduce Wa_18019271663
On Wed, Nov 23, 2022 at 10:36:48AM -0800, Matt Atwood wrote: > Wa_18019271663 applies to all DG2 steppings and skus. > > Bspec: 66622 > > Signed-off-by: Matt Atwood Reviewed-by: Gustavo Sousa > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > 2 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 74379d3c5a4d..784152548472 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -429,9 +429,10 @@ > #define RC_OP_FLUSH_ENABLE (1 << 0) > #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) > #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ > -#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6) > -#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6) > -#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1) > +#define MSAA_OPTIMIZATION_REDUC_DISABLEREG_BIT(11) > +#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE REG_BIT(6) > +#define GEN8_4x4_STC_OPTIMIZATION_DISABLE REG_BIT(6) > +#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1) > > #define GEN7_GT_MODE _MMIO(0x7008) > #define GEN9_IZ_HASHING_MASK(slice)(0x3 << ((slice) * 2)) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 870db5a202dd..1b0e40e68a9d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -781,6 +781,9 @@ static void dg2_ctx_workarounds_init(struct > intel_engine_cs *engine, > > /* Wa_15010599737:dg2 */ > wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > + > + /* Wa_18019271663:dg2 */ > + wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); > } > > static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, > -- > 2.38.1 >
Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978
On Wed, Nov 23, 2022 at 10:36:47AM -0800, Matt Atwood wrote: > Wa_18018764978 applies to specific steppings of DG2 (G10 C0+, > G11 and G12 A0+). Clean up style in function at the same time. > > Bspec: 66622 > > Signed-off-by: Matt Atwood Reviewed-by: Gustavo Sousa > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++- > 2 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 80a979e6f6be..74379d3c5a4d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -457,6 +457,9 @@ > #define GEN8_L3CNTLREG _MMIO(0x7034) > #define GEN8_ERRDETBCTRL (1 << 9) > > +#define PSS_MODE2_MMIO(0x703c) > +#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) > + > #define GEN7_SC_INSTDONE _MMIO(0x7100) > #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) > #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 2afb4f80a954..870db5a202dd 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -771,9 +771,14 @@ static void dg2_ctx_workarounds_init(struct > intel_engine_cs *engine, > > /* Wa_14014947963:dg2 */ > if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || > - IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > wa_masked_field_set(wal, VF_PREEMPTION, > PREEMPTION_VERTEX_COUNT, 0x4000); > > + /* Wa_18018764978:dg2 */ > + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > + wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); > + > /* Wa_15010599737:dg2 */ > wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > } > -- > 2.38.1 >
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/perf: Do not parse context image for HSW (rev2)
== Series Details == Series: drm/i915/perf: Do not parse context image for HSW (rev2) URL : https://patchwork.freedesktop.org/series/111231/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12419_full -> Patchwork_111231v2_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_111231v2_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_111231v2_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_111231v2_full: ### IGT changes ### Possible regressions * igt@gem_exec_schedule@deep@vecs0: - shard-skl: NOTRUN -> [INCOMPLETE][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v2/shard-skl3/igt@gem_exec_schedule@d...@vecs0.html * igt@kms_vblank@pipe-d-ts-continuation-modeset-hang: - shard-tglb: [PASS][2] -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-tglb8/igt@kms_vbl...@pipe-d-ts-continuation-modeset-hang.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v2/shard-tglb8/igt@kms_vbl...@pipe-d-ts-continuation-modeset-hang.html Known issues Here are the changes found in Patchwork_111231v2_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ccs@block-copy-compressed: - shard-iclb: NOTRUN -> [SKIP][4] ([i915#5327]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v2/shard-iclb5/igt@gem_...@block-copy-compressed.html * igt@gem_ctx_persistence@hang: - shard-skl: NOTRUN -> [SKIP][5] ([fdo#109271]) +166 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v2/shard-skl10/igt@gem_ctx_persiste...@hang.html * igt@gem_exec_balancer@parallel-balancer: - shard-iclb: [PASS][6] -> [SKIP][7] ([i915#4525]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-iclb2/igt@gem_exec_balan...@parallel-balancer.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v2/shard-iclb5/igt@gem_exec_balan...@parallel-balancer.html * igt@gem_exec_balancer@parallel-keep-submit-fence: - shard-iclb: NOTRUN -> [SKIP][8] ([i915#4525]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v2/shard-iclb5/igt@gem_exec_balan...@parallel-keep-submit-fence.html * igt@gem_exec_params@larger-than-life-batch: - shard-glk: NOTRUN -> [SKIP][9] ([fdo#109271]) +44 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v2/shard-glk8/igt@gem_exec_par...@larger-than-life-batch.html * igt@gem_lmem_swapping@heavy-random: - shard-glk: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v2/shard-glk8/igt@gem_lmem_swapp...@heavy-random.html * igt@gen9_exec_parse@cmd-crossing-page: - shard-iclb: NOTRUN -> [SKIP][11] ([i915#2856]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v2/shard-iclb5/igt@gen9_exec_pa...@cmd-crossing-page.html * igt@i915_pipe_stress@stress-xrgb-ytiled: - shard-skl: NOTRUN -> [FAIL][12] ([i915#7036]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v2/shard-skl9/igt@i915_pipe_str...@stress-xrgb-ytiled.html * igt@i915_pm_rc6_residency@rc6-idle@vcs0: - shard-skl: NOTRUN -> [WARN][13] ([i915#1804]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v2/shard-skl10/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html * igt@i915_selftest@live@hangcheck: - shard-tglb: [PASS][14] -> [DMESG-WARN][15] ([i915#5591]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-tglb3/igt@i915_selftest@l...@hangcheck.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v2/shard-tglb1/igt@i915_selftest@l...@hangcheck.html * igt@i915_suspend@fence-restore-untiled: - shard-skl: [PASS][16] -> [INCOMPLETE][17] ([i915#7232]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-skl9/igt@i915_susp...@fence-restore-untiled.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v2/shard-skl2/igt@i915_susp...@fence-restore-untiled.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#5286]) [18]:
Re: [Intel-gfx] [PATCH v2 2/4] drm/i915: Introduce guard pages to i915_vma
Hi Tvrtko,
[...]
> > @@ -768,6 +768,9 @@ i915_vma_insert(struct i915_vma *vma, struct
> > i915_gem_ww_ctx *ww,
> > GEM_BUG_ON(!IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
> > GEM_BUG_ON(!is_power_of_2(alignment));
> > + guard = vma->guard; /* retain guard across rebinds */
> > + guard = ALIGN(guard, alignment);
>
> Why does guard area needs the same alignment as the requested mapping? What
> about the fact on 32-bit builds guard is 32-bit and alignment u64?
I guess this just to round up/down guard to something, not
necessarily to that alignment.
Shall I remove it?
[...]
> > @@ -777,6 +780,7 @@ i915_vma_insert(struct i915_vma *vma, struct
> > i915_gem_ww_ctx *ww,
> > if (flags & PIN_ZONE_4G)
> > end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE);
> > GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
> > + GEM_BUG_ON(2 * guard > end);
>
> End is the size of relevant VA area at this point so what and why is this
> checking?
I think because we want to make sure the padding is at least not
bigger that the size. What is actually wrong with this.
[...]
> > @@ -855,6 +869,7 @@ i915_vma_insert(struct i915_vma *vma, struct
> > i915_gem_ww_ctx *ww,
> > GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, color));
> > list_move_tail(>vm_link, >vm->bound_list);
> > + vma->guard = guard;
>
> unsigned long into u32 - what guarantees no truncation?
we are missing here this part above:
guard = vma->guard; /* retain guard across rebinds */
if (flags & PIN_OFFSET_GUARD) {
GEM_BUG_ON(overflows_type(flags & PIN_OFFSET_MASK, u32));
guard = max_t(u32, guard, flags & PIN_OFFSET_MASK);
}
that should make sure that we fit into 32 bits.
[...]
> > @@ -197,14 +197,15 @@ struct i915_vma {
> > struct i915_fence_reg *fence;
> > u64 size;
> > - u64 display_alignment;
> > struct i915_page_sizes page_sizes;
> > /* mmap-offset associated with fencing for this vma */
> > struct i915_mmap_offset *mmo;
> > + u32 guard; /* padding allocated around vma->pages within the node */
> > u32 fence_size;
> > u32 fence_alignment;
> > + u32 display_alignment;
>
> u64 -> u32 for display_alignment looks unrelated change.
>
> ./display/intel_fb_pin.c: vma->display_alignment = max_t(u64,
> vma->display_alignment, alignment);
> ./gem/i915_gem_domain.c:vma->display_alignment = max_t(u64,
> vma->display_alignment, alignment);
>
> These two sites need to be changed not to use u64.
>
> Do this part in a separate patch?
Right! will remove it.
> > /**
> > * Count of the number of times this vma has been opened by different
>
> Regards,
Thanks,
Andi
> Tvrtko
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Gamma/DSB prep work
== Series Details == Series: drm/i915: Gamma/DSB prep work URL : https://patchwork.freedesktop.org/series/111262/ State : success == Summary == CI Bug Log - changes from CI_DRM_12424 -> Patchwork_111262v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/index.html Participating hosts (37 -> 37) -- Additional (2): fi-icl-u2 bat-dg1-6 Missing(2): fi-ctg-p8600 fi-ilk-m540 Known issues Here are the changes found in Patchwork_111262v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - fi-icl-u2: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/fi-icl-u2/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-icl-u2: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@random-engines: - fi-icl-u2: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html * igt@gem_mmap@basic: - bat-dg1-6: NOTRUN -> [SKIP][4] ([i915#4083]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/bat-dg1-6/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][5] ([i915#4079]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-6: NOTRUN -> [SKIP][7] ([i915#7561]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#6621]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/bat-dg1-6/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[PASS][9] -> [INCOMPLETE][10] ([i915#4785]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12424/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html * igt@i915_suspend@basic-s2idle-without-i915: - fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][11] ([i915#146]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/fi-bdw-gvtdvm/igt@i915_susp...@basic-s2idle-without-i915.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: [PASS][12] -> [FAIL][13] ([fdo#103375]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12424/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-6: NOTRUN -> [SKIP][14] ([i915#4215]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@tile-pitch-mismatch: - bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#4212]) +7 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html * igt@kms_chamelium@common-hpd-after-suspend: - bat-dg1-5: NOTRUN -> [SKIP][16] ([fdo#111827]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/bat-dg1-5/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-crc-fast: - bat-dg1-6: NOTRUN -> [SKIP][17] ([fdo#111827]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][18] ([fdo#111827]) +8 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html - fi-bdw-gvtdvm: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +7 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111262v1/fi-bdw-gvtdvm/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - fi-icl-u2: NOTRUN -> [SKIP][20] ([i915#4103]) [20]:
[Intel-gfx] [PATCH v4 2/2] drm/i915/dg2: Introduce Wa_18019271663
Wa_18019271663 applies to all DG2 steppings and skus. Bspec: 66622 Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 74379d3c5a4d..784152548472 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -429,9 +429,10 @@ #define RC_OP_FLUSH_ENABLE (1 << 0) #define HIZ_RAW_STALL_OPT_DISABLE(1 << 2) #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ -#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE(1 << 6) -#define GEN8_4x4_STC_OPTIMIZATION_DISABLE(1 << 6) -#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1) +#define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) +#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLEREG_BIT(6) +#define GEN8_4x4_STC_OPTIMIZATION_DISABLEREG_BIT(6) +#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1) #define GEN7_GT_MODE _MMIO(0x7008) #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 870db5a202dd..1b0e40e68a9d 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -781,6 +781,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, /* Wa_15010599737:dg2 */ wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); + + /* Wa_18019271663:dg2 */ + wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); } static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, -- 2.38.1
[Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978
Wa_18018764978 applies to specific steppings of DG2 (G10 C0+, G11 and G12 A0+). Clean up style in function at the same time. Bspec: 66622 Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 80a979e6f6be..74379d3c5a4d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -457,6 +457,9 @@ #define GEN8_L3CNTLREG _MMIO(0x7034) #define GEN8_ERRDETBCTRL (1 << 9) +#define PSS_MODE2 _MMIO(0x703c) +#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) + #define GEN7_SC_INSTDONE _MMIO(0x7100) #define GEN12_SC_INSTDONE_EXTRA_MMIO(0x7104) #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 2afb4f80a954..870db5a202dd 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -771,9 +771,14 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, /* Wa_14014947963:dg2 */ if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || - IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); + /* Wa_18018764978:dg2 */ + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) + wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); + /* Wa_15010599737:dg2 */ wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); } -- 2.38.1
Re: [Intel-gfx] [PATCH 5/6] drm/i915/gsc: Disable GSC engine and power well if FW is not selected
On Tue, Nov 22, 2022 at 02:58:37PM -0800, Ceraolo Spurio, Daniele wrote:
>
>
> On 11/22/2022 12:52 PM, Rodrigo Vivi wrote:
> > On Mon, Nov 21, 2022 at 03:16:16PM -0800, Daniele Ceraolo Spurio wrote:
> > > From: Jonathan Cavitt
> > >
> > > The GSC CS is only used for communicating with the GSC FW, so no need to
> > > initialize it if we're not going to use the FW. If we're not using
> > > neither the engine nor the microcontoller, then we can also disable the
> > > power well.
> > >
> > > IMPORTANT: lack of GSC FW breaks media C6 due to opposing requirements
> > > between CS setup and forcewake idleness. See in-code comment for detail.
> > >
> > > Signed-off-by: Jonathan Cavitt
> > > Signed-off-by: Daniele Ceraolo Spurio
> > > Cc: Matt Roper
> > > Cc: John C Harrison
> > > Cc: Rodrigo Vivi
> > > Cc: Vinay Belgaumkar
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 18 ++
> > > drivers/gpu/drm/i915/intel_uncore.c | 3 +++
> > > 2 files changed, 21 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > index c33e0d72d670..99c4b866addd 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > @@ -894,6 +894,24 @@ static intel_engine_mask_t init_engine_mask(struct
> > > intel_gt *gt)
> > > engine_mask_apply_compute_fuses(gt);
> > > engine_mask_apply_copy_fuses(gt);
> > > + /*
> > > + * The only use of the GSC CS is to load and communicate with the GSC
> > > + * FW, so we have no use for it if we don't have the FW.
> > > + *
> > > + * IMPORTANT: in cases where we don't have the GSC FW, we have a
> > > + * catch-22 situation that breaks media C6 due to 2 requirements:
> > > + * 1) once turned on, the GSC power well will not go to sleep unless the
> > > + *GSC FW is loaded.
> > > + * 2) to enable idling (which is required for media C6) we need to
> > > + *initialize the IDLE_MSG register for the GSC CS and do at least 1
> > > + *submission, which will wake up the GSC power well.
> > > + */
> > > + if (__HAS_ENGINE(info->engine_mask, GSC0) &&
> > > !intel_uc_wants_gsc_uc(>uc)) {
> > > + drm_notice(>i915->drm,
> > > +"No GSC FW selected, disabling GSC CS and media
> > > C6\n");
> > > + info->engine_mask &= ~BIT(GSC0);
> > > + }
> > > +
> > > return info->engine_mask;
> > > }
> > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> > > b/drivers/gpu/drm/i915/intel_uncore.c
> > > index c1befa33ff59..e63d957b59eb 100644
> > > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > > @@ -2701,6 +2701,9 @@ void intel_uncore_prune_engine_fw_domains(struct
> > > intel_uncore *uncore,
> > > if (fw_domains & BIT(domain_id))
> > > fw_domain_fini(uncore, domain_id);
> > > }
> > > +
> > > + if ((fw_domains & BIT(FW_DOMAIN_ID_GSC)) && !HAS_ENGINE(gt, GSC0))
> > > + fw_domain_fini(uncore, FW_DOMAIN_ID_GSC);
> > On a quick glace I was asking "why do you need this since it doesn't have
> > the gsc0?
> > Then I remember that fw_domain got initialized and it will be skipped,
> > right?
> > Then I though about at least have a comment here, but finally I got myself
> > wondering
> > why we don't do this already in the if above, while we are cleaning the
> > engine mask?
>
> I've followed the existing code flows that we have in place for fused off
> VCS/VECS. Basically the existing code goes like this:
>
> 1) All FW domains for the platform are initialized
> 2) We read the fuses and adjust the engine mask accordingly
> 3) We go back and prune the FW domains that are not applicable anymore due
> to the updated mask.
>
> The idea is to have a single gt-level function doing all the mask adjusting
> and an uncore-level one doing all the domain pruning. I'm not against
> changing this approach, but in that case we should update the behavior for
> VCS/VECS as well (which might be complicated, because VCS/VECS engines share
> FW domains, so the pruning logic is ugly).
okay, then let's move with this...
Reviewed-by: Rodrigo Vivi
>
> Daniele
>
> >
> > > }
> > > static void driver_flr(struct intel_uncore *uncore)
> > > --
> > > 2.37.3
> > >
>
Re: [Intel-gfx] [PATCH 4/6] drm/i915/gsc: Do a driver-FLR on unload if GSC was loaded
On Tue, Nov 22, 2022 at 02:50:17PM -0800, Ceraolo Spurio, Daniele wrote:
>
>
> On 11/22/2022 12:46 PM, Rodrigo Vivi wrote:
> > On Mon, Nov 21, 2022 at 03:16:15PM -0800, Daniele Ceraolo Spurio wrote:
> > > If the GSC was loaded, the only way to stop it during the driver unload
> > > flow is to do a driver-FLR.
> > > The driver-FLR is not the same as PCI config space FLR in that
> > > it doesn't reset the SGUnit and doesn't modify the PCI config
> > > space. Thus, it doesn't require a re-enumeration of the PCI BARs.
> > > However, the driver-FLR does cause a memory wipe of graphics memory
> > > on all discrete GPU platforms or a wipe limited to stolen memory
> > > on the integrated GPU platforms.
> > Nothing major or blocking, but a few thoughts:
> >
> > 1. Should we document this in the code, at least in a comment in the
> > flr function?
>
> Sure, I'll add it in
>
> > 2. Should we call this driver_initiated_flr, aiming to reduce even more
> > the ambiguity of it?
>
> ok
>
> >
> > > We perform the FLR as the last action before releasing the MMIO bar, so
> > > that we don't have to care about the consequences of the reset on the
> > > unload flow.
> > 3. should we try to implement this already in the gt_reset case as the
> > last resrouce before wedging the gt? So we can already test this flow
> > in the current platforms?
>
> This would be nice to have, but very complicated to implement. The fact that
> FLR kills everything on the system, including resetting display and wiping
> LMEM, means that we would need a new recovery path to re-initialize all
> components. There are also potential questions on how to handle LMEM: do we
> try to migrate it to SMEM before triggering the FLR (potentially via CPU
> memcpy if the GT is dead), or do we just let it get wiped?
>
> The reason why I wanted the FLR to be the very last thing before releasing
> MMIO access was exactly to not have to care about the recovery path ;)
it makes sense indeed.
>
> Daniele
>
> >
> > > Signed-off-by: Daniele Ceraolo Spurio
> > > Signed-off-by: Alan Previn
> > > ---
> > > drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 9 +
> > > drivers/gpu/drm/i915/i915_reg.h | 3 ++
> > > drivers/gpu/drm/i915/intel_uncore.c | 45 +++
> > > drivers/gpu/drm/i915/intel_uncore.h | 13 +++
> > > 4 files changed, 70 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
> > > b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
> > > index 510fb47193ec..5dad3c19c445 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
> > > @@ -173,6 +173,15 @@ int intel_gsc_fw_upload(struct intel_gsc_uc *gsc)
> > > if (err)
> > > goto fail;
> > > + /*
> > > + * Once the GSC FW is loaded, the only way to kill it on driver unload
> > > + * is to do a driver FLR. Given this is a very disruptive action, we
> > > + * want to do it as the last action before releasing the access to the
> > > + * MMIO bar, which means we need to do it as part of the primary uncore
> > > + * cleanup.
> > > + */
> > > + intel_uncore_set_flr_on_fini(>i915->uncore);
> > > +
> > > /* FW is not fully operational until we enable SW proxy */
> > > intel_uc_fw_change_status(gsc_fw,
> > > INTEL_UC_FIRMWARE_TRANSFERRED);
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 8e1892d14774..60e55245200b 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -118,6 +118,9 @@
> > > #define GU_CNTL _MMIO(0x101010)
> > > #define LMEM_INIT REG_BIT(7)
> > > +#define DRIVERFLR REG_BIT(31)
> > > +#define GU_DEBUG _MMIO(0x101018)
> > > +#define DRIVERFLR_STATUS REG_BIT(31)
> > > #define GEN6_STOLEN_RESERVED_MMIO(0x1082C0)
> > > #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
> > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> > > b/drivers/gpu/drm/i915/intel_uncore.c
> > > index 8006a6c61466..c1befa33ff59 100644
> > > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > > @@ -2703,6 +2703,48 @@ void intel_uncore_prune_engine_fw_domains(struct
> > > intel_uncore *uncore,
> > > }
> > > }
> > > +static void driver_flr(struct intel_uncore *uncore)
> > > +{
> > > + struct drm_i915_private *i915 = uncore->i915;
> > > + const unsigned int flr_timeout_ms = 3000; /* specs recommend a 3s wait
> > > */
> > > + int ret;
> > > +
> > > + drm_dbg(>drm, "Triggering Driver-FLR\n");
> > > +
> > > + /*
> > > + * Make sure any pending FLR requests have cleared by waiting for the
> > > + * FLR trigger bit to go to zero. Also clear GU_DEBUG's DRIVERFLR_STATUS
> > > + * to make sure it's not still set from a prior attempt (it's a write to
> > > + * clear
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Gamma/DSB prep work
== Series Details == Series: drm/i915: Gamma/DSB prep work URL : https://patchwork.freedesktop.org/series/111262/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/display/intel_dsb.c:201: warning: Excess function parameter 'crtc_state' description in 'intel_dsb_reg_write' ./drivers/gpu/drm/i915/display/intel_dsb.c:201: warning: Function parameter or member 'dsb' not described in 'intel_dsb_reg_write' ./drivers/gpu/drm/i915/display/intel_dsb.c:201: warning: Excess function parameter 'crtc_state' description in 'intel_dsb_reg_write' ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Gamma/DSB prep work
== Series Details == Series: drm/i915: Gamma/DSB prep work URL : https://patchwork.freedesktop.org/series/111262/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma/DSB prep work
== Series Details == Series: drm/i915: Gamma/DSB prep work URL : https://patchwork.freedesktop.org/series/111262/ State : warning == Summary == Error: dim checkpatch failed 8f9716b0038b drm/i915: Shorten GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED a bit 725e303baa7f drm/i915: Clean up GAMMA_MODE defines -:35: WARNING:LONG_LINE_COMMENT: line length of 101 exceeds 100 columns #35: FILE: drivers/gpu/drm/i915/i915_reg.h:5318: +#define GAMMA_MODE_MODE_SPLIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* ivb-bdw */ -:36: WARNING:LONG_LINE_COMMENT: line length of 101 exceeds 100 columns #36: FILE: drivers/gpu/drm/i915/i915_reg.h:5319: +#define GAMMA_MODE_MODE_12BIT_MULTI_SEG REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */ total: 0 errors, 2 warnings, 0 checks, 22 lines checked 67b6bbe92e61 drm/i915: Define skl+ palette anti-collision bit bbcbe1d1b741 drm/i915: Clean up various indexed LUT registers -:197: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #197: FILE: drivers/gpu/drm/i915/i915_reg.h:7576: +#define PAL_PREC_MULTI_SEG_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK, (x)) total: 0 errors, 1 warnings, 0 checks, 162 lines checked 1c9ea03dbbbe drm/i915: Standardize auto-increment LUT load procedure 8a2f660eccfe drm/i915: Document LUT "max" register precision -:32: WARNING:LONG_LINE_COMMENT: line length of 105 exceeds 100 columns #32: FILE: drivers/gpu/drm/i915/i915_reg.h:5307: +#define PREC_PIPEGCMAX(pipe, i)_MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1.16 */ -:43: WARNING:LONG_LINE: line length of 120 exceeds 100 columns #43: FILE: drivers/gpu/drm/i915/i915_reg.h:7554: +#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) /* u1.16 */ -:44: WARNING:LONG_LINE: line length of 128 exceeds 100 columns #44: FILE: drivers/gpu/drm/i915/i915_reg.h:7555: +#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) /* u3.16 */ -:45: WARNING:LONG_LINE: line length of 136 exceeds 100 columns #45: FILE: drivers/gpu/drm/i915/i915_reg.h:7556: +#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) /* glk+, u3.16 */ total: 0 errors, 4 warnings, 0 checks, 28 lines checked c56e8ed19533 drm/i915: Move the DSB->mmio fallback into the LUT code 643c7b5484d7 drm/i915: Move the DSB setup/cleaup into the color code -:131: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects? #131: FILE: drivers/gpu/drm/i915/display/intel_display.h:443: +#define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \ + for ((__i) = 0; \ +(__i) < (__state)->base.dev->mode_config.num_crtc && \ +((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ + (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \ +(__i)++) \ + for_each_if(crtc) -:131: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'crtc' - possible side-effects? #131: FILE: drivers/gpu/drm/i915/display/intel_display.h:443: +#define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \ + for ((__i) = 0; \ +(__i) < (__state)->base.dev->mode_config.num_crtc && \ +((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ + (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \ +(__i)++) \ + for_each_if(crtc) -:131: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects? #131: FILE: drivers/gpu/drm/i915/display/intel_display.h:443: +#define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \ + for ((__i) = 0; \ +(__i) < (__state)->base.dev->mode_config.num_crtc && \ +((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ + (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \ +(__i)++) \ + for_each_if(crtc) -:135: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #135: FILE: drivers/gpu/drm/i915/display/intel_display.h:447: + (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \ total: 0 errors, 1 warnings, 3 checks, 99 lines checked 3376369f655d drm/i915: Make DSB lower level 254311de0fb7 drm/i915: Disable DSB usage specifically for LUTs 029ab662a202 Revert "drm/i915: Disable DSB usage for now" fcb5168a004e drm/i915: Use ilk_lut_write*() for all ilk+ gamma modes 042ad2520eaf drm/i915: Do state check for color management changes
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/uc: Fix table order verification to check all FW types
== Series Details == Series: drm/i915/uc: Fix table order verification to check all FW types URL : https://patchwork.freedesktop.org/series/111228/ State : success == Summary == CI Bug Log - changes from CI_DRM_12419_full -> Patchwork_111228v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_111228v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ccs@block-copy-compressed: - shard-iclb: NOTRUN -> [SKIP][1] ([i915#5327]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111228v1/shard-iclb1/igt@gem_...@block-copy-compressed.html * igt@gem_ctx_persistence@hang: - shard-skl: NOTRUN -> [SKIP][2] ([fdo#109271]) +147 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111228v1/shard-skl6/igt@gem_ctx_persiste...@hang.html * igt@gem_eio@in-flight-suspend: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#7112]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-skl4/igt@gem_...@in-flight-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111228v1/shard-skl3/igt@gem_...@in-flight-suspend.html * igt@gem_exec_balancer@parallel-balancer: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-iclb2/igt@gem_exec_balan...@parallel-balancer.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111228v1/shard-iclb8/igt@gem_exec_balan...@parallel-balancer.html * igt@gem_exec_params@larger-than-life-batch: - shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271]) +45 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111228v1/shard-glk7/igt@gem_exec_par...@larger-than-life-batch.html * igt@gem_lmem_swapping@heavy-random: - shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111228v1/shard-glk7/igt@gem_lmem_swapp...@heavy-random.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111228v1/shard-skl10/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_userptr_blits@input-checking: - shard-skl: NOTRUN -> [DMESG-WARN][10] ([i915#4991]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111228v1/shard-skl10/igt@gem_userptr_bl...@input-checking.html * igt@gen9_exec_parse@cmd-crossing-page: - shard-iclb: NOTRUN -> [SKIP][11] ([i915#2856]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111228v1/shard-iclb1/igt@gen9_exec_pa...@cmd-crossing-page.html * igt@i915_pipe_stress@stress-xrgb-ytiled: - shard-skl: NOTRUN -> [FAIL][12] ([i915#7036]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111228v1/shard-skl2/igt@i915_pipe_str...@stress-xrgb-ytiled.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#3989] / [i915#454]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12419/shard-iclb7/igt@i915_pm...@dc6-psr.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111228v1/shard-iclb3/igt@i915_pm...@dc6-psr.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip: - shard-iclb: NOTRUN -> [SKIP][15] ([i915#5286]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111228v1/shard-iclb1/igt@kms_big...@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html * igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc: - shard-iclb: NOTRUN -> [SKIP][16] ([fdo#109278]) +7 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111228v1/shard-iclb1/igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc.html * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs: - shard-iclb: NOTRUN -> [SKIP][17] ([fdo#109278] / [i915#3886]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111228v1/shard-iclb1/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3886]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111228v1/shard-skl10/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc: - shard-glk: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3886]) +1 similar issue [19]:
[Intel-gfx] [PATCH i-g-t v2] tests/i915/gem_ppgtt: verify GTT eviction with contended locks
We should still be able to GTT evict objects during execbuf (old
bindings can linger around), even if there is object lock contention. In
the worst case the execbuf should just wait on the contented locks.
Returning -ENOSPC smells like a regression from past behaviour, and
seems to break userspace.
v2:
- Add coverage for explicit softpin
- Add timeout for the spinner
References: https://gitlab.freedesktop.org/drm/intel/-/issues/7570
Signed-off-by: Matthew Auld
Cc: Andrzej Hajda
Cc: Nirmoy Das
---
tests/i915/gem_ppgtt.c | 120 +
1 file changed, 120 insertions(+)
diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c
index 9673ce22..c0b954e0 100644
--- a/tests/i915/gem_ppgtt.c
+++ b/tests/i915/gem_ppgtt.c
@@ -255,6 +255,118 @@ static void flink_and_close(void)
close(fd2);
}
+#define PAGE_SIZE 4096
+
+static uint32_t batch_create_size(int fd, uint64_t size)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(fd, size);
+ gem_write(fd, handle, 0, , sizeof(bbe));
+
+ return handle;
+}
+
+#define IGT_USE_ANY0x1
+#define IGT_USE_PINNED 0x2
+static void upload(int fd, uint32_t handle, uint32_t in_fence, uint32_t ctx_id,
+ unsigned int flags)
+{
+ struct drm_i915_gem_exec_object2 exec[2] = {};
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(),
+ .buffer_count = 1,
+ .rsvd1 = ctx_id,
+ };
+
+ if (in_fence) {
+ execbuf.rsvd2 = in_fence;
+ execbuf.flags = I915_EXEC_FENCE_IN;
+ }
+
+ exec[0].handle = handle;
+ exec[0].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+ if (flags & IGT_USE_PINNED)
+ exec[0].flags |= EXEC_OBJECT_PINNED; /* offset = 0 */
+
+ if (flags & IGT_USE_ANY) {
+ exec[0].flags |= EXEC_OBJECT_PAD_TO_SIZE;
+ exec[0].pad_to_size = gem_aperture_size(fd);
+ }
+
+ gem_execbuf(fd, );
+}
+
+static void shrink_vs_evict(unsigned int flags)
+{
+ const unsigned int nproc = sysconf(_SC_NPROCESSORS_ONLN) + 1;
+ const uint64_t timeout_5s = 50LL;
+ int fd = drm_open_driver(DRIVER_INTEL);
+ uint64_t ahnd = get_reloc_ahnd(fd, 0);
+ const intel_ctx_t *ctx_arr[nproc];
+ igt_spin_t *spinner;
+ uint32_t handle1;
+ int i;
+
+ igt_require(gem_uses_full_ppgtt(fd));
+
+ igt_drop_caches_set(fd, DROP_ALL);
+
+ handle1 = gem_create(fd, PAGE_SIZE);
+
+ spinner = igt_spin_new(fd,
+ .ahnd = ahnd,
+ .flags = IGT_SPIN_FENCE_OUT);
+ igt_spin_set_timeout(spinner, timeout_5s);
+
+ /*
+* Create several VMs to ensure we don't block on the same vm lock. The
+* goal of the test is to ensure that object lock contention doesn't
+* somehow result in -ENOSPC from execbuf, if we need to trigger GTT
+* eviction.
+*/
+ for (i = 0; i < nproc; i++) {
+ ctx_arr[i] = intel_ctx_create(fd, NULL);
+
+ upload(fd, handle1, spinner->execbuf.rsvd2 >> 32,
+ ctx_arr[i]->id, flags);
+ }
+
+ igt_fork(child, 1)
+ igt_drop_caches_set(fd, DROP_ALL);
+
+ sleep(2); /* Give the shrinker time to find handle1 */
+
+ igt_fork(child, nproc) {
+ uint32_t handle2 = gem_create(fd, PAGE_SIZE);
+
+ /*
+* One of these forks will be stuck on the vm mutex, since the
+* shrinker is holding it (along with the object lock) while
+* trying to unbind the chosen vma, but is blocked by the
+* spinner. The rest should only block waiting to grab the
+* object lock for handle1, before then trying to GTT evict it
+* from their respective vm. In either case the contention of
+* the vm->mutex or object lock should never result in -ENOSPC
+* or some other error.
+*/
+ handle2 = batch_create_size(fd, PAGE_SIZE);
+
+ upload(fd, handle2, 0, ctx_arr[child]->id, flags);
+ gem_close(fd, handle2);
+ }
+
+ igt_waitchildren();
+ igt_spin_free(fd, spinner);
+
+ for (i = 0; i < nproc; i++)
+ intel_ctx_destroy(fd, ctx_arr[i]);
+
+ gem_close(fd, handle1);
+}
+
static bool has_contexts(void)
{
bool result;
@@ -331,4 +443,12 @@ igt_main
igt_subtest("flink-and-close-vma-leak")
flink_and_close();
+
+ igt_describe("Verify GTT eviction can't randomly fail due to object
lock contention");
+ igt_subtest_group {
+ igt_subtest("shrink-vs-evict-any")
+ shrink_vs_evict(IGT_USE_ANY);
+ igt_subtest("shrink-vs-evict-pinned")
+
Re: [Intel-gfx] [PATCH] drm/i915/gt: remove some limited use register access wrappers
On Wed, Nov 23, 2022 at 06:49:16PM +0200, Jani Nikula wrote:
> Remove rmw_set(), rmw_clear(), clear_register(), rmw_set_fw(), and
> rmw_clear_fw(). They're just one too many levels of abstraction for
> register access, for very specific purposes.
>
> clear_register() seems like a micro-optimization bypassing the write
> when the register is already clear, but that trick has ceased to work
> since commit 06b975d58fd6 ("drm/i915: make intel_uncore_rmw() write
> unconditionally"). Just clear the register in the most obvious way.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c| 29 +++
> drivers/gpu/drm/i915/gt/intel_reset.c | 18 -
> 2 files changed, 11 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index b5ad9caa5537..efd9d722d77f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -210,21 +210,6 @@ int intel_gt_init_hw(struct intel_gt *gt)
> return ret;
> }
>
> -static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
> -{
> - intel_uncore_rmw(uncore, reg, 0, set);
> -}
> -
> -static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
> -{
> - intel_uncore_rmw(uncore, reg, clr, 0);
> -}
> -
> -static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
> -{
> - intel_uncore_rmw(uncore, reg, 0, 0);
> -}
> -
> static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
> {
> GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
> @@ -250,14 +235,14 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
> u32 eir;
>
> if (GRAPHICS_VER(i915) != 2)
> - clear_register(uncore, PGTBL_ER);
> + intel_uncore_write(uncore, PGTBL_ER, 0);
>
> if (GRAPHICS_VER(i915) < 4)
> - clear_register(uncore, IPEIR(RENDER_RING_BASE));
> + intel_uncore_write(uncore, IPEIR(RENDER_RING_BASE), 0);
> else
> - clear_register(uncore, IPEIR_I965);
> + intel_uncore_write(uncore, IPEIR_I965, 0);
>
> - clear_register(uncore, EIR);
> + intel_uncore_write(uncore, EIR, 0);
> eir = intel_uncore_read(uncore, EIR);
> if (eir) {
> /*
> @@ -265,7 +250,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
>* mask them.
>*/
> drm_dbg(>i915->drm, "EIR stuck: 0x%08x, masking\n", eir);
> - rmw_set(uncore, EMR, eir);
> + intel_uncore_rmw(uncore, EMR, 0, eir);
> intel_uncore_write(uncore, GEN2_IIR,
> I915_MASTER_ERROR_INTERRUPT);
> }
> @@ -275,10 +260,10 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
> RING_FAULT_VALID, 0);
> intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
> } else if (GRAPHICS_VER(i915) >= 12) {
> - rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
> + intel_uncore_rmw(uncore, GEN12_RING_FAULT_REG,
> RING_FAULT_VALID, 0);
> intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
> } else if (GRAPHICS_VER(i915) >= 8) {
> - rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
> + intel_uncore_rmw(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID,
> 0);
> intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
> } else if (GRAPHICS_VER(i915) >= 6) {
> struct intel_engine_cs *engine;
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 24736ebee17c..ffde89c5835a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -35,16 +35,6 @@
> /* XXX How to handle concurrent GGTT updates using tiling registers? */
> #define RESET_UNDER_STOP_MACHINE 0
>
> -static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
> -{
> - intel_uncore_rmw_fw(uncore, reg, 0, set);
> -}
> -
> -static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32
> clr)
> -{
> - intel_uncore_rmw_fw(uncore, reg, clr, 0);
> -}
> -
> static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
> {
> struct drm_i915_file_private *file_priv = ctx->file_priv;
> @@ -212,7 +202,7 @@ static int g4x_do_reset(struct intel_gt *gt,
> int ret;
>
> /* WaVcpClkGateDisableForMediaReset:ctg,elk */
> - rmw_set_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_rmw_fw(uncore, VDECCLK_GATE_D, 0,
> VCP_UNIT_CLOCK_GATE_DISABLE);
> intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
>
> pci_write_config_byte(pdev, I915_GDRST,
> @@ -234,7 +224,7 @@ static int g4x_do_reset(struct intel_gt *gt,
> out:
>
Re: [Intel-gfx] [PATCH] drm/i915/dg1: Remove require_force_probe protection
On Fri, Oct 21, 2022 at 11:17:19AM +0530, Chaitanya Kumar Borah wrote:
> Remove force probe protection from DG1 platform as testing suggests
> that the platform is stable enough.
>
> Signed-off-by: Chaitanya Kumar Borah
We do have a clean CI now that Umesh merged these patches:
e746f84b8e81 ("i915/uncore: Acquire fw before loop in intel_uncore_read64_2x32")
529d95a6067b ("drm/i915/selftest: Bump up sample period for busy stats
selftest")
The suspend issue that we now see on our CI is a new non-gfx issue:
<6> [781.604766] r8169 :06:00.0 enp6s0: Link is Down
<3> [782.752413] e1000e :00:1f.6: PM: pci_pm_suspend():
e1000e_pm_suspend+0x0/0x7a0 [e1000e] returns -2
<3> [782.752427] e1000e :00:1f.6: PM: dpm_run_callback():
pci_pm_suspend+0x0/0x150 returns -2
<3> [782.752436] e1000e :00:1f.6: PM: failed to suspend async: error -2
<3> [782.752492] PM: Some devices failed to suspend, or early wake event
detected
so, on this force_probe protection removal now:
Acked-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 19bf5ef6a20d..bbd3e8befb55 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -926,7 +926,6 @@ static const struct intel_device_info dg1_info = {
> .__runtime.graphics.ip.rel = 10,
> PLATFORM(INTEL_DG1),
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) |
> BIT(PIPE_D),
> - .require_force_probe = 1,
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
> BIT(VCS0) | BIT(VCS2),
> --
> 2.25.1
>
[Intel-gfx] [PATCH] drm/i915/gt: remove some limited use register access wrappers
Remove rmw_set(), rmw_clear(), clear_register(), rmw_set_fw(), and
rmw_clear_fw(). They're just one too many levels of abstraction for
register access, for very specific purposes.
clear_register() seems like a micro-optimization bypassing the write
when the register is already clear, but that trick has ceased to work
since commit 06b975d58fd6 ("drm/i915: make intel_uncore_rmw() write
unconditionally"). Just clear the register in the most obvious way.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/intel_gt.c| 29 +++
drivers/gpu/drm/i915/gt/intel_reset.c | 18 -
2 files changed, 11 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index b5ad9caa5537..efd9d722d77f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -210,21 +210,6 @@ int intel_gt_init_hw(struct intel_gt *gt)
return ret;
}
-static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
-{
- intel_uncore_rmw(uncore, reg, 0, set);
-}
-
-static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
-{
- intel_uncore_rmw(uncore, reg, clr, 0);
-}
-
-static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
-{
- intel_uncore_rmw(uncore, reg, 0, 0);
-}
-
static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
{
GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
@@ -250,14 +235,14 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
u32 eir;
if (GRAPHICS_VER(i915) != 2)
- clear_register(uncore, PGTBL_ER);
+ intel_uncore_write(uncore, PGTBL_ER, 0);
if (GRAPHICS_VER(i915) < 4)
- clear_register(uncore, IPEIR(RENDER_RING_BASE));
+ intel_uncore_write(uncore, IPEIR(RENDER_RING_BASE), 0);
else
- clear_register(uncore, IPEIR_I965);
+ intel_uncore_write(uncore, IPEIR_I965, 0);
- clear_register(uncore, EIR);
+ intel_uncore_write(uncore, EIR, 0);
eir = intel_uncore_read(uncore, EIR);
if (eir) {
/*
@@ -265,7 +250,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
* mask them.
*/
drm_dbg(>i915->drm, "EIR stuck: 0x%08x, masking\n", eir);
- rmw_set(uncore, EMR, eir);
+ intel_uncore_rmw(uncore, EMR, 0, eir);
intel_uncore_write(uncore, GEN2_IIR,
I915_MASTER_ERROR_INTERRUPT);
}
@@ -275,10 +260,10 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
RING_FAULT_VALID, 0);
intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
} else if (GRAPHICS_VER(i915) >= 12) {
- rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
+ intel_uncore_rmw(uncore, GEN12_RING_FAULT_REG,
RING_FAULT_VALID, 0);
intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
} else if (GRAPHICS_VER(i915) >= 8) {
- rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
+ intel_uncore_rmw(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID,
0);
intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
} else if (GRAPHICS_VER(i915) >= 6) {
struct intel_engine_cs *engine;
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 24736ebee17c..ffde89c5835a 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -35,16 +35,6 @@
/* XXX How to handle concurrent GGTT updates using tiling registers? */
#define RESET_UNDER_STOP_MACHINE 0
-static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
-{
- intel_uncore_rmw_fw(uncore, reg, 0, set);
-}
-
-static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
-{
- intel_uncore_rmw_fw(uncore, reg, clr, 0);
-}
-
static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
{
struct drm_i915_file_private *file_priv = ctx->file_priv;
@@ -212,7 +202,7 @@ static int g4x_do_reset(struct intel_gt *gt,
int ret;
/* WaVcpClkGateDisableForMediaReset:ctg,elk */
- rmw_set_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_rmw_fw(uncore, VDECCLK_GATE_D, 0,
VCP_UNIT_CLOCK_GATE_DISABLE);
intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
pci_write_config_byte(pdev, I915_GDRST,
@@ -234,7 +224,7 @@ static int g4x_do_reset(struct intel_gt *gt,
out:
pci_write_config_byte(pdev, I915_GDRST, 0);
- rmw_clear_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_rmw_fw(uncore, VDECCLK_GATE_D,
VCP_UNIT_CLOCK_GATE_DISABLE, 0);
intel_uncore_posting_read_fw(uncore,
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/4] i915: Move list_count() to list.h for broader use
== Series Details ==
Series: series starting with [v4,1/4] i915: Move list_count() to list.h for
broader use
URL : https://patchwork.freedesktop.org/series/111259/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12423 -> Patchwork_111259v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111259v1/index.html
Participating hosts (37 -> 37)
--
Additional (2): fi-cfl-8109u fi-apl-guc
Missing(2): fi-ctg-p8600 fi-ilk-m540
Known issues
Here are the changes found in Patchwork_111259v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: NOTRUN -> [INCOMPLETE][1] ([i915#7073])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111259v1/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111259v1/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111259v1/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-glk-j4005: [PASS][4] -> [DMESG-FAIL][5] ([i915#5334])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12423/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111259v1/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cfl-8109u: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111259v1/fi-cfl-8109u/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +7
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111259v1/fi-apl-guc/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-apl-guc: NOTRUN -> [SKIP][8] ([fdo#109271]) +12 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111259v1/fi-apl-guc/igt@kms_force_connector_ba...@force-connector-state.html
* igt@prime_vgem@basic-userptr:
- fi-cfl-8109u: NOTRUN -> [SKIP][9] ([fdo#109271]) +9 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111259v1/fi-cfl-8109u/igt@prime_v...@basic-userptr.html
Possible fixes
* igt@i915_selftest@live@migrate:
- {bat-dg2-11}: [DMESG-WARN][10] ([i915#7359]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12423/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111259v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html
- {bat-adlp-6}: [INCOMPLETE][12] ([i915#7348]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12423/bat-adlp-6/igt@i915_selftest@l...@migrate.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111259v1/bat-adlp-6/igt@i915_selftest@l...@migrate.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][14] ([i915#4983]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12423/bat-rpls-1/igt@i915_selftest@l...@reset.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111259v1/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@i915_selftest@live@slpc:
- {bat-adln-1}: [DMESG-FAIL][16] ([i915#6997]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12423/bat-adln-1/igt@i915_selftest@l...@slpc.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111259v1/bat-adln-1/igt@i915_selftest@l...@slpc.html
Warnings
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [FAIL][18] ([fdo#103375]) -> [INCOMPLETE][19]
([i915#4817])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12423/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111259v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#2190]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/4] i915: Move list_count() to list.h for broader use
== Series Details == Series: series starting with [v4,1/4] i915: Move list_count() to list.h for broader use URL : https://patchwork.freedesktop.org/series/111259/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [v4,1/4] i915: Move list_count() to list.h for broader use
== Series Details == Series: series starting with [v4,1/4] i915: Move list_count() to list.h for broader use URL : https://patchwork.freedesktop.org/series/111259/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead
Re: [Intel-gfx] [Linaro-mm-sig] Re: [PATCH] dma-buf: Require VM_PFNMAP vma for mmap
On Wed, 23 Nov 2022 at 16:15, Christian König wrote: > > Am 23.11.22 um 16:08 schrieb Jason Gunthorpe: > > On Wed, Nov 23, 2022 at 03:34:54PM +0100, Daniel Vetter wrote: > >>> diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c > >>> index 1376a47fedeedb..4161241fc3228c 100644 > >>> --- a/virt/kvm/kvm_main.c > >>> +++ b/virt/kvm/kvm_main.c > >>> @@ -2598,6 +2598,19 @@ static int hva_to_pfn_remapped(struct > >>> vm_area_struct *vma, > >>> return r; > >>> } > >>> > >>> + /* > >>> +* Special PTEs are never convertible into a struct page, even if > >>> the > >>> +* driver that owns them might have put a PFN with a struct page > >>> into > >>> +* the PFNMAP. If the arch doesn't support special then we cannot > >>> +* safely process these pages. > >>> +*/ > >>> +#ifdef CONFIG_ARCH_HAS_PTE_SPECIAL > >>> + if (pte_special(*ptep)) > >>> + return -EINVAL; > >> On second thought this wont work, because it completely defeats the > >> point of why this code here exists. remap_pfn_range() (which is what > >> the various dma_mmap functions and the ioremap functions are built on > >> top of too) sets VM_PFNMAP too, so this check would even catch the > >> static mappings. > > The problem with the way this code is designed is how it allows > > returning the pfn without taking any reference based on things like > > !pfn_valid or page_reserved. This allows it to then conditionally put > > back the reference based on the same reasoning. It is impossible to > > thread pte special into that since it is a PTE flag, not a property of > > the PFN. > > > > I don't entirely understand why it needs the page reference at all, > > That's exactly what I've pointed out in the previous discussion about > that code as well. > > As far as I can see it this is just another case where people assumed > that grabbing a page reference somehow magically prevents the pte from > changing. > > I have not the slightest idea how people got this impression, but I have > heard it so many time from so many different sources that there must be > some common cause to this. Is the maybe some book or tutorial how to > sophisticate break the kernel or something like this? It's what get_user_pages does, so it does "work". Except this path here is the fallback for when get_user_pages does not work (because of the pte_special/VM_SPECIAL case). So essentially it's just a rather broken get_user_pages that handrolls a bunch of things with bugs I have no idea why people don't realize they're just reinventing gup without using gup, but that's essentially what's going on. > Anyway as far as I can see only correct approach would be to use an MMU > notifier or more high level hmm_range_fault()+seq number. Yeah, plus if you go through ptes you really have to obey all the flags or things will break. Especially the RO pte flag. -Daniel > > Regards, > Christian. > > > even if it is available - so I can't guess why it is OK to ignore the > > page reference in other cases, or why it is OK to be racy.. > > > > Eg hmm_range_fault() does not obtain page references and implements a > > very similar algorithm to kvm. > > > >> Plus these static mappings aren't all that static either, e.g. pci > >> access also can revoke bar mappings nowadays. > > And there are already mmu notifiers to handle that, AFAIK. > > > > Jason > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
Re: [Intel-gfx] [Linaro-mm-sig] Re: [PATCH] dma-buf: Require VM_PFNMAP vma for mmap
On Wed, 23 Nov 2022 at 16:04, Jason Gunthorpe wrote: > > On Wed, Nov 23, 2022 at 03:28:27PM +0100, Daniel Vetter wrote: > > > > This patch is known to be broken in so many ways. It also has a major > > > security hole that it ignores the PTE flags making the page > > > RO. Ignoring the special bit is somehow not surprising :( > > > > > > This probably doesn't work, but is the general idea of what KVM needs > > > to do: > > > > Oh dear, when I dug around in there I entirely missed that > > kvm_try_get_pfn exists, and it's very broken indeed. kvm really needs > > to grow a proper mmu notifier. > > > > Another thing I'm wondering right now, the follow_pte(); > > fixup_user_fault(); follow_pte(); approach does not make any > > guarantees of actually being right. If you're sufficiently unlucky you > > might race against an immediate pte invalidate between the fixup and > > the 2nd follow_pte(). But you can also not loop, because that would > > fail to catch permanent faults. > > Yes, it is pretty broken. > > kvm already has support for mmu notifiers and uses it for other > stuff. I can't remember what exactly this code path was for, IIRC > Paolo talked about having a big rework/fix for it when we last talked > about the missing write protect. I also vauagely recall he had some > explanation why this might be safe. > > > I think the iommu fault drivers have a similar pattern. > > Where? It shouldn't > > The common code for SVA just calls handle_mm_fault() and restarts the > PRI. Since the page table is physically shared there is no issue with > a stale copy. > > > What am I missing here? Or is that also just broken. gup works around > > this with the slow path that takes the mmap sem and walking the vma > > tree, follow_pte/fixup_user_fautl users dont. > > follow_pte() is just fundamentally broken, things must not use it. > > > Maybe mmu notifier based restarting would help with this too, if > > done properly. > > That is called hmm_range_fault() Ah right I mixed that up on a quick grep, thanks for pointing me in the right direction. Worries appeased. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Allow error capture without a request
== Series Details ==
Series: drm/i915: Allow error capture without a request
URL : https://patchwork.freedesktop.org/series/111224/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12418_full -> Patchwork_111224v1_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_111224v1_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_111224v1_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111224v1_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_suspend@basic-s3@smem:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12418/shard-tglb1/igt@gem_exec_suspend@basic...@smem.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111224v1/shard-tglb3/igt@gem_exec_suspend@basic...@smem.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a4:
- {shard-dg1}:[PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12418/shard-dg1-15/igt@kms_flip@flip-vs-expired-vbl...@a-hdmi-a4.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111224v1/shard-dg1-17/igt@kms_flip@flip-vs-expired-vbl...@a-hdmi-a4.html
Known issues
Here are the changes found in Patchwork_111224v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#6268])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12418/shard-tglb5/igt@gem_ctx_e...@basic-nohangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111224v1/shard-tglb5/igt@gem_ctx_e...@basic-nohangcheck.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#4525])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12418/shard-iclb2/igt@gem_exec_balan...@parallel-bb-first.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111224v1/shard-iclb5/igt@gem_exec_balan...@parallel-bb-first.html
* igt@gem_exec_endless@dispatch@vcs0:
- shard-tglb: [PASS][9] -> [TIMEOUT][10] ([i915#3778])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12418/shard-tglb5/igt@gem_exec_endless@dispa...@vcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111224v1/shard-tglb6/igt@gem_exec_endless@dispa...@vcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12418/shard-apl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111224v1/shard-apl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12418/shard-glk5/igt@gem_exec_fair@basic-n...@vcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111224v1/shard-glk9/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111224v1/shard-apl1/igt@gem_lmem_swapp...@heavy-multi.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [INCOMPLETE][16] ([i915#7248])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111224v1/shard-apl1/igt@gem_pwr...@basic-exhaustion.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#5566] /
[i915#716])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12418/shard-glk1/igt@gen9_exec_pa...@allowed-single.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111224v1/shard-glk2/igt@gen9_exec_pa...@allowed-single.html
* igt@i915_module_load@reload-no-display:
- shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([i915#2867]) +2
similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12418/shard-iclb8/igt@i915_module_l...@reload-no-display.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111224v1/shard-iclb6/igt@i915_module_l...@reload-no-display.html
* igt@i915_pipe_stress@stress-xrgb-untiled:
- shard-apl: NOTRUN ->
Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: Never return 0 if not all requests retired
On 21.11.2022 15:56, Janusz Krzysztofik wrote:
Users of intel_gt_retire_requests_timeout() expect 0 return value on
success. However, we have no protection from passing back 0 potentially
returned by a call to dma_fence_wait_timeout() when it succedes right
after its timeout has expired.
Replace 0 with -ETIME before potentially using the timeout value as return
code, so -ETIME is returned if there are still some requests not retired
after timeout, 0 otherwise.
v3: Use conditional expression, more compact but also better reflecting
intention standing behind the change.
v2: Move the added lines down so flush_submission() is not affected.
Fixes: f33a8a51602c ("drm/i915: Merge wait_for_timelines with retire_request")
Signed-off-by: Janusz Krzysztofik
Reviewed-by: Andrzej Hajda
I confirm my r-b.
Regards
Andrzej
Cc: sta...@vger.kernel.org # v5.5+
---
drivers/gpu/drm/i915/gt/intel_gt_requests.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
index edb881d756309..1dfd01668c79c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
@@ -199,7 +199,7 @@ out_active: spin_lock(>lock);
if (remaining_timeout)
*remaining_timeout = timeout;
- return active_count ? timeout : 0;
+ return active_count ? timeout ?: -ETIME : 0;
}
static void retire_work_handler(struct work_struct *work)
[Intel-gfx] [PATCH 01/13] drm/i915: Shorten GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED a bit
From: Ville Syrjälä s/GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED/GAMMA_MODE_MODE_12BIT_MULTI_SEG/ to make this thing slightly shorter. Also fix up the platform comment while at it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 10 +- drivers/gpu/drm/i915/i915_reg.h| 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 842d58da3128..956b221860e6 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1212,7 +1212,7 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) case GAMMA_MODE_MODE_8BIT: ilk_load_lut_8(crtc, post_csc_lut); break; - case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: + case GAMMA_MODE_MODE_12BIT_MULTI_SEG: icl_program_gamma_superfine_segment(crtc_state); icl_program_gamma_multi_segment(crtc_state); ivb_load_lut_ext_max(crtc_state); @@ -2091,7 +2091,7 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) else if (DISPLAY_VER(i915) >= 13) gamma_mode |= GAMMA_MODE_MODE_10BIT; else - gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED; + gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEG; return gamma_mode; } @@ -2283,7 +2283,7 @@ static int icl_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) return 8; case GAMMA_MODE_MODE_10BIT: return 10; - case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: + case GAMMA_MODE_MODE_12BIT_MULTI_SEG: return 16; default: MISSING_CASE(crtc_state->gamma_mode); @@ -2455,7 +2455,7 @@ static bool icl_lut_equal(const struct intel_crtc_state *crtc_state, /* hw readout broken except for the super fine segment :( */ if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) == - GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED) + GAMMA_MODE_MODE_12BIT_MULTI_SEG) check_size = 9; return intel_lut_equal(blob1, blob2, check_size, @@ -2971,7 +2971,7 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state) case GAMMA_MODE_MODE_10BIT: crtc_state->post_csc_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); break; - case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: + case GAMMA_MODE_MODE_12BIT_MULTI_SEG: crtc_state->post_csc_lut = icl_read_lut_multi_segment(crtc); break; default: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0b90fe6a28f7..b1c314093737 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5316,7 +5316,7 @@ #define GAMMA_MODE_MODE_10BIT (1 << 0) #define GAMMA_MODE_MODE_12BIT (2 << 0) #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ -#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ +#define GAMMA_MODE_MODE_12BIT_MULTI_SEG (3 << 0) /* icl-tgl */ /* Display Internal Timeout Register */ #define RM_TIMEOUT _MMIO(0x42060) -- 2.37.4
[Intel-gfx] [PATCH 10/13] drm/i915: Disable DSB usage specifically for LUTs
From: Ville Syrjälä
The DSB has problem loading the LUTs at the moment. Some
of that is due to the palette anti collision logic, some
due to what seem real hw issues. Disable it the whole
thing locally in the color management code for now.
Note that we currently have this weird situation where on
adl+ we load parts of the LUT with DSB and parts with mmio.
That is due to the fact that only some parts of the LUT code
are using the DSB register write functions (ivb_load_lut_ext*()),
while the rest is using pure mmio (bdw_load_lut_10()). So now
we'll go back to pure mmio temporarily, until the DSB issues
get fixed (at which point we should be going for pure DSB).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 2715f1b617e1..9978d21f1634 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1394,6 +1394,9 @@ void intel_color_prepare_commit(struct intel_crtc_state
*crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ /* FIXME DSB has issues loading LUTs, disable it for now */
+ return;
+
crtc_state->dsb = intel_dsb_prepare(crtc);
}
--
2.37.4
[Intel-gfx] [PATCH 09/13] drm/i915: Make DSB lower level
From: Ville Syrjälä
We could have many different uses for the DSB(s) during a
single commit, so the current approach of passing the whole
crtc_state to the DSB functions is far too high level. Lower
the abstraction a little bit so each DSB user can decide where
to stick the command buffer/etc.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 17 +++--
drivers/gpu/drm/i915/display/intel_dsb.c | 79 ++
drivers/gpu/drm/i915/display/intel_dsb.h | 13 ++--
3 files changed, 55 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 5a8652407f30..2715f1b617e1 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -842,7 +842,7 @@ static void ilk_lut_write(const struct intel_crtc_state
*crtc_state,
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
if (crtc_state->dsb)
- intel_dsb_reg_write(crtc_state, reg, val);
+ intel_dsb_reg_write(crtc_state->dsb, reg, val);
else
intel_de_write_fw(i915, reg, val);
}
@@ -853,7 +853,7 @@ static void ilk_lut_write_indexed(const struct
intel_crtc_state *crtc_state,
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
if (crtc_state->dsb)
- intel_dsb_indexed_reg_write(crtc_state, reg, val);
+ intel_dsb_indexed_reg_write(crtc_state->dsb, reg, val);
else
intel_de_write_fw(i915, reg, val);
}
@@ -1273,7 +1273,8 @@ static void icl_load_luts(const struct intel_crtc_state
*crtc_state)
break;
}
- intel_dsb_commit(crtc_state);
+ if (crtc_state->dsb)
+ intel_dsb_commit(crtc_state->dsb);
}
static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
@@ -1391,12 +1392,18 @@ void intel_color_commit_arm(const struct
intel_crtc_state *crtc_state)
void intel_color_prepare_commit(struct intel_crtc_state *crtc_state)
{
- intel_dsb_prepare(crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ crtc_state->dsb = intel_dsb_prepare(crtc);
}
void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)
{
- intel_dsb_cleanup(crtc_state);
+ if (!crtc_state->dsb)
+ return;
+
+ intel_dsb_cleanup(crtc_state->dsb);
+ crtc_state->dsb = NULL;
}
static bool intel_can_preload_luts(const struct intel_crtc_state
*new_crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index b4f0356c2463..ab74bfc89465 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -24,8 +24,10 @@ enum dsb_id {
struct intel_dsb {
enum dsb_id id;
+
u32 *cmd_buf;
struct i915_vma *vma;
+ struct intel_crtc *crtc;
/*
* free_pos will point the first free entry position
@@ -113,7 +115,7 @@ static bool intel_dsb_disable_engine(struct
drm_i915_private *i915,
/**
* intel_dsb_indexed_reg_write() -Write to the DSB context for auto
* increment register.
- * @crtc_state: intel_crtc_state structure
+ * @dsb: DSB context
* @reg: register address.
* @val: value.
*
@@ -123,11 +125,10 @@ static bool intel_dsb_disable_engine(struct
drm_i915_private *i915,
* is done through mmio write.
*/
-void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state,
+void intel_dsb_indexed_reg_write(struct intel_dsb *dsb,
i915_reg_t reg, u32 val)
{
- struct intel_dsb *dsb = crtc_state->dsb;
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct intel_crtc *crtc = dsb->crtc;
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 *buf = dsb->cmd_buf;
u32 reg_val;
@@ -195,12 +196,11 @@ void intel_dsb_indexed_reg_write(const struct
intel_crtc_state *crtc_state,
* and rest all erroneous condition register programming is done
* through mmio write.
*/
-void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state,
+void intel_dsb_reg_write(struct intel_dsb *dsb,
i915_reg_t reg, u32 val)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct intel_crtc *crtc = dsb->crtc;
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_dsb *dsb = crtc_state->dsb;
u32 *buf = dsb->cmd_buf;
if (drm_WARN_ON(_priv->drm, dsb->free_pos >= DSB_BUF_SIZE)) {
@@ -217,17 +217,14 @@ void intel_dsb_reg_write(const struct intel_crtc_state
*crtc_state,
/**
* intel_dsb_commit() - Trigger workload execution of DSB.
- * @crtc_state: intel_crtc_state structure
+ * @dsb: DSB context
*
* This function is used to do actual write to hardware using DSB.
- * On
[Intel-gfx] [PATCH 11/13] Revert "drm/i915: Disable DSB usage for now"
From: Ville Syrjälä
This reverts commit 99510e1afb4863a225207146bd988064c5fd0629.
DSB is now getting disabled locally in the color management
code so we don't need to apply this big hammer via the device
info (not that we have other DSB users at the moment).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 414b4bfd514b..d8f0f512c944 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -889,7 +889,7 @@ static const struct intel_device_info jsl_info = {
TGL_CURSOR_OFFSETS, \
.has_global_mocs = 1, \
.has_pxp = 1, \
- .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */
+ .display.has_dsb = 1
static const struct intel_device_info tgl_info = {
GEN12_FEATURES,
--
2.37.4
[Intel-gfx] [PATCH 07/13] drm/i915: Move the DSB->mmio fallback into the LUT code
From: Ville Syrjälä
The use of DSB has to be done differently on a case by case basis.
So no way this kind of blind mmio fallback in the guts of the DSB
code will work properly. Move it at least one level up into the
LUT loading code. Not sure if this is the way we want do the
DSB vs. mmio handling in the end, but at least it's a bit
closer than what we had before.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 94 ++
drivers/gpu/drm/i915/display/intel_dsb.c | 18 +
2 files changed, 62 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index bd7e781d9d07..5a4f794e1d08 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -836,6 +836,28 @@ static void i965_load_luts(const struct intel_crtc_state
*crtc_state)
}
}
+static void ilk_lut_write(const struct intel_crtc_state *crtc_state,
+ i915_reg_t reg, u32 val)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+
+ if (crtc_state->dsb)
+ intel_dsb_reg_write(crtc_state, reg, val);
+ else
+ intel_de_write_fw(i915, reg, val);
+}
+
+static void ilk_lut_write_indexed(const struct intel_crtc_state *crtc_state,
+ i915_reg_t reg, u32 val)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+
+ if (crtc_state->dsb)
+ intel_dsb_indexed_reg_write(crtc_state, reg, val);
+ else
+ intel_de_write_fw(i915, reg, val);
+}
+
static void ilk_load_lut_8(struct intel_crtc *crtc,
const struct drm_property_blob *blob)
{
@@ -958,9 +980,9 @@ static void ivb_load_lut_ext_max(const struct
intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
/* Program the max register to clamp values > 1.0. */
- intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
- intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
- intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
+ ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
+ ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
+ ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
}
static void glk_load_lut_ext2_max(const struct intel_crtc_state *crtc_state)
@@ -969,9 +991,9 @@ static void glk_load_lut_ext2_max(const struct
intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
/* Program the max register to clamp values > 1.0. */
- intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);
- intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);
- intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);
+ ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);
+ ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);
+ ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);
}
static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
@@ -1118,9 +1140,9 @@ ivb_load_lut_max(const struct intel_crtc_state
*crtc_state,
enum pipe pipe = crtc->pipe;
/* FIXME LUT entries are 16 bit only, so we can prog 0x max */
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red);
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green);
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red);
+ ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green);
+ ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue);
}
static void
@@ -1139,23 +1161,23 @@ icl_program_gamma_superfine_segment(const struct
intel_crtc_state *crtc_state)
* 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
* 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
*/
- intel_dsb_reg_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),
- PAL_PREC_MULTI_SEG_INDEX_VALUE(0));
- intel_dsb_reg_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),
- PAL_PREC_AUTO_INCREMENT |
- PAL_PREC_MULTI_SEG_INDEX_VALUE(0));
+ ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),
+ PAL_PREC_MULTI_SEG_INDEX_VALUE(0));
+ ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),
+ PAL_PREC_AUTO_INCREMENT |
+ PAL_PREC_MULTI_SEG_INDEX_VALUE(0));
for (i = 0; i < 9; i++) {
const struct drm_color_lut *entry = [i];
- intel_dsb_indexed_reg_write(crtc_state,
[Intel-gfx] [PATCH 03/13] drm/i915: Define skl+ palette anti-collision bit
From: Ville Syrjälä I've been frobbing the palette anti-collision logic bit while playing around with DSB. Not sure we'll have real use for this but let's define the bit anyways so I don't have to carry it around locally. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 52d289f55ce1..80ac50d80af4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5311,6 +5311,7 @@ #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) #define PRE_CSC_GAMMA_ENABLE REG_BIT(31) /* icl+ */ #define POST_CSC_GAMMA_ENABLE REG_BIT(30) /* icl+ */ +#define PALETTE_ANTICOL_DISABLE REG_BIT(15) /* skl+ */ #define GAMMA_MODE_MODE_MASK REG_GENMASK(1, 0) #define GAMMA_MODE_MODE_8BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 0) #define GAMMA_MODE_MODE_10BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 1) -- 2.37.4
[Intel-gfx] [PATCH 13/13] drm/i915: Do state check for color management changes
From: Ville Syrjälä
In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.
Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening. Maybe we should have
an extra knob for this that we could enable in CI?
v2: Skip for initial_commit to avoid FDI dotclock
sanity checks/etc. tripping up
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_modeset_verify.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 842d70f0dfd2..9e4767e1b900 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -228,6 +228,8 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc,
struct intel_crtc_state *new_crtc_state)
{
if (!intel_crtc_needs_modeset(new_crtc_state) &&
+ (!intel_crtc_needs_color_update(new_crtc_state) ||
+new_crtc_state->inherited) &&
!intel_crtc_needs_fastset(new_crtc_state))
return;
--
2.37.4
[Intel-gfx] [PATCH 06/13] drm/i915: Document LUT "max" register precision
From: Ville Syrjälä
Document the precision of the LUT "max" registers, just
so we don't have to dig through the spec so much.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 22fb9fd78483..cd0a445814c7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3620,7 +3620,7 @@
#define _PIPEAGCMAX 0x70010
#define _PIPEBGCMAX 0x71010
-#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
+#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) /*
u1.16 */
#define _PIPE_ARB_CTL_A0x70028 /* icl+ */
#define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A)
@@ -5304,7 +5304,7 @@
#define _PREC_PIPEAGCMAX 0x4d000
#define _PREC_PIPEBGCMAX 0x4d010
-#define PREC_PIPEGCMAX(pipe, i)_MMIO(_PIPE(pipe, _PIPEAGCMAX,
_PIPEBGCMAX) + (i) * 4)
+#define PREC_PIPEGCMAX(pipe, i)_MMIO(_PIPE(pipe, _PIPEAGCMAX,
_PIPEBGCMAX) + (i) * 4) /* u1.16 */
#define _GAMMA_MODE_A 0x4a480
#define _GAMMA_MODE_B 0x4ac80
@@ -7551,9 +7551,9 @@ enum skl_power_gate {
#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A,
_PAL_PREC_INDEX_B)
#define PREC_PAL_DATA(pipe)_MMIO_PIPE(pipe, _PAL_PREC_DATA_A,
_PAL_PREC_DATA_B)
-#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A,
_PAL_PREC_GC_MAX_B) + (i) * 4)
-#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
_PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
-#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
_PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
+#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A,
_PAL_PREC_GC_MAX_B) + (i) * 4) /* u1.16 */
+#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
_PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) /* u3.16 */
+#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
_PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) /* glk+, u3.16 */
#define _PRE_CSC_GAMC_INDEX_A 0x4A484
#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
--
2.37.4
[Intel-gfx] [PATCH 12/13] drm/i915: Use ilk_lut_write*() for all ilk+ gamma modes
From: Ville Syrjälä
We could use the dsb to load the LUT in any gamma mode, not just
when using the multi-segment mode. So replace the direct mmio
on all ilk+ paths with the wrapper.
There are a few functions (ilk_load_lut_10(), ivb_load_lut_10())
that would never be used on a platform with dsb so we could
skip those, but probably better to keep all this 100% consistent
to avoid people getting confused and copy pasting the wrong thing
when adding a new gamma mode.
The gmch stuff I left with direct mmio since those are fairly
distinct and shouldn't cause too much confusion. Although
I've also pondered about converting everything over to dsb
command buffers and just executing it on the CPU when the
real hw is not available. But dunno if that would actually
be a good idea or not...
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 106 ++---
1 file changed, 50 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 9978d21f1634..d57631b0bb9a 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -858,10 +858,10 @@ static void ilk_lut_write_indexed(const struct
intel_crtc_state *crtc_state,
intel_de_write_fw(i915, reg, val);
}
-static void ilk_load_lut_8(struct intel_crtc *crtc,
+static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state,
const struct drm_property_blob *blob)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
const struct drm_color_lut *lut;
enum pipe pipe = crtc->pipe;
int i;
@@ -872,36 +872,35 @@ static void ilk_load_lut_8(struct intel_crtc *crtc,
lut = blob->data;
for (i = 0; i < 256; i++)
- intel_de_write_fw(i915, LGC_PALETTE(pipe, i),
- i9xx_lut_8([i]));
+ ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
+ i9xx_lut_8([i]));
}
-static void ilk_load_lut_10(struct intel_crtc *crtc,
+static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state,
const struct drm_property_blob *blob)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
const struct drm_color_lut *lut = blob->data;
int i, lut_size = drm_color_lut_size(blob);
enum pipe pipe = crtc->pipe;
for (i = 0; i < lut_size; i++)
- intel_de_write_fw(i915, PREC_PALETTE(pipe, i),
- ilk_lut_10([i]));
+ ilk_lut_write(crtc_state, PREC_PALETTE(pipe, i),
+ ilk_lut_10([i]));
}
static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
const struct drm_property_blob *blob = post_csc_lut ?: pre_csc_lut;
switch (crtc_state->gamma_mode) {
case GAMMA_MODE_MODE_8BIT:
- ilk_load_lut_8(crtc, blob);
+ ilk_load_lut_8(crtc_state, blob);
break;
case GAMMA_MODE_MODE_10BIT:
- ilk_load_lut_10(crtc, blob);
+ ilk_load_lut_10(crtc_state, blob);
break;
default:
MISSING_CASE(crtc_state->gamma_mode);
@@ -922,56 +921,56 @@ static int ivb_lut_10_size(u32 prec_index)
* "Restriction : Index auto increment mode is not
* supported and must not be enabled."
*/
-static void ivb_load_lut_10(struct intel_crtc *crtc,
+static void ivb_load_lut_10(const struct intel_crtc_state *crtc_state,
const struct drm_property_blob *blob,
u32 prec_index)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
const struct drm_color_lut *lut = blob->data;
int i, lut_size = drm_color_lut_size(blob);
enum pipe pipe = crtc->pipe;
for (i = 0; i < lut_size; i++) {
- intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
- prec_index + i);
- intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
- ilk_lut_10([i]));
+ ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
+ prec_index + i);
+ ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe),
+ ilk_lut_10([i]));
}
/*
* Reset the index, otherwise it prevents the legacy palette to be
* written properly.
