[Intel-gfx] [PATCH v3 9/9] drm/i915: Improve PPS debugs
From: Ville Syrjälä
Always include both the encoder and PPS instance information
in the debug prints so that we know what piece of hardware
we're actually dealing with.
v2: Make sure pps is selected before debug prints/etc. in
intel_pps_vdd_on_unlocked() on vlv/chv
There is no pps on pipe C on chv
Cc: Animesh Manna
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_pps.c | 188 +++
1 file changed, 122 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 880c530d5832..44f4d801c6bd 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -22,6 +22,34 @@ static void vlv_steal_power_sequencer(struct
drm_i915_private *dev_priv,
static void pps_init_delays(struct intel_dp *intel_dp);
static void pps_init_registers(struct intel_dp *intel_dp, bool
force_disable_vdd);
+static const char *pps_name(struct drm_i915_private *i915,
+ struct intel_pps *pps)
+{
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+ switch (pps->pps_pipe) {
+ case PIPE_A:
+ return "PPS A";
+ case PIPE_B:
+ return "PPS B";
+ default:
+ MISSING_CASE(pps->pps_pipe);
+ break;
+ }
+ } else {
+ switch (pps->pps_idx) {
+ case 0:
+ return "PPS 0";
+ case 1:
+ return "PPS 1";
+ default:
+ MISSING_CASE(pps->pps_idx);
+ break;
+ }
+ }
+
+ return "PPS ";
+}
+
intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -60,15 +88,15 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
if (drm_WARN(&dev_priv->drm,
intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
-"skipping pipe %c power sequencer kick due to
[ENCODER:%d:%s] being active\n",
-pipe_name(pipe), dig_port->base.base.base.id,
-dig_port->base.base.name))
+"skipping %s kick due to [ENCODER:%d:%s] being active\n",
+pps_name(dev_priv, &intel_dp->pps),
+dig_port->base.base.base.id, dig_port->base.base.name))
return;
drm_dbg_kms(&dev_priv->drm,
- "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
- pipe_name(pipe), dig_port->base.base.base.id,
- dig_port->base.base.name);
+ "kicking %s for [ENCODER:%d:%s]\n",
+ pps_name(dev_priv, &intel_dp->pps),
+ dig_port->base.base.base.id, dig_port->base.base.name);
/* Preserve the BIOS-computed detected bit. This is
* supposed to be read-only.
@@ -95,7 +123,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
drm_err(&dev_priv->drm,
- "Failed to force on pll for pipe %c!\n",
+ "Failed to force on PLL for pipe %c!\n",
pipe_name(pipe));
return;
}
@@ -190,10 +218,9 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
intel_dp->pps.pps_pipe = pipe;
drm_dbg_kms(&dev_priv->drm,
- "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
- pipe_name(intel_dp->pps.pps_pipe),
- dig_port->base.base.base.id,
- dig_port->base.base.name);
+ "picked %s for [ENCODER:%d:%s]\n",
+ pps_name(dev_priv, &intel_dp->pps),
+ dig_port->base.base.base.id, dig_port->base.base.name);
/* init power sequencer on this pipe and port */
pps_init_delays(intel_dp);
@@ -297,17 +324,15 @@ vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp)
/* didn't find one? just let vlv_power_sequencer_pipe() pick one when
needed */
if (intel_dp->pps.pps_pipe == INVALID_PIPE) {
drm_dbg_kms(&dev_priv->drm,
- "no initial power sequencer for [ENCODER:%d:%s]\n",
- dig_port->base.base.base.id,
- dig_port->base.base.name);
+ "[ENCODER:%d:%s] no initial power sequencer\n",
+ dig_port->base.base.base.id,
dig_port->base.base.name);
return;
}
drm_dbg_kms(&dev_priv->drm,
- "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
- dig_port->base.base.base.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fake dual eDP VBT fixes (rev3)
== Series Details == Series: drm/i915: Fake dual eDP VBT fixes (rev3) URL : https://patchwork.freedesktop.org/series/110693/ State : warning == Summary == Error: dim checkpatch failed 75c8e4541d7c drm/i915: Introduce intel_panel_init_alloc() 175ec6587f67 drm/i915: Do panel VBT init early if the VBT declares an explicit panel type b2c65996e56d drm/i915: Generalize the PPS vlv_pipe_check() stuff b1641bb0a6e7 drm/i915: Try to use the correct power sequencer intiially on bxt/glk 47fc67e06f24 drm/i915: Extend dual PPS handlind for ICP+ 215613ee31ae drm/i915: Reject unusablee power sequencers 6b2987422b20 drm/i915: Print the PPS registers using consistent format d41bcff953c5 drm/i915: Fix whitespace -:23: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #23: FILE: drivers/gpu/drm/i915/display/intel_pps.c:538: +#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) total: 0 errors, 1 warnings, 0 checks, 8 lines checked 1af1f53c850c drm/i915: Improve PPS debugs
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fake dual eDP VBT fixes (rev3)
== Series Details ==
Series: drm/i915: Fake dual eDP VBT fixes (rev3)
URL : https://patchwork.freedesktop.org/series/110693/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12435 -> Patchwork_110693v3
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_110693v3 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_110693v3, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v3/index.html
Participating hosts (36 -> 31)
--
Additional (1): fi-adl-ddr5
Missing(6): fi-kbl-7567u fi-snb-2520m fi-ctg-p8600 fi-glk-j4005
fi-ivb-3770 fi-kbl-8809g
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_110693v3:
### IGT changes ###
Possible regressions
* igt@i915_pm_rpm@module-reload:
- fi-bsw-kefka: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12435/fi-bsw-kefka/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v3/fi-bsw-kefka/igt@i915_pm_...@module-reload.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_suspend@basic-s2idle-without-i915:
- {bat-rpls-1}: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12435/bat-rpls-1/igt@i915_susp...@basic-s2idle-without-i915.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v3/bat-rpls-1/igt@i915_susp...@basic-s2idle-without-i915.html
Known issues
Here are the changes found in Patchwork_110693v3 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [PASS][5] -> [INCOMPLETE][6] ([i915#7073])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12435/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v3/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
* igt@debugfs_test@basic-hwmon:
- fi-adl-ddr5:NOTRUN -> [SKIP][7] ([i915#7456])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v3/fi-adl-ddr5/igt@debugfs_t...@basic-hwmon.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-adl-ddr5:NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v3/fi-adl-ddr5/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_tiled_pread_basic:
- fi-adl-ddr5:NOTRUN -> [SKIP][9] ([i915#3282])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v3/fi-adl-ddr5/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-adl-ddr5:NOTRUN -> [SKIP][10] ([i915#7561])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v3/fi-adl-ddr5/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-adl-ddr5:NOTRUN -> [DMESG-WARN][11] ([i915#5591])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v3/fi-adl-ddr5/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-4770:[PASS][12] -> [INCOMPLETE][13] ([i915#4785])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12435/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v3/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@dp-edid-read:
- fi-adl-ddr5:NOTRUN -> [SKIP][14] ([fdo#111827]) +8 similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v3/fi-adl-ddr5/igt@kms_chamel...@dp-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-adl-ddr5:NOTRUN -> [SKIP][15] ([i915#4103])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v3/fi-adl-ddr5/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-adl-ddr5:NOTRUN -> [SKIP][16] ([fdo#109285])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v3/fi-adl-ddr5/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_psr@cursor_plane_move:
- fi-adl-ddr5:NOTRUN -> [SKIP][17] ([i915#1072]) +3 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v3/fi-adl-ddr5/igt@kms_psr@cursor_plane_move.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-adl-ddr5:NOTRUN -> [SKIP][18] ([i915#3555])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v3/fi
[Intel-gfx] [PATCH v4 9/9] drm/i915: Improve PPS debugs
From: Ville Syrjälä
Always include both the encoder and PPS instance information
in the debug prints so that we know what piece of hardware
we're actually dealing with.
v2: Make sure pps is selected before debug prints/etc. in
intel_pps_vdd_on_unlocked() on vlv/chv
There is no pps on pipe C on chv
v3: Allow PPS=INVALID_PIPE for vlv/chv
Cc: Animesh Manna
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_pps.c | 194 +++
1 file changed, 128 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 880c530d5832..7b21438edd9b 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -22,6 +22,40 @@ static void vlv_steal_power_sequencer(struct
drm_i915_private *dev_priv,
static void pps_init_delays(struct intel_dp *intel_dp);
static void pps_init_registers(struct intel_dp *intel_dp, bool
force_disable_vdd);
+static const char *pps_name(struct drm_i915_private *i915,
+ struct intel_pps *pps)
+{
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+ switch (pps->pps_pipe) {
+ case INVALID_PIPE:
+ /*
+* FIXME would be nice if we can guarantee
+* to always have a valid PPS when calling this.
+*/
+ return "PPS ";
+ case PIPE_A:
+ return "PPS A";
+ case PIPE_B:
+ return "PPS B";
+ default:
+ MISSING_CASE(pps->pps_pipe);
+ break;
+ }
+ } else {
+ switch (pps->pps_idx) {
+ case 0:
+ return "PPS 0";
+ case 1:
+ return "PPS 1";
+ default:
+ MISSING_CASE(pps->pps_idx);
+ break;
+ }
+ }
+
+ return "PPS ";
+}
+
intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -60,15 +94,15 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
if (drm_WARN(&dev_priv->drm,
intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
-"skipping pipe %c power sequencer kick due to
[ENCODER:%d:%s] being active\n",
-pipe_name(pipe), dig_port->base.base.base.id,
-dig_port->base.base.name))
+"skipping %s kick due to [ENCODER:%d:%s] being active\n",
+pps_name(dev_priv, &intel_dp->pps),
+dig_port->base.base.base.id, dig_port->base.base.name))
return;
drm_dbg_kms(&dev_priv->drm,
- "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
- pipe_name(pipe), dig_port->base.base.base.id,
- dig_port->base.base.name);
+ "kicking %s for [ENCODER:%d:%s]\n",
+ pps_name(dev_priv, &intel_dp->pps),
+ dig_port->base.base.base.id, dig_port->base.base.name);
/* Preserve the BIOS-computed detected bit. This is
* supposed to be read-only.
@@ -95,7 +129,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
drm_err(&dev_priv->drm,
- "Failed to force on pll for pipe %c!\n",
+ "Failed to force on PLL for pipe %c!\n",
pipe_name(pipe));
return;
}
@@ -190,10 +224,9 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
intel_dp->pps.pps_pipe = pipe;
drm_dbg_kms(&dev_priv->drm,
- "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
- pipe_name(intel_dp->pps.pps_pipe),
- dig_port->base.base.base.id,
- dig_port->base.base.name);
+ "picked %s for [ENCODER:%d:%s]\n",
+ pps_name(dev_priv, &intel_dp->pps),
+ dig_port->base.base.base.id, dig_port->base.base.name);
/* init power sequencer on this pipe and port */
pps_init_delays(intel_dp);
@@ -297,17 +330,15 @@ vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp)
/* didn't find one? just let vlv_power_sequencer_pipe() pick one when
needed */
if (intel_dp->pps.pps_pipe == INVALID_PIPE) {
drm_dbg_kms(&dev_priv->drm,
- "no initial power sequencer for [ENCODER:%d:%s]\n",
- dig_port->base.base.base.id,
- dig_port->base.base.name);
+ "[ENCODER:%d:%s] no
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fake dual eDP VBT fixes (rev4)
== Series Details == Series: drm/i915: Fake dual eDP VBT fixes (rev4) URL : https://patchwork.freedesktop.org/series/110693/ State : warning == Summary == Error: dim checkpatch failed 8a03452322e7 drm/i915: Introduce intel_panel_init_alloc() 3098cd62da06 drm/i915: Do panel VBT init early if the VBT declares an explicit panel type 65cca7eeeadc drm/i915: Generalize the PPS vlv_pipe_check() stuff a207c294313f drm/i915: Try to use the correct power sequencer intiially on bxt/glk 4782674843b2 drm/i915: Extend dual PPS handlind for ICP+ e2fb74bd91fb drm/i915: Reject unusablee power sequencers 7e8f697f249c drm/i915: Print the PPS registers using consistent format 50fae29aa77a drm/i915: Fix whitespace -:23: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #23: FILE: drivers/gpu/drm/i915/display/intel_pps.c:538: +#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) total: 0 errors, 1 warnings, 0 checks, 8 lines checked e63545ffbd4d drm/i915: Improve PPS debugs
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fake dual eDP VBT fixes (rev4)
== Series Details ==
Series: drm/i915: Fake dual eDP VBT fixes (rev4)
URL : https://patchwork.freedesktop.org/series/110693/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12435 -> Patchwork_110693v4
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/index.html
Participating hosts (36 -> 30)
--
Additional (1): fi-adl-ddr5
Missing(7): fi-kbl-7567u bat-dg1-6 fi-snb-2520m fi-ctg-p8600 fi-glk-j4005
fi-ivb-3770 fi-kbl-8809g
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_110693v4:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rpls-1}: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12435/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
Known issues
Here are the changes found in Patchwork_110693v4 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- fi-adl-ddr5:NOTRUN -> [SKIP][3] ([i915#7456])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/fi-adl-ddr5/igt@debugfs_t...@basic-hwmon.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-adl-ddr5:NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/fi-adl-ddr5/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_tiled_pread_basic:
- fi-adl-ddr5:NOTRUN -> [SKIP][5] ([i915#3282])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/fi-adl-ddr5/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-adl-ddr5:NOTRUN -> [SKIP][6] ([i915#7561])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/fi-adl-ddr5/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-adl-ddr5:NOTRUN -> [DMESG-WARN][7] ([i915#5591])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/fi-adl-ddr5/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@dp-edid-read:
- fi-adl-ddr5:NOTRUN -> [SKIP][8] ([fdo#111827]) +8 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/fi-adl-ddr5/igt@kms_chamel...@dp-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-adl-ddr5:NOTRUN -> [SKIP][9] ([i915#4103])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/fi-adl-ddr5/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-adl-ddr5:NOTRUN -> [SKIP][10] ([fdo#109285])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/fi-adl-ddr5/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_psr@cursor_plane_move:
- fi-adl-ddr5:NOTRUN -> [SKIP][11] ([i915#1072]) +3 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/fi-adl-ddr5/igt@kms_psr@cursor_plane_move.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-adl-ddr5:NOTRUN -> [SKIP][12] ([i915#3555])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/fi-adl-ddr5/igt@kms_setm...@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-adl-ddr5:NOTRUN -> [SKIP][13] ([fdo#109295] / [i915#3301])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/fi-adl-ddr5/igt@prime_v...@basic-userptr.html
* igt@prime_vgem@basic-write:
- fi-adl-ddr5:NOTRUN -> [SKIP][14] ([fdo#109295] / [i915#3291]) +2
similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/fi-adl-ddr5/igt@prime_v...@basic-write.html
Possible fixes
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][15] ([i915#2867]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12435/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_module_load@load:
- fi-bsw-kefka: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12435/fi-bsw-kefka/igt@i915_module_l...@load.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v4/fi-bsw-kefka/igt@i915_module_l...@load.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][19] ([i915#5334]) -
Re: [Intel-gfx] [PATCH 1/9] drm/amdgpu: generally allow over-commit during BO allocation
Hi Christian,
Looks good to me.
Reviewed-by: Arunpravin Paneer Selvam
for the series.
Regards,
Arun.
On 11/25/2022 3:51 PM, Christian König wrote:
We already fallback to a dummy BO with no backing store when we
allocate GDS,GWS and OA resources and to GTT when we allocate VRAM.
Drop all those workarounds and generalize this for GTT as well. This
fixes ENOMEM issues with runaway applications which try to allocate/free
GTT in a loop and are otherwise only limited by the CPU speed.
The CS will wait for the cleanup of freed up BOs to satisfy the
various domain specific limits and so effectively throttle those
buggy applications down to a sane allocation behavior again.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 16 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 +-
2 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index a0780a4e3e61..62e98f1ad770 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -113,7 +113,7 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev,
unsigned long size,
bp.resv = resv;
bp.preferred_domain = initial_domain;
bp.flags = flags;
- bp.domain = initial_domain;
+ bp.domain = initial_domain | AMDGPU_GEM_DOMAIN_CPU;
bp.bo_ptr_size = sizeof(struct amdgpu_bo);
r = amdgpu_bo_create_user(adev, &bp, &ubo);
@@ -332,20 +332,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
*data,
}
initial_domain = (u32)(0x & args->in.domains);
-retry:
r = amdgpu_gem_object_create(adev, size, args->in.alignment,
-initial_domain,
-flags, ttm_bo_type_device, resv, &gobj);
+initial_domain, flags, ttm_bo_type_device,
+resv, &gobj);
if (r && r != -ERESTARTSYS) {
- if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
- flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
- goto retry;
- }
-
- if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
- initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
- goto retry;
- }
DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu,
%d)\n",
size, initial_domain, args->in.alignment, r);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 974e85d8b6cc..919bbea2e3ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -581,11 +581,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
bo->tbo.bdev = &adev->mman.bdev;
- if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
- AMDGPU_GEM_DOMAIN_GDS))
- amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
- else
- amdgpu_bo_placement_from_domain(bo, bp->domain);
+ amdgpu_bo_placement_from_domain(bo, bp->domain);
if (bp->type == ttm_bo_type_kernel)
bo->tbo.priority = 1;
[Intel-gfx] [PATCH v7 00/11] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes
This series fixes issues faced when an HDMI2.1 sink that does not support DSC is connected via HDMI2.1PCON. It also includes other minor HDMI2.1 PCON fixes/refactoring. Patch 1-2 Have minor fixes/cleanups. Patch 3-6 Pull the decision making to use DFP conversion capabilities for every mode during compute config, instead of having that decision during DP initializing phase. Patch 7-8 Calculate the max BPC that can be sufficient with either RGB or YCbcr420 format for the maximum FRL rate supported. Rev2: Split the refactoring of DFP RG->YCBCR conversion into smaller patches, as suggested by Jani N. Also dropped the unnecessary helper for DSC1.2 support for HDMI2.1 DFP. Rev3: As suggested by Ville, added new member sink_format to store the final format that the sink will be using, which might be different than the output format, and thus might need color/format conversion performed by the PCON. Rev4: Fix typo in switch case as, reported by kernel test bot. Rev5: Corrected order of setting sink_format and output_format. (Ville) Avoided the flag ycbcr420_output and used the sink_format to facilitate 4:2:2 support at a later stage. (Ville) Rev6: Added missing changes for sdvo. (Ville) Added check for scaler and DSC constraints with YCbCr420. Rev7: Split change to add scaler constraint in separate patch, and rebased. Ankit Nautiyal (11): drm/i915/display: Add new member to configure PCON color conversion drm/i915/display: Add new member in intel_dp to store ycbcr420 passthrough cap drm/i915/dp: Add Scaler constraint for YCbCr420 output drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state sink_format drm/i915/dp: Compute output format with/without DSC drm/i915/display: Use sink_format instead of ycbcr420_output flag drm/i915/display: Add helper function to check if sink_format is 420 drm/i915/dp: Avoid DSC with output_format YCBC420 drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints drivers/gpu/drm/i915/display/icl_dsi.c| 1 + drivers/gpu/drm/i915/display/intel_crt.c | 1 + .../drm/i915/display/intel_crtc_state_dump.c | 5 +- drivers/gpu/drm/i915/display/intel_display.c | 5 + .../drm/i915/display/intel_display_types.h| 18 +- drivers/gpu/drm/i915/display/intel_dp.c | 456 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 + drivers/gpu/drm/i915/display/intel_dvo.c | 1 + drivers/gpu/drm/i915/display/intel_hdmi.c | 74 +-- drivers/gpu/drm/i915/display/intel_hdmi.h | 5 +- drivers/gpu/drm/i915/display/intel_lvds.c | 1 + drivers/gpu/drm/i915/display/intel_sdvo.c | 1 + drivers/gpu/drm/i915/display/intel_tv.c | 1 + drivers/gpu/drm/i915/display/vlv_dsi.c| 1 + 14 files changed, 409 insertions(+), 162 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH v1 03/11] drm/i915/dp: Add Scaler constraint for YCbCr420 output
For YCbCr420 output, scaler is required for downsampling.
Scaler can be used only when source size smaller than 4096x5120.
So go for native YCbCr420 only if there are no scaler constraints.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 3ff9796f83e1..a0e1fbc8eea1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -786,8 +786,15 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp
*intel_dp,
return 0;
}
+static bool
+ycbcr420_scaler_constraints(const struct drm_display_mode *mode)
+{
+ return mode->hdisplay > 4096 || mode->vdisplay > 5120;
+}
+
static enum intel_output_format
intel_dp_output_format(struct intel_connector *connector,
+ const struct drm_display_mode *mode,
enum intel_output_format sink_format)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -802,8 +809,15 @@ intel_dp_output_format(struct intel_connector *connector,
if (intel_dp->dfp.ycbcr_444_to_420)
return INTEL_OUTPUT_FORMAT_YCBCR444;
- else
+
+ /*
+* For YCbCr420 output, scaler is required for downsampling
+* So go for native YCbCr420 only if there are no scaler constraints.
+*/
+ if (!ycbcr420_scaler_constraints(mode))
return INTEL_OUTPUT_FORMAT_YCBCR420;
+
+ return INTEL_OUTPUT_FORMAT_RGB;
}
int intel_dp_min_bpp(enum intel_output_format output_format)
@@ -839,7 +853,7 @@ intel_dp_mode_min_output_bpp(struct intel_connector
*connector,
else
sink_format = INTEL_OUTPUT_FORMAT_RGB;
- output_format = intel_dp_output_format(connector, sink_format);
+ output_format = intel_dp_output_format(connector, mode, sink_format);
return intel_dp_output_bpp(output_format,
intel_dp_min_bpp(output_format));
}
@@ -2002,7 +2016,8 @@ intel_dp_compute_output_format(struct intel_encoder
*encoder,
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
}
- crtc_state->output_format = intel_dp_output_format(connector,
crtc_state->sink_format);
+ crtc_state->output_format = intel_dp_output_format(connector,
adjusted_mode,
+
crtc_state->sink_format);
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
respect_downstream_limits);
@@ -2012,7 +2027,7 @@ intel_dp_compute_output_format(struct intel_encoder
*encoder,
return ret;
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- crtc_state->output_format = intel_dp_output_format(connector,
+ crtc_state->output_format = intel_dp_output_format(connector,
adjusted_mode,
crtc_state->sink_format);
ret = intel_dp_compute_link_config(encoder, crtc_state,
conn_state,
respect_downstream_limits);
--
2.25.1
[Intel-gfx] [PATCH v7 04/11] drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state sink_format
The decision to use DFP output format conversion capabilities should be
during compute_config phase.
This patch uses the members of intel_dp->dfp to only store the
format conversion capabilities of the DP device and uses the crtc_state
sink_format member, to program the protocol-converter for
colorspace/format conversion.
v2: Use sink_format to determine the color conversion config for the
pcon (Ville).
v3: Fix typo: missing 'break' in switch case (lkp kernel test robot).
v4: Add helper to check if DP supports YCBCR420.
v5: Simplify logic for computing output_format, based on the given
sink_format. (Ville).
Added scaler constraint for YCbCr420 output.
v6: Split the patch for Scaler constraint for Ycbcr420.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 191 +---
1 file changed, 134 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a0e1fbc8eea1..496333285d32 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -786,6 +786,67 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp
*intel_dp,
return 0;
}
+static bool source_can_output(struct intel_dp *intel_dp,
+ enum intel_output_format format)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ bool is_branch = drm_dp_is_branch(intel_dp->dpcd);
+
+ if (format == INTEL_OUTPUT_FORMAT_RGB)
+ return true;
+
+ /*
+* No YCbCr output support on gmch platforms.
+* Also, ILK doesn't seem capable of DP YCbCr output.
+* The displayed image is severly corrupted. SNB+ is fine.
+*/
+ if (HAS_GMCH(i915) || IS_IRONLAKE(i915))
+ return false;
+
+ if (format == INTEL_OUTPUT_FORMAT_YCBCR444)
+ return true;
+
+ /* Platform < Gen 11 cannot output YCbCr420 format */
+ if (DISPLAY_VER(i915) < 11)
+ return false;
+
+ /* If branch device then PCONs should support YCbCr420 Passthrough */
+ if (format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ return !is_branch || intel_dp->dfp.ycbcr420_passthrough;
+
+ return false;
+}
+
+static bool
+dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
+enum intel_output_format sink_format)
+{
+ if (!drm_dp_is_branch(intel_dp->dpcd))
+ return false;
+
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
+ return intel_dp->dfp.rgb_to_ycbcr;
+
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ return intel_dp->dfp.rgb_to_ycbcr &&
+ intel_dp->dfp.ycbcr_444_to_420;
+
+ return false;
+}
+
+static bool
+dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
+ enum intel_output_format sink_format)
+{
+ if (!drm_dp_is_branch(intel_dp->dpcd))
+ return false;
+
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ return intel_dp->dfp.ycbcr_444_to_420;
+
+ return false;
+}
+
static bool
ycbcr420_scaler_constraints(const struct drm_display_mode *mode)
{
@@ -799,24 +860,22 @@ intel_dp_output_format(struct intel_connector *connector,
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
- if (!connector->base.ycbcr_420_allowed ||
- sink_format != INTEL_OUTPUT_FORMAT_YCBCR420)
- return INTEL_OUTPUT_FORMAT_RGB;
+ /*
+* For YCbCr420 output, scaler is required for downsampling.
+* So go for native YCbCr420 only if there are no scaler constraints.
+*/
+ if ((sink_format != INTEL_OUTPUT_FORMAT_YCBCR420 ||
!ycbcr420_scaler_constraints(mode)) &&
+ source_can_output(intel_dp, sink_format))
+ return sink_format;
- if (intel_dp->dfp.rgb_to_ycbcr &&
- intel_dp->dfp.ycbcr_444_to_420)
+ if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
+ dfp_can_convert_from_rgb(intel_dp, sink_format))
return INTEL_OUTPUT_FORMAT_RGB;
- if (intel_dp->dfp.ycbcr_444_to_420)
+ if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
+ dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
return INTEL_OUTPUT_FORMAT_YCBCR444;
- /*
-* For YCbCr420 output, scaler is required for downsampling
-* So go for native YCbCr420 only if there are no scaler constraints.
-*/
- if (!ycbcr420_scaler_constraints(mode))
- return INTEL_OUTPUT_FORMAT_YCBCR420;
-
return INTEL_OUTPUT_FORMAT_RGB;
}
@@ -2684,6 +2743,8 @@ void intel_dp_configure_protocol_converter(struct
intel_dp *intel_dp,
const struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ bool ycbcr444_to_42
[Intel-gfx] [PATCH v5 06/11] drm/i915/display: Use sink_format instead of ycbcr420_output flag
Start passing the sink_format, to all functions that take a bool
ycbcr420_output as parameter. This will make the functions generic,
and will serve as a slight step towards 4:2:2 support later.
Suggested-by: Ville Syrj_l_
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 33 +++
drivers/gpu/drm/i915/display/intel_hdmi.c | 50 ---
drivers/gpu/drm/i915/display/intel_hdmi.h | 5 ++-
3 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1bdf930c4146..09246e1d33ef 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -961,7 +961,8 @@ static int intel_dp_max_tmds_clock(struct intel_dp
*intel_dp)
static enum drm_mode_status
intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
- int clock, int bpc, bool ycbcr420_output,
+ int clock, int bpc,
+ enum intel_output_format sink_format,
bool respect_downstream_limits)
{
int tmds_clock, min_tmds_clock, max_tmds_clock;
@@ -969,7 +970,7 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
if (!respect_downstream_limits)
return MODE_OK;
- tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
+ tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
min_tmds_clock = intel_dp->dfp.min_tmds_clock;
max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
@@ -992,6 +993,7 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
const struct drm_display_info *info = &connector->base.display_info;
enum drm_mode_status status;
bool ycbcr_420_only;
+ enum intel_output_format sink_format;
/* If PCON supports FRL MODE, check FRL bandwidth constraints */
if (intel_dp->dfp.pcon_max_frl_bw) {
@@ -1018,18 +1020,22 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
ycbcr_420_only = drm_mode_is_420_only(info, mode);
+ if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
+ sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ else
+ sink_format = INTEL_OUTPUT_FORMAT_RGB;
+
/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
- 8, ycbcr_420_only, true);
+ 8, sink_format, true);
if (status != MODE_OK) {
- if (ycbcr_420_only ||
- !connector->base.ycbcr_420_allowed ||
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
!drm_mode_is_420_also(info, mode))
return status;
-
+ sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
- 8, true, true);
+ 8, sink_format, true);
if (status != MODE_OK)
return status;
}
@@ -1268,19 +1274,10 @@ static bool intel_dp_supports_dsc(struct intel_dp
*intel_dp,
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
}
-static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
-const struct intel_crtc_state *crtc_state)
-{
- return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
- (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
-intel_dp->dfp.ycbcr_444_to_420);
-}
-
static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
int bpc, bool respect_downstream_limits)
{
- bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
int clock = crtc_state->hw.adjusted_mode.crtc_clock;
/*
@@ -1300,8 +1297,8 @@ static int intel_dp_hdmi_compute_bpc(struct intel_dp
*intel_dp,
for (; bpc >= 8; bpc -= 2) {
if (intel_hdmi_bpc_possible(crtc_state, bpc,
- intel_dp->has_hdmi_sink,
ycbcr420_output) &&
- intel_dp_tmds_clock_valid(intel_dp, clock, bpc,
ycbcr420_output,
+ intel_dp->has_hdmi_sink) &&
+ intel_dp_tmds_clock_valid(intel_dp, clock, bpc,
crtc_state->sink_format,
respect_downstream_limits) ==
MODE_OK)
return bpc;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 2d822cacf169..85453c3f7dc1 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/
[Intel-gfx] [PATCH v5 02/11] drm/i915/display: Add new member in intel_dp to store ycbcr420 passthrough cap
New member to store the YCBCR20 Pass through capability of the DP sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index a7c9fdb44101..9e31aa008f22 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1728,6 +1728,7 @@ struct intel_dp {
int pcon_max_frl_bw;
u8 max_bpc;
bool ycbcr_444_to_420;
+ bool ycbcr420_passthrough;
bool rgb_to_ycbcr;
} dfp;
--
2.25.1
[Intel-gfx] [PATCH v1 05/11] drm/i915/dp: Compute output format with/without DSC
Currently we compute the output format first and later try DSC if the
bandwidth without compression is not sufficient for that output format.
Since we do not support DSC with YCbCr420 format, this creates problem
for YCbCr420 only modes, that can be still be set if DFP has color
conversion and DSC capabilities.
So compute output format, first without DSC and inturn compute the link
config without DSC. If cannot be supported without DSC, compute the
output format with DSC and continue.
With this apporach, check can be added for YCbCr420 output, which cannot
be supported with DSC.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 81 +
1 file changed, 56 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 496333285d32..1bdf930c4146 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -848,24 +848,34 @@ dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
}
static bool
-ycbcr420_scaler_constraints(const struct drm_display_mode *mode)
+ycbcr420_constraints(const struct drm_display_mode *mode, bool with_dsc)
{
+ /*
+* DSC with YCbCr420 is a constraint as currently we do not support
compression
+* with 420 format.
+*/
+ if (with_dsc)
+ return true;
+
return mode->hdisplay > 4096 || mode->vdisplay > 5120;
}
static enum intel_output_format
intel_dp_output_format(struct intel_connector *connector,
const struct drm_display_mode *mode,
- enum intel_output_format sink_format)
+ enum intel_output_format sink_format,
+ bool with_dsc)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
/*
* For YCbCr420 output, scaler is required for downsampling.
-* So go for native YCbCr420 only if there are no scaler constraints.
+* DSC1.1 supports compression only with 444 formats.
+* So go for native YCbCr420 only if there are no scaler and dsc
constraints.
*/
- if ((sink_format != INTEL_OUTPUT_FORMAT_YCBCR420 ||
!ycbcr420_scaler_constraints(mode)) &&
- source_can_output(intel_dp, sink_format))
+ if (source_can_output(intel_dp, sink_format) &&
+ (sink_format != INTEL_OUTPUT_FORMAT_YCBCR420 ||
+!ycbcr420_constraints(mode, with_dsc)))
return sink_format;
if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
@@ -912,7 +922,7 @@ intel_dp_mode_min_output_bpp(struct intel_connector
*connector,
else
sink_format = INTEL_OUTPUT_FORMAT_RGB;
- output_format = intel_dp_output_format(connector, mode, sink_format);
+ output_format = intel_dp_output_format(connector, mode, sink_format,
false);
return intel_dp_output_bpp(output_format,
intel_dp_min_bpp(output_format));
}
@@ -1661,7 +1671,8 @@ static int
intel_dp_compute_link_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
-bool respect_downstream_limits)
+bool respect_downstream_limits,
+bool with_dsc)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
@@ -1672,6 +1683,20 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
bool joiner_needs_dsc = false;
int ret;
+ if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
+ adjusted_mode->crtc_clock))
+ pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1,
crtc->pipe);
+
+ /*
+* Pipe joiner needs compression up to display 12 due to bandwidth
+* limitation. DG2 onwards pipe joiner can be enabled without
+* compression.
+*/
+ joiner_needs_dsc = DISPLAY_VER(i915) < 13 &&
pipe_config->bigjoiner_pipes;
+
+ if (joiner_needs_dsc && !with_dsc)
+ return -EINVAL;
+
limits.min_rate = intel_dp_common_rate(intel_dp, 0);
limits.max_rate = intel_dp_max_link_rate(intel_dp);
@@ -1701,23 +1726,15 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
limits.max_lane_count, limits.max_rate,
limits.max_bpp, adjusted_mode->crtc_clock);
- if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
- adjusted_mode->crtc_clock))
- pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1,
crtc->pipe);
-
- /*
-* Pipe joiner needs compression up to display 12 due to bandwidth
-* limitation. DG2 onwards pipe joiner can be enabled without
-
[Intel-gfx] [PATCH v5 07/11] drm/i915/display: Add helper function to check if sink_format is 420
Add an inline helper function to check if the sink_format is set to
YCBCR420 format.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++
drivers/gpu/drm/i915/display/intel_dp.c| 4 ++--
drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +++---
3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9e31aa008f22..f28858668339 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2062,4 +2062,10 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
+static inline bool
+intel_crtc_has_420_sink_format(const struct intel_crtc_state *crtc_state)
+{
+ return crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420;
+}
+
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 09246e1d33ef..d97832b8da32 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2096,7 +2096,7 @@ intel_dp_compute_output_format(struct intel_encoder
*encoder,
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
respect_downstream_limits, with_dsc);
if (ret) {
- if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+ if (intel_crtc_has_420_sink_format(crtc_state) ||
!drm_mode_is_420_also(info, adjusted_mode))
return ret;
@@ -2789,7 +2789,7 @@ void intel_dp_configure_protocol_converter(struct
intel_dp *intel_dp,
drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI
mode\n",
str_enable_disable(intel_dp->has_hdmi_sink));
- if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+ if (intel_crtc_has_420_sink_format(crtc_state)) {
switch (crtc_state->output_format) {
case INTEL_OUTPUT_FORMAT_YCBCR420:
/*
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 85453c3f7dc1..aa36dd43c992 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2062,7 +2062,7 @@ static bool hdmi_bpc_possible(const struct
intel_crtc_state *crtc_state, int bpc
return false;
/* Display Wa_1405510057:icl,ehl */
- if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
+ if (intel_crtc_has_420_sink_format(crtc_state) &&
bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
(adjusted_mode->crtc_hblank_end -
adjusted_mode->crtc_hblank_start) % 8 == 2)
@@ -2224,7 +2224,7 @@ static int intel_hdmi_compute_output_format(struct
intel_encoder *encoder,
crtc_state->output_format = intel_hdmi_output_format(crtc_state,
connector);
ret = intel_hdmi_compute_clock(encoder, crtc_state,
respect_downstream_limits);
if (ret) {
- if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+ if (intel_crtc_has_420_sink_format(crtc_state) ||
!drm_mode_is_420_also(info, adjusted_mode))
return ret;
@@ -2284,7 +2284,7 @@ int intel_hdmi_compute_config(struct intel_encoder
*encoder,
return ret;
}
- if (pipe_config->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+ if (intel_crtc_has_420_sink_format(pipe_config)) {
ret = intel_panel_fitting(pipe_config, conn_state);
if (ret)
return ret;
--
2.25.1
[Intel-gfx] [PATCH v5 10/11] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
During FRL bandwidth check for downstream HDMI2.1 sink,
the min BPC supported is incorrectly taken for DP, and the check does
not consider ybcr420 only modes.
This patch fixes the bandwidth calculation similar to the TMDS case, by
taking min 8Bpc and considering Ycbcr420 only modes.
v2: Rebase
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 66 +
1 file changed, 46 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index d4de5c3da0ae..3e258e487d9e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -119,6 +119,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp);
+static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -985,6 +986,32 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
return MODE_OK;
}
+static enum drm_mode_status
+intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
+ int bpc, enum intel_output_format sink_format)
+{
+ int target_bw;
+ int max_frl_bw;
+ int bpp = bpc * 3;
+
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ target_clock /= 2;
+
+ target_bw = bpp * target_clock;
+
+ /* check for MAX FRL BW for both PCON and HDMI2.1 sink */
+ max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw,
+intel_dp_hdmi_sink_max_frl(intel_dp));
+
+ /* converting bw from Gbps to Kbps*/
+ max_frl_bw = max_frl_bw * 100;
+
+ if (target_bw > max_frl_bw)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector *connector,
const struct drm_display_mode *mode,
@@ -993,24 +1020,30 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
struct intel_dp *intel_dp = intel_attached_dp(connector);
const struct drm_display_info *info = &connector->base.display_info;
enum drm_mode_status status;
- bool ycbcr_420_only;
+ bool ycbcr_420_only = drm_mode_is_420_only(info, mode);
enum intel_output_format sink_format;
+ ycbcr_420_only = drm_mode_is_420_only(info, mode);
+
/* If PCON supports FRL MODE, check FRL bandwidth constraints */
if (intel_dp->dfp.pcon_max_frl_bw) {
- int target_bw;
- int max_frl_bw;
- int bpp = intel_dp_mode_min_output_bpp(connector, mode);
-
- target_bw = bpp * target_clock;
-
- max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
- /* converting bw from Gbps to Kbps*/
- max_frl_bw = max_frl_bw * 100;
-
- if (target_bw > max_frl_bw)
- return MODE_CLOCK_HIGH;
+ if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
+ sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ else
+ sink_format = INTEL_OUTPUT_FORMAT_RGB;
+
+ /* Assume 8bpc for the HDMI2.1 FRL BW check */
+ status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8,
sink_format);
+ if (status != MODE_OK) {
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+ !drm_mode_is_420_also(info, mode))
+ return status;
+ sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ status = intel_dp_frl_bw_valid(intel_dp, target_clock,
8, sink_format);
+ if (status != MODE_OK)
+ return status;
+ }
return MODE_OK;
}
@@ -1019,13 +1052,6 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
target_clock > intel_dp->dfp.max_dotclock)
return MODE_CLOCK_HIGH;
- ycbcr_420_only = drm_mode_is_420_only(info, mode);
-
- if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
- sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- else
- sink_format = INTEL_OUTPUT_FORMAT_RGB;
-
/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
8, sink_format, true);
--
2.25.1
[Intel-gfx] [PATCH v5 11/11] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints
Add a wrapper function to check dp_downstream clock/bandwidth
constraints. Based on whether the sink supports FRL/TMDS the wrapper
calls the appropriate FRL/TMDS functions.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 51 +++--
1 file changed, 23 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 3e258e487d9e..ce4684141fb1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1012,6 +1012,18 @@ intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int
target_clock,
return MODE_OK;
}
+static enum drm_mode_status
+intel_dp_hdmi_bw_check(struct intel_dp *intel_dp,
+ int target_clock, int bpc,
+ enum intel_output_format sink_format,
+ bool is_frl)
+{
+ if (is_frl)
+ return intel_dp_frl_bw_valid(intel_dp, target_clock, 8,
sink_format);
+
+ return intel_dp_tmds_clock_valid(intel_dp, target_clock, 8,
sink_format, true);
+}
+
static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector *connector,
const struct drm_display_mode *mode,
@@ -1021,48 +1033,31 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
const struct drm_display_info *info = &connector->base.display_info;
enum drm_mode_status status;
bool ycbcr_420_only = drm_mode_is_420_only(info, mode);
+ bool is_frl;
enum intel_output_format sink_format;
+ int bpc = 8; /* Assume 8bpc for the DP++/HDMI/DVI TMDS/FRL bw heck */
- ycbcr_420_only = drm_mode_is_420_only(info, mode);
+ if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
+ sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ else
+ sink_format = INTEL_OUTPUT_FORMAT_RGB;
/* If PCON supports FRL MODE, check FRL bandwidth constraints */
- if (intel_dp->dfp.pcon_max_frl_bw) {
-
- if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
- sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- else
- sink_format = INTEL_OUTPUT_FORMAT_RGB;
-
- /* Assume 8bpc for the HDMI2.1 FRL BW check */
- status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8,
sink_format);
- if (status != MODE_OK) {
- if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
- !drm_mode_is_420_also(info, mode))
- return status;
- sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- status = intel_dp_frl_bw_valid(intel_dp, target_clock,
8, sink_format);
- if (status != MODE_OK)
- return status;
- }
+ is_frl = intel_dp->dfp.pcon_max_frl_bw ? true : false;
- return MODE_OK;
- }
-
- if (intel_dp->dfp.max_dotclock &&
+ if (!is_frl && intel_dp->dfp.max_dotclock &&
target_clock > intel_dp->dfp.max_dotclock)
return MODE_CLOCK_HIGH;
- /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
- status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
- 8, sink_format, true);
+ status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc,
sink_format, is_frl);
if (status != MODE_OK) {
if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
!drm_mode_is_420_also(info, mode))
return status;
sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
- 8, sink_format, true);
+ status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc,
sink_format, is_frl);
+ } else {
if (status != MODE_OK)
return status;
}
--
2.25.1
[Intel-gfx] [PATCH v6 01/11] drm/i915/display: Add new member to configure PCON color conversion
The decision to use DFP output format conversion capabilities should be during compute_config phase. This patch adds new member to crtc_state to represent the final output_format to the sink. In case of a DFP this can be different than the output_format, as per the format conversion done via the PCON. This will help to store only the format conversion capabilities of the DP device in intel_dp->dfp, and use crtc_state to compute and store the configuration for color/format conversion for a given mode. v2: modified the new member to crtc_state to represent the final output_format that eaches the sink, after possible conversion by PCON kind of devices. (Ville) v3: Addressed comments from Ville: -Added comments to clarify difference between sink_format and output_format. -Corrected the order of setting sink_format and output_format. -Added readout for sink_format in get_pipe_config hooks. v4: Set sink_format for intel_sdvo too. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä (v3) --- drivers/gpu/drm/i915/display/icl_dsi.c| 1 + drivers/gpu/drm/i915/display/intel_crt.c | 1 + .../drm/i915/display/intel_crtc_state_dump.c | 5 +-- drivers/gpu/drm/i915/display/intel_display.c | 5 +++ .../drm/i915/display/intel_display_types.h| 11 +- drivers/gpu/drm/i915/display/intel_dp.c | 34 +-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 + drivers/gpu/drm/i915/display/intel_dvo.c | 1 + drivers/gpu/drm/i915/display/intel_hdmi.c | 24 +++-- drivers/gpu/drm/i915/display/intel_lvds.c | 1 + drivers/gpu/drm/i915/display/intel_sdvo.c | 1 + drivers/gpu/drm/i915/display/intel_tv.c | 1 + drivers/gpu/drm/i915/display/vlv_dsi.c| 1 + 13 files changed, 62 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index d16b30a2dded..0ca0d23f42c6 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1667,6 +1667,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder, &pipe_config->hw.adjusted_mode; int ret; + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; ret = intel_panel_compute_config(intel_connector, adjusted_mode); diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 797ad9489f7e..eb5964b3ff95 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -393,6 +393,7 @@ static int intel_crt_compute_config(struct intel_encoder *encoder, if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) return -EINVAL; + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; return 0; diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index e3273fe8ddac..9b61884851fc 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -163,10 +163,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); drm_dbg_kms(&i915->drm, - "active: %s, output_types: %s (0x%x), output format: %s\n", + "active: %s, output_types: %s (0x%x), output format: %s, sink format: %s\n", str_yes_no(pipe_config->hw.active), buf, pipe_config->output_types, - output_formats(pipe_config->output_format)); + output_formats(pipe_config->output_format), + output_formats(pipe_config->sink_format)); drm_dbg_kms(&i915->drm, "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b3e23708d194..79b5e9843f74 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3243,6 +3243,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, return false; pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; + pipe_config->sink_format = pipe_config->output_format; pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; pipe_config->shared_dpll = NULL; @@ -3702,6 +3703,8 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, break; } + pipe_config->sink_format = pipe_config->output_format; + pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; @@ -4096,6 +4099,8 @@
[Intel-gfx] [PATCH v5 08/11] drm/i915/dp: Avoid DSC with output_format YCBC420
Currently, DSC with YCBCR420 is not supported.
Return -EINVAL when trying with DSC with output_format as YCBCR420.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index d97832b8da32..c40d081358f8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1570,6 +1570,10 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
+ /* Currently DSC with YCBCR420 format is not supported */
+ if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ return -EINVAL;
+
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
conn_state->max_requested_bpc);
if (intel_dp->force_dsc_bpc) {
--
2.25.1
[Intel-gfx] [PATCH v5 09/11] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC
Currently we use the highest input BPC supported by DP sink while using
DSC.In cases where PCON with HDMI2.1 as branch device, if PCON supports
DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same
input BPC that is used between Source and the PCON without DSC, which
might not work even with the maximum FRL rate supported by HDMI2.1
sink.
This patch calculates the max BPC that can be sufficient with either
RGB or YCBCR420 format for the maximum FRL rate supported.
v2: Rebase
v3: Use the sink_format in the functions instead of ycbcr420 flag.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 61 +++--
1 file changed, 58 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index c40d081358f8..d4de5c3da0ae 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -118,6 +118,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -1552,12 +1553,47 @@ static int intel_dp_dsc_compute_params(struct
intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
+static int
+intel_dp_pcon_hdmi21_get_bpp_nodsc(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int max_bpc)
+{
+ struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct drm_connector *connector = &intel_connector->base;
+ const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
+ int i, num_bpc;
+ u8 dsc_bpc[3] = {0};
+ int req_rate_gbps;
+ int max_frl_rate = connector->display_info.hdmi.max_lanes *
+ connector->display_info.hdmi.max_frl_rate_per_lane;
+
+ num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
+ dsc_bpc);
+ for (i = 0; i < num_bpc; i++) {
+ if (dsc_bpc[i] > max_bpc)
+ continue;
+
+ req_rate_gbps = DIV_ROUND_UP(dsc_bpc[i] * 3 *
adjusted_mode->clock, 100);
+
+ /* YCBCR420 reduces data rate by 2 */
+ if (intel_crtc_has_420_sink_format(pipe_config))
+ req_rate_gbps /= 2;
+
+ if (req_rate_gbps < max_frl_rate)
+ return dsc_bpc[i] * 3;
+ }
+
+ return 0;
+}
+
static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
struct link_config_limits *limits)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct drm_connector *connector = &intel_connector->base;
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
@@ -1574,11 +1610,30 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
return -EINVAL;
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
conn_state->max_requested_bpc);
-
- if (intel_dp->force_dsc_bpc) {
+ /*
+* In cases where PCON with HDMI2.1 as branch device, if PCON supports
+* DSC but HDMI2.1 sink does not supports DSC, there can be issues due
+* to the bpc used.
+* With DSC, a source-PCON pair can support the mode with higher bpcs.
+* But PCON->Sink pair, cannot support the same bpc without sink having
+* DSC support.
+* So use the max BPC as input BPC that will be sufficient to show the
+* mode without DSC from PCON->HDMI2.1
+*/
+ if (intel_dp_is_hdmi_2_1_sink(intel_dp) &&
+ !connector->display_info.hdmi.dsc_cap.v_1p2) {
+ pipe_bpp = intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp,
pipe_config,
+
conn_state->max_requested_bpc);
+ if (!pipe_bpp) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No BPC possible to support the mode
without HDMI2.1 DSC\n");
+ return -EINVAL;
+ }
+ } else if (intel_dp->force_dsc_bpc) {
pipe_bpp = intel_dp->force_dsc_bpc * 3;
Re: [Intel-gfx] [RFC 1/2] drm/connector: add connector list iteration with filtering
Hi Jani,
Thank you for the patch.
On Wed, Oct 05, 2022 at 01:51:43PM +0300, Jani Nikula wrote:
> Add new function drm_connector_list_iter_filter_begin() to initialize
> connector list iterator with a filter function. Subsequent iteration on
> the list will only return connectors on which the filter function
> returns true.
>
> Cc: Arun R Murthy
> Cc: Suraj Kandpal
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/drm_connector.c | 57 ++---
> include/drm/drm_connector.h | 9 ++
> 2 files changed, 54 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index e3142c8142b3..d54b4b54cecb 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -762,6 +762,29 @@ static struct lockdep_map connector_list_iter_dep_map = {
> };
> #endif
>
> +/**
> + * drm_connector_list_iter_filter_begin - initialize a connector_list
> iterator with filter
> + * @dev: DRM device
> + * @iter: connector_list iterator
> + * @filter: connector filter function
> + * @filter_context: context to be passed to the filter function
> + *
> + * Same as drm_connector_list_iter_begin(), but sets up the iterator to only
> + * return connectors where filter(connector) returns true.
> + */
> +void drm_connector_list_iter_filter_begin(struct drm_device *dev,
> + struct drm_connector_list_iter *iter,
> + drm_connector_list_iter_filter_fn
> filter,
> + void *filter_context)
> +{
> + iter->dev = dev;
> + iter->conn = NULL;
> + iter->filter = filter;
> + iter->filter_context = filter_context;
> + lock_acquire_shared_recursive(&connector_list_iter_dep_map, 0, 1, NULL,
> _RET_IP_);
> +}
> +EXPORT_SYMBOL(drm_connector_list_iter_filter_begin);
> +
> /**
> * drm_connector_list_iter_begin - initialize a connector_list iterator
> * @dev: DRM device
> @@ -775,9 +798,7 @@ static struct lockdep_map connector_list_iter_dep_map = {
> void drm_connector_list_iter_begin(struct drm_device *dev,
> struct drm_connector_list_iter *iter)
> {
> - iter->dev = dev;
> - iter->conn = NULL;
> - lock_acquire_shared_recursive(&connector_list_iter_dep_map, 0, 1, NULL,
> _RET_IP_);
> + drm_connector_list_iter_filter_begin(dev, iter, NULL, NULL);
> }
> EXPORT_SYMBOL(drm_connector_list_iter_begin);
I would have made this a static inline function in
include/drm/drm_connector.h. Apart from that,
Reviewed-by: Laurent Pinchart
>
> @@ -800,15 +821,8 @@ __drm_connector_put_safe(struct drm_connector *conn)
> schedule_work(&config->connector_free_work);
> }
>
> -/**
> - * drm_connector_list_iter_next - return next connector
> - * @iter: connector_list iterator
> - *
> - * Returns: the next connector for @iter, or NULL when the list walk has
> - * completed.
> - */
> -struct drm_connector *
> -drm_connector_list_iter_next(struct drm_connector_list_iter *iter)
> +static struct drm_connector *
> +__drm_connector_list_iter_next(struct drm_connector_list_iter *iter)
> {
> struct drm_connector *old_conn = iter->conn;
> struct drm_mode_config *config = &iter->dev->mode_config;
> @@ -836,6 +850,25 @@ drm_connector_list_iter_next(struct
> drm_connector_list_iter *iter)
>
> return iter->conn;
> }
> +
> +/**
> + * drm_connector_list_iter_next - return next connector
> + * @iter: connector_list iterator
> + *
> + * Returns: the next connector for @iter, or NULL when the list walk has
> + * completed.
> + */
> +struct drm_connector *
> +drm_connector_list_iter_next(struct drm_connector_list_iter *iter)
> +{
> + struct drm_connector *connector;
> +
> + while ((connector = __drm_connector_list_iter_next(iter)) &&
> +iter->filter && !iter->filter(connector, iter->filter_context))
> + ;
> +
> + return connector;
> +}
> EXPORT_SYMBOL(drm_connector_list_iter_next);
>
> /**
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 56aee949c6fa..497b98197d3a 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -1868,6 +1868,9 @@ struct drm_tile_group *drm_mode_get_tile_group(struct
> drm_device *dev,
> void drm_mode_put_tile_group(struct drm_device *dev,
>struct drm_tile_group *tg);
>
> +typedef bool (*drm_connector_list_iter_filter_fn)(const struct drm_connector
> *connector,
> + void *filter_context);
> +
> /**
> * struct drm_connector_list_iter - connector_list iterator
> *
> @@ -1886,10 +1889,16 @@ struct drm_connector_list_iter {
> /* private: */
> struct drm_device *dev;
> struct drm_connector *conn;
> + drm_connector_list_iter_filter_fn filter;
> + void *filter_context;
> };
>
> void drm_connector_list_iter_b
[Intel-gfx] ✓ Fi.CI.BAT: success for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev7)
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev7)
URL : https://patchwork.freedesktop.org/series/107550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12436 -> Patchwork_107550v7
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v7/index.html
Participating hosts (31 -> 30)
--
Missing(1): bat-rpls-2
Known issues
Here are the changes found in Patchwork_107550v7 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v7/fi-apl-guc/igt@gem_lmem_swapp...@basic.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-apl-guc: NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#111827])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v7/fi-apl-guc/igt@kms_chamel...@common-hpd-after-suspend.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [INCOMPLETE][3] ([i915#7073]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12436/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v7/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#7073]: https://gitlab.freedesktop.org/drm/intel/issues/7073
Build changes
-
* Linux: CI_DRM_12436 -> Patchwork_107550v7
CI-20190529: 20190529
CI_DRM_12436: a1b695b469432195cef49cd7b19e32e6bbacd609 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7072: 69ba7163475925cdc69aebbdfa0e87453ae165c7 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107550v7: a1b695b469432195cef49cd7b19e32e6bbacd609 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
b1c5a71460b1 drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints
24381576dc96 drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
b38b65984701 drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC
551d8d4e7931 drm/i915/dp: Avoid DSC with output_format YCBC420
fd3b482f8904 drm/i915/display: Add helper function to check if sink_format is
420
295e1b9668d5 drm/i915/display: Use sink_format instead of ycbcr420_output flag
ed7076511e19 drm/i915/dp: Compute output format with/without DSC
f57e3d249960 drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state
sink_format
eda0ef218006 drm/i915/dp: Add Scaler constraint for YCbCr420 output
3d89a4861eff drm/i915/display: Add new member in intel_dp to store ycbcr420
passthrough cap
a169d61a19b4 drm/i915/display: Add new member to configure PCON color conversion
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v7/index.html
