[Intel-gfx] ✓ Fi.CI.BAT: success for Enable HDCP2.x via GSC CS (rev9)
== Series Details ==
Series: Enable HDCP2.x via GSC CS (rev9)
URL : https://patchwork.freedesktop.org/series/111876/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12670 -> Patchwork_111876v9
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v9/index.html
Participating hosts (25 -> 24)
--
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111876v9:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_fence@basic-await@vecs1:
- {bat-dg2-9}:[PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/bat-dg2-9/igt@gem_exec_fence@basic-aw...@vecs1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v9/bat-dg2-9/igt@gem_exec_fence@basic-aw...@vecs1.html
Known issues
Here are the changes found in Patchwork_111876v9 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-n3050: [PASS][3] -> [FAIL][4] ([i915#6298])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v9/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][5] ([i915#5334]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v9/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@slpc:
- {bat-rpls-1}: [DMESG-FAIL][7] ([i915#6367]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v9/bat-rpls-1/igt@i915_selftest@l...@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7977]: https://gitlab.freedesktop.org/drm/intel/issues/7977
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
Build changes
-
* Linux: CI_DRM_12670 -> Patchwork_111876v9
CI-20190529: 20190529
CI_DRM_12670: d98d1a109aa7df08b5398b29e2e90ba50b3f680a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7143: c7b12dcc460fc2348e1fa7f4dcb791bb82e29e44 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111876v9: d98d1a109aa7df08b5398b29e2e90ba50b3f680a @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
66b5bd6bd08e drm/i915/mtl: Add HDCP GSC interface
eb8882d66854 drm/i915/mtl: Add function to send command to GSC CS
1f791658d46a drm/i915/hdcp: Refactor HDCP API structures
b172ac7fe330 i915/hdcp: HDCP2.x Refactoring to agnostic hdcp
e5cf965f336a drm/i915/hdcp: Keep hdcp agonstic naming convention
3e5a24837cbe drm/i915/gsc: Create GSC request submission mechanism
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v9/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable HDCP2.x via GSC CS (rev9)
== Series Details == Series: Enable HDCP2.x via GSC CS (rev9) URL : https://patchwork.freedesktop.org/series/111876/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/4] drm/i915: Don't do the WM0->WM1 copy w/a if WM1 is already enabled
== Series Details ==
Series: series starting with [1/4] drm/i915: Don't do the WM0->WM1 copy w/a if
WM1 is already enabled
URL : https://patchwork.freedesktop.org/series/113512/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12669_full -> Patchwork_113512v1_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_113512v1_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_113512v1_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113512v1/index.html
Participating hosts (10 -> 11)
--
Additional (1): shard-rkl0
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_113512v1_full:
### IGT changes ###
Possible regressions
* igt@i915_pm_rps@engine-order:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12669/shard-glk9/igt@i915_pm_...@engine-order.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113512v1/shard-glk8/igt@i915_pm_...@engine-order.html
Known issues
Here are the changes found in Patchwork_113512v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#3886]) +2
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113512v1/shard-glk4/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
- shard-glk: NOTRUN -> [SKIP][4] ([fdo#109271]) +25 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113512v1/shard-glk4/igt@kms_frontbuffer_track...@psr-rgb565-draw-mmap-gtt.html
Possible fixes
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- {shard-rkl}:[FAIL][5] ([i915#7742]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12669/shard-rkl-1/igt@drm_fdinfo@most-busy-check-...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113512v1/shard-rkl-3/igt@drm_fdinfo@most-busy-check-...@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-glk: [FAIL][7] ([i915#2842]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12669/shard-glk4/igt@gem_exec_fair@basic-n...@vecs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113512v1/shard-glk2/igt@gem_exec_fair@basic-n...@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- {shard-rkl}:[FAIL][9] ([i915#2842]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12669/shard-rkl-3/igt@gem_exec_fair@basic-throt...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113512v1/shard-rkl-5/igt@gem_exec_fair@basic-throt...@rcs0.html
* igt@gem_pwrite@basic-self:
- {shard-rkl}:[SKIP][11] ([i915#3282]) -> [PASS][12] +3 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12669/shard-rkl-3/igt@gem_pwr...@basic-self.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113512v1/shard-rkl-5/igt@gem_pwr...@basic-self.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- {shard-rkl}:[SKIP][13] ([i915#3281]) -> [PASS][14] +13 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12669/shard-rkl-3/igt@gem_set_tiling_vs_...@tiled-to-untiled.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113512v1/shard-rkl-5/igt@gem_set_tiling_vs_...@tiled-to-untiled.html
* igt@gen9_exec_parse@valid-registers:
- {shard-rkl}:[SKIP][15] ([i915#2527]) -> [PASS][16] +3 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12669/shard-rkl-3/igt@gen9_exec_pa...@valid-registers.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113512v1/shard-rkl-5/igt@gen9_exec_pa...@valid-registers.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- {shard-dg1}:[SKIP][17] ([i915#1937]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12669/shard-dg1-17/igt@i915_pm_lpsp@kms-l...@kms-lpsp-hdmi-a.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113512v1/shard-dg1-14/igt@i915_pm_lpsp@kms-l...@kms-lpsp-hdmi-a.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [FAIL][19] ([i915#2346]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12669/shard-glk9/igt@kms_cursor_legacy@flip-vs-cur...@atomic-transitions-varying-size.html
[20]:
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Expose SAGV state via debugfs
On Tue, 31 Jan 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Since SAGV is controlled via unidirectional pcode commands
> we have no way to query the current state. So instead let's
> expose the last programmed state via debugfs. This way we
> can at least know whether SAGV should be enabled or not
> (which can be important to know when dealing with underruns/etc.).
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> .../drm/i915/display/intel_display_debugfs.c | 2 +-
> drivers/gpu/drm/i915/display/skl_watermark.c | 31 ---
> drivers/gpu/drm/i915/display/skl_watermark.h | 2 +-
> 3 files changed, 28 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 7bcd90384a46..9e2fb8626c96 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1622,7 +1622,7 @@ void intel_display_debugfs_register(struct
> drm_i915_private *i915)
> intel_dmc_debugfs_register(i915);
> intel_fbc_debugfs_register(i915);
> intel_hpd_debugfs_register(i915);
> - skl_watermark_ipc_debugfs_register(i915);
> + skl_watermark_debugfs_register(i915);
> }
>
> static int i915_panel_show(struct seq_file *m, void *data)
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 5916694f147c..022aed8dd440 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3545,13 +3545,34 @@ static const struct file_operations
> skl_watermark_ipc_status_fops = {
> .write = skl_watermark_ipc_status_write
> };
>
> -void skl_watermark_ipc_debugfs_register(struct drm_i915_private *i915)
> +static int intel_sagv_status_show(struct seq_file *m, void *unused)
> +{
> + struct drm_i915_private *i915 = m->private;
> + static const char * const sagv_status[] = {
> + [I915_SAGV_UNKNOWN] = "unknown",
> + [I915_SAGV_DISABLED] = "disabled",
> + [I915_SAGV_ENABLED] = "enabled",
> + [I915_SAGV_NOT_CONTROLLED] = "not controlled",
> + };
> +
> + seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(i915)));
> + seq_printf(m, "SAGV status: %s\n",
> sagv_status[i915->display.sagv.status]);
> + seq_printf(m, "SAGV block time: %d usec\n",
> i915->display.sagv.block_time_us);
> +
> + return 0;
> +}
> +
> +DEFINE_SHOW_ATTRIBUTE(intel_sagv_status);
> +
> +void skl_watermark_debugfs_register(struct drm_i915_private *i915)
> {
> struct drm_minor *minor = i915->drm.primary;
>
> - if (!HAS_IPC(i915))
> - return;
> + if (HAS_IPC(i915))
> + debugfs_create_file("i915_ipc_status", 0644,
> minor->debugfs_root, i915,
> + _watermark_ipc_status_fops);
>
> - debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root, i915,
> - _watermark_ipc_status_fops);
> + if (HAS_SAGV(i915))
> + debugfs_create_file("i915_sagv_status", 0444,
> minor->debugfs_root, i915,
> + _sagv_status_fops);
> }
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h
> b/drivers/gpu/drm/i915/display/skl_watermark.h
> index 37954c472070..1f81e1a5a4a3 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.h
> @@ -47,7 +47,7 @@ void intel_wm_state_verify(struct intel_crtc *crtc,
> void skl_watermark_ipc_init(struct drm_i915_private *i915);
> void skl_watermark_ipc_update(struct drm_i915_private *i915);
> bool skl_watermark_ipc_enabled(struct drm_i915_private *i915);
> -void skl_watermark_ipc_debugfs_register(struct drm_i915_private *i915);
> +void skl_watermark_debugfs_register(struct drm_i915_private *i915);
>
> void skl_wm_init(struct drm_i915_private *i915);
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Introduce HAS_SAGV()
On Tue, 31 Jan 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Introuce a HAS_SAGV() macro to answer the question whether
> the platform in general supports SAGV. intel_has_sagv() will
> keep on giving us the more specific answer whether the current
> device supports SAGV or not.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 6 +++---
> drivers/gpu/drm/i915/i915_drv.h | 3 ++-
> 2 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 0c605034356f..5916694f147c 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -64,7 +64,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private
> *i915)
> static bool
> intel_has_sagv(struct drm_i915_private *i915)
> {
> - return DISPLAY_VER(i915) >= 9 && !IS_LP(i915) &&
> + return HAS_SAGV(i915) &&
> i915->display.sagv.status != I915_SAGV_NOT_CONTROLLED;
> }
>
> @@ -92,7 +92,7 @@ intel_sagv_block_time(struct drm_i915_private *i915)
> return val;
> } else if (DISPLAY_VER(i915) == 11) {
> return 10;
> - } else if (DISPLAY_VER(i915) == 9 && !IS_LP(i915)) {
> + } else if (HAS_SAGV(i915)) {
> return 30;
> } else {
> return 0;
> @@ -101,7 +101,7 @@ intel_sagv_block_time(struct drm_i915_private *i915)
>
> static void intel_sagv_init(struct drm_i915_private *i915)
> {
> - if (!intel_has_sagv(i915))
> + if (!HAS_SAGV(i915))
> i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a0dcf3352b66..0393273faa09 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -863,7 +863,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> */
> #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
>
> -#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
> +#define HAS_IPC(dev_priv)(INTEL_INFO(dev_priv)->display.has_ipc)
> +#define HAS_SAGV(dev_priv) (DISPLAY_VER(dev_priv) >= 9 &&
> !IS_LP(dev_priv))
>
> #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
> #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH v2] drm/i915/gt: Add sysfs RAPL PL1 interface
Adding sysfs attribute rapl_pl1_freq_mhz. This shows the RAPL PL1
FREQUENCY LIMIT.
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 15 +++
drivers/gpu/drm/i915/gt/intel_rps.c | 18 ++
drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
4 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 7fa18a3b3957..1c78fc89a37a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1656,6 +1656,10 @@
#define GT0_PACKAGE_POWER_SKU_UNIT _MMIO(0x250068)
#define GT0_PLATFORM_ENERGY_STATUS _MMIO(0x25006c)
+#define XEHPSDV_RAPL_PL1_FREQ_LIMIT_MMIO(0x250070)
+#define MTL_RAPL_PL1_FREQ_LIMIT_MMIO(0x281070)
+#define RAPL_PL1_FREQ_LIMIT_MASK REG_GENMASK(15, 0)
+
/*
* Standalone Media's non-engine GT registers are located at their regular GT
* offsets plus 0x38. This extra offset is stored inside the intel_uncore
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 28f27091cd3b..0b52962e2856 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -451,6 +451,16 @@ static ssize_t punit_req_freq_mhz_show(struct kobject
*kobj,
return sysfs_emit(buff, "%u\n", preq);
}
+static ssize_t rapl_pl1_freq_mhz_show(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ char *buff)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
+ u32 rapl_pl1 = intel_rps_read_rapl_pl1(>rps);
+
+ return sysfs_emit(buff, "%u\n", rapl_pl1);
+}
+
struct intel_gt_bool_throttle_attr {
struct attribute attr;
ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
@@ -480,6 +490,7 @@ struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
}
INTEL_GT_ATTR_RO(punit_req_freq_mhz);
+INTEL_GT_ATTR_RO(rapl_pl1_freq_mhz);
static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_status,
GT0_PERF_LIMIT_REASONS_MASK);
static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl1, POWER_LIMIT_1_MASK);
static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl2, POWER_LIMIT_2_MASK);
@@ -744,6 +755,10 @@ void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct
kobject *kobj)
if (ret)
gt_warn(gt, "failed to create punit_req_freq_mhz sysfs (%pe)",
ERR_PTR(ret));
+ ret = sysfs_create_file(kobj, _rapl_pl1_freq_mhz.attr);
+ if (ret)
+ gt_warn(gt, "failed to create rapl_pl1_freq_mhz sysfs (%pe)",
ERR_PTR(ret));
+
if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
ret = sysfs_create_files(kobj, throttle_reason_attrs);
if (ret)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index f5d7b5126433..f66d6f47f2cf 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2202,6 +2202,24 @@ u32 intel_rps_get_max_frequency(struct intel_rps *rps)
return intel_gpu_freq(rps, rps->max_freq_softlimit);
}
+u32 intel_rps_read_rapl_pl1(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ u32 rapl_pl1;
+ u32 rapl;
+
+ if (IS_METEORLAKE(i915))
+ rapl_pl1 = intel_uncore_read(rps_to_gt(rps)->uncore,
MTL_RAPL_PL1_FREQ_LIMIT);
+ else if (IS_XEHPSDV(i915))
+ rapl_pl1 = intel_uncore_read(rps_to_gt(rps)->uncore,
XEHPSDV_RAPL_PL1_FREQ_LIMIT);
+
+
+ if (IS_METEORLAKE(i915) || IS_XEHPSDV(i915))
+ rapl = REG_FIELD_GET(RAPL_PL1_FREQ_LIMIT_MASK, rapl_pl1);
+
+ return rapl;
+}
+
/**
* intel_rps_get_max_raw_freq - returns the max frequency in some raw format.
* @rps: the intel_rps structure
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h
b/drivers/gpu/drm/i915/gt/intel_rps.h
index c622962c6bef..c37d297c9d82 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -51,6 +51,7 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
u32 intel_rps_read_punit_req(struct intel_rps *rps);
u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
+u32 intel_rps_read_rapl_pl1(struct intel_rps *rps);
u32 intel_rps_read_rpstat(struct intel_rps *rps);
u32 intel_rps_read_rpstat_fw(struct intel_rps *rps);
void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps
*caps);
--
2.34.1
Re: [Intel-gfx] [PATCH 0/8] drm/i915: LVDS cleanup
On Mon, 30 Jan 2023, Ville Syrjala wrote: > From: Ville Syrjälä > > Some cleanup/modernization of the LVDS code. Please spell check the commit messages, otherwise the series is Reviewed-by: Jani Nikula > > Ville Syrjälä (8): > drm/i915/lvds: Split long lines > drm/i915/lvds: Use intel_de_rmw() > drm/i915/lvds: Use REG_BIT() & co. > drm/i915/lvds: Extract intel_lvds_regs.h > drm/i915/lvds: Fix whitespace > drm/i915/lvds: s/dev_priv/i915/ > drm/i915/lvds: s/intel_encoder/encoder/ etc. > drm/i915/lvds: s/pipe_config/crtc_state/ > > drivers/gpu/drm/i915/display/intel_display.c | 1 + > drivers/gpu/drm/i915/display/intel_lvds.c | 332 +- > .../gpu/drm/i915/display/intel_lvds_regs.h| 65 > drivers/gpu/drm/i915/display/intel_panel.c| 1 + > .../gpu/drm/i915/display/intel_pch_display.c | 1 + > drivers/gpu/drm/i915/display/intel_pps.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 56 --- > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + > 8 files changed, 232 insertions(+), 226 deletions(-) > create mode 100644 drivers/gpu/drm/i915/display/intel_lvds_regs.h -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Prefix hex numbers with 0x
On Mon, 30 Jan 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> It's hard to figure out whether the number is hex
> or decimal if doesn't have the 0x to indicate hex.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 599c6d399de4..524f93768c41 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -125,8 +125,8 @@ void intel_device_info_print(const struct
> intel_device_info *info,
> drm_printf(p, "base die stepping: %s\n",
> intel_step_name(runtime->step.basedie_step));
>
> drm_printf(p, "gt: %d\n", info->gt);
> - drm_printf(p, "memory-regions: %x\n", runtime->memory_regions);
> - drm_printf(p, "page-sizes: %x\n", runtime->page_sizes);
> + drm_printf(p, "memory-regions: 0x%x\n", runtime->memory_regions);
> + drm_printf(p, "page-sizes: 0x%x\n", runtime->page_sizes);
> drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
> drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size);
> drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type);
> @@ -540,5 +540,5 @@ void intel_driver_caps_print(const struct
> intel_driver_caps *caps,
> {
> drm_printf(p, "Has logical contexts? %s\n",
> str_yes_no(caps->has_logical_contexts));
> - drm_printf(p, "scheduler: %x\n", caps->scheduler);
> + drm_printf(p, "scheduler: 0x%x\n", caps->scheduler);
> }
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Include stepping informaiton in device info dump
On Tue, 31 Jan 2023, Jani Nikula wrote: > On Mon, 30 Jan 2023, Ville Syrjala wrote: >> From: Ville Syrjälä >> >> Dump the stepping information alongside all the other device >> info. Might avoid some guesswork when reading logs. >> >> Signed-off-by: Ville Syrjälä > > Reviewed-by: Jani Nikula *information in the subject line, can be fixed while applying. > >> --- >> drivers/gpu/drm/i915/intel_device_info.c | 5 + >> 1 file changed, 5 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c >> b/drivers/gpu/drm/i915/intel_device_info.c >> index 98769e5f2c3d..599c6d399de4 100644 >> --- a/drivers/gpu/drm/i915/intel_device_info.c >> +++ b/drivers/gpu/drm/i915/intel_device_info.c >> @@ -119,6 +119,11 @@ void intel_device_info_print(const struct >> intel_device_info *info, >> drm_printf(p, "display version: %u\n", >> runtime->display.ip.ver); >> >> +drm_printf(p, "graphics stepping: %s\n", >> intel_step_name(runtime->step.graphics_step)); >> +drm_printf(p, "media stepping: %s\n", >> intel_step_name(runtime->step.media_step)); >> +drm_printf(p, "display stepping: %s\n", >> intel_step_name(runtime->step.display_step)); >> +drm_printf(p, "base die stepping: %s\n", >> intel_step_name(runtime->step.basedie_step)); >> + >> drm_printf(p, "gt: %d\n", info->gt); >> drm_printf(p, "memory-regions: %x\n", runtime->memory_regions); >> drm_printf(p, "page-sizes: %x\n", runtime->page_sizes); -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Include stepping informaiton in device info dump
On Mon, 30 Jan 2023, Ville Syrjala wrote: > From: Ville Syrjälä > > Dump the stepping information alongside all the other device > info. Might avoid some guesswork when reading logs. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/intel_device_info.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c > b/drivers/gpu/drm/i915/intel_device_info.c > index 98769e5f2c3d..599c6d399de4 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -119,6 +119,11 @@ void intel_device_info_print(const struct > intel_device_info *info, > drm_printf(p, "display version: %u\n", > runtime->display.ip.ver); > > + drm_printf(p, "graphics stepping: %s\n", > intel_step_name(runtime->step.graphics_step)); > + drm_printf(p, "media stepping: %s\n", > intel_step_name(runtime->step.media_step)); > + drm_printf(p, "display stepping: %s\n", > intel_step_name(runtime->step.display_step)); > + drm_printf(p, "base die stepping: %s\n", > intel_step_name(runtime->step.basedie_step)); > + > drm_printf(p, "gt: %d\n", info->gt); > drm_printf(p, "memory-regions: %x\n", runtime->memory_regions); > drm_printf(p, "page-sizes: %x\n", runtime->page_sizes); -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] linux-next: manual merge of the usb tree with the drm-intel-fixes tree
On Tue, Jan 31, 2023 at 01:03:05PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the usb tree got a conflict in:
>
> drivers/gpu/drm/i915/gt/intel_engine_cs.c
>
> between commit:
>
> 5bc4b43d5c6c ("drm/i915: Fix up locking around dumping requests lists")
>
> from the drm-intel-fixes tree and commit:
>
> 4d70c74659d9 ("i915: Move list_count() to list.h as list_count_nodes() for
> broader use")
>
> from the usb tree.
>
> I fixed it up (the former removed the code changed by the latter) and
> can carry the fix as necessary. This is now fixed as far as linux-next
> is concerned, but any non trivial conflicts should be mentioned to your
> upstream maintainer when your tree is submitted for merging. You may
> also want to consider cooperating with the maintainer of the conflicting
> tree to minimise any particularly complex conflicts.
Thanks for the merge resolution.
greg k-h
[Intel-gfx] [PATCH v9 6/6] drm/i915/mtl: Add HDCP GSC interface
MTL uses GSC command streamer i.e gsc cs to send HDCP/PXP commands
to GSC f/w. It requires to keep hdcp display driver
agnostic to content protection f/w (ME/GSC fw) in the form of
i915_hdcp_fw_ops generic ops.
Adding HDCP GSC CS interface by leveraging the i915_hdcp_fw_ops generic
ops instead of I915_HDCP_COMPONENT as integral part of i915.
Adding checks to see if GSC is loaded and proxy is setup
--v6
-dont change the license date in same patch series [Jani]
-fix the license year {Jani]
--v8
-remove stale comment [Ankit]
-get headers in alphabetical order [Ankit]
-fix hdcp2_supported check [Ankit]
--v9
-remove return statement from hdcp_gsc_fini [Ankit]
Cc: Tomas Winkler
Cc: Rodrigo Vivi
Cc: Uma Shankar
Cc: Ankit Nautiyal
Signed-off-by: Anshuman Gupta
Signed-off-by: Suraj Kandpal
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 28 +-
drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 637 +-
drivers/gpu/drm/i915/display/intel_hdcp_gsc.h | 3 +
3 files changed, 660 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 0d6aed1eb171..61bb2bbd0349 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -23,6 +23,7 @@
#include "intel_display_power_well.h"
#include "intel_display_types.h"
#include "intel_hdcp.h"
+#include "intel_hdcp_gsc.h"
#include "intel_hdcp_regs.h"
#include "intel_pcode.h"
@@ -203,13 +204,20 @@ bool intel_hdcp2_capable(struct intel_connector
*connector)
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = >hdcp;
+ struct intel_gt *gt = dev_priv->media_gt;
+ struct intel_gsc_uc *gsc = >uc.gsc;
bool capable = false;
/* I915 support for HDCP2.2 */
if (!hdcp->hdcp2_supported)
return false;
- /* MEI interface is solid */
+ /* If MTL+ make sure gsc is loaded and proxy is setup */
+ if (intel_hdcp_gsc_cs_required(dev_priv))
+ if (!intel_uc_fw_is_running(>fw))
+ return false;
+
+ /* MEI/GSC interface is solid depending on which is used */
mutex_lock(_priv->display.hdcp.comp_mutex);
if (!dev_priv->display.hdcp.comp_added ||
!dev_priv->display.hdcp.master) {
mutex_unlock(_priv->display.hdcp.comp_mutex);
@@ -2235,6 +2243,9 @@ static int initialize_hdcp_port_data(struct
intel_connector *connector,
static bool is_hdcp2_supported(struct drm_i915_private *dev_priv)
{
+ if (intel_hdcp_gsc_cs_required(dev_priv))
+ return true;
+
if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP))
return false;
@@ -2256,10 +2267,14 @@ void intel_hdcp_component_init(struct drm_i915_private
*dev_priv)
dev_priv->display.hdcp.comp_added = true;
mutex_unlock(_priv->display.hdcp.comp_mutex);
- ret = component_add_typed(dev_priv->drm.dev, _hdcp_ops,
- I915_COMPONENT_HDCP);
+ if (intel_hdcp_gsc_cs_required(dev_priv))
+ ret = intel_hdcp_gsc_init(dev_priv);
+ else
+ ret = component_add_typed(dev_priv->drm.dev, _hdcp_ops,
+ I915_COMPONENT_HDCP);
+
if (ret < 0) {
- drm_dbg_kms(_priv->drm, "Failed at component add(%d)\n",
+ drm_dbg_kms(_priv->drm, "Failed at fw component add(%d)\n",
ret);
mutex_lock(_priv->display.hdcp.comp_mutex);
dev_priv->display.hdcp.comp_added = false;
@@ -2486,7 +2501,10 @@ void intel_hdcp_component_fini(struct drm_i915_private
*dev_priv)
dev_priv->display.hdcp.comp_added = false;
mutex_unlock(_priv->display.hdcp.comp_mutex);
- component_del(dev_priv->drm.dev, _hdcp_ops);
+ if (intel_hdcp_gsc_cs_required(dev_priv))
+ intel_hdcp_gsc_fini(dev_priv);
+ else
+ component_del(dev_priv->drm.dev, _hdcp_ops);
}
void intel_hdcp_cleanup(struct intel_connector *connector)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
index 6bf81414d34f..6f123a107e5f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
@@ -3,12 +3,617 @@
* Copyright 2023, Intel Corporation.
*/
+#include
+
#include "display/intel_hdcp_gsc.h"
#include "gem/i915_gem_region.h"
#include "gt/uc/intel_gsc_uc_heci_cmd_submit.h"
#include "i915_drv.h"
#include "i915_utils.h"
+bool intel_hdcp_gsc_cs_required(struct drm_i915_private *i915)
+{
+ return DISPLAY_VER(i915) >= 14;
+}
+
+static int
+gsc_hdcp_initiate_session(struct device *dev, struct hdcp_port_data *data,
+ struct hdcp2_ake_init
[Intel-gfx] [PATCH v9 5/6] drm/i915/mtl: Add function to send command to GSC CS
Add function that takes care of sending command to gsc cs. We start
of with allocation of memory for our command intel_hdcp_gsc_message that
contains gsc cs memory header as directed in specs followed by the
actual payload hdcp message that we want to send.
Spec states that we need to poll pending bit of response header around
20 times each try being 50ms apart hence adding that to current
gsc_msg_send function
Also we use the same function to take care of both sending and receiving
hence no separate function to get the response.
--v4
-Create common function to fill in gsc_mtl_header [Alan]
-define host session bitmask [Alan]
--v5
-use i915 directly instead of gt->i915 [Alan]
-No need to make fields NULL as we are already
using kzalloc [Alan]
--v8
-change mechanism to reuse the same memory for one hdcp session[Alan]
-fix header ordering
-add comments to explain flags and host session mask [Alan]
--v9
-remove gem obj from hdcp message as we can use
i915_vma_unpin_and_release [Alan]
-move hdcp message allocation and deallocation from hdcp2_enable and
hdcp2_disable to init and teardown of HDCP [Alan]
Cc: Ankit Nautiyal
Cc: Daniele Ceraolo Spurio
Cc: Alan Pervin Teres
Cc: Uma Shankar
Cc: Anshuman Gupta
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/display/intel_display_core.h | 5 +
drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 200 ++
drivers/gpu/drm/i915/display/intel_hdcp_gsc.h | 23 ++
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 15 ++
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 16 ++
6 files changed, 260 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
create mode 100644 drivers/gpu/drm/i915/display/intel_hdcp_gsc.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 482928cffb1c..ba76bec715af 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -255,6 +255,7 @@ i915-y += \
display/intel_frontbuffer.o \
display/intel_global_state.o \
display/intel_hdcp.o \
+ display/intel_hdcp_gsc.o \
display/intel_hotplug.o \
display/intel_hti.o \
display/intel_lpe_audio.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 139100fe2383..20d2a79a5d05 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -382,6 +382,11 @@ struct intel_display {
struct i915_hdcp_master *master;
bool comp_added;
+ /*HDCP message struct for allocation of memory which can be
reused
+* when sending message to gsc cs
+* this is only populated post Meteorlake
+*/
+ struct intel_hdcp_gsc_message *hdcp_message;
/* Mutex to protect the above hdcp component related values. */
struct mutex comp_mutex;
} hdcp;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
new file mode 100644
index ..6bf81414d34f
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2023, Intel Corporation.
+ */
+
+#include "display/intel_hdcp_gsc.h"
+#include "gem/i915_gem_region.h"
+#include "gt/uc/intel_gsc_uc_heci_cmd_submit.h"
+#include "i915_drv.h"
+#include "i915_utils.h"
+
+/*This function helps allocate memory for the command that we will send to gsc
cs */
+static int intel_hdcp_gsc_initialize_message(struct drm_i915_private *i915,
+struct intel_hdcp_gsc_message
*hdcp_message)
+{
+ struct intel_gt *gt = i915->media_gt;
+ struct drm_i915_gem_object *obj = NULL;
+ struct i915_vma *vma = NULL;
+ void *cmd;
+ int err;
+
+ /* allocate object of one page for HDCP command memory and store it */
+ obj = i915_gem_object_create_shmem(i915, PAGE_SIZE);
+
+ if (IS_ERR(obj)) {
+ drm_err(>drm, "Failed to allocate HDCP streaming
command!\n");
+ return PTR_ERR(obj);
+ }
+
+ cmd = i915_gem_object_pin_map_unlocked(obj,
i915_coherent_map_type(i915, obj, true));
+ if (IS_ERR(cmd)) {
+ drm_err(>drm, "Failed to map gsc message page!\n");
+ err = PTR_ERR(cmd);
+ goto out_unpin;
+ }
+
+ vma = i915_vma_instance(obj, >ggtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_unmap;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+ if (err)
+ goto out_unmap;
+
+ memset(cmd, 0, obj->base.size);
+
+ hdcp_message->hdcp_cmd = cmd;
+ hdcp_message->vma = vma;
+
+ return 0;
+
+out_unmap:
+ i915_gem_object_unpin_map(obj);
[Intel-gfx] [PATCH v9 4/6] drm/i915/hdcp: Refactor HDCP API structures
It requires to move intel specific HDCP API structures to
i915_hdcp_interface.h from driver/misc/mei/hdcp/mei_hdcp.h
so that any content protection fw interfaces can use these
structures.
Cc: Tomas Winkler
Cc: Rodrigo Vivi
Cc: Uma Shankar
Cc: Ankit Nautiyal
Signed-off-by: Anshuman Gupta
Signed-off-by: Suraj Kandpal
Reviewed-by: Ankit Nautiyal
---
drivers/misc/mei/hdcp/mei_hdcp.c | 44 ++--
drivers/misc/mei/hdcp/mei_hdcp.h | 354 -
include/drm/i915_hdcp_interface.h | 355 ++
3 files changed, 377 insertions(+), 376 deletions(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index b2c49599809c..a262e1fa3b48 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -52,7 +52,7 @@ mei_hdcp_initiate_session(struct device *dev, struct
hdcp_port_data *data,
session_init_in.header.api_version = HDCP_API_VERSION;
session_init_in.header.command_id = WIRED_INITIATE_HDCP2_SESSION;
- session_init_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ session_init_in.header.status = FW_HDCP_STATUS_SUCCESS;
session_init_in.header.buffer_len =
WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN;
@@ -75,7 +75,7 @@ mei_hdcp_initiate_session(struct device *dev, struct
hdcp_port_data *data,
return byte;
}
- if (session_init_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+ if (session_init_out.header.status != FW_HDCP_STATUS_SUCCESS) {
dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
WIRED_INITIATE_HDCP2_SESSION,
session_init_out.header.status);
@@ -122,7 +122,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device *dev,
verify_rxcert_in.header.api_version = HDCP_API_VERSION;
verify_rxcert_in.header.command_id = WIRED_VERIFY_RECEIVER_CERT;
- verify_rxcert_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ verify_rxcert_in.header.status = FW_HDCP_STATUS_SUCCESS;
verify_rxcert_in.header.buffer_len =
WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN;
@@ -148,7 +148,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device *dev,
return byte;
}
- if (verify_rxcert_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+ if (verify_rxcert_out.header.status != FW_HDCP_STATUS_SUCCESS) {
dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
WIRED_VERIFY_RECEIVER_CERT,
verify_rxcert_out.header.status);
@@ -194,7 +194,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct
hdcp_port_data *data,
send_hprime_in.header.api_version = HDCP_API_VERSION;
send_hprime_in.header.command_id = WIRED_AKE_SEND_HPRIME;
- send_hprime_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ send_hprime_in.header.status = FW_HDCP_STATUS_SUCCESS;
send_hprime_in.header.buffer_len = WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN;
send_hprime_in.port.integrated_port_type = data->port_type;
@@ -218,7 +218,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct
hdcp_port_data *data,
return byte;
}
- if (send_hprime_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+ if (send_hprime_out.header.status != FW_HDCP_STATUS_SUCCESS) {
dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
WIRED_AKE_SEND_HPRIME, send_hprime_out.header.status);
return -EIO;
@@ -251,7 +251,7 @@ mei_hdcp_store_pairing_info(struct device *dev, struct
hdcp_port_data *data,
pairing_info_in.header.api_version = HDCP_API_VERSION;
pairing_info_in.header.command_id = WIRED_AKE_SEND_PAIRING_INFO;
- pairing_info_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ pairing_info_in.header.status = FW_HDCP_STATUS_SUCCESS;
pairing_info_in.header.buffer_len =
WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN;
@@ -276,7 +276,7 @@ mei_hdcp_store_pairing_info(struct device *dev, struct
hdcp_port_data *data,
return byte;
}
- if (pairing_info_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+ if (pairing_info_out.header.status != FW_HDCP_STATUS_SUCCESS) {
dev_dbg(dev, "ME cmd 0x%08X failed. Status: 0x%X\n",
WIRED_AKE_SEND_PAIRING_INFO,
pairing_info_out.header.status);
@@ -311,7 +311,7 @@ mei_hdcp_initiate_locality_check(struct device *dev,
lc_init_in.header.api_version = HDCP_API_VERSION;
lc_init_in.header.command_id = WIRED_INIT_LOCALITY_CHECK;
- lc_init_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ lc_init_in.header.status = FW_HDCP_STATUS_SUCCESS;
lc_init_in.header.buffer_len = WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN;
[Intel-gfx] [PATCH v9 3/6] i915/hdcp: HDCP2.x Refactoring to agnostic hdcp
As now we have more then one type of content protection
secrity firmware. Let change the i915_hdcp_interface.h
header naming convention to suit generic f/w type.
%s/MEI_/HDCP_
%s/mei_dev/hdcp_dev
As interface to CP FW can be either a non i915 component or
i915 intergral component, change structure name Accordingly.
%s/i915_hdcp_comp_master/i915_hdcp_master
%s/i915_hdcp_component_ops/i915_hdcp_ops
--v3
-Changing names to drop cp_fw to make naming more agnostic[Jani]
Cc: Tomas Winkler
Cc: Rodrigo Vivi
Cc: Uma Shankar
Cc: Ankit Nautiyal
Signed-off-by: Anshuman Gupta
Signed-off-by: Suraj Kandpal
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display_core.h | 1 +
drivers/gpu/drm/i915/display/intel_hdcp.c | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 8e7a68339876..139100fe2383 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -15,6 +15,7 @@
#include
#include
+#include
#include "intel_cdclk.h"
#include "intel_display_limits.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 262c76f21801..0d6aed1eb171 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1409,7 +1409,7 @@ static int hdcp2_authenticate_port(struct intel_connector
*connector)
return ret;
}
-static int hdcp2_close_mei_session(struct intel_connector *connector)
+static int hdcp2_close_session(struct intel_connector *connector)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
@@ -1433,7 +1433,7 @@ static int hdcp2_close_mei_session(struct intel_connector
*connector)
static int hdcp2_deauthenticate_port(struct intel_connector *connector)
{
- return hdcp2_close_mei_session(connector);
+ return hdcp2_close_session(connector);
}
/* Authentication flow starts from here */
--
2.25.1
[Intel-gfx] [PATCH v9 2/6] drm/i915/hdcp: Keep hdcp agonstic naming convention
From: Anshuman Gupta
Change the include/drm/i915_mei_hdcp_interface.h to
include/drm/i915_hdcp_interface.h
--v6
-make each patch build individually [Jani]
--v8
-change ME FW to ME/GSC FW [Ankit]
-fix formatting issue [Ankit]
Cc: Tomas Winkler
Cc: Rodrigo Vivi
Cc: Uma Shankar
Cc: Ankit Nautiyal
Signed-off-by: Anshuman Gupta
Signed-off-by: Suraj Kandpal
Reviewed-by: Ankit Nautiyal
Acked-by: Tomas Winkler
---
.../gpu/drm/i915/display/intel_display_core.h | 2 +-
.../drm/i915/display/intel_display_types.h| 2 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 81
drivers/misc/mei/hdcp/mei_hdcp.c | 61 ++--
...hdcp_interface.h => i915_hdcp_interface.h} | 92 +--
5 files changed, 118 insertions(+), 120 deletions(-)
rename include/drm/{i915_mei_hdcp_interface.h => i915_hdcp_interface.h} (73%)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index fb8670aa2932..8e7a68339876 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -378,7 +378,7 @@ struct intel_display {
} gmbus;
struct {
- struct i915_hdcp_comp_master *master;
+ struct i915_hdcp_master *master;
bool comp_added;
/* Mutex to protect the above hdcp component related values. */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9ccae7a46020..7accd3a8877c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -43,7 +43,7 @@
#include
#include
#include
-#include
+#include
#include
#include "i915_vma.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 6406fd487ee5..262c76f21801 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1143,7 +1143,7 @@ hdcp2_prepare_ake_init(struct intel_connector *connector,
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct hdcp_port_data *data = _port->hdcp_port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- struct i915_hdcp_comp_master *comp;
+ struct i915_hdcp_master *comp;
int ret;
mutex_lock(_priv->display.hdcp.comp_mutex);
@@ -1154,7 +1154,7 @@ hdcp2_prepare_ake_init(struct intel_connector *connector,
return -EINVAL;
}
- ret = comp->ops->initiate_hdcp2_session(comp->mei_dev, data, ake_data);
+ ret = comp->ops->initiate_hdcp2_session(comp->hdcp_dev, data, ake_data);
if (ret)
drm_dbg_kms(_priv->drm, "Prepare_ake_init failed. %d\n",
ret);
@@ -1173,7 +1173,7 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct hdcp_port_data *data = _port->hdcp_port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- struct i915_hdcp_comp_master *comp;
+ struct i915_hdcp_master *comp;
int ret;
mutex_lock(_priv->display.hdcp.comp_mutex);
@@ -1184,7 +1184,7 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
return -EINVAL;
}
- ret = comp->ops->verify_receiver_cert_prepare_km(comp->mei_dev, data,
+ ret = comp->ops->verify_receiver_cert_prepare_km(comp->hdcp_dev, data,
rx_cert, paired,
ek_pub_km, msg_sz);
if (ret < 0)
@@ -1201,7 +1201,7 @@ static int hdcp2_verify_hprime(struct intel_connector
*connector,
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct hdcp_port_data *data = _port->hdcp_port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- struct i915_hdcp_comp_master *comp;
+ struct i915_hdcp_master *comp;
int ret;
mutex_lock(_priv->display.hdcp.comp_mutex);
@@ -1212,7 +1212,7 @@ static int hdcp2_verify_hprime(struct intel_connector
*connector,
return -EINVAL;
}
- ret = comp->ops->verify_hprime(comp->mei_dev, data, rx_hprime);
+ ret = comp->ops->verify_hprime(comp->hdcp_dev, data, rx_hprime);
if (ret < 0)
drm_dbg_kms(_priv->drm, "Verify hprime failed. %d\n", ret);
mutex_unlock(_priv->display.hdcp.comp_mutex);
@@ -1227,7 +1227,7 @@ hdcp2_store_pairing_info(struct intel_connector
*connector,
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct hdcp_port_data *data = _port->hdcp_port_data;
struct drm_i915_private
[Intel-gfx] [PATCH v9 1/6] drm/i915/gsc: Create GSC request submission mechanism
HDCP and PXP will require a common function to allow it to
submit commands to the gsc cs. Also adding the gsc mtl header
that needs to be added on to the existing payloads of HDCP
and PXP.
--v4
-Seprate gsc load and heci cmd submission into different
functions in different files for better scalability [Alan]
-Rename gsc address field [Alan]
Cc: Daniele Ceraolo Spurio
Cc: Alan Previn
Signed-off-by: Suraj Kandpal
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h | 1 +
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 94 +++
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 45 +
5 files changed, 143 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 918470a04591..482928cffb1c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -195,6 +195,7 @@ i915-y += \
i915-y += \
gt/uc/intel_gsc_fw.o \
gt/uc/intel_gsc_uc.o \
+ gt/uc/intel_gsc_uc_heci_cmd_submit.o\
gt/uc/intel_guc.o \
gt/uc/intel_guc_ads.o \
gt/uc/intel_guc_capture.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 2af1ae3831df..454179884801 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -439,6 +439,8 @@
#define GSC_FW_LOAD GSC_INSTR(1, 0, 2)
#define HECI1_FW_LIMIT_VALID (1 << 31)
+#define GSC_HECI_CMD_PKT GSC_INSTR(0, 0, 6)
+
/*
* Used to convert any address to canonical form.
* Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
index 4b5dbb44afb4..146ac0128f69 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
@@ -12,4 +12,5 @@ struct intel_gsc_uc;
int intel_gsc_uc_fw_upload(struct intel_gsc_uc *gsc);
bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc);
+
#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
new file mode 100644
index ..be2424af521d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_ring.h"
+#include "intel_gsc_uc_heci_cmd_submit.h"
+
+struct gsc_heci_pkt {
+ u64 addr_in;
+ u32 size_in;
+ u64 addr_out;
+ u32 size_out;
+};
+
+static int emit_gsc_heci_pkt(struct i915_request *rq, struct gsc_heci_pkt *pkt)
+{
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 8);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ *cs++ = GSC_HECI_CMD_PKT;
+ *cs++ = lower_32_bits(pkt->addr_in);
+ *cs++ = upper_32_bits(pkt->addr_in);
+ *cs++ = pkt->size_in;
+ *cs++ = lower_32_bits(pkt->addr_out);
+ *cs++ = upper_32_bits(pkt->addr_out);
+ *cs++ = pkt->size_out;
+ *cs++ = 0;
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+int intel_gsc_uc_heci_cmd_submit_packet(struct intel_gsc_uc *gsc, u64 addr_in,
+ u32 size_in, u64 addr_out,
+ u32 size_out)
+{
+ struct intel_context *ce = gsc->ce;
+ struct i915_request *rq;
+ struct gsc_heci_pkt pkt = {
+ .addr_in = addr_in,
+ .size_in = size_in,
+ .addr_out = addr_out,
+ .size_out = size_out
+ };
+ int err;
+
+ if (!ce)
+ return -ENODEV;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ if (ce->engine->emit_init_breadcrumb) {
+ err = ce->engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_rq;
+ }
+
+ err = emit_gsc_heci_pkt(rq, );
+
+ if (err)
+ goto out_rq;
+
+ err = ce->engine->emit_flush(rq, 0);
+
+out_rq:
+ i915_request_get(rq);
+
+ if (unlikely(err))
+ i915_request_set_error_once(rq, err);
+
+ i915_request_add(rq);
+
+ if (!err && i915_request_wait(rq, 0, msecs_to_jiffies(500)) < 0)
+ err = -ETIME;
+
+ i915_request_put(rq);
+
+ if (err)
+ drm_err(_uc_to_gt(gsc)->i915->drm,
+ "Request submission for GSC heci cmd failed (%d)\n",
+ err);
+
+ return err;
+}
diff --git
Re: [Intel-gfx] [PATCH v3] drm/i915/hdmi: Go for scrambling only if platform supports TMDS clock > 340MHz
> -Original Message-
> From: Intel-gfx On Behalf Of Ankit
> Nautiyal
> Sent: Thursday, December 22, 2022 9:39 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3] drm/i915/hdmi: Go for scrambling only if
> platform
> supports TMDS clock > 340MHz
>
> There are cases, where devices have an HDMI1.4 retimer, and TMDS clock rate is
> capped to 340MHz via VBT. In such cases scrambling might be supported by the
> platform and an HDMI2.0 sink for lower TMDS rates, but not supported by the
> retimer, causing blankouts.
>
> So avoid enabling scrambling, if the TMDS clock is capped to <= 340MHz.
>
> v2: Added comment, documenting the rationale to check for TMDS clock, before
> going for scrambling. (Arun)
>
> v3: Fixed the function name to check if source supports scrambling. (Jani)
Pushed to drm-intel-next. Thanks for the patch and reviews.
Regards,
Uma Shankar
> Signed-off-by: Ankit Nautiyal
> Reviewed-by: Arun R Murthy
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 21 -
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index efa2da080f62..dd3465f992f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2244,6 +2244,25 @@ static bool intel_hdmi_is_cloned(const struct
> intel_crtc_state *crtc_state)
> !is_power_of_2(crtc_state->uapi.encoder_mask);
> }
>
> +static bool source_supports_scrambling(struct intel_encoder *encoder) {
> + /*
> + * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and
> + * scrambling is supported.
> + * But there seem to be cases where certain platforms that support
> + * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is
> + * capped by VBT to less than 340MHz.
> + *
> + * In such cases when an HDMI2.0 sink is connected, it creates a
> + * problem : the platform and the sink both support scrambling but the
> + * HDMI 1.4 retimer chip doesn't.
> + *
> + * So go for scrambling, based on the max tmds clock taking into
> account,
> + * restrictions coming from VBT.
> + */
> + return intel_hdmi_source_max_tmds_clock(encoder) > 34; }
> +
> int intel_hdmi_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state) @@ -2301,7
> +2320,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
>
> pipe_config->lane_count = 4;
>
> - if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
> + if (scdc->scrambling.supported && source_supports_scrambling(encoder))
> +{
> if (scdc->scrambling.low_rates)
> pipe_config->hdmi_scrambling = true;
>
> --
> 2.25.1
[Intel-gfx] [PATCH v9 0/6] Enable HDCP2.x via GSC CS
These patches enable HDCP2.x on machines MTL and above. >From MTL onwards CSME is spilt into GSC and CSC and now we use GSC CS instead of MEI to talk to firmware to start HDCP authentication --v2 -Fixing some checkpatch changes which I forgot before sending out the series --v3 -Drop cp and fw to make naming more agnostic[Jani] -Sort header[Jani] -remove static inline function from i915_hdcp_interface[Jani] -abstract DISPLAY_VER check[Jani] --v4 -Remove stale comment P2 [Jani] -Fix part where file rename looks like its removed in P2 and added in P3 [Jani] -Add bitmask definition for host session id[Alan] -Seprating gsc load and heci cmd submission into different funcs[Alan] -Create comman function to fill gsc_mtl_header[Alan] --v5 -No need to make hdcp_message field null as we use kzalloc [Alan] -use i915->drm instead of gt->i915->drm [Alan] --v6 -Make each patch build individually [Jani] -drop cp_fw stale commit subject [Jani] -fix the date on license [Jani] -revert back to orginal design where mei and gsc fill their own header --v7 -remove RB by Ankit --v8 -change design to allocate and deallocate hdcp_message only at enablement and disabling of hdcp [Alan] -fix few formatting issue [Ankit] -fix stale comments [Ankit] --v9 -move allocation dealloc of hdcp messgae to init and teardown [Alan] -remove obj from hdcp message , use i915_vma_unpin_and_release [Alan] -remove return statement from intel_hdcp_gsc_fini [Ankit] Anshuman Gupta (1): drm/i915/hdcp: Keep hdcp agonstic naming convention Suraj Kandpal (5): drm/i915/gsc: Create GSC request submission mechanism i915/hdcp: HDCP2.x Refactoring to agnostic hdcp drm/i915/hdcp: Refactor HDCP API structures drm/i915/mtl: Add function to send command to GSC CS drm/i915/mtl: Add HDCP GSC interface drivers/gpu/drm/i915/Makefile | 2 + .../gpu/drm/i915/display/intel_display_core.h | 8 +- .../drm/i915/display/intel_display_types.h| 2 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 109 ++- drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 831 ++ drivers/gpu/drm/i915/display/intel_hdcp_gsc.h | 26 + drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 + drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h | 1 + .../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 109 +++ .../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 61 ++ drivers/misc/mei/hdcp/mei_hdcp.c | 105 ++- drivers/misc/mei/hdcp/mei_hdcp.h | 354 include/drm/i915_hdcp_interface.h | 539 include/drm/i915_mei_hdcp_interface.h | 184 14 files changed, 1694 insertions(+), 639 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_hdcp_gsc.c create mode 100644 drivers/gpu/drm/i915/display/intel_hdcp_gsc.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h create mode 100644 include/drm/i915_hdcp_interface.h delete mode 100644 include/drm/i915_mei_hdcp_interface.h -- 2.25.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Include stepping informaiton in device info dump (rev2)
== Series Details ==
Series: series starting with [1/2] drm/i915: Include stepping informaiton in
device info dump (rev2)
URL : https://patchwork.freedesktop.org/series/113504/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12668_full -> Patchwork_113504v2_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_113504v2_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_113504v2_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v2/index.html
Participating hosts (11 -> 11)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_113504v2_full:
### IGT changes ###
Possible regressions
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
- shard-glk: [PASS][1] -> [TIMEOUT][2] +2 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12668/shard-glk5/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-spr-indfb-onoff.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v2/shard-glk6/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-spr-indfb-onoff.html
Known issues
Here are the changes found in Patchwork_113504v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12668/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v2/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_lmem_swapping@verify-random:
- shard-glk: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v2/shard-glk9/igt@gem_lmem_swapp...@verify-random.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3886])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v2/shard-glk9/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_cursor_crc@cursor-random-max-size:
- shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271]) +45 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v2/shard-glk9/igt@kms_cursor_...@cursor-random-max-size.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#2346])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12668/shard-glk9/igt@kms_cursor_legacy@flip-vs-cur...@atomic-transitions-varying-size.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v2/shard-glk2/igt@kms_cursor_legacy@flip-vs-cur...@atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][10] -> [FAIL][11] ([i915#79]) +1 similar issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12668/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v2/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-glk: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#658])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v2/shard-glk9/igt@kms_psr2...@plane-move-sf-dmg-area.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v2/shard-glk9/igt@kms_vbl...@pipe-d-wait-idle.html
* igt@perf@enable-disable:
- shard-glk: [PASS][14] -> [TIMEOUT][15] ([i915#6943])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12668/shard-glk5/igt@p...@enable-disable.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v2/shard-glk6/igt@p...@enable-disable.html
Possible fixes
* igt@drm_fdinfo@idle@rcs0:
- {shard-rkl}:[FAIL][16] ([i915#7742]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12668/shard-rkl-6/igt@drm_fdinfo@i...@rcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v2/shard-rkl-6/igt@drm_fdinfo@i...@rcs0.html
* igt@fbdev@read:
- {shard-rkl}:[SKIP][18] ([i915#2582]) -> [PASS][19] +1 similar
issue
[18]:
Re: [Intel-gfx] [PATCH v8 6/6] drm/i915/mtl: Add HDCP GSC interface
Hi Suraj,
Minor suggestions inline.
Otherwise patch looks good to me.
Reviewed-by: Ankit Nautiyal
On 1/24/2023 3:12 PM, Suraj Kandpal wrote:
MTL uses GSC command streamer i.e gsc cs to send HDCP/PXP commands
to GSC f/w. It requires to keep hdcp display driver
agnostic to content protection f/w (ME/GSC fw) in the form of
i915_hdcp_fw_ops generic ops.
Adding HDCP GSC CS interface by leveraging the i915_hdcp_fw_ops generic
ops instead of I915_HDCP_COMPONENT as integral part of i915.
Adding checks to see if GSC is loaded and proxy is setup
--v6
-dont change the license date in same patch series [Jani]
-fix the license year {Jani]
--v8
-remove stale comment [Ankit]
-get headers in alphabetical order [Ankit]
-fix hdcp2_supported check [Ankit]
Cc: Tomas Winkler
Cc: Rodrigo Vivi
Cc: Uma Shankar
Cc: Ankit Nautiyal
Signed-off-by: Anshuman Gupta
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 31 +-
drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 631 +-
drivers/gpu/drm/i915/display/intel_hdcp_gsc.h | 3 +
3 files changed, 657 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index c578fcc34bfd..ddae476e4371 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -204,13 +204,20 @@ bool intel_hdcp2_capable(struct intel_connector
*connector)
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = >hdcp;
+ struct intel_gt *gt = dev_priv->media_gt;
+ struct intel_gsc_uc *gsc = >uc.gsc;
bool capable = false;
/* I915 support for HDCP2.2 */
if (!hdcp->hdcp2_supported)
return false;
- /* MEI interface is solid */
+ /* If MTL+ make sure gsc is loaded and proxy is setup */
+ if (intel_hdcp_gsc_cs_required(dev_priv))
+ if (!intel_uc_fw_is_running(>fw))
+ return false;
+
+ /* MEI/GSC interface is solid depending on which is used */
mutex_lock(_priv->display.hdcp.comp_mutex);
if (!dev_priv->display.hdcp.comp_added ||
!dev_priv->display.hdcp.master) {
mutex_unlock(_priv->display.hdcp.comp_mutex);
@@ -1974,7 +1981,7 @@ static int _intel_hdcp2_enable(struct intel_connector
*connector)
connector->base.name, connector->base.base.id,
hdcp->content_type);
- if (DISPLAY_VER(i915) >= 14) {
+ if (intel_hdcp_gsc_cs_required(i915)) {
hdcp_message = kzalloc(sizeof(*hdcp_message), GFP_KERNEL);
if (!hdcp_message)
@@ -2035,7 +2042,7 @@ _intel_hdcp2_disable(struct intel_connector *connector,
bool hdcp2_link_recovery
if (hdcp2_deauthenticate_port(connector) < 0)
drm_dbg_kms(>drm, "Port deauth failed.\n");
- if (DISPLAY_VER(i915) >= 14)
+ if (intel_hdcp_gsc_cs_required(i915))
intel_hdcp_gsc_free_message(i915);
connector->hdcp.hdcp2_encrypted = false;
@@ -2255,6 +2262,9 @@ static int initialize_hdcp_port_data(struct
intel_connector *connector,
static bool is_hdcp2_supported(struct drm_i915_private *dev_priv)
{
+ if (intel_hdcp_gsc_cs_required(dev_priv))
+ return true;
+
if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP))
return false;
@@ -2276,10 +2286,14 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv)
dev_priv->display.hdcp.comp_added = true;
mutex_unlock(_priv->display.hdcp.comp_mutex);
- ret = component_add_typed(dev_priv->drm.dev, _hdcp_ops,
- I915_COMPONENT_HDCP);
+ if (intel_hdcp_gsc_cs_required(dev_priv))
+ ret = intel_hdcp_gsc_init(dev_priv);
+ else
+ ret = component_add_typed(dev_priv->drm.dev, _hdcp_ops,
+ I915_COMPONENT_HDCP);
+
if (ret < 0) {
- drm_dbg_kms(_priv->drm, "Failed at component add(%d)\n",
+ drm_dbg_kms(_priv->drm, "Failed at fw component add(%d)\n",
ret);
mutex_lock(_priv->display.hdcp.comp_mutex);
dev_priv->display.hdcp.comp_added = false;
@@ -2506,7 +2520,10 @@ void intel_hdcp_component_fini(struct drm_i915_private
*dev_priv)
dev_priv->display.hdcp.comp_added = false;
mutex_unlock(_priv->display.hdcp.comp_mutex);
- component_del(dev_priv->drm.dev, _hdcp_ops);
+ if (intel_hdcp_gsc_cs_required(dev_priv))
+ intel_hdcp_gsc_fini(dev_priv);
+ else
+ component_del(dev_priv->drm.dev, _hdcp_ops);
}
void intel_hdcp_cleanup(struct intel_connector *connector)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
index
[Intel-gfx] ✗ Fi.CI.BAT: failure for Enable YCbCr420 for VDSC (rev2)
== Series Details ==
Series: Enable YCbCr420 for VDSC (rev2)
URL : https://patchwork.freedesktop.org/series/112993/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12669 -> Patchwork_112993v2
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_112993v2 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_112993v2, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v2/index.html
Participating hosts (25 -> 24)
--
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_112993v2:
### IGT changes ###
Possible regressions
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12669/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-dp-1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v2/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-dp-1.html
Known issues
Here are the changes found in Patchwork_112993v2 that come from known issues:
### IGT changes ###
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
Build changes
-
* Linux: CI_DRM_12669 -> Patchwork_112993v2
CI-20190529: 20190529
CI_DRM_12669: 0ba44f2494c482325e1a25982c2e0754cbee2a48 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7143: c7b12dcc460fc2348e1fa7f4dcb791bb82e29e44 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_112993v2: 0ba44f2494c482325e1a25982c2e0754cbee2a48 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
b59922ae7675 drm/i915/vdsc: Check slice design requirement
370639404544 drm/i915: Fill in native_420 field
a1fb6aeb17ae drm/i915: Enable YCbCr420 for VDSC
6046c8096822 drm/i915: Adding the new registers for DSC
44972ac25002 drm/i915/dp: Check if DSC supports the given output_format
f5523b62eb21 drm/dp_helper: Add helper to check if the sink supports given
format with DSC
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v2/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable YCbCr420 for VDSC (rev2)
== Series Details == Series: Enable YCbCr420 for VDSC (rev2) URL : https://patchwork.freedesktop.org/series/112993/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] [PATCH v9 6/6] drm/i915/vdsc: Check slice design requirement
Add function to check if slice design requirements are being
met as defined in Bspec: 49259 in the section
Slice Design Requirement
--v7
-remove full bspec link [Jani]
-rename intel_dsc_check_slice_design_req to
intel_dsc_slice_dimensions_valid [Jani]
--v8
-fix condition to check if slice width and height are
of two
-fix minimum pixel in slice condition
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 13ad853e24eb..6ebefc195e83 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -447,6 +447,29 @@ calculate_rc_params(struct rc_parameters *rc,
}
}
+static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state
*pipe_config,
+ struct drm_dsc_config *vdsc_cfg)
+{
+ if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
+ pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
+ if (vdsc_cfg->slice_height > 4095)
+ return -EINVAL;
+ if (vdsc_cfg->slice_height * vdsc_cfg->slice_width <= 15000)
+ return -EINVAL;
+ } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+ if (vdsc_cfg->slice_width % 2)
+ return -EINVAL;
+ if (vdsc_cfg->slice_height % 2)
+ return -EINVAL;
+ if (vdsc_cfg->slice_height > 4094)
+ return -EINVAL;
+ if (vdsc_cfg->slice_height * vdsc_cfg->slice_width <= 3)
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
{
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
@@ -455,11 +478,20 @@ int intel_dsc_compute_params(struct intel_crtc_state
*pipe_config)
u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
const struct rc_parameters *rc_params;
struct rc_parameters *rc = NULL;
+ int err;
u8 i = 0;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
pipe_config->dsc.slice_count);
+
+ err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
+
+ if (err) {
+ drm_dbg_kms(_priv->drm, "Slice dimension requirements not
met\n");
+ return err;
+ }
+
/*
* According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb
is 0
* else 1
--
2.25.1
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Use sysfs_emit() and sysfs_emit_at() (rev2)
== Series Details ==
Series: drm/i915/gt: Use sysfs_emit() and sysfs_emit_at() (rev2)
URL : https://patchwork.freedesktop.org/series/113490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12667_full -> Patchwork_113490v2_full
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v2/index.html
Participating hosts (10 -> 10)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_113490v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2842])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-glk9/igt@gem_exec_fair@basic-n...@vcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v2/shard-glk3/igt@gem_exec_fair@basic-n...@vcs0.html
Possible fixes
* igt@drm_fdinfo@idle@rcs0:
- {shard-rkl}:[FAIL][3] ([i915#7742]) -> [PASS][4] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-1/igt@drm_fdinfo@i...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v2/shard-rkl-1/igt@drm_fdinfo@i...@rcs0.html
* igt@drm_read@empty-nonblock:
- {shard-tglu}: [SKIP][5] ([i915#1845] / [i915#7651]) -> [PASS][6] +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-tglu-6/igt@drm_r...@empty-nonblock.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v2/shard-tglu-7/igt@drm_r...@empty-nonblock.html
* igt@fbdev@nullptr:
- {shard-rkl}:[SKIP][7] ([i915#2582]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-3/igt@fb...@nullptr.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v2/shard-rkl-6/igt@fb...@nullptr.html
* igt@gem_bad_reloc@negative-reloc:
- {shard-rkl}:[SKIP][9] ([i915#3281]) -> [PASS][10] +7 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-3/igt@gem_bad_re...@negative-reloc.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v2/shard-rkl-5/igt@gem_bad_re...@negative-reloc.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][11] ([i915#2842]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v2/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- {shard-rkl}:[FAIL][13] ([i915#2842]) -> [PASS][14] +2 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-3/igt@gem_exec_fair@basic-p...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v2/shard-rkl-5/igt@gem_exec_fair@basic-p...@rcs0.html
* igt@gem_set_tiling_vs_pwrite:
- {shard-rkl}:[SKIP][15] ([i915#3282]) -> [PASS][16] +2 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-2/igt@gem_set_tiling_vs_pwrite.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v2/shard-rkl-5/igt@gem_set_tiling_vs_pwrite.html
* igt@gen9_exec_parse@secure-batches:
- {shard-rkl}:[SKIP][17] ([i915#2527]) -> [PASS][18] +1 similar
issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-6/igt@gen9_exec_pa...@secure-batches.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v2/shard-rkl-5/igt@gen9_exec_pa...@secure-batches.html
* igt@i915_pm_dc@dc6-psr:
- {shard-rkl}:[SKIP][19] ([i915#658]) -> [PASS][20] +1 similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-3/igt@i915_pm...@dc6-psr.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v2/shard-rkl-6/igt@i915_pm...@dc6-psr.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- {shard-rkl}:[SKIP][21] ([i915#1397]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-1/igt@i915_pm_...@dpms-mode-unset-lpsp.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v2/shard-rkl-6/igt@i915_pm_...@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-tglu}: [SKIP][23] ([i915#1397]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-tglu-6/igt@i915_pm_...@modeset-lpsp-stress-no-wait.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v2/shard-tglu-7/igt@i915_pm_...@modeset-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@pm-tiling:
- {shard-rkl}:[SKIP][25] ([fdo#109308]) -> [PASS][26] +1 similar
issue
[25]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: LVDS cleanup
== Series Details ==
Series: drm/i915: LVDS cleanup
URL : https://patchwork.freedesktop.org/series/113503/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12667_full -> Patchwork_113503v1_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_113503v1_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_113503v1_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113503v1/index.html
Participating hosts (10 -> 11)
--
Additional (1): shard-tglu-9
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_113503v1_full:
### IGT changes ###
Possible regressions
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
- shard-glk: [PASS][1] -> [TIMEOUT][2] +2 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-glk5/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-spr-indfb-onoff.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113503v1/shard-glk2/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-spr-indfb-onoff.html
Known issues
Here are the changes found in Patchwork_113503v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@perf@enable-disable:
- shard-glk: [PASS][3] -> [TIMEOUT][4] ([i915#6943])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-glk5/igt@p...@enable-disable.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113503v1/shard-glk2/igt@p...@enable-disable.html
Possible fixes
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[FAIL][5] ([i915#7742]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113503v1/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
* igt@drm_read@empty-nonblock:
- {shard-tglu}: [SKIP][7] ([i915#1845] / [i915#7651]) -> [PASS][8] +3
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-tglu-6/igt@drm_r...@empty-nonblock.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113503v1/shard-tglu-1/igt@drm_r...@empty-nonblock.html
* igt@fbdev@unaligned-read:
- {shard-rkl}:[SKIP][9] ([i915#2582]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-1/igt@fb...@unaligned-read.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113503v1/shard-rkl-6/igt@fb...@unaligned-read.html
* igt@feature_discovery@psr1:
- {shard-rkl}:[SKIP][11] ([i915#658]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-5/igt@feature_discov...@psr1.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113503v1/shard-rkl-6/igt@feature_discov...@psr1.html
* igt@gem_bad_reloc@negative-reloc:
- {shard-rkl}:[SKIP][13] ([i915#3281]) -> [PASS][14] +5 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-3/igt@gem_bad_re...@negative-reloc.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113503v1/shard-rkl-5/igt@gem_bad_re...@negative-reloc.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][15] ([i915#2842]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113503v1/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- {shard-rkl}:[FAIL][17] ([i915#2842]) -> [PASS][18] +3 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-3/igt@gem_exec_fair@basic-p...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113503v1/shard-rkl-5/igt@gem_exec_fair@basic-p...@rcs0.html
* igt@gen9_exec_parse@batch-zero-length:
- {shard-rkl}:[SKIP][19] ([i915#2527]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-6/igt@gen9_exec_pa...@batch-zero-length.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113503v1/shard-rkl-5/igt@gen9_exec_pa...@batch-zero-length.html
* igt@i915_pm_rpm@cursor-dpms:
- {shard-tglu}: [SKIP][21] ([i915#1849]) -> [PASS][22] +9 similar
issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-tglu-6/igt@i915_pm_...@cursor-dpms.html
[22]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Add selftests for TLB invalidation (rev7)
== Series Details ==
Series: drm/i915/gt: Add selftests for TLB invalidation (rev7)
URL : https://patchwork.freedesktop.org/series/112894/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12667_full -> Patchwork_112894v7_full
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v7/index.html
Participating hosts (10 -> 10)
--
Additional (1): shard-tglu-9
Missing(1): shard-rkl0
New tests
-
New tests have been introduced between CI_DRM_12667_full and
Patchwork_112894v7_full:
### New IGT tests (2) ###
* igt@i915_pipe_stress:
- Statuses :
- Exec time: [None] s
* igt@i915_selftest@live@gt_tlb:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_112894v7_full that come from known
issues:
### IGT changes ###
Possible fixes
* igt@api_intel_bb@object-reloc-keep-cache:
- {shard-rkl}:[SKIP][1] ([i915#3281]) -> [PASS][2] +5 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-4/igt@api_intel...@object-reloc-keep-cache.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v7/shard-rkl-5/igt@api_intel...@object-reloc-keep-cache.html
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[FAIL][3] ([i915#7742]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v7/shard-rkl-5/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
* igt@drm_read@empty-nonblock:
- {shard-tglu}: [SKIP][5] ([i915#1845] / [i915#7651]) -> [PASS][6] +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-tglu-6/igt@drm_r...@empty-nonblock.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v7/shard-tglu-8/igt@drm_r...@empty-nonblock.html
* igt@fbdev@read:
- {shard-rkl}:[SKIP][7] ([i915#2582]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-2/igt@fb...@read.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v7/shard-rkl-6/igt@fb...@read.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-rkl}:[FAIL][9] ([i915#6268]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-4/igt@gem_ctx_e...@basic-nohangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v7/shard-rkl-5/igt@gem_ctx_e...@basic-nohangcheck.html
* igt@gem_exec_fair@basic-deadline:
- {shard-rkl}:[FAIL][11] ([i915#2846]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-4/igt@gem_exec_f...@basic-deadline.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v7/shard-rkl-5/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][13] ([i915#2842]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v7/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_pread@bench:
- {shard-rkl}:[SKIP][15] ([i915#3282]) -> [PASS][16] +4 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-1/igt@gem_pr...@bench.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v7/shard-rkl-5/igt@gem_pr...@bench.html
* igt@gen9_exec_parse@basic-rejected:
- {shard-rkl}:[SKIP][17] ([i915#2527]) -> [PASS][18] +1 similar
issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-1/igt@gen9_exec_pa...@basic-rejected.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v7/shard-rkl-5/igt@gen9_exec_pa...@basic-rejected.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-tglu}: [SKIP][19] ([i915#1397]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-tglu-6/igt@i915_pm_...@modeset-lpsp-stress-no-wait.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v7/shard-tglu-8/igt@i915_pm_...@modeset-lpsp-stress-no-wait.html
* igt@kms_atomic@atomic_plane_damage:
- {shard-rkl}:[SKIP][21] ([i915#4098]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/shard-rkl-2/igt@kms_atomic@atomic_plane_damage.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v7/shard-rkl-6/igt@kms_atomic@atomic_plane_damage.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- {shard-rkl}:[SKIP][23] ([i915#1845] / [i915#4098]) -> [PASS][24]
[Intel-gfx] linux-next: manual merge of the usb tree with the drm-intel-fixes tree
Hi all,
Today's linux-next merge of the usb tree got a conflict in:
drivers/gpu/drm/i915/gt/intel_engine_cs.c
between commit:
5bc4b43d5c6c ("drm/i915: Fix up locking around dumping requests lists")
from the drm-intel-fixes tree and commit:
4d70c74659d9 ("i915: Move list_count() to list.h as list_count_nodes() for
broader use")
from the usb tree.
I fixed it up (the former removed the code changed by the latter) and
can carry the fix as necessary. This is now fixed as far as linux-next
is concerned, but any non trivial conflicts should be mentioned to your
upstream maintainer when your tree is submitted for merging. You may
also want to consider cooperating with the maintainer of the conflicting
tree to minimise any particularly complex conflicts.
--
Cheers,
Stephen Rothwell
pgpndQPlVuwHy.pgp
Description: OpenPGP digital signature
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Don't do the WM0->WM1 copy w/a if WM1 is already enabled
== Series Details ==
Series: series starting with [1/4] drm/i915: Don't do the WM0->WM1 copy w/a if
WM1 is already enabled
URL : https://patchwork.freedesktop.org/series/113512/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12669 -> Patchwork_113512v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113512v1/index.html
Participating hosts (25 -> 24)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_113512v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][1] -> [DMESG-FAIL][2] ([i915#5334])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12669/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113512v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
Possible fixes
* igt@fbdev@write:
- fi-blb-e6850: [SKIP][3] ([fdo#109271]) -> [PASS][4] +4 similar
issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12669/fi-blb-e6850/igt@fb...@write.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113512v1/fi-blb-e6850/igt@fb...@write.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
Build changes
-
* Linux: CI_DRM_12669 -> Patchwork_113512v1
CI-20190529: 20190529
CI_DRM_12669: 0ba44f2494c482325e1a25982c2e0754cbee2a48 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7143: c7b12dcc460fc2348e1fa7f4dcb791bb82e29e44 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113512v1: 0ba44f2494c482325e1a25982c2e0754cbee2a48 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
179db19c54be drm/i915: Expose SAGV state via debugfs
7cae35ee1982 drm/i915: Keep sagv status updated on icl+
40ec3cf76984 drm/i915: Introduce HAS_SAGV()
a35224c55f64 drm/i915: Don't do the WM0->WM1 copy w/a if WM1 is already enabled
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113512v1/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915: Don't do the WM0->WM1 copy w/a if WM1 is already enabled
== Series Details == Series: series starting with [1/4] drm/i915: Don't do the WM0->WM1 copy w/a if WM1 is already enabled URL : https://patchwork.freedesktop.org/series/113512/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] [PATCH 1/4] drm/i915: Don't do the WM0->WM1 copy w/a if WM1 is already enabled
From: Ville Syrjälä
Due to a workaround we have to make sure the WM1 watermarks block/lines
values are sensible even when WM1 is disabled. To that end we copy those
values from WM0.
However since we now keep each wm level enabled on a per-plane basis
it doesn't seem necessary to do that copy when we already have an
enabled WM1 on the current plane. That is, we might be in a situation
where another plane can only do WM0 (and thus needs the copy) but
the current plane's WM1 is still perfectly valid (ie. fits into the
current DDB allocation).
Skipping the copy could avoid reprogramming the plane's registers
needlessly in some cases.
Fixes: a301cb0fca2d ("drm/i915: Keep plane watermarks enabled more
aggressively")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_watermark.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 261cdab390b4..0c605034356f 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -1586,7 +1586,8 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state
*state,
skl_check_wm_level(>wm[level], ddb);
if (icl_need_wm1_wa(i915, plane_id) &&
- level == 1 && wm->wm[0].enable) {
+ level == 1 && !wm->wm[level].enable &&
+ wm->wm[0].enable) {
wm->wm[level].blocks = wm->wm[0].blocks;
wm->wm[level].lines = wm->wm[0].lines;
wm->wm[level].ignore_lines =
wm->wm[0].ignore_lines;
--
2.39.1
[Intel-gfx] [PATCH 4/4] drm/i915: Expose SAGV state via debugfs
From: Ville Syrjälä
Since SAGV is controlled via unidirectional pcode commands
we have no way to query the current state. So instead let's
expose the last programmed state via debugfs. This way we
can at least know whether SAGV should be enabled or not
(which can be important to know when dealing with underruns/etc.).
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 31 ---
drivers/gpu/drm/i915/display/skl_watermark.h | 2 +-
3 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 7bcd90384a46..9e2fb8626c96 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1622,7 +1622,7 @@ void intel_display_debugfs_register(struct
drm_i915_private *i915)
intel_dmc_debugfs_register(i915);
intel_fbc_debugfs_register(i915);
intel_hpd_debugfs_register(i915);
- skl_watermark_ipc_debugfs_register(i915);
+ skl_watermark_debugfs_register(i915);
}
static int i915_panel_show(struct seq_file *m, void *data)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 5916694f147c..022aed8dd440 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3545,13 +3545,34 @@ static const struct file_operations
skl_watermark_ipc_status_fops = {
.write = skl_watermark_ipc_status_write
};
-void skl_watermark_ipc_debugfs_register(struct drm_i915_private *i915)
+static int intel_sagv_status_show(struct seq_file *m, void *unused)
+{
+ struct drm_i915_private *i915 = m->private;
+ static const char * const sagv_status[] = {
+ [I915_SAGV_UNKNOWN] = "unknown",
+ [I915_SAGV_DISABLED] = "disabled",
+ [I915_SAGV_ENABLED] = "enabled",
+ [I915_SAGV_NOT_CONTROLLED] = "not controlled",
+ };
+
+ seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(i915)));
+ seq_printf(m, "SAGV status: %s\n",
sagv_status[i915->display.sagv.status]);
+ seq_printf(m, "SAGV block time: %d usec\n",
i915->display.sagv.block_time_us);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(intel_sagv_status);
+
+void skl_watermark_debugfs_register(struct drm_i915_private *i915)
{
struct drm_minor *minor = i915->drm.primary;
- if (!HAS_IPC(i915))
- return;
+ if (HAS_IPC(i915))
+ debugfs_create_file("i915_ipc_status", 0644,
minor->debugfs_root, i915,
+ _watermark_ipc_status_fops);
- debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root, i915,
- _watermark_ipc_status_fops);
+ if (HAS_SAGV(i915))
+ debugfs_create_file("i915_sagv_status", 0444,
minor->debugfs_root, i915,
+ _sagv_status_fops);
}
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h
b/drivers/gpu/drm/i915/display/skl_watermark.h
index 37954c472070..1f81e1a5a4a3 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -47,7 +47,7 @@ void intel_wm_state_verify(struct intel_crtc *crtc,
void skl_watermark_ipc_init(struct drm_i915_private *i915);
void skl_watermark_ipc_update(struct drm_i915_private *i915);
bool skl_watermark_ipc_enabled(struct drm_i915_private *i915);
-void skl_watermark_ipc_debugfs_register(struct drm_i915_private *i915);
+void skl_watermark_debugfs_register(struct drm_i915_private *i915);
void skl_wm_init(struct drm_i915_private *i915);
--
2.39.1
[Intel-gfx] [PATCH 3/4] drm/i915: Keep sagv status updated on icl+
From: Ville Syrjälä
On icl+ SAGV is controlled by masking of the QGV points.
Reduce the QGV point mask to the same kind of enabled vs.
disable information that we had on previous platforms.
Will be useful in answering the question whether SAGV is
actually enabled or not.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 49 +++--
1 file changed, 29 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 1c236f02b380..202321ffbe2a 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -119,6 +119,32 @@ static int adls_pcode_read_psf_gv_point_info(struct
drm_i915_private *dev_priv,
return 0;
}
+static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
+{
+ unsigned int num_psf_gv_points =
i915->display.bw.max[0].num_psf_gv_points;
+ unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
+ u16 qgv_points = 0, psf_points = 0;
+
+ /*
+* We can _not_ use the whole ADLS_QGV_PT_MASK here, as PCode rejects
+* it with failure if we try masking any unadvertised points.
+* So need to operate only with those returned from PCode.
+*/
+ if (num_qgv_points > 0)
+ qgv_points = GENMASK(num_qgv_points - 1, 0);
+
+ if (num_psf_gv_points > 0)
+ psf_points = GENMASK(num_psf_gv_points - 1, 0);
+
+ return ICL_PCODE_REQ_QGV_PT(qgv_points) |
ADLS_PCODE_REQ_PSF_PT(psf_points);
+}
+
+static bool is_sagv_enabled(struct drm_i915_private *i915, u16 points_mask)
+{
+ return !is_power_of_2(~points_mask & icl_qgv_points_mask(i915) &
+ ICL_PCODE_REQ_QGV_PT_MASK);
+}
+
int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
u32 points_mask)
{
@@ -136,6 +162,9 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private
*dev_priv,
return ret;
}
+ dev_priv->display.sagv.status = is_sagv_enabled(dev_priv, points_mask) ?
+ I915_SAGV_ENABLED : I915_SAGV_DISABLED;
+
return 0;
}
@@ -965,26 +994,6 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state
*state,
return 0;
}
-static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
-{
- unsigned int num_psf_gv_points =
i915->display.bw.max[0].num_psf_gv_points;
- unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
- u16 qgv_points = 0, psf_points = 0;
-
- /*
-* We can _not_ use the whole ADLS_QGV_PT_MASK here, as PCode rejects
-* it with failure if we try masking any unadvertised points.
-* So need to operate only with those returned from PCode.
-*/
- if (num_qgv_points > 0)
- qgv_points = GENMASK(num_qgv_points - 1, 0);
-
- if (num_psf_gv_points > 0)
- psf_points = GENMASK(num_psf_gv_points - 1, 0);
-
- return ICL_PCODE_REQ_QGV_PT(qgv_points) |
ADLS_PCODE_REQ_PSF_PT(psf_points);
-}
-
static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool
*changed)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
--
2.39.1
[Intel-gfx] [PATCH 2/4] drm/i915: Introduce HAS_SAGV()
From: Ville Syrjälä
Introuce a HAS_SAGV() macro to answer the question whether
the platform in general supports SAGV. intel_has_sagv() will
keep on giving us the more specific answer whether the current
device supports SAGV or not.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_watermark.c | 6 +++---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 0c605034356f..5916694f147c 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -64,7 +64,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private
*i915)
static bool
intel_has_sagv(struct drm_i915_private *i915)
{
- return DISPLAY_VER(i915) >= 9 && !IS_LP(i915) &&
+ return HAS_SAGV(i915) &&
i915->display.sagv.status != I915_SAGV_NOT_CONTROLLED;
}
@@ -92,7 +92,7 @@ intel_sagv_block_time(struct drm_i915_private *i915)
return val;
} else if (DISPLAY_VER(i915) == 11) {
return 10;
- } else if (DISPLAY_VER(i915) == 9 && !IS_LP(i915)) {
+ } else if (HAS_SAGV(i915)) {
return 30;
} else {
return 0;
@@ -101,7 +101,7 @@ intel_sagv_block_time(struct drm_i915_private *i915)
static void intel_sagv_init(struct drm_i915_private *i915)
{
- if (!intel_has_sagv(i915))
+ if (!HAS_SAGV(i915))
i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
/*
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a0dcf3352b66..0393273faa09 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -863,7 +863,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
*/
#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
-#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
+#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
+#define HAS_SAGV(dev_priv) (DISPLAY_VER(dev_priv) >= 9 &&
!IS_LP(dev_priv))
#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
--
2.39.1
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Implement workaround for CDCLK PLL disable/enable (rev2)
== Series Details ==
Series: drm/i915: Implement workaround for CDCLK PLL disable/enable (rev2)
URL : https://patchwork.freedesktop.org/series/113226/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12666_full -> Patchwork_113226v2_full
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/index.html
Participating hosts (11 -> 10)
--
Missing(1): shard-rkl0
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_113226v2_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_eio@in-flight-immediate:
- {shard-rkl}:[PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-rkl-5/igt@gem_...@in-flight-immediate.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/shard-rkl-4/igt@gem_...@in-flight-immediate.html
Known issues
Here are the changes found in Patchwork_113226v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2846])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-glk2/igt@gem_exec_f...@basic-deadline.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/shard-glk9/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-glk5/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/shard-glk4/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_userptr_blits@vma-merge:
- shard-glk: NOTRUN -> [FAIL][7] ([i915#3318])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/shard-glk3/igt@gem_userptr_bl...@vma-merge.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#3886]) +3
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/shard-glk3/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-glk: NOTRUN -> [SKIP][9] ([fdo#109271]) +42 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/shard-glk3/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
Possible fixes
* igt@api_intel_bb@object-reloc-keep-cache:
- {shard-rkl}:[SKIP][10] ([i915#3281]) -> [PASS][11] +5 similar
issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-rkl-6/igt@api_intel...@object-reloc-keep-cache.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/shard-rkl-5/igt@api_intel...@object-reloc-keep-cache.html
* igt@core_hotunplug@unbind-rebind:
- {shard-dg1}:[DMESG-WARN][12] ([i915#4391]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-dg1-16/igt@core_hotunp...@unbind-rebind.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/shard-dg1-16/igt@core_hotunp...@unbind-rebind.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-rkl}:[FAIL][14] ([i915#6268]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-rkl-6/igt@gem_ctx_e...@basic-nohangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/shard-rkl-3/igt@gem_ctx_e...@basic-nohangcheck.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: [FAIL][16] ([i915#2842]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-glk3/igt@gem_exec_fair@basic-n...@rcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/shard-glk5/igt@gem_exec_fair@basic-n...@rcs0.html
* igt@gem_tiled_partial_pwrite_pread@writes:
- {shard-rkl}:[SKIP][18] ([i915#3282]) -> [PASS][19] +1 similar
issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-rkl-1/igt@gem_tiled_partial_pwrite_pr...@writes.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/shard-rkl-5/igt@gem_tiled_partial_pwrite_pr...@writes.html
* igt@gen9_exec_parse@unaligned-access:
- {shard-rkl}:[SKIP][20] ([i915#2527]) -> [PASS][21] +2 similar
issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-rkl-1/igt@gen9_exec_pa...@unaligned-access.html
[21]:
Re: [Intel-gfx] [PATCH] [v2] vfio-mdev: add back CONFIG_VFIO dependency
On Thu, 26 Jan 2023 22:08:31 +0100
Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> CONFIG_VFIO_MDEV cannot be selected when VFIO itself is
> disabled, otherwise we get a link failure:
>
> WARNING: unmet direct dependencies detected for VFIO_MDEV
> Depends on [n]: VFIO [=n]
> Selected by [y]:
> - SAMPLE_VFIO_MDEV_MTTY [=y] && SAMPLES [=y]
> - SAMPLE_VFIO_MDEV_MDPY [=y] && SAMPLES [=y]
> - SAMPLE_VFIO_MDEV_MBOCHS [=y] && SAMPLES [=y]
> /home/arnd/cross/arm64/gcc-13.0.1-nolibc/x86_64-linux/bin/x86_64-linux-ld:
> samples/vfio-mdev/mdpy.o: in function `mdpy_remove':
> mdpy.c:(.text+0x1e1): undefined reference to `vfio_unregister_group_dev'
> /home/arnd/cross/arm64/gcc-13.0.1-nolibc/x86_64-linux/bin/x86_64-linux-ld:
> samples/vfio-mdev/mdpy.o: in function `mdpy_probe':
> mdpy.c:(.text+0x149e): undefined reference to `_vfio_alloc_device'
>
> Fixes: 8bf8c5ee1f38 ("vfio-mdev: turn VFIO_MDEV into a selectable symbol")
> Signed-off-by: Arnd Bergmann
> ---
> v2: fix the s390 and drm drivers as well, in addition to the
> sample code.
> ---
> arch/s390/Kconfig| 4 +++-
> drivers/gpu/drm/i915/Kconfig | 1 +
> samples/Kconfig | 3 +++
> 3 files changed, 7 insertions(+), 1 deletion(-)
Applied to vfio next branch for v6.3. Thanks,
Alex
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Include stepping informaiton in device info dump (rev2)
== Series Details ==
Series: series starting with [1/2] drm/i915: Include stepping informaiton in
device info dump (rev2)
URL : https://patchwork.freedesktop.org/series/113504/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12668 -> Patchwork_113504v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v2/index.html
Participating hosts (25 -> 24)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_113504v2 that come from known issues:
### IGT changes ###
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
Build changes
-
* Linux: CI_DRM_12668 -> Patchwork_113504v2
CI-20190529: 20190529
CI_DRM_12668: c43f5b8a56e821d415239c615237ae4f8b994fcb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7143: c7b12dcc460fc2348e1fa7f4dcb791bb82e29e44 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113504v2: c43f5b8a56e821d415239c615237ae4f8b994fcb @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
cbf6fa22448c drm/i915: Prefix hex numbers with 0x
df5759fa3252 drm/i915: Include stepping informaiton in device info dump
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v2/index.html
Re: [Intel-gfx] [PATCH v2 3/3] drm: Call vga_switcheroo_process_delayed_switch() in drm_lastclose
Acked-by: Lyude Paul
On Thu, 2023-01-12 at 21:11 +0100, Thomas Zimmermann wrote:
> Several lastclose helpers call vga_switcheroo_process_delayed_switch().
> It's better to call the helper from drm_lastclose() after the kernel
> client's screen has been restored. This way, all drivers can benefit
> without having to implement their own lastclose helper. For drivers
> without vga-switcheroo, vga_switcheroo_process_delayed_switch() does
> nothing.
>
> There was an earlier patchset to do something similar. [1]
>
> v2:
> * handle vga_switcheroo_client_fb_set() in a separate patch
> * also update i915, nouveau and radeon
> * remove unnecessary include statements
> * update vga-switcheroo docs
>
> Suggested-by: Alexander Deucher
> Signed-off-by: Thomas Zimmermann
> Reviewed-by: Daniel Vetter
> Reviewed-by: Alex Deucher
> Link:
> https://lore.kernel.org/amd-gfx/20221020143603.563929-1-alexander.deuc...@amd.com/
> # 1
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 13 -
> drivers/gpu/drm/drm_file.c | 3 +++
> drivers/gpu/drm/i915/i915_driver.c | 25 ++---
> drivers/gpu/drm/nouveau/nouveau_drm.c | 1 -
> drivers/gpu/drm/nouveau/nouveau_vga.c | 7 ---
> drivers/gpu/drm/nouveau/nouveau_vga.h | 1 -
> drivers/gpu/drm/radeon/radeon_drv.c | 2 +-
> drivers/gpu/drm/radeon/radeon_drv.h | 1 -
> drivers/gpu/drm/radeon/radeon_kms.c | 18 --
> drivers/gpu/vga/vga_switcheroo.c| 4 ++--
> 12 files changed, 8 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 63c921c55fb9..7120b9b6e580 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1330,7 +1330,6 @@ extern const int amdgpu_max_kms_ioctl;
>
> int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
> void amdgpu_driver_unload_kms(struct drm_device *dev);
> -void amdgpu_driver_lastclose_kms(struct drm_device *dev);
> int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file
> *file_priv);
> void amdgpu_driver_postclose_kms(struct drm_device *dev,
>struct drm_file *file_priv);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 1353ffd08988..783c1e284a22 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -34,7 +34,6 @@
> #include
> #include
> #include
> -#include
> #include
> #include
> #include
> @@ -2785,7 +2784,6 @@ static const struct drm_driver amdgpu_kms_driver = {
> DRIVER_SYNCOBJ_TIMELINE,
> .open = amdgpu_driver_open_kms,
> .postclose = amdgpu_driver_postclose_kms,
> - .lastclose = amdgpu_driver_lastclose_kms,
> .ioctls = amdgpu_ioctls_kms,
> .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
> .dumb_create = amdgpu_mode_dumb_create,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 7aa7e52ca784..a37be02fb2fc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -34,7 +34,6 @@
> #include "amdgpu_vce.h"
> #include "atom.h"
>
> -#include
> #include
> #include
> #include
> @@ -1104,18 +1103,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void
> *data, struct drm_file *filp)
> /*
> * Outdated mess for old drm with Xorg being in charge (void function now).
> */
> -/**
> - * amdgpu_driver_lastclose_kms - drm callback for last close
> - *
> - * @dev: drm dev pointer
> - *
> - * Switch vga_switcheroo state after last close (all asics).
> - */
> -void amdgpu_driver_lastclose_kms(struct drm_device *dev)
> -{
> - drm_fb_helper_lastclose(dev);
> - vga_switcheroo_process_delayed_switch();
> -}
>
> /**
> * amdgpu_driver_open_kms - drm callback for open
> diff --git a/drivers/gpu/drm/drm_file.c b/drivers/gpu/drm/drm_file.c
> index a51ff8cee049..314c309db9a3 100644
> --- a/drivers/gpu/drm/drm_file.c
> +++ b/drivers/gpu/drm/drm_file.c
> @@ -38,6 +38,7 @@
> #include
> #include
> #include
> +#include
>
> #include
> #include
> @@ -460,6 +461,8 @@ void drm_lastclose(struct drm_device * dev)
> drm_legacy_dev_reinit(dev);
>
> drm_client_dev_restore(dev);
> +
> + vga_switcheroo_process_delayed_switch();
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
> index 33e231b120c1..bf6ad8620970 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -29,6 +29,7 @@
>
> #include
> #include
> +#include /* for FBINFO_STATE_ */
> #include
> #include
> #include
> @@ -37,7 +38,6 @@
> #include
> #include
> #include
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/6] drm/i915/ttm: fix sparse warning
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/ttm: fix sparse warning
URL : https://patchwork.freedesktop.org/series/113484/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12666_full -> Patchwork_113484v1_full
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/index.html
Participating hosts (11 -> 11)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_113484v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@perf@oa-exponents:
- {shard-rkl}:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-rkl-1/igt@p...@oa-exponents.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/shard-rkl-3/igt@p...@oa-exponents.html
Known issues
Here are the changes found in Patchwork_113484v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-glk5/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/shard-glk3/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_userptr_blits@vma-merge:
- shard-glk: NOTRUN -> [FAIL][5] ([i915#3318])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/shard-glk8/igt@gem_userptr_bl...@vma-merge.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3886]) +3
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/shard-glk8/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271]) +42 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/shard-glk8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
Possible fixes
* igt@api_intel_bb@object-reloc-keep-cache:
- {shard-rkl}:[SKIP][8] ([i915#3281]) -> [PASS][9] +6 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-rkl-6/igt@api_intel...@object-reloc-keep-cache.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/shard-rkl-5/igt@api_intel...@object-reloc-keep-cache.html
* igt@core_hotunplug@unbind-rebind:
- {shard-dg1}:[DMESG-WARN][10] ([i915#4391]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-dg1-16/igt@core_hotunp...@unbind-rebind.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/shard-dg1-17/igt@core_hotunp...@unbind-rebind.html
* igt@fbdev@info:
- {shard-rkl}:[SKIP][12] ([i915#2582]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-rkl-3/igt@fb...@info.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/shard-rkl-6/igt@fb...@info.html
* igt@feature_discovery@psr2:
- {shard-rkl}:[SKIP][14] ([i915#658]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-rkl-5/igt@feature_discov...@psr2.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/shard-rkl-6/igt@feature_discov...@psr2.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-rkl}:[FAIL][16] ([i915#6268]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-rkl-6/igt@gem_ctx_e...@basic-nohangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/shard-rkl-3/igt@gem_ctx_e...@basic-nohangcheck.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][18] ([i915#2842]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-glk9/igt@gem_exec_fair@basic-throt...@rcs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/shard-glk5/igt@gem_exec_fair@basic-throt...@rcs0.html
* igt@gem_tiled_partial_pwrite_pread@writes:
- {shard-rkl}:[SKIP][20] ([i915#3282]) -> [PASS][21] +2 similar
issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/shard-rkl-1/igt@gem_tiled_partial_pwrite_pr...@writes.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/shard-rkl-5/igt@gem_tiled_partial_pwrite_pr...@writes.html
* igt@gen9_exec_parse@secure-batches:
- {shard-rkl}:[SKIP][22]
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Use sysfs_emit() and sysfs_emit_at() (rev2)
== Series Details ==
Series: drm/i915/gt: Use sysfs_emit() and sysfs_emit_at() (rev2)
URL : https://patchwork.freedesktop.org/series/113490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12667 -> Patchwork_113490v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v2/index.html
Participating hosts (26 -> 25)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_113490v2 that come from known issues:
### IGT changes ###
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
Build changes
-
* Linux: CI_DRM_12667 -> Patchwork_113490v2
CI-20190529: 20190529
CI_DRM_12667: c30c24a1b2ef039980198dcfd7c3328fd61f404d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7143: c7b12dcc460fc2348e1fa7f4dcb791bb82e29e44 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113490v2: c30c24a1b2ef039980198dcfd7c3328fd61f404d @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
035cf6f7cea9 drm/i915/gt: Use sysfs_emit() and sysfs_emit_at()
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v2/index.html
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Include stepping informaiton in device info dump
== Series Details ==
Series: series starting with [1/2] drm/i915: Include stepping informaiton in
device info dump
URL : https://patchwork.freedesktop.org/series/113504/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12667 -> Patchwork_113504v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_113504v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_113504v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v1/index.html
Participating hosts (26 -> 25)
--
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_113504v1:
### IGT changes ###
Possible regressions
* igt@gem_exec_suspend@basic-s3@smem:
- fi-blb-e6850: [PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/fi-blb-e6850/igt@gem_exec_suspend@basic...@smem.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v1/fi-blb-e6850/igt@gem_exec_suspend@basic...@smem.html
Known issues
Here are the changes found in Patchwork_113504v1 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [DMESG-FAIL][3] ([i915#5334] / [i915#7872]) ->
[PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
Build changes
-
* Linux: CI_DRM_12667 -> Patchwork_113504v1
CI-20190529: 20190529
CI_DRM_12667: c30c24a1b2ef039980198dcfd7c3328fd61f404d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7143: c7b12dcc460fc2348e1fa7f4dcb791bb82e29e44 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113504v1: c30c24a1b2ef039980198dcfd7c3328fd61f404d @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
0f4f1824b451 drm/i915: Prefix hex numbers with 0x
b71d32ed566e drm/i915: Include stepping informaiton in device info dump
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113504v1/index.html
Re: [Intel-gfx] [PATCH] drm/i915/gt: Use sysfs_emit() and sysfs_emit_at()
Hi Nirmoy,
On Mon, Jan 30, 2023 at 02:13:58PM +0100, Nirmoy Das wrote:
> Use sysfs_emit() and sysfs_emit_at() in show() callback
> as recommended by Documentation/filesystems/sysfs.rst
>
> Cc: Andi Shyti
> Signed-off-by: Nirmoy Das
I thought we didn't have anymore of those...
Reviewed-by: Andi Shyti
Thanks,
Andi
> ---
> drivers/gpu/drm/i915/gt/sysfs_engines.c | 34 -
> 1 file changed, 16 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c
> b/drivers/gpu/drm/i915/gt/sysfs_engines.c
> index f2d9858d827c..323cead181b8 100644
> --- a/drivers/gpu/drm/i915/gt/sysfs_engines.c
> +++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c
> @@ -24,7 +24,7 @@ static struct intel_engine_cs *kobj_to_engine(struct
> kobject *kobj)
> static ssize_t
> name_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
> {
> - return sprintf(buf, "%s\n", kobj_to_engine(kobj)->name);
> + return sysfs_emit(buf, "%s\n", kobj_to_engine(kobj)->name);
> }
>
> static struct kobj_attribute name_attr =
> @@ -33,7 +33,7 @@ __ATTR(name, 0444, name_show, NULL);
> static ssize_t
> class_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
> {
> - return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_class);
> + return sysfs_emit(buf, "%d\n", kobj_to_engine(kobj)->uabi_class);
> }
>
> static struct kobj_attribute class_attr =
> @@ -42,7 +42,7 @@ __ATTR(class, 0444, class_show, NULL);
> static ssize_t
> inst_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
> {
> - return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_instance);
> + return sysfs_emit(buf, "%d\n", kobj_to_engine(kobj)->uabi_instance);
> }
>
> static struct kobj_attribute inst_attr =
> @@ -51,7 +51,7 @@ __ATTR(instance, 0444, inst_show, NULL);
> static ssize_t
> mmio_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
> {
> - return sprintf(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base);
> + return sysfs_emit(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base);
> }
>
> static struct kobj_attribute mmio_attr =
> @@ -107,11 +107,9 @@ __caps_show(struct intel_engine_cs *engine,
> for_each_set_bit(n, , show_unknown ? BITS_PER_LONG : count) {
> if (n >= count || !repr[n]) {
> if (GEM_WARN_ON(show_unknown))
> - len += snprintf(buf + len, PAGE_SIZE - len,
> - "[%x] ", n);
> + len += sysfs_emit_at(buf, len, "[%x] ", n);
> } else {
> - len += snprintf(buf + len, PAGE_SIZE - len,
> - "%s ", repr[n]);
> + len += sysfs_emit_at(buf, len, "%s ", repr[n]);
> }
> if (GEM_WARN_ON(len >= PAGE_SIZE))
> break;
> @@ -182,7 +180,7 @@ max_spin_show(struct kobject *kobj, struct kobj_attribute
> *attr, char *buf)
> {
> struct intel_engine_cs *engine = kobj_to_engine(kobj);
>
> - return sprintf(buf, "%lu\n", engine->props.max_busywait_duration_ns);
> + return sysfs_emit(buf, "%lu\n", engine->props.max_busywait_duration_ns);
> }
>
> static struct kobj_attribute max_spin_attr =
> @@ -193,7 +191,7 @@ max_spin_default(struct kobject *kobj, struct
> kobj_attribute *attr, char *buf)
> {
> struct intel_engine_cs *engine = kobj_to_engine(kobj);
>
> - return sprintf(buf, "%lu\n", engine->defaults.max_busywait_duration_ns);
> + return sysfs_emit(buf, "%lu\n",
> engine->defaults.max_busywait_duration_ns);
> }
>
> static struct kobj_attribute max_spin_def =
> @@ -236,7 +234,7 @@ timeslice_show(struct kobject *kobj, struct
> kobj_attribute *attr, char *buf)
> {
> struct intel_engine_cs *engine = kobj_to_engine(kobj);
>
> - return sprintf(buf, "%lu\n", engine->props.timeslice_duration_ms);
> + return sysfs_emit(buf, "%lu\n", engine->props.timeslice_duration_ms);
> }
>
> static struct kobj_attribute timeslice_duration_attr =
> @@ -247,7 +245,7 @@ timeslice_default(struct kobject *kobj, struct
> kobj_attribute *attr, char *buf)
> {
> struct intel_engine_cs *engine = kobj_to_engine(kobj);
>
> - return sprintf(buf, "%lu\n", engine->defaults.timeslice_duration_ms);
> + return sysfs_emit(buf, "%lu\n", engine->defaults.timeslice_duration_ms);
> }
>
> static struct kobj_attribute timeslice_duration_def =
> @@ -287,7 +285,7 @@ stop_show(struct kobject *kobj, struct kobj_attribute
> *attr, char *buf)
> {
> struct intel_engine_cs *engine = kobj_to_engine(kobj);
>
> - return sprintf(buf, "%lu\n", engine->props.stop_timeout_ms);
> + return sysfs_emit(buf, "%lu\n", engine->props.stop_timeout_ms);
> }
>
> static struct kobj_attribute stop_timeout_attr =
> @@ -298,7 +296,7 @@ stop_default(struct kobject *kobj, struct kobj_attribute
> *attr, char *buf)
> {
> struct
Re: [Intel-gfx] [PATCH] drm/i915/pcode: Wait 10 seconds for pcode to settle
Hi Rodrigo,
first of all, thanks for looking into this!
> > > > > > In the call flow invoked by intel_pcode_init(), I've added brief
> > > > > > comments
> > > > > > where further clarification is needed in this scenario, and a
> > > > > > description of
> > > > > > the suspicious scenario at the bottom.
> > > > > >
> > > > > > -
> > > > > > intel_pcode_init()
> > > > > > |
> > > > > > +-> skl_pcode_request(uncore, DG1_PCODE_STATUS,
> > > > > >DG1_UNCORE_GET_INIT_STATUS,
> > > > > >DG1_UNCORE_INIT_STATUS_COMPLETE,
> > > > > >DG1_UNCORE_INIT_STATUS_COMPLETE, 18);
> > > > > >|
> > > > > >+-> skl_pcode_try_request()
> > > > > > |
> > > > > > +-> *status = __snb_pcode_rw(uncore, mbox, ,
> > > > > > NULL,
> > > > > >500, 0, true);
> > > > > >
> > > > > > -
> > > > > > static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
> > > > > > u32 *val, u32 *val1,
> > > > > > int fast_timeout_us, int slow_timeout_ms,
> > > > > > bool is_read)
> > > > > > {
> > > > > > ...
> > > > > > /* Before writing a value to the GEN6_PCODE_DATA register,
> > > > > >check if the bit in the GEN6_PCODE_MAILBOX register
> > > > > > indicates
> > > > > >BUSY. */
> > > > > > if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) &
> > > > > > GEN6_PCODE_READY)
> > > > > > return -EAGAIN;
> > > > >
> > > > > what if we fail here because the punit is still initializing and
> > > > > will be ready, say, in 10 seconds?
> > > > >
> > > > > GG, without going any further, we fail here! The -EAGAIN we
> > > > > receive from the test comes from this point. We don't fail with
> > > > > -ETIMEDOUT, but with -EAGAIN and the reason is because the punit
> > > > > is not ready to perform the very fist communication and we fail
> > > > > the probing.
> > > > >
> > > > > It doesn't mean, though, that there is anything wrong, we just
> > > > > need to wait a bit before "taking drastic decisions"!
> > > > >
> > > > > This patch is suggesting to wait up to 10s for the punit to be
> > > > > ready and eventually try to probe again... and, indeed, it works!
> > > >
> > > > As GG, what I still don't understand is how this extra 10 seconds
> > > > wait helps... have you tried to simple add the 10 to the 180 and
> > > > make the code 190 sec instead?
> > >
> > > maybe I haven't been able to explain the issue properly.
> > >
> > > I can even set that timer to 2hrs and a half and nothing changes
> > > because we fail before.
> > >
> > > Here it's not a matter of how much do I wait but when do I check
> > > the pcode readiness (i.e. signalled by the GEN6_PCODE_READY bit
> > > in the GEN6_PCODE_MAILBOX register).
> > >
> > > During a normal run we are always sure that communicating with
> > > the punit works, because we made it sure during the previous
> > > transaction.
> > >
> > > During probe there is no previous transaction and we start
> > > communicating with the punit without making sure that it is
> > > ready. And indeed some times it is not, so that we suppress the
> > > probing on purpose instead of giving it another chance.
> > >
> > > I admit that the commit message is not written properly and
> > > rather misleading, but here it's not at all a matter of how much
> > > do I wait.
> >
> > The commit message was initially confused because it looks like
> > we are just adding a wait, without doing anything
> >
> > But looking to the code we can see that it will wait until
> > pcode is ready with a timeout of 10 seconds.
> >
> > But if pcode is ready in 10 seconds, why pcode is not ready
> > in 190 seconds. We are doing absolutely nothing more that could
> > make pcode ready in 10 seconds that won't be in 190.
> >
> > This is what we are missing here... The code as is doesn't make
> > a lot of sense to us and it looks like it is solving the issue
> > by the 10 extra seconds and not by some special status checking.
>
> Okay, after an offline talk I am convinced now that we need some
> check like this in some place.
>
> But the commit message needs be be fully re-written.
>
> It needs to be clear that underneath, the pcode communication
> functions will do a check for ready without any wait, what will
> make desired timeout to never really wait for the pcode done
> and prematurely return.
>
> at __snb_pcode_rw():
>
> if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
> return -EAGAIN;
>
> So, for this reason we need to ensure that pcode is really ready
> before we wait.
>
> Other options are to handle the EAGAIN return and then wait.
> Or even change the
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: LVDS cleanup
== Series Details ==
Series: drm/i915: LVDS cleanup
URL : https://patchwork.freedesktop.org/series/113503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12667 -> Patchwork_113503v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113503v1/index.html
Participating hosts (26 -> 24)
--
Missing(2): fi-kbl-soraka fi-snb-2520m
Known issues
Here are the changes found in Patchwork_113503v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][1] -> [DMESG-FAIL][2] ([i915#5334])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113503v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
Possible fixes
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rpls-1}: [ABORT][3] ([i915#6311] / [i915#7359]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12667/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113503v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#7359]: https://gitlab.freedesktop.org/drm/intel/issues/7359
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
Build changes
-
* Linux: CI_DRM_12667 -> Patchwork_113503v1
CI-20190529: 20190529
CI_DRM_12667: c30c24a1b2ef039980198dcfd7c3328fd61f404d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7143: c7b12dcc460fc2348e1fa7f4dcb791bb82e29e44 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113503v1: c30c24a1b2ef039980198dcfd7c3328fd61f404d @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4d6e9b1c9ffd drm/i915/lvds: s/pipe_config/crtc_state/
06b70b12d475 drm/i915/lvds: s/intel_encoder/encoder/ etc.
945379acd2bd drm/i915/lvds: s/dev_priv/i915/
dd41c76e79f2 drm/i915/lvds: Fix whitespace
18e49ae44b43 drm/i915/lvds: Extract intel_lvds_regs.h
f6bdf12601e4 drm/i915/lvds: Use REG_BIT() & co.
41af5c474557 drm/i915/lvds: Use intel_de_rmw()
5e304bbb6a58 drm/i915/lvds: Split long lines
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113503v1/index.html
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: LVDS cleanup
== Series Details == Series: drm/i915: LVDS cleanup URL : https://patchwork.freedesktop.org/series/113503/ State : warning == Summary == Error: dim checkpatch failed ed78aebbde6f drm/i915/lvds: Split long lines -:34: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #34: FILE: drivers/gpu/drm/i915/display/intel_lvds.c:229: + REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); total: 0 errors, 1 warnings, 0 checks, 20 lines checked d349e9ae1383 drm/i915/lvds: Use intel_de_rmw() a2ddc2b5a37a drm/i915/lvds: Use REG_BIT() & co. c7d9325b3ecf drm/i915/lvds: Extract intel_lvds_regs.h Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:39: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #39: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 173 lines checked a315da9bcc1a drm/i915/lvds: Fix whitespace de3f39fece6a drm/i915/lvds: s/dev_priv/i915/ b3f145849bf5 drm/i915/lvds: s/intel_encoder/encoder/ etc. -:189: CHECK:CAMELCASE: Avoid CamelCase: #189: FILE: drivers/gpu/drm/i915/display/intel_lvds.c:922: + connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; total: 0 errors, 0 warnings, 1 checks, 252 lines checked 0fc60b0c377c drm/i915/lvds: s/pipe_config/crtc_state/
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add selftests for TLB invalidation (rev7)
== Series Details ==
Series: drm/i915/gt: Add selftests for TLB invalidation (rev7)
URL : https://patchwork.freedesktop.org/series/112894/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12667 -> Patchwork_112894v7
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v7/index.html
Participating hosts (26 -> 24)
--
Missing(2): fi-kbl-soraka fi-snb-2520m
New tests
-
New tests have been introduced between CI_DRM_12667 and Patchwork_112894v7:
### New IGT tests (1) ###
* igt@i915_selftest@live@gt_tlb:
- Statuses : 24 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_112894v7 that come from known issues:
### IGT changes ###
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
Build changes
-
* Linux: CI_DRM_12667 -> Patchwork_112894v7
CI-20190529: 20190529
CI_DRM_12667: c30c24a1b2ef039980198dcfd7c3328fd61f404d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7143: c7b12dcc460fc2348e1fa7f4dcb791bb82e29e44 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_112894v7: c30c24a1b2ef039980198dcfd7c3328fd61f404d @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
f5a491df3085 drm/i915/gt: Add selftests for TLB invalidation
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v7/index.html
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Add selftests for TLB invalidation (rev7)
== Series Details == Series: drm/i915/gt: Add selftests for TLB invalidation (rev7) URL : https://patchwork.freedesktop.org/series/112894/ State : warning == Summary == Error: dim checkpatch failed bacf86f3ccc1 drm/i915/gt: Add selftests for TLB invalidation Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:39: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #39: new file mode 100644 -:67: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #67: FILE: drivers/gpu/drm/i915/gt/selftest_tlb.c:24: + GEM_BUG_ON(addr < i915_vma_offset(vma)); -:68: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #68: FILE: drivers/gpu/drm/i915/gt/selftest_tlb.c:25: + GEM_BUG_ON(addr >= i915_vma_offset(vma) + i915_vma_size(vma) + sizeof(val)); -:114: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #114: FILE: drivers/gpu/drm/i915/gt/selftest_tlb.c:71: + GEM_BUG_ON(i915_vma_offset(va) != addr); -:180: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst #180: FILE: drivers/gpu/drm/i915/gt/selftest_tlb.c:137: + msleep(10); -:219: WARNING:MEMORY_BARRIER: memory barrier without comment #219: FILE: drivers/gpu/drm/i915/gt/selftest_tlb.c:176: + wmb(); -:264: WARNING:LINE_SPACING: Missing a blank line after declarations #264: FILE: drivers/gpu/drm/i915/gt/selftest_tlb.c:221: + enum intel_engine_id id; + I915_RND_STATE(prng); -:298: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #298: FILE: drivers/gpu/drm/i915/gt/selftest_tlb.c:255: + GEM_BUG_ON(A->base.size != B->base.size); -:359: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #359: FILE: drivers/gpu/drm/i915/gt/selftest_tlb.c:316: + err = pte_tlbinv(ce, va, vb, + BIT_ULL(bit), total: 0 errors, 8 warnings, 1 checks, 409 lines checked
Re: [Intel-gfx] [PATCH] drm/i915: Implement workaround for CDCLK PLL disable/enable
> -Original Message-
> From: Lisovskiy, Stanislav
> Sent: Monday, January 30, 2023 5:59 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Lisovskiy, Stanislav ; Saarinen, Jani
> ; Srivatsa, Anusha
> Subject: [PATCH] drm/i915: Implement workaround for CDCLK PLL
> disable/enable
>
> It was reported that we might get a hung and loss of register access in some
> cases when CDCLK PLL is disabled and then enabled, while squashing is enabled.
> As a workaround it was proposed by HW team that SW should disable squashing
> when CDCLK PLL is being reenabled.
>
> v2: - Added WA number comment(Rodrigo Vivi)
>
> Signed-off-by: Stanislav Lisovskiy
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 7e16b655c833..8ae2b4c81f31 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1801,6 +1801,13 @@ static bool
> cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
> return true;
> }
>
> +static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) {
> + return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv))
> + && dev_priv->display.cdclk.hw.vco > 0
> + && HAS_CDCLK_SQUASH(dev_priv));
> +}
> +
> static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> @@ -1815,9 +1822,13 @@ static void _bxt_set_cdclk(struct drm_i915_private
> *dev_priv,
> !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
> if (dev_priv->display.cdclk.hw.vco != vco)
> adlp_cdclk_pll_crawl(dev_priv, vco);
> - } else if (DISPLAY_VER(dev_priv) >= 11)
> + } else if (DISPLAY_VER(dev_priv) >= 11) {
> + /* wa_15010685871: dg2, mtl */
> + if (pll_enable_wa_needed(dev_priv))
> + dg2_cdclk_squash_program(dev_priv, 0);
> +
> icl_cdclk_pll_update(dev_priv, vco);
> - else
> + } else
> bxt_cdclk_pll_update(dev_priv, vco);
>
> waveform = cdclk_squash_waveform(dev_priv, cdclk);
> --
> 2.37.3
[Intel-gfx] [linux-next:master] BUILD REGRESSION ae0c77e1bc6963c67c6c09e8c72959fcb1ed8d5f
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: ae0c77e1bc6963c67c6c09e8c72959fcb1ed8d5f Add linux-next specific files for 20230130 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/202301230743.xnut0zvc-...@intel.com https://lore.kernel.org/oe-kbuild-all/202301300743.bp7dpazv-...@intel.com https://lore.kernel.org/oe-kbuild-all/202301301722.6fghrppl-...@intel.com https://lore.kernel.org/oe-kbuild-all/202301301801.y5o08tqx-...@intel.com https://lore.kernel.org/oe-kbuild-all/202301302110.metnwkbd-...@intel.com Error/Warning: (recently discovered and may have been fixed) Documentation/riscv/uabi.rst:24: WARNING: Enumerated list ends without a blank line; unexpected unindent. ERROR: modpost: "devm_platform_ioremap_resource" [drivers/dma/fsl-edma.ko] undefined! ERROR: modpost: "devm_platform_ioremap_resource" [drivers/dma/idma64.ko] undefined! arch/arm64/kvm/arm.c:2211: warning: expecting prototype for Initialize Hyp(). Prototype was for kvm_arm_init() instead drivers/clk/qcom/gcc-sa8775p.c:313:32: warning: unused variable 'gcc_parent_map_10' [-Wunused-const-variable] drivers/clk/qcom/gcc-sa8775p.c:318:37: warning: unused variable 'gcc_parent_data_10' [-Wunused-const-variable] drivers/clk/qcom/gcc-sa8775p.c:333:32: warning: unused variable 'gcc_parent_map_12' [-Wunused-const-variable] drivers/clk/qcom/gcc-sa8775p.c:338:37: warning: unused variable 'gcc_parent_data_12' [-Wunused-const-variable] drivers/gpu/drm/amd/amdgpu/../display/dc/link/accessories/link_dp_trace.c:148:6: warning: no previous prototype for 'link_dp_trace_set_edp_power_timestamp' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/link/accessories/link_dp_trace.c:158:10: warning: no previous prototype for 'link_dp_trace_get_edp_poweron_timestamp' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/link/accessories/link_dp_trace.c:163:10: warning: no previous prototype for 'link_dp_trace_get_edp_poweroff_timestamp' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_capability.c:1295:32: warning: variable 'result_write_min_hblank' set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_capability.c:279:42: warning: variable 'ds_port' set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training.c:1585:38: warning: variable 'result' set but not used [-Wunused-but-set-variable] kismet: WARNING: unmet direct dependencies detected for VFIO_MDEV when selected by SAMPLE_VFIO_MDEV_MTTY libbpf: failed to find '.BTF' ELF section in vmlinux Unverified Error/Warning (likely false positive, please contact us if interested): drivers/nvmem/imx-ocotp.c:599:21: sparse: sparse: symbol 'imx_ocotp_layout' was not declared. Should it be static? drivers/nvmem/layouts/sl28vpd.c:143:21: sparse: sparse: symbol 'sl28vpd_layout' was not declared. Should it be static? drivers/thermal/qcom/tsens-v0_1.c:106:40: sparse: sparse: symbol 'tsens_9607_nvmem' was not declared. Should it be static? drivers/thermal/qcom/tsens-v0_1.c:26:40: sparse: sparse: symbol 'tsens_8916_nvmem' was not declared. Should it be static? drivers/thermal/qcom/tsens-v0_1.c:42:40: sparse: sparse: symbol 'tsens_8939_nvmem' was not declared. Should it be static? drivers/thermal/qcom/tsens-v0_1.c:62:40: sparse: sparse: symbol 'tsens_8974_nvmem' was not declared. Should it be static? drivers/thermal/qcom/tsens-v0_1.c:84:40: sparse: sparse: symbol 'tsens_8974_backup_nvmem' was not declared. Should it be static? drivers/thermal/qcom/tsens-v1.c:24:40: sparse: sparse: symbol 'tsens_qcs404_nvmem' was not declared. Should it be static? drivers/thermal/qcom/tsens-v1.c:45:40: sparse: sparse: symbol 'tsens_8976_nvmem' was not declared. Should it be static? pahole: .tmp_vmlinux.btf: No such file or directory Error/Warning ids grouped by kconfigs: gcc_recent_errors |-- alpha-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-accessories-link_dp_trace.c:warning:no-previous-prototype-for-link_dp_trace_get_edp_poweroff_timestamp | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-accessories-link_dp_trace.c:warning:no-previous-prototype-for-link_dp_trace_get_edp_poweron_timestamp | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-accessories-link_dp_trace.c:warning:no-previous-prototype-for-link_dp_trace_set_edp_power_timestamp | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:variable-ds_port-set-but-not-used | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:variable-result_write_min_hblank-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_training.c:warning:variable-result-set-but-not-used |-- alpha-randconfig-r016-20230130 | |-- drivers-gpu-drm-amd-amdgpu-..-display
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for Drop TGL/DG1 workarounds for pre-prod steppings
On Sat, Jan 28, 2023 at 06:28:35AM +, Patchwork wrote:
> == Series Details ==
>
> Series: Drop TGL/DG1 workarounds for pre-prod steppings
> URL : https://patchwork.freedesktop.org/series/113453/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_12658_full -> Patchwork_113453v1_full
>
>
> Summary
> ---
>
> **SUCCESS**
>
> No regressions found.
Applied to di-next. Thanks Rodrigo for the reviews.
Matt
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/index.html
>
> Participating hosts (10 -> 10)
> --
>
> No changes in participating hosts
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_113453v1_full:
>
> ### IGT changes ###
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@gem_exec_suspend@basic-s3-devices@smem:
> - {shard-rkl}:[PASS][1] -> [FAIL][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-6/igt@gem_exec_suspend@basic-s3-devi...@smem.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-4/igt@gem_exec_suspend@basic-s3-devi...@smem.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_113453v1_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_exec_fair@basic-pace-solo@rcs0:
> - shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-glk3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-glk5/igt@gem_exec_fair@basic-pace-s...@rcs0.html
>
> * igt@perf@stress-open-close:
> - shard-glk: [PASS][5] -> [ABORT][6] ([i915#5213])
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-glk5/igt@p...@stress-open-close.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-glk9/igt@p...@stress-open-close.html
>
>
> Possible fixes
>
> * igt@drm_fdinfo@idle@rcs0:
> - {shard-rkl}:[FAIL][7] ([i915#7742]) -> [PASS][8]
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-4/igt@drm_fdinfo@i...@rcs0.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@drm_fdinfo@i...@rcs0.html
>
> * igt@drm_read@empty-block:
> - {shard-rkl}:[SKIP][9] ([i915#4098]) -> [PASS][10] +2 similar
> issues
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@drm_r...@empty-block.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@drm_r...@empty-block.html
>
> * igt@fbdev@unaligned-read:
> - {shard-rkl}:[SKIP][11] ([i915#2582]) -> [PASS][12]
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-2/igt@fb...@unaligned-read.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@fb...@unaligned-read.html
>
> * igt@gem_eio@in-flight-suspend:
> - {shard-rkl}:[FAIL][13] ([fdo#103375]) -> [PASS][14]
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@gem_...@in-flight-suspend.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@gem_...@in-flight-suspend.html
>
> * igt@gem_exec_capture@pi@vcs0:
> - {shard-rkl}:[ABORT][15] -> [PASS][16]
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-6/igt@gem_exec_capture@p...@vcs0.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@gem_exec_capture@p...@vcs0.html
>
> * igt@gem_exec_fair@basic-pace-share@rcs0:
> - {shard-tglu}: [FAIL][17] ([i915#2842]) -> [PASS][18]
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-tglu-5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-tglu-7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
>
> * igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
> - {shard-rkl}:[SKIP][19] ([i915#3281]) -> [PASS][20] +4 similar
> issues
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@gem_exec_re...@basic-cpu-gtt-noreloc.html
>[20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@gem_exec_re...@basic-cpu-gtt-noreloc.html
>
> * igt@gem_mmap_wc@set-cache-level:
> - {shard-rkl}:[SKIP][21] ([i915#1850]) -> [PASS][22]
>[21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-4/igt@gem_mmap...@set-cache-level.html
>[22]:
>
[Intel-gfx] [PATCH 2/2] drm/i915: Prefix hex numbers with 0x
From: Ville Syrjälä
It's hard to figure out whether the number is hex
or decimal if doesn't have the 0x to indicate hex.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_device_info.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 599c6d399de4..524f93768c41 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -125,8 +125,8 @@ void intel_device_info_print(const struct intel_device_info
*info,
drm_printf(p, "base die stepping: %s\n",
intel_step_name(runtime->step.basedie_step));
drm_printf(p, "gt: %d\n", info->gt);
- drm_printf(p, "memory-regions: %x\n", runtime->memory_regions);
- drm_printf(p, "page-sizes: %x\n", runtime->page_sizes);
+ drm_printf(p, "memory-regions: 0x%x\n", runtime->memory_regions);
+ drm_printf(p, "page-sizes: 0x%x\n", runtime->page_sizes);
drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size);
drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type);
@@ -540,5 +540,5 @@ void intel_driver_caps_print(const struct intel_driver_caps
*caps,
{
drm_printf(p, "Has logical contexts? %s\n",
str_yes_no(caps->has_logical_contexts));
- drm_printf(p, "scheduler: %x\n", caps->scheduler);
+ drm_printf(p, "scheduler: 0x%x\n", caps->scheduler);
}
--
2.39.1
[Intel-gfx] [PATCH 1/2] drm/i915: Include stepping informaiton in device info dump
From: Ville Syrjälä Dump the stepping information alongside all the other device info. Might avoid some guesswork when reading logs. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_device_info.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 98769e5f2c3d..599c6d399de4 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -119,6 +119,11 @@ void intel_device_info_print(const struct intel_device_info *info, drm_printf(p, "display version: %u\n", runtime->display.ip.ver); + drm_printf(p, "graphics stepping: %s\n", intel_step_name(runtime->step.graphics_step)); + drm_printf(p, "media stepping: %s\n", intel_step_name(runtime->step.media_step)); + drm_printf(p, "display stepping: %s\n", intel_step_name(runtime->step.display_step)); + drm_printf(p, "base die stepping: %s\n", intel_step_name(runtime->step.basedie_step)); + drm_printf(p, "gt: %d\n", info->gt); drm_printf(p, "memory-regions: %x\n", runtime->memory_regions); drm_printf(p, "page-sizes: %x\n", runtime->page_sizes); -- 2.39.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Implement workaround for CDCLK PLL disable/enable (rev2)
== Series Details ==
Series: drm/i915: Implement workaround for CDCLK PLL disable/enable (rev2)
URL : https://patchwork.freedesktop.org/series/113226/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12666 -> Patchwork_113226v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/index.html
Participating hosts (25 -> 24)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_113226v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-n3050: [PASS][1] -> [FAIL][2] ([i915#6298])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][3] ([i915#5334]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [ABORT][5] ([i915#4983] / [i915#7981]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/bat-rpls-1/igt@i915_selftest@l...@reset.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@i915_selftest@live@slpc:
- {bat-adlp-6}: [DMESG-FAIL][7] ([i915#6367] / [i915#7913]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/bat-adlp-6/igt@i915_selftest@l...@slpc.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/bat-adlp-6/igt@i915_selftest@l...@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7979]: https://gitlab.freedesktop.org/drm/intel/issues/7979
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
Build changes
-
* Linux: CI_DRM_12666 -> Patchwork_113226v2
CI-20190529: 20190529
CI_DRM_12666: 908c84b836ee39b5565561a0b352c2dc18378215 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7142: adeeb8527422155ff4039aed34a922da4a7d @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113226v2: 908c84b836ee39b5565561a0b352c2dc18378215 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
a9e5309dd3bf drm/i915: Implement workaround for CDCLK PLL disable/enable
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113226v2/index.html
[Intel-gfx] [PATCH 8/8] drm/i915/lvds: s/pipe_config/crtc_state/
From: Ville Syrjälä
Call the crtc state 'crtc_state' rather than 'pipe_config',
as is the modern style.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_lvds.c | 46 +++
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c
b/drivers/gpu/drm/i915/display/intel_lvds.c
index 37969aac91b4..1df67457f10a 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -121,13 +121,13 @@ static bool intel_lvds_get_hw_state(struct intel_encoder
*encoder,
}
static void intel_lvds_get_config(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
+ struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
u32 tmp, flags = 0;
- pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
+ crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS);
tmp = intel_de_read(dev_priv, lvds_encoder->reg);
if (tmp & LVDS_HSYNC_POLARITY)
@@ -139,20 +139,20 @@ static void intel_lvds_get_config(struct intel_encoder
*encoder,
else
flags |= DRM_MODE_FLAG_PVSYNC;
- pipe_config->hw.adjusted_mode.flags |= flags;
+ crtc_state->hw.adjusted_mode.flags |= flags;
if (DISPLAY_VER(dev_priv) < 5)
- pipe_config->gmch_pfit.lvds_border_bits =
+ crtc_state->gmch_pfit.lvds_border_bits =
tmp & LVDS_BORDER_ENABLE;
/* gen2/3 store dither state in pfit control, needs to match */
if (DISPLAY_VER(dev_priv) < 4) {
tmp = intel_de_read(dev_priv, PFIT_CONTROL);
- pipe_config->gmch_pfit.control |= tmp &
PANEL_8TO6_DITHER_ENABLE;
+ crtc_state->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
}
- pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
+ crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;
}
static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
@@ -231,19 +231,19 @@ static void intel_lvds_pps_init_hw(struct
drm_i915_private *dev_priv,
static void intel_pre_enable_lvds(struct intel_atomic_state *state,
struct intel_encoder *encoder,
- const struct intel_crtc_state *pipe_config,
+ const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
- const struct drm_display_mode *adjusted_mode =
_config->hw.adjusted_mode;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct drm_display_mode *adjusted_mode =
_state->hw.adjusted_mode;
enum pipe pipe = crtc->pipe;
u32 temp;
if (HAS_PCH_SPLIT(i915)) {
assert_fdi_rx_pll_disabled(i915, pipe);
- assert_shared_dpll_disabled(i915, pipe_config->shared_dpll);
+ assert_shared_dpll_disabled(i915, crtc_state->shared_dpll);
} else {
assert_pll_disabled(i915, pipe);
}
@@ -263,7 +263,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state
*state,
/* set the corresponsding LVDS_BORDER bit */
temp &= ~LVDS_BORDER_ENABLE;
- temp |= pipe_config->gmch_pfit.lvds_border_bits;
+ temp |= crtc_state->gmch_pfit.lvds_border_bits;
/*
* Set the B0-B3 data pairs corresponding to whether we're going to
@@ -293,7 +293,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state
*state,
* Bspec wording suggests that LVDS port dithering only exists
* for 18bpp panels.
*/
- if (pipe_config->dither && pipe_config->pipe_bpp == 18)
+ if (crtc_state->dither && crtc_state->pipe_bpp == 18)
temp |= LVDS_ENABLE_DITHER;
else
temp &= ~LVDS_ENABLE_DITHER;
@@ -312,7 +312,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state
*state,
*/
static void intel_enable_lvds(struct intel_atomic_state *state,
struct intel_encoder *encoder,
- const struct intel_crtc_state *pipe_config,
+ const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
@@ -327,7 +327,7 @@ static void
[Intel-gfx] [PATCH 7/8] drm/i915/lvds: s/intel_encoder/encoder/ etc.
From: Ville Syrjälä
Get rid of the some of the annoying aliasing drm_ vs.
intel_ encoder/connector variables. Just prefer the
intel_ types.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_lvds.c | 130 +++---
1 file changed, 62 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c
b/drivers/gpu/drm/i915/display/intel_lvds.c
index 295d7b9fc399..37969aac91b4 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -384,19 +384,19 @@ static void intel_lvds_shutdown(struct intel_encoder
*encoder)
}
static enum drm_mode_status
-intel_lvds_mode_valid(struct drm_connector *connector,
+intel_lvds_mode_valid(struct drm_connector *_connector,
struct drm_display_mode *mode)
{
- struct intel_connector *intel_connector = to_intel_connector(connector);
+ struct intel_connector *connector = to_intel_connector(_connector);
const struct drm_display_mode *fixed_mode =
- intel_panel_fixed_mode(intel_connector, mode);
- int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
+ intel_panel_fixed_mode(connector, mode);
+ int max_pixclk = to_i915(connector->base.dev)->max_dotclk_freq;
enum drm_mode_status status;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
- status = intel_panel_mode_valid(intel_connector, mode);
+ status = intel_panel_mode_valid(connector, mode);
if (status != MODE_OK)
return status;
@@ -406,15 +406,13 @@ intel_lvds_mode_valid(struct drm_connector *connector,
return MODE_OK;
}
-static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
+static int intel_lvds_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
- struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
- struct intel_lvds_encoder *lvds_encoder =
- to_lvds_encoder(intel_encoder);
- struct intel_connector *intel_connector =
- lvds_encoder->attached_connector;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
+ struct intel_connector *connector = lvds_encoder->attached_connector;
struct drm_display_mode *adjusted_mode = _config->hw.adjusted_mode;
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
unsigned int lvds_bpp;
@@ -446,7 +444,7 @@ static int intel_lvds_compute_config(struct intel_encoder
*intel_encoder,
* with the panel scaling set up to source from the H/VDisplay
* of the original mode.
*/
- ret = intel_panel_compute_config(intel_connector, adjusted_mode);
+ ret = intel_panel_compute_config(connector, adjusted_mode);
if (ret)
return ret;
@@ -472,19 +470,19 @@ static int intel_lvds_compute_config(struct intel_encoder
*intel_encoder,
/*
* Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
*/
-static int intel_lvds_get_modes(struct drm_connector *connector)
+static int intel_lvds_get_modes(struct drm_connector *_connector)
{
- struct intel_connector *intel_connector = to_intel_connector(connector);
- const struct drm_edid *fixed_edid = intel_connector->panel.fixed_edid;
+ struct intel_connector *connector = to_intel_connector(_connector);
+ const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
/* Use panel fixed edid if we have one */
if (!IS_ERR_OR_NULL(fixed_edid)) {
- drm_edid_connector_update(connector, fixed_edid);
+ drm_edid_connector_update(>base, fixed_edid);
- return drm_edid_connector_add_modes(connector);
+ return drm_edid_connector_add_modes(>base);
}
- return intel_panel_get_modes(intel_connector);
+ return intel_panel_get_modes(connector);
}
static const struct drm_connector_helper_funcs
intel_lvds_connector_helper_funcs = {
@@ -832,11 +830,9 @@ static void intel_lvds_add_properties(struct drm_connector
*connector)
void intel_lvds_init(struct drm_i915_private *i915)
{
struct intel_lvds_encoder *lvds_encoder;
- struct intel_encoder *intel_encoder;
- struct intel_connector *intel_connector;
- struct drm_connector *connector;
- struct drm_encoder *encoder;
+ struct intel_connector *connector;
const struct drm_edid *drm_edid;
+ struct intel_encoder *encoder;
i915_reg_t lvds_reg;
u32 lvds;
u8 pin;
@@ -881,55 +877,53 @@ void intel_lvds_init(struct drm_i915_private *i915)
if (!lvds_encoder)
return;
- intel_connector =
[Intel-gfx] [PATCH 6/8] drm/i915/lvds: s/dev_priv/i915/
From: Ville Syrjälä
Do the customary s/dev_priv/i915/ rename and alising
'dev' pointer removal. Though various register definitons
still depend on the magic 'dev_priv' variable so not
a 100% conversion.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_lvds.c | 111 +++---
1 file changed, 54 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c
b/drivers/gpu/drm/i915/display/intel_lvds.c
index a5ead4e56ec2..295d7b9fc399 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -85,15 +85,15 @@ static struct intel_lvds_encoder *to_lvds_encoder(struct
intel_encoder *encoder)
return container_of(encoder, struct intel_lvds_encoder, base);
}
-bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
+bool intel_lvds_port_enabled(struct drm_i915_private *i915,
i915_reg_t lvds_reg, enum pipe *pipe)
{
u32 val;
- val = intel_de_read(dev_priv, lvds_reg);
+ val = intel_de_read(i915, lvds_reg);
/* asserts want to know the pipe even if the port is disabled */
- if (HAS_PCH_CPT(dev_priv))
+ if (HAS_PCH_CPT(i915))
*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val);
else
*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val);
@@ -104,19 +104,18 @@ bool intel_lvds_port_enabled(struct drm_i915_private
*dev_priv,
static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
intel_wakeref_t wakeref;
bool ret;
- wakeref = intel_display_power_get_if_enabled(dev_priv,
-encoder->power_domain);
+ wakeref = intel_display_power_get_if_enabled(i915,
encoder->power_domain);
if (!wakeref)
return false;
- ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe);
+ ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe);
- intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
+ intel_display_power_put(i915, encoder->power_domain, wakeref);
return ret;
}
@@ -236,26 +235,25 @@ static void intel_pre_enable_lvds(struct
intel_atomic_state *state,
const struct drm_connector_state *conn_state)
{
struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
const struct drm_display_mode *adjusted_mode =
_config->hw.adjusted_mode;
enum pipe pipe = crtc->pipe;
u32 temp;
- if (HAS_PCH_SPLIT(dev_priv)) {
- assert_fdi_rx_pll_disabled(dev_priv, pipe);
- assert_shared_dpll_disabled(dev_priv,
- pipe_config->shared_dpll);
+ if (HAS_PCH_SPLIT(i915)) {
+ assert_fdi_rx_pll_disabled(i915, pipe);
+ assert_shared_dpll_disabled(i915, pipe_config->shared_dpll);
} else {
- assert_pll_disabled(dev_priv, pipe);
+ assert_pll_disabled(i915, pipe);
}
- intel_lvds_pps_init_hw(dev_priv, _encoder->init_pps);
+ intel_lvds_pps_init_hw(i915, _encoder->init_pps);
temp = lvds_encoder->init_lvds_val;
temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
- if (HAS_PCH_CPT(dev_priv)) {
+ if (HAS_PCH_CPT(i915)) {
temp &= ~LVDS_PIPE_SEL_MASK_CPT;
temp |= LVDS_PIPE_SEL_CPT(pipe);
} else {
@@ -290,7 +288,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state
*state,
* special lvds dither control bit on pch-split platforms, dithering is
* only controlled through the PIPECONF reg.
*/
- if (DISPLAY_VER(dev_priv) == 4) {
+ if (DISPLAY_VER(i915) == 4) {
/*
* Bspec wording suggests that LVDS port dithering only exists
* for 18bpp panels.
@@ -306,7 +304,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state
*state,
if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
temp |= LVDS_VSYNC_POLARITY;
- intel_de_write(dev_priv, lvds_encoder->reg, temp);
+ intel_de_write(i915, lvds_encoder->reg, temp);
}
/*
@@ -317,9 +315,8 @@ static void intel_enable_lvds(struct intel_atomic_state
*state,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
-
[Intel-gfx] [PATCH 4/8] drm/i915/lvds: Extract intel_lvds_regs.h
From: Ville Syrjälä Extract the integrated LVDS port register definitions into their own header file. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_lvds.c | 1 + .../gpu/drm/i915/display/intel_lvds_regs.h| 65 +++ drivers/gpu/drm/i915/display/intel_panel.c| 1 + .../gpu/drm/i915/display/intel_pch_display.c | 1 + drivers/gpu/drm/i915/display/intel_pps.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 54 --- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + 8 files changed, 71 insertions(+), 54 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_lvds_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index fcd3f1c7af32..12ade593 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -94,6 +94,7 @@ #include "intel_hotplug.h" #include "intel_hti.h" #include "intel_lvds.h" +#include "intel_lvds_regs.h" #include "intel_modeset_setup.h" #include "intel_modeset_verify.h" #include "intel_overlay.h" diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index c338895d8545..2fa337ad8155 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -49,6 +49,7 @@ #include "intel_fdi.h" #include "intel_gmbus.h" #include "intel_lvds.h" +#include "intel_lvds_regs.h" #include "intel_panel.h" /* Private structure for the integrated LVDS support */ diff --git a/drivers/gpu/drm/i915/display/intel_lvds_regs.h b/drivers/gpu/drm/i915/display/intel_lvds_regs.h new file mode 100644 index ..a0051565ebd7 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_lvds_regs.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2023 Intel Corporation + */ + +#ifndef __INTEL_LVDS_REGS_H__ +#define __INTEL_LVDS_REGS_H__ + +#include "intel_display_reg_defs.h" + +/* LVDS port control */ +#define LVDS _MMIO(0x61180) +/* + * Enables the LVDS port. This bit must be set before DPLLs are enabled, as + * the DPLL semantics change when the LVDS is assigned to that pipe. + */ +#define LVDS_PORT_EN REG_BIT(31) +/* Selects pipe B for LVDS data. Must be set on pre-965. */ +#define LVDS_PIPE_SEL_MASK REG_BIT(30) +#define LVDS_PIPE_SEL(x) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK, (x)) +#define LVDS_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29) +#define LVDS_PIPE_SEL_CPT(x) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK_CPT, (x)) +/* LVDS dithering flag on 965/g4x platform */ +#define LVDS_ENABLE_DITHER REG_BIT(25) +/* LVDS sync polarity flags. Set to invert (i.e. negative) */ +#define LVDS_VSYNC_POLARITY REG_BIT(21) +#define LVDS_HSYNC_POLARITY REG_BIT(20) + +/* Enable border for unscaled (or aspect-scaled) display */ +#define LVDS_BORDER_ENABLE REG_BIT(15) +/* + * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per + * pixel. + */ +#define LVDS_A0A2_CLKA_POWER_MASKREG_GENMASK(9, 8) +#define LVDS_A0A2_CLKA_POWER_DOWN REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 0) +#define LVDS_A0A2_CLKA_POWER_UP REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 3) +/* + * Controls the A3 data pair, which contains the additional LSBs for 24 bit + * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be + * on. + */ +#define LVDS_A3_POWER_MASK REG_GENMASK(7, 6) +#define LVDS_A3_POWER_DOWN REG_FIELD_PREP(LVDS_A3_POWER_MASK, 0) +#define LVDS_A3_POWER_UP REG_FIELD_PREP(LVDS_A3_POWER_MASK, 3) +/* + * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP + * is set. + */ +#define LVDS_CLKB_POWER_MASK REG_GENMASK(5, 4) +#define LVDS_CLKB_POWER_DOWN REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 0) +#define LVDS_CLKB_POWER_UP REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 3) +/* + * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 + * setting for whether we are in dual-channel mode. The B3 pair will + * additionally only be powered up when LVDS_A3_POWER_UP is set. + */ +#define LVDS_B0B3_POWER_MASK REG_GENMASK(3, 2) +#define LVDS_B0B3_POWER_DOWN REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 0) +#define LVDS_B0B3_POWER_UP REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 3) + +#define PCH_LVDS _MMIO(0xe1180) +#define LVDS_DETECTEDREG_BIT(1) + +#endif /* __INTEL_LVDS_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 42aa04bac261..ce2a34a25211 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -39,6 +39,7 @@ #include "intel_de.h" #include "intel_display_types.h"
[Intel-gfx] [PATCH 5/8] drm/i915/lvds: Fix whitespace
From: Ville Syrjälä
Replace some stray spaes with tabs.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_lvds.c | 28 +++
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c
b/drivers/gpu/drm/i915/display/intel_lvds.c
index 2fa337ad8155..a5ead4e56ec2 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -586,12 +586,12 @@ static const struct dmi_system_id intel_no_lvds[] = {
},
{
.callback = intel_no_lvds_dmi_callback,
-.ident = "AOpen i45GMx-I",
-.matches = {
-DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
-DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
-},
-},
+ .ident = "AOpen i45GMx-I",
+ .matches = {
+ DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
+ DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
+ },
+ },
{
.callback = intel_no_lvds_dmi_callback,
.ident = "Aopen i945GTt-VFA",
@@ -608,14 +608,14 @@ static const struct dmi_system_id intel_no_lvds[] = {
},
},
{
-.callback = intel_no_lvds_dmi_callback,
-.ident = "Clientron E830",
-.matches = {
-DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
-DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
-},
-},
-{
+ .callback = intel_no_lvds_dmi_callback,
+ .ident = "Clientron E830",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
+ },
+ },
+ {
.callback = intel_no_lvds_dmi_callback,
.ident = "Asus EeeBox PC EB1007",
.matches = {
--
2.39.1
[Intel-gfx] [PATCH 3/8] drm/i915/lvds: Use REG_BIT() & co.
From: Ville Syrjälä Use REG_BIT() & co. for the LVDS port register. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_lvds.c | 4 +- drivers/gpu/drm/i915/i915_reg.h | 46 +++ 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 86a100eabd0d..c338895d8545 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -93,9 +93,9 @@ bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, /* asserts want to know the pipe even if the port is disabled */ if (HAS_PCH_CPT(dev_priv)) - *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT; + *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val); else - *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT; + *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val); return val & LVDS_PORT_EN; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b134a1f357c8..58ff9671c74d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2603,52 +2603,50 @@ * Enables the LVDS port. This bit must be set before DPLLs are enabled, as * the DPLL semantics change when the LVDS is assigned to that pipe. */ -#define LVDS_PORT_EN (1 << 31) +#define LVDS_PORT_EN REG_BIT(31) /* Selects pipe B for LVDS data. Must be set on pre-965. */ -#define LVDS_PIPE_SEL_SHIFT 30 -#define LVDS_PIPE_SEL_MASK (1 << 30) -#define LVDS_PIPE_SEL(pipe) ((pipe) << 30) -#define LVDS_PIPE_SEL_SHIFT_CPT 29 -#define LVDS_PIPE_SEL_MASK_CPT (3 << 29) -#define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29) +#define LVDS_PIPE_SEL_MASK REG_BIT(30) +#define LVDS_PIPE_SEL(x) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK, (x)) +#define LVDS_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29) +#define LVDS_PIPE_SEL_CPT(x) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK_CPT, (x)) /* LVDS dithering flag on 965/g4x platform */ -#define LVDS_ENABLE_DITHER (1 << 25) +#define LVDS_ENABLE_DITHER REG_BIT(25) /* LVDS sync polarity flags. Set to invert (i.e. negative) */ -#define LVDS_VSYNC_POLARITY (1 << 21) -#define LVDS_HSYNC_POLARITY (1 << 20) +#define LVDS_VSYNC_POLARITY REG_BIT(21) +#define LVDS_HSYNC_POLARITY REG_BIT(20) /* Enable border for unscaled (or aspect-scaled) display */ -#define LVDS_BORDER_ENABLE (1 << 15) +#define LVDS_BORDER_ENABLE REG_BIT(15) /* * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per * pixel. */ -#define LVDS_A0A2_CLKA_POWER_MASK(3 << 8) -#define LVDS_A0A2_CLKA_POWER_DOWN(0 << 8) -#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) +#define LVDS_A0A2_CLKA_POWER_MASKREG_GENMASK(9, 8) +#define LVDS_A0A2_CLKA_POWER_DOWN REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 0) +#define LVDS_A0A2_CLKA_POWER_UP REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 3) /* * Controls the A3 data pair, which contains the additional LSBs for 24 bit * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be * on. */ -#define LVDS_A3_POWER_MASK (3 << 6) -#define LVDS_A3_POWER_DOWN (0 << 6) -#define LVDS_A3_POWER_UP (3 << 6) +#define LVDS_A3_POWER_MASK REG_GENMASK(7, 6) +#define LVDS_A3_POWER_DOWN REG_FIELD_PREP(LVDS_A3_POWER_MASK, 0) +#define LVDS_A3_POWER_UP REG_FIELD_PREP(LVDS_A3_POWER_MASK, 3) /* * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP * is set. */ -#define LVDS_CLKB_POWER_MASK (3 << 4) -#define LVDS_CLKB_POWER_DOWN (0 << 4) -#define LVDS_CLKB_POWER_UP (3 << 4) +#define LVDS_CLKB_POWER_MASK REG_GENMASK(5, 4) +#define LVDS_CLKB_POWER_DOWN REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 0) +#define LVDS_CLKB_POWER_UP REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 3) /* * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 * setting for whether we are in dual-channel mode. The B3 pair will * additionally only be powered up when LVDS_A3_POWER_UP is set. */ -#define LVDS_B0B3_POWER_MASK (3 << 2) -#define LVDS_B0B3_POWER_DOWN (0 << 2) -#define LVDS_B0B3_POWER_UP (3 << 2) +#define LVDS_B0B3_POWER_MASK REG_GENMASK(3, 2) +#define LVDS_B0B3_POWER_DOWN REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 0) +#define LVDS_B0B3_POWER_UP REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 3) /* Video Data Island Packet control */ #define VIDEO_DIP_DATA _MMIO(0x61178) @@ -6398,7 +6396,7 @@ #define FDI_PLL_CTL_2 _MMIO(0xfe004) #define PCH_LVDS
[Intel-gfx] [PATCH 2/8] drm/i915/lvds: Use intel_de_rmw()
From: Ville Syrjälä Replace the hand rolled rmw stuff with intel_de_rmw(). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_lvds.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 49b6cddeb67e..86a100eabd0d 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -320,11 +320,9 @@ static void intel_enable_lvds(struct intel_atomic_state *state, struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); struct drm_i915_private *dev_priv = to_i915(dev); - intel_de_write(dev_priv, lvds_encoder->reg, - intel_de_read(dev_priv, lvds_encoder->reg) | LVDS_PORT_EN); + intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN); - intel_de_write(dev_priv, PP_CONTROL(0), - intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON); + intel_de_rmw(dev_priv, PP_CONTROL(0), 0, PANEL_POWER_ON); intel_de_posting_read(dev_priv, lvds_encoder->reg); if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) @@ -342,14 +340,12 @@ static void intel_disable_lvds(struct intel_atomic_state *state, struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - intel_de_write(dev_priv, PP_CONTROL(0), - intel_de_read(dev_priv, PP_CONTROL(0)) & ~PANEL_POWER_ON); + intel_de_rmw(dev_priv, PP_CONTROL(0), PANEL_POWER_ON, 0); if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) drm_err(_priv->drm, "timed out waiting for panel to power off\n"); - intel_de_write(dev_priv, lvds_encoder->reg, - intel_de_read(dev_priv, lvds_encoder->reg) & ~LVDS_PORT_EN); + intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0); intel_de_posting_read(dev_priv, lvds_encoder->reg); } -- 2.39.1
[Intel-gfx] [PATCH 1/8] drm/i915/lvds: Split long lines
From: Ville Syrjälä Split some overly long lines. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_lvds.c | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index a1557d84ce0a..49b6cddeb67e 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -216,13 +216,17 @@ static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, intel_de_write(dev_priv, PP_CONTROL(0), val); intel_de_write(dev_priv, PP_ON_DELAYS(0), - REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); + REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | + REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | + REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); intel_de_write(dev_priv, PP_OFF_DELAYS(0), - REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); + REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | + REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); intel_de_write(dev_priv, PP_DIVISOR(0), - REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); + REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | + REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); } static void intel_pre_enable_lvds(struct intel_atomic_state *state, -- 2.39.1
[Intel-gfx] [PATCH 0/8] drm/i915: LVDS cleanup
From: Ville Syrjälä Some cleanup/modernization of the LVDS code. Ville Syrjälä (8): drm/i915/lvds: Split long lines drm/i915/lvds: Use intel_de_rmw() drm/i915/lvds: Use REG_BIT() & co. drm/i915/lvds: Extract intel_lvds_regs.h drm/i915/lvds: Fix whitespace drm/i915/lvds: s/dev_priv/i915/ drm/i915/lvds: s/intel_encoder/encoder/ etc. drm/i915/lvds: s/pipe_config/crtc_state/ drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_lvds.c | 332 +- .../gpu/drm/i915/display/intel_lvds_regs.h| 65 drivers/gpu/drm/i915/display/intel_panel.c| 1 + .../gpu/drm/i915/display/intel_pch_display.c | 1 + drivers/gpu/drm/i915/display/intel_pps.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 56 --- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + 8 files changed, 232 insertions(+), 226 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_lvds_regs.h -- 2.39.1
Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg1: Drop support for pre-production steppings
On Mon, Jan 30, 2023 at 09:34:22AM -0800, Matt Roper wrote:
> On Mon, Jan 30, 2023 at 12:19:48PM -0500, Rodrigo Vivi wrote:
> > On Fri, Jan 27, 2023 at 02:43:12PM -0800, Matt Roper wrote:
> > > Several post-DG1 platforms have been brought up now, so we're well past
> > > the point where we usually drop the workarounds that are only applicable
> > > to internal/pre-production hardware.
> > >
> > > Production DG1 hardware always has a B0 stepping for both display and
> > > GT.
> > >
> > > Bspec: 44463
> > > Signed-off-by: Matt Roper
> > > ---
> > > .../drm/i915/display/intel_display_power.c| 1 -
> > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 ++-
> > > drivers/gpu/drm/i915/i915_driver.c| 1 +
> > > drivers/gpu/drm/i915/i915_drv.h | 2 -
> > > drivers/gpu/drm/i915/intel_pm.c | 12 -
> > > 5 files changed, 5 insertions(+), 59 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 1dc31f0f5e0a..7222502a760c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -1580,7 +1580,6 @@ static void tgl_bw_buddy_init(struct
> > > drm_i915_private *dev_priv)
> > > return;
> > >
> > > if (IS_ALDERLAKE_S(dev_priv) ||
> > > - IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > > /* Wa_1409767108 */
> > > table = wa_1409767108_buddy_page_masks;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index 82a8f372bde6..648fceba5bb6 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -1463,12 +1463,6 @@ dg1_gt_workarounds_init(struct intel_gt *gt,
> > > struct i915_wa_list *wal)
> > >
> > > gen12_gt_workarounds_init(gt, wal);
> > >
> > > - /* Wa_1607087056:dg1 */
> > > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > > - wa_write_or(wal,
> > > - GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> > > - L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> > > -
> > > /* Wa_1409420604:dg1 */
> > > if (IS_DG1(i915))
> > > wa_mcr_write_or(wal,
> > > @@ -2103,20 +2097,6 @@ static void tgl_whitelist_build(struct
> > > intel_engine_cs *engine)
> > > }
> > > }
> > >
> > > -static void dg1_whitelist_build(struct intel_engine_cs *engine)
> > > -{
> > > - struct i915_wa_list *w = >whitelist;
> > > -
> > > - tgl_whitelist_build(engine);
> > > -
> > > - /* GEN:BUG:1409280441:dg1 */
> > > - if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) &&
> > > - (engine->class == RENDER_CLASS ||
> > > - engine->class == COPY_ENGINE_CLASS))
> > > - whitelist_reg_ext(w, RING_ID(engine->mmio_base),
> > > - RING_FORCE_TO_NONPRIV_ACCESS_RD);
> > > -}
> > > -
> > > static void xehpsdv_whitelist_build(struct intel_engine_cs *engine)
> > > {
> > > allow_read_ctx_timestamp(engine);
> > > @@ -2196,8 +2176,6 @@ void intel_engine_init_whitelist(struct
> > > intel_engine_cs *engine)
> > > dg2_whitelist_build(engine);
> > > else if (IS_XEHPSDV(i915))
> > > xehpsdv_whitelist_build(engine);
> > > - else if (IS_DG1(i915))
> > > - dg1_whitelist_build(engine);
> > > else if (GRAPHICS_VER(i915) == 12)
> > > tgl_whitelist_build(engine);
> > > else if (GRAPHICS_VER(i915) == 11)
> > > @@ -2410,16 +2388,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> > > struct i915_wa_list *wal)
> > > true);
> > > }
> > >
> > > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > > - /*
> > > - * Wa_1607138336
> > > - * Wa_1607063988
> > > - */
> > > - wa_write_or(wal,
> > > - GEN9_CTX_PREEMPT_REG,
> > > - GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> > > - }
> > > -
> > > if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> > > IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> > > /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> > > @@ -2449,30 +2417,22 @@ rcs_engine_wa_init(struct intel_engine_cs
> > > *engine, struct i915_wa_list *wal)
> > > }
> > >
> > > if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
> > > - IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > > IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> > > - /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
> > > + /* Wa_1409804808 */
> > > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> > >GEN12_PUSH_CONST_DEREF_HOLD_DIS);
> > >
> > > - /*
> > > - * Wa_1409085225:tgl
> > > - * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p
> > > -
Re: [Intel-gfx] [PATCH] drm/i915/display: Fix typo for reference clock
> -Original Message-
> From: Jani Nikula
> Sent: Monday, January 30, 2023 5:29 PM
> To: Roper, Matthew D ; Borah, Chaitanya
> Kumar
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Fix typo for reference
> clock
>
> On Thu, 12 Jan 2023, Matt Roper wrote:
> > On Thu, Jan 12, 2023 at 03:11:31PM +0530, Chaitanya Kumar Borah wrote:
> >> Fix typo for reference clock from 24400 to 24000
> >>
> >> Signed-off-by: Chaitanya Kumar Borah
>
> >
> > Fixes: 626426ff9ce4 ("drm/i915/adl_p: Add cdclk support for ADL-P")
> > Reviewed-by: Matt Roper
>
> Pushed to drm-intel-next, thanks for the patch and review.
>
Thank you Jani.
Regards
Chaitanya
> BR,
> Jani.
>
> >
> >> ---
> >> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> index 0c107a38f9d0..7e16b655c833 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> @@ -1319,7 +1319,7 @@ static const struct intel_cdclk_vals
> adlp_cdclk_table[] = {
> >>{ .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> >>{ .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> >>{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> >> - { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
> >> + { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> >>
> >>{ .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> >>{ .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> >> --
> >> 2.25.1
> >>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Use sysfs_emit() and sysfs_emit_at()
== Series Details ==
Series: drm/i915/gt: Use sysfs_emit() and sysfs_emit_at()
URL : https://patchwork.freedesktop.org/series/113490/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12666 -> Patchwork_113490v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_113490v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_113490v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v1/index.html
Participating hosts (25 -> 25)
--
Additional (1): fi-kbl-soraka
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_113490v1:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@execlists:
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v1/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html
Known issues
Here are the changes found in Patchwork_113490v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][4] ([i915#1886])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271]) +15 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v1/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][6] ([i915#5334]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [ABORT][8] ([i915#4983] / [i915#7981]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/bat-rpls-1/igt@i915_selftest@l...@reset.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v1/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@i915_selftest@live@slpc:
- {bat-adlp-6}: [DMESG-FAIL][10] ([i915#6367] / [i915#7913]) ->
[PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/bat-adlp-6/igt@i915_selftest@l...@slpc.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113490v1/bat-adlp-6/igt@i915_selftest@l...@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7908]: https://gitlab.freedesktop.org/drm/intel/issues/7908
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
Build changes
-
* Linux: CI_DRM_12666 -> Patchwork_113490v1
CI-20190529: 20190529
CI_DRM_12666: 908c84b836ee39b5565561a0b352c2dc18378215 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7142: adeeb8527422155ff4039aed34a922da4a7d @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113490v1: 908c84b836ee39b5565561a0b352c2dc18378215 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
093d7c03c708 drm/i915/gt: Use sysfs_emit() and sysfs_emit_at()
== Logs ==
For more details see:
Re: [Intel-gfx] [PATCH v3 8/8] drm/i915/guc: Update GT/GuC messages in intel_uc.c
On 1/28/2023 11:59, Michal Wajdeczko wrote:
Use new macros to have common prefix that also include GT#.
v2: pass gt to print_fw_ver
v3: prefer guc_dbg in suspend/resume logs
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 80 +--
1 file changed, 39 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 9a8a1abf71d7..de7f987cf611 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -6,11 +6,13 @@
#include
#include "gt/intel_gt.h"
+#include "gt/intel_gt_print.h"
#include "gt/intel_reset.h"
#include "intel_gsc_fw.h"
#include "intel_gsc_uc.h"
#include "intel_guc.h"
#include "intel_guc_ads.h"
+#include "intel_guc_print.h"
#include "intel_guc_submission.h"
#include "gt/intel_rps.h"
#include "intel_uc.h"
@@ -67,14 +69,14 @@ static int __intel_uc_reset_hw(struct intel_uc *uc)
ret = intel_reset_guc(gt);
if (ret) {
- DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
+ gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
return ret;
}
guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
- WARN(!(guc_status & GS_MIA_IN_RESET),
-"GuC status: 0x%x, MIA core expected to be in reset\n",
-guc_status);
+ gt_WARN(gt, !(guc_status & GS_MIA_IN_RESET),
+ "GuC status: 0x%x, MIA core expected to be in reset\n",
+ guc_status);
return ret;
}
@@ -252,15 +254,13 @@ static int guc_enable_communication(struct intel_guc *guc)
intel_guc_ct_event_handler(>ct);
spin_unlock_irq(gt->irq_lock);
- drm_dbg(>drm, "GuC communication enabled\n");
+ guc_dbg(guc, "communication enabled\n");
return 0;
}
static void guc_disable_communication(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
-
/*
* Events generated during or after CT disable are logged by guc in
* via mmio. Make sure the register is clear before disabling CT since
@@ -280,11 +280,12 @@ static void guc_disable_communication(struct intel_guc
*guc)
*/
guc_get_mmio_msg(guc);
- drm_dbg(>drm, "GuC communication disabled\n");
+ guc_dbg(guc, "communication disabled\n");
}
static void __uc_fetch_firmwares(struct intel_uc *uc)
{
+ struct intel_gt *gt = uc_to_gt(uc);
int err;
GEM_BUG_ON(!intel_uc_wants_guc(uc));
@@ -293,15 +294,13 @@ static void __uc_fetch_firmwares(struct intel_uc *uc)
if (err) {
/* Make sure we transition out of transient "SELECTED" state */
if (intel_uc_wants_huc(uc)) {
- drm_dbg(_to_gt(uc)->i915->drm,
- "Failed to fetch GuC: %d disabling HuC\n", err);
+ gt_dbg(gt, "Failed to fetch GuC fw (%pe) disabling
HuC\n", ERR_PTR(err));
intel_uc_fw_change_status(>huc.fw,
INTEL_UC_FIRMWARE_ERROR);
}
if (intel_uc_wants_gsc_uc(uc)) {
- drm_dbg(_to_gt(uc)->i915->drm,
- "Failed to fetch GuC: %d disabling GSC\n", err);
+ gt_dbg(gt, "Failed to fetch GuC fw (%pe) disabling
GSC\n", ERR_PTR(err));
intel_uc_fw_change_status(>gsc.fw,
INTEL_UC_FIRMWARE_ERROR);
}
@@ -382,7 +381,7 @@ static int uc_init_wopcm(struct intel_uc *uc)
int err;
if (unlikely(!base || !size)) {
- i915_probe_error(gt->i915, "Unsuccessful WOPCM partitioning\n");
+ gt_probe_error(gt, "Unsuccessful WOPCM partitioning\n");
return -E2BIG;
}
@@ -413,13 +412,13 @@ static int uc_init_wopcm(struct intel_uc *uc)
return 0;
err_out:
- i915_probe_error(gt->i915, "Failed to init uC WOPCM registers!\n");
- i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
-i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
-intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
- i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
-i915_mmio_reg_offset(GUC_WOPCM_SIZE),
-intel_uncore_read(uncore, GUC_WOPCM_SIZE));
+ gt_probe_error(gt, "Failed to init uC WOPCM registers!\n");
+ gt_probe_error(gt, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
+ i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
+ intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
+ gt_probe_error(gt, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
+ i915_mmio_reg_offset(GUC_WOPCM_SIZE),
+
Re: [Intel-gfx] [PATCH v3 6/8] drm/i915/guc: Update GuC messages in intel_guc_log.c
On 1/28/2023 11:59, Michal Wajdeczko wrote:
Use new macros to have common prefix that also include GT#.
v2: drop redundant GuC strings, minor improvements
v3: more message improvements
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 38 +++---
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 68331c538b0a..c3792ddeec80 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -12,6 +12,7 @@
#include "i915_memcpy.h"
#include "intel_guc_capture.h"
#include "intel_guc_log.h"
+#include "intel_guc_print.h"
#if defined(CONFIG_DRM_I915_DEBUG_GUC)
#define GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE SZ_2M
@@ -39,7 +40,6 @@ struct guc_log_section {
static void _guc_log_init_sizes(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
static const struct guc_log_section sections[GUC_LOG_SECTIONS_LIMIT] = {
{
GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT,
@@ -82,12 +82,12 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
}
if (!IS_ALIGNED(log->sizes[i].bytes, log->sizes[i].units))
- drm_err(>drm, "Mis-aligned GuC log %s size: 0x%X vs
0x%X!",
+ guc_err(guc, "Mis-aligned log %s size: 0x%X vs 0x%X!\n",
sections[i].name, log->sizes[i].bytes,
log->sizes[i].units);
log->sizes[i].count = log->sizes[i].bytes / log->sizes[i].units;
if (!log->sizes[i].count) {
- drm_err(>drm, "Zero GuC log %s size!",
sections[i].name);
+ guc_err(guc, "Zero log %s size!\n", sections[i].name);
} else {
/* Size is +1 unit */
log->sizes[i].count--;
@@ -95,14 +95,14 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
/* Clip to field size */
if (log->sizes[i].count > sections[i].max) {
- drm_err(>drm, "GuC log %s size too large: %d vs
%d!",
+ guc_err(guc, "log %s size too large: %d vs %d!\n",
sections[i].name, log->sizes[i].count + 1,
sections[i].max + 1);
log->sizes[i].count = sections[i].max;
}
}
if (log->sizes[GUC_LOG_SECTIONS_CRASH].units != log->sizes[GUC_LOG_SECTIONS_DEBUG].units) {
- drm_err(>drm, "Unit mis-match for GuC log crash and debug
sections: %d vs %d!",
+ guc_err(guc, "Unit mismatch for crash and debug sections: %d vs
%d!\n",
log->sizes[GUC_LOG_SECTIONS_CRASH].units,
log->sizes[GUC_LOG_SECTIONS_DEBUG].units);
log->sizes[GUC_LOG_SECTIONS_CRASH].units =
log->sizes[GUC_LOG_SECTIONS_DEBUG].units;
@@ -374,6 +374,7 @@ size_t intel_guc_get_log_buffer_offset(struct intel_guc_log
*log,
static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
{
+ struct intel_guc *guc = log_to_guc(log);
unsigned int buffer_size, read_offset, write_offset, bytes_to_copy,
full_cnt;
struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
struct guc_log_buffer_state log_buf_state_local;
@@ -383,7 +384,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct
intel_guc_log *log)
mutex_lock(>relay.lock);
- if (WARN_ON(!intel_guc_log_relay_created(log)))
+ if (guc_WARN_ON(guc, !intel_guc_log_relay_created(log)))
goto out_unlock;
/* Get the pointer to shared GuC log buffer */
@@ -398,7 +399,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct
intel_guc_log *log)
* Used rate limited to avoid deluge of messages, logs might be
* getting consumed by User at a slow rate.
*/
- DRM_ERROR_RATELIMITED("no sub-buffer to copy general logs\n");
+ guc_err_ratelimited(guc, "no sub-buffer to copy general
logs\n");
log->relay.full_count++;
goto out_unlock;
@@ -451,7 +452,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct
intel_guc_log *log)
write_offset = buffer_size;
} else if (unlikely((read_offset > buffer_size) ||
(write_offset > buffer_size))) {
- DRM_ERROR("invalid log buffer state\n");
+ guc_err(guc, "invalid log buffer state\n");
/* copy whole buffer as offsets are unreliable */
read_offset = 0;
write_offset = buffer_size;
@@ -547,7 +548,7 @@ static int
Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg1: Drop support for pre-production steppings
On Mon, Jan 30, 2023 at 12:19:48PM -0500, Rodrigo Vivi wrote:
> On Fri, Jan 27, 2023 at 02:43:12PM -0800, Matt Roper wrote:
> > Several post-DG1 platforms have been brought up now, so we're well past
> > the point where we usually drop the workarounds that are only applicable
> > to internal/pre-production hardware.
> >
> > Production DG1 hardware always has a B0 stepping for both display and
> > GT.
> >
> > Bspec: 44463
> > Signed-off-by: Matt Roper
> > ---
> > .../drm/i915/display/intel_display_power.c| 1 -
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 ++-
> > drivers/gpu/drm/i915/i915_driver.c| 1 +
> > drivers/gpu/drm/i915/i915_drv.h | 2 -
> > drivers/gpu/drm/i915/intel_pm.c | 12 -
> > 5 files changed, 5 insertions(+), 59 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 1dc31f0f5e0a..7222502a760c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -1580,7 +1580,6 @@ static void tgl_bw_buddy_init(struct drm_i915_private
> > *dev_priv)
> > return;
> >
> > if (IS_ALDERLAKE_S(dev_priv) ||
> > - IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > /* Wa_1409767108 */
> > table = wa_1409767108_buddy_page_masks;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 82a8f372bde6..648fceba5bb6 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -1463,12 +1463,6 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct
> > i915_wa_list *wal)
> >
> > gen12_gt_workarounds_init(gt, wal);
> >
> > - /* Wa_1607087056:dg1 */
> > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > - wa_write_or(wal,
> > - GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> > - L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> > -
> > /* Wa_1409420604:dg1 */
> > if (IS_DG1(i915))
> > wa_mcr_write_or(wal,
> > @@ -2103,20 +2097,6 @@ static void tgl_whitelist_build(struct
> > intel_engine_cs *engine)
> > }
> > }
> >
> > -static void dg1_whitelist_build(struct intel_engine_cs *engine)
> > -{
> > - struct i915_wa_list *w = >whitelist;
> > -
> > - tgl_whitelist_build(engine);
> > -
> > - /* GEN:BUG:1409280441:dg1 */
> > - if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) &&
> > - (engine->class == RENDER_CLASS ||
> > -engine->class == COPY_ENGINE_CLASS))
> > - whitelist_reg_ext(w, RING_ID(engine->mmio_base),
> > - RING_FORCE_TO_NONPRIV_ACCESS_RD);
> > -}
> > -
> > static void xehpsdv_whitelist_build(struct intel_engine_cs *engine)
> > {
> > allow_read_ctx_timestamp(engine);
> > @@ -2196,8 +2176,6 @@ void intel_engine_init_whitelist(struct
> > intel_engine_cs *engine)
> > dg2_whitelist_build(engine);
> > else if (IS_XEHPSDV(i915))
> > xehpsdv_whitelist_build(engine);
> > - else if (IS_DG1(i915))
> > - dg1_whitelist_build(engine);
> > else if (GRAPHICS_VER(i915) == 12)
> > tgl_whitelist_build(engine);
> > else if (GRAPHICS_VER(i915) == 11)
> > @@ -2410,16 +2388,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> > struct i915_wa_list *wal)
> >true);
> > }
> >
> > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > - /*
> > -* Wa_1607138336
> > -* Wa_1607063988
> > -*/
> > - wa_write_or(wal,
> > - GEN9_CTX_PREEMPT_REG,
> > - GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> > - }
> > -
> > if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> > IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> > /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> > @@ -2449,30 +2417,22 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> > struct i915_wa_list *wal)
> > }
> >
> > if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
> > - IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> > - /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
> > + /* Wa_1409804808 */
> > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> > GEN12_PUSH_CONST_DEREF_HOLD_DIS);
> >
> > - /*
> > -* Wa_1409085225:tgl
> > -* Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p
> > -*/
> > + /* Wa_14010229206 */
> > wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4,
> > GEN12_DISABLE_TDL_PUSH);
> > }
> >
> > - if
Re: [Intel-gfx] [PATCH] drm/i915/pcode: Wait 10 seconds for pcode to settle
On Mon, Jan 30, 2023 at 11:37:29AM -0500, Rodrigo Vivi wrote:
> On Mon, Jan 30, 2023 at 05:12:48PM +0100, Andi Shyti wrote:
> > Hi Rodrigo,
> >
> > > > > In the call flow invoked by intel_pcode_init(), I've added brief
> > > > > comments
> > > > > where further clarification is needed in this scenario, and a
> > > > > description of
> > > > > the suspicious scenario at the bottom.
> > > > >
> > > > > -
> > > > > intel_pcode_init()
> > > > > |
> > > > > +-> skl_pcode_request(uncore, DG1_PCODE_STATUS,
> > > > >DG1_UNCORE_GET_INIT_STATUS,
> > > > >DG1_UNCORE_INIT_STATUS_COMPLETE,
> > > > >DG1_UNCORE_INIT_STATUS_COMPLETE, 18);
> > > > >|
> > > > >+-> skl_pcode_try_request()
> > > > > |
> > > > > +-> *status = __snb_pcode_rw(uncore, mbox, ,
> > > > > NULL,
> > > > >500, 0, true);
> > > > >
> > > > > -
> > > > > static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
> > > > > u32 *val, u32 *val1,
> > > > > int fast_timeout_us, int slow_timeout_ms,
> > > > > bool is_read)
> > > > > {
> > > > > ...
> > > > > /* Before writing a value to the GEN6_PCODE_DATA register,
> > > > >check if the bit in the GEN6_PCODE_MAILBOX register
> > > > > indicates
> > > > >BUSY. */
> > > > > if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) &
> > > > > GEN6_PCODE_READY)
> > > > > return -EAGAIN;
> > > >
> > > > what if we fail here because the punit is still initializing and
> > > > will be ready, say, in 10 seconds?
> > > >
> > > > GG, without going any further, we fail here! The -EAGAIN we
> > > > receive from the test comes from this point. We don't fail with
> > > > -ETIMEDOUT, but with -EAGAIN and the reason is because the punit
> > > > is not ready to perform the very fist communication and we fail
> > > > the probing.
> > > >
> > > > It doesn't mean, though, that there is anything wrong, we just
> > > > need to wait a bit before "taking drastic decisions"!
> > > >
> > > > This patch is suggesting to wait up to 10s for the punit to be
> > > > ready and eventually try to probe again... and, indeed, it works!
> > >
> > > As GG, what I still don't understand is how this extra 10 seconds
> > > wait helps... have you tried to simple add the 10 to the 180 and
> > > make the code 190 sec instead?
> >
> > maybe I haven't been able to explain the issue properly.
> >
> > I can even set that timer to 2hrs and a half and nothing changes
> > because we fail before.
> >
> > Here it's not a matter of how much do I wait but when do I check
> > the pcode readiness (i.e. signalled by the GEN6_PCODE_READY bit
> > in the GEN6_PCODE_MAILBOX register).
> >
> > During a normal run we are always sure that communicating with
> > the punit works, because we made it sure during the previous
> > transaction.
> >
> > During probe there is no previous transaction and we start
> > communicating with the punit without making sure that it is
> > ready. And indeed some times it is not, so that we suppress the
> > probing on purpose instead of giving it another chance.
> >
> > I admit that the commit message is not written properly and
> > rather misleading, but here it's not at all a matter of how much
> > do I wait.
>
> The commit message was initially confused because it looks like
> we are just adding a wait, without doing anything
>
> But looking to the code we can see that it will wait until
> pcode is ready with a timeout of 10 seconds.
>
> But if pcode is ready in 10 seconds, why pcode is not ready
> in 190 seconds. We are doing absolutely nothing more that could
> make pcode ready in 10 seconds that won't be in 190.
>
> This is what we are missing here... The code as is doesn't make
> a lot of sense to us and it looks like it is solving the issue
> by the 10 extra seconds and not by some special status checking.
Okay, after an offline talk I am convinced now that we need some
check like this in some place.
But the commit message needs be be fully re-written.
It needs to be clear that underneath, the pcode communication
functions will do a check for ready without any wait, what will
make desired timeout to never really wait for the pcode done
and prematurely return.
at __snb_pcode_rw():
if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
return -EAGAIN;
So, for this reason we need to ensure that pcode is really ready
before we wait.
Other options are to handle the EAGAIN return and then wait.
Or even change the __snb_pcode_rw to ensure that it is ready...
Something like:
- if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) &
Re: [Intel-gfx] [PATCH 3/3] drm/i915/dg1: Drop final use of IS_DG1_GRAPHICS_STEP
On Fri, Jan 27, 2023 at 02:43:13PM -0800, Matt Roper wrote:
> All production DG1 hardware has graphics stepping B0; there is no such
> thing as C0. As such, we can simplify
>
> IS_DG1_GRAPHICS_STEP(uncore->i915, STEP_A0, STEP_C0)
>
> to just match DG1 in general.
>
> Bspec: 44463
> Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 ---
> 2 files changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index f3ad93db0b21..89fdfc67f8d1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -158,7 +158,7 @@ static const struct intel_memory_region_ops
> intel_region_lmem_ops = {
> static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
>u64 *start, u32 *size)
> {
> - if (!IS_DG1_GRAPHICS_STEP(uncore->i915, STEP_A0, STEP_C0))
> + if (!IS_DG1(uncore->i915))
> return false;
>
> *start = 0;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 57b84dbca084..495788e18b77 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -656,9 +656,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_RKL_DISPLAY_STEP(p, since, until) \
> (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
>
> -#define IS_DG1_GRAPHICS_STEP(p, since, until) \
> - (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
> -
> #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
> (IS_ALDERLAKE_S(__i915) && \
>IS_DISPLAY_STEP(__i915, since, until))
> --
> 2.39.1
>
Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg1: Drop support for pre-production steppings
On Fri, Jan 27, 2023 at 02:43:12PM -0800, Matt Roper wrote:
> Several post-DG1 platforms have been brought up now, so we're well past
> the point where we usually drop the workarounds that are only applicable
> to internal/pre-production hardware.
>
> Production DG1 hardware always has a B0 stepping for both display and
> GT.
>
> Bspec: 44463
> Signed-off-by: Matt Roper
> ---
> .../drm/i915/display/intel_display_power.c| 1 -
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 ++-
> drivers/gpu/drm/i915/i915_driver.c| 1 +
> drivers/gpu/drm/i915/i915_drv.h | 2 -
> drivers/gpu/drm/i915/intel_pm.c | 12 -
> 5 files changed, 5 insertions(+), 59 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 1dc31f0f5e0a..7222502a760c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1580,7 +1580,6 @@ static void tgl_bw_buddy_init(struct drm_i915_private
> *dev_priv)
> return;
>
> if (IS_ALDERLAKE_S(dev_priv) ||
> - IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> /* Wa_1409767108 */
> table = wa_1409767108_buddy_page_masks;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 82a8f372bde6..648fceba5bb6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1463,12 +1463,6 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct
> i915_wa_list *wal)
>
> gen12_gt_workarounds_init(gt, wal);
>
> - /* Wa_1607087056:dg1 */
> - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> - wa_write_or(wal,
> - GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> - L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> -
> /* Wa_1409420604:dg1 */
> if (IS_DG1(i915))
> wa_mcr_write_or(wal,
> @@ -2103,20 +2097,6 @@ static void tgl_whitelist_build(struct intel_engine_cs
> *engine)
> }
> }
>
> -static void dg1_whitelist_build(struct intel_engine_cs *engine)
> -{
> - struct i915_wa_list *w = >whitelist;
> -
> - tgl_whitelist_build(engine);
> -
> - /* GEN:BUG:1409280441:dg1 */
> - if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) &&
> - (engine->class == RENDER_CLASS ||
> - engine->class == COPY_ENGINE_CLASS))
> - whitelist_reg_ext(w, RING_ID(engine->mmio_base),
> - RING_FORCE_TO_NONPRIV_ACCESS_RD);
> -}
> -
> static void xehpsdv_whitelist_build(struct intel_engine_cs *engine)
> {
> allow_read_ctx_timestamp(engine);
> @@ -2196,8 +2176,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs
> *engine)
> dg2_whitelist_build(engine);
> else if (IS_XEHPSDV(i915))
> xehpsdv_whitelist_build(engine);
> - else if (IS_DG1(i915))
> - dg1_whitelist_build(engine);
> else if (GRAPHICS_VER(i915) == 12)
> tgl_whitelist_build(engine);
> else if (GRAPHICS_VER(i915) == 11)
> @@ -2410,16 +2388,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> true);
> }
>
> - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> - /*
> - * Wa_1607138336
> - * Wa_1607063988
> - */
> - wa_write_or(wal,
> - GEN9_CTX_PREEMPT_REG,
> - GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> - }
> -
> if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> @@ -2449,30 +2417,22 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> }
>
> if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
> - IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> - /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
> + /* Wa_1409804808 */
> wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>GEN12_PUSH_CONST_DEREF_HOLD_DIS);
>
> - /*
> - * Wa_1409085225:tgl
> - * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p
> - */
> + /* Wa_14010229206 */
> wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4,
> GEN12_DISABLE_TDL_PUSH);
> }
>
> - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> - IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) {
> + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) ||
Re: [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings
On Mon, Jan 30, 2023 at 09:03:17AM -0800, Matt Roper wrote:
> On Mon, Jan 30, 2023 at 11:42:41AM -0500, Rodrigo Vivi wrote:
> > On Mon, Jan 30, 2023 at 07:51:51AM -0800, Matt Roper wrote:
> > > On Mon, Jan 30, 2023 at 10:46:16AM -0500, Rodrigo Vivi wrote:
> > > > On Fri, Jan 27, 2023 at 02:43:11PM -0800, Matt Roper wrote:
> > > > > Several post-TGL platforms have been brought up now, so we're well
> > > > > past
> > > > > the point where we usually drop the workarounds that are only
> > > > > applicable
> > > > > to internal/pre-production hardware.
> > > > >
> > > > > Production TGL hardware always has display stepping C0 or later and GT
> > > > > stepping B0 or later (this is true for both the original TGL and the
> > > > > U/Y
> > > > > subplatform).
> > > > >
> > > > > Bspec 44455
> > > > > Signed-off-by: Matt Roper
> > > > > ---
> > > > > .../drm/i915/display/intel_display_power.c| 5 +--
> > > > > drivers/gpu/drm/i915/display/intel_psr.c | 26 ---
> > > > > .../drm/i915/display/skl_universal_plane.c| 2 +-
> > > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 44
> > > > > ++-
> > > > > drivers/gpu/drm/i915/i915_driver.c| 1 +
> > > > > drivers/gpu/drm/i915/i915_drv.h | 8
> > > > > drivers/gpu/drm/i915/intel_pm.c | 4 --
> > > > > 7 files changed, 7 insertions(+), 83 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > index 1a23ecd4623a..1dc31f0f5e0a 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > @@ -1581,9 +1581,8 @@ static void tgl_bw_buddy_init(struct
> > > > > drm_i915_private *dev_priv)
> > > > >
> > > > > if (IS_ALDERLAKE_S(dev_priv) ||
> > > > > IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > > > - IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > > > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> > > > > - /* Wa_1409767108:tgl,dg1,adl-s */
> > > > > + IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > > >
> > > > I believe we should go ahead and also remove the RKL ones like this.
> > > > After all we have ADL and MTL and none needed this for instance.
> > >
> > > Do we know for sure that A0 RKL wasn't productized? I can't find the
> > > details about which stepping(s) were pre-prod-only in the bspec, so I've
> > > left RKL and ADL workarounds alone for the time being.
> >
> > Very good point. However this point may be against this patch,
> > or at least part of it, since there are some TGL GT2 B0
> > not marked as pre-production.
>
> The CPU, GT, and display stepping are all independent of each other.
> According to bspec 44455, all production steppings of TGL have either
> display stepping C0 or D0.
oh, indeed!
Reviewed-by: Rodrigo Vivi
>
>
> Matt
>
> >
> > >
> > >
> > > Matt
> > >
> > > >
> > > > > + /* Wa_1409767108 */
> > > > > table = wa_1409767108_buddy_page_masks;
> > > > > else
> > > > > table = tgl_buddy_page_masks;
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > index 7d4a15a283a0..5dca58dd97a9 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > @@ -591,12 +591,6 @@ static void hsw_activate_psr2(struct intel_dp
> > > > > *intel_dp)
> > > > > if (intel_dp->psr.psr2_sel_fetch_enabled) {
> > > > > u32 tmp;
> > > > >
> > > > > - /* Wa_1408330847 */
> > > > > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > > > > - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > > > > - DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> > > > > - DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> > > > > -
> > > > > tmp = intel_de_read(dev_priv,
> > > > > PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
> > > > > drm_WARN_ON(_priv->drm, !(tmp &
> > > > > PSR2_MAN_TRK_CTL_ENABLE));
> > > > > } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> > > > > @@ -765,13 +759,6 @@ static bool
> > > > > intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > > > > return false;
> > > > > }
> > > > >
> > > > > - /* Wa_14010254185 Wa_14010103792 */
> > > > > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > > > - drm_dbg_kms(_priv->drm,
> > > > > - "PSR2 sel fetch not enabled, missing the
> > > > > implementation of WAs\n");
> > > > > - return false;
> > > > > - }
> > > > > -
> > > > > return crtc_state->enable_psr2_sel_fetch = true;
> > > > > }
> > > > >
> > > >
Re: [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings
On Mon, Jan 30, 2023 at 11:42:41AM -0500, Rodrigo Vivi wrote:
> On Mon, Jan 30, 2023 at 07:51:51AM -0800, Matt Roper wrote:
> > On Mon, Jan 30, 2023 at 10:46:16AM -0500, Rodrigo Vivi wrote:
> > > On Fri, Jan 27, 2023 at 02:43:11PM -0800, Matt Roper wrote:
> > > > Several post-TGL platforms have been brought up now, so we're well past
> > > > the point where we usually drop the workarounds that are only applicable
> > > > to internal/pre-production hardware.
> > > >
> > > > Production TGL hardware always has display stepping C0 or later and GT
> > > > stepping B0 or later (this is true for both the original TGL and the U/Y
> > > > subplatform).
> > > >
> > > > Bspec 44455
> > > > Signed-off-by: Matt Roper
> > > > ---
> > > > .../drm/i915/display/intel_display_power.c| 5 +--
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 26 ---
> > > > .../drm/i915/display/skl_universal_plane.c| 2 +-
> > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 44 ++-
> > > > drivers/gpu/drm/i915/i915_driver.c| 1 +
> > > > drivers/gpu/drm/i915/i915_drv.h | 8
> > > > drivers/gpu/drm/i915/intel_pm.c | 4 --
> > > > 7 files changed, 7 insertions(+), 83 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > index 1a23ecd4623a..1dc31f0f5e0a 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > @@ -1581,9 +1581,8 @@ static void tgl_bw_buddy_init(struct
> > > > drm_i915_private *dev_priv)
> > > >
> > > > if (IS_ALDERLAKE_S(dev_priv) ||
> > > > IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > > - IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> > > > - /* Wa_1409767108:tgl,dg1,adl-s */
> > > > + IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > >
> > > I believe we should go ahead and also remove the RKL ones like this.
> > > After all we have ADL and MTL and none needed this for instance.
> >
> > Do we know for sure that A0 RKL wasn't productized? I can't find the
> > details about which stepping(s) were pre-prod-only in the bspec, so I've
> > left RKL and ADL workarounds alone for the time being.
>
> Very good point. However this point may be against this patch,
> or at least part of it, since there are some TGL GT2 B0
> not marked as pre-production.
The CPU, GT, and display stepping are all independent of each other.
According to bspec 44455, all production steppings of TGL have either
display stepping C0 or D0.
Matt
>
> >
> >
> > Matt
> >
> > >
> > > > + /* Wa_1409767108 */
> > > > table = wa_1409767108_buddy_page_masks;
> > > > else
> > > > table = tgl_buddy_page_masks;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 7d4a15a283a0..5dca58dd97a9 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -591,12 +591,6 @@ static void hsw_activate_psr2(struct intel_dp
> > > > *intel_dp)
> > > > if (intel_dp->psr.psr2_sel_fetch_enabled) {
> > > > u32 tmp;
> > > >
> > > > - /* Wa_1408330847 */
> > > > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > > > - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > > > -DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> > > > -DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> > > > -
> > > > tmp = intel_de_read(dev_priv,
> > > > PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
> > > > drm_WARN_ON(_priv->drm, !(tmp &
> > > > PSR2_MAN_TRK_CTL_ENABLE));
> > > > } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> > > > @@ -765,13 +759,6 @@ static bool
> > > > intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > > > return false;
> > > > }
> > > >
> > > > - /* Wa_14010254185 Wa_14010103792 */
> > > > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > > - drm_dbg_kms(_priv->drm,
> > > > - "PSR2 sel fetch not enabled, missing the
> > > > implementation of WAs\n");
> > > > - return false;
> > > > - }
> > > > -
> > > > return crtc_state->enable_psr2_sel_fetch = true;
> > > > }
> > > >
> > > > @@ -945,13 +932,6 @@ static bool intel_psr2_config_valid(struct
> > > > intel_dp *intel_dp,
> > > > }
> > > > }
> > > >
> > > > - /* Wa_2209313811 */
> > > > - if (!crtc_state->enable_psr2_sel_fetch &&
> > > > - IS_TGL_DISPLAY_STEP(dev_priv,
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 5/6] intel_gpu_top: Fix cleanup on old kernels / unsupported GPU
Hi,
On 2023-01-30 at 10:55:42 +, Tvrtko Ursulin wrote:
>
> On 27/01/2023 16:10, Kamil Konieczny wrote:
> > Hi Tvrtko,
> >
> > On 2023-01-27 at 11:12:40 +, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin
> > >
> > > Avoid trying to dereference null engines on exit when there are either
> > > none which are supported, or kernel does not have i915 PMU support.
> > >
> > > Also fix a memory leak on the same failure path just so Valgrind runs are
> > > quite.
> > >
> > > v2:
> > > * Fix a memory leak in the same failure mode too.
> >
> > Please rebase, patch do not apply.
>
> Hm how, CI applied it fine. Maybe you mean as standalone? There is the same
> patch here:
> https://patchwork.freedesktop.org/patch/519751/?series=113096=2
>
> > > Signed-off-by: Tvrtko Ursulin
> > > Acked-by: Nirmoy Das # v1
> > ^
> > Delete this.
>
> I can do that only if Nirmoy agrees. ;)
>
> Regards,
>
> Tvrtko
It is already too late, that was merged some time ago and got
into git history so nothing can be done now.
Regards,
Kamil
>
> > Rest looks good,
> >
> > Regards,
> > Kamil
> >
> > > ---
> > > tools/intel_gpu_top.c | 21 ++---
> > > 1 file changed, 14 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> > > index 7aa233570463..0a1de41b3374 100644
> > > --- a/tools/intel_gpu_top.c
> > > +++ b/tools/intel_gpu_top.c
> > > @@ -340,7 +340,7 @@ static struct engines *discover_engines(char *device)
> > > d = opendir(sysfs_root);
> > > if (!d)
> > > - return NULL;
> > > + goto err;
> > > while ((dent = readdir(d)) != NULL) {
> > > const char *endswith = "-busy";
> > > @@ -423,10 +423,8 @@ static struct engines *discover_engines(char *device)
> > > }
> > > if (ret) {
> > > - free(engines);
> > > errno = ret;
> > > -
> > > - return NULL;
> > > + goto err;
> > > }
> > > qsort(engine_ptr(engines, 0), engines->num_engines,
> > > @@ -435,6 +433,11 @@ static struct engines *discover_engines(char *device)
> > > engines->root = d;
> > > return engines;
> > > +
> > > +err:
> > > + free(engines);
> > > +
> > > + return NULL;
> > > }
> > > static void free_engines(struct engines *engines)
> > > @@ -448,6 +451,9 @@ static void free_engines(struct engines *engines)
> > > };
> > > unsigned int i;
> > > + if (!engines)
> > > + return;
> > > +
> > > for (pmu = _list[0]; *pmu; pmu++) {
> > > if ((*pmu)->present)
> > > free((char *)(*pmu)->units);
> > > @@ -2568,7 +2574,7 @@ int main(int argc, char **argv)
> > > "Failed to detect engines! (%s)\n(Kernel 4.16
> > > or newer is required for i915 PMU support.)\n",
> > > strerror(errno));
> > > ret = EXIT_FAILURE;
> > > - goto err;
> > > + goto err_engines;
> > > }
> > > ret = pmu_init(engines);
> > > @@ -2585,7 +2591,7 @@ int main(int argc, char **argv)
> > > "More information can be found at 'Perf events and tool security'
> > > document:\n"
> > >
> > > "https://www.kernel.org/doc/html/latest/admin-guide/perf-security.html\n;);
> > > ret = EXIT_FAILURE;
> > > - goto err;
> > > + goto err_pmu;
> > > }
> > > ret = EXIT_SUCCESS;
> > > @@ -2699,8 +2705,9 @@ int main(int argc, char **argv)
> > > free_clients(clients);
> > > free(codename);
> > > -err:
> > > +err_pmu:
> > > free_engines(engines);
> > > +err_engines:
> > > free(pmu_device);
> > > exit:
> > > igt_devices_free();
> > > --
> > > 2.34.1
> > >
Re: [Intel-gfx] [PATCH v5] drm/i915/gt: Add selftests for TLB invalidation
On 30.01.2023 13:35, Tvrtko Ursulin wrote:
On 30/01/2023 10:14, Andrzej Hajda wrote:
From: Chris Wilson
Check that we invalidate the TLB cache, the updated physical addresses
are immediately visible to the HW, and there is no retention of the old
physical address for concurrent HW access.
Signed-off-by: Chris Wilson
[ahajda: adjust to upstream driver, v2+]
Signed-off-by: Andrzej Hajda
---
v2:
- addressed comments (Tvrtko),
- changed pin/sample address calculation,
- removed checks for platforms older than 8,
- use low ints in MI_DO_COMPARE to be more clear,
- continue test if physical addresses have the same uppper 32 bits,
- consolidate two calls to pte_tlbinv into one
v3:
- skip pages not supported by vm (CI reported EINVAL),
- fix dw size in MI_CONDITIONAL_BATCH_BUFFER_END for gen8 (CI
reported EIO),
- remove aggressive allocation to get different upper halves of
physical
address (CI reported OOM).
v4:
- align address in MI_CONDITIONAL_BATCH_BUFFER_END to 8b,
- set QWORD pointed by addr in above cmd, as required by Gen8/VCS.
v5:
- set dw size again to 2 (CI reports EIO due to semaphore
sanitycheck).
Sorry for spamming, but apparently CI is the only way to test Gen8.
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 4 +
drivers/gpu/drm/i915/gt/selftest_tlb.c | 379 ++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
4 files changed, 385 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_tlb.c
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 2af1ae3831df98..e10507fa71ce63 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -394,6 +394,7 @@
#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
+#define MI_DO_COMPARE REG_BIT(21)
#define STATE_BASE_ADDRESS \
((0x3 << 29) | (0x0 << 27) | (0x1 << 24) | (0x1 << 16))
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f0dbfc434e0773..001a7ec5b86182 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1205,3 +1205,7 @@ void intel_gt_invalidate_tlb(struct intel_gt
*gt, u32 seqno)
mutex_unlock(>tlb.invalidate_lock);
}
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_tlb.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c
b/drivers/gpu/drm/i915/gt/selftest_tlb.c
new file mode 100644
index 00..166d18a614d51d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "i915_selftest.h"
+
+#include "gem/i915_gem_internal.h"
+#include "gem/i915_gem_region.h"
+
+#include "gen8_engine_cs.h"
+#include "i915_gem_ww.h"
+#include "intel_engine_regs.h"
+#include "intel_gpu_commands.h"
+#include "intel_context.h"
+#include "intel_gt.h"
+#include "intel_ring.h"
+
+#include "selftests/igt_flush_test.h"
+#include "selftests/i915_random.h"
+
+static void vma_set_qw(struct i915_vma *vma, u64 addr, u64 val)
+{
+ GEM_BUG_ON(addr < i915_vma_offset(vma));
+ GEM_BUG_ON(addr >= i915_vma_offset(vma) + i915_vma_size(vma) +
sizeof(val));
+ memset64(page_mask_bits(vma->obj->mm.mapping) +
+ (addr - i915_vma_offset(vma)), val, 1);
+}
+
+static int
+pte_tlbinv(struct intel_context *ce,
+ struct i915_vma *va,
+ struct i915_vma *vb,
+ u64 align,
+ void (*tlbinv)(struct i915_address_space *vm, u64 addr, u64
length),
+ u64 length,
+ struct rnd_state *prng)
+{
+ struct drm_i915_gem_object *batch;
+ struct i915_request *rq;
+ struct i915_vma *vma;
+ u64 addr;
+ int err;
+ u32 *cs;
+
+ batch = i915_gem_object_create_internal(ce->vm->i915, 4096);
+ if (IS_ERR(batch))
+ return PTR_ERR(batch);
+
+ vma = i915_vma_instance(batch, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto out;
+
+ /* Pin va at random but aligned offset after vma */
+ addr = round_up(vma->node.start + vma->node.size, align);
+ /* MI_CONDITIONAL_BATCH_BUFFER_END limits address to 48b */
+ addr = igt_random_offset(prng, addr, min(ce->vm->total,
BIT_ULL(48)),
+ va->size, align);
+ err = i915_vma_pin(va, 0, 0, addr | PIN_OFFSET_FIXED | PIN_USER);
+ if (err) {
+ pr_err("Cannot pin at %llx+%llx\n", addr, va->size);
+ goto out;
+ }
+ GEM_BUG_ON(i915_vma_offset(va) != addr);
+ vb->node = va->node; /* overwrites the _same_ PTE */
+
+ /*
+ * Now choose random dword at the 1st pinned
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 6/6] lib/igt_device_scan: Improve Intel discrete GPU selection
Hi,
On 2023-01-30 at 11:04:07 +, Tvrtko Ursulin wrote:
>
> On 27/01/2023 16:17, Kamil Konieczny wrote:
> > Hi Tvrtko,
> >
> > On 2023-01-27 at 11:12:41 +, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin
> > >
> > > Now that DRM subsystem can contain PCI cards with the vendor set to Intel
> > > but they are not Intel GPUs, we need a better selection logic than looking
> > > at the vendor. Use the driver name instead.
> > >
> > > Caveat that the driver key was on a blacklist so far, and although I can't
> > > imagine it can be slow to probe, this is something to double check.
> > >
> > > Signed-off-by: Tvrtko Ursulin
> > > Cc: Kamil Konieczny
> > > Cc: Zbigniew Kempczyński
> >
> > Please send this as separate patch, not in this series.
>
> Yeah I was lazy and wanting to save time so okay.
>
Well maybe next time, I already merged your series without 5/6,
that one were merged some time ago.
Regards,
Kamil
> > > ---
> > > lib/igt_device_scan.c | 7 +--
> > > 1 file changed, 5 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/lib/igt_device_scan.c b/lib/igt_device_scan.c
> > > index ed128d24dd10..8b767eed202d 100644
> > > --- a/lib/igt_device_scan.c
> > > +++ b/lib/igt_device_scan.c
> > > @@ -237,6 +237,7 @@ struct igt_device {
> > > char *vendor;
> > > char *device;
> > > char *pci_slot_name;
> > > + char *driver;
> > > int gpu_index; /* For more than one GPU with same vendor and
> > > device. */
> > > char *codename; /* For grouping by codename */
> > > @@ -440,7 +441,6 @@ static bool is_on_blacklist(const char *what)
> > > "resource3", "resource4",
> > > "resource5",
> > > "resource0_wc", "resource1_wc",
> > > "resource2_wc",
> > > "resource3_wc", "resource4_wc",
> > > "resource5_wc",
> > > - "driver",
> > > "uevent", NULL};
> > > const char *key;
> > > int i = 0;
> > > @@ -662,6 +662,8 @@ static struct igt_device
> > > *igt_device_new_from_udev(struct udev_device *dev)
> > > get_pci_vendor_device(idev, , );
> > > idev->codename = __pci_codename(vendor, device);
> > > idev->dev_type = __pci_devtype(vendor, device,
> > > idev->pci_slot_name);
> > > + idev->driver = strdup_nullsafe(get_attr(idev, "driver"));
> > > + igt_assert(idev->driver);
> > > }
> > > return idev;
> > > @@ -776,7 +778,7 @@ static bool __find_first_i915_card(struct
> > > igt_device_card *card, bool discrete)
> > > igt_list_for_each_entry(dev, _devs.all, link) {
> > > - if (!is_pci_subsystem(dev) || !is_vendor_matched(dev, "intel"))
> > > + if (!is_pci_subsystem(dev) || strcmp(dev->driver, "i915"))
> >
> > Put the comment here why it can be problematic to relay on driver name.
>
> Function name being __find_first_*i915*_card is IMO enough so it feels any
> comment to the same effect would be redundant.
>
> Hm if anything igt_device_find_integrated_card should be renamed..
>
> Regards,
>
> Tvrtko
>
> >
> > Regards,
> > Kamil
> >
> > > continue;
> > > cmp = strncmp(dev->pci_slot_name,
> > > INTEGRATED_I915_GPU_PCI_ID,
> > > @@ -1023,6 +1025,7 @@ static void igt_device_free(struct igt_device *dev)
> > > free(dev->drm_render);
> > > free(dev->vendor);
> > > free(dev->device);
> > > + free(dev->driver);
> > > free(dev->pci_slot_name);
> > > g_hash_table_destroy(dev->attrs_ht);
> > > g_hash_table_destroy(dev->props_ht);
> > > --
> > > 2.34.1
> > >
[Intel-gfx] [PATCH v6] drm/i915/gt: Add selftests for TLB invalidation
From: Chris Wilson
Check that we invalidate the TLB cache, the updated physical addresses
are immediately visible to the HW, and there is no retention of the old
physical address for concurrent HW access.
Signed-off-by: Chris Wilson
[ahajda: adjust to upstream driver, v2+]
Signed-off-by: Andrzej Hajda
---
v2:
- addressed comments (Tvrtko),
- changed pin/sample address calculation,
- removed checks for platforms older than 8,
- use low ints in MI_DO_COMPARE to be more clear,
- continue test if physical addresses have the same uppper 32 bits,
- consolidate two calls to pte_tlbinv into one
v3:
- skip pages not supported by vm (CI reported EINVAL),
- fix dw size in MI_CONDITIONAL_BATCH_BUFFER_END for gen8 (CI reported EIO),
- remove aggressive allocation to get different upper halves of physical
address (CI reported OOM).
v4:
- align address in MI_CONDITIONAL_BATCH_BUFFER_END to 8b,
- set QWORD pointed by addr in above cmd, as required by Gen8/VCS.
v5:
- set dw size again to 2 (CI reports EIO due to semaphore sanitycheck).
v6:
- restore original vb->node on exit (Tvrtko),
- print sanitycheck params only on error (Tvrtko),
- comment fixes (Tvrtko)
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/gt/intel_gt.c| 4 +
drivers/gpu/drm/i915/gt/selftest_tlb.c| 388 ++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
4 files changed, 394 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_tlb.c
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 2af1ae3831df98..e10507fa71ce63 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -394,6 +394,7 @@
#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
#define MI_STORE_URB_MEMMI_INSTR(0x2D, 0)
#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
+#define MI_DO_COMPARE REG_BIT(21)
#define STATE_BASE_ADDRESS \
((0x3 << 29) | (0x0 << 27) | (0x1 << 24) | (0x1 << 16))
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f0dbfc434e0773..001a7ec5b86182 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1205,3 +1205,7 @@ void intel_gt_invalidate_tlb(struct intel_gt *gt, u32
seqno)
mutex_unlock(>tlb.invalidate_lock);
}
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_tlb.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c
b/drivers/gpu/drm/i915/gt/selftest_tlb.c
new file mode 100644
index 00..355646c001762f
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "i915_selftest.h"
+
+#include "gem/i915_gem_internal.h"
+#include "gem/i915_gem_region.h"
+
+#include "gen8_engine_cs.h"
+#include "i915_gem_ww.h"
+#include "intel_engine_regs.h"
+#include "intel_gpu_commands.h"
+#include "intel_context.h"
+#include "intel_gt.h"
+#include "intel_ring.h"
+
+#include "selftests/igt_flush_test.h"
+#include "selftests/i915_random.h"
+
+static void vma_set_qw(struct i915_vma *vma, u64 addr, u64 val)
+{
+ GEM_BUG_ON(addr < i915_vma_offset(vma));
+ GEM_BUG_ON(addr >= i915_vma_offset(vma) + i915_vma_size(vma) +
sizeof(val));
+ memset64(page_mask_bits(vma->obj->mm.mapping) +
+(addr - i915_vma_offset(vma)), val, 1);
+}
+
+static int
+pte_tlbinv(struct intel_context *ce,
+ struct i915_vma *va,
+ struct i915_vma *vb,
+ u64 align,
+ void (*tlbinv)(struct i915_address_space *vm, u64 addr, u64 length),
+ u64 length,
+ struct rnd_state *prng)
+{
+ struct drm_i915_gem_object *batch;
+ struct drm_mm_node vb_node;
+ struct i915_request *rq;
+ struct i915_vma *vma;
+ u64 addr;
+ int err;
+ u32 *cs;
+
+ batch = i915_gem_object_create_internal(ce->vm->i915, 4096);
+ if (IS_ERR(batch))
+ return PTR_ERR(batch);
+
+ vma = i915_vma_instance(batch, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto out;
+
+ /* Pin va at random but aligned offset after vma */
+ addr = round_up(vma->node.start + vma->node.size, align);
+ /* MI_CONDITIONAL_BATCH_BUFFER_END limits address to 48b */
+ addr = igt_random_offset(prng, addr, min(ce->vm->total, BIT_ULL(48)),
+va->size, align);
+ err = i915_vma_pin(va, 0, 0, addr | PIN_OFFSET_FIXED | PIN_USER);
+ if (err) {
+ pr_err("Cannot pin at %llx+%llx\n", addr, va->size);
+ goto out;
+ }
+
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/6] drm/i915/ttm: fix sparse warning
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/ttm: fix sparse warning
URL : https://patchwork.freedesktop.org/series/113484/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12666 -> Patchwork_113484v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/index.html
Participating hosts (25 -> 24)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_113484v1 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][1] ([i915#5334]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@slpc:
- {bat-adlp-6}: [DMESG-FAIL][3] ([i915#6367] / [i915#7913]) ->
[PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12666/bat-adlp-6/igt@i915_selftest@l...@slpc.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/bat-adlp-6/igt@i915_selftest@l...@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
Build changes
-
* Linux: CI_DRM_12666 -> Patchwork_113484v1
CI-20190529: 20190529
CI_DRM_12666: 908c84b836ee39b5565561a0b352c2dc18378215 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7142: adeeb8527422155ff4039aed34a922da4a7d @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113484v1: 908c84b836ee39b5565561a0b352c2dc18378215 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
eb29c526bc38 drm/ttm: prevent moving of pinned BOs
6f65d4b71375 drm/ttm: stop allocating a dummy resource for pipelined gutting
4f490e93000d drm/ttm: stop allocating dummy resources during BO creation
e46562673b6e drm/ttm: clear the ttm_tt when bo->resource is NULL
a97096bdbf82 drm/i915/ttm: audit remaining bo->resource
e5538d79c03c drm/i915/ttm: fix sparse warning
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113484v1/index.html
Re: [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings
On Mon, Jan 30, 2023 at 07:51:51AM -0800, Matt Roper wrote:
> On Mon, Jan 30, 2023 at 10:46:16AM -0500, Rodrigo Vivi wrote:
> > On Fri, Jan 27, 2023 at 02:43:11PM -0800, Matt Roper wrote:
> > > Several post-TGL platforms have been brought up now, so we're well past
> > > the point where we usually drop the workarounds that are only applicable
> > > to internal/pre-production hardware.
> > >
> > > Production TGL hardware always has display stepping C0 or later and GT
> > > stepping B0 or later (this is true for both the original TGL and the U/Y
> > > subplatform).
> > >
> > > Bspec 44455
> > > Signed-off-by: Matt Roper
> > > ---
> > > .../drm/i915/display/intel_display_power.c| 5 +--
> > > drivers/gpu/drm/i915/display/intel_psr.c | 26 ---
> > > .../drm/i915/display/skl_universal_plane.c| 2 +-
> > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 44 ++-
> > > drivers/gpu/drm/i915/i915_driver.c| 1 +
> > > drivers/gpu/drm/i915/i915_drv.h | 8
> > > drivers/gpu/drm/i915/intel_pm.c | 4 --
> > > 7 files changed, 7 insertions(+), 83 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 1a23ecd4623a..1dc31f0f5e0a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -1581,9 +1581,8 @@ static void tgl_bw_buddy_init(struct
> > > drm_i915_private *dev_priv)
> > >
> > > if (IS_ALDERLAKE_S(dev_priv) ||
> > > IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > - IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> > > - /* Wa_1409767108:tgl,dg1,adl-s */
> > > + IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >
> > I believe we should go ahead and also remove the RKL ones like this.
> > After all we have ADL and MTL and none needed this for instance.
>
> Do we know for sure that A0 RKL wasn't productized? I can't find the
> details about which stepping(s) were pre-prod-only in the bspec, so I've
> left RKL and ADL workarounds alone for the time being.
Very good point. However this point may be against this patch,
or at least part of it, since there are some TGL GT2 B0
not marked as pre-production.
>
>
> Matt
>
> >
> > > + /* Wa_1409767108 */
> > > table = wa_1409767108_buddy_page_masks;
> > > else
> > > table = tgl_buddy_page_masks;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 7d4a15a283a0..5dca58dd97a9 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -591,12 +591,6 @@ static void hsw_activate_psr2(struct intel_dp
> > > *intel_dp)
> > > if (intel_dp->psr.psr2_sel_fetch_enabled) {
> > > u32 tmp;
> > >
> > > - /* Wa_1408330847 */
> > > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > > - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > > - DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> > > - DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> > > -
> > > tmp = intel_de_read(dev_priv,
> > > PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
> > > drm_WARN_ON(_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
> > > } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> > > @@ -765,13 +759,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct
> > > intel_dp *intel_dp,
> > > return false;
> > > }
> > >
> > > - /* Wa_14010254185 Wa_14010103792 */
> > > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > - drm_dbg_kms(_priv->drm,
> > > - "PSR2 sel fetch not enabled, missing the
> > > implementation of WAs\n");
> > > - return false;
> > > - }
> > > -
> > > return crtc_state->enable_psr2_sel_fetch = true;
> > > }
> > >
> > > @@ -945,13 +932,6 @@ static bool intel_psr2_config_valid(struct intel_dp
> > > *intel_dp,
> > > }
> > > }
> > >
> > > - /* Wa_2209313811 */
> > > - if (!crtc_state->enable_psr2_sel_fetch &&
> > > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > - drm_dbg_kms(_priv->drm, "PSR2 HW tracking is not supported
> > > this Display stepping\n");
> > > - goto unsupported;
> > > - }
> > > -
> > > if (!psr2_granularity_check(intel_dp, crtc_state)) {
> > > drm_dbg_kms(_priv->drm, "PSR2 not enabled, SU granularity
> > > not compatible\n");
> > > goto unsupported;
> > > @@ -1360,12 +1340,6 @@ static void intel_psr_disable_locked(struct
> > > intel_dp *intel_dp)
> > > intel_psr_exit(intel_dp);
> > > intel_psr_wait_exit_locked(intel_dp);
> > >
> > > - /* Wa_1408330847 */
> > > - if (intel_dp->psr.psr2_sel_fetch_enabled &&
> > > -
Re: [Intel-gfx] [PATCH] drm/i915/pcode: Wait 10 seconds for pcode to settle
On Mon, Jan 30, 2023 at 05:12:48PM +0100, Andi Shyti wrote:
> Hi Rodrigo,
>
> > > > In the call flow invoked by intel_pcode_init(), I've added brief
> > > > comments
> > > > where further clarification is needed in this scenario, and a
> > > > description of
> > > > the suspicious scenario at the bottom.
> > > >
> > > > -
> > > > intel_pcode_init()
> > > > |
> > > > +-> skl_pcode_request(uncore, DG1_PCODE_STATUS,
> > > >DG1_UNCORE_GET_INIT_STATUS,
> > > >DG1_UNCORE_INIT_STATUS_COMPLETE,
> > > >DG1_UNCORE_INIT_STATUS_COMPLETE, 18);
> > > >|
> > > >+-> skl_pcode_try_request()
> > > > |
> > > > +-> *status = __snb_pcode_rw(uncore, mbox, , NULL,
> > > >500, 0, true);
> > > >
> > > > -
> > > > static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
> > > > u32 *val, u32 *val1,
> > > > int fast_timeout_us, int slow_timeout_ms,
> > > > bool is_read)
> > > > {
> > > > ...
> > > > /* Before writing a value to the GEN6_PCODE_DATA register,
> > > >check if the bit in the GEN6_PCODE_MAILBOX register indicates
> > > >BUSY. */
> > > > if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) &
> > > > GEN6_PCODE_READY)
> > > > return -EAGAIN;
> > >
> > > what if we fail here because the punit is still initializing and
> > > will be ready, say, in 10 seconds?
> > >
> > > GG, without going any further, we fail here! The -EAGAIN we
> > > receive from the test comes from this point. We don't fail with
> > > -ETIMEDOUT, but with -EAGAIN and the reason is because the punit
> > > is not ready to perform the very fist communication and we fail
> > > the probing.
> > >
> > > It doesn't mean, though, that there is anything wrong, we just
> > > need to wait a bit before "taking drastic decisions"!
> > >
> > > This patch is suggesting to wait up to 10s for the punit to be
> > > ready and eventually try to probe again... and, indeed, it works!
> >
> > As GG, what I still don't understand is how this extra 10 seconds
> > wait helps... have you tried to simple add the 10 to the 180 and
> > make the code 190 sec instead?
>
> maybe I haven't been able to explain the issue properly.
>
> I can even set that timer to 2hrs and a half and nothing changes
> because we fail before.
>
> Here it's not a matter of how much do I wait but when do I check
> the pcode readiness (i.e. signalled by the GEN6_PCODE_READY bit
> in the GEN6_PCODE_MAILBOX register).
>
> During a normal run we are always sure that communicating with
> the punit works, because we made it sure during the previous
> transaction.
>
> During probe there is no previous transaction and we start
> communicating with the punit without making sure that it is
> ready. And indeed some times it is not, so that we suppress the
> probing on purpose instead of giving it another chance.
>
> I admit that the commit message is not written properly and
> rather misleading, but here it's not at all a matter of how much
> do I wait.
The commit message was initially confused because it looks like
we are just adding a wait, without doing anything
But looking to the code we can see that it will wait until
pcode is ready with a timeout of 10 seconds.
But if pcode is ready in 10 seconds, why pcode is not ready
in 190 seconds. We are doing absolutely nothing more that could
make pcode ready in 10 seconds that won't be in 190.
This is what we are missing here... The code as is doesn't make
a lot of sense to us and it looks like it is solving the issue
by the 10 extra seconds and not by some special status checking.
>
> Thanks, Rodrigo!
> Andi
>
> > >
> > > Andi
> > >
> > > >
> > > > /* write value to GEN6_PCODE_DATA register */
> > > > intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val);
> > > >
> > > > intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 :
> > > > 0);
> > > >
> > > > /* In this scenario, the value
> > > >"DG1_PCODE_STATUS | GEN6_PCODE_READY"
> > > >is written to the GEN6_PCODE_MAILBOX register,
> > > >so that the Busy status of the GEN6_PCODE_MAILBOX register
> > > >can be checked later.
> > > >(When the value of the GEN6_PCODE_READY bit of the
> > > > GEN6_PCODE_MAILBOX register changes to 0, the operation can
> > > > be considered completed.) */
> > > > intel_uncore_write_fw(uncore,
> > > > GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
> > > > mbox);
> > > >
> > > > /* In this scenario, verify that the BUSY status bit in the
> > > >
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/6] drm/i915/ttm: fix sparse warning
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/ttm: fix sparse warning
URL : https://patchwork.freedesktop.org/series/113484/
State : warning
== Summary ==
Error: dim checkpatch failed
b61deae6cd53 drm/i915/ttm: fix sparse warning
-:4: WARNING:EMAIL_SUBJECT: A patch subject line should describe the change not
the tool that found it
#4:
Subject: [PATCH] drm/i915/ttm: fix sparse warning
total: 0 errors, 1 warnings, 0 checks, 14 lines checked
b01ce1ac0799 drm/i915/ttm: audit remaining bo->resource
-:18: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 516198d317d8 ("drm/i915: audit
bo->resource usage v3")'
#18:
References: 516198d317d8 ("drm/i915: audit bo->resource usage v3")
total: 1 errors, 0 warnings, 0 checks, 59 lines checked
40dfa7888d44 drm/ttm: clear the ttm_tt when bo->resource is NULL
613ca8d70136 drm/ttm: stop allocating dummy resources during BO creation
652f0970e275 drm/ttm: stop allocating a dummy resource for pipelined gutting
e257da7a88a8 drm/ttm: prevent moving of pinned BOs
Re: [Intel-gfx] [PATCH] drm/i915/pcode: Wait 10 seconds for pcode to settle
Hi Rodrigo,
> > > In the call flow invoked by intel_pcode_init(), I've added brief comments
> > > where further clarification is needed in this scenario, and a description
> > > of
> > > the suspicious scenario at the bottom.
> > >
> > > -
> > > intel_pcode_init()
> > > |
> > > +-> skl_pcode_request(uncore, DG1_PCODE_STATUS,
> > >DG1_UNCORE_GET_INIT_STATUS,
> > >DG1_UNCORE_INIT_STATUS_COMPLETE,
> > >DG1_UNCORE_INIT_STATUS_COMPLETE, 18);
> > >|
> > >+-> skl_pcode_try_request()
> > > |
> > > +-> *status = __snb_pcode_rw(uncore, mbox, , NULL,
> > >500, 0, true);
> > >
> > > -
> > > static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
> > > u32 *val, u32 *val1,
> > > int fast_timeout_us, int slow_timeout_ms,
> > > bool is_read)
> > > {
> > > ...
> > > /* Before writing a value to the GEN6_PCODE_DATA register,
> > >check if the bit in the GEN6_PCODE_MAILBOX register indicates
> > >BUSY. */
> > > if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
> > > return -EAGAIN;
> >
> > what if we fail here because the punit is still initializing and
> > will be ready, say, in 10 seconds?
> >
> > GG, without going any further, we fail here! The -EAGAIN we
> > receive from the test comes from this point. We don't fail with
> > -ETIMEDOUT, but with -EAGAIN and the reason is because the punit
> > is not ready to perform the very fist communication and we fail
> > the probing.
> >
> > It doesn't mean, though, that there is anything wrong, we just
> > need to wait a bit before "taking drastic decisions"!
> >
> > This patch is suggesting to wait up to 10s for the punit to be
> > ready and eventually try to probe again... and, indeed, it works!
>
> As GG, what I still don't understand is how this extra 10 seconds
> wait helps... have you tried to simple add the 10 to the 180 and
> make the code 190 sec instead?
maybe I haven't been able to explain the issue properly.
I can even set that timer to 2hrs and a half and nothing changes
because we fail before.
Here it's not a matter of how much do I wait but when do I check
the pcode readiness (i.e. signalled by the GEN6_PCODE_READY bit
in the GEN6_PCODE_MAILBOX register).
During a normal run we are always sure that communicating with
the punit works, because we made it sure during the previous
transaction.
During probe there is no previous transaction and we start
communicating with the punit without making sure that it is
ready. And indeed some times it is not, so that we suppress the
probing on purpose instead of giving it another chance.
I admit that the commit message is not written properly and
rather misleading, but here it's not at all a matter of how much
do I wait.
Thanks, Rodrigo!
Andi
> >
> > Andi
> >
> > >
> > > /* write value to GEN6_PCODE_DATA register */
> > > intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val);
> > >
> > > intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 : 0);
> > >
> > > /* In this scenario, the value
> > >"DG1_PCODE_STATUS | GEN6_PCODE_READY"
> > >is written to the GEN6_PCODE_MAILBOX register,
> > >so that the Busy status of the GEN6_PCODE_MAILBOX register
> > >can be checked later.
> > >(When the value of the GEN6_PCODE_READY bit of the
> > > GEN6_PCODE_MAILBOX register changes to 0, the operation can
> > > be considered completed.) */
> > > intel_uncore_write_fw(uncore,
> > > GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
> > >
> > > /* In this scenario, verify that the BUSY status bit in the
> > >GEN6_PCODE_MAILBOX register turns off for up to 500us. */
> > > if (__intel_wait_for_register_fw(uncore,
> > >GEN6_PCODE_MAILBOX,
> > >GEN6_PCODE_READY, 0,
> > >fast_timeout_us,
> > >slow_timeout_ms,
> > >))
> > > return -ETIMEDOUT;
> > > /* If there is a failure here, it may be considered that the
> > >"DG1_PCODE_STATUS | GEN6_PCODE_READY" operation was not
> > >completed within 500us */
> > > ...
> > > }
> > >
> > > int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
> > > u32 reply_mask, u32 reply, int timeout_base_ms)
> > > {
> > > u32 status;
> > > int ret;
> > >
> > > mutex_lock(>i915->sb_lock);
> > >
> > > #define COND \
> > > skl_pcode_try_request(uncore,
Re: [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings
On Mon, Jan 30, 2023 at 10:46:16AM -0500, Rodrigo Vivi wrote:
> On Fri, Jan 27, 2023 at 02:43:11PM -0800, Matt Roper wrote:
> > Several post-TGL platforms have been brought up now, so we're well past
> > the point where we usually drop the workarounds that are only applicable
> > to internal/pre-production hardware.
> >
> > Production TGL hardware always has display stepping C0 or later and GT
> > stepping B0 or later (this is true for both the original TGL and the U/Y
> > subplatform).
> >
> > Bspec 44455
> > Signed-off-by: Matt Roper
> > ---
> > .../drm/i915/display/intel_display_power.c| 5 +--
> > drivers/gpu/drm/i915/display/intel_psr.c | 26 ---
> > .../drm/i915/display/skl_universal_plane.c| 2 +-
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 44 ++-
> > drivers/gpu/drm/i915/i915_driver.c| 1 +
> > drivers/gpu/drm/i915/i915_drv.h | 8
> > drivers/gpu/drm/i915/intel_pm.c | 4 --
> > 7 files changed, 7 insertions(+), 83 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 1a23ecd4623a..1dc31f0f5e0a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -1581,9 +1581,8 @@ static void tgl_bw_buddy_init(struct drm_i915_private
> > *dev_priv)
> >
> > if (IS_ALDERLAKE_S(dev_priv) ||
> > IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > - IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> > - /* Wa_1409767108:tgl,dg1,adl-s */
> > + IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>
> I believe we should go ahead and also remove the RKL ones like this.
> After all we have ADL and MTL and none needed this for instance.
Do we know for sure that A0 RKL wasn't productized? I can't find the
details about which stepping(s) were pre-prod-only in the bspec, so I've
left RKL and ADL workarounds alone for the time being.
Matt
>
> > + /* Wa_1409767108 */
> > table = wa_1409767108_buddy_page_masks;
> > else
> > table = tgl_buddy_page_masks;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 7d4a15a283a0..5dca58dd97a9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -591,12 +591,6 @@ static void hsw_activate_psr2(struct intel_dp
> > *intel_dp)
> > if (intel_dp->psr.psr2_sel_fetch_enabled) {
> > u32 tmp;
> >
> > - /* Wa_1408330847 */
> > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > -DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> > -DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> > -
> > tmp = intel_de_read(dev_priv,
> > PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
> > drm_WARN_ON(_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
> > } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> > @@ -765,13 +759,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct
> > intel_dp *intel_dp,
> > return false;
> > }
> >
> > - /* Wa_14010254185 Wa_14010103792 */
> > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > - drm_dbg_kms(_priv->drm,
> > - "PSR2 sel fetch not enabled, missing the
> > implementation of WAs\n");
> > - return false;
> > - }
> > -
> > return crtc_state->enable_psr2_sel_fetch = true;
> > }
> >
> > @@ -945,13 +932,6 @@ static bool intel_psr2_config_valid(struct intel_dp
> > *intel_dp,
> > }
> > }
> >
> > - /* Wa_2209313811 */
> > - if (!crtc_state->enable_psr2_sel_fetch &&
> > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > - drm_dbg_kms(_priv->drm, "PSR2 HW tracking is not supported
> > this Display stepping\n");
> > - goto unsupported;
> > - }
> > -
> > if (!psr2_granularity_check(intel_dp, crtc_state)) {
> > drm_dbg_kms(_priv->drm, "PSR2 not enabled, SU granularity
> > not compatible\n");
> > goto unsupported;
> > @@ -1360,12 +1340,6 @@ static void intel_psr_disable_locked(struct intel_dp
> > *intel_dp)
> > intel_psr_exit(intel_dp);
> > intel_psr_wait_exit_locked(intel_dp);
> >
> > - /* Wa_1408330847 */
> > - if (intel_dp->psr.psr2_sel_fetch_enabled &&
> > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > -DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> > -
> > /*
> > * Wa_16013835468
> > * Wa_14015648006
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >
Re: [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings
On Fri, Jan 27, 2023 at 02:43:11PM -0800, Matt Roper wrote:
> Several post-TGL platforms have been brought up now, so we're well past
> the point where we usually drop the workarounds that are only applicable
> to internal/pre-production hardware.
>
> Production TGL hardware always has display stepping C0 or later and GT
> stepping B0 or later (this is true for both the original TGL and the U/Y
> subplatform).
>
> Bspec 44455
> Signed-off-by: Matt Roper
> ---
> .../drm/i915/display/intel_display_power.c| 5 +--
> drivers/gpu/drm/i915/display/intel_psr.c | 26 ---
> .../drm/i915/display/skl_universal_plane.c| 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 44 ++-
> drivers/gpu/drm/i915/i915_driver.c| 1 +
> drivers/gpu/drm/i915/i915_drv.h | 8
> drivers/gpu/drm/i915/intel_pm.c | 4 --
> 7 files changed, 7 insertions(+), 83 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 1a23ecd4623a..1dc31f0f5e0a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1581,9 +1581,8 @@ static void tgl_bw_buddy_init(struct drm_i915_private
> *dev_priv)
>
> if (IS_ALDERLAKE_S(dev_priv) ||
> IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> - IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> - /* Wa_1409767108:tgl,dg1,adl-s */
> + IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
I believe we should go ahead and also remove the RKL ones like this.
After all we have ADL and MTL and none needed this for instance.
> + /* Wa_1409767108 */
> table = wa_1409767108_buddy_page_masks;
> else
> table = tgl_buddy_page_masks;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7d4a15a283a0..5dca58dd97a9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -591,12 +591,6 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> if (intel_dp->psr.psr2_sel_fetch_enabled) {
> u32 tmp;
>
> - /* Wa_1408330847 */
> - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> - DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> - DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> -
> tmp = intel_de_read(dev_priv,
> PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
> drm_WARN_ON(_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
> } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> @@ -765,13 +759,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct
> intel_dp *intel_dp,
> return false;
> }
>
> - /* Wa_14010254185 Wa_14010103792 */
> - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> - drm_dbg_kms(_priv->drm,
> - "PSR2 sel fetch not enabled, missing the
> implementation of WAs\n");
> - return false;
> - }
> -
> return crtc_state->enable_psr2_sel_fetch = true;
> }
>
> @@ -945,13 +932,6 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> }
> }
>
> - /* Wa_2209313811 */
> - if (!crtc_state->enable_psr2_sel_fetch &&
> - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> - drm_dbg_kms(_priv->drm, "PSR2 HW tracking is not supported
> this Display stepping\n");
> - goto unsupported;
> - }
> -
> if (!psr2_granularity_check(intel_dp, crtc_state)) {
> drm_dbg_kms(_priv->drm, "PSR2 not enabled, SU granularity
> not compatible\n");
> goto unsupported;
> @@ -1360,12 +1340,6 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
> intel_psr_exit(intel_dp);
> intel_psr_wait_exit_locked(intel_dp);
>
> - /* Wa_1408330847 */
> - if (intel_dp->psr.psr2_sel_fetch_enabled &&
> - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> - DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> -
> /*
>* Wa_16013835468
>* Wa_14015648006
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 9b172a1e90de..e956edb87398 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2180,7 +2180,7 @@ static bool gen12_plane_has_mc_ccs(struct
> drm_i915_private *i915,
> if (DISPLAY_VER(i915) < 12)
> return false;
>
> - /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
Re: [Intel-gfx] [PATCH] drm/i915/gt: Use sysfs_emit() and sysfs_emit_at()
On Mon, Jan 30, 2023 at 02:13:58PM +0100, Nirmoy Das wrote:
> Use sysfs_emit() and sysfs_emit_at() in show() callback
> as recommended by Documentation/filesystems/sysfs.rst
>
> Cc: Andi Shyti
> Signed-off-by: Nirmoy Das
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/sysfs_engines.c | 34 -
> 1 file changed, 16 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c
> b/drivers/gpu/drm/i915/gt/sysfs_engines.c
> index f2d9858d827c..323cead181b8 100644
> --- a/drivers/gpu/drm/i915/gt/sysfs_engines.c
> +++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c
> @@ -24,7 +24,7 @@ static struct intel_engine_cs *kobj_to_engine(struct
> kobject *kobj)
> static ssize_t
> name_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
> {
> - return sprintf(buf, "%s\n", kobj_to_engine(kobj)->name);
> + return sysfs_emit(buf, "%s\n", kobj_to_engine(kobj)->name);
> }
>
> static struct kobj_attribute name_attr =
> @@ -33,7 +33,7 @@ __ATTR(name, 0444, name_show, NULL);
> static ssize_t
> class_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
> {
> - return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_class);
> + return sysfs_emit(buf, "%d\n", kobj_to_engine(kobj)->uabi_class);
> }
>
> static struct kobj_attribute class_attr =
> @@ -42,7 +42,7 @@ __ATTR(class, 0444, class_show, NULL);
> static ssize_t
> inst_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
> {
> - return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_instance);
> + return sysfs_emit(buf, "%d\n", kobj_to_engine(kobj)->uabi_instance);
> }
>
> static struct kobj_attribute inst_attr =
> @@ -51,7 +51,7 @@ __ATTR(instance, 0444, inst_show, NULL);
> static ssize_t
> mmio_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
> {
> - return sprintf(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base);
> + return sysfs_emit(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base);
> }
>
> static struct kobj_attribute mmio_attr =
> @@ -107,11 +107,9 @@ __caps_show(struct intel_engine_cs *engine,
> for_each_set_bit(n, , show_unknown ? BITS_PER_LONG : count) {
> if (n >= count || !repr[n]) {
> if (GEM_WARN_ON(show_unknown))
> - len += snprintf(buf + len, PAGE_SIZE - len,
> - "[%x] ", n);
> + len += sysfs_emit_at(buf, len, "[%x] ", n);
> } else {
> - len += snprintf(buf + len, PAGE_SIZE - len,
> - "%s ", repr[n]);
> + len += sysfs_emit_at(buf, len, "%s ", repr[n]);
> }
> if (GEM_WARN_ON(len >= PAGE_SIZE))
> break;
> @@ -182,7 +180,7 @@ max_spin_show(struct kobject *kobj, struct kobj_attribute
> *attr, char *buf)
> {
> struct intel_engine_cs *engine = kobj_to_engine(kobj);
>
> - return sprintf(buf, "%lu\n", engine->props.max_busywait_duration_ns);
> + return sysfs_emit(buf, "%lu\n", engine->props.max_busywait_duration_ns);
> }
>
> static struct kobj_attribute max_spin_attr =
> @@ -193,7 +191,7 @@ max_spin_default(struct kobject *kobj, struct
> kobj_attribute *attr, char *buf)
> {
> struct intel_engine_cs *engine = kobj_to_engine(kobj);
>
> - return sprintf(buf, "%lu\n", engine->defaults.max_busywait_duration_ns);
> + return sysfs_emit(buf, "%lu\n",
> engine->defaults.max_busywait_duration_ns);
> }
>
> static struct kobj_attribute max_spin_def =
> @@ -236,7 +234,7 @@ timeslice_show(struct kobject *kobj, struct
> kobj_attribute *attr, char *buf)
> {
> struct intel_engine_cs *engine = kobj_to_engine(kobj);
>
> - return sprintf(buf, "%lu\n", engine->props.timeslice_duration_ms);
> + return sysfs_emit(buf, "%lu\n", engine->props.timeslice_duration_ms);
> }
>
> static struct kobj_attribute timeslice_duration_attr =
> @@ -247,7 +245,7 @@ timeslice_default(struct kobject *kobj, struct
> kobj_attribute *attr, char *buf)
> {
> struct intel_engine_cs *engine = kobj_to_engine(kobj);
>
> - return sprintf(buf, "%lu\n", engine->defaults.timeslice_duration_ms);
> + return sysfs_emit(buf, "%lu\n", engine->defaults.timeslice_duration_ms);
> }
>
> static struct kobj_attribute timeslice_duration_def =
> @@ -287,7 +285,7 @@ stop_show(struct kobject *kobj, struct kobj_attribute
> *attr, char *buf)
> {
> struct intel_engine_cs *engine = kobj_to_engine(kobj);
>
> - return sprintf(buf, "%lu\n", engine->props.stop_timeout_ms);
> + return sysfs_emit(buf, "%lu\n", engine->props.stop_timeout_ms);
> }
>
> static struct kobj_attribute stop_timeout_attr =
> @@ -298,7 +296,7 @@ stop_default(struct kobject *kobj, struct kobj_attribute
> *attr, char *buf)
> {
> struct intel_engine_cs *engine = kobj_to_engine(kobj);
>
> - return
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915/ttm: fix sparse warning
== Series Details ==
Series: series starting with [1/6] drm/i915/ttm: fix sparse warning
URL : https://patchwork.freedesktop.org/series/113482/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12665 -> Patchwork_113482v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_113482v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_113482v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113482v1/index.html
Participating hosts (25 -> 25)
--
Additional (1): fi-kbl-soraka
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_113482v1:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@execlists:
- fi-kbl-soraka: NOTRUN -> [ABORT][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113482v1/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html
Known issues
Here are the changes found in Patchwork_113482v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s0@smem:
- bat-dg1-5: [PASS][2] -> [FAIL][3] ([fdo#103375]) +7 similar
issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12665/bat-dg1-5/igt@gem_exec_suspend@basic...@smem.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113482v1/bat-dg1-5/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113482v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113482v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][6] ([i915#1886])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113482v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271]) +15 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113482v1/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- {bat-dg2-11}: [ABORT][8] -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12665/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113482v1/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@reset:
- {bat-rpls-2}: [ABORT][10] ([i915#4983]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12665/bat-rpls-2/igt@i915_selftest@l...@reset.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113482v1/bat-rpls-2/igt@i915_selftest@l...@reset.html
*
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-n3050: [FAIL][12] ([i915#6298]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12665/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113482v1/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
Build changes
-
* Linux: CI_DRM_12665 -> Patchwork_113482v1
CI-20190529: 20190529
CI_DRM_12665: 9fe703f7b1b32722945b20286223666c52241113 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7141:
Re: [Intel-gfx] [PATCH v4] drm/i915: implement async_flip mode per plane tracking
On Fri, Jan 27, 2023 at 04:30:02PM +0100, Andrzej Hajda wrote:
> Current implementation of async flip w/a relies on assumption that
> previous atomic commit contains valid information if async_flip is still
> enabled on the plane. It is incorrect. If previous commit did not modify
> the plane its state->uapi.async_flip can be false. As a result DMAR/PIPE
> errors can be observed:
> i915 :00:02.0: [drm] *ERROR* Fault errors on pipe A: 0x0080
> i915 :00:02.0: [drm] *ERROR* Fault errors on pipe A: 0x0080
> DMAR: DRHD: handling fault status reg 2
> DMAR: [DMA Read NO_PASID] Request device [00:02.0] fault addr 0x0 [fault
> reason 0x06] PTE Read access is not set
>
> v2: update async_flip_planes in more reliable places (Ville)
> v3: reset async_flip_planes and do_async_flip in more scenarios (Ville)
> v4: move all resets to plane loops (Ville)
>
> Signed-off-by: Andrzej Hajda
> ---
> Hi Ville,
>
> I am not sure about this change. I wonder if in case of
> for*plane loops code could be like:
>
> new_crtc_state->async_flip_planes &= ~BIT(plane->id);
> if (!new_crtc_state->async_flip_planes)
> new_crtc_state->do_async_flip = false;
>
> But let's see what CI says.
>
> Regards
> Andrzej
> ---
> drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 -
> drivers/gpu/drm/i915/display/intel_color.c | 3 +++
> drivers/gpu/drm/i915/display/intel_display.c | 9 ++---
> drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
> drivers/gpu/drm/i915/display/skl_watermark.c | 4
> 5 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 1409bcfb6fd3d9..3bd8f7eb75a60b 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -363,6 +363,7 @@ void intel_plane_set_invisible(struct intel_crtc_state
> *crtc_state,
> crtc_state->scaled_planes &= ~BIT(plane->id);
> crtc_state->nv12_planes &= ~BIT(plane->id);
> crtc_state->c8_planes &= ~BIT(plane->id);
> + crtc_state->async_flip_planes &= ~BIT(plane->id);
> crtc_state->data_rate[plane->id] = 0;
> crtc_state->data_rate_y[plane->id] = 0;
> crtc_state->rel_data_rate[plane->id] = 0;
> @@ -582,8 +583,10 @@ static int intel_plane_atomic_calc_changes(const struct
> intel_crtc_state *old_cr
>intel_plane_is_scaled(new_plane_state
> new_crtc_state->disable_lp_wm = true;
>
> - if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state))
> + if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
> new_crtc_state->do_async_flip = true;
> + new_crtc_state->async_flip_planes |= BIT(plane->id);
> + }
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 8d97c299e6577b..2ca7a016a9d9d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1500,12 +1500,15 @@ intel_color_add_affected_planes(struct
> intel_crtc_state *new_crtc_state)
> return PTR_ERR(plane_state);
>
> new_crtc_state->update_planes |= BIT(plane->id);
> + new_crtc_state->async_flip_planes = 0;
> + new_crtc_state->do_async_flip = false;
>
> /* plane control register changes blocked by CxSR */
> if (HAS_GMCH(i915))
> new_crtc_state->disable_cxsr = true;
> }
>
> +
> return 0;
> }
Thanks. Pushed now. I nuked that bogus extra newline while pushing.
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 717ca3d7890d34..fcd3f1c7af3291 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1252,7 +1252,8 @@ static void intel_crtc_async_flip_disable_wa(struct
> intel_atomic_state *state,
> intel_atomic_get_old_crtc_state(state, crtc);
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - u8 update_planes = new_crtc_state->update_planes;
> + u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
> +~new_crtc_state->async_flip_planes;
> const struct intel_plane_state *old_plane_state;
> struct intel_plane *plane;
> bool need_vbl_wait = false;
> @@ -1261,7 +1262,7 @@ static void intel_crtc_async_flip_disable_wa(struct
> intel_atomic_state *state,
> for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
> if (plane->need_async_flip_disable_wa &&
> plane->pipe == crtc->pipe &&
> - update_planes & BIT(plane->id)) {
> +
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Add selftests for TLB invalidation (rev6)
== Series Details ==
Series: drm/i915/gt: Add selftests for TLB invalidation (rev6)
URL : https://patchwork.freedesktop.org/series/112894/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12663_full -> Patchwork_112894v6_full
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v6/index.html
Participating hosts (10 -> 11)
--
Additional (1): shard-rkl0
New tests
-
New tests have been introduced between CI_DRM_12663_full and
Patchwork_112894v6_full:
### New IGT tests (1) ###
* igt@i915_selftest@live@gt_tlb:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_112894v6_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2846])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-glk9/igt@gem_exec_f...@basic-deadline.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v6/shard-glk5/igt@gem_exec_f...@basic-deadline.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-glk: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v6/shard-glk2/igt@gem_lmem_swapp...@parallel-multi.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
- shard-glk: NOTRUN -> [SKIP][4] ([fdo#109271]) +7 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v6/shard-glk2/igt@gem_render_c...@y-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#3886])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v6/shard-glk2/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][6] -> [FAIL][7] ([i915#79])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vbl...@bc-hdmi-a1-hdmi-a2.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v6/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vbl...@bc-hdmi-a1-hdmi-a2.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#658])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v6/shard-glk2/igt@kms_psr2...@overlay-plane-move-continuous-exceed-sf.html
Possible fixes
* igt@api_intel_bb@object-reloc-keep-cache:
- {shard-rkl}:[SKIP][9] ([i915#3281]) -> [PASS][10] +8 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-4/igt@api_intel...@object-reloc-keep-cache.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v6/shard-rkl-5/igt@api_intel...@object-reloc-keep-cache.html
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[FAIL][11] ([i915#7742]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v6/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-rkl}:[FAIL][13] ([i915#2842]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v6/shard-rkl-5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_pwrite@basic-self:
- {shard-rkl}:[SKIP][15] ([i915#3282]) -> [PASS][16] +5 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-6/igt@gem_pwr...@basic-self.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v6/shard-rkl-5/igt@gem_pwr...@basic-self.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [ABORT][17] ([i915#5566]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-glk8/igt@gen9_exec_pa...@allowed-single.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v6/shard-glk2/igt@gen9_exec_pa...@allowed-single.html
* igt@gen9_exec_parse@bb-start-out:
- {shard-rkl}:[SKIP][19] ([i915#2527]) -> [PASS][20] +1 similar
issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-6/igt@gen9_exec_pa...@bb-start-out.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112894v6/shard-rkl-5/igt@gen9_exec_pa...@bb-start-out.html
* igt@i915_hangman@gt-engine-error@bcs0:
- {shard-rkl}:[SKIP][21]
Re: [Intel-gfx] [PATCH v3] drm/i915/psr: Split sel fetch plane configuration into arm and noarm
On Mon, 2023-01-30 at 13:22 +, Coelho, Luciano wrote: > On Mon, 2023-01-30 at 10:06 +0200, Jouni Högander wrote: > > SEL_FETCH_CTL registers are armed immediately when plane is > > disabled. > > SEL_FETCH_* instances of plane configuration are used when doing > > selective update and normal plane register instances for full > > updates. > > Currently all SEL_FETCH_* registers are written as a part of noarm > > plane configuration. If noarm and arm plane configuration are not > > happening within same vblank we may end up having plane as a part > > of > > selective update before it's PLANE_SURF register is written. > > > > Fix this by splitting plane selective fetch configuration into arm > > and > > noarm versions and call them accordingly. Write SEL_FETCH_CTL in > > arm > > version. > > > > v3: > > - add arm suffix into intel_psr2_disable_plane_sel_fetch > > v2: > > - drop color_plane parameter from arm part > > - dev_priv -> i915 in arm part > > > > Cc: Ville Syrjälä > > Cc: José Roberto de Souza > > Cc: Mika Kahola > > Cc: Vinod Govindapillai > > Cc: Stanislav Lisovskiy > > Cc: Luca Coelho > > Signed-off-by: Jouni Högander > > Reviewed-by: José Roberto de Souza > > --- > > Reviewed-by: Luca Coelho Thank you, this is now merged. > > -- > Cheers, > Luca.
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/6] drm/i915/ttm: fix sparse warning
== Series Details == Series: series starting with [1/6] drm/i915/ttm: fix sparse warning URL : https://patchwork.freedesktop.org/series/113482/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:195:9: warning:
Re: [Intel-gfx] [PATCH] drm/i915/pcode: Wait 10 seconds for pcode to settle
On Mon, Jan 30, 2023 at 09:48:31AM +0100, Andi Shyti wrote:
> Hi GG,
>
> thanks for the deep analysis!
>
> > Hi Andi,
> > In the call flow invoked by intel_pcode_init(), I've added brief comments
> > where further clarification is needed in this scenario, and a description of
> > the suspicious scenario at the bottom.
> >
> > -
> > intel_pcode_init()
> > |
> > +-> skl_pcode_request(uncore, DG1_PCODE_STATUS,
> >DG1_UNCORE_GET_INIT_STATUS,
> >DG1_UNCORE_INIT_STATUS_COMPLETE,
> >DG1_UNCORE_INIT_STATUS_COMPLETE, 18);
> >|
> >+-> skl_pcode_try_request()
> > |
> > +-> *status = __snb_pcode_rw(uncore, mbox, , NULL,
> >500, 0, true);
> >
> > -
> > static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
> > u32 *val, u32 *val1,
> > int fast_timeout_us, int slow_timeout_ms,
> > bool is_read)
> > {
> > ...
> > /* Before writing a value to the GEN6_PCODE_DATA register,
> >check if the bit in the GEN6_PCODE_MAILBOX register indicates
> >BUSY. */
> > if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
> > return -EAGAIN;
>
> what if we fail here because the punit is still initializing and
> will be ready, say, in 10 seconds?
>
> GG, without going any further, we fail here! The -EAGAIN we
> receive from the test comes from this point. We don't fail with
> -ETIMEDOUT, but with -EAGAIN and the reason is because the punit
> is not ready to perform the very fist communication and we fail
> the probing.
>
> It doesn't mean, though, that there is anything wrong, we just
> need to wait a bit before "taking drastic decisions"!
>
> This patch is suggesting to wait up to 10s for the punit to be
> ready and eventually try to probe again... and, indeed, it works!
As GG, what I still don't understand is how this extra 10 seconds
wait helps... have you tried to simple add the 10 to the 180 and
make the code 190 sec instead?
>
> Andi
>
> >
> > /* write value to GEN6_PCODE_DATA register */
> > intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val);
> >
> > intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 : 0);
> >
> > /* In this scenario, the value
> >"DG1_PCODE_STATUS | GEN6_PCODE_READY"
> >is written to the GEN6_PCODE_MAILBOX register,
> >so that the Busy status of the GEN6_PCODE_MAILBOX register
> >can be checked later.
> >(When the value of the GEN6_PCODE_READY bit of the
> > GEN6_PCODE_MAILBOX register changes to 0, the operation can
> > be considered completed.) */
> > intel_uncore_write_fw(uncore,
> > GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
> >
> > /* In this scenario, verify that the BUSY status bit in the
> >GEN6_PCODE_MAILBOX register turns off for up to 500us. */
> > if (__intel_wait_for_register_fw(uncore,
> > GEN6_PCODE_MAILBOX,
> > GEN6_PCODE_READY, 0,
> > fast_timeout_us,
> > slow_timeout_ms,
> > ))
> > return -ETIMEDOUT;
> > /* If there is a failure here, it may be considered that the
> >"DG1_PCODE_STATUS | GEN6_PCODE_READY" operation was not
> >completed within 500us */
> > ...
> > }
> >
> > int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
> > u32 reply_mask, u32 reply, int timeout_base_ms)
> > {
> > u32 status;
> > int ret;
> >
> > mutex_lock(>i915->sb_lock);
> >
> > #define COND \
> > skl_pcode_try_request(uncore, mbox, request, reply_mask, reply, )
> >
> > /* the first trial for skl_pcode_try_request() can return
> >-EAGAIN or -ETIMEDOUT. And the code did not check the error
> >code here, so we don't know how far the __snb_pcode_rw()
> >function went. It is not known whether the pcode_mailbox
> >status was busy before writing the value to the
> >GEN6_PCODE_DATA register or after.*/
> > if (COND) {
> > ret = 0;
> > goto out;
> > }
> >
> > /* In this scenario, skl_pcode_try_request() is invoked every
> >10us for 180 seconds. When skl_pcode_try_request() returns
> >-EAGAIN and -ETIMEDOUT by _wait_for(),
> >-ETIMEDOUT is returned to a variable ret. */
> >
> > ret = _wait_for(COND, timeout_base_ms * 1000, 10, 10);
> >
> > if (!ret)
> >
[Intel-gfx] [PATCH 5.15 118/204] drm/i915: Allow switching away via vga-switcheroo if uninitialized
From: Thomas Zimmermann
[ Upstream commit a273e95721e96885971a05f1b34cb6d093904d9d ]
Always allow switching away via vga-switcheroo if the display is
uninitalized. Instead prevent switching to i915 if the device has
not been initialized.
This issue was introduced by commit 5df7bd130818 ("drm/i915: skip
display initialization when there is no display") protected, which
protects code paths from being executed on uninitialized devices.
In the case of vga-switcheroo, we want to allow a switch away from
i915's device. So run vga_switcheroo_process_delayed_switch() and
test in the switcheroo callbacks if the i915 device is available.
Fixes: 5df7bd130818 ("drm/i915: skip display initialization when there is no
display")
Signed-off-by: Thomas Zimmermann
Reviewed-by: Alex Deucher
Cc: Radhakrishna Sripada
Cc: Lucas De Marchi
Cc: José Roberto de Souza
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: "Ville Syrjälä"
Cc: Manasi Navare
Cc: Stanislav Lisovskiy
Cc: Imre Deak
Cc: "Jouni Högander"
Cc: Uma Shankar
Cc: Ankit Nautiyal
Cc: "Jason A. Donenfeld"
Cc: Matt Roper
Cc: Ramalingam C
Cc: Thomas Zimmermann
Cc: Andi Shyti
Cc: Andrzej Hajda
Cc: "José Roberto de Souza"
Cc: Julia Lawall
Cc: intel-gfx@lists.freedesktop.org
Cc: # v5.14+
Link:
https://patchwork.freedesktop.org/patch/msgid/20230116115425.13484-2-tzimmerm...@suse.de
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/i915/i915_drv.c| 3 +--
drivers/gpu/drm/i915/i915_switcheroo.c | 6 +-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 59fb4c710c8c..20b9e58de155 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -990,8 +990,7 @@ static void i915_driver_lastclose(struct drm_device *dev)
intel_fbdev_restore_mode(dev);
- if (HAS_DISPLAY(i915))
- vga_switcheroo_process_delayed_switch();
+ vga_switcheroo_process_delayed_switch();
}
static void i915_driver_postclose(struct drm_device *dev, struct drm_file
*file)
diff --git a/drivers/gpu/drm/i915/i915_switcheroo.c
b/drivers/gpu/drm/i915/i915_switcheroo.c
index de0e224b56ce..f1ce9f591efa 100644
--- a/drivers/gpu/drm/i915/i915_switcheroo.c
+++ b/drivers/gpu/drm/i915/i915_switcheroo.c
@@ -18,6 +18,10 @@ static void i915_switcheroo_set_state(struct pci_dev *pdev,
dev_err(>dev, "DRM not initialized, aborting switch.\n");
return;
}
+ if (!HAS_DISPLAY(i915)) {
+ dev_err(>dev, "Device state not initialized, aborting
switch.\n");
+ return;
+ }
if (state == VGA_SWITCHEROO_ON) {
drm_info(>drm, "switched on\n");
@@ -43,7 +47,7 @@ static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
* locking inversion with the driver load path. And the access here is
* completely racy anyway. So don't bother with locking for now.
*/
- return i915 && atomic_read(>drm.open_count) == 0;
+ return i915 && HAS_DISPLAY(i915) && atomic_read(>drm.open_count)
== 0;
}
static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
--
2.39.0
[Intel-gfx] ✓ Fi.CI.IGT: success for Add new CDCLK step for RPL-U (rev6)
== Series Details ==
Series: Add new CDCLK step for RPL-U (rev6)
URL : https://patchwork.freedesktop.org/series/111472/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12663_full -> Patchwork_111472v6_full
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/index.html
Participating hosts (10 -> 10)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_111472v6_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2846])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-glk9/igt@gem_exec_f...@basic-deadline.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-glk1/igt@gem_exec_f...@basic-deadline.html
Possible fixes
* igt@api_intel_bb@object-reloc-keep-cache:
- {shard-rkl}:[SKIP][3] ([i915#3281]) -> [PASS][4] +6 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-4/igt@api_intel...@object-reloc-keep-cache.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-5/igt@api_intel...@object-reloc-keep-cache.html
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[FAIL][5] ([i915#7742]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-3/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
* igt@fbdev@read:
- {shard-rkl}:[SKIP][7] ([i915#2582]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-4/igt@fb...@read.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@fb...@read.html
* igt@feature_discovery@psr2:
- {shard-rkl}:[SKIP][9] ([i915#658]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-2/igt@feature_discov...@psr2.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@feature_discov...@psr2.html
* igt@gem_eio@in-flight-suspend:
- {shard-rkl}:[FAIL][11] ([fdo#103375]) -> [PASS][12] +1 similar
issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-3/igt@gem_...@in-flight-suspend.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@gem_...@in-flight-suspend.html
* igt@gem_eio@suspend:
- {shard-rkl}:[FAIL][13] ([i915#7052]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-3/igt@gem_...@suspend.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-2/igt@gem_...@suspend.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-rkl}:[FAIL][15] ([i915#2842]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_suspend@basic-s3-devices@smem:
- {shard-rkl}:[FAIL][17] -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-3/igt@gem_exec_suspend@basic-s3-devi...@smem.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-2/igt@gem_exec_suspend@basic-s3-devi...@smem.html
* igt@gem_readwrite@write-bad-handle:
- {shard-rkl}:[SKIP][19] ([i915#3282]) -> [PASS][20] +1 similar
issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-4/igt@gem_readwr...@write-bad-handle.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-5/igt@gem_readwr...@write-bad-handle.html
* igt@gen9_exec_parse@bb-secure:
- {shard-rkl}:[SKIP][21] ([i915#2527]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-1/igt@gen9_exec_pa...@bb-secure.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-5/igt@gen9_exec_pa...@bb-secure.html
* igt@i915_pm_rpm@i2c:
- {shard-rkl}:[SKIP][23] ([fdo#109308]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-3/igt@i915_pm_...@i2c.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@i915_pm_...@i2c.html
* igt@i915_pm_rpm@modeset-lpsp:
- {shard-rkl}:[SKIP][25] ([i915#1397]) -> [PASS][26]
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-4/igt@i915_pm_...@modeset-lpsp.html
[26]:
[Intel-gfx] [PATCH] drm/i915: Implement workaround for CDCLK PLL disable/enable
It was reported that we might get a hung and loss of register access in
some cases when CDCLK PLL is disabled and then enabled, while squashing
is enabled.
As a workaround it was proposed by HW team that SW should disable squashing
when CDCLK PLL is being reenabled.
v2: - Added WA number comment(Rodrigo Vivi)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 7e16b655c833..8ae2b4c81f31 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1801,6 +1801,13 @@ static bool
cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
return true;
}
+static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
+{
+ return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv))
+ && dev_priv->display.cdclk.hw.vco > 0
+ && HAS_CDCLK_SQUASH(dev_priv));
+}
+
static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
@@ -1815,9 +1822,13 @@ static void _bxt_set_cdclk(struct drm_i915_private
*dev_priv,
!cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
if (dev_priv->display.cdclk.hw.vco != vco)
adlp_cdclk_pll_crawl(dev_priv, vco);
- } else if (DISPLAY_VER(dev_priv) >= 11)
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
+ /* wa_15010685871: dg2, mtl */
+ if (pll_enable_wa_needed(dev_priv))
+ dg2_cdclk_squash_program(dev_priv, 0);
+
icl_cdclk_pll_update(dev_priv, vco);
- else
+ } else
bxt_cdclk_pll_update(dev_priv, vco);
waveform = cdclk_squash_waveform(dev_priv, cdclk);
--
2.37.3
Re: [Intel-gfx] [PATCH v3] drm/i915/psr: Split sel fetch plane configuration into arm and noarm
On Mon, 2023-01-30 at 10:06 +0200, Jouni Högander wrote: > SEL_FETCH_CTL registers are armed immediately when plane is disabled. > SEL_FETCH_* instances of plane configuration are used when doing > selective update and normal plane register instances for full updates. > Currently all SEL_FETCH_* registers are written as a part of noarm > plane configuration. If noarm and arm plane configuration are not > happening within same vblank we may end up having plane as a part of > selective update before it's PLANE_SURF register is written. > > Fix this by splitting plane selective fetch configuration into arm and > noarm versions and call them accordingly. Write SEL_FETCH_CTL in arm > version. > > v3: > - add arm suffix into intel_psr2_disable_plane_sel_fetch > v2: > - drop color_plane parameter from arm part > - dev_priv -> i915 in arm part > > Cc: Ville Syrjälä > Cc: José Roberto de Souza > Cc: Mika Kahola > Cc: Vinod Govindapillai > Cc: Stanislav Lisovskiy > Cc: Luca Coelho > Signed-off-by: Jouni Högander > Reviewed-by: José Roberto de Souza > --- Reviewed-by: Luca Coelho -- Cheers, Luca.
[Intel-gfx] [PATCH] drm/i915/gt: Use sysfs_emit() and sysfs_emit_at()
Use sysfs_emit() and sysfs_emit_at() in show() callback
as recommended by Documentation/filesystems/sysfs.rst
Cc: Andi Shyti
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/sysfs_engines.c | 34 -
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c
b/drivers/gpu/drm/i915/gt/sysfs_engines.c
index f2d9858d827c..323cead181b8 100644
--- a/drivers/gpu/drm/i915/gt/sysfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c
@@ -24,7 +24,7 @@ static struct intel_engine_cs *kobj_to_engine(struct kobject
*kobj)
static ssize_t
name_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
{
- return sprintf(buf, "%s\n", kobj_to_engine(kobj)->name);
+ return sysfs_emit(buf, "%s\n", kobj_to_engine(kobj)->name);
}
static struct kobj_attribute name_attr =
@@ -33,7 +33,7 @@ __ATTR(name, 0444, name_show, NULL);
static ssize_t
class_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
{
- return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_class);
+ return sysfs_emit(buf, "%d\n", kobj_to_engine(kobj)->uabi_class);
}
static struct kobj_attribute class_attr =
@@ -42,7 +42,7 @@ __ATTR(class, 0444, class_show, NULL);
static ssize_t
inst_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
{
- return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_instance);
+ return sysfs_emit(buf, "%d\n", kobj_to_engine(kobj)->uabi_instance);
}
static struct kobj_attribute inst_attr =
@@ -51,7 +51,7 @@ __ATTR(instance, 0444, inst_show, NULL);
static ssize_t
mmio_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
{
- return sprintf(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base);
+ return sysfs_emit(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base);
}
static struct kobj_attribute mmio_attr =
@@ -107,11 +107,9 @@ __caps_show(struct intel_engine_cs *engine,
for_each_set_bit(n, , show_unknown ? BITS_PER_LONG : count) {
if (n >= count || !repr[n]) {
if (GEM_WARN_ON(show_unknown))
- len += snprintf(buf + len, PAGE_SIZE - len,
- "[%x] ", n);
+ len += sysfs_emit_at(buf, len, "[%x] ", n);
} else {
- len += snprintf(buf + len, PAGE_SIZE - len,
- "%s ", repr[n]);
+ len += sysfs_emit_at(buf, len, "%s ", repr[n]);
}
if (GEM_WARN_ON(len >= PAGE_SIZE))
break;
@@ -182,7 +180,7 @@ max_spin_show(struct kobject *kobj, struct kobj_attribute
*attr, char *buf)
{
struct intel_engine_cs *engine = kobj_to_engine(kobj);
- return sprintf(buf, "%lu\n", engine->props.max_busywait_duration_ns);
+ return sysfs_emit(buf, "%lu\n", engine->props.max_busywait_duration_ns);
}
static struct kobj_attribute max_spin_attr =
@@ -193,7 +191,7 @@ max_spin_default(struct kobject *kobj, struct
kobj_attribute *attr, char *buf)
{
struct intel_engine_cs *engine = kobj_to_engine(kobj);
- return sprintf(buf, "%lu\n", engine->defaults.max_busywait_duration_ns);
+ return sysfs_emit(buf, "%lu\n",
engine->defaults.max_busywait_duration_ns);
}
static struct kobj_attribute max_spin_def =
@@ -236,7 +234,7 @@ timeslice_show(struct kobject *kobj, struct kobj_attribute
*attr, char *buf)
{
struct intel_engine_cs *engine = kobj_to_engine(kobj);
- return sprintf(buf, "%lu\n", engine->props.timeslice_duration_ms);
+ return sysfs_emit(buf, "%lu\n", engine->props.timeslice_duration_ms);
}
static struct kobj_attribute timeslice_duration_attr =
@@ -247,7 +245,7 @@ timeslice_default(struct kobject *kobj, struct
kobj_attribute *attr, char *buf)
{
struct intel_engine_cs *engine = kobj_to_engine(kobj);
- return sprintf(buf, "%lu\n", engine->defaults.timeslice_duration_ms);
+ return sysfs_emit(buf, "%lu\n", engine->defaults.timeslice_duration_ms);
}
static struct kobj_attribute timeslice_duration_def =
@@ -287,7 +285,7 @@ stop_show(struct kobject *kobj, struct kobj_attribute
*attr, char *buf)
{
struct intel_engine_cs *engine = kobj_to_engine(kobj);
- return sprintf(buf, "%lu\n", engine->props.stop_timeout_ms);
+ return sysfs_emit(buf, "%lu\n", engine->props.stop_timeout_ms);
}
static struct kobj_attribute stop_timeout_attr =
@@ -298,7 +296,7 @@ stop_default(struct kobject *kobj, struct kobj_attribute
*attr, char *buf)
{
struct intel_engine_cs *engine = kobj_to_engine(kobj);
- return sprintf(buf, "%lu\n", engine->defaults.stop_timeout_ms);
+ return sysfs_emit(buf, "%lu\n", engine->defaults.stop_timeout_ms);
}
static struct kobj_attribute stop_timeout_def =
@@ -343,7 +341,7 @@ preempt_timeout_show(struct kobject *kobj, struct
Re: [Intel-gfx] [PATCH] drm/i915/display/fdi: use intel_de_rmw if possible
On Mon, 30 Jan 2023, Andrzej Hajda wrote:
> Hi all,
>
> Gently ping on merging this and all other intel_de_rmw patches.
> All patches reviewed.
> drm/i915/display/fdi: use intel_de_rmw if possible
> drm/i915/display/vlv: fix pixel overlap register update
> drm/i915/display/vlv: use intel_de_rmw if possible
> drm/i915/display/dsi: use intel_de_rmw if possible
Pushed the above, sorry for the delay.
The below are R-b by Rodrigo in [1], I'll let him deal with them.
Andrzej, looks like you now meet the criteria for commit access
[2]. Please check the documentation and apply for drm-intel commit
access, so you can start pushing your own patches.
Thanks,
Jani.
[1] https://patchwork.freedesktop.org/series/112438/
[2]
https://drm.pages.freedesktop.org/maintainer-tools/commit-access.html#drm-intel
> drm/i915/display/core: use intel_de_rmw if possible
> drm/i915/display/power: use intel_de_rmw if possible
> drm/i915/display/dpll: use intel_de_rmw if possible
> drm/i915/display/phys: use intel_de_rmw if possible
> drm/i915/display/pch: use intel_de_rmw if possible
> drm/i915/display/hdmi: use intel_de_rmw if possible
> drm/i915/display/panel: use intel_de_rmw if possible in panel related code
> drm/i915/display/interfaces: use intel_de_rmw if possible
> drm/i915/display/misc: use intel_de_rmw if possible
>
> Regards
> Andrzej
>
> On 15.12.2022 13:56, Andrzej Hajda wrote:
>> The helper makes the code more compact and readable.
>>
>> Signed-off-by: Andrzej Hajda
>> ---
>> drivers/gpu/drm/i915/display/intel_fdi.c | 148 +++
>> 1 file changed, 44 insertions(+), 104 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
>> b/drivers/gpu/drm/i915/display/intel_fdi.c
>> index 063f1da4f229cf..f62d9a9313498c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
>> @@ -439,19 +439,11 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
>> drm_err(_priv->drm, "FDI train 1 fail!\n");
>>
>> /* Train 2 */
>> -reg = FDI_TX_CTL(pipe);
>> -temp = intel_de_read(dev_priv, reg);
>> -temp &= ~FDI_LINK_TRAIN_NONE;
>> -temp |= FDI_LINK_TRAIN_PATTERN_2;
>> -intel_de_write(dev_priv, reg, temp);
>> -
>> -reg = FDI_RX_CTL(pipe);
>> -temp = intel_de_read(dev_priv, reg);
>> -temp &= ~FDI_LINK_TRAIN_NONE;
>> -temp |= FDI_LINK_TRAIN_PATTERN_2;
>> -intel_de_write(dev_priv, reg, temp);
>> -
>> -intel_de_posting_read(dev_priv, reg);
>> +intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
>> +intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
>> +intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
>> udelay(150);
>>
>> reg = FDI_RX_IIR(pipe);
>> @@ -538,13 +530,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
>> udelay(150);
>>
>> for (i = 0; i < 4; i++) {
>> -reg = FDI_TX_CTL(pipe);
>> -temp = intel_de_read(dev_priv, reg);
>> -temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
>> -temp |= snb_b_fdi_train_param[i];
>> -intel_de_write(dev_priv, reg, temp);
>> -
>> -intel_de_posting_read(dev_priv, reg);
>> +intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_VOL_EMP_MASK,
>> snb_b_fdi_train_param[i]);
>> +intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>> udelay(500);
>>
>> for (retry = 0; retry < 5; retry++) {
>> @@ -593,13 +581,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
>> udelay(150);
>>
>> for (i = 0; i < 4; i++) {
>> -reg = FDI_TX_CTL(pipe);
>> -temp = intel_de_read(dev_priv, reg);
>> -temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
>> -temp |= snb_b_fdi_train_param[i];
>> -intel_de_write(dev_priv, reg, temp);
>> -
>> -intel_de_posting_read(dev_priv, reg);
>> +intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_VOL_EMP_MASK,
>> snb_b_fdi_train_param[i]);
>> +intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>> udelay(500);
>>
>> for (retry = 0; retry < 5; retry++) {
>> @@ -719,19 +703,13 @@ static void ivb_manual_fdi_link_train(struct
>> intel_crtc *crtc,
>> }
>>
>> /* Train 2 */
>> -reg = FDI_TX_CTL(pipe);
>> -temp = intel_de_read(dev_priv, reg);
>> -temp &= ~FDI_LINK_TRAIN_NONE_IVB;
>> -temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
>> -intel_de_write(dev_priv, reg, temp);
>> -
>> -reg = FDI_RX_CTL(pipe);
>> -temp = intel_de_read(dev_priv, reg);
>> -temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
>> -temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
>> -
Re: [Intel-gfx] [PATCH] drm/i915/display/dsi: use intel_de_rmw if possible
On Tue, 20 Dec 2022, Jani Nikula wrote:
> On Mon, 19 Dec 2022, Andrzej Hajda wrote:
>> The helper makes the code more compact and readable.
>>
>> Signed-off-by: Andrzej Hajda
>
> Reviewed-by: Jani Nikula
And pushed to din, thanks for the patch.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/display/icl_dsi.c | 256 -
>> 1 file changed, 82 insertions(+), 174 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>> b/drivers/gpu/drm/i915/display/icl_dsi.c
>> index ae14c794c4bc09..b02ac9d2b1e4a2 100644
>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> @@ -207,7 +207,7 @@ void icl_dsi_frame_update(struct intel_crtc_state
>> *crtc_state)
>> {
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> -u32 tmp, mode_flags;
>> +u32 mode_flags;
>> enum port port;
>>
>> mode_flags = crtc_state->mode_flags;
>> @@ -224,9 +224,7 @@ void icl_dsi_frame_update(struct intel_crtc_state
>> *crtc_state)
>> else
>> return;
>>
>> -tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port));
>> -tmp |= DSI_FRAME_UPDATE_REQUEST;
>> -intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp);
>> +intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), 0,
>> DSI_FRAME_UPDATE_REQUEST);
>> }
>>
>> static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
>> @@ -234,7 +232,7 @@ static void dsi_program_swing_and_deemphasis(struct
>> intel_encoder *encoder)
>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>> enum phy phy;
>> -u32 tmp;
>> +u32 tmp, mask, val;
>> int lane;
>>
>> for_each_dsi_phy(phy, intel_dsi->phys) {
>> @@ -242,56 +240,35 @@ static void dsi_program_swing_and_deemphasis(struct
>> intel_encoder *encoder)
>> * Program voltage swing and pre-emphasis level values as per
>> * table in BSPEC under DDI buffer programing
>> */
>> +mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK;
>> +val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE |
>> + RTERM_SELECT(0x6);
>> tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
>> -tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
>> -tmp |= SCALING_MODE_SEL(0x2);
>> -tmp |= TAP2_DISABLE | TAP3_DISABLE;
>> -tmp |= RTERM_SELECT(0x6);
>> +tmp &= ~mask;
>> +tmp |= val;
>> intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
>> +intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), mask, val);
>>
>> -tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
>> -tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
>> -tmp |= SCALING_MODE_SEL(0x2);
>> -tmp |= TAP2_DISABLE | TAP3_DISABLE;
>> -tmp |= RTERM_SELECT(0x6);
>> -intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
>> -
>> +mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
>> + RCOMP_SCALAR_MASK;
>> +val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) |
>> + RCOMP_SCALAR(0x98);
>> tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
>> -tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
>> - RCOMP_SCALAR_MASK);
>> -tmp |= SWING_SEL_UPPER(0x2);
>> -tmp |= SWING_SEL_LOWER(0x2);
>> -tmp |= RCOMP_SCALAR(0x98);
>> +tmp &= ~mask;
>> +tmp |= val;
>> intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
>> +intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), mask, val);
>>
>> -tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy));
>> -tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
>> - RCOMP_SCALAR_MASK);
>> -tmp |= SWING_SEL_UPPER(0x2);
>> -tmp |= SWING_SEL_LOWER(0x2);
>> -tmp |= RCOMP_SCALAR(0x98);
>> -intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
>> -
>> -tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy));
>> -tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
>> - CURSOR_COEFF_MASK);
>> -tmp |= POST_CURSOR_1(0x0);
>> -tmp |= POST_CURSOR_2(0x0);
>> -tmp |= CURSOR_COEFF(0x3f);
>> -intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp);
>> -
>> -for (lane = 0; lane <= 3; lane++) {
>> -/* Bspec: must not use GRP register for write */
>> -tmp = intel_de_read(dev_priv,
>> -ICL_PORT_TX_DW4_LN(lane, phy));
>> -
Re: [Intel-gfx] [PATCH 1/2] drm/i915/display/vlv: fix pixel overlap register update
On Mon, 19 Dec 2022, Jani Nikula wrote:
> On Mon, 19 Dec 2022, Andrzej Hajda wrote:
>> To update properly bits in the register the mask should be used
>> to clear old value and then the result should be or-ed with new
>> value, for such updates there is separate helper intel_de_rmw.
>>
>> Signed-off-by: Andrzej Hajda
>
> Seems like the right thing to do.
>
> Reviewed-by: Jani Nikula
And pushed both to din, thanks for the patches.
BR,
Jani.
>
>
>> ---
>> drivers/gpu/drm/i915/display/vlv_dsi.c | 24 +---
>> 1 file changed, 9 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
>> b/drivers/gpu/drm/i915/display/vlv_dsi.c
>> index 662bdb656aa304..f5268997a3e172 100644
>> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
>> @@ -649,23 +649,17 @@ static void intel_dsi_port_enable(struct intel_encoder
>> *encoder,
>> enum port port;
>>
>> if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>> -u32 temp;
>> +u32 temp = intel_dsi->pixel_overlap;
>> +
>> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
>> -for_each_dsi_port(port, intel_dsi->ports) {
>> -temp = intel_de_read(dev_priv,
>> - MIPI_CTRL(port));
>> -temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
>> -intel_dsi->pixel_overlap <<
>> -BXT_PIXEL_OVERLAP_CNT_SHIFT;
>> -intel_de_write(dev_priv, MIPI_CTRL(port),
>> - temp);
>> -}
>> +for_each_dsi_port(port, intel_dsi->ports)
>> +intel_de_rmw(dev_priv, MIPI_CTRL(port),
>> + BXT_PIXEL_OVERLAP_CNT_MASK,
>> + temp <<
>> BXT_PIXEL_OVERLAP_CNT_SHIFT);
>> } else {
>> -temp = intel_de_read(dev_priv, VLV_CHICKEN_3);
>> -temp &= ~PIXEL_OVERLAP_CNT_MASK |
>> -intel_dsi->pixel_overlap <<
>> -PIXEL_OVERLAP_CNT_SHIFT;
>> -intel_de_write(dev_priv, VLV_CHICKEN_3, temp);
>> +intel_de_rmw(dev_priv, VLV_CHICKEN_3,
>> + PIXEL_OVERLAP_CNT_MASK,
>> + temp << PIXEL_OVERLAP_CNT_SHIFT);
>> }
>> }
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915/display/fdi: use intel_de_rmw if possible
On Mon, 30 Jan 2023, Andrzej Hajda wrote:
> Hi all,
>
> Gently ping on merging this and all other intel_de_rmw patches.
Pushed this one to din, thanks for the patch.
BR,
Jani.
> All patches reviewed.
> drm/i915/display/fdi: use intel_de_rmw if possible
> drm/i915/display/vlv: fix pixel overlap register update
> drm/i915/display/vlv: use intel_de_rmw if possible
> drm/i915/display/dsi: use intel_de_rmw if possible
> drm/i915/display/core: use intel_de_rmw if possible
> drm/i915/display/power: use intel_de_rmw if possible
> drm/i915/display/dpll: use intel_de_rmw if possible
> drm/i915/display/phys: use intel_de_rmw if possible
> drm/i915/display/pch: use intel_de_rmw if possible
> drm/i915/display/hdmi: use intel_de_rmw if possible
> drm/i915/display/panel: use intel_de_rmw if possible in panel related code
> drm/i915/display/interfaces: use intel_de_rmw if possible
> drm/i915/display/misc: use intel_de_rmw if possible
>
> Regards
> Andrzej
>
> On 15.12.2022 13:56, Andrzej Hajda wrote:
>> The helper makes the code more compact and readable.
>>
>> Signed-off-by: Andrzej Hajda
>> ---
>> drivers/gpu/drm/i915/display/intel_fdi.c | 148 +++
>> 1 file changed, 44 insertions(+), 104 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
>> b/drivers/gpu/drm/i915/display/intel_fdi.c
>> index 063f1da4f229cf..f62d9a9313498c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
>> @@ -439,19 +439,11 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
>> drm_err(_priv->drm, "FDI train 1 fail!\n");
>>
>> /* Train 2 */
>> -reg = FDI_TX_CTL(pipe);
>> -temp = intel_de_read(dev_priv, reg);
>> -temp &= ~FDI_LINK_TRAIN_NONE;
>> -temp |= FDI_LINK_TRAIN_PATTERN_2;
>> -intel_de_write(dev_priv, reg, temp);
>> -
>> -reg = FDI_RX_CTL(pipe);
>> -temp = intel_de_read(dev_priv, reg);
>> -temp &= ~FDI_LINK_TRAIN_NONE;
>> -temp |= FDI_LINK_TRAIN_PATTERN_2;
>> -intel_de_write(dev_priv, reg, temp);
>> -
>> -intel_de_posting_read(dev_priv, reg);
>> +intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
>> +intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
>> +intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
>> udelay(150);
>>
>> reg = FDI_RX_IIR(pipe);
>> @@ -538,13 +530,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
>> udelay(150);
>>
>> for (i = 0; i < 4; i++) {
>> -reg = FDI_TX_CTL(pipe);
>> -temp = intel_de_read(dev_priv, reg);
>> -temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
>> -temp |= snb_b_fdi_train_param[i];
>> -intel_de_write(dev_priv, reg, temp);
>> -
>> -intel_de_posting_read(dev_priv, reg);
>> +intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_VOL_EMP_MASK,
>> snb_b_fdi_train_param[i]);
>> +intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>> udelay(500);
>>
>> for (retry = 0; retry < 5; retry++) {
>> @@ -593,13 +581,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
>> udelay(150);
>>
>> for (i = 0; i < 4; i++) {
>> -reg = FDI_TX_CTL(pipe);
>> -temp = intel_de_read(dev_priv, reg);
>> -temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
>> -temp |= snb_b_fdi_train_param[i];
>> -intel_de_write(dev_priv, reg, temp);
>> -
>> -intel_de_posting_read(dev_priv, reg);
>> +intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_VOL_EMP_MASK,
>> snb_b_fdi_train_param[i]);
>> +intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>> udelay(500);
>>
>> for (retry = 0; retry < 5; retry++) {
>> @@ -719,19 +703,13 @@ static void ivb_manual_fdi_link_train(struct
>> intel_crtc *crtc,
>> }
>>
>> /* Train 2 */
>> -reg = FDI_TX_CTL(pipe);
>> -temp = intel_de_read(dev_priv, reg);
>> -temp &= ~FDI_LINK_TRAIN_NONE_IVB;
>> -temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
>> -intel_de_write(dev_priv, reg, temp);
>> -
>> -reg = FDI_RX_CTL(pipe);
>> -temp = intel_de_read(dev_priv, reg);
>> -temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
>> -temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
>> -intel_de_write(dev_priv, reg, temp);
>> -
>> -intel_de_posting_read(dev_priv, reg);
>> +intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_NONE_IVB,
>> + FDI_LINK_TRAIN_PATTERN_2_IVB);
>> +intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
>> + FDI_LINK_TRAIN_PATTERN_MASK_CPT,
>> +
