[Intel-gfx] ✓ Fi.CI.IGT: success for video/hdmi: minor fixes for *_infoframe_init functions (rev2)
== Series Details ==
Series: video/hdmi: minor fixes for *_infoframe_init functions (rev2)
URL : https://patchwork.freedesktop.org/series/116819/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13043_full -> Patchwork_116819v2_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116819v2_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_schedule@semaphore-codependency:
- {shard-dg1}:NOTRUN -> [DMESG-WARN][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/shard-dg1-15/igt@gem_exec_sched...@semaphore-codependency.html
Known issues
Here are the changes found in Patchwork_116819v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: NOTRUN -> [FAIL][2] ([i915#2842])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/shard-glk5/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][3] -> [FAIL][4] ([i915#2842]) +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-apl2/igt@gem_exec_fair@basic-none-s...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-glk: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/shard-glk5/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3886]) +1
similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/shard-glk5/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_color@ctm-green-to-red@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271]) +27 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/shard-snb1/igt@kms_color@ctm-green-to-...@pipe-a-hdmi-a-1.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [PASS][8] -> [FAIL][9] ([i915#2346])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-apl7/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/shard-apl1/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@plain-flip-ts-check@c-hdmi-a1:
- shard-glk: [PASS][10] -> [FAIL][11] ([i915#2122])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-glk6/igt@kms_flip@plain-flip-ts-ch...@c-hdmi-a1.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/shard-glk2/igt@kms_flip@plain-flip-ts-ch...@c-hdmi-a1.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render:
- shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271]) +3 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/shard-apl3/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271]) +42 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/shard-glk5/igt@kms_frontbuffer_track...@psr-rgb101010-draw-blt.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#658])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/shard-glk5/igt@kms_psr2...@primary-plane-update-sf-dmg-area.html
Possible fixes
* igt@gem_exec_endless@dispatch@vecs0:
- {shard-tglu}: [TIMEOUT][15] ([i915#3778]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-tglu-10/igt@gem_exec_endless@dispa...@vecs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/shard-tglu-6/igt@gem_exec_endless@dispa...@vecs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- {shard-rkl}:[FAIL][17] ([i915#2842]) -> [PASS][18] +1 similar
issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-rkl-1/igt@gem_exec_fair@basic-n...@vcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/shard-rkl-7/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@gem_
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: prevent potential div-by-zero
== Series Details ==
Series: drm/i915/dp: prevent potential div-by-zero
URL : https://patchwork.freedesktop.org/series/116821/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13043_full -> Patchwork_116821v1_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_116821v1_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_116821v1_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116821v1_full:
### IGT changes ###
Possible regressions
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-snb: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-snb1/igt@gem_pp...@blt-vs-render-ctxn.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/shard-snb1/igt@gem_pp...@blt-vs-render-ctxn.html
Known issues
Here are the changes found in Patchwork_116821v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: NOTRUN -> [FAIL][3] ([i915#2842])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/shard-glk1/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-glk: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +1
similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/shard-glk1/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#3886]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/shard-glk1/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1:
- shard-apl: [PASS][6] -> [FAIL][7] ([i915#79])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-apl7/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-dp1.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/shard-apl3/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-dp1.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render:
- shard-apl: NOTRUN -> [SKIP][8] ([fdo#109271]) +3 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/shard-apl7/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
- shard-glk: NOTRUN -> [SKIP][9] ([fdo#109271]) +42 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/shard-glk1/igt@kms_frontbuffer_track...@psr-rgb101010-draw-blt.html
*
igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-0-25@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271]) +21 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/shard-snb1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-0...@pipe-a-hdmi-a-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#658])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/shard-glk1/igt@kms_psr2...@primary-plane-update-sf-dmg-area.html
Possible fixes
* igt@gem_exec_endless@dispatch@vecs0:
- {shard-tglu}: [TIMEOUT][12] ([i915#3778]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-tglu-10/igt@gem_exec_endless@dispa...@vecs0.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/shard-tglu-9/igt@gem_exec_endless@dispa...@vecs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- {shard-rkl}:[FAIL][14] ([i915#2842]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-rkl-1/igt@gem_exec_fair@basic-n...@vcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/shard-rkl-7/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@gem_exec_schedule@smoketest@rcs0:
- shard-glk: [DMESG-WARN][16] ([i915#118]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-glk4/igt@gem_exec_schedule@smoket...@rcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/shard-glk2/igt@gem_exec_schedule@smoket...@rcs0.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [ABORT][18] ([i915#5566]) -> [PASS][19]
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add support for MTL GSC SW Proxy (rev2)
== Series Details ==
Series: drm/i915: Add support for MTL GSC SW Proxy (rev2)
URL : https://patchwork.freedesktop.org/series/115806/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13043 -> Patchwork_115806v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v2/index.html
Participating hosts (36 -> 37)
--
Additional (2): fi-kbl-soraka bat-mtlp-8
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_115806v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v2/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3
similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v2/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][3] ([i915#5334] / [i915#7872])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v2/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][4] ([i915#1886])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271]) +16 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v2/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html
Possible fixes
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-FAIL][6] ([i915#6367] / [i915#7996]) ->
[PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v2/bat-rpls-1/igt@i915_selftest@l...@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
[i915#8346]: https://gitlab.freedesktop.org/drm/intel/issues/8346
[i915#8368]: https://gitlab.freedesktop.org/drm/intel/issues/8368
[i915#8369]: https://gitlab.freedesktop.org/drm/intel/issues/8369
[i915#8379]: https://gitlab.freedesktop.org/drm/intel/issues/8379
Build changes
-
* Linux: CI_DRM_13043 -> Patchwork_115806v2
CI-20190529: 20190529
CI_DRM_13043: 2fa9c266135355c9993507d7c27cc6722956bfec @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_115806v2: 2fa9c266135355c9993507d7c27cc6722956bfec @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
36bf70621b26 drm/i915/gsc: add support for GSC proxy interrupt
91c855f53582 drm/i915/gsc: add initial support for GSC proxy
125dd7f8c476 mei: gsc_proxy: add gsc proxy driver
9664586015c7 drm/i915/mtl: Define GSC Proxy component interface
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v2/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Add support for MTL GSC SW Proxy (rev2)
== Series Details == Series: drm/i915: Add support for MTL GSC SW Proxy (rev2) URL : https://patchwork.freedesktop.org/series/115806/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add support for MTL GSC SW Proxy (rev2)
== Series Details == Series: drm/i915: Add support for MTL GSC SW Proxy (rev2) URL : https://patchwork.freedesktop.org/series/115806/ State : warning == Summary == Error: dim checkpatch failed fa63c332dc60 drm/i915/mtl: Define GSC Proxy component interface Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #30: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 62 lines checked 9a038b290687 mei: gsc_proxy: add gsc proxy driver Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #35: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 238 lines checked 5732d39863a4 drm/i915/gsc: add initial support for GSC proxy Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:48: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #48: new file mode 100644 -:53: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #53: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c:1: +#include "intel_gsc_proxy.h" -:55: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #55: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c:3: +// SPDX-License-Identifier: MIT -:192: WARNING:MEMORY_BARRIER: memory barrier without comment #192: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c:140: + wmb(); -:235: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #235: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c:183: + +} total: 0 errors, 4 warnings, 1 checks, 525 lines checked 684a9e53700f drm/i915/gsc: add support for GSC proxy interrupt
[Intel-gfx] [PATCH v2 4/4] drm/i915/gsc: add support for GSC proxy interrupt
The GSC notifies us of a proxy request via the HECI2 interrupt. The
interrupt must be enabled both in the HECI layer and in our usual gt irq
programming; for the latter, the interrupt is enabled via the same enable
register as the GSC CS, but it does have its own mask register. When the
interrupt is received, we also need to de-assert it in both layers.
The handling of the proxy request is deferred to the same worker that we
use for GSC load. New flags have been added to distinguish between the
init case and the proxy interrupt.
v2: Make sure not to set the reset bit when enabling/disabling the GSC
interrupts, fix defines (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 22 --
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 44 +++-
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c| 44
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h| 3 ++
6 files changed, 103 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index c0f3ff4746ad..95e59ed6651d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -16,6 +16,7 @@
#include "intel_uncore.h"
#include "intel_rps.h"
#include "pxp/intel_pxp_irq.h"
+#include "uc/intel_gsc_proxy.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -82,6 +83,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
if (instance == OTHER_GSC_INSTANCE)
return intel_gsc_irq_handler(gt, iir);
+ if (instance == OTHER_GSC_HECI_2_INSTANCE)
+ return intel_gsc_proxy_irq_handler(>->uc.gsc, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
@@ -101,6 +105,8 @@ static struct intel_gt *pick_gt(struct intel_gt *gt, u8
class, u8 instance)
case VIDEO_ENHANCEMENT_CLASS:
return media_gt;
case OTHER_CLASS:
+ if (instance == OTHER_GSC_HECI_2_INSTANCE)
+ return media_gt;
if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt,
GSC0))
return media_gt;
fallthrough;
@@ -257,6 +263,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
u32 irqs = GT_RENDER_USER_INTERRUPT;
u32 guc_mask = intel_uc_wants_guc(>->uc) ? GUC_INTR_GUC2HOST : 0;
u32 gsc_mask = 0;
+ u32 heci_mask = 0;
u32 dmask;
u32 smask;
@@ -268,10 +275,16 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
dmask = irqs << 16 | irqs;
smask = irqs << 16;
- if (HAS_ENGINE(gt, GSC0))
+ if (HAS_ENGINE(gt, GSC0)) {
+ /*
+* the heci2 interrupt is enabled via the same register as the
+* GSC interrupt, but it has its own mask register.
+*/
gsc_mask = irqs;
- else if (HAS_HECI_GSC(gt->i915))
+ heci_mask = GSC_IRQ_INTF(1); /* HECI2 IRQ for SW Proxy*/
+ } else if (HAS_HECI_GSC(gt->i915)) {
gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
+ }
BUILD_BUG_ON(irqs & 0x);
@@ -281,7 +294,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
if (CCS_MASK(gt))
intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
if (gsc_mask)
- intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
gsc_mask);
+ intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
gsc_mask | heci_mask);
/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
@@ -309,6 +322,9 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
if (gsc_mask)
intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK,
~gsc_mask);
+ if (heci_mask)
+ intel_uncore_write(uncore, GEN12_HECI2_RSVD_INTR_MASK,
+ ~REG_FIELD_PREP(ENGINE1_MASK, heci_mask));
if (guc_mask) {
/* the enable bit is common for both GTs but the masks are
separate */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index fd1f9cd35e9d..23884db9c097 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1587,6 +1587,7 @@
#define GEN11_GT_INTR_DW(x)_MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
+#define GEN12_HECI_2 (30)
#define GEN11_GUNIT (28)
#define GEN11_GUC(25)
#defin
[Intel-gfx] [PATCH v2 2/4] mei: gsc_proxy: add gsc proxy driver
From: Alexander Usyskin
Add GSC proxy driver. It to allows messaging between GSC component
on Intel graphics card and CSE device.
Cc: Alan Previn
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Acked-by: Greg Kroah-Hartman
---
v2: re-order included, drop reference to "on board" card in commit
message and comments.
drivers/misc/mei/Kconfig | 2 +-
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/gsc_proxy/Kconfig | 14 ++
drivers/misc/mei/gsc_proxy/Makefile| 7 +
drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c | 208 +
5 files changed, 231 insertions(+), 1 deletion(-)
create mode 100644 drivers/misc/mei/gsc_proxy/Kconfig
create mode 100644 drivers/misc/mei/gsc_proxy/Makefile
create mode 100644 drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index d21486d69df2..37db142de413 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -62,4 +62,4 @@ config INTEL_MEI_GSC
source "drivers/misc/mei/hdcp/Kconfig"
source "drivers/misc/mei/pxp/Kconfig"
-
+source "drivers/misc/mei/gsc_proxy/Kconfig"
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index fb740d754900..14aee253ae48 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -30,3 +30,4 @@ CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
+obj-$(CONFIG_INTEL_MEI_GSC_PROXY) += gsc_proxy/
diff --git a/drivers/misc/mei/gsc_proxy/Kconfig
b/drivers/misc/mei/gsc_proxy/Kconfig
new file mode 100644
index ..5f68d9f3d691
--- /dev/null
+++ b/drivers/misc/mei/gsc_proxy/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_GSC_PROXY
+ tristate "Intel GSC Proxy services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for GSC Proxy Services on Intel platforms.
+
+ MEI GSC proxy enables messaging between GSC service on
+ Intel graphics card and services on CSE (MEI) firmware
+ residing SoC or PCH.
+
diff --git a/drivers/misc/mei/gsc_proxy/Makefile
b/drivers/misc/mei/gsc_proxy/Makefile
new file mode 100644
index ..358847e9aaa9
--- /dev/null
+++ b/drivers/misc/mei/gsc_proxy/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
+#
+# Makefile - GSC Proxy client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_GSC_PROXY) += mei_gsc_proxy.o
diff --git a/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
b/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
new file mode 100644
index ..be52b113aea9
--- /dev/null
+++ b/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022-2023 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_GSC_PROXY Client Driver
+ *
+ * The mei_gsc_proxy driver acts as a translation layer between
+ * proxy user (I915) and ME FW by proxying messages to ME FW
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * mei_gsc_proxy_send - Sends a proxy message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buf: a message buffer to send
+ * @size: size of the message
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int mei_gsc_proxy_send(struct device *dev, const void *buf, size_t size)
+{
+ ssize_t ret;
+
+ if (!dev || !buf)
+ return -EINVAL;
+
+ ret = mei_cldev_send(to_mei_cl_device(dev), buf, size);
+ if (ret < 0)
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", ret);
+
+ return ret;
+}
+
+/**
+ * mei_gsc_proxy_recv - Receives a proxy message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buf: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes received on Success, <0 on Failure
+ */
+static int mei_gsc_proxy_recv(struct device *dev, void *buf, size_t size)
+{
+ ssize_t ret;
+
+ if (!dev || !buf)
+ return -EINVAL;
+
+ ret = mei_cldev_recv(to_mei_cl_device(dev), buf, size);
+ if (ret < 0)
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", ret);
+
+ return ret;
+}
+
+static const struct i915_gsc_proxy_component_ops mei_gsc_proxy_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_gsc_proxy_send,
+ .recv = mei_gsc_proxy_recv,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_gsc_proxy_component *comp_master =
mei_cldev_get_drvdata(cldev);
+
+ comp_master->ops = &mei_gsc_proxy_ops;
+ comp_master->mei_dev = dev;
+ retu
[Intel-gfx] [PATCH v2 3/4] drm/i915/gsc: add initial support for GSC proxy
The GSC uC needs to communicate with the CSME to perform certain
operations. Since the GSC can't perform this communication directly
on platforms where it is integrated in GT, i915 needs to transfer the
messages from GSC to CSME and back.
The proxy flow is as follow:
1 - i915 submits a request to GSC asking for the message to CSME
2 - GSC replies with the proxy header + payload for CSME
3 - i915 sends the reply from GSC as-is to CSME via the mei proxy
component
4 - CSME replies with the proxy header + payload for GSC
5 - i915 submits a request to GSC with the reply from CSME
6 - GSC replies either with a new header + payload (same as step 2,
so we restart from there) or with an end message.
After GSC load, i915 is expected to start the first proxy message chain,
while all subsequent ones will be triggered by the GSC via interrupt.
To communicate with the CSME, we use a dedicated mei component, which
means that we need to wait for it to bind before we can initialize the
proxies. This usually happens quite fast, but given that there is a
chance that we'll have to wait a few seconds the GSC work has been moved
to a dedicated WQ to not stall other processes.
v2: fix code style, includes and variable naming (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 384 ++
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h | 17 +
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 40 +-
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h | 14 +-
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 1 +
6 files changed, 452 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9af76e376ca9..f2ac803e35b4 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -194,6 +194,7 @@ i915-y += \
# general-purpose microcontroller (GuC) support
i915-y += \
gt/uc/intel_gsc_fw.o \
+ gt/uc/intel_gsc_proxy.o \
gt/uc/intel_gsc_uc.o \
gt/uc/intel_gsc_uc_heci_cmd_submit.o\
gt/uc/intel_guc.o \
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
new file mode 100644
index ..cc94f2e88658
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
@@ -0,0 +1,384 @@
+#include "intel_gsc_proxy.h"
+
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include
+
+#include "drm/i915_component.h"
+#include "drm/i915_gsc_proxy_mei_interface.h"
+
+#include "gt/intel_gt.h"
+#include "gt/intel_gt_print.h"
+#include "intel_gsc_uc.h"
+#include "intel_gsc_uc_heci_cmd_submit.h"
+#include "i915_drv.h"
+
+/*
+ * GSC proxy:
+ * The GSC uC needs to communicate with the CSME to perform certain operations.
+ * Since the GSC can't perform this communication directly on platforms where
it
+ * is integrated in GT, i915 needs to transfer the messages from GSC to CSME
+ * and back. i915 must manually start the proxy flow after the GSC is loaded to
+ * signal to GSC that we're ready to handle its messages and allow it to query
+ * its init data from CSME; GSC will then trigger an HECI2 interrupt if it
needs
+ * to send messages to CSME again.
+ * The proxy flow is as follow:
+ * 1 - i915 submits a request to GSC asking for the message to CSME
+ * 2 - GSC replies with the proxy header + payload for CSME
+ * 3 - i915 sends the reply from GSC as-is to CSME via the mei proxy component
+ * 4 - CSME replies with the proxy header + payload for GSC
+ * 5 - i915 submits a request to GSC with the reply from CSME
+ * 6 - GSC replies either with a new header + payload (same as step 2, so we
+ * restart from there) or with an end message.
+ */
+
+/*
+ * The component should load quite quickly in most cases, but it could take
+ * a bit. Using a very big timeout just to cover the worst case scenario
+ */
+#define GSC_PROXY_INIT_TIMEOUT_MS 2
+
+/* the protocol supports up to 32K in each direction */
+#define GSC_PROXY_BUFFER_SIZE SZ_32K
+#define GSC_PROXY_CHANNEL_SIZE (GSC_PROXY_BUFFER_SIZE * 2)
+#define GSC_PROXY_MAX_MSG_SIZE (GSC_PROXY_BUFFER_SIZE - sizeof(struct
intel_gsc_mtl_header))
+
+/* FW-defined proxy header */
+struct intel_gsc_proxy_header {
+ /*
+* hdr:
+* Bits 0-7: type of the proxy message (see enum intel_gsc_proxy_type)
+* Bits 8-15: rsvd
+* Bits 16-31: length in bytes of the payload following the proxy header
+*/
+ u32 hdr;
+#define GSC_PROXY_TYPE GENMASK(7, 0)
+#define GSC_PROXY_PAYLOAD_LENGTH GENMASK(31, 16)
+
+ u32 source; /* Source of the Proxy message */
+ u32 destination;/* Destination of the Proxy message */
+#define GSC_PROXY_ADDRESSING_
[Intel-gfx] [PATCH v2 1/4] drm/i915/mtl: Define GSC Proxy component interface
From: Alexander Usyskin
GSC Proxy component is used for communication between the
Intel graphics driver and MEI driver.
Cc: Alan Previn
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Acked-by: Greg Kroah-Hartman
---
v2: Improve documentation, remove unneeded includes
include/drm/i915_component.h | 3 +-
include/drm/i915_gsc_proxy_mei_interface.h | 53 ++
2 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 include/drm/i915_gsc_proxy_mei_interface.h
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index c1e2a43d2d1e..56a84ee1c64c 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -29,7 +29,8 @@
enum i915_component_type {
I915_COMPONENT_AUDIO = 1,
I915_COMPONENT_HDCP,
- I915_COMPONENT_PXP
+ I915_COMPONENT_PXP,
+ I915_COMPONENT_GSC_PROXY,
};
/* MAX_PORT is the number of port
diff --git a/include/drm/i915_gsc_proxy_mei_interface.h
b/include/drm/i915_gsc_proxy_mei_interface.h
new file mode 100644
index ..9462341d3ae1
--- /dev/null
+++ b/include/drm/i915_gsc_proxy_mei_interface.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright (c) 2022-2023 Intel Corporation
+ */
+
+#ifndef _I915_GSC_PROXY_MEI_INTERFACE_H_
+#define _I915_GSC_PROXY_MEI_INTERFACE_H_
+
+#include
+
+struct device;
+struct module;
+
+/**
+ * struct i915_gsc_proxy_component_ops - ops for GSC Proxy services.
+ * @owner: Module providing the ops
+ * @send: sends a proxy message from GSC FW to ME FW
+ * @recv: receives a proxy message for GSC FW from ME FW
+ */
+struct i915_gsc_proxy_component_ops {
+ struct module *owner;
+
+ /**
+* send - Sends a proxy message to ME FW.
+* @dev: device struct corresponding to the mei device
+* @buf: message buffer to send
+* @size: size of the message
+* Return: bytes sent on success, negative errno value on failure
+*/
+ int (*send)(struct device *dev, const void *buf, size_t size);
+
+ /**
+* recv - Receives a proxy message from ME FW.
+* @dev: device struct corresponding to the mei device
+* @buf: message buffer to contain the received message
+* @size: size of the buffer
+* Return: bytes received on success, negative errno value on failure
+*/
+ int (*recv)(struct device *dev, void *buf, size_t size);
+};
+
+/**
+ * struct i915_gsc_proxy_component - Used for communication between i915 and
+ * MEI drivers for GSC proxy services
+ * @mei_dev: device that provide the GSC proxy service.
+ * @ops: Ops implemented by GSC proxy driver, used by i915 driver.
+ */
+struct i915_gsc_proxy_component {
+ struct device *mei_dev;
+ const struct i915_gsc_proxy_component_ops *ops;
+};
+
+#endif /* _I915_GSC_PROXY_MEI_INTERFACE_H_ */
--
2.40.0
[Intel-gfx] [PATCH v2 0/4] drm/i915: Add support for MTL GSC SW Proxy
On platforms where the GSC is part of GT, it needs to communicate with CSME for some of its operations. However, there is no direct HW communication channel, so the i915 and mei drivers must carry the messages back and forth between the 2 units. The protocol is fully described in the i915 patch that adds the initial support, but it basically amounts to SW blindly moving messages back and forth until the GSC tells us to stop. Implementing this features requires a new mei component to handle the mei side of things. The patches for this have already been reviewed on the char-misc ML and we already have an ack from Greg to merge them via the drm tree [1]. v2: small fixes, better docs, code cleanup [1] https://lore.kernel.org/lkml/20230208142358.1401618-1-tomas.wink...@intel.com/t/ Cc: Alan Previn Cc: Suraj Kandpal Cc: Alexander Usyskin Cc: Greg Kroah-Hartman Alexander Usyskin (2): drm/i915/mtl: Define GSC Proxy component interface mei: gsc_proxy: add gsc proxy driver Daniele Ceraolo Spurio (2): drm/i915/gsc: add initial support for GSC proxy drm/i915/gsc: add support for GSC proxy interrupt drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_gt_irq.c| 22 +- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 + drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 424 ++ drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h | 18 + drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 66 ++- drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h | 17 +- .../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 1 + drivers/misc/mei/Kconfig | 2 +- drivers/misc/mei/Makefile | 1 + drivers/misc/mei/gsc_proxy/Kconfig| 14 + drivers/misc/mei/gsc_proxy/Makefile | 7 + drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c| 208 + include/drm/i915_component.h | 3 +- include/drm/i915_gsc_proxy_mei_interface.h| 53 +++ 15 files changed, 830 insertions(+), 10 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h create mode 100644 drivers/misc/mei/gsc_proxy/Kconfig create mode 100644 drivers/misc/mei/gsc_proxy/Makefile create mode 100644 drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c create mode 100644 include/drm/i915_gsc_proxy_mei_interface.h -- 2.40.0
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix memory leaks in i915 selftests (rev4)
== Series Details ==
Series: drm/i915: Fix memory leaks in i915 selftests (rev4)
URL : https://patchwork.freedesktop.org/series/116513/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13043_full -> Patchwork_116513v4_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_116513v4_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][1] -> [FAIL][2] ([i915#2842])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-apl2/igt@gem_exec_fair@basic-none-s...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2346])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-glk8/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/shard-glk5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2122])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-glk1/igt@kms_flip@2x-flip-vs-blocking-wf-vbl...@ab-hdmi-a1-hdmi-a2.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/shard-glk2/igt@kms_flip@2x-flip-vs-blocking-wf-vbl...@ab-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render:
- shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271]) +3 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/shard-apl3/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-shrfb-draw-render.html
*
igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271]) +23 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/shard-snb6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0...@pipe-a-vga-1.html
Possible fixes
* igt@gem_exec_endless@dispatch@vecs0:
- {shard-tglu}: [TIMEOUT][11] ([i915#3778]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-tglu-10/igt@gem_exec_endless@dispa...@vecs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/shard-tglu-5/igt@gem_exec_endless@dispa...@vecs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- {shard-rkl}:[FAIL][13] ([i915#2842]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-rkl-4/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/shard-rkl-6/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_exec_schedule@smoketest@rcs0:
- shard-glk: [DMESG-WARN][15] ([i915#118]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-glk4/igt@gem_exec_schedule@smoket...@rcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/shard-glk2/igt@gem_exec_schedule@smoket...@rcs0.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [ABORT][17] ([i915#5566]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-apl7/igt@gen9_exec_pa...@allowed-all.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/shard-apl3/igt@gen9_exec_pa...@allowed-all.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-tglu}: [FAIL][19] ([i915#3989] / [i915#454]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-tglu-5/igt@i915_pm...@dc6-dpms.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/shard-tglu-4/igt@i915_pm...@dc6-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- {shard-rkl}:[SKIP][21] ([i915#1937]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-rkl-6/igt@i915_pm_lpsp@kms-l...@kms-lpsp-hdmi-a.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/shard-rkl-7/igt@i915_pm_lpsp@kms-l...@kms-lpsp-hdmi-a.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-dg1}:
[Intel-gfx] [PATCH i-g-t 3/4] i915_pm_freq_api: Add some basic SLPC igt tests
Validate basic api for GT freq control. Also test
interaction with GT reset. We skip rps tests with
SLPC enabled, this will re-introduce some coverage.
SLPC selftests are already covering some other workload
related scenarios.
v2: Rename test (Rodrigo)
v3: Review comments (Ashutosh)
v4: Skip when SLPC is disabled. Check for enable_guc is
not sufficient as kernel config may have it but the
platform doesn't actually support it.
v5: Use the updated SLPC helper
Reviewed-by: Ashutosh Dixit
Cc: Rodrigo Vivi
Signed-off-by: Vinay Belgaumkar
---
tests/i915/i915_pm_freq_api.c | 152 ++
tests/meson.build | 1 +
2 files changed, 153 insertions(+)
create mode 100644 tests/i915/i915_pm_freq_api.c
diff --git a/tests/i915/i915_pm_freq_api.c b/tests/i915/i915_pm_freq_api.c
new file mode 100644
index ..f0f4e3f9
--- /dev/null
+++ b/tests/i915/i915_pm_freq_api.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "drmtest.h"
+#include "i915/gem.h"
+#include "igt_sysfs.h"
+#include "igt.h"
+
+IGT_TEST_DESCRIPTION("Test SLPC freq API");
+/*
+ * Too many intermediate components and steps before freq is adjusted
+ * Specially if workload is under execution, so let's wait 100 ms.
+ */
+#define ACT_FREQ_LATENCY_US 10
+
+static uint32_t get_freq(int dirfd, uint8_t id)
+{
+ uint32_t val;
+
+ igt_assert(igt_sysfs_rps_scanf(dirfd, id, "%u", &val) == 1);
+
+ return val;
+}
+
+static int set_freq(int dirfd, uint8_t id, uint32_t val)
+{
+ return igt_sysfs_rps_printf(dirfd, id, "%u", val);
+}
+
+static void test_freq_basic_api(int dirfd, int gt)
+{
+ uint32_t rpn, rp0, rpe;
+
+ /* Save frequencies */
+ rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ);
+ rp0 = get_freq(dirfd, RPS_RP0_FREQ_MHZ);
+ rpe = get_freq(dirfd, RPS_RP1_FREQ_MHZ);
+ igt_info("System min freq: %dMHz; max freq: %dMHz\n", rpn, rp0);
+
+ /*
+* Negative bound tests
+* RPn is the floor
+* RP0 is the ceiling
+*/
+ igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn - 1) < 0);
+ igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0 + 1) < 0);
+ igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn - 1) < 0);
+ igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0 + 1) < 0);
+
+ /* Assert min requests are respected from rp0 to rpn */
+ igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0) > 0);
+ igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rp0);
+ igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpe) > 0);
+ igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpe);
+ igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0);
+ igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpn);
+
+ /* Assert max requests are respected from rpn to rp0 */
+ igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0);
+ igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpn);
+ igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpe) > 0);
+ igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpe);
+ igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0) > 0);
+ igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rp0);
+
+}
+
+static void test_reset(int i915, int dirfd, int gt)
+{
+ uint32_t rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ);
+ int fd;
+
+ igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0);
+ igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0);
+ usleep(ACT_FREQ_LATENCY_US);
+ igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpn);
+
+ /* Manually trigger a GT reset */
+ fd = igt_debugfs_gt_open(i915, gt, "reset", O_WRONLY);
+ igt_require(fd >= 0);
+ igt_ignore_warn(write(fd, "1\n", 2));
+ close(fd);
+
+ igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpn);
+ igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpn);
+}
+
+igt_main
+{
+ int i915 = -1;
+ uint32_t *stash_min, *stash_max;
+
+ igt_fixture {
+ int num_gts, dirfd, gt;
+
+ i915 = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(i915);
+ /* i915_pm_rps already covers execlist path */
+ igt_skip_on_f(!i915_is_slpc_enabled(i915),
+ "This test is supported only with SLPC
enabled\n");
+
+ num_gts = igt_sysfs_get_num_gt(i915);
+ stash_min = (uint32_t*)malloc(sizeof(uint32_t) * num_gts);
+ stash_max = (uint32_t*)malloc(sizeof(uint32_t) * num_gts);
+
+ /* Save curr min and max across GTs */
+ for_each_sysfs_gt_dirfd(i915, dirfd, gt) {
+ stash_min[gt] = get_freq(dirfd, RPS_MIN_FREQ_MHZ);
+ stash_max[gt] = get_freq(dirfd, RPS_MAX_FREQ_MHZ);
+ }
+ }
+
+
[Intel-gfx] [PATCH i-g-t 4/4] HAX: tests/i915: Try out the SLPC IGT tests
Trying out for CI. Do not review. Signed-off-by: Vinay Belgaumkar --- tests/intel-ci/fast-feedback.testlist | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist index d9fcb62d..653668dd 100644 --- a/tests/intel-ci/fast-feedback.testlist +++ b/tests/intel-ci/fast-feedback.testlist @@ -139,6 +139,8 @@ igt@prime_self_import@basic-with_fd_dup igt@prime_self_import@basic-with_one_bo igt@prime_self_import@basic-with_one_bo_two_files igt@prime_self_import@basic-with_two_bos +igt@i915_pm_freq_api@freq-basic-api +igt@i915_pm_freq_api@freq-reset igt@prime_vgem@basic-fence-flip igt@prime_vgem@basic-fence-mmap igt@prime_vgem@basic-fence-read -- 2.38.1
[Intel-gfx] [PATCH i-g-t 2/4] lib: Make SLPC helper function per GT
Use default of 0 where GT id is not being used.
Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/8308
v2: Add a helper for GT 0 (Ashutosh)
v3: Additional review comments (Ashutosh)
Signed-off-by: Vinay Belgaumkar
Reviewed-by: Ashutosh Dixit
---
lib/igt_pm.c | 34 +-
lib/igt_pm.h | 3 ++-
2 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index 704acf7d..15a9cf81 100644
--- a/lib/igt_pm.c
+++ b/lib/igt_pm.c
@@ -1329,21 +1329,37 @@ void igt_pm_print_pci_card_runtime_status(void)
}
}
-bool i915_is_slpc_enabled(int fd)
+/**
+ * i915_is_slpc_enabled_gt:
+ * @drm_fd: DRM file descriptor
+ * @gt: GT id
+ * Check if SLPC is enabled on a GT
+ */
+bool i915_is_slpc_enabled_gt(int drm_fd, int gt)
{
- int debugfs_fd = igt_debugfs_dir(fd);
+ int debugfs_fd;
char buf[4096] = {};
- int len;
- igt_require(debugfs_fd != -1);
+ debugfs_fd = igt_debugfs_gt_open(drm_fd, gt, "uc/guc_slpc_info",
O_RDONLY);
+
+ /* if guc_slpc_info not present then return false */
+ igt_require(debugfs_fd >= 0);
+
+ read(debugfs_fd, buf, sizeof(buf)-1);
- len = igt_debugfs_simple_read(debugfs_fd, "gt/uc/guc_slpc_info", buf,
sizeof(buf));
close(debugfs_fd);
- if (len < 0)
- return false;
- else
- return strstr(buf, "SLPC state: running");
+ return strstr(buf, "SLPC state: running");
+}
+
+/**
+ * i915_is_slpc_enabled:
+ * @drm_fd: DRM file descriptor
+ * Check if SLPC is enabled for the device
+ */
+bool i915_is_slpc_enabled(int drm_fd)
+{
+ return i915_is_slpc_enabled_gt(drm_fd, 0);
}
int igt_pm_get_runtime_suspended_time(struct pci_device *pci_dev)
diff --git a/lib/igt_pm.h b/lib/igt_pm.h
index d0d6d673..448cf42d 100644
--- a/lib/igt_pm.h
+++ b/lib/igt_pm.h
@@ -84,7 +84,8 @@ void igt_pm_set_d3cold_allowed(struct igt_device_card *card,
const char *val);
void igt_pm_setup_pci_card_runtime_pm(struct pci_device *pci_dev);
void igt_pm_restore_pci_card_runtime_pm(void);
void igt_pm_print_pci_card_runtime_status(void);
-bool i915_is_slpc_enabled(int fd);
+bool i915_is_slpc_enabled_gt(int drm_fd, int gt);
+bool i915_is_slpc_enabled(int drm_fd);
int igt_pm_get_runtime_suspended_time(struct pci_device *pci_dev);
int igt_pm_get_runtime_usage(struct pci_device *pci_dev);
--
2.38.1
[Intel-gfx] [PATCH i-g-t 1/4] lib/debugfs: Add per GT debugfs helpers
These can be used to open per-gt debugfs files.
Reviewed-by: Ashutosh Dixit
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
---
lib/igt_debugfs.c | 60 +++
lib/igt_debugfs.h | 4
2 files changed, 64 insertions(+)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index 05889bbe..afde2da6 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -217,6 +217,37 @@ int igt_debugfs_dir(int device)
return open(path, O_RDONLY);
}
+/**
+ * igt_debugfs_gt_dir:
+ * @device: fd of the device
+ * @gt: GT instance number
+ *
+ * This opens the debugfs directory corresponding to device for use
+ * with igt_sysfs_get() and related functions.
+ *
+ * Returns:
+ * The directory fd, or -1 on failure.
+ */
+int igt_debugfs_gt_dir(int device, unsigned int gt)
+{
+ int debugfs_gt_dir_fd;
+ char path[PATH_MAX];
+ char gtpath[16];
+ int ret;
+
+ if (!igt_debugfs_path(device, path, sizeof(path)))
+ return -1;
+
+ ret = snprintf(gtpath, sizeof(gtpath), "/gt%u", gt);
+ igt_assert(ret < sizeof(gtpath));
+ strncat(path, gtpath, sizeof(path) - 1);
+
+ debugfs_gt_dir_fd = open(path, O_RDONLY);
+ igt_debug_on_f(debugfs_gt_dir_fd < 0, "path: %s\n", path);
+
+ return debugfs_gt_dir_fd;
+}
+
/**
* igt_debugfs_connector_dir:
* @device: fd of the device
@@ -313,6 +344,35 @@ bool igt_debugfs_exists(int device, const char *filename,
int mode)
return false;
}
+/**
+ * igt_debugfs_gt_open:
+ * @device: open i915 drm fd
+ * @gt: gt instance number
+ * @filename: name of the debugfs node to open
+ * @mode: mode bits as used by open()
+ *
+ * This opens a debugfs file as a Unix file descriptor. The filename should be
+ * relative to the drm device's root, i.e. without "drm/$minor".
+ *
+ * Returns:
+ * The Unix file descriptor for the debugfs file or -1 if that didn't work out.
+ */
+int
+igt_debugfs_gt_open(int device, unsigned int gt, const char *filename, int
mode)
+{
+ int dir, ret;
+
+ dir = igt_debugfs_gt_dir(device, gt);
+ if (dir < 0)
+ return dir;
+
+ ret = openat(dir, filename, mode);
+
+ close(dir);
+
+ return ret;
+}
+
/**
* igt_debugfs_simple_read:
* @dir: fd of the debugfs directory
diff --git a/lib/igt_debugfs.h b/lib/igt_debugfs.h
index 4824344a..3e6194ad 100644
--- a/lib/igt_debugfs.h
+++ b/lib/igt_debugfs.h
@@ -45,6 +45,10 @@ void __igt_debugfs_write(int fd, const char *filename, const
char *buf, int size
int igt_debugfs_simple_read(int dir, const char *filename, char *buf, int
size);
bool igt_debugfs_search(int fd, const char *filename, const char *substring);
+int igt_debugfs_gt_dir(int device, unsigned int gt);
+int igt_debugfs_gt_open(int device, unsigned int gt, const char *filename,
+ int mode);
+
/**
* igt_debugfs_read:
* @filename: name of the debugfs file
--
2.38.1
[Intel-gfx] [PATCH v7 i-g-t 0/4] tests/slpc: Add basic IGT test
Borrow some subtests from xe_guc_pc. Also add per GT SLPC debugfs helpers. v3: Review comments and add HAX patch v4: Modify the condition for skipping the test v5: Update the SLPC helper to per GT v6: Review comments (Ashutosh) v6: Review comments for SLPC debugfs patch (Ashutosh) v7: More comments (Ashutosh) Signed-off-by: Vinay Belgaumkar Reviewed-by: Ashutosh Dixit Vinay Belgaumkar (4): lib/debugfs: Add per GT debugfs helpers lib: Make SLPC helper function per GT i915_pm_freq_api: Add some basic SLPC igt tests HAX: tests/i915: Try out the SLPC IGT tests lib/igt_debugfs.c | 60 ++ lib/igt_debugfs.h | 4 + lib/igt_pm.c | 34 -- lib/igt_pm.h | 3 +- tests/i915/i915_pm_freq_api.c | 152 ++ tests/intel-ci/fast-feedback.testlist | 2 + tests/meson.build | 1 + 7 files changed, 246 insertions(+), 10 deletions(-) create mode 100644 tests/i915/i915_pm_freq_api.c -- 2.38.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/rc6: throw out set() wrapper
== Series Details ==
Series: drm/i915/rc6: throw out set() wrapper
URL : https://patchwork.freedesktop.org/series/116817/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13041_full -> Patchwork_116817v1_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_116817v1_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_116817v1_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116817v1_full:
### IGT changes ###
Possible regressions
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-snb: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-snb1/igt@gem_pp...@blt-vs-render-ctx0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-snb1/igt@gem_pp...@blt-vs-render-ctx0.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl3/igt@gem_pp...@flink-and-close-vma-leak.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-apl7/igt@gem_pp...@flink-and-close-vma-leak.html
Known issues
Here are the changes found in Patchwork_116817v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-glk8/igt@gem_huc_c...@huc-copy.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][8] -> [ABORT][9] ([i915#5566])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-glk9/igt@gen9_exec_pa...@allowed-all.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-glk3/igt@gen9_exec_pa...@allowed-all.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-1:
- shard-apl: [PASS][10] -> [FAIL][11] ([i915#2521])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl3/igt@kms_async_flips@alternate-sync-async-f...@pipe-b-dp-1.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-apl7/igt@kms_async_flips@alternate-sync-async-f...@pipe-b-dp-1.html
*
igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271]) +7 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-snb5/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scal...@pipe-b-vga-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#658])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-glk8/igt@kms_psr2...@primary-plane-update-sf-dmg-area-big-fb.html
* igt@v3d/v3d_submit_csd@bad-multisync-in-sync:
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271]) +11 similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-glk8/igt@v3d/v3d_submit_...@bad-multisync-in-sync.html
Possible fixes
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][15] ([i915#2846]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-glk1/igt@gem_exec_f...@basic-deadline.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-glk4/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none@bcs0:
- {shard-rkl}:[FAIL][17] ([i915#2842]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-rkl-3/igt@gem_exec_fair@basic-n...@bcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-rkl-4/igt@gem_exec_fair@basic-n...@bcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl: [FAIL][19] ([i915#2842]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-apl6/igt@gem_exec_fair@basic-pace-sh...
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Actually return an error if GuC version range check fails
== Series Details ==
Series: drm/i915/guc: Actually return an error if GuC version range check fails
URL : https://patchwork.freedesktop.org/series/116848/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13043 -> Patchwork_116848v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116848v1/index.html
Participating hosts (36 -> 37)
--
Additional (2): fi-kbl-soraka bat-mtlp-8
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116848v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@hugepages:
- {bat-mtlp-8}: NOTRUN -> [DMESG-FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116848v1/bat-mtlp-8/igt@i915_selftest@l...@hugepages.html
Known issues
Here are the changes found in Patchwork_116848v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116848v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116848v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][4] ([i915#1886])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116848v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@guc:
- bat-rpls-1: [PASS][5] -> [DMESG-WARN][6] ([i915#7852])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rpls-1/igt@i915_selftest@l...@guc.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116848v1/bat-rpls-1/igt@i915_selftest@l...@guc.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271]) +16 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116848v1/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7852]: https://gitlab.freedesktop.org/drm/intel/issues/7852
[i915#8346]: https://gitlab.freedesktop.org/drm/intel/issues/8346
[i915#8368]: https://gitlab.freedesktop.org/drm/intel/issues/8368
[i915#8369]: https://gitlab.freedesktop.org/drm/intel/issues/8369
[i915#8379]: https://gitlab.freedesktop.org/drm/intel/issues/8379
Build changes
-
* Linux: CI_DRM_13043 -> Patchwork_116848v1
CI-20190529: 20190529
CI_DRM_13043: 2fa9c266135355c9993507d7c27cc6722956bfec @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116848v1: 2fa9c266135355c9993507d7c27cc6722956bfec @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
c1e36e840768 drm/i915/guc: Actually return an error if GuC version range check
fails
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116848v1/index.html
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr: Restore HSW/BDW PSR1
== Series Details ==
Series: drm/i915/psr: Restore HSW/BDW PSR1
URL : https://patchwork.freedesktop.org/series/116814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13041_full -> Patchwork_116814v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_116814v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][1] -> [ABORT][2] ([i915#5566])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl1/igt@gen9_exec_pa...@allowed-single.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/shard-apl1/igt@gen9_exec_pa...@allowed-single.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][3] -> [INCOMPLETE][4] ([i915#7790])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-snb5/igt@i915_pm_...@reset.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/shard-snb5/igt@i915_pm_...@reset.html
* igt@kms_color@ctm-green-to-red@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271]) +28 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/shard-snb1/igt@kms_color@ctm-green-to-...@pipe-a-hdmi-a-1.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][6] -> [FAIL][7] ([i915#79]) +1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
Possible fixes
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [FAIL][8] ([i915#2842]) -> [PASS][9] +1 similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/shard-apl2/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [FAIL][10] ([i915#2842]) -> [PASS][11] +1 similar
issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-glk9/igt@gem_exec_fair@basic-p...@rcs0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/shard-glk7/igt@gem_exec_fair@basic-p...@rcs0.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- {shard-rkl}:[SKIP][12] ([i915#1397]) -> [PASS][13] +4 similar
issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-rkl-7/igt@i915_pm_...@dpms-non-lpsp.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/shard-rkl-6/igt@i915_pm_...@dpms-non-lpsp.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [DMESG-FAIL][14] ([i915#5334]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl3/igt@i915_selftest@live@gt_heartbeat.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/shard-apl7/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][16] ([i915#2346]) -> [PASS][17] +1 similar
issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/shard-apl3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@single-move@pipe-b:
- {shard-rkl}:[INCOMPLETE][18] ([i915#8011]) -> [PASS][19] +1
similar issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-rkl-7/igt@kms_cursor_legacy@single-m...@pipe-b.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/shard-rkl-6/igt@kms_cursor_legacy@single-m...@pipe-b.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [FAIL][20] ([i915#4767]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl1/igt@kms_fbcon_...@fbc-suspend.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/shard-apl1/igt@kms_fbcon_...@fbc-suspend.html
* igt@perf_pmu@idle@rcs0:
- {shard-dg1}:[FAIL][22] ([i915#4349]) -> [PASS][23]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-dg1-17/igt@perf_pmu@i...@rcs0.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/shard-dg1-18/igt@perf_pmu@i...@rcs0.html
- {shard-rkl}:[FAIL][24] ([i915#4349]) -> [PASS][25]
[24]:
https://intel-gfx-ci
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc: Actually return an error if GuC version range check fails
== Series Details == Series: drm/i915/guc: Actually return an error if GuC version range check fails URL : https://patchwork.freedesktop.org/series/116848/ State : warning == Summary == Error: dim checkpatch failed b0b33de7f7c8 drm/i915/guc: Actually return an error if GuC version range check fails -:19: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Link: with a URL to the report #19: Reported-by: Dan Carpenter Signed-off-by: John Harrison total: 0 errors, 1 warnings, 0 checks, 53 lines checked
Re: [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming
Hi Mika,
On Thu, Apr 20, 2023 at 03:40:38PM +0300, Mika Kahola wrote:
> C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
> HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
> 4 lane support for c20.
>
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Mika Kahola
> Signed-off-by: Bhanuprakash Modem
> Signed-off-by: Imre Deak
> Signed-off-by: Arun R Murthy
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 280 +++---
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 32 ++
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
> .../drm/i915/display/intel_display_types.h| 15 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 12 +-
> 5 files changed, 300 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 83180074b512..dd96bf5e179e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -273,6 +273,18 @@ static void intel_cx0_write(struct drm_i915_private
> *i915, enum port port,
> __intel_cx0_write(i915, port, lane, addr, data, committed);
> }
>
> +static void intel_c20_sram_write(struct drm_i915_private *i915, enum port
> port,
> + int lane, u16 addr, u16 data)
> +{
> + assert_dc_off(i915);
> +
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0);
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0);
> +
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_H, data >> 8, 0);
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1);
> +}
> +
> static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> int lane, u16 addr, u8 clear, u8 set, bool
> committed)
> {
> @@ -1415,6 +1427,207 @@ void intel_c10pll_dump_hw_state(struct
> drm_i915_private *i915,
> i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i
> + 3]);
> }
>
> +static bool intel_c20_use_mplla(u32 clock)
> +{
> + /* 10G and 20G rates use MPLLA */
> + if (clock == 312500 || clock == 625000)
> + return true;
> +
> + return false;
> +}
> +
> +static u8 intel_c20_get_dp_rate(u32 clock)
> +{
> + switch (clock) {
> + case 162000: /* 1.62 Gbps DP1.4 */
> + return 0;
> + case 27: /* 2.7 Gbps DP1.4 */
> + return 1;
> + case 54: /* 5.4 Gbps DP 1.4 */
> + return 2;
> + case 81: /* 8.1 Gbps DP1.4 */
> + return 3;
> + case 216000: /* 2.16 Gbps eDP */
> + return 4;
> + case 243000: /* 2.43 Gbps eDP */
> + return 5;
> + case 324000: /* 3.24 Gbps eDP */
> + return 6;
> + case 432000: /* 4.32 Gbps eDP */
> + return 7;
> + case 312500: /* 10 Gbps DP2.0 */
> + return 8;
> + case 421875: /* 13.5 Gbps DP2.0 */
> + return 9;
> + case 625000: /* 20 Gbps DP2.0*/
> + return 10;
Worth adding the rate for 6.75 Gbps eDP.
> + default:
> + MISSING_CASE(clock);
> + return 0;
> + }
> +}
> +
> +static u8 intel_c20_get_hdmi_rate(u32 clock)
> +{
> + switch (clock) {
> + case 25175:
> + case 27000:
> + case 74250:
> + case 148500:
> + case 594000:
> + return 0;
> + case 166670: /* 3 Gbps */
> + case 30: /* 6 Gbps */
> + case 70: /* 12 Gbps */
> + return 1;
> + case 40: /* 8 Gbps */
> + return 2;
> + case 60: /* 10 Gbps */
> + return 3;
> + default:
> + MISSING_CASE(clock);
> + return 0;
> + }
> +}
> +
> +static bool is_dp2(u32 clock)
> +{
> + /* DP2.0 clock rates */
> + if (clock == 312500 || clock == 421875 || clock == 625000)
> + return true;
> +
> + return false;
> +}
> +
> +static bool is_hdmi_frl(u32 clock)
> +{
> + switch (clock) {
> + case 166670: /* 3 Gbps */
> + case 30: /* 6 Gbps */
> + case 40: /* 8 Gbps */
> + case 60: /* 10 Gbps */
> + case 70: /* 12 Gbps */
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
> +{
> + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> +
> + /* banks should not be cleared for DPALT/USB4/TBT modes */
> + /* TODO: optimize re-calibration in legacy mode */
> + return intel_tc_port_in_legacy_mode(intel_dig_port);
> +}
> +
> +static void intel_c20_pll_program(struct drm_i915_private *i915,
> + const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + const struct intel_c20pll_state *pll_state =
> &crtc_stat
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v5,1/2] drm/i915/guc/slpc: Provide sysfs for efficient freq
== Series Details == Series: series starting with [v5,1/2] drm/i915/guc/slpc: Provide sysfs for efficient freq URL : https://patchwork.freedesktop.org/series/116840/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13043 -> Patchwork_116840v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_116840v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_116840v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116840v1/index.html Participating hosts (36 -> 37) -- Additional (2): fi-kbl-soraka bat-mtlp-8 Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_116840v1: ### IGT changes ### Possible regressions * igt@i915_pm_rps@basic-api: - bat-adlp-9: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-adlp-9/igt@i915_pm_...@basic-api.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116840v1/bat-adlp-9/igt@i915_pm_...@basic-api.html - bat-adlp-6: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-adlp-6/igt@i915_pm_...@basic-api.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116840v1/bat-adlp-6/igt@i915_pm_...@basic-api.html - bat-atsm-1: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-atsm-1/igt@i915_pm_...@basic-api.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116840v1/bat-atsm-1/igt@i915_pm_...@basic-api.html - bat-adlm-1: [PASS][7] -> [FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-adlm-1/igt@i915_pm_...@basic-api.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116840v1/bat-adlm-1/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@slpc: - bat-dg1-7: [PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-dg1-7/igt@i915_selftest@l...@slpc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116840v1/bat-dg1-7/igt@i915_selftest@l...@slpc.html - bat-adlm-1: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-adlm-1/igt@i915_selftest@l...@slpc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116840v1/bat-adlm-1/igt@i915_selftest@l...@slpc.html Known issues Here are the changes found in Patchwork_116840v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#2190]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116840v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116840v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_pm_rps@basic-api: - bat-dg1-7: [PASS][15] -> [FAIL][16] ([i915#8308]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-dg1-7/igt@i915_pm_...@basic-api.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116840v1/bat-dg1-7/igt@i915_pm_...@basic-api.html - bat-rplp-1: [PASS][17] -> [FAIL][18] ([i915#8308]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rplp-1/igt@i915_pm_...@basic-api.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116840v1/bat-rplp-1/igt@i915_pm_...@basic-api.html - bat-dg1-5: [PASS][19] -> [FAIL][20] ([i915#8308]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-dg1-5/igt@i915_pm_...@basic-api.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116840v1/bat-dg1-5/igt@i915_pm_...@basic-api.html - bat-dg2-9: [PASS][21] -> [FAIL][22] ([i915#8308]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-dg2-9/igt@i915_pm_...@basic-api.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116840v1/bat-dg2-9/igt@i915_pm_...@basic-api.html - bat-adln-1: [PASS][23] -> [FAIL][24] ([i915#8308]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-adln-1/igt@i915_pm_...@basic-api.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116840v1/bat-adln-1/igt@i915_pm_...@basic-api.html - bat-dg2-8: [PASS][25] -> [FAIL][26] ([i915#8308]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-dg2-8/igt@i915_pm_...@basic-api.h
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v5,1/2] drm/i915/guc/slpc: Provide sysfs for efficient freq
== Series Details == Series: series starting with [v5,1/2] drm/i915/guc/slpc: Provide sysfs for efficient freq URL : https://patchwork.freedesktop.org/series/116840/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] [PATCH] drm/i915/guc: Actually return an error if GuC version range check fails
From: John Harrison
Dan Carpenter pointed out that 'err' was not being set in the case
where the GuC firmware version range check fails. Fix that.
Note that while this is bug fix for a previous patch (see Fixes tag
below). It is an exceedingly low risk bug. The range check is
asserting that the GuC firmware version is within spec. So it should
not be possible to ever have a firmware file that fails this check. If
larger version numbers are required in the future, that would be a
backwards breaking spec change and thus require a major version bump,
in which case an old i915 driver would not load that new version anyway.
Fixes: 9bbba0667f37 ("drm/i915/guc: Use GuC submission API version number")
Reported-by: Dan Carpenter
Signed-off-by: John Harrison
Cc: John Harrison
Cc: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: Umesh Nerlige Ramappa
Cc: Rodrigo Vivi
Cc: Matthew Brost
Cc: Andi Shyti
Cc: Matthew Auld
Cc: Tvrtko Ursulin
Cc: Lucas De Marchi
Cc: Jani Nikula
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index a82a53dbbc86d..6b71b9febd74c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -636,9 +636,10 @@ static bool is_ver_8bit(struct intel_uc_fw_ver *ver)
return ver->major < 0xFF && ver->minor < 0xFF && ver->patch < 0xFF;
}
-static bool guc_check_version_range(struct intel_uc_fw *uc_fw)
+static int guc_check_version_range(struct intel_uc_fw *uc_fw)
{
struct intel_guc *guc = container_of(uc_fw, struct intel_guc, fw);
+ struct intel_gt *gt = __uc_fw_to_gt(uc_fw);
/*
* GuC version number components are defined as being 8-bits.
@@ -647,24 +648,24 @@ static bool guc_check_version_range(struct intel_uc_fw
*uc_fw)
*/
if (!is_ver_8bit(&uc_fw->file_selected.ver)) {
- gt_warn(__uc_fw_to_gt(uc_fw), "%s firmware: invalid file
version: 0x%02X:%02X:%02X\n",
+ gt_warn(gt, "%s firmware: invalid file version:
0x%02X:%02X:%02X\n",
intel_uc_fw_type_repr(uc_fw->type),
uc_fw->file_selected.ver.major,
uc_fw->file_selected.ver.minor,
uc_fw->file_selected.ver.patch);
- return false;
+ return -EINVAL;
}
if (!is_ver_8bit(&guc->submission_version)) {
- gt_warn(__uc_fw_to_gt(uc_fw), "%s firmware: invalid submit
version: 0x%02X:%02X:%02X\n",
+ gt_warn(gt, "%s firmware: invalid submit version:
0x%02X:%02X:%02X\n",
intel_uc_fw_type_repr(uc_fw->type),
guc->submission_version.major,
guc->submission_version.minor,
guc->submission_version.patch);
- return false;
+ return -EINVAL;
}
- return true;
+ return i915_inject_probe_error(gt->i915, -EINVAL);
}
static int check_fw_header(struct intel_gt *gt,
@@ -773,8 +774,11 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
if (err)
goto fail;
- if (uc_fw->type == INTEL_UC_FW_TYPE_GUC &&
!guc_check_version_range(uc_fw))
- goto fail;
+ if (uc_fw->type == INTEL_UC_FW_TYPE_GUC) {
+ err = guc_check_version_range(uc_fw);
+ if (err)
+ goto fail;
+ }
if (uc_fw->file_wanted.ver.major && uc_fw->file_selected.ver.major) {
/* Check the file's major version was as it claimed */
--
2.39.1
[Intel-gfx] ✓ Fi.CI.BAT: success for Use i915 instead of dev_priv (rev2)
== Series Details ==
Series: Use i915 instead of dev_priv (rev2)
URL : https://patchwork.freedesktop.org/series/116816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13043 -> Patchwork_116816v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/index.html
Participating hosts (36 -> 36)
--
Additional (1): bat-mtlp-8
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116816v2:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gem:
- {bat-mtlp-8}: NOTRUN -> [DMESG-FAIL][1] +2 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/bat-mtlp-8/igt@i915_selftest@l...@gem.html
Known issues
Here are the changes found in Patchwork_116816v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1:
- fi-rkl-11600: [PASS][2] -> [FAIL][3] ([fdo#103375])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/fi-rkl-11600/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-hdmi-a-1.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/fi-rkl-11600/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-hdmi-a-1.html
Possible fixes
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-FAIL][4] ([i915#6367] / [i915#7996]) ->
[PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/bat-rpls-1/igt@i915_selftest@l...@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
[i915#8346]: https://gitlab.freedesktop.org/drm/intel/issues/8346
[i915#8368]: https://gitlab.freedesktop.org/drm/intel/issues/8368
[i915#8369]: https://gitlab.freedesktop.org/drm/intel/issues/8369
[i915#8379]: https://gitlab.freedesktop.org/drm/intel/issues/8379
Build changes
-
* Linux: CI_DRM_13043 -> Patchwork_116816v2
CI-20190529: 20190529
CI_DRM_13043: 2fa9c266135355c9993507d7c27cc6722956bfec @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116816v2: 2fa9c266135355c9993507d7c27cc6722956bfec @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
2a9c436a72a6 drm/i915/i915_drv: Use i915 instead of dev_priv insied the
file_priv structure
4b2e8a9001db drm/i915/i915_drv: Use proper parameter naming in for_each_engine()
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/index.html
Re: [Intel-gfx] [PATCH v3 12/12] vfio/pci: Report dev_id in VFIO_DEVICE_GET_PCI_HOT_RESET_INFO
On Thu, Apr 20, 2023 at 08:08:39AM -0600, Alex Williamson wrote: > > Hide this device in the list looks fine to me. But the calling user should > > not do any new device open before finishing hot-reset. Otherwise, user may > > miss a device that needs to do pre/post reset. I think this requirement is > > acceptable. Is it? > > I think Kevin and Jason are leaning towards reporting the entire > dev-set. The INFO ioctl has always been a point-in-time reading, no > guarantees are made if the host or user configuration is changed. > Nothing changes in that respect. Yeah, I think your point about qemu community formus suggest we should err toward having qemu provide some fully detailed debug report. > > > Whereas dev-id < 0 > > > (== -1) is an affected device which prevents hot-reset, ex. an un-owned > > > device, device configured within a different iommufd_ctx, or device > > > opened outside of the vfio cdev API." Is that about right? Thanks, > > > > Do you mean to have separate err-code for the three possibilities? As > > the devid is generated by iommufd and it is u32. I'm not sure if we can > > have such err-code definition without reserving some ids in iommufd. > > Yes, if we're going to report the full dev-set, I think we need at > least two unique error codes or else the user has no way to determine > the subset of invalid dev-ids which block the reset. If you think this is important to report we should report 0 and -1, and adjust the iommufd xarray allocator to reserve -1 It depends what you want to show for the debugging. eg if we have debugging where qemu dumps this table: BDF In VM iommu_group Has VFIO driver Has Kernel Driver By also doing various sysfs probes based on the BDF, then the admin action to remedy the situation is: Make "Has VFIO driver = y" or "Has Kernel Driver = n" for every row in the table to make the reset work. And we don't need the distinction. Adding the 0/-1 lets you make a useful table without doing any sysfs work. > I think Jason is proposing the set of valid dev-ids are >0, a dev-id > of zero indicates some form of non-blocking, while <0 (or maybe > specifically -1) indicates a blocking device. Yes, 0 and -1 would be fine with those definitions. The only use of the data is to add a 'blocking use of reset' colum to the table above.. Thanks, Jason
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/display & drm/i915: more struct drm_edid conversions
== Series Details ==
Series: drm/display & drm/i915: more struct drm_edid conversions
URL : https://patchwork.freedesktop.org/series/116813/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13041_full -> Patchwork_116813v1_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_116813v1_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_116813v1_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116813v1_full:
### IGT changes ###
Possible regressions
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] +9 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-blt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/shard-apl1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-blt.html
Known issues
Here are the changes found in Patchwork_116813v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_barrier_race@remote-request@rcs0:
- shard-apl: [PASS][3] -> [ABORT][4] ([i915#8211] / [i915#8234])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl3/igt@gem_barrier_race@remote-requ...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/shard-apl4/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@i915_module_load@reload:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180] / [i915#62]
/ [i915#7634])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl4/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/shard-apl1/igt@i915_module_l...@reload.html
* igt@kms_cursor_crc@cursor-onscreen-128x128@pipe-c-dp-1:
- shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180] / [i915#62])
+32 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl4/igt@kms_cursor_crc@cursor-onscreen-128x...@pipe-c-dp-1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/shard-apl1/igt@kms_cursor_crc@cursor-onscreen-128x...@pipe-c-dp-1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/shard-apl1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl4/igt@kms_frontbuffer_track...@fbc-rgb101010-draw-mmap-cpu.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/shard-apl1/igt@kms_frontbuffer_track...@fbc-rgb101010-draw-mmap-cpu.html
*
igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271]) +27 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/shard-snb1/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0...@pipe-b-hdmi-a-1.html
Possible fixes
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[FAIL][14] ([i915#7742]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/shard-rkl-3/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][16] ([i915#2846]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-glk1/igt@gem_exec_f...@basic-deadline.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/shard-glk1/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none@bcs0:
- {shard-rkl}:[FAIL][18] ([i915#2842]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-rkl-3/igt@gem_exec_fair@basic-n...@bcs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/shard-rkl-4/igt@gem_exec_fair@basic-n...@bcs0.html
* igt@gem_exe
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Use i915 instead of dev_priv (rev2)
== Series Details == Series: Use i915 instead of dev_priv (rev2) URL : https://patchwork.freedesktop.org/series/116816/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use i915 instead of dev_priv (rev2)
== Series Details ==
Series: Use i915 instead of dev_priv (rev2)
URL : https://patchwork.freedesktop.org/series/116816/
State : warning
== Summary ==
Error: dim checkpatch failed
a9e68a5b12c6 drm/i915/i915_drv: Use proper parameter naming in for_each_engine()
-:24: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#24: FILE: drivers/gpu/drm/i915/i915_drv.h:384:
+#define for_each_engine(engine__, gt__, id__) \
for ((id__) = 0; \
(id__) < I915_NUM_ENGINES; \
(id__)++) \
+ for_each_if ((engine__) = (gt__)->engine[(id__)])
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id__' - possible
side-effects?
#24: FILE: drivers/gpu/drm/i915/i915_drv.h:384:
+#define for_each_engine(engine__, gt__, id__) \
for ((id__) = 0; \
(id__) < I915_NUM_ENGINES; \
(id__)++) \
+ for_each_if ((engine__) = (gt__)->engine[(id__)])
-:29: WARNING:SPACING: space prohibited between function name and open
parenthesis '('
#29: FILE: drivers/gpu/drm/i915/i915_drv.h:388:
+ for_each_if ((engine__) = (gt__)->engine[(id__)])
total: 1 errors, 1 warnings, 1 checks, 13 lines checked
efd966c35aaa drm/i915/i915_drv: Use i915 instead of dev_priv insied the
file_priv structure
-:141: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#141: FILE: drivers/gpu/drm/i915/i915_drv.h:534:
+#define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915))
-:145: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#145: FILE: drivers/gpu/drm/i915/i915_drv.h:538:
+#define IS_IRONLAKE_M(i915) \
+ (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
-:149: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#149: FILE: drivers/gpu/drm/i915/i915_drv.h:542:
+#define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \
+INTEL_INFO(i915)->gt == 1)
-:162: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#162: FILE: drivers/gpu/drm/i915/i915_drv.h:555:
+#define IS_JSL_EHL(i915) (IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
+ IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
-:192: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#192: FILE: drivers/gpu/drm/i915/i915_drv.h:585:
+#define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \
+ (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
-:198: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#198: FILE: drivers/gpu/drm/i915/i915_drv.h:591:
+#define IS_BDW_GT3(i915) (IS_BROADWELL(i915) && \
+INTEL_INFO(i915)->gt == 3)
-:202: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#202: FILE: drivers/gpu/drm/i915/i915_drv.h:595:
+#define IS_HSW_GT3(i915) (IS_HASWELL(i915) && \
+INTEL_INFO(i915)->gt == 3)
-:204: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#204: FILE: drivers/gpu/drm/i915/i915_drv.h:597:
+#define IS_HSW_GT1(i915) (IS_HASWELL(i915) && \
+INTEL_INFO(i915)->gt == 1)
-:258: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#258: FILE: drivers/gpu/drm/i915/i915_drv.h:610:
+#define IS_SKL_GT2(i915) (IS_SKYLAKE(i915) && \
+INTEL_INFO(i915)->gt == 2)
-:260: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#260: FILE: drivers/gpu/drm/i915/i915_drv.h:612:
+#define IS_SKL_GT3(i915) (IS_SKYLAKE(i915) && \
+INTEL_INFO(i915)->gt == 3)
-:262: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#262: FILE: drivers/gpu/drm/i915/i915_drv.h:614:
+#define IS_SKL_GT4(i915) (IS_SKYLAKE(i915) && \
+INTEL_INFO(i915)->gt == 4)
-:264: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#264: FILE: drivers/gpu/drm/i915/i915_drv.h:616:
+#define IS_KBL_GT2(i915) (IS_KABYLAKE(i915) && \
+INTEL_INFO(i915)->gt == 2)
-:266: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#266: FILE: drivers/gpu/drm/i915/i915_drv.h:618:
+#define IS_KBL_GT3(i915) (IS_KABYLAKE(i915) && \
+INTEL_INFO(i915)->gt == 3)
-:272: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#272: FILE: drivers/gpu/drm/i915/i915_drv.h:624:
+#define IS_CFL_GT2(i915) (IS_COFFEELAKE(i915) && \
+INTEL_INFO(i915)->gt == 2)
-:274: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#274: FILE: drivers/gpu/drm/i915/i915_drv.h:626:
+#define IS_CFL_GT3(i915) (IS_COFFEELAKE(i915) && \
+INTEL_INFO
[Intel-gfx] ✓ Fi.CI.BAT: success for Define MOCS and PAT tables for MTL
== Series Details ==
Series: Define MOCS and PAT tables for MTL
URL : https://patchwork.freedesktop.org/series/116837/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13043 -> Patchwork_116837v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116837v1/index.html
Participating hosts (36 -> 36)
--
Additional (1): bat-mtlp-8
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116837v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@load:
- {bat-mtlp-8}: NOTRUN -> [ABORT][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116837v1/bat-mtlp-8/igt@i915_module_l...@load.html
Known issues
Here are the changes found in Patchwork_116837v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][2] -> [ABORT][3] ([i915#7911] / [i915#7913])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116837v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@slpc:
- bat-rplp-1: [PASS][4] -> [DMESG-FAIL][5] ([i915#6367] /
[i915#7913])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rplp-1/igt@i915_selftest@l...@slpc.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116837v1/bat-rplp-1/igt@i915_selftest@l...@slpc.html
* igt@i915_selftest@live@workarounds:
- bat-dg1-7: [PASS][6] -> [ABORT][7] ([i915#4983])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-dg1-7/igt@i915_selftest@l...@workarounds.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116837v1/bat-dg1-7/igt@i915_selftest@l...@workarounds.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-1: NOTRUN -> [SKIP][8] ([i915#7828])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116837v1/bat-rpls-1/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-1: NOTRUN -> [SKIP][9] ([i915#1845])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116837v1/bat-rpls-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-1: [ABORT][10] ([i915#6687] / [i915#7978]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116837v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-FAIL][12] ([i915#6367] / [i915#7996]) ->
[PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116837v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
Build changes
-
* Linux: CI_DRM_13043 -> Patchwork_116837v1
CI-20190529: 20190529
CI_DRM_13043: 2fa9c266135355c9993507d7c27cc6722956bfec @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116837v1: 2fa9c266135355c9993507d7c27cc6722956bfec @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
a8d1e27ce905 drm/i915/mtl: fix mocs selftest
145699c605eb drm/i915/mtl: Define MOCS and PAT tables for MTL
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116837v1/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Define MOCS and PAT tables for MTL
== Series Details == Series: Define MOCS and PAT tables for MTL URL : https://patchwork.freedesktop.org/series/116837/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Define MOCS and PAT tables for MTL (rev10)
== Series Details ==
Series: drm/i915/mtl: Define MOCS and PAT tables for MTL (rev10)
URL : https://patchwork.freedesktop.org/series/115980/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13043 -> Patchwork_115980v10
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115980v10/index.html
Participating hosts (36 -> 37)
--
Additional (2): fi-kbl-soraka bat-mtlp-8
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_115980v10 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115980v10/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3
similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115980v10/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@execlists:
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][3] ([i915#7156] / [i915#7913])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115980v10/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html
- fi-bsw-nick:[PASS][4] -> [ABORT][5] ([i915#7911] / [i915#7913])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115980v10/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][6] -> [DMESG-FAIL][7] ([i915#5334])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115980v10/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][8] ([i915#1886])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115980v10/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@mman:
- bat-rpls-1: [PASS][9] -> [TIMEOUT][10] ([i915#6794])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rpls-1/igt@i915_selftest@l...@mman.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115980v10/bat-rpls-1/igt@i915_selftest@l...@mman.html
* igt@i915_selftest@live@slpc:
- bat-rplp-1: [PASS][11] -> [DMESG-FAIL][12] ([i915#6367] /
[i915#7913])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rplp-1/igt@i915_selftest@l...@slpc.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115980v10/bat-rplp-1/igt@i915_selftest@l...@slpc.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271]) +16 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115980v10/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-1: NOTRUN -> [SKIP][14] ([i915#7828])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115980v10/bat-rpls-1/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-1: NOTRUN -> [SKIP][15] ([i915#1845])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115980v10/bat-rpls-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-1: [ABORT][16] ([i915#6687] / [i915#7978]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115980v10/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/iss
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Define MOCS and PAT tables for MTL (rev10)
== Series Details == Series: drm/i915/mtl: Define MOCS and PAT tables for MTL (rev10) URL : https://patchwork.freedesktop.org/series/115980/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Define MOCS and PAT tables for MTL (rev10)
== Series Details == Series: drm/i915/mtl: Define MOCS and PAT tables for MTL (rev10) URL : https://patchwork.freedesktop.org/series/115980/ State : warning == Summary == Error: dim checkpatch failed 9e568e869ce8 drm/i915/mtl: Define MOCS and PAT tables for MTL 61f1e9e5a3cd drm/i915/mtl: fix mocs selftest fea798a30121 drm/i915/mtl: Add PTE encode function 5e9f621ae3f4 drm/i915: preparation for using PAT index 28e4dd4c864a drm/i915: use pat_index instead of cache_level 5ff383845c93 drm/i915: make sure correct pte encode is used -:26: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #26: FILE: drivers/gpu/drm/i915/gt/gen8_ppgtt.c:59: +static u64 gen12_pte_encode(dma_addr_t addr, unsigned int pat_index, total: 0 errors, 0 warnings, 1 checks, 18 lines checked a3038577a7c3 drm/i915/mtl: end support for set caching ioctl 70b58f9ac8cc drm/i915: Allow user to set cache at BO creation
[Intel-gfx] ✗ Fi.CI.BAT: failure for Improvements to uc firmare management (rev3)
== Series Details ==
Series: Improvements to uc firmare management (rev3)
URL : https://patchwork.freedesktop.org/series/116517/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13043 -> Patchwork_116517v3
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_116517v3 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_116517v3, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116517v3/index.html
Participating hosts (36 -> 36)
--
Additional (1): bat-mtlp-8
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116517v3:
### IGT changes ###
Possible regressions
* igt@kms_flip@basic-flip-vs-wf_vblank@a-hdmi-a1:
- fi-elk-e7500: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/fi-elk-e7500/igt@kms_flip@basic-flip-vs-wf_vbl...@a-hdmi-a1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116517v3/fi-elk-e7500/igt@kms_flip@basic-flip-vs-wf_vbl...@a-hdmi-a1.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@hugepages:
- {bat-mtlp-8}: NOTRUN -> [DMESG-FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116517v3/bat-mtlp-8/igt@i915_selftest@l...@hugepages.html
Known issues
Here are the changes found in Patchwork_116517v3 that come from known issues:
### IGT changes ###
Warnings
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-FAIL][4] ([i915#6367] / [i915#7996]) ->
[DMESG-FAIL][5] ([i915#6367])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116517v3/bat-rpls-1/igt@i915_selftest@l...@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
[i915#8346]: https://gitlab.freedesktop.org/drm/intel/issues/8346
[i915#8368]: https://gitlab.freedesktop.org/drm/intel/issues/8368
[i915#8369]: https://gitlab.freedesktop.org/drm/intel/issues/8369
[i915#8379]: https://gitlab.freedesktop.org/drm/intel/issues/8379
Build changes
-
* Linux: CI_DRM_13043 -> Patchwork_116517v3
CI-20190529: 20190529
CI_DRM_13043: 2fa9c266135355c9993507d7c27cc6722956bfec @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116517v3: 2fa9c266135355c9993507d7c27cc6722956bfec @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
9124e14cc346 drm/i915/uc: Make unexpected firmware versions an error in debug
builds
285925456608 drm/i915/uc: Reject duplicate entries in firmware table
9d456229f40e drm/i915/uc: Enhancements to firmware table validation
f88b23c6bd08 drm/i915/uc: Track patch level versions on reduced version
firmware files
0230c2d1ec3d drm/i915/guc: Print status register when waiting for GuC to load
99d1c102d0f1 drm/i915/guc: Decode another GuC load failure case
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116517v3/index.html
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: use ref_tracker library for tracking wakerefs (rev8)
== Series Details ==
Series: drm/i915: use ref_tracker library for tracking wakerefs (rev8)
URL : https://patchwork.freedesktop.org/series/100327/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13040_full -> Patchwork_100327v8_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_100327v8_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v8/shard-dg1-16/igt@kms_flip_scaled_...@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html
Known issues
Here are the changes found in Patchwork_100327v8_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_close_race@multigpu-basic-process:
- shard-apl: NOTRUN -> [SKIP][2] ([fdo#109271]) +19 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v8/shard-apl3/igt@gem_close_r...@multigpu-basic-process.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13040/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v8/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v8/shard-apl3/igt@gem_huc_c...@huc-copy.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][6] -> [ABORT][7] ([i915#5566])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13040/shard-glk6/igt@gen9_exec_pa...@allowed-all.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v8/shard-glk1/igt@gen9_exec_pa...@allowed-all.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [PASS][8] -> [DMESG-FAIL][9] ([i915#5334])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13040/shard-apl4/igt@i915_selftest@live@gt_heartbeat.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v8/shard-apl3/igt@i915_selftest@live@gt_heartbeat.html
*
igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271]) +7 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v8/shard-snb1/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotat...@pipe-b-hdmi-a-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-apl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#658])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v8/shard-apl3/igt@kms_psr2...@primary-plane-update-sf-dmg-area-big-fb.html
* igt@perf@stress-open-close@0-rcs0:
- shard-glk: [PASS][12] -> [ABORT][13] ([i915#5213])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13040/shard-glk1/igt@perf@stress-open-cl...@0-rcs0.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v8/shard-glk6/igt@perf@stress-open-cl...@0-rcs0.html
Possible fixes
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- {shard-rkl}:[FAIL][14] ([i915#7742]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13040/shard-rkl-3/igt@drm_fdinfo@most-busy-check-...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v8/shard-rkl-3/igt@drm_fdinfo@most-busy-check-...@rcs0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-rkl}:[FAIL][16] ([i915#6268]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13040/shard-rkl-7/igt@gem_ctx_e...@basic-nohangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v8/shard-rkl-1/igt@gem_ctx_e...@basic-nohangcheck.html
* igt@gem_eio@hibernate:
- shard-glk: [DMESG-WARN][18] ([i915#118]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13040/shard-glk7/igt@gem_...@hibernate.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v8/shard-glk2/igt@gem_...@hibernate.html
* igt@gem_exec_fair@basic-none@bcs0:
- {shard-rkl}:[FAIL][20] ([i915#2842]) -> [PASS][21] +3 similar
issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13040/shard-rkl-3/igt@gem_exec_fair@basic-n...@bcs0.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_1
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Improvements to uc firmare management (rev3)
== Series Details == Series: Improvements to uc firmare management (rev3) URL : https://patchwork.freedesktop.org/series/116517/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Improvements to uc firmare management (rev3)
== Series Details == Series: Improvements to uc firmare management (rev3) URL : https://patchwork.freedesktop.org/series/116517/ State : warning == Summary == Error: dim checkpatch failed c9c1858ce1b5 drm/i915/guc: Decode another GuC load failure case 78137da72e02 drm/i915/guc: Print status register when waiting for GuC to load b5a9b016719f drm/i915/uc: Track patch level versions on reduced version firmware files -:61: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'major_' - possible side-effects? #61: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:200: +#define GUC_FW_BLOB(prefix_, major_, minor_, patch_) \ + UC_FW_BLOB_NEW(major_, minor_, patch_, false, \ + MAKE_GUC_FW_PATH_MAJOR(prefix_, major_, minor_, patch_)) -:61: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'minor_' - possible side-effects? #61: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:200: +#define GUC_FW_BLOB(prefix_, major_, minor_, patch_) \ + UC_FW_BLOB_NEW(major_, minor_, patch_, false, \ + MAKE_GUC_FW_PATH_MAJOR(prefix_, major_, minor_, patch_)) -:61: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'patch_' - possible side-effects? #61: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:200: +#define GUC_FW_BLOB(prefix_, major_, minor_, patch_) \ + UC_FW_BLOB_NEW(major_, minor_, patch_, false, \ + MAKE_GUC_FW_PATH_MAJOR(prefix_, major_, minor_, patch_)) total: 0 errors, 0 warnings, 3 checks, 73 lines checked 1280d8f010c6 drm/i915/uc: Enhancements to firmware table validation a4d2663e570b drm/i915/uc: Reject duplicate entries in firmware table cd22dd08e779 drm/i915/uc: Make unexpected firmware versions an error in debug builds
Re: [Intel-gfx] [PATCH 8/8] drm/i915: Allow user to set cache at BO creation
On 2023-04-20 09:11:18, Yang, Fei wrote:
> > On 20/04/2023 12:39, Andi Shyti wrote:
> >> Hi Fei,
> >>
> >>> To comply with the design that buffer objects shall have immutable
> >>> cache setting through out their life cycle, {set, get}_caching ioctl's
> >>> are no longer supported from MTL onward. With that change caching
> >>> policy can only be set at object creation time. The current code
> >>> applies a default (platform dependent) cache setting for all objects.
> >>> However this is not optimal for performance tuning. The patch extends
> >>> the existing gem_create uAPI to let user set PAT index for the object
> >>> at creation time.
> >>> The new extension is platform independent, so UMD's can switch to using
> >>> this extension for older platforms as well, while {set, get}_caching are
> >>> still supported on these legacy paltforms for compatibility reason.
> >>>
> >>> Cc: Chris Wilson
> >>> Cc: Matt Roper
> >>> Cc: Andi Shyti
> >>> Signed-off-by: Fei Yang
> >>> Reviewed-by: Andi Shyti
> >>
> >> because this is an API change, we need some more information
> >> here.
> >>
> >> First of all you need to CC the userspace guys that have been
> >> working on top of your series and get their ack's.
> >
> > Yes, and a link to a Mesa merge request which uses the uapi should be
> > included.
>
> Working with Mesa team on this, stay tuned.
>
I would like to see the extension detection issue is handled before
ack'ing this.
How about a new DRM_I915_QUERY_GEM_CREATE_EXTENSIONS item, that
returns a u64 array of usable extension names for
DRM_IOCTL_I915_GEM_CREATE_EXT?
A similar DRM_I915_QUERY_GEM_CONTEXT_CREATE_EXTENSIONS could also
provide an alternative to Alan's "drm/i915/uapi/pxp: Add a GET_PARAM
for PXP", and more easily allow advertising future new extensions for
context/buffer creation.
-Jordan
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: workaround coherency issue for Media (rev3)
== Series Details == Series: drm/i915/mtl: workaround coherency issue for Media (rev3) URL : https://patchwork.freedesktop.org/series/116751/ State : success == Summary == CI Bug Log - changes from CI_DRM_13043 -> Patchwork_116751v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116751v3/index.html Participating hosts (36 -> 35) -- Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_116751v3 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@requests: - bat-rpls-1: [PASS][1] -> [ABORT][2] ([i915#7911] / [i915#7982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rpls-1/igt@i915_selftest@l...@requests.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116751v3/bat-rpls-1/igt@i915_selftest@l...@requests.html [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911 [i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982 Build changes - * Linux: CI_DRM_13043 -> Patchwork_116751v3 CI-20190529: 20190529 CI_DRM_13043: 2fa9c266135355c9993507d7c27cc6722956bfec @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_116751v3: 2fa9c266135355c9993507d7c27cc6722956bfec @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits b6c0c2c1546d drm/i915/mtl: workaround coherency issue for Media == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116751v3/index.html
[Intel-gfx] [PATCH v5 2/2] drm/i915/selftest: Update the SLPC selftest
Use the new efficient frequency toggling interface. Also
create a helper function to restore the frequencies after
the test is done.
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/selftest_slpc.c | 42 ++---
1 file changed, 37 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c
b/drivers/gpu/drm/i915/gt/selftest_slpc.c
index bd44ce73a504..248646b3d3e8 100644
--- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
@@ -70,6 +70,31 @@ static int slpc_set_freq(struct intel_gt *gt, u32 freq)
return err;
}
+static int slpc_restore_freq(struct intel_guc_slpc *slpc, u32 min, u32 max)
+{
+ int err;
+
+ err = slpc_set_min_freq(slpc, min);
+ if (err) {
+ pr_err("Unable to restore min freq");
+ return err;
+ }
+
+ err = slpc_set_max_freq(slpc, max);
+ if (err) {
+ pr_err("Unable to restore min freq");
+ return err;
+ }
+
+ err = intel_guc_slpc_set_ignore_eff_freq(slpc, false);
+ if (err) {
+ pr_err("Unable to restore efficient freq");
+ return err;
+ }
+
+ return 0;
+}
+
static u64 measure_power_at_freq(struct intel_gt *gt, int *freq, u64 *power)
{
int err = 0;
@@ -268,8 +293,7 @@ static int run_test(struct intel_gt *gt, int test_type)
/*
* Set min frequency to RPn so that we can test the whole
-* range of RPn-RP0. This also turns off efficient freq
-* usage and makes results more predictable.
+* range of RPn-RP0.
*/
err = slpc_set_min_freq(slpc, slpc->min_freq);
if (err) {
@@ -277,6 +301,15 @@ static int run_test(struct intel_gt *gt, int test_type)
return err;
}
+ /*
+* Turn off efficient frequency so RPn/RP0 ranges are obeyed.
+*/
+ err = intel_guc_slpc_set_ignore_eff_freq(slpc, true);
+ if (err) {
+ pr_err("Unable to turn off efficient freq!");
+ return err;
+ }
+
intel_gt_pm_wait_for_idle(gt);
intel_gt_pm_get(gt);
for_each_engine(engine, gt, id) {
@@ -358,9 +391,8 @@ static int run_test(struct intel_gt *gt, int test_type)
break;
}
- /* Restore min/max frequencies */
- slpc_set_max_freq(slpc, slpc_max_freq);
- slpc_set_min_freq(slpc, slpc_min_freq);
+ /* Restore min/max/efficient frequencies */
+ err = slpc_restore_freq(slpc, slpc_min_freq, slpc_max_freq);
if (igt_flush_test(gt->i915))
err = -EIO;
--
2.38.1
[Intel-gfx] [PATCH v5 1/2] drm/i915/guc/slpc: Provide sysfs for efficient freq
SLPC enables use of efficient freq at init by default. It is
possible for GuC to request frequencies that are higher than
the 'software' max if user has set it lower than the efficient
level.
Scenarios/tests that require strict fixing of freq below the efficient
level will need to disable it through this interface.
v2: Keep just one interface to toggle sysfs. With this, user will
be completely responsible for toggling efficient frequency if need
be. There will be no implicit disabling when user sets min < RP1 (Ashutosh)
v3: Remove unused label, review comments (Ashutosh)
v4: Toggle efficient freq usage in SLPC selftest and checkpatch fixes
v5: Review comments (Andi) and add a separate patch for selftest updates
Fixes: 95ccf312a1e4 ("drm/i915/guc/slpc: Allow SLPC to use efficient frequency")
Signed-off-by: Vinay Belgaumkar
Reviewed-by: Rodrigo Vivi
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 35 +
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 38 +--
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 1 +
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 1 +
4 files changed, 64 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 28f27091cd3b..ee2b44f896a2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -451,6 +451,33 @@ static ssize_t punit_req_freq_mhz_show(struct kobject
*kobj,
return sysfs_emit(buff, "%u\n", preq);
}
+static ssize_t slpc_ignore_eff_freq_show(struct kobject *kobj,
+struct kobj_attribute *attr,
+char *buff)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
+ struct intel_guc_slpc *slpc = >->uc.guc.slpc;
+
+ return sysfs_emit(buff, "%u\n", slpc->ignore_eff_freq);
+}
+
+static ssize_t slpc_ignore_eff_freq_store(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buff, size_t count)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
+ struct intel_guc_slpc *slpc = >->uc.guc.slpc;
+ int err;
+ u32 val;
+
+ err = kstrtou32(buff, 0, &val);
+ if (err)
+ return err;
+
+ err = intel_guc_slpc_set_ignore_eff_freq(slpc, val);
+ return err ?: count;
+}
+
struct intel_gt_bool_throttle_attr {
struct attribute attr;
ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
@@ -663,6 +690,8 @@ static struct kobj_attribute attr_media_freq_factor_scale =
INTEL_GT_ATTR_RO(media_RP0_freq_mhz);
INTEL_GT_ATTR_RO(media_RPn_freq_mhz);
+INTEL_GT_ATTR_RW(slpc_ignore_eff_freq);
+
static const struct attribute *media_perf_power_attrs[] = {
&attr_media_freq_factor.attr,
&attr_media_freq_factor_scale.attr,
@@ -744,6 +773,12 @@ void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct
kobject *kobj)
if (ret)
gt_warn(gt, "failed to create punit_req_freq_mhz sysfs (%pe)",
ERR_PTR(ret));
+ if (intel_uc_uses_guc_slpc(>->uc)) {
+ ret = sysfs_create_file(kobj, &attr_slpc_ignore_eff_freq.attr);
+ if (ret)
+ gt_warn(gt, "failed to create ignore_eff_freq sysfs
(%pe)", ERR_PTR(ret));
+ }
+
if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
ret = sysfs_create_files(kobj, throttle_reason_attrs);
if (ret)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 026d73855f36..56dbba1ef668 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -277,6 +277,7 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
slpc->max_freq_softlimit = 0;
slpc->min_freq_softlimit = 0;
+ slpc->ignore_eff_freq = false;
slpc->min_is_rpmax = false;
slpc->boost_freq = 0;
@@ -457,6 +458,29 @@ int intel_guc_slpc_get_max_freq(struct intel_guc_slpc
*slpc, u32 *val)
return ret;
}
+int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val)
+{
+ struct drm_i915_private *i915 = slpc_to_i915(slpc);
+ intel_wakeref_t wakeref;
+ int ret;
+
+ mutex_lock(&slpc->lock);
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+
+ ret = slpc_set_param(slpc,
+SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
+val);
+ if (ret)
+ guc_probe_error(slpc_to_guc(slpc), "Failed to set efficient
freq(%d): %pe\n",
+ val, ERR_PTR(ret));
+ else
+ slpc->ignore_eff_freq = val;
+
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
[Intel-gfx] ✓ Fi.CI.BAT: success for video/hdmi: minor fixes for *_infoframe_init functions (rev2)
== Series Details == Series: video/hdmi: minor fixes for *_infoframe_init functions (rev2) URL : https://patchwork.freedesktop.org/series/116819/ State : success == Summary == CI Bug Log - changes from CI_DRM_13043 -> Patchwork_116819v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/index.html Participating hosts (36 -> 36) -- Additional (1): fi-kbl-soraka Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_116819v2 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@execlists: - fi-bsw-n3050: [PASS][3] -> [ABORT][4] ([i915#7911] / [i915#7913]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_heartbeat: - fi-glk-j4005: [PASS][5] -> [DMESG-FAIL][6] ([i915#5334]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][7] ([i915#1886]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@reset: - bat-rpls-1: [PASS][8] -> [ABORT][9] ([i915#4983] / [i915#8384]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rpls-1/igt@i915_selftest@l...@reset.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/bat-rpls-1/igt@i915_selftest@l...@reset.html * igt@i915_selftest@live@workarounds: - bat-dg1-7: [PASS][10] -> [ABORT][11] ([i915#4983]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-dg1-7/igt@i915_selftest@l...@workarounds.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/bat-dg1-7/igt@i915_selftest@l...@workarounds.html * igt@kms_chamelium_frames@hdmi-crc-fast: - fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271]) +16 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-adlp-9: NOTRUN -> [SKIP][13] ([i915#3546]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/bat-adlp-9/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384 Build changes - * Linux: CI_DRM_13043 -> Patchwork_116819v2 CI-20190529: 20190529 CI_DRM_13043: 2fa9c266135355c9993507d7c27cc6722956bfec @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_116819v2: 2fa9c266135355c9993507d7c27cc6722956bfec @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 188c8acce610 video/hdmi: minor fixes for *_infoframe_init functions == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116819v2/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for video/hdmi: minor fixes for *_infoframe_init functions (rev2)
== Series Details == Series: video/hdmi: minor fixes for *_infoframe_init functions (rev2) URL : https://patchwork.freedesktop.org/series/116819/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for video/hdmi: minor fixes for *_infoframe_init functions (rev2)
== Series Details == Series: video/hdmi: minor fixes for *_infoframe_init functions (rev2) URL : https://patchwork.freedesktop.org/series/116819/ State : warning == Summary == Error: dim checkpatch failed c9787366d4ea video/hdmi: minor fixes for *_infoframe_init functions -:218: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #218: FILE: drivers/video/hdmi.c:221: +void hdmi_spd_infoframe_init(struct hdmi_spd_infoframe *frame, const char *vendor, const char *product) -:384: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #384: FILE: include/linux/hdmi.h:253: +void hdmi_spd_infoframe_init(struct hdmi_spd_infoframe *frame, const char *vendor, const char *product); total: 0 errors, 0 warnings, 2 checks, 309 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: prevent potential div-by-zero
== Series Details ==
Series: drm/i915/dp: prevent potential div-by-zero
URL : https://patchwork.freedesktop.org/series/116821/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13043 -> Patchwork_116821v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/index.html
Participating hosts (36 -> 36)
--
Additional (1): bat-mtlp-8
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116821v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-mtlp-8}: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/bat-mtlp-8/igt@gem_exec_suspend@basic...@smem.html
Known issues
Here are the changes found in Patchwork_116821v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-1: NOTRUN -> [SKIP][2] ([i915#7828])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/bat-rpls-1/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-1: NOTRUN -> [SKIP][3] ([i915#1845])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/bat-rpls-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-1: [ABORT][4] ([i915#6687] / [i915#7978]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#8346]: https://gitlab.freedesktop.org/drm/intel/issues/8346
[i915#8368]: https://gitlab.freedesktop.org/drm/intel/issues/8368
[i915#8369]: https://gitlab.freedesktop.org/drm/intel/issues/8369
[i915#8379]: https://gitlab.freedesktop.org/drm/intel/issues/8379
[i915#8382]: https://gitlab.freedesktop.org/drm/intel/issues/8382
Build changes
-
* Linux: CI_DRM_13043 -> Patchwork_116821v1
CI-20190529: 20190529
CI_DRM_13043: 2fa9c266135355c9993507d7c27cc6722956bfec @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116821v1: 2fa9c266135355c9993507d7c27cc6722956bfec @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1d01202741d7 drm/i915/dp: prevent potential div-by-zero
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116821v1/index.html
[Intel-gfx] [PATCH v2 2/2] drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure
In the process of renaming all instances of 'dev_priv' to 'i915', start using 'i915' within the i915_drv.h file. Signed-off-by: Andi Shyti Reviewed-by: Andrzej Hajda --- drivers/gpu/drm/i915/i915_drv.h | 458 1 file changed, 229 insertions(+), 229 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c16f8a3cd914f..14c5338c96a6b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -407,11 +407,11 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) (engine__) && (engine__)->uabi_class == (class__); \ (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) -#define INTEL_INFO(dev_priv) (&(dev_priv)->__info) -#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) -#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) +#define INTEL_INFO(i915) (&(i915)->__info) +#define RUNTIME_INFO(i915) (&(i915)->__runtime) +#define DRIVER_CAPS(i915) (&(i915)->caps) -#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) +#define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id) #define IP_VER(ver, rel) ((ver) << 8 | (rel)) @@ -431,7 +431,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) #define IS_DISPLAY_VER(i915, from, until) \ (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) -#define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision) +#define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision) #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step) @@ -516,135 +516,135 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); } -#define IS_MOBILE(dev_priv)(INTEL_INFO(dev_priv)->is_mobile) -#define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) - -#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) -#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) -#define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) -#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) -#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) -#define IS_I915GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915GM) -#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) -#define IS_I945GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945GM) -#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) -#define IS_I965GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I965GM) -#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) -#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) -#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) -#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) -#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) -#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) -#define IS_IRONLAKE_M(dev_priv) \ - (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) -#define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE) -#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) -#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ -INTEL_INFO(dev_priv)->gt == 1) -#define IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) -#define IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) -#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) -#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) -#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) -#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) -#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) -#define IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) -#define IS_COFFEELAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) -#define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) -#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) -#define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ - IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) -#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) -#define IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) -#define IS_DG1(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG1) -#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S) -#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) -#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV) -#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2) -#define IS_PONTEVECCHIO(dev_priv) IS_PLAT
[Intel-gfx] [PATCH v2 1/2] drm/i915/i915_drv: Use proper parameter naming in for_each_engine()
for_each_engine() loops through engines in the GT, not in dev_priv. Because it's misleading, call it "gt__" instead of "dev_priv__". Signed-off-by: Andi Shyti Reviewed-by: Rodrigo Vivi Reviewed-by: Andrzej Hajda --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fe7eeafe9cff6..c16f8a3cd914f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -381,11 +381,11 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) } /* Simple iterator over all initialised engines */ -#define for_each_engine(engine__, dev_priv__, id__) \ +#define for_each_engine(engine__, gt__, id__) \ for ((id__) = 0; \ (id__) < I915_NUM_ENGINES; \ (id__)++) \ - for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) + for_each_if ((engine__) = (gt__)->engine[(id__)]) /* Iterator over subset of engines selected by mask */ #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ -- 2.40.0
[Intel-gfx] [PATCH v2 0/2] Use i915 instead of dev_priv
Hi, just another "Friday patch". While reviewing some patches from Tejas I found a bit confusing the use of dev_priv__ inside the for_each_engine(), perhaps it should be moved inside the gt/? As I was at it I made the /dev_priv/i915/ change which is still harmless. Next in queue is to change the i915_irq.h, which is a bit tricky (but not much) as the "dev_priv" is hardcoded inside some defines. Thank you Andrzej and Rodrigo for your reviews. Andi Changelog = v1 -> v2 - Fix double typo in the patch 1 commit: /for_each_gt/for_each_engine/ - Phrase properly the commit of patch 2. Andi Shyti (2): drm/i915/i915_drv: Use proper parameter naming in for_each_engine() drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure drivers/gpu/drm/i915/i915_drv.h | 462 1 file changed, 231 insertions(+), 231 deletions(-) -- 2.40.0
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mtl: Copy c10 phy pll sw state from master to slave for bigjoiner
== Series Details ==
Series: drm/i915/mtl: Copy c10 phy pll sw state from master to slave for
bigjoiner
URL : https://patchwork.freedesktop.org/series/116805/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13039_full -> Patchwork_116805v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 8)
--
Additional (1): shard-rkl0
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116805v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_rotation_crc@primary-rotation-270:
- {shard-rkl}:[PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13039/shard-rkl-4/igt@kms_rotation_...@primary-rotation-270.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116805v1/shard-rkl-4/igt@kms_rotation_...@primary-rotation-270.html
Known issues
Here are the changes found in Patchwork_116805v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_barrier_race@remote-request@rcs0:
- shard-apl: [PASS][3] -> [ABORT][4] ([i915#8211] / [i915#8234])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13039/shard-apl2/igt@gem_barrier_race@remote-requ...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116805v1/shard-apl4/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271]) +22 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116805v1/shard-snb7/igt@kms_f...@2x-nonexisting-fb.html
*
igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling@pipe-a-valid-mode:
- shard-glk: NOTRUN -> [SKIP][6] ([fdo#109271]) +9 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116805v1/shard-glk9/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscal...@pipe-a-valid-mode.html
* igt@kms_setmode@basic@pipe-a-vga-1:
- shard-snb: NOTRUN -> [FAIL][7] ([i915#5465]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116805v1/shard-snb5/igt@kms_setmode@ba...@pipe-a-vga-1.html
Possible fixes
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [FAIL][8] ([i915#2842]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13039/shard-apl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116805v1/shard-apl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [FAIL][10] ([i915#2842]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13039/shard-glk1/igt@gem_exec_fair@basic-p...@rcs0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116805v1/shard-glk7/igt@gem_exec_fair@basic-p...@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [ABORT][12] ([i915#5566]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13039/shard-glk8/igt@gen9_exec_pa...@allowed-single.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116805v1/shard-glk9/igt@gen9_exec_pa...@allowed-single.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- {shard-rkl}:[SKIP][14] ([i915#1937]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13039/shard-rkl-1/igt@i915_pm_lpsp@kms-l...@kms-lpsp-hdmi-a.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116805v1/shard-rkl-7/igt@i915_pm_lpsp@kms-l...@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- {shard-rkl}:[SKIP][16] ([i915#1397]) -> [PASS][17] +1 similar
issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13039/shard-rkl-7/igt@i915_pm_...@dpms-non-lpsp.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116805v1/shard-rkl-6/igt@i915_pm_...@dpms-non-lpsp.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs:
- {shard-dg1}:[DMESG-WARN][18] -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13039/shard-dg1-17/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116805v1/shard-dg1-17/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][20] ([i915#2346]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13039/shard-apl3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116805v1/shard-apl6/
[Intel-gfx] [PATCH v2 2/2] drm/i915/mtl: fix mocs selftest
From: Fei Yang
Media GT has a different base for MOCS register, need to apply
gsi_offset to the mmio address if not using the intel_uncore_r/w
functions for register access.
Cc: Matt Roper
Signed-off-by: Fei Yang
Reviewed-by: Matt Roper
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/selftest_mocs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c
b/drivers/gpu/drm/i915/gt/selftest_mocs.c
index ca009a6a13bdb..a8446ab825012 100644
--- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -131,13 +131,14 @@ static int read_mocs_table(struct i915_request *rq,
const struct drm_i915_mocs_table *table,
u32 *offset)
{
+ struct intel_gt *gt = rq->engine->gt;
u32 addr;
if (!table)
return 0;
if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
- addr = global_mocs_offset();
+ addr = global_mocs_offset() + gt->uncore->gsi_offset;
else
addr = mocs_offset(rq->engine);
--
2.40.0
[Intel-gfx] [PATCH v2 1/2] drm/i915/mtl: Define MOCS and PAT tables for MTL
From: Madhumitha Tolakanahalli Pradeep
On MTL, GT can no longer allocate on LLC - only the CPU can.
This, along with programming new register bits that MTL
requires calls for a MOCS/PAT table update.
Also the PAT index registers are multicasted for primary GT,
and there is an address jump from index 7 to 8. This patch
makes sure that these registers are programmed in the proper
way.
BSpec: 44509, 45101, 44235
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Madhumitha Tolakanahalli Pradeep
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Nirmoy Das
Signed-off-by: Fei Yang
Reviewed-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
Reviewed-by: Andi Shyti
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 ++-
drivers/gpu/drm/i915/gt/intel_gtt.c | 47 -
drivers/gpu/drm/i915/gt/intel_gtt.h | 8 +++
drivers/gpu/drm/i915/gt/intel_mocs.c| 70 -
4 files changed, 128 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index fd1f9cd35e9d7..e8c3b762a92a3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -356,7 +356,11 @@
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
-#define XEHP_PAT_INDEX(index) MCR_REG(0x4800 + (index) * 4)
+#define _PAT_INDEX(index) _PICK_EVEN_2RANGES(index, 8, \
+ 0x4800,
0x4804, \
+ 0x4848,
0x484c)
+#define XEHP_PAT_INDEX(index) MCR_REG(_PAT_INDEX(index))
+#define XELPMP_PAT_INDEX(index)_MMIO(_PAT_INDEX(index))
#define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
#define XEHP_TILE_LMEM_RANGE_SHIFT 8
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 4f436ba7a3c83..2f6a9be0ffe61 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -468,6 +468,44 @@ void gtt_write_workarounds(struct intel_gt *gt)
}
}
+static void xelpmp_setup_private_ppat(struct intel_uncore *uncore)
+{
+ intel_uncore_write(uncore, XELPMP_PAT_INDEX(0),
+ MTL_PPAT_L4_0_WB);
+ intel_uncore_write(uncore, XELPMP_PAT_INDEX(1),
+ MTL_PPAT_L4_1_WT);
+ intel_uncore_write(uncore, XELPMP_PAT_INDEX(2),
+ MTL_PPAT_L4_3_UC);
+ intel_uncore_write(uncore, XELPMP_PAT_INDEX(3),
+ MTL_PPAT_L4_0_WB | MTL_2_COH_1W);
+ intel_uncore_write(uncore, XELPMP_PAT_INDEX(4),
+ MTL_PPAT_L4_0_WB | MTL_3_COH_2W);
+
+ /*
+* Remaining PAT entries are left at the hardware-default
+* fully-cached setting
+*/
+}
+
+static void xelpg_setup_private_ppat(struct intel_gt *gt)
+{
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(0),
+MTL_PPAT_L4_0_WB);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(1),
+MTL_PPAT_L4_1_WT);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(2),
+MTL_PPAT_L4_3_UC);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(3),
+MTL_PPAT_L4_0_WB | MTL_2_COH_1W);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(4),
+MTL_PPAT_L4_0_WB | MTL_3_COH_2W);
+
+ /*
+* Remaining PAT entries are left at the hardware-default
+* fully-cached setting
+*/
+}
+
static void tgl_setup_private_ppat(struct intel_uncore *uncore)
{
/* TGL doesn't support LLC or AGE settings */
@@ -603,7 +641,14 @@ void setup_private_pat(struct intel_gt *gt)
GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ if (gt->type == GT_MEDIA) {
+ xelpmp_setup_private_ppat(gt->uncore);
+ return;
+ }
+
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ xelpg_setup_private_ppat(gt);
+ else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
xehp_setup_private_ppat(gt);
else if (GRAPHICS_VER(i915) >= 12)
tgl_setup_private_ppat(uncore);
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 69ce55f517f56..ea17849e7a5c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -147,6 +147,14 @@ typedef u64 gen8_pte_t;
#define GEN8_PDE_IPS_64K BIT(11)
#define GEN8_PDE_PS_2M BIT(7)
+#define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2)
+#define MTL_PAT_INDEX_COH_MODE_MASKREG_GENMASK(1, 0)
+#define MTL_PPAT_L4_3_U
[Intel-gfx] [PATCH v2 0/2] Define MOCS and PAT tables for MTL
Hi, just extracting this patch from Fei's series. Andi Changelog: == v1 -> v2: Taken from Fei's new series: https://patchwork.freedesktop.org/series/115980/ - Removed unnecessary defines - Place the selftest patches in a different patch Fei Yang (1): drm/i915/mtl: fix mocs selftest Madhumitha Tolakanahalli Pradeep (1): drm/i915/mtl: Define MOCS and PAT tables for MTL drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 ++- drivers/gpu/drm/i915/gt/intel_gtt.c | 47 - drivers/gpu/drm/i915/gt/intel_gtt.h | 8 +++ drivers/gpu/drm/i915/gt/intel_mocs.c| 70 - drivers/gpu/drm/i915/gt/selftest_mocs.c | 3 +- 5 files changed, 130 insertions(+), 4 deletions(-) -- 2.40.0
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix memory leaks in i915 selftests (rev4)
== Series Details ==
Series: drm/i915: Fix memory leaks in i915 selftests (rev4)
URL : https://patchwork.freedesktop.org/series/116513/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13043 -> Patchwork_116513v4
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/index.html
Participating hosts (36 -> 36)
--
Additional (1): bat-mtlp-8
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116513v4:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@load:
- {bat-mtlp-8}: NOTRUN -> [ABORT][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/bat-mtlp-8/igt@i915_module_l...@load.html
Known issues
Here are the changes found in Patchwork_116513v4 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][2] -> [ABORT][3] ([i915#7911] / [i915#7913])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: [PASS][4] -> [ABORT][5] ([i915#4983] / [i915#8384])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rpls-1/igt@i915_selftest@l...@reset.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/bat-rpls-1/igt@i915_selftest@l...@reset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384
Build changes
-
* Linux: CI_DRM_13043 -> Patchwork_116513v4
CI-20190529: 20190529
CI_DRM_13043: 2fa9c266135355c9993507d7c27cc6722956bfec @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116513v4: 2fa9c266135355c9993507d7c27cc6722956bfec @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116513v4/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix memory leaks in i915 selftests (rev4)
== Series Details == Series: drm/i915: Fix memory leaks in i915 selftests (rev4) URL : https://patchwork.freedesktop.org/series/116513/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2
Re: [Intel-gfx] [PATCH v4 8/8] drm/i915: Allow user to set cache at BO creation
On Fri, Apr 21, 2023 at 10:38:01AM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> To comply with the design that buffer objects shall have immutable
> cache setting through out their life cycle, {set, get}_caching ioctl's
> are no longer supported from MTL onward. With that change caching
> policy can only be set at object creation time. The current code
> applies a default (platform dependent) cache setting for all objects.
> However this is not optimal for performance tuning. The patch extends
> the existing gem_create uAPI to let user set PAT index for the object
> at creation time.
> The new extension is platform independent, so UMD's can switch to using
> this extension for older platforms as well, while {set, get}_caching are
> still supported on these legacy paltforms for compatibility reason.
>
> Cc: Chris Wilson
> Cc: Matt Roper
> Cc: Andi Shyti
> Signed-off-by: Fei Yang
> Reviewed-by: Andi Shyti
This still needs links links to the opensource userspace pull requests
(which must be fully reviewed, approved, and ready to merge by those
projects before we can apply the kernel changes), Cc's for the relevant
userspace developers (we need their ack on this as well), and a
Testcase: trailer indicating what IGT test(s) cover this new uapi.
Matt
> ---
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 ++
> drivers/gpu/drm/i915/gem/i915_gem_object.c | 6
> include/uapi/drm/i915_drm.h| 36 ++
> tools/include/uapi/drm/i915_drm.h | 36 ++
> 4 files changed, 114 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> index bfe1dbda4cb7..723c3ddd6c74 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> @@ -245,6 +245,7 @@ struct create_ext {
> unsigned int n_placements;
> unsigned int placement_mask;
> unsigned long flags;
> + unsigned int pat_index;
> };
>
> static void repr_placements(char *buf, size_t size,
> @@ -394,11 +395,39 @@ static int ext_set_protected(struct i915_user_extension
> __user *base, void *data
> return 0;
> }
>
> +static int ext_set_pat(struct i915_user_extension __user *base, void *data)
> +{
> + struct create_ext *ext_data = data;
> + struct drm_i915_private *i915 = ext_data->i915;
> + struct drm_i915_gem_create_ext_set_pat ext;
> + unsigned int max_pat_index;
> +
> + BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
> + offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
> +
> + if (copy_from_user(&ext, base, sizeof(ext)))
> + return -EFAULT;
> +
> + max_pat_index = INTEL_INFO(i915)->max_pat_index;
> +
> + if (ext.pat_index > max_pat_index) {
> + drm_dbg(&i915->drm, "PAT index is invalid: %u\n",
> + ext.pat_index);
> + return -EINVAL;
> + }
> +
> + ext_data->pat_index = ext.pat_index;
> +
> + return 0;
> +}
> +
> static const i915_user_extension_fn create_extensions[] = {
> [I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements,
> [I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected,
> + [I915_GEM_CREATE_EXT_SET_PAT] = ext_set_pat,
> };
>
> +#define PAT_INDEX_NOT_SET0x
> /**
> * i915_gem_create_ext_ioctl - Creates a new mm object and returns a handle
> to it.
> * @dev: drm device pointer
> @@ -418,6 +447,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
> *data,
> if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS)
> return -EINVAL;
>
> + ext_data.pat_index = PAT_INDEX_NOT_SET;
> ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
> create_extensions,
> ARRAY_SIZE(create_extensions),
> @@ -454,5 +484,11 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
> *data,
> if (IS_ERR(obj))
> return PTR_ERR(obj);
>
> + if (ext_data.pat_index != PAT_INDEX_NOT_SET) {
> + i915_gem_object_set_pat_index(obj, ext_data.pat_index);
> + /* Mark pat_index is set by UMD */
> + obj->cache_level = I915_CACHE_INVAL;
> + }
> +
> return i915_gem_publish(obj, file, &args->size, &args->handle);
> }
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> index 27c948350b5b..61651f7e5806 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> @@ -209,6 +209,12 @@ bool i915_gem_object_can_bypass_llc(struct
> drm_i915_gem_object *obj)
> if (!(obj->flags & I915_BO_ALLOC_USER))
> return false;
>
> + /*
> + * Always flush cache for UMD objects at creation time.
> + */
> + if (obj->cache_level == I915_CACHE_INVAL)
> +
Re: [Intel-gfx] [bug report] drm/i915/guc: Use GuC submission API version number
On 3/24/2023 02:12, Dan Carpenter wrote:
Hello John Harrison,
The patch 9bbba0667f37: "drm/i915/guc: Use GuC submission API version
number" from Nov 29, 2022, leads to the following Smatch static
checker warning:
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:821 intel_uc_fw_fetch()
warn: passing zero to 'ERR_PTR'
Doh! Yes. That is a bug. It's an error path that should never be hit -
it means a firmware file has been released with a version number that
breaks the spec or is simply corrupted data. So it's a low risk bug but
it should still be fixed. I'll post a patch...
Thanks,
John.
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
709 int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
710 {
711 struct intel_gt *gt = __uc_fw_to_gt(uc_fw);
712 struct drm_i915_private *i915 = gt->i915;
713 struct intel_uc_fw_file file_ideal;
714 struct drm_i915_gem_object *obj;
715 const struct firmware *fw = NULL;
716 bool old_ver = false;
717 int err;
718
719 GEM_BUG_ON(!gt->wopcm.size);
720 GEM_BUG_ON(!intel_uc_fw_is_enabled(uc_fw));
721
722 err = i915_inject_probe_error(i915, -ENXIO);
723 if (err)
724 goto fail;
725
726 __force_fw_fetch_failures(uc_fw, -EINVAL);
727 __force_fw_fetch_failures(uc_fw, -ESTALE);
728
729 err = try_firmware_load(uc_fw, &fw);
730 memcpy(&file_ideal, &uc_fw->file_wanted, sizeof(file_ideal));
731
732 /* Any error is terminal if overriding. Don't bother searching
for older versions */
733 if (err && intel_uc_fw_is_overridden(uc_fw))
734 goto fail;
735
736 while (err == -ENOENT) {
737 old_ver = true;
738
739 __uc_fw_auto_select(i915, uc_fw);
740 if (!uc_fw->file_selected.path) {
741 /*
742 * No more options! But set the path back to
something
743 * valid just in case it gets dereferenced.
744 */
745 uc_fw->file_selected.path = file_ideal.path;
746
747 /* Also, preserve the version that was really
wanted */
748 memcpy(&uc_fw->file_wanted, &file_ideal,
sizeof(uc_fw->file_wanted));
749 break;
750 }
751
752 err = try_firmware_load(uc_fw, &fw);
753 }
754
755 if (err)
756 goto fail;
757
758 err = check_fw_header(gt, fw, uc_fw);
759 if (err)
760 goto fail;
761
762 if (uc_fw->type == INTEL_UC_FW_TYPE_GUC &&
!guc_check_version_range(uc_fw))
763 goto fail;
^
Should "err" be set on this path?
764
765 if (uc_fw->file_wanted.ver.major &&
uc_fw->file_selected.ver.major) {
766 /* Check the file's major version was as it claimed */
767 if (uc_fw->file_selected.ver.major !=
uc_fw->file_wanted.ver.major) {
768 gt_notice(gt, "%s firmware %s: unexpected version:
%u.%u != %u.%u\n",
769 intel_uc_fw_type_repr(uc_fw->type),
uc_fw->file_selected.path,
770 uc_fw->file_selected.ver.major,
uc_fw->file_selected.ver.minor,
771 uc_fw->file_wanted.ver.major,
uc_fw->file_wanted.ver.minor);
772 if (!intel_uc_fw_is_overridden(uc_fw)) {
773 err = -ENOEXEC;
774 goto fail;
775 }
776 } else {
777 if (uc_fw->file_selected.ver.minor <
uc_fw->file_wanted.ver.minor)
778 old_ver = true;
779 }
780 }
781
782 if (old_ver && uc_fw->file_selected.ver.major) {
783 /* Preserve the version that was really wanted */
784 memcpy(&uc_fw->file_wanted, &file_ideal,
sizeof(uc_fw->file_wanted));
785
786 gt_notice(gt, "%s firmware %s (%d.%d) is recommended, but
only %s (%d.%d) was found\n",
787 intel_uc_fw_type_repr(uc_fw->type),
788 uc_fw->file_wanted.path,
789 uc_fw->file_wanted.ver.major,
uc_fw->file_wanted.ver.minor,
790 uc_fw->file_selected.path,
791 uc_fw->file_selected.ver.major,
uc_fw->file_selected.ver.m
Re: [Intel-gfx] [PATCH v4 2/8] drm/i915/mtl: fix mocs selftest
On Fri, Apr 21, 2023 at 10:37:55AM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> Media GT has a different base for MOCS register, need to apply
> gsi_offset to the mmio address if not using the intel_uncore_r/w
> functions for register access.
>
> Cc: Matt Roper
> Signed-off-by: Fei Yang
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/selftest_mocs.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> index ca009a6a13bd..a8446ab82501 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> @@ -131,13 +131,14 @@ static int read_mocs_table(struct i915_request *rq,
> const struct drm_i915_mocs_table *table,
> u32 *offset)
> {
> + struct intel_gt *gt = rq->engine->gt;
> u32 addr;
>
> if (!table)
> return 0;
>
> if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
> - addr = global_mocs_offset();
> + addr = global_mocs_offset() + gt->uncore->gsi_offset;
> else
> addr = mocs_offset(rq->engine);
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH 3/8] drm/i915/mtl: Add PTE encode function
On Fri, Apr 21, 2023 at 10:27:22AM -0700, Yang, Fei wrote:
>> On Wed, Apr 19, 2023 at 04:00:53PM -0700, fei.y...@intel.com wrote:
>>> From: Fei Yang
>>>
>>> PTE encode functions are platform dependent. This patch implements
>>> PTE functions for MTL, and ensures the correct PTE encode function
>>> is used by calling pte_encode function pointer instead of the
>>> hardcoded gen8 version of PTE encode.
>>>
>>> Signed-off-by: Fei Yang
>>> Reviewed-by: Andrzej Hajda
>>> Reviewed-by: Andi Shyti
>>> Acked-by: Nirmoy Das
>>
>> Bspec: 45015, 45040
>>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_dpt.c | 2 +-
>>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 45
>>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 36 +--
>>> 3 files changed, 72 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
>b/drivers/gpu/drm/i915/display/intel_dpt.c
>>> index b8027392144d..c5eacfdba1a5 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dpt.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dpt.c
>>> @@ -300,7 +300,7 @@ intel_dpt_create(struct intel_framebuffer *fb)
>>> vm->vma_ops.bind_vma = dpt_bind_vma;
>>> vm->vma_ops.unbind_vma = dpt_unbind_vma;
>>>
>>> - vm->pte_encode = gen8_ggtt_pte_encode;
>>> + vm->pte_encode = vm->gt->ggtt->vm.pte_encode;
>>>
>>> dpt->obj = dpt_obj;
>>> dpt->obj->is_dpt = true;
>>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>>> index 4daaa6f55668..11b91e0453c8 100644
>>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>>> @@ -55,6 +55,34 @@ static u64 gen8_pte_encode(dma_addr_t addr,
>>> return pte;
>>> }
>>>
>>> +static u64 mtl_pte_encode(dma_addr_t addr,
>>> + enum i915_cache_level level,
>>> + u32 flags)
>>> +{
>>> + gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
>>> +
>>> + if (unlikely(flags & PTE_READ_ONLY))
>>> + pte &= ~GEN8_PAGE_RW;
>>> +
>>> + if (flags & PTE_LM)
>>> + pte |= GEN12_PPGTT_PTE_LM | GEN12_PPGTT_PTE_NC;
>>
>> GEN12_PPGTT_PTE_NC got defined in the previous patch as BIT(5). But
>> according to bspec 45040, bit 5 is ignored in the PTE encoding. What is
>> this trying to do?
>This takes effect only for PTE_LM, doesn't affect MTL.
>PTE_NC is needed for PVC (use of access counter).
>I believe this function was writen based on the one for PVC. And this
>function
>did get extended to cover all gen12 in a later patch.
Even though MTL doesn't have local memory, PTE_LM is supposed to be used
on MTL for access to BAR2 stolen memory.
Matt
>-Fei
>> Matt
>>
>>> +
>>> + switch (level) {
>>> + case I915_CACHE_NONE:
>>> + pte |= GEN12_PPGTT_PTE_PAT1;
>>> + break;
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
[Intel-gfx] [PATCH v4 5/8] drm/i915: use pat_index instead of cache_level
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent, having to translate
between i915_cache_level and PAT index is not reliable, and makes the code
more complicated.
>From UMD's perspective there is also a necessity to set caching policy for
performance fine tuning. It's much easier for the UMD to directly use PAT
index because the behavior of each PAT index is clearly defined in Bspec.
Having the abstracted i915_cache_level sitting in between would only cause
more ambiguity.
For these reasons this patch replaces i915_cache_level with PAT index. Also
note, the cache_level is not completely removed yet, because the KMD still
has the need of creating buffer objects with simple cache settings such as
cached, uncached, or writethrough. For such simple cases, using cache_level
would help simplify the code.
Cc: Chris Wilson
Cc: Matt Roper
Signed-off-by: Fei Yang
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/display/intel_dpt.c | 12 +--
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 27 ++
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 10 ++-
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_object.c| 52 +++-
drivers/gpu/drm/i915/gem/i915_gem_object.h| 4 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 25 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 4 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 16 ++--
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
.../drm/i915/gem/selftests/i915_gem_migrate.c | 2 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 2 +-
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 10 ++-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 71
drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 3 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 82 +--
drivers/gpu/drm/i915/gt/intel_gtt.h | 20 ++---
drivers/gpu/drm/i915/gt/intel_migrate.c | 47 ++-
drivers/gpu/drm/i915/gt/intel_migrate.h | 13 ++-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 6 +-
drivers/gpu/drm/i915/gt/selftest_migrate.c| 47 ++-
drivers/gpu/drm/i915/gt/selftest_reset.c | 8 +-
drivers/gpu/drm/i915/gt/selftest_timeline.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_tlb.c| 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 10 ++-
drivers/gpu/drm/i915/i915_debugfs.c | 55 ++---
drivers/gpu/drm/i915/i915_gem.c | 16 +++-
drivers/gpu/drm/i915/i915_gpu_error.c | 8 +-
drivers/gpu/drm/i915/i915_vma.c | 16 ++--
drivers/gpu/drm/i915/i915_vma.h | 2 +-
drivers/gpu/drm/i915/i915_vma_types.h | 2 -
drivers/gpu/drm/i915/selftests/i915_gem.c | 5 +-
.../gpu/drm/i915/selftests/i915_gem_evict.c | 4 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 15 ++--
.../drm/i915/selftests/intel_memory_region.c | 4 +-
drivers/gpu/drm/i915/selftests/mock_gtt.c | 8 +-
36 files changed, 378 insertions(+), 239 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index c5eacfdba1a5..7c5fddb203ba 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -43,24 +43,24 @@ static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
static void dpt_insert_page(struct i915_address_space *vm,
dma_addr_t addr,
u64 offset,
- enum i915_cache_level level,
+ unsigned int pat_index,
u32 flags)
{
struct i915_dpt *dpt = i915_vm_to_dpt(vm);
gen8_pte_t __iomem *base = dpt->iomem;
gen8_set_pte(base + offset / I915_GTT_PAGE_SIZE,
-vm->pte_encode(addr, level, flags));
+vm->pte_encode(addr, pat_index, flags));
}
static void dpt_insert_entries(struct i915_address_space *vm,
struct i915_vma_resource *vma_res,
- enum i915_cache_level level,
+ unsigned int pat_index,
u32 flags)
{
struct i915_dpt *dpt = i915_vm_to_dpt(vm);
gen8_pte_t __iomem *base = dpt->iomem;
- const gen8_pte_t pte_encode = vm->pte_encode(0, level, flags);
+ const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
struct sgt_iter sgt_iter;
dma_addr_t addr;
int i;
@@ -83,7 +83,7 @@ static void dpt_clear_range(struct i915_address_space *vm,
static void dpt_bind_vma(struct i915_address_space *vm,
struct i915_vm_pt_stash *stash,
struct i9
[Intel-gfx] [PATCH v4 4/8] drm/i915: preparation for using PAT index
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by adding some platform dependent data structures
and helper functions to translate the cache_level to pat_index.
cachelevel_to_pat: a platform dependent array mapping cache_level to
pat_index.
max_pat_index: the maximum PAT index supported by the hardware. Needed for
validating the PAT index passed in from user space.
i915_gem_get_pat_index: function to convert cache_level to PAT index.
obj_to_i915(obj): macro moved to header file for wider usage.
I915_MAX_CACHE_LEVEL: upper bound of i915_cache_level for the
convenience of coding.
Cc: Chris Wilson
Cc: Matt Roper
Cc: Andi Shyti
Signed-off-by: Fei Yang
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_object.c| 9 +++
drivers/gpu/drm/i915/gem/i915_gem_object.h| 4 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 -
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 ++
drivers/gpu/drm/i915/gt/intel_ggtt.c | 6 ++
drivers/gpu/drm/i915/i915_pci.c | 79 ---
drivers/gpu/drm/i915/intel_device_info.h | 5 ++
.../gpu/drm/i915/selftests/mock_gem_device.c | 9 +++
9 files changed, 110 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 4666bb82f312..8c70a0ec7d2f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -45,6 +45,15 @@ static struct kmem_cache *slab_objects;
static const struct drm_gem_object_funcs i915_gem_object_funcs;
+unsigned int i915_gem_get_pat_index(struct drm_i915_private *i915,
+ enum i915_cache_level level)
+{
+ if (drm_WARN_ON(&i915->drm, level >= I915_MAX_CACHE_LEVEL))
+ return 0;
+
+ return INTEL_INFO(i915)->cachelevel_to_pat[level];
+}
+
struct drm_i915_gem_object *i915_gem_object_alloc(void)
{
struct drm_i915_gem_object *obj;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 885ccde9dc3c..4c92e17b4337 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -20,6 +20,8 @@
enum intel_region_id;
+#define obj_to_i915(obj__) to_i915((obj__)->base.dev)
+
static inline bool i915_gem_object_size_2big(u64 size)
{
struct drm_i915_gem_object *obj;
@@ -30,6 +32,8 @@ static inline bool i915_gem_object_size_2big(u64 size)
return false;
}
+unsigned int i915_gem_get_pat_index(struct drm_i915_private *i915,
+ enum i915_cache_level level);
void i915_gem_init__objects(struct drm_i915_private *i915);
void i915_objects_module_exit(void);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 830c11431ee8..41b35abccf88 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -194,6 +194,7 @@ enum i915_cache_level {
* engine.
*/
I915_CACHE_WT,
+ I915_MAX_CACHE_LEVEL,
};
enum i915_map_type {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index b1672e054b21..214763942aa2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -460,8 +460,6 @@ void i915_gem_shrinker_taints_mutex(struct drm_i915_private
*i915,
fs_reclaim_release(GFP_KERNEL);
}
-#define obj_to_i915(obj__) to_i915((obj__)->base.dev)
-
/**
* i915_gem_object_make_unshrinkable - Hide the object from the shrinker. By
* default all object types that support shrinking(see IS_SHRINKABLE), will
also
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 11b91e0453c8..7a4b1d1afce9 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -78,6 +78,12 @@ static u64 mtl_pte_encode(dma_addr_t addr,
case I915_CACHE_WT:
pte |= GEN12_PPGTT_PTE_PAT0;
break;
+ default:
+ /* This should never happen. Added to deal with the compile
+* error due to the addition of I915_MAX_CACHE_LEVEL. Will
+* be removed by the pat_index patch.
+*/
+ break;
}
return pte;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 20915edc8bd9..c8390d03fce2 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i91
[Intel-gfx] [PATCH v4 7/8] drm/i915/mtl: end support for set caching ioctl
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
cache. For UMD's need to fine tune the caching policy for BO's, a follow
up patch will extend the GEM_CREATE uAPI to allow UMD's specify caching
mode at BO creation time.
Signed-off-by: Fei Yang
Reviewed-by: Andi Shyti
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 9 -
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 89938084af97..d5fd4c9cd9f8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -328,6 +328,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void
*data,
if (IS_DGFX(i915))
return -ENODEV;
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ return -EOPNOTSUPP;
+
switch (args->caching) {
case I915_CACHING_NONE:
level = I915_CACHE_NONE;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 37d1efcd3ca6..cad4a6017f4b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region
*mem,
obj->write_domain = I915_GEM_DOMAIN_CPU;
obj->read_domains = I915_GEM_DOMAIN_CPU;
- if (HAS_LLC(i915))
+ /*
+* MTL doesn't snoop CPU cache by default for GPU access (namely
+* 1-way coherency). However some UMD's are currently depending on
+* that. Make 1-way coherent the default setting for MTL. A follow
+* up patch will extend the GEM_CREATE uAPI to allow UMD's specify
+* caching mode at BO creation time
+*/
+ if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)))
/* On some devices, we can have the GPU use the LLC (the CPU
* cache) for about a 10% performance improvement
* compared to uncached. Graphics requests other than
--
2.25.1
[Intel-gfx] [PATCH v4 8/8] drm/i915: Allow user to set cache at BO creation
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a default (platform dependent) cache setting for all objects.
However this is not optimal for performance tuning. The patch extends
the existing gem_create uAPI to let user set PAT index for the object
at creation time.
The new extension is platform independent, so UMD's can switch to using
this extension for older platforms as well, while {set, get}_caching are
still supported on these legacy paltforms for compatibility reason.
Cc: Chris Wilson
Cc: Matt Roper
Cc: Andi Shyti
Signed-off-by: Fei Yang
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 ++
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6
include/uapi/drm/i915_drm.h| 36 ++
tools/include/uapi/drm/i915_drm.h | 36 ++
4 files changed, 114 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index bfe1dbda4cb7..723c3ddd6c74 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -245,6 +245,7 @@ struct create_ext {
unsigned int n_placements;
unsigned int placement_mask;
unsigned long flags;
+ unsigned int pat_index;
};
static void repr_placements(char *buf, size_t size,
@@ -394,11 +395,39 @@ static int ext_set_protected(struct i915_user_extension
__user *base, void *data
return 0;
}
+static int ext_set_pat(struct i915_user_extension __user *base, void *data)
+{
+ struct create_ext *ext_data = data;
+ struct drm_i915_private *i915 = ext_data->i915;
+ struct drm_i915_gem_create_ext_set_pat ext;
+ unsigned int max_pat_index;
+
+ BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
+offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ max_pat_index = INTEL_INFO(i915)->max_pat_index;
+
+ if (ext.pat_index > max_pat_index) {
+ drm_dbg(&i915->drm, "PAT index is invalid: %u\n",
+ ext.pat_index);
+ return -EINVAL;
+ }
+
+ ext_data->pat_index = ext.pat_index;
+
+ return 0;
+}
+
static const i915_user_extension_fn create_extensions[] = {
[I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements,
[I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected,
+ [I915_GEM_CREATE_EXT_SET_PAT] = ext_set_pat,
};
+#define PAT_INDEX_NOT_SET 0x
/**
* i915_gem_create_ext_ioctl - Creates a new mm object and returns a handle to
it.
* @dev: drm device pointer
@@ -418,6 +447,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
*data,
if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS)
return -EINVAL;
+ ext_data.pat_index = PAT_INDEX_NOT_SET;
ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
create_extensions,
ARRAY_SIZE(create_extensions),
@@ -454,5 +484,11 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
*data,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ if (ext_data.pat_index != PAT_INDEX_NOT_SET) {
+ i915_gem_object_set_pat_index(obj, ext_data.pat_index);
+ /* Mark pat_index is set by UMD */
+ obj->cache_level = I915_CACHE_INVAL;
+ }
+
return i915_gem_publish(obj, file, &args->size, &args->handle);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 27c948350b5b..61651f7e5806 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -209,6 +209,12 @@ bool i915_gem_object_can_bypass_llc(struct
drm_i915_gem_object *obj)
if (!(obj->flags & I915_BO_ALLOC_USER))
return false;
+ /*
+* Always flush cache for UMD objects at creation time.
+*/
+ if (obj->cache_level == I915_CACHE_INVAL)
+ return true;
+
/*
* EHL and JSL add the 'Bypass LLC' MOCS entry, which should make it
* possible for userspace to bypass the GTT caching bits set by the
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index dba7c5a5b25e..03c5c314846e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3630,9 +3630,13 @@ struct drm_i915_gem_create_ext {
*
* For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see
* struct drm_i915_gem_create_ext_protected_content.
+
[Intel-gfx] [PATCH v4 6/8] drm/i915: make sure correct pte encode is used
From: Fei Yang
PTE encode is platform dependent. After replacing cache_level with
pat_index, the newly introduced mtl_pte_encode is actually generic
for all gen12 platforms, thus rename it to gen12_pte_encode and
apply it to all gen12 platforms.
Cc: Chris Wilson
Cc: Matt Roper
Signed-off-by: Fei Yang
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index c046813514f4..3373b2aeae86 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -55,7 +55,7 @@ static u64 gen8_pte_encode(dma_addr_t addr,
return pte;
}
-static u64 mtl_pte_encode(dma_addr_t addr,
+static u64 gen12_pte_encode(dma_addr_t addr,
unsigned int pat_index,
u32 flags)
{
@@ -994,8 +994,8 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
*/
ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
- if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
- ppgtt->vm.pte_encode = mtl_pte_encode;
+ if (GRAPHICS_VER(gt->i915) >= 12)
+ ppgtt->vm.pte_encode = gen12_pte_encode;
else
ppgtt->vm.pte_encode = gen8_pte_encode;
--
2.25.1
[Intel-gfx] [PATCH v4 3/8] drm/i915/mtl: Add PTE encode function
From: Fei Yang
PTE encode functions are platform dependent. This patch implements
PTE functions for MTL, and ensures the correct PTE encode function
is used by calling pte_encode function pointer instead of the
hardcoded gen8 version of PTE encode.
Signed-off-by: Fei Yang
Reviewed-by: Andrzej Hajda
Reviewed-by: Andi Shyti
Acked-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_dpt.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 45
drivers/gpu/drm/i915/gt/intel_ggtt.c | 36 +--
drivers/gpu/drm/i915/gt/intel_gtt.h | 13 +--
4 files changed, 83 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index b8027392144d..c5eacfdba1a5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -300,7 +300,7 @@ intel_dpt_create(struct intel_framebuffer *fb)
vm->vma_ops.bind_vma= dpt_bind_vma;
vm->vma_ops.unbind_vma = dpt_unbind_vma;
- vm->pte_encode = gen8_ggtt_pte_encode;
+ vm->pte_encode = vm->gt->ggtt->vm.pte_encode;
dpt->obj = dpt_obj;
dpt->obj->is_dpt = true;
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 4daaa6f55668..11b91e0453c8 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -55,6 +55,34 @@ static u64 gen8_pte_encode(dma_addr_t addr,
return pte;
}
+static u64 mtl_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
+
+ if (unlikely(flags & PTE_READ_ONLY))
+ pte &= ~GEN8_PAGE_RW;
+
+ if (flags & PTE_LM)
+ pte |= GEN12_PPGTT_PTE_LM | GEN12_PPGTT_PTE_NC;
+
+ switch (level) {
+ case I915_CACHE_NONE:
+ pte |= GEN12_PPGTT_PTE_PAT1;
+ break;
+ case I915_CACHE_LLC:
+ case I915_CACHE_L3_LLC:
+ pte |= GEN12_PPGTT_PTE_PAT0 | GEN12_PPGTT_PTE_PAT1;
+ break;
+ case I915_CACHE_WT:
+ pte |= GEN12_PPGTT_PTE_PAT0;
+ break;
+ }
+
+ return pte;
+}
+
static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
{
struct drm_i915_private *i915 = ppgtt->vm.i915;
@@ -427,7 +455,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
u32 flags)
{
struct i915_page_directory *pd;
- const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
+ const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0, cache_level,
flags);
gen8_pte_t *vaddr;
pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));
@@ -580,7 +608,7 @@ static void gen8_ppgtt_insert_huge(struct
i915_address_space *vm,
enum i915_cache_level cache_level,
u32 flags)
{
- const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
+ const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags);
unsigned int rem = sg_dma_len(iter->sg);
u64 start = vma_res->start;
@@ -743,7 +771,7 @@ static void gen8_ppgtt_insert_entry(struct
i915_address_space *vm,
GEM_BUG_ON(pt->is_compact);
vaddr = px_vaddr(pt);
- vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
+ vaddr[gen8_pd_index(idx, 0)] = vm->pte_encode(addr, level, flags);
drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
}
@@ -773,7 +801,7 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct
i915_address_space *vm,
}
vaddr = px_vaddr(pt);
- vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level, flags);
+ vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, level, flags);
}
static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
@@ -820,8 +848,8 @@ static int gen8_init_scratch(struct i915_address_space *vm)
pte_flags |= PTE_LM;
vm->scratch[0]->encode =
- gen8_pte_encode(px_dma(vm->scratch[0]),
- I915_CACHE_NONE, pte_flags);
+ vm->pte_encode(px_dma(vm->scratch[0]),
+ I915_CACHE_NONE, pte_flags);
for (i = 1; i <= vm->top; i++) {
struct drm_i915_gem_object *obj;
@@ -963,7 +991,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
*/
ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
- ppgtt->vm.pte_encode = gen8_pte_encode;
+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
+ ppgtt->vm.pte_encode = mtl_pte_encode;
+ else
+ ppgtt->vm.pte_encode = gen8_pte_encode;
ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
ppgtt->vm.insert_entries =
[Intel-gfx] [PATCH v4 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL
From: Fei Yang The series includes patches needed to enable MTL. Also add new extension for GEM_CREATE uAPI to let user space set cache policy for buffer objects. v2: addressing review comments and checkpatch warnings v3: make mtl_ggtt_pte_encode static v4: addressing more comments from Matt drop two patches from previous version (to be merged separately) extend mtl_pte_encode to cover all gen12 Fei Yang (7): drm/i915/mtl: fix mocs selftest drm/i915/mtl: Add PTE encode function drm/i915: preparation for using PAT index drm/i915: use pat_index instead of cache_level drm/i915: make sure correct pte encode is used drm/i915/mtl: end support for set caching ioctl drm/i915: Allow user to set cache at BO creation Madhumitha Tolakanahalli Pradeep (1): drm/i915/mtl: Define MOCS and PAT tables for MTL drivers/gpu/drm/i915/display/intel_dpt.c | 14 ++-- drivers/gpu/drm/i915/gem/i915_gem_create.c| 36 drivers/gpu/drm/i915/gem/i915_gem_domain.c| 30 +++ .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 10 ++- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 3 +- drivers/gpu/drm/i915/gem/i915_gem_object.c| 67 ++- drivers/gpu/drm/i915/gem/i915_gem_object.h| 8 ++ .../gpu/drm/i915/gem/i915_gem_object_types.h | 26 +- drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 9 +- drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 - drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 4 +- drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 16 ++-- .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +- .../drm/i915/gem/selftests/i915_gem_migrate.c | 2 +- .../drm/i915/gem/selftests/i915_gem_mman.c| 2 +- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 10 ++- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 76 - drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 3 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 84 +-- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 +- drivers/gpu/drm/i915/gt/intel_gtt.c | 47 ++- drivers/gpu/drm/i915/gt/intel_gtt.h | 37 +--- drivers/gpu/drm/i915/gt/intel_migrate.c | 47 ++- drivers/gpu/drm/i915/gt/intel_migrate.h | 13 ++- drivers/gpu/drm/i915/gt/intel_mocs.c | 70 +++- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 6 +- drivers/gpu/drm/i915/gt/selftest_migrate.c| 47 ++- drivers/gpu/drm/i915/gt/selftest_mocs.c | 3 +- drivers/gpu/drm/i915/gt/selftest_reset.c | 8 +- drivers/gpu/drm/i915/gt/selftest_timeline.c | 2 +- drivers/gpu/drm/i915/gt/selftest_tlb.c| 4 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 10 ++- drivers/gpu/drm/i915/i915_debugfs.c | 55 +--- drivers/gpu/drm/i915/i915_gem.c | 16 +++- drivers/gpu/drm/i915/i915_gpu_error.c | 8 +- drivers/gpu/drm/i915/i915_pci.c | 79 +++-- drivers/gpu/drm/i915/i915_vma.c | 16 ++-- drivers/gpu/drm/i915/i915_vma.h | 2 +- drivers/gpu/drm/i915/i915_vma_types.h | 2 - drivers/gpu/drm/i915/intel_device_info.h | 5 ++ drivers/gpu/drm/i915/selftests/i915_gem.c | 5 +- .../gpu/drm/i915/selftests/i915_gem_evict.c | 4 +- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 15 ++-- .../drm/i915/selftests/intel_memory_region.c | 4 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 9 ++ drivers/gpu/drm/i915/selftests/mock_gtt.c | 8 +- include/uapi/drm/i915_drm.h | 36 tools/include/uapi/drm/i915_drm.h | 36 48 files changed, 781 insertions(+), 223 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH v4 1/8] drm/i915/mtl: Define MOCS and PAT tables for MTL
From: Madhumitha Tolakanahalli Pradeep
On MTL, GT can no longer allocate on LLC - only the CPU can.
This, along with programming new register bits that MTL
requires calls for a MOCS/PAT table update.
Also the PAT index registers are multicasted for primary GT,
and there is an address jump from index 7 to 8. This patch
makes sure that these registers are programmed in the proper
way.
BSpec: 44509, 45101, 44235
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Madhumitha Tolakanahalli Pradeep
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Nirmoy Das
Signed-off-by: Fei Yang
Reviewed-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 ++-
drivers/gpu/drm/i915/gt/intel_gtt.c | 47 -
drivers/gpu/drm/i915/gt/intel_gtt.h | 8 +++
drivers/gpu/drm/i915/gt/intel_mocs.c| 70 -
4 files changed, 128 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index fd1f9cd35e9d..e8c3b762a92a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -356,7 +356,11 @@
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
-#define XEHP_PAT_INDEX(index) MCR_REG(0x4800 + (index) * 4)
+#define _PAT_INDEX(index) _PICK_EVEN_2RANGES(index, 8, \
+ 0x4800,
0x4804, \
+ 0x4848,
0x484c)
+#define XEHP_PAT_INDEX(index) MCR_REG(_PAT_INDEX(index))
+#define XELPMP_PAT_INDEX(index)_MMIO(_PAT_INDEX(index))
#define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
#define XEHP_TILE_LMEM_RANGE_SHIFT 8
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 4f436ba7a3c8..2f6a9be0ffe6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -468,6 +468,44 @@ void gtt_write_workarounds(struct intel_gt *gt)
}
}
+static void xelpmp_setup_private_ppat(struct intel_uncore *uncore)
+{
+ intel_uncore_write(uncore, XELPMP_PAT_INDEX(0),
+ MTL_PPAT_L4_0_WB);
+ intel_uncore_write(uncore, XELPMP_PAT_INDEX(1),
+ MTL_PPAT_L4_1_WT);
+ intel_uncore_write(uncore, XELPMP_PAT_INDEX(2),
+ MTL_PPAT_L4_3_UC);
+ intel_uncore_write(uncore, XELPMP_PAT_INDEX(3),
+ MTL_PPAT_L4_0_WB | MTL_2_COH_1W);
+ intel_uncore_write(uncore, XELPMP_PAT_INDEX(4),
+ MTL_PPAT_L4_0_WB | MTL_3_COH_2W);
+
+ /*
+* Remaining PAT entries are left at the hardware-default
+* fully-cached setting
+*/
+}
+
+static void xelpg_setup_private_ppat(struct intel_gt *gt)
+{
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(0),
+MTL_PPAT_L4_0_WB);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(1),
+MTL_PPAT_L4_1_WT);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(2),
+MTL_PPAT_L4_3_UC);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(3),
+MTL_PPAT_L4_0_WB | MTL_2_COH_1W);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(4),
+MTL_PPAT_L4_0_WB | MTL_3_COH_2W);
+
+ /*
+* Remaining PAT entries are left at the hardware-default
+* fully-cached setting
+*/
+}
+
static void tgl_setup_private_ppat(struct intel_uncore *uncore)
{
/* TGL doesn't support LLC or AGE settings */
@@ -603,7 +641,14 @@ void setup_private_pat(struct intel_gt *gt)
GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ if (gt->type == GT_MEDIA) {
+ xelpmp_setup_private_ppat(gt->uncore);
+ return;
+ }
+
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ xelpg_setup_private_ppat(gt);
+ else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
xehp_setup_private_ppat(gt);
else if (GRAPHICS_VER(i915) >= 12)
tgl_setup_private_ppat(uncore);
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 69ce55f517f5..ea17849e7a5c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -147,6 +147,14 @@ typedef u64 gen8_pte_t;
#define GEN8_PDE_IPS_64K BIT(11)
#define GEN8_PDE_PS_2M BIT(7)
+#define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2)
+#define MTL_PAT_INDEX_COH_MODE_MASKREG_GENMASK(1, 0)
+#define MTL_PPAT_L4_3_UC REG_FIELD_PREP(MTL_PPAT_L
[Intel-gfx] [PATCH v4 2/8] drm/i915/mtl: fix mocs selftest
From: Fei Yang
Media GT has a different base for MOCS register, need to apply
gsi_offset to the mmio address if not using the intel_uncore_r/w
functions for register access.
Cc: Matt Roper
Signed-off-by: Fei Yang
---
drivers/gpu/drm/i915/gt/selftest_mocs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c
b/drivers/gpu/drm/i915/gt/selftest_mocs.c
index ca009a6a13bd..a8446ab82501 100644
--- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -131,13 +131,14 @@ static int read_mocs_table(struct i915_request *rq,
const struct drm_i915_mocs_table *table,
u32 *offset)
{
+ struct intel_gt *gt = rq->engine->gt;
u32 addr;
if (!table)
return 0;
if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
- addr = global_mocs_offset();
+ addr = global_mocs_offset() + gt->uncore->gsi_offset;
else
addr = mocs_offset(rq->engine);
--
2.25.1
Re: [Intel-gfx] [PATCH 3/8] drm/i915/mtl: Add PTE encode function
> On Wed, Apr 19, 2023 at 04:00:53PM -0700, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> PTE encode functions are platform dependent. This patch implements
>> PTE functions for MTL, and ensures the correct PTE encode function
>> is used by calling pte_encode function pointer instead of the
>> hardcoded gen8 version of PTE encode.
>>
>> Signed-off-by: Fei Yang
>> Reviewed-by: Andrzej Hajda
>> Reviewed-by: Andi Shyti
>> Acked-by: Nirmoy Das
>
> Bspec: 45015, 45040
>
>> ---
>> drivers/gpu/drm/i915/display/intel_dpt.c | 2 +-
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 45
>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 36 +--
>> 3 files changed, 72 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
>> b/drivers/gpu/drm/i915/display/intel_dpt.c
>> index b8027392144d..c5eacfdba1a5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dpt.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dpt.c
>> @@ -300,7 +300,7 @@ intel_dpt_create(struct intel_framebuffer *fb)
>>vm->vma_ops.bind_vma= dpt_bind_vma;
>>vm->vma_ops.unbind_vma = dpt_unbind_vma;
>>
>> - vm->pte_encode = gen8_ggtt_pte_encode;
>> + vm->pte_encode = vm->gt->ggtt->vm.pte_encode;
>>
>>dpt->obj = dpt_obj;
>>dpt->obj->is_dpt = true;
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> index 4daaa6f55668..11b91e0453c8 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> @@ -55,6 +55,34 @@ static u64 gen8_pte_encode(dma_addr_t addr,
>>return pte;
>> }
>>
>> +static u64 mtl_pte_encode(dma_addr_t addr,
>> + enum i915_cache_level level,
>> + u32 flags)
>> +{
>> + gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
>> +
>> + if (unlikely(flags & PTE_READ_ONLY))
>> + pte &= ~GEN8_PAGE_RW;
>> +
>> + if (flags & PTE_LM)
>> + pte |= GEN12_PPGTT_PTE_LM | GEN12_PPGTT_PTE_NC;
>
> GEN12_PPGTT_PTE_NC got defined in the previous patch as BIT(5). But
> according to bspec 45040, bit 5 is ignored in the PTE encoding. What is
> this trying to do?
This takes effect only for PTE_LM, doesn't affect MTL.
PTE_NC is needed for PVC (use of access counter).
I believe this function was writen based on the one for PVC. And this function
did get extended to cover all gen12 in a later patch.
-Fei
> Matt
>
>> +
>> + switch (level) {
>> + case I915_CACHE_NONE:
>> + pte |= GEN12_PPGTT_PTE_PAT1;
>> + break;
Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/mtl: Extend Wa_22011802037 to MTL A-step
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, April 21, 2023 8:09 AM
> To: Atwood, Matthew S
> Cc: Sripada, Radhakrishna ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/mtl: Extend Wa_22011802037
> to MTL A-step
>
> On Fri, Apr 21, 2023 at 08:05:50AM -0700, Matt Roper wrote:
> > On Wed, Apr 19, 2023 at 02:40:33PM -0700, Matt Atwood wrote:
> > > On Tue, Apr 18, 2023 at 03:04:45PM -0700, Radhakrishna Sripada wrote:
> > > > From: Madhumitha Tolakanahalli Pradeep
>
> > > >
> > > > Wa_22011802037 was being applied to all graphics_ver 11 & 12. This patch
> > > > updates the if statement to apply the W/A to right platforms and extends
> > > > it to MTL-M:A step.
> > > >
> > > Bspec: 53509
> > > > v1.1: Fix checkpatch warning.
> > > > v2: Change the check to reflect the wa at other palces(Lucas)
> > > s/palces/places.
> > > >
> > > > Cc: Lucas De Marchi
> > > > Cc: Umesh Nerlige Ramappa
> > > With that.
> > > Reviewed-by: Matt Atwood
> > > > Signed-off-by: Madhumitha Tolakanahalli Pradeep
>
> > > > Signed-off-by: Radhakrishna Sripada
> >
> > It doesn't look like this patch is complete? It's only changing one
> > condition for Wa_22011802037, even though there are several in the code.
> > From a quick grep, you're still missing updates for at least
> > guc_ctl_wa_flags, execlists_reset_prepare, and __intel_engine_stop_cs.
>
> Actually, scratch that. Those other spots already have a MTL clause as
> part of the condition. But in that case it means the commit message
> here is inaccurate; you're not extending this workaround to MTL a-step
> because that already happened on a previous patch. You're just
> providing a fix for an incomplete implementation that happened earlier.
> The commit message should be explaining that.
>
> >
> > Since this workaround is a complicated one that touches so many areas of
> > the code, and has a complex platform list, it's probably time to factor
> > the condition out into a needs_wa_22011802037() helper or something.
>
> I still suggest doing this, especially since we've clearly screwed up
> the handling of this workaround at least once already.
>
Sure Matt. With the patch already merged, I will handle this as a separate
patch.
- Radhakrishna(RK) Sripada
>
> Matt
>
> >
> >
> > Matt
> >
> > > > ---
> > > > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 ++--
> > > > 1 file changed, 6 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > > index 88e881b100cf..ee3e8352637f 100644
> > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > > @@ -1629,16 +1629,16 @@ static void guc_reset_state(struct
> intel_context *ce, u32 head, bool scrub)
> > > >
> > > > static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
> > > > {
> > > > - if (!IS_GRAPHICS_VER(engine->i915, 11, 12))
> > > > - return;
> > > > -
> > > > - intel_engine_stop_cs(engine);
> > > > -
> > > > /*
> > > > * Wa_22011802037: In addition to stopping the cs, we need
> > > > * to wait for any pending mi force wakeups
> > > > */
> > > > - intel_engine_wait_for_pending_mi_fw(engine);
> > > > + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > > > + (GRAPHICS_VER(engine->i915) >= 11 &&
> > > > +GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
> > > > + intel_engine_stop_cs(engine);
> > > > + intel_engine_wait_for_pending_mi_fw(engine);
> > > > + }
> > > > }
> > > >
> > > > static void guc_reset_nop(struct intel_engine_cs *engine)
> > > > --
> > > > 2.34.1
> > > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
[Intel-gfx] [PATCH v2] drm/i915/mtl: workaround coherency issue for Media
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by the Media tile update the whole
cache line, even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to different locations within a single cache line.
This patch circumvents the issue by making CPU/GPU shared memory
uncacheable (WC on CPU side, and PAT index 2 for GPU). Additionally,
it ensures that CPU writes are visible to the GPU with an
intel_guc_write_barrier().
While fixing the CTB issue, we noticed some random GSC firmware
loading failure because the share buffers are cacheable (WB) on CPU
side but uncached on GPU side. To fix these issues we need to map
such shared buffers as WC on CPU side. Since such allocations are
not all done through GuC allocator, to avoid too many code changes,
the i915_coherent_map_type() is now hard coded to return WC for MTL.
v2: Simplify the commit message(Matt).
BSpec: 45101
Signed-off-by: Fei Yang
Reviewed-by: Andi Shyti
Acked-by: Nirmoy Das
Reviewed-by: Andrzej Hajda
Reviewed-by: Matt Roper
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 5 -
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 13 +
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 7 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 ++
4 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index ecd86130b74f..89fc8ea6bcfc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -469,7 +469,10 @@ enum i915_map_type i915_coherent_map_type(struct
drm_i915_private *i915,
struct drm_i915_gem_object *obj,
bool always_coherent)
{
- if (i915_gem_object_is_lmem(obj))
+ /*
+* Wa_22016122933: always return I915_MAP_WC for MTL
+*/
+ if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(i915))
return I915_MAP_WC;
if (HAS_LLC(i915) || always_coherent)
return I915_MAP_WB;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
index 1d9fdfb11268..236673c02f9a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
@@ -110,6 +110,13 @@ static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc)
if (obj->base.size < gsc->fw.size)
return -ENOSPC;
+ /*
+* Wa_22016122933: For MTL the shared memory needs to be mapped
+* as WC on CPU side and UC (PAT index 2) on GPU side
+*/
+ if (IS_METEORLAKE(i915))
+ i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
+
dst = i915_gem_object_pin_map_unlocked(obj,
i915_coherent_map_type(i915,
obj, true));
if (IS_ERR(dst))
@@ -125,6 +132,12 @@ static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc)
memset(dst, 0, obj->base.size);
memcpy(dst, src, gsc->fw.size);
+ /*
+* Wa_22016122933: Making sure the data in dst is
+* visible to GSC right away
+*/
+ intel_guc_write_barrier(>->uc.guc);
+
i915_gem_object_unpin_map(gsc->fw.obj);
i915_gem_object_unpin_map(obj);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index e89f16ecf1ae..c9f20385f6a0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -744,6 +744,13 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc
*guc, u32 size)
if (IS_ERR(obj))
return ERR_CAST(obj);
+ /*
+* Wa_22016122933: For MTL the shared memory needs to be mapped
+* as WC on CPU side and UC (PAT index 2) on GPU side
+*/
+ if (IS_METEORLAKE(gt->i915))
+ i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
+
vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
if (IS_ERR(vma))
goto err;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 1803a633ed64..99a0a89091e7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -902,6 +902,12 @@ static int ct_read(struct intel_guc_ct *ct, struct
ct_incoming_msg **msg)
/* now update descriptor */
WRITE_ONCE(desc->head, head);
+ /*
+* Wa_22016122933: Making sure the head update is
+* visible to GuC right away
+*/
+ intel_guc_write_barrier(ct_to_guc(ct));
+
return available - len;
corrupted:
--
2.39.0
Re: [Intel-gfx] [PATCH v8 3/8] drm/i915/pxp: Add MTL helpers to submit Heci-Cmd-Packet to GSC
On 4/20/2023 10:34 PM, Alan Previn wrote:
Add helper functions into a new file for heci-packet-submission.
The helpers will handle generating the MTL GSC-CS Memory-Header
and submission of the Heci-Cmd-Packet instructions to the engine.
NOTE1: These common functions for heci-packet-submission will be used
by different i915 callers:
1- GSC-SW-Proxy: This is pending upstream publication awaiting
a few remaining opens
2- MTL-HDCP: An equivalent patch has also been published at:
https://patchwork.freedesktop.org/series/111876/. (Patch 1)
3- PXP: This series.
NOTE2: A difference in this patch vs what is appearing is in bullet 2
above is that HDCP (and SW-Proxy) will be using priveleged submission
(GGTT and common gsc-uc-context) while PXP will be using non-priveleged
PPGTT, context and batch buffer. Therefore this patch will only slightly
overlap with the MTL-HDCP patches despite have very similar function
names (emit_foo vs emit_nonpriv_foo). This is because HECI_CMD_PKT
instructions require different flows and hw-specific code when done
via PPGTT based submission (not different from other engines). MTL-HDCP
contains the same intel_gsc_mtl_header_t structures as this but the
helpers there are different. Both add the same new file names.
NOTE3: Additional clarity about the heci-cmd-pkt layout and where the
common helpers come in:
- On MTL, when an i915 subsystem needs to send a command request
to the security firmware, it will send that via the GSC-
engine-command-streamer.
- However those commands, (lets call them "gsc_specific_fw_api"
calls), are not understood by the GSC command streamer hw.
- The GSC CS only looks at the GSC_HECI_CMD_PKT instruction and
passes it along to the GSC firmware.
- The GSC FW on the other hand needs additional metadata to know
which usage service is being called (PXP, HDCP, proxy, etc) along
with session specific info. Thus an extra header called GSC-CS
HECI Memory Header, (C) in below diagram is prepended before
the FW specific API, (D).
- Thus, the structural layout of the request submitted would
need to look like the diagram below (for non-priv PXP).
- In the diagram, the common helper for HDCP, (GSC-Sw-Proxy) and
PXP (i.e. new function intel_gsc_uc_heci_cmd_emit_mtl_header)
will populate blob (C) while additional helpers, different for
PPGGTT (this patch) vs GGTT (HDCP series) will populate
blobs (A) and (B) below.
___
(A) | MI_BATCH_BUFFER_START (ppgtt, batchbuff-addr, ...) |
| | |
|_| |
| (B)| GSC_HECI_CMD_PKT (pkt-addr-in, pkt-size-in,| |
|| pkt-addr-out, pkt-size-out) |
|| MI_BATCH_BUFFER_END| | |
||| | |
| | |
|_| |
|
-
|
\|/
__V___
| _|
|(C)| ||
| | struct intel_gsc_mtl_header { ||
| | validity marker ||
| | heci_clent_id ||
| | ... ||
| | }||
| |___||
|(D)| ||
| | struct gsc_fw_specific_api_foobar { ||
| | ... ||
| | For an example, see ||
| | 'struct pxp43_create_arb_in' at ||
| | intel_pxp_cmd_interface_43.h ||
| | ||
| | } ||
| | Struture depends on command type ||
| | struct gsc_fw_specific_api_foobar { ||
| |___||
||
That said, this patch provides basic helpers but leaves the
PXP subsystem (i.e. the caller) to handle (D) and everything
else such as input/output size verification or handling the
responses from security firmware (for example, requiring a retry).
Signed-off-by: Alan Previn
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
.../i
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/rc6: throw out set() wrapper
== Series Details ==
Series: drm/i915/rc6: throw out set() wrapper
URL : https://patchwork.freedesktop.org/series/116817/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13041 -> Patchwork_116817v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/index.html
Participating hosts (37 -> 36)
--
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116817v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@hugepages:
- {bat-mtlp-8}: NOTRUN -> [DMESG-FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/bat-mtlp-8/igt@i915_selftest@l...@hugepages.html
Known issues
Here are the changes found in Patchwork_116817v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][2] -> [DMESG-FAIL][3] ([i915#5334])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
Possible fixes
* igt@gem_exec_parallel@engines@basic:
- {bat-mtlp-8}: [FAIL][4] -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-mtlp-8/igt@gem_exec_parallel@engi...@basic.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/bat-mtlp-8/igt@gem_exec_parallel@engi...@basic.html
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [ABORT][6] ([i915#4983]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-bsw-n3050: [DMESG-WARN][8] ([i915#1982]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/fi-bsw-n3050/igt@i915_susp...@basic-s2idle-without-i915.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/fi-bsw-n3050/igt@i915_susp...@basic-s2idle-without-i915.html
Warnings
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-FAIL][10] ([i915#6997]) -> [DMESG-FAIL][11]
([i915#6367] / [i915#7996])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
Build changes
-
* Linux: CI_DRM_13041 -> Patchwork_116817v1
CI-20190529: 20190529
CI_DRM_13041: a172f81b6b3534fd9e5c1e0f25764fceabdd8343 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116817v1: a172f81b6b3534fd9e5c1e0f25764fceabdd8343 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
5df3ab695ba2 drm/i915/rc6: throw out set() wrapper
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/index.html
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/rc6: throw out set() wrapper
== Series Details == Series: drm/i915/rc6: throw out set() wrapper URL : https://patchwork.freedesktop.org/series/116817/ State : warning == Summary == Error: dim checkpatch failed df045eca0cc1 drm/i915/rc6: throw out set() wrapper -:38: WARNING:LONG_LINE_COMMENT: line length of 104 exceeds 100 columns #38: FILE: drivers/gpu/drm/i915/gt/intel_rc6.c:73: + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ total: 0 errors, 1 warnings, 0 checks, 298 lines checked
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mtl: Set has_llc=0
On Thu, Apr 20, 2023 at 02:49:16PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/mtl: Set has_llc=0
> URL : https://patchwork.freedesktop.org/series/116747/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_13033_full -> Patchwork_116747v1_full
>
>
> Summary
> ---
>
> **SUCCESS**
Applied to drm-intel-gt-next. Thanks for the patch and reviews.
Matt
>
> No regressions found.
>
>
>
> Participating hosts (7 -> 7)
> --
>
> No changes in participating hosts
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_116747v1_full:
>
> ### IGT changes ###
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
> - {shard-rkl}:[PASS][1] -> [ABORT][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13033/shard-rkl-2/igt@kms_rotation_...@sprite-rotation-90-pos-100-0.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116747v1/shard-rkl-6/igt@kms_rotation_...@sprite-rotation-90-pos-100-0.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_116747v1_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@i915_suspend@debugfs-reader:
> - shard-snb: [PASS][3] -> [DMESG-WARN][4] ([i915#5090])
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13033/shard-snb1/igt@i915_susp...@debugfs-reader.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116747v1/shard-snb5/igt@i915_susp...@debugfs-reader.html
>
> * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
> - shard-glk: [PASS][5] -> [FAIL][6] ([i915#79])
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13033/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116747v1/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
>
> * igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
> - shard-apl: [PASS][7] -> [FAIL][8] ([i915#1188])
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13033/shard-apl1/igt@kms_hdr@bpc-switch-d...@pipe-a-dp-1.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116747v1/shard-apl4/igt@kms_hdr@bpc-switch-d...@pipe-a-dp-1.html
>
> *
> igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-b-vga-1:
> - shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271]) +34 similar
> issues
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116747v1/shard-snb5/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-...@pipe-b-vga-1.html
>
> * igt@kms_psr@psr2_primary_page_flip:
> - shard-apl: NOTRUN -> [SKIP][10] ([fdo#109271]) +18 similar
> issues
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116747v1/shard-apl6/igt@kms_psr@psr2_primary_page_flip.html
>
>
> Possible fixes
>
> * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
> - {shard-rkl}:[FAIL][11] ([i915#7742]) -> [PASS][12]
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13033/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116747v1/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
>
> * igt@gem_exec_fair@basic-pace-solo@rcs0:
> - shard-apl: [FAIL][13] ([i915#2842]) -> [PASS][14]
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13033/shard-apl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116747v1/shard-apl1/igt@gem_exec_fair@basic-pace-s...@rcs0.html
>
> * igt@gen9_exec_parse@allowed-single:
> - shard-apl: [ABORT][15] ([i915#5566]) -> [PASS][16]
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13033/shard-apl7/igt@gen9_exec_pa...@allowed-single.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116747v1/shard-apl6/igt@gen9_exec_pa...@allowed-single.html
>
> * igt@i915_pm_dc@dc9-dpms:
> - {shard-tglu}: [SKIP][17] ([i915#4281]) -> [PASS][18]
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13033/shard-tglu-6/igt@i915_pm...@dc9-dpms.html
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116747v1/shard-tglu-4/igt@i915_pm...@dc9-dpms.html
>
> * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
> - {shard-dg1}:[SKIP][19] ([i915#1937]) -> [PASS][20]
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13033/shard-dg1-18/igt@i915_pm_lpsp@kms-l...@kms-lpsp-hdmi-a.html
>[2
[Intel-gfx] ✓ Fi.CI.BAT: success for Use i915 instead of dev_priv
== Series Details ==
Series: Use i915 instead of dev_priv
URL : https://patchwork.freedesktop.org/series/116816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13041 -> Patchwork_116816v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/index.html
Participating hosts (37 -> 36)
--
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116816v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [ABORT][1] ([i915#4983]) -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html
Known issues
Here are the changes found in Patchwork_116816v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-1: [PASS][3] -> [ABORT][4] ([i915#6687] / [i915#7978])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][5] ([i915#3546]) +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html
Possible fixes
* igt@gem_exec_parallel@engines@basic:
- {bat-mtlp-8}: [FAIL][6] -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-mtlp-8/igt@gem_exec_parallel@engi...@basic.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/bat-mtlp-8/igt@gem_exec_parallel@engi...@basic.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-bsw-n3050: [DMESG-WARN][8] ([i915#1982]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/fi-bsw-n3050/igt@i915_susp...@basic-s2idle-without-i915.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/fi-bsw-n3050/igt@i915_susp...@basic-s2idle-without-i915.html
Warnings
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-FAIL][10] ([i915#6997]) -> [DMESG-FAIL][11]
([i915#6367] / [i915#7996])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
Build changes
-
* Linux: CI_DRM_13041 -> Patchwork_116816v1
CI-20190529: 20190529
CI_DRM_13041: a172f81b6b3534fd9e5c1e0f25764fceabdd8343 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116816v1: a172f81b6b3534fd9e5c1e0f25764fceabdd8343 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
b2b666af4dd2 drm/i915/i915_drv: Use i915 instead of dev_priv insied the
file_priv structure
b11418a94280 drm/i915/i915_drv: Use proper parameter naming in for_each_gt()
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/index.html
Re: [Intel-gfx] [PATCH 2/2] drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure
On 21.04.2023 15:46, Andi Shyti wrote: In the process of renaming all instances of 'dev_priv' to 'i915', start using 'i915' within the 'drm_i915_file_private' structure. Signed-off-by: Andi Shyti --- Reviewed-by: Andrzej Hajda Regards Andrzej
Re: [Intel-gfx] [PATCH 1/2] drm/i915/i915_drv: Use proper parameter naming in for_each_gt()
On 21.04.2023 15:46, Andi Shyti wrote: for_each_gt() loops through engines in the GT, not in dev_priv. Because it's misleading, call it "gt__" instead of "dev_priv__". Signed-off-by: Andi Shyti With fixes mentioned by Rodrigo. Reviewed-by: Andrzej Hajda Regards Andrzej --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fe7eeafe9cff6..c16f8a3cd914f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -381,11 +381,11 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) } /* Simple iterator over all initialised engines */ -#define for_each_engine(engine__, dev_priv__, id__) \ +#define for_each_engine(engine__, gt__, id__) \ for ((id__) = 0; \ (id__) < I915_NUM_ENGINES; \ (id__)++) \ - for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) + for_each_if ((engine__) = (gt__)->engine[(id__)]) /* Iterator over subset of engines selected by mask */ #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use i915 instead of dev_priv
== Series Details ==
Series: Use i915 instead of dev_priv
URL : https://patchwork.freedesktop.org/series/116816/
State : warning
== Summary ==
Error: dim checkpatch failed
4f2ff1f3fb31 drm/i915/i915_drv: Use proper parameter naming in for_each_gt()
-:22: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#22: FILE: drivers/gpu/drm/i915/i915_drv.h:384:
+#define for_each_engine(engine__, gt__, id__) \
for ((id__) = 0; \
(id__) < I915_NUM_ENGINES; \
(id__)++) \
+ for_each_if ((engine__) = (gt__)->engine[(id__)])
-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id__' - possible
side-effects?
#22: FILE: drivers/gpu/drm/i915/i915_drv.h:384:
+#define for_each_engine(engine__, gt__, id__) \
for ((id__) = 0; \
(id__) < I915_NUM_ENGINES; \
(id__)++) \
+ for_each_if ((engine__) = (gt__)->engine[(id__)])
-:27: WARNING:SPACING: space prohibited between function name and open
parenthesis '('
#27: FILE: drivers/gpu/drm/i915/i915_drv.h:388:
+ for_each_if ((engine__) = (gt__)->engine[(id__)])
total: 1 errors, 1 warnings, 1 checks, 13 lines checked
51c8ab2e0ecd drm/i915/i915_drv: Use i915 instead of dev_priv insied the
file_priv structure
-:140: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#140: FILE: drivers/gpu/drm/i915/i915_drv.h:534:
+#define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915))
-:144: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#144: FILE: drivers/gpu/drm/i915/i915_drv.h:538:
+#define IS_IRONLAKE_M(i915) \
+ (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
-:148: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#148: FILE: drivers/gpu/drm/i915/i915_drv.h:542:
+#define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \
+INTEL_INFO(i915)->gt == 1)
-:161: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#161: FILE: drivers/gpu/drm/i915/i915_drv.h:555:
+#define IS_JSL_EHL(i915) (IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
+ IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
-:191: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#191: FILE: drivers/gpu/drm/i915/i915_drv.h:585:
+#define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \
+ (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
-:197: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#197: FILE: drivers/gpu/drm/i915/i915_drv.h:591:
+#define IS_BDW_GT3(i915) (IS_BROADWELL(i915) && \
+INTEL_INFO(i915)->gt == 3)
-:201: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#201: FILE: drivers/gpu/drm/i915/i915_drv.h:595:
+#define IS_HSW_GT3(i915) (IS_HASWELL(i915) && \
+INTEL_INFO(i915)->gt == 3)
-:203: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#203: FILE: drivers/gpu/drm/i915/i915_drv.h:597:
+#define IS_HSW_GT1(i915) (IS_HASWELL(i915) && \
+INTEL_INFO(i915)->gt == 1)
-:257: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#257: FILE: drivers/gpu/drm/i915/i915_drv.h:610:
+#define IS_SKL_GT2(i915) (IS_SKYLAKE(i915) && \
+INTEL_INFO(i915)->gt == 2)
-:259: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#259: FILE: drivers/gpu/drm/i915/i915_drv.h:612:
+#define IS_SKL_GT3(i915) (IS_SKYLAKE(i915) && \
+INTEL_INFO(i915)->gt == 3)
-:261: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#261: FILE: drivers/gpu/drm/i915/i915_drv.h:614:
+#define IS_SKL_GT4(i915) (IS_SKYLAKE(i915) && \
+INTEL_INFO(i915)->gt == 4)
-:263: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#263: FILE: drivers/gpu/drm/i915/i915_drv.h:616:
+#define IS_KBL_GT2(i915) (IS_KABYLAKE(i915) && \
+INTEL_INFO(i915)->gt == 2)
-:265: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#265: FILE: drivers/gpu/drm/i915/i915_drv.h:618:
+#define IS_KBL_GT3(i915) (IS_KABYLAKE(i915) && \
+INTEL_INFO(i915)->gt == 3)
-:271: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#271: FILE: drivers/gpu/drm/i915/i915_drv.h:624:
+#define IS_CFL_GT2(i915) (IS_COFFEELAKE(i915) && \
+INTEL_INFO(i915)->gt == 2)
-:273: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#273: FILE: drivers/gpu/drm/i915/i915_drv.h:626:
+#define IS_CFL_GT3(i915) (IS_COFFEELAKE(i915) && \
+INTEL_INFO(i915)->gt
Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/mtl: Extend Wa_22011802037 to MTL A-step
On Fri, Apr 21, 2023 at 08:05:50AM -0700, Matt Roper wrote:
> On Wed, Apr 19, 2023 at 02:40:33PM -0700, Matt Atwood wrote:
> > On Tue, Apr 18, 2023 at 03:04:45PM -0700, Radhakrishna Sripada wrote:
> > > From: Madhumitha Tolakanahalli Pradeep
> > >
> > >
> > > Wa_22011802037 was being applied to all graphics_ver 11 & 12. This patch
> > > updates the if statement to apply the W/A to right platforms and extends
> > > it to MTL-M:A step.
> > >
> > Bspec: 53509
> > > v1.1: Fix checkpatch warning.
> > > v2: Change the check to reflect the wa at other palces(Lucas)
> > s/palces/places.
> > >
> > > Cc: Lucas De Marchi
> > > Cc: Umesh Nerlige Ramappa
> > With that.
> > Reviewed-by: Matt Atwood
> > > Signed-off-by: Madhumitha Tolakanahalli Pradeep
> > >
> > > Signed-off-by: Radhakrishna Sripada
>
> It doesn't look like this patch is complete? It's only changing one
> condition for Wa_22011802037, even though there are several in the code.
> From a quick grep, you're still missing updates for at least
> guc_ctl_wa_flags, execlists_reset_prepare, and __intel_engine_stop_cs.
Actually, scratch that. Those other spots already have a MTL clause as
part of the condition. But in that case it means the commit message
here is inaccurate; you're not extending this workaround to MTL a-step
because that already happened on a previous patch. You're just
providing a fix for an incomplete implementation that happened earlier.
The commit message should be explaining that.
>
> Since this workaround is a complicated one that touches so many areas of
> the code, and has a complex platform list, it's probably time to factor
> the condition out into a needs_wa_22011802037() helper or something.
I still suggest doing this, especially since we've clearly screwed up
the handling of this workaround at least once already.
Matt
>
>
> Matt
>
> > > ---
> > > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 ++--
> > > 1 file changed, 6 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > index 88e881b100cf..ee3e8352637f 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > @@ -1629,16 +1629,16 @@ static void guc_reset_state(struct intel_context
> > > *ce, u32 head, bool scrub)
> > >
> > > static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
> > > {
> > > - if (!IS_GRAPHICS_VER(engine->i915, 11, 12))
> > > - return;
> > > -
> > > - intel_engine_stop_cs(engine);
> > > -
> > > /*
> > >* Wa_22011802037: In addition to stopping the cs, we need
> > >* to wait for any pending mi force wakeups
> > >*/
> > > - intel_engine_wait_for_pending_mi_fw(engine);
> > > + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > > + (GRAPHICS_VER(engine->i915) >= 11 &&
> > > + GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
> > > + intel_engine_stop_cs(engine);
> > > + intel_engine_wait_for_pending_mi_fw(engine);
> > > + }
> > > }
> > >
> > > static void guc_reset_nop(struct intel_engine_cs *engine)
> > > --
> > > 2.34.1
> > >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/mtl: Extend Wa_22011802037 to MTL A-step
On Wed, Apr 19, 2023 at 02:40:33PM -0700, Matt Atwood wrote:
> On Tue, Apr 18, 2023 at 03:04:45PM -0700, Radhakrishna Sripada wrote:
> > From: Madhumitha Tolakanahalli Pradeep
> >
> >
> > Wa_22011802037 was being applied to all graphics_ver 11 & 12. This patch
> > updates the if statement to apply the W/A to right platforms and extends
> > it to MTL-M:A step.
> >
> Bspec: 53509
> > v1.1: Fix checkpatch warning.
> > v2: Change the check to reflect the wa at other palces(Lucas)
> s/palces/places.
> >
> > Cc: Lucas De Marchi
> > Cc: Umesh Nerlige Ramappa
> With that.
> Reviewed-by: Matt Atwood
> > Signed-off-by: Madhumitha Tolakanahalli Pradeep
> >
> > Signed-off-by: Radhakrishna Sripada
It doesn't look like this patch is complete? It's only changing one
condition for Wa_22011802037, even though there are several in the code.
>From a quick grep, you're still missing updates for at least
guc_ctl_wa_flags, execlists_reset_prepare, and __intel_engine_stop_cs.
Since this workaround is a complicated one that touches so many areas of
the code, and has a complex platform list, it's probably time to factor
the condition out into a needs_wa_22011802037() helper or something.
Matt
> > ---
> > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 ++--
> > 1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 88e881b100cf..ee3e8352637f 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -1629,16 +1629,16 @@ static void guc_reset_state(struct intel_context
> > *ce, u32 head, bool scrub)
> >
> > static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
> > {
> > - if (!IS_GRAPHICS_VER(engine->i915, 11, 12))
> > - return;
> > -
> > - intel_engine_stop_cs(engine);
> > -
> > /*
> > * Wa_22011802037: In addition to stopping the cs, we need
> > * to wait for any pending mi force wakeups
> > */
> > - intel_engine_wait_for_pending_mi_fw(engine);
> > + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > + (GRAPHICS_VER(engine->i915) >= 11 &&
> > +GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
> > + intel_engine_stop_cs(engine);
> > + intel_engine_wait_for_pending_mi_fw(engine);
> > + }
> > }
> >
> > static void guc_reset_nop(struct intel_engine_cs *engine)
> > --
> > 2.34.1
> >
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Restore HSW/BDW PSR1
== Series Details ==
Series: drm/i915/psr: Restore HSW/BDW PSR1
URL : https://patchwork.freedesktop.org/series/116814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13041 -> Patchwork_116814v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/index.html
Participating hosts (37 -> 36)
--
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116814v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@hugepages:
- {bat-mtlp-8}: NOTRUN -> [DMESG-FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/bat-mtlp-8/igt@i915_selftest@l...@hugepages.html
Known issues
Here are the changes found in Patchwork_116814v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@slpc:
- bat-rplp-1: [PASS][2] -> [DMESG-FAIL][3] ([i915#6367] /
[i915#7913])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-rplp-1/igt@i915_selftest@l...@slpc.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/bat-rplp-1/igt@i915_selftest@l...@slpc.html
Possible fixes
* igt@gem_exec_parallel@engines@basic:
- {bat-mtlp-8}: [FAIL][4] -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-mtlp-8/igt@gem_exec_parallel@engi...@basic.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/bat-mtlp-8/igt@gem_exec_parallel@engi...@basic.html
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [ABORT][6] ([i915#4983]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-FAIL][8] ([i915#6997]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-bsw-n3050: [DMESG-WARN][10] ([i915#1982]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/fi-bsw-n3050/igt@i915_susp...@basic-s2idle-without-i915.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/fi-bsw-n3050/igt@i915_susp...@basic-s2idle-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
Build changes
-
* Linux: CI_DRM_13041 -> Patchwork_116814v1
CI-20190529: 20190529
CI_DRM_13041: a172f81b6b3534fd9e5c1e0f25764fceabdd8343 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116814v1: a172f81b6b3534fd9e5c1e0f25764fceabdd8343 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
6290e5537e6c drm/i915/psr: Re-enable PSR1 on hdw/bdw
861574c93411 drm/i915/psr: Allow PSR with sprite enabled on hsw/bdw
ba48e7937919 drm/i915/psr: Don't skip both TP1 and TP2/3 on hsw/bdw
3b4260f2841e drm/i915/psr: Do no mask display register writes on hsw/bdw
2e3089bc0e2e drm/i915/psr: Implement WaPsrDPRSUnmaskVBlankInSRD:hsw
fadd5c87e0ea drm/i915/psr: Implement WaPsrDPAMaskVBlankInSRD:hsw
6f0f18e486f3 drm/i915/psr: Restore PSR interrupt handler for HSW
8798980ec12f drm/i915/psr: HSW/BDW have no PSR2
32acd6eb4c9a drm/i915/psr: Bring back HSW/BDW PSR AUX CH registers/setup
f4a0bc562ae5 drm/i915/psr: Reintroduce HSW PSR1 registers
7eec7dfff210 drm/i915/psr: Wrap PSR1 register with functions
74286a1ff473 drm/i915/psr: Fix BDW PSR AUX CH data register offsets
1ed8b3a87eb0 drm/i915: Re-init clock gating on coming out of PC8+
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116814v1/index.html
Re: [Intel-gfx] [PATCH] drm/i915/rc6: throw out set() wrapper
On Fri, Apr 21, 2023 at 04:59:48PM +0300, Jani Nikula wrote:
> Remove useless indirection that's just misdirection for the readers.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_rc6.c | 157 ++--
> 1 file changed, 76 insertions(+), 81 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
> b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 8f3cd68d14f8..908a3d0f2343 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -53,11 +53,6 @@ static struct drm_i915_private *rc6_to_i915(struct
> intel_rc6 *rc)
> return rc6_to_gt(rc)->i915;
> }
>
> -static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
> -{
> - intel_uncore_write_fw(uncore, reg, val);
> -}
> -
> static void gen11_rc6_enable(struct intel_rc6 *rc6)
> {
> struct intel_gt *gt = rc6_to_gt(rc6);
> @@ -72,19 +67,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
>*/
> if (!intel_uc_uses_guc_rc(>->uc)) {
> /* 2b: Program RC6 thresholds.*/
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> - set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 <<
> 16 | 85);
> + intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
>
> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 *
> 1280ns */
> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL,
> 125000); /* 12500 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /*
> 25 * 1280ns */
> for_each_engine(engine, rc6_to_gt(rc6), id)
> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> + intel_uncore_write_fw(uncore,
> RING_MAX_IDLE(engine->mmio_base), 10);
>
> - set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
> + intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
>
> - set(uncore, GEN6_RC_SLEEP, 0);
> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
>
> - set(uncore, GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 5); /*
> 50/125ms per EI */
> }
>
> /*
> @@ -105,8 +100,8 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
>* Broadwell+, To be conservative, we want to factor in a context
>* switch on top (due to ksoftirqd).
>*/
> - set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
> - set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
> + intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
> + intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
>
> /* 3a: Enable RC6
>*
> @@ -141,7 +136,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
> VDN_MFX_POWERGATE_ENABLE(i));
> }
>
> - set(uncore, GEN9_PG_ENABLE, pg_enable);
> + intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, pg_enable);
> }
>
> static void gen9_rc6_enable(struct intel_rc6 *rc6)
> @@ -152,26 +147,26 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
>
> /* 2b: Program RC6 thresholds.*/
> if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) {
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> - set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 <<
> 16 | 85);
> + intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
> } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
> /*
>* WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
>* when CPG is enabled
>*/
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 <<
> 16);
> } else {
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 <<
> 16);
> }
>
> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /*
> 12500 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 *
> 1280ns */
> for_each_engine(engine, rc6_to_gt(rc6), id)
> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base),
> 10);
>
> - set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
> + intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
>
> -
Re: [Intel-gfx] [PATCH 2/2] drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure
On Fri, Apr 21, 2023 at 10:07:28AM -0400, Rodrigo Vivi wrote: > On Fri, Apr 21, 2023 at 03:46:54PM +0200, Andi Shyti wrote: > > In the process of renaming all instances of 'dev_priv' to 'i915', > > start using 'i915' within the 'drm_i915_file_private' structure. > > The patch looks good but the commit message seems off to me... Will rephrase. > One thing we need to take care with mass conversions of dev_priv > to i915 is to ensure we are not converting the implicit declarations, > since we want to kill that. But on a quick glance it looks fine. > > Did you generated this with full s/dev_priv/i915 in i915_drv.h? Yes, I did such swap in i915_drv.h but I checked each line not to break anything. In this file it's OK to do a /dev_priv/i915/ change. It will be different with i915_irq.h where dev_priv is embedded in the define. I there is anything off it wouldn't have compiled and anyway, CI will warn. Thanks, Rodrigo! Andi
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Restore HSW/BDW PSR1
== Series Details == Series: drm/i915/psr: Restore HSW/BDW PSR1 URL : https://patchwork.freedesktop.org/series/116814/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./ar
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: Restore HSW/BDW PSR1
== Series Details == Series: drm/i915/psr: Restore HSW/BDW PSR1 URL : https://patchwork.freedesktop.org/series/116814/ State : warning == Summary == Error: dim checkpatch failed 142f6d9f694b drm/i915: Re-init clock gating on coming out of PC8+ fceac0743cce drm/i915/psr: Fix BDW PSR AUX CH data register offsets -:26: WARNING:LONG_LINE_COMMENT: line length of 111 exceeds 100 columns #26: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:84: +#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */ total: 0 errors, 1 warnings, 0 checks, 8 lines checked f2797b5b7fb7 drm/i915/psr: Wrap PSR1 register with functions -:142: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #142: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1242: + intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder)) & EDP_PSR_ENABLE); total: 0 errors, 1 warnings, 0 checks, 208 lines checked d3088201e30c drm/i915/psr: Reintroduce HSW PSR1 registers e70295cefd48 drm/i915/psr: Bring back HSW/BDW PSR AUX CH registers/setup 40c55dcdbc37 drm/i915/psr: HSW/BDW have no PSR2 988e78a2917e drm/i915/psr: Restore PSR interrupt handler for HSW db43341eea49 drm/i915/psr: Implement WaPsrDPAMaskVBlankInSRD:hsw 2117b84e684f drm/i915/psr: Implement WaPsrDPRSUnmaskVBlankInSRD:hsw -:13: WARNING:TYPO_SPELLING: 'correspoding' may be misspelled - perhaps 'corresponding'? #13: in case it matters in some cases, and the correspoding bit total: 0 errors, 1 warnings, 0 checks, 20 lines checked 78f16cfafe7a drm/i915/psr: Do no mask display register writes on hsw/bdw 200f043d0bf0 drm/i915/psr: Don't skip both TP1 and TP2/3 on hsw/bdw 1b6709cbd4de drm/i915/psr: Allow PSR with sprite enabled on hsw/bdw 41a11c91c60f drm/i915/psr: Re-enable PSR1 on hdw/bdw
Re: [Intel-gfx] [PATCH 1/2] drm/i915/i915_drv: Use proper parameter naming in for_each_gt()
Hi Rodrigo, On Fri, Apr 21, 2023 at 10:05:07AM -0400, Rodrigo Vivi wrote: > On Fri, Apr 21, 2023 at 10:00:29AM -0400, Rodrigo Vivi wrote: > > On Fri, Apr 21, 2023 at 03:46:53PM +0200, Andi Shyti wrote: > > > for_each_gt() loops through engines in the GT, not in dev_priv. > > > > typo here? ^ > > > > with that fixed: > > oh, in the commit subject as well... The power of habit! Thanks! Andi
Re: [Intel-gfx] [PATCH v7 2/7] lib/ref_tracker: improve printing stats
On 21.04.2023 16:21, Eric Dumazet wrote:
On Fri, Apr 21, 2023 at 1:35 PM Andrzej Hajda wrote:
In case the library is tracking busy subsystem, simply
printing stack for every active reference will spam log
with long, hard to read, redundant stack traces. To improve
readabilty following changes have been made:
- reports are printed per stack_handle - log is more compact,
- added display name for ref_tracker_dir - it will differentiate
multiple subsystems,
- stack trace is printed indented, in the same printk call,
- info about dropped references is printed as well.
Signed-off-by: Andrzej Hajda
Reviewed-by: Andi Shyti
---
include/linux/ref_tracker.h | 15 ++--
lib/ref_tracker.c | 90 +++--
2 files changed, 91 insertions(+), 14 deletions(-)
diff --git a/include/linux/ref_tracker.h b/include/linux/ref_tracker.h
index 87a92f2bec1b88..fc9ef9952f01fd 100644
--- a/include/linux/ref_tracker.h
+++ b/include/linux/ref_tracker.h
@@ -17,12 +17,19 @@ struct ref_tracker_dir {
booldead;
struct list_headlist; /* List of active trackers */
struct list_headquarantine; /* List of dead trackers */
+ charname[32];
#endif
};
#ifdef CONFIG_REF_TRACKER
-static inline void ref_tracker_dir_init(struct ref_tracker_dir *dir,
- unsigned int quarantine_count)
+
+/* Temporary allow two and three arguments, until consumers are converted */
+#define ref_tracker_dir_init(_d, _q, args...) _ref_tracker_dir_init(_d, _q,
##args, #_d)
+#define _ref_tracker_dir_init(_d, _q, _n, ...) __ref_tracker_dir_init(_d, _q,
_n)
+
We only have four callers of ref_tracker_dir_init() .
Why not simply add a name on them, and avoid this magic ?
If this can be done in one patch, that's great.
Regards
Andrzej
Re: [Intel-gfx] [PATCH v7 1/7] lib/ref_tracker: add unlocked leak print helper
On Fri, Apr 21, 2023 at 1:35 PM Andrzej Hajda wrote: > > To have reliable detection of leaks, caller must be able to check under the > same > lock both: tracked counter and the leaks. dir.lock is natural candidate for > such > lock and unlocked print helper can be called with this lock taken. > As a bonus we can reuse this helper in ref_tracker_dir_exit. > > Signed-off-by: Andrzej Hajda > Reviewed-by: Andi Shyti > --- SGTM, thanks. Reviewed-by: Eric Dumazet
Re: [Intel-gfx] [PATCH v7 4/7] lib/ref_tracker: remove warnings in case of allocation failure
On Fri, Apr 21, 2023 at 1:35 PM Andrzej Hajda wrote: > > Library can handle allocation failures. To avoid allocation warnings > __GFP_NOWARN has been added everywhere. Moreover GFP_ATOMIC has been > replaced with GFP_NOWAIT in case of stack allocation on tracker free > call. > > Signed-off-by: Andrzej Hajda > Reviewed-by: Andi Shyti > --- Reviewed-by: Eric Dumazet Thanks.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/display & drm/i915: more struct drm_edid conversions
== Series Details ==
Series: drm/display & drm/i915: more struct drm_edid conversions
URL : https://patchwork.freedesktop.org/series/116813/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13041 -> Patchwork_116813v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/index.html
Participating hosts (37 -> 36)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_116813v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][1] ([i915#3546]) +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html
Possible fixes
* igt@gem_exec_parallel@engines@basic:
- {bat-mtlp-8}: [FAIL][2] -> [PASS][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-mtlp-8/igt@gem_exec_parallel@engi...@basic.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/bat-mtlp-8/igt@gem_exec_parallel@engi...@basic.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-bsw-n3050: [DMESG-WARN][4] ([i915#1982]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/fi-bsw-n3050/igt@i915_susp...@basic-s2idle-without-i915.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/fi-bsw-n3050/igt@i915_susp...@basic-s2idle-without-i915.html
Warnings
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-FAIL][6] ([i915#6997]) -> [DMESG-FAIL][7]
([i915#6367] / [i915#7996])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
Build changes
-
* Linux: CI_DRM_13041 -> Patchwork_116813v1
CI-20190529: 20190529
CI_DRM_13041: a172f81b6b3534fd9e5c1e0f25764fceabdd8343 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116813v1: a172f81b6b3534fd9e5c1e0f25764fceabdd8343 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
06b49e8d44ec drm/i915/display: switch the rest of the connectors to struct
drm_edid
7a23607a15a2 drm/display/dp_mst: convert to struct drm_edid
72c89e375955 drm/edid: make drm_edid_duplicate() safe to call with NULL
parameter
a73fb9511920 drm/i915/lvds: switch to drm_edid_read_switcheroo()
965b828ff6ce drm/edid: add drm_edid_read_switcheroo()
2b018fb0546b drm/i915/sdvo: stop caching has_hdmi_audio in struct intel_sdvo
fb9b63218d7f drm/i915/sdvo: stop caching has_hdmi_monitor in struct intel_sdvo
a30cbde3e239 drm/i915/hdmi: stop caching has_hdmi_sink in struct intel_hdmi
e2747783cf4e drm/i915/hdmi: stop caching has_audio in struct intel_hdmi
36c08f927f1a drm/i915/dp: stop caching has_hdmi_sink in struct intel_dp
3bf07467679e drm/i915/dp: stop caching has_audio in struct intel_dp
5a4029334bdf drm/display/dp_mst: drop has_audio from struct drm_dp_mst_port
9f8cc0d0be0f drm/edid: parse display info has_audio similar to is_hdmi
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v1/index.html
Re: [Intel-gfx] [PATCH v7 2/7] lib/ref_tracker: improve printing stats
On Fri, Apr 21, 2023 at 1:35 PM Andrzej Hajda wrote:
>
> In case the library is tracking busy subsystem, simply
> printing stack for every active reference will spam log
> with long, hard to read, redundant stack traces. To improve
> readabilty following changes have been made:
> - reports are printed per stack_handle - log is more compact,
> - added display name for ref_tracker_dir - it will differentiate
> multiple subsystems,
> - stack trace is printed indented, in the same printk call,
> - info about dropped references is printed as well.
>
> Signed-off-by: Andrzej Hajda
> Reviewed-by: Andi Shyti
> ---
> include/linux/ref_tracker.h | 15 ++--
> lib/ref_tracker.c | 90
> +++--
> 2 files changed, 91 insertions(+), 14 deletions(-)
>
> diff --git a/include/linux/ref_tracker.h b/include/linux/ref_tracker.h
> index 87a92f2bec1b88..fc9ef9952f01fd 100644
> --- a/include/linux/ref_tracker.h
> +++ b/include/linux/ref_tracker.h
> @@ -17,12 +17,19 @@ struct ref_tracker_dir {
> booldead;
> struct list_headlist; /* List of active trackers */
> struct list_headquarantine; /* List of dead trackers */
> + charname[32];
> #endif
> };
>
> #ifdef CONFIG_REF_TRACKER
> -static inline void ref_tracker_dir_init(struct ref_tracker_dir *dir,
> - unsigned int quarantine_count)
> +
> +/* Temporary allow two and three arguments, until consumers are converted */
> +#define ref_tracker_dir_init(_d, _q, args...) _ref_tracker_dir_init(_d, _q,
> ##args, #_d)
> +#define _ref_tracker_dir_init(_d, _q, _n, ...) __ref_tracker_dir_init(_d,
> _q, _n)
> +
We only have four callers of ref_tracker_dir_init() .
Why not simply add a name on them, and avoid this magic ?
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/display & drm/i915: more struct drm_edid conversions
== Series Details == Series: drm/display & drm/i915: more struct drm_edid conversions URL : https://patchwork.freedesktop.org/series/116813/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [BUG?] INFO: rcu_sched detected expedited stalls on CPUs/tasks: { 0-.... } 3 jiffies s: 309 root: 0x1/.
Hi again, everyone.
So, while preparing to file the bug report with the requested
information, I got a trace completely unrelated to DRM (on a swapon
call, it seems).
[4.868340] rcu: INFO: rcu_sched detected expedited stalls on
CPUs/tasks: { 4- } 3 jiffies s: 265 root: 0x10/.
[4.868349] rcu: blocking rcu_node structures (internal RCU debug):
[4.868351] Sending NMI from CPU 3 to CPUs 4:
[4.868355] NMI backtrace for cpu 4
[4.868357] CPU: 4 PID: 462 Comm: swapon Not tainted 6.3.0-rc6-debug+ #57
[4.868359] Hardware name: Apple Inc.
Macmini6,2/Mac-F65AE981FFA204ED, BIOS 429.0.0.0.0 03/18/2022
[4.868360] RIP: 0010:zram_submit_bio+0x57c/0x940
[4.868365] Code: 04 4c 01 f0 48 8d 48 08 f0 48 0f ba 68 08 0d 0f
82 80 00 00 00 4c 89 ef e8 01 eb ff ff 49 8b 45 00 4a 8d 44 30 09 f0
80 20 df 48 ff 45 00 48 81 eb 00 10 00 00 41 83 c4 01 48 81 fb ff
0f 00
[4.868366] RSP: 0018:8881057dbcd8 EFLAGS: 0246
[4.868368] RAX: c90001c186d9 RBX: 3e893000 RCX: c90001c186d8
[4.868369] RDX: c90001c186d0 RSI: RDI: 88810083b400
[4.868369] RBP: 88810083b470 R08: 00027e40 R09: 00025850
[4.868370] R10: 0014b212 R11: 88810ba03180 R12: 000c176d
[4.868371] R13: 88810083b400 R14: 00c176d0 R15:
[4.868372] FS: 7fbd8f8ce800() GS:88826610()
knlGS:
[4.868373] CS: 0010 DS: ES: CR0: 80050033
[4.868374] CR2: 563005371000 CR3: 00010355c003 CR4: 001706e0
[4.868375] Call Trace:
[4.868377]
[4.868378] ? block_read_full_folio+0x23e/0x2e0
[4.868383] ? kmem_cache_alloc+0x1b/0x110
[4.868385] ? mempool_alloc+0x37/0x140
[4.868388] ? pcpu_block_update_hint_alloc+0xce/0x2f0
[4.868390] __submit_bio+0x41/0xd0
[4.868394] submit_bio_noacct_nocheck+0xc4/0x2b0
[4.868396] blk_next_bio+0x55/0x70
[4.868398] __blkdev_issue_discard+0xc8/0x180
[4.868401] blkdev_issue_discard+0x3c/0x80
[4.868403] __x64_sys_swapon+0xb71/0x1120
[4.868407] do_syscall_64+0x2b/0x50
[4.868410] entry_SYSCALL_64_after_hwframe+0x46/0xb0
[4.868414] RIP: 0033:0x7fbd8f712d5b
[4.868416] Code: 73 01 c3 48 8b 0d bd 30 0e 00 f7 d8 64 89 01 48
83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa b8 a7 00 00
00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 8d 30 0e 00 f7 d8 64 89
01 48
[4.868417] RSP: 002b:7ffcaf9a3448 EFLAGS: 0246 ORIG_RAX:
00a7
[4.868418] RAX: ffda RBX: 00018064 RCX: 7fbd8f712d5b
[4.868419] RDX: 00018064 RSI: 00018064 RDI: 56300535fb10
[4.868420] RBP: 7ffcaf9a3530 R08: 00014b213000 R09: 7fbd8f7f70f0
[4.868420] R10: 1000 R11: 0246 R12: 56300535fb10
[4.868421] R13: 0064 R14: 7ffcaf9a3530 R15:
[4.868423]
Could it be that RCU is reporting expedited stalls too eagerly? And,
if so, why only on this machine?
[Intel-gfx] [PATCH] video/hdmi: minor fixes for *_infoframe_init functions
Multiple hdmi_*_infoframe_init() functions that initialize different
types of hdmi infoframes only return default 0 value (contrary to their
descriptions). Yet these functions are still checked against possible
errors in case of failure.
This patch removes redundant checks for errors in calls to following
functions:
- hdmi_spd_infoframe_init
- hdmi_audio_infoframe_init
- hdmi_vendor_infoframe_init
- hdmi_drm_infoframe_init
Also, change their return types to void and fix descriptions.
Fixes: 2c676f378edb ("[media] hdmi: added unpack and logging functions for
InfoFrames")
Signed-off-by: Nikita Zhandarovich
---
drivers/gpu/drm/display/drm_hdmi_helper.c | 5 +---
drivers/gpu/drm/drm_edid.c| 5 +---
drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +--
drivers/gpu/drm/mediatek/mtk_hdmi.c | 14 ++
drivers/gpu/drm/radeon/r600_hdmi.c| 6 +
drivers/gpu/drm/sti/sti_hdmi.c| 6 +
drivers/gpu/drm/tegra/hdmi.c | 7 +
drivers/gpu/drm/tegra/sor.c | 6 +
drivers/gpu/drm/vc4/vc4_hdmi.c| 7 +
drivers/video/hdmi.c | 44 ++-
include/linux/hdmi.h | 8 +++---
11 files changed, 23 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_hdmi_helper.c
b/drivers/gpu/drm/display/drm_hdmi_helper.c
index faf5e9efa7d3..ce7038a3a183 100644
--- a/drivers/gpu/drm/display/drm_hdmi_helper.c
+++ b/drivers/gpu/drm/display/drm_hdmi_helper.c
@@ -27,7 +27,6 @@ int drm_hdmi_infoframe_set_hdr_metadata(struct
hdmi_drm_infoframe *frame,
{
struct drm_connector *connector;
struct hdr_output_metadata *hdr_metadata;
- int err;
if (!frame || !conn_state)
return -EINVAL;
@@ -47,9 +46,7 @@ int drm_hdmi_infoframe_set_hdr_metadata(struct
hdmi_drm_infoframe *frame,
connector->hdr_sink_metadata.hdmi_type1.eotf))
DRM_DEBUG_KMS("Unknown EOTF %d\n",
hdr_metadata->hdmi_metadata_type1.eotf);
- err = hdmi_drm_infoframe_init(frame);
- if (err < 0)
- return err;
+ hdmi_drm_infoframe_init(frame);
frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 261a62e15934..c268148502d6 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -7159,7 +7159,6 @@ drm_hdmi_vendor_infoframe_from_display_mode(struct
hdmi_vendor_infoframe *frame,
*/
bool has_hdmi_infoframe = connector ?
connector->display_info.has_hdmi_infoframe : false;
- int err;
if (!frame || !mode)
return -EINVAL;
@@ -7167,9 +7166,7 @@ drm_hdmi_vendor_infoframe_from_display_mode(struct
hdmi_vendor_infoframe *frame,
if (!has_hdmi_infoframe)
return -EINVAL;
- err = hdmi_vendor_infoframe_init(frame);
- if (err < 0)
- return err;
+ hdmi_vendor_infoframe_init(frame);
/*
* Even if it's not absolutely necessary to send the infoframe
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index c0ce6d3dc505..2190dcf68f7f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -778,9 +778,9 @@ intel_hdmi_compute_spd_infoframe(struct intel_encoder
*encoder,
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
if (IS_DGFX(i915))
- ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
+ hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
else
- ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
+ hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
if (drm_WARN_ON(encoder->base.dev, ret))
return false;
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 0a8e0a13f516..75899e4a011f 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -995,12 +995,7 @@ static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi
*hdmi,
u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE];
ssize_t err;
- err = hdmi_spd_infoframe_init(&frame, vendor, product);
- if (err < 0) {
- dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
- err);
- return err;
- }
+ hdmi_spd_infoframe_init(&frame, vendor, product);
err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
if (err < 0) {
@@ -1018,12 +1013,7 @@ static int mtk_hdmi_setup_audio_infoframe(struct
mtk_hdmi *hdmi)
u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
ssize_t er
[Intel-gfx] [PATCH] drm/i915: Fix memory leaks in i915 selftests
Fixes: c3bfba9a2225 ("drm/i915: Check for integer truncation on scatterlist
creation")
Signed-off-by: Cong Liu
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 5361ce70d3f2..154801f1c468 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -69,8 +69,10 @@ static int fake_get_pages(struct drm_i915_gem_object *obj)
rem = round_up(obj->base.size, BIT(31)) >> 31;
/* restricted by sg_alloc_table */
- if (overflows_type(rem, unsigned int))
+ if (overflows_type(rem, unsigned int)) {
+ kfree(pages);
return -E2BIG;
+ }
if (sg_alloc_table(pages, rem, GFP)) {
kfree(pages);
--
2.34.1
No virus found
Checked by Hillstone Network AntiVirus
[Intel-gfx] [PATCH] drm/i915/dp: prevent potential div-by-zero
drm_dp_dsc_sink_max_slice_count() may return 0 if something goes
wrong on the part of the DSC sink and its DPCD register. This null
value may be later used as a divisor in intel_dsc_compute_params(),
which will lead to an error.
In the unlikely event that this issue occurs, fix it by testing the
return value of drm_dp_dsc_sink_max_slice_count() against zero.
Found by Linux Verification Center (linuxtesting.org) with static
analysis tool SVACE.
Fixes: a4a15c80 ("drm/i915/dp: Compute DSC pipe config in atomic check")
Signed-off-by: Nikita Zhandarovich
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 62cbab7402e9..c1825f8f885c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1533,6 +1533,11 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
pipe_config->dsc.slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
+ if (!pipe_config->dsc.slice_count) {
+ drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count
%d\n",
+ pipe_config->dsc.slice_count);
+ return -EINVAL;
+ }
} else {
u16 dsc_max_output_bpp = 0;
u8 dsc_dp_slice_count;
--
2.25.1
Re: [Intel-gfx] [PATCH v7 0/7] drm/i915: use ref_tracker library for tracking wakerefs
On Fri, 21 Apr 2023 13:35:04 +0200 Andrzej Hajda wrote: > Gently ping for network developers, could you look at ref_tracker patches, > as the ref_tracker library was developed for network. Putting Eric in the To: field, I know email so hard and confusing...
Re: [Intel-gfx] [PATCH 2/2] drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure
On Fri, Apr 21, 2023 at 03:46:54PM +0200, Andi Shyti wrote: > In the process of renaming all instances of 'dev_priv' to 'i915', > start using 'i915' within the 'drm_i915_file_private' structure. The patch looks good but the commit message seems off to me... One thing we need to take care with mass conversions of dev_priv to i915 is to ensure we are not converting the implicit declarations, since we want to kill that. But on a quick glance it looks fine. Did you generated this with full s/dev_priv/i915 in i915_drv.h? > > Signed-off-by: Andi Shyti > --- > drivers/gpu/drm/i915/i915_drv.h | 458 > 1 file changed, 229 insertions(+), 229 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index c16f8a3cd914f..14c5338c96a6b 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -407,11 +407,11 @@ static inline struct intel_gt *to_gt(struct > drm_i915_private *i915) >(engine__) && (engine__)->uabi_class == (class__); \ >(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) > > -#define INTEL_INFO(dev_priv) (&(dev_priv)->__info) > -#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) > -#define DRIVER_CAPS(dev_priv)(&(dev_priv)->caps) > +#define INTEL_INFO(i915) (&(i915)->__info) > +#define RUNTIME_INFO(i915) (&(i915)->__runtime) > +#define DRIVER_CAPS(i915)(&(i915)->caps) > > -#define INTEL_DEVID(dev_priv)(RUNTIME_INFO(dev_priv)->device_id) > +#define INTEL_DEVID(i915)(RUNTIME_INFO(i915)->device_id) > > #define IP_VER(ver, rel) ((ver) << 8 | (rel)) > > @@ -431,7 +431,7 @@ static inline struct intel_gt *to_gt(struct > drm_i915_private *i915) > #define IS_DISPLAY_VER(i915, from, until) \ > (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) > > -#define INTEL_REVID(dev_priv) > (to_pci_dev((dev_priv)->drm.dev)->revision) > +#define INTEL_REVID(i915)(to_pci_dev((i915)->drm.dev)->revision) > > #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) > #define INTEL_GRAPHICS_STEP(__i915) > (RUNTIME_INFO(__i915)->step.graphics_step) > @@ -516,135 +516,135 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); > } > > -#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) > -#define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) > - > -#define IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830) > -#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) > -#define IS_I85X(dev_priv)IS_PLATFORM(dev_priv, INTEL_I85X) > -#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) > -#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) > -#define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) > -#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) > -#define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) > -#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) > -#define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) > -#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) > -#define IS_GM45(dev_priv)IS_PLATFORM(dev_priv, INTEL_GM45) > -#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) > -#define IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW) > -#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) > -#define IS_IRONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IRONLAKE) > -#define IS_IRONLAKE_M(dev_priv) \ > - (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) > -#define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE) > -#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) > -#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ > - INTEL_INFO(dev_priv)->gt == 1) > -#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) > -#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) > -#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) > -#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) > -#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) > -#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) > -#define IS_KABYLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_KABYLAKE) > -#define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) > -#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) > -#define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) > -#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) > -#define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ > - IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > -#define
[Intel-gfx] [PATCH v2] video/hdmi: minor fixes for *_infoframe_init functions
Multiple hdmi_*_infoframe_init() functions that initialize different
types of hdmi infoframes only return default 0 value (contrary to their
descriptions). Yet these functions are still checked against possible
errors in case of failure.
This patch removes redundant checks for errors in calls to following
functions:
- hdmi_spd_infoframe_init
- hdmi_audio_infoframe_init
- hdmi_vendor_infoframe_init
- hdmi_drm_infoframe_init
Also, change their return types to void and fix descriptions.
Fixes: 2c676f378edb ("[media] hdmi: added unpack and logging functions for
InfoFrames")
Signed-off-by: Nikita Zhandarovich
---
v2: Fix build warning by removing unnecessary call to drm_WARN_ON()
with uninitialized value.
Reported-by: kernel test robot
Link:
https://lore.kernel.org/oe-kbuild-all/202304131234.ht3mzkju-...@intel.com/
drivers/gpu/drm/display/drm_hdmi_helper.c | 5 +---
drivers/gpu/drm/drm_edid.c| 5 +---
drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +--
drivers/gpu/drm/mediatek/mtk_hdmi.c | 14 ++
drivers/gpu/drm/radeon/r600_hdmi.c
drivers/gpu/drm/display/drm_hdmi_helper.c | 5 +---
drivers/gpu/drm/drm_edid.c| 5 +---
drivers/gpu/drm/i915/display/intel_hdmi.c | 7 ++---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 14 ++
drivers/gpu/drm/radeon/r600_hdmi.c| 6 +
drivers/gpu/drm/sti/sti_hdmi.c| 6 +
drivers/gpu/drm/tegra/hdmi.c | 7 +
drivers/gpu/drm/tegra/sor.c | 6 +
drivers/gpu/drm/vc4/vc4_hdmi.c| 7 +
drivers/video/hdmi.c | 44 ++-
include/linux/hdmi.h | 8 +++---
11 files changed, 23 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_hdmi_helper.c
b/drivers/gpu/drm/display/drm_hdmi_helper.c
index faf5e9efa7d3..ce7038a3a183 100644
--- a/drivers/gpu/drm/display/drm_hdmi_helper.c
+++ b/drivers/gpu/drm/display/drm_hdmi_helper.c
@@ -27,7 +27,6 @@ int drm_hdmi_infoframe_set_hdr_metadata(struct
hdmi_drm_infoframe *frame,
{
struct drm_connector *connector;
struct hdr_output_metadata *hdr_metadata;
- int err;
if (!frame || !conn_state)
return -EINVAL;
@@ -47,9 +46,7 @@ int drm_hdmi_infoframe_set_hdr_metadata(struct
hdmi_drm_infoframe *frame,
connector->hdr_sink_metadata.hdmi_type1.eotf))
DRM_DEBUG_KMS("Unknown EOTF %d\n",
hdr_metadata->hdmi_metadata_type1.eotf);
- err = hdmi_drm_infoframe_init(frame);
- if (err < 0)
- return err;
+ hdmi_drm_infoframe_init(frame);
frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 261a62e15934..c268148502d6 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -7159,7 +7159,6 @@ drm_hdmi_vendor_infoframe_from_display_mode(struct
hdmi_vendor_infoframe *frame,
*/
bool has_hdmi_infoframe = connector ?
connector->display_info.has_hdmi_infoframe : false;
- int err;
if (!frame || !mode)
return -EINVAL;
@@ -7167,9 +7166,7 @@ drm_hdmi_vendor_infoframe_from_display_mode(struct
hdmi_vendor_infoframe *frame,
if (!has_hdmi_infoframe)
return -EINVAL;
- err = hdmi_vendor_infoframe_init(frame);
- if (err < 0)
- return err;
+ hdmi_vendor_infoframe_init(frame);
/*
* Even if it's not absolutely necessary to send the infoframe
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index c0ce6d3dc505..59e2f53015c0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -778,12 +778,9 @@ intel_hdmi_compute_spd_infoframe(struct intel_encoder
*encoder,
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
if (IS_DGFX(i915))
- ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
+ hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
else
- ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
-
- if (drm_WARN_ON(encoder->base.dev, ret))
- return false;
+ hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
frame->sdi = HDMI_SPD_SDI_PC;
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 0a8e0a13f516..75899e4a011f 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -995,12 +995,7 @@ static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi
*hdmi,
u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE];
ssize_t err;
- err = hdmi_spd_infoframe_init(&frame,
