Re: [Intel-gfx] [PATCH v2 5/8] drm/i915/huc: differentiate the 2 steps of the MTL HuC auth flow
On 5/19/2023 11:45 AM, John Harrison wrote:
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth, with meu
binaries being considered fully authenticated only after the GSC auth
step.
To report the difference between the 2 auth steps, a new case is added
to the HuC getparam. This way, the clear media driver can start
submitting before full auth, as partial auth is enough for those
workloads.
v2: fix authentication status check for DG2
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 94 +--
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 16 +++-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 3 +
include/uapi/drm/i915_drm.h | 3 +-
5 files changed, 91 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index c189ede4ef55..60f95d98e5fd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -10,6 +10,7 @@
#include "intel_huc.h"
#include "intel_huc_print.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include
#include
@@ -106,7 +107,7 @@ static enum hrtimer_restart
huc_delayed_load_timer_callback(struct hrtimer *hrti
{
struct intel_huc *huc = container_of(hrtimer, struct intel_huc,
delayed_load.timer);
- if (!intel_huc_is_authenticated(huc)) {
+ if (!intel_huc_is_authenticated(huc, INTEL_HUC_AUTH_BY_GSC)) {
if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_GSC)
huc_notice(huc, "timed out waiting for MEI GSC\n");
else if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_PXP)
@@ -124,7 +125,7 @@ static void huc_delayed_load_start(struct
intel_huc *huc)
{
ktime_t delay;
- GEM_BUG_ON(intel_huc_is_authenticated(huc));
+ GEM_BUG_ON(intel_huc_is_authenticated(huc, INTEL_HUC_AUTH_BY_GSC));
/*
* On resume we don't have to wait for MEI-GSC to be re-probed,
but we
@@ -284,13 +285,23 @@ void intel_huc_init_early(struct intel_huc *huc)
}
if (GRAPHICS_VER(i915) >= 11) {
- huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
- huc->status.mask = HUC_LOAD_SUCCESSFUL;
- huc->status.value = HUC_LOAD_SUCCESSFUL;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].reg =
GEN11_HUC_KERNEL_LOAD_INFO;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL;
} else {
- huc->status.reg = HUC_STATUS2;
- huc->status.mask = HUC_FW_VERIFIED;
- huc->status.value = HUC_FW_VERIFIED;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED;
+ }
+
+ if (IS_DG2(i915)) {
+ huc->status[INTEL_HUC_AUTH_BY_GSC].reg =
GEN11_HUC_KERNEL_LOAD_INFO;
+ huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL;
+ huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL;
+ } else {
+ huc->status[INTEL_HUC_AUTH_BY_GSC].reg =
HECI_FWSTS5(MTL_GSC_HECI1_BASE);
+ huc->status[INTEL_HUC_AUTH_BY_GSC].mask =
HECI_FWSTS5_HUC_AUTH_DONE;
+ huc->status[INTEL_HUC_AUTH_BY_GSC].value =
HECI_FWSTS5_HUC_AUTH_DONE;
}
}
@@ -381,28 +392,39 @@ void intel_huc_suspend(struct intel_huc *huc)
delayed_huc_load_complete(huc);
}
-int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
+static const char *auth_mode_string(struct intel_huc *huc,
+ enum intel_huc_authentication_type type)
+{
+ bool partial = !huc->loaded_via_gsc && huc->fw.is_meu_binary &&
+ type == INTEL_HUC_AUTH_BY_GUC;
partial = !loaded_via_gsc?
If it is not a GSC load then there is no two stage authentication, is
there? Does that mean the single stage auth does not count as 'all
workloads' even on platforms where two stage is not supported?
Single step authentication always counts as "all workloads". The auth is
partial only if this is a DMA (i.e. non-gsc) load with a gsc-enabled
binary and we're doing an auth via GuC, which is what the condition
above is checking.
+
+ return partial ? "clear media" : "all workloads";
+}
+
+int intel_huc_wait_for_auth_complete(struct intel_huc *huc,
+ enum intel_huc_authentication_type type)
{
struct intel_gt *gt = huc_to_gt(huc);
int ret;
ret = __intel_wait_for_register(gt->uncore,
- huc->status.reg,
- huc->status.mask,
- huc->status.value,
+ huc->status[type].reg,
+
Re: [Intel-gfx] [PATCH v2 4/8] drm/i915/huc: Load GSC-enabled HuC via DMA xfer if the fuse says so
On 5/19/2023 11:03 AM, John Harrison wrote:
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that we now need to differentiate between "GSC-enabled binary" and
"loaded by GSC", so the former case has been renamed to "MEU binary" for
clarity, while the latter is now based on the fuse instead of the binary
format. This way, all the legacy load paths are automatically taken
(including the auth by GuC) without having to implement further code
changes.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 27 ++-
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 4 +++-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 14 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 +-
5 files changed, 29 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 062ff914b274..c189ede4ef55 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -298,31 +298,38 @@ void intel_huc_init_early(struct intel_huc *huc)
static int check_huc_loading_mode(struct intel_huc *huc)
{
struct intel_gt *gt = huc_to_gt(huc);
- bool fw_needs_gsc = intel_huc_is_loaded_by_gsc(huc);
- bool hw_uses_gsc = false;
+ bool fw_is_meu = huc->fw.is_meu_binary;
/*
* The fuse for HuC load via GSC is only valid on platforms
that have
* GuC deprivilege.
*/
if (HAS_GUC_DEPRIVILEGE(gt->i915))
- hw_uses_gsc = intel_uncore_read(gt->uncore,
GUC_SHIM_CONTROL2) &
- GSC_LOADS_HUC;
+ huc->loaded_via_gsc = intel_uncore_read(gt->uncore,
GUC_SHIM_CONTROL2) &
+ GSC_LOADS_HUC;
- if (fw_needs_gsc != hw_uses_gsc) {
- huc_err(huc, "mismatch between FW (%s) and HW (%s) load
modes\n",
- HUC_LOAD_MODE_STRING(fw_needs_gsc),
HUC_LOAD_MODE_STRING(hw_uses_gsc));
+ if (huc->loaded_via_gsc && !fw_is_meu) {
+ huc_err(huc, "HW requires a MEU blob, but we found a legacy
one\n");
return -ENOEXEC;
}
- /* make sure we can access the GSC via the mei driver if we
need it */
+ /*
+ * Newer meu blobs contain the old FW structure inside. If we found
+ * that, we can use it to load the legacy way.
+ */
+ if (!huc->loaded_via_gsc && fw_is_meu &&
!huc->fw.dma_start_offset) {
+ huc_err(huc," HW in legacy mode, but we have an incompatible
meu blob\n");
Leading space in the message? MEU or meu?
As mentioned in the reply on the previous patch, I'm going to drop the
meu tag.
+ return -ENOEXEC;
+ }
+
+ /* make sure we can access the GSC if we need it */
if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) &&
IS_ENABLED(CONFIG_INTEL_MEI_GSC)) &&
- fw_needs_gsc) {
+ !HAS_ENGINE(gt, GSC0) && huc->loaded_via_gsc) {
Should that be || !HAS_ENGINE ?
No. The config check is for DG2, while the engine check is for MTL+. We
need one of the two to be true, not both, so we only fail if both are false.
huc_info(huc, "can't load due to missing MEI modules\n");
'missing MEI modules or GSC engine'?
I'll update it to "missing requirements" or something like that.
return -EIO;
}
- huc_dbg(huc, "loaded by GSC = %s\n", str_yes_no(fw_needs_gsc));
+ huc_dbg(huc, "loaded by GSC = %s\n",
str_yes_no(huc->loaded_via_gsc));
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index db555b3c1f56..345e1b9aa062 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -39,6 +39,8 @@ struct intel_huc {
struct notifier_block nb;
enum intel_huc_delayed_load_status status;
} delayed_load;
+
+ bool loaded_via_gsc;
};
int intel_huc_sanitize(struct intel_huc *huc);
@@ -73,7 +75,7 @@ static inline bool intel_huc_is_used(struct
intel_huc *huc)
static inline bool intel_huc_is_loaded_by_gsc(const struct
intel_huc *huc)
{
- return huc->fw.loaded_via_gsc;
+ return huc->loaded_via_gsc;
}
static inline bool intel_huc_wait_required(struct intel_huc *huc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index f1c973e1c676..88ad2c322c4a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -34,7 +34,7 @@ int intel_huc_fw_get_binary_info(struct intel_uc_fw
*huc_fw, const void *data, s
size_t min_size = sizeof(*header);
int i;
- if (!huc_fw->loaded_via_gsc) {
+ if (!huc_fw->is_meu_binary) {
huc_err(huc, "Invalid FW type MEU parsing!\n");
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915/perf: Avoid reading OA reports before they land
== Series Details == Series: i915/perf: Avoid reading OA reports before they land URL : https://patchwork.freedesktop.org/series/118054/ State : warning == Summary == Error: dim checkpatch failed 0e9ec65e25cf i915/perf: Avoid reading OA reports before they land -:9: WARNING:TYPO_SPELLING: 'occassionally' may be misspelled - perhaps 'occasionally'? #9: (13.3 us) and heavy render workload, occassionally, the OA HW TAIL ^ -:26: WARNING:COMMIT_LOG_USE_LINK: Unknown link reference 'Bug:', use 'Link:' or 'Closes:' instead #26: Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7484 -:27: WARNING:COMMIT_LOG_USE_LINK: Unknown link reference 'Bug:', use 'Link:' or 'Closes:' instead #27: Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7757 total: 0 errors, 3 warnings, 0 checks, 21 lines checked
[Intel-gfx] ✓ Fi.CI.IGT: success for Add MTL PMU support for multi-gt
== Series Details ==
Series: Add MTL PMU support for multi-gt
URL : https://patchwork.freedesktop.org/series/118034/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13168_full -> Patchwork_118034v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118034v1_full:
### IGT changes ###
Possible regressions
* {igt@perf_pmu@frequency@gt0} (NEW):
- {shard-dg1}:NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/shard-dg1-18/igt@perf_pmu@freque...@gt0.html
* {igt@perf_pmu@rc6-all-gts} (NEW):
- {shard-dg1}:NOTRUN -> [SKIP][2] +1 similar issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/shard-dg1-14/igt@perf_...@rc6-all-gts.html
- {shard-tglu}: NOTRUN -> [SKIP][3] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/shard-tglu-7/igt@perf_...@rc6-all-gts.html
* {igt@perf_pmu@rc6@other-idle-gt0} (NEW):
- {shard-rkl}:NOTRUN -> [SKIP][4] +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/shard-rkl-4/igt@perf_pmu@r...@other-idle-gt0.html
New tests
-
New tests have been introduced between CI_DRM_13168_full and
Patchwork_118034v1_full:
### New IGT tests (7) ###
* igt@perf_pmu@frequency@gt0:
- Statuses : 1 fail(s) 5 pass(s)
- Exec time: [0.0] s
* igt@perf_pmu@frequency@idle-gt0:
- Statuses : 6 pass(s)
- Exec time: [0.0] s
* igt@perf_pmu@rc6-all-gts:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@perf_pmu@rc6@gt0:
- Statuses : 6 pass(s)
- Exec time: [0.0] s
* igt@perf_pmu@rc6@other-idle-gt0:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@perf_pmu@rc6@runtime-pm-gt0:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@perf_pmu@rc6@runtime-pm-long-gt0:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_118034v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2846])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13168/shard-glk1/igt@gem_exec_f...@basic-deadline.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/shard-glk2/igt@gem_exec_f...@basic-deadline.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/shard-glk8/igt@gem_lmem_swapp...@verify-ccs.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][8] -> [ABORT][9] ([i915#5566]) +1 similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13168/shard-apl7/igt@gen9_exec_pa...@allowed-all.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/shard-apl7/igt@gen9_exec_pa...@allowed-all.html
* igt@i915_pm_dc@dc9-dpms:
- shard-apl: [PASS][10] -> [SKIP][11] ([fdo#109271])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13168/shard-apl2/igt@i915_pm...@dc9-dpms.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/shard-apl6/igt@i915_pm...@dc9-dpms.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][12] -> [INCOMPLETE][13] ([i915#7790])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13168/shard-snb4/igt@i915_pm_...@reset.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/shard-snb6/igt@i915_pm_...@reset.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][14] -> [FAIL][15] ([i915#2346])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13168/shard-glk5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/shard-glk8/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271]) +21 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/shard-snb2/igt@kms_f...@2x-nonexisting-fb.html
*
igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-glk: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4579])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/shard-glk5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscal...@pipe-a-valid-mode.html
*
Re: [Intel-gfx] [PATCH v10 00/10] drm/hdcp: Pull HDCP auth/exchange/check into helpers
On 20/05/2023 00:16, Rodrigo Vivi wrote: On Fri, May 19, 2023 at 07:55:47PM +0300, Dmitry Baryshkov wrote: On 19/04/2023 18:43, Mark Yacoub wrote: Hi all, This is v10 of the HDCP patches. The patches are authored by Sean Paul. I rebased and addressed the review comments in v6-v10. Main change in v10 is handling the kernel test bot warnings. Patches 1-4 focus on moving the common HDCP helpers to common DRM. This introduces a slight change in the original intel flow as it splits the unique driver protocol from the generic implementation. Patches 5-7 split the HDCP flow on the i915 driver to make use of the common DRM helpers. Patches 8-10 implement HDCP on MSM driver. Thanks, -Mark Yacoub Sean Paul (10): drm/hdcp: Add drm_hdcp_atomic_check() drm/hdcp: Avoid changing crtc state in hdcp atomic check drm/hdcp: Update property value on content type and user changes drm/hdcp: Expand HDCP helper library for enable/disable/check drm/i915/hdcp: Consolidate HDCP setup/state cache drm/i915/hdcp: Retain hdcp_capable return codes drm/i915/hdcp: Use HDCP helpers for i915 dt-bindings: msm/dp: Add bindings for HDCP registers arm64: dts: qcom: sc7180: Add support for HDCP in dp-controller Dear i915 maintainers, I wanted to ping you regarding this patch series. If there are no comments for the series from you side, would it be possible to land Intel-specific and generic patches into drm-intel tree? We will continue working on the msm specific parts and merge them through the msm tree. pushed to drm-intel-next. should be propagated in a few weeks to drm-next on our next pull request. Probably there is some kind of confusion here. You've pushed the DSC patches, while the response was sent to the HDCP series. -- With best wishes Dmitry
[Intel-gfx] [PATCH] i915/perf: Avoid reading OA reports before they land
On DG2, capturing OA reports while running heavy render workloads sometimes results in invalid OA reports where 64-byte chunks inside reports have stale values. Under memory pressure, high OA sampling rates (13.3 us) and heavy render workload, occassionally, the OA HW TAIL pointer does not progress as fast as the sampling rate. When these glitches occur, the TAIL pointer takes approx. 200us to progress. While this is expected behavior from the HW perspective, invalid reports are not expected. In oa_buffer_check_unlocked(), when we execute the if condition, we are updating the oa_buffer.tail to the aging tail and then setting pollin based on this tail value, however, we do not have a chance to rewind and validate the reports prior to setting pollin. The validation happens in a subsequent call to oa_buffer_check_unlocked(). If a read occurs before this validation, then we end up reading reports up until this oa_buffer.tail value which includes invalid reports. Though found on DG2, this affects all platforms. Set the pollin only in the else condition in oa_buffer_check_unlocked. Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7484 Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7757 Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/i915_perf.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 19d5652300ee..61536e3c4ac9 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -545,7 +545,7 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream) u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); int report_size = stream->oa_buffer.format->size; unsigned long flags; - bool pollin; + bool pollin = false; u32 hw_tail; u64 now; u32 partial_report_size; @@ -620,10 +620,10 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream) stream->oa_buffer.tail = gtt_offset + tail; stream->oa_buffer.aging_tail = gtt_offset + hw_tail; stream->oa_buffer.aging_timestamp = now; - } - pollin = OA_TAKEN(stream->oa_buffer.tail - gtt_offset, - stream->oa_buffer.head - gtt_offset) >= report_size; + pollin = OA_TAKEN(stream->oa_buffer.tail - gtt_offset, + stream->oa_buffer.head - gtt_offset) >= report_size; + } spin_unlock_irqrestore(>oa_buffer.ptr_lock, flags); -- 2.38.1
Re: [Intel-gfx] [PATCH v10 00/10] drm/hdcp: Pull HDCP auth/exchange/check into helpers
On Fri, May 19, 2023 at 07:55:47PM +0300, Dmitry Baryshkov wrote: > On 19/04/2023 18:43, Mark Yacoub wrote: > > Hi all, > > This is v10 of the HDCP patches. The patches are authored by Sean Paul. > > I rebased and addressed the review comments in v6-v10. > > > > Main change in v10 is handling the kernel test bot warnings. > > > > Patches 1-4 focus on moving the common HDCP helpers to common DRM. > > This introduces a slight change in the original intel flow > > as it splits the unique driver protocol from the generic implementation. > > > > Patches 5-7 split the HDCP flow on the i915 driver to make use of the > > common DRM helpers. > > > > Patches 8-10 implement HDCP on MSM driver. > > > > Thanks, > > -Mark Yacoub > > > > Sean Paul (10): > >drm/hdcp: Add drm_hdcp_atomic_check() > >drm/hdcp: Avoid changing crtc state in hdcp atomic check > >drm/hdcp: Update property value on content type and user changes > >drm/hdcp: Expand HDCP helper library for enable/disable/check > >drm/i915/hdcp: Consolidate HDCP setup/state cache > >drm/i915/hdcp: Retain hdcp_capable return codes > >drm/i915/hdcp: Use HDCP helpers for i915 > >dt-bindings: msm/dp: Add bindings for HDCP registers > >arm64: dts: qcom: sc7180: Add support for HDCP in dp-controller > > Dear i915 maintainers, > > I wanted to ping you regarding this patch series. If there are no comments > for the series from you side, would it be possible to land Intel-specific > and generic patches into drm-intel tree? We will continue working on the msm > specific parts and merge them through the msm tree. pushed to drm-intel-next. should be propagated in a few weeks to drm-next on our next pull request. > > >drm/msm: Implement HDCP 1.x using the new drm HDCP helpers > > > > .../bindings/display/msm/dp-controller.yaml |7 +- > > arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi |8 + > > drivers/gpu/drm/display/drm_hdcp_helper.c | 1224 + > > drivers/gpu/drm/i915/display/intel_atomic.c |8 +- > > drivers/gpu/drm/i915/display/intel_ddi.c | 32 +- > > .../drm/i915/display/intel_display_debugfs.c | 12 +- > > .../drm/i915/display/intel_display_types.h| 51 +- > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 352 ++--- > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +- > > drivers/gpu/drm/i915/display/intel_hdcp.c | 1060 +++--- > > drivers/gpu/drm/i915/display/intel_hdcp.h | 48 +- > > drivers/gpu/drm/i915/display/intel_hdmi.c | 267 ++-- > > drivers/gpu/drm/msm/Kconfig |1 + > > drivers/gpu/drm/msm/Makefile |1 + > > drivers/gpu/drm/msm/dp/dp_catalog.c | 156 +++ > > drivers/gpu/drm/msm/dp/dp_catalog.h | 18 + > > drivers/gpu/drm/msm/dp/dp_debug.c | 46 +- > > drivers/gpu/drm/msm/dp/dp_debug.h | 11 +- > > drivers/gpu/drm/msm/dp/dp_display.c | 39 +- > > drivers/gpu/drm/msm/dp/dp_display.h |5 + > > drivers/gpu/drm/msm/dp/dp_drm.c | 39 +- > > drivers/gpu/drm/msm/dp/dp_drm.h |7 + > > drivers/gpu/drm/msm/dp/dp_hdcp.c | 389 ++ > > drivers/gpu/drm/msm/dp/dp_hdcp.h | 33 + > > drivers/gpu/drm/msm/dp/dp_parser.c| 14 + > > drivers/gpu/drm/msm/dp/dp_parser.h|4 + > > drivers/gpu/drm/msm/dp/dp_reg.h | 30 +- > > drivers/gpu/drm/msm/msm_atomic.c | 19 + > > include/drm/display/drm_hdcp.h| 296 > > include/drm/display/drm_hdcp_helper.h | 23 + > > 30 files changed, 2867 insertions(+), 1349 deletions(-) > > create mode 100644 drivers/gpu/drm/msm/dp/dp_hdcp.c > > create mode 100644 drivers/gpu/drm/msm/dp/dp_hdcp.h > > > > -- > With best wishes > Dmitry >
Re: [Intel-gfx] [PATCH v2] drm/i915: Fix memory leaks in function live_nop_switch
On Wed, May 17, 2023 at 01:02:03PM +0800, Cong Liu wrote:
> Be sure to properly free the allocated memory before exiting
> the live_nop_switch function.
>
> Signed-off-by: Cong Liu
> Suggested-by: Rodrigo Vivi
pushed, thanks for the patch
> ---
> .../gpu/drm/i915/gem/selftests/i915_gem_context.c | 14 --
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> index a81fa6a20f5a..2fb125d0cb5e 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> @@ -66,7 +66,7 @@ static int live_nop_switch(void *arg)
> ctx[n] = live_context(i915, file);
> if (IS_ERR(ctx[n])) {
> err = PTR_ERR(ctx[n]);
> - goto out_file;
> + goto out_ctx;
> }
> }
>
> @@ -82,7 +82,7 @@ static int live_nop_switch(void *arg)
> this = igt_request_alloc(ctx[n], engine);
> if (IS_ERR(this)) {
> err = PTR_ERR(this);
> - goto out_file;
> + goto out_ctx;
> }
> if (rq) {
> i915_request_await_dma_fence(this, >fence);
> @@ -96,7 +96,7 @@ static int live_nop_switch(void *arg)
> intel_gt_set_wedged(to_gt(i915));
> i915_request_put(rq);
> err = -EIO;
> - goto out_file;
> + goto out_ctx;
> }
> i915_request_put(rq);
>
> @@ -107,7 +107,7 @@ static int live_nop_switch(void *arg)
>
> err = igt_live_test_begin(, i915, __func__, engine->name);
> if (err)
> - goto out_file;
> + goto out_ctx;
>
> end_time = jiffies + i915_selftest.timeout_jiffies;
> for_each_prime_number_from(prime, 2, 8192) {
> @@ -120,7 +120,7 @@ static int live_nop_switch(void *arg)
> this = igt_request_alloc(ctx[n % nctx], engine);
> if (IS_ERR(this)) {
> err = PTR_ERR(this);
> - goto out_file;
> + goto out_ctx;
> }
>
> if (rq) { /* Force submission order */
> @@ -165,7 +165,7 @@ static int live_nop_switch(void *arg)
>
> err = igt_live_test_end();
> if (err)
> - goto out_file;
> + goto out_ctx;
>
> pr_info("Switch latencies on %s: 1 = %lluns, %lu = %lluns\n",
> engine->name,
> @@ -173,6 +173,8 @@ static int live_nop_switch(void *arg)
> prime - 1, div64_u64(ktime_to_ns(times[1]), prime - 1));
> }
>
> +out_ctx:
> + kfree(ctx);
> out_file:
> fput(file);
> return err;
> --
> 2.34.1
>
>
> No virus found
> Checked by Hillstone Network AntiVirus
Re: [Intel-gfx] [RFC 4/4] drm/i915: Expose RPS thresholds in sysfs
On Fri, May 19, 2023 at 07:36:56PM +, Prahlad Kilambi wrote: > > One question is are we able to find a "one size fits all" values. > > > However regardless of that, given we already expose frequency controls in > > sysfs > > with the same reasoning of allowing system owners explicit control if so > > wanted, > > I think exposing the thresholds can be equally justified. > > Exposing these RPS thresholds via sysfs allows for dynamic tuning of these > values at runtime. Common scenarios where we can benefit from variable > frequency ramping include plugged in vs battery where differing thresholds > allow to weight more for performance vs power. Data from testing on ChromeOS > Gen12 platforms where GuC isn't enabled indicates gains > 10% across several > games. See > https://gitlab.freedesktop.org/drm/intel/-/issues/8389#note_1890428 for > details. > In general we should always try to reduce the knobs and specially with a register that doesn't work with the new platforms with FW on control of all these variations. But this is a compelling argument. Acked-by: Rodrigo Vivi (if patch 3 doesn't break compilation and the other chunk has the placement explained this is a rv-b for the series)
Re: [Intel-gfx] [RFC 3/4] drm/i915: Add helpers for managing rps thresholds
On Fri, Apr 28, 2023 at 09:14:56AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> In preparation for exposing via sysfs add helpers for managing rps
> thresholds.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 36 +
> drivers/gpu/drm/i915/gt/intel_rps.h | 4
> 2 files changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index a39eee444849..a5a7315f5ace 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2573,6 +2573,42 @@ int intel_rps_set_min_frequency(struct intel_rps *rps,
> u32 val)
> return set_min_freq(rps, val);
> }
>
> +u8 intel_rps_get_up_threshold(struct intel_rps *rps)
> +{
> + return rps->power.up_threshold;
> +}
> +
> +static int rps_set_threshold(struct intel_rps *rps, u8 *threshold, u8 val)
> +{
> + int ret;
> +
> + if (val > 100)
> + return -EINVAL;
> +
> + ret = mutex_lock_interruptible(>lock);
> + if (ret)
> + return ret;
> + *threshold = val;
> + mutex_unlock(>lock);
> +
> + return 0;
> +}
> +
> +int intel_rps_set_up_threshold(struct intel_rps *rps, u8 threshold)
> +{
> + return rps_set_threshold(rps, >power.up_threshold, threshold);
> +}
> +
> +u8 intel_rps_get_down_threshold(struct intel_rps *rps)
> +{
> + return rps->power.down_threshold;
> +}
> +
> +int intel_rps_set_down_threshold(struct intel_rps *rps, u8 threshold)
> +{
> + return rps_set_threshold(rps, >power.down_threshold, threshold);
> +}
> +
Isn't this breaking compilation with the unused functions?
> static void intel_rps_set_manual(struct intel_rps *rps, bool enable)
> {
> struct intel_uncore *uncore = rps_to_uncore(rps);
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h
> b/drivers/gpu/drm/i915/gt/intel_rps.h
> index a3fa987aa91f..92fb01f5a452 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.h
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.h
> @@ -37,6 +37,10 @@ void intel_rps_mark_interactive(struct intel_rps *rps,
> bool interactive);
>
> int intel_gpu_freq(struct intel_rps *rps, int val);
> int intel_freq_opcode(struct intel_rps *rps, int val);
> +u8 intel_rps_get_up_threshold(struct intel_rps *rps);
> +int intel_rps_set_up_threshold(struct intel_rps *rps, u8 threshold);
> +u8 intel_rps_get_down_threshold(struct intel_rps *rps);
> +int intel_rps_set_down_threshold(struct intel_rps *rps, u8 threshold);
> u32 intel_rps_read_actual_frequency(struct intel_rps *rps);
> u32 intel_rps_read_actual_frequency_fw(struct intel_rps *rps);
> u32 intel_rps_get_requested_frequency(struct intel_rps *rps);
> --
> 2.37.2
>
Re: [Intel-gfx] [RFC 4/4] drm/i915: Expose RPS thresholds in sysfs
On Fri, Apr 28, 2023 at 09:44:53AM +0100, Tvrtko Ursulin wrote:
>
> On 28/04/2023 09:14, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > User feedback indicates significant performance gains are possible in
> > specific games with non default RPS up/down thresholds.
> >
> > Expose these tunables via sysfs which will allow users to achieve best
> > performance when running games and best power efficiency elsewhere.
> >
> > Note this patch supports non GuC based platforms only.
> >
> > Signed-off-by: Tvrtko Ursulin
> > References: https://gitlab.freedesktop.org/drm/intel/-/issues/8389
>
> [snip]
>
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> > b/drivers/gpu/drm/i915/gt/intel_rps.c
> > index a5a7315f5ace..f790e81546ff 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> > @@ -2588,7 +2588,12 @@ static int rps_set_threshold(struct intel_rps *rps,
> > u8 *threshold, u8 val)
> > ret = mutex_lock_interruptible(>lock);
> > if (ret)
> > return ret;
> > - *threshold = val;
> > + if (*threshold != val) {
> > + *threshold = val;
> > + intel_rps_set(rps, clamp(rps->cur_freq,
> > +rps->min_freq_softlimit,
> > +rps->max_freq_softlimit));
> > + }
> > mutex_unlock(>lock);
> > return 0;
>
> This hunk belongs to a previous patch - moved locally.
I probably missed something then becuase I didn't miss this in any
of the previous patches. To the point that this looked like a new
separated patch.
>
> Regards,
>
> Tvrtko
Re: [Intel-gfx] [PATCH v2] drm/i915/huc: Parse the GSC-enabled HuC binary
On 5/17/2023 2:04 PM, John Harrison wrote:
On 5/2/2023 08:27, Daniele Ceraolo Spurio wrote:
The new binaries that support the 2-step authentication have contain the
have contain?
legacy-style binary, which we can use for loading the HuC via DMA. To
find out where this is located in the image, we need to parse the meu
'meu manifest' needs some kind of explanation. 'meu' is mentioned many
times but nothing ever seems to explain what it is or where it comes
from. Also, sometimes it is capitalised and sometimes not.
MEU is the name of the tool that packages the binary. I think I'll
switch it to gsc_binary instead of meu_binary, so we don't have
references to non-public tools.
manifest of the GSC binary. The manifest consist of a partition header
followed by entries, one of which contains the offset we're looking for.
Note that the DG2 GSC binary contains entries with the same names, but
it doesn't contain a full legacy binary, so we need to skip assigning
the dma offset in that case (which we can do by checking the ccs).
Also, since we're now parsing the entries, we can extract the HuC
version that way instead of using hardcoded offsets.
Note that the meu structure will be re-used for parsing the GSC binary,
so they've been added in their own header.
v2: fix structure names to match meu defines (s/CPT/CPD/), update commit
message, check ccs validity, drop old version location defines.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
.../drm/i915/gt/uc/intel_gsc_meu_headers.h | 74 ++
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 11 +-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 135 ++
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 5 +-
drivers/gpu/drm/i915/gt/uc/intel_huc_print.h | 21 +++
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 71 +
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 +
drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 6 -
8 files changed, 272 insertions(+), 53 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_print.h
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
new file mode 100644
index ..d55a66202576
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _INTEL_GSC_MEU_H_
+#define _INTEL_GSC_MEU_H_
+
+#include
+
+/* Code partition directory (CPD) structures */
+struct intel_gsc_cpd_header_v2 {
+ u32 header_marker;
+#define INTEL_GSC_CPD_HEADER_MARKER 0x44504324
+
+ u32 num_of_entries;
+ u8 header_version;
+ u8 entry_version;
+ u8 header_length; /* in bytes */
+ u8 flags;
+ u32 partition_name;
+ u32 crc32;
+} __packed;
+
+struct intel_gsc_cpd_entry {
+ u8 name[12];
+
+ /*
+ * Bits 0-24: offset from the beginning of the code partition
+ * Bit 25: huffman compressed
+ * Bits 26-31: reserved
+ */
+ u32 offset;
+#define INTEL_GSC_CPD_ENTRY_OFFSET_MASK GENMASK(24, 0)
+#define INTEL_GSC_CPD_ENTRY_HUFFMAN_COMP BIT(25)
+
+ /*
+ * Module/Item length, in bytes. For Huffman-compressed modules,
this
+ * refers to the uncompressed size. For software-compressed
modules,
+ * this refers to the compressed size.
+ */
+ u32 length;
+
+ u8 reserved[4];
+} __packed;
+
+struct intel_gsc_meu_version {
+ u16 major;
+ u16 minor;
+ u16 hotfix;
+ u16 build;
+} __packed;
+
+struct intel_gsc_manifest_header {
+ u32 header_type; /* 0x4 for manifest type */
+ u32 header_length; /* in dwords */
+ u32 header_version;
+ u32 flags;
+ u32 vendor;
+ u32 date;
+ u32 size; /* In dwords, size of entire manifest (header +
extensions) */
+ u32 header_id;
+ u32 internal_data;
+ struct intel_gsc_meu_version fw_version;
+ u32 security_version;
+ struct intel_gsc_meu_version meu_kit_version;
+ u32 meu_manifest_version;
+ u8 general_data[4];
+ u8 reserved3[56];
+ u32 modulus_size; /* in dwords */
+ u32 exponent_size; /* in dwords */
+} __packed;
+
+#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 9721761373fb..062ff914b274 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -6,23 +6,14 @@
#include
#include "gt/intel_gt.h"
-#include "gt/intel_gt_print.h"
#include "intel_guc_reg.h"
#include "intel_huc.h"
+#include "intel_huc_print.h"
#include "i915_drv.h"
#include
#include
-#define huc_printk(_huc, _level, _fmt, ...) \
- gt_##_level(huc_to_gt(_huc), "HuC: " _fmt, ##__VA_ARGS__)
-#define huc_err(_huc, _fmt, ...) huc_printk((_huc), err, _fmt,
##__VA_ARGS__)
-#define huc_warn(_huc, _fmt, ...) huc_printk((_huc), warn, _fmt,
##__VA_ARGS__)
-#define
[Intel-gfx] ✓ Fi.CI.BAT: success for Add MTL PMU support for multi-gt
== Series Details ==
Series: Add MTL PMU support for multi-gt
URL : https://patchwork.freedesktop.org/series/118034/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13168 -> Patchwork_118034v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/index.html
Participating hosts (36 -> 35)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_118034v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][1] ([i915#6687] / [i915#7978])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][2] ([i915#7828])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: NOTRUN -> [ABORT][3] ([i915#4579] / [i915#8260])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@gem_exec_fence@basic-await@ccs0:
- bat-dg2-8: [FAIL][4] -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13168/bat-dg2-8/igt@gem_exec_fence@basic-aw...@ccs0.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/bat-dg2-8/igt@gem_exec_fence@basic-aw...@ccs0.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [ABORT][6] ([i915#4983] / [i915#7911] / [i915#7920])
-> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13168/bat-rpls-1/igt@i915_selftest@l...@requests.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/bat-rpls-1/igt@i915_selftest@l...@requests.html
- bat-dg2-11: [ABORT][8] ([i915#7913]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13168/bat-dg2-11/igt@i915_selftest@l...@requests.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/bat-dg2-11/igt@i915_selftest@l...@requests.html
Warnings
* igt@kms_psr@primary_mmap_gtt:
- bat-rplp-1: [ABORT][10] ([i915#8434] / [i915#8442]) -> [SKIP][11]
([i915#1072])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13168/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#8260]: https://gitlab.freedesktop.org/drm/intel/issues/8260
[i915#8434]: https://gitlab.freedesktop.org/drm/intel/issues/8434
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
Build changes
-
* IGT: IGT_7297 -> IGTPW_9012
* Linux: CI_DRM_13168 -> Patchwork_118034v1
CI-20190529: 20190529
CI_DRM_13168: 8fd37d92685f450a69f6657f9a01edbfbc257f94 @
git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9012: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9012/index.html
IGT_7297: 0f0754413f14abe2fe6434fd0873c158dbc47ec9 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_118034v1: 8fd37d92685f450a69f6657f9a01edbfbc257f94 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
e604e5ea811f drm/i915/pmu: Export counters from all tiles
b98ea2bbf104 drm/i915/pmu: Prepare for multi-tile non-engine counters
3375fce6ec83 drm/i915/pmu: Add reference counting to the sampling timer
83b287e7c8a9 drm/i915/pmu: Transform PMU parking code to be GT based
38f45614cfed drm/i915/pmu: Skip sampling engines with no enabled counters
91209d1d37da drm/i915/pmu: Support PMU for all engines
e0e8b5f7d01f drm/i915/pmu: Change bitmask of enabled events to u32
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118034v1/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add MTL PMU support for multi-gt
== Series Details == Series: Add MTL PMU support for multi-gt URL : https://patchwork.freedesktop.org/series/118034/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add MTL PMU support for multi-gt
== Series Details == Series: Add MTL PMU support for multi-gt URL : https://patchwork.freedesktop.org/series/118034/ State : warning == Summary == Error: dim checkpatch failed b0667b45bb9b drm/i915/pmu: Change bitmask of enabled events to u32 3120083f65f4 drm/i915/pmu: Support PMU for all engines cc2b26b90bb2 drm/i915/pmu: Skip sampling engines with no enabled counters 4bb62bb0f5b4 drm/i915/pmu: Transform PMU parking code to be GT based dca8c7e0a4df drm/i915/pmu: Add reference counting to the sampling timer ab1fae8f9e3f drm/i915/pmu: Prepare for multi-tile non-engine counters -:106: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #106: FILE: drivers/gpu/drm/i915/i915_pmu.c:205: + GEM_BUG_ON(idx >= ARRAY_SIZE(pmu->sample)); total: 0 errors, 1 warnings, 0 checks, 338 lines checked 990ae3bbf7f2 drm/i915/pmu: Export counters from all tiles
Re: [Intel-gfx] [PATCH v2 5/8] drm/i915/huc: differentiate the 2 steps of the MTL HuC auth flow
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth, with meu
binaries being considered fully authenticated only after the GSC auth
step.
To report the difference between the 2 auth steps, a new case is added
to the HuC getparam. This way, the clear media driver can start
submitting before full auth, as partial auth is enough for those
workloads.
v2: fix authentication status check for DG2
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 94 +--
drivers/gpu/drm/i915/gt/uc/intel_huc.h| 16 +++-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 3 +
include/uapi/drm/i915_drm.h | 3 +-
5 files changed, 91 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index c189ede4ef55..60f95d98e5fd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -10,6 +10,7 @@
#include "intel_huc.h"
#include "intel_huc_print.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include
#include
@@ -106,7 +107,7 @@ static enum hrtimer_restart
huc_delayed_load_timer_callback(struct hrtimer *hrti
{
struct intel_huc *huc = container_of(hrtimer, struct intel_huc,
delayed_load.timer);
- if (!intel_huc_is_authenticated(huc)) {
+ if (!intel_huc_is_authenticated(huc, INTEL_HUC_AUTH_BY_GSC)) {
if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_GSC)
huc_notice(huc, "timed out waiting for MEI GSC\n");
else if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_PXP)
@@ -124,7 +125,7 @@ static void huc_delayed_load_start(struct intel_huc *huc)
{
ktime_t delay;
- GEM_BUG_ON(intel_huc_is_authenticated(huc));
+ GEM_BUG_ON(intel_huc_is_authenticated(huc, INTEL_HUC_AUTH_BY_GSC));
/*
* On resume we don't have to wait for MEI-GSC to be re-probed, but we
@@ -284,13 +285,23 @@ void intel_huc_init_early(struct intel_huc *huc)
}
if (GRAPHICS_VER(i915) >= 11) {
- huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
- huc->status.mask = HUC_LOAD_SUCCESSFUL;
- huc->status.value = HUC_LOAD_SUCCESSFUL;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].reg =
GEN11_HUC_KERNEL_LOAD_INFO;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL;
} else {
- huc->status.reg = HUC_STATUS2;
- huc->status.mask = HUC_FW_VERIFIED;
- huc->status.value = HUC_FW_VERIFIED;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED;
+ }
+
+ if (IS_DG2(i915)) {
+ huc->status[INTEL_HUC_AUTH_BY_GSC].reg =
GEN11_HUC_KERNEL_LOAD_INFO;
+ huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL;
+ huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL;
+ } else {
+ huc->status[INTEL_HUC_AUTH_BY_GSC].reg =
HECI_FWSTS5(MTL_GSC_HECI1_BASE);
+ huc->status[INTEL_HUC_AUTH_BY_GSC].mask =
HECI_FWSTS5_HUC_AUTH_DONE;
+ huc->status[INTEL_HUC_AUTH_BY_GSC].value =
HECI_FWSTS5_HUC_AUTH_DONE;
}
}
@@ -381,28 +392,39 @@ void intel_huc_suspend(struct intel_huc *huc)
delayed_huc_load_complete(huc);
}
-int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
+static const char *auth_mode_string(struct intel_huc *huc,
+ enum intel_huc_authentication_type type)
+{
+ bool partial = !huc->loaded_via_gsc && huc->fw.is_meu_binary &&
+ type == INTEL_HUC_AUTH_BY_GUC;
partial = !loaded_via_gsc?
If it is not a GSC load then there is no two stage authentication, is
there? Does that mean the single stage auth does not count as 'all
workloads' even on platforms where two stage is not supported?
+
+ return partial ? "clear media" : "all workloads";
+}
+
+int intel_huc_wait_for_auth_complete(struct intel_huc *huc,
+enum intel_huc_authentication_type type)
{
struct intel_gt *gt = huc_to_gt(huc);
int ret;
ret = __intel_wait_for_register(gt->uncore,
- huc->status.reg,
- huc->status.mask,
- huc->status.value,
+ huc->status[type].reg,
+
Re: [Intel-gfx] [PATCH v2 4/8] drm/i915/huc: Load GSC-enabled HuC via DMA xfer if the fuse says so
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that we now need to differentiate between "GSC-enabled binary" and
"loaded by GSC", so the former case has been renamed to "MEU binary" for
clarity, while the latter is now based on the fuse instead of the binary
format. This way, all the legacy load paths are automatically taken
(including the auth by GuC) without having to implement further code
changes.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 27 ++-
drivers/gpu/drm/i915/gt/uc/intel_huc.h| 4 +++-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 14 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 +-
5 files changed, 29 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 062ff914b274..c189ede4ef55 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -298,31 +298,38 @@ void intel_huc_init_early(struct intel_huc *huc)
static int check_huc_loading_mode(struct intel_huc *huc)
{
struct intel_gt *gt = huc_to_gt(huc);
- bool fw_needs_gsc = intel_huc_is_loaded_by_gsc(huc);
- bool hw_uses_gsc = false;
+ bool fw_is_meu = huc->fw.is_meu_binary;
/*
* The fuse for HuC load via GSC is only valid on platforms that have
* GuC deprivilege.
*/
if (HAS_GUC_DEPRIVILEGE(gt->i915))
- hw_uses_gsc = intel_uncore_read(gt->uncore, GUC_SHIM_CONTROL2) &
- GSC_LOADS_HUC;
+ huc->loaded_via_gsc = intel_uncore_read(gt->uncore,
GUC_SHIM_CONTROL2) &
+ GSC_LOADS_HUC;
- if (fw_needs_gsc != hw_uses_gsc) {
- huc_err(huc, "mismatch between FW (%s) and HW (%s) load
modes\n",
- HUC_LOAD_MODE_STRING(fw_needs_gsc),
HUC_LOAD_MODE_STRING(hw_uses_gsc));
+ if (huc->loaded_via_gsc && !fw_is_meu) {
+ huc_err(huc, "HW requires a MEU blob, but we found a legacy
one\n");
return -ENOEXEC;
}
- /* make sure we can access the GSC via the mei driver if we need it */
+ /*
+* Newer meu blobs contain the old FW structure inside. If we found
+* that, we can use it to load the legacy way.
+*/
+ if (!huc->loaded_via_gsc && fw_is_meu && !huc->fw.dma_start_offset) {
+ huc_err(huc," HW in legacy mode, but we have an incompatible meu
blob\n");
Leading space in the message? MEU or meu?
+ return -ENOEXEC;
+ }
+
+ /* make sure we can access the GSC if we need it */
if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) && IS_ENABLED(CONFIG_INTEL_MEI_GSC))
&&
- fw_needs_gsc) {
+ !HAS_ENGINE(gt, GSC0) && huc->loaded_via_gsc) {
Should that be || !HAS_ENGINE ?
huc_info(huc, "can't load due to missing MEI modules\n");
'missing MEI modules or GSC engine'?
return -EIO;
}
- huc_dbg(huc, "loaded by GSC = %s\n", str_yes_no(fw_needs_gsc));
+ huc_dbg(huc, "loaded by GSC = %s\n", str_yes_no(huc->loaded_via_gsc));
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index db555b3c1f56..345e1b9aa062 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -39,6 +39,8 @@ struct intel_huc {
struct notifier_block nb;
enum intel_huc_delayed_load_status status;
} delayed_load;
+
+ bool loaded_via_gsc;
};
int intel_huc_sanitize(struct intel_huc *huc);
@@ -73,7 +75,7 @@ static inline bool intel_huc_is_used(struct intel_huc *huc)
static inline bool intel_huc_is_loaded_by_gsc(const struct intel_huc *huc)
{
- return huc->fw.loaded_via_gsc;
+ return huc->loaded_via_gsc;
}
static inline bool intel_huc_wait_required(struct intel_huc *huc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index f1c973e1c676..88ad2c322c4a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -34,7 +34,7 @@ int intel_huc_fw_get_binary_info(struct intel_uc_fw *huc_fw,
const void *data, s
size_t min_size = sizeof(*header);
int i;
- if (!huc_fw->loaded_via_gsc) {
+ if (!huc_fw->is_meu_binary) {
huc_err(huc, "Invalid FW type MEU parsing!\n");
return -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index da6fcfe1d80a..3338dd45e78b 100644
---
Re: [Intel-gfx] [PATCH i-g-t v3] tests/i915: Exercise coherency of mmapped frame buffers
On Friday, 19 May 2023 12:28:49 CEST Andrzej Hajda wrote:
> On 19.05.2023 11:43, Janusz Krzysztofik wrote:
> > Visible glitches have been observed when running graphics applications on
> > Linux under Xen hypervisor. Those observations have been confirmed with
> > failures from kms_pwrite_crc IGT test that verifies data coherency of DRM
> > frame buffer objects using hardware CRC checksums calculated by display
> > controllers, exposed to userspace via debugfs. Since not all applications
> > exhibit the issue, we need to exercise more methods than just pwrite in
> > order to identify all affected processing paths.
> >
> > Create a new test focused on exercising coherency of future scanout
> > buffers populated over mmap. Cover all available mmap methods and caching
> > modes expected to be device coherent.
> >
> > v3: Drop redundant prerequisite checks (Andrzej),
> >- if (condition) return; construct gives shorter code than
> > if (!condition) continue; (Andrzej),
> >- gem_has_lmem() implies gem_has_mmap_offset(), flatten related nested
> > conditions.
> > v2: Drop unused functions -- left-overs from unsuccessful negative subtest
> > attempts requiring consistent crc mismatches in non-coherent modes,
> >- since all subtests now call igt_assert_crc_equal(), move it from
> > subtest bodies to an updated and renamed helper,
> >- drop "derived from ..." info from copyrights comment (Kamil),
> >- fix order of includes (Kamil),
> >- fix whitespace (Kamil),
> >- Cc: Bhanuprakash (Kamil).
> >
> > Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7648
> > Cc: Bhanuprakash Modem
> > Reviewed-by: Andrzej Hajda # v2
> > Signed-off-by: Janusz Krzysztofik
> > ---
> > Hi Andrzej,
> >
> > Your requested optimisations applied. I've introduced one more
> > optimisation -- see changelog. Please confirm your R-b still applies.
>
> Yes, it applies :)
Thank you, Andrzej, pushed.
Janusz
>
> Regards
> Andrzej
>
> >
> > Thanks,
> > Janusz
> >
> >
> > tests/i915/kms_fb_coherency.c | 288 ++
> > tests/meson.build | 1 +
> > 2 files changed, 289 insertions(+)
> > create mode 100644 tests/i915/kms_fb_coherency.c
> >
> > diff --git a/tests/i915/kms_fb_coherency.c b/tests/i915/kms_fb_coherency.c
> > new file mode 100644
> > index 00..b530bf5dcd
> > --- /dev/null
> > +++ b/tests/i915/kms_fb_coherency.c
> > @@ -0,0 +1,288 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2023 Intel Corporation
> > + */
> > +
> > +/**
> > + * TEST: kms_fb_coherency
> > + * Description: Exercise coherency of future scanout buffer objects
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#include "igt.h"
> > +
> > +typedef struct {
> > + int drm_fd;
> > + igt_display_t display;
> > + struct igt_fb fb[2];
> > + igt_output_t *output;
> > + igt_plane_t *primary;
> > + enum pipe pipe;
> > + igt_crc_t ref_crc;
> > + igt_pipe_crc_t *pipe_crc;
> > + uint32_t devid;
> > +} data_t;
> > +
> > +static void prepare_crtc(data_t *data)
> > +{
> > + igt_display_t *display = >display;
> > + igt_output_t *output = data->output;
> > + drmModeModeInfo *mode;
> > +
> > + igt_display_reset(display);
> > + /* select the pipe we want to use */
> > + igt_output_set_pipe(output, data->pipe);
> > +
> > + mode = igt_output_get_mode(output);
> > +
> > + /* create a white reference fb and flip to it */
> > + igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
> > + DRM_FORMAT_XRGB, DRM_FORMAT_MOD_LINEAR,
> > + 1.0, 1.0, 1.0, >fb[0]);
> > +
> > + data->primary = igt_output_get_plane_type(output,
> > DRM_PLANE_TYPE_PRIMARY);
> > +
> > + igt_plane_set_fb(data->primary, >fb[0]);
> > + igt_display_commit(display);
> > +
> > + if (data->pipe_crc)
> > + igt_pipe_crc_free(data->pipe_crc);
> > +
> > + data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe,
> > + IGT_PIPE_CRC_SOURCE_AUTO);
> > +
> > + /* get reference crc for the white fb */
> > + igt_pipe_crc_collect_crc(data->pipe_crc, >ref_crc);
> > +}
> > +
> > +static struct igt_fb *prepare_fb(data_t *data)
> > +{
> > + igt_output_t *output = data->output;
> > + struct igt_fb *fb = >fb[1];
> > + drmModeModeInfo *mode;
> > +
> > + prepare_crtc(data);
> > +
> > + mode = igt_output_get_mode(output);
> > +
> > + /* create a non-white fb we can overwrite later */
> > + igt_create_pattern_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
> > + DRM_FORMAT_XRGB, DRM_FORMAT_MOD_LINEAR, fb);
> > +
> > + /* flip to it to make it UC/WC and fully flushed */
> > + drmModeSetPlane(data->drm_fd,
> > + data->primary->drm_plane->plane_id,
> > + output->config.crtc->crtc_id,
> > + fb->fb_id, 0,
> > +
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for C20 Computed HDMI TMDS pixel clocks (rev3)
On Thu, May 18, 2023 at 10:08:42PM +, Taylor, Clinton A wrote:
> On Thu, 2023-05-18 at 19:31 +, Patchwork wrote:
> > Patch Details
> > Series: C20 Computed HDMI TMDS pixel clocks (rev3)
> > URL:https://patchwork.freedesktop.org/series/117399/
> > State: failure
> > Details:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v3/index.html
> > CI Bug Log - changes from CI_DRM_13164 -> Patchwork_117399v3
> > Summary
> > FAILURE
> >
> > Serious unknown changes coming with Patchwork_117399v3 absolutely need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in Patchwork_117399v3, please notify your bug team to allow them
> > to document this new failure mode, which will reduce false positives in CI.
> >
> > External URL:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v3/index.html
> >
> > Participating hosts (39 -> 36)
> > Missing (3): fi-kbl-soraka fi-snb-2520m fi-bsw-n3050
> >
> > Possible new issues
> > Here are the unknown changes that may have been introduced in
> > Patchwork_117399v3:
> >
> > IGT changes
> > Possible regressions
> > igt@kms_pipe_crc_basic@read-crc@pipe-c-edp-1:
> > bat-adlp-6: PASS -> ABORT
>
> Changes in this patch series not relevant to ADLP (v3) or ADLS (v2)
> platforms. Series can
> only cause regressions on MTL platform with C20 HDMI output.
And we have no MTL machines in the shards pool yet, so that means these
patches can't impact shard results and we don't need to worry about the
fact we never got them.
Applied to drm-intel-next (with a small tweak to wrap one overly long
line). Thanks for the patches and reviews.
Matt
>
> -Clint
>
> > Suppressed
> > The following results come from untrusted machines, tests, or statuses.
> > They do not affect the overall result.
> >
> > igt@i915_selftest@live@migrate:
> > {bat-mtlp-8}: PASS -> DMESG-FAIL
> > Known issues
> > Here are the changes found in Patchwork_117399v3 that come from known
> > issues:
> >
> > IGT changes
> > Issues hit
> > igt@i915_selftest@live@gt_engines:
> >
> > bat-atsm-1: PASS -> FAIL (i915#6268)
> > igt@i915_selftest@live@gt_pm:
> >
> > bat-rpls-2: NOTRUN -> DMESG-FAIL (i915#4258 / i915#7913)
> > igt@i915_selftest@live@requests:
> >
> > bat-rpls-2: NOTRUN -> ABORT (i915#7913 / i915#7982)
> > Possible fixes
> > igt@i915_selftest@live@gt_heartbeat:
> >
> > fi-glk-j4005: DMESG-FAIL (i915#5334) -> PASS
> > igt@i915_selftest@live@gt_lrc:
> >
> > bat-rpls-2: INCOMPLETE (i915#4983 / i915#7913) -> PASS
> > igt@i915_selftest@live@gt_mocs:
> >
> > {bat-mtlp-8}: DMESG-FAIL -> PASS
> > igt@i915_suspend@basic-s3-without-i915:
> >
> > bat-adls-5: FAIL (fdo#103375) -> PASS +3 similar issues
> > igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1:
> >
> > bat-dg2-8: FAIL (i915#7932) -> PASS
> > igt@kms_pipe_crc_basic@read-crc@pipe-b-edp-1:
> >
> > bat-adlp-6: ABORT -> PASS
> > Warnings
> > igt@i915_selftest@live@requests:
> >
> > bat-rpls-1: ABORT (i915#7911 / i915#7920 / i915#7982) -> ABORT (i915#7911 /
> > i915#7920)
> > igt@kms_setmode@basic-clone-single-crtc:
> >
> > bat-rplp-1: SKIP (i915#3555 / i915#4579) -> ABORT (i915#4579 / i915#8260)
> > {name}: This element is suppressed. This means it is ignored when computing
> > the status of the difference (SUCCESS, WARNING, or FAILURE).
> >
> > Build changes
> > Linux: CI_DRM_13164 -> Patchwork_117399v3
> > CI-20190529: 20190529
> > CI_DRM_13164: 30793067f161dfcbaca1b0249d919c9fc306754e @
> > git://anongit.freedesktop.org/gfx-ci/linux
> > IGT_7296: f58eaf30c30c1cc9f00c8b5c596ee5c94d054198 @
> > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> > Patchwork_117399v3: 30793067f161dfcbaca1b0249d919c9fc306754e @
> > git://anongit.freedesktop.org/gfx-ci/linux
> >
> > Linux commits
> > e2b63090a956 drm/i915/hdmi: C20 computed PLL frequencies
> > 273769d73c7b drm/i915: Add 16bit register/mask operators
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix memory leaks in function live_nop_switch (rev3)
== Series Details ==
Series: drm/i915: Fix memory leaks in function live_nop_switch (rev3)
URL : https://patchwork.freedesktop.org/series/117458/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13166_full -> Patchwork_117458v3_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_117458v3_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2842])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13166/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][3] -> [INCOMPLETE][4] ([i915#7790])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13166/shard-snb4/igt@i915_pm_...@reset.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/shard-snb1/igt@i915_pm_...@reset.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-hdmi-a2:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2122]) +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13166/shard-glk4/igt@kms_flip@plain-flip-fb-recreate-interrupti...@c-hdmi-a2.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/shard-glk8/igt@kms_flip@plain-flip-fb-recreate-interrupti...@c-hdmi-a2.html
*
igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4579]) +17
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/shard-snb7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-...@pipe-b-vga-1.html
*
igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271]) +68 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/shard-snb5/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotat...@pipe-a-vga-1.html
Possible fixes
* igt@gem_barrier_race@remote-request@rcs0:
- {shard-rkl}:[ABORT][9] ([i915#7461] / [i915#8211]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13166/shard-rkl-7/igt@gem_barrier_race@remote-requ...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/shard-rkl-3/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@gem_exec_endless@dispatch@vecs0:
- {shard-tglu}: [TIMEOUT][11] ([i915#3778]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13166/shard-tglu-8/igt@gem_exec_endless@dispa...@vecs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/shard-tglu-5/igt@gem_exec_endless@dispa...@vecs0.html
* igt@gem_mmap_gtt@fault-concurrent-x:
- shard-snb: [ABORT][13] ([i915#5161]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13166/shard-snb7/igt@gem_mmap_...@fault-concurrent-x.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/shard-snb7/igt@gem_mmap_...@fault-concurrent-x.html
* igt@i915_pm_rc6_residency@rc6-idle@bcs0:
- {shard-dg1}:[FAIL][15] ([i915#3591]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13166/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-i...@bcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-i...@bcs0.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][17] ([i915#2346]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13166/shard-apl3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/shard-apl6/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- {shard-tglu}: [FAIL][19] ([i915#4767]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13166/shard-tglu-10/igt@kms_fbcon_...@fbc-suspend.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/shard-tglu-10/igt@kms_fbcon_...@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
- shard-glk: [FAIL][21] ([i915#79]) -> [PASS][22] +2 similar issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13166/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a2.html
[22]:
Re: [Intel-gfx] [PATCH v10 00/10] drm/hdcp: Pull HDCP auth/exchange/check into helpers
On 19/04/2023 18:43, Mark Yacoub wrote: Hi all, This is v10 of the HDCP patches. The patches are authored by Sean Paul. I rebased and addressed the review comments in v6-v10. Main change in v10 is handling the kernel test bot warnings. Patches 1-4 focus on moving the common HDCP helpers to common DRM. This introduces a slight change in the original intel flow as it splits the unique driver protocol from the generic implementation. Patches 5-7 split the HDCP flow on the i915 driver to make use of the common DRM helpers. Patches 8-10 implement HDCP on MSM driver. Thanks, -Mark Yacoub Sean Paul (10): drm/hdcp: Add drm_hdcp_atomic_check() drm/hdcp: Avoid changing crtc state in hdcp atomic check drm/hdcp: Update property value on content type and user changes drm/hdcp: Expand HDCP helper library for enable/disable/check drm/i915/hdcp: Consolidate HDCP setup/state cache drm/i915/hdcp: Retain hdcp_capable return codes drm/i915/hdcp: Use HDCP helpers for i915 dt-bindings: msm/dp: Add bindings for HDCP registers arm64: dts: qcom: sc7180: Add support for HDCP in dp-controller Dear i915 maintainers, I wanted to ping you regarding this patch series. If there are no comments for the series from you side, would it be possible to land Intel-specific and generic patches into drm-intel tree? We will continue working on the msm specific parts and merge them through the msm tree. drm/msm: Implement HDCP 1.x using the new drm HDCP helpers .../bindings/display/msm/dp-controller.yaml |7 +- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi |8 + drivers/gpu/drm/display/drm_hdcp_helper.c | 1224 + drivers/gpu/drm/i915/display/intel_atomic.c |8 +- drivers/gpu/drm/i915/display/intel_ddi.c | 32 +- .../drm/i915/display/intel_display_debugfs.c | 12 +- .../drm/i915/display/intel_display_types.h| 51 +- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 352 ++--- drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 1060 +++--- drivers/gpu/drm/i915/display/intel_hdcp.h | 48 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 267 ++-- drivers/gpu/drm/msm/Kconfig |1 + drivers/gpu/drm/msm/Makefile |1 + drivers/gpu/drm/msm/dp/dp_catalog.c | 156 +++ drivers/gpu/drm/msm/dp/dp_catalog.h | 18 + drivers/gpu/drm/msm/dp/dp_debug.c | 46 +- drivers/gpu/drm/msm/dp/dp_debug.h | 11 +- drivers/gpu/drm/msm/dp/dp_display.c | 39 +- drivers/gpu/drm/msm/dp/dp_display.h |5 + drivers/gpu/drm/msm/dp/dp_drm.c | 39 +- drivers/gpu/drm/msm/dp/dp_drm.h |7 + drivers/gpu/drm/msm/dp/dp_hdcp.c | 389 ++ drivers/gpu/drm/msm/dp/dp_hdcp.h | 33 + drivers/gpu/drm/msm/dp/dp_parser.c| 14 + drivers/gpu/drm/msm/dp/dp_parser.h|4 + drivers/gpu/drm/msm/dp/dp_reg.h | 30 +- drivers/gpu/drm/msm/msm_atomic.c | 19 + include/drm/display/drm_hdcp.h| 296 include/drm/display/drm_hdcp_helper.h | 23 + 30 files changed, 2867 insertions(+), 1349 deletions(-) create mode 100644 drivers/gpu/drm/msm/dp/dp_hdcp.c create mode 100644 drivers/gpu/drm/msm/dp/dp_hdcp.h -- With best wishes Dmitry
[Intel-gfx] [PATCH v7 5/7] drm/i915/pmu: Add reference counting to the sampling timer
From: Tvrtko Ursulin
We do not want to have timers per tile and waste CPU cycles and energy via
multiple wake-up sources, for a relatively un-important task of PMU
sampling, so keeping a single timer works well. But we also do not want
the first GT which goes idle to turn off the timer.
Add some reference counting, via a mask of unparked GTs, to solve this.
v2: Drop the check for unparked in i915_sample (Ashutosh)
v3: Revert v2 (Tvrtko)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 12 ++--
drivers/gpu/drm/i915/i915_pmu.h | 4
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 890693fdaf9e..ecb57a94143e 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -262,7 +262,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt)
* Signal sampling timer to stop if only engine events are enabled and
* GPU went idle.
*/
- pmu->timer_enabled = pmu_needs_timer(pmu, false);
+ pmu->unparked &= ~BIT(gt->info.id);
+ if (pmu->unparked == 0)
+ pmu->timer_enabled = pmu_needs_timer(pmu, false);
spin_unlock_irq(>lock);
}
@@ -279,7 +281,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt)
/*
* Re-enable sampling timer when GPU goes active.
*/
- __i915_pmu_maybe_start_timer(pmu);
+ if (pmu->unparked == 0)
+ __i915_pmu_maybe_start_timer(pmu);
+
+ pmu->unparked |= BIT(gt->info.id);
spin_unlock_irq(>lock);
}
@@ -449,6 +454,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
*/
for_each_gt(gt, i915, i) {
+ if (!(pmu->unparked & BIT(i)))
+ continue;
+
engines_sample(gt, period_ns);
if (i == 0) /* FIXME */
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index a686fd7ccedf..3a811266ac6a 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -76,6 +76,10 @@ struct i915_pmu {
* @lock: Lock protecting enable mask and ref count handling.
*/
spinlock_t lock;
+ /**
+* @unparked: GT unparked mask.
+*/
+ unsigned int unparked;
/**
* @timer: Timer for internal i915 PMU sampling.
*/
--
2.36.1
[Intel-gfx] [PATCH v7 4/7] drm/i915/pmu: Transform PMU parking code to be GT based
From: Tvrtko Ursulin
Trivial prep work for full multi-tile enablement later.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++--
drivers/gpu/drm/i915/i915_pmu.c | 16
drivers/gpu/drm/i915/i915_pmu.h | 9 +
3 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index e02cb90723ae..c2e69bafd02b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -87,7 +87,7 @@ static int __gt_unpark(struct intel_wakeref *wf)
intel_rc6_unpark(>rc6);
intel_rps_unpark(>rps);
- i915_pmu_gt_unparked(i915);
+ i915_pmu_gt_unparked(gt);
intel_guc_busyness_unpark(gt);
intel_gt_unpark_requests(gt);
@@ -109,7 +109,7 @@ static int __gt_park(struct intel_wakeref *wf)
intel_guc_busyness_park(gt);
i915_vma_parked(gt);
- i915_pmu_gt_parked(i915);
+ i915_pmu_gt_parked(gt);
intel_rps_park(>rps);
intel_rc6_park(>rc6);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 6d594f67f365..890693fdaf9e 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -228,11 +228,11 @@ static void init_rc6(struct i915_pmu *pmu)
}
}
-static void park_rc6(struct drm_i915_private *i915)
+static void park_rc6(struct intel_gt *gt)
{
- struct i915_pmu *pmu = >pmu;
+ struct i915_pmu *pmu = >i915->pmu;
- pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915));
+ pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(gt);
pmu->sleep_last = ktime_get_raw();
}
@@ -247,16 +247,16 @@ static void __i915_pmu_maybe_start_timer(struct i915_pmu
*pmu)
}
}
-void i915_pmu_gt_parked(struct drm_i915_private *i915)
+void i915_pmu_gt_parked(struct intel_gt *gt)
{
- struct i915_pmu *pmu = >pmu;
+ struct i915_pmu *pmu = >i915->pmu;
if (!pmu->base.event_init)
return;
spin_lock_irq(>lock);
- park_rc6(i915);
+ park_rc6(gt);
/*
* Signal sampling timer to stop if only engine events are enabled and
@@ -267,9 +267,9 @@ void i915_pmu_gt_parked(struct drm_i915_private *i915)
spin_unlock_irq(>lock);
}
-void i915_pmu_gt_unparked(struct drm_i915_private *i915)
+void i915_pmu_gt_unparked(struct intel_gt *gt)
{
- struct i915_pmu *pmu = >pmu;
+ struct i915_pmu *pmu = >i915->pmu;
if (!pmu->base.event_init)
return;
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index c30f43319a78..a686fd7ccedf 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -13,6 +13,7 @@
#include
struct drm_i915_private;
+struct intel_gt;
/*
* Non-engine events that we need to track enabled-disabled transition and
@@ -151,15 +152,15 @@ int i915_pmu_init(void);
void i915_pmu_exit(void);
void i915_pmu_register(struct drm_i915_private *i915);
void i915_pmu_unregister(struct drm_i915_private *i915);
-void i915_pmu_gt_parked(struct drm_i915_private *i915);
-void i915_pmu_gt_unparked(struct drm_i915_private *i915);
+void i915_pmu_gt_parked(struct intel_gt *gt);
+void i915_pmu_gt_unparked(struct intel_gt *gt);
#else
static inline int i915_pmu_init(void) { return 0; }
static inline void i915_pmu_exit(void) {}
static inline void i915_pmu_register(struct drm_i915_private *i915) {}
static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
-static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
-static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}
+static inline void i915_pmu_gt_parked(struct intel_gt *gt) {}
+static inline void i915_pmu_gt_unparked(struct intel_gt *gt) {}
#endif
#endif
--
2.36.1
[Intel-gfx] [PATCH v7 7/7] drm/i915/pmu: Export counters from all tiles
From: Tvrtko Ursulin
Start exporting frequency and RC6 counters from all tiles.
Existing counters keep their names and config values and new one use the
namespace added in the previous patch, with the "-gtN" added to their
names.
Interrupts counter is an odd one off. Because it is the global device
counters (not only GT) we choose not to add per tile versions for now.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Aravind Iddamsetty
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 82 ++---
1 file changed, 55 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 5cfc322e69b4..a814583e19fd 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -940,11 +940,20 @@ static const struct attribute_group
i915_pmu_cpumask_attr_group = {
.attrs = i915_cpumask_attrs,
};
-#define __event(__config, __name, __unit) \
+#define __event(__counter, __name, __unit) \
{ \
- .config = (__config), \
+ .counter = (__counter), \
.name = (__name), \
.unit = (__unit), \
+ .global = false, \
+}
+
+#define __global_event(__counter, __name, __unit) \
+{ \
+ .counter = (__counter), \
+ .name = (__name), \
+ .unit = (__unit), \
+ .global = true, \
}
#define __engine_event(__sample, __name) \
@@ -983,15 +992,16 @@ create_event_attributes(struct i915_pmu *pmu)
{
struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
static const struct {
- u64 config;
+ unsigned int counter;
const char *name;
const char *unit;
+ bool global;
} events[] = {
- __event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "M"),
- __event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency",
"M"),
- __event(I915_PMU_INTERRUPTS, "interrupts", NULL),
- __event(I915_PMU_RC6_RESIDENCY, "rc6-residency", "ns"),
- __event(I915_PMU_SOFTWARE_GT_AWAKE_TIME,
"software-gt-awake-time", "ns"),
+ __event(0, "actual-frequency", "M"),
+ __event(1, "requested-frequency", "M"),
+ __global_event(2, "interrupts", NULL),
+ __event(3, "rc6-residency", "ns"),
+ __event(4, "software-gt-awake-time", "ns"),
};
static const struct {
enum drm_i915_pmu_engine_sample sample;
@@ -1006,12 +1016,17 @@ create_event_attributes(struct i915_pmu *pmu)
struct i915_ext_attribute *i915_attr = NULL, *i915_iter;
struct attribute **attr = NULL, **attr_iter;
struct intel_engine_cs *engine;
- unsigned int i;
+ struct intel_gt *gt;
+ unsigned int i, j;
/* Count how many counters we will be exposing. */
- for (i = 0; i < ARRAY_SIZE(events); i++) {
- if (!config_status(i915, events[i].config))
- count++;
+ for_each_gt(gt, i915, j) {
+ for (i = 0; i < ARRAY_SIZE(events); i++) {
+ u64 config = ___I915_PMU_OTHER(j, events[i].counter);
+
+ if (!config_status(i915, config))
+ count++;
+ }
}
for_each_uabi_engine(engine, i915) {
@@ -1041,26 +1056,39 @@ create_event_attributes(struct i915_pmu *pmu)
attr_iter = attr;
/* Initialize supported non-engine counters. */
- for (i = 0; i < ARRAY_SIZE(events); i++) {
- char *str;
-
- if (config_status(i915, events[i].config))
- continue;
-
- str = kstrdup(events[i].name, GFP_KERNEL);
- if (!str)
- goto err;
+ for_each_gt(gt, i915, j) {
+ for (i = 0; i < ARRAY_SIZE(events); i++) {
+ u64 config = ___I915_PMU_OTHER(j, events[i].counter);
+ char *str;
- *attr_iter++ = _iter->attr.attr;
- i915_iter = add_i915_attr(i915_iter, str, events[i].config);
+ if (config_status(i915, config))
+ continue;
- if (events[i].unit) {
- str = kasprintf(GFP_KERNEL, "%s.unit", events[i].name);
+ if (events[i].global || !HAS_EXTRA_GT_LIST(i915))
+ str = kstrdup(events[i].name, GFP_KERNEL);
+ else
+ str = kasprintf(GFP_KERNEL, "%s-gt%u",
+ events[i].name, j);
if (!str)
goto err;
- *attr_iter++ = _iter->attr.attr;
- pmu_iter = add_pmu_attr(pmu_iter, str, events[i].unit);
+
[Intel-gfx] [PATCH v7 0/7] Add MTL PMU support for multi-gt
With MTL, frequency and rc6 counters are specific to a gt. Export these counters via gt-specific events to the user space. v2: Remove aggregation support from kernel v3: Review comments (Ashutosh, Tvrtko) v4: - Include R-b for 6/6 - Add Test-with - Fix versioning info in cover letter v5: - Include "drm/i915/pmu: Change bitmask of enabled events to u32" v6: s/u64/u32 (Ashutosh) v7: CI rerun with updated IGT Signed-off-by: Umesh Nerlige Ramappa Test-with: 20230519154650.3751855-1-umesh.nerlige.rama...@intel.com Tvrtko Ursulin (7): drm/i915/pmu: Change bitmask of enabled events to u32 drm/i915/pmu: Support PMU for all engines drm/i915/pmu: Skip sampling engines with no enabled counters drm/i915/pmu: Transform PMU parking code to be GT based drm/i915/pmu: Add reference counting to the sampling timer drm/i915/pmu: Prepare for multi-tile non-engine counters drm/i915/pmu: Export counters from all tiles drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +- drivers/gpu/drm/i915/i915_pmu.c | 290 ++ drivers/gpu/drm/i915/i915_pmu.h | 22 +- include/uapi/drm/i915_drm.h | 17 +- 4 files changed, 238 insertions(+), 95 deletions(-) -- 2.36.1
[Intel-gfx] [PATCH v7 6/7] drm/i915/pmu: Prepare for multi-tile non-engine counters
From: Tvrtko Ursulin
Reserve some bits in the counter config namespace which will carry the
tile id and prepare the code to handle this.
No per tile counters have been added yet.
v2:
- Fix checkpatch issues
- Use 4 bits for gt id in non-engine counters. Drop FIXME.
- Set MAX GTs to 4. Drop FIXME.
v3: (Ashutosh, Tvrtko)
- Drop BUG_ON that would never fire
- Make enable u64
- Pull in some code from next patch
v4: Set I915_PMU_MAX_GTS to 2 (Tvrtko)
v5: s/u64/u32 where needed (Ashutosh)
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 146 +++-
drivers/gpu/drm/i915/i915_pmu.h | 9 +-
include/uapi/drm/i915_drm.h | 17 +++-
3 files changed, 127 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index ecb57a94143e..5cfc322e69b4 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -56,11 +56,21 @@ static bool is_engine_config(const u64 config)
return config < __I915_PMU_OTHER(0);
}
+static unsigned int config_gt_id(const u64 config)
+{
+ return config >> __I915_PMU_GT_SHIFT;
+}
+
+static u64 config_counter(const u64 config)
+{
+ return config & ~(~0ULL << __I915_PMU_GT_SHIFT);
+}
+
static unsigned int other_bit(const u64 config)
{
unsigned int val;
- switch (config) {
+ switch (config_counter(config)) {
case I915_PMU_ACTUAL_FREQUENCY:
val = __I915_PMU_ACTUAL_FREQUENCY_ENABLED;
break;
@@ -78,7 +88,9 @@ static unsigned int other_bit(const u64 config)
return -1;
}
- return I915_ENGINE_SAMPLE_COUNT + val;
+ return I915_ENGINE_SAMPLE_COUNT +
+ config_gt_id(config) * __I915_PMU_TRACKED_EVENT_COUNT +
+ val;
}
static unsigned int config_bit(const u64 config)
@@ -115,6 +127,18 @@ static unsigned int event_bit(struct perf_event *event)
return config_bit(event->attr.config);
}
+static u32 frequency_enabled_mask(void)
+{
+ unsigned int i;
+ u32 mask = 0;
+
+ for (i = 0; i < I915_PMU_MAX_GTS; i++)
+ mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) |
+ config_mask(__I915_PMU_REQUESTED_FREQUENCY(i));
+
+ return mask;
+}
+
static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
{
struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
@@ -131,9 +155,7 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool
gpu_active)
* Mask out all the ones which do not need the timer, or in
* other words keep all the ones that could need the timer.
*/
- enable &= config_mask(I915_PMU_ACTUAL_FREQUENCY) |
- config_mask(I915_PMU_REQUESTED_FREQUENCY) |
- ENGINE_SAMPLE_MASK;
+ enable &= frequency_enabled_mask() | ENGINE_SAMPLE_MASK;
/*
* When the GPU is idle per-engine counters do not need to be
@@ -175,9 +197,37 @@ static inline s64 ktime_since_raw(const ktime_t kt)
return ktime_to_ns(ktime_sub(ktime_get_raw(), kt));
}
+static unsigned int
+__sample_idx(struct i915_pmu *pmu, unsigned int gt_id, int sample)
+{
+ unsigned int idx = gt_id * __I915_NUM_PMU_SAMPLERS + sample;
+
+ GEM_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
+
+ return idx;
+}
+
+static u64 read_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample)
+{
+ return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur;
+}
+
+static void
+store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val)
+{
+ pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val;
+}
+
+static void
+add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id, int sample, u32 val,
u32 mul)
+{
+ pmu->sample[__sample_idx(pmu, gt_id, sample)].cur += mul_u32_u32(val,
mul);
+}
+
static u64 get_rc6(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
+ const unsigned int gt_id = gt->info.id;
struct i915_pmu *pmu = >pmu;
unsigned long flags;
bool awake = false;
@@ -192,7 +242,7 @@ static u64 get_rc6(struct intel_gt *gt)
spin_lock_irqsave(>lock, flags);
if (awake) {
- pmu->sample[__I915_SAMPLE_RC6].cur = val;
+ store_sample(pmu, gt_id, __I915_SAMPLE_RC6, val);
} else {
/*
* We think we are runtime suspended.
@@ -201,14 +251,14 @@ static u64 get_rc6(struct intel_gt *gt)
* on top of the last known real value, as the approximated RC6
* counter value.
*/
- val = ktime_since_raw(pmu->sleep_last);
- val += pmu->sample[__I915_SAMPLE_RC6].cur;
+ val = ktime_since_raw(pmu->sleep_last[gt_id]);
+ val += read_sample(pmu, gt_id, __I915_SAMPLE_RC6);
}
[Intel-gfx] [PATCH v7 1/7] drm/i915/pmu: Change bitmask of enabled events to u32
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
in the future.
v2: Fix WARN_ON firing for INTERRUPT event (Umesh)
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 7ece883a7d95..96543dce2db1 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -50,7 +50,7 @@ static u8 engine_event_instance(struct perf_event *event)
return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
}
-static bool is_engine_config(u64 config)
+static bool is_engine_config(const u64 config)
{
return config < __I915_PMU_OTHER(0);
}
@@ -88,9 +88,20 @@ static unsigned int config_bit(const u64 config)
return other_bit(config);
}
-static u64 config_mask(u64 config)
+static u32 config_mask(const u64 config)
{
- return BIT_ULL(config_bit(config));
+ unsigned int bit = config_bit(config);
+
+ if (__builtin_constant_p(config))
+ BUILD_BUG_ON(bit >
+BITS_PER_TYPE(typeof_member(struct i915_pmu,
+enable)) - 1);
+ else
+ WARN_ON_ONCE(bit >
+BITS_PER_TYPE(typeof_member(struct i915_pmu,
+enable)) - 1);
+
+ return BIT(config_bit(config));
}
static bool is_engine_event(struct perf_event *event)
@@ -633,11 +644,10 @@ static void i915_pmu_enable(struct perf_event *event)
{
struct drm_i915_private *i915 =
container_of(event->pmu, typeof(*i915), pmu.base);
+ const unsigned int bit = event_bit(event);
struct i915_pmu *pmu = >pmu;
unsigned long flags;
- unsigned int bit;
- bit = event_bit(event);
if (bit == -1)
goto update;
@@ -651,7 +661,7 @@ static void i915_pmu_enable(struct perf_event *event)
GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
GEM_BUG_ON(pmu->enable_count[bit] == ~0);
- pmu->enable |= BIT_ULL(bit);
+ pmu->enable |= BIT(bit);
pmu->enable_count[bit]++;
/*
@@ -698,7 +708,7 @@ static void i915_pmu_disable(struct perf_event *event)
{
struct drm_i915_private *i915 =
container_of(event->pmu, typeof(*i915), pmu.base);
- unsigned int bit = event_bit(event);
+ const unsigned int bit = event_bit(event);
struct i915_pmu *pmu = >pmu;
unsigned long flags;
@@ -734,7 +744,7 @@ static void i915_pmu_disable(struct perf_event *event)
* bitmask when the last listener on an event goes away.
*/
if (--pmu->enable_count[bit] == 0) {
- pmu->enable &= ~BIT_ULL(bit);
+ pmu->enable &= ~BIT(bit);
pmu->timer_enabled &= pmu_needs_timer(pmu, true);
}
--
2.36.1
[Intel-gfx] [PATCH v7 3/7] drm/i915/pmu: Skip sampling engines with no enabled counters
From: Tvrtko Ursulin
As we have more and more engines do not waste time sampling the ones no-
one is monitoring.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 9edf87ee5d10..6d594f67f365 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -350,6 +350,9 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns)
return;
for_each_engine(engine, gt, id) {
+ if (!engine->pmu.enable)
+ continue;
+
if (!intel_engine_pm_get_if_awake(engine))
continue;
--
2.36.1
[Intel-gfx] [PATCH v7 2/7] drm/i915/pmu: Support PMU for all engines
From: Tvrtko Ursulin
Given how the metrics are already exported, we also need to run sampling
over engines from all GTs.
Problem of GT frequencies is left for later.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 96543dce2db1..9edf87ee5d10 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -10,6 +10,7 @@
#include "gt/intel_engine_pm.h"
#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_user.h"
+#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_rc6.h"
@@ -425,8 +426,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
struct drm_i915_private *i915 =
container_of(hrtimer, struct drm_i915_private, pmu.timer);
struct i915_pmu *pmu = >pmu;
- struct intel_gt *gt = to_gt(i915);
unsigned int period_ns;
+ struct intel_gt *gt;
+ unsigned int i;
ktime_t now;
if (!READ_ONCE(pmu->timer_enabled))
@@ -442,8 +444,13 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
* grabbing the forcewake. However the potential error from timer call-
* back delay greatly dominates this so we keep it simple.
*/
- engines_sample(gt, period_ns);
- frequency_sample(gt, period_ns);
+
+ for_each_gt(gt, i915, i) {
+ engines_sample(gt, period_ns);
+
+ if (i == 0) /* FIXME */
+ frequency_sample(gt, period_ns);
+ }
hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD));
--
2.36.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix memory leaks in function live_nop_switch (rev3)
== Series Details == Series: drm/i915: Fix memory leaks in function live_nop_switch (rev3) URL : https://patchwork.freedesktop.org/series/117458/ State : success == Summary == CI Bug Log - changes from CI_DRM_13166 -> Patchwork_117458v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/index.html Participating hosts (36 -> 36) -- Additional (1): fi-kbl-soraka Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_117458v3 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][3] ([i915#1886] / [i915#7913]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - bat-dg2-11: [PASS][4] -> [ABORT][5] ([i915#7913] / [i915#7979]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13166/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@reset: - bat-rpls-1: [PASS][6] -> [ABORT][7] ([i915#4983] / [i915#7461] / [i915#8347] / [i915#8384]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13166/bat-rpls-1/igt@i915_selftest@l...@reset.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/bat-rpls-1/igt@i915_selftest@l...@reset.html * igt@kms_chamelium_frames@hdmi-crc-fast: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271]) +14 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html * igt@kms_setmode@basic-clone-single-crtc: - fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4579]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/fi-kbl-soraka/igt@kms_setm...@basic-clone-single-crtc.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7979]: https://gitlab.freedesktop.org/drm/intel/issues/7979 [i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347 [i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384 Build changes - * Linux: CI_DRM_13166 -> Patchwork_117458v3 CI-20190529: 20190529 CI_DRM_13166: d517ff66aa5fd8e8fd71831eb218aa6d1bb1a3c5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7296: f58eaf30c30c1cc9f00c8b5c596ee5c94d054198 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_117458v3: d517ff66aa5fd8e8fd71831eb218aa6d1bb1a3c5 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits e460e25a1e46 drm/i915: Fix memory leaks in function live_nop_switch == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117458v3/index.html
Re: [Intel-gfx] [PATCH v5 2/8] drm/i915/dsc: move rc_buf_thresh values to common helper
On 2023-05-04 18:35:05, Dmitry Baryshkov wrote:
>
> The rc_buf_thresh values are common to all DSC implementations. Move
> them to the common helper together with the code to propagage them to
Propagate*
> the drm_dsc_config.
>
> Reviewed-by: Jani Nikula
> Signed-off-by: Dmitry Baryshkov
After right-shifting these values by 6 they are indeed, as promised,
identical to the values used in MSM.
Reviewed-by: Marijn Suijten
If a tested-by is relevant in addition to r-b, let me know. This works
(no regressions) on quite a few MSM devices on my end.
(same question for the other patches)
- Marijn
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 35 +++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +---
> include/drm/display/drm_dsc_helper.h | 1 +
> 3 files changed, 37 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
> b/drivers/gpu/drm/display/drm_dsc_helper.c
> index c869c6e51e2b..be91abe2cfb2 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -270,6 +270,41 @@ void drm_dsc_pps_payload_pack(struct
> drm_dsc_picture_parameter_set *pps_payload,
> }
> EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>
> +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> +static const u16 drm_dsc_rc_buf_thresh[] = {
> + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> + 7744, 7872, 8000, 8064
> +};
> +
> +/**
> + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
> + * in accordance with the DSC 1.2 specification.
> + *
> + * @vdsc_cfg: DSC Configuration data partially filled by driver
> + */
> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> +{
> + int i;
> +
> + BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=
> + DSC_NUM_BUF_RANGES - 1);
> + BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=
> + ARRAY_SIZE(vdsc_cfg->rc_buf_thresh));
> +
> + for (i = 0; i < ARRAY_SIZE(drm_dsc_rc_buf_thresh); i++)
> + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
> +
> + /*
> + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> + * as per C Model
> + */
> + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
> + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
> + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
> + }
> +}
> +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
> +
> /**
> * drm_dsc_compute_rc_parameters() - Write rate control
> * parameters to the dsc configuration defined in
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 7003ae9f683a..2fd08375bbe3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -37,12 +37,6 @@ enum COLUMN_INDEX_BPC {
> MAX_COLUMN_INDEX
> };
>
> -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> -static const u16 rc_buf_thresh[] = {
> - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> - 7744, 7872, 8000, 8064
> -};
> -
> struct rc_parameters {
> u16 initial_xmit_delay;
> u8 first_line_bpg_offset;
> @@ -543,23 +537,7 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
>
> vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>
> - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> - /*
> - * six 0s are appended to the lsb of each threshold value
> - * internally in h/w.
> - * Only 8 bits are allowed for programming RcBufThreshold
> - */
> - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
> - }
> -
> - /*
> - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> - * as per C Model
> - */
> - if (compressed_bpp == 6) {
> - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
> - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
> - }
> + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
>
> /*
>* From XE_LPD onwards we supports compression bpps in steps of 1
> diff --git a/include/drm/display/drm_dsc_helper.h
> b/include/drm/display/drm_dsc_helper.h
> index 8b41edbbabab..706ba1d34742 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header
> *pps_header);
> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
> --
> 2.39.2
>
[Intel-gfx] [bug report] drm/i915: Use ttm mmap handling for ttm bo's.
Hello Maarten Lankhorst,
This is a semi-automatic email about new static checker warnings.
The patch cf3e3e86d779: "drm/i915: Use ttm mmap handling for ttm
bo's." from Jun 10, 2021, leads to the following Smatch complaint:
./drivers/gpu/drm/i915/gem/i915_gem_mman.c:1008 i915_gem_mmap()
error: we previously assumed 'node' could be null (see line 953)
./drivers/gpu/drm/i915/gem/i915_gem_mman.c
949 drm_vma_offset_lock_lookup(dev->vma_offset_manager);
950 node =
drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager,
951vma->vm_pgoff,
952vma_pages(vma));
953 if (node && drm_vma_node_is_allowed(node, priv)) {
Lots of NULL checking
954 /*
955 * Skip 0-refcnted objects as it is in the process of
being
956 * destroyed and will be invalid when the vma manager
lock
957 * is released.
958 */
959 if (!node->driver_private) {
960 mmo = container_of(node, struct
i915_mmap_offset, vma_node);
961 obj = i915_gem_object_get_rcu(mmo->obj);
962
963 GEM_BUG_ON(obj && obj->ops->mmap_ops);
964 } else {
965 obj = i915_gem_object_get_rcu
966 (container_of(node, struct
drm_i915_gem_object,
967base.vma_node));
968
969 GEM_BUG_ON(obj && !obj->ops->mmap_ops);
970 }
971 }
972 drm_vma_offset_unlock_lookup(dev->vma_offset_manager);
973 rcu_read_unlock();
974 if (!obj)
975 return node ? -EACCES : -EINVAL;
Checked
976
977 if (i915_gem_object_is_readonly(obj)) {
978 if (vma->vm_flags & VM_WRITE) {
979 i915_gem_object_put(obj);
980 return -EINVAL;
981 }
982 vm_flags_clear(vma, VM_MAYWRITE);
983 }
984
985 anon = mmap_singleton(to_i915(dev));
986 if (IS_ERR(anon)) {
987 i915_gem_object_put(obj);
988 return PTR_ERR(anon);
989 }
990
991 vm_flags_set(vma, VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
VM_IO);
992
993 /*
994 * We keep the ref on mmo->obj, not vm_file, but we require
995 * vma->vm_file->f_mapping, see vma_link(), for later
revocation.
996 * Our userspace is accustomed to having per-file resource
cleanup
997 * (i.e. contexts, objects and requests) on their close(fd),
which
998 * requires avoiding extraneous references to their filp, hence
why
999 * we prefer to use an anonymous file for their mmaps.
1000 */
1001 vma_set_file(vma, anon);
1002 /* Drop the initial creation reference, the vma is now holding
one. */
1003 fput(anon);
1004
1005 if (obj->ops->mmap_ops) {
1006 vma->vm_page_prot =
pgprot_decrypted(vm_get_page_prot(vma->vm_flags));
1007 vma->vm_ops = obj->ops->mmap_ops;
1008 vma->vm_private_data = node->driver_private;
Patch adds unchecked dereference.
1009 return 0;
1010 }
regards,
dan carpenter
[Intel-gfx] [PATCH v2] drm/i915: Fix memory leaks in function live_nop_switch
Be sure to properly free the allocated memory before exiting
the live_nop_switch function.
Signed-off-by: Cong Liu
Suggested-by: Rodrigo Vivi
---
.../gpu/drm/i915/gem/selftests/i915_gem_context.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index a81fa6a20f5a..2fb125d0cb5e 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -66,7 +66,7 @@ static int live_nop_switch(void *arg)
ctx[n] = live_context(i915, file);
if (IS_ERR(ctx[n])) {
err = PTR_ERR(ctx[n]);
- goto out_file;
+ goto out_ctx;
}
}
@@ -82,7 +82,7 @@ static int live_nop_switch(void *arg)
this = igt_request_alloc(ctx[n], engine);
if (IS_ERR(this)) {
err = PTR_ERR(this);
- goto out_file;
+ goto out_ctx;
}
if (rq) {
i915_request_await_dma_fence(this, >fence);
@@ -96,7 +96,7 @@ static int live_nop_switch(void *arg)
intel_gt_set_wedged(to_gt(i915));
i915_request_put(rq);
err = -EIO;
- goto out_file;
+ goto out_ctx;
}
i915_request_put(rq);
@@ -107,7 +107,7 @@ static int live_nop_switch(void *arg)
err = igt_live_test_begin(, i915, __func__, engine->name);
if (err)
- goto out_file;
+ goto out_ctx;
end_time = jiffies + i915_selftest.timeout_jiffies;
for_each_prime_number_from(prime, 2, 8192) {
@@ -120,7 +120,7 @@ static int live_nop_switch(void *arg)
this = igt_request_alloc(ctx[n % nctx], engine);
if (IS_ERR(this)) {
err = PTR_ERR(this);
- goto out_file;
+ goto out_ctx;
}
if (rq) { /* Force submission order */
@@ -165,7 +165,7 @@ static int live_nop_switch(void *arg)
err = igt_live_test_end();
if (err)
- goto out_file;
+ goto out_ctx;
pr_info("Switch latencies on %s: 1 = %lluns, %lu = %lluns\n",
engine->name,
@@ -173,6 +173,8 @@ static int live_nop_switch(void *arg)
prime - 1, div64_u64(ktime_to_ns(times[1]), prime - 1));
}
+out_ctx:
+ kfree(ctx);
out_file:
fput(file);
return err;
--
2.34.1
No virus found
Checked by Hillstone Network AntiVirus
Re: [Intel-gfx] (subset) [PATCH v2 0/7] Move dma-buf mmap() reservation locking down to exporters
On Thu, 06 Apr 2023 19:06:30 +0300, Dmitry Osipenko wrote: > This patchset makes dma-buf exporters responisble for taking care of > the reservation lock. I also included patch that moves drm-shmem to use > reservation lock, to let CI test the whole set. I'm going to take all > the patches via the drm-misc tree, please give an ack. > > Previous policy stated that dma-buf core takes the lock around mmap() > callback. Which meant that both importers and exporters shouldn't touch > the reservation lock in the mmap() code path. This worked well until > Intel-CI found a deadlock problem in a case of self-imported dma-buf [1]. > > [...] Applied, thanks! [4/7] fastrpc: Don't assert held reservation lock for dma-buf mmapping commit: 3f6b4c6f0bd0126f673f3578429239ae3860718b Best regards, -- Srinivas Kandagatla
[Intel-gfx] ✗ Fi.CI.BAT: failure for Use different intel_hdcp_gsc_message instances
== Series Details ==
Series: Use different intel_hdcp_gsc_message instances
URL : https://patchwork.freedesktop.org/series/118009/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13165 -> Patchwork_118009v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_118009v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_118009v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/index.html
Participating hosts (37 -> 38)
--
Additional (2): bat-rpls-2 bat-mtlp-8
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118009v1:
### IGT changes ###
Possible regressions
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-a-edp-1:
- bat-adlp-6: NOTRUN -> [ABORT][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-adlp-6/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-a-edp-1.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@migrate:
- {bat-mtlp-8}: NOTRUN -> [DMESG-FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-mtlp-8/igt@i915_selftest@l...@migrate.html
Known issues
Here are the changes found in Patchwork_118009v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- bat-rpls-2: NOTRUN -> [SKIP][3] ([i915#7456])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-rpls-2/igt@debugfs_t...@basic-hwmon.html
* igt@fbdev@read:
- bat-rpls-2: NOTRUN -> [SKIP][4] ([i915#2582]) +4 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-rpls-2/igt@fb...@read.html
* igt@gem_lmem_swapping@verify-random:
- bat-rpls-2: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-rpls-2/igt@gem_lmem_swapp...@verify-random.html
* igt@gem_tiled_pread_basic:
- bat-rpls-2: NOTRUN -> [SKIP][6] ([i915#3282])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-rpls-2/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-rpls-2: NOTRUN -> [SKIP][7] ([i915#7561])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-rpls-2/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-rpls-2: NOTRUN -> [SKIP][8] ([i915#6621])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-rpls-2/igt@i915_pm_...@basic-api.html
* igt@i915_selftest@live@gt_pm:
- bat-rpls-2: NOTRUN -> [DMESG-FAIL][9] ([i915#4258] / [i915#7913])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][10] ([i915#6367])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][11] ([i915#6687])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_busy@basic:
- bat-rpls-2: NOTRUN -> [SKIP][12] ([i915#1845]) +14 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-rpls-2/igt@kms_b...@basic.html
* igt@kms_chamelium_edid@hdmi-edid-read:
- bat-rpls-2: NOTRUN -> [SKIP][13] ([i915#7828]) +7 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-rpls-2/igt@kms_chamelium_e...@hdmi-edid-read.html
* igt@kms_flip@basic-flip-vs-dpms:
- bat-rpls-2: NOTRUN -> [SKIP][14] ([i915#3637]) +3 similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-rpls-2/igt@kms_f...@basic-flip-vs-dpms.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-rpls-2: NOTRUN -> [SKIP][15] ([fdo#109285])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-rpls-2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- bat-rpls-2: NOTRUN -> [SKIP][16] ([i915#1849])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118009v1/bat-rpls-2/igt@kms_frontbuffer_track...@basic.html
*
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Use different intel_hdcp_gsc_message instances
== Series Details == Series: Use different intel_hdcp_gsc_message instances URL : https://patchwork.freedesktop.org/series/118009/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH v7 6/8] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
> -Original Message-
> From: Dmitry Baryshkov
> Sent: Wednesday, May 17, 2023 3:58 PM
> To: David Airlie ; Daniel Vetter ; Jani
> Nikula ; Kandpal, Suraj
> ; Joonas Lahtinen
> ; Vivi, Rodrigo ;
> Tvrtko Ursulin ; Rob Clark
> ; Abhinav Kumar ;
> Sean Paul ; Marijn Suijten
>
> Cc: Ville Syrjälä ; dri-
> de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; linux-arm-
> m...@vger.kernel.org; freedr...@lists.freedesktop.org
> Subject: [PATCH v7 6/8] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR)
> parameters
>
> The array of rc_parameters contains a mixture of parameters from DSC 1.1
> and DSC 1.2 standards. Split these tow configuration arrays in preparation to
> adding more configuration data.
>
LGTM.
Reviewed-by: Suraj Kandpal
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 139 ++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> include/drm/display/drm_dsc_helper.h | 7 +-
> 3 files changed, 129 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
> b/drivers/gpu/drm/display/drm_dsc_helper.c
> index acb93d4116e0..f1ba39df5708 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -325,10 +325,88 @@ struct rc_parameters_data {
> #define DSC_BPP(bpp) ((bpp) << 4)
>
> /*
> - * Selected Rate Control Related Parameter Recommended Values
> - * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> + * Rate Control Related Parameter Recommended Values from DSC_v1.1
> spec
> + prior
> + * to DSC 1.1 fractional bpp underflow SCR (DSC_v1.1_E1.pdf)
> + *
> + * Cross-checked against C Model releases: DSC_model_20161212 and
> + 20210623
> */
> -static const struct rc_parameters_data rc_parameters[] = {
> +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> + {
> + .bpp = DSC_BPP(8), .bpc = 8,
> + { 512, 12, 6144, 3, 12, 11, 11, {
> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12,
> -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 10,
> + { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for
> range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12,
> -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16,
> -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 12,
> + { 512, 12, 6144, 11, 20, 19, 19, {
> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11,
> 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 8,
> + { 341, 15, 2048, 3, 12, 11, 11, {
> + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13,
> 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 10,
> + { 341, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8
> },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16,
> -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 12,
> + { 341, 15, 2048, 11, 20, 19, 19, {
> + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11,
> 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> +
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Allow user to set cache at BO creation (rev10)
== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation (rev10)
URL : https://patchwork.freedesktop.org/series/116870/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13165_full -> Patchwork_116870v10_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116870v10_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_force_connector_basic@force-connector-state:
- {shard-tglu}: [PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13165/shard-tglu-4/igt@kms_force_connector_ba...@force-connector-state.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/shard-tglu-8/igt@kms_force_connector_ba...@force-connector-state.html
Known issues
Here are the changes found in Patchwork_116870v10_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13165/shard-apl2/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/shard-apl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#3886]) +3
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/shard-glk8/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_cursor_crc@cursor-random-max-size:
- shard-glk: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4579]) +2
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/shard-glk8/igt@kms_cursor_...@cursor-random-max-size.html
* igt@kms_draw_crc@draw-method-blt@xrgb2101010-ytiled:
- shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#7936])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13165/shard-glk9/igt@kms_draw_crc@draw-method-...@xrgb2101010-ytiled.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/shard-glk7/igt@kms_draw_crc@draw-method-...@xrgb2101010-ytiled.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#79])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13165/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@ac-hdmi-a1-hdmi-a2.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@ac-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@psr-slowdraw:
- shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271]) +18 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/shard-glk8/igt@kms_frontbuffer_track...@psr-slowdraw.html
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271]) +16 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/shard-snb2/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0...@pipe-a-vga-1.html
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4579]) +12
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/shard-snb2/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0...@pipe-b-vga-1.html
Possible fixes
* igt@gem_barrier_race@remote-request@rcs0:
- shard-glk: [ABORT][14] ([i915#7461] / [i915#8211]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13165/shard-glk4/igt@gem_barrier_race@remote-requ...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/shard-glk8/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@gem_ctx_freq@sysfs:
- {shard-dg1}:[FAIL][16] ([i915#6786]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13165/shard-dg1-17/igt@gem_ctx_f...@sysfs.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/shard-dg1-16/igt@gem_ctx_f...@sysfs.html
* igt@gem_ctx_persistence@smoketest:
- {shard-rkl}:[FAIL][18] ([i915#5099]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13165/shard-rkl-6/igt@gem_ctx_persiste...@smoketest.html
[19]:
Re: [Intel-gfx] [PATCH i-g-t v3] tests/i915: Exercise coherency of mmapped frame buffers
On 19.05.2023 11:43, Janusz Krzysztofik wrote:
Visible glitches have been observed when running graphics applications on
Linux under Xen hypervisor. Those observations have been confirmed with
failures from kms_pwrite_crc IGT test that verifies data coherency of DRM
frame buffer objects using hardware CRC checksums calculated by display
controllers, exposed to userspace via debugfs. Since not all applications
exhibit the issue, we need to exercise more methods than just pwrite in
order to identify all affected processing paths.
Create a new test focused on exercising coherency of future scanout
buffers populated over mmap. Cover all available mmap methods and caching
modes expected to be device coherent.
v3: Drop redundant prerequisite checks (Andrzej),
- if (condition) return; construct gives shorter code than
if (!condition) continue; (Andrzej),
- gem_has_lmem() implies gem_has_mmap_offset(), flatten related nested
conditions.
v2: Drop unused functions -- left-overs from unsuccessful negative subtest
attempts requiring consistent crc mismatches in non-coherent modes,
- since all subtests now call igt_assert_crc_equal(), move it from
subtest bodies to an updated and renamed helper,
- drop "derived from ..." info from copyrights comment (Kamil),
- fix order of includes (Kamil),
- fix whitespace (Kamil),
- Cc: Bhanuprakash (Kamil).
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7648
Cc: Bhanuprakash Modem
Reviewed-by: Andrzej Hajda # v2
Signed-off-by: Janusz Krzysztofik
---
Hi Andrzej,
Your requested optimisations applied. I've introduced one more
optimisation -- see changelog. Please confirm your R-b still applies.
Yes, it applies :)
Regards
Andrzej
Thanks,
Janusz
tests/i915/kms_fb_coherency.c | 288 ++
tests/meson.build | 1 +
2 files changed, 289 insertions(+)
create mode 100644 tests/i915/kms_fb_coherency.c
diff --git a/tests/i915/kms_fb_coherency.c b/tests/i915/kms_fb_coherency.c
new file mode 100644
index 00..b530bf5dcd
--- /dev/null
+++ b/tests/i915/kms_fb_coherency.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+/**
+ * TEST: kms_fb_coherency
+ * Description: Exercise coherency of future scanout buffer objects
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "igt.h"
+
+typedef struct {
+ int drm_fd;
+ igt_display_t display;
+ struct igt_fb fb[2];
+ igt_output_t *output;
+ igt_plane_t *primary;
+ enum pipe pipe;
+ igt_crc_t ref_crc;
+ igt_pipe_crc_t *pipe_crc;
+ uint32_t devid;
+} data_t;
+
+static void prepare_crtc(data_t *data)
+{
+ igt_display_t *display = >display;
+ igt_output_t *output = data->output;
+ drmModeModeInfo *mode;
+
+ igt_display_reset(display);
+ /* select the pipe we want to use */
+ igt_output_set_pipe(output, data->pipe);
+
+ mode = igt_output_get_mode(output);
+
+ /* create a white reference fb and flip to it */
+ igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB, DRM_FORMAT_MOD_LINEAR,
+ 1.0, 1.0, 1.0, >fb[0]);
+
+ data->primary = igt_output_get_plane_type(output,
DRM_PLANE_TYPE_PRIMARY);
+
+ igt_plane_set_fb(data->primary, >fb[0]);
+ igt_display_commit(display);
+
+ if (data->pipe_crc)
+ igt_pipe_crc_free(data->pipe_crc);
+
+ data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe,
+ IGT_PIPE_CRC_SOURCE_AUTO);
+
+ /* get reference crc for the white fb */
+ igt_pipe_crc_collect_crc(data->pipe_crc, >ref_crc);
+}
+
+static struct igt_fb *prepare_fb(data_t *data)
+{
+ igt_output_t *output = data->output;
+ struct igt_fb *fb = >fb[1];
+ drmModeModeInfo *mode;
+
+ prepare_crtc(data);
+
+ mode = igt_output_get_mode(output);
+
+ /* create a non-white fb we can overwrite later */
+ igt_create_pattern_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB, DRM_FORMAT_MOD_LINEAR, fb);
+
+ /* flip to it to make it UC/WC and fully flushed */
+ drmModeSetPlane(data->drm_fd,
+ data->primary->drm_plane->plane_id,
+ output->config.crtc->crtc_id,
+ fb->fb_id, 0,
+ 0, 0, fb->width, fb->height,
+ 0, 0, fb->width << 16, fb->height << 16);
+
+ /* flip back the original white buffer */
+ drmModeSetPlane(data->drm_fd,
+ data->primary->drm_plane->plane_id,
+ output->config.crtc->crtc_id,
+ data->fb[0].fb_id, 0,
+ 0, 0, fb->width, fb->height,
+ 0, 0, fb->width << 16,
[Intel-gfx] [PATCH 2/2] drm/i915/hdcp: Fill in hdcp_gsc_out message
Fill out hdcp_gsc_message_in and hdcp_gsc_message_out structure
which also includes differentiating header of both messages
using header_in and header_out.
Cc: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: Ankit Nautiyal
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 59 +++
1 file changed, 34 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
index be505b2d679e..ab47724f7f05 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
@@ -738,38 +738,42 @@ void intel_hdcp_gsc_fini(struct drm_i915_private *i915)
}
static int intel_gsc_send_sync(struct drm_i915_private *i915,
- struct intel_gsc_mtl_header *header, u64 addr,
+ struct intel_gsc_mtl_header *header_in,
+ struct intel_gsc_mtl_header *header_out,
+ u64 addr_in, u64 addr_out,
size_t msg_out_len)
{
struct intel_gt *gt = i915->media_gt;
int ret;
- header->flags = 0;
- ret = intel_gsc_uc_heci_cmd_submit_packet(>uc.gsc, addr,
- header->message_size,
- addr,
- msg_out_len +
sizeof(*header));
+ ret = intel_gsc_uc_heci_cmd_submit_packet(>uc.gsc, addr_in,
+ header_in->message_size,
+ addr_out,
+ msg_out_len +
sizeof(*header_in));
if (ret) {
drm_err(>drm, "failed to send gsc HDCP msg (%d)\n", ret);
return ret;
}
/*
-* Checking validity marker for memory sanity
+* Check validity marker and status to see if some error is
+* blocking SW to FW communication
*/
- if (header->validity_marker != GSC_HECI_VALIDITY_MARKER) {
+ if (header_out->validity_marker != GSC_HECI_VALIDITY_MARKER) {
drm_err(>drm, "invalid validity marker\n");
return -EINVAL;
}
- if (header->status != 0) {
+ if (header_out->status != 0) {
drm_err(>drm, "header status indicates error %d\n",
- header->status);
+ header_out->status);
return -EINVAL;
}
- if (header->flags & GSC_OUTFLAG_MSG_PENDING)
+ if (header_out->flags & GSC_OUTFLAG_MSG_PENDING) {
+ header_in->gsc_message_handle = header_out->gsc_message_handle;
return -EAGAIN;
+ }
return 0;
}
@@ -786,10 +790,10 @@ ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private
*i915, u8 *msg_in,
size_t msg_out_len)
{
struct intel_gt *gt = i915->media_gt;
- struct intel_gsc_mtl_header *header;
- const size_t max_msg_size = PAGE_SIZE - sizeof(*header);
- struct intel_hdcp_gsc_message *hdcp_message;
- u64 addr, host_session_id;
+ struct intel_gsc_mtl_header *header_in, *header_out;
+ const size_t max_msg_size = PAGE_SIZE - sizeof(*header_in);
+ struct intel_hdcp_gsc_message *hdcp_message_in, *hdcp_message_out;
+ u64 addr_in, addr_out, host_session_id;
u32 reply_size, msg_size;
int ret, tries = 0;
@@ -799,16 +803,20 @@ ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private
*i915, u8 *msg_in,
if (msg_in_len > max_msg_size || msg_out_len > max_msg_size)
return -ENOSPC;
- hdcp_message = i915->display.hdcp.hdcp_message_in;
- header = hdcp_message->hdcp_cmd;
- addr = i915_ggtt_offset(hdcp_message->vma);
+ hdcp_message_in = i915->display.hdcp.hdcp_message_in;
+ hdcp_message_out = i915->display.hdcp.hdcp_message_out;
+ header_in = hdcp_message_in->hdcp_cmd;
+ header_out = hdcp_message_out->hdcp_cmd;
+ addr_in = i915_ggtt_offset(hdcp_message_in->vma);
+ addr_out = i915_ggtt_offset(hdcp_message_out->vma);
- msg_size = msg_in_len + sizeof(*header);
- memset(header, 0, msg_size);
+ msg_size = msg_in_len + sizeof(*header_in);
+ memset(header_in, 0, msg_size);
+ memset(header_out, 0, msg_size);
get_random_bytes(_session_id, sizeof(u64));
- intel_gsc_uc_heci_cmd_emit_mtl_header(header, HECI_MEADDRESS_HDCP,
+ intel_gsc_uc_heci_cmd_emit_mtl_header(header_in, HECI_MEADDRESS_HDCP,
msg_size, host_session_id);
- memcpy(hdcp_message->hdcp_cmd + sizeof(*header), msg_in, msg_in_len);
+ memcpy(hdcp_message_in->hdcp_cmd + sizeof(*header_in), msg_in,
msg_in_len);
/*
* Keep sending request in case the pending bit
[Intel-gfx] [PATCH 1/2] drm/i915/hdcp: Create hdcp_gsc_message in and out
Add hdcp_gsc_message_in and hdcp_gsc_message_out to help
differenctiate the reply given by gsc to avoid any kind of
message corruption due message structure reuse.
hdcp_gsc_message_out will be filled in upcoming patches
Cc: Ankit Nautiyal
Cc: Alan Previn
Cc: Daniele Ceraolo Spurio
Signed-off-by: Suraj Kandpal
---
.../gpu/drm/i915/display/intel_display_core.h | 3 +-
drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 41 +--
2 files changed, 31 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index e36f88a39b86..ead16d341f5c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -403,7 +403,8 @@ struct intel_display {
* reused when sending message to gsc cs.
* this is only populated post Meteorlake
*/
- struct intel_hdcp_gsc_message *hdcp_message;
+ struct intel_hdcp_gsc_message *hdcp_message_in;
+ struct intel_hdcp_gsc_message *hdcp_message_out;
/* Mutex to protect the above hdcp component related values. */
struct mutex comp_mutex;
} hdcp;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
index 7e52aea6aa17..be505b2d679e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
@@ -665,34 +665,51 @@ static int intel_hdcp_gsc_initialize_message(struct
drm_i915_private *i915,
static int intel_hdcp_gsc_hdcp2_init(struct drm_i915_private *i915)
{
- struct intel_hdcp_gsc_message *hdcp_message;
+ struct intel_hdcp_gsc_message *hdcp_message_in, *hdcp_message_out;
int ret;
- hdcp_message = kzalloc(sizeof(*hdcp_message), GFP_KERNEL);
+ hdcp_message_in = kzalloc(sizeof(*hdcp_message_in), GFP_KERNEL);
- if (!hdcp_message)
+ if (!hdcp_message_in)
return -ENOMEM;
+ hdcp_message_out = kzalloc(sizeof(*hdcp_message_out), GFP_KERNEL);
+
+ if (!hdcp_message_out)
+ return -ENOMEM;
/*
* NOTE: No need to lock the comp mutex here as it is already
* going to be taken before this function called
*/
- i915->display.hdcp.hdcp_message = hdcp_message;
- ret = intel_hdcp_gsc_initialize_message(i915, hdcp_message);
+ i915->display.hdcp.hdcp_message_in = hdcp_message_in;
+ ret = intel_hdcp_gsc_initialize_message(i915, hdcp_message_in);
+
+ if (ret) {
+ drm_err(>drm, "Could not initialize hdcp_message_in\n");
+ goto out;
+ }
+
+ i915->display.hdcp.hdcp_message_out = hdcp_message_out;
+ ret = intel_hdcp_gsc_initialize_message(i915, hdcp_message_out);
if (ret)
- drm_err(>drm, "Could not initialize hdcp_message\n");
+ drm_err(>drm, "Could not initialize hdcp_message_out\n");
+out:
return ret;
}
static void intel_hdcp_gsc_free_message(struct drm_i915_private *i915)
{
- struct intel_hdcp_gsc_message *hdcp_message =
- i915->display.hdcp.hdcp_message;
-
- i915_vma_unpin_and_release(_message->vma, I915_VMA_RELEASE_MAP);
- kfree(hdcp_message);
+ struct intel_hdcp_gsc_message *hdcp_message_in =
+ i915->display.hdcp.hdcp_message_in;
+ struct intel_hdcp_gsc_message *hdcp_message_out =
+ i915->display.hdcp.hdcp_message_out;
+
+ i915_vma_unpin_and_release(_message_in->vma, I915_VMA_RELEASE_MAP);
+ i915_vma_unpin_and_release(_message_out->vma,
I915_VMA_RELEASE_MAP);
+ kfree(hdcp_message_in);
+ kfree(hdcp_message_out);
}
int intel_hdcp_gsc_init(struct drm_i915_private *i915)
@@ -782,7 +799,7 @@ ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private
*i915, u8 *msg_in,
if (msg_in_len > max_msg_size || msg_out_len > max_msg_size)
return -ENOSPC;
- hdcp_message = i915->display.hdcp.hdcp_message;
+ hdcp_message = i915->display.hdcp.hdcp_message_in;
header = hdcp_message->hdcp_cmd;
addr = i915_ggtt_offset(hdcp_message->vma);
--
2.25.1
[Intel-gfx] [PATCH 0/2] Use different intel_hdcp_gsc_message instances
Use different intel_hdcp_gsc_message instances to send and receive the messages from gsc since there are chances using the same instance can cause corruption of data. Signed-off-by: Suraj Kandpal Suraj Kandpal (2): drm/i915/hdcp: Create hdcp_gsc_message in and out drm/i915/hdcp: Fill in hdcp_gsc_out message .../gpu/drm/i915/display/intel_display_core.h | 3 +- drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 98 --- 2 files changed, 64 insertions(+), 37 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH i-g-t v3] tests/i915: Exercise coherency of mmapped frame buffers
Visible glitches have been observed when running graphics applications on
Linux under Xen hypervisor. Those observations have been confirmed with
failures from kms_pwrite_crc IGT test that verifies data coherency of DRM
frame buffer objects using hardware CRC checksums calculated by display
controllers, exposed to userspace via debugfs. Since not all applications
exhibit the issue, we need to exercise more methods than just pwrite in
order to identify all affected processing paths.
Create a new test focused on exercising coherency of future scanout
buffers populated over mmap. Cover all available mmap methods and caching
modes expected to be device coherent.
v3: Drop redundant prerequisite checks (Andrzej),
- if (condition) return; construct gives shorter code than
if (!condition) continue; (Andrzej),
- gem_has_lmem() implies gem_has_mmap_offset(), flatten related nested
conditions.
v2: Drop unused functions -- left-overs from unsuccessful negative subtest
attempts requiring consistent crc mismatches in non-coherent modes,
- since all subtests now call igt_assert_crc_equal(), move it from
subtest bodies to an updated and renamed helper,
- drop "derived from ..." info from copyrights comment (Kamil),
- fix order of includes (Kamil),
- fix whitespace (Kamil),
- Cc: Bhanuprakash (Kamil).
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7648
Cc: Bhanuprakash Modem
Reviewed-by: Andrzej Hajda # v2
Signed-off-by: Janusz Krzysztofik
---
Hi Andrzej,
Your requested optimisations applied. I've introduced one more
optimisation -- see changelog. Please confirm your R-b still applies.
Thanks,
Janusz
tests/i915/kms_fb_coherency.c | 288 ++
tests/meson.build | 1 +
2 files changed, 289 insertions(+)
create mode 100644 tests/i915/kms_fb_coherency.c
diff --git a/tests/i915/kms_fb_coherency.c b/tests/i915/kms_fb_coherency.c
new file mode 100644
index 00..b530bf5dcd
--- /dev/null
+++ b/tests/i915/kms_fb_coherency.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+/**
+ * TEST: kms_fb_coherency
+ * Description: Exercise coherency of future scanout buffer objects
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "igt.h"
+
+typedef struct {
+ int drm_fd;
+ igt_display_t display;
+ struct igt_fb fb[2];
+ igt_output_t *output;
+ igt_plane_t *primary;
+ enum pipe pipe;
+ igt_crc_t ref_crc;
+ igt_pipe_crc_t *pipe_crc;
+ uint32_t devid;
+} data_t;
+
+static void prepare_crtc(data_t *data)
+{
+ igt_display_t *display = >display;
+ igt_output_t *output = data->output;
+ drmModeModeInfo *mode;
+
+ igt_display_reset(display);
+ /* select the pipe we want to use */
+ igt_output_set_pipe(output, data->pipe);
+
+ mode = igt_output_get_mode(output);
+
+ /* create a white reference fb and flip to it */
+ igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB, DRM_FORMAT_MOD_LINEAR,
+ 1.0, 1.0, 1.0, >fb[0]);
+
+ data->primary = igt_output_get_plane_type(output,
DRM_PLANE_TYPE_PRIMARY);
+
+ igt_plane_set_fb(data->primary, >fb[0]);
+ igt_display_commit(display);
+
+ if (data->pipe_crc)
+ igt_pipe_crc_free(data->pipe_crc);
+
+ data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe,
+ IGT_PIPE_CRC_SOURCE_AUTO);
+
+ /* get reference crc for the white fb */
+ igt_pipe_crc_collect_crc(data->pipe_crc, >ref_crc);
+}
+
+static struct igt_fb *prepare_fb(data_t *data)
+{
+ igt_output_t *output = data->output;
+ struct igt_fb *fb = >fb[1];
+ drmModeModeInfo *mode;
+
+ prepare_crtc(data);
+
+ mode = igt_output_get_mode(output);
+
+ /* create a non-white fb we can overwrite later */
+ igt_create_pattern_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB, DRM_FORMAT_MOD_LINEAR, fb);
+
+ /* flip to it to make it UC/WC and fully flushed */
+ drmModeSetPlane(data->drm_fd,
+ data->primary->drm_plane->plane_id,
+ output->config.crtc->crtc_id,
+ fb->fb_id, 0,
+ 0, 0, fb->width, fb->height,
+ 0, 0, fb->width << 16, fb->height << 16);
+
+ /* flip back the original white buffer */
+ drmModeSetPlane(data->drm_fd,
+ data->primary->drm_plane->plane_id,
+ output->config.crtc->crtc_id,
+ data->fb[0].fb_id, 0,
+ 0, 0, fb->width, fb->height,
+ 0, 0, fb->width << 16, fb->height << 16);
+
+ if (!gem_has_lmem(data->drm_fd)) {
+ uint32_t caching;
+
+
Re: [Intel-gfx] [PATCH v4] drm/i915: avoid flush_scheduled_work() usage
On 18/05/2023 15:44, Tetsuo Handa wrote:
Like commit c4f135d643823a86 ("workqueue: Wrap flush_workqueue() using a
macro") says, flush_scheduled_work() is dangerous and will be forbidden.
i915 became the last flush_scheduled_work() user, but developers cannot
find time for auditing which work items does this flush_scheduled_work()
need to wait.
Therefore, for now let's start with blind/mechanical conversion within
the whole drivers/gpu/drm/i915/ directory, based on an assumption that
i915 does not need to wait for work items outside of this directory.
Link: https://lkml.kernel.org/r/87sfeita1p@intel.com
Signed-off-by: Tetsuo Handa
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Ville Syrjälä
---
Changes in v4:
Refreshed using drm-tip.git.
Changes in v3:
Refreshed using drm-tip.git, for commit 40053823baad ("drm/i915/display:
move modeset probe/remove functions to intel_display_driver.c") moved
flush_scheduled_work() from intel_display.c to intel_display_driver.c .
Please check the comment from Daniel Vetter at
https://lkml.kernel.org/r/ZDuntOkUeh0Eve8a@phenom.ffwll.local .
I can't help with that display code assesment but in general the
approach with a driver global wq works for me.
Acked-by: Tvrtko Ursulin
I haven't read the patch in detail, just one thing caught my eye which
is that we already have a workqueue named "i915" (see
i915_workqueues_init). So I'd suggest naming the one from this patch
"i915-global" or something. Just so it is clearer if/when debugging aids
start firing what is what.
Regards,
Tvrtko
Changes in v2:
Add missing alloc_workqueue() failure check.
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
.../drm/i915/display/intel_display_driver.c| 2 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c| 2 +-
.../drm/i915/display/intel_dp_link_training.c | 2 +-
drivers/gpu/drm/i915/display/intel_drrs.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 18 +-
drivers/gpu/drm/i915/display/intel_hotplug.c | 12 ++--
drivers/gpu/drm/i915/display/intel_opregion.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 6 +++---
.../drm/i915/gt/intel_execlists_submission.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c | 8
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_requests.c| 10 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c| 14 +++---
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_module.c | 7 +++
drivers/gpu/drm/i915/i915_request.c| 2 +-
drivers/gpu/drm/i915/intel_wakeref.c | 4 +++-
drivers/gpu/drm/i915/selftests/i915_sw_fence.c | 4 +++-
25 files changed, 64 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 09320e14d75c..5f1ba9c908cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7145,7 +7145,7 @@ intel_atomic_commit_ready(struct i915_sw_fence *fence,
_i915(state->base.dev)->display.atomic_helper;
if (llist_add(>freed, >free_list))
- schedule_work(>free_work);
+ queue_work(i915_wq, >free_work);
break;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 60ce10fc7205..a20a9cfaab0e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -435,7 +435,7 @@ void intel_display_driver_remove_noirq(struct
drm_i915_private *i915)
intel_unregister_dsm_handler();
/* flush any delayed tasks or pending work */
- flush_scheduled_work();
+ flush_workqueue(i915_wq);
intel_hdcp_component_fini(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 8a88de67ff0a..57d015006784 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1057,7 +1057,7 @@ void intel_dmc_init(struct drm_i915_private *i915)
i915->display.dmc.dmc = dmc;
drm_dbg_kms(>drm, "Loading %s\n", dmc->fw_path);
- schedule_work(>work);
+ queue_work(i915_wq, >work);
return;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4bec8cd7979f..4782bdfc7c61
Re: [Intel-gfx] [PATCH v5 06/10] vfio-iommufd: Add helper to retrieve iommufd_ctx and devid for vfio_device
> From: Liu, Yi L
> Sent: Thursday, May 18, 2023 9:26 PM
> > > +int vfio_iommufd_physical_devid(struct vfio_device *vdev)
> > > +{
> > > + if (vdev->iommufd_device)
> > > + return iommufd_device_to_id(vdev->iommufd_device);
> > > + if (vdev->noiommu_access)
> > > + return iommufd_access_to_id(vdev->noiommu_access);
> > > + return -EINVAL;
> > > +}
> > > +EXPORT_SYMBOL_GPL(vfio_iommufd_physical_devid);
> >
> > I think these exemplify that it would be better if both emulated and
> > noiommu use the same iommufd_access pointer. Thanks,
>
> Sure. Then I shall rename this helper. vfio_iommufd_device_devid()
> What about your opinion?
>
Probably just vfio_iommufd_device_id().
Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: create workqueue dedicated to wake references
On 17/05/2023 12:18, Coelho, Luciano wrote:
On Fri, 2023-05-12 at 13:16 +0100, Tvrtko Ursulin wrote:
On 12/05/2023 10:54, Coelho, Luciano wrote:
On Fri, 2023-05-12 at 10:32 +0100, Tvrtko Ursulin wrote:
On 12/05/2023 10:10, Coelho, Luciano wrote:
On Fri, 2023-05-12 at 10:04 +0100, Tvrtko Ursulin wrote:
On 11/05/2023 09:20, Luca Coelho wrote:
Add a work queue in the intel_wakeref structure to be used exclusively
by the wake reference mechanism. This is needed in order to avoid
using the system workqueue and relying on flush_scheduled_work().
Cc: Tetsuo Handa
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Luca Coelho
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++-
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 15 --
drivers/gpu/drm/i915/gt/intel_engine_pm.h | 3 ++-
drivers/gpu/drm/i915/gt/mock_engine.c | 8 +++-
drivers/gpu/drm/i915/intel_wakeref.c | 21 ++-
drivers/gpu/drm/i915/intel_wakeref.h | 25 +++
6 files changed, 60 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 0aff5bb13c53..6505bfa70cd0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1290,7 +1290,11 @@ static int engine_setup_common(struct intel_engine_cs
*engine)
goto err_cmd_parser;
intel_engine_init_execlists(engine);
- intel_engine_init__pm(engine);
+
+ err = intel_engine_init__pm(engine);
+ if (err)
+ goto err_cmd_parser;
+
intel_engine_init_retire(engine);
/* Use the whole device by default */
@@ -1525,6 +1529,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
{
GEM_BUG_ON(!list_empty(>sched_engine->requests));
+ intel_engine_destroy__pm(engine);
i915_sched_engine_put(engine->sched_engine);
intel_breadcrumbs_put(engine->breadcrumbs);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index ee531a5c142c..859b62cf660f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -294,14 +294,25 @@ static const struct intel_wakeref_ops wf_ops = {
.put = __engine_park,
};
-void intel_engine_init__pm(struct intel_engine_cs *engine)
+int intel_engine_init__pm(struct intel_engine_cs *engine)
{
struct intel_runtime_pm *rpm = engine->uncore->rpm;
+ int err;
+
+ err = intel_wakeref_init(>wakeref, rpm, _ops);
+ if (err)
+ return err;
- intel_wakeref_init(>wakeref, rpm, _ops);
intel_engine_init_heartbeat(engine);
intel_gsc_idle_msg_enable(engine);
+
+ return 0;
+}
+
+void intel_engine_destroy__pm(struct intel_engine_cs *engine)
+{
+ intel_wakeref_destroy(>wakeref);
}
/**
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.h
b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
index d68675925b79..e8568f7d10c6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
@@ -104,7 +104,8 @@ intel_engine_create_kernel_request(struct intel_engine_cs
*engine)
return rq;
}
-void intel_engine_init__pm(struct intel_engine_cs *engine);
+int intel_engine_init__pm(struct intel_engine_cs *engine);
+void intel_engine_destroy__pm(struct intel_engine_cs *engine);
void intel_engine_reset_pinned_contexts(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
index c0637bf799a3..0a3c702c21e2 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -336,6 +336,7 @@ static void mock_engine_release(struct intel_engine_cs
*engine)
intel_context_put(engine->kernel_context);
intel_engine_fini_retire(engine);
+ intel_engine_destroy__pm(engine);
}
struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
@@ -393,6 +394,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private
*i915,
int mock_engine_init(struct intel_engine_cs *engine)
{
struct intel_context *ce;
+ int err;
INIT_LIST_HEAD(>pinned_contexts_list);
@@ -402,7 +404,11 @@ int mock_engine_init(struct intel_engine_cs *engine)
engine->sched_engine->private_data = engine;
intel_engine_init_execlists(engine);
- intel_engine_init__pm(engine);
+
+ err = intel_engine_init__pm(engine);
+ if (err)
+ return err;
+
intel_engine_init_retire(engine);
engine->breadcrumbs = intel_breadcrumbs_create(NULL);
diff --git a/drivers/gpu/drm/i915/intel_wakeref.c
b/drivers/gpu/drm/i915/intel_wakeref.c
index dfd87d082218..6bae609e1312 100644
---
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow user to set cache at BO creation (rev10)
== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation (rev10)
URL : https://patchwork.freedesktop.org/series/116870/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13165 -> Patchwork_116870v10
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/index.html
Participating hosts (37 -> 37)
--
Additional (1): bat-rpls-2
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116870v10:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@requests:
- {bat-mtlp-6}: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13165/bat-mtlp-6/igt@i915_selftest@l...@requests.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/bat-mtlp-6/igt@i915_selftest@l...@requests.html
Known issues
Here are the changes found in Patchwork_116870v10 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- bat-rpls-2: NOTRUN -> [SKIP][3] ([i915#7456])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/bat-rpls-2/igt@debugfs_t...@basic-hwmon.html
* igt@fbdev@read:
- bat-rpls-2: NOTRUN -> [SKIP][4] ([i915#2582]) +4 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/bat-rpls-2/igt@fb...@read.html
* igt@gem_lmem_swapping@verify-random:
- bat-rpls-2: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/bat-rpls-2/igt@gem_lmem_swapp...@verify-random.html
* igt@gem_tiled_pread_basic:
- bat-rpls-2: NOTRUN -> [SKIP][6] ([i915#3282])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/bat-rpls-2/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-rpls-2: NOTRUN -> [SKIP][7] ([i915#7561])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/bat-rpls-2/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-rpls-2: NOTRUN -> [SKIP][8] ([i915#6621])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/bat-rpls-2/igt@i915_pm_...@basic-api.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [PASS][9] -> [DMESG-FAIL][10] ([i915#5334] /
[i915#7872])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13165/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- bat-rpls-2: NOTRUN -> [DMESG-FAIL][11] ([i915#4258] / [i915#7913])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][12] ([i915#6687])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
- fi-rkl-11600: [PASS][13] -> [FAIL][14] ([fdo#103375])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13165/fi-rkl-11600/igt@i915_susp...@basic-s2idle-without-i915.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/fi-rkl-11600/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_busy@basic:
- bat-rpls-2: NOTRUN -> [SKIP][15] ([i915#1845]) +14 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/bat-rpls-2/igt@kms_b...@basic.html
* igt@kms_chamelium_edid@hdmi-edid-read:
- bat-rpls-2: NOTRUN -> [SKIP][16] ([i915#7828]) +7 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/bat-rpls-2/igt@kms_chamelium_e...@hdmi-edid-read.html
* igt@kms_flip@basic-flip-vs-dpms:
- bat-rpls-2: NOTRUN -> [SKIP][17] ([i915#3637]) +3 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/bat-rpls-2/igt@kms_f...@basic-flip-vs-dpms.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-rpls-2: NOTRUN -> [SKIP][18] ([fdo#109285])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/bat-rpls-2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- bat-rpls-2: NOTRUN -> [SKIP][19] ([i915#1849])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v10/bat-rpls-2/igt@kms_frontbuffer_track...@basic.html
*
