[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: GSC FW support for MTL (rev3)
== Series Details ==
Series: drm/i915: GSC FW support for MTL (rev3)
URL : https://patchwork.freedesktop.org/series/117396/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13234 -> Patchwork_117396v3
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/index.html
Participating hosts (38 -> 36)
--
Missing(2): fi-kbl-soraka fi-snb-2520m
Known issues
Here are the changes found in Patchwork_117396v3 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [PASS][1] -> [ABORT][2] ([i915#7911] / [i915#7913])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@migrate:
- bat-adlp-9: [PASS][3] -> [DMESG-FAIL][4] ([i915#7699] /
[i915#7913])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-adlp-9/igt@i915_selftest@l...@migrate.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/bat-adlp-9/igt@i915_selftest@l...@migrate.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][5] -> [ABORT][6] ([i915#4983] / [i915#7911] /
[i915#7920])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-rpls-1/igt@i915_selftest@l...@requests.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/bat-rpls-1/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@workarounds:
- bat-adlm-1: [PASS][7] -> [INCOMPLETE][8] ([i915#4983] /
[i915#7677])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-adlp-9: NOTRUN -> [SKIP][9] ([i915#3546]) +2 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/bat-adlp-9/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1:
- bat-dg2-8: [PASS][10] -> [FAIL][11] ([i915#7932])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html
Possible fixes
* igt@i915_pm_rpm@basic-pci-d3-state:
- {bat-mtlp-8}: [ABORT][12] ([i915#7953]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-mtlp-8/igt@i915_pm_...@basic-pci-d3-state.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/bat-mtlp-8/igt@i915_pm_...@basic-pci-d3-state.html
* {igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-d-dp-5}:
- {bat-adlp-11}: [ABORT][14] ([i915#4423]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-d-dp-5.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-d-dp-5.html
Warnings
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][16] ([i915#4983] / [i915#7461] / [i915#7913]
/ [i915#7981] / [i915#8347]) -> [ABORT][17] ([i915#4983] / [i915#7461] /
[i915#7913] / [i915#8347])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-rpls-2/igt@i915_selftest@l...@reset.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/bat-rpls-2/igt@i915_selftest@l...@reset.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [SKIP][18] ([i915#3555] / [i915#4579]) -> [ABORT][19]
([i915#4579] / [i915#8260])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: GSC FW support for MTL (rev3)
== Series Details == Series: drm/i915: GSC FW support for MTL (rev3) URL : https://patchwork.freedesktop.org/series/117396/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GSC FW support for MTL (rev3)
== Series Details == Series: drm/i915: GSC FW support for MTL (rev3) URL : https://patchwork.freedesktop.org/series/117396/ State : warning == Summary == Error: dim checkpatch failed b8b9ea4aab9a drm/i915/gsc: fixes and updates for GSC memory allocation a3b0ea9a67d7 drm/i915/mtl/gsc: extract release and security versions from the gsc binary -:83: CHECK:LINE_SPACING: Please don't use multiple blank lines #83: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h:64: + + -:92: ERROR:SPACING: space required after that ',' (ctx:VxV) #92: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h:73: +#define INTEL_GSC_BPDT_ENTRY_TYPE_MASK GENMASK(15,0) ^ -:282: CHECK:LINE_SPACING: Please don't use multiple blank lines #282: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c:196: + + total: 1 errors, 0 warnings, 2 checks, 395 lines checked bcc84b63080f drm/i915/mtl/gsc: query the GSC FW for its compatibility version -:104: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #104: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c:370: + gt_err(gt, "invalid GSC reply length %u [expected %zu], s=0x%x, f=0x%x, r=0x%x\n", + msg_out->header.message_size, sizeof(*msg_out), total: 0 errors, 0 warnings, 1 checks, 193 lines checked 2d081dbad641 drm/i915/mtl/gsc: Add a gsc_info debugfs Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:147: CHECK:LINE_SPACING: Please don't use multiple blank lines #147: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c:330: + + -:189: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #189: new file mode 100644 -:317: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects? #317: FILE: drivers/gpu/drm/i915/i915_reg.h:961: +#define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \ + HECI_FWSTS1, \ + HECI_FWSTS2, \ + HECI_FWSTS3, \ + HECI_FWSTS4, \ + HECI_FWSTS5, \ + HECI_FWSTS6)) total: 0 errors, 1 warnings, 2 checks, 250 lines checked 0d75b5b4975a drm/i915/gsc: define gsc fw -:66: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'major_' - possible side-effects? #66: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:242: +#define GSC_FW_BLOB(prefix_, major_, minor_) \ + UC_FW_BLOB_NEW(major_, minor_, 0, true, \ + MAKE_GSC_FW_PATH(prefix_, major_, minor_)) -:66: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'minor_' - possible side-effects? #66: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:242: +#define GSC_FW_BLOB(prefix_, major_, minor_) \ + UC_FW_BLOB_NEW(major_, minor_, 0, true, \ + MAKE_GSC_FW_PATH(prefix_, major_, minor_)) total: 0 errors, 0 warnings, 2 checks, 71 lines checked
[Intel-gfx] [PATCH v3] drm/i915/mtl/gsc: Add a gsc_info debugfs
Add a new debugfs to dump information about the GSC. This includes:
- the FW path and SW tracking status;
- the release, security and compatibility versions;
- the HECI1 status registers.
Note that those are the same registers that the mei driver dumps in
their own status sysfs on DG2 (where mei owns the GSC).
To make it simpler to loop through the status register, the code has
been update to use a PICK macro and the existing code using the regs had
been adapted to match.
v2: fix includes and copyright dates (Alan)
v3: actually fix the includes
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 29 +--
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 48 ++-
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h | 2 +
.../gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.c | 39 +++
.../gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.h | 14 ++
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 6 +--
drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 +
drivers/gpu/drm/i915/i915_reg.h | 26 +-
9 files changed, 144 insertions(+), 25 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1c9ed4c52760..b6c54fb0b4cc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -192,7 +192,8 @@ i915-y += \
gt/uc/intel_gsc_fw.o \
gt/uc/intel_gsc_proxy.o \
gt/uc/intel_gsc_uc.o \
- gt/uc/intel_gsc_uc_heci_cmd_submit.o\
+ gt/uc/intel_gsc_uc_debugfs.o \
+ gt/uc/intel_gsc_uc_heci_cmd_submit.o \
gt/uc/intel_guc.o \
gt/uc/intel_guc_ads.o \
gt/uc/intel_guc_capture.o \
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
index 7d48d59011c8..b069459e2596 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
@@ -12,36 +12,31 @@
#include "intel_gsc_binary_headers.h"
#include "intel_gsc_fw.h"
#include "intel_gsc_uc_heci_cmd_submit.h"
-
-#define GSC_FW_STATUS_REG _MMIO(0x116C40)
-#define GSC_FW_CURRENT_STATE REG_GENMASK(3, 0)
-#define GSC_FW_CURRENT_STATE_RESET 0
-#define GSC_FW_PROXY_STATE_NORMAL5
-#define GSC_FW_INIT_COMPLETE_BIT REG_BIT(9)
+#include "i915_reg.h"
static bool gsc_is_in_reset(struct intel_uncore *uncore)
{
- u32 fw_status = intel_uncore_read(uncore, GSC_FW_STATUS_REG);
+ u32 fw_status = intel_uncore_read(uncore,
HECI_FWSTS(MTL_GSC_HECI1_BASE, 1));
- return REG_FIELD_GET(GSC_FW_CURRENT_STATE, fw_status) ==
- GSC_FW_CURRENT_STATE_RESET;
+ return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE, fw_status) ==
+ HECI1_FWSTS1_CURRENT_STATE_RESET;
}
bool intel_gsc_uc_fw_proxy_init_done(struct intel_gsc_uc *gsc)
{
struct intel_uncore *uncore = gsc_uc_to_gt(gsc)->uncore;
- u32 fw_status = intel_uncore_read(uncore, GSC_FW_STATUS_REG);
+ u32 fw_status = intel_uncore_read(uncore,
HECI_FWSTS(MTL_GSC_HECI1_BASE, 1));
- return REG_FIELD_GET(GSC_FW_CURRENT_STATE, fw_status) ==
- GSC_FW_PROXY_STATE_NORMAL;
+ return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE, fw_status) ==
+ HECI1_FWSTS1_PROXY_STATE_NORMAL;
}
bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc)
{
struct intel_uncore *uncore = gsc_uc_to_gt(gsc)->uncore;
- u32 fw_status = intel_uncore_read(uncore, GSC_FW_STATUS_REG);
+ u32 fw_status = intel_uncore_read(uncore,
HECI_FWSTS(MTL_GSC_HECI1_BASE, 1));
- return fw_status & GSC_FW_INIT_COMPLETE_BIT;
+ return fw_status & HECI1_FWSTS1_INIT_COMPLETE;
}
static inline u32 cpd_entry_offset(const struct intel_gsc_cpd_entry *entry)
@@ -293,9 +288,9 @@ static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc)
static int gsc_fw_wait(struct intel_gt *gt)
{
return intel_wait_for_register(gt->uncore,
- GSC_FW_STATUS_REG,
- GSC_FW_INIT_COMPLETE_BIT,
- GSC_FW_INIT_COMPLETE_BIT,
+ HECI_FWSTS(MTL_GSC_HECI1_BASE, 1),
+ HECI1_FWSTS1_INIT_COMPLETE,
+ HECI1_FWSTS1_INIT_COMPLETE,
500);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
index 4fe639a80564..6826aa5d6985 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
@@ -7,10 +7,11 @@
#include "gt/intel_gt.h"
#include
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Avoid circular locking dependency when flush delayed work on gt reset
== Series Details ==
Series: drm/i915: Avoid circular locking dependency when flush delayed work on
gt reset
URL : https://patchwork.freedesktop.org/series/118898/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13234 -> Patchwork_118898v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_118898v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_118898v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118898v1/index.html
Participating hosts (38 -> 36)
--
Missing(2): fi-kbl-soraka fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118898v1:
### IGT changes ###
Possible regressions
* igt@i915_suspend@basic-s3-without-i915:
- bat-adlp-6: NOTRUN -> [ABORT][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118898v1/bat-adlp-6/igt@i915_susp...@basic-s3-without-i915.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_force_connector_basic@prune-stale-modes:
- {bat-adlp-11}: [SKIP][2] ([i915#4093]) -> [FAIL][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-adlp-11/igt@kms_force_connector_ba...@prune-stale-modes.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118898v1/bat-adlp-11/igt@kms_force_connector_ba...@prune-stale-modes.html
Known issues
Here are the changes found in Patchwork_118898v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@basic:
- bat-adln-1: NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118898v1/bat-adln-1/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-rplp-1: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118898v1/bat-rplp-1/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- bat-adlp-6: NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118898v1/bat-adlp-6/igt@gem_lmem_swapp...@random-engines.html
* igt@i915_pm_rps@basic-api:
- bat-adlp-6: NOTRUN -> [SKIP][7] ([i915#6621])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118898v1/bat-adlp-6/igt@i915_pm_...@basic-api.html
- bat-rplp-1: NOTRUN -> [SKIP][8] ([i915#6621])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118898v1/bat-rplp-1/igt@i915_pm_...@basic-api.html
- bat-adln-1: NOTRUN -> [SKIP][9] ([i915#6621])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118898v1/bat-adln-1/igt@i915_pm_...@basic-api.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][10] -> [DMESG-FAIL][11] ([i915#5334])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118898v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [PASS][12] -> [DMESG-WARN][13] ([i915#7699])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118898v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][14] -> [ABORT][15] ([i915#4983] / [i915#7911]
/ [i915#7920])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-rpls-1/igt@i915_selftest@l...@requests.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118898v1/bat-rpls-1/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][16] ([i915#6367])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118898v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][17] ([i915#6687])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118898v1/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rplp-1: NOTRUN -> [SKIP][18] ([i915#7828])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118898v1/bat-rplp-1/igt@kms_chamelium_...@common-hpd-after-suspend.html
- bat-adln-1:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Avoid circular locking dependency when flush delayed work on gt reset
== Series Details == Series: drm/i915: Avoid circular locking dependency when flush delayed work on gt reset URL : https://patchwork.freedesktop.org/series/118898/ State : warning == Summary == Error: dim checkpatch failed 0f88e7218ac1 drm/i915: Avoid circular locking dependency when flush delayed work on gt reset -:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #7: This attemps to avoid circular locing dependency between flush delayed work and intel_gt_reset. -:7: WARNING:TYPO_SPELLING: 'attemps' may be misspelled - perhaps 'attempts'? #7: This attemps to avoid circular locing dependency between flush delayed work and intel_gt_reset. ^^^ total: 0 errors, 2 warnings, 0 checks, 8 lines checked
[Intel-gfx] [PATCH] drm/i915: Avoid circular locking dependency when flush delayed work on gt reset
This attemps to avoid circular locing dependency between flush delayed work and
intel_gt_reset.
WARNING: possible circular locking dependency detected
6.4.0-rc1-drmtip_1340-g31e3463b0edb+ #1 Not tainted
--
kms_pipe_crc_ba/6415 is trying to acquire lock:
88813e6cc640
((work_completion)(&(>timestamp.work)->work)){+.+.}-{0:0}, at:
__flush_work+0x42/0x530
but task is already holding lock:
88813e6cce90 (>reset.mutex){+.+.}-{3:3}, at: intel_gt_reset+0x19e/0x470
[i915]
which lock already depends on the new lock.
the existing dependency chain (in reverse order) is:
-> #3 (>reset.mutex){+.+.}-{3:3}:
lock_acquire+0xd8/0x2d0
i915_gem_shrinker_taints_mutex+0x31/0x50 [i915]
intel_gt_init_reset+0x65/0x80 [i915]
intel_gt_common_init_early+0xe1/0x170 [i915]
intel_root_gt_init_early+0x48/0x60 [i915]
i915_driver_probe+0x671/0xcb0 [i915]
i915_pci_probe+0xdc/0x210 [i915]
pci_device_probe+0x95/0x120
really_probe+0x164/0x3c0
__driver_probe_device+0x73/0x160
driver_probe_device+0x19/0xa0
__driver_attach+0xb6/0x180
bus_for_each_dev+0x77/0xd0
bus_add_driver+0x114/0x210
driver_register+0x5b/0x110
__pfx_vgem_open+0x3/0x10 [vgem]
do_one_initcall+0x57/0x270
do_init_module+0x5f/0x220
load_module+0x1ca4/0x1f00
__do_sys_finit_module+0xb4/0x130
do_syscall_64+0x3c/0x90
entry_SYSCALL_64_after_hwframe+0x72/0xdc
-> #2 (fs_reclaim){+.+.}-{0:0}:
lock_acquire+0xd8/0x2d0
fs_reclaim_acquire+0xac/0xe0
kmem_cache_alloc+0x32/0x260
i915_vma_instance+0xb2/0xc60 [i915]
i915_gem_object_ggtt_pin_ww+0x175/0x370 [i915]
vm_fault_gtt+0x22d/0xf60 [i915]
__do_fault+0x2f/0x1d0
do_pte_missing+0x4a/0xd20
__handle_mm_fault+0x5b0/0x790
handle_mm_fault+0xa2/0x230
do_user_addr_fault+0x3ea/0xa10
exc_page_fault+0x68/0x1a0
asm_exc_page_fault+0x26/0x30
-> #1 (>reset.backoff_srcu){}-{0:0}:
lock_acquire+0xd8/0x2d0
_intel_gt_reset_lock+0x57/0x330 [i915]
guc_timestamp_ping+0x35/0x130 [i915]
process_one_work+0x250/0x510
worker_thread+0x4f/0x3a0
kthread+0xff/0x130
ret_from_fork+0x29/0x50
-> #0 ((work_completion)(&(>timestamp.work)->work)){+.+.}-{0:0}:
check_prev_add+0x90/0xc60
__lock_acquire+0x1998/0x2590
lock_acquire+0xd8/0x2d0
__flush_work+0x74/0x530
__cancel_work_timer+0x14f/0x1f0
intel_guc_submission_reset_prepare+0x81/0x4b0 [i915]
intel_uc_reset_prepare+0x9c/0x120 [i915]
reset_prepare+0x21/0x60 [i915]
intel_gt_reset+0x1dd/0x470 [i915]
intel_gt_reset_global+0xfb/0x170 [i915]
intel_gt_handle_error+0x368/0x420 [i915]
intel_gt_debugfs_reset_store+0x5c/0xc0 [i915]
i915_wedged_set+0x29/0x40 [i915]
simple_attr_write_xsigned.constprop.0+0xb4/0x110
full_proxy_write+0x52/0x80
vfs_write+0xc5/0x4f0
ksys_write+0x64/0xe0
do_syscall_64+0x3c/0x90
entry_SYSCALL_64_after_hwframe+0x72/0xdc
other info that might help us debug this:
Chain exists of:
(work_completion)(&(>timestamp.work)->work) --> fs_reclaim -->
>reset.mutex
Possible unsafe locking scenario:
CPU0CPU1
lock(>reset.mutex);
lock(fs_reclaim);
lock(>reset.mutex);
lock((work_completion)(&(>timestamp.work)->work));
*** DEADLOCK ***
3 locks held by kms_pipe_crc_ba/6415:
#0: 888101541430 (sb_writers#15){.+.+}-{0:0}, at: ksys_write+0x64/0xe0
#1: 888136c7eab8 (>mutex){+.+.}-{3:3}, at:
simple_attr_write_xsigned.constprop.0+0x47/0x110
#2: 88813e6cce90 (>reset.mutex){+.+.}-{3:3}, at:
intel_gt_reset+0x19e/0x470 [i915]
Signed-off-by: Zhanjun Dong
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0e3ef1c65d2..22390704542e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1359,7 +1359,7 @@ static void guc_enable_busyness_worker(struct intel_guc
*guc)
static void guc_cancel_busyness_worker(struct intel_guc *guc)
{
- cancel_delayed_work_sync(>timestamp.work);
+ cancel_delayed_work(>timestamp.work);
}
static void __reset_guc_busyness_stats(struct intel_guc *guc)
--
2.34.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Force a reset on internal GuC error
== Series Details ==
Series: drm/i915/guc: Force a reset on internal GuC error
URL : https://patchwork.freedesktop.org/series/118890/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13234 -> Patchwork_118890v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/index.html
Participating hosts (38 -> 36)
--
Missing(2): fi-kbl-soraka fi-snb-2520m
Known issues
Here are the changes found in Patchwork_118890v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][1] ([i915#6367])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][2] ([i915#6687])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1:
- bat-dg2-8: [PASS][3] -> [FAIL][4] ([i915#7932])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html
Possible fixes
* igt@i915_pm_rpm@basic-pci-d3-state:
- {bat-mtlp-8}: [ABORT][5] ([i915#7953]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-mtlp-8/igt@i915_pm_...@basic-pci-d3-state.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/bat-mtlp-8/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][7] ([i915#4983] / [i915#7461] / [i915#7913] /
[i915#7981] / [i915#8347]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-rpls-2/igt@i915_selftest@l...@reset.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/bat-rpls-2/igt@i915_selftest@l...@reset.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-WARN][9] ([i915#6367]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html
* {igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-d-dp-5}:
- {bat-adlp-11}: [ABORT][11] ([i915#4423]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-d-dp-5.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-d-dp-5.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7953]: https://gitlab.freedesktop.org/drm/intel/issues/7953
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
Build changes
-
* Linux: CI_DRM_13234 -> Patchwork_118890v1
CI-20190529: 20190529
CI_DRM_13234: cb7bb5b791053c0ff10e314d24e6752795283803 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7319: 2e1bcd49944452b5f9516eecee48e1fa3ae6a636 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_118890v1: cb7bb5b791053c0ff10e314d24e6752795283803 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4ea24f81628a drm/i915/guc: Force a reset on internal GuC error
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/index.html
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: GSC FW support for MTL (rev2)
== Series Details == Series: drm/i915: GSC FW support for MTL (rev2) URL : https://patchwork.freedesktop.org/series/117396/ State : failure == Summary == Error: make failed CALLscripts/checksyscalls.sh DESCEND objtool INSTALL libsubcmd_headers CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.o drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.c:28:6: error: no previous prototype for ‘intel_gsc_uc_debugfs_register’ [-Werror=missing-prototypes] 28 | void intel_gsc_uc_debugfs_register(struct intel_gsc_uc *gsc_uc, struct dentry *root) | ^ cc1: all warnings being treated as errors make[5]: *** [scripts/Makefile.build:252: drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.o] Error 1 make[4]: *** [scripts/Makefile.build:494: drivers/gpu/drm/i915] Error 2 make[3]: *** [scripts/Makefile.build:494: drivers/gpu/drm] Error 2 make[2]: *** [scripts/Makefile.build:494: drivers/gpu] Error 2 make[1]: *** [scripts/Makefile.build:494: drivers] Error 2 make: *** [Makefile:2026: .] Error 2 Build failed, no error log produced
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Force a reset on internal GuC error
== Series Details == Series: drm/i915/guc: Force a reset on internal GuC error URL : https://patchwork.freedesktop.org/series/118890/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] [PATCH v2 5/5] drm/i915/gsc: define gsc fw
Add FW definition and the matching override modparam.
The GSC FW has both a release version, based on platform and a rolling
counter, and a compatibility version, which is the one tracking
interface changes. Since what we care about is the interface, we use
the compatibility version in the binary names.
Same as with the GuC, a major version bump indicate a
backward-incompatible change, while a minor version bump indicates a
backward-compatible one, so we use only the former in the file name.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 32 ++--
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index d408856ae4c0..08e16017584b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -130,6 +130,17 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
fw_def(BROXTON, 0, huc_mmp(bxt, 2, 0, 0)) \
fw_def(SKYLAKE, 0, huc_mmp(skl, 2, 0, 0))
+/*
+ * The GSC FW has multiple version (see intel_gsc_uc.h for details); since what
+ * we care about is the interface, we use the compatibility version in the
+ * binary names.
+ * Same as with the GuC, a major version bump indicate a
+ * backward-incompatible change, while a minor version bump indicates a
+ * backward-compatible one, so we use only the former in the file name.
+ */
+#define INTEL_GSC_FIRMWARE_DEFS(fw_def, gsc_def) \
+ fw_def(METEORLAKE, 0, gsc_def(mtl, 1, 0))
+
/*
* Set of macros for producing a list of filenames from the above table.
*/
@@ -165,6 +176,9 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
#define MAKE_HUC_FW_PATH_MMP(prefix_, major_, minor_, patch_) \
__MAKE_UC_FW_PATH_MMP(prefix_, "huc", major_, minor_, patch_)
+#define MAKE_GSC_FW_PATH(prefix_, major_, minor_) \
+ __MAKE_UC_FW_PATH_MAJOR(prefix_, "gsc", major_)
+
/*
* All blobs need to be declared via MODULE_FIRMWARE().
* This first expansion of the table macros is solely to provide
@@ -175,6 +189,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
INTEL_GUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH_MAJOR,
MAKE_GUC_FW_PATH_MMP)
INTEL_HUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_HUC_FW_PATH_BLANK,
MAKE_HUC_FW_PATH_MMP, MAKE_HUC_FW_PATH_GSC)
+INTEL_GSC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GSC_FW_PATH)
/*
* The next expansion of the table macros (in __uc_fw_auto_select below)
provides
@@ -224,6 +239,10 @@ struct __packed uc_fw_blob {
#define HUC_FW_BLOB_GSC(prefix_) \
UC_FW_BLOB_NEW(0, 0, 0, true, MAKE_HUC_FW_PATH_GSC(prefix_))
+#define GSC_FW_BLOB(prefix_, major_, minor_) \
+ UC_FW_BLOB_NEW(major_, minor_, 0, true, \
+ MAKE_GSC_FW_PATH(prefix_, major_, minor_))
+
struct __packed uc_fw_platform_requirement {
enum intel_platform p;
u8 rev; /* first platform rev using this FW */
@@ -250,9 +269,14 @@ static const struct uc_fw_platform_requirement blobs_huc[]
= {
INTEL_HUC_FIRMWARE_DEFS(MAKE_FW_LIST, HUC_FW_BLOB, HUC_FW_BLOB_MMP,
HUC_FW_BLOB_GSC)
};
+static const struct uc_fw_platform_requirement blobs_gsc[] = {
+ INTEL_GSC_FIRMWARE_DEFS(MAKE_FW_LIST, GSC_FW_BLOB)
+};
+
static const struct fw_blobs_by_type blobs_all[INTEL_UC_FW_NUM_TYPES] = {
[INTEL_UC_FW_TYPE_GUC] = { blobs_guc, ARRAY_SIZE(blobs_guc) },
[INTEL_UC_FW_TYPE_HUC] = { blobs_huc, ARRAY_SIZE(blobs_huc) },
+ [INTEL_UC_FW_TYPE_GSC] = { blobs_gsc, ARRAY_SIZE(blobs_gsc) },
};
static void
@@ -265,14 +289,6 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct
intel_uc_fw *uc_fw)
int i;
bool found;
- /*
-* GSC FW support is still not fully in place, so we're not defining
-* the FW blob yet because we don't want the driver to attempt to load
-* it until we're ready for it.
-*/
- if (uc_fw->type == INTEL_UC_FW_TYPE_GSC)
- return;
-
/*
* The only difference between the ADL GuC FWs is the HWConfig support.
* ADL-N does not support HWConfig, so we should use the same binary as
--
2.40.0
[Intel-gfx] [PATCH v2 3/5] drm/i915/mtl/gsc: query the GSC FW for its compatibility version
The compatibility version is queried via an MKHI command. Right now, the
only existing interface is 1.0
This is basically the interface version for the GSC FW, so the plan is
to use it as the main tracked version, including for the binary naming
in the fetch code.
v2: use define for the object size (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Reviewed-by: Alan Previn #v1
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 95 ++-
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 50 ++
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 1 +
4 files changed, 127 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
index 953c155b5170..7d48d59011c8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
@@ -11,6 +11,7 @@
#include "gt/intel_ring.h"
#include "intel_gsc_binary_headers.h"
#include "intel_gsc_fw.h"
+#include "intel_gsc_uc_heci_cmd_submit.h"
#define GSC_FW_STATUS_REG _MMIO(0x116C40)
#define GSC_FW_CURRENT_STATE REG_GENMASK(3, 0)
@@ -298,6 +299,88 @@ static int gsc_fw_wait(struct intel_gt *gt)
500);
}
+struct intel_gsc_mkhi_header {
+ u8 group_id;
+#define MKHI_GROUP_ID_GFX_SRV 0x30
+
+ u8 command;
+#define MKHI_GFX_SRV_GET_HOST_COMPATIBILITY_VERSION (0x42)
+
+ u8 reserved;
+ u8 result;
+} __packed;
+
+struct mtl_gsc_ver_msg_in {
+ struct intel_gsc_mtl_header header;
+ struct intel_gsc_mkhi_header mkhi;
+} __packed;
+
+struct mtl_gsc_ver_msg_out {
+ struct intel_gsc_mtl_header header;
+ struct intel_gsc_mkhi_header mkhi;
+ u16 proj_major;
+ u16 compat_major;
+ u16 compat_minor;
+ u16 reserved[5];
+} __packed;
+
+#define GSC_VER_PKT_SZ SZ_4K
+
+static int gsc_fw_query_compatibility_version(struct intel_gsc_uc *gsc)
+{
+ struct intel_gt *gt = gsc_uc_to_gt(gsc);
+ struct mtl_gsc_ver_msg_in *msg_in;
+ struct mtl_gsc_ver_msg_out *msg_out;
+ struct i915_vma *vma;
+ u64 offset;
+ void *vaddr;
+ int err;
+
+ err = intel_guc_allocate_and_map_vma(>uc.guc, GSC_VER_PKT_SZ * 2,
+, );
+ if (err) {
+ gt_err(gt, "failed to allocate vma for GSC version query\n");
+ return err;
+ }
+
+ offset = i915_ggtt_offset(vma);
+ msg_in = vaddr;
+ msg_out = vaddr + GSC_VER_PKT_SZ;
+
+ intel_gsc_uc_heci_cmd_emit_mtl_header(_in->header,
+ HECI_MEADDRESS_MKHI,
+ sizeof(*msg_in), 0);
+ msg_in->mkhi.group_id = MKHI_GROUP_ID_GFX_SRV;
+ msg_in->mkhi.command = MKHI_GFX_SRV_GET_HOST_COMPATIBILITY_VERSION;
+
+ err = intel_gsc_uc_heci_cmd_submit_packet(>uc.gsc,
+ offset,
+ sizeof(*msg_in),
+ offset + GSC_VER_PKT_SZ,
+ GSC_VER_PKT_SZ);
+ if (err) {
+ gt_err(gt,
+ "failed to submit GSC request for compatibility version:
%d\n",
+ err);
+ goto out_vma;
+ }
+
+ if (msg_out->header.message_size != sizeof(*msg_out)) {
+ gt_err(gt, "invalid GSC reply length %u [expected %zu], s=0x%x,
f=0x%x, r=0x%x\n",
+ msg_out->header.message_size, sizeof(*msg_out),
+ msg_out->header.status, msg_out->header.flags,
msg_out->mkhi.result);
+ err = -EPROTO;
+ goto out_vma;
+ }
+
+ gsc->fw.file_selected.ver.major = msg_out->compat_major;
+ gsc->fw.file_selected.ver.minor = msg_out->compat_minor;
+
+out_vma:
+ i915_vma_unpin_and_release(, I915_VMA_RELEASE_MAP);
+ return err;
+}
+
int intel_gsc_uc_fw_upload(struct intel_gsc_uc *gsc)
{
struct intel_gt *gt = gsc_uc_to_gt(gsc);
@@ -355,11 +438,21 @@ int intel_gsc_uc_fw_upload(struct intel_gsc_uc *gsc)
if (err)
goto fail;
+ err = gsc_fw_query_compatibility_version(gsc);
+ if (err)
+ goto fail;
+
+ /* we only support compatibility version 1.0 at the moment */
+ err = intel_uc_check_file_version(gsc_fw, NULL);
+ if (err)
+ goto fail;
+
/* FW is not fully operational until we enable SW proxy */
intel_uc_fw_change_status(gsc_fw, INTEL_UC_FIRMWARE_TRANSFERRED);
- gt_info(gt, "Loaded GSC firmware %s (r%u.%u.%u.%u, svn%u)\n",
+ gt_info(gt, "Loaded GSC firmware %s (cv%u.%u, r%u.%u.%u.%u, svn %u)\n",
gsc_fw->file_selected.path,
+
[Intel-gfx] [PATCH v2 4/5] drm/i915/mtl/gsc: Add a gsc_info debugfs
Add a new debugfs to dump information about the GSC. This includes:
- the FW path and SW tracking status;
- the release, security and compatibility versions;
- the HECI1 status registers.
Note that those are the same registers that the mei driver dumps in
their own status sysfs on DG2 (where mei owns the GSC).
To make it simpler to loop through the status register, the code has
been update to use a PICK macro and the existing code using the regs had
been adapted to match.
v2: fix includes and copyright dates (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 29 +--
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 48 ++-
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h | 2 +
.../gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.c | 38 +++
.../gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.h | 14 ++
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 6 +--
drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 +
drivers/gpu/drm/i915/i915_reg.h | 26 +-
9 files changed, 143 insertions(+), 25 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1c9ed4c52760..b6c54fb0b4cc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -192,7 +192,8 @@ i915-y += \
gt/uc/intel_gsc_fw.o \
gt/uc/intel_gsc_proxy.o \
gt/uc/intel_gsc_uc.o \
- gt/uc/intel_gsc_uc_heci_cmd_submit.o\
+ gt/uc/intel_gsc_uc_debugfs.o \
+ gt/uc/intel_gsc_uc_heci_cmd_submit.o \
gt/uc/intel_guc.o \
gt/uc/intel_guc_ads.o \
gt/uc/intel_guc_capture.o \
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
index 7d48d59011c8..b069459e2596 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
@@ -12,36 +12,31 @@
#include "intel_gsc_binary_headers.h"
#include "intel_gsc_fw.h"
#include "intel_gsc_uc_heci_cmd_submit.h"
-
-#define GSC_FW_STATUS_REG _MMIO(0x116C40)
-#define GSC_FW_CURRENT_STATE REG_GENMASK(3, 0)
-#define GSC_FW_CURRENT_STATE_RESET 0
-#define GSC_FW_PROXY_STATE_NORMAL5
-#define GSC_FW_INIT_COMPLETE_BIT REG_BIT(9)
+#include "i915_reg.h"
static bool gsc_is_in_reset(struct intel_uncore *uncore)
{
- u32 fw_status = intel_uncore_read(uncore, GSC_FW_STATUS_REG);
+ u32 fw_status = intel_uncore_read(uncore,
HECI_FWSTS(MTL_GSC_HECI1_BASE, 1));
- return REG_FIELD_GET(GSC_FW_CURRENT_STATE, fw_status) ==
- GSC_FW_CURRENT_STATE_RESET;
+ return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE, fw_status) ==
+ HECI1_FWSTS1_CURRENT_STATE_RESET;
}
bool intel_gsc_uc_fw_proxy_init_done(struct intel_gsc_uc *gsc)
{
struct intel_uncore *uncore = gsc_uc_to_gt(gsc)->uncore;
- u32 fw_status = intel_uncore_read(uncore, GSC_FW_STATUS_REG);
+ u32 fw_status = intel_uncore_read(uncore,
HECI_FWSTS(MTL_GSC_HECI1_BASE, 1));
- return REG_FIELD_GET(GSC_FW_CURRENT_STATE, fw_status) ==
- GSC_FW_PROXY_STATE_NORMAL;
+ return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE, fw_status) ==
+ HECI1_FWSTS1_PROXY_STATE_NORMAL;
}
bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc)
{
struct intel_uncore *uncore = gsc_uc_to_gt(gsc)->uncore;
- u32 fw_status = intel_uncore_read(uncore, GSC_FW_STATUS_REG);
+ u32 fw_status = intel_uncore_read(uncore,
HECI_FWSTS(MTL_GSC_HECI1_BASE, 1));
- return fw_status & GSC_FW_INIT_COMPLETE_BIT;
+ return fw_status & HECI1_FWSTS1_INIT_COMPLETE;
}
static inline u32 cpd_entry_offset(const struct intel_gsc_cpd_entry *entry)
@@ -293,9 +288,9 @@ static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc)
static int gsc_fw_wait(struct intel_gt *gt)
{
return intel_wait_for_register(gt->uncore,
- GSC_FW_STATUS_REG,
- GSC_FW_INIT_COMPLETE_BIT,
- GSC_FW_INIT_COMPLETE_BIT,
+ HECI_FWSTS(MTL_GSC_HECI1_BASE, 1),
+ HECI1_FWSTS1_INIT_COMPLETE,
+ HECI1_FWSTS1_INIT_COMPLETE,
500);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
index 4fe639a80564..6826aa5d6985 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
@@ -7,10 +7,11 @@
#include "gt/intel_gt.h"
#include "gt/intel_gt_print.h"
-#include
[Intel-gfx] [PATCH v2 2/5] drm/i915/mtl/gsc: extract release and security versions from the gsc binary
The release and security versions of the GSC binary are not used at
runtime to decide interface compatibility (there is a separate version
for that), but they're still useful for debug, so it is still worth
extracting them and printing them out in dmesg.
To get to these version, we need to navigate through various headers in
the binary. See in-code comment for details.
v2: fix and improve size checks when crawling the binary header, add
comment about the different version, wrap the partition base/offset
pairs in the GSC header in a struct (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
.../drm/i915/gt/uc/intel_gsc_binary_headers.h | 76 -
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 158 +-
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h | 2 +
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h | 18 ++
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 13 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 30 +++-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 3 +
7 files changed, 273 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h
index 714f0c256118..ad80afcafd23 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h
@@ -8,6 +8,75 @@
#include
+struct intel_gsc_version {
+ u16 major;
+ u16 minor;
+ u16 hotfix;
+ u16 build;
+} __packed;
+
+struct intel_gsc_partition {
+ u32 offset;
+ u32 size;
+} __packed;
+
+struct intel_gsc_layout_pointers {
+ u8 rom_bypass_vector[16];
+
+ /* size of pointers layout not including ROM bypass vector */
+ u16 size;
+
+ /*
+* bit0: Backup copy of layout pointers exist
+* bits1-15: reserved
+*/
+ u8 flags;
+
+ u8 reserved;
+
+ u32 crc32;
+
+ struct intel_gsc_partition datap;
+ struct intel_gsc_partition boot1;
+ struct intel_gsc_partition boot2;
+ struct intel_gsc_partition boot3;
+ struct intel_gsc_partition boot4;
+ struct intel_gsc_partition boot5;
+ struct intel_gsc_partition temp_pages;
+} __packed;
+
+/* Boot partition structures */
+struct intel_gsc_bpdt_header {
+ u32 signature;
+#define INTEL_GSC_BPDT_HEADER_SIGNATURE 0x55AA
+
+ u16 descriptor_count; /* num of entries after the header */
+
+ u8 version;
+ u8 configuration;
+
+ u32 crc32;
+
+ u32 build_version;
+ struct intel_gsc_version tool_version;
+} __packed;
+
+
+struct intel_gsc_bpdt_entry {
+ /*
+* Bits 0-15: BPDT entry type
+* Bits 16-17: reserved
+* Bit 18: code sub-partition
+* Bits 19-31: reserved
+*/
+ u32 type;
+#define INTEL_GSC_BPDT_ENTRY_TYPE_MASK GENMASK(15,0)
+#define INTEL_GSC_BPDT_ENTRY_TYPE_GSC_RBE 0x1
+
+ u32 sub_partition_offset; /* from the base of the BPDT header */
+ u32 sub_partition_size;
+} __packed;
+
/* Code partition directory (CPD) structures */
struct intel_gsc_cpd_header_v2 {
u32 header_marker;
@@ -44,13 +113,6 @@ struct intel_gsc_cpd_entry {
u8 reserved[4];
} __packed;
-struct intel_gsc_version {
- u16 major;
- u16 minor;
- u16 hotfix;
- u16 build;
-} __packed;
-
struct intel_gsc_manifest_header {
u32 header_type; /* 0x4 for manifest type */
u32 header_length; /* in dwords */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
index 445995e55d87..953c155b5170 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
@@ -9,6 +9,7 @@
#include "gt/intel_gt.h"
#include "gt/intel_gt_print.h"
#include "gt/intel_ring.h"
+#include "intel_gsc_binary_headers.h"
#include "intel_gsc_fw.h"
#define GSC_FW_STATUS_REG _MMIO(0x116C40)
@@ -42,6 +43,157 @@ bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc)
return fw_status & GSC_FW_INIT_COMPLETE_BIT;
}
+static inline u32 cpd_entry_offset(const struct intel_gsc_cpd_entry *entry)
+{
+ return entry->offset & INTEL_GSC_CPD_ENTRY_OFFSET_MASK;
+}
+
+int intel_gsc_fw_get_binary_info(struct intel_uc_fw *gsc_fw, const void *data,
size_t size)
+{
+ struct intel_gsc_uc *gsc = container_of(gsc_fw, struct intel_gsc_uc,
fw);
+ struct intel_gt *gt = gsc_uc_to_gt(gsc);
+ const struct intel_gsc_layout_pointers *layout = data;
+ const struct intel_gsc_bpdt_header *bpdt_header = NULL;
+ const struct intel_gsc_bpdt_entry *bpdt_entry = NULL;
+ const struct intel_gsc_cpd_header_v2 *cpd_header = NULL;
+ const struct intel_gsc_cpd_entry *cpd_entry = NULL;
+ const struct intel_gsc_manifest_header *manifest;
+ size_t min_size = sizeof(*layout);
+ int i;
+
+ if (size < min_size) {
+ gt_err(gt, "GSC FW too small!
[Intel-gfx] [PATCH v2 0/5] drm/i915: GSC FW support for MTL
Last chunk of the required support for the GSC FW. This includes some fixes to the GSC memory allocation, FW idefinition and version management, plus a new debugfs for debug information. Adding the FW definition will enable all the features that are dependent on the GSC being loaded (Media C6, HuC loading, SW proxy, PXP, HDCP). NOTE: the FW team has asked to not send the current FW blob to linux-firmware yet, as they're planning some updates. Therefore, the FW definition patch will have to be merged to the topic/core-for-CI branch for now and moved to gt-next once the FW is ready. v2: fix header parsing, address other minor review comments. Cc: Alan Previn Cc: John Harrison Cc: Suraj Kandpal Daniele Ceraolo Spurio (5): drm/i915/gsc: fixes and updates for GSC memory allocation drm/i915/mtl/gsc: extract release and security versions from the gsc binary drm/i915/mtl/gsc: query the GSC FW for its compatibility version drm/i915/mtl/gsc: Add a gsc_info debugfs drm/i915/gsc: define gsc fw drivers/gpu/drm/i915/Makefile | 3 +- .../drm/i915/gt/uc/intel_gsc_binary_headers.h | 76 - drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 309 +++--- drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h | 2 + drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 125 ++- drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h | 21 ++ .../gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.c | 38 +++ .../gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.h | 14 + .../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 1 + drivers/gpu/drm/i915/gt/uc/intel_huc.c| 6 +- drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 13 +- drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 + drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 112 +-- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 4 + drivers/gpu/drm/i915/i915_reg.h | 26 +- 15 files changed, 641 insertions(+), 111 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.h -- 2.40.0
[Intel-gfx] [PATCH v2 1/5] drm/i915/gsc: fixes and updates for GSC memory allocation
A few fixes/updates are required around the GSC memory allocation and it
is easier to do them all at the same time. The changes are as follows:
1 - Switch the memory allocation to stolen memory. We need to avoid
accesses from GSC FW to normal memory after the suspend function has
completed and to do so we can either switch to using stolen or make sure
the GSC is gone to sleep before the end of the suspend function. Given
that the GSC waits for a bit before going idle even if there are no
pending operations, it is easier and quicker to just use stolen memory.
2 - Reduce the GSC allocation size to 4MBs, which is the POR requirement.
The 8MBs were needed only for early FW and I had misunderstood that as
being the expected POR size when I sent the original patch.
3 - Perma-map the GSC allocation. This isn't required immediately, but it
will be needed later to be able to quickly extract the GSC logs, which are
inside the allocation. Since the mapping code needs to be rewritten due to
switching to stolen, it makes sense to do the switch immediately to avoid
having to change it again later.
Note that the explicit setting of CACHE_NONE for Wa_22016122933 has been
dropped because that's the default setting for stolen memory on !LLC
platforms.
v2: only memset the memory we're not overwriting (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Cc: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 29 ++---
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 77 ---
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h | 1 +
3 files changed, 75 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
index f46eb17a7a98..445995e55d87 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
@@ -3,6 +3,7 @@
* Copyright © 2022 Intel Corporation
*/
+#include "gem/i915_gem_lmem.h"
#include "gt/intel_engine_pm.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt.h"
@@ -109,38 +110,21 @@ static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc)
{
struct intel_gt *gt = gsc_uc_to_gt(gsc);
struct drm_i915_private *i915 = gt->i915;
- struct drm_i915_gem_object *obj;
- void *src, *dst;
+ void *src;
if (!gsc->local)
return -ENODEV;
- obj = gsc->local->obj;
-
- if (obj->base.size < gsc->fw.size)
+ if (gsc->local->size < gsc->fw.size)
return -ENOSPC;
- /*
-* Wa_22016122933: For MTL the shared memory needs to be mapped
-* as WC on CPU side and UC (PAT index 2) on GPU side
-*/
- if (IS_METEORLAKE(i915))
- i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
-
- dst = i915_gem_object_pin_map_unlocked(obj,
- i915_coherent_map_type(i915,
obj, true));
- if (IS_ERR(dst))
- return PTR_ERR(dst);
-
src = i915_gem_object_pin_map_unlocked(gsc->fw.obj,
i915_coherent_map_type(i915,
gsc->fw.obj, true));
- if (IS_ERR(src)) {
- i915_gem_object_unpin_map(obj);
+ if (IS_ERR(src))
return PTR_ERR(src);
- }
- memset(dst, 0, obj->base.size);
- memcpy(dst, src, gsc->fw.size);
+ memcpy_toio(gsc->local_vaddr, src, gsc->fw.size);
+ memset_io(gsc->local_vaddr + gsc->fw.size, 0, gsc->local->size -
gsc->fw.size);
/*
* Wa_22016122933: Making sure the data in dst is
@@ -149,7 +133,6 @@ static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc)
intel_guc_write_barrier(>uc.guc);
i915_gem_object_unpin_map(gsc->fw.obj);
- i915_gem_object_unpin_map(obj);
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
index c659cc01f32f..4fe639a80564 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
@@ -133,26 +133,85 @@ void intel_gsc_uc_init_early(struct intel_gsc_uc *gsc)
}
}
+static int gsc_allocate_and_map_vma(struct intel_gsc_uc *gsc, u32 size)
+{
+ struct intel_gt *gt = gsc_uc_to_gt(gsc);
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ void __iomem *vaddr;
+ int ret = 0;
+
+ /*
+* The GSC FW doesn't immediately suspend after becoming idle, so there
+* is a chance that it could still be awake after we successfully
+* return from the pci suspend function, even if there are no pending
+* operations.
+* The FW might therefore try to access memory for its suspend operation
+* after the kernel has completed the HW suspend flow; this can cause
+* issues if the FW is mapped in normal RAM memory, as some of the
+* involved HW units might've already lost
Re: [Intel-gfx] [PATCH v2 1/2] vgaarb: various coding style and comments fix
Hi,
On 2023/6/6 06:16, Andi Shyti wrote:
Hi Sui,
On Mon, Jun 05, 2023 at 04:58:30AM +0800, Sui Jingfeng wrote:
From: Sui Jingfeng
To keep consistent with vga_iostate_to_str() function, the third argument
of vga_str_to_iostate() function should be 'unsigned int *'.
I think the real reason is not to keep consistent with
vga_iostate_to_str() but because vga_str_to_iostate() is actually
only taking "unsigned int *" parameters.
Yes, right.
my expression is not completely correct, I will update it at next version.
I think, we have the same opinion.
Originally, I also want to express the opinion.
Because, it make no sense to interpret the return value
(VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM) as int type.
IO state should be should be donate by a unsigned type.
vga_iostate_to_str() also receive unsigned type.
static const char *vga_iostate_to_str(unsigned int iostate)
Signed-off-by: Sui Jingfeng
---
drivers/pci/vgaarb.c | 29 +++--
include/linux/vgaarb.h | 8 +++-
2 files changed, 18 insertions(+), 19 deletions(-)
diff --git a/drivers/pci/vgaarb.c b/drivers/pci/vgaarb.c
index 5a696078b382..e40e6e5e5f03 100644
--- a/drivers/pci/vgaarb.c
+++ b/drivers/pci/vgaarb.c
@@ -61,7 +61,6 @@ static bool vga_arbiter_used;
static DEFINE_SPINLOCK(vga_lock);
static DECLARE_WAIT_QUEUE_HEAD(vga_wait_queue);
-
drop this change
OK,
This is a double blank line.
Originally, I intend to accumulate all tiny fix, commit together.
As they are trivial.
Now, Should I split this patch,
then this patch set will contain two trivial patch ?
static const char *vga_iostate_to_str(unsigned int iostate)
{
/* Ignore VGA_RSRC_IO and VGA_RSRC_MEM */
@@ -77,10 +76,12 @@ static const char *vga_iostate_to_str(unsigned int iostate)
return "none";
}
-static int vga_str_to_iostate(char *buf, int str_size, int *io_state)
+static int vga_str_to_iostate(char *buf, int str_size, unsigned int *io_state)
this is OK, it's actually what you are describing in the commit
log, but...
{
- /* we could in theory hand out locks on IO and mem
-* separately to userspace but it can cause deadlocks */
+ /*
+* we could in theory hand out locks on IO and mem
+* separately to userspace but it can cause deadlocks
+*/
... all the rest needs to go on different patches as it doesn't
have anything to do with what you describe.
OK,
I will wait a few days for more reviews,
I process them together, also avoid version grow too fast.
Thanks.
Andi
--
Jingfeng
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix a VMA UAF for multi-gt platform
== Series Details ==
Series: drm/i915: Fix a VMA UAF for multi-gt platform
URL : https://patchwork.freedesktop.org/series/118887/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13233 -> Patchwork_118887v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/index.html
Participating hosts (38 -> 37)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_118887v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_backlight@basic-brightness@edp-1:
- bat-rplp-1: NOTRUN -> [ABORT][1] ([i915#7077])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/bat-rplp-1/igt@i915_pm_backlight@basic-brightn...@edp-1.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [PASS][2] -> [DMESG-FAIL][3] ([i915#5334] /
[i915#7872])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13233/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: NOTRUN -> [ABORT][4] ([i915#4983] / [i915#7461] /
[i915#7913] / [i915#8347])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/bat-rpls-2/igt@i915_selftest@l...@reset.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][5] ([i915#6687] / [i915#7978])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html
Possible fixes
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [DMESG-WARN][6] ([i915#7699]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13233/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html
* igt@i915_selftest@live@requests:
- bat-rpls-2: [ABORT][8] ([i915#7913] / [i915#7982]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13233/bat-rpls-2/igt@i915_selftest@l...@requests.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/bat-rpls-2/igt@i915_selftest@l...@requests.html
- {bat-mtlp-8}: [DMESG-FAIL][10] ([i915#8497]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13233/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html
- bat-rpls-1: [ABORT][12] ([i915#7911] / [i915#7920] / [i915#7982])
-> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13233/bat-rpls-1/igt@i915_selftest@l...@requests.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/bat-rpls-1/igt@i915_selftest@l...@requests.html
Warnings
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [ABORT][14] ([i915#4579] / [i915#8260]) -> [SKIP][15]
([i915#3555] / [i915#4579])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13233/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8260]: https://gitlab.freedesktop.org/drm/intel/issues/8260
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497
Build changes
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] vgaarb: various coding style and comments fix
== Series Details == Series: series starting with [v2,1/2] vgaarb: various coding style and comments fix URL : https://patchwork.freedesktop.org/series/118846/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13226_full -> Patchwork_118846v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_118846v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_118846v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (7 -> 7) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_118846v1_full: ### IGT changes ### Possible regressions * igt@kms_cursor_legacy@single-move@pipe-a: - shard-snb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13226/shard-snb1/igt@kms_cursor_legacy@single-m...@pipe-a.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118846v1/shard-snb7/igt@kms_cursor_legacy@single-m...@pipe-a.html * igt@kms_flip@2x-flip-vs-fences-interruptible@ab-vga1-hdmi-a1: - shard-snb: NOTRUN -> [DMESG-FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118846v1/shard-snb1/igt@kms_flip@2x-flip-vs-fences-interrupti...@ab-vga1-hdmi-a1.html * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1: - shard-apl: [PASS][4] -> [INCOMPLETE][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13226/shard-apl2/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-dp-1.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118846v1/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-dp-1.html Known issues Here are the changes found in Patchwork_118846v1_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_read@short-buffer-block: - shard-snb: [PASS][6] -> [SKIP][7] ([fdo#109271]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13226/shard-snb1/igt@drm_r...@short-buffer-block.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118846v1/shard-snb7/igt@drm_r...@short-buffer-block.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13226/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118846v1/shard-apl3/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_lmem_swapping@verify-random: - shard-apl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118846v1/shard-apl4/igt@gem_lmem_swapp...@verify-random.html * igt@gem_pwrite@basic-exhaustion: - shard-apl: NOTRUN -> [WARN][11] ([i915#2658]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118846v1/shard-apl1/igt@gem_pwr...@basic-exhaustion.html * igt@i915_pipe_stress@stress-xrgb-ytiled: - shard-apl: NOTRUN -> [FAIL][12] ([i915#7036]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118846v1/shard-apl4/igt@i915_pipe_str...@stress-xrgb-ytiled.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-vga: - shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4579]) +11 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118846v1/shard-snb6/igt@i915_pm_lpsp@kms-l...@kms-lpsp-vga.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-1: - shard-glk: [PASS][14] -> [FAIL][15] ([i915#2521]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13226/shard-glk2/igt@kms_async_flips@alternate-sync-async-f...@pipe-b-hdmi-a-1.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118846v1/shard-glk7/igt@kms_async_flips@alternate-sync-async-f...@pipe-b-hdmi-a-1.html * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3886]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118846v1/shard-apl4/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271]) +57 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118846v1/shard-apl4/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs.html * igt@kms_cursor_crc@cursor-sliding-32x32: - shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4579]) +7 similar issues [18]:
Re: [Intel-gfx] [PATCH 2/6] drm/i915/uc/gsc: fixes and updates for GSC memory allocation
On Tue, 2023-05-23 at 08:21 -0700, Ceraolo Spurio, Daniele wrote:
>
> >
> > > +static int gsc_allocate_and_map_vma(struct intel_gsc_uc *gsc, u32 size)
> > alan:snip
> > > + obj = i915_gem_object_create_stolen(gt->i915, s0ize);
> > > + if (IS_ERR(obj))
> > > + return PTR_ERR(obj);
> > > +
> > > + vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
> > alan: should we be passing in the PIN_MAPPABLE flag into the last param?
>
> No, PIN_MAPPABLE is only for legacy platform that used the aperture BAR
> for stolen mem access via GGTT. MTL doesn't have it and stolen is
> directly accessible via the LMEM BAR (which is actually the same BAR 2,
> but now behaves differently).
alan: thanks - sounds good - i forgot about those differentiations
>
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h
> > > @@ -18,6 +18,7 @@ struct intel_gsc_uc {
> > >
> > > /* GSC-specific additions */
> > > struct i915_vma *local; /* private memory for GSC usage */
> > > + void __iomem *local_vaddr; /* pointer to access the private memory */
> > alan:nit: relooking at the these variable names that originate from
> > last year's patch you worked on introducing gsc_uc, i am wondering now
> > if we should rename "local" to "privmem" and local_vaddr becomes
> > privmem_vaddr.
> > (no significant reason other than improving readibility of the code)
>
> IIRC I used local because one of the GSC docs referred to it that way. I
> don't mind the renaming, but I don't think it should be done as part of
> this patch.
alan: sure - sounds good.
Re: [Intel-gfx] [PATCH 6/6] drm/i915/uc/gsc: Add a gsc_info debugfs
On 6/5/2023 4:46 PM, Teres Alexis, Alan Previn wrote:
On Wed, 2023-05-31 at 17:25 -0700, Ceraolo Spurio, Daniele wrote:
On 5/26/2023 3:57 PM, Teres Alexis, Alan Previn wrote:
On Fri, 2023-05-05 at 09:04 -0700, Ceraolo Spurio, Daniele wrote:
Add a new debugfs to dump information about the GSC. This includes:
alan:snip
Actually everything looks good except for a couple of questions + asks - hope
we can close on this patch in next rev.
- the FW path and SW tracking status;
- the release, security and compatibility versions;
- the HECI1 status registers.
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
index 0b6dcd982b14..3014e982aab2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
@@ -12,36 +12,31 @@
#include "intel_gsc_fw.h"
#include "intel_gsc_meu_headers.h"
#include "intel_gsc_uc_heci_cmd_submit.h"
-
-#define GSC_FW_STATUS_REG _MMIO(0x116C40)
-#define GSC_FW_CURRENT_STATE REG_GENMASK(3, 0)
-#define GSC_FW_CURRENT_STATE_RESET 0
-#define GSC_FW_PROXY_STATE_NORMAL5
-#define GSC_FW_INIT_COMPLETE_BIT REG_BIT(9)
+#include "i915_reg.h"
alan:snip
alan: btw, just to be consistent with other top-level "intel_foo_is..." checking functions,
why don't we take the runtime wakeref inside the following functions and make
it easier for any callers?
(just like what we do for "intel_huc_is_authenticated"):
static bool gsc_is_in_reset(struct intel_uncore *uncore)
bool intel_gsc_uc_fw_proxy_init_done(struct intel_gsc_uc *gsc)
bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc)
The idea was that we shouldn't check the FW status if we're not planning
to do something with it, in which case we should already have a wakeref.
HuC is a special case because userspace can query that when the HW is
idle. This said, I have nothing against adding an extra wakeref , but I
don't think it should be in this patch.
alan: i believe intel_pxp_gsccs_is_ready_for_sessions is being used in a
similar way where one of the uses it to check huc-status and gsc-proxy
status without actually doing any operation. If u still wanna keep it
differently then I'll have to update the PXP code. Or perhaps you could
help me fix that on the PXP side?
Sure, but let's take this to a separate patch. This patch is not adding
that code nor any calls to it (just updating the defines), so it isn't
the right place to add that fix.
Daniele
alna:snip
+void intel_gsc_uc_load_status(struct intel_gsc_uc *gsc, struct drm_printer *p)
+{
+ struct intel_gt *gt = gsc_uc_to_gt(gsc);
+ struct intel_uncore *uncore = gt->uncore;
+ intel_wakeref_t wakeref;
+
+ if (!intel_gsc_uc_is_supported(gsc)) {
alan: this was already checked in caller so we'll never get here. i think we
should remove the check in the caller, let below msg appear.
I did the same as what we do for GuC and HuC. I'd prefer to be
consistent in behavior with those.
alan: okay - sounds good
+ drm_printf(p, "GSC not supported\n");
+ return;
+ }
alan:snip
+ drm_printf(p, "HECI1 FWSTST%u = 0x%08x\n", i, status);
alan:nit: do you we could add those additional shim regs? (seemed useful in
recent offline debugs).
Agreed that it would be useful; I'll try to get a complete list from
arch and/or the GSC FW team. Are you ok if we go ahead with this in the
meantime?
alan: yes sure.
Re: [Intel-gfx] [PATCH 3/6] drm/i915/uc/gsc: extract release and security versions from the gsc binary
On Fri, 2023-05-26 at 18:27 -0700, Ceraolo Spurio, Daniele wrote:
>
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
> > > b/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
> > > index d55a66202576..8bce2b8aed84 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
alan:snip
> > alan: structure layout seems unnecessarily repetitive... why not ->
> > struct partition_info {
> > u32 offset;
> > u32 size;
> > };
> > struct intel_gsc_layout_pointers {
> > u8 rom_bypass_vector[16];
> > ...
> > struct partition_info datap;
> > struct partition_info bootregion[5];
> > struct partition_info trace;
> > }__packed;
> >
>
> I've just realized that I didn't reply to this comment. The specs have
> the structure defined that way, so I tried to keep a 1:1 match like we
> usually do. I think switching to a partition_info structure is ok, but
> I'll avoid the array because the GSC partition are 1-based, which could
> cause confusion (i.e. partition boot1 would be bootregion[0]).
alan: sure - that's fine - let's stick to align with the spec definitions
Re: [Intel-gfx] [PATCH 6/6] drm/i915/uc/gsc: Add a gsc_info debugfs
On Wed, 2023-05-31 at 17:25 -0700, Ceraolo Spurio, Daniele wrote:
>
> On 5/26/2023 3:57 PM, Teres Alexis, Alan Previn wrote:
> > On Fri, 2023-05-05 at 09:04 -0700, Ceraolo Spurio, Daniele wrote:
> > > Add a new debugfs to dump information about the GSC. This includes:
> > alan:snip
> > Actually everything looks good except for a couple of questions + asks -
> > hope we can close on this patch in next rev.
> >
> > > - the FW path and SW tracking status;
> > > - the release, security and compatibility versions;
> > > - the HECI1 status registers.
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
> > > b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
> > > index 0b6dcd982b14..3014e982aab2 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
> > > @@ -12,36 +12,31 @@
> > > #include "intel_gsc_fw.h"
> > > #include "intel_gsc_meu_headers.h"
> > > #include "intel_gsc_uc_heci_cmd_submit.h"
> > > -
> > > -#define GSC_FW_STATUS_REG_MMIO(0x116C40)
> > > -#define GSC_FW_CURRENT_STATE REG_GENMASK(3, 0)
> > > -#define GSC_FW_CURRENT_STATE_RESET 0
> > > -#define GSC_FW_PROXY_STATE_NORMAL 5
> > > -#define GSC_FW_INIT_COMPLETE_BIT REG_BIT(9)
> > > +#include "i915_reg.h"
> > >
> > alan:snip
> >
> > alan: btw, just to be consistent with other top-level "intel_foo_is..."
> > checking functions,
> > why don't we take the runtime wakeref inside the following functions and
> > make it easier for any callers?
> > (just like what we do for "intel_huc_is_authenticated"):
> > static bool gsc_is_in_reset(struct intel_uncore *uncore)
> > bool intel_gsc_uc_fw_proxy_init_done(struct intel_gsc_uc *gsc)
> > bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc)
>
> The idea was that we shouldn't check the FW status if we're not planning
> to do something with it, in which case we should already have a wakeref.
> HuC is a special case because userspace can query that when the HW is
> idle. This said, I have nothing against adding an extra wakeref , but I
> don't think it should be in this patch.
alan: i believe intel_pxp_gsccs_is_ready_for_sessions is being used in a
similar way where one of the uses it to check huc-status and gsc-proxy
status without actually doing any operation. If u still wanna keep it
differently then I'll have to update the PXP code. Or perhaps you could
help me fix that on the PXP side?
alna:snip
> >
> > > +void intel_gsc_uc_load_status(struct intel_gsc_uc *gsc, struct
> > > drm_printer *p)
> > > +{
> > > + struct intel_gt *gt = gsc_uc_to_gt(gsc);
> > > + struct intel_uncore *uncore = gt->uncore;
> > > + intel_wakeref_t wakeref;
> > > +
> > > + if (!intel_gsc_uc_is_supported(gsc)) {
> > alan: this was already checked in caller so we'll never get here. i think
> > we should remove the check in the caller, let below msg appear.
>
> I did the same as what we do for GuC and HuC. I'd prefer to be
> consistent in behavior with those.
alan: okay - sounds good
>
> > > + drm_printf(p, "GSC not supported\n");
> > > + return;
> > > + }
> > alan:snip
> > > + drm_printf(p, "HECI1 FWSTST%u = 0x%08x\n", i, status);
> > alan:nit: do you we could add those additional shim regs? (seemed useful in
> > recent offline debugs).
>
> Agreed that it would be useful; I'll try to get a complete list from
> arch and/or the GSC FW team. Are you ok if we go ahead with this in the
> meantime?
alan: yes sure.
>
> >
>
[Intel-gfx] ✗ Fi.CI.BAT: failure for Avoid reading OA reports before they land
== Series Details == Series: Avoid reading OA reports before they land URL : https://patchwork.freedesktop.org/series/118886/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13232 -> Patchwork_118886v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_118886v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_118886v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/index.html Participating hosts (37 -> 37) -- Additional (1): bat-rpls-2 Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_118886v1: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_timelines: - fi-apl-guc: [PASS][1] -> [DMESG-WARN][2] +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html Warnings * igt@kms_psr@sprite_plane_onoff: - bat-rplp-1: [SKIP][3] ([i915#1072]) -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html Known issues Here are the changes found in Patchwork_118886v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-rpls-2: NOTRUN -> [SKIP][5] ([i915#7456]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/bat-rpls-2/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@read: - bat-rpls-2: NOTRUN -> [SKIP][6] ([i915#2582]) +4 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/bat-rpls-2/igt@fb...@read.html * igt@gem_lmem_swapping@verify-random: - bat-rpls-2: NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/bat-rpls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_tiled_pread_basic: - bat-rpls-2: NOTRUN -> [SKIP][8] ([i915#3282]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/bat-rpls-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-rpls-2: NOTRUN -> [SKIP][9] ([i915#7561]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/bat-rpls-2/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rpm@module-reload: - fi-apl-guc: [PASS][10] -> [DMESG-WARN][11] ([i915#180] / [i915#1982] / [i915#7634]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/fi-apl-guc/igt@i915_pm_...@module-reload.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/fi-apl-guc/igt@i915_pm_...@module-reload.html * igt@i915_pm_rps@basic-api: - bat-rpls-2: NOTRUN -> [SKIP][12] ([i915#6621]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/bat-rpls-2/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][13] -> [ABORT][14] ([i915#7911] / [i915#7913]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_pm: - bat-rpls-2: NOTRUN -> [DMESG-FAIL][15] ([i915#4258] / [i915#7913]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/bat-rpls-2/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@requests: - bat-rpls-2: NOTRUN -> [ABORT][16] ([i915#4983] / [i915#7913]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/bat-rpls-2/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@reset: - fi-apl-guc: [PASS][17] -> [DMESG-WARN][18] ([i915#7634]) +33 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/fi-apl-guc/igt@i915_selftest@l...@reset.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/fi-apl-guc/igt@i915_selftest@l...@reset.html * igt@i915_selftest@live@slpc: - bat-rpls-1: NOTRUN -> [DMESG-WARN][19] ([i915#6367]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html * igt@i915_suspend@basic-s2idle-without-i915: - fi-apl-guc:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Avoid reading OA reports before they land
== Series Details == Series: Avoid reading OA reports before they land URL : https://patchwork.freedesktop.org/series/118886/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: do not dereference dangling engine pointer on fence release
== Series Details == Series: drm/i915: do not dereference dangling engine pointer on fence release URL : https://patchwork.freedesktop.org/series/118879/ State : success == Summary == CI Bug Log - changes from CI_DRM_13232 -> Patchwork_118879v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/index.html Participating hosts (37 -> 37) -- Additional (1): bat-rpls-2 Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_118879v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-rpls-2: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-rpls-2/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@read: - bat-rpls-2: NOTRUN -> [SKIP][2] ([i915#2582]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-rpls-2/igt@fb...@read.html * igt@gem_lmem_swapping@verify-random: - bat-rpls-2: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-rpls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_tiled_pread_basic: - bat-rpls-2: NOTRUN -> [SKIP][4] ([i915#3282]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-rpls-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-rpls-2: NOTRUN -> [SKIP][5] ([i915#7561]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-rpls-2/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_backlight@basic-brightness@edp-1: - bat-rplp-1: NOTRUN -> [ABORT][6] ([i915#7077]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-rplp-1/igt@i915_pm_backlight@basic-brightn...@edp-1.html * igt@i915_pm_rps@basic-api: - bat-rpls-2: NOTRUN -> [SKIP][7] ([i915#6621]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-rpls-2/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_pm: - bat-rpls-2: NOTRUN -> [DMESG-FAIL][8] ([i915#4258] / [i915#7913]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-rpls-2/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@guc_hang: - fi-kbl-soraka: [PASS][9] -> [INCOMPLETE][10] ([i915#7640]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/fi-kbl-soraka/igt@i915_selftest@live@guc_hang.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/fi-kbl-soraka/igt@i915_selftest@live@guc_hang.html * igt@i915_selftest@live@hangcheck: - bat-dg2-11: [PASS][11] -> [ABORT][12] ([i915#7913] / [i915#7979]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@reset: - bat-rpls-2: NOTRUN -> [ABORT][13] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#8347]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-rpls-2/igt@i915_selftest@l...@reset.html * igt@kms_busy@basic: - bat-rpls-2: NOTRUN -> [SKIP][14] ([i915#1845]) +14 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-rpls-2/igt@kms_b...@basic.html * igt@kms_chamelium_edid@hdmi-edid-read: - bat-rpls-2: NOTRUN -> [SKIP][15] ([i915#7828]) +7 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-rpls-2/igt@kms_chamelium_e...@hdmi-edid-read.html * igt@kms_flip@basic-flip-vs-dpms: - bat-rpls-2: NOTRUN -> [SKIP][16] ([i915#3637]) +3 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-rpls-2/igt@kms_f...@basic-flip-vs-dpms.html * igt@kms_force_connector_basic@force-load-detect: - bat-rpls-2: NOTRUN -> [SKIP][17] ([fdo#109285]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-rpls-2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_frontbuffer_tracking@basic: - bat-rpls-2: NOTRUN -> [SKIP][18] ([i915#1849]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-rpls-2/igt@kms_frontbuffer_track...@basic.html * igt@kms_psr@sprite_plane_onoff: - bat-rpls-2: NOTRUN -> [SKIP][19] ([i915#1072]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/bat-rpls-2/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-rpls-2: NOTRUN -> [SKIP][20] ([i915#3555] / [i915#4579]) [20]:
Re: [Intel-gfx] [PATCH] drm/i915: Fix error handling if driver creation fails during probe
On Thu, Jun 01, 2023 at 03:12:42PM -0300, Gustavo Sousa wrote:
> Quoting Matt Roper (2023-06-01 14:38:04-03:00)
> >If i915_driver_create() fails to create a valid 'i915' object, we
> >should just disable the PCI device and return immediately without trying
> >to call i915_probe_error() that relies on a valid i915 pointer.
> >
> >Fixes: 12e6f6dc78e4 ("drm/i915/display: Handle GMD_ID identification in
> >display code")
> >Reported-by: Dan Carpenter
> >Signed-off-by: Matt Roper
>
> Reviewed-by: Gustavo Sousa
Applied to drm-intel-next. Thanks for the review.
Matt
>
> >---
> > drivers/gpu/drm/i915/i915_driver.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_driver.c
> >b/drivers/gpu/drm/i915/i915_driver.c
> >index c3ab5c32d492..5c3fc57cc4fe 100644
> >--- a/drivers/gpu/drm/i915/i915_driver.c
> >+++ b/drivers/gpu/drm/i915/i915_driver.c
> >@@ -762,8 +762,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
> >pci_device_id *ent)
> >
> > i915 = i915_driver_create(pdev, ent);
> > if (IS_ERR(i915)) {
> >-ret = PTR_ERR(i915);
> >-goto out_pci_disable;
> >+pci_disable_device(pdev);
> >+return PTR_ERR(i915);
> > }
> >
> > ret = i915_driver_early_probe(i915);
> >--
> >2.40.1
> >
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Extract display init from intel_device_info_runtime_init (rev2)
On Mon, Jun 05, 2023 at 09:14:58AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/display: Extract display init from > intel_device_info_runtime_init (rev2) > URL : https://patchwork.freedesktop.org/series/118730/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_13222_full -> Patchwork_118730v2_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_118730v2_full absolutely need > to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_118730v2_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Participating hosts (7 -> 7) > -- > > No changes in participating hosts > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_118730v2_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_busy@extended-modeset-hang-newfb-with-reset@pipe-b: > - shard-snb: [PASS][1] -> [INCOMPLETE][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-snb2/igt@kms_busy@extended-modeset-hang-newfb-with-re...@pipe-b.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-snb2/igt@kms_busy@extended-modeset-hang-newfb-with-re...@pipe-b.html Random incomplete; no reason in the logs. Does not appear to be related to this patch. Applied to drm-intel-next. Thanks Jani for the review. Matt > > > Known issues > > > Here are the changes found in Patchwork_118730v2_full that come from known > issues: > > ### CI changes ### > > Possible fixes > > * boot: > - shard-glk: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], > [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], > [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], > [PASS][19], [FAIL][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], > [PASS][25], [PASS][26]) ([i915#7849] / [i915#8293]) -> ([PASS][27], > [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], > [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], > [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], > [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51]) >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk1/boot.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk1/boot.html >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk1/boot.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk2/boot.html >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk2/boot.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk2/boot.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/boot.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/boot.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/boot.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk4/boot.html >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk4/boot.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk5/boot.html >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk5/boot.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk6/boot.html >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk6/boot.html >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk6/boot.html >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk7/boot.html >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk7/boot.html >[21]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk7/boot.html >[22]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/boot.html >[23]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/boot.html >[24]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/boot.html >[25]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk9/boot.html >[26]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk9/boot.html >[27]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk7/boot.html >[28]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk7/boot.html >[29]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk7/boot.html >[30]: >
Re: [Intel-gfx] [PATCH v9 0/4] drm/i915: use ref_tracker library for tracking wakerefs
On Fri, 02 Jun 2023 12:21:32 +0200 Andrzej Hajda wrote: > This is reviewed series of ref_tracker patches, ready to merge > via network tree, rebased on net-next/main. > i915 patches will be merged later via intel-gfx tree. FWIW I'll try to merge these on top of the -rc4 tag so with a bit of luck you should be able to cross merge cleanly into another -next tree.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Remove some obsolete definitions (rev2)
== Series Details == Series: drm/i915/guc: Remove some obsolete definitions (rev2) URL : https://patchwork.freedesktop.org/series/118658/ State : success == Summary == CI Bug Log - changes from CI_DRM_13232 -> Patchwork_118658v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/index.html Participating hosts (37 -> 36) -- Additional (1): bat-rpls-2 Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_118658v2 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-rpls-2: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rpls-2/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@read: - bat-rpls-2: NOTRUN -> [SKIP][2] ([i915#2582]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rpls-2/igt@fb...@read.html * igt@gem_lmem_swapping@verify-random: - bat-rpls-2: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rpls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_tiled_pread_basic: - bat-rpls-2: NOTRUN -> [SKIP][4] ([i915#3282]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rpls-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-rpls-2: NOTRUN -> [SKIP][5] ([i915#7561]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rpls-2/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_backlight@basic-brightness@edp-1: - bat-rplp-1: NOTRUN -> [ABORT][6] ([i915#7077]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rplp-1/igt@i915_pm_backlight@basic-brightn...@edp-1.html * igt@i915_pm_rps@basic-api: - bat-rpls-2: NOTRUN -> [SKIP][7] ([i915#6621]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rpls-2/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [PASS][8] -> [DMESG-FAIL][9] ([i915#5334]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - bat-rpls-2: NOTRUN -> [DMESG-FAIL][10] ([i915#4258] / [i915#7913]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rpls-2/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@slpc: - bat-rpls-1: NOTRUN -> [DMESG-WARN][11] ([i915#6367]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rpls-1/igt@i915_selftest@l...@slpc.html * igt@i915_suspend@basic-s2idle-without-i915: - bat-rpls-2: NOTRUN -> [ABORT][12] ([i915#6687]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html * igt@i915_suspend@basic-s3-without-i915: - bat-rpls-1: NOTRUN -> [ABORT][13] ([i915#6687] / [i915#7978]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_busy@basic: - bat-rpls-2: NOTRUN -> [SKIP][14] ([i915#1845]) +14 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rpls-2/igt@kms_b...@basic.html * igt@kms_chamelium_edid@hdmi-edid-read: - bat-rpls-2: NOTRUN -> [SKIP][15] ([i915#7828]) +7 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rpls-2/igt@kms_chamelium_e...@hdmi-edid-read.html * igt@kms_flip@basic-flip-vs-dpms: - bat-rpls-2: NOTRUN -> [SKIP][16] ([i915#3637]) +3 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rpls-2/igt@kms_f...@basic-flip-vs-dpms.html * igt@kms_force_connector_basic@force-load-detect: - bat-rpls-2: NOTRUN -> [SKIP][17] ([fdo#109285]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rpls-2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_frontbuffer_tracking@basic: - bat-rpls-2: NOTRUN -> [SKIP][18] ([i915#1849]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-rpls-2/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@read-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][19] ([i915#1845] / [i915#5354]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc-frame-sequence.html * igt@kms_psr@sprite_plane_onoff: -
Re: [Intel-gfx] [PATCH] drm/i915: Implement fdinfo memory stats printing
Hi Tvrtko,
On Mon, Jun 05, 2023 at 03:37:20PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Use the newly added drm_print_memory_stats helper to show memory
> utilisation of our objects in drm/driver specific fdinfo output.
>
> To collect the stats we walk the per memory regions object lists
> and accumulate object size into the respective drm_memory_stats
> categories.
>
> Objects with multiple possible placements are reported in multiple
> regions for total and shared sizes, while other categories are
> counted only for the currently active region.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Rob Clark
> ---
> drivers/gpu/drm/i915/i915_drm_client.c | 66 ++
> 1 file changed, 66 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drm_client.c
> b/drivers/gpu/drm/i915/i915_drm_client.c
> index 2a44b3876cb5..2a40f763f8f6 100644
> --- a/drivers/gpu/drm/i915/i915_drm_client.c
> +++ b/drivers/gpu/drm/i915/i915_drm_client.c
> @@ -41,6 +41,70 @@ void __i915_drm_client_free(struct kref *kref)
> }
>
> #ifdef CONFIG_PROC_FS
> +static void
> +add_obj_meminfo(struct drm_i915_gem_object *obj,
> + struct intel_memory_region *mr,
> + struct drm_memory_stats stats[INTEL_REGION_UNKNOWN])
> +{
> + u64 sz = obj->base.size;
> + enum intel_region_id id;
> + unsigned int i;
> +
> + id = mr->id;
> + if (obj->base.handle_count > 1)
> + stats[id].shared += sz;
> + else
> + stats[id].private += sz;
> +
> + if (i915_gem_object_has_pages(obj)) {
> + stats[id].resident += sz;
> +
> + if (!dma_resv_test_signaled(obj->base.resv,
> + dma_resv_usage_rw(true)))
> + stats[id].active += sz;
> + else if (i915_gem_object_is_shrinkable(obj) &&
> + obj->mm.madv == I915_MADV_DONTNEED)
> + stats[id].purgeable += sz;
this is a bit off... otherwise:
Reviewed-by: Andi Shyti
Andi
> + }
> +
> + /* Attribute size and shared to all possible object memory regions. */
> + for (i = 0; i < obj->mm.n_placements; i++) {
> + if (obj->mm.placements[i] == mr)
> + continue;
> +
> + id = obj->mm.placements[i]->id;
> + if (obj->base.handle_count > 1)
> + stats[id].shared += sz;
> + else
> + stats[id].private += sz;
> + }
> +}
> +
> +static void show_meminfo(struct drm_printer *p, struct drm_file *file)
> +{
> + struct drm_i915_file_private *file_priv = file->driver_priv;
> + struct drm_memory_stats stats[INTEL_REGION_UNKNOWN] = {};
> + struct drm_i915_private *i915 = file_priv->i915;
> + struct intel_memory_region *mr;
> + unsigned int id;
> +
> + for_each_memory_region(mr, i915, id) {
> + struct drm_i915_gem_object *obj;
> +
> + mutex_lock(>objects.lock);
> + list_for_each_entry(obj, >objects.list, mm.region_link)
> + add_obj_meminfo(obj, mr, stats);
> + mutex_unlock(>objects.lock);
> + }
> +
> + for_each_memory_region(mr, i915, id)
> + drm_print_memory_stats(p,
> +[id],
> +DRM_GEM_OBJECT_RESIDENT |
> +DRM_GEM_OBJECT_PURGEABLE,
> +mr->name);
> +}
> +
> static const char * const uabi_class_names[] = {
> [I915_ENGINE_CLASS_RENDER] = "render",
> [I915_ENGINE_CLASS_COPY] = "copy",
> @@ -102,6 +166,8 @@ void i915_drm_client_fdinfo(struct drm_printer *p, struct
> drm_file *file)
>* **
>*/
>
> + show_meminfo(p, file);
> +
> if (GRAPHICS_VER(i915) < 8)
> return;
>
> --
> 2.39.2
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Remove some obsolete definitions (rev2)
== Series Details == Series: drm/i915/guc: Remove some obsolete definitions (rev2) URL : https://patchwork.freedesktop.org/series/118658/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH v2 1/2] vgaarb: various coding style and comments fix
Hi Sui,
On Mon, Jun 05, 2023 at 04:58:30AM +0800, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> To keep consistent with vga_iostate_to_str() function, the third argument
> of vga_str_to_iostate() function should be 'unsigned int *'.
I think the real reason is not to keep consistent with
vga_iostate_to_str() but because vga_str_to_iostate() is actually
only taking "unsigned int *" parameters.
> Signed-off-by: Sui Jingfeng
> ---
> drivers/pci/vgaarb.c | 29 +++--
> include/linux/vgaarb.h | 8 +++-
> 2 files changed, 18 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/pci/vgaarb.c b/drivers/pci/vgaarb.c
> index 5a696078b382..e40e6e5e5f03 100644
> --- a/drivers/pci/vgaarb.c
> +++ b/drivers/pci/vgaarb.c
> @@ -61,7 +61,6 @@ static bool vga_arbiter_used;
> static DEFINE_SPINLOCK(vga_lock);
> static DECLARE_WAIT_QUEUE_HEAD(vga_wait_queue);
>
> -
drop this change
> static const char *vga_iostate_to_str(unsigned int iostate)
> {
> /* Ignore VGA_RSRC_IO and VGA_RSRC_MEM */
> @@ -77,10 +76,12 @@ static const char *vga_iostate_to_str(unsigned int
> iostate)
> return "none";
> }
>
> -static int vga_str_to_iostate(char *buf, int str_size, int *io_state)
> +static int vga_str_to_iostate(char *buf, int str_size, unsigned int
> *io_state)
this is OK, it's actually what you are describing in the commit
log, but...
> {
> - /* we could in theory hand out locks on IO and mem
> - * separately to userspace but it can cause deadlocks */
> + /*
> + * we could in theory hand out locks on IO and mem
> + * separately to userspace but it can cause deadlocks
> + */
... all the rest needs to go on different patches as it doesn't
have anything to do with what you describe.
Andi
Re: [Intel-gfx] [PATCH] drm/i915: Use the fdinfo helper
Hi Tvrtko, On Mon, Jun 05, 2023 at 01:32:24PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Use the common fdinfo helper for printing the basics. Remove now unused > client id allocation code. > > Signed-off-by: Tvrtko Ursulin > Cc: Rob Clark looks good to me: Reviewed-by: Andi Shyti Andi
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow user to set cache at BO creation (rev2)
== Series Details == Series: drm/i915: Allow user to set cache at BO creation (rev2) URL : https://patchwork.freedesktop.org/series/118660/ State : success == Summary == CI Bug Log - changes from CI_DRM_13232 -> Patchwork_118660v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/index.html Participating hosts (37 -> 36) -- Additional (1): bat-rpls-2 Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_118660v2 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-rpls-2: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-rpls-2/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@read: - bat-rpls-2: NOTRUN -> [SKIP][2] ([i915#2582]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-rpls-2/igt@fb...@read.html * igt@gem_lmem_swapping@verify-random: - bat-rpls-2: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-rpls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_tiled_pread_basic: - bat-rpls-2: NOTRUN -> [SKIP][4] ([i915#3282]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-rpls-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-rpls-2: NOTRUN -> [SKIP][5] ([i915#7561]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-rpls-2/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-rpls-2: NOTRUN -> [SKIP][6] ([i915#6621]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-rpls-2/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_heartbeat: - bat-jsl-3: [PASS][7] -> [DMESG-FAIL][8] ([i915#5334]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/bat-jsl-3/igt@i915_selftest@live@gt_heartbeat.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-jsl-3/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_lrc: - bat-adlp-9: [PASS][9] -> [INCOMPLETE][10] ([i915#7913]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/bat-adlp-9/igt@i915_selftest@live@gt_lrc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-adlp-9/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@gt_pm: - bat-rpls-2: NOTRUN -> [DMESG-FAIL][11] ([i915#4258] / [i915#7913]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-rpls-2/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@reset: - bat-rpls-2: NOTRUN -> [ABORT][12] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#8347]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-rpls-2/igt@i915_selftest@l...@reset.html * igt@i915_selftest@live@slpc: - bat-rpls-1: NOTRUN -> [DMESG-WARN][13] ([i915#6367]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-rpls-1/igt@i915_selftest@l...@slpc.html * igt@i915_suspend@basic-s3-without-i915: - bat-rpls-1: NOTRUN -> [ABORT][14] ([i915#6687] / [i915#7978]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_busy@basic: - bat-rpls-2: NOTRUN -> [SKIP][15] ([i915#1845]) +14 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-rpls-2/igt@kms_b...@basic.html * igt@kms_chamelium_edid@hdmi-edid-read: - bat-rpls-2: NOTRUN -> [SKIP][16] ([i915#7828]) +7 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-rpls-2/igt@kms_chamelium_e...@hdmi-edid-read.html * igt@kms_flip@basic-flip-vs-dpms: - bat-rpls-2: NOTRUN -> [SKIP][17] ([i915#3637]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-rpls-2/igt@kms_f...@basic-flip-vs-dpms.html * igt@kms_force_connector_basic@force-load-detect: - bat-rpls-2: NOTRUN -> [SKIP][18] ([fdo#109285]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-rpls-2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_frontbuffer_tracking@basic: - bat-rpls-2: NOTRUN -> [SKIP][19] ([i915#1849]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/bat-rpls-2/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1: - bat-dg2-8: [PASS][20] -> [FAIL][21] ([i915#7932]) [20]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Allow user to set cache at BO creation (rev2)
== Series Details == Series: drm/i915: Allow user to set cache at BO creation (rev2) URL : https://patchwork.freedesktop.org/series/118660/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Allow user to set cache at BO creation (rev2)
== Series Details == Series: drm/i915: Allow user to set cache at BO creation (rev2) URL : https://patchwork.freedesktop.org/series/118660/ State : warning == Summary == Error: dim checkpatch failed 50bed5f80c75 drm/i915: Allow user to set cache at BO creation -:28: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #28: https://github.com/intel/media-driver/commit/92c00a857433ebb34ec575e9834f473c6fcb6341 total: 0 errors, 1 warnings, 0 checks, 132 lines checked
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Implement fdinfo memory stats printing
== Series Details == Series: drm/i915: Implement fdinfo memory stats printing URL : https://patchwork.freedesktop.org/series/118870/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/118870/revisions/1/mbox/ not applied Applying: drm/i915: Implement fdinfo memory stats printing Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_drm_client.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_drm_client.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_drm_client.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 drm/i915: Implement fdinfo memory stats printing When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
[Intel-gfx] [PATCH] drm/i915/guc: Force a reset on internal GuC error
From: John Harrison
If GuC hits an internal error (and survives long enough to report it
to the KMD), it is basically toast and will stop until a GT reset and
subsequent GuC reload is performed. Previously, the KMD just printed
an error message and then waited for the heartbeat to eventually kick
in and trigger a reset (assuming the heartbeat had not been disabled).
Instead, force the reset immediately to guarantee that it happens and
to eliminate the very long heartbeat delay. The captured error state
is also more likely to be useful if captured at the time of the error
rather than many seconds later.
Note that it is not possible to trigger a reset from with the G2H
handler itself. The reset prepare process involves flushing
outstanding G2H contents. So a deadlock could result. Instead, the G2H
handler queues a worker thread to do the reset asynchronously.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 26 +++
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 9
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +-
3 files changed, 36 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2eb891b270aec..c35cf10f52b56 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -159,6 +159,13 @@ static void gen11_disable_guc_interrupts(struct intel_guc
*guc)
gen11_reset_guc_interrupts(guc);
}
+static void guc_dead_worker_func(struct work_struct *w)
+{
+ struct intel_guc *guc = container_of(w, struct intel_guc,
dead_guc_worker);
+
+ intel_gt_handle_error(guc_to_gt(guc), ALL_ENGINES, I915_ERROR_CAPTURE,
"dead GuC");
+}
+
void intel_guc_init_early(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
@@ -171,6 +178,8 @@ void intel_guc_init_early(struct intel_guc *guc)
intel_guc_slpc_init_early(>slpc);
intel_guc_rc_init_early(guc);
+ INIT_WORK(>dead_guc_worker, guc_dead_worker_func);
+
mutex_init(>send_mutex);
spin_lock_init(>irq_lock);
if (GRAPHICS_VER(i915) >= 11) {
@@ -585,6 +594,20 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
return ret;
}
+int intel_guc_crash_process_msg(struct intel_guc *guc, u32 action)
+{
+ if (action == INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED)
+ guc_err(guc, "Crash dump notification\n");
+ else if (action == INTEL_GUC_ACTION_NOTIFY_EXCEPTION)
+ guc_err(guc, "Exception notification\n");
+ else
+ guc_err(guc, "Unknown crash notification\n");
+
+ queue_work(system_unbound_wq, >dead_guc_worker);
+
+ return 0;
+}
+
int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
const u32 *payload, u32 len)
{
@@ -601,6 +624,9 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc
*guc,
if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)
guc_err(guc, "Received early exception notification!\n");
+ if (msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
INTEL_GUC_RECV_MSG_EXCEPTION))
+ queue_work(system_unbound_wq, >dead_guc_worker);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 8dc291ff00935..0b54eec95fc00 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -266,6 +266,14 @@ struct intel_guc {
unsigned long last_stat_jiffies;
} timestamp;
+ /**
+* @dead_guc_worker: Asynchronous worker thread for forcing a GuC reset.
+* Specifically used when the G2H handler wants to issue a reset. Resets
+* require flushing the G2H queue. So, the G2H processing itself must
not
+* trigger a reset directly. Instead, go via this worker.
+*/
+ struct work_struct dead_guc_worker;
+
#ifdef CONFIG_DRM_I915_SELFTEST
/**
* @number_guc_id_stolen: The number of guc_ids that have been stolen
@@ -476,6 +484,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc
*guc,
const u32 *msg, u32 len);
int intel_guc_error_capture_process_msg(struct intel_guc *guc,
const u32 *msg, u32 len);
+int intel_guc_crash_process_msg(struct intel_guc *guc, u32 action);
struct intel_engine_cs *
intel_guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index f28a3a83742dc..7b09ad6931021 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -1116,12 +1116,8 @@ static int ct_process_request(struct intel_guc_ct *ct,
struct ct_incoming_msg *r
ret = 0;
break;
case
Re: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
+Tvrtko
+Joonas
> -Original Message-
> From: Jani Nikula
> Sent: Monday, June 5, 2023 11:29 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for
> display and graphics step
>
> On Mon, 05 Jun 2023, "Srivatsa, Anusha" wrote:
> >> -Original Message-
> >> From: Jani Nikula
> >> Sent: Monday, June 5, 2023 8:14 AM
> >> To: Srivatsa, Anusha ; intel-
> >> g...@lists.freedesktop.org
> >> Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/adlp:
> >> s/ADLP/ALDERLAKE_P for display and graphics step
> >>
> >> On Tue, 30 May 2023, Anusha Srivatsa wrote:
> >> > Driver refers to the platfrom Alderlake P as ADLP in places and
> >> > ALDERLAKE_P in some. Making the consistent change to avoid
> >> > confusion of the right naming convention for the platform.
> >>
> >> $ git grep "#define IS_.*_DISPLAY_STEP" --
> >> drivers/gpu/drm/i915/i915_drv.h
> >> drivers/gpu/drm/i915/i915_drv.h:#define IS_KBL_DISPLAY_STEP(i915,
> >> since,
> >> until) \ drivers/gpu/drm/i915/i915_drv.h:#define
> >> IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
> >> drivers/gpu/drm/i915/i915_drv.h:#define
> >> IS_TGL_DISPLAY_STEP(__i915, since, until) \
> >> drivers/gpu/drm/i915/i915_drv.h:#define IS_RKL_DISPLAY_STEP(p, since,
> >> until) \ drivers/gpu/drm/i915/i915_drv.h:#define
> >> IS_ADLS_DISPLAY_STEP(__i915, since,
> >> until) \ drivers/gpu/drm/i915/i915_drv.h:#define
> >> IS_ADLP_DISPLAY_STEP(__i915, since, until) \
> >> drivers/gpu/drm/i915/i915_drv.h:#define IS_MTL_DISPLAY_STEP(__i915,
> >> since,
> >> until) \ drivers/gpu/drm/i915/i915_drv.h:#define
> >> IS_DG2_DISPLAY_STEP(__i915, since, until) \
> >>
> >> They all use the acronym. Do you suggest to rename all of them, or just
> >> ADL-
> P?
> >
> > Got the idea after looking at subplatform defines in i915_drv.h:
> >
> > #define IS_METEORLAKE_M(i915) \
> > IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
> > #define IS_METEORLAKE_P(i915) \
> > IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
> > #define IS_DG2_G10(i915) \
> > IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) #define
> > IS_DG2_G11(i915) \
> > IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) #define
> > IS_DG2_G12(i915) \
> > IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) #define
> > IS_ADLS_RPLS(i915) \
> > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S,
> INTEL_SUBPLATFORM_RPL)
> > #define IS_ADLP_N(i915) \
> > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
> > #define IS_ADLP_RPLP(i915) \
> > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P,
> INTEL_SUBPLATFORM_RPL)
> > #define IS_ADLP_RPLU(i915) \
> > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P,
> > INTEL_SUBPLATFORM_RPLU)
> >
> > We are using the same platform name for platform and sub-platform defines
> for Meteor Lake and DG2, but somehow for flavors of Alder Lake, the sub-
> platform has acronym. The idea was that developers should not think if the
> full
> name or acronym has to be used. And that resulted in the series. But now that
> you have pointed out the above other such occurrences, I am leaning towards
> having them changed as well. That is for a platform defined as TIGERLAKE, All
> of
> its steppings etc should have
> TIGERLAKE_(TIGERLAKE_MEDIA_,TIGERLAKE_DISPLAY_, TIGERLAKE_GRAPHICS_
> ) etc instead of having TIGERLAKE in some places and TGL in its stepping or
> sub-
> platform defines.
> >
> > This was the naming is uniform and consistent.
>
> One could also make the case for switching all of them use the acronym instead
> for brevity.
That works too.
Anusha
> BR,
> Jani.
>
>
> >
> > Anusha
> >> BR,
> >> Jani.
> >>
> >>
> >>
> >> >
> >> > Signed-off-by: Anusha Srivatsa
> >> > ---
> >> > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> >> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
> >> > drivers/gpu/drm/i915/display/intel_psr.c | 8
> >> > drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
> >> > drivers/gpu/drm/i915/i915_drv.h| 4 ++--
> >> > 5 files changed, 10 insertions(+), 10 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> > index 6bed75f1541a..013678caaca8 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> > @@ -3541,7 +3541,7 @@ void intel_init_cdclk_hooks(struct
> >> > drm_i915_private
> >> *dev_priv)
> >> > } else if (IS_ALDERLAKE_P(dev_priv)) {
> >> > dev_priv->display.funcs.cdclk = _cdclk_funcs;
> >> > /* Wa_22011320316:adl-p[a0] */
> >> > -if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >> > +if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0,
> >> STEP_B0))
> >> >
Re: [Intel-gfx] [PATCH] drm/i915: Fix a VMA UAF for multi-gt platform
Hi Nirmoy,
On Mon, Jun 05, 2023 at 10:10:21PM +0200, Nirmoy Das wrote:
> Ensure correct handling of closed VMAs on multi-gt platforms to prevent
> Use-After-Free. Currently, when GT0 goes idle, closed VMAs that are
> exclusively added to GT0's closed_vma link (gt->closed_vma) and
> subsequently freed by i915_vma_parked(), which assumes the entire GPU is
> idle. However, on platforms with multiple GTs, such as MTL, GT1 may
> remain active while GT0 is idle. This causes GT0 to mistakenly consider
> the closed VMAs in its closed_vma list as unnecessary, potentially
> leading to Use-After-Free issues if a job for GT1 attempts to access a
> freed VMA.
>
> Although we do take a wakeref for GT0 but it happens later, after
> evaluating VMAs. To mitigate this, it is necessary to hold a GT0 wakeref
> early.
hooray! this is great, Nirmoy! I will give it a shot.
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: Tvrtko Ursulin
> Cc: Thomas Hellström
> Cc: Chris Wilson
> Cc: Andi Shyti
> Cc: Andrzej Hajda
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 5fb459ea4294..adcf8837dfe6 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -2692,6 +2692,7 @@ static int
> eb_select_engine(struct i915_execbuffer *eb)
> {
> struct intel_context *ce, *child;
> + struct intel_gt *gt;
> unsigned int idx;
> int err;
>
> @@ -2715,10 +2716,16 @@ eb_select_engine(struct i915_execbuffer *eb)
> }
> }
> eb->num_batches = ce->parallel.number_children + 1;
> + gt = ce->engine->gt;
>
> for_each_child(ce, child)
> intel_context_get(child);
> intel_gt_pm_get(ce->engine->gt);
> + /* Keep GT0 active on MTL so that i915_vma_parked() doesn't
> + * free VMAs while execbuf ioctl is validating VMAs.
> + */
> + if (gt != to_gt(gt->i915))
you can use gt->info.id
> + intel_gt_pm_get(to_gt(ce->engine->gt->i915));
>
> if (!test_bit(CONTEXT_ALLOC_BIT, >flags)) {
> err = intel_context_alloc_state(ce);
> @@ -2757,6 +2764,9 @@ eb_select_engine(struct i915_execbuffer *eb)
> return err;
>
> err:
> + if (ce->engine->gt != to_gt(ce->engine->gt->i915))
if (gt->info.id)
gt is already ce->engine->gt
> + intel_gt_pm_get(to_gt(ce->engine->gt->i915));
> +
> intel_gt_pm_put(ce->engine->gt);
> for_each_child(ce, child)
> intel_context_put(child);
> @@ -2770,6 +2780,8 @@ eb_put_engine(struct i915_execbuffer *eb)
> struct intel_context *child;
>
> i915_vm_put(eb->context->vm);
> + if (eb->gt != to_gt(eb->gt->i915))
> + intel_gt_pm_put(to_gt(eb->gt->i915));
this wakeref going up and down is a bit ugly... Perhaps we can
add some flag about the GT type in the info structure. MTL is a
weird multi-gt platform and, indeed, you can't shut down GT0
without affecting GT1.
For now it's OK, though, as to test it.
Andi
> intel_gt_pm_put(eb->gt);
> for_each_child(eb->context, child)
> intel_context_put(child);
> --
> 2.39.0
[Intel-gfx] [PATCH] drm/i915: Fix a VMA UAF for multi-gt platform
Ensure correct handling of closed VMAs on multi-gt platforms to prevent
Use-After-Free. Currently, when GT0 goes idle, closed VMAs that are
exclusively added to GT0's closed_vma link (gt->closed_vma) and
subsequently freed by i915_vma_parked(), which assumes the entire GPU is
idle. However, on platforms with multiple GTs, such as MTL, GT1 may
remain active while GT0 is idle. This causes GT0 to mistakenly consider
the closed VMAs in its closed_vma list as unnecessary, potentially
leading to Use-After-Free issues if a job for GT1 attempts to access a
freed VMA.
Although we do take a wakeref for GT0 but it happens later, after
evaluating VMAs. To mitigate this, it is necessary to hold a GT0 wakeref
early.
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: Thomas Hellström
Cc: Chris Wilson
Cc: Andi Shyti
Cc: Andrzej Hajda
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 5fb459ea4294..adcf8837dfe6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2692,6 +2692,7 @@ static int
eb_select_engine(struct i915_execbuffer *eb)
{
struct intel_context *ce, *child;
+ struct intel_gt *gt;
unsigned int idx;
int err;
@@ -2715,10 +2716,16 @@ eb_select_engine(struct i915_execbuffer *eb)
}
}
eb->num_batches = ce->parallel.number_children + 1;
+ gt = ce->engine->gt;
for_each_child(ce, child)
intel_context_get(child);
intel_gt_pm_get(ce->engine->gt);
+ /* Keep GT0 active on MTL so that i915_vma_parked() doesn't
+* free VMAs while execbuf ioctl is validating VMAs.
+*/
+ if (gt != to_gt(gt->i915))
+ intel_gt_pm_get(to_gt(ce->engine->gt->i915));
if (!test_bit(CONTEXT_ALLOC_BIT, >flags)) {
err = intel_context_alloc_state(ce);
@@ -2757,6 +2764,9 @@ eb_select_engine(struct i915_execbuffer *eb)
return err;
err:
+ if (ce->engine->gt != to_gt(ce->engine->gt->i915))
+ intel_gt_pm_get(to_gt(ce->engine->gt->i915));
+
intel_gt_pm_put(ce->engine->gt);
for_each_child(ce, child)
intel_context_put(child);
@@ -2770,6 +2780,8 @@ eb_put_engine(struct i915_execbuffer *eb)
struct intel_context *child;
i915_vm_put(eb->context->vm);
+ if (eb->gt != to_gt(eb->gt->i915))
+ intel_gt_pm_put(to_gt(eb->gt->i915));
intel_gt_pm_put(eb->gt);
for_each_child(eb->context, child)
intel_context_put(child);
--
2.39.0
[Intel-gfx] [PATCH v4 0/2] Avoid reading OA reports before they land
Fix OA issue seen on DG2 where parts of OA reports are zeroed out or have stale values. This was due to the fact that rewind logic was not being run when the tail pointer was aged. The series drops the complex aging/aged logic and just checks the reports for validity. rev1 - https://patchwork.freedesktop.org/series/118054/ v2: Drop aging logic completely v3: Remove unnecessary renames and squash patches v4: Indentaion fixes Signed-off-by: Umesh Nerlige Ramappa Umesh Nerlige Ramappa (2): i915/perf: Drop the aging_tail logic in perf OA i915/perf: Do not add ggtt offset to hw_tail drivers/gpu/drm/i915/i915_perf.c | 92 ++ drivers/gpu/drm/i915/i915_perf_types.h | 12 2 files changed, 36 insertions(+), 68 deletions(-) -- 2.36.1
[Intel-gfx] [PATCH v4 1/2] i915/perf: Drop the aging_tail logic in perf OA
On DG2, capturing OA reports while running heavy render workloads
sometimes results in invalid OA reports where 64-byte chunks inside
reports have stale values. Under memory pressure, high OA sampling rates
(13.3 us) and heavy render workload, occasionally, the OA HW TAIL
pointer does not progress as fast as the sampling rate. When these
glitches occur, the TAIL pointer takes approx. 200us to progress. While
this is expected behavior from the HW perspective, invalid reports are
not expected.
In oa_buffer_check_unlocked(), when we execute the if condition, we are
updating the oa_buffer.tail to the aging tail and then setting pollin
based on this tail value, however, we do not have a chance to rewind and
validate the reports prior to setting pollin. The validation happens
in a subsequent call to oa_buffer_check_unlocked(). If a read occurs
before this validation, then we end up reading reports up until this
oa_buffer.tail value which includes invalid reports. Though found on
DG2, this affects all platforms.
The aging tail logic is no longer necessary since we are explicitly
checking for landed reports.
Start by dropping the aging tail logic.
v2:
- Drop extra blank line
- Add reason to drop aging logic (Ashutosh)
- Add bug links (Ashutosh)
- rename aged_tail to read_tail
- Squash patches 3 and 1
v3: (Ashutosh)
- Remove extra spaces
- Remove gtt_offset from the pollin calculation
- s/Bug:/Link/ in commit message (checkpatch)
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7484
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7757
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 95 +++---
drivers/gpu/drm/i915/i915_perf_types.h | 12
2 files changed, 38 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 58284156428d..a8d43bf1f6d5 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -531,8 +531,7 @@ static void oa_context_id_squash(struct i915_perf_stream
*stream, u32 *report)
* (See description of OA_TAIL_MARGIN_NSEC above for further details.)
*
* Besides returning true when there is data available to read() this function
- * also updates the tail, aging_tail and aging_timestamp in the oa_buffer
- * object.
+ * also updates the tail in the oa_buffer object.
*
* Note: It's safe to read OA config state here unlocked, assuming that this is
* only called while the stream is enabled, while the global OA configuration
@@ -544,10 +543,10 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
{
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
int report_size = stream->oa_buffer.format->size;
+ u32 head, tail, read_tail;
unsigned long flags;
bool pollin;
u32 hw_tail;
- u64 now;
u32 partial_report_size;
/* We have to consider the (unlikely) possibility that read() errors
@@ -568,62 +567,47 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
/* Subtract partial amount off the tail */
hw_tail = gtt_offset + OA_TAKEN(hw_tail, partial_report_size);
- now = ktime_get_mono_fast_ns();
-
- if (hw_tail == stream->oa_buffer.aging_tail &&
- (now - stream->oa_buffer.aging_timestamp) > OA_TAIL_MARGIN_NSEC) {
- /* If the HW tail hasn't move since the last check and the HW
-* tail has been aging for long enough, declare it the new
-* tail.
-*/
- stream->oa_buffer.tail = stream->oa_buffer.aging_tail;
- } else {
- u32 head, tail, aged_tail;
-
- /* NB: The head we observe here might effectively be a little
-* out of date. If a read() is in progress, the head could be
-* anywhere between this head and stream->oa_buffer.tail.
-*/
- head = stream->oa_buffer.head - gtt_offset;
- aged_tail = stream->oa_buffer.tail - gtt_offset;
-
- hw_tail -= gtt_offset;
- tail = hw_tail;
-
- /* Walk the stream backward until we find a report with report
-* id and timestmap not at 0. Since the circular buffer pointers
-* progress by increments of 64 bytes and that reports can be up
-* to 256 bytes long, we can't tell whether a report has fully
-* landed in memory before the report id and timestamp of the
-* following report have effectively landed.
-*
-* This is assuming that the writes of the OA unit land in
-* memory in the order they were written to.
-* If not : (╯°□°）╯︵ ┻━┻
-*/
- while (OA_TAKEN(tail, aged_tail) >= report_size) {
- void *report =
[Intel-gfx] [PATCH v4 2/2] i915/perf: Do not add ggtt offset to hw_tail
ggtt offset for hw_tail is not required for the calculations, so drop it. Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Ashutosh Dixit --- drivers/gpu/drm/i915/i915_perf.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index a8d43bf1f6d5..0a111b281578 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -565,7 +565,7 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream) partial_report_size %= report_size; /* Subtract partial amount off the tail */ - hw_tail = gtt_offset + OA_TAKEN(hw_tail, partial_report_size); + hw_tail = OA_TAKEN(hw_tail, partial_report_size); /* NB: The head we observe here might effectively be a little * out of date. If a read() is in progress, the head could be @@ -574,7 +574,6 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream) head = stream->oa_buffer.head - gtt_offset; read_tail = stream->oa_buffer.tail - gtt_offset; - hw_tail -= gtt_offset; tail = hw_tail; /* Walk the stream backward until we find a report with report -- 2.36.1
Re: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
On Mon, 05 Jun 2023, "Srivatsa, Anusha" wrote:
>> -Original Message-
>> From: Jani Nikula
>> Sent: Monday, June 5, 2023 8:14 AM
>> To: Srivatsa, Anusha ; intel-
>> g...@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for
>> display and graphics step
>>
>> On Tue, 30 May 2023, Anusha Srivatsa wrote:
>> > Driver refers to the platfrom Alderlake P as ADLP in places and
>> > ALDERLAKE_P in some. Making the consistent change to avoid confusion
>> > of the right naming convention for the platform.
>>
>> $ git grep "#define IS_.*_DISPLAY_STEP" -- drivers/gpu/drm/i915/i915_drv.h
>> drivers/gpu/drm/i915/i915_drv.h:#define IS_KBL_DISPLAY_STEP(i915, since,
>> until) \ drivers/gpu/drm/i915/i915_drv.h:#define IS_JSL_EHL_DISPLAY_STEP(p,
>> since, until) \ drivers/gpu/drm/i915/i915_drv.h:#define
>> IS_TGL_DISPLAY_STEP(__i915, since, until) \
>> drivers/gpu/drm/i915/i915_drv.h:#define IS_RKL_DISPLAY_STEP(p, since, until)
>> \
>> drivers/gpu/drm/i915/i915_drv.h:#define IS_ADLS_DISPLAY_STEP(__i915, since,
>> until) \ drivers/gpu/drm/i915/i915_drv.h:#define
>> IS_ADLP_DISPLAY_STEP(__i915, since, until) \
>> drivers/gpu/drm/i915/i915_drv.h:#define IS_MTL_DISPLAY_STEP(__i915, since,
>> until) \ drivers/gpu/drm/i915/i915_drv.h:#define IS_DG2_DISPLAY_STEP(__i915,
>> since, until) \
>>
>> They all use the acronym. Do you suggest to rename all of them, or just
>> ADL-P?
>
> Got the idea after looking at subplatform defines in i915_drv.h:
>
> #define IS_METEORLAKE_M(i915) \
> IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
> #define IS_METEORLAKE_P(i915) \
> IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
> #define IS_DG2_G10(i915) \
> IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
> #define IS_DG2_G11(i915) \
> IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
> #define IS_DG2_G12(i915) \
> IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
> #define IS_ADLS_RPLS(i915) \
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
> #define IS_ADLP_N(i915) \
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
> #define IS_ADLP_RPLP(i915) \
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
> #define IS_ADLP_RPLU(i915) \
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
>
> We are using the same platform name for platform and sub-platform defines for
> Meteor Lake and DG2, but somehow for flavors of Alder Lake, the sub-platform
> has acronym. The idea was that developers should not think if the full name
> or acronym has to be used. And that resulted in the series. But now that you
> have pointed out the above other such occurrences, I am leaning towards
> having them changed as well. That is for a platform defined as TIGERLAKE, All
> of its steppings etc should have
> TIGERLAKE_(TIGERLAKE_MEDIA_,TIGERLAKE_DISPLAY_, TIGERLAKE_GRAPHICS_ ) etc
> instead of having TIGERLAKE in some places and TGL in its stepping or
> sub-platform defines.
>
> This was the naming is uniform and consistent.
One could also make the case for switching all of them use the acronym
instead for brevity.
BR,
Jani.
>
> Anusha
>> BR,
>> Jani.
>>
>>
>>
>> >
>> > Signed-off-by: Anusha Srivatsa
>> > ---
>> > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
>> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
>> > drivers/gpu/drm/i915/display/intel_psr.c | 8
>> > drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
>> > drivers/gpu/drm/i915/i915_drv.h| 4 ++--
>> > 5 files changed, 10 insertions(+), 10 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> > index 6bed75f1541a..013678caaca8 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> > @@ -3541,7 +3541,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
>> *dev_priv)
>> >} else if (IS_ALDERLAKE_P(dev_priv)) {
>> >dev_priv->display.funcs.cdclk = _cdclk_funcs;
>> >/* Wa_22011320316:adl-p[a0] */
>> > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>> > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0,
>> STEP_B0))
>> >dev_priv->display.cdclk.table =
>> adlp_a_step_cdclk_table;
>> >else if (IS_ADLP_RPLU(dev_priv))
>> >dev_priv->display.cdclk.table = rplu_cdclk_table; diff
>> > --
>> git
>> > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> > index 6b2d8a1e2aa9..81f3ce5a0a1e 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> > @@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct
>> > drm_i915_private *i915,
Re: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
> -Original Message-
> From: Jani Nikula
> Sent: Monday, June 5, 2023 8:14 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for
> display and graphics step
>
> On Tue, 30 May 2023, Anusha Srivatsa wrote:
> > Driver refers to the platfrom Alderlake P as ADLP in places and
> > ALDERLAKE_P in some. Making the consistent change to avoid confusion
> > of the right naming convention for the platform.
>
> $ git grep "#define IS_.*_DISPLAY_STEP" -- drivers/gpu/drm/i915/i915_drv.h
> drivers/gpu/drm/i915/i915_drv.h:#define IS_KBL_DISPLAY_STEP(i915, since,
> until) \ drivers/gpu/drm/i915/i915_drv.h:#define IS_JSL_EHL_DISPLAY_STEP(p,
> since, until) \ drivers/gpu/drm/i915/i915_drv.h:#define
> IS_TGL_DISPLAY_STEP(__i915, since, until) \
> drivers/gpu/drm/i915/i915_drv.h:#define IS_RKL_DISPLAY_STEP(p, since, until) \
> drivers/gpu/drm/i915/i915_drv.h:#define IS_ADLS_DISPLAY_STEP(__i915, since,
> until) \ drivers/gpu/drm/i915/i915_drv.h:#define
> IS_ADLP_DISPLAY_STEP(__i915, since, until) \
> drivers/gpu/drm/i915/i915_drv.h:#define IS_MTL_DISPLAY_STEP(__i915, since,
> until) \ drivers/gpu/drm/i915/i915_drv.h:#define IS_DG2_DISPLAY_STEP(__i915,
> since, until) \
>
> They all use the acronym. Do you suggest to rename all of them, or just ADL-P?
Got the idea after looking at subplatform defines in i915_drv.h:
#define IS_METEORLAKE_M(i915) \
IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
#define IS_METEORLAKE_P(i915) \
IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
#define IS_DG2_G10(i915) \
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
#define IS_DG2_G11(i915) \
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
#define IS_DG2_G12(i915) \
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
#define IS_ADLS_RPLS(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
#define IS_ADLP_N(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
#define IS_ADLP_RPLP(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
#define IS_ADLP_RPLU(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
We are using the same platform name for platform and sub-platform defines for
Meteor Lake and DG2, but somehow for flavors of Alder Lake, the sub-platform
has acronym. The idea was that developers should not think if the full name or
acronym has to be used. And that resulted in the series. But now that you have
pointed out the above other such occurrences, I am leaning towards having them
changed as well. That is for a platform defined as TIGERLAKE, All of its
steppings etc should have TIGERLAKE_(TIGERLAKE_MEDIA_,TIGERLAKE_DISPLAY_,
TIGERLAKE_GRAPHICS_ ) etc instead of having TIGERLAKE in some places and TGL
in its stepping or sub-platform defines.
This was the naming is uniform and consistent.
Anusha
> BR,
> Jani.
>
>
>
> >
> > Signed-off-by: Anusha Srivatsa
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_psr.c | 8
> > drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
> > drivers/gpu/drm/i915/i915_drv.h| 4 ++--
> > 5 files changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 6bed75f1541a..013678caaca8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -3541,7 +3541,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
> *dev_priv)
> > } else if (IS_ALDERLAKE_P(dev_priv)) {
> > dev_priv->display.funcs.cdclk = _cdclk_funcs;
> > /* Wa_22011320316:adl-p[a0] */
> > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0,
> STEP_B0))
> > dev_priv->display.cdclk.table =
> adlp_a_step_cdclk_table;
> > else if (IS_ADLP_RPLU(dev_priv))
> > dev_priv->display.cdclk.table = rplu_cdclk_table; diff
> > --
> git
> > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index 6b2d8a1e2aa9..81f3ce5a0a1e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct
> > drm_i915_private *i915, struct inte {
> > u32 val;
> >
> > - if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
> > + if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
> > pll->info->id != DPLL_ID_ICL_DPLL0)
> > return;
> > /*
> > diff --git
[Intel-gfx] ✓ Fi.CI.IGT: success for Update various *MAX_GT* definitions
== Series Details ==
Series: Update various *MAX_GT* definitions
URL : https://patchwork.freedesktop.org/series/118807/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13225_full -> Patchwork_118807v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_118807v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][1] -> [ABORT][2] ([i915#5566])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13225/shard-glk4/igt@gen9_exec_pa...@allowed-single.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-glk9/igt@gen9_exec_pa...@allowed-single.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-vga:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4579]) +13
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-snb4/igt@i915_pm_lpsp@kms-l...@kms-lpsp-vga.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-90:
- shard-glk: NOTRUN -> [SKIP][4] ([fdo#109271]) +27 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-glk6/igt@kms_big...@x-tiled-32bpp-rotate-90.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#3886]) +2
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-glk6/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [PASS][6] -> [FAIL][7] ([i915#2346]) +1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13225/shard-apl1/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-apl1/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271]) +34 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-snb7/igt@kms_f...@2x-plain-flip-fb-recreate.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [PASS][9] -> [ABORT][10] ([i915#180])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13225/shard-apl6/igt@kms_flip@flip-vs-suspend-interrupti...@b-dp1.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-apl6/igt@kms_flip@flip-vs-suspend-interrupti...@b-dp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13225/shard-apl6/igt@kms_flip@flip-vs-suspend-interrupti...@c-dp1.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-apl6/igt@kms_flip@flip-vs-suspend-interrupti...@c-dp1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#658])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-glk6/igt@kms_psr2...@primary-plane-update-sf-dmg-area.html
* igt@kms_scaling_modes@scaling-mode-full:
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4579]) +2
similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-glk6/igt@kms_scaling_mo...@scaling-mode-full.html
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
- shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271]) +4 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-apl2/igt@kms_universal_pl...@disable-primary-vs-flip-pipe-d.html
Possible fixes
* igt@gem_barrier_race@remote-request@rcs0:
- shard-apl: [ABORT][16] ([i915#7461] / [i915#8234] / [i915#8272])
-> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13225/shard-apl4/igt@gem_barrier_race@remote-requ...@rcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-apl2/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-rkl}:[FAIL][18] ([i915#6268]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13225/shard-rkl-6/igt@gem_ctx_e...@basic-nohangcheck.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-rkl-7/igt@gem_ctx_e...@basic-nohangcheck.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][20] ([i915#2842]) -> [PASS][21]
[20]:
Re: [Intel-gfx] [PATCH] drm/i915: do not dereference dangling engine pointer on fence release
Hi Andrzej, On 6/5/2023 6:48 PM, Andrzej Hajda wrote: rq->engine can be a dangling pointer if rq->execution_mask has more than one bit set, ie it could be already freed virtual engine. Changing check order prevents dereferncing it in intel_engine_is_virtual(rq->engine). Full description of possible scenarios at the inline comment before the change. I came to the same conclusion but Chris mentioned "you create a guc virtual engine with just one bit in execution_mask" :) Suggestion from Chris was to have "guc virtual bit" in there or "eliminate the single engine guc virtuals". Regards, Nirmoy Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7926 Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/i915/i915_request.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 630a732aaecca8..8775952f5c1bbd 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -166,8 +166,8 @@ static void i915_fence_release(struct dma_fence *fence) * know that if the rq->execution_mask is a single bit, rq->engine * can be a physical engine with the exact corresponding mask. */ - if (!intel_engine_is_virtual(rq->engine) && - is_power_of_2(rq->execution_mask) && + if (is_power_of_2(rq->execution_mask) && + !intel_engine_is_virtual(rq->engine) && !cmpxchg(>engine->request_pool, NULL, rq)) return;
[Intel-gfx] [PATCH] drm/i915: do not dereference dangling engine pointer on fence release
rq->engine can be a dangling pointer if rq->execution_mask has more than one bit set, ie it could be already freed virtual engine. Changing check order prevents dereferncing it in intel_engine_is_virtual(rq->engine). Full description of possible scenarios at the inline comment before the change. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7926 Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/i915/i915_request.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 630a732aaecca8..8775952f5c1bbd 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -166,8 +166,8 @@ static void i915_fence_release(struct dma_fence *fence) * know that if the rq->execution_mask is a single bit, rq->engine * can be a physical engine with the exact corresponding mask. */ - if (!intel_engine_is_virtual(rq->engine) && - is_power_of_2(rq->execution_mask) && + if (is_power_of_2(rq->execution_mask) && + !intel_engine_is_virtual(rq->engine) && !cmpxchg(>engine->request_pool, NULL, rq)) return; -- 2.34.1
Re: [Intel-gfx] [PATCH v15 1/1] drm/i915: Allow user to set cache at BO creation
> On 31/05/2023 18:10, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> To comply with the design that buffer objects shall have immutable
>> cache setting through out their life cycle, {set, get}_caching ioctl's
>> are no longer supported from MTL onward. With that change caching
>> policy can only be set at object creation time. The current code
>> applies a default (platform dependent) cache setting for all objects.
>> However this is not optimal for performance tuning. The patch extends
>> the existing gem_create uAPI to let user set PAT index for the object
>> at creation time.
>> The new extension is platform independent, so UMD's can switch to using
>> this extension for older platforms as well, while {set, get}_caching are
>> still supported on these legacy paltforms for compatibility reason.
>>
>> Note: The detailed description of PAT index is missing in current PRM
>> even for older hardware and will be added by the next PRM update under
>> chapter name "Memory Views".
>>
>> BSpec: 45101
>>
>> Mesa support has been submitted in this merge request:
>> https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
>>
>> The media driver is supported by the following commits:
>> https://github.com/intel/media-driver/commit/92c00a857433ebb34ec575e9834f473c6fcb6341
>> https://github.com/intel/media-driver/commit/fd375cf2c5e1f6bf6b43258ff797b3134aadc9fd
>> https://github.com/intel/media-driver/commit/08dd244b22484770a33464c2c8ae85430e548000
>
> On which platforms will media-driver use the uapi? I couldn't easily
> figure out myself from the links above and also in the master branch I
> couldn't find the implementation of CachePolicyGetPATIndex.
These commits look like platform independent. Carl, could you chime in here?
> Now that PRMs for Tigerlake have been published and Meteorlake situation
> is documented indirectly in Mesa code, my only remaining concern is with
> the older platforms. So if there is no particular reason to have the
> extension working on those, I would strongly suggest we disable there.
What's the concern? There is no change required for older platforms, existing
user space code should continue to work. And this extension should be made
available for any new development because the cache settings for BO's need
to be immutable. And that is platform independent.
> For a precedent see I915_CONTEXT_PARAM_SSEU and how it allows the
> extension only on Gen11 and only for a very specific usecase (see
> restrictions in set_sseu() and i915_gem_user_to_context_sseu()).
>
> Regards,
>
> Tvrtko
>
>>
>> The IGT test related to this change is
>> igt@gem_create@create-ext-set-pat
>>
>> Signed-off-by: Fei Yang
>> Cc: Chris Wilson
>> Cc: Matt Roper
>> Cc: Andi Shyti
>> Reviewed-by: Andi Shyti
>> Acked-by: Jordan Justen
>> Tested-by: Jordan Justen
>> Acked-by: Carl Zhang
>> Tested-by: Lihao Gu
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++
>> drivers/gpu/drm/i915/gem/i915_gem_object.c | 6
>> include/uapi/drm/i915_drm.h| 41 ++
>> 3 files changed, 83 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_create.c
>> index bfe1dbda4cb7..644a936248ad 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
>> @@ -245,6 +245,7 @@ struct create_ext {
>>unsigned int n_placements;
>>unsigned int placement_mask;
>>unsigned long flags;
>> + unsigned int pat_index;
>> };
>>
>> static void repr_placements(char *buf, size_t size,
>> @@ -394,11 +395,39 @@ static int ext_set_protected(struct
>> i915_user_extension __user *base, void *data
>>return 0;
>> }
>>
>> +static int ext_set_pat(struct i915_user_extension __user *base, void *data)
>> +{
>> + struct create_ext *ext_data = data;
>> + struct drm_i915_private *i915 = ext_data->i915;
>> + struct drm_i915_gem_create_ext_set_pat ext;
>> + unsigned int max_pat_index;
>> +
>> + BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
>> + offsetofend(struct drm_i915_gem_create_ext_set_pat,
>> rsvd));
>> +
>> + if (copy_from_user(, base, sizeof(ext)))
>> + return -EFAULT;
>> +
>> + max_pat_index = INTEL_INFO(i915)->max_pat_index;
>> +
>> + if (ext.pat_index > max_pat_index) {
>> + drm_dbg(>drm, "PAT index is invalid: %u\n",
>> + ext.pat_index);
>> + return -EINVAL;
>> + }
>> +
>> + ext_data->pat_index = ext.pat_index;
>> +
>> + return 0;
>> +}
>> +
>> static const i915_user_extension_fn create_extensions[] = {
>>[I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements,
>>[I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected,
>> + [I915_GEM_CREATE_EXT_SET_PAT] = ext_set_pat,
>> };
>>
>> +#define PAT_INDEX_NOT_SET0x
>> /**
>>* i915_gem_create_ext_ioctl
Re: [Intel-gfx] [RESUBMIT][PATCH] x86/mm: Fix PAT bit missing from page protection modify mask
(fixed misspelled Cc: email address of intel-gfx list) On Friday, 2 June 2023 16:53:30 CEST Juergen Gross wrote: > On 02.06.23 16:48, Juergen Gross wrote: > > On 02.06.23 16:43, Borislav Petkov wrote: > >> On Thu, Jun 01, 2023 at 10:47:39AM +0200, Juergen Gross wrote: > >>> As described in the commit message, this only works on bare metal due to the > >>> PAT bit not being needed for WC mappings. > >>> > >>> Making this patch Xen specific would try to cure the symptoms without fixing > >>> the underlying problem: _PAGE_PAT should be regarded the same way as the bits > >>> for caching mode (_PAGE_CHG_MASK). > >> > >> So why isn't _PAGE_PAT part of _PAGE_CHG_MASK? > > > > This would result in problems for large pages: _PAGE_PSE is at the same > > position as _PAGE_PAT (large pages are using _PAGE_PAT_LARGE instead). > > > > Yes, x86 ABI is a mess. > > Oh, wait: I originally thought _PAGE_CHG_MASK would be used for large pages, > too. There is _HPAGE_CHG_MASK for that purpose. Since _HPAGE_CHG_MASK has the _PAGE_PSE aka _PAGE_PAT bit already set, while _PAGE_CHK_MASK has not, the real question is not about large pages processing, I believe, which won't change whether we add _PAGE_PAT to _PAGE_CHG_MASK or not. If we extend _PAGE_CHG_MASK with _PAGE_PAT bit then its value will be not any different from _HPAGE_CHG_MASK. Then, one may ask why _HPAGE_CHG_MASK, with _PAGE_PSE aka PAGE_PAT bit set unlike in _PAGE_CHG_MASK, was introduced once for use with large pages, and _PAGE_CHG_MASK left intact for use with standard pages, if we now think that adding that bit to _PAGE_CHG_MASK won't break processing of standard pages. If we are sure that adding _PAGE_PAT to _PAGE_CHG_MASK won't break any of its users then let's go for it. Thanks, Janusz > > So adding _PAGE_PAT to _PAGE_CHG_MASK and _PAGE_PAT_LARGE to _HPAGE_CHG_MASK > should do the job. At least I hope so. > > > Juergen >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Add some missing error propagation
== Series Details ==
Series: drm/i915/selftests: Add some missing error propagation
URL : https://patchwork.freedesktop.org/series/118867/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13230 -> Patchwork_118867v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/index.html
Participating hosts (38 -> 37)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_118867v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][1] -> [ABORT][2] ([i915#4983] / [i915#7911] /
[i915#7920])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13230/bat-rpls-1/igt@i915_selftest@l...@requests.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/bat-rpls-1/igt@i915_selftest@l...@requests.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1:
- bat-dg2-8: [PASS][3] -> [FAIL][4] ([i915#7932]) +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13230/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
Build changes
-
* Linux: CI_DRM_13230 -> Patchwork_118867v1
CI-20190529: 20190529
CI_DRM_13230: 3a501775a2f12967e4dc3ffe93fda0a99eba4e9a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7318: c2d8ef8b9397d0976959f29dc1dd7c8a698d65fe @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_118867v1: 3a501775a2f12967e4dc3ffe93fda0a99eba4e9a @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
39d2370f8880 drm/i915/selftests: Add some missing error propagation
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/index.html
Re: [Intel-gfx] [PATCHv3] drm/i915/display: Print useful information on error
On Fri, 02 Jun 2023, Arun R Murthy wrote:
> For modifier not supporting async flip, print the modifier and display
> version. Helps in reading the error message.
>
> v2: Reframe the error message (Jani)
>
> Signed-off-by: Arun R Murthy
Thanks for the patch, pushed to din.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f51a55f4e9d0..f23dd937c27c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6012,8 +6012,9 @@ static int intel_async_flip_check_hw(struct
> intel_atomic_state *state, struct in
>*/
> if (DISPLAY_VER(i915) < 12) {
> drm_dbg_kms(>drm,
> - "[PLANE:%d:%s] Modifier does not
> support async flips\n",
> - plane->base.base.id,
> plane->base.name);
> + "[PLANE:%d:%s] Modifier 0x%llx does
> not support async flip on display ver %d\n",
> + plane->base.base.id,
> plane->base.name,
> + new_plane_state->hw.fb->modifier,
> DISPLAY_VER(i915));
> return -EINVAL;
> }
> break;
> @@ -6025,8 +6026,9 @@ static int intel_async_flip_check_hw(struct
> intel_atomic_state *state, struct in
> break;
> default:
> drm_dbg_kms(>drm,
> - "[PLANE:%d:%s] Modifier does not support
> async flips\n",
> - plane->base.base.id, plane->base.name);
> + "[PLANE:%d:%s] Modifier 0x%llx does not
> support async flip\n",
> + plane->base.base.id, plane->base.name,
> + new_plane_state->hw.fb->modifier);
> return -EINVAL;
> }
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE
On Tue, 30 May 2023, Anusha Srivatsa wrote: > Replace all occurences of ADL -> ALDERLAKE in > platform and subplatform defines. This way there is a > consistent pattern to how platforms are referred. While > the change is minor and could be combined to have lesser patches, > splitting to per subpaltform for easier cherrypicks, if needed. Cc: Joonas, Tvrtko Commented on a couple of patches. I'm not necessarily opposed to switching from acronyms to full names, but this series alone does not improve consistency. Quite the opposite actually. It's a lot of churn to rename everything. Do we really want that? BR, Jani. > > Anusha Srivatsa (5): > drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step > drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines > drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines > drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines > drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines > > drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++-- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c| 2 +- > drivers/gpu/drm/i915/display/intel_psr.c | 8 > .../gpu/drm/i915/display/skl_universal_plane.c | 4 ++-- > drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +- > drivers/gpu/drm/i915/gt/uc/intel_uc.c| 2 +- > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 16 > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > drivers/gpu/drm/i915/intel_step.c| 6 +++--- > 10 files changed, 24 insertions(+), 24 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Add some missing error propagation
== Series Details == Series: drm/i915/selftests: Add some missing error propagation URL : https://patchwork.freedesktop.org/series/118867/ State : warning == Summary == Error: dim checkpatch failed d98c3c8a49dd drm/i915/selftests: Add some missing error propagation -:13: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report #13: Reported-by: Dan Carpenter Cc: Andi Shyti total: 0 errors, 1 warnings, 0 checks, 34 lines checked
Re: [Intel-gfx] [PATCH 2/5] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines
On Tue, 30 May 2023, Anusha Srivatsa wrote:
> Follow consistent naming convention. Replace ADLP with
> ALDERLAKE_P.
Here too the consistent naming convention for all macros using
IS_SUBPLATFORM() is to use the acronym. The IS_METEORLAKE_M() and
IS_METEORLAKE_P() macros are the outliers.
Again, do you suggest we rename all of them, or just ADL-P? The former
is a lot of churn, and the latter is not consistent.
BR,
Jani.
>
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_step.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1a50b8b2f00d..43414cdc137c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -581,7 +581,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
> #define IS_ADLP_N(i915) \
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
> -#define IS_ADLP_RPLP(i915) \
> +#define IS_ALDERLAKE_P_RPLP(i915) \
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
> #define IS_ADLP_RPLU(i915) \
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index 8a9ff6227e53..10d86c525beb 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -195,7 +195,7 @@ void intel_step_init(struct drm_i915_private *i915)
> } else if (IS_ADLP_N(i915)) {
> revids = adlp_n_revids;
> size = ARRAY_SIZE(adlp_n_revids);
> - } else if (IS_ADLP_RPLP(i915)) {
> + } else if (IS_ALDERLAKE_P_RPLP(i915)) {
> revids = adlp_rplp_revids;
> size = ARRAY_SIZE(adlp_rplp_revids);
> } else if (IS_ALDERLAKE_P(i915)) {
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
On Tue, 30 May 2023, Anusha Srivatsa wrote:
> Driver refers to the platfrom Alderlake P as ADLP in places
> and ALDERLAKE_P in some. Making the consistent change
> to avoid confusion of the right naming convention for
> the platform.
$ git grep "#define IS_.*_DISPLAY_STEP" -- drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_drv.h:#define IS_KBL_DISPLAY_STEP(i915, since, until)
\
drivers/gpu/drm/i915/i915_drv.h:#define IS_JSL_EHL_DISPLAY_STEP(p, since,
until) \
drivers/gpu/drm/i915/i915_drv.h:#define IS_TGL_DISPLAY_STEP(__i915, since,
until) \
drivers/gpu/drm/i915/i915_drv.h:#define IS_RKL_DISPLAY_STEP(p, since, until) \
drivers/gpu/drm/i915/i915_drv.h:#define IS_ADLS_DISPLAY_STEP(__i915, since,
until) \
drivers/gpu/drm/i915/i915_drv.h:#define IS_ADLP_DISPLAY_STEP(__i915, since,
until) \
drivers/gpu/drm/i915/i915_drv.h:#define IS_MTL_DISPLAY_STEP(__i915, since,
until) \
drivers/gpu/drm/i915/i915_drv.h:#define IS_DG2_DISPLAY_STEP(__i915, since,
until) \
They all use the acronym. Do you suggest to rename all of them, or just
ADL-P?
BR,
Jani.
>
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 8
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h| 4 ++--
> 5 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 6bed75f1541a..013678caaca8 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3541,7 +3541,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
> *dev_priv)
> } else if (IS_ALDERLAKE_P(dev_priv)) {
> dev_priv->display.funcs.cdclk = _cdclk_funcs;
> /* Wa_22011320316:adl-p[a0] */
> - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
> else if (IS_ADLP_RPLU(dev_priv))
> dev_priv->display.cdclk.table = rplu_cdclk_table;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 6b2d8a1e2aa9..81f3ce5a0a1e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct
> drm_i915_private *i915, struct inte
> {
> u32 val;
>
> - if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
> + if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
> pll->info->id != DPLL_ID_ICL_DPLL0)
> return;
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index ea0389c5f656..c25457dae315 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -639,7 +639,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> }
>
> /* Wa_22012278275:adl-p */
> - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
> + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
> static const u8 map[] = {
> 2, /* 5 lines */
> 1, /* 6 lines */
> @@ -807,7 +807,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp
> *intel_dp,
> return;
>
> /* Wa_16011303918:adl-p */
> - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> return;
>
> /*
> @@ -975,7 +975,7 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> return false;
> }
>
> - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> drm_dbg_kms(_priv->drm, "PSR2 not completely functional in
> this stepping\n");
> return false;
> }
> @@ -1033,7 +1033,7 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
>
> /* Wa_16011303918:adl-p */
> if (crtc_state->vrr.enable &&
> - IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> + IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> drm_dbg_kms(_priv->drm,
> "PSR2 not enabled, not compatible with HW stepping
> + VRR\n");
> return false;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 36070d86550f..2019e0a87bd3 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++
Re: [Intel-gfx] [PATCH v15 0/1] drm/i915: Allow user to set cache at BO creation
> On 05/06/2023 09:53, Tvrtko Ursulin wrote:
>> On 31/05/2023 18:10, fei.y...@intel.com wrote:
>>> From: Fei Yang
>>>
>>> This series introduce a new extension for GEM_CREATE,
>>> 1. end support for set caching ioctl [PATCH 1/2]
>>> 2. add set_pat extension for gem_create [PATCH 2/2]
>>>
>>> v2: drop one patch that was merged separately
>>> commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
>>> v3: rebased on https://patchwork.freedesktop.org/series/117082/
>>> v4: fix missing unlock introduced in v3, and
>>> solve a rebase conflict
>>> v5: replace obj->cache_level with pat_set_by_user,
>>> fix i915_cache_level_str() for legacy platforms.
>>> v6: rebased on https://patchwork.freedesktop.org/series/117480/
>>> v7: rebased on https://patchwork.freedesktop.org/series/117528/
>>> v8: dropped the two dependent patches that has been merged
>>> separately. Add IGT link and Tested-by (MESA).
>>> v9: addressing comments (Andi)
>>> v10: acked-by and tested-by MESA
>>> v11: drop "end support for set caching ioctl" (merged)
>>> remove tools/include/uapi/drm/i915_drm.h
>>> v12: drop Bspec reference in comment. add to commit message instead
>>> v13: sent to test with igt@gem_create@create-ext-set-pat
>>> v14: sent to test with igt@gem_create@create-ext-set-pat
>>> v15: update commit message with documentation note and t-b/a-b from
>>> Media driver folks.
>>>
>>> Fei Yang (1):
>>>drm/i915: Allow user to set cache at BO creation
>>>
>>> drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++
>>> drivers/gpu/drm/i915/gem/i915_gem_object.c | 6
>>> include/uapi/drm/i915_drm.h| 41 ++
>>> 3 files changed, 83 insertions(+)
>>>
>>
>> Try with:
>>
>> Test-with: 20230526172221.1438998-1-fei.y...@intel.com
>>
>> That is how it is supposed to be done, to do a CI run against a test
>> case not yet merged that is.
Yes, the result can be found at https://patchwork.freedesktop.org/series/116870/
, under rev14, expand Fi.CI.IGT, you would see,
New IGT tests (1)
igt@gem_create@create-ext-set-pat:
Statuses : 6 pass(s)
Exec time: [0.0] s
> Or I see that IGT has been since merged so you probably have results
> already?
Seems like the last update ran into some random failure which caused CI to stop.
> Regards,
>
> Tvrtko
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: implement internal workqueues (rev3)
On Wed, 31 May 2023, Patchwork wrote: > Possible regressions > > * igt@gem_close_race@basic-process: > - fi-blb-e6850: [PASS][1] -> [ABORT][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/fi-blb-e6850/igt@gem_close_r...@basic-process.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/fi-blb-e6850/igt@gem_close_r...@basic-process.html > - fi-hsw-4770:[PASS][3] -> [ABORT][4] >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/fi-hsw-4770/igt@gem_close_r...@basic-process.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/fi-hsw-4770/igt@gem_close_r...@basic-process.html > - fi-elk-e7500: [PASS][5] -> [ABORT][6] >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/fi-elk-e7500/igt@gem_close_r...@basic-process.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/fi-elk-e7500/igt@gem_close_r...@basic-process.html > > * igt@i915_selftest@live@evict: > - bat-adlp-9: [PASS][7] -> [ABORT][8] >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-adlp-9/igt@i915_selftest@l...@evict.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-adlp-9/igt@i915_selftest@l...@evict.html > - bat-rpls-2: [PASS][9] -> [ABORT][10] >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-rpls-2/igt@i915_selftest@l...@evict.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-rpls-2/igt@i915_selftest@l...@evict.html > - bat-adlm-1: [PASS][11] -> [ABORT][12] >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-adlm-1/igt@i915_selftest@l...@evict.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-adlm-1/igt@i915_selftest@l...@evict.html > - bat-rpls-1: [PASS][13] -> [ABORT][14] >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-rpls-1/igt@i915_selftest@l...@evict.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-rpls-1/igt@i915_selftest@l...@evict.html This still fails consistently, I have no clue why, and the above aren't even remotely related to display. What now? Tvrtko? BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v15 0/1] drm/i915: Allow user to set cache at BO creation
On Mon, Jun 05, 2023 at 10:16:22AM +0100, Tvrtko Ursulin wrote:
>
> On 05/06/2023 09:53, Tvrtko Ursulin wrote:
> >
> > On 31/05/2023 18:10, fei.y...@intel.com wrote:
> > > From: Fei Yang
> > >
> > > This series introduce a new extension for GEM_CREATE,
> > > 1. end support for set caching ioctl [PATCH 1/2]
> > > 2. add set_pat extension for gem_create [PATCH 2/2]
> > >
> > > v2: drop one patch that was merged separately
> > > commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
> > > v3: rebased on https://patchwork.freedesktop.org/series/117082/
> > > v4: fix missing unlock introduced in v3, and
> > > solve a rebase conflict
> > > v5: replace obj->cache_level with pat_set_by_user,
> > > fix i915_cache_level_str() for legacy platforms.
> > > v6: rebased on https://patchwork.freedesktop.org/series/117480/
> > > v7: rebased on https://patchwork.freedesktop.org/series/117528/
> > > v8: dropped the two dependent patches that has been merged
> > > separately. Add IGT link and Tested-by (MESA).
> > > v9: addressing comments (Andi)
> > > v10: acked-by and tested-by MESA
> > > v11: drop "end support for set caching ioctl" (merged)
> > > remove tools/include/uapi/drm/i915_drm.h
> > > v12: drop Bspec reference in comment. add to commit message instead
> > > v13: sent to test with igt@gem_create@create-ext-set-pat
> > > v14: sent to test with igt@gem_create@create-ext-set-pat
> > > v15: update commit message with documentation note and t-b/a-b from
> > > Media driver folks.
> > >
> > > Fei Yang (1):
> > > drm/i915: Allow user to set cache at BO creation
> > >
> > > drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++
> > > drivers/gpu/drm/i915/gem/i915_gem_object.c | 6
> > > include/uapi/drm/i915_drm.h | 41 ++
> > > 3 files changed, 83 insertions(+)
> > >
> >
> > Try with:
> >
> > Test-with: 20230526172221.1438998-1-fei.y...@intel.com
> >
> > That is how it is supposed to be done, to do a CI run against a test
> > case not yet merged that is.
>
> Or I see that IGT has been since merged so you probably have results
> already?
CI has stopped somewhere in the BAT tests. Can anyone hit the
"Test revision 1 again" button? Fei, would you?
We had it tested some revisions back, though.
Andi
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT (rev2)
== Series Details == Series: drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT (rev2) URL : https://patchwork.freedesktop.org/series/118672/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13224_full -> Patchwork_118672v2_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_118672v2_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_118672v2_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (7 -> 7) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_118672v2_full: ### IGT changes ### Possible regressions * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: - shard-glk: [PASS][1] -> [TIMEOUT][2] +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13224/shard-glk7/igt@kms_cursor_leg...@2x-flip-vs-cursor-legacy.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v2/shard-glk9/igt@kms_cursor_leg...@2x-flip-vs-cursor-legacy.html * igt@prime_vgem@wait: - shard-glk: NOTRUN -> [TIMEOUT][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v2/shard-glk9/igt@prime_v...@wait.html Warnings * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip: - shard-glk: [SKIP][4] ([fdo#109271]) -> [TIMEOUT][5] +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13224/shard-glk7/igt@kms_big...@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v2/shard-glk9/igt@kms_big...@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html * igt@kms_hdr@bpc-switch: - shard-glk: [SKIP][6] ([fdo#109271] / [i915#4579]) -> [TIMEOUT][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13224/shard-glk7/igt@kms_...@bpc-switch.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v2/shard-glk9/igt@kms_...@bpc-switch.html Known issues Here are the changes found in Patchwork_118672v2_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fair@basic-pace@rcs0: - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13224/shard-glk4/igt@gem_exec_fair@basic-p...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v2/shard-glk8/igt@gem_exec_fair@basic-p...@rcs0.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a: - shard-glk: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1937] / [i915#4579]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v2/shard-glk3/igt@i915_pm_lpsp@kms-l...@kms-lpsp-hdmi-a.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-vga: - shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4579]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v2/shard-snb4/igt@i915_pm_lpsp@kms-l...@kms-lpsp-vga.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-2: - shard-glk: [PASS][12] -> [FAIL][13] ([i915#2521]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13224/shard-glk8/igt@kms_async_flips@alternate-sync-async-f...@pipe-a-hdmi-a-2.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v2/shard-glk4/igt@kms_async_flips@alternate-sync-async-f...@pipe-a-hdmi-a-2.html * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#3886]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v2/shard-glk3/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@ac-hdmi-a1-hdmi-a2: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#407]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13224/shard-glk7/igt@kms_flip@2x-dpms-vs-vblank-race-interrupti...@ac-hdmi-a1-hdmi-a2.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v2/shard-glk9/igt@kms_flip@2x-dpms-vs-vblank-race-interrupti...@ac-hdmi-a1-hdmi-a2.html * igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#79]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13224/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vbl...@ab-hdmi-a1-hdmi-a2.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v2/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vbl...@ab-hdmi-a1-hdmi-a2.html *
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Add some missing error propagation
On 05/06/2023 14:43, Dan Carpenter wrote:
On Mon, Jun 05, 2023 at 02:11:35PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Add some missing error propagation in live_parallel_switch.
To avoid needlessly burdening the various backport processes, note I am
not marking it as a fix against any patches and not copying stable since
it is debug/selftests only code.
This patch is unlikely to make a difference in real life, but I don't
think avoiding Fixes tags and backports is the right thing.
I would add a Fixes tag and not add a stable tag.
The real burden with Fixes tags is if it breaks someone's system. But
if it's breaking selftests then hopefully those are the people best
able to deal with it.
Fixes tags are different from stable tags. If the code is very recent
then the fixes tag can automatically allow us to filter out that patch
from going back to stable. So for new patches Fixes is the opposite of
CC'ing stable.
If the bug is old, then adding a Fixes tag does increase the chance of a
backport though, that's true.
My guess is that if the stable maintainers thought that selftests/ were
causing too much issue with backports they would add a grep line to
their scripts to solve that problem. Instead we were having the
opposite discussion the other week where the bpf people didn't want to
backport selftest stuff and Greg wanted to.
I just don't see the benefit since to my knowledge no one outside our CI
systems runs selftests. And this implies mostly the current development kernel
is tested. So backporting is irrelevant.
Even with just the Fixes: tags the internal tooling will be picking the patches
up during the -rc phase and even that can cause conflicts and some mental load
to maintainers.
Granted, *if* patch truly is a fix for a selftest failure which can actually
happen then it is useful to pick it up for the -rc window. Although that feels
extremely rare, otherwise it would have been spotted much before.
In any case, I struggle to make myself interested into Fixes: tag for
"impossible" selftests failures.
But I can also put them in, 99% of time is not a big deal:
Fixes: 50d16d44cce4 ("drm/i915/selftests: Exercise context switching in
parallel")
Fixes: 6407cf533217 ("drm/i915/selftests: Stop using kthread_stop()")
Stable is even worse since to handle them the pointless workload is even
bigger. But if stable wants everything sure, we can send everything. :)
Cc: # v5.5+
As long as it is accepted that it is unlikely no one will bother to create
conflict free backports for all kernels where those don't apply.
Regards,
Tvrtko
https://lore.kernel.org/all/2023052647-tacking-wince-85c5@gregkh/
regards,
dan carpenter
[Intel-gfx] [PATCH] drm/i915: Implement fdinfo memory stats printing
From: Tvrtko Ursulin
Use the newly added drm_print_memory_stats helper to show memory
utilisation of our objects in drm/driver specific fdinfo output.
To collect the stats we walk the per memory regions object lists
and accumulate object size into the respective drm_memory_stats
categories.
Objects with multiple possible placements are reported in multiple
regions for total and shared sizes, while other categories are
counted only for the currently active region.
Signed-off-by: Tvrtko Ursulin
Cc: Rob Clark
---
drivers/gpu/drm/i915/i915_drm_client.c | 66 ++
1 file changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c
b/drivers/gpu/drm/i915/i915_drm_client.c
index 2a44b3876cb5..2a40f763f8f6 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -41,6 +41,70 @@ void __i915_drm_client_free(struct kref *kref)
}
#ifdef CONFIG_PROC_FS
+static void
+add_obj_meminfo(struct drm_i915_gem_object *obj,
+ struct intel_memory_region *mr,
+ struct drm_memory_stats stats[INTEL_REGION_UNKNOWN])
+{
+ u64 sz = obj->base.size;
+ enum intel_region_id id;
+ unsigned int i;
+
+ id = mr->id;
+ if (obj->base.handle_count > 1)
+ stats[id].shared += sz;
+ else
+ stats[id].private += sz;
+
+ if (i915_gem_object_has_pages(obj)) {
+ stats[id].resident += sz;
+
+ if (!dma_resv_test_signaled(obj->base.resv,
+ dma_resv_usage_rw(true)))
+ stats[id].active += sz;
+ else if (i915_gem_object_is_shrinkable(obj) &&
+obj->mm.madv == I915_MADV_DONTNEED)
+ stats[id].purgeable += sz;
+ }
+
+ /* Attribute size and shared to all possible object memory regions. */
+ for (i = 0; i < obj->mm.n_placements; i++) {
+ if (obj->mm.placements[i] == mr)
+ continue;
+
+ id = obj->mm.placements[i]->id;
+ if (obj->base.handle_count > 1)
+ stats[id].shared += sz;
+ else
+ stats[id].private += sz;
+ }
+}
+
+static void show_meminfo(struct drm_printer *p, struct drm_file *file)
+{
+ struct drm_i915_file_private *file_priv = file->driver_priv;
+ struct drm_memory_stats stats[INTEL_REGION_UNKNOWN] = {};
+ struct drm_i915_private *i915 = file_priv->i915;
+ struct intel_memory_region *mr;
+ unsigned int id;
+
+ for_each_memory_region(mr, i915, id) {
+ struct drm_i915_gem_object *obj;
+
+ mutex_lock(>objects.lock);
+ list_for_each_entry(obj, >objects.list, mm.region_link)
+ add_obj_meminfo(obj, mr, stats);
+ mutex_unlock(>objects.lock);
+ }
+
+ for_each_memory_region(mr, i915, id)
+ drm_print_memory_stats(p,
+ [id],
+ DRM_GEM_OBJECT_RESIDENT |
+ DRM_GEM_OBJECT_PURGEABLE,
+ mr->name);
+}
+
static const char * const uabi_class_names[] = {
[I915_ENGINE_CLASS_RENDER] = "render",
[I915_ENGINE_CLASS_COPY] = "copy",
@@ -102,6 +166,8 @@ void i915_drm_client_fdinfo(struct drm_printer *p, struct
drm_file *file)
* **
*/
+ show_meminfo(p, file);
+
if (GRAPHICS_VER(i915) < 8)
return;
--
2.39.2
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gvt: remove unused variable gma_bottom in command parser (rev2)
On Fri, 02 Jun 2023, Jani Nikula wrote: > On Wed, 31 May 2023, Patchwork wrote: >> == Series Details == >> >> Series: drm/i915/gvt: remove unused variable gma_bottom in command parser >> (rev2) >> URL : https://patchwork.freedesktop.org/series/118512/ >> State : warning >> >> == Summary == >> >> Error: dim checkpatch failed >> c6878ab01be9 drm/i915/gvt: remove unused variable gma_bottom in command >> parser >> -:63: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address >> mismatch: 'From: Zhi Wang ' != 'Signed-off-by: Zhi >> Wang ' > > I can fix this while applying, but please indicate whether you intended > to have From: Zhi Wang or Signed-off-by: Zhi Wang > . Ping. I can't apply this with this warning, and I can't fix Signed-off-by unless you tell me what to do. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PULL] drm-intel-next
Hi Dave & Daniel - Due to miscommunication (mea culpa) there was no earlier drm-intel-next pull request for v6.5, so this is the first one and therefore quite big. Sorry about that. (But hey, if there's going to be another pull request, it'll be tiny! ;) This round, Meteorlake display enabling stands out, although it's just one line in the summary below. Thanks to Mika, Radhakrishna, José, Ankit, Clint, Gustavo, Imre, Anusha, Juha-Pekka, and Matt for a ton of MTL enabling patches. BR, Jani. drm-intel-next-2023-06-05: drm/i915 features for v6.5: Features and functionality: - Meteorlake (MTL) display enabling (Mika, Radhakrishna, José, Ankit, Clint, Gustavo, Imre, Anusha, Juha-Pekka, Matt) - Allow VRR to be toggled during fastsets (Ville) - Allow arbitrary refresh rates with VRR eDP panels (Ville) - Support async flips on linear buffers on display ver 12+ (Arun) - New debugfs for display clock frequencies (Bhanuprakash) - Taint kernel when force probing unsupported devices (Jani) - Expose CRTC CTM property on ILK/SNB/VLV (Ville) DRM subsystem changes: - EDID changes to support further conversion to struct drm_edid (Jani) - Move i915 DSC parameter code to common DRM helpers (Dmitry Baryshkov) Refactoring and cleanups: - CSC color refactoring (Ville) - VRR cleanups (Ville) - Finish i915 conversion to struct drm_edid (Jani) - Start high level display driver file (Jani) - Hotplug refactoring (Ville) - Misc display refactoring and cleanups (Jani, Ville) - Use device based logging for state checker warnings (Jani) - Split out hotplug and display irq handling (Jani) - Move display device info and probe under display/ (Matt) - HDCP cleanups (Suraj) - Use localized warning ignores instead of per file (Jani) - Remove superfluous enum i915_drm_suspend_mode (Maarten) - PSR, pfit, scaler and chicken register definition cleanups (Ville) - Constify pointers to hwmon_channel_info (Krzysztof Kozlowski) - Replace all non-returning strlcpy with strscpy (Azeem Shaikh) - Refactor VBT aux channel and DDC pin mapping (Ville) - Include cleanups (Jani) Fixes: - Fix modeset locking issue in DP MST HDCP (Suraj) - Fix disconnected Type-C/DP-alt disable at probe (Imre) - Fix HDMI PCON DSC usage and color conversions (Ankit) - Fix g4x HDMI infoframe/audio transmission port usage (Ville) - Avoid use-after-free when DP connector init fails (Maarten) - Fix voltage level for 480 MHz CDCLK (Chaitanya) - Check HPD live state during eDP probe (Ville) - Fix active port PLL selection for secondary MST streams (Imre) - Check pipe source size when using SKL+ scalers (Ville) - Fix MIPI DSI sleep sequences (Hans de Goede) - Fix DPCD register write order to match 128b/132b requirement (Arun) - Increase AUX timeout for Type-C (Suraj) - Communicate display power demands to pcode (Stan) - Fix potential division by zero in DSC compute config (Nikita Zhandarovich) - Fix fast wake AUX sync length (Jouni) - Fix potential oops on intel_get_crtc_new_encoder() (Ville) Merges: - drm-next backmerges (Rodrigo, Jani) BR, Jani. The following changes since commit 85d712f033d23bb56a373e29465470c036532d46: Merge tag 'drm-intel-gt-next-2023-05-24' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2023-05-29 06:21:51 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2023-06-05 for you to fetch changes up to 619a06dba6fa38de1b85c09ac74bb8aa2449ce0c: drm/i915/mtl: Reset only one lane in case of MFD (2023-06-05 12:35:29 +0300) drm/i915 features for v6.5: Features and functionality: - Meteorlake (MTL) display enabling (Mika, Radhakrishna, José, Ankit, Clint, Gustavo, Imre, Anusha, Juha-Pekka, Matt) - Allow VRR to be toggled during fastsets (Ville) - Allow arbitrary refresh rates with VRR eDP panels (Ville) - Support async flips on linear buffers on display ver 12+ (Arun) - New debugfs for display clock frequencies (Bhanuprakash) - Taint kernel when force probing unsupported devices (Jani) - Expose CRTC CTM property on ILK/SNB/VLV (Ville) DRM subsystem changes: - EDID changes to support further conversion to struct drm_edid (Jani) - Move i915 DSC parameter code to common DRM helpers (Dmitry Baryshkov) Refactoring and cleanups: - CSC color refactoring (Ville) - VRR cleanups (Ville) - Finish i915 conversion to struct drm_edid (Jani) - Start high level display driver file (Jani) - Hotplug refactoring (Ville) - Misc display refactoring and cleanups (Jani, Ville) - Use device based logging for state checker warnings (Jani) - Split out hotplug and display irq handling (Jani) - Move display device info and probe under display/ (Matt) - HDCP cleanups (Suraj) - Use localized warning ignores instead of per file (Jani) - Remove superfluous enum i915_drm_suspend_mode (Maarten) - PSR, pfit, scaler and chicken register definition cleanups (Ville) - Constify pointers to hwmon_channel_info (Krzysztof Kozlowski) -
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Add some missing error propagation
Hi Tvrtko,
> Add some missing error propagation in live_parallel_switch.
>
> To avoid needlessly burdening the various backport processes, note I am
> not marking it as a fix against any patches and not copying stable since
> it is debug/selftests only code.
which I did :/
But I guess you are right and it's not necessary.
> Signed-off-by: Tvrtko Ursulin
> Reported-by: Dan Carpenter
> Cc: Andi Shyti
> ---
> .../gpu/drm/i915/gem/selftests/i915_gem_context.c | 14 ++
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> index ad6a3b2fb387..7021b6e9b219 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> @@ -348,8 +348,10 @@ static int live_parallel_switch(void *arg)
> continue;
>
> ce = intel_context_create(data[m].ce[0]->engine);
> - if (IS_ERR(ce))
> + if (IS_ERR(ce)) {
> + err = PTR_ERR(ce);
> goto out;
> + }
>
> err = intel_context_pin(ce);
> if (err) {
> @@ -369,8 +371,10 @@ static int live_parallel_switch(void *arg)
>
> worker = kthread_create_worker(0, "igt/parallel:%s",
> data[n].ce[0]->engine->name);
> - if (IS_ERR(worker))
> + if (IS_ERR(worker)) {
> + err = PTR_ERR(worker);
> goto out;
> + }
>
> data[n].worker = worker;
> }
> @@ -399,8 +403,10 @@ static int live_parallel_switch(void *arg)
> }
> }
>
> - if (igt_live_test_end())
> - err = -EIO;
> + if (igt_live_test_end()) {
> + err = err ?: -EIO;
Nice catch!
Reviewed-by: Andi Shyti
Andi
> + break;
> + }
> }
>
> out:
> --
> 2.39.2
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Add some missing error propagation
On Mon, Jun 05, 2023 at 02:11:35PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Add some missing error propagation in live_parallel_switch. > > To avoid needlessly burdening the various backport processes, note I am > not marking it as a fix against any patches and not copying stable since > it is debug/selftests only code. > This patch is unlikely to make a difference in real life, but I don't think avoiding Fixes tags and backports is the right thing. I would add a Fixes tag and not add a stable tag. The real burden with Fixes tags is if it breaks someone's system. But if it's breaking selftests then hopefully those are the people best able to deal with it. Fixes tags are different from stable tags. If the code is very recent then the fixes tag can automatically allow us to filter out that patch from going back to stable. So for new patches Fixes is the opposite of CC'ing stable. If the bug is old, then adding a Fixes tag does increase the chance of a backport though, that's true. My guess is that if the stable maintainers thought that selftests/ were causing too much issue with backports they would add a grep line to their scripts to solve that problem. Instead we were having the opposite discussion the other week where the bpf people didn't want to backport selftest stuff and Greg wanted to. https://lore.kernel.org/all/2023052647-tacking-wince-85c5@gregkh/ regards, dan carpenter
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use the fdinfo helper
== Series Details ==
Series: drm/i915: Use the fdinfo helper
URL : https://patchwork.freedesktop.org/series/118864/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13228 -> Patchwork_118864v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118864v1/index.html
Participating hosts (37 -> 36)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_118864v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_backlight@basic-brightness@edp-1:
- bat-rplp-1: NOTRUN -> [ABORT][1] ([i915#7077])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118864v1/bat-rplp-1/igt@i915_pm_backlight@basic-brightn...@edp-1.html
* igt@i915_selftest@live@workarounds:
- bat-rpls-1: [PASS][2] -> [DMESG-FAIL][3] ([i915#6763])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13228/bat-rpls-1/igt@i915_selftest@l...@workarounds.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118864v1/bat-rpls-1/igt@i915_selftest@l...@workarounds.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1:
- bat-dg2-8: [PASS][4] -> [FAIL][5] ([i915#7932])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13228/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118864v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: NOTRUN -> [SKIP][6] ([i915#3555] / [i915#4579])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118864v1/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [DMESG-WARN][7] ([i915#7699]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13228/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118864v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1:
- bat-dg2-8: [FAIL][9] ([i915#7932]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13228/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118864v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
Warnings
* igt@kms_psr@primary_mmap_gtt:
- bat-rplp-1: [ABORT][11] ([i915#8442]) -> [SKIP][12] ([i915#1072])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13228/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118864v1/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6763]: https://gitlab.freedesktop.org/drm/intel/issues/6763
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
Build changes
-
* Linux: CI_DRM_13228 -> Patchwork_118864v1
CI-20190529: 20190529
CI_DRM_13228: e1c7a0f8d1ad2af33f6c71852b9f2d85a7db32ac @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7318: c2d8ef8b9397d0976959f29dc1dd7c8a698d65fe @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_118864v1: e1c7a0f8d1ad2af33f6c71852b9f2d85a7db32ac @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
e689bd83bfdc drm/i915: Use the fdinfo helper
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118864v1/index.html
[Intel-gfx] [PATCH] drm/i915/selftests: Add some missing error propagation
From: Tvrtko Ursulin
Add some missing error propagation in live_parallel_switch.
To avoid needlessly burdening the various backport processes, note I am
not marking it as a fix against any patches and not copying stable since
it is debug/selftests only code.
Signed-off-by: Tvrtko Ursulin
Reported-by: Dan Carpenter
Cc: Andi Shyti
---
.../gpu/drm/i915/gem/selftests/i915_gem_context.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index ad6a3b2fb387..7021b6e9b219 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -348,8 +348,10 @@ static int live_parallel_switch(void *arg)
continue;
ce = intel_context_create(data[m].ce[0]->engine);
- if (IS_ERR(ce))
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
goto out;
+ }
err = intel_context_pin(ce);
if (err) {
@@ -369,8 +371,10 @@ static int live_parallel_switch(void *arg)
worker = kthread_create_worker(0, "igt/parallel:%s",
data[n].ce[0]->engine->name);
- if (IS_ERR(worker))
+ if (IS_ERR(worker)) {
+ err = PTR_ERR(worker);
goto out;
+ }
data[n].worker = worker;
}
@@ -399,8 +403,10 @@ static int live_parallel_switch(void *arg)
}
}
- if (igt_live_test_end())
- err = -EIO;
+ if (igt_live_test_end()) {
+ err = err ?: -EIO;
+ break;
+ }
}
out:
--
2.39.2
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Use the fdinfo helper
== Series Details == Series: drm/i915: Use the fdinfo helper URL : https://patchwork.freedesktop.org/series/118864/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915: Move setting of rps thresholds to init
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Move setting of rps thresholds
to init
URL : https://patchwork.freedesktop.org/series/118856/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13228 -> Patchwork_118856v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118856v1/index.html
Participating hosts (37 -> 36)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_118856v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_backlight@basic-brightness@edp-1:
- bat-rplp-1: NOTRUN -> [ABORT][1] ([i915#7077])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118856v1/bat-rplp-1/igt@i915_pm_backlight@basic-brightn...@edp-1.html
* igt@i915_selftest@live@guc:
- bat-rpls-2: [PASS][2] -> [DMESG-WARN][3] ([i915#7852])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13228/bat-rpls-2/igt@i915_selftest@l...@guc.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118856v1/bat-rpls-2/igt@i915_selftest@l...@guc.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: [PASS][4] -> [ABORT][5] ([i915#4983] / [i915#7461] /
[i915#8347] / [i915#8384])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13228/bat-rpls-1/igt@i915_selftest@l...@reset.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118856v1/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#1845] / [i915#5354]) +1
similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118856v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1:
- bat-dg2-8: [PASS][7] -> [FAIL][8] ([i915#7932])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13228/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118856v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: NOTRUN -> [SKIP][9] ([i915#3555] / [i915#4579])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118856v1/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [DMESG-WARN][10] ([i915#7699]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13228/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118856v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1:
- bat-dg2-8: [FAIL][12] ([i915#7932]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13228/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118856v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
Warnings
* igt@kms_psr@primary_mmap_gtt:
- bat-rplp-1: [ABORT][14] ([i915#8442]) -> [SKIP][15] ([i915#1072])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13228/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118856v1/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7852]: https://gitlab.freedesktop.org/drm/intel/issues/7852
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
[i915#8497]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/4] drm/i915: Move setting of rps thresholds to init
== Series Details == Series: series starting with [CI,1/4] drm/i915: Move setting of rps thresholds to init URL : https://patchwork.freedesktop.org/series/118856/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/4] drm/i915: Move setting of rps thresholds to init
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Move setting of rps thresholds
to init
URL : https://patchwork.freedesktop.org/series/118856/
State : warning
== Summary ==
Error: dim checkpatch failed
6ddf054e3527 drm/i915: Move setting of rps thresholds to init
-:6: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 36d516be867c ("drm/i915/gt:
Switch to manual evaluation of RPS")'
#6:
Since 36d516be867c ("drm/i915/gt: Switch to manual evaluation of RPS")
total: 1 errors, 0 warnings, 0 checks, 73 lines checked
332fd33b850a drm/i915: Record default rps threshold values
24378f56b579 drm/i915: Add helpers for managing rps thresholds
d57aea8a9e29 drm/i915: Expose RPS thresholds in sysfs
[Intel-gfx] [PATCH] drm/i915: Use the fdinfo helper
From: Tvrtko Ursulin
Use the common fdinfo helper for printing the basics. Remove now unused
client id allocation code.
Signed-off-by: Tvrtko Ursulin
Cc: Rob Clark
---
drivers/gpu/drm/i915/i915_driver.c | 6 +--
drivers/gpu/drm/i915/i915_drm_client.c | 65 --
drivers/gpu/drm/i915/i915_drm_client.h | 22 ++---
drivers/gpu/drm/i915/i915_drv.h| 2 -
drivers/gpu/drm/i915/i915_gem.c| 6 +--
5 files changed, 18 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index 8e92649124d4..97244541ec28 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -243,8 +243,6 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
if (ret < 0)
goto err_rootgt;
- i915_drm_clients_init(_priv->clients, dev_priv);
-
i915_gem_init_early(dev_priv);
/* This must be called before any calls to HAS_PCH_* */
@@ -278,7 +276,6 @@ static void i915_driver_late_release(struct
drm_i915_private *dev_priv)
intel_power_domains_cleanup(dev_priv);
i915_gem_cleanup_early(dev_priv);
intel_gt_driver_late_release_all(dev_priv);
- i915_drm_clients_fini(_priv->clients);
intel_region_ttm_device_fini(dev_priv);
vlv_suspend_cleanup(dev_priv);
i915_workqueues_cleanup(dev_priv);
@@ -1706,7 +1703,7 @@ static const struct file_operations i915_driver_fops = {
.compat_ioctl = i915_ioc32_compat_ioctl,
.llseek = noop_llseek,
#ifdef CONFIG_PROC_FS
- .show_fdinfo = i915_drm_client_fdinfo,
+ .show_fdinfo = drm_show_fdinfo,
#endif
};
@@ -1806,6 +1803,7 @@ static const struct drm_driver i915_drm_driver = {
.open = i915_driver_open,
.lastclose = i915_driver_lastclose,
.postclose = i915_driver_postclose,
+ .show_fdinfo = i915_drm_client_fdinfo,
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c
b/drivers/gpu/drm/i915/i915_drm_client.c
index d18d0a3ed905..2a44b3876cb5 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -17,64 +17,29 @@
#include "i915_gem.h"
#include "i915_utils.h"
-void i915_drm_clients_init(struct i915_drm_clients *clients,
- struct drm_i915_private *i915)
-{
- clients->i915 = i915;
- clients->next_id = 0;
-
- xa_init_flags(>xarray, XA_FLAGS_ALLOC | XA_FLAGS_LOCK_IRQ);
-}
-
-struct i915_drm_client *i915_drm_client_add(struct i915_drm_clients *clients)
+struct i915_drm_client *i915_drm_client_alloc(void)
{
struct i915_drm_client *client;
- struct xarray *xa = >xarray;
- int ret;
client = kzalloc(sizeof(*client), GFP_KERNEL);
if (!client)
- return ERR_PTR(-ENOMEM);
-
- xa_lock_irq(xa);
- ret = __xa_alloc_cyclic(xa, >id, client, xa_limit_32b,
- >next_id, GFP_KERNEL);
- xa_unlock_irq(xa);
- if (ret < 0)
- goto err;
+ return NULL;
kref_init(>kref);
spin_lock_init(>ctx_lock);
INIT_LIST_HEAD(>ctx_list);
- client->clients = clients;
return client;
-
-err:
- kfree(client);
-
- return ERR_PTR(ret);
}
void __i915_drm_client_free(struct kref *kref)
{
struct i915_drm_client *client =
container_of(kref, typeof(*client), kref);
- struct xarray *xa = >clients->xarray;
- unsigned long flags;
- xa_lock_irqsave(xa, flags);
- __xa_erase(xa, client->id);
- xa_unlock_irqrestore(xa, flags);
kfree(client);
}
-void i915_drm_clients_fini(struct i915_drm_clients *clients)
-{
- GEM_BUG_ON(!xa_empty(>xarray));
- xa_destroy(>xarray);
-}
-
#ifdef CONFIG_PROC_FS
static const char * const uabi_class_names[] = {
[I915_ENGINE_CLASS_RENDER] = "render",
@@ -101,38 +66,34 @@ static u64 busy_add(struct i915_gem_context *ctx, unsigned
int class)
}
static void
-show_client_class(struct seq_file *m,
+show_client_class(struct drm_printer *p,
+ struct drm_i915_private *i915,
struct i915_drm_client *client,
unsigned int class)
{
- const struct list_head *list = >ctx_list;
+ const unsigned int capacity = i915->engine_uabi_class_count[class];
u64 total = atomic64_read(>past_runtime[class]);
- const unsigned int capacity =
- client->clients->i915->engine_uabi_class_count[class];
struct i915_gem_context *ctx;
rcu_read_lock();
- list_for_each_entry_rcu(ctx, list, client_link)
+ list_for_each_entry_rcu(ctx, >ctx_list, client_link)
total += busy_add(ctx, class);
rcu_read_unlock();
if (capacity)
-
[Intel-gfx] ✓ Fi.CI.IGT: success for Avoid reading OA reports before they land
== Series Details ==
Series: Avoid reading OA reports before they land
URL : https://patchwork.freedesktop.org/series/118802/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13223_full -> Patchwork_118802v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_118802v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@idempotent:
- shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118802v1/shard-snb6/igt@gem_ctx_persiste...@idempotent.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][2] -> [ABORT][3] ([i915#5566])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13223/shard-glk9/igt@gen9_exec_pa...@allowed-single.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118802v1/shard-glk1/igt@gen9_exec_pa...@allowed-single.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-vga:
- shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4579]) +13
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118802v1/shard-snb2/igt@i915_pm_lpsp@kms-l...@kms-lpsp-vga.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271]) +79 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118802v1/shard-snb6/igt@kms_big...@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3886])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118802v1/shard-apl4/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][7] ([fdo#109271]) +4 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118802v1/shard-apl4/igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_vrr@flipline:
- shard-apl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4579])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118802v1/shard-apl4/igt@kms_...@flipline.html
Possible fixes
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[FAIL][9] ([i915#7742]) -> [PASS][10] +1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13223/shard-rkl-7/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118802v1/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
* igt@gem_eio@unwedge-stress:
- {shard-dg1}:[FAIL][11] ([i915#5784]) -> [PASS][12] +1 similar
issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13223/shard-dg1-18/igt@gem_...@unwedge-stress.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118802v1/shard-dg1-17/igt@gem_...@unwedge-stress.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][13] ([i915#2842]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13223/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118802v1/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-none@bcs0:
- {shard-rkl}:[FAIL][15] ([i915#2842]) -> [PASS][16] +3 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13223/shard-rkl-3/igt@gem_exec_fair@basic-n...@bcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118802v1/shard-rkl-6/igt@gem_exec_fair@basic-n...@bcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [FAIL][17] ([i915#2842]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13223/shard-glk9/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118802v1/shard-glk1/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_mmap_offset@clear@smem0:
- {shard-dg1}:[DMESG-WARN][19] ([i915#8304]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13223/shard-dg1-17/igt@gem_mmap_offset@cl...@smem0.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118802v1/shard-dg1-15/igt@gem_mmap_offset@cl...@smem0.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-tglu}: [FAIL][21] ([i915#3989] / [i915#454]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13223/shard-tglu-5/igt@i915_pm...@dc6-dpms.html
[22]:
Re: [Intel-gfx] [PATCH v12 7/7] drm/i915/mtl: Add support for PM DEMAND
On Thu, Jun 01, 2023 at 07:03:50PM +0300, Vinod Govindapillai wrote:
> From: Mika Kahola
>
> MTL introduces a new way to instruct the PUnit with
> power and bandwidth requirements of DE. Add the functionality
> to program the registers and handle waits using interrupts.
> The current wait time for timeouts is programmed for 10 msecs to
> factor in the worst case scenarios. Changes made to use REG_BIT
> for a register that we touched(GEN8_DE_MISC_IER _MMIO).
>
> Wa_14016740474 is added which applies to Xe_LPD+ display
>
> v2: checkpatch warning fixes, simplify program pmdemand part
>
> v3: update to dbufs and pipes values to pmdemand register(stan)
> Removed the macro usage in update_pmdemand_values()
>
> v4: move the pmdemand_pre_plane_update before cdclk update
> pmdemand_needs_update included cdclk params comparisons
> pmdemand_state NULL check (Gustavo)
> pmdemand.o in sorted order in the makefile (Jani)
> update pmdemand misc irq handler loop (Gustavo)
> active phys bitmask and programming correction (Gustavo)
>
> v5: simplify pmdemand_state structure
> simplify methods to find active phys and max port clock
> Timeout in case of previou pmdemand task pending (Gustavo)
>
> v6: rebasing
> updates to max_ddiclk calculations (Gustavo)
> updates to active_phys count method (Gustavo)
>
> v7: use two separate loop to iterate throug old and new
> crtc states to calculate the active phys (Gustavo)
>
> v8: use uniform function names (Gustavo)
>
> v9: For phys change iterate through connectors (Imre)
> Look for change in phys for pmdemand update (Gustavo, Imre)
> Some more stlying changes (Imre)
> Update pmdemand state during HW readout/sanitize (Imre)
>
> v10: Fix CI checkpatch warnings
>
> v11: use correct pmdemand object pointer during hw readout,
> simplify the check for phys need update (Gustavo)
>
> Bspec: 66451, 64636, 64602, 64603
> Cc: Matt Atwood
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Cc: Gustavo Sousa
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Gustavo Sousa
> Signed-off-by: Mika Kahola
> Signed-off-by: Vinod Govindapillai
> Reviewed-by: Stanislav Lisovskiy
> Acked-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 14 +
> .../gpu/drm/i915/display/intel_display_core.h | 9 +
> .../drm/i915/display/intel_display_driver.c | 7 +
> .../gpu/drm/i915/display/intel_display_irq.c | 23 +-
> .../drm/i915/display/intel_display_power.c| 14 +-
> .../drm/i915/display/intel_modeset_setup.c| 18 +
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 525 ++
> drivers/gpu/drm/i915/display/intel_pmdemand.h | 56 ++
> drivers/gpu/drm/i915/i915_reg.h | 36 +-
> 10 files changed, 697 insertions(+), 6 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 1c9ed4c52760..2cd8de174bf6 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -269,6 +269,7 @@ i915-y += \
> display/intel_pch_display.o \
> display/intel_pch_refclk.o \
> display/intel_plane_initial.o \
> + display/intel_pmdemand.o \
> display/intel_psr.o \
> display/intel_quirks.o \
> display/intel_sprite.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f51a55f4e9d0..5cbf5eae2414 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -99,6 +99,7 @@
> #include "intel_pcode.h"
> #include "intel_pipe_crc.h"
> #include "intel_plane_initial.h"
> +#include "intel_pmdemand.h"
> #include "intel_pps.h"
> #include "intel_psr.h"
> #include "intel_sdvo.h"
> @@ -6352,6 +6353,10 @@ int intel_atomic_check(struct drm_device *dev,
> return ret;
> }
>
> + ret = intel_pmdemand_atomic_check(state);
> + if (ret)
> + goto fail;
> +
> ret = intel_atomic_check_crtcs(state);
> if (ret)
> goto fail;
> @@ -6997,6 +7002,14 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> crtc->config = new_crtc_state;
>
> + /*
> + * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
> + * plls, cdclk frequency, QGV point selection parameter etc. Voltage
> + * index, cdclk/ddiclk frequencies are supposed to be configured before
> + * the cdclk config is set.
> + */
> + intel_pmdemand_pre_plane_update(state);
> +
> if (state->modeset) {
> drm_atomic_helper_update_legacy_modeset_state(dev,
>
Re: [Intel-gfx] [PATCH v12 6/7] drm/i915/mtl: find the best QGV point for the SAGV configuration
On Mon, 2023-06-05 at 12:49 +0300, Imre Deak wrote:
> On Thu, Jun 01, 2023 at 07:03:49PM +0300, Vinod Govindapillai wrote:
> > From MTL onwards, we need to find the best QGV point based on
> > the required data rate and pass the peak BW of that point to
> > the punit to lock the corresponding QGV point.
> >
> > v1: Fix for warning from kernel test robot
> >
> > Bspec: 64636
> >
> > Reported-by: kernel test robot
> > Closes: https://lore.kernel.org/r/202305280253.ab8brv2w-...@intel.com/
> > Reported-by: Dan Carpenter
> > Closes: https://lore.kernel.org/r/202305280253.ab8brv2w-...@intel.com/
> > Signed-off-by: Vinod Govindapillai
> > Reviewed-by: Stanislav Lisovskiy
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.c | 87 -
> > drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
> > 2 files changed, 91 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index b1cbeda0b2e3..7672963dc49c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -803,6 +803,85 @@ intel_atomic_get_bw_state(struct intel_atomic_state
> > *state)
> > return to_intel_bw_state(bw_state);
> > }
> >
> > +static int mtl_find_qgv_points(struct drm_i915_private *i915,
> > + unsigned int data_rate,
> > + unsigned int num_active_planes,
> > + const struct intel_bw_state *old_bw_state,
> > + struct intel_bw_state *new_bw_state)
> > +{
> > + unsigned int best_rate = UINT_MAX;
> > + unsigned int num_qgv_points =
> > i915->display.bw.max[0].num_qgv_points;
> > + unsigned int qgv_peak_bw = 0;
> > + int i;
> > + int ret;
> > +
> > + ret = intel_atomic_lock_global_state(_bw_state->base);
> > + if (ret)
> > + return ret;
> > +
> > + /*
> > + * If SAGV cannot be enabled, disable the pcode SAGV by passing all
> > 1's
> > + * for qgv peak bw in PM Demand request. So assign UINT_MAX if SAGV
> > is
> > + * not enabled. PM Demand code will clamp the value for the register
> > + */
> > + if (!intel_can_enable_sagv(i915, new_bw_state)) {
> > + new_bw_state->qgv_point_peakbw = UINT_MAX;
> > + drm_dbg_kms(>drm, "No SAGV, use UINT_MAX as peak
> > bw.");
> > + goto out;
> > + }
> > +
> > + /*
> > + * Find the best QGV point by comparing the data_rate with max data
> > rate
> > + * offered per plane group
> > + */
> > + for (i = 0; i < num_qgv_points; i++) {
> > + unsigned int bw_index =
> > + tgl_max_bw_index(i915, num_active_planes, i);
> > + unsigned int max_data_rate;
> > +
> > + if (bw_index >= ARRAY_SIZE(i915->display.bw.max))
> > + continue;
> > +
> > + max_data_rate = i915->display.bw.max[bw_index].deratedbw[i];
> > +
> > + if (max_data_rate < data_rate)
> > + continue;
> > +
> > + if (max_data_rate - data_rate < best_rate) {
> > + best_rate = max_data_rate - data_rate;
> > + qgv_peak_bw =
> > i915->display.bw.max[bw_index].peakbw[i];
> > + }
> > +
> > + drm_dbg_kms(>drm, "QGV point %d: max bw %d required
> > %d qgv_peak_bw: %d\n",
> > + i, max_data_rate, data_rate, qgv_peak_bw);
> > + }
> > +
> > + drm_dbg_kms(>drm, "Matching peaks QGV bw: %d for required
> > data rate: %d\n",
> > + qgv_peak_bw, data_rate);
> > +
> > + /*
> > + * The display configuration cannot be supported if no QGV point
> > + * satisfying the required data rate is found
> > + */
> > + if (qgv_peak_bw == 0) {
> > + drm_dbg_kms(>drm, "No QGV points for bw %d for
> > display configuration(%d
> > active planes).\n",
> > + data_rate, num_active_planes);
> > + return -EINVAL;
> > + }
> > +
> > + /* MTL PM DEMAND expects QGV BW parameter in multiples of 100 mbps
> > */
> > + new_bw_state->qgv_point_peakbw = DIV_ROUND_CLOSEST(qgv_peak_bw,
> > 100);
> > +
> > +out:
> > + if (new_bw_state->qgv_point_peakbw !=
> > old_bw_state->qgv_point_peakbw) {
> > + ret =
> > intel_atomic_serialize_global_state(_bw_state->base);
>
> qgv_point_beakbw is used as a parameter for the pmdemand command, for
> which there is a check later whether programming it is required or not.
> So why is global state serialized here?
Yes. good point. This need not to be serialized here. Will remove it.
Thanks
Vinod
>
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
>
Re: [Intel-gfx] [PATCH v12 6/7] drm/i915/mtl: find the best QGV point for the SAGV configuration
On Thu, Jun 01, 2023 at 07:03:49PM +0300, Vinod Govindapillai wrote:
> From MTL onwards, we need to find the best QGV point based on
> the required data rate and pass the peak BW of that point to
> the punit to lock the corresponding QGV point.
>
> v1: Fix for warning from kernel test robot
>
> Bspec: 64636
>
> Reported-by: kernel test robot
> Closes: https://lore.kernel.org/r/202305280253.ab8brv2w-...@intel.com/
> Reported-by: Dan Carpenter
> Closes: https://lore.kernel.org/r/202305280253.ab8brv2w-...@intel.com/
> Signed-off-by: Vinod Govindapillai
> Reviewed-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 87 -
> drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
> 2 files changed, 91 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index b1cbeda0b2e3..7672963dc49c 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -803,6 +803,85 @@ intel_atomic_get_bw_state(struct intel_atomic_state
> *state)
> return to_intel_bw_state(bw_state);
> }
>
> +static int mtl_find_qgv_points(struct drm_i915_private *i915,
> +unsigned int data_rate,
> +unsigned int num_active_planes,
> +const struct intel_bw_state *old_bw_state,
> +struct intel_bw_state *new_bw_state)
> +{
> + unsigned int best_rate = UINT_MAX;
> + unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> + unsigned int qgv_peak_bw = 0;
> + int i;
> + int ret;
> +
> + ret = intel_atomic_lock_global_state(_bw_state->base);
> + if (ret)
> + return ret;
> +
> + /*
> + * If SAGV cannot be enabled, disable the pcode SAGV by passing all 1's
> + * for qgv peak bw in PM Demand request. So assign UINT_MAX if SAGV is
> + * not enabled. PM Demand code will clamp the value for the register
> + */
> + if (!intel_can_enable_sagv(i915, new_bw_state)) {
> + new_bw_state->qgv_point_peakbw = UINT_MAX;
> + drm_dbg_kms(>drm, "No SAGV, use UINT_MAX as peak bw.");
> + goto out;
> + }
> +
> + /*
> + * Find the best QGV point by comparing the data_rate with max data rate
> + * offered per plane group
> + */
> + for (i = 0; i < num_qgv_points; i++) {
> + unsigned int bw_index =
> + tgl_max_bw_index(i915, num_active_planes, i);
> + unsigned int max_data_rate;
> +
> + if (bw_index >= ARRAY_SIZE(i915->display.bw.max))
> + continue;
> +
> + max_data_rate = i915->display.bw.max[bw_index].deratedbw[i];
> +
> + if (max_data_rate < data_rate)
> + continue;
> +
> + if (max_data_rate - data_rate < best_rate) {
> + best_rate = max_data_rate - data_rate;
> + qgv_peak_bw = i915->display.bw.max[bw_index].peakbw[i];
> + }
> +
> + drm_dbg_kms(>drm, "QGV point %d: max bw %d required %d
> qgv_peak_bw: %d\n",
> + i, max_data_rate, data_rate, qgv_peak_bw);
> + }
> +
> + drm_dbg_kms(>drm, "Matching peaks QGV bw: %d for required data
> rate: %d\n",
> + qgv_peak_bw, data_rate);
> +
> + /*
> + * The display configuration cannot be supported if no QGV point
> + * satisfying the required data rate is found
> + */
> + if (qgv_peak_bw == 0) {
> + drm_dbg_kms(>drm, "No QGV points for bw %d for display
> configuration(%d active planes).\n",
> + data_rate, num_active_planes);
> + return -EINVAL;
> + }
> +
> + /* MTL PM DEMAND expects QGV BW parameter in multiples of 100 mbps */
> + new_bw_state->qgv_point_peakbw = DIV_ROUND_CLOSEST(qgv_peak_bw, 100);
> +
> +out:
> + if (new_bw_state->qgv_point_peakbw != old_bw_state->qgv_point_peakbw) {
> + ret = intel_atomic_serialize_global_state(_bw_state->base);
qgv_point_beakbw is used as a parameter for the pmdemand command, for
which there is a check later whether programming it is required or not.
So why is global state serialized here?
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> static int icl_find_qgv_points(struct drm_i915_private *i915,
> unsigned int data_rate,
> unsigned int num_active_planes,
> @@ -928,8 +1007,12 @@ static int intel_bw_check_qgv_points(struct
> drm_i915_private *i915,
>
> data_rate = DIV_ROUND_UP(data_rate, 1000);
>
> - return icl_find_qgv_points(i915, data_rate, num_active_planes,
> -old_bw_state, new_bw_state);
> + if (DISPLAY_VER(i915) >= 14)
> + return
[Intel-gfx] [CI 4/4] drm/i915: Expose RPS thresholds in sysfs
From: Tvrtko Ursulin
User feedback indicates significant performance gains are possible in
specific games with non default RPS up/down thresholds.
Expose these tunables via sysfs which will allow users to achieve best
performance when running games and best power efficiency elsewhere.
Note this patch supports non GuC based platforms only.
v2:
* Make checkpatch happy.
Signed-off-by: Tvrtko Ursulin
References: https://gitlab.freedesktop.org/drm/intel/-/issues/8389
Cc: Rodrigo Vivi
Acked-by: Rodrigo Vivi
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 108
1 file changed, 108 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index ee2b44f896a2..f0dea54880af 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -700,6 +700,80 @@ static const struct attribute *media_perf_power_attrs[] = {
NULL
};
+static ssize_t
+rps_up_threshold_pct_show(struct kobject *kobj, struct kobj_attribute *attr,
+ char *buf)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
+ struct intel_rps *rps = >rps;
+
+ return sysfs_emit(buf, "%u\n", intel_rps_get_up_threshold(rps));
+}
+
+static ssize_t
+rps_up_threshold_pct_store(struct kobject *kobj, struct kobj_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
+ struct intel_rps *rps = >rps;
+ int ret;
+ u8 val;
+
+ ret = kstrtou8(buf, 10, );
+ if (ret)
+ return ret;
+
+ ret = intel_rps_set_up_threshold(rps, val);
+
+ return ret == 0 ? count : ret;
+}
+
+static struct kobj_attribute rps_up_threshold_pct =
+ __ATTR(rps_up_threshold_pct,
+ 0664,
+ rps_up_threshold_pct_show,
+ rps_up_threshold_pct_store);
+
+static ssize_t
+rps_down_threshold_pct_show(struct kobject *kobj, struct kobj_attribute *attr,
+ char *buf)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
+ struct intel_rps *rps = >rps;
+
+ return sysfs_emit(buf, "%u\n", intel_rps_get_down_threshold(rps));
+}
+
+static ssize_t
+rps_down_threshold_pct_store(struct kobject *kobj, struct kobj_attribute *attr,
+const char *buf, size_t count)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
+ struct intel_rps *rps = >rps;
+ int ret;
+ u8 val;
+
+ ret = kstrtou8(buf, 10, );
+ if (ret)
+ return ret;
+
+ ret = intel_rps_set_down_threshold(rps, val);
+
+ return ret == 0 ? count : ret;
+}
+
+static struct kobj_attribute rps_down_threshold_pct =
+ __ATTR(rps_down_threshold_pct,
+ 0664,
+ rps_down_threshold_pct_show,
+ rps_down_threshold_pct_store);
+
+static const struct attribute * const gen6_gt_rps_attrs[] = {
+ _up_threshold_pct.attr,
+ _down_threshold_pct.attr,
+ NULL
+};
+
static ssize_t
default_min_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr,
char *buf)
{
@@ -722,9 +796,37 @@ default_max_freq_mhz_show(struct kobject *kobj, struct
kobj_attribute *attr, cha
static struct kobj_attribute default_max_freq_mhz =
__ATTR(rps_max_freq_mhz, 0444, default_max_freq_mhz_show, NULL);
+static ssize_t
+default_rps_up_threshold_pct_show(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ char *buf)
+{
+ struct intel_gt *gt = kobj_to_gt(kobj->parent);
+
+ return sysfs_emit(buf, "%u\n", gt->defaults.rps_up_threshold);
+}
+
+static struct kobj_attribute default_rps_up_threshold_pct =
+__ATTR(rps_up_threshold_pct, 0444, default_rps_up_threshold_pct_show, NULL);
+
+static ssize_t
+default_rps_down_threshold_pct_show(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ char *buf)
+{
+ struct intel_gt *gt = kobj_to_gt(kobj->parent);
+
+ return sysfs_emit(buf, "%u\n", gt->defaults.rps_down_threshold);
+}
+
+static struct kobj_attribute default_rps_down_threshold_pct =
+__ATTR(rps_down_threshold_pct, 0444, default_rps_down_threshold_pct_show,
NULL);
+
static const struct attribute * const rps_defaults_attrs[] = {
_min_freq_mhz.attr,
_max_freq_mhz.attr,
+ _rps_up_threshold_pct.attr,
+ _rps_down_threshold_pct.attr,
NULL
};
@@ -752,6 +854,12 @@ static int intel_sysfs_rps_init(struct intel_gt *gt,
struct kobject *kobj)
if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915))
ret = sysfs_create_file(kobj, vlv_attr);
+ if (is_object_gt(kobj) && !intel_uc_uses_guc_slpc(>uc)) {
+ ret =
[Intel-gfx] [CI 3/4] drm/i915: Add helpers for managing rps thresholds
From: Tvrtko Ursulin
In preparation for exposing via sysfs add helpers for managing rps
thresholds.
v2:
* Force sw and hw re-programming on threshold change.
Signed-off-by: Tvrtko Ursulin
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_rps.c | 54 +
drivers/gpu/drm/i915/gt/intel_rps.h | 4 +++
2 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 333abc8f7ecb..afde601a6111 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -16,7 +16,9 @@
#include "intel_gt.h"
#include "intel_gt_clock_utils.h"
#include "intel_gt_irq.h"
+#include "intel_gt_pm.h"
#include "intel_gt_pm_irq.h"
+#include "intel_gt_print.h"
#include "intel_gt_regs.h"
#include "intel_mchbar_regs.h"
#include "intel_pcode.h"
@@ -2574,6 +2576,58 @@ int intel_rps_set_min_frequency(struct intel_rps *rps,
u32 val)
return set_min_freq(rps, val);
}
+u8 intel_rps_get_up_threshold(struct intel_rps *rps)
+{
+ return rps->power.up_threshold;
+}
+
+static int rps_set_threshold(struct intel_rps *rps, u8 *threshold, u8 val)
+{
+ int ret;
+
+ if (val > 100)
+ return -EINVAL;
+
+ ret = mutex_lock_interruptible(>lock);
+ if (ret)
+ return ret;
+
+ if (*threshold == val)
+ goto out_unlock;
+
+ *threshold = val;
+
+ /* Force reset. */
+ rps->last_freq = -1;
+ mutex_lock(>power.mutex);
+ rps->power.mode = -1;
+ mutex_unlock(>power.mutex);
+
+ intel_rps_set(rps, clamp(rps->cur_freq,
+rps->min_freq_softlimit,
+rps->max_freq_softlimit));
+
+out_unlock:
+ mutex_unlock(>lock);
+
+ return ret;
+}
+
+int intel_rps_set_up_threshold(struct intel_rps *rps, u8 threshold)
+{
+ return rps_set_threshold(rps, >power.up_threshold, threshold);
+}
+
+u8 intel_rps_get_down_threshold(struct intel_rps *rps)
+{
+ return rps->power.down_threshold;
+}
+
+int intel_rps_set_down_threshold(struct intel_rps *rps, u8 threshold)
+{
+ return rps_set_threshold(rps, >power.down_threshold, threshold);
+}
+
static void intel_rps_set_manual(struct intel_rps *rps, bool enable)
{
struct intel_uncore *uncore = rps_to_uncore(rps);
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h
b/drivers/gpu/drm/i915/gt/intel_rps.h
index a3fa987aa91f..92fb01f5a452 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -37,6 +37,10 @@ void intel_rps_mark_interactive(struct intel_rps *rps, bool
interactive);
int intel_gpu_freq(struct intel_rps *rps, int val);
int intel_freq_opcode(struct intel_rps *rps, int val);
+u8 intel_rps_get_up_threshold(struct intel_rps *rps);
+int intel_rps_set_up_threshold(struct intel_rps *rps, u8 threshold);
+u8 intel_rps_get_down_threshold(struct intel_rps *rps);
+int intel_rps_set_down_threshold(struct intel_rps *rps, u8 threshold);
u32 intel_rps_read_actual_frequency(struct intel_rps *rps);
u32 intel_rps_read_actual_frequency_fw(struct intel_rps *rps);
u32 intel_rps_get_requested_frequency(struct intel_rps *rps);
--
2.39.2
[Intel-gfx] [CI 2/4] drm/i915: Record default rps threshold values
From: Tvrtko Ursulin
Record the default values as preparation for exposing the sysfs controls.
Signed-off-by: Tvrtko Ursulin
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
drivers/gpu/drm/i915/gt/intel_rps.c | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index f08c2556aa25..1b22d7a50665 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -83,6 +83,9 @@ enum intel_submission_method {
struct gt_defaults {
u32 min_freq;
u32 max_freq;
+
+ u8 rps_up_threshold;
+ u8 rps_down_threshold;
};
enum intel_gt_type {
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 791097eb9bfd..333abc8f7ecb 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2016,7 +2016,9 @@ void intel_rps_init(struct intel_rps *rps)
/* Set default thresholds in % */
rps->power.up_threshold = 95;
+ rps_to_gt(rps)->defaults.rps_up_threshold = rps->power.up_threshold;
rps->power.down_threshold = 85;
+ rps_to_gt(rps)->defaults.rps_down_threshold = rps->power.down_threshold;
/* Finally allow us to boost to max by default */
rps->boost_freq = rps->max_freq;
--
2.39.2
[Intel-gfx] [CI 1/4] drm/i915: Move setting of rps thresholds to init
From: Tvrtko Ursulin
Since 36d516be867c ("drm/i915/gt: Switch to manual evaluation of RPS")
thresholds are invariant so lets move their setting to init time.
Signed-off-by: Tvrtko Ursulin
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_rps.c | 27 ---
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index e68a99205599..791097eb9bfd 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -671,7 +671,6 @@ static void rps_set_power(struct intel_rps *rps, int
new_power)
{
struct intel_gt *gt = rps_to_gt(rps);
struct intel_uncore *uncore = gt->uncore;
- u32 threshold_up = 0, threshold_down = 0; /* in % */
u32 ei_up = 0, ei_down = 0;
lockdep_assert_held(>power.mutex);
@@ -679,9 +678,6 @@ static void rps_set_power(struct intel_rps *rps, int
new_power)
if (new_power == rps->power.mode)
return;
- threshold_up = 95;
- threshold_down = 85;
-
/* Note the units here are not exactly 1us, but 1280ns. */
switch (new_power) {
case LOW_POWER:
@@ -708,17 +704,22 @@ static void rps_set_power(struct intel_rps *rps, int
new_power)
GT_TRACE(gt,
"changing power mode [%d], up %d%% @ %dus, down %d%% @ %dus\n",
-new_power, threshold_up, ei_up, threshold_down, ei_down);
+new_power,
+rps->power.up_threshold, ei_up,
+rps->power.down_threshold, ei_down);
set(uncore, GEN6_RP_UP_EI,
intel_gt_ns_to_pm_interval(gt, ei_up * 1000));
set(uncore, GEN6_RP_UP_THRESHOLD,
- intel_gt_ns_to_pm_interval(gt, ei_up * threshold_up * 10));
+ intel_gt_ns_to_pm_interval(gt,
+ ei_up * rps->power.up_threshold * 10));
set(uncore, GEN6_RP_DOWN_EI,
intel_gt_ns_to_pm_interval(gt, ei_down * 1000));
set(uncore, GEN6_RP_DOWN_THRESHOLD,
- intel_gt_ns_to_pm_interval(gt, ei_down * threshold_down * 10));
+ intel_gt_ns_to_pm_interval(gt,
+ ei_down *
+ rps->power.down_threshold * 10));
set(uncore, GEN6_RP_CONTROL,
(GRAPHICS_VER(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
@@ -730,8 +731,6 @@ static void rps_set_power(struct intel_rps *rps, int
new_power)
skip_hw_write:
rps->power.mode = new_power;
- rps->power.up_threshold = threshold_up;
- rps->power.down_threshold = threshold_down;
}
static void gen6_rps_set_thresholds(struct intel_rps *rps, u8 val)
@@ -1557,10 +1556,12 @@ void intel_rps_enable(struct intel_rps *rps)
return;
GT_TRACE(rps_to_gt(rps),
-"min:%x, max:%x, freq:[%d, %d]\n",
+"min:%x, max:%x, freq:[%d, %d], thresholds:[%u, %u]\n",
rps->min_freq, rps->max_freq,
intel_gpu_freq(rps, rps->min_freq),
-intel_gpu_freq(rps, rps->max_freq));
+intel_gpu_freq(rps, rps->max_freq),
+rps->power.up_threshold,
+rps->power.down_threshold);
GEM_BUG_ON(rps->max_freq < rps->min_freq);
GEM_BUG_ON(rps->idle_freq > rps->max_freq);
@@ -2013,6 +2014,10 @@ void intel_rps_init(struct intel_rps *rps)
}
}
+ /* Set default thresholds in % */
+ rps->power.up_threshold = 95;
+ rps->power.down_threshold = 85;
+
/* Finally allow us to boost to max by default */
rps->boost_freq = rps->max_freq;
rps->idle_freq = rps->min_freq;
--
2.39.2
Re: [Intel-gfx] [PATCH V5] drm/i915/gt: Add workaround 14016712196
Hi Tejas, On Thu, Jun 01, 2023 at 04:39:59PM +0530, Tejas Upadhyay wrote: > For mtl, workaround suggests that, SW insert a > dummy PIPE_CONTROL prior to PIPE_CONTROL which > contains a post sync: Timestamp or Write Immediate. > > Bspec: 72197 > > V5: > - Remove ret variable - Andi > V4: > - Update commit message, avoid returing cs - Andi/Matt > V3: > - Wrap dummy pipe control stuff in API - Andi > V2: > - Fix kernel test robot warnings > > Closes: > https://lore.kernel.org/oe-kbuild-all/202305121525.3ewdgoby-...@intel.com/ > Reviewed-by: Andi Shyti > Signed-off-by: Tejas Upadhyay pushed to drm-intel-gt-next. Thanks, Andi
Re: [Intel-gfx] [PATCH v2] drm/i915/mtl: Reset only one lane in case of MFD
On Thu, 2023-06-01 at 15:34 +0300, Luca Coelho wrote: > On Thu, 2023-06-01 at 13:13 +0300, Mika Kahola wrote: > > In case when only two or less transmit lanes are owned such as MFD > > (DP-alt with x2 lanes) we need to reset only one data lane (lane0). > > With only x2 lanes we don't need to poll for the phy current > > status on both data lanes since only the owned data lane will > > respond. > > > > v2: Find better naming for lanes and revise the commit message > > (Luca) > > > > Reviewed-by: Arun R Murthy (v1) > > Signed-off-by: Mika Kahola > > --- > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 39 > > > > 1 file changed, 23 insertions(+), 16 deletions(-) > > Reviewed-by: Luca Coelho Thank you Luca for the review. This is now pushed. > > -- > Cheers, > Luca.
Re: [Intel-gfx] [PATCH v3] drm/i915: Use 18 fast wake AUX sync len
On Fri, 2023-06-02 at 11:40 +0300, Luca Coelho wrote:
> On Tue, 2023-05-30 at 13:16 +0300, Jouni Högander wrote:
> > HW default for wake sync pulses is 18. 10 precarge and 8 preamble.
> > There is
>
> Small typo: s/precarge/precharge/
>
>
> > no reason to change this especially as it is causing problems with
> > certain
> > eDP panels.
> >
> > v3: Change "Fixes:" commit
> > v2: Remove "fast wake" repeat from subject
> >
> > Signed-off-by: Jouni Högander
> > Fixes: e1c71f8f9180 ("drm/i915: Fix fast wake AUX sync len")
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8475
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > index 0c27db8ae4f1..197c6e81db14 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > @@ -129,7 +129,7 @@ static int intel_dp_aux_sync_len(void)
> >
> > static int intel_dp_aux_fw_sync_len(void)
> > {
> > - int precharge = 16; /* 10-16 */
> > + int precharge = 10; /* 10-16 */
> > int preamble = 8;
> >
> > return precharge + preamble;
>
> If this really solves the problem, and since the comment clearly says
> that the range is from 10 to 16, it looks good to me.
>
> Reviewed-by: Luca Coelho
Thank you Luca for the review. This is now pushed with your rb tag and
typo mentioned above fixed.
>
> --
> Cheers,
> Luca.
Re: [Intel-gfx] [PATCH 2/2] drm/i915: rename I915_PMU_MAX_GTS to I915_PMU_MAX_GT
On 03/06/2023 00:17, Matt Atwood wrote:
_GTS as an abbreviation here leads to some confusion, match other
definitions and drop the s.
Cc: Matt Roper
Cc: Ashutosh Dixit
Cc: Andi Shyti
Cc: Tvrtko Ursulin
Cc: Umesh Nerlige Ramappa
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/i915_pmu.c | 2 +-
drivers/gpu/drm/i915/i915_pmu.h | 8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index f96fe92dca4e..d35973b41186 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -132,7 +132,7 @@ static u32 frequency_enabled_mask(void)
unsigned int i;
u32 mask = 0;
- for (i = 0; i < I915_PMU_MAX_GTS; i++)
+ for (i = 0; i < I915_PMU_MAX_GT; i++)
mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) |
config_mask(__I915_PMU_REQUESTED_FREQUENCY(i));
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index d20592e7db99..41af038c3738 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -38,7 +38,7 @@ enum {
__I915_NUM_PMU_SAMPLERS
};
-#define I915_PMU_MAX_GTS 2
+#define I915_PMU_MAX_GT 2
Shrug from me since I wasn't a fan* of the original s/gts/gt/ effort.
But AFAIR that has been done already, I guess consistency wins so I am
not blocking it either.
Regards,
Tvrtko
*) What is a max gt? Can I index it into the array? Or expect the gt id
to contain that value? Neither is true hence my dislike.
/*
* How many different events we track in the global PMU mask.
@@ -47,7 +47,7 @@ enum {
*/
#define I915_PMU_MASK_BITS \
(I915_ENGINE_SAMPLE_COUNT + \
-I915_PMU_MAX_GTS * __I915_PMU_TRACKED_EVENT_COUNT)
+I915_PMU_MAX_GT * __I915_PMU_TRACKED_EVENT_COUNT)
#define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)
@@ -127,11 +127,11 @@ struct i915_pmu {
* Only global counters are held here, while the per-engine ones are in
* struct intel_engine_cs.
*/
- struct i915_pmu_sample
sample[I915_PMU_MAX_GTS][__I915_NUM_PMU_SAMPLERS];
+ struct i915_pmu_sample sample[I915_PMU_MAX_GT][__I915_NUM_PMU_SAMPLERS];
/**
* @sleep_last: Last time GT parked for RC6 estimation.
*/
- ktime_t sleep_last[I915_PMU_MAX_GTS];
+ ktime_t sleep_last[I915_PMU_MAX_GT];
/**
* @irq_count: Number of interrupts
*
Re: [Intel-gfx] [PATCH v15 0/1] drm/i915: Allow user to set cache at BO creation
On 05/06/2023 09:53, Tvrtko Ursulin wrote:
On 31/05/2023 18:10, fei.y...@intel.com wrote:
From: Fei Yang
This series introduce a new extension for GEM_CREATE,
1. end support for set caching ioctl [PATCH 1/2]
2. add set_pat extension for gem_create [PATCH 2/2]
v2: drop one patch that was merged separately
commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
v3: rebased on https://patchwork.freedesktop.org/series/117082/
v4: fix missing unlock introduced in v3, and
solve a rebase conflict
v5: replace obj->cache_level with pat_set_by_user,
fix i915_cache_level_str() for legacy platforms.
v6: rebased on https://patchwork.freedesktop.org/series/117480/
v7: rebased on https://patchwork.freedesktop.org/series/117528/
v8: dropped the two dependent patches that has been merged
separately. Add IGT link and Tested-by (MESA).
v9: addressing comments (Andi)
v10: acked-by and tested-by MESA
v11: drop "end support for set caching ioctl" (merged)
remove tools/include/uapi/drm/i915_drm.h
v12: drop Bspec reference in comment. add to commit message instead
v13: sent to test with igt@gem_create@create-ext-set-pat
v14: sent to test with igt@gem_create@create-ext-set-pat
v15: update commit message with documentation note and t-b/a-b from
Media driver folks.
Fei Yang (1):
drm/i915: Allow user to set cache at BO creation
drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6
include/uapi/drm/i915_drm.h | 41 ++
3 files changed, 83 insertions(+)
Try with:
Test-with: 20230526172221.1438998-1-fei.y...@intel.com
That is how it is supposed to be done, to do a CI run against a test
case not yet merged that is.
Or I see that IGT has been since merged so you probably have results
already?
Regards,
Tvrtko
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Extract display init from intel_device_info_runtime_init (rev2)
== Series Details == Series: drm/i915/display: Extract display init from intel_device_info_runtime_init (rev2) URL : https://patchwork.freedesktop.org/series/118730/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13222_full -> Patchwork_118730v2_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_118730v2_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_118730v2_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (7 -> 7) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_118730v2_full: ### IGT changes ### Possible regressions * igt@kms_busy@extended-modeset-hang-newfb-with-reset@pipe-b: - shard-snb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-snb2/igt@kms_busy@extended-modeset-hang-newfb-with-re...@pipe-b.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-snb2/igt@kms_busy@extended-modeset-hang-newfb-with-re...@pipe-b.html Known issues Here are the changes found in Patchwork_118730v2_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-glk: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [FAIL][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) ([i915#7849] / [i915#8293]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk1/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk1/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk2/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk2/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk2/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk4/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk5/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk5/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk6/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk6/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk6/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk7/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk7/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk7/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk9/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk9/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk7/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk7/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk7/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk6/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk6/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk6/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk5/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk5/boot.html [35]:
Re: [Intel-gfx] [PATCH v15 1/1] drm/i915: Allow user to set cache at BO creation
On 31/05/2023 18:10, fei.y...@intel.com wrote:
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a default (platform dependent) cache setting for all objects.
However this is not optimal for performance tuning. The patch extends
the existing gem_create uAPI to let user set PAT index for the object
at creation time.
The new extension is platform independent, so UMD's can switch to using
this extension for older platforms as well, while {set, get}_caching are
still supported on these legacy paltforms for compatibility reason.
Note: The detailed description of PAT index is missing in current PRM
even for older hardware and will be added by the next PRM update under
chapter name "Memory Views".
BSpec: 45101
Mesa support has been submitted in this merge request:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
The media driver is supported by the following commits:
https://github.com/intel/media-driver/commit/92c00a857433ebb34ec575e9834f473c6fcb6341
https://github.com/intel/media-driver/commit/fd375cf2c5e1f6bf6b43258ff797b3134aadc9fd
https://github.com/intel/media-driver/commit/08dd244b22484770a33464c2c8ae85430e548000
On which platforms will media-driver use the uapi? I couldn't easily
figure out myself from the links above and also in the master branch I
couldn't find the implementation of CachePolicyGetPATIndex.
Now that PRMs for Tigerlake have been published and Meteorlake situation
is documented indirectly in Mesa code, my only remaining concern is with
the older platforms. So if there is no particular reason to have the
extension working on those, I would strongly suggest we disable there.
For a precedent see I915_CONTEXT_PARAM_SSEU and how it allows the
extension only on Gen11 and only for a very specific usecase (see
restrictions in set_sseu() and i915_gem_user_to_context_sseu()).
Regards,
Tvrtko
The IGT test related to this change is
igt@gem_create@create-ext-set-pat
Signed-off-by: Fei Yang
Cc: Chris Wilson
Cc: Matt Roper
Cc: Andi Shyti
Reviewed-by: Andi Shyti
Acked-by: Jordan Justen
Tested-by: Jordan Justen
Acked-by: Carl Zhang
Tested-by: Lihao Gu
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6
include/uapi/drm/i915_drm.h| 41 ++
3 files changed, 83 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index bfe1dbda4cb7..644a936248ad 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -245,6 +245,7 @@ struct create_ext {
unsigned int n_placements;
unsigned int placement_mask;
unsigned long flags;
+ unsigned int pat_index;
};
static void repr_placements(char *buf, size_t size,
@@ -394,11 +395,39 @@ static int ext_set_protected(struct i915_user_extension
__user *base, void *data
return 0;
}
+static int ext_set_pat(struct i915_user_extension __user *base, void *data)
+{
+ struct create_ext *ext_data = data;
+ struct drm_i915_private *i915 = ext_data->i915;
+ struct drm_i915_gem_create_ext_set_pat ext;
+ unsigned int max_pat_index;
+
+ BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
+offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
+
+ if (copy_from_user(, base, sizeof(ext)))
+ return -EFAULT;
+
+ max_pat_index = INTEL_INFO(i915)->max_pat_index;
+
+ if (ext.pat_index > max_pat_index) {
+ drm_dbg(>drm, "PAT index is invalid: %u\n",
+ ext.pat_index);
+ return -EINVAL;
+ }
+
+ ext_data->pat_index = ext.pat_index;
+
+ return 0;
+}
+
static const i915_user_extension_fn create_extensions[] = {
[I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements,
[I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected,
+ [I915_GEM_CREATE_EXT_SET_PAT] = ext_set_pat,
};
+#define PAT_INDEX_NOT_SET 0x
/**
* i915_gem_create_ext_ioctl - Creates a new mm object and returns a handle
to it.
* @dev: drm device pointer
@@ -418,6 +447,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
*data,
if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS)
return -EINVAL;
+ ext_data.pat_index = PAT_INDEX_NOT_SET;
ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
create_extensions,
ARRAY_SIZE(create_extensions),
@@ -454,5 +484,11 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
*data,
if
Re: [Intel-gfx] [PATCH] drm/i915/gt: limit lmem allocation size to succeed on SmallBars
On 02.06.2023 11:07, Andi Shyti wrote:
Hi Andrzej,
On Thu, Jun 01, 2023 at 04:44:50PM +0200, Andrzej Hajda wrote:
In case system is short on mappable memory (256MB on SmallBar) allocation
of two 1GB buffers will fail.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8300
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/selftest_tlb.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c
b/drivers/gpu/drm/i915/gt/selftest_tlb.c
index 4493c8518e91b2..3bd6b540257b46 100644
--- a/drivers/gpu/drm/i915/gt/selftest_tlb.c
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -190,11 +190,18 @@ pte_tlbinv(struct intel_context *ce,
static struct drm_i915_gem_object *create_lmem(struct intel_gt *gt)
{
+ struct intel_memory_region *mr =
gt->i915->mm.regions[INTEL_REGION_LMEM_0];
+ resource_size_t size = SZ_1G;
+
/*
* Allocation of largest possible page size allows to test all types
-* of pages.
+* of pages. To succeed with both allocations, especially in case of
Small
+* BAR, try to allocate no more than quarter of mappable memory.
*/
- return i915_gem_object_create_lmem(gt->i915, SZ_1G,
I915_BO_ALLOC_CONTIGUOUS);
+ if (mr && size > mr->io_size / 4)
+ size = mr->io_size / 4;
+
+ return i915_gem_object_create_lmem(gt->i915, size,
I915_BO_ALLOC_CONTIGUOUS);
makes sense to me.
Reviewed-by: Andi Shyti
Thx, patch merged.
Regards
Andrzej
Thanks,
Andi
Re: [Intel-gfx] [PATCH v15 0/1] drm/i915: Allow user to set cache at BO creation
On 31/05/2023 18:10, fei.y...@intel.com wrote:
From: Fei Yang
This series introduce a new extension for GEM_CREATE,
1. end support for set caching ioctl [PATCH 1/2]
2. add set_pat extension for gem_create [PATCH 2/2]
v2: drop one patch that was merged separately
commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
v3: rebased on https://patchwork.freedesktop.org/series/117082/
v4: fix missing unlock introduced in v3, and
solve a rebase conflict
v5: replace obj->cache_level with pat_set_by_user,
fix i915_cache_level_str() for legacy platforms.
v6: rebased on https://patchwork.freedesktop.org/series/117480/
v7: rebased on https://patchwork.freedesktop.org/series/117528/
v8: dropped the two dependent patches that has been merged
separately. Add IGT link and Tested-by (MESA).
v9: addressing comments (Andi)
v10: acked-by and tested-by MESA
v11: drop "end support for set caching ioctl" (merged)
remove tools/include/uapi/drm/i915_drm.h
v12: drop Bspec reference in comment. add to commit message instead
v13: sent to test with igt@gem_create@create-ext-set-pat
v14: sent to test with igt@gem_create@create-ext-set-pat
v15: update commit message with documentation note and t-b/a-b from
Media driver folks.
Fei Yang (1):
drm/i915: Allow user to set cache at BO creation
drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6
include/uapi/drm/i915_drm.h| 41 ++
3 files changed, 83 insertions(+)
Try with:
Test-with: 20230526172221.1438998-1-fei.y...@intel.com
That is how it is supposed to be done, to do a CI run against a test
case not yet merged that is.
Regards,
Tvrtko
Re: [Intel-gfx] [PATCH v2] drm/i915/display: Extract display init from intel_device_info_runtime_init
On Fri, 02 Jun 2023, Matt Roper wrote:
> Moving display-specific runtime info initialization into display/ makes
> the display code more self-contained and also makes it easier to call
> from the Xe driver.
>
> v2:
> - Drop unnecessary display/ prefix from #includes. (Jani)
> - Clear runtime info if fusing leaves no pipes remaining, the same as
>we do when fusing indicates the entire display controller is
>unavailable. (Jani)
> - Move adjustment of DRIVER_MODESET / DRIVER_ATOMIC after call to
>intel_display_device_info_runtime_init(); HAS_DISPLAY may have
>changed to false during the runtime init. (Jani)
>
> Cc: Jani Nikula
> Signed-off-by: Matt Roper
Reviewed-by: Jani Nikula
> ---
> .../drm/i915/display/intel_display_device.c | 127 +++
> .../drm/i915/display/intel_display_device.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.c | 154 ++
> 3 files changed, 144 insertions(+), 138 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 464df1764a86..967bac29b5d5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -9,6 +9,8 @@
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> +#include "intel_de.h"
> +#include "intel_display.h"
> #include "intel_display_device.h"
> #include "intel_display_power.h"
> #include "intel_display_reg_defs.h"
> @@ -778,3 +780,128 @@ intel_display_device_probe(struct drm_i915_private
> *i915, bool has_gmdid,
>
> return _display;
> }
> +
> +void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
> +{
> + struct intel_display_runtime_info *display_runtime =
> DISPLAY_RUNTIME_INFO(i915);
> + enum pipe pipe;
> +
> + /* Wa_14011765242: adl-s A0,A1 */
> + if (IS_ADLS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
> + for_each_pipe(i915, pipe)
> + display_runtime->num_scalers[pipe] = 0;
> + else if (DISPLAY_VER(i915) >= 11) {
> + for_each_pipe(i915, pipe)
> + display_runtime->num_scalers[pipe] = 2;
> + } else if (DISPLAY_VER(i915) >= 9) {
> + display_runtime->num_scalers[PIPE_A] = 2;
> + display_runtime->num_scalers[PIPE_B] = 2;
> + display_runtime->num_scalers[PIPE_C] = 1;
> + }
> +
> + if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
> + for_each_pipe(i915, pipe)
> + display_runtime->num_sprites[pipe] = 4;
> + else if (DISPLAY_VER(i915) >= 11)
> + for_each_pipe(i915, pipe)
> + display_runtime->num_sprites[pipe] = 6;
> + else if (DISPLAY_VER(i915) == 10)
> + for_each_pipe(i915, pipe)
> + display_runtime->num_sprites[pipe] = 3;
> + else if (IS_BROXTON(i915)) {
> + /*
> + * Skylake and Broxton currently don't expose the topmost plane
> as its
> + * use is exclusive with the legacy cursor and we only want to
> expose
> + * one of those, not both. Until we can safely expose the
> topmost plane
> + * as a DRM_PLANE_TYPE_CURSOR with all the features
> exposed/supported,
> + * we don't expose the topmost plane at all to prevent ABI
> breakage
> + * down the line.
> + */
> +
> + display_runtime->num_sprites[PIPE_A] = 2;
> + display_runtime->num_sprites[PIPE_B] = 2;
> + display_runtime->num_sprites[PIPE_C] = 1;
> + } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
> + for_each_pipe(i915, pipe)
> + display_runtime->num_sprites[pipe] = 2;
> + } else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) {
> + for_each_pipe(i915, pipe)
> + display_runtime->num_sprites[pipe] = 1;
> + }
> +
> + if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) &&
> + !(intel_de_read(i915, GU_CNTL_PROTECTED) & DEPRESENT)) {
> + drm_info(>drm, "Display not present, disabling\n");
> + goto display_fused_off;
> + }
> +
> + if (IS_GRAPHICS_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) {
> + u32 fuse_strap = intel_de_read(i915, FUSE_STRAP);
> + u32 sfuse_strap = intel_de_read(i915, SFUSE_STRAP);
> +
> + /*
> + * SFUSE_STRAP is supposed to have a bit signalling the display
> + * is fused off. Unfortunately it seems that, at least in
> + * certain cases, fused off display means that PCH display
> + * reads don't land anywhere. In that case, we read 0s.
> + *
> + * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
> + * should be set when taking over after the firmware.
> + */
> + if (fuse_strap &
Re: [Intel-gfx] [PATCH v2 2/4] drm/i915: Add getter/setter for i915_gem_object->frontbuffer
On Fri, 2023-06-02 at 19:50 +0300, Jani Nikula wrote:
> On Tue, 30 May 2023, Jouni Högander wrote:
> > Add getter/setter for i915_gem_object->frontbuffer and use it
> > instead of
> > directly touching i915_gem_object->frontbuffer frontbuffer pointer.
>
> Before going into the details (which, at a glance, look fine) I think
> we
> need to talk about the potential performance impact. I've never seen
> any
> other reason for the static inlines here than avoiding a function
> call
> when possible. Are there any other reasons? Is that a useless
> micro-optimization or something that could have an impact? On what?
I was thinking this as well. I couldn't figure out any other reason for
this being static inline than optimization. Maybe safest option would
still be just move it to i915_gem_object.h and have set_frontbuffer
there as well?
>
> BR,
> Jani.
>
> >
> > Signed-off-by: Jouni Högander
> > ---
> > .../gpu/drm/i915/display/intel_frontbuffer.c | 18 ++---
> > .../gpu/drm/i915/display/intel_frontbuffer.h | 27 ---
> > drivers/gpu/drm/i915/gem/i915_gem_object.c | 70
> > ++-
> > drivers/gpu/drm/i915/gem/i915_gem_object.h | 6 ++
> > drivers/gpu/drm/i915/i915_vma.c | 2 +-
> > 5 files changed, 81 insertions(+), 42 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
> > b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
> > index 3ce0436a0c7d..41ac65c98720 100644
> > --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
> > +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
> > @@ -237,7 +237,7 @@ static void frontbuffer_release(struct kref
> > *ref)
> > }
> > spin_unlock(>vma.lock);
> >
> > - RCU_INIT_POINTER(obj->frontbuffer, NULL);
> > + i915_gem_object_set_frontbuffer(obj, NULL);
> > spin_unlock(_bo_to_i915(obj)-
> > >display.fb_tracking.lock);
> >
> > i915_active_fini(>write);
> > @@ -250,9 +250,9 @@ struct intel_frontbuffer *
> > intel_frontbuffer_get(struct drm_i915_gem_object *obj)
> > {
> > struct drm_i915_private *i915 = intel_bo_to_i915(obj);
> > - struct intel_frontbuffer *front;
> > + struct intel_frontbuffer *front, *front_ret;
> >
> > - front = __intel_frontbuffer_get(obj);
> > + front = i915_gem_object_get_frontbuffer(obj);
> > if (front)
> > return front;
> >
> > @@ -269,16 +269,10 @@ intel_frontbuffer_get(struct
> > drm_i915_gem_object *obj)
> > I915_ACTIVE_RETIRE_SLEEPS);
> >
> > spin_lock(>display.fb_tracking.lock);
> > - if (rcu_access_pointer(obj->frontbuffer)) {
> > - kfree(front);
> > - front = rcu_dereference_protected(obj->frontbuffer,
> > true);
> > - kref_get(>ref);
> > - } else {
> > - i915_gem_object_get(obj);
> > - rcu_assign_pointer(obj->frontbuffer, front);
> > - }
> > + front_ret = i915_gem_object_set_frontbuffer(obj, front);
> > spin_unlock(>display.fb_tracking.lock);
> > -
> > + if (front_ret != front)
> > + kfree(front);
> > return front;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.h
> > b/drivers/gpu/drm/i915/display/intel_frontbuffer.h
> > index 3c474ed937fb..eeccc847331d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.h
> > +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.h
> > @@ -75,33 +75,6 @@ void intel_frontbuffer_flip(struct
> > drm_i915_private *i915,
> >
> > void intel_frontbuffer_put(struct intel_frontbuffer *front);
> >
> > -static inline struct intel_frontbuffer *
> > -__intel_frontbuffer_get(const struct drm_i915_gem_object *obj)
> > -{
> > - struct intel_frontbuffer *front;
> > -
> > - if (likely(!rcu_access_pointer(obj->frontbuffer)))
> > - return NULL;
> > -
> > - rcu_read_lock();
> > - do {
> > - front = rcu_dereference(obj->frontbuffer);
> > - if (!front)
> > - break;
> > -
> > - if (unlikely(!kref_get_unless_zero(>ref)))
> > - continue;
> > -
> > - if (likely(front == rcu_access_pointer(obj-
> > >frontbuffer)))
> > - break;
> > -
> > - intel_frontbuffer_put(front);
> > - } while (1);
> > - rcu_read_unlock();
> > -
> > - return front;
> > -}
> > -
> > struct intel_frontbuffer *
> > intel_frontbuffer_get(struct drm_i915_gem_object *obj);
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > index 46a19b099ec8..6945e903e106 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > @@ -463,7 +463,7 @@ void __i915_gem_object_flush_frontbuffer(struct
> > drm_i915_gem_object *obj,
> > {
> > struct intel_frontbuffer *front;
> >
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pxp: Optimize GET_PARAM:PXP_STATUS (rev2)
== Series Details == Series: drm/i915/pxp: Optimize GET_PARAM:PXP_STATUS (rev2) URL : https://patchwork.freedesktop.org/series/118723/ State : success == Summary == CI Bug Log - changes from CI_DRM_13222_full -> Patchwork_118723v2_full Summary --- **SUCCESS** No regressions found. Participating hosts (7 -> 7) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_118723v2_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-glk: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [FAIL][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24]) ([i915#7849] / [i915#8293]) -> ([PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk4/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk2/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk2/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk2/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk1/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk1/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk1/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk9/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk9/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk7/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk7/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk7/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk6/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk6/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk6/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk5/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk5/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk4/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk9/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk9/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk8/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk7/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk7/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk7/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk6/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk5/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk5/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk5/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk4/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk4/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v2/shard-glk4/boot.html [43]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pxp: Fix size_t format specifier in gsccs_send_message() (rev2)
== Series Details == Series: drm/i915/pxp: Fix size_t format specifier in gsccs_send_message() (rev2) URL : https://patchwork.freedesktop.org/series/118593/ State : success == Summary == CI Bug Log - changes from CI_DRM_13222_full -> Patchwork_118593v2_full Summary --- **SUCCESS** No regressions found. Participating hosts (7 -> 7) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_118593v2_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-glk: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [FAIL][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24]) ([i915#7849] / [i915#8293]) -> ([PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk1/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk1/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk2/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk2/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk2/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk4/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk4/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk5/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk6/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk6/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk7/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk7/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk7/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk9/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk9/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk8/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk8/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk7/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk7/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk7/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk6/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk6/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk5/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk5/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk4/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk4/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk4/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk3/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk3/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk3/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk2/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk2/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v2/shard-glk2/boot.html [43]:
