Re: [Intel-gfx] [PATCH v7 7/8] drm/amdgpu: Implement the is_boot_device callback function
Hi, Does anyone has the bandwidth to review this? I provide more additional information here, hope it helps. On a non-x86 multiple platform, the discrete AMDGPU fails to override the integrated one. because the PCI BAR 0 of the AMDGPU gets moved. Below is the log of 'dmesg | grep vgaarb'. So relaying on screen_info is not always reliable. [0.361928] pci :00:06.1: vgaarb: setting as boot VGA device [0.361932] pci :00:06.1: vgaarb: bridge control possible [0.361933] pci :00:06.1: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none [0.361940] pci :05:00.0: vgaarb: bridge control possible [0.361941] pci :05:00.0: vgaarb: VGA device added: decodes=io+mem,owns=none,locks=none [0.361943] vgaarb: loaded [ 11.352087] amdgpu :05:00.0: vgaarb: Set as boot device (dictated by driver) [ 11.575505] loongson :00:06.1: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=none:owns=io+mem [ 11.585100] amdgpu :05:00.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=none:owns=none dmesg | grep efifb: [ 0.356355] pci :05:00.0: BAR 0: assigned to efifb [ 0.375793] efifb: probing for efifb [ 0.375795] pci :05:00.0: BAR has moved, updating efifb address [ 0.375803] efifb: framebuffer at 0xe003000, using 976k, total 975k [ 0.375805] efifb: mode is 800x600x16, linelength=1664, pages=1 [ 0.375806] efifb: scrolling: redraw [ 0.375808] efifb: Truecolor: size=0:5:6:5, shift=0:11:5:0 efifb can also prove that "BAR has been moved" From dmesg | grep "pci :05:00.0": [ 0.356286] pci :05:00.0: [1002:699f] type 00 class 0x03 [ 0.356303] pci :05:00.0: reg 0x10: [mem 0xe002000-0xe002fff 64bit pref] [ 0.356315] pci :05:00.0: reg 0x18: [mem 0xe003000-0xe00301f 64bit pref] [ 0.356323] pci :05:00.0: reg 0x20: [io 0x4-0x400ff] [ 0.356331] pci :05:00.0: reg 0x24: [mem 0xe005310-0xe005313] [ 0.356339] pci :05:00.0: reg 0x30: [mem 0xfffe-0x pref] [ 0.356346] pci :05:00.0: enabling Extended Tags [ 0.356355] pci :05:00.0: BAR 0: assigned to efifb [ 0.356421] pci :05:00.0: supports D1 D2 [ 0.356422] pci :05:00.0: PME# supported from D1 D2 D3hot D3cold [ 0.356858] pci :05:00.0: BAR 0: assigned [mem 0xe003000-0xe003fff 64bit pref] [ 0.356866] pci :05:00.0: BAR 2: assigned [mem 0xe004000-0xe00401f 64bit pref] [ 0.356875] pci :05:00.0: BAR 5: assigned [mem 0xe004900-0xe004903] [ 0.356878] pci :05:00.0: BAR 6: assigned [mem 0xe004904-0xe004905 pref] [ 0.356889] pci :05:00.0: BAR 4: assigned [io 0x4000-0x40ff] [ 0.361940] pci :05:00.0: vgaarb: bridge control possible [ 0.361941] pci :05:00.0: vgaarb: VGA device added: decodes=io+mem,owns=none,locks=none [ 0.375795] pci :05:00.0: BAR has moved, updating efifb address We can see that the Bar 0 of AMDGPU moved from '0xe002000-0xe002fff' to '0xe003000-0xe003fff' while the fb location information recorded by the screen_info still belong to '0xe002000-0xe002fff' I suspect this is also the reason that video/aperture don't relay on the information provided by screen_info in the contrast, it require the firmware framebuffer driver(efifb) to call devm_aperture_acquire_from_firmware() function, only in this way video/aperture could record the correct information about the aperture being used the by the firmware framebuffe. While vgaarb is loaded too early, even before efifb. so that we can only relay on the pci_notifier call back to us. On 2023/6/13 11:01, Sui Jingfeng wrote: From: Sui Jingfeng [why] The vga_is_firmware_default() defined in drivers/pci/vgaarb.c is arch-dependent, it's a dummy on non-x86 architectures currently. This made VGAARB lost an important condition for the arbitration. It could still be wrong even if we remove the #ifdef and #endif guards. because the PCI bar will move (resource re-allocation). [how] The device that owns the firmware framebuffer should be the default boot device. This patch adds an arch-independent function to enforce this rule -- Jingfeng
[Intel-gfx] [RFC 3/3] drm/i915/display: Add wrapper to Compute SAD
Compute SADs that takes into account the supported rate and channel
based on the capabilities of the audio source. This wrapper function
should encapsulate the logic for determining the supported rate and
channel and should return a set of SADs that are compatible with the
source.
--v1:
- call intel_audio_compute_eld in this commit as it is defined here
--v2:
- Handle case when max frequency is less than 32k.
- remove drm prefix.
- name change for parse_sad to eld_to_sad.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_audio.c | 69 ++
drivers/gpu/drm/i915/display/intel_audio.h | 1 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +
3 files changed, 72 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index e20ffc8e9654..335bfce18994 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -794,6 +794,75 @@ bool intel_audio_compute_config(struct intel_encoder
*encoder,
return true;
}
+static unsigned int sad_to_channels(const u8 *sad)
+{
+ return 1 + (sad[0] & 0x7);
+}
+
+static inline u8 *eld_to_sad(u8 *eld)
+{
+ unsigned int ver, mnl;
+
+ ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT;
+ if (ver != 2 && ver != 31)
+ return NULL;
+
+ mnl = drm_eld_mnl(eld);
+ if (mnl > 16)
+ return NULL;
+
+ return eld + DRM_ELD_CEA_SAD(mnl, 0);
+}
+
+static u8 get_supported_freq_mask(struct intel_crtc_state *crtc_state)
+{
+ int audio_freq_hz[] = {32000, 44100, 48000, 88000, 96000, 176000,
192000};
+ u8 mask = 0;
+
+ if(crtc_state->audio.max_frequency < 32000)
+ return mask;
+
+ for (u8 index = 0; index < ARRAY_SIZE(audio_freq_hz); index++) {
+ mask |= 1 << index;
+ if (crtc_state->audio.max_frequency != audio_freq_hz[index])
+ continue;
+ else
+ break;
+ }
+
+ return mask;
+}
+
+void intel_audio_compute_eld(struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ u8 *eld, *sad, index, mask = 0;
+
+ eld = crtc_state->eld;
+ if (!eld) {
+ drm_err(&i915->drm, "failed to locate eld\n");
+ return;
+ }
+
+ sad = (u8 *)eld_to_sad(eld);
+ if (sad) {
+ mask = get_supported_freq_mask(crtc_state);
+
+ for (index = 0; index < drm_eld_sad_count(eld); index++, sad +=
3) {
+ /*
+* Respect to source restrictions. If source limit is
greater than sink
+* capabilities then follow to sink's highest
supported rate.
+*/
+ if (sad_to_channels(sad) >=
crtc_state->audio.max_channel) {
+ sad[0] &= ~0x7;
+ sad[0] |= crtc_state->audio.max_channel - 1;
+ }
+
+ sad[1] &= mask;
+ }
+ }
+}
+
/**
* intel_audio_codec_enable - Enable the audio codec for HD audio
* @encoder: encoder on which to enable audio
diff --git a/drivers/gpu/drm/i915/display/intel_audio.h
b/drivers/gpu/drm/i915/display/intel_audio.h
index 07d034a981e9..2ec7fafd9711 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.h
+++ b/drivers/gpu/drm/i915/display/intel_audio.h
@@ -14,6 +14,7 @@ struct intel_crtc_state;
struct intel_encoder;
void intel_audio_hooks_init(struct drm_i915_private *dev_priv);
+void intel_audio_compute_eld(struct intel_crtc_state *crtc_state);
bool intel_audio_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0188a600f9f5..beafeff494f8 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2403,6 +2403,8 @@ int intel_hdmi_compute_config(struct intel_encoder
*encoder,
return -EINVAL;
}
+ intel_audio_compute_eld(pipe_config);
+
return 0;
}
--
2.25.1
[Intel-gfx] [RFC 2/3] drm/i915/display: Configure and initialize HDMI audio capabilities
Initialize the source audio capabilities for HDMI in crtc_state
property by setting them to their maximum supported values,
including max_channel and max_frequency. This allows for the
calculation of HDMI audio source capabilities with respect to
the available mode bandwidth. These capabilities encompass
parameters such as supported frequency and channel configurations.
--v1:
- Refactor max_channel and max_rate to this commit as it is being
initialised here
- Remove call for intel_audio_compute_eld to avoid any regression while
merge. instead call it in different commit when it is defined.
- Use int instead of unsigned int for max_channel and max_frequecy
- Update commit message and header
Signed-off-by: Mitul Golani
---
.../drm/i915/display/intel_display_types.h| 6
drivers/gpu/drm/i915/display/intel_hdmi.c | 35 +++
drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
3 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index ebd147180a6e..74eee87d2df1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1131,6 +1131,12 @@ struct intel_crtc_state {
struct {
bool has_audio;
+
+ /* Audio rate in Hz */
+ int max_frequency;
+
+ /* Number of audio channels */
+ int max_channel;
} audio;
/*
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 32157bef2eef..0188a600f9f5 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2277,6 +2277,40 @@ bool intel_hdmi_compute_has_hdmi_sink(struct
intel_encoder *encoder,
!intel_hdmi_is_cloned(crtc_state);
}
+static unsigned int calc_audio_bw(int channel, int frequency)
+{
+ int bits_per_sample = 32;
+ unsigned int bandwidth = channel * frequency * bits_per_sample;
+ return bandwidth;
+}
+
+void
+intel_hdmi_audio_compute_config(struct intel_crtc_state *pipe_config)
+{
+ struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ int num_of_channel, aud_rates[7] = {192000, 176000, 96000, 88000,
48000, 44100, 32000};
+ unsigned int audio_req_bandwidth, available_blank_bandwidth, vblank,
hblank;
+
+ hblank = adjusted_mode->htotal - adjusted_mode->hdisplay;
+ vblank = adjusted_mode->vtotal - adjusted_mode->vdisplay;
+ available_blank_bandwidth = hblank * vblank *
+ drm_mode_vrefresh(adjusted_mode) *
pipe_config->pipe_bpp;
+ for (num_of_channel = 8; num_of_channel > 0; num_of_channel--) {
+ for (int index = 0; index < 7; index++) {
+ audio_req_bandwidth = calc_audio_bw(num_of_channel,
+ aud_rates[index]);
+ if (audio_req_bandwidth < available_blank_bandwidth) {
+ pipe_config->audio.max_frequency =
aud_rates[index];
+ pipe_config->audio.max_channel = num_of_channel;
+ return;
+ }
+ }
+ }
+
+ pipe_config->audio.max_frequency = 0;
+ pipe_config->audio.max_channel = 0;
+}
+
int intel_hdmi_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
@@ -2344,6 +2378,7 @@ int intel_hdmi_compute_config(struct intel_encoder
*encoder,
pipe_config->hdmi_high_tmds_clock_ratio = true;
}
}
+ intel_hdmi_audio_compute_config(pipe_config);
intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h
b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 6b39df38d57a..6df303daf348 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -27,6 +27,7 @@ void intel_hdmi_init_connector(struct intel_digital_port
*dig_port,
bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state);
+void intel_hdmi_audio_compute_config(struct intel_crtc_state *pipe_config);
int intel_hdmi_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state);
--
2.25.1
[Intel-gfx] [RFC 1/3] drm/i915/hdmi: Optimize source audio parameter handling
To enhance the relationship between the has_audio and the source
audio parameter, create a separate crtc_state audio property and
add the has_audio parameter into it. Additionally, update the
access of the has_audio parameter from the crtc_state pointer as
it is wrapped under the audio. These modifications establish
a more cohesive structure and improve the accessibility and
organization of the audio-related parameters within the codebase.
--v1:
- add audio instead of audio_config in crtc_state
- add only has_audio then update related parameter access
- refactor other member to different commit where it is being used
- update commit message and header
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/g4x_dp.c| 4 ++--
drivers/gpu/drm/i915/display/g4x_hdmi.c | 16
drivers/gpu/drm/i915/display/intel_audio.c | 6 +++---
drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++---
.../gpu/drm/i915/display/intel_crtc_state_dump.c | 4 ++--
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
.../gpu/drm/i915/display/intel_display_types.h | 6 +++---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c| 2 +-
drivers/gpu/drm/i915/display/intel_sdvo.c| 10 +-
12 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
b/drivers/gpu/drm/i915/display/g4x_dp.c
index 112d91d81fdc..19f94f3331ee 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -345,7 +345,7 @@ static void intel_dp_get_config(struct intel_encoder
*encoder,
tmp = intel_de_read(dev_priv, intel_dp->output_reg);
- pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
+ pipe_config->audio.has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port !=
PORT_A;
if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
u32 trans_dp = intel_de_read(dev_priv,
@@ -625,7 +625,7 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp,
* fail when the power sequencer is freshly used for this port.
*/
intel_dp->DP |= DP_PORT_EN;
- if (crtc_state->has_audio)
+ if (crtc_state->audio.has_audio)
intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 5c187e6e0472..363e21156304 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -178,7 +178,7 @@ static void intel_hdmi_get_config(struct intel_encoder
*encoder,
pipe_config->has_infoframe = true;
if (tmp & HDMI_AUDIO_ENABLE)
- pipe_config->has_audio = true;
+ pipe_config->audio.has_audio = true;
if (!HAS_PCH_SPLIT(dev_priv) &&
tmp & HDMI_COLOR_RANGE_16_235)
@@ -224,7 +224,7 @@ static void g4x_hdmi_enable_port(struct intel_encoder
*encoder,
temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
temp |= SDVO_ENABLE;
- if (pipe_config->has_audio)
+ if (pipe_config->audio.has_audio)
temp |= HDMI_AUDIO_ENABLE;
intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
@@ -240,7 +240,7 @@ static void g4x_enable_hdmi(struct intel_atomic_state
*state,
g4x_hdmi_enable_port(encoder, pipe_config);
- drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio &&
+ drm_WARN_ON(&dev_priv->drm, pipe_config->audio.has_audio &&
!pipe_config->has_hdmi_sink);
intel_audio_codec_enable(encoder, pipe_config, conn_state);
}
@@ -258,7 +258,7 @@ static void ibx_enable_hdmi(struct intel_atomic_state
*state,
temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
temp |= SDVO_ENABLE;
- if (pipe_config->has_audio)
+ if (pipe_config->audio.has_audio)
temp |= HDMI_AUDIO_ENABLE;
/*
@@ -293,7 +293,7 @@ static void ibx_enable_hdmi(struct intel_atomic_state
*state,
intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
}
- drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio &&
+ drm_WARN_ON(&dev_priv->drm, pipe_config->audio.has_audio &&
!pipe_config->has_hdmi_sink);
intel_audio_codec_enable(encoder, pipe_config, conn_state);
}
@@ -313,7 +313,7 @@ static void cpt_enable_hdmi(struct intel_atomic_state
*state,
temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
temp |= SDVO_ENABLE;
- if (pipe_config->has_audio)
+ if (pipe_config->audio.has_audio)
temp |= HDMI_AUDIO_ENABLE;
/*
@@ -348,7 +348,7 @@ static void cpt_enable_hdmi(struct intel_atomic_state
*state
[Intel-gfx] [RFC 0/3] Get optimal audio frequency and channels
Currently we do not check if there is enough bandwidth for audio, and what channels and freq it can really support. Also sometimes there can be HW constraints e.g. GLK where audio channels supported are only 2. https://patchwork.freedesktop.org/series/107647/ Obtain the optimal audio rate and channel based on available display timing constraints. This can be achieved by: - Retrieve the supported channel and rate information from SADs - Adding audio-related config parameters in the CRTC state, such as audio support, rate, and channel. - Initializing the audio config parameters with the maximum supported rate and channel by the audio source. - Computing the SADs based on the audio source's capabilities. Signed-off-by: Mitul Golani Mitul Golani (3): drm/i915/hdmi: Optimize source audio parameter handling drm/i915/display: Configure and initialize HDMI audio capabilities drm/i915/display: Add wrapper to Compute SAD drivers/gpu/drm/i915/display/g4x_dp.c | 4 +- drivers/gpu/drm/i915/display/g4x_hdmi.c | 16 ++-- drivers/gpu/drm/i915/display/intel_audio.c| 75 ++- drivers/gpu/drm/i915/display/intel_audio.h| 1 + drivers/gpu/drm/i915/display/intel_cdclk.c| 6 +- .../drm/i915/display/intel_crtc_state_dump.c | 4 +- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 4 +- .../drm/i915/display/intel_display_types.h| 12 ++- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 39 +- drivers/gpu/drm/i915/display/intel_hdmi.h | 1 + drivers/gpu/drm/i915/display/intel_sdvo.c | 10 +-- 14 files changed, 146 insertions(+), 32 deletions(-) -- 2.25.1
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Replace acronym with full platform name in defines.
== Series Details ==
Series: Replace acronym with full platform name in defines.
URL : https://patchwork.freedesktop.org/series/119361/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
INSTALL libsubcmd_headers
CC [M] drivers/gpu/drm/i915/display/intel_cdclk.o
drivers/gpu/drm/i915/display/intel_cdclk.c: In function
‘intel_init_cdclk_hooks’:
drivers/gpu/drm/i915/display/intel_cdclk.c:3562:3: error: this ‘if’ clause does
not guard... [-Werror=misleading-indentation]
3562 | if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
| ^~
drivers/gpu/drm/i915/display/intel_cdclk.c:3564:4: note: ...this statement, but
the latter is misleadingly indented as if it were guarded by the ‘if’
3564 |dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c: At top level:
drivers/gpu/drm/i915/display/intel_cdclk.c:3572:4: error: expected identifier
or ‘(’ before ‘else’
3572 | } else if (IS_ROCKETLAKE(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3575:4: error: expected identifier
or ‘(’ before ‘else’
3575 | } else if (DISPLAY_VER(dev_priv) >= 12) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3578:4: error: expected identifier
or ‘(’ before ‘else’
3578 | } else if (IS_JASPERLAKE_EHL(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3581:4: error: expected identifier
or ‘(’ before ‘else’
3581 | } else if (DISPLAY_VER(dev_priv) >= 11) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3584:4: error: expected identifier
or ‘(’ before ‘else’
3584 | } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3590:4: error: expected identifier
or ‘(’ before ‘else’
3590 | } else if (DISPLAY_VER(dev_priv) == 9) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3592:4: error: expected identifier
or ‘(’ before ‘else’
3592 | } else if (IS_BROADWELL(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3594:4: error: expected identifier
or ‘(’ before ‘else’
3594 | } else if (IS_HASWELL(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3596:4: error: expected identifier
or ‘(’ before ‘else’
3596 | } else if (IS_CHERRYVIEW(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3598:4: error: expected identifier
or ‘(’ before ‘else’
3598 | } else if (IS_VALLEYVIEW(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3600:4: error: expected identifier
or ‘(’ before ‘else’
3600 | } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3602:4: error: expected identifier
or ‘(’ before ‘else’
3602 | } else if (IS_IRONLAKE(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3604:4: error: expected identifier
or ‘(’ before ‘else’
3604 | } else if (IS_GM45(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3606:4: error: expected identifier
or ‘(’ before ‘else’
3606 | } else if (IS_G45(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3608:4: error: expected identifier
or ‘(’ before ‘else’
3608 | } else if (IS_I965GM(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3610:4: error: expected identifier
or ‘(’ before ‘else’
3610 | } else if (IS_I965G(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3612:4: error: expected identifier
or ‘(’ before ‘else’
3612 | } else if (IS_PINEVIEW(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3614:4: error: expected identifier
or ‘(’ before ‘else’
3614 | } else if (IS_G33(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3616:4: error: expected identifier
or ‘(’ before ‘else’
3616 | } else if (IS_I945GM(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3618:4: error: expected identifier
or ‘(’ before ‘else’
3618 | } else if (IS_I945G(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3620:4: error: expected identifier
or ‘(’ before ‘else’
3620 | } else if (IS_I915GM(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3622:4: error: expected identifier
or ‘(’ before ‘else’
3622 | } else if (IS_I915G(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3624:4: error: expected identifier
or ‘(’ before ‘else’
3624 | } else if (IS_I865G(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3626:4: error: expected identifier
or ‘(’ before ‘else’
3626 | } else if (IS_I85X(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3628:4: error: expected identifier
or ‘(’ before ‘else’
3628 | } else if (IS_I845G(dev_priv)) {
|^~~~
drivers/gpu/drm/i915/
[Intel-gfx] [PATCH 11/11] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines
From: Anusha Srivatsa
Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 831d1258ea3f..d4d4bf72bc6d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3562,7 +3562,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
- } else if (IS_ADLP_RPLU(dev_priv)) {
+ } else if (IS_ALDERLAKE_RPLU(dev_priv)) {
dev_priv->display.cdclk.table = rplu_cdclk_table;
dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
} else {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1dad0c9b4f30..c6ad78381dd1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -591,7 +591,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
#define IS_ALDERLAKE_P_RPLP(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_RPLU(i915) \
+#define IS_ALDERLAKE_RPLU(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
#define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \
(INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
--
2.34.1
[Intel-gfx] [PATCH 09/11] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines
From: Anusha Srivatsa
Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_step.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
index 852bea0208ce..cc9569af7f0c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
@@ -94,7 +94,7 @@ static int guc_hwconfig_fill_buffer(struct intel_guc *guc,
struct intel_hwconfig
static bool has_table(struct drm_i915_private *i915)
{
- if (IS_ALDERLAKE_P(i915) && !IS_ADLP_N(i915))
+ if (IS_ALDERLAKE_P(i915) && !IS_ALDERLAKE_P_N(i915))
return true;
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
return true;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index d408856ae4c0..dfb2837a3ed4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -279,7 +279,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct
intel_uc_fw *uc_fw)
* ADL-S, otherwise the GuC might attempt to fetch a config table that
* does not exist.
*/
- if (IS_ADLP_N(i915))
+ if (IS_ALDERLAKE_P_N(i915))
p = INTEL_ALDERLAKE_S;
GEM_BUG_ON(uc_fw->type >= ARRAY_SIZE(blobs_all));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bff9218b9f78..d3ce6ed3be86 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -587,7 +587,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
#define IS_ADLS_RPLS(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_N(i915) \
+#define IS_ALDERLAKE_P_N(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
#define IS_ALDERLAKE_P_RPLP(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 9072f4ccd3c1..fe447063a064 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -192,7 +192,7 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_XEHPSDV(i915)) {
revids = xehpsdv_revids;
size = ARRAY_SIZE(xehpsdv_revids);
- } else if (IS_ADLP_N(i915)) {
+ } else if (IS_ALDERLAKE_P_N(i915)) {
revids = adlp_n_revids;
size = ARRAY_SIZE(adlp_n_revids);
} else if (IS_ALDERLAKE_P_RPLP(i915)) {
--
2.34.1
[Intel-gfx] [PATCH 10/11] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines
From: Anusha Srivatsa
Driver refers to the platfrom Alderlake S as ADLS in places
and ALDERLAKE_S in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 6 +++---
drivers/gpu/drm/i915/intel_step.c | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 3fd30e7f0062..f3090b8afc60 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -797,7 +797,7 @@ void intel_display_device_info_runtime_init(struct
drm_i915_private *i915)
enum pipe pipe;
/* Wa_14011765242: adl-s A0,A1 */
- if (IS_ADLS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
+ if (IS_ALDERLAKE_S_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
for_each_pipe(i915, pipe)
display_runtime->num_scalers[pipe] = 0;
else if (DISPLAY_VER(i915) >= 11) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 18250fb64bd8..eb28705b88bd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -43,7 +43,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
}
/* Intermediate platforms are HuC authentication only */
- if (IS_ALDERLAKE_S(i915) && !IS_ADLS_RPLS(i915)) {
+ if (IS_ALDERLAKE_S(i915) && !IS_ALDERLAKE_S_RPLS(i915)) {
i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
return;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d3ce6ed3be86..1dad0c9b4f30 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -585,7 +585,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
#define IS_DG2_G12(i915) \
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
-#define IS_ADLS_RPLS(i915) \
+#define IS_ALDERLAKE_S_RPLS(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
#define IS_ALDERLAKE_P_N(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
@@ -669,11 +669,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ROCKETLAKE_DISPLAY_STEP(p, since, until) \
(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
-#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_S_DISPLAY_STEP(__i915, since, until) \
(IS_ALDERLAKE_S(__i915) && \
IS_DISPLAY_STEP(__i915, since, until))
-#define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_GRAPHICS_STEP(__i915, since, until) \
(IS_ALDERLAKE_S(__i915) && \
IS_GRAPHICS_STEP(__i915, since, until))
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index fe447063a064..f410aa2a8077 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -201,7 +201,7 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ALDERLAKE_P(i915)) {
revids = adlp_revids;
size = ARRAY_SIZE(adlp_revids);
- } else if (IS_ADLS_RPLS(i915)) {
+ } else if (IS_ALDERLAKE_S_RPLS(i915)) {
revids = adls_rpls_revids;
size = ARRAY_SIZE(adls_rpls_revids);
} else if (IS_ALDERLAKE_S(i915)) {
--
2.34.1
[Intel-gfx] [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
From: Anusha Srivatsa
Driver refers to the platfrom Alderlake P as ADLP in places
and ALDERLAKE_P in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 8
drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h| 4 ++--
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 2acfa0435675..831d1258ea3f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3559,7 +3559,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
/* Wa_22011320316:adl-p[a0] */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+ if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
} else if (IS_ADLP_RPLU(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c6d376d414b8..47fe8311067e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct
drm_i915_private *i915, struct inte
{
u32 val;
- if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
+ if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
pll->info->id != DPLL_ID_ICL_DPLL0)
return;
/*
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index f61d39d2b0fc..00c98c2b4324 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -639,7 +639,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
}
/* Wa_22012278275:adl-p */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
+ if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
static const u8 map[] = {
2, /* 5 lines */
1, /* 6 lines */
@@ -807,7 +807,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
return;
/* Wa_16011303918:adl-p */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
return;
/*
@@ -975,7 +975,7 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
return false;
}
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+ if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in
this stepping\n");
return false;
}
@@ -1033,7 +1033,7 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
/* Wa_16011303918:adl-p */
if (crtc_state->vrr.enable &&
- IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+ IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
drm_dbg_kms(&dev_priv->drm,
"PSR2 not enabled, not compatible with HW stepping
+ VRR\n");
return false;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 25b06ced9ce7..2458a9ea25ba 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private
*i915,
return false;
/* Wa_22011186057 */
- if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+ if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
return false;
if (DISPLAY_VER(i915) >= 11)
@@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct
drm_i915_private *i915,
return false;
/* Wa_22011186057 */
- if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+ if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
return false;
/* Wa_14013215631 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3c4a66f1a7ba..08e14cf225b5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -677,11 +677,11 @@ IS_SUBPLATFORM(co
[Intel-gfx] [PATCH 08/11] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines
From: Anusha Srivatsa
Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_step.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 08e14cf225b5..bff9218b9f78 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -589,7 +589,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
#define IS_ADLP_N(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
-#define IS_ADLP_RPLP(i915) \
+#define IS_ALDERLAKE_P_RPLP(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
#define IS_ADLP_RPLU(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 847c7de50e1f..9072f4ccd3c1 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -195,7 +195,7 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ADLP_N(i915)) {
revids = adlp_n_revids;
size = ARRAY_SIZE(adlp_n_revids);
- } else if (IS_ADLP_RPLP(i915)) {
+ } else if (IS_ALDERLAKE_P_RPLP(i915)) {
revids = adlp_rplp_revids;
size = ARRAY_SIZE(adlp_rplp_revids);
} else if (IS_ALDERLAKE_P(i915)) {
--
2.34.1
[Intel-gfx] [PATCH 06/11] drm/i915/SKL: s/SKL/SKYLAKE for platform/subplatform defines
Follow consistent naming convention. Replace SKL with
SKYLAKE.
Signed-off-by: Dnyaneshwar Bhadane
---
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_workarounds.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h| 14 +++---
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 84b09d188d2a..ab84d003232c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1724,9 +1724,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder
*encoder)
encoder->get_buf_trans = kbl_u_get_buf_trans;
} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) ||
IS_KABYLAKE(i915)) {
encoder->get_buf_trans = kbl_get_buf_trans;
- } else if (IS_SKL_ULX(i915)) {
+ } else if (IS_SKYLAKE_ULX(i915)) {
encoder->get_buf_trans = skl_y_get_buf_trans;
- } else if (IS_SKL_ULT(i915)) {
+ } else if (IS_SKYLAKE_ULT(i915)) {
encoder->get_buf_trans = skl_u_get_buf_trans;
} else if (IS_SKYLAKE(i915)) {
encoder->get_buf_trans = skl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b632fb5592a8..10a4e0fc23ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1173,7 +1173,7 @@ skl_gt_workarounds_init(struct intel_gt *gt, struct
i915_wa_list *wal)
GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
/* WaInPlaceDecompressionHang:skl */
- if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
+ if (IS_SKYLAKE_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
wa_write_or(wal,
GEN9_GAMT_ECO_REG_RW_IA,
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f19915115cff..3c4a66f1a7ba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -610,19 +610,19 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
/* ULX machines are also considered ULT. */
#define IS_HSW_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_ULT(i915) \
+#define IS_SKYLAKE_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_SKL_ULX(i915) \
+#define IS_SKYLAKE_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
#define IS_KABYLAKE_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
#define IS_KABYLAKE_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_GT2(i915) (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \
INTEL_INFO(i915)->gt == 2)
-#define IS_SKL_GT3(i915) (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \
INTEL_INFO(i915)->gt == 3)
-#define IS_SKL_GT4(i915) (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \
INTEL_INFO(i915)->gt == 4)
#define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \
INTEL_INFO(i915)->gt == 2)
@@ -650,7 +650,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_TIGERLAKE_UY(i915) \
IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
-#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) &&
IS_GRAPHICS_STEP(p, since, until))
+#define IS_SKYLAKE_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) &&
IS_GRAPHICS_STEP(p, since, until))
#define IS_KABYLAKE_GRAPHICS_STEP(i915, since, until) \
(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
@@ -801,7 +801,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
/* WaRsDisableCoarsePowerGating:skl,cnl */
#define NEEDS_WaRsDisableCoarsePowerGating(i915) \
- (IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
+ (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming.
--
2.34.1
[Intel-gfx] [PATCH 05/11] drm/i915/KBL: s/KBL/KABYLAKE for platform/subplatform defines
Follow consistent naming convention. Replace KBL with
KABYLAKE.
Signed-off-by: Dnyaneshwar Bhadane
---
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 4 ++--
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c| 6 +++---
drivers/gpu/drm/i915/i915_drv.h| 12 ++--
drivers/gpu/drm/i915/intel_clock_gating.c | 4 ++--
5 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 9e34cc103aeb..84b09d188d2a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1718,9 +1718,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder
*encoder)
encoder->get_buf_trans = icl_get_mg_buf_trans;
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
encoder->get_buf_trans = bxt_get_buf_trans;
- } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
+ } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) ||
IS_KABYLAKE_ULX(i915)) {
encoder->get_buf_trans = kbl_y_get_buf_trans;
- } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) {
+ } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) ||
IS_KABYLAKE_ULT(i915)) {
encoder->get_buf_trans = kbl_u_get_buf_trans;
} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) ||
IS_KABYLAKE(i915)) {
encoder->get_buf_trans = kbl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index eb72610a8588..ec0771dc662a 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -43,7 +43,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
vf_flush_wa = true;
/* WaForGAMHang:kbl */
- if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
+ if (IS_KABYLAKE_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
dc_flush_wa = true;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a62dcbc2f901..b632fb5592a8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -584,7 +584,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs
*engine,
gen9_ctx_workarounds_init(engine, wal);
/* WaToEnableHwFixForPushConstHWBug:kbl */
- if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
+ if (IS_KABYLAKE_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
@@ -1185,7 +1185,7 @@ kbl_gt_workarounds_init(struct intel_gt *gt, struct
i915_wa_list *wal)
gen9_gt_workarounds_init(gt, wal);
/* WaDisableDynamicCreditSharing:kbl */
- if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
+ if (IS_KABYLAKE_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
wa_write_or(wal,
GAMT_CHKN_BIT_REG,
GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
@@ -2933,7 +2933,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
struct drm_i915_private *i915 = engine->i915;
/* WaKBLVECSSemaphoreWaitPoll:kbl */
- if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
+ if (IS_KABYLAKE_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
wa_write(wal,
RING_SEMA_WAIT_POLL(engine->mmio_base),
1);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3981b890f053..f19915115cff 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -614,9 +614,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
#define IS_SKL_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_KBL_ULT(i915) \
+#define IS_KABYLAKE_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_KBL_ULX(i915) \
+#define IS_KABYLAKE_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
#define IS_SKL_GT2(i915) (IS_SKYLAKE(i915) && \
INTEL_INFO(i915)->gt == 2)
@@ -624,9 +624,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
INTEL_INFO(i915)->gt == 3)
#define IS_SKL_GT4(i915) (IS_SKYLAKE(i915) && \
INTEL_INFO(i915)->gt == 4)
-#define IS_KBL_GT2(i915) (IS_KABYLAKE(i915) && \
+#define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \
[Intel-gfx] [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines
Follow consistent naming convention. Replace JSL with
JASPERLAKE.
Signed-off-by: Dnyaneshwar Bhadane
---
drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
drivers/gpu/drm/i915/display/intel_combo_phy.c | 6 +++---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dp.c| 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 18 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h| 10 +-
drivers/gpu/drm/i915/intel_step.c | 2 +-
drivers/gpu/drm/i915/soc/intel_pch.c | 6 +++---
15 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 59a2a289d9be..70f045da3bac 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -444,7 +444,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct
intel_encoder *encoder)
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
- if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
+ if (IS_JASPERLAKE_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >=
12)) {
intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
@@ -553,7 +553,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
}
}
- if (IS_JSL_EHL(dev_priv)) {
+ if (IS_JASPERLAKE_EHL(dev_priv)) {
for_each_dsi_phy(phy, intel_dsi->phys)
intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4207863b7b2a..2acfa0435675 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3147,7 +3147,7 @@ static int intel_compute_max_dotclk(struct
drm_i915_private *dev_priv)
*/
void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
{
- if (IS_JSL_EHL(dev_priv)) {
+ if (IS_JASPERLAKE_EHL(dev_priv)) {
if (dev_priv->display.cdclk.hw.ref == 24000)
dev_priv->display.cdclk.max_cdclk_freq = 552000;
else
@@ -3575,7 +3575,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
} else if (DISPLAY_VER(dev_priv) >= 12) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = icl_cdclk_table;
- } else if (IS_JSL_EHL(dev_priv)) {
+ } else if (IS_JASPERLAKE_EHL(dev_priv)) {
dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
dev_priv->display.cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 922a6d87b553..37bd6d31ced1 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -141,7 +141,7 @@ static bool has_phy_misc(struct drm_i915_private *i915,
enum phy phy)
if (IS_ALDERLAKE_S(i915))
return phy == PHY_A;
- else if (IS_JSL_EHL(i915) ||
+ else if (IS_JASPERLAKE_EHL(i915) ||
IS_ROCKETLAKE(i915) ||
IS_DG1(i915))
return phy < PHY_C;
@@ -242,7 +242,7 @@ static bool icl_combo_phy_verify_state(struct
drm_i915_private *dev_priv,
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
IREFGEN, IREFGEN);
- if (IS_JSL_EHL(dev_priv)) {
+ if (IS_JASPERLAKE_EHL(dev_priv)) {
if (ehl_vbt_ddi_d_present(dev_priv))
expected_val = ICL_PHY_MISC_MUX_DDID;
@@ -333,7 +333,7 @@ static void icl_combo_phys_init(struct drm_i915_private
*dev_priv)
* "internal" child devices.
*/
val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
- if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
+ if (IS_JASPERLAKE_EHL(dev_priv) && phy == PHY_A) {
val &= ~ICL_PHY_MISC_MUX_DDID;
if (ehl_vbt_ddi_d_present(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drive
[Intel-gfx] [PATCH 02/11] drm/i915/MTL: s/MTL/METEORLAKE for platform/subplatform defines
Follow consistent naming convention. Replace MTL with
METEORLAKE
Signed-off-by: Dnyaneshwar Bhadane
---
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 10 ++---
.../drm/i915/display/skl_universal_plane.c| 4 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8 ++--
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 4 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 44 +--
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 4 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 6 +--
drivers/gpu/drm/i915/i915_perf.c | 4 +-
15 files changed, 51 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7f8b2d7713c7..6358a8b26172 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
intel_atomic_state *state,
/* Wa_14016291713 */
if ((IS_DISPLAY_VER(i915, 12, 13) ||
-IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
crtc_state->has_psr) {
plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d363634..8c3158b188ef 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
&pmdemand_state->base,
&intel_pmdemand_funcs);
- if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+ if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
/* Wa_14016740474 */
intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
DMD_RSP_TIMEOUT_DISABLE);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index d58ed9b62e67..06b464229efe 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
bool set_wa_bit = false;
/* Wa_14015648006 */
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+ if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
IS_DISPLAY_VER(dev_priv, 11, 13))
set_wa_bit |= crtc_state->wm_level_disabled;
@@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
* All supported adlp panels have 1-based X granularity, this
may
* cause issues if non-supported panels are used.
*/
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
MTL_CHICKEN_TRANS(cpu_transcoder), 0,
ADLP_1_BASED_X_GRANULARITY);
else if (IS_ALDERLAKE_P(dev_priv))
@@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
ADLP_1_BASED_X_GRANULARITY);
/* Wa_16012604467:adlp,mtl[a0,b0] */
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
if (intel_dp->psr.psr2_enabled) {
/* Wa_16012604467:adlp,mtl[a0,b0] */
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -1963,7 +1963,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state
*state,
goto skip_sel_fetch_set_loop;
/* Wa_14014971492 */
- if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+ if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
IS_ALD
[Intel-gfx] [PATCH 03/11] drm/i915/TGL: s/RKL/ROCKETLAKE for platform/subplatform defines
Follow consistent naming convention. Replace RKL with ROCKETLAKE. Signed-off-by: Dnyaneshwar Bhadane --- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- drivers/gpu/drm/i915/i915_drv.h| 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index db5437043904..c65505b82065 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1586,7 +1586,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) return; if (IS_ALDERLAKE_S(dev_priv) || - IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) + IS_ROCKETLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) /* Wa_1409767108 */ table = wa_1409767108_buddy_page_masks; else diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 472a36cf1a72..3e9567f9ad15 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -666,7 +666,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, (IS_TIGERLAKE(__i915) && \ IS_DISPLAY_STEP(__i915, since, until)) -#define IS_RKL_DISPLAY_STEP(p, since, until) \ +#define IS_ROCKETLAKE_DISPLAY_STEP(p, since, until) \ (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until)) #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \ -- 2.34.1
[Intel-gfx] [PATCH 01/11] drm/i915/TGL: s/TGL/TIGERLAKE for platform/subplatform defines
Follow consistent naming convention. Replace TGL with
TIGERLAKE.
Signed-off-by: Dnyaneshwar Bhadane
---
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 2 +-
drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h| 4 ++--
drivers/gpu/drm/i915/intel_step.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index b7d20485bde5..9e34cc103aeb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1390,7 +1390,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
if (crtc_state->port_clock > 27) {
- if (IS_TGL_UY(dev_priv)) {
+ if (IS_TIGERLAKE_UY(dev_priv)) {
return
intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2,
n_entries);
} else {
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6b01a0b68b97..26def9cb86e4 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2196,7 +2196,7 @@ static bool gen12_plane_has_mc_ccs(struct
drm_i915_private *i915,
/* Wa_14010477008 */
if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
- IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
+ IS_TIGERLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
return false;
/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b4cf6f0f636d..0f30dc890209 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -647,7 +647,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ICL_WITH_PORT_F(i915) \
IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
-#define IS_TGL_UY(i915) \
+#define IS_TIGERLAKE_UY(i915) \
IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) &&
IS_GRAPHICS_STEP(p, since, until))
@@ -662,7 +662,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
-#define IS_TGL_DISPLAY_STEP(__i915, since, until) \
+#define IS_TIGERLAKE_DISPLAY_STEP(__i915, since, until) \
(IS_TIGERLAKE(__i915) && \
IS_DISPLAY_STEP(__i915, since, until))
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 8a9ff6227e53..67054c87bb5f 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -213,7 +213,7 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ROCKETLAKE(i915)) {
revids = rkl_revids;
size = ARRAY_SIZE(rkl_revids);
- } else if (IS_TGL_UY(i915)) {
+ } else if (IS_TIGERLAKE_UY(i915)) {
revids = tgl_uy_revids;
size = ARRAY_SIZE(tgl_uy_revids);
} else if (IS_TIGERLAKE(i915)) {
--
2.34.1
[Intel-gfx] [PATCH 00/11] Replace acronym with full platform name in defines.
Replace all occurences of ADL with ALDERLAKE, TGL with TIGERLAKE, MTL with METEORLAKE, RKL with ROCKETLAKE, JSL with JASPERLAKE, KBL with KABYLAKE and SKL with SKYLAKE in platform and subplatform defines. This way there is a consistent pattern to how platforms are referred. While the change is minor and could be combined to have lesser patches, splitting to per subpaltform for easier cherrypicks, if needed. Anusha Srivatsa (5): drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines Dnyaneshwar Bhadane (6): drm/i915/TGL: s/TGL/TIGERLAKE for platform/subplatform defines drm/i915/MTL: s/MTL/METEORLAKE for platform/subplatform defines drm/i915/TGL: s/RKL/ROCKETLAKE for platform/subplatform defines drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines drm/i915/KBL: s/KBL/KABYLAKE for platform/subplatform defines drm/i915/SKL: s/SKL/SKYLAKE for platform/subplatform defines drivers/gpu/drm/i915/display/icl_dsi.c| 4 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 8 +-- .../gpu/drm/i915/display/intel_combo_phy.c| 6 +- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +- .../drm/i915/display/intel_ddi_buf_trans.c| 10 +-- drivers/gpu/drm/i915/display/intel_display.c | 6 +- .../drm/i915/display/intel_display_device.c | 2 +- .../drm/i915/display/intel_display_power.c| 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 +++--- drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 20 +++--- .../drm/i915/display/skl_universal_plane.c| 10 +-- drivers/gpu/drm/i915/gem/i915_gem_object.c| 2 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 10 +-- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- .../drm/i915/gt/intel_execlists_submission.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 4 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +- drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 54 drivers/gpu/drm/i915/gt/uc/intel_guc.c| 4 +- .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 64 +-- drivers/gpu/drm/i915/i915_perf.c | 4 +- drivers/gpu/drm/i915/intel_clock_gating.c | 4 +- drivers/gpu/drm/i915/intel_step.c | 10 +-- drivers/gpu/drm/i915/soc/intel_pch.c | 6 +- 34 files changed, 143 insertions(+), 143 deletions(-) -- 2.34.1
Re: [Intel-gfx] [PATCH v2] drm/i915/display/lspcon: Increase LSPCON mode settle timeout
On 6/15/2023 5:24 AM, Pablo Ceballos wrote: This is to eliminate all cases of "*ERROR* LSPCON mode hasn't settled", followed by link training errors. Intel engineers recommended increasing this timeout and that does resolve the issue. On some CometLake-based device designs the Parade PS175 takes more than 400ms to settle in PCON mode. 100 reboot trials on one device resulted in a median settle time of 440ms and a maximum of 444ms. Even after increasing the timeout to 500ms, 2% of devices still had this error. So this increases the timeout to 800ms. In one of the gitlab issue, it was tried with 1000ms as well, situation did improve, but issue didn't get fully resolved. [1]. I was wondering if trying to set LS/PCON mode multiple time will have any effect. Unfortunately I do not have access to machine with Parade LSPCON chip, had suggested in yet another git lab issue [2]. I have a patch for this, sent to try-bot, though not sent to intel-gfx yet [3]. The timeout value was already increased from 100 ms to 400 ms earlier too. If there is indeed no other way, perhaps need to have this solution. [1] https://gitlab.freedesktop.org/drm/intel/-/issues/4516#note_1406500 [2] https://gitlab.freedesktop.org/drm/intel/-/issues/4458#note_1922654 [3] Patch : https://patchwork.freedesktop.org/patch/538819/?series=118208&rev=1 Regards, Ankit Signed-off-by: Pablo Ceballos --- Changelog since v1: - Added more details in the commit message drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index bb3b5355a0d9..d7299fdc43ad 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -167,7 +167,7 @@ static enum drm_lspcon_mode lspcon_wait_mode(struct intel_lspcon *lspcon, drm_dbg_kms(&i915->drm, "Waiting for LSPCON mode %s to settle\n", lspcon_mode_name(mode)); - wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 400); + wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 800); if (current_mode != mode) drm_err(&i915->drm, "LSPCON mode hasn't settled\n");
Re: [Intel-gfx] [RFC 3/3] drm/i915/display: Add wrapper to Compute SAD
Hello Mitul,
> -Original Message-
> From: Golani, Mitulkumar Ajitkumar
> Sent: Friday, June 9, 2023 11:12 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Borah, Chaitanya Kumar
> ; Golani, Mitulkumar Ajitkumar
> ; Nautiyal, Ankit K
>
> Subject: [RFC 3/3] drm/i915/display: Add wrapper to Compute SAD
>
> Compute SADs that takes into account the supported rate and channel based
> on the capabilities of the audio source. This wrapper function should
> encapsulate the logic for determining the supported rate and channel and
> should return a set of SADs that are compatible with the source.
>
> --v1:
> - call intel_audio_compute_eld in this commit as it is defined here
>
> Signed-off-by: Mitul Golani
> ---
> drivers/gpu/drm/i915/display/intel_audio.c | 66 ++
> drivers/gpu/drm/i915/display/intel_audio.h | 1 +
> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +
> 3 files changed, 69 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index e20ffc8e9654..a6a58b0f0717 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -794,6 +794,72 @@ bool intel_audio_compute_config(struct
> intel_encoder *encoder,
> return true;
> }
>
> +static unsigned int drm_sad_to_channels(const u8 *sad) {
> + return 1 + (sad[0] & 0x7);
> +}
> +
We can do away with the drm_ prefix here.
> +static inline u8 *parse_sad(u8 *eld)
> +{
Nit: eld_to_sad() could be a better name here.
> + unsigned int ver, mnl;
> +
> + ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >>
> DRM_ELD_VER_SHIFT;
> + if (ver != 2 && ver != 31)
> + return NULL;
> +
> + mnl = drm_eld_mnl(eld);
> + if (mnl > 16)
> + return NULL;
> +
> + return eld + DRM_ELD_CEA_SAD(mnl, 0);
> +}
> +
> +static u8 get_supported_freq_mask(struct intel_crtc_state *crtc_state)
> +{
> + int audio_freq_hz[] = {32000, 44100, 48000, 88000, 96000, 176000,
> 192000, 0};
Please check if we really need this trailing 0 here.
To cover the case where the maximum rate is set to 0Hz(init value) we can have
a check of
if (crtc_state->audio.max_frequency < 32000)
Regards
Chaitanya
> + u8 mask = 0;
> +
> + for (u8 index = 0; index < ARRAY_SIZE(audio_freq_hz); index++) {
> + mask |= 1 << index;
> + if (crtc_state->audio.max_frequency != audio_freq_hz[index])
> + continue;
> + else
> + break;
> + }
> +
> + return mask;
> +}
> +
> +void intel_audio_compute_eld(struct intel_crtc_state *crtc_state) {
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + u8 *eld, *sad, index, mask = 0;
> +
> + eld = crtc_state->eld;
> + if (!eld) {
> + drm_err(&i915->drm, "failed to locate eld\n");
> + return;
> + }
> +
> + sad = (u8 *)parse_sad(eld);
> + if (sad) {
> + mask = get_supported_freq_mask(crtc_state);
> +
> + for (index = 0; index < drm_eld_sad_count(eld); index++, sad
> += 3) {
> + /*
> + * Respect to source restrictions. If source limit is
> greater than sink
> + * capabilities then follow to sink's highest supported
> rate.
> + */
> + if (drm_sad_to_channels(sad) >= crtc_state-
> >audio.max_channel) {
> + sad[0] &= ~0x7;
> + sad[0] |= crtc_state->audio.max_channel - 1;
> + }
> +
> + sad[1] &= mask;
> + }
> + }
> +}
> +
> /**
> * intel_audio_codec_enable - Enable the audio codec for HD audio
> * @encoder: encoder on which to enable audio diff --git
> a/drivers/gpu/drm/i915/display/intel_audio.h
> b/drivers/gpu/drm/i915/display/intel_audio.h
> index 07d034a981e9..2ec7fafd9711 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.h
> +++ b/drivers/gpu/drm/i915/display/intel_audio.h
> @@ -14,6 +14,7 @@ struct intel_crtc_state; struct intel_encoder;
>
> void intel_audio_hooks_init(struct drm_i915_private *dev_priv);
> +void intel_audio_compute_eld(struct intel_crtc_state *crtc_state);
> bool intel_audio_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state); diff
> --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 0188a600f9f5..beafeff494f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2403,6 +2403,8 @@ int intel_hdmi_compute_config(struct intel_encoder
> *encoder,
> return -EINVAL;
> }
>
> + intel_audio_compute_eld(pipe_config);
> +
> return 0;
> }
>
> --
> 2.25.1
Re: [Intel-gfx] [PATCH v7 8/9] vfio/pci: Extend VFIO_DEVICE_GET_PCI_HOT_RESET_INFO for vfio device cdev
> From: Jason Gunthorpe > Sent: Wednesday, June 14, 2023 9:38 PM > > On Wed, Jun 14, 2023 at 01:05:45PM +, Liu, Yi L wrote: > > > -EAGAIN basically means the kernel internally malfunctioned - eg it > > > allocated too little space for the actual size of devices. That is no > > > longer possible in this version so it should never return -EAGAIN. > > > > I still have one doubt. Per my understanding, this is to handle newly > > plugged devices during the info reporting path. I don’t think holding > > dev_set lock can prevent it. but maybe -ENOSPC is enough. @Alex, > > what about your opinion? > > If the device was plug instantly before we computed the size we returned > ENOSPC > > If it was plugged instantly after we computed the size we returned > EAGAIN Yes. > Here we just resolve this race consistently to always return ENOSPC, > which always means we ran out of space in the user provided buffer. This makes sense. > > > - kfree(devices); > > > - return ret; > > > + if (fill.count != fill.devices - arg->devices) > > > > Should be "if (fill.count != (fill.devices - arg->devices) / > > sizeof(arg->devices[0]))" 😊 > > devices is already a typed pointer so the compiler computes the > /sizeof() itself > > Your version above is needed if it was void * Got it. Regards, Yi Liu
[Intel-gfx] [PATCH v2] drm/i915/display/lspcon: Increase LSPCON mode settle timeout
This is to eliminate all cases of "*ERROR* LSPCON mode hasn't settled", followed by link training errors. Intel engineers recommended increasing this timeout and that does resolve the issue. On some CometLake-based device designs the Parade PS175 takes more than 400ms to settle in PCON mode. 100 reboot trials on one device resulted in a median settle time of 440ms and a maximum of 444ms. Even after increasing the timeout to 500ms, 2% of devices still had this error. So this increases the timeout to 800ms. Signed-off-by: Pablo Ceballos --- Changelog since v1: - Added more details in the commit message drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index bb3b5355a0d9..d7299fdc43ad 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -167,7 +167,7 @@ static enum drm_lspcon_mode lspcon_wait_mode(struct intel_lspcon *lspcon, drm_dbg_kms(&i915->drm, "Waiting for LSPCON mode %s to settle\n", lspcon_mode_name(mode)); - wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 400); + wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 800); if (current_mode != mode) drm_err(&i915->drm, "LSPCON mode hasn't settled\n"); -- 2.41.0.162.gfafddb0af9-goog
[Intel-gfx] [CI] drm/i915/huc: Fix missing error code in intel_huc_init()
From: Harshit Mogalapalli
Smatch warns:
drivers/gpu/drm/i915/gt/uc/intel_huc.c:388
intel_huc_init() warn: missing error code 'err'
When the allocation of VMAs fail: The value of err is zero at this
point and it is passed to PTR_ERR and also finally returning zero which
is success instead of failure.
Fix this by adding the missing error code when VMA allocation fails.
Fixes: 08872cb13a71 ("drm/i915/mtl/huc: auth HuC via GSC")
Signed-off-by: Harshit Mogalapalli
Reviewed-by: Daniele Ceraolo Spurio
---
Re-sending for testing, because it looks like the original didn't make
it to intel-gfx and patchwork.
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index d3a7219e9ed1..bb95bdd1c3f9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -384,6 +384,7 @@ int intel_huc_init(struct intel_huc *huc)
vma = intel_guc_allocate_vma(>->uc.guc,
PXP43_HUC_AUTH_INOUT_SIZE * 2);
if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
huc_info(huc, "Failed to allocate heci pkt\n");
goto out;
}
--
2.40.0
Re: [Intel-gfx] [PATCH next] drm/i915/huc: Fix missing error code in intel_huc_init()
On 6/14/2023 1:41 PM, Harshit Mogalapalli wrote:
Smatch warns:
drivers/gpu/drm/i915/gt/uc/intel_huc.c:388
intel_huc_init() warn: missing error code 'err'
When the allocation of VMAs fail: The value of err is zero at this
point and it is passed to PTR_ERR and also finally returning zero which
is success instead of failure.
Fix this by adding the missing error code when VMA allocation fails.
Fixes: 08872cb13a71 ("drm/i915/mtl/huc: auth HuC via GSC")
Signed-off-by: Harshit Mogalapalli
Thanks for the fix.
Reviewed-by: Daniele Ceraolo Spurio
It looks like the patch wasn't picked out by our CI, so I'm going to
re-send it to intel-gfx for testing and then merge it via drm-intel once
we get the results.
Daniele
---
Found using Static analysis with Smatch, only compile tested.
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index e0afd8f89502..ddd146265beb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -384,6 +384,7 @@ int intel_huc_init(struct intel_huc *huc)
vma = intel_guc_allocate_vma(>->uc.guc, PXP43_HUC_AUTH_INOUT_SIZE * 2);
if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
huc_info(huc, "Failed to allocate heci pkt\n");
goto out;
}
Re: [Intel-gfx] [RFC 1/2] drm/xe: Move mmio read/write functions to xe_mmio.c
> -Original Message-
> From: Roper, Matthew D
> Sent: Tuesday, June 13, 2023 7:03 PM
> To: Sripada, Radhakrishna
> Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; De
> Marchi,
> Lucas
> Subject: Re: [RFC 1/2] drm/xe: Move mmio read/write functions to xe_mmio.c
>
> On Tue, Jun 13, 2023 at 05:13:14PM -0700, Radhakrishna Sripada wrote:
> > Move the register read/write apis to xe_mmio.c to prepare for
> > adding tracing infrastructure for the same. Adding tracing support
> > in xe_mmio.h messes with the compilation of the display code.
> >
> > Cc: Lucas De Marchi
> > Cc: Matt Roper
> > Signed-off-by: Radhakrishna Sripada
> > ---
> > drivers/gpu/drm/xe/xe_mmio.c | 113 ++
> > drivers/gpu/drm/xe/xe_mmio.h | 129 ---
> > 2 files changed, 128 insertions(+), 114 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> > index 475b14fe4356..70ad1b6a17a0 100644
> > --- a/drivers/gpu/drm/xe/xe_mmio.c
> > +++ b/drivers/gpu/drm/xe/xe_mmio.c
> > @@ -435,6 +435,119 @@ static const struct xe_reg mmio_read_whitelist[] = {
> > RING_TIMESTAMP(RENDER_RING_BASE),
> > };
> >
> > +inline u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg)
>
> We shouldn't have 'inline' on non-static functions in a .c file (and
> generally we don't really want it on static functions either since the
> compiler can generally do a better job of figuring out whether or not
> inlining would be beneficial).
>
Sure Matt. Will do that in next rev.
-Radhakrishna(RK) Sripada
>
> Matt
>
> > +{
> > + struct xe_tile *tile = gt_to_tile(gt);
> > +
> > + if (reg.addr < gt->mmio.adj_limit)
> > + reg.addr += gt->mmio.adj_offset;
> > +
> > + return readb(tile->mmio.regs + reg.addr);
> > +}
> > +
> > +inline void xe_mmio_write32(struct xe_gt *gt,
> > + struct xe_reg reg, u32 val)
> > +{
> > + struct xe_tile *tile = gt_to_tile(gt);
> > +
> > + if (reg.addr < gt->mmio.adj_limit)
> > + reg.addr += gt->mmio.adj_offset;
> > +
> > + writel(val, tile->mmio.regs + reg.addr);
> > +}
> > +
> > +inline u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)
> > +{
> > + struct xe_tile *tile = gt_to_tile(gt);
> > +
> > + if (reg.addr < gt->mmio.adj_limit)
> > + reg.addr += gt->mmio.adj_offset;
> > +
> > + return readl(tile->mmio.regs + reg.addr);
> > +}
> > +
> > +inline u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr,
> > +u32 set)
> > +{
> > + u32 old, reg_val;
> > +
> > + old = xe_mmio_read32(gt, reg);
> > + reg_val = (old & ~clr) | set;
> > + xe_mmio_write32(gt, reg, reg_val);
> > +
> > + return old;
> > +}
> > +
> > +inline void xe_mmio_write64(struct xe_gt *gt,
> > + struct xe_reg reg, u64 val)
> > +{
> > + struct xe_tile *tile = gt_to_tile(gt);
> > +
> > + if (reg.addr < gt->mmio.adj_limit)
> > + reg.addr += gt->mmio.adj_offset;
> > +
> > + writeq(val, tile->mmio.regs + reg.addr);
> > +}
> > +
> > +inline u64 xe_mmio_read64(struct xe_gt *gt, struct xe_reg reg)
> > +{
> > + struct xe_tile *tile = gt_to_tile(gt);
> > +
> > + if (reg.addr < gt->mmio.adj_limit)
> > + reg.addr += gt->mmio.adj_offset;
> > +
> > + return readq(tile->mmio.regs + reg.addr);
> > +}
> > +
> > +inline int xe_mmio_write32_and_verify(struct xe_gt *gt,
> > + struct xe_reg reg, u32 val,
> > + u32 mask, u32 eval)
> > +{
> > + u32 reg_val;
> > +
> > + xe_mmio_write32(gt, reg, val);
> > + reg_val = xe_mmio_read32(gt, reg);
> > +
> > + return (reg_val & mask) != eval ? -EINVAL : 0;
> > +}
> > +
> > +inline int xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 val,
> > + u32 mask, u32 timeout_us, u32 *out_val,
> > + bool atomic)
> > +{
> > + ktime_t cur = ktime_get_raw();
> > + const ktime_t end = ktime_add_us(cur, timeout_us);
> > + int ret = -ETIMEDOUT;
> > + s64 wait = 10;
> > + u32 read;
> > +
> > + for (;;) {
> > + read = xe_mmio_read32(gt, reg);
> > + if ((read & mask) == val) {
> > + ret = 0;
> > + break;
> > + }
> > +
> > + cur = ktime_get_raw();
> > + if (!ktime_before(cur, end))
> > + break;
> > +
> > + if (ktime_after(ktime_add_us(cur, wait), end))
> > + wait = ktime_us_delta(end, cur);
> > +
> > + if (atomic)
> > + udelay(wait);
> > + else
> > + usleep_range(wait, wait << 1);
> > + wait <<= 1;
> > + }
> > +
> > + if (out_val)
> > + *out_val = read;
> > +
> > + return ret;
> > +}
> > +
> > int xe_mmio_ioctl(struct drm_device *dev, void *data,
> > struct drm_file *file)
> > {
> > diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers
[Intel-gfx] [linux-next:master] BUILD REGRESSION b16049b21162bb649cdd8519642a35972b7910fe
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: b16049b21162bb649cdd8519642a35972b7910fe Add linux-next specific files for 20230614 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/20230613.hher4zoo-...@intel.com https://lore.kernel.org/oe-kbuild-all/202306132237.z4lje8bp-...@intel.com https://lore.kernel.org/oe-kbuild-all/202306140505.ztbob65w-...@intel.com https://lore.kernel.org/oe-kbuild-all/202306141702.zao9v2lk-...@intel.com https://lore.kernel.org/oe-kbuild-all/202306141719.mjhclsrc-...@intel.com https://lore.kernel.org/oe-kbuild-all/202306141920.ttvpsxwj-...@intel.com https://lore.kernel.org/oe-kbuild-all/202306141934.ukmm9bfx-...@intel.com https://lore.kernel.org/oe-kbuild-all/202306142017.23vmblmg-...@intel.com https://lore.kernel.org/oe-kbuild-all/202306142023.vjeafkk5-...@intel.com Error/Warning: (recently discovered and may have been fixed) Documentation/networking/device_drivers/ethernet/mellanox/mlx5/switchdev.rst:57: WARNING: Unexpected indentation. Documentation/networking/device_drivers/ethernet/mellanox/mlx5/switchdev.rst:66: WARNING: undefined label: documentation/networking/devlink/devlink-params.rst (if the link has no caption the label must precede a section header) arch/parisc/kernel/pdt.c:65:6: warning: no previous prototype for 'arch_report_meminfo' [-Wmissing-prototypes] drivers/ata/pata_octeon_cf.c:835:7: error: call to undeclared function 'of_property_read_reg'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] drivers/char/mem.c:164:25: error: implicit declaration of function 'unxlate_dev_mem_ptr'; did you mean 'xlate_dev_mem_ptr'? [-Werror=implicit-function-declaration] drivers/gpu/drm/i915/display/intel_display_power.h:255:70: error: declaration of 'struct seq_file' will not be visible outside of this function [-Werror,-Wvisibility] drivers/gpu/drm/i915/display/intel_display_power.h:256:70: error: declaration of 'struct seq_file' will not be visible outside of this function [-Werror,-Wvisibility] drivers/gpu/drm/i915/i915_driver.c:1806:17: error: use of undeclared identifier 'i915_drm_client_fdinfo' drivers/leds/leds-cht-wcove.c:144:21: warning: no previous prototype for 'cht_wc_leds_brightness_get' [-Wmissing-prototypes] drivers/net/ethernet/sfc/ef100_netdev.c:313: undefined reference to `efx_tc_netdev_event' drivers/net/ethernet/sfc/ef100_netdev.c:329: undefined reference to `efx_tc_netevent_event' kernel/rcu/rcuscale.c:301:20: error: use of undeclared identifier 'get_rcu_tasks_gp_kthread'; did you mean 'get_rcu_tasks_trace_gp_kthread'? kernel/rcu/rcuscale.c:322:14: error: use of undeclared identifier 'tasks_scale_read_lock' kernel/rcu/rcuscale.c:323:16: error: use of undeclared identifier 'tasks_scale_read_unlock' kernel/rcu/rcuscale.c:330:20: error: use of undeclared identifier 'get_rcu_tasks_rude_gp_kthread'; did you mean 'get_rcu_tasks_trace_gp_kthread'? kernel/rcu/tasks.h:1113:21: warning: no previous prototype for function 'get_rcu_tasks_gp_kthread' [-Wmissing-prototypes] lib/kunit/executor_test.c:138:4: warning: cast from 'void (*)(const void *)' to 'kunit_action_t *' (aka 'void (*)(void *)') converts to incompatible function type [-Wcast-function-type-strict] lib/kunit/test.c:775:38: warning: cast from 'void (*)(const void *)' to 'kunit_action_t *' (aka 'void (*)(void *)') converts to incompatible function type [-Wcast-function-type-strict] security/apparmor/policy_unpack.c:1144: warning: expecting prototype for verify_dfa_accept_xindex(). Prototype was for verify_dfa_accept_index() instead Unverified Error/Warning (likely false positive, please contact us if interested): drivers/char/tpm/tpm_tis_spi_main.c:137 tpm_tis_spi_transfer_half() error: uninitialized symbol 'ret'. drivers/net/ethernet/emulex/benet/be_main.c:2460 be_rx_compl_process_gro() error: buffer overflow '((skb_end_pointer(skb)))->frags' 17 <= u16max drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c:98 mlx5_devcom_register_device() error: uninitialized symbol 'tmp_dev'. drivers/usb/cdns3/cdns3-starfive.c:23: warning: expecting prototype for cdns3(). Prototype was for USB_STRAP_HOST() instead fs/smb/client/cifsfs.c:982 cifs_smb3_do_mount() warn: possible memory leak of 'cifs_sb' fs/smb/client/cifssmb.c:4089 CIFSFindFirst() warn: missing error code? 'rc' fs/smb/client/cifssmb.c:4216 CIFSFindNext() warn: missing error code? 'rc' fs/smb/client/connect.c:2775 cifs_match_super() error: 'tlink' dereferencing possible ERR_PTR() fs/smb/client/connect.c:2974 generic_ip_connect() error: we previously assumed 'socket' could be null (see line 2962)
Re: [Intel-gfx] [PATCH v12 21/24] vfio: Determine noiommu device in __vfio_register_dev()
On Wed, Jun 14, 2023 at 01:12:50PM +, Liu, Yi L wrote:
> diff --git a/drivers/vfio/group.c b/drivers/vfio/group.c
> index 41a09a2df690..c2e0128323a7 100644
> --- a/drivers/vfio/group.c
> +++ b/drivers/vfio/group.c
> @@ -687,16 +687,6 @@ static struct vfio_group
> *vfio_group_find_or_alloc(struct device *dev)
> if (!iommu_group)
> return ERR_PTR(-EINVAL);
>
> - /*
> - * VFIO always sets IOMMU_CACHE because we offer no way for userspace to
> - * restore cache coherency. It has to be checked here because it is only
> - * valid for cases where we are using iommu groups.
> - */
> - if (!device_iommu_capable(dev, IOMMU_CAP_CACHE_COHERENCY)) {
> - iommu_group_put(iommu_group);
> - return ERR_PTR(-EINVAL);
> - }
> -
> mutex_lock(&vfio.group_lock);
> group = vfio_group_find_from_iommu(iommu_group);
> if (group) {
> diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
> index 51c80eb32af6..ffb4585b7f0e 100644
> --- a/drivers/vfio/vfio_main.c
> +++ b/drivers/vfio/vfio_main.c
> @@ -292,6 +292,17 @@ static int __vfio_register_dev(struct vfio_device
> *device,
> if (ret)
> return ret;
>
> + /*
> + * VFIO always sets IOMMU_CACHE because we offer no way for userspace to
> + * restore cache coherency. It has to be checked here because it is only
> + * valid for cases where we are using iommu groups.
> + */
> + if (type == VFIO_IOMMU && !vfio_device_is_noiommu(device) &&
> + !device_iommu_capable(device->dev, IOMMU_CAP_CACHE_COHERENCY)) {
> + ret = -EINVAL;
> + goto err_out;
> + }
> +
> ret = vfio_device_add(device);
> if (ret)
> goto err_out;
Yes that looks right
>
> > I prefer the idea that vfio_device_is_noiommu() works in all the
> > kconfig scenarios rather than adding #ifdefs.
>
> But the vfio_group would be empty when CONFIG_VFIO_GROUP is unset.
> From what I got now, when CONFIG_VFIO_GROUP is unset, the stub
> function always returns false.
It seems fine, you could also put the ifdef inside the stub
Jason
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Add vfio_device cdev for iommufd support (rev16)
== Series Details == Series: Add vfio_device cdev for iommufd support (rev16) URL : https://patchwork.freedesktop.org/series/113696/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/113696/revisions/16/mbox/ not applied Applying: vfio: Allocate per device file structure Applying: vfio: Refine vfio file kAPIs for KVM Applying: vfio: Accept vfio device file in the KVM facing kAPI Applying: kvm/vfio: Prepare for accepting vfio device fd Applying: kvm/vfio: Accept vfio device file from userspace Applying: vfio: Pass struct vfio_device_file * to vfio_device_open/close() Applying: vfio: Block device access via device fd until device is opened Applying: vfio: Add cdev_device_open_cnt to vfio_group Applying: vfio: Make vfio_df_open() single open for device cdev path Applying: vfio-iommufd: Move noiommu compat validation out of vfio_iommufd_bind() Applying: vfio-iommufd: Split bind/attach into two steps Applying: vfio: Record devid in vfio_device_file Applying: vfio-iommufd: Add detach_ioas support for physical VFIO devices Applying: iommufd/device: Add iommufd_access_detach() API Applying: vfio-iommufd: Add detach_ioas support for emulated VFIO devices error: sha1 information is lacking or useless (drivers/vfio/iommufd.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0015 vfio-iommufd: Add detach_ioas support for emulated VFIO devices When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Enhance vfio PCI hot reset for vfio cdev device (rev7)
== Series Details == Series: Enhance vfio PCI hot reset for vfio cdev device (rev7) URL : https://patchwork.freedesktop.org/series/116991/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/116991/revisions/7/mbox/ not applied Applying: vfio/pci: Update comment around group_fd get in vfio_pci_ioctl_pci_hot_reset() Applying: vfio/pci: Move the existing hot reset logic to be a helper Applying: iommufd: Reserve all negative IDs in the iommufd xarray Applying: iommufd: Add iommufd_ctx_has_group() Applying: iommufd: Add helper to retrieve iommufd_ctx and devid Applying: vfio: Mark cdev usage in vfio_device Applying: vfio: Add helper to search vfio_device in a dev_set Applying: vfio/pci: Extend VFIO_DEVICE_GET_PCI_HOT_RESET_INFO for vfio device cdev Using index info to reconstruct a base tree... M drivers/vfio/pci/vfio_pci_core.c Falling back to patching base and 3-way merge... Auto-merging drivers/vfio/pci/vfio_pci_core.c CONFLICT (content): Merge conflict in drivers/vfio/pci/vfio_pci_core.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0008 vfio/pci: Extend VFIO_DEVICE_GET_PCI_HOT_RESET_INFO for vfio device cdev When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
Re: [Intel-gfx] [PATCH] drm/i915: Call page_address() on page acquired with GFP_KERNEL flag
On 6/14/23 15:22, Tvrtko Ursulin wrote: On 14/06/2023 13:35, Sumitra Sharma wrote: Pages allocated with GFP_KERNEL cannot come from Highmem. That is why there is no need to call kmap() on them. Are you sure it is GFP_KERNEL backed and not tmpfs? I am not sure myself so let me copy Matt and Thomas if they happen to know off hand. It looks to me these are shmem pages or TTM pages. Both could be highmem. So I think kmap is the correct choice here. /Thomas Regards, Tvrtko Therefore, don't call kmap() on the page coming from vma_res->bi.pages using for_each_sgt_page() in i915_vma_coredump_create(). Use a plain page_address() to get the kernel address instead. Signed-off-by: Sumitra Sharma --- drivers/gpu/drm/i915/i915_gpu_error.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index f020c0086fbc..6f51cb4fc55c 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1164,9 +1164,8 @@ i915_vma_coredump_create(const struct intel_gt *gt, drm_clflush_pages(&page, 1); - s = kmap(page); + s = page_address(page); ret = compress_page(compress, s, dst, false); - kunmap(page); drm_clflush_pages(&page, 1);
Re: [Intel-gfx] [PATCH v7 8/9] vfio/pci: Extend VFIO_DEVICE_GET_PCI_HOT_RESET_INFO for vfio device cdev
On Wed, Jun 14, 2023 at 01:05:45PM +, Liu, Yi L wrote: > > -EAGAIN basically means the kernel internally malfunctioned - eg it > > allocated too little space for the actual size of devices. That is no > > longer possible in this version so it should never return -EAGAIN. > > I still have one doubt. Per my understanding, this is to handle newly > plugged devices during the info reporting path. I don’t think holding > dev_set lock can prevent it. but maybe -ENOSPC is enough. @Alex, > what about your opinion? If the device was plug instantly before we computed the size we returned ENOSPC If it was plugged instantly after we computed the size we returned EAGAIN Here we just resolve this race consistently to always return ENOSPC, which always means we ran out of space in the user provided buffer. > > - kfree(devices); > > - return ret; > > + if (fill.count != fill.devices - arg->devices) > > Should be "if (fill.count != (fill.devices - arg->devices) / > sizeof(arg->devices[0]))" 😊 devices is already a typed pointer so the compiler computes the /sizeof() itself Your version above is needed if it was void * Jason
Re: [Intel-gfx] [PATCH] drm/i915: Call page_address() on page acquired with GFP_KERNEL flag
On 14/06/2023 13:35, Sumitra Sharma wrote: Pages allocated with GFP_KERNEL cannot come from Highmem. That is why there is no need to call kmap() on them. Are you sure it is GFP_KERNEL backed and not tmpfs? I am not sure myself so let me copy Matt and Thomas if they happen to know off hand. Regards, Tvrtko Therefore, don't call kmap() on the page coming from vma_res->bi.pages using for_each_sgt_page() in i915_vma_coredump_create(). Use a plain page_address() to get the kernel address instead. Signed-off-by: Sumitra Sharma --- drivers/gpu/drm/i915/i915_gpu_error.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index f020c0086fbc..6f51cb4fc55c 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1164,9 +1164,8 @@ i915_vma_coredump_create(const struct intel_gt *gt, drm_clflush_pages(&page, 1); - s = kmap(page); + s = page_address(page); ret = compress_page(compress, s, dst, false); - kunmap(page); drm_clflush_pages(&page, 1);
Re: [Intel-gfx] [PATCH v12 21/24] vfio: Determine noiommu device in __vfio_register_dev()
> From: Jason Gunthorpe
> Sent: Wednesday, June 14, 2023 8:23 PM
> On Wed, Jun 14, 2023 at 06:20:10AM +, Tian, Kevin wrote:
> > > From: Liu, Yi L
> > > Sent: Wednesday, June 14, 2023 2:14 PM
> > >
> > >
> > > > With that I think Jason's suggestion is to lift that test into main.c:
> > > >
> > > > int vfio_register_group_dev(struct vfio_device *device)
> > > > {
> > > > /*
> > > > * VFIO always sets IOMMU_CACHE because we offer no way for
> > > userspace to
> > > > * restore cache coherency. It has to be checked here because
> > > > it is
> > > only
> > > > * valid for cases where we are using iommu groups.
> > > > */
> > > > if (type == VFIO_IOMMU && !vfio_device_is_noiommu(device) &&
> > > > !device_iommu_capable(dev, IOMMU_CAP_CACHE_COHERENCY))
> > > > return ERR_PTR(-EINVAL);
> > >
> > > vfio_device_is_noiommu() needs to be called after vfio_device_set_group().
> > > Otherwise, it's always false. So still needs to call it in the
> > > __vfio_register_dev().
> >
> > yes
>
> Right, but it needs to be in vfio_main.c, not in the group.c - so
> another patch should be added to move it.
I've got a patch as below to move it.
>From 306e71325d255eef34a1c44312bf9cdc8c302faa Mon Sep 17 00:00:00 2001
From: Yi Liu
Date: Wed, 14 Jun 2023 00:37:52 -0700
Subject: [PATCH] vfio: Move the IOMMU_CAP_CACHE_COHERENCY check in
__vfio_register_dev()
The IOMMU_CAP_CACHE_COHERENCY check only applies to the physical devices
that are IOMMU-backed. This change prepares for compiling the vfio_group
infrastructure optionally as cdev does not support the physical devices
that are not IOMMU-backed. This check help to fail the device registration
for such devices if only vfio_group infrastructure is compiled out.
Signed-off-by: Yi Liu
---
drivers/vfio/group.c | 10 --
drivers/vfio/vfio_main.c | 11 +++
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/vfio/group.c b/drivers/vfio/group.c
index 41a09a2df690..c2e0128323a7 100644
--- a/drivers/vfio/group.c
+++ b/drivers/vfio/group.c
@@ -687,16 +687,6 @@ static struct vfio_group *vfio_group_find_or_alloc(struct
device *dev)
if (!iommu_group)
return ERR_PTR(-EINVAL);
- /*
-* VFIO always sets IOMMU_CACHE because we offer no way for userspace to
-* restore cache coherency. It has to be checked here because it is only
-* valid for cases where we are using iommu groups.
-*/
- if (!device_iommu_capable(dev, IOMMU_CAP_CACHE_COHERENCY)) {
- iommu_group_put(iommu_group);
- return ERR_PTR(-EINVAL);
- }
-
mutex_lock(&vfio.group_lock);
group = vfio_group_find_from_iommu(iommu_group);
if (group) {
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index 51c80eb32af6..ffb4585b7f0e 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -292,6 +292,17 @@ static int __vfio_register_dev(struct vfio_device *device,
if (ret)
return ret;
+ /*
+* VFIO always sets IOMMU_CACHE because we offer no way for userspace to
+* restore cache coherency. It has to be checked here because it is only
+* valid for cases where we are using iommu groups.
+*/
+ if (type == VFIO_IOMMU && !vfio_device_is_noiommu(device) &&
+ !device_iommu_capable(device->dev, IOMMU_CAP_CACHE_COHERENCY)) {
+ ret = -EINVAL;
+ goto err_out;
+ }
+
ret = vfio_device_add(device);
if (ret)
goto err_out;
--
2.34.1
> I prefer the idea that vfio_device_is_noiommu() works in all the
> kconfig scenarios rather than adding #ifdefs.
But the vfio_group would be empty when CONFIG_VFIO_GROUP is unset.
>From what I got now, when CONFIG_VFIO_GROUP is unset, the stub
function always returns false.
#if IS_ENABLED(CONFIG_VFIO_GROUP)
struct vfio_group {
...;
};
static inline bool vfio_device_is_noiommu(struct vfio_device *vdev)
{
return IS_ENABLED(CONFIG_VFIO_NOIOMMU) &&
vdev->group->type == VFIO_NO_IOMMU;
}
#else
struct vfio_group;
static inline bool vfio_device_is_noiommu(struct vfio_device *vdev)
{
return false;
}
#endif
Regards,
Yi Liu
Re: [Intel-gfx] [PATCH v7 8/9] vfio/pci: Extend VFIO_DEVICE_GET_PCI_HOT_RESET_INFO for vfio device cdev
> From: Jason Gunthorpe
> Sent: Wednesday, June 14, 2023 8:17 PM
>
> On Wed, Jun 14, 2023 at 10:35:10AM +, Liu, Yi L wrote:
>
> > > - if (fill->cur == fill->max)
> > > - return -EAGAIN; /* Something changed, try again */
> > > + if (fill->devices_end >= fill->devices)
> > > + return -ENOSPC;
> >
> > This should be fill->devices_end <= fill->devices.
>
> Yep
>
> > Even it's corrected. The
> > new code does not return -EAGAIN.
>
> Right, there is no EAGAIN. If the caller didn't provide enough space
> the previous version returned ENOSPC:
>
> > > - if (hdr.argsz < sizeof(hdr) + (fill.max * sizeof(*devices))) {
> > > - ret = -ENOSPC;
> > > - hdr.count = fill.max;
> > > - goto reset_info_exit;
> > > - }
>
> -EAGAIN basically means the kernel internally malfunctioned - eg it
> allocated too little space for the actual size of devices. That is no
> longer possible in this version so it should never return -EAGAIN.
I still have one doubt. Per my understanding, this is to handle newly
plugged devices during the info reporting path. I don’t think holding
dev_set lock can prevent it. but maybe -ENOSPC is enough. @Alex,
what about your opinion?
> > And if return -ENOSPC, the expected
> > size should be returned. But I didn't see it. As the hunk below[1] is
> > removed,
> > seems no way to know how many memory it requires.
>
> Yes, I missed that, it should keep counting
>
> Like this then
>
> diff --git a/drivers/vfio/pci/vfio_pci_core.c
> b/drivers/vfio/pci/vfio_pci_core.c
> index b0eadafcbcf502..05c064896a7a94 100644
> --- a/drivers/vfio/pci/vfio_pci_core.c
> +++ b/drivers/vfio/pci/vfio_pci_core.c
> @@ -775,19 +775,25 @@ static int vfio_pci_count_devs(struct pci_dev *pdev,
> void
> *data)
> }
>
> struct vfio_pci_fill_info {
> - int max;
> - int cur;
> - struct vfio_pci_dependent_device *devices;
> + struct vfio_pci_dependent_device __user *devices;
> + struct vfio_pci_dependent_device __user *devices_end;
> struct vfio_device *vdev;
> + u32 count;
> u32 flags;
> };
>
> static int vfio_pci_fill_devs(struct pci_dev *pdev, void *data)
> {
> + struct vfio_pci_dependent_device info = {
> + .segment = pci_domain_nr(pdev->bus),
> + .bus = pdev->bus->number,
> + .devfn = pdev->devfn,
> + };
> struct vfio_pci_fill_info *fill = data;
>
> - if (fill->cur == fill->max)
> - return -EAGAIN; /* Something changed, try again */
> + fill.count++;
> + if (fill->devices >= fill->devices_end)
> + return 0;
>
> if (fill->flags & VFIO_PCI_HOT_RESET_FLAG_DEV_ID) {
> struct iommufd_ctx *iommufd =
> vfio_iommufd_device_ictx(fill->vdev);
> @@ -800,12 +806,12 @@ static int vfio_pci_fill_devs(struct pci_dev *pdev,
> void *data)
>*/
> vdev = vfio_find_device_in_devset(dev_set, &pdev->dev);
> if (!vdev)
> - fill->devices[fill->cur].devid =
> VFIO_PCI_DEVID_NOT_OWNED;
> + info.devid = VFIO_PCI_DEVID_NOT_OWNED;
> else
> - fill->devices[fill->cur].devid =
> - vfio_iommufd_device_hot_reset_devid(vdev,
> iommufd);
> + info.devid = vfio_iommufd_device_hot_reset_devid(
> + vdev, iommufd);
> /* If devid is VFIO_PCI_DEVID_NOT_OWNED, clear owned flag. */
> - if (fill->devices[fill->cur].devid == VFIO_PCI_DEVID_NOT_OWNED)
> + if (info.devid == VFIO_PCI_DEVID_NOT_OWNED)
> fill->flags &= ~VFIO_PCI_HOT_RESET_FLAG_DEV_ID_OWNED;
> } else {
> struct iommu_group *iommu_group;
> @@ -814,13 +820,13 @@ static int vfio_pci_fill_devs(struct pci_dev *pdev,
> void *data)
> if (!iommu_group)
> return -EPERM; /* Cannot reset non-isolated devices */
>
> - fill->devices[fill->cur].group_id = iommu_group_id(iommu_group);
> + info.group_id = iommu_group_id(iommu_group);
> iommu_group_put(iommu_group);
> }
> - fill->devices[fill->cur].segment = pci_domain_nr(pdev->bus);
> - fill->devices[fill->cur].bus = pdev->bus->number;
> - fill->devices[fill->cur].devfn = pdev->devfn;
> - fill->cur++;
> +
> + if (copy_to_user(fill->devices, &info, sizeof(info)))
> + return -EFAULT;
> + fill->devices++;
> return 0;
> }
>
> @@ -1212,8 +1218,7 @@ static int vfio_pci_ioctl_get_pci_hot_reset_info(
> unsigned long minsz =
> offsetofend(struct vfio_pci_hot_reset_info, count);
> struct vfio_pci_hot_reset_info hdr;
> - struct vfio_pci_fill_info fill = { 0 };
> - struct vfio_pci_dependent_device *devices = NULL;
> + struct vfio_pci_fill_info fill = {};
> bool slot = false;
> int ret = 0;
>
> @@ -1231,29 +1236,9 @@ static int vfio_pci_ioctl_get_pci_
Re: [Intel-gfx] [PATCH] drm/i915/display : Remove support for interlace mode
On Wed, Jun 14, 2023 at 09:37:49AM +0530, Ankit Nautiyal wrote: > There are multiple panels with which Interlace mode is seen to cause > flickering (interlacing artifacts) with different platforms. > > The issue is seen with both HDMI, DP with CML, CFL, ICL, EHL with > different display models from Acer, Benq, Dell etc. > There are some models where the issue is not seen with same setup. > > Due to this, cases where multiple display are configured in clone mode, > sometimes interlaced mode gets picked up in one of the displays > and flickers are seen. > > Since its difficult to pin point if issue is due to the HW or due to > panels, removing interlace mode for DP and HDMI till this is > root caused. I though people already confirmewd the problem on non-Intel hw? So seems pretty clear that it's the displays themselves that are garbage. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8395 > > Signed-off-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_dp.c | 3 --- > drivers/gpu/drm/i915/display/intel_hdmi.c | 3 --- > 2 files changed, 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index f4192fda1a76..78d8ceb590a3 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5665,9 +5665,6 @@ intel_dp_init_connector(struct intel_digital_port > *dig_port, > drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); > drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); > > - if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12) > - connector->interlace_allowed = true; > - > intel_connector->polled = DRM_CONNECTOR_POLL_HPD; > > intel_dp_aux_init(intel_dp); > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c > b/drivers/gpu/drm/i915/display/intel_hdmi.c > index 7ac5e6c5e00d..9b3ea307ef40 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c > @@ -2998,9 +2998,6 @@ void intel_hdmi_init_connector(struct > intel_digital_port *dig_port, > ddc); > drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); > > - if (DISPLAY_VER(dev_priv) < 12) > - connector->interlace_allowed = true; > - > connector->stereo_allowed = true; > > if (DISPLAY_VER(dev_priv) >= 10) > -- > 2.40.1 -- Ville Syrjälä Intel
Re: [Intel-gfx] [PATCH v12 21/24] vfio: Determine noiommu device in __vfio_register_dev()
On Wed, Jun 14, 2023 at 06:20:10AM +, Tian, Kevin wrote:
> > From: Liu, Yi L
> > Sent: Wednesday, June 14, 2023 2:14 PM
> >
> >
> > > With that I think Jason's suggestion is to lift that test into main.c:
> > >
> > > int vfio_register_group_dev(struct vfio_device *device)
> > > {
> > > /*
> > >* VFIO always sets IOMMU_CACHE because we offer no way for
> > userspace to
> > >* restore cache coherency. It has to be checked here because it is
> > only
> > >* valid for cases where we are using iommu groups.
> > >*/
> > > if (type == VFIO_IOMMU && !vfio_device_is_noiommu(device) &&
> > > !device_iommu_capable(dev, IOMMU_CAP_CACHE_COHERENCY))
> > > return ERR_PTR(-EINVAL);
> >
> > vfio_device_is_noiommu() needs to be called after vfio_device_set_group().
> > Otherwise, it's always false. So still needs to call it in the
> > __vfio_register_dev().
>
> yes
Right, but it needs to be in vfio_main.c, not in the group.c - so
another patch should be added to move it.
I prefer the idea that vfio_device_is_noiommu() works in all the
kconfig scenarios rather than adding #ifdefs.
Jason
Re: [Intel-gfx] [PATCH v7 8/9] vfio/pci: Extend VFIO_DEVICE_GET_PCI_HOT_RESET_INFO for vfio device cdev
On Wed, Jun 14, 2023 at 10:35:10AM +, Liu, Yi L wrote:
> > - if (fill->cur == fill->max)
> > - return -EAGAIN; /* Something changed, try again */
> > + if (fill->devices_end >= fill->devices)
> > + return -ENOSPC;
>
> This should be fill->devices_end <= fill->devices.
Yep
> Even it's corrected. The
> new code does not return -EAGAIN.
Right, there is no EAGAIN. If the caller didn't provide enough space
the previous version returned ENOSPC:
> > - if (hdr.argsz < sizeof(hdr) + (fill.max * sizeof(*devices))) {
> > - ret = -ENOSPC;
> > - hdr.count = fill.max;
> > - goto reset_info_exit;
> > - }
-EAGAIN basically means the kernel internally malfunctioned - eg it
allocated too little space for the actual size of devices. That is no
longer possible in this version so it should never return -EAGAIN.
> And if return -ENOSPC, the expected
> size should be returned. But I didn't see it. As the hunk below[1] is removed,
> seems no way to know how many memory it requires.
Yes, I missed that, it should keep counting
Like this then
diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c
index b0eadafcbcf502..05c064896a7a94 100644
--- a/drivers/vfio/pci/vfio_pci_core.c
+++ b/drivers/vfio/pci/vfio_pci_core.c
@@ -775,19 +775,25 @@ static int vfio_pci_count_devs(struct pci_dev *pdev, void
*data)
}
struct vfio_pci_fill_info {
- int max;
- int cur;
- struct vfio_pci_dependent_device *devices;
+ struct vfio_pci_dependent_device __user *devices;
+ struct vfio_pci_dependent_device __user *devices_end;
struct vfio_device *vdev;
+ u32 count;
u32 flags;
};
static int vfio_pci_fill_devs(struct pci_dev *pdev, void *data)
{
+ struct vfio_pci_dependent_device info = {
+ .segment = pci_domain_nr(pdev->bus),
+ .bus = pdev->bus->number,
+ .devfn = pdev->devfn,
+ };
struct vfio_pci_fill_info *fill = data;
- if (fill->cur == fill->max)
- return -EAGAIN; /* Something changed, try again */
+ fill.count++;
+ if (fill->devices >= fill->devices_end)
+ return 0;
if (fill->flags & VFIO_PCI_HOT_RESET_FLAG_DEV_ID) {
struct iommufd_ctx *iommufd =
vfio_iommufd_device_ictx(fill->vdev);
@@ -800,12 +806,12 @@ static int vfio_pci_fill_devs(struct pci_dev *pdev, void
*data)
*/
vdev = vfio_find_device_in_devset(dev_set, &pdev->dev);
if (!vdev)
- fill->devices[fill->cur].devid =
VFIO_PCI_DEVID_NOT_OWNED;
+ info.devid = VFIO_PCI_DEVID_NOT_OWNED;
else
- fill->devices[fill->cur].devid =
- vfio_iommufd_device_hot_reset_devid(vdev,
iommufd);
+ info.devid = vfio_iommufd_device_hot_reset_devid(
+ vdev, iommufd);
/* If devid is VFIO_PCI_DEVID_NOT_OWNED, clear owned flag. */
- if (fill->devices[fill->cur].devid == VFIO_PCI_DEVID_NOT_OWNED)
+ if (info.devid == VFIO_PCI_DEVID_NOT_OWNED)
fill->flags &= ~VFIO_PCI_HOT_RESET_FLAG_DEV_ID_OWNED;
} else {
struct iommu_group *iommu_group;
@@ -814,13 +820,13 @@ static int vfio_pci_fill_devs(struct pci_dev *pdev, void
*data)
if (!iommu_group)
return -EPERM; /* Cannot reset non-isolated devices */
- fill->devices[fill->cur].group_id = iommu_group_id(iommu_group);
+ info.group_id = iommu_group_id(iommu_group);
iommu_group_put(iommu_group);
}
- fill->devices[fill->cur].segment = pci_domain_nr(pdev->bus);
- fill->devices[fill->cur].bus = pdev->bus->number;
- fill->devices[fill->cur].devfn = pdev->devfn;
- fill->cur++;
+
+ if (copy_to_user(fill->devices, &info, sizeof(info)))
+ return -EFAULT;
+ fill->devices++;
return 0;
}
@@ -1212,8 +1218,7 @@ static int vfio_pci_ioctl_get_pci_hot_reset_info(
unsigned long minsz =
offsetofend(struct vfio_pci_hot_reset_info, count);
struct vfio_pci_hot_reset_info hdr;
- struct vfio_pci_fill_info fill = { 0 };
- struct vfio_pci_dependent_device *devices = NULL;
+ struct vfio_pci_fill_info fill = {};
bool slot = false;
int ret = 0;
@@ -1231,29 +1236,9 @@ static int vfio_pci_ioctl_get_pci_hot_reset_info(
else if (pci_probe_reset_bus(vdev->pdev->bus))
return -ENODEV;
- /* How many devices are affected? */
- ret = vfio_pci_for_each_slot_or_bus(vdev->pdev, vfio_pci_count_devs,
- &fill.max, slot);
- if (ret)
- return ret;
-
- WARN_ON(!fill.max); /* Should always be at least one */
-
-
Re: [Intel-gfx] [PATCH v7 6/9] vfio: Mark cdev usage in vfio_device
On Wed, Jun 14, 2023 at 05:56:08AM +, Liu, Yi L wrote:
> > From: Jason Gunthorpe
> > Sent: Wednesday, June 14, 2023 1:56 AM
> >
> > On Fri, Jun 02, 2023 at 05:15:12AM -0700, Yi Liu wrote:
> > > This can be used to differentiate whether to report group_id or devid in
> > > the revised VFIO_DEVICE_GET_PCI_HOT_RESET_INFO ioctl. At this moment, no
> > > cdev path yet, so the vfio_device_cdev_opened() helper always returns
> > > false.
> > >
> > > Reviewed-by: Kevin Tian
> > > Tested-by: Terrence Xu
> > > Signed-off-by: Yi Liu
> > > ---
> > > include/linux/vfio.h | 5 +
> > > 1 file changed, 5 insertions(+)
> > >
> > > diff --git a/include/linux/vfio.h b/include/linux/vfio.h
> > > index 2c137ea94a3e..2a45853773a6 100644
> > > --- a/include/linux/vfio.h
> > > +++ b/include/linux/vfio.h
> > > @@ -139,6 +139,11 @@ int vfio_iommufd_emulated_attach_ioas(struct
> > > vfio_device
> > *vdev, u32 *pt_id);
> > > ((int (*)(struct vfio_device *vdev, u32 *pt_id)) NULL)
> > > #endif
> > >
> > > +static inline bool vfio_device_cdev_opened(struct vfio_device *device)
> > > +{
> > > + return false;
> > > +}
> >
> > This and the two hunks in the other two patches that use this function
> > should be folded into the cdev series, probably just flattened to one
> > patch
>
> Hmmm. I have a doubt about the rule. I think the reason to have this
> sub-series is to avoid bumping the cdev series. So perhaps we can still
> put this and the patch 9 in this series? Otherwise, most of the series
> needs to be in the cdev series.
Well, then Alex should apply them at the same time..
Jason
Re: [Intel-gfx] [PATCH v5 02/13] fbdev: Add initializer macros for struct fb_ops
Hi
Am 14.06.23 um 13:29 schrieb Christian König:
Am 30.05.23 um 17:02 schrieb Thomas Zimmermann:
For framebuffers in I/O and system memory, add macros that set
struct fb_ops to the respective callback functions.
For deferred I/O, add macros that generate callback functions with
damage handling. Add initializer macros that set struct fb_ops to
the generated callbacks.
These macros can remove a lot boilerplate code from fbdev drivers.
The drivers are supposed to use the macro that is required for its
framebuffer. Each macro is split into smaller helpers, so that
drivers with non-standard callbacks can pick and customize callbacks
as needed. There are individual helper macros for read/write, mmap
and drawing.
v5:
* fix whitespace errors (Jingfeng)
Signed-off-by: Thomas Zimmermann
Reviewed-by: Sam Ravnborg
---
include/linux/fb.h | 112 +
1 file changed, 112 insertions(+)
diff --git a/include/linux/fb.h b/include/linux/fb.h
index 2cf8efcb9e32..ce6823e157e6 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -538,9 +538,31 @@ extern ssize_t fb_io_read(struct fb_info *info,
char __user *buf,
extern ssize_t fb_io_write(struct fb_info *info, const char __user
*buf,
size_t count, loff_t *ppos);
+/*
+ * Initializes struct fb_ops for framebuffers in I/O memory.
+ */
+
+#define __FB_DEFAULT_IO_OPS_RDWR \
+ .fb_read = fb_io_read, \
+ .fb_write = fb_io_write
+
+#define __FB_DEFAULT_IO_OPS_DRAW \
+ .fb_fillrect = cfb_fillrect, \
+ .fb_copyarea = cfb_copyarea, \
+ .fb_imageblit = cfb_imageblit
+
+#define __FB_DEFAULT_IO_OPS_MMAP \
+ .fb_mmap = NULL // default implementation
// style comment in a macro? That's usually a very bad idea.
I think I see it now. Thanks! That should delete any commas at the end
of the line. I'll send out an update. It works so far, as I only used
that macro in the correct way.
Best regards
Thomas
Christian.
+
+#define FB_DEFAULT_IO_OPS \
+ __FB_DEFAULT_IO_OPS_RDWR, \
+ __FB_DEFAULT_IO_OPS_DRAW, \
+ __FB_DEFAULT_IO_OPS_MMAP
+
/*
* Drawing operations where framebuffer is in system RAM
*/
+
extern void sys_fillrect(struct fb_info *info, const struct
fb_fillrect *rect);
extern void sys_copyarea(struct fb_info *info, const struct
fb_copyarea *area);
extern void sys_imageblit(struct fb_info *info, const struct
fb_image *image);
@@ -549,6 +571,27 @@ extern ssize_t fb_sys_read(struct fb_info *info,
char __user *buf,
extern ssize_t fb_sys_write(struct fb_info *info, const char __user
*buf,
size_t count, loff_t *ppos);
+/*
+ * Initializes struct fb_ops for framebuffers in system memory.
+ */
+
+#define __FB_DEFAULT_SYS_OPS_RDWR \
+ .fb_read = fb_sys_read, \
+ .fb_write = fb_sys_write
+
+#define __FB_DEFAULT_SYS_OPS_DRAW \
+ .fb_fillrect = sys_fillrect, \
+ .fb_copyarea = sys_copyarea, \
+ .fb_imageblit = sys_imageblit
+
+#define __FB_DEFAULT_SYS_OPS_MMAP \
+ .fb_mmap = NULL // default implementation
+
+#define FB_DEFAULT_SYS_OPS \
+ __FB_DEFAULT_SYS_OPS_RDWR, \
+ __FB_DEFAULT_SYS_OPS_DRAW, \
+ __FB_DEFAULT_SYS_OPS_MMAP
+
/* drivers/video/fbmem.c */
extern int register_framebuffer(struct fb_info *fb_info);
extern void unregister_framebuffer(struct fb_info *fb_info);
@@ -604,6 +647,75 @@ extern void fb_deferred_io_cleanup(struct fb_info
*info);
extern int fb_deferred_io_fsync(struct file *file, loff_t start,
loff_t end, int datasync);
+/*
+ * Generate callbacks for deferred I/O
+ */
+
+#define __FB_GEN_DEFAULT_DEFERRED_OPS_RDWR(__prefix, __damage_range,
__mode) \
+ static ssize_t __prefix ## _defio_read(struct fb_info *info, char
__user *buf, \
+ size_t count, loff_t *ppos) \
+ { \
+ return fb_ ## __mode ## _read(info, buf, count, ppos); \
+ } \
+ static ssize_t __prefix ## _defio_write(struct fb_info *info,
const char __user *buf, \
+ size_t count, loff_t *ppos) \
+ { \
+ unsigned long offset = *ppos; \
+ ssize_t ret = fb_ ## __mode ## _write(info, buf, count, ppos); \
+ if (ret > 0) \
+ __damage_range(info, offset, ret); \
+ return ret; \
+ }
+
+#define __FB_GEN_DEFAULT_DEFERRED_OPS_DRAW(__prefix, __damage_area,
__mode) \
+ static void __prefix ## _defio_fillrect(struct fb_info *info, \
+ const struct fb_fillrect *rect) \
+ { \
+ __mode ## _fillrect(info, rect); \
+ __damage_area(info, rect->dx, rect->dy, rect->width,
rect->height); \
+ } \
+ static void __prefix ## _defio_copyarea(struct fb_info *info, \
+ const struct fb_copyarea *area) \
+ { \
+ __mode ## _copyarea(info, area); \
+ __damage_area(info, area->dx, area->dy, area->width,
area->height); \
+ } \
+ static void __prefix ## _defio_imageblit(struct fb_info *info, \
+
Re: [Intel-gfx] [PATCH v5 02/13] fbdev: Add initializer macros for struct fb_ops
Am 30.05.23 um 17:02 schrieb Thomas Zimmermann:
For framebuffers in I/O and system memory, add macros that set
struct fb_ops to the respective callback functions.
For deferred I/O, add macros that generate callback functions with
damage handling. Add initializer macros that set struct fb_ops to
the generated callbacks.
These macros can remove a lot boilerplate code from fbdev drivers.
The drivers are supposed to use the macro that is required for its
framebuffer. Each macro is split into smaller helpers, so that
drivers with non-standard callbacks can pick and customize callbacks
as needed. There are individual helper macros for read/write, mmap
and drawing.
v5:
* fix whitespace errors (Jingfeng)
Signed-off-by: Thomas Zimmermann
Reviewed-by: Sam Ravnborg
---
include/linux/fb.h | 112 +
1 file changed, 112 insertions(+)
diff --git a/include/linux/fb.h b/include/linux/fb.h
index 2cf8efcb9e32..ce6823e157e6 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -538,9 +538,31 @@ extern ssize_t fb_io_read(struct fb_info *info, char
__user *buf,
extern ssize_t fb_io_write(struct fb_info *info, const char __user *buf,
size_t count, loff_t *ppos);
+/*
+ * Initializes struct fb_ops for framebuffers in I/O memory.
+ */
+
+#define __FB_DEFAULT_IO_OPS_RDWR \
+ .fb_read= fb_io_read, \
+ .fb_write = fb_io_write
+
+#define __FB_DEFAULT_IO_OPS_DRAW \
+ .fb_fillrect= cfb_fillrect, \
+ .fb_copyarea= cfb_copyarea, \
+ .fb_imageblit = cfb_imageblit
+
+#define __FB_DEFAULT_IO_OPS_MMAP \
+ .fb_mmap= NULL // default implementation
// style comment in a macro? That's usually a very bad idea.
Christian.
+
+#define FB_DEFAULT_IO_OPS \
+ __FB_DEFAULT_IO_OPS_RDWR, \
+ __FB_DEFAULT_IO_OPS_DRAW, \
+ __FB_DEFAULT_IO_OPS_MMAP
+
/*
* Drawing operations where framebuffer is in system RAM
*/
+
extern void sys_fillrect(struct fb_info *info, const struct fb_fillrect
*rect);
extern void sys_copyarea(struct fb_info *info, const struct fb_copyarea
*area);
extern void sys_imageblit(struct fb_info *info, const struct fb_image *image);
@@ -549,6 +571,27 @@ extern ssize_t fb_sys_read(struct fb_info *info, char
__user *buf,
extern ssize_t fb_sys_write(struct fb_info *info, const char __user *buf,
size_t count, loff_t *ppos);
+/*
+ * Initializes struct fb_ops for framebuffers in system memory.
+ */
+
+#define __FB_DEFAULT_SYS_OPS_RDWR \
+ .fb_read= fb_sys_read, \
+ .fb_write = fb_sys_write
+
+#define __FB_DEFAULT_SYS_OPS_DRAW \
+ .fb_fillrect= sys_fillrect, \
+ .fb_copyarea= sys_copyarea, \
+ .fb_imageblit = sys_imageblit
+
+#define __FB_DEFAULT_SYS_OPS_MMAP \
+ .fb_mmap= NULL // default implementation
+
+#define FB_DEFAULT_SYS_OPS \
+ __FB_DEFAULT_SYS_OPS_RDWR, \
+ __FB_DEFAULT_SYS_OPS_DRAW, \
+ __FB_DEFAULT_SYS_OPS_MMAP
+
/* drivers/video/fbmem.c */
extern int register_framebuffer(struct fb_info *fb_info);
extern void unregister_framebuffer(struct fb_info *fb_info);
@@ -604,6 +647,75 @@ extern void fb_deferred_io_cleanup(struct fb_info *info);
extern int fb_deferred_io_fsync(struct file *file, loff_t start,
loff_t end, int datasync);
+/*
+ * Generate callbacks for deferred I/O
+ */
+
+#define __FB_GEN_DEFAULT_DEFERRED_OPS_RDWR(__prefix, __damage_range, __mode) \
+ static ssize_t __prefix ## _defio_read(struct fb_info *info, char
__user *buf, \
+ size_t count, loff_t *ppos) \
+ { \
+ return fb_ ## __mode ## _read(info, buf, count, ppos); \
+ } \
+ static ssize_t __prefix ## _defio_write(struct fb_info *info, const
char __user *buf, \
+ size_t count, loff_t *ppos) \
+ { \
+ unsigned long offset = *ppos; \
+ ssize_t ret = fb_ ## __mode ## _write(info, buf, count, ppos); \
+ if (ret > 0) \
+ __damage_range(info, offset, ret); \
+ return ret; \
+ }
+
+#define __FB_GEN_DEFAULT_DEFERRED_OPS_DRAW(__prefix, __damage_area, __mode) \
+ static void __prefix ## _defio_fillrect(struct fb_info *info, \
+ const struct fb_fillrect *rect)
\
+ { \
+ __mode ## _fillrect(info, rect); \
+ __damage_area(info, rect->dx, rect->dy, rect->width,
rect->height); \
+ } \
+ static void __prefix ## _defio_copyarea(struct fb_info *info, \
+ const struct fb_copyarea *area)
\
+ { \
+ __mode ## _copyarea(info, area); \
+ __damage_area(info, area->dx, area->dy, area->width,
area->height); \
+ } \
+ static vo
Re: [Intel-gfx] [PATCH v7 2/8] PCI/VGA: Deal only with VGA class devices
Hi,
On 2023/6/13 11:01, Sui Jingfeng wrote:
From: Sui Jingfeng
Deal only with the VGA devcie(pdev->class == 0x0300), so replace the
pci_get_subsys() function with pci_get_class(). Filter the non-PCI display
device(pdev->class != 0x0300) out. There no need to process the non-display
PCI device.
Cc: Bjorn Helgaas
Signed-off-by: Sui Jingfeng
---
drivers/pci/vgaarb.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/vgaarb.c b/drivers/pci/vgaarb.c
index c1bc6c983932..22a505e877dc 100644
--- a/drivers/pci/vgaarb.c
+++ b/drivers/pci/vgaarb.c
@@ -754,10 +754,6 @@ static bool vga_arbiter_add_pci_device(struct pci_dev
*pdev)
struct pci_dev *bridge;
u16 cmd;
- /* Only deal with VGA class devices */
- if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
- return false;
-
Hi, here is probably a bug fixing.
For an example, nvidia render only GPU typically has 0x0380.
at its PCI class number, but render only GPU should not participate in
the arbitration.
As it shouldn't snoop the legacy fixed VGA address.
It(render only GPU) can not display anything.
But 0x0380 >> 8 = 0x03, the filter failed.
/* Allocate structure */
vgadev = kzalloc(sizeof(struct vga_device), GFP_KERNEL);
if (vgadev == NULL) {
@@ -1500,7 +1496,9 @@ static int pci_notify(struct notifier_block *nb, unsigned
long action,
struct pci_dev *pdev = to_pci_dev(dev);
bool notify = false;
- vgaarb_dbg(dev, "%s\n", __func__);
+ /* Only deal with VGA class devices */
+ if (pdev->class != PCI_CLASS_DISPLAY_VGA << 8)
+ return 0;
So here we only care 0x0300, my initial intent is to make an optimization,
nowadays sane display graphic card should all has 0x0300 as its PCI
class number, is this complete right?
```
#define PCI_BASE_CLASS_DISPLAY 0x03
#define PCI_CLASS_DISPLAY_VGA 0x0300
#define PCI_CLASS_DISPLAY_XGA 0x0301
#define PCI_CLASS_DISPLAY_3D 0x0302
#define PCI_CLASS_DISPLAY_OTHER 0x0380
```
Any ideas ?
/* For now we're only intereted in devices added and removed. I didn't
* test this thing here, so someone needs to double check for the
@@ -1510,6 +1508,8 @@ static int pci_notify(struct notifier_block *nb, unsigned
long action,
else if (action == BUS_NOTIFY_DEL_DEVICE)
notify = vga_arbiter_del_pci_device(pdev);
+ vgaarb_dbg(dev, "%s: action = %lu\n", __func__, action);
+
if (notify)
vga_arbiter_notify_clients();
return 0;
@@ -1534,8 +1534,8 @@ static struct miscdevice vga_arb_device = {
static int __init vga_arb_device_init(void)
{
+ struct pci_dev *pdev = NULL;
int rc;
- struct pci_dev *pdev;
rc = misc_register(&vga_arb_device);
if (rc < 0)
@@ -1545,11 +1545,13 @@ static int __init vga_arb_device_init(void)
/* We add all PCI devices satisfying VGA class in the arbiter by
* default */
- pdev = NULL;
- while ((pdev =
- pci_get_subsys(PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_ANY_ID, pdev)) != NULL)
+ while (1) {
+ pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev);
+ if (!pdev)
+ break;
+
vga_arbiter_add_pci_device(pdev);
+ }
pr_info("loaded\n");
return rc;
--
Jingfeng
Re: [Intel-gfx] [PATCH v7 8/9] vfio/pci: Extend VFIO_DEVICE_GET_PCI_HOT_RESET_INFO for vfio device cdev
> From: Jason Gunthorpe
> Sent: Wednesday, June 14, 2023 2:23 AM
>
> On Fri, Jun 02, 2023 at 05:15:14AM -0700, Yi Liu wrote:
> > This allows VFIO_DEVICE_GET_PCI_HOT_RESET_INFO ioctl use the iommufd_ctx
> > of the cdev device to check the ownership of the other affected devices.
> >
> > When VFIO_DEVICE_GET_PCI_HOT_RESET_INFO is called on an IOMMUFD managed
> > device, the new flag VFIO_PCI_HOT_RESET_FLAG_DEV_ID is reported to indicate
> > the values returned are IOMMUFD devids rather than group IDs as used when
> > accessing vfio devices through the conventional vfio group interface.
> > Additionally the flag VFIO_PCI_HOT_RESET_FLAG_DEV_ID_OWNED will be reported
> > in this mode if all of the devices affected by the hot-reset are owned by
> > either virtue of being directly bound to the same iommufd context as the
> > calling device, or implicitly owned via a shared IOMMU group.
> >
> > Suggested-by: Jason Gunthorpe
> > Suggested-by: Alex Williamson
> > Signed-off-by: Yi Liu
> > ---
> > drivers/vfio/iommufd.c | 49 +++
> > drivers/vfio/pci/vfio_pci_core.c | 47 +-
> > include/linux/vfio.h | 16 ++
> > include/uapi/linux/vfio.h| 50 +++-
> > 4 files changed, 154 insertions(+), 8 deletions(-)
>
> This could use some more fiddling, like we could copy each
> vfio_pci_dependent_device to user memory inside the loop instead of
> allocating an array.
I understand the motivation. But have some concerns. Please check
inline.
> Add another patch with something like this in it:
>
> diff --git a/drivers/vfio/pci/vfio_pci_core.c
> b/drivers/vfio/pci/vfio_pci_core.c
> index b0eadafcbcf502..516e0fda74bec9 100644
> --- a/drivers/vfio/pci/vfio_pci_core.c
> +++ b/drivers/vfio/pci/vfio_pci_core.c
> @@ -775,19 +775,23 @@ static int vfio_pci_count_devs(struct pci_dev *pdev,
> void
> *data)
> }
>
> struct vfio_pci_fill_info {
> - int max;
> - int cur;
> - struct vfio_pci_dependent_device *devices;
> + struct vfio_pci_dependent_device __user *devices;
> + struct vfio_pci_dependent_device __user *devices_end;
> struct vfio_device *vdev;
> u32 flags;
> };
>
> static int vfio_pci_fill_devs(struct pci_dev *pdev, void *data)
> {
> + struct vfio_pci_dependent_device info = {
> + .segment = pci_domain_nr(pdev->bus),
> + .bus = pdev->bus->number,
> + .devfn = pdev->devfn,
> + };
> struct vfio_pci_fill_info *fill = data;
>
> - if (fill->cur == fill->max)
> - return -EAGAIN; /* Something changed, try again */
> + if (fill->devices_end >= fill->devices)
> + return -ENOSPC;
This should be fill->devices_end <= fill->devices. Even it's corrected. The
new code does not return -EAGAIN. And if return -ENOSPC, the expected
size should be returned. But I didn't see it. As the hunk below[1] is removed,
seems no way to know how many memory it requires.
>
> if (fill->flags & VFIO_PCI_HOT_RESET_FLAG_DEV_ID) {
> struct iommufd_ctx *iommufd =
> vfio_iommufd_device_ictx(fill->vdev);
> @@ -800,12 +804,12 @@ static int vfio_pci_fill_devs(struct pci_dev *pdev,
> void *data)
>*/
> vdev = vfio_find_device_in_devset(dev_set, &pdev->dev);
> if (!vdev)
> - fill->devices[fill->cur].devid =
> VFIO_PCI_DEVID_NOT_OWNED;
> + info.devid = VFIO_PCI_DEVID_NOT_OWNED;
> else
> - fill->devices[fill->cur].devid =
> - vfio_iommufd_device_hot_reset_devid(vdev,
> iommufd);
> + info.devid = vfio_iommufd_device_hot_reset_devid(
> + vdev, iommufd);
> /* If devid is VFIO_PCI_DEVID_NOT_OWNED, clear owned flag. */
> - if (fill->devices[fill->cur].devid == VFIO_PCI_DEVID_NOT_OWNED)
> + if (info.devid == VFIO_PCI_DEVID_NOT_OWNED)
> fill->flags &= ~VFIO_PCI_HOT_RESET_FLAG_DEV_ID_OWNED;
> } else {
> struct iommu_group *iommu_group;
> @@ -814,13 +818,13 @@ static int vfio_pci_fill_devs(struct pci_dev *pdev,
> void *data)
> if (!iommu_group)
> return -EPERM; /* Cannot reset non-isolated devices */
>
> - fill->devices[fill->cur].group_id = iommu_group_id(iommu_group);
> + info.group_id = iommu_group_id(iommu_group);
> iommu_group_put(iommu_group);
> }
> - fill->devices[fill->cur].segment = pci_domain_nr(pdev->bus);
> - fill->devices[fill->cur].bus = pdev->bus->number;
> - fill->devices[fill->cur].devfn = pdev->devfn;
> - fill->cur++;
> +
> + if (copy_to_user(fill->devices, &info, sizeof(info)))
> + return -EFAULT;
> + fill->devices++;
> return 0;
> }
>
> @@ -1212,8 +1216,7 @@ static int vfio_pci_ioctl_get_pci_hot_reset_
[Intel-gfx] ✗ Fi.CI.IGT: failure for Move stolen memory handling details into i915_gem_stolen (rev2)
== Series Details == Series: Move stolen memory handling details into i915_gem_stolen (rev2) URL : https://patchwork.freedesktop.org/series/119123/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13269_full -> Patchwork_119123v2_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_119123v2_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_119123v2_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (8 -> 8) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_119123v2_full: ### IGT changes ### Possible regressions * igt@syncobj_timeline@invalid-transfer-bad-pad: - shard-glk: [PASS][1] -> [TIMEOUT][2] +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-glk9/igt@syncobj_timel...@invalid-transfer-bad-pad.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119123v2/shard-glk9/igt@syncobj_timel...@invalid-transfer-bad-pad.html Known issues Here are the changes found in Patchwork_119123v2_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglu: [PASS][3] -> [FAIL][4] ([i915#6268]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-tglu-9/igt@gem_ctx_e...@basic-nohangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119123v2/shard-tglu-5/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-rkl: [PASS][5] -> [FAIL][6] ([i915#2842]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-rkl-6/igt@gem_exec_fair@basic-pace-s...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119123v2/shard-rkl-3/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_lmem_swapping@heavy-verify-multi-ccs: - shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119123v2/shard-glk9/igt@gem_lmem_swapp...@heavy-verify-multi-ccs.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-tglu: NOTRUN -> [SKIP][8] ([i915#4613]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119123v2/shard-tglu-4/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gen9_exec_parse@allowed-all: - shard-apl: [PASS][9] -> [ABORT][10] ([i915#5566]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-apl4/igt@gen9_exec_pa...@allowed-all.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119123v2/shard-apl4/igt@gen9_exec_pa...@allowed-all.html * igt@i915_pm_dc@dc6-dpms: - shard-tglu: [PASS][11] -> [FAIL][12] ([i915#3989] / [i915#454]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-tglu-2/igt@i915_pm...@dc6-dpms.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119123v2/shard-tglu-8/igt@i915_pm...@dc6-dpms.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-rkl: [PASS][13] -> [SKIP][14] ([i915#1397]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-rkl-6/igt@i915_pm_...@dpms-non-lpsp.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119123v2/shard-rkl-7/igt@i915_pm_...@dpms-non-lpsp.html * igt@kms_big_joiner@basic: - shard-tglu: NOTRUN -> [SKIP][15] ([i915#2705]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119123v2/shard-tglu-4/igt@kms_big_joi...@basic.html * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs: - shard-glk: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3886]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119123v2/shard-glk9/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-apl: [PASS][17] -> [FAIL][18] ([i915#2346]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-apl2/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119123v2/shard-apl7/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_cursor_legacy@single-move@pipe-b: - shard-rkl: [PASS][19] -> [INCOMPLETE][20] ([i915#8011]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-rkl-6/igt@kms_cursor_legacy@single-m...@pipe-b.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gsc: define gsc fw
== Series Details == Series: drm/i915/gsc: define gsc fw URL : https://patchwork.freedesktop.org/series/119310/ State : success == Summary == CI Bug Log - changes from CI_DRM_13269_full -> Patchwork_119310v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (8 -> 8) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_119310v1_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_fdinfo@most-busy-check-all@rcs0: - shard-rkl: [PASS][1] -> [FAIL][2] ([i915#7742]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-rkl-4/igt@drm_fdinfo@most-busy-check-...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-rkl-1/igt@drm_fdinfo@most-busy-check-...@rcs0.html * igt@gem_barrier_race@remote-request@rcs0: - shard-glk: [PASS][3] -> [ABORT][4] ([i915#7461] / [i915#8211]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-glk2/igt@gem_barrier_race@remote-requ...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-glk6/igt@gem_barrier_race@remote-requ...@rcs0.html * igt@gem_basic@multigpu-create-close: - shard-rkl: NOTRUN -> [SKIP][5] ([i915#7697]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-rkl-4/igt@gem_ba...@multigpu-create-close.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglu: [PASS][6] -> [FAIL][7] ([i915#6268]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-tglu-9/igt@gem_ctx_e...@basic-nohangcheck.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-tglu-3/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_eio@hibernate: - shard-rkl: NOTRUN -> [ABORT][8] ([i915#7975] / [i915#8213]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-rkl-4/igt@gem_...@hibernate.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-rkl: NOTRUN -> [FAIL][9] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-rkl-4/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-glk5/igt@gem_exec_fair@basic-none-sh...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-glk3/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-rkl: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-rkl-6/igt@gem_exec_fair@basic-pace-s...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-rkl-4/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_reloc@basic-gtt-wc: - shard-rkl: NOTRUN -> [SKIP][14] ([i915#3281]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-rkl-4/igt@gem_exec_re...@basic-gtt-wc.html * igt@gem_huc_copy@huc-copy: - shard-rkl: NOTRUN -> [SKIP][15] ([i915#2190]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-rkl-4/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-verify-multi-ccs: - shard-glk: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-glk3/igt@gem_lmem_swapp...@heavy-verify-multi-ccs.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-tglu: NOTRUN -> [SKIP][17] ([i915#4613]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-tglu-4/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_pread@snoop: - shard-rkl: NOTRUN -> [SKIP][18] ([i915#3282]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-rkl-4/igt@gem_pr...@snoop.html * igt@gem_pxp@reject-modify-context-protection-off-1: - shard-rkl: NOTRUN -> [SKIP][19] ([i915#4270]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-rkl-4/igt@gem_...@reject-modify-context-protection-off-1.html * igt@gem_softpin@evict-snoop-interruptible: - shard-rkl: NOTRUN -> [SKIP][20] ([fdo#109312]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-rkl-4/igt@gem_soft...@evict-snoop-interruptible.html * igt@gen9_exec_parse@allowed-all: - shard-apl: [PASS][21] -> [ABORT][22] ([i915#5566]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-apl4/igt@gen9_exec_pa...@allowed-all.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119310v1/shard-apl2/igt@gen9_exec_pa..
[Intel-gfx] ✓ Fi.CI.IGT: success for Use non traceable api in display trace code
== Series Details == Series: Use non traceable api in display trace code URL : https://patchwork.freedesktop.org/series/119303/ State : success == Summary == CI Bug Log - changes from CI_DRM_13269_full -> Patchwork_119303v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (8 -> 7) -- Missing(1): shard-rkl0 Known issues Here are the changes found in Patchwork_119303v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_basic@multigpu-create-close: - shard-rkl: NOTRUN -> [SKIP][1] ([i915#7697]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-rkl-1/igt@gem_ba...@multigpu-create-close.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglu: [PASS][2] -> [FAIL][3] ([i915#6268]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-tglu-9/igt@gem_ctx_e...@basic-nohangcheck.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-tglu-2/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_eio@hibernate: - shard-rkl: NOTRUN -> [ABORT][4] ([i915#7975] / [i915#8213]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-rkl-1/igt@gem_...@hibernate.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-rkl: NOTRUN -> [FAIL][5] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-rkl-1/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-glk5/igt@gem_exec_fair@basic-none-sh...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-glk3/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@bcs0: - shard-rkl: [PASS][8] -> [FAIL][9] ([i915#2842]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-rkl-6/igt@gem_exec_fair@basic-n...@bcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-rkl-4/igt@gem_exec_fair@basic-n...@bcs0.html * igt@gem_exec_reloc@basic-gtt-wc: - shard-rkl: NOTRUN -> [SKIP][10] ([i915#3281]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-rkl-1/igt@gem_exec_re...@basic-gtt-wc.html * igt@gem_huc_copy@huc-copy: - shard-rkl: NOTRUN -> [SKIP][11] ([i915#2190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-rkl-1/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-verify-multi-ccs: - shard-glk: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-glk2/igt@gem_lmem_swapp...@heavy-verify-multi-ccs.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-tglu: NOTRUN -> [SKIP][13] ([i915#4613]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-tglu-7/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_pread@snoop: - shard-rkl: NOTRUN -> [SKIP][14] ([i915#3282]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-rkl-1/igt@gem_pr...@snoop.html * igt@gem_pxp@reject-modify-context-protection-off-1: - shard-rkl: NOTRUN -> [SKIP][15] ([i915#4270]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-rkl-1/igt@gem_...@reject-modify-context-protection-off-1.html * igt@gem_softpin@evict-snoop-interruptible: - shard-rkl: NOTRUN -> [SKIP][16] ([fdo#109312]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-rkl-1/igt@gem_soft...@evict-snoop-interruptible.html * igt@gen9_exec_parse@allowed-all: - shard-apl: [PASS][17] -> [ABORT][18] ([i915#5566]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-apl4/igt@gen9_exec_pa...@allowed-all.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-apl6/igt@gen9_exec_pa...@allowed-all.html * igt@gen9_exec_parse@bb-start-param: - shard-rkl: NOTRUN -> [SKIP][19] ([i915#2527]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-rkl-1/igt@gen9_exec_pa...@bb-start-param.html * igt@i915_pm_dc@dc6-dpms: - shard-tglu: [PASS][20] -> [FAIL][21] ([i915#3989] / [i915#454]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-tglu-2/igt@i915_pm...@dc6-dpms.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119303v1/shard-tglu-6/igt@i915_pm...@dc6-dpms.html * igt@kms_big_fb@4-tiled-32bpp-rotate-270: - shard-rkl: NOTRUN -> [SKIP][22] ([i915#5286]) [22]: https://intel-gfx-ci.01.org/tree/dr
Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Apply min softlimit correctly
On 6/13/2023 7:25 PM, Dixit, Ashutosh wrote:
On Fri, 09 Jun 2023 15:02:52 -0700, Vinay Belgaumkar wrote:
Hi Vinay,
We were skipping when min_softlimit was equal to RPn. We need to apply
it rergardless as efficient frequency will push the SLPC min to RPe.
regardless
This will break scenarios where user sets a min softlimit < RPe before
reset and then performs a GT reset.
Can you explain the reason for the patch clearly in terms of variables in
the code, what variable has what value and what is the bug. I am not
following from the above description.
Hi Ashutosh,
Scenario being fixed here is exactly the one in i915_pm_freq_api
reset/suspend subtests (currently in review). Test sets min freq to RPn
and then performs a reset. It then checks if cur_freq is RPn.
Here's the sequence that shows the problem-
RPLS:/home/gta# modprobe i915
RPLS:/home/gta# echo 1 > /sys/class/drm/card0/gt/gt0/slpc_ignore_eff_freq
RPLS:/home/gta# echo 300 > /sys/class/drm/card0/gt_min_freq_mhz (RPn)
RPLS:/home/gta# cat /sys/class/drm/card0/gt_cur_freq_mhz --> cur == RPn
as expected
300
RPLS:/home/gta# echo 1 > /sys/kernel/debug/dri/0/gt0/reset --> reset
RPLS:/home/gta# cat /sys/class/drm/card0/gt_min_freq_mhz --> shows the
internal cached variable correctly
300
RPLS:/home/gta# cat /sys/class/drm/card0/gt_cur_freq_mhz --> actual freq
being requested by SLPC (it's not RPn!!)
700
We need to sync up driver min freq value and SLPC min after a
reset/suspend. Currently, we skip if the user had manually set min to
RPn (this was an optimization we had before we enabled efficient freq
usage).
Thanks,
Vinay.
Thanks.
--
Ashutosh
Fixes: 95ccf312a1e4 ("drm/i915/guc/slpc: Allow SLPC to use efficient frequency")
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 01b75529311c..ee9f83af7cf6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -606,7 +606,7 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
if (unlikely(ret))
return ret;
slpc_to_gt(slpc)->defaults.min_freq = slpc->min_freq_softlimit;
- } else if (slpc->min_freq_softlimit != slpc->min_freq) {
+ } else {
return intel_guc_slpc_set_min_freq(slpc,
slpc->min_freq_softlimit);
}
--
2.38.1
