[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/gt: Do not use stolen on MTL
== Series Details == Series: series starting with [1/2] drm/i915/gt: Do not use stolen on MTL URL : https://patchwork.freedesktop.org/series/120086/ State : success == Summary == CI Bug Log - changes from CI_DRM_13340_full -> Patchwork_120086v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_120086v1_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_fdinfo@most-busy-check-all@rcs0: - shard-rkl: [PASS][1] -> [FAIL][2] ([i915#7742]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-rkl-2/igt@drm_fdinfo@most-busy-check-...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-rkl-2/igt@drm_fdinfo@most-busy-check-...@rcs0.html * igt@gem_create@create-ext-set-pat: - shard-dg2: NOTRUN -> [FAIL][3] ([i915#8621]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-dg2-1/igt@gem_cre...@create-ext-set-pat.html * igt@gem_eio@hibernate: - shard-dg2: [PASS][4] -> [ABORT][5] ([i915#7975] / [i915#8213]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-dg2-11/igt@gem_...@hibernate.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-dg2-7/igt@gem_...@hibernate.html * igt@gem_exec_balancer@bonded-false-hang: - shard-dg2: NOTRUN -> [SKIP][6] ([i915#4812]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-dg2-12/igt@gem_exec_balan...@bonded-false-hang.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2846]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-glk2/igt@gem_exec_f...@basic-deadline.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-glk3/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-pace-solo: - shard-dg2: NOTRUN -> [SKIP][9] ([i915#3539]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-dg2-1/igt@gem_exec_f...@basic-pace-solo.html * igt@gem_exec_flush@basic-wb-prw-default: - shard-dg2: NOTRUN -> [SKIP][10] ([i915#3539] / [i915#4852]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-dg2-12/igt@gem_exec_fl...@basic-wb-prw-default.html * igt@gem_exec_gttfill@multigpu-basic: - shard-mtlp: NOTRUN -> [SKIP][11] ([i915#7697]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-mtlp-2/igt@gem_exec_gttf...@multigpu-basic.html * igt@gem_exec_reloc@basic-wc-active: - shard-mtlp: NOTRUN -> [SKIP][12] ([i915#3281]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-mtlp-2/igt@gem_exec_re...@basic-wc-active.html * igt@gem_exec_suspend@basic-s4-devices@lmem0: - shard-dg2: NOTRUN -> [ABORT][13] ([i915#7975] / [i915#8213] / [i915#8682]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-dg2-12/igt@gem_exec_suspend@basic-s4-devi...@lmem0.html * igt@gem_exec_whisper@basic-normal: - shard-mtlp: [PASS][14] -> [FAIL][15] ([i915#6363]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-mtlp-5/igt@gem_exec_whis...@basic-normal.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-mtlp-4/igt@gem_exec_whis...@basic-normal.html * igt@gem_lmem_swapping@heavy-verify-random-ccs: - shard-mtlp: NOTRUN -> [SKIP][16] ([i915#4613]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-mtlp-2/igt@gem_lmem_swapp...@heavy-verify-random-ccs.html * igt@gem_mmap_gtt@basic-small-copy: - shard-mtlp: NOTRUN -> [SKIP][17] ([i915#4077]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-mtlp-5/igt@gem_mmap_...@basic-small-copy.html * igt@gem_mmap_gtt@medium-copy-xy: - shard-dg2: NOTRUN -> [SKIP][18] ([i915#4077]) +5 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-dg2-12/igt@gem_mmap_...@medium-copy-xy.html * igt@gem_mmap_wc@set-cache-level: - shard-dg2: NOTRUN -> [SKIP][19] ([i915#4083]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-dg2-12/igt@gem_mmap...@set-cache-level.html * igt@gem_pwrite_snooped: - shard-dg2: NOTRUN -> [SKIP][20] ([i915#3282]) +3 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-dg2-12/igt@gem_pwrite_snooped.html * igt@gem_pxp@create-regular-buffer: - shard-mtlp: NOTRUN -> [SKIP][21] ([i915#4270]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/shard-mtlp-8/igt@gem_...@crea
[Intel-gfx] [drm-intel:drm-intel-next 1/2] htmldocs: Documentation/gpu/rfc/i915_scheduler.rst:138: WARNING: Unknown directive type "c:namespace-push".
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next head: 0c4f52bac4401dfd6f82984040bc0e163b0ccb9c commit: f6757dfcfde722fdeaee371b66f63d7eb61dd7e4 [1/2] drm/doc: fix duplicate declaration warning reproduce: (https://download.01.org/0day-ci/archive/20230701/202307011340.vny1abul-...@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202307011340.vny1abul-...@intel.com/ All warnings (new ones prefixed by >>): >> Documentation/gpu/rfc/i915_scheduler.rst:138: WARNING: Unknown directive >> type "c:namespace-push". >> Documentation/gpu/rfc/i915_scheduler.rst:143: WARNING: Unknown directive >> type "c:namespace-pop". vim +138 Documentation/gpu/rfc/i915_scheduler.rst 137 > 138 .. c:namespace-push:: rfc 139 140 .. kernel-doc:: include/uapi/drm/i915_drm.h 141 :functions: i915_context_engines_parallel_submit 142 > 143 .. c:namespace-pop:: 144 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki
[Intel-gfx] ✗ Fi.CI.IGT: failure for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev15)
== Series Details == Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev15) URL : https://patchwork.freedesktop.org/series/107550/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13340_full -> Patchwork_107550v15_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_107550v15_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107550v15_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_107550v15_full: ### IGT changes ### Possible regressions * igt@perf_pmu@rc6-suspend: - shard-dg2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-dg2-12/igt@perf_...@rc6-suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/shard-dg2-7/igt@perf_...@rc6-suspend.html Known issues Here are the changes found in Patchwork_107550v15_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_fdinfo@all-busy-idle-check-all: - shard-dg2: NOTRUN -> [SKIP][3] ([i915#8414]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/shard-dg2-11/igt@drm_fdi...@all-busy-idle-check-all.html * igt@drm_fdinfo@most-busy-check-all@rcs0: - shard-rkl: [PASS][4] -> [FAIL][5] ([i915#7742]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-rkl-2/igt@drm_fdinfo@most-busy-check-...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/shard-rkl-1/igt@drm_fdinfo@most-busy-check-...@rcs0.html * igt@gem_create@create-ext-set-pat: - shard-dg2: NOTRUN -> [FAIL][6] ([i915#8621]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/shard-dg2-12/igt@gem_cre...@create-ext-set-pat.html * igt@gem_eio@hibernate: - shard-dg2: [PASS][7] -> [ABORT][8] ([i915#7975] / [i915#8213]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-dg2-11/igt@gem_...@hibernate.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/shard-dg2-1/igt@gem_...@hibernate.html * igt@gem_exec_balancer@bonded-false-hang: - shard-dg2: NOTRUN -> [SKIP][9] ([i915#4812]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/shard-dg2-11/igt@gem_exec_balan...@bonded-false-hang.html * igt@gem_exec_fair@basic-deadline: - shard-rkl: [PASS][10] -> [FAIL][11] ([i915#2846]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-rkl-1/igt@gem_exec_f...@basic-deadline.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/shard-rkl-4/igt@gem_exec_f...@basic-deadline.html - shard-glk: [PASS][12] -> [FAIL][13] ([i915#2846]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-glk2/igt@gem_exec_f...@basic-deadline.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/shard-glk3/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-rkl: [PASS][14] -> [FAIL][15] ([i915#2842]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-rkl-1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/shard-rkl-6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo: - shard-dg2: NOTRUN -> [SKIP][16] ([i915#3539]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/shard-dg2-12/igt@gem_exec_f...@basic-pace-solo.html * igt@gem_exec_flush@basic-wb-prw-default: - shard-dg2: NOTRUN -> [SKIP][17] ([i915#3539] / [i915#4852]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/shard-dg2-11/igt@gem_exec_fl...@basic-wb-prw-default.html * igt@gem_exec_schedule@deep@vcs0: - shard-mtlp: [PASS][18] -> [FAIL][19] ([i915#8545]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-mtlp-1/igt@gem_exec_schedule@d...@vcs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/shard-mtlp-4/igt@gem_exec_schedule@d...@vcs0.html * igt@gem_exec_whisper@basic-normal: - shard-mtlp: [PASS][20] -> [FAIL][21] ([i915#6363]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-mtlp-5/igt@gem_exec_whis...@basic-normal.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/shard-mtlp-8/igt@gem_exec_whis...@basic-normal.html
[Intel-gfx] ✓ Fi.CI.IGT: success for DSC misc fixes (rev3)
== Series Details == Series: DSC misc fixes (rev3) URL : https://patchwork.freedesktop.org/series/117662/ State : success == Summary == CI Bug Log - changes from CI_DRM_13340_full -> Patchwork_117662v3_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts New tests - New tests have been introduced between CI_DRM_13340_full and Patchwork_117662v3_full: ### New IGT tests (4) ### * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-a-hdmi-a-3: - Statuses : 2 pass(s) - Exec time: [0.0] s * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-b-hdmi-a-3: - Statuses : 2 pass(s) - Exec time: [0.0] s * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-hdmi-a-3: - Statuses : 2 pass(s) - Exec time: [0.0] s * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-hdmi-a-3: - Statuses : 2 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_117662v3_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_fdinfo@most-busy-check-all@rcs0: - shard-rkl: [PASS][1] -> [FAIL][2] ([i915#7742]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-rkl-2/igt@drm_fdinfo@most-busy-check-...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/shard-rkl-2/igt@drm_fdinfo@most-busy-check-...@rcs0.html * igt@drm_fdinfo@virtual-busy-hang: - shard-mtlp: NOTRUN -> [SKIP][3] ([i915#8414]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/shard-mtlp-7/igt@drm_fdi...@virtual-busy-hang.html * igt@gem_create@create-ext-set-pat: - shard-dg2: NOTRUN -> [FAIL][4] ([i915#8621]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/shard-dg2-10/igt@gem_cre...@create-ext-set-pat.html * igt@gem_ctx_persistence@heartbeat-stop: - shard-mtlp: NOTRUN -> [SKIP][5] ([i915#8555]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/shard-mtlp-7/igt@gem_ctx_persiste...@heartbeat-stop.html * igt@gem_eio@hibernate: - shard-dg2: [PASS][6] -> [ABORT][7] ([i915#7975] / [i915#8213]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-dg2-11/igt@gem_...@hibernate.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/shard-dg2-7/igt@gem_...@hibernate.html * igt@gem_exec_balancer@bonded-false-hang: - shard-dg2: NOTRUN -> [SKIP][8] ([i915#4812]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/shard-dg2-3/igt@gem_exec_balan...@bonded-false-hang.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-rkl: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-rkl-1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/shard-rkl-1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo: - shard-dg2: NOTRUN -> [SKIP][11] ([i915#3539]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/shard-dg2-10/igt@gem_exec_f...@basic-pace-solo.html * igt@gem_exec_flush@basic-wb-prw-default: - shard-dg2: NOTRUN -> [SKIP][12] ([i915#3539] / [i915#4852]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/shard-dg2-3/igt@gem_exec_fl...@basic-wb-prw-default.html * igt@gem_exec_suspend@basic-s4-devices@lmem0: - shard-dg2: NOTRUN -> [ABORT][13] ([i915#7975] / [i915#8213] / [i915#8682]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/shard-dg2-3/igt@gem_exec_suspend@basic-s4-devi...@lmem0.html * igt@gem_exec_whisper@basic-normal: - shard-mtlp: [PASS][14] -> [FAIL][15] ([i915#6363]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-mtlp-5/igt@gem_exec_whis...@basic-normal.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/shard-mtlp-4/igt@gem_exec_whis...@basic-normal.html * igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible: - shard-mtlp: NOTRUN -> [SKIP][16] ([i915#4860]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/shard-mtlp-7/igt@gem_fenced_exec_thr...@no-spare-fences-busy-interruptible.html * igt@gem_lmem_swapping@heavy-verify-random-ccs: - shard-mtlp: NOTRUN -> [SKIP][17] ([i915#4613]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/shard-mtlp-3/igt@gem_lmem_swapp...@heavy-verify-random-ccs.html * igt@gem_lmem_swapping@smem-oom@lmem0: - shard-dg2: [PASS][18] -> [TIMEOUT][19] ([i915#5493]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/shard-dg2-7/igt@gem_lmem_sw
Re: [Intel-gfx] [PATCH v3 0/7] Fix ctx workarounds for non-masked regs
On Friday, June 30, 2023 1:35:02 PM PDT Lucas De Marchi wrote: > v3 of https://patchwork.freedesktop.org/series/119766/ > > Changes from v2: > > - Do not rmw if (clr | set) covers all bits > - Add patch to make sure the set bits are also checked on > wa_*_clr_set() when clr is not a superset. > > Tested on DG2 with intel_reg reading 0xb158 with a busy render engine. > Now it's not losing the upper bit anymore. > > Lucas De Marchi (7): > drm/i915/gt: Move wal_get_fw_for_rmw() > drm/i915/gt: Clear all bits from GEN12_FF_MODE2 > drm/i915/gt: Fix context workarounds with non-masked regs > drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround > drm/i915/gt: Enable read back on XEHP_FF_MODE2 > drm/i915/gt: Remove bogus comment on IVB_FBC_RT_BASE_UPPER > drm/i915/gt: Also check set bits in clr_set() > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 129 ++-- > 1 file changed, 66 insertions(+), 63 deletions(-) Whole series is now: Reviewed-by: Kenneth Graunke Thanks a lot for fixing this, Lucas! signature.asc Description: This is a digitally signed message part.
[Intel-gfx] ✓ Fi.CI.BAT: success for Fix ctx workarounds for non-masked regs (rev3)
== Series Details == Series: Fix ctx workarounds for non-masked regs (rev3) URL : https://patchwork.freedesktop.org/series/119826/ State : success == Summary == CI Bug Log - changes from CI_DRM_13340 -> Patchwork_119826v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/index.html Participating hosts (42 -> 39) -- Missing(3): fi-kbl-soraka fi-kbl-7567u fi-snb-2520m Known issues Here are the changes found in Patchwork_119826v3 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@parallel-random-engines: - bat-mtlp-8: NOTRUN -> [SKIP][1] ([i915#4613]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/bat-mtlp-8/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_pm_rps@basic-api: - bat-mtlp-8: NOTRUN -> [SKIP][2] ([i915#6621]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/bat-mtlp-8/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@requests: - bat-rpls-2: [PASS][3] -> [ABORT][4] ([i915#4983] / [i915#7913]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-rpls-2/igt@i915_selftest@l...@requests.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/bat-rpls-2/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@slpc: - bat-mtlp-8: NOTRUN -> [DMESG-WARN][5] ([i915#6367]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/bat-mtlp-8/igt@i915_selftest@l...@slpc.html * igt@i915_suspend@basic-s3-without-i915: - bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#6645]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/bat-mtlp-8/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#7828]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/bat-mtlp-8/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#1845] / [i915#5354]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_psr@primary_mmap_gtt: - bat-rplp-1: NOTRUN -> [SKIP][9] ([i915#1072]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html * igt@kms_setmode@basic-clone-single-crtc: - bat-rplp-1: NOTRUN -> [ABORT][10] ([i915#8260] / [i915#8668]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-read: - bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#3708]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/bat-mtlp-8/igt@prime_v...@basic-fence-read.html * igt@prime_vgem@basic-gtt: - bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#3708] / [i915#4077]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/bat-mtlp-8/igt@prime_v...@basic-gtt.html Possible fixes * igt@i915_pm_rpm@basic-pci-d3-state: - bat-mtlp-8: [ABORT][13] ([i915#7077] / [i915#7977]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-8/igt@i915_pm_...@basic-pci-d3-state.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/bat-mtlp-8/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-6: [DMESG-FAIL][15] ([i915#7059]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@hangcheck: - fi-skl-guc: [DMESG-FAIL][17] ([i915#8723]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html Warnings * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-hdmi-a-2: - fi-skl-guc: [SKIP][19] ([fdo#109271] / [i915#4579]) -> [SKIP][20] ([fdo#109271]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-c-hdmi-a-2.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119826v3/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-c-hdmi-a
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix ctx workarounds for non-masked regs (rev3)
== Series Details == Series: Fix ctx workarounds for non-masked regs (rev3) URL : https://patchwork.freedesktop.org/series/119826/ State : warning == Summary == Error: dim checkpatch failed f9ace84612b8 drm/i915/gt: Move wal_get_fw_for_rmw() 98981921388c drm/i915/gt: Clear all bits from GEN12_FF_MODE2 eb7d4114d6aa drm/i915/gt: Fix context workarounds with non-masked regs 8f8c8e52b8f1 drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround 37b65fa3e839 drm/i915/gt: Enable read back on XEHP_FF_MODE2 f51f5bbbc763 drm/i915/gt: Remove bogus comment on IVB_FBC_RT_BASE_UPPER 9ed2964f40d6 drm/i915/gt: Also check set bits in clr_set() -:6: WARNING:TYPO_SPELLING: 'succesfully' may be misspelled - perhaps 'successfully'? #6: When checking if the workarounds were applied succesfully, the read-back ^^^ total: 0 errors, 1 warnings, 0 checks, 15 lines checked
[Intel-gfx] [PATCH v3 3/7] drm/i915/gt: Fix context workarounds with non-masked regs
Most of the context workarounds tweak masked registers, but not all. For
masked registers, when writing the value it's sufficient to just write
the wa->set_bits since that will take care of both the clr and set bits
as well as not overwriting other bits.
However there are some workarounds, the registers are non-masked. Up
until now the driver was simply emitting a MI_LOAD_REGISTER_IMM with the
set_bits to program the register via the GPU in the WA bb. This has the
side effect of overwriting the content of the register outside of bits
that should be set and also doesn't handle the bits that should be
cleared.
Kenneth reported that on DG2, mesa was seeing a weird behavior due to
the kernel programming of L3SQCREG5 in dg2_ctx_gt_tuning_init(). With
the GPU idle, that register could be read via intel_reg as 0x00e001ff,
but during a 3D workload it would change to 0x007f. So the
programming of that tuning was affecting more than the bits in
L3_PWM_TIMER_INIT_VAL_MASK. Matt Roper noticed the lack of rmw for the
context workarounds due to the use of MI_LOAD_REGISTER_IMM.
So, for registers that are not masked, read its value via mmio, modify
and then set it in the buffer to be written by the GPU. This should take
care in a simple way of programming just the bits required by the
tuning/workaround. If in future there are registers that involved that
can't be read by the CPU, a more complex approach may be required like
a) issuing additional instructions to read and modify; or b) scan the
golden context and patch it in place before saving it; or something
else. But for now this should suffice.
Scanning the context workarounds for all platforms, these are the
impacted ones with the respective registers
mtl: DRAW_WATERMARK
mtl/dg2: XEHP_L3SQCREG5, XEHP_FF_MODE2
ICL has some non-masked registers in the context workarounds:
GEN8_L3CNTLREG, IVB_FBC_RT_BASE and VB_FBC_RT_BASE_UPPER, but there
shouldn't be an impact. The first is already being manually read and the
other 2 are intentionally overwriting the entire register. Same
reasoning applies to GEN12_FF_MODE2: the WA is intentionally
overwriting all the bits to avoid a read-modify-write.
v2: Reword commit message wrt GEN12_FF_MODE2 and the changed behavior
on preparatory patches.
v3: Also skip reading if clear|set bits covers everything
Cc: Kenneth Graunke
Cc: Matt Roper
Link:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23783#note_1968971
Signed-off-by: Lucas De Marchi
Reviewed-by: Kenneth Graunke
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 28 -
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 7d48bd57b6ef..0a9c3be4817c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -986,6 +986,9 @@ void intel_engine_init_ctx_wa(struct intel_engine_cs
*engine)
int intel_engine_emit_ctx_wa(struct i915_request *rq)
{
struct i915_wa_list *wal = &rq->engine->ctx_wa_list;
+ struct intel_uncore *uncore = rq->engine->uncore;
+ enum forcewake_domains fw;
+ unsigned long flags;
struct i915_wa *wa;
unsigned int i;
u32 *cs;
@@ -1002,13 +1005,36 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
if (IS_ERR(cs))
return PTR_ERR(cs);
+ fw = wal_get_fw_for_rmw(uncore, wal);
+
+ intel_gt_mcr_lock(wal->gt, &flags);
+ spin_lock(&uncore->lock);
+ intel_uncore_forcewake_get__locked(uncore, fw);
+
*cs++ = MI_LOAD_REGISTER_IMM(wal->count);
for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
+ u32 val;
+
+ /* Skip reading the register if it's not really needed */
+ if (wa->masked_reg || (wa->clr | wa->set) == U32_MAX) {
+ val = wa->set;
+ } else {
+ val = wa->is_mcr ?
+ intel_gt_mcr_read_any_fw(wal->gt, wa->mcr_reg) :
+ intel_uncore_read_fw(uncore, wa->reg);
+ val &= ~wa->clr;
+ val |= wa->set;
+ }
+
*cs++ = i915_mmio_reg_offset(wa->reg);
- *cs++ = wa->set;
+ *cs++ = val;
}
*cs++ = MI_NOOP;
+ intel_uncore_forcewake_put__locked(uncore, fw);
+ spin_unlock(&uncore->lock);
+ intel_gt_mcr_unlock(wal->gt, flags);
+
intel_ring_advance(rq, cs);
ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
--
2.40.1
[Intel-gfx] [PATCH v3 7/7] drm/i915/gt: Also check set bits in clr_set()
When checking if the workarounds were applied succesfully, the read-back
mask should also contain the bits being set: it's possible that in a
call to wa_write_clr_set(), the cleared bits are not a superset of the
set bits.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a6f3f160ebe2..b177c588698b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -241,13 +241,13 @@ static void wa_mcr_add(struct i915_wa_list *wal,
i915_mcr_reg_t reg,
static void
wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
{
- wa_add(wal, reg, clear, set, clear, false);
+ wa_add(wal, reg, clear, set, clear | set, false);
}
static void
wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear,
u32 set)
{
- wa_mcr_add(wal, reg, clear, set, clear, false);
+ wa_mcr_add(wal, reg, clear, set, clear | set, false);
}
static void
--
2.40.1
[Intel-gfx] [PATCH v3 4/7] drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround
Now that non-masked registers are already read before programming the
context reads, the additional read became redudant, so remove it.
Signed-off-by: Lucas De Marchi
Reviewed-by: Kenneth Graunke
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 0a9c3be4817c..b07f84c3fa21 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -637,10 +637,7 @@ static void icl_ctx_workarounds_init(struct
intel_engine_cs *engine,
struct i915_wa_list *wal)
{
/* Wa_1406697149 (WaDisableBankHangMode:icl) */
- wa_write(wal,
-GEN8_L3CNTLREG,
-intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
-GEN8_ERRDETBCTRL);
+ wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL);
/* WaForceEnableNonCoherent:icl
* This is not the same workaround as in early Gen9 platforms, where
--
2.40.1
[Intel-gfx] [PATCH v3 0/7] Fix ctx workarounds for non-masked regs
v3 of https://patchwork.freedesktop.org/series/119766/ Changes from v2: - Do not rmw if (clr | set) covers all bits - Add patch to make sure the set bits are also checked on wa_*_clr_set() when clr is not a superset. Tested on DG2 with intel_reg reading 0xb158 with a busy render engine. Now it's not losing the upper bit anymore. Lucas De Marchi (7): drm/i915/gt: Move wal_get_fw_for_rmw() drm/i915/gt: Clear all bits from GEN12_FF_MODE2 drm/i915/gt: Fix context workarounds with non-masked regs drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround drm/i915/gt: Enable read back on XEHP_FF_MODE2 drm/i915/gt: Remove bogus comment on IVB_FBC_RT_BASE_UPPER drm/i915/gt: Also check set bits in clr_set() drivers/gpu/drm/i915/gt/intel_workarounds.c | 129 ++-- 1 file changed, 66 insertions(+), 63 deletions(-) -- 2.40.1
[Intel-gfx] [PATCH v3 6/7] drm/i915/gt: Remove bogus comment on IVB_FBC_RT_BASE_UPPER
The comment on the parameter being 0 to avoid the read back doesn't apply as this is not a call to wa_add(), but rather to wa_write_clr_set(). So, this register is actually checked and it's according to the Bspec that the register is RW, not RO. Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index e2025c363949..a6f3f160ebe2 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -666,7 +666,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, /* Wa_1604278689:icl,ehl */ wa_write(wal, IVB_FBC_RT_BASE, 0x & ~ILK_FBC_RT_VALID); wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, -0, /* write-only register; skip validation */ +0, 0x); /* Wa_1406306137:icl,ehl */ -- 2.40.1
[Intel-gfx] [PATCH v3 5/7] drm/i915/gt: Enable read back on XEHP_FF_MODE2
Contrary to GEN12_FF_MODE2, platforms using XEHP_FF_MODE2 are not affected by Wa_1608008084, hence read back can be enabled. Signed-off-by: Lucas De Marchi Reviewed-by: Kenneth Graunke --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index b07f84c3fa21..e2025c363949 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -683,11 +683,8 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP); wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); - wa_mcr_add(wal, - XEHP_FF_MODE2, - FF_MODE2_TDS_TIMER_MASK, - FF_MODE2_TDS_TIMER_128, - 0, false); + wa_mcr_write_clr_set(wal, XEHP_FF_MODE2, FF_MODE2_TDS_TIMER_MASK, +FF_MODE2_TDS_TIMER_128); } static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, -- 2.40.1
[Intel-gfx] [PATCH v3 2/7] drm/i915/gt: Clear all bits from GEN12_FF_MODE2
Right now context workarounds don't do a rmw and instead only write to
the register. Since 2 separate programmings to the same register are
coalesced into a single write, this is not problematic for
GEN12_FF_MODE2 since both TDS and GS timer are going to be written
together and the other remaining bits be zeroed.
However in order to fix other workarounds that may want to preserve the
unrelated bits in the same register, context workarounds need to
be changed to a rmw. To prepare for that, move the programming of
GEN12_FF_MODE2 to a single place so the value passed for "clear" can
be all the bits. Otherwise the second workaround would be dropped as
it'd be detected as overwriting a previously programmed workaround.
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 51 +++--
1 file changed, 17 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 8f8346df3c18..7d48bd57b6ef 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -693,40 +693,11 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs
*engine,
0, false);
}
-/*
- * These settings aren't actually workarounds, but general tuning settings that
- * need to be programmed on several platforms.
- */
-static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
-struct i915_wa_list *wal)
-{
- /*
-* Although some platforms refer to it as Wa_1604555607, we need to
-* program it even on those that don't explicitly list that
-* workaround.
-*
-* Note that the programming of this register is further modified
-* according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
-* Wa_1608008084 tells us the FF_MODE2 register will return the wrong
-* value when read. The default value for this register is zero for all
-* fields and there are no bit masks. So instead of doing a RMW we
-* should just write TDS timer value. For the same reason read
-* verification is ignored.
-*/
- wa_add(wal,
- GEN12_FF_MODE2,
- FF_MODE2_TDS_TIMER_MASK,
- FF_MODE2_TDS_TIMER_128,
- 0, false);
-}
-
static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- gen12_ctx_gt_tuning_init(engine, wal);
-
/*
* Wa_1409142259:tgl,dg1,adl-p
* Wa_1409347922:tgl,dg1,adl-p
@@ -748,15 +719,27 @@ static void gen12_ctx_workarounds_init(struct
intel_engine_cs *engine,
GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
/*
-* Wa_16011163337
+* Wa_16011163337 - GS_TIMER
+*
+* TDS_TIMER: Although some platforms refer to it as Wa_1604555607, we
+* need to program it even on those that don't explicitly list that
+* workaround.
+*
+* Note that the programming of GEN12_FF_MODE2 is further modified
+* according to the FF_MODE2 guidance given by Wa_1608008084.
+* Wa_1608008084 tells us the FF_MODE2 register will return the wrong
+* value when read from the CPU.
*
-* Like in gen12_ctx_gt_tuning_init(), read verification is ignored due
-* to Wa_1608008084.
+* The default value for this register is zero for all fields.
+* So instead of doing a RMW we should just write the desired values
+* for TDS and GS timers. Note that since the readback can't be trusted,
+* the clear mask is just set to ~0 to make sure other bits are not
+* inadvertently set. For the same reason read verification is ignored.
*/
wa_add(wal,
GEN12_FF_MODE2,
- FF_MODE2_GS_TIMER_MASK,
- FF_MODE2_GS_TIMER_224,
+ ~0,
+ FF_MODE2_TDS_TIMER_128 | FF_MODE2_GS_TIMER_224,
0, false);
if (!IS_DG1(i915)) {
--
2.40.1
[Intel-gfx] [PATCH v3 1/7] drm/i915/gt: Move wal_get_fw_for_rmw()
Move helper function to get all the forcewakes required by the wa list
to the top, so it can be re-used by other functions.
Signed-off-by: Lucas De Marchi
Reviewed-by: Kenneth Graunke
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 ++---
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 01807a7dd2c1..8f8346df3c18 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -123,6 +123,22 @@ static void wa_init_finish(struct i915_wa_list *wal)
wal->wa_count, wal->name, wal->engine_name);
}
+static enum forcewake_domains
+wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
+{
+ enum forcewake_domains fw = 0;
+ struct i915_wa *wa;
+ unsigned int i;
+
+ for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
+ fw |= intel_uncore_forcewake_for_reg(uncore,
+wa->reg,
+FW_REG_READ |
+FW_REG_WRITE);
+
+ return fw;
+}
+
static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
{
unsigned int addr = i915_mmio_reg_offset(wa->reg);
@@ -1859,22 +1875,6 @@ void intel_gt_init_workarounds(struct intel_gt *gt)
wa_init_finish(wal);
}
-static enum forcewake_domains
-wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
-{
- enum forcewake_domains fw = 0;
- struct i915_wa *wa;
- unsigned int i;
-
- for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
- fw |= intel_uncore_forcewake_for_reg(uncore,
-wa->reg,
-FW_REG_READ |
-FW_REG_WRITE);
-
- return fw;
-}
-
static bool
wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur,
const char *name, const char *from)
--
2.40.1
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/i915_pm_rps: Exercise sysfs thresholds
On 5/23/2023 3:51 AM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Exercise a bunch of up and down rps thresholds to verify hardware
is happy with them all.
To limit the overall runtime relies on probability and number of runs
to approach complete coverage.
Signed-off-by: Tvrtko Ursulin
Cc: Rodrigo Vivi
---
tests/i915/i915_pm_rps.c | 232 +++
1 file changed, 232 insertions(+)
diff --git a/tests/i915/i915_pm_rps.c b/tests/i915/i915_pm_rps.c
index 050d68a16559..acff59207311 100644
--- a/tests/i915/i915_pm_rps.c
+++ b/tests/i915/i915_pm_rps.c
@@ -39,8 +39,10 @@
#include "i915/gem.h"
#include "i915/gem_create.h"
#include "igt.h"
+#include "igt_aux.h"
#include "igt_dummyload.h"
#include "igt_perf.h"
+#include "igt_rand.h"
#include "igt_sysfs.h"
/**
* TEST: i915 pm rps
@@ -914,6 +916,200 @@ static void pm_rps_exit_handler(int sig)
close(drm_fd);
}
+static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e)
+{
+ struct igt_spin_factory opts = {
+ .ahnd = ahnd,
+ .ctx = ctx,
+ .engine = e->flags,
+ };
+
+ if (gem_class_can_store_dword(fd, e->class))
+ opts.flags |= IGT_SPIN_POLL_RUN;
+
+ return __igt_spin_factory(fd, &opts);
+}
+
+static unsigned long __spin_wait(int fd, igt_spin_t *spin)
+{
+ struct timespec start = { };
+
+ igt_nsec_elapsed(&start);
+
+ if (igt_spin_has_poll(spin)) {
+ unsigned long timeout = 0;
+
+ while (!igt_spin_has_started(spin)) {
+ unsigned long t = igt_nsec_elapsed(&start);
+
+ igt_assert(gem_bo_busy(fd, spin->handle));
+ if ((t - timeout) > 250e6) {
+ timeout = t;
+ igt_warn("Spinner not running after %.2fms\n",
+(double)t / 1e6);
+ igt_assert(t < 2e9);
+ }
+ }
+ } else {
+ igt_debug("__spin_wait - usleep mode\n");
+ usleep(500e3); /* Better than nothing! */
+ }
+
+ igt_assert(gem_bo_busy(fd, spin->handle));
+ return igt_nsec_elapsed(&start);
+}
+
+static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e)
+{
+ igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
+
+ __spin_wait(fd, spin);
+
+ return spin;
+}
All the above spin functions have been duplicated across 2-3 tests, time
to create a lib for them?
+
+static struct i915_engine_class_instance
+find_dword_engine(int i915, const unsigned int gt)
+{
+ struct i915_engine_class_instance *engines, ci = { -1, -1 };
+ unsigned int i, count;
+
+ engines = gem_list_engines(i915, 1u << gt, ~0u, &count);
+ igt_assert(engines);
+
+ for (i = 0; i < count; i++) {
+ if (!gem_class_can_store_dword(i915, engines[i].engine_class))
+ continue;
+
+ ci = engines[i];
+ break;
+ }
+
+ free(engines);
+
+ return ci;
+}
+
+static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
+ const intel_ctx_t **ctx)
+{
+ struct i915_engine_class_instance ci = { -1, -1 };
+ struct intel_execution_engine2 e = { };
+
+ ci = find_dword_engine(i915, gt);
+
+ igt_require(ci.engine_class != (uint16_t)I915_ENGINE_CLASS_INVALID);
+
+ if (gem_has_contexts(i915)) {
+ e.class = ci.engine_class;
+ e.instance = ci.engine_instance;
+ e.flags = 0;
+ *ctx = intel_ctx_create_for_engine(i915, e.class, e.instance);
+ } else {
+ igt_require(gt == 0); /* Impossible anyway. */
+ e.class = gem_execbuf_flags_to_engine_class(I915_EXEC_DEFAULT);
+ e.instance = 0;
+ e.flags = I915_EXEC_DEFAULT;
+ *ctx = intel_ctx_0(i915);
+ }
+
+ igt_debug("Using engine %u:%u\n", e.class, e.instance);
+
+ return __spin_sync(i915, ahnd, *ctx, &e);
+}
+
+#define TEST_IDLE 0x1
+#define TEST_PARK 0x2
+static void test_thresholds(int i915, unsigned int gt, unsigned int flags)
+{
+ uint64_t ahnd = get_reloc_ahnd(i915, 0);
+ const unsigned int points = 10;
+ unsigned int def_up, def_down;
+ igt_spin_t *spin = NULL;
+ const intel_ctx_t *ctx;
+ unsigned int *ta, *tb;
+ unsigned int i;
+ int sysfs;
+
+ sysfs = igt_sysfs_gt_open(i915, gt);
+ igt_require(sysfs >= 0);
+
+ /* Feature test */
+ def_up = igt_sysfs_get_u32(sysfs, "rps_up_threshold_pct");
+ def_down = igt_sysfs_get_u32(sysfs, "rps_down_threshold_pct");
+ igt_require(def_up
Re: [Intel-gfx] [PATCH v7 6/8] PCI/VGA: Introduce is_boot_device function callback to vga_client_register
On Fri, 30 Jun 2023, Bjorn Helgaas wrote: > On Fri, Jun 30, 2023 at 10:14:11AM +0800, suijingfeng wrote: >> On 2023/6/30 01:44, Limonciello, Mario wrote: >> > > On 2023/6/29 23:54, Bjorn Helgaas wrote: >> > > > On Thu, Jun 22, 2023 at 01:08:15PM +0800, Sui Jingfeng wrote: > >> > > > 4) Right now we're in the middle of the v6.5 merge window, so new >> > > > content, e.g., this series, is too late for v6.5. Most >> > > > maintainers, including me, wait to merge new content until the >> > > > merge window closes and a new -rc1 is tagged. This merge window >> > > > should close on July 9, and people will start merging content for >> > > > v6.6, typically based on v6.5-rc1. >> > > >> > > Would you will merge all of the patches in this series (e.g. including >> > > the patch for drm/amdgpu(7/8) and drm/radeon(8/8)) ? >> > > >> > > Or just part of them? > > The bulk of this series is drivers/pci changes, so typically I would > merge all the patches after getting Acked-by tags from the other > subsystems (DRM and VFIO). For the (negligible) i915 parts, Acked-by: Jani Nikula >> Is it possible to merge the PCI/VGA part as fast as possible, >> especially the PATCH-0006 PCI/VGA: Introduce is_boot_device function >> callback to vga_client_register > > We're in the middle of the v6.5 merge window, so it's too late to add > things to v6.5-rc1. The most likely path for new material like this > would be to queue it for v6.6, which means I would merge it after > v6.5-rc1 is tagged (that tag will probably happen on July 9). Perhaps the part that causes confusion here is that the drm-misc-next and drm-intel-next branches, for example, are always open for new patches; it's just that there's a cutoff at around rc5/rc6 after which they start targeting the next+1 release. We basically hide the merge window from a lot of drm developers. > It would then be in -next until the v6.6 merge window opens (likely in > September), when it would be merged into Linus' tree. > > If the series fixes a regression or other major defect, it's > *possible* to merge things earlier, so they appear in v6.5. But this > series doesn't seem to fall in that category, so I think v6.6 is a > more realistic target. > > Merging for v6.6 would include both the PCI parts and the DRM parts at > the same time, so hopefully that addresses your dependency concerns. I guess the main question is whether Sui Jingfeng has follow-up work planned in drm that depends on these being merged. This would set that back by a full release. (But it happens.) BR, Jani. > > I suggest that you wait until v6.5-rc1, rebase your patches so they > apply cleanly on that tag, collect all the Reviewed-by and Acked-by > tags, include them in your commit logs, and then repost them. > > Bjorn -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Do not use stolen on MTL
== Series Details == Series: series starting with [1/2] drm/i915/gt: Do not use stolen on MTL URL : https://patchwork.freedesktop.org/series/120086/ State : success == Summary == CI Bug Log - changes from CI_DRM_13340 -> Patchwork_120086v1 Summary --- **WARNING** Minor unknown changes coming with Patchwork_120086v1 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_120086v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/index.html Participating hosts (42 -> 40) -- Missing(2): fi-kbl-soraka fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_120086v1: ### IGT changes ### Warnings * igt@kms_setmode@basic-clone-single-crtc: - bat-mtlp-6: [SKIP][1] ([i915#4579]) -> [SKIP][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-6/igt@kms_setm...@basic-clone-single-crtc.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/bat-mtlp-6/igt@kms_setm...@basic-clone-single-crtc.html - bat-mtlp-8: [SKIP][3] ([i915#4579]) -> [SKIP][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-8/igt@kms_setm...@basic-clone-single-crtc.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/bat-mtlp-8/igt@kms_setm...@basic-clone-single-crtc.html Known issues Here are the changes found in Patchwork_120086v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@parallel-random-engines: - bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/bat-mtlp-8/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_pm_rps@basic-api: - bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#6621]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-8: NOTRUN -> [DMESG-FAIL][7] ([i915#7059]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [PASS][8] -> [DMESG-WARN][9] ([i915#7699]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-dg2-11/igt@i915_selftest@l...@migrate.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@requests: - bat-rpls-1: [PASS][10] -> [ABORT][11] ([i915#4983] / [i915#7911] / [i915#7920]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-rpls-1/igt@i915_selftest@l...@requests.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/bat-rpls-1/igt@i915_selftest@l...@requests.html - bat-mtlp-6: [PASS][12] -> [DMESG-FAIL][13] ([i915#8497]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-6/igt@i915_selftest@l...@requests.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/bat-mtlp-6/igt@i915_selftest@l...@requests.html * igt@i915_suspend@basic-s3-without-i915: - bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#6645]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/bat-mtlp-8/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-mtlp-8: NOTRUN -> [SKIP][15] ([i915#7828]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/bat-mtlp-8/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@prime_vgem@basic-fence-read: - bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#3708]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/bat-mtlp-8/igt@prime_v...@basic-fence-read.html * igt@prime_vgem@basic-gtt: - bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#3708] / [i915#4077]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/bat-mtlp-8/igt@prime_v...@basic-gtt.html Possible fixes * igt@i915_pm_rpm@basic-pci-d3-state: - bat-mtlp-8: [ABORT][18] ([i915#7077] / [i915#7977]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-8/igt@i915_pm_...@basic-pci-d3-state.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120086v1/bat-mtlp-8/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-6: [DMESG-FAIL][20] ([i915#7059]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-t
Re: [Intel-gfx] [PATCH v7 6/8] PCI/VGA: Introduce is_boot_device function callback to vga_client_register
On Fri, Jun 30, 2023 at 10:14:11AM +0800, suijingfeng wrote: > On 2023/6/30 01:44, Limonciello, Mario wrote: > > > On 2023/6/29 23:54, Bjorn Helgaas wrote: > > > > On Thu, Jun 22, 2023 at 01:08:15PM +0800, Sui Jingfeng wrote: > > > > 4) Right now we're in the middle of the v6.5 merge window, so new > > > > content, e.g., this series, is too late for v6.5. Most > > > > maintainers, including me, wait to merge new content until the > > > > merge window closes and a new -rc1 is tagged. This merge window > > > > should close on July 9, and people will start merging content for > > > > v6.6, typically based on v6.5-rc1. > > > > > > Would you will merge all of the patches in this series (e.g. including > > > the patch for drm/amdgpu(7/8) and drm/radeon(8/8)) ? > > > > > > Or just part of them? The bulk of this series is drivers/pci changes, so typically I would merge all the patches after getting Acked-by tags from the other subsystems (DRM and VFIO). > Is it possible to merge the PCI/VGA part as fast as possible, > especially the PATCH-0006 PCI/VGA: Introduce is_boot_device function > callback to vga_client_register We're in the middle of the v6.5 merge window, so it's too late to add things to v6.5-rc1. The most likely path for new material like this would be to queue it for v6.6, which means I would merge it after v6.5-rc1 is tagged (that tag will probably happen on July 9). It would then be in -next until the v6.6 merge window opens (likely in September), when it would be merged into Linus' tree. If the series fixes a regression or other major defect, it's *possible* to merge things earlier, so they appear in v6.5. But this series doesn't seem to fall in that category, so I think v6.6 is a more realistic target. Merging for v6.6 would include both the PCI parts and the DRM parts at the same time, so hopefully that addresses your dependency concerns. I suggest that you wait until v6.5-rc1, rebase your patches so they apply cleanly on that tag, collect all the Reviewed-by and Acked-by tags, include them in your commit logs, and then repost them. Bjorn
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/gt: Do not use stolen on MTL
== Series Details == Series: series starting with [1/2] drm/i915/gt: Do not use stolen on MTL URL : https://patchwork.freedesktop.org/series/120086/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +drivers/gpu/drm/i915/gt/intel_gt.h:112:16: warning: trying to copy expression type 31 +./drivers/gpu/drm/i915/intel_uncore.h:346:1: warning: trying to copy expression type 31 +./drivers/gpu/drm/i915/intel_uncore.h:351:1: warning: trying to copy expression type 31 +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non
Re: [Intel-gfx] [PATCH] drm/i915: Don't preserve dpll_hw_state for slave crtc in Bigjoiner
On Wed, Jun 28, 2023 at 05:10:17PM +0300, Stanislav Lisovskiy wrote:
> If we are using Bigjoiner dpll_hw_state is supposed to be exactly
> same as for master crtc, so no need to save it's state for slave crtc.
Yeah, and the master has recalculated this already. I guess this
used to make some sense in the times when we did the dpll
calculations much later.
So probably deserves a
Fixes: 0ff0e219d9b8 ("drm/i915: Compute clocks earlier")
Anyways,
Reviewed-by: Ville Syrjälä
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 43d6ba980780..c3e93bdde29d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4568,7 +4568,6 @@ copy_bigjoiner_crtc_state_modeset(struct
> intel_atomic_state *state,
> saved_state->uapi = slave_crtc_state->uapi;
> saved_state->scaler_state = slave_crtc_state->scaler_state;
> saved_state->shared_dpll = slave_crtc_state->shared_dpll;
> - saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state;
Seems like we should also remove it from the
intel_crtc_prepare_cleared_state() but that one clearly needs
much more thought due to the port_dpll[] stuff...
> saved_state->crc_enabled = slave_crtc_state->crc_enabled;
>
> intel_crtc_free_hw_state(slave_crtc_state);
> --
> 2.37.3
--
Ville Syrjälä
Intel
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Init DDI ports in VBT order (rev5)
== Series Details == Series: drm/i915: Init DDI ports in VBT order (rev5) URL : https://patchwork.freedesktop.org/series/114200/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13340 -> Patchwork_114200v5 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_114200v5 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_114200v5, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114200v5/index.html Participating hosts (42 -> 40) -- Missing(2): fi-snb-2520m fi-pnv-d510 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_114200v5: ### IGT changes ### Possible regressions * igt@gem_exec_suspend@basic-s0@smem: - fi-cfl-8700k: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/fi-cfl-8700k/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114200v5/fi-cfl-8700k/igt@gem_exec_suspend@basic...@smem.html Warnings * igt@kms_psr@cursor_plane_move: - bat-rplp-1: [ABORT][3] ([i915#8434] / [i915#8668]) -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-rplp-1/igt@kms_psr@cursor_plane_move.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114200v5/bat-rplp-1/igt@kms_psr@cursor_plane_move.html * igt@kms_setmode@basic-clone-single-crtc: - bat-mtlp-6: [SKIP][5] ([i915#4579]) -> [SKIP][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-6/igt@kms_setm...@basic-clone-single-crtc.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114200v5/bat-mtlp-6/igt@kms_setm...@basic-clone-single-crtc.html - bat-mtlp-8: [SKIP][7] ([i915#4579]) -> [SKIP][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-8/igt@kms_setm...@basic-clone-single-crtc.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114200v5/bat-mtlp-8/igt@kms_setm...@basic-clone-single-crtc.html Known issues Here are the changes found in Patchwork_114200v5 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@parallel-random-engines: - bat-mtlp-8: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114200v5/bat-mtlp-8/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_pm_rps@basic-api: - bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#6621]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114200v5/bat-mtlp-8/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-8: NOTRUN -> [DMESG-FAIL][11] ([i915#7059]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114200v5/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@requests: - bat-mtlp-8: NOTRUN -> [ABORT][12] ([i915#7982]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114200v5/bat-mtlp-8/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@reset: - bat-rpls-1: [PASS][13] -> [ABORT][14] ([i915#4983] / [i915#7461] / [i915#8347] / [i915#8384]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-rpls-1/igt@i915_selftest@l...@reset.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114200v5/bat-rpls-1/igt@i915_selftest@l...@reset.html * igt@prime_vgem@basic-fence-read: - bat-mtlp-8: NOTRUN -> [SKIP][15] ([i915#3708]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114200v5/bat-mtlp-8/igt@prime_v...@basic-fence-read.html * igt@prime_vgem@basic-gtt: - bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#3708] / [i915#4077]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114200v5/bat-mtlp-8/igt@prime_v...@basic-gtt.html Possible fixes * igt@i915_pm_rpm@basic-pci-d3-state: - bat-mtlp-8: [ABORT][17] ([i915#7077] / [i915#7977]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-8/igt@i915_pm_...@basic-pci-d3-state.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114200v5/bat-mtlp-8/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-6: [DMESG-FAIL][19] ([i915#7059]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114200v5/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html * igt@i
[Intel-gfx] [PATCH 1/2] drm/i915/gt: Do not use stolen on MTL
Use smem on MTL due to a HW bug in MTL that prevents reading from stolen memory using LMEM BAR. Cc: Oak Zeng Cc: Jani Nikula Cc: Joonas Lahtinen Cc: Andi Shyti Cc: Andrzej Hajda Signed-off-by: Nirmoy Das --- drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 33a61046ba58..9f64d61dd5fc 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -466,7 +466,7 @@ static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size) obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE | I915_BO_ALLOC_GPU_ONLY); - if (IS_ERR(obj)) + if (IS_ERR(obj) && !IS_METEORLAKE(i915)) /* Wa_22018444074 */ obj = i915_gem_object_create_stolen(i915, size); if (IS_ERR(obj)) obj = i915_gem_object_create_internal(i915, size); -- 2.39.0
[Intel-gfx] [PATCH 2/2] drm/i915/display: Do not use stolen on MTL
Use smem on MTL due to a HW bug in MTL that prevents
reading from stolen memory using LMEM BAR.
Cc: Oak Zeng
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Andi Shyti
Cc: Andrzej Hajda
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 2 ++
drivers/gpu/drm/i915/display/intel_overlay.c | 7 ---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 1cc0ddc6a310..10e38d60f9ef 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -182,6 +182,8 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
obj = i915_gem_object_create_lmem(dev_priv, size,
I915_BO_ALLOC_CONTIGUOUS |
I915_BO_ALLOC_USER);
+ } else if (IS_METEORLAKE(dev_priv)) { /* Wa_22018444074 */
+ obj = i915_gem_object_create_shmem(dev_priv, size);
} else {
/*
* If the FB is too big, just don't use it since fbdev is not
very
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
b/drivers/gpu/drm/i915/display/intel_overlay.c
index d6fe2bbabe55..05ae446c8a56 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -1348,12 +1348,13 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev,
void *data,
static int get_registers(struct intel_overlay *overlay, bool use_phys)
{
struct drm_i915_private *i915 = overlay->i915;
- struct drm_i915_gem_object *obj;
+ struct drm_i915_gem_object *obj = NULL;
struct i915_vma *vma;
int err;
- obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
- if (IS_ERR(obj))
+ if (!IS_METEORLAKE(i915)) /* Wa_22018444074 */
+ obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
+ if (IS_ERR_OR_NULL(obj))
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
if (IS_ERR(obj))
return PTR_ERR(obj);
--
2.39.0
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Init DDI ports in VBT order (rev5)
== Series Details == Series: drm/i915: Init DDI ports in VBT order (rev5) URL : https://patchwork.freedesktop.org/series/114200/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Init DDI ports in VBT order (rev5)
== Series Details ==
Series: drm/i915: Init DDI ports in VBT order (rev5)
URL : https://patchwork.freedesktop.org/series/114200/
State : warning
== Summary ==
Error: dim checkpatch failed
458507c5d81b drm/i915: Initialize dig_port->aux_ch to NONE to be sure
c63ca1d72c9b drm/i915: Only populate aux_ch if really needed
69486e70e413 drm/i915: Remove DDC pin sanitation
20a36bbd9fad drm/i915: Remove AUX CH sanitation
0ac47bfae38a drm/i915/bios: Extract intel_bios_encoder_port()
e469fc890c76 drm/i915: Try to initialize DDI/ICL+ DSI ports for every VBT child
device
-:181: ERROR:OPEN_BRACE: that open brace { should be on the previous line
#181: FILE: drivers/gpu/drm/i915/display/intel_bios.c:3600:
+void intel_bios_for_each_encoder(struct drm_i915_private *i915,
+void (*func)(struct drm_i915_private *i915,
+ const struct
intel_bios_encoder_data *devdata))
+{
total: 1 errors, 0 warnings, 0 checks, 299 lines checked
Re: [Intel-gfx] [PATCH v3 6/6] drm/i915: Try to initialize DDI/ICL+ DSI ports for every VBT child device
On Fri, 30 Jun 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Try to deal with duplicate child devices for the same DDI port
> by attempting to initialize them in VBT defined order The first
> on to succeed for a specific DDI port will be the one we use.
>
> We'll also get rid of i915->display.vbt.ports[] here as any conflicts
> will now be handled at encoder registration time rather than during
> VBT parsing. Note that intel_bios_encoder_data_lookup() still remaims
> for pre-DDI DP/HDMI ports as those don't (at least yet) use VBT
> driven initialization.
>
> TODO: DSI dual link handling is sketchy at best
Despite the sketchy bits this seems like a step forward.
Reviewed-by: Jani Nikula
>
> v2: Leave intel_bios_encoder_port() to the encoder callback (Jani)
>
> Cc: Jani Nikula
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c| 9 ++-
> drivers/gpu/drm/i915/display/icl_dsi.h| 4 +-
> drivers/gpu/drm/i915/display/intel_bios.c | 47 ---
> drivers/gpu/drm/i915/display/intel_bios.h | 6 ++
> drivers/gpu/drm/i915/display/intel_ddi.c | 57 +++
> drivers/gpu/drm/i915/display/intel_ddi.h | 4 +-
> drivers/gpu/drm/i915/display/intel_display.c | 11 +---
> .../gpu/drm/i915/display/intel_display_core.h | 2 -
> 8 files changed, 93 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 59a2a289d9be..f7ebc146f96d 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1933,7 +1933,8 @@ static void icl_dsi_add_properties(struct
> intel_connector *connector)
> fixed_mode->vdisplay);
> }
>
> -void icl_dsi_init(struct drm_i915_private *dev_priv)
> +void icl_dsi_init(struct drm_i915_private *dev_priv,
> + const struct intel_bios_encoder_data *devdata)
> {
> struct intel_dsi *intel_dsi;
> struct intel_encoder *encoder;
> @@ -1941,7 +1942,8 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> struct drm_connector *connector;
> enum port port;
>
> - if (!intel_bios_is_dsi_present(dev_priv, &port))
> + port = intel_bios_encoder_port(devdata);
> + if (port == PORT_NONE)
> return;
>
> intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
> @@ -1958,6 +1960,8 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> intel_dsi->attached_connector = intel_connector;
> connector = &intel_connector->base;
>
> + encoder->devdata = devdata;
> +
> /* register DSI encoder with DRM subsystem */
> drm_encoder_init(&dev_priv->drm, &encoder->base,
> &gen11_dsi_encoder_funcs,
>DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
> @@ -1995,7 +1999,6 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
>
> intel_dsi->panel_power_off_time = ktime_get_boottime();
>
> - encoder->devdata = intel_bios_encoder_data_lookup(dev_priv, port);
> intel_bios_init_panel_late(dev_priv, &intel_connector->panel,
> encoder->devdata, NULL);
>
> mutex_lock(&dev_priv->drm.mode_config.mutex);
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.h
> b/drivers/gpu/drm/i915/display/icl_dsi.h
> index b4861b56b5b2..43fa7d72eeb1 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.h
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.h
> @@ -7,9 +7,11 @@
> #define __ICL_DSI_H__
>
> struct drm_i915_private;
> +struct intel_bios_encoder_data;
> struct intel_crtc_state;
>
> -void icl_dsi_init(struct drm_i915_private *i915);
> +void icl_dsi_init(struct drm_i915_private *dev_priv,
> + const struct intel_bios_encoder_data *devdata);
> void icl_dsi_frame_update(struct intel_crtc_state *crtc_state);
>
> #endif /* __ICL_DSI_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index c96bbbe4448e..858c959f7bab 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2374,7 +2374,7 @@ dsi_dvo_port_to_port(struct drm_i915_private *i915, u8
> dvo_port)
> }
> }
>
> -static enum port intel_bios_encoder_port(const struct
> intel_bios_encoder_data *devdata)
> +enum port intel_bios_encoder_port(const struct intel_bios_encoder_data
> *devdata)
> {
> struct drm_i915_private *i915 = devdata->i915;
> const struct child_device_config *child = &devdata->child;
> @@ -2497,7 +2497,7 @@ intel_bios_encoder_supports_edp(const struct
> intel_bios_encoder_data *devdata)
> devdata->child.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR;
> }
>
> -static bool
> +bool
> intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data
> *devdata)
> {
> return devdata->child.device_type & DEVICE_TYPE_MIPI_OUTPUT;
> @@ -2556,13 +2556,17 @@ static bool is_port_valid(struct
Re: [Intel-gfx] [PATCH v3 3/6] drm/i915: Remove DDC pin sanitation
On Fri, 30 Jun 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Stop with the VBT DDC pin sanitation, and instead just check
> that the appropriate DDC pin is still available when initializing
> a HDMI connector.
>
> The reason being that we want to start initializing ports in
> VBT order to deal with VBTs that declare child devices with
> seemingly conflicting ports. As the encoder initialization can
> fail for other reasons (at least for eDP+AUX) we can't know
> upfront which way the conflicts should be resolved.
>
> Note that the old way of sanitizing gave priority to the last
> port declared in the VBT, but now we sort of do the opposite by
> favoring the first encoder to successfully initialize. So far
> we're not aware of HDMI/DDC use cases where this would matter
> but for AUX CH (will be subject to a similar change) there are
> known cases where it matters.
>
> Also note that the old code fell back to the platform default DDC
> pin if the VBT pin was populated but invalid. That doesn't seem like
> such a great idea because the VBT might have later declared another
> port using that platform default pin, and so we might just be
> creating more DDC pin conflicts here. So lets not second guess the
> VBT and simply reject the entire HDMI encoder if the VBT DDC pin is
> invalid.
>
> v2: Pimp the commit message (Jani)
>
> Cc: Jani Nikula
> Signed-off-by: Ville Syrjälä
Fingers crossed!
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 69 --
> drivers/gpu/drm/i915/display/intel_hdmi.c | 72 +++
> 2 files changed, 59 insertions(+), 82 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 4b9bf76e137d..6aeebd3c97f9 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2230,72 +2230,6 @@ static u8 map_ddc_pin(struct drm_i915_private *i915,
> u8 vbt_pin)
> return 0;
> }
>
> -static enum port get_port_by_ddc_pin(struct drm_i915_private *i915, u8
> ddc_pin)
> -{
> - enum port port;
> -
> - if (!ddc_pin)
> - return PORT_NONE;
> -
> - for_each_port(port) {
> - const struct intel_bios_encoder_data *devdata =
> - i915->display.vbt.ports[port];
> -
> - if (devdata && ddc_pin == devdata->child.ddc_pin)
> - return port;
> - }
> -
> - return PORT_NONE;
> -}
> -
> -static void sanitize_ddc_pin(struct intel_bios_encoder_data *devdata,
> - enum port port)
> -{
> - struct drm_i915_private *i915 = devdata->i915;
> - struct child_device_config *child;
> - u8 mapped_ddc_pin;
> - enum port p;
> -
> - if (!devdata->child.ddc_pin)
> - return;
> -
> - mapped_ddc_pin = map_ddc_pin(i915, devdata->child.ddc_pin);
> - if (!intel_gmbus_is_valid_pin(i915, mapped_ddc_pin)) {
> - drm_dbg_kms(&i915->drm,
> - "Port %c has invalid DDC pin %d, "
> - "sticking to defaults\n",
> - port_name(port), mapped_ddc_pin);
> - devdata->child.ddc_pin = 0;
> - return;
> - }
> -
> - p = get_port_by_ddc_pin(i915, devdata->child.ddc_pin);
> - if (p == PORT_NONE)
> - return;
> -
> - drm_dbg_kms(&i915->drm,
> - "port %c trying to use the same DDC pin (0x%x) as port %c, "
> - "disabling port %c DVI/HDMI support\n",
> - port_name(port), mapped_ddc_pin,
> - port_name(p), port_name(p));
> -
> - /*
> - * If we have multiple ports supposedly sharing the pin, then dvi/hdmi
> - * couldn't exist on the shared port. Otherwise they share the same ddc
> - * pin and system couldn't communicate with them separately.
> - *
> - * Give inverse child device order the priority, last one wins. Yes,
> - * there are real machines (eg. Asrock B250M-HDV) where VBT has both
> - * port A and port E with the same AUX ch and we must pick port E :(
> - */
> - child = &i915->display.vbt.ports[p]->child;
> -
> - child->device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING;
> - child->device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT;
> -
> - child->ddc_pin = 0;
> -}
> -
> static enum port get_port_by_aux_ch(struct drm_i915_private *i915, u8 aux_ch)
> {
> enum port port;
> @@ -2754,9 +2688,6 @@ static void parse_ddi_port(struct
> intel_bios_encoder_data *devdata)
>
> sanitize_device_type(devdata, port);
>
> - if (intel_bios_encoder_supports_dvi(devdata))
> - sanitize_ddc_pin(devdata, port);
> -
> if (intel_bios_encoder_supports_dp(devdata))
> sanitize_aux_ch(devdata, port);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 7ac5e6c5e00d..8d1c8abfcffa 1006
Re: [Intel-gfx] [PATCH v3 5/6] drm/i915/bios: Extract intel_bios_encoder_port()
On Fri, 30 Jun 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We'll have a few places where we need to do the full (incl. ICL+ DSI)
> DVO port->port conversion, so extract the code for that into a helper.
>
> Suggested-by: Jani Nikula
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 18 ++
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index ae83788177ce..c96bbbe4448e 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2374,6 +2374,19 @@ dsi_dvo_port_to_port(struct drm_i915_private *i915, u8
> dvo_port)
> }
> }
>
> +static enum port intel_bios_encoder_port(const struct
> intel_bios_encoder_data *devdata)
> +{
> + struct drm_i915_private *i915 = devdata->i915;
> + const struct child_device_config *child = &devdata->child;
> + enum port port;
> +
> + port = dvo_port_to_port(i915, child->dvo_port);
> + if (port == PORT_NONE && DISPLAY_VER(i915) >= 11)
> + port = dsi_dvo_port_to_port(i915, child->dvo_port);
> +
> + return port;
> +}
> +
> static int parse_bdb_230_dp_max_link_rate(const int vbt_max_link_rate)
> {
> switch (vbt_max_link_rate) {
> @@ -2613,12 +2626,9 @@ static void print_ddi_port(const struct
> intel_bios_encoder_data *devdata,
> static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
> {
> struct drm_i915_private *i915 = devdata->i915;
> - const struct child_device_config *child = &devdata->child;
> enum port port;
>
> - port = dvo_port_to_port(i915, child->dvo_port);
> - if (port == PORT_NONE && DISPLAY_VER(i915) >= 11)
> - port = dsi_dvo_port_to_port(i915, child->dvo_port);
> + port = intel_bios_encoder_port(devdata);
> if (port == PORT_NONE)
> return;
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [linux-next:master] BUILD REGRESSION 6352a698ca5bf26a9199202666b16cf741f579f6
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 6352a698ca5bf26a9199202666b16cf741f579f6 Add linux-next specific
files for 20230630
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/20230613.hher4zoo-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202306260401.qzlyqpv2-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202306291857.nyjjywqk-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202306301709.lvrxzycj-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202306301756.x8dgyynl-...@intel.com
Error/Warning: (recently discovered and may have been fixed)
arch/parisc/kernel/pdt.c:66:6: warning: no previous prototype for
'arch_report_meminfo' [-Wmissing-prototypes]
drivers/bluetooth/btmtk.c:386:32: error: no member named 'dump' in 'struct
hci_dev'
drivers/bluetooth/btmtk.c:386:44: error: 'struct hci_dev' has no member named
'dump'
drivers/char/mem.c:164:25: error: implicit declaration of function
'unxlate_dev_mem_ptr'; did you mean 'xlate_dev_mem_ptr'?
[-Werror=implicit-function-declaration]
drivers/gpu/drm/i915/soc/intel_gmch.c:41:13: error: variable 'mchbar_addr' set
but not used [-Werror=unused-but-set-variable]
drivers/mfd/max77541.c:176:18: warning: cast to smaller integer type 'enum
max7754x_ids' from 'const void *' [-Wvoid-pointer-to-enum-cast]
lib/kunit/executor_test.c:138:4: warning: cast from 'void (*)(const void *)' to
'kunit_action_t *' (aka 'void (*)(void *)') converts to incompatible function
type [-Wcast-function-type-strict]
lib/kunit/test.c:775:38: warning: cast from 'void (*)(const void *)' to
'kunit_action_t *' (aka 'void (*)(void *)') converts to incompatible function
type [-Wcast-function-type-strict]
Unverified Error/Warning (likely false positive, please contact us if
interested):
drivers/usb/cdns3/cdns3-starfive.c:23: warning: expecting prototype for
cdns3(). Prototype was for USB_STRAP_HOST() instead
fs/btrfs/volumes.c:6407 btrfs_map_block() error: we previously assumed
'mirror_num_ret' could be null (see line 6244)
{standard input}: Error: local label `"2" (instance number 9 of a fb label)' is
not defined
{standard input}:1097: Error: pcrel too far
Error/Warning ids grouped by kconfigs:
gcc_recent_errors
|-- i386-buildonly-randconfig-r005-20230629
| `--
drivers-gpu-drm-i915-soc-intel_gmch.c:error:variable-mchbar_addr-set-but-not-used
|-- i386-randconfig-i006-20230629
| `-- drivers-bluetooth-btmtk.c:error:struct-hci_dev-has-no-member-named-dump
|-- parisc-allyesconfig
| `--
arch-parisc-kernel-pdt.c:warning:no-previous-prototype-for-arch_report_meminfo
|-- parisc-defconfig
| `--
arch-parisc-kernel-pdt.c:warning:no-previous-prototype-for-arch_report_meminfo
|-- parisc64-defconfig
| `--
arch-parisc-kernel-pdt.c:warning:no-previous-prototype-for-arch_report_meminfo
|-- riscv-allmodconfig
| `--
drivers-usb-cdns3-cdns3-starfive.c:warning:expecting-prototype-for-cdns3().-Prototype-was-for-USB_STRAP_HOST()-instead
|-- riscv-allyesconfig
| `--
drivers-usb-cdns3-cdns3-starfive.c:warning:expecting-prototype-for-cdns3().-Prototype-was-for-USB_STRAP_HOST()-instead
|-- sh-allmodconfig
| |--
drivers-char-mem.c:error:implicit-declaration-of-function-unxlate_dev_mem_ptr
| |--
standard-input:Error:local-label-(instance-number-of-a-fb-label)-is-not-defined
| `-- standard-input:Error:pcrel-too-far
|-- sparc64-randconfig-r004-20230630
| `-- drivers-bluetooth-btmtk.c:error:struct-hci_dev-has-no-member-named-dump
`-- x86_64-randconfig-m001-20230629
`--
fs-btrfs-volumes.c-btrfs_map_block()-error:we-previously-assumed-mirror_num_ret-could-be-null-(see-line-)
clang_recent_errors
|-- arm64-randconfig-r015-20230630
| |--
lib-kunit-executor_test.c:warning:cast-from-void-(-)(const-void-)-to-kunit_action_t-(aka-void-(-)(void-)-)-converts-to-incompatible-function-type
| `--
lib-kunit-test.c:warning:cast-from-void-(-)(const-void-)-to-kunit_action_t-(aka-void-(-)(void-)-)-converts-to-incompatible-function-type
|-- hexagon-randconfig-r005-20230630
| |--
lib-kunit-executor_test.c:warning:cast-from-void-(-)(const-void-)-to-kunit_action_t-(aka-void-(-)(void-)-)-converts-to-incompatible-function-type
| `--
lib-kunit-test.c:warning:cast-from-void-(-)(const-void-)-to-kunit_action_t-(aka-void-(-)(void-)-)-converts-to-incompatible-function-type
|-- hexagon-randconfig-r041-20230630
| |--
lib-kunit-executor_test.c:warning:cast-from-void-(-)(const-void-)-to-kunit_action_t-(aka-void-(-)(void-)-)-converts-to-incompatible-function-type
| `--
lib-kunit-test.c:warning:cast-from-void-(-)(const-void-)-to-kunit_action_t-(aka-void-(-)(void-)-)-converts-to-incompatible-function-type
|-- i386-randconfig-i016-20230629
| `-- drivers-bluetooth-btmtk.c:error:no-member-named-dump-in-struct-hci_dev
|--
[Intel-gfx] [PATCH v3 5/6] drm/i915/bios: Extract intel_bios_encoder_port()
From: Ville Syrjälä
We'll have a few places where we need to do the full (incl. ICL+ DSI)
DVO port->port conversion, so extract the code for that into a helper.
Suggested-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index ae83788177ce..c96bbbe4448e 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2374,6 +2374,19 @@ dsi_dvo_port_to_port(struct drm_i915_private *i915, u8
dvo_port)
}
}
+static enum port intel_bios_encoder_port(const struct intel_bios_encoder_data
*devdata)
+{
+ struct drm_i915_private *i915 = devdata->i915;
+ const struct child_device_config *child = &devdata->child;
+ enum port port;
+
+ port = dvo_port_to_port(i915, child->dvo_port);
+ if (port == PORT_NONE && DISPLAY_VER(i915) >= 11)
+ port = dsi_dvo_port_to_port(i915, child->dvo_port);
+
+ return port;
+}
+
static int parse_bdb_230_dp_max_link_rate(const int vbt_max_link_rate)
{
switch (vbt_max_link_rate) {
@@ -2613,12 +2626,9 @@ static void print_ddi_port(const struct
intel_bios_encoder_data *devdata,
static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
{
struct drm_i915_private *i915 = devdata->i915;
- const struct child_device_config *child = &devdata->child;
enum port port;
- port = dvo_port_to_port(i915, child->dvo_port);
- if (port == PORT_NONE && DISPLAY_VER(i915) >= 11)
- port = dsi_dvo_port_to_port(i915, child->dvo_port);
+ port = intel_bios_encoder_port(devdata);
if (port == PORT_NONE)
return;
--
2.39.3
[Intel-gfx] [PATCH v3 4/6] drm/i915: Remove AUX CH sanitation
From: Ville Syrjälä
Stop with the VBT AUX CH sanitation, and instead just check
that the appropriate AUX CH is still available when initializing
a DP/TC port.
The reason being that we want to start initializing ports in
VBT order to deal with VBTs that declare child devices with
seemingly conflicting ports. As the encoder initialization can
fail for other reasons (at least for eDP+AUX) we can't know
upfront which way the conflicts should be resolved.
Note that the old way of sanitizing gave priority to the last
port declared in the VBT, but now we sort of do the opposite by
favoring the first encoder to successfully initialize. The reason
for the old "last port wins" preference was eg. Asrock B250M-HDV
where port A (eDP) and port E (DP->VGA) have an AUX CH conflict
and we need to prefer port E. However with the new way port A (eDP)
will be probed first, but will fail to probe due to HPD and thus
port E will still win in the end.
v2: Pimp the commit message (Jani)
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/g4x_dp.c | 3 ++
drivers/gpu/drm/i915/display/intel_bios.c | 53 -
drivers/gpu/drm/i915/display/intel_ddi.c| 5 +-
drivers/gpu/drm/i915/display/intel_dp_aux.c | 51
4 files changed, 50 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
b/drivers/gpu/drm/i915/display/g4x_dp.c
index 0cab5992e3da..4c7187f7913e 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -1378,6 +1378,9 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
intel_infoframe_init(dig_port);
dig_port->aux_ch = intel_dp_aux_ch(intel_encoder);
+ if (dig_port->aux_ch == AUX_CH_NONE)
+ goto err_init_connector;
+
if (!intel_dp_init_connector(dig_port, intel_connector))
goto err_init_connector;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 6aeebd3c97f9..ae83788177ce 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2230,56 +2230,6 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8
vbt_pin)
return 0;
}
-static enum port get_port_by_aux_ch(struct drm_i915_private *i915, u8 aux_ch)
-{
- enum port port;
-
- if (!aux_ch)
- return PORT_NONE;
-
- for_each_port(port) {
- const struct intel_bios_encoder_data *devdata =
- i915->display.vbt.ports[port];
-
- if (devdata && aux_ch == devdata->child.aux_channel)
- return port;
- }
-
- return PORT_NONE;
-}
-
-static void sanitize_aux_ch(struct intel_bios_encoder_data *devdata,
- enum port port)
-{
- struct drm_i915_private *i915 = devdata->i915;
- struct child_device_config *child;
- enum port p;
-
- p = get_port_by_aux_ch(i915, devdata->child.aux_channel);
- if (p == PORT_NONE)
- return;
-
- drm_dbg_kms(&i915->drm,
- "port %c trying to use the same AUX CH (0x%x) as port %c, "
- "disabling port %c DP support\n",
- port_name(port), devdata->child.aux_channel,
- port_name(p), port_name(p));
-
- /*
-* If we have multiple ports supposedly sharing the aux channel, then DP
-* couldn't exist on the shared port. Otherwise they share the same aux
-* channel and system couldn't communicate with them separately.
-*
-* Give inverse child device order the priority, last one wins. Yes,
-* there are real machines (eg. Asrock B250M-HDV) where VBT has both
-* port A and port E with the same AUX ch and we must pick port E :(
-*/
- child = &i915->display.vbt.ports[p]->child;
-
- child->device_type &= ~DEVICE_TYPE_DISPLAYPORT_OUTPUT;
- child->aux_channel = 0;
-}
-
static u8 dvo_port_type(u8 dvo_port)
{
switch (dvo_port) {
@@ -2688,9 +2638,6 @@ static void parse_ddi_port(struct intel_bios_encoder_data
*devdata)
sanitize_device_type(devdata, port);
- if (intel_bios_encoder_supports_dp(devdata))
- sanitize_aux_ch(devdata, port);
-
i915->display.vbt.ports[port] = devdata;
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 662b5ceef3c8..9e4e6482aa26 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4938,8 +4938,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
dig_port->dp.output_reg = INVALID_MMIO_REG;
dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
- if (need_aux_ch(encoder, init_dp))
+ if (need_aux_ch(encoder, init_dp)) {
dig_port->aux_ch = intel_dp_aux_ch(e
[Intel-gfx] [PATCH v3 3/6] drm/i915: Remove DDC pin sanitation
From: Ville Syrjälä
Stop with the VBT DDC pin sanitation, and instead just check
that the appropriate DDC pin is still available when initializing
a HDMI connector.
The reason being that we want to start initializing ports in
VBT order to deal with VBTs that declare child devices with
seemingly conflicting ports. As the encoder initialization can
fail for other reasons (at least for eDP+AUX) we can't know
upfront which way the conflicts should be resolved.
Note that the old way of sanitizing gave priority to the last
port declared in the VBT, but now we sort of do the opposite by
favoring the first encoder to successfully initialize. So far
we're not aware of HDMI/DDC use cases where this would matter
but for AUX CH (will be subject to a similar change) there are
known cases where it matters.
Also note that the old code fell back to the platform default DDC
pin if the VBT pin was populated but invalid. That doesn't seem like
such a great idea because the VBT might have later declared another
port using that platform default pin, and so we might just be
creating more DDC pin conflicts here. So lets not second guess the
VBT and simply reject the entire HDMI encoder if the VBT DDC pin is
invalid.
v2: Pimp the commit message (Jani)
Cc: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 69 --
drivers/gpu/drm/i915/display/intel_hdmi.c | 72 +++
2 files changed, 59 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 4b9bf76e137d..6aeebd3c97f9 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2230,72 +2230,6 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8
vbt_pin)
return 0;
}
-static enum port get_port_by_ddc_pin(struct drm_i915_private *i915, u8 ddc_pin)
-{
- enum port port;
-
- if (!ddc_pin)
- return PORT_NONE;
-
- for_each_port(port) {
- const struct intel_bios_encoder_data *devdata =
- i915->display.vbt.ports[port];
-
- if (devdata && ddc_pin == devdata->child.ddc_pin)
- return port;
- }
-
- return PORT_NONE;
-}
-
-static void sanitize_ddc_pin(struct intel_bios_encoder_data *devdata,
-enum port port)
-{
- struct drm_i915_private *i915 = devdata->i915;
- struct child_device_config *child;
- u8 mapped_ddc_pin;
- enum port p;
-
- if (!devdata->child.ddc_pin)
- return;
-
- mapped_ddc_pin = map_ddc_pin(i915, devdata->child.ddc_pin);
- if (!intel_gmbus_is_valid_pin(i915, mapped_ddc_pin)) {
- drm_dbg_kms(&i915->drm,
- "Port %c has invalid DDC pin %d, "
- "sticking to defaults\n",
- port_name(port), mapped_ddc_pin);
- devdata->child.ddc_pin = 0;
- return;
- }
-
- p = get_port_by_ddc_pin(i915, devdata->child.ddc_pin);
- if (p == PORT_NONE)
- return;
-
- drm_dbg_kms(&i915->drm,
- "port %c trying to use the same DDC pin (0x%x) as port %c, "
- "disabling port %c DVI/HDMI support\n",
- port_name(port), mapped_ddc_pin,
- port_name(p), port_name(p));
-
- /*
-* If we have multiple ports supposedly sharing the pin, then dvi/hdmi
-* couldn't exist on the shared port. Otherwise they share the same ddc
-* pin and system couldn't communicate with them separately.
-*
-* Give inverse child device order the priority, last one wins. Yes,
-* there are real machines (eg. Asrock B250M-HDV) where VBT has both
-* port A and port E with the same AUX ch and we must pick port E :(
-*/
- child = &i915->display.vbt.ports[p]->child;
-
- child->device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING;
- child->device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT;
-
- child->ddc_pin = 0;
-}
-
static enum port get_port_by_aux_ch(struct drm_i915_private *i915, u8 aux_ch)
{
enum port port;
@@ -2754,9 +2688,6 @@ static void parse_ddi_port(struct intel_bios_encoder_data
*devdata)
sanitize_device_type(devdata, port);
- if (intel_bios_encoder_supports_dvi(devdata))
- sanitize_ddc_pin(devdata, port);
-
if (intel_bios_encoder_supports_dp(devdata))
sanitize_aux_ch(devdata, port);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7ac5e6c5e00d..8d1c8abfcffa 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2880,21 +2880,12 @@ static u8 g4x_port_to_ddc_pin(struct drm_i915_private
*dev_priv,
return ddc_pin;
}
-static u8 intel_
[Intel-gfx] [PATCH v3 2/6] drm/i915: Only populate aux_ch if really needed
From: Ville Syrjälä
Mixing VBT based AUX CH with platform defaults seems like
a recipe for conflicts. Let's only populate AUX CH if we
absolutely need it, that is only if we are dealing with
a DP output or a TC port (which need it due to some power
well shenanigans).
TODO: double check that real VBTs do in fact populate
the AUX CH for HDMI TC legacy ports...
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/g4x_hdmi.c | 1 -
drivers/gpu/drm/i915/display/intel_ddi.c | 12 +++-
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index c1fd13bdc9d2..634b14116d9d 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -775,6 +775,5 @@ void g4x_hdmi_init(struct drm_i915_private *dev_priv,
intel_infoframe_init(dig_port);
- dig_port->aux_ch = intel_dp_aux_ch(intel_encoder);
intel_hdmi_init_connector(dig_port, intel_connector);
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6cb24a472a9b..662b5ceef3c8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4676,6 +4676,14 @@ static bool port_strap_detected(struct drm_i915_private
*i915, enum port port)
}
}
+static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ return init_dp || intel_phy_is_tc(i915, phy);
+}
+
void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
{
struct intel_digital_port *dig_port;
@@ -4929,7 +4937,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
dig_port->dp.output_reg = INVALID_MMIO_REG;
dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
- dig_port->aux_ch = intel_dp_aux_ch(encoder);
+
+ if (need_aux_ch(encoder, init_dp))
+ dig_port->aux_ch = intel_dp_aux_ch(encoder);
if (intel_phy_is_tc(dev_priv, phy)) {
bool is_legacy =
--
2.39.3
[Intel-gfx] [PATCH v3 6/6] drm/i915: Try to initialize DDI/ICL+ DSI ports for every VBT child device
From: Ville Syrjälä
Try to deal with duplicate child devices for the same DDI port
by attempting to initialize them in VBT defined order The first
on to succeed for a specific DDI port will be the one we use.
We'll also get rid of i915->display.vbt.ports[] here as any conflicts
will now be handled at encoder registration time rather than during
VBT parsing. Note that intel_bios_encoder_data_lookup() still remaims
for pre-DDI DP/HDMI ports as those don't (at least yet) use VBT
driven initialization.
TODO: DSI dual link handling is sketchy at best
v2: Leave intel_bios_encoder_port() to the encoder callback (Jani)
Cc: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c| 9 ++-
drivers/gpu/drm/i915/display/icl_dsi.h| 4 +-
drivers/gpu/drm/i915/display/intel_bios.c | 47 ---
drivers/gpu/drm/i915/display/intel_bios.h | 6 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 57 +++
drivers/gpu/drm/i915/display/intel_ddi.h | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 11 +---
.../gpu/drm/i915/display/intel_display_core.h | 2 -
8 files changed, 93 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 59a2a289d9be..f7ebc146f96d 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1933,7 +1933,8 @@ static void icl_dsi_add_properties(struct intel_connector
*connector)
fixed_mode->vdisplay);
}
-void icl_dsi_init(struct drm_i915_private *dev_priv)
+void icl_dsi_init(struct drm_i915_private *dev_priv,
+ const struct intel_bios_encoder_data *devdata)
{
struct intel_dsi *intel_dsi;
struct intel_encoder *encoder;
@@ -1941,7 +1942,8 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
struct drm_connector *connector;
enum port port;
- if (!intel_bios_is_dsi_present(dev_priv, &port))
+ port = intel_bios_encoder_port(devdata);
+ if (port == PORT_NONE)
return;
intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
@@ -1958,6 +1960,8 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
intel_dsi->attached_connector = intel_connector;
connector = &intel_connector->base;
+ encoder->devdata = devdata;
+
/* register DSI encoder with DRM subsystem */
drm_encoder_init(&dev_priv->drm, &encoder->base,
&gen11_dsi_encoder_funcs,
DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
@@ -1995,7 +1999,6 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
intel_dsi->panel_power_off_time = ktime_get_boottime();
- encoder->devdata = intel_bios_encoder_data_lookup(dev_priv, port);
intel_bios_init_panel_late(dev_priv, &intel_connector->panel,
encoder->devdata, NULL);
mutex_lock(&dev_priv->drm.mode_config.mutex);
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.h
b/drivers/gpu/drm/i915/display/icl_dsi.h
index b4861b56b5b2..43fa7d72eeb1 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.h
+++ b/drivers/gpu/drm/i915/display/icl_dsi.h
@@ -7,9 +7,11 @@
#define __ICL_DSI_H__
struct drm_i915_private;
+struct intel_bios_encoder_data;
struct intel_crtc_state;
-void icl_dsi_init(struct drm_i915_private *i915);
+void icl_dsi_init(struct drm_i915_private *dev_priv,
+ const struct intel_bios_encoder_data *devdata);
void icl_dsi_frame_update(struct intel_crtc_state *crtc_state);
#endif /* __ICL_DSI_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index c96bbbe4448e..858c959f7bab 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2374,7 +2374,7 @@ dsi_dvo_port_to_port(struct drm_i915_private *i915, u8
dvo_port)
}
}
-static enum port intel_bios_encoder_port(const struct intel_bios_encoder_data
*devdata)
+enum port intel_bios_encoder_port(const struct intel_bios_encoder_data
*devdata)
{
struct drm_i915_private *i915 = devdata->i915;
const struct child_device_config *child = &devdata->child;
@@ -2497,7 +2497,7 @@ intel_bios_encoder_supports_edp(const struct
intel_bios_encoder_data *devdata)
devdata->child.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR;
}
-static bool
+bool
intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata)
{
return devdata->child.device_type & DEVICE_TYPE_MIPI_OUTPUT;
@@ -2556,13 +2556,17 @@ static bool is_port_valid(struct drm_i915_private
*i915, enum port port)
return true;
}
-static void print_ddi_port(const struct intel_bios_encoder_data *devdata,
- enum port port)
+static void print_ddi_port(const struct intel_bios_encoder_data *devdata)
{
struct drm_i915_private *i915 = devdata->i
[Intel-gfx] [PATCH v3 0/6] drm/i915: Init DDI ports in VBT order
From: Ville Syrjälä The remaining parts of the big VBT based DDI port initialization series. The main goal being to get the HDMI port working on many ADL-P machines where the VBT declares both eDP and HDMI for the same DDI port (B). v3: Pimped commit messages Add intel_bios_encoder_port() and use it Ville Syrjälä (6): drm/i915: Initialize dig_port->aux_ch to NONE to be sure drm/i915: Only populate aux_ch if really needed drm/i915: Remove DDC pin sanitation drm/i915: Remove AUX CH sanitation drm/i915/bios: Extract intel_bios_encoder_port() drm/i915: Try to initialize DDI/ICL+ DSI ports for every VBT child device drivers/gpu/drm/i915/display/g4x_dp.c | 5 + drivers/gpu/drm/i915/display/g4x_hdmi.c | 3 +- drivers/gpu/drm/i915/display/icl_dsi.c| 9 +- drivers/gpu/drm/i915/display/icl_dsi.h| 4 +- drivers/gpu/drm/i915/display/intel_bios.c | 185 -- drivers/gpu/drm/i915/display/intel_bios.h | 6 + drivers/gpu/drm/i915/display/intel_ddi.c | 74 +-- drivers/gpu/drm/i915/display/intel_ddi.h | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 11 +- .../gpu/drm/i915/display/intel_display_core.h | 2 - drivers/gpu/drm/i915/display/intel_dp_aux.c | 51 - drivers/gpu/drm/i915/display/intel_hdmi.c | 72 +-- 12 files changed, 231 insertions(+), 195 deletions(-) -- 2.39.3
[Intel-gfx] [PATCH v3 1/6] drm/i915: Initialize dig_port->aux_ch to NONE to be sure
From: Ville Syrjälä
Make sure dig_port->aux_ch is trustworthy by initializing it
to NONE (-1) at the start. The encoder init will later fill in
the actual value, if appropriate.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/g4x_dp.c| 2 ++
drivers/gpu/drm/i915/display/g4x_hdmi.c | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
b/drivers/gpu/drm/i915/display/g4x_dp.c
index c58a3f249a01..0cab5992e3da 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -1273,6 +1273,8 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
if (!dig_port)
return false;
+ dig_port->aux_ch = AUX_CH_NONE;
+
intel_connector = intel_connector_alloc();
if (!intel_connector)
goto err_connector_alloc;
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 8c71e3ede680..c1fd13bdc9d2 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -698,6 +698,8 @@ void g4x_hdmi_init(struct drm_i915_private *dev_priv,
if (!dig_port)
return;
+ dig_port->aux_ch = AUX_CH_NONE;
+
intel_connector = intel_connector_alloc();
if (!intel_connector) {
kfree(dig_port);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 61722556bb47..6cb24a472a9b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4747,6 +4747,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
if (!dig_port)
return;
+ dig_port->aux_ch = AUX_CH_NONE;
+
encoder = &dig_port->base;
encoder->devdata = devdata;
--
2.39.3
[Intel-gfx] ✓ Fi.CI.BAT: success for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev15)
== Series Details == Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev15) URL : https://patchwork.freedesktop.org/series/107550/ State : success == Summary == CI Bug Log - changes from CI_DRM_13340 -> Patchwork_107550v15 Summary --- **WARNING** Minor unknown changes coming with Patchwork_107550v15 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107550v15, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/index.html Participating hosts (42 -> 39) -- Missing(3): fi-kbl-soraka fi-snb-2520m fi-pnv-d510 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_107550v15: ### IGT changes ### Warnings * igt@kms_setmode@basic-clone-single-crtc: - bat-mtlp-6: [SKIP][1] ([i915#4579]) -> [SKIP][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-6/igt@kms_setm...@basic-clone-single-crtc.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/bat-mtlp-6/igt@kms_setm...@basic-clone-single-crtc.html - bat-mtlp-8: [SKIP][3] ([i915#4579]) -> [SKIP][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-8/igt@kms_setm...@basic-clone-single-crtc.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/bat-mtlp-8/igt@kms_setm...@basic-clone-single-crtc.html Known issues Here are the changes found in Patchwork_107550v15 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@parallel-random-engines: - bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/bat-mtlp-8/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_pm_rps@basic-api: - bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#6621]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/bat-mtlp-8/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-8: NOTRUN -> [DMESG-FAIL][7] ([i915#7059]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@requests: - bat-rpls-2: [PASS][8] -> [ABORT][9] ([i915#7913]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-rpls-2/igt@i915_selftest@l...@requests.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/bat-rpls-2/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@reset: - bat-rpls-1: [PASS][10] -> [ABORT][11] ([i915#4983] / [i915#7461] / [i915#7981] / [i915#8347] / [i915#8384]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-rpls-1/igt@i915_selftest@l...@reset.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/bat-rpls-1/igt@i915_selftest@l...@reset.html * igt@i915_suspend@basic-s3-without-i915: - bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#6645]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/bat-mtlp-8/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#7828]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/bat-mtlp-8/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@read-crc-frame-sequence: - bat-adlp-9: NOTRUN -> [SKIP][14] ([i915#3546]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1: - bat-rplp-1: [PASS][15] -> [ABORT][16] ([i915#8442] / [i915#8668]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html * igt@prime_vgem@basic-fence-read: - bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#3708]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/bat-mtlp-8/igt@prime_v...@basic-fence-read.html * igt@prime_vgem@basic-gtt: - bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#3708] / [i915#4077]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v15/bat-mtlp-8/igt@prime_v...@basic-gtt.html Possible fixes * igt@i915_pm_rpm@basic-pci-d3-state: - bat-mtlp-8:
[Intel-gfx] ✓ Fi.CI.BAT: success for DSC misc fixes (rev3)
== Series Details == Series: DSC misc fixes (rev3) URL : https://patchwork.freedesktop.org/series/117662/ State : success == Summary == CI Bug Log - changes from CI_DRM_13340 -> Patchwork_117662v3 Summary --- **WARNING** Minor unknown changes coming with Patchwork_117662v3 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_117662v3, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/index.html Participating hosts (42 -> 40) -- Missing(2): fi-kbl-soraka fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_117662v3: ### IGT changes ### Warnings * igt@kms_setmode@basic-clone-single-crtc: - bat-mtlp-6: [SKIP][1] ([i915#4579]) -> [SKIP][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-6/igt@kms_setm...@basic-clone-single-crtc.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/bat-mtlp-6/igt@kms_setm...@basic-clone-single-crtc.html - bat-mtlp-8: [SKIP][3] ([i915#4579]) -> [SKIP][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-8/igt@kms_setm...@basic-clone-single-crtc.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/bat-mtlp-8/igt@kms_setm...@basic-clone-single-crtc.html Known issues Here are the changes found in Patchwork_117662v3 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gt_lrc: - bat-dg2-11: [PASS][5] -> [INCOMPLETE][6] ([i915#7609] / [i915#7913]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@slpc: - bat-mtlp-6: [PASS][7] -> [DMESG-WARN][8] ([i915#6367]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-6/igt@i915_selftest@l...@slpc.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/bat-mtlp-6/igt@i915_selftest@l...@slpc.html - bat-rpls-2: NOTRUN -> [DMESG-WARN][9] ([i915#6367]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/bat-rpls-2/igt@i915_selftest@l...@slpc.html * igt@i915_suspend@basic-s2idle-without-i915: - bat-rpls-2: NOTRUN -> [ABORT][10] ([i915#6687] / [i915#8668]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#1845] / [i915#5354]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_psr@primary_mmap_gtt: - bat-rplp-1: NOTRUN -> [SKIP][12] ([i915#1072]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html * igt@kms_setmode@basic-clone-single-crtc: - bat-rplp-1: NOTRUN -> [ABORT][13] ([i915#8260] / [i915#8668]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html Possible fixes * igt@i915_selftest@live@gt_mocs: - bat-mtlp-6: [DMESG-FAIL][14] ([i915#7059]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@hangcheck: - fi-skl-guc: [DMESG-FAIL][16] ([i915#8723]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@reset: - bat-rpls-2: [ABORT][18] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#7981] / [i915#8347]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-rpls-2/igt@i915_selftest@l...@reset.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v3/bat-rpls-2/igt@i915_selftest@l...@reset.html Warnings * igt@i915_module_load@load: - bat-adlp-11:[DMESG-WARN][20] ([i915#4423]) -> [ABORT][21] ([i915#4423]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13340/bat-adlp-11/igt@i915_module_l...@load.html [
Re: [Intel-gfx] [RFC] tentative fix for drm/i915/gt regression on preempt-rt
On 2023-06-22 20:57:50 [-0400], Paul Gortmaker wrote:
[ longer report about what is broken.]
Commit ade8a0f598443 ("drm/i915: Make all GPU resets atomic") introduces
a preempt_disable() section around the invocation of the reset callback.
I can't find an explanation why this is needed. There was a comment
saying
| * We want to perform per-engine reset from atomic context (e.g.
| * softirq), which imposes the constraint that we cannot sleep.
but it does not state the problem with being preempted while waiting for
the reset. The commit itself does not explain why an atomic reset is
needed, it just states that it is a requirement now. On !RT we could
pull packets from a NICs and forward them other NICs for 2ms.
I've been looking over the reset callbacks and gen8_reset_engines() +
gen6_reset_engines() acquire a spinlock_t. Since this becomes a sleeping
lock on PREEMPT_RT it must not be acquired with disabled preemption.
i915_do_reset() acquires no lock but then has two udelay()s of 50us
each. Not good latency wise in a preempt-off section.
Could someone please explain why atomic is needed during reset, what
problems are introduced by a possible preemption?
Sebastian
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DSC misc fixes (rev3)
== Series Details == Series: DSC misc fixes (rev3) URL : https://patchwork.freedesktop.org/series/117662/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DSC misc fixes (rev3)
== Series Details == Series: DSC misc fixes (rev3) URL : https://patchwork.freedesktop.org/series/117662/ State : warning == Summary == Error: dim checkpatch failed eaaa78e717b1 drm/i915/dp: Consider output_format while computing dsc bpp 6395d26c8fa4 drm/i915/dp: Move compressed bpp check with 420 format inside the helper bd41f59ecfd6 drm/i915/dp_mst: Use output_format to get the final link bpp 53de81e156b5 drm/i915/dp: Use consistent name for link bpp and compressed bpp 6bb10c993db5 drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp a2651d52a8a2 drm/i915/display: Account for DSC not split case while computing cdclk f459c9b8e0cb drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck f8f3b73cb322 drm/i915/dp: Remove extra logs for printing DSC info ab776e175f24 drm/display/dp: Fix the DP DSC Receiver cap size db60aff677cd drm/i915/dp: Avoid forcing DSC BPC for MST case -:26: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #26: FILE: drivers/gpu/drm/i915/display/intel_dp.c:1691: + drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc); total: 0 errors, 1 warnings, 0 checks, 30 lines checked 6eee2757cbce drm/i915/dp: Add functions to get min/max src input bpc with DSC b76db3c66d95 drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also -:63: WARNING:LONG_LINE: line length of 109 exceeds 100 columns #63: FILE: drivers/gpu/drm/i915/display/intel_dp.c:1723: + drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc); total: 0 errors, 1 warnings, 0 checks, 77 lines checked 21e6f7ac7a39 drm/i915/dp: Avoid left shift of DSC output bpp by 4 b0bbbe39762f drm/i915/dp: Rename helper to get DSC max pipe_bpp f5002142f8ee drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp -:38: WARNING:LONG_LINE: line length of 109 exceeds 100 columns #38: FILE: drivers/gpu/drm/i915/display/intel_dp.c:1707: + drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n", intel_dp->force_dsc_bpc); total: 0 errors, 1 warnings, 0 checks, 220 lines checked 390eb4cfcf83 drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with DSC fd08f0fb355f drm/i915/dp: Separate out function to get compressed bpp with joiner 1ac66f2ab1ca drm/i915/dp: Get optimal link config to have best compressed bpp 8941a0ebbb9f drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info -:62: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #62: FILE: drivers/gpu/drm/i915/display/intel_dp.c:1892: + dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3); -:117: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #117: FILE: drivers/gpu/drm/i915/display/intel_dp_mst.c:236: + max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp, crtc_state, max_bpp / 3); -:126: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #126: FILE: drivers/gpu/drm/i915/display/intel_dp_mst.c:242: + max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp, crtc_state->pipe_bpp); -:127: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #127: FILE: drivers/gpu/drm/i915/display/intel_dp_mst.c:243: + min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp, crtc_state->pipe_bpp); total: 0 errors, 4 warnings, 0 checks, 107 lines checked
[Intel-gfx] [PATCH 2/2] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints
Add a wrapper function to check dp_downstream clock/bandwidth
constraints. Based on whether the sink supports FRL/TMDS the wrapper
calls the appropriate FRL/TMDS functions.
v2: Use new wrapper while getting max bpc also.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 54 -
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0d938f430856..a96425a6ea31 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1065,6 +1065,25 @@ intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int
target_clock,
return MODE_OK;
}
+static bool
+pcon_sink_pair_support_frl(struct intel_dp *intel_dp)
+{
+ return intel_dp->dfp.pcon_max_frl_bw &&
intel_dp_hdmi_sink_max_frl(intel_dp);
+}
+
+static enum drm_mode_status
+intel_dp_hdmi_bw_check(struct intel_dp *intel_dp,
+ int target_clock, int bpc,
+ enum intel_output_format sink_format,
+ bool respect_downstream_limits)
+{
+ if (pcon_sink_pair_support_frl(intel_dp))
+ return intel_dp_frl_bw_valid(intel_dp, target_clock, bpc,
sink_format);
+
+ return intel_dp_tmds_clock_valid(intel_dp, target_clock, bpc,
sink_format,
+respect_downstream_limits);
+}
+
static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector *connector,
const struct drm_display_mode *mode,
@@ -1074,42 +1093,23 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
const struct drm_display_info *info = &connector->base.display_info;
enum drm_mode_status status;
enum intel_output_format sink_format = intel_dp_sink_format(connector,
mode);
+ int bpc = 8; /* Assume 8bpc for the DP++/HDMI/DVI TMDS/FRL bw check */
- /* If PCON supports FRL MODE, check FRL bandwidth constraints */
- if (intel_dp->dfp.pcon_max_frl_bw &&
intel_dp_hdmi_sink_max_frl(intel_dp)) {
- /* Assume 8bpc for the HDMI2.1 FRL BW check */
- status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8,
sink_format);
- if (status != MODE_OK) {
- if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
- !connector->base.ycbcr_420_allowed ||
- !drm_mode_is_420_also(info, mode))
- return status;
-
- sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- status = intel_dp_frl_bw_valid(intel_dp, target_clock,
8, sink_format);
- if (status != MODE_OK)
- return status;
- }
-
- return MODE_OK;
- }
-
- if (intel_dp->dfp.max_dotclock &&
+ if (!intel_dp_hdmi_sink_max_frl(intel_dp) &&
+ intel_dp->dfp.max_dotclock &&
target_clock > intel_dp->dfp.max_dotclock)
return MODE_CLOCK_HIGH;
- /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
- status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
- 8, sink_format, true);
+ status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc,
sink_format, true);
if (status != MODE_OK) {
if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
!connector->base.ycbcr_420_allowed ||
!drm_mode_is_420_also(info, mode))
return status;
+
sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
- 8, sink_format, true);
+ status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc,
sink_format, true);
if (status != MODE_OK)
return status;
}
@@ -1376,8 +1376,8 @@ static int intel_dp_hdmi_compute_bpc(struct intel_dp
*intel_dp,
for (; bpc >= 8; bpc -= 2) {
if (intel_hdmi_bpc_possible(crtc_state, bpc,
intel_dp_has_hdmi_sink(intel_dp)) &&
- intel_dp_tmds_clock_valid(intel_dp, clock, bpc,
crtc_state->sink_format,
- respect_downstream_limits) ==
MODE_OK)
+ intel_dp_hdmi_bw_check(intel_dp, clock, bpc,
crtc_state->sink_format,
+ respect_downstream_limits) ==
MODE_OK)
return bpc;
}
--
2.40.1
[Intel-gfx] [PATCH 1/2] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
During FRL bandwidth check for downstream HDMI2.1 sink,
the min BPC supported is incorrectly taken for DP, and the check does
not consider ybcr420 only modes.
This patch fixes the bandwidth calculation similar to the TMDS case, by
taking min 8Bpc and considering Ycbcr420 only modes.
v2: Check for both Pcon and Sink FRL capabilities.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 60 ++---
1 file changed, 43 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9f40da20e88d..0d938f430856 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -120,6 +120,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
+static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -1037,6 +1038,33 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
return MODE_OK;
}
+static enum drm_mode_status
+intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
+ int bpc, enum intel_output_format sink_format)
+{
+ int target_bw;
+ int max_frl_bw;
+ int bpp = bpc * 3;
+
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ target_clock /= 2;
+
+ target_bw = bpp * target_clock;
+
+ /* check for MAX FRL BW for both PCON and HDMI2.1 sink */
+ max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw,
+intel_dp_hdmi_sink_max_frl(intel_dp));
+
+ /* converting bw from Gbps to Kbps*/
+ max_frl_bw = max_frl_bw * 100;
+
+ /* #FIXME check bandwidth with DSC if both PCON and HDMI sink support
DSC */
+ if (target_bw > max_frl_bw)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector *connector,
const struct drm_display_mode *mode,
@@ -1045,23 +1073,23 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
struct intel_dp *intel_dp = intel_attached_dp(connector);
const struct drm_display_info *info = &connector->base.display_info;
enum drm_mode_status status;
- enum intel_output_format sink_format;
+ enum intel_output_format sink_format = intel_dp_sink_format(connector,
mode);
/* If PCON supports FRL MODE, check FRL bandwidth constraints */
- if (intel_dp->dfp.pcon_max_frl_bw) {
- int target_bw;
- int max_frl_bw;
- int bpp = intel_dp_mode_min_output_bpp(connector, mode);
-
- target_bw = bpp * target_clock;
-
- max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
-
- /* converting bw from Gbps to Kbps*/
- max_frl_bw = max_frl_bw * 100;
-
- if (target_bw > max_frl_bw)
- return MODE_CLOCK_HIGH;
+ if (intel_dp->dfp.pcon_max_frl_bw &&
intel_dp_hdmi_sink_max_frl(intel_dp)) {
+ /* Assume 8bpc for the HDMI2.1 FRL BW check */
+ status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8,
sink_format);
+ if (status != MODE_OK) {
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+ !connector->base.ycbcr_420_allowed ||
+ !drm_mode_is_420_also(info, mode))
+ return status;
+
+ sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ status = intel_dp_frl_bw_valid(intel_dp, target_clock,
8, sink_format);
+ if (status != MODE_OK)
+ return status;
+ }
return MODE_OK;
}
@@ -1070,8 +1098,6 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
target_clock > intel_dp->dfp.max_dotclock)
return MODE_CLOCK_HIGH;
- sink_format = intel_dp_sink_format(connector, mode);
-
/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
8, sink_format, true);
--
2.40.1
[Intel-gfx] [PATCH 0/2] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes
This series fixes issues faced when an HDMI2.1 sink that does not support DSC is connected via HDMI2.1PCON. It also includes other minor HDMI2.1 PCON fixes/refactoring. Patch 1-3 Have minor fixes to consider output_format while computing dsc_bpp and have consistent naming for pipe_bpp, link_bpp and compressed_bpp. Patch 4-6 Calculate the max BPC that can be sufficient with either RGB or YCbcr420 format for the maximum FRL rate supported. Rev2: Split the refactoring of DFP RG->YCBCR conversion into smaller patches, as suggested by Jani N. Also dropped the unnecessary helper for DSC1.2 support for HDMI2.1 DFP. Rev3: As suggested by Ville, added new member sink_format to store the final format that the sink will be using, which might be different than the output format, and thus might need color/format conversion performed by the PCON. Rev4: Fix typo in switch case as, reported by kernel test bot. Rev5: Corrected order of setting sink_format and output_format. (Ville) Avoided the flag ycbcr420_output and used the sink_format to facilitate 4:2:2 support at a later stage. (Ville) Rev6: Added missing changes for sdvo. (Ville) Added check for scaler and DSC constraints with YCbCr420. Rev7: Split change to add scaler constraint in separate patch, and rebased. Rev8: Rebased. Fixed check for mode rate with dsc in modevalid. Fixed scaler constraint as per display version. Rev9: Rebased. Rev10: Addressed review comments from Ville. Dropped patch to check for mode rate with dsc during modevalid, as the compressed bpp is already selected with bandwidth considerations. Rev11: Fixed the policy to use output format as RGB first if possible, followed by YCbCr444, atlast YCbCr420. Also removed the scaler-constraints with YCbCr420, as these are handled in scaler code. (Ville) Rev12: Added a patch for configuring PCON to convert output_format to YCBCR444. Added patch to have consistent naming for link bpp and compressed bpp. Rev13: Few patches of original series are merged. Rebased the patches and addressed few comments from Ville on last series. Rev14: Use new wrapper for checking frl/tmds downstream constraints while getting max bpc also. Ankit Nautiyal (2): drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints drivers/gpu/drm/i915/display/intel_dp.c | 86 - 1 file changed, 56 insertions(+), 30 deletions(-) -- 2.40.1
[Intel-gfx] [PATCH 15/19] drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
Refactor code to separate functions for eDP and DP for computing
pipe_bpp/compressed bpp when DSC is involved.
This will help to optimize the link configuration for DP later.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 189
1 file changed, 125 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4495dcbb03e1..633dba7885fd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1688,6 +1688,114 @@ bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private
*i915, int pipe_bpp)
return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
}
+static
+int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int forced_bpp;
+
+ if (!intel_dp->force_dsc_bpc)
+ return 0;
+
+ forced_bpp = intel_dp->force_dsc_bpc * 3;
+
+ if (is_dsc_pipe_bpp_sufficient(i915, forced_bpp)) {
+ drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n",
intel_dp->force_dsc_bpc);
+ return forced_bpp;
+ }
+
+ drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC
limits\n", intel_dp->force_dsc_bpc);
+
+ return 0;
+}
+
+static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+struct intel_crtc_state *pipe_config,
+struct drm_connector_state *conn_state,
+struct link_config_limits *limits,
+int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u16 output_bpp, dsc_max_compressed_bpp = 0;
+ int forced_bpp, pipe_bpp;
+
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+
+ if (forced_bpp) {
+ pipe_bpp = forced_bpp;
+ } else {
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
conn_state->max_requested_bpc);
+
+ if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ drm_dbg_kms(&i915->drm,
+ "Computed BPC less than min supported by
source for DSC\n");
+ return -EINVAL;
+ }
+ }
+ /*
+* For now enable DSC for max link rate, max lane count.
+* Optimize this later for the minimum possible link rate/lane count
+* with DSC enabled for the requested mode.
+*/
+ pipe_config->port_clock = limits->max_rate;
+ pipe_config->lane_count = limits->max_lane_count;
+ dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915,
+
pipe_config->port_clock,
+
pipe_config->lane_count,
+
adjusted_mode->crtc_clock,
+
adjusted_mode->crtc_hdisplay,
+
pipe_config->bigjoiner_pipes,
+
pipe_config->output_format,
+pipe_bpp,
+timeslots);
+ if (!dsc_max_compressed_bpp) {
+ drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n");
+ return -EINVAL;
+ }
+
+ output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp);
+
+ pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp,
output_bpp);
+
+ pipe_config->pipe_bpp = pipe_bpp;
+
+ return 0;
+}
+
+static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state
*conn_state,
+ struct link_config_limits *limits)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int pipe_bpp, forced_bpp;
+
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+
+ if (forced_bpp) {
+ pipe_bpp = forced_bpp;
+ } else {
+ /* For eDP use max bpp that can be supported with DSC. */
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
+
conn_state->max_requested_bpc);
+ if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ drm_dbg_kms(&i915->drm,
+ "Computed BPC less than min s
[Intel-gfx] [PATCH 17/19] drm/i915/dp: Separate out function to get compressed bpp with joiner
Pull the code to get joiner constraints on maximum compressed bpp into
separate function.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 49 ++---
1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f6f9b061fc0b..01fdab148d74 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -731,6 +731,30 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private
*i915, u32 bpp, u32 p
return bits_per_pixel;
}
+static
+u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner)
+{
+ u32 max_bpp_small_joiner_ram;
+
+ /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
+ max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
mode_hdisplay;
+
+ if (bigjoiner) {
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 :
24;
+ u32 max_bpp_bigjoiner =
+ i915->display.cdclk.max_cdclk_freq * 2 *
bigjoiner_interface_bits /
+ intel_dp_mode_to_fec_clock(mode_clock);
+
+ max_bpp_small_joiner_ram *= 2;
+
+ return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);
+ }
+
+ return max_bpp_small_joiner_ram;
+}
+
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
@@ -739,7 +763,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct
drm_i915_private *i915,
u32 pipe_bpp,
u32 timeslots)
{
- u32 bits_per_pixel, max_bpp_small_joiner_ram;
+ u32 bits_per_pixel, joiner_max_bpp;
/*
* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
@@ -779,27 +803,10 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct
drm_i915_private *i915,
(link_clock * lane_count * 8),
intel_dp_mode_to_fec_clock(mode_clock));
- /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
- max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
- mode_hdisplay;
-
- if (bigjoiner)
- max_bpp_small_joiner_ram *= 2;
-
- /*
-* Greatest allowed DSC BPP = MIN (output BPP from available Link BW
-* check, output bpp from small joiner RAM check)
-*/
- bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
+ joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
+ mode_hdisplay,
bigjoiner);
- if (bigjoiner) {
- int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 :
24;
- u32 max_bpp_bigjoiner =
- i915->display.cdclk.max_cdclk_freq * 2 *
bigjoiner_interface_bits /
- intel_dp_mode_to_fec_clock(mode_clock);
-
- bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
- }
+ bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel,
pipe_bpp);
--
2.40.1
[Intel-gfx] [PATCH 18/19] drm/i915/dp: Get optimal link config to have best compressed bpp
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
-Fix the checks for limits->max/min_bpp while iterating over list of
valid DSC bpcs. (Stan)
v3:
-Refactor the code to have pipe bpp/compressed bpp computation and slice
count calculation separately for different cases.
v4:
-Separate the pipe_bpp calculation for eDP and DP.
v5:
-Get rid of magic numbers for max and min bpp,
and improve documentation. (Stan).
-Use functions for {src_sink}_{min_max}_compressed_bpp (Ville).
v6:
-Remove lines to set link config to max.
v7:
-Split the part to separate edp and dp functions for computing DSC BPP
into separate patch.
v8:
-Separate mechanism to get compressed bpp for ICL,TGL and XELPD+.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 294 +---
1 file changed, 261 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 01fdab148d74..119a1eff8e6c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1679,6 +1679,231 @@ static bool intel_dp_dsc_supports_format(struct
intel_dp *intel_dp,
return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
sink_dsc_format);
}
+static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
+ u32 lane_count, u32 mode_clock,
+ enum intel_output_format
output_format,
+ int timeslots)
+{
+ u32 available_bw, required_bw;
+
+ available_bw = (link_clock * lane_count * timeslots) / 8;
+ required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock));
+
+ return available_bw > required_bw;
+}
+
+static int dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ u16 compressed_bpp,
+ int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
+ int link_rate, lane_count;
+ int i;
+
+ for (i = 0; i < intel_dp->num_common_rates; i++) {
+ link_rate = intel_dp_common_rate(intel_dp, i);
+ if (link_rate < limits->min_rate || link_rate >
limits->max_rate)
+ continue;
+
+ for (lane_count = limits->min_lane_count;
+lane_count <= limits->max_lane_count;
+lane_count <<= 1) {
+ if (!is_bw_sufficient_for_dsc_config(compressed_bpp,
link_rate, lane_count,
+
adjusted_mode->clock,
+
pipe_config->output_format,
+timeslots))
+ continue;
+
+ pipe_config->lane_count = lane_count;
+ pipe_config->port_clock = link_rate;
+
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static
+u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp,
+ struct intel_crtc_state
*pipe_config,
+ int bpc)
+{
+ u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd);
+
+ if (max_bppx16)
+ return max_bppx16;
+ /*
+* If support not given in DPCD 67h, 68h use the Maximum Allowed bit
rate
+* values as given in spec Table 2-157 DP v2.0
+*/
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return (3 * bpc) << 4;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return (3 * (bpc / 2)) << 4;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
+{
+ /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return 8;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return 6;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static int dsc_
[Intel-gfx] [PATCH 14/19] drm/i915/dp: Rename helper to get DSC max pipe_bpp
The helper intel_dp_dsc_compute_bpp gives the maximum
pipe bpp that is allowed with DSC.
Rename the this to reflect that it returns max pipe bpp supported
with DSC.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 16dc32846f5a..4495dcbb03e1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1172,7 +1172,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be
picked
*/
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX);
/*
* Output bpp is stored in 6.4 format so right shift by 4 to
get the
@@ -1532,7 +1532,7 @@ u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private
*i915)
return 0;
}
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
@@ -1722,8 +1722,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
"Cannot force DSC BPC:%d, due to DSC BPC
limits\n",
intel_dp->force_dsc_bpc);
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
-
conn_state->max_requested_bpc);
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
+
conn_state->max_requested_bpc);
if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 6fd423463f5c..788a577ebe16 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -106,7 +106,7 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4895d6242915..3eb085fbc7c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -971,7 +971,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be
picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX);
if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_compressed_bpp =
--
2.40.1
[Intel-gfx] [PATCH 19/19] drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info
From: Stanislav Lisovskiy
Currently we seem to be using wrong DPCD register for reading
compressed bpps, reading min/max input bpc instead of compressed bpp.
Fix that, so that we now apply min/max compressed bpp limitations we
get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD
register DP_DSC_MAX_BITS_PER_PIXEL_LOW/HIGH.
This might also allow us to get rid of an ugly compressed bpp
recalculation, which we had to add to make some MST hubs usable.
v2: - Fix operator precedence
v3: - Added debug info about compressed bpps
v4: - Don't try to intersect Sink input bpp and compressed bpps.
v5: - Decrease step while looking for suitable compressed bpp to
accommodate.
v6: - Use helper for getting min and max compressed_bpp (Ankit)
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 +++---
drivers/gpu/drm/i915/display/intel_dp.h | 4 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 43 -
3 files changed, 26 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 119a1eff8e6c..9f157ff6cce4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1753,7 +1753,7 @@ u16 intel_dp_dsc_max_sink_compressed_bppx16(struct
intel_dp *intel_dp,
return 0;
}
-static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
+int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
{
/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
switch (pipe_config->output_format) {
@@ -1770,9 +1770,9 @@ static int dsc_sink_min_compressed_bpp(struct
intel_crtc_state *pipe_config)
return 0;
}
-static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
- struct intel_crtc_state *pipe_config,
- int bpc)
+int intel_dp_dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
+struct intel_crtc_state *pipe_config,
+int bpc)
{
return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp,
pipe_config, bpc) >> 4;
@@ -1885,11 +1885,11 @@ static int dsc_compute_compressed_bpp(struct intel_dp
*intel_dp,
int dsc_joiner_max_bpp;
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
- dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
+ dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
- dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config,
pipe_bpp / 3);
+ dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp,
pipe_config, pipe_bpp / 3);
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp)
: dsc_src_max_bpp;
dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915,
adjusted_mode->clock,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 788a577ebe16..f29e48028f39 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -114,6 +114,10 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct
drm_i915_private *i915,
enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots);
+int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);
+int intel_dp_dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
+struct intel_crtc_state *pipe_config,
+int bpc);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3eb085fbc7c8..0df930d605ed 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -101,6 +101,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct
intel_encoder *encoder,
crtc_state->lane_count);
}
+ drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp
%d\n",
+ min_bpp, max_bpp);
+
for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
@@ -194,8 +197,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct
intel_encoder *encoder,
u8 dsc_bpc[3] = {0};
int
[Intel-gfx] [PATCH 16/19] drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with DSC
Currently we check if pipe_bpp is max the min DSC bpc requirements.
Add checks for max DSC BPC/BPP constraints while computing the
pipe_bpp when DSC is in use.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 34 +
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 633dba7885fd..f6f9b061fc0b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1683,13 +1683,27 @@ u8 intel_dp_dsc_min_src_input_bpc(struct
drm_i915_private *i915)
}
static
-bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
+bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits,
+ int pipe_bpp)
{
- return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
+ u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
+
+ dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915),
conn_state->max_requested_bpc);
+ dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+
+ dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->max_bpp);
+ dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->min_bpp);
+
+ return pipe_bpp >= dsc_min_pipe_bpp &&
+ pipe_bpp <= dsc_max_pipe_bpp;
}
static
-int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
+int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int forced_bpp;
@@ -1699,7 +1713,7 @@ int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
forced_bpp = intel_dp->force_dsc_bpc * 3;
- if (is_dsc_pipe_bpp_sufficient(i915, forced_bpp)) {
+ if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n",
intel_dp->force_dsc_bpc);
return forced_bpp;
}
@@ -1720,16 +1734,16 @@ static int intel_dp_dsc_compute_pipe_bpp(struct
intel_dp *intel_dp,
u16 output_bpp, dsc_max_compressed_bpp = 0;
int forced_bpp, pipe_bpp;
- forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
if (forced_bpp) {
pipe_bpp = forced_bpp;
} else {
pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
conn_state->max_requested_bpc);
- if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits,
pipe_bpp)) {
drm_dbg_kms(&i915->drm,
- "Computed BPC less than min supported by
source for DSC\n");
+ "Computed BPC is not in DSC BPC limits\n");
return -EINVAL;
}
}
@@ -1771,7 +1785,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp
*intel_dp,
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int pipe_bpp, forced_bpp;
- forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
if (forced_bpp) {
pipe_bpp = forced_bpp;
@@ -1779,9 +1793,9 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp
*intel_dp,
/* For eDP use max bpp that can be supported with DSC. */
pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
conn_state->max_requested_bpc);
- if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits,
pipe_bpp)) {
drm_dbg_kms(&i915->drm,
- "Computed BPC less than min supported by
source for DSC\n");
+ "Computed BPC is not in DSC BPC limits\n");
return -EINVAL;
}
}
--
2.40.1
[Intel-gfx] [PATCH 13/19] drm/i915/dp: Avoid left shift of DSC output bpp by 4
To make way for fractional bpp support, avoid left shifting the output_bpp by 4 in helper intel_dp_dsc_get_output_bpp. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 10 +++--- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9e815408c0d9..16dc32846f5a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -803,11 +803,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp); - /* -* Compressed BPP in U6.4 format so multiply by 16, for Gen 11, -* fractional part is 0 -*/ - return bits_per_pixel << 4; + return bits_per_pixel; } u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, @@ -1197,7 +1193,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, mode->hdisplay, bigjoiner, output_format, - pipe_bpp, 64) >> 4; + pipe_bpp, 64); dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, @@ -1802,7 +1798,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->pipe_bpp); pipe_config->dsc.compressed_bpp = min_t(u16, - dsc_max_compressed_bpp >> 4, + dsc_max_compressed_bpp, output_bpp); } pipe_config->dsc.slice_count = dsc_dp_slice_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index dff4717edbd0..4895d6242915 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -982,7 +982,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, mode->hdisplay, bigjoiner, INTEL_OUTPUT_FORMAT_RGB, - pipe_bpp, 64) >> 4; + pipe_bpp, 64); dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, -- 2.40.1
[Intel-gfx] [PATCH 12/19] drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases where bpc is forced by debugfs flag
dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
flag.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not required.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 46 -
1 file changed, 30 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1abcdf42e408..9e815408c0d9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1686,6 +1686,12 @@ u8 intel_dp_dsc_min_src_input_bpc(struct
drm_i915_private *i915)
return 0;
}
+static
+bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
+{
+ return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1697,7 +1703,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- int pipe_bpp;
int ret;
pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
@@ -1709,27 +1714,36 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
return -EINVAL;
- if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
- pipe_bpp = intel_dp->force_dsc_bpc * 3;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
intel_dp->force_dsc_bpc);
- } else if (compute_pipe_bpp) {
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
conn_state->max_requested_bpc);
- } else {
- pipe_bpp = pipe_config->pipe_bpp;
- }
+ if (compute_pipe_bpp) {
+ int pipe_bpp;
+ int forced_bpp = intel_dp->force_dsc_bpc * 3;
- if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {
- drm_dbg_kms(&dev_priv->drm,
- "Computed BPC less than min supported by source for
DSC\n");
- return -EINVAL;
+ if (forced_bpp && is_dsc_pipe_bpp_sufficient(dev_priv,
forced_bpp)) {
+ pipe_bpp = forced_bpp;
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to
%d\n", intel_dp->force_dsc_bpc);
+ } else {
+ drm_WARN(&dev_priv->drm, forced_bpp,
+"Cannot force DSC BPC:%d, due to DSC BPC
limits\n",
+intel_dp->force_dsc_bpc);
+
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
+
conn_state->max_requested_bpc);
+
+ if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Computed BPC less than min
supported by source for DSC\n");
+ return -EINVAL;
+ }
+ }
+
+ pipe_config->pipe_bpp = pipe_bpp;
}
/*
-* For now enable DSC for max bpp, max link rate, max lane count.
+* For now enable DSC for max link rate, max lane count.
* Optimize this later for the minimum possible link rate/lane count
* with DSC enabled for the requested mode.
*/
- pipe_config->pipe_bpp = pipe_bpp;
pipe_config->port_clock = limits->max_rate;
pipe_config->lane_count = limits->max_lane_count;
@@ -1758,7 +1772,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
pipe_config->output_format,
- pipe_bpp,
+
pipe_config->pipe_bpp,
timeslots);
if (!dsc_max_compressed_bpp) {
drm_dbg_kms(&dev_priv->drm,
--
2.40.1
[Intel-gfx] [PATCH 08/19] drm/i915/dp: Remove extra logs for printing DSC info
DSC compressed bpp and slice counts are already getting printed at the end of dsc compute config. Remove extra logs. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8edac9462f5a..62329132d2d0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1771,9 +1771,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, output_bpp); } pipe_config->dsc.slice_count = dsc_dp_slice_count; - drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n", - pipe_config->dsc.compressed_bpp, - pipe_config->dsc.slice_count); } /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate -- 2.40.1
[Intel-gfx] [PATCH 10/19] drm/i915/dp: Avoid forcing DSC BPC for MST case
For MST the bpc is hardcoded to 8, and pipe bpp to 24.
So avoid forcing DSC bpc for MST case.
v2: Warn and ignore the debug flag than to bail out. (Jani)
v3: Fix dbg message to mention forced bpc instead of bpp.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 11 +--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 62329132d2d0..df262a623811 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1686,14 +1686,13 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
return -EINVAL;
- if (compute_pipe_bpp)
+ if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
+ pipe_bpp = intel_dp->force_dsc_bpc * 3;
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
intel_dp->force_dsc_bpc);
+ } else if (compute_pipe_bpp) {
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
conn_state->max_requested_bpc);
- else
+ } else {
pipe_bpp = pipe_config->pipe_bpp;
-
- if (intel_dp->force_dsc_bpc) {
- pipe_bpp = intel_dp->force_dsc_bpc * 3;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d",
pipe_bpp);
}
/* Min Input BPC for ICL+ is 8 */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 1f00713fb1ad..dff4717edbd0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -361,6 +361,11 @@ static int intel_dp_mst_compute_config(struct
intel_encoder *encoder,
/* enable compression if the mode doesn't fit available BW */
drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n",
intel_dp->force_dsc_en);
if (ret || intel_dp->force_dsc_en) {
+ /*
+* FIXME: As bpc is hardcoded to 8, as mentioned above,
+* WARN and ignore the debug flag force_dsc_bpc for now.
+*/
+ drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force
BPC for MST\n");
/*
* Try to get at least some timeslots and then see, if
* we can fit there with DSC.
--
2.40.1
[Intel-gfx] [PATCH 11/19] drm/i915/dp: Add functions to get min/max src input bpc with DSC
Separate out functions for getting maximum and minimum input BPC based
on platforms, when DSC is used.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 38 +++--
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index df262a623811..1abcdf42e408 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1524,6 +1524,18 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
return -EINVAL;
}
+static
+u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
+{
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (DISPLAY_VER(i915) >= 12)
+ return 12;
+ if (DISPLAY_VER(i915) == 11)
+ return 10;
+
+ return 0;
+}
+
int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1531,11 +1543,12 @@ int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp,
u8 max_req_bpc)
u8 dsc_bpc[3] = {0};
u8 dsc_max_bpc;
- /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
- if (DISPLAY_VER(i915) >= 12)
- dsc_max_bpc = min_t(u8, 12, max_req_bpc);
- else
- dsc_max_bpc = min_t(u8, 10, max_req_bpc);
+ dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
+
+ if (!dsc_max_bpc)
+ return dsc_max_bpc;
+
+ dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
dsc_bpc);
@@ -1663,6 +1676,16 @@ static bool intel_dp_dsc_supports_format(struct intel_dp
*intel_dp,
return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
sink_dsc_format);
}
+static
+u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
+{
+ /* Min DSC Input BPC for ICL+ is 8 */
+ if (DISPLAY_VER(i915) >= 11)
+ return 8;
+
+ return 0;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1695,10 +1718,9 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
pipe_bpp = pipe_config->pipe_bpp;
}
- /* Min Input BPC for ICL+ is 8 */
- if (pipe_bpp < 8 * 3) {
+ if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {
drm_dbg_kms(&dev_priv->drm,
- "No DSC support for less than 8bpc\n");
+ "Computed BPC less than min supported by source for
DSC\n");
return -EINVAL;
}
--
2.40.1
[Intel-gfx] [PATCH 09/19] drm/display/dp: Fix the DP DSC Receiver cap size
DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh.
Fix the DSC RECEIVER CAP SIZE accordingly.
Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define
and missing SHIFT")
Cc: Anusha Srivatsa
Cc: Manasi Navare
Cc: # v5.0+
Signed-off-by: Ankit Nautiyal
---
include/drm/display/drm_dp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 02f2ac4dd2df..e69cece404b3 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1537,7 +1537,7 @@ enum drm_dp_phy {
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
-#define DP_DSC_RECEIVER_CAP_SIZE0xf
+#define DP_DSC_RECEIVER_CAP_SIZE0x10 /* DSC Capabilities 0x60 through
0x6F */
#define EDP_PSR_RECEIVER_CAP_SIZE 2
#define EDP_DISPLAY_CTL_CAP_SIZE 3
#define DP_LTTPR_COMMON_CAP_SIZE 8
--
2.40.1
[Intel-gfx] [PATCH 05/19] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
v2: Corrected Display ver to 13.
v3: Follow convention for conditional statement. (Ville)
v4: Fix check for display ver. (Ville)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index c4e0a2704860..8edac9462f5a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -793,8 +793,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct
drm_i915_private *i915,
bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
if (bigjoiner) {
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 :
24;
u32 max_bpp_bigjoiner =
- i915->display.cdclk.max_cdclk_freq * 48 /
+ i915->display.cdclk.max_cdclk_freq * 2 *
bigjoiner_interface_bits /
intel_dp_mode_to_fec_clock(mode_clock);
bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
--
2.40.1
[Intel-gfx] [PATCH 07/19] drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
As per Bsepc:49259, Bigjoiner BW check puts restriction on the
compressed bpp for a given CDCLK, pixelclock in cases where
Bigjoiner + DSC are used.
Currently compressed bpp is computed first, and it is ensured that
the bpp will work at least with the max CDCLK freq.
Since the CDCLK is computed later, lets account for Bigjoiner BW
check while calculating Min CDCLK.
v2: Use pixel clock in the bw calculations. (Ville)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 51 +++---
1 file changed, 44 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 990dc16511f9..58c1fb773435 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2533,6 +2533,48 @@ static int intel_planes_min_cdclk(const struct
intel_crtc_state *crtc_state)
return min_cdclk;
}
+static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ int min_cdclk = 0;
+
+ /*
+* When we decide to use only one VDSC engine, since
+* each VDSC operates with 1 ppc throughput, pixel clock
+* cannot be higher than the VDSC clock (cdclk)
+*/
+ if (!crtc_state->dsc.dsc_split)
+ min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
+
+ if (crtc_state->bigjoiner_pipes) {
+ int pixel_clock = crtc_state->hw.adjusted_mode.clock;
+
+ /*
+* According to Bigjoiner bw check:
+* compressed_bpp <= PPC * CDCLK * Big joiner Interface bits /
Pixel clock
+*
+* We have already computed compressed_bpp, so now compute the
min CDCLK that
+* is required to support this compressed_bpp.
+*
+* => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner
Interface bits)
+*
+* Since PPC = 2 with bigjoiner
+* => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner
Interface bits
+*
+* #TODO Bspec mentions to account for FEC overhead while using
pixel clock.
+* Check if we need to use FEC overhead in the above
calculations.
+*/
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
+ int min_cdclk_bj = (crtc_state->dsc.compressed_bpp *
pixel_clock) /
+ (2 * bigjoiner_interface_bits);
+
+ min_cdclk = max(min_cdclk, min_cdclk_bj);
+ }
+
+ return min_cdclk;
+}
+
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv =
@@ -2604,13 +2646,8 @@ int intel_crtc_compute_min_cdclk(const struct
intel_crtc_state *crtc_state)
/* Account for additional needs from the planes */
min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
- /*
-* When we decide to use only one VDSC engine, since
-* each VDSC operates with 1 ppc throughput, pixel clock
-* cannot be higher than the VDSC clock (cdclk)
-*/
- if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
- min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
+ if (crtc_state->dsc.compression_enable)
+ min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
/*
* HACK. Currently for TGL/DG2 platforms we calculate
--
2.40.1
[Intel-gfx] [PATCH 06/19] drm/i915/display: Account for DSC not split case while computing cdclk
Currently we assume 2 Pixels Per Clock (PPC) while computing
plane cdclk and min_cdlck. In cases where DSC single engine
is used the throughput is 1 PPC.
So account for the above case, while computing cdclk.
v2: Use helper to get the adjusted pixel rate.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 3 ++-
drivers/gpu/drm/i915/display/intel_vdsc.c | 12
drivers/gpu/drm/i915/display/intel_vdsc.h | 2 ++
drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
4 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4207863b7b2a..990dc16511f9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -37,6 +37,7 @@
#include "intel_pci_config.h"
#include "intel_pcode.h"
#include "intel_psr.h"
+#include "intel_vdsc.h"
#include "vlv_sideband.h"
/**
@@ -2507,7 +2508,7 @@ static int intel_pixel_rate_to_cdclk(const struct
intel_crtc_state *crtc_state)
int pixel_rate = crtc_state->pixel_rate;
if (DISPLAY_VER(dev_priv) >= 10)
- return DIV_ROUND_UP(pixel_rate, 2);
+ return intel_dsc_get_adjusted_pixel_rate(crtc_state,
pixel_rate);
else if (DISPLAY_VER(dev_priv) == 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
return pixel_rate;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index bd9116d2cd76..11227491834e 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -974,3 +974,15 @@ void intel_dsc_get_config(struct intel_crtc_state
*crtc_state)
out:
intel_display_power_put(dev_priv, power_domain, wakeref);
}
+
+int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state
*crtc_state, int pixel_rate)
+{
+ /*
+* If single VDSC engine is used, it uses one pixel per clock
+* otherwise we use two pixels per clock.
+*/
+ if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
+ return pixel_rate;
+
+ return DIV_ROUND_UP(pixel_rate, 2);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h
b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 8763f00fa7e2..9f21a6c565c6 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -27,4 +27,6 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state
*crtc_state, int pixel_rate);
+
#endif /* __INTEL_VDSC_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6b01a0b68b97..9eeb25ec4be9 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -17,6 +17,7 @@
#include "intel_fb.h"
#include "intel_fbc.h"
#include "intel_psr.h"
+#include "intel_vdsc.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
#include "skl_watermark.h"
@@ -263,8 +264,7 @@ static int icl_plane_min_cdclk(const struct
intel_crtc_state *crtc_state,
{
unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state,
plane_state);
- /* two pixels per clock */
- return DIV_ROUND_UP(pixel_rate, 2);
+ return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
}
static void
--
2.40.1
[Intel-gfx] [PATCH 02/19] drm/i915/dp: Move compressed bpp check with 420 format inside the helper
Move the check for limiting compressed bite_per_pixel for 420,422
formats in the helper to compute bits_per_pixel.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f6061aa1cd42..e67071a6b5a2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -764,6 +764,15 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private
*i915,
if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
bits_per_pixel *= 2;
+ /*
+* According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
+* supported PPS value can be 63.9375 and with the further
+* mention that for 420, 422 formats, bpp should be programmed double
+* the target bpp restricting our target bpp to be 31.9375 at max.
+*/
+ if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ bits_per_pixel = min_t(u32, bits_per_pixel, 31);
+
drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
"total bw %u pixel clock %u\n",
bits_per_pixel, timeslots,
@@ -1729,15 +1738,6 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
pipe_config->output_format,
pipe_bpp,
timeslots);
- /*
-* According to DSC 1.2a Section 4.1.1 Table 4.1 the
maximum
-* supported PPS value can be 63.9375 and with the
further
-* mention that bpp should be programmed double the
target bpp
-* restricting our target bpp to be 31.9375 at max
-*/
- if (pipe_config->output_format ==
INTEL_OUTPUT_FORMAT_YCBCR420)
- dsc_max_output_bpp = min_t(u16,
dsc_max_output_bpp, 31 << 4);
-
if (!dsc_max_output_bpp) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP not supported\n");
--
2.40.1
[Intel-gfx] [PATCH 04/19] drm/i915/dp: Use consistent name for link bpp and compressed bpp
Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
output_format chroma subsampling.
compressed_bpp : target bpp for the DSC encoder.
link_bpp : final bpp used in the link.
For 444 sampling without DSC:
link_bpp = output_bpp = pipe_bpp
For 420 sampling without DSC:
output_bpp = pipe_bpp / 2
link_bpp = output_bpp
For 444 sampling with DSC:
output_bpp = pipe_bpp
link_bpp = compressed_bpp, computed with output_bpp (i.e. pipe_bpp in
this case)
For 420 sampling with DSC:
output_bpp = pipe_bpp/2
link_bpp = compressed_bpp, computed with output_bpp
Signed-off-by: Ankit Nautiyal
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 84 ++---
drivers/gpu/drm/i915/display/intel_dp.h | 14 ++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +++---
3 files changed, 60 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ba4f8b5ded96..c4e0a2704860 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -731,13 +731,13 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct
drm_i915_private *i915, u32 bpp, u32 p
return bits_per_pixel;
}
-u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- enum intel_output_format output_format,
- u32 pipe_bpp,
- u32 timeslots)
+u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ enum intel_output_format output_format,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
@@ -1127,7 +1127,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
int max_dotclk = dev_priv->max_dotclk_freq;
- u16 dsc_max_output_bpp = 0;
+ u16 dsc_max_compressed_bpp = 0;
u8 dsc_slice_count = 0;
enum drm_mode_status status;
bool dsc = false, bigjoiner = false;
@@ -1182,21 +1182,21 @@ intel_dp_mode_valid(struct drm_connector *_connector,
* integer value since we support only integer values of bpp.
*/
if (intel_dp_is_edp(intel_dp)) {
- dsc_max_output_bpp =
+ dsc_max_compressed_bpp =
drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd)
>> 4;
dsc_slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
- dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- max_link_clock,
- max_lanes,
- target_clock,
- mode->hdisplay,
- bigjoiner,
- output_format,
- pipe_bpp, 64) >> 4;
+ dsc_max_compressed_bpp =
+ intel_dp_dsc_get_max_compressed_bpp(dev_priv,
+
max_link_clock,
+ max_lanes,
+
target_clock,
+
mode->hdisplay,
+ bigjoiner,
+
output_format,
+ pipe_bpp,
64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1204,7 +1204,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
[Intel-gfx] [PATCH 03/19] drm/i915/dp_mst: Use output_format to get the final link bpp
The final link bpp used to calculate the m_n values depend on the
output_format. Though the output_format is set to RGB for MST case and
the link bpp will be same as the pipe bpp, for the sake of semantics,
lets calculate the m_n values with the link bpp, instead of pipe_bpp.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 -
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index e67071a6b5a2..ba4f8b5ded96 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -956,7 +956,7 @@ int intel_dp_min_bpp(enum intel_output_format output_format)
return 8 * 3;
}
-static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
+int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
{
/*
* bpp value was assumed to RGB format. And YCbCr 4:2:0 output
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index bb4f976af296..7dd015385054 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -144,5 +144,6 @@ void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
void intel_dp_phy_test(struct intel_encoder *encoder);
void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
+int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index aa8d9d570626..ef5375eb923e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -155,6 +155,7 @@ static int intel_dp_mst_compute_link_config(struct
intel_encoder *encoder,
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
int slots = -EINVAL;
+ int link_bpp;
slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
limits->max_bpp,
limits->min_bpp, limits,
@@ -163,7 +164,9 @@ static int intel_dp_mst_compute_link_config(struct
intel_encoder *encoder,
if (slots < 0)
return slots;
- intel_link_compute_m_n(crtc_state->pipe_bpp,
+ link_bpp = intel_dp_output_bpp(crtc_state->output_format,
crtc_state->pipe_bpp);
+
+ intel_link_compute_m_n(link_bpp,
crtc_state->lane_count,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
--
2.40.1
[Intel-gfx] [PATCH 01/19] drm/i915/dp: Consider output_format while computing dsc bpp
While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.
For DP-MST we currently use RGB output format only, so continue
using RGB while computing compressed bpp for MST case.
v2: Use output_bpp instead for pipe_bpp to clamp compressed_bpp. (Ville)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 19 +--
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9f40da20e88d..f6061aa1cd42 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -735,6 +735,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private
*i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
bool bigjoiner,
+ enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots)
{
@@ -759,6 +760,10 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private
*i915,
bits_per_pixel = ((link_clock * lane_count) * timeslots) /
(intel_dp_mode_to_fec_clock(mode_clock) * 8);
+ /* Bandwidth required for 420 is half, that of 444 format */
+ if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ bits_per_pixel *= 2;
+
drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
"total bw %u pixel clock %u\n",
bits_per_pixel, timeslots,
@@ -1152,11 +1157,16 @@ intel_dp_mode_valid(struct drm_connector *_connector,
if (HAS_DSC(dev_priv) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ enum intel_output_format sink_format, output_format;
+ int pipe_bpp;
+
+ sink_format = intel_dp_sink_format(connector, mode);
+ output_format = intel_dp_output_format(connector, sink_format);
/*
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be
picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
/*
* Output bpp is stored in 6.4 format so right shift by 4 to
get the
@@ -1176,6 +1186,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
target_clock,
mode->hdisplay,
bigjoiner,
+ output_format,
pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
@@ -1715,6 +1726,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
+
pipe_config->output_format,
pipe_bpp,
timeslots);
/*
@@ -1750,9 +1762,12 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
* calculation procedure is bit different for MST case.
*/
if (compute_pipe_bpp) {
+ u16 output_bpp =
intel_dp_output_bpp(pipe_config->output_format,
+
pipe_config->pipe_bpp);
+
pipe_config->dsc.compressed_bpp = min_t(u16,
dsc_max_output_bpp >> 4,
-
pipe_config->pipe_bpp);
+ output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count
%d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 22099de3ca45..bb4f976af296 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
[Intel-gfx] [PATCH 00/19] DSC misc fixes
This series is an attempt to address multiple issues with DSC, scattered in separate existing series. Patches 1-3 are DSC fixes from series to Handle BPC for HDMI2.1 PCON https://patchwork.freedesktop.org/series/107550/ Patches 4-5 are from series DSC fixes for Bigjoiner: https://patchwork.freedesktop.org/series/115773/ Patches 6-12 are from series to add DSC fractional BPP support: https://patchwork.freedesktop.org/series/111391/ Patch 13 is to fix compressed bpc for MST DSC, from Stan's series : https://patchwork.freedesktop.org/series/116179/ Rev2: Addressed review comments from Stan, Ville. Rev3: Split larger patches. Separate out common helpers. Ankit Nautiyal (18): drm/i915/dp: Consider output_format while computing dsc bpp drm/i915/dp: Move compressed bpp check with 420 format inside the helper drm/i915/dp_mst: Use output_format to get the final link bpp drm/i915/dp: Use consistent name for link bpp and compressed bpp drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp drm/i915/display: Account for DSC not split case while computing cdclk drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck drm/i915/dp: Remove extra logs for printing DSC info drm/display/dp: Fix the DP DSC Receiver cap size drm/i915/dp: Avoid forcing DSC BPC for MST case drm/i915/dp: Add functions to get min/max src input bpc with DSC drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also drm/i915/dp: Avoid left shift of DSC output bpp by 4 drm/i915/dp: Rename helper to get DSC max pipe_bpp drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with DSC drm/i915/dp: Separate out function to get compressed bpp with joiner drm/i915/dp: Get optimal link config to have best compressed bpp Stanislav Lisovskiy (1): drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info drivers/gpu/drm/i915/display/intel_cdclk.c| 54 +- drivers/gpu/drm/i915/display/intel_dp.c | 608 ++ drivers/gpu/drm/i915/display/intel_dp.h | 20 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 76 ++- drivers/gpu/drm/i915/display/intel_vdsc.c | 12 + drivers/gpu/drm/i915/display/intel_vdsc.h | 2 + .../drm/i915/display/skl_universal_plane.c| 4 +- include/drm/display/drm_dp.h | 2 +- 8 files changed, 594 insertions(+), 184 deletions(-) -- 2.40.1
[Intel-gfx] [v2] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines
Follow consistent naming convention. Replace MTL with
METEORLAKE. Added defines that are replacing IS_MTL_GRAPHICS_STEP with
IS_METEORLAKE_P_GRAPHICS_STEP and IS_METEORLAKE_M_GRAPHICS_STEP.
v2:
- Replace IS_MLT_GRAPHICS_STEP with IS_METEROLAKE_(P/M)_GRAPHICS_STEP (Tvrtko).
- Changed subject prefix mtl with MTL (Anusha)
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Anusha Srivatsa
Signed-off-by: Dnyaneshwar Bhadane
---
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 10 ++---
.../drm/i915/display/skl_universal_plane.c| 4 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8 ++--
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 4 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 44 +--
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 4 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 15 +--
drivers/gpu/drm/i915/i915_perf.c | 4 +-
15 files changed, 60 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7f8b2d7713c7..6358a8b26172 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
intel_atomic_state *state,
/* Wa_14016291713 */
if ((IS_DISPLAY_VER(i915, 12, 13) ||
-IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
crtc_state->has_psr) {
plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d363634..8c3158b188ef 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
&pmdemand_state->base,
&intel_pmdemand_funcs);
- if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+ if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
/* Wa_14016740474 */
intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
DMD_RSP_TIMEOUT_DISABLE);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 62151abe4748..ecd4e36119b2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
bool set_wa_bit = false;
/* Wa_14015648006 */
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+ if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
IS_DISPLAY_VER(dev_priv, 11, 13))
set_wa_bit |= crtc_state->wm_level_disabled;
@@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
* All supported adlp panels have 1-based X granularity, this
may
* cause issues if non-supported panels are used.
*/
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
MTL_CHICKEN_TRANS(cpu_transcoder), 0,
ADLP_1_BASED_X_GRANULARITY);
else if (IS_ALDERLAKE_P(dev_priv))
@@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
ADLP_1_BASED_X_GRANULARITY);
/* Wa_16012604467:adlp,mtl[a0,b0] */
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
if (intel_dp->psr.psr2_enabled) {
/* Wa_16012604467:adlp,mtl[a0,b0] */
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
[Intel-gfx] [PATCH v1 2/4] PCI/VGA: Improve the default VGA device selection
Currently, the default VGA device selection is not perfect. Potential
problems are:
1) This function is a no-op on non-x86 architectures.
2) It does not take the PCI Bar may get relocated into consideration.
3) It is not effective for the PCI device without a dedicated VRAM Bar.
4) It is device-agnostic, thus it has to waste the effort to iterate all
of the PCI Bar to find the VRAM aperture.
5) It has invented lots of methods to determine which one is the default
boot device on a multiple video card coexistence system. But this is
still a policy because it doesn't give the user a choice to override.
With the observation that device drivers or video aperture helpers may
have better knowledge about which PCI bar contains the firmware FB,
This patch tries to solve the above problems by introducing a function
callback to the vga_client_register() function interface. DRM device
drivers for the PCI device need to register the is_boot_device() function
callback during the driver loading time. Once the driver binds the device
successfully, VRAARB will call back to the driver. This gives the device
drivers a chance to provide accurate boot device identification. Which in
turn unlock the abitration service to non-x86 architectures. A device
driver can also pass a NULL pointer to the keep the original behavior.
This patch is to introduce the mechanism only, while the implementation
is left to the authors of various device driver. Also honor the comment:
"Clients have two callback mechanisms they can use"
Cc: Alex Deucher
Cc: Christian Konig
Cc: Pan Xinhui
Cc: David Airlie
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: Ben Skeggs
Cc: Karol Herbst
Cc: Lyude Paul
Cc: Bjorn Helgaas
Cc: Alex Williamson
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: Hawking Zhang
Cc: Mario Limonciello
Cc: Lijo Lazar
Cc: YiPeng Chai
Cc: Bokun Zhang
Cc: Likun Gao
Cc: Ville Syrjala
Cc: Jason Gunthorpe
CC: Kevin Tian
Cc: Cornelia Huck
Cc: Yishai Hadas
Cc: Abhishek Sahu
Cc: Yi Liu
Reviewed-by: Lyude Paul # nouveau
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/gpu/drm/i915/display/intel_vga.c | 3 +--
drivers/gpu/drm/nouveau/nouveau_vga.c | 2 +-
drivers/gpu/drm/radeon/radeon_device.c | 2 +-
drivers/pci/vgaarb.c | 21 -
drivers/vfio/pci/vfio_pci_core.c | 2 +-
include/linux/vgaarb.h | 8 +---
7 files changed, 30 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e25f085ee886..c5bdf6eff29e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4082,7 +4082,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
/* this will fail for cards that aren't VGA class devices, just
* ignore it */
if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
- vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
+ vga_client_register(adev->pdev, amdgpu_device_vga_set_decode,
NULL);
px = amdgpu_device_supports_px(ddev);
diff --git a/drivers/gpu/drm/i915/display/intel_vga.c
b/drivers/gpu/drm/i915/display/intel_vga.c
index 286a0bdd28c6..98d7d4dffe9f 100644
--- a/drivers/gpu/drm/i915/display/intel_vga.c
+++ b/drivers/gpu/drm/i915/display/intel_vga.c
@@ -115,7 +115,6 @@ intel_vga_set_decode(struct pci_dev *pdev, bool
enable_decode)
int intel_vga_register(struct drm_i915_private *i915)
{
-
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
int ret;
@@ -127,7 +126,7 @@ int intel_vga_register(struct drm_i915_private *i915)
* then we do not take part in VGA arbitration and the
* vga_client_register() fails with -ENODEV.
*/
- ret = vga_client_register(pdev, intel_vga_set_decode);
+ ret = vga_client_register(pdev, intel_vga_set_decode, NULL);
if (ret && ret != -ENODEV)
return ret;
diff --git a/drivers/gpu/drm/nouveau/nouveau_vga.c
b/drivers/gpu/drm/nouveau/nouveau_vga.c
index f8bf0ec26844..162b4f4676c7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_vga.c
+++ b/drivers/gpu/drm/nouveau/nouveau_vga.c
@@ -92,7 +92,7 @@ nouveau_vga_init(struct nouveau_drm *drm)
return;
pdev = to_pci_dev(dev->dev);
- vga_client_register(pdev, nouveau_vga_set_decode);
+ vga_client_register(pdev, nouveau_vga_set_decode, NULL);
/* don't register Thunderbolt eGPU with vga_switcheroo */
if (pci_is_thunderbolt_attached(pdev))
diff --git a/drivers/gpu/drm/radeon/radeon_device.c
b/drivers/gpu/drm/radeon/radeon_device.c
index afbb3a80c0c6..71f2ff39d6a1 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1425,7 +1425,7 @@ int radeon_device_init(struct ra
[Intel-gfx] [PATCH v1 0/4] PCI/VGA: Improve the default VGA device selection
Currently, the default VGA device selection is not perfect. Potential problems are: 1) This function is a no-op on non-x86 architectures. 2) It does not take the PCI Bar may get relocated into consideration. 3) It is not effective for the PCI device without a dedicated VRAM Bar. 4) It is device-agnostic, thus it has to waste the effort to iterate all of the PCI Bar to find the VRAM aperture. 5) It has invented lots of methods to determine which one is the default boot device on a multiple video card coexistence system. But this is still a policy because it doesn't give the user a choice to override. With the observation that device drivers or video aperture helpers may have better knowledge about which PCI bar contains the firmware FB, This patch tries to solve the above problems by introducing a function callback to the vga_client_register() function interface. DRM device drivers for the PCI device need to register the is_boot_device() function callback during the driver loading time. Once the driver binds the device successfully, VRAARB will call back to the driver. This gives the device drivers a chance to provide accurate boot device identification. Which in turn unlock the abitration service to non-x86 architectures. A device driver can also pass a NULL pointer to the keep the original behavior. Sui Jingfeng (4): video/aperture: Add a helper to detect if an aperture contains firmware FB PCI/VGA: Improve the default VGA device selection drm/amdgpu: Implement the is_boot_device callback function drm/radeon: Implement the is_boot_device callback function drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 - drivers/gpu/drm/drm_aperture.c | 16 drivers/gpu/drm/i915/display/intel_vga.c | 3 +-- drivers/gpu/drm/nouveau/nouveau_vga.c | 2 +- drivers/gpu/drm/radeon/radeon_device.c | 12 - drivers/pci/vgaarb.c | 21 +++- drivers/vfio/pci/vfio_pci_core.c | 2 +- drivers/video/aperture.c | 29 ++ include/drm/drm_aperture.h | 2 ++ include/linux/aperture.h | 7 ++ include/linux/vgaarb.h | 8 +++--- 11 files changed, 104 insertions(+), 10 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH v1 1/4] video/aperture: Add a helper to detect if an aperture contains firmware FB
This patch adds the aperture_contain_firmware_fb() function to do the
determination. Unfortunately due to the fact that apertures list will be
freed dynamically, the location and size information of the firmware fb
will be lost after dedicated drivers call
aperture_remove_conflicting_devices(),
aperture_remove_conflicting_pci_devices() or
aperture_remove_all_conflicting_devices() functions
We handle this problem by introducing two static variables which record the
firmware framebuffer's start addrness and end addrness. It assumes that the
system has only one active firmware framebuffer driver at a time.
We don't use the global structure screen_info here, because PCI resource
may get reallocated(the VRAM BAR could be moved) at kernel boot stage.
Cc: Thomas Zimmermann
Cc: Javier Martinez Canillas
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: David Airlie
Cc: Daniel Vetter
Cc: Helge Deller
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/drm_aperture.c | 16
drivers/video/aperture.c | 29 +
include/drm/drm_aperture.h | 2 ++
include/linux/aperture.h | 7 +++
4 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/drm_aperture.c b/drivers/gpu/drm/drm_aperture.c
index 5729f3bb4398..6e5d8a08683c 100644
--- a/drivers/gpu/drm/drm_aperture.c
+++ b/drivers/gpu/drm/drm_aperture.c
@@ -190,3 +190,19 @@ int
drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev,
return aperture_remove_conflicting_pci_devices(pdev, req_driver->name);
}
EXPORT_SYMBOL(drm_aperture_remove_conflicting_pci_framebuffers);
+
+/**
+ * drm_aperture_contain_firmware_fb - Determine if a aperture contains
firmware framebuffer
+ *
+ * @base: the aperture's base address in physical memory
+ * @size: aperture size in bytes
+ *
+ * Returns:
+ * true on if there is a firmware framebuffer belong to the aperture passed in,
+ * or false otherwise.
+ */
+bool drm_aperture_contain_firmware_fb(resource_size_t base, resource_size_t
size)
+{
+ return aperture_contain_firmware_fb(base, base + size);
+}
+EXPORT_SYMBOL(drm_aperture_contain_firmware_fb);
diff --git a/drivers/video/aperture.c b/drivers/video/aperture.c
index 561be8feca96..5a5422cec669 100644
--- a/drivers/video/aperture.c
+++ b/drivers/video/aperture.c
@@ -141,6 +141,9 @@ struct aperture_range {
static LIST_HEAD(apertures);
static DEFINE_MUTEX(apertures_lock);
+static resource_size_t firm_fb_start;
+static resource_size_t firm_fb_end;
+
static bool overlap(resource_size_t base1, resource_size_t end1,
resource_size_t base2, resource_size_t end2)
{
@@ -170,6 +173,9 @@ static int devm_aperture_acquire(struct device *dev,
mutex_lock(&apertures_lock);
+ firm_fb_start = base;
+ firm_fb_end = end;
+
list_for_each(pos, &apertures) {
ap = container_of(pos, struct aperture_range, lh);
if (overlap(base, end, ap->base, ap->base + ap->size)) {
@@ -377,3 +383,26 @@ int aperture_remove_conflicting_pci_devices(struct pci_dev
*pdev, const char *na
}
EXPORT_SYMBOL(aperture_remove_conflicting_pci_devices);
+
+/**
+ * aperture_contain_firmware_fb - Detect if the firmware framebuffer belong to
+ *a aperture.
+ * @ap_start: the aperture's start address in physical memory
+ * @ap_end: the aperture's end address in physical memory
+ *
+ * Returns:
+ * true on if there is a firmware framebuffer belong to the aperture passed in,
+ * or false otherwise.
+ */
+bool aperture_contain_firmware_fb(resource_size_t ap_start, resource_size_t
ap_end)
+{
+ /* No firmware framebuffer support */
+ if (!firm_fb_start || !firm_fb_end)
+ return false;
+
+ if (firm_fb_start >= ap_start && firm_fb_end <= ap_end)
+ return true;
+
+ return false;
+}
+EXPORT_SYMBOL(aperture_contain_firmware_fb);
diff --git a/include/drm/drm_aperture.h b/include/drm/drm_aperture.h
index cbe33b49fd5d..6a0b9bacb081 100644
--- a/include/drm/drm_aperture.h
+++ b/include/drm/drm_aperture.h
@@ -35,4 +35,6 @@ drm_aperture_remove_framebuffers(const struct drm_driver
*req_driver)
req_driver);
}
+bool drm_aperture_contain_firmware_fb(resource_size_t base, resource_size_t
size);
+
#endif
diff --git a/include/linux/aperture.h b/include/linux/aperture.h
index 1a9a88b11584..d4dc5917c49b 100644
--- a/include/linux/aperture.h
+++ b/include/linux/aperture.h
@@ -19,6 +19,8 @@ int aperture_remove_conflicting_devices(resource_size_t base,
resource_size_t si
int __aperture_remove_legacy_vga_devices(struct pci_dev *pdev);
int aperture_remove_conflicting_pci_devices(struct pci_dev *pdev, const char
*name);
+
+bool aperture_contain_firmware_fb(resource_size_t ap_start, resource_size_t
ap_end);
#else
static inline int devm_aperture_acquire_for_platform_device(struct
platform_device *pdev,
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/shrinker: Treat fb's with higher priority than active reference
== Series Details == Series: drm/i915/shrinker: Treat fb's with higher priority than active reference URL : https://patchwork.freedesktop.org/series/120039/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13337_full -> Patchwork_120039v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_120039v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_120039v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (8 -> 8) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_120039v1_full: ### IGT changes ### Possible regressions * igt@runner@aborted: - shard-apl: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120039v1/shard-apl1/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_120039v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_barrier_race@remote-request@rcs0: - shard-apl: [PASS][2] -> [ABORT][3] ([i915#7461] / [i915#8190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13337/shard-apl3/igt@gem_barrier_race@remote-requ...@rcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120039v1/shard-apl2/igt@gem_barrier_race@remote-requ...@rcs0.html * igt@gem_eio@hibernate: - shard-tglu: [PASS][4] -> [ABORT][5] ([i915#7975] / [i915#8213] / [i915#8398]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13337/shard-tglu-2/igt@gem_...@hibernate.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120039v1/shard-tglu-10/igt@gem_...@hibernate.html * igt@gem_exec_balancer@full-pulse: - shard-dg2: [PASS][6] -> [FAIL][7] ([i915#6032]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13337/shard-dg2-8/igt@gem_exec_balan...@full-pulse.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120039v1/shard-dg2-1/igt@gem_exec_balan...@full-pulse.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13337/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120039v1/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-rkl: [PASS][10] -> [FAIL][11] ([i915#2842]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13337/shard-rkl-6/igt@gem_exec_fair@basic-pace-s...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120039v1/shard-rkl-2/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_workarounds@suspend-resume: - shard-dg2: [PASS][12] -> [FAIL][13] ([fdo#103375]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13337/shard-dg2-7/igt@gem_workarou...@suspend-resume.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120039v1/shard-dg2-5/igt@gem_workarou...@suspend-resume.html * igt@i915_pm_rpm@modeset-non-lpsp-stress: - shard-dg2: [PASS][14] -> [SKIP][15] ([i915#1397]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13337/shard-dg2-5/igt@i915_pm_...@modeset-non-lpsp-stress.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120039v1/shard-dg2-12/igt@i915_pm_...@modeset-non-lpsp-stress.html * igt@i915_suspend@basic-s3-without-i915: - shard-dg2: [PASS][16] -> [FAIL][17] ([fdo#103375] / [i915#6121]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13337/shard-dg2-11/igt@i915_susp...@basic-s3-without-i915.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120039v1/shard-dg2-5/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_async_flips@crc@pipe-a-dp-4: - shard-dg2: NOTRUN -> [FAIL][18] ([i915#8247]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120039v1/shard-dg2-11/igt@kms_async_flips@c...@pipe-a-dp-4.html * igt@kms_cdclk@mode-transition@pipe-d-dp-4: - shard-dg2: NOTRUN -> [SKIP][19] ([i915#4087] / [i915#4579]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120039v1/shard-dg2-11/igt@kms_cdclk@mode-transit...@pipe-d-dp-4.html * igt@kms_cdclk@plane-scaling@pipe-c-dp-2: - shard-dg2: NOTRUN -> [SKIP][20] ([i915#4087]) +5 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120039v1/shard-dg2-12/igt@kms_cdclk@plane-scal...@pipe-c-dp-2.html * igt@kms_content_protection@at
